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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
ef9348c8 CML |
44 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
45 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) | |
46 | ||
3dec0095 | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 49 | |
f1f644dc JB |
50 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
51 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
52 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
53 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 54 | |
e7457a9a DL |
55 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
56 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
57 | static int intel_framebuffer_init(struct drm_device *dev, |
58 | struct intel_framebuffer *ifb, | |
59 | struct drm_mode_fb_cmd2 *mode_cmd, | |
60 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
61 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
62 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
63 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab DV |
64 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
65 | struct intel_link_m_n *m_n); | |
66 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
229fca97 DV |
67 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
68 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 69 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 70 | |
79e53945 | 71 | typedef struct { |
0206e353 | 72 | int min, max; |
79e53945 JB |
73 | } intel_range_t; |
74 | ||
75 | typedef struct { | |
0206e353 AJ |
76 | int dot_limit; |
77 | int p2_slow, p2_fast; | |
79e53945 JB |
78 | } intel_p2_t; |
79 | ||
d4906093 ML |
80 | typedef struct intel_limit intel_limit_t; |
81 | struct intel_limit { | |
0206e353 AJ |
82 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
83 | intel_p2_t p2; | |
d4906093 | 84 | }; |
79e53945 | 85 | |
d2acd215 DV |
86 | int |
87 | intel_pch_rawclk(struct drm_device *dev) | |
88 | { | |
89 | struct drm_i915_private *dev_priv = dev->dev_private; | |
90 | ||
91 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
92 | ||
93 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
94 | } | |
95 | ||
021357ac CW |
96 | static inline u32 /* units of 100MHz */ |
97 | intel_fdi_link_freq(struct drm_device *dev) | |
98 | { | |
8b99e68c CW |
99 | if (IS_GEN5(dev)) { |
100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
101 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
102 | } else | |
103 | return 27; | |
021357ac CW |
104 | } |
105 | ||
5d536e28 | 106 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 107 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 108 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 109 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
110 | .m = { .min = 96, .max = 140 }, |
111 | .m1 = { .min = 18, .max = 26 }, | |
112 | .m2 = { .min = 6, .max = 16 }, | |
113 | .p = { .min = 4, .max = 128 }, | |
114 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
115 | .p2 = { .dot_limit = 165000, |
116 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
117 | }; |
118 | ||
5d536e28 DV |
119 | static const intel_limit_t intel_limits_i8xx_dvo = { |
120 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 121 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 122 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
123 | .m = { .min = 96, .max = 140 }, |
124 | .m1 = { .min = 18, .max = 26 }, | |
125 | .m2 = { .min = 6, .max = 16 }, | |
126 | .p = { .min = 4, .max = 128 }, | |
127 | .p1 = { .min = 2, .max = 33 }, | |
128 | .p2 = { .dot_limit = 165000, | |
129 | .p2_slow = 4, .p2_fast = 4 }, | |
130 | }; | |
131 | ||
e4b36699 | 132 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 133 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 134 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 135 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
136 | .m = { .min = 96, .max = 140 }, |
137 | .m1 = { .min = 18, .max = 26 }, | |
138 | .m2 = { .min = 6, .max = 16 }, | |
139 | .p = { .min = 4, .max = 128 }, | |
140 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
141 | .p2 = { .dot_limit = 165000, |
142 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 143 | }; |
273e27ca | 144 | |
e4b36699 | 145 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
146 | .dot = { .min = 20000, .max = 400000 }, |
147 | .vco = { .min = 1400000, .max = 2800000 }, | |
148 | .n = { .min = 1, .max = 6 }, | |
149 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
150 | .m1 = { .min = 8, .max = 18 }, |
151 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
152 | .p = { .min = 5, .max = 80 }, |
153 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
154 | .p2 = { .dot_limit = 200000, |
155 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
156 | }; |
157 | ||
158 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
159 | .dot = { .min = 20000, .max = 400000 }, |
160 | .vco = { .min = 1400000, .max = 2800000 }, | |
161 | .n = { .min = 1, .max = 6 }, | |
162 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
163 | .m1 = { .min = 8, .max = 18 }, |
164 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
165 | .p = { .min = 7, .max = 98 }, |
166 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
167 | .p2 = { .dot_limit = 112000, |
168 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
169 | }; |
170 | ||
273e27ca | 171 | |
e4b36699 | 172 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
173 | .dot = { .min = 25000, .max = 270000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 17, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 10, .max = 30 }, | |
180 | .p1 = { .min = 1, .max = 3}, | |
181 | .p2 = { .dot_limit = 270000, | |
182 | .p2_slow = 10, | |
183 | .p2_fast = 10 | |
044c7c41 | 184 | }, |
e4b36699 KP |
185 | }; |
186 | ||
187 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
188 | .dot = { .min = 22000, .max = 400000 }, |
189 | .vco = { .min = 1750000, .max = 3500000}, | |
190 | .n = { .min = 1, .max = 4 }, | |
191 | .m = { .min = 104, .max = 138 }, | |
192 | .m1 = { .min = 16, .max = 23 }, | |
193 | .m2 = { .min = 5, .max = 11 }, | |
194 | .p = { .min = 5, .max = 80 }, | |
195 | .p1 = { .min = 1, .max = 8}, | |
196 | .p2 = { .dot_limit = 165000, | |
197 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
201 | .dot = { .min = 20000, .max = 115000 }, |
202 | .vco = { .min = 1750000, .max = 3500000 }, | |
203 | .n = { .min = 1, .max = 3 }, | |
204 | .m = { .min = 104, .max = 138 }, | |
205 | .m1 = { .min = 17, .max = 23 }, | |
206 | .m2 = { .min = 5, .max = 11 }, | |
207 | .p = { .min = 28, .max = 112 }, | |
208 | .p1 = { .min = 2, .max = 8 }, | |
209 | .p2 = { .dot_limit = 0, | |
210 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 211 | }, |
e4b36699 KP |
212 | }; |
213 | ||
214 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
215 | .dot = { .min = 80000, .max = 224000 }, |
216 | .vco = { .min = 1750000, .max = 3500000 }, | |
217 | .n = { .min = 1, .max = 3 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 14, .max = 42 }, | |
222 | .p1 = { .min = 2, .max = 6 }, | |
223 | .p2 = { .dot_limit = 0, | |
224 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 225 | }, |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000}, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 231 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
232 | .n = { .min = 3, .max = 6 }, |
233 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 234 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
235 | .m1 = { .min = 0, .max = 0 }, |
236 | .m2 = { .min = 0, .max = 254 }, | |
237 | .p = { .min = 5, .max = 80 }, | |
238 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
239 | .p2 = { .dot_limit = 200000, |
240 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
241 | }; |
242 | ||
f2b115e6 | 243 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
244 | .dot = { .min = 20000, .max = 400000 }, |
245 | .vco = { .min = 1700000, .max = 3500000 }, | |
246 | .n = { .min = 3, .max = 6 }, | |
247 | .m = { .min = 2, .max = 256 }, | |
248 | .m1 = { .min = 0, .max = 0 }, | |
249 | .m2 = { .min = 0, .max = 254 }, | |
250 | .p = { .min = 7, .max = 112 }, | |
251 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
252 | .p2 = { .dot_limit = 112000, |
253 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
254 | }; |
255 | ||
273e27ca EA |
256 | /* Ironlake / Sandybridge |
257 | * | |
258 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
259 | * the range value for them is (actual_value - 2). | |
260 | */ | |
b91ad0ec | 261 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
262 | .dot = { .min = 25000, .max = 350000 }, |
263 | .vco = { .min = 1760000, .max = 3510000 }, | |
264 | .n = { .min = 1, .max = 5 }, | |
265 | .m = { .min = 79, .max = 127 }, | |
266 | .m1 = { .min = 12, .max = 22 }, | |
267 | .m2 = { .min = 5, .max = 9 }, | |
268 | .p = { .min = 5, .max = 80 }, | |
269 | .p1 = { .min = 1, .max = 8 }, | |
270 | .p2 = { .dot_limit = 225000, | |
271 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
272 | }; |
273 | ||
b91ad0ec | 274 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
275 | .dot = { .min = 25000, .max = 350000 }, |
276 | .vco = { .min = 1760000, .max = 3510000 }, | |
277 | .n = { .min = 1, .max = 3 }, | |
278 | .m = { .min = 79, .max = 118 }, | |
279 | .m1 = { .min = 12, .max = 22 }, | |
280 | .m2 = { .min = 5, .max = 9 }, | |
281 | .p = { .min = 28, .max = 112 }, | |
282 | .p1 = { .min = 2, .max = 8 }, | |
283 | .p2 = { .dot_limit = 225000, | |
284 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
285 | }; |
286 | ||
287 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
288 | .dot = { .min = 25000, .max = 350000 }, |
289 | .vco = { .min = 1760000, .max = 3510000 }, | |
290 | .n = { .min = 1, .max = 3 }, | |
291 | .m = { .min = 79, .max = 127 }, | |
292 | .m1 = { .min = 12, .max = 22 }, | |
293 | .m2 = { .min = 5, .max = 9 }, | |
294 | .p = { .min = 14, .max = 56 }, | |
295 | .p1 = { .min = 2, .max = 8 }, | |
296 | .p2 = { .dot_limit = 225000, | |
297 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
298 | }; |
299 | ||
273e27ca | 300 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 301 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
302 | .dot = { .min = 25000, .max = 350000 }, |
303 | .vco = { .min = 1760000, .max = 3510000 }, | |
304 | .n = { .min = 1, .max = 2 }, | |
305 | .m = { .min = 79, .max = 126 }, | |
306 | .m1 = { .min = 12, .max = 22 }, | |
307 | .m2 = { .min = 5, .max = 9 }, | |
308 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 309 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
310 | .p2 = { .dot_limit = 225000, |
311 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
312 | }; |
313 | ||
314 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
315 | .dot = { .min = 25000, .max = 350000 }, |
316 | .vco = { .min = 1760000, .max = 3510000 }, | |
317 | .n = { .min = 1, .max = 3 }, | |
318 | .m = { .min = 79, .max = 126 }, | |
319 | .m1 = { .min = 12, .max = 22 }, | |
320 | .m2 = { .min = 5, .max = 9 }, | |
321 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 322 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
323 | .p2 = { .dot_limit = 225000, |
324 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
325 | }; |
326 | ||
dc730512 | 327 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
328 | /* |
329 | * These are the data rate limits (measured in fast clocks) | |
330 | * since those are the strictest limits we have. The fast | |
331 | * clock and actual rate limits are more relaxed, so checking | |
332 | * them would make no difference. | |
333 | */ | |
334 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 335 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 336 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
337 | .m1 = { .min = 2, .max = 3 }, |
338 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 339 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 340 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
341 | }; |
342 | ||
ef9348c8 CML |
343 | static const intel_limit_t intel_limits_chv = { |
344 | /* | |
345 | * These are the data rate limits (measured in fast clocks) | |
346 | * since those are the strictest limits we have. The fast | |
347 | * clock and actual rate limits are more relaxed, so checking | |
348 | * them would make no difference. | |
349 | */ | |
350 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
351 | .vco = { .min = 4860000, .max = 6700000 }, | |
352 | .n = { .min = 1, .max = 1 }, | |
353 | .m1 = { .min = 2, .max = 2 }, | |
354 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
355 | .p1 = { .min = 2, .max = 4 }, | |
356 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
357 | }; | |
358 | ||
6b4bf1c4 VS |
359 | static void vlv_clock(int refclk, intel_clock_t *clock) |
360 | { | |
361 | clock->m = clock->m1 * clock->m2; | |
362 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
363 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
364 | return; | |
fb03ac01 VS |
365 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
366 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
367 | } |
368 | ||
e0638cdf PZ |
369 | /** |
370 | * Returns whether any output on the specified pipe is of the specified type | |
371 | */ | |
372 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
373 | { | |
374 | struct drm_device *dev = crtc->dev; | |
375 | struct intel_encoder *encoder; | |
376 | ||
377 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
378 | if (encoder->type == type) | |
379 | return true; | |
380 | ||
381 | return false; | |
382 | } | |
383 | ||
1b894b59 CW |
384 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
385 | int refclk) | |
2c07245f | 386 | { |
b91ad0ec | 387 | struct drm_device *dev = crtc->dev; |
2c07245f | 388 | const intel_limit_t *limit; |
b91ad0ec ZW |
389 | |
390 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 391 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 392 | if (refclk == 100000) |
b91ad0ec ZW |
393 | limit = &intel_limits_ironlake_dual_lvds_100m; |
394 | else | |
395 | limit = &intel_limits_ironlake_dual_lvds; | |
396 | } else { | |
1b894b59 | 397 | if (refclk == 100000) |
b91ad0ec ZW |
398 | limit = &intel_limits_ironlake_single_lvds_100m; |
399 | else | |
400 | limit = &intel_limits_ironlake_single_lvds; | |
401 | } | |
c6bb3538 | 402 | } else |
b91ad0ec | 403 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
404 | |
405 | return limit; | |
406 | } | |
407 | ||
044c7c41 ML |
408 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
409 | { | |
410 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
411 | const intel_limit_t *limit; |
412 | ||
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 414 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 415 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 416 | else |
e4b36699 | 417 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
418 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
419 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 420 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 421 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 422 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 423 | } else /* The option is for other outputs */ |
e4b36699 | 424 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
425 | |
426 | return limit; | |
427 | } | |
428 | ||
1b894b59 | 429 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
430 | { |
431 | struct drm_device *dev = crtc->dev; | |
432 | const intel_limit_t *limit; | |
433 | ||
bad720ff | 434 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 435 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 436 | else if (IS_G4X(dev)) { |
044c7c41 | 437 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 438 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 439 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 440 | limit = &intel_limits_pineview_lvds; |
2177832f | 441 | else |
f2b115e6 | 442 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
443 | } else if (IS_CHERRYVIEW(dev)) { |
444 | limit = &intel_limits_chv; | |
a0c4da24 | 445 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 446 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
447 | } else if (!IS_GEN2(dev)) { |
448 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
449 | limit = &intel_limits_i9xx_lvds; | |
450 | else | |
451 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
452 | } else { |
453 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 454 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 455 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 456 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
457 | else |
458 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
459 | } |
460 | return limit; | |
461 | } | |
462 | ||
f2b115e6 AJ |
463 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
464 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 465 | { |
2177832f SL |
466 | clock->m = clock->m2 + 2; |
467 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
468 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
469 | return; | |
fb03ac01 VS |
470 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
471 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
472 | } |
473 | ||
7429e9d4 DV |
474 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
475 | { | |
476 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
477 | } | |
478 | ||
ac58c3f0 | 479 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 480 | { |
7429e9d4 | 481 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 482 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
483 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
484 | return; | |
fb03ac01 VS |
485 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
486 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
487 | } |
488 | ||
ef9348c8 CML |
489 | static void chv_clock(int refclk, intel_clock_t *clock) |
490 | { | |
491 | clock->m = clock->m1 * clock->m2; | |
492 | clock->p = clock->p1 * clock->p2; | |
493 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
494 | return; | |
495 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
496 | clock->n << 22); | |
497 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
498 | } | |
499 | ||
7c04d1d9 | 500 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
501 | /** |
502 | * Returns whether the given set of divisors are valid for a given refclk with | |
503 | * the given connectors. | |
504 | */ | |
505 | ||
1b894b59 CW |
506 | static bool intel_PLL_is_valid(struct drm_device *dev, |
507 | const intel_limit_t *limit, | |
508 | const intel_clock_t *clock) | |
79e53945 | 509 | { |
f01b7962 VS |
510 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
511 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 512 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 513 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 514 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 515 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 516 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 517 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
518 | |
519 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
520 | if (clock->m1 <= clock->m2) | |
521 | INTELPllInvalid("m1 <= m2\n"); | |
522 | ||
523 | if (!IS_VALLEYVIEW(dev)) { | |
524 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
525 | INTELPllInvalid("p out of range\n"); | |
526 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
527 | INTELPllInvalid("m out of range\n"); | |
528 | } | |
529 | ||
79e53945 | 530 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 531 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
532 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
533 | * connector, etc., rather than just a single range. | |
534 | */ | |
535 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 536 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
537 | |
538 | return true; | |
539 | } | |
540 | ||
d4906093 | 541 | static bool |
ee9300bb | 542 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
543 | int target, int refclk, intel_clock_t *match_clock, |
544 | intel_clock_t *best_clock) | |
79e53945 JB |
545 | { |
546 | struct drm_device *dev = crtc->dev; | |
79e53945 | 547 | intel_clock_t clock; |
79e53945 JB |
548 | int err = target; |
549 | ||
a210b028 | 550 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 551 | /* |
a210b028 DV |
552 | * For LVDS just rely on its current settings for dual-channel. |
553 | * We haven't figured out how to reliably set up different | |
554 | * single/dual channel state, if we even can. | |
79e53945 | 555 | */ |
1974cad0 | 556 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
557 | clock.p2 = limit->p2.p2_fast; |
558 | else | |
559 | clock.p2 = limit->p2.p2_slow; | |
560 | } else { | |
561 | if (target < limit->p2.dot_limit) | |
562 | clock.p2 = limit->p2.p2_slow; | |
563 | else | |
564 | clock.p2 = limit->p2.p2_fast; | |
565 | } | |
566 | ||
0206e353 | 567 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 568 | |
42158660 ZY |
569 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
570 | clock.m1++) { | |
571 | for (clock.m2 = limit->m2.min; | |
572 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 573 | if (clock.m2 >= clock.m1) |
42158660 ZY |
574 | break; |
575 | for (clock.n = limit->n.min; | |
576 | clock.n <= limit->n.max; clock.n++) { | |
577 | for (clock.p1 = limit->p1.min; | |
578 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
579 | int this_err; |
580 | ||
ac58c3f0 DV |
581 | i9xx_clock(refclk, &clock); |
582 | if (!intel_PLL_is_valid(dev, limit, | |
583 | &clock)) | |
584 | continue; | |
585 | if (match_clock && | |
586 | clock.p != match_clock->p) | |
587 | continue; | |
588 | ||
589 | this_err = abs(clock.dot - target); | |
590 | if (this_err < err) { | |
591 | *best_clock = clock; | |
592 | err = this_err; | |
593 | } | |
594 | } | |
595 | } | |
596 | } | |
597 | } | |
598 | ||
599 | return (err != target); | |
600 | } | |
601 | ||
602 | static bool | |
ee9300bb DV |
603 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
604 | int target, int refclk, intel_clock_t *match_clock, | |
605 | intel_clock_t *best_clock) | |
79e53945 JB |
606 | { |
607 | struct drm_device *dev = crtc->dev; | |
79e53945 | 608 | intel_clock_t clock; |
79e53945 JB |
609 | int err = target; |
610 | ||
a210b028 | 611 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 612 | /* |
a210b028 DV |
613 | * For LVDS just rely on its current settings for dual-channel. |
614 | * We haven't figured out how to reliably set up different | |
615 | * single/dual channel state, if we even can. | |
79e53945 | 616 | */ |
1974cad0 | 617 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
618 | clock.p2 = limit->p2.p2_fast; |
619 | else | |
620 | clock.p2 = limit->p2.p2_slow; | |
621 | } else { | |
622 | if (target < limit->p2.dot_limit) | |
623 | clock.p2 = limit->p2.p2_slow; | |
624 | else | |
625 | clock.p2 = limit->p2.p2_fast; | |
626 | } | |
627 | ||
0206e353 | 628 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 629 | |
42158660 ZY |
630 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
631 | clock.m1++) { | |
632 | for (clock.m2 = limit->m2.min; | |
633 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
634 | for (clock.n = limit->n.min; |
635 | clock.n <= limit->n.max; clock.n++) { | |
636 | for (clock.p1 = limit->p1.min; | |
637 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
638 | int this_err; |
639 | ||
ac58c3f0 | 640 | pineview_clock(refclk, &clock); |
1b894b59 CW |
641 | if (!intel_PLL_is_valid(dev, limit, |
642 | &clock)) | |
79e53945 | 643 | continue; |
cec2f356 SP |
644 | if (match_clock && |
645 | clock.p != match_clock->p) | |
646 | continue; | |
79e53945 JB |
647 | |
648 | this_err = abs(clock.dot - target); | |
649 | if (this_err < err) { | |
650 | *best_clock = clock; | |
651 | err = this_err; | |
652 | } | |
653 | } | |
654 | } | |
655 | } | |
656 | } | |
657 | ||
658 | return (err != target); | |
659 | } | |
660 | ||
d4906093 | 661 | static bool |
ee9300bb DV |
662 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
663 | int target, int refclk, intel_clock_t *match_clock, | |
664 | intel_clock_t *best_clock) | |
d4906093 ML |
665 | { |
666 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
667 | intel_clock_t clock; |
668 | int max_n; | |
669 | bool found; | |
6ba770dc AJ |
670 | /* approximately equals target * 0.00585 */ |
671 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
672 | found = false; |
673 | ||
674 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 675 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
676 | clock.p2 = limit->p2.p2_fast; |
677 | else | |
678 | clock.p2 = limit->p2.p2_slow; | |
679 | } else { | |
680 | if (target < limit->p2.dot_limit) | |
681 | clock.p2 = limit->p2.p2_slow; | |
682 | else | |
683 | clock.p2 = limit->p2.p2_fast; | |
684 | } | |
685 | ||
686 | memset(best_clock, 0, sizeof(*best_clock)); | |
687 | max_n = limit->n.max; | |
f77f13e2 | 688 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 689 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 690 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
691 | for (clock.m1 = limit->m1.max; |
692 | clock.m1 >= limit->m1.min; clock.m1--) { | |
693 | for (clock.m2 = limit->m2.max; | |
694 | clock.m2 >= limit->m2.min; clock.m2--) { | |
695 | for (clock.p1 = limit->p1.max; | |
696 | clock.p1 >= limit->p1.min; clock.p1--) { | |
697 | int this_err; | |
698 | ||
ac58c3f0 | 699 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
700 | if (!intel_PLL_is_valid(dev, limit, |
701 | &clock)) | |
d4906093 | 702 | continue; |
1b894b59 CW |
703 | |
704 | this_err = abs(clock.dot - target); | |
d4906093 ML |
705 | if (this_err < err_most) { |
706 | *best_clock = clock; | |
707 | err_most = this_err; | |
708 | max_n = clock.n; | |
709 | found = true; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
2c07245f ZW |
715 | return found; |
716 | } | |
717 | ||
a0c4da24 | 718 | static bool |
ee9300bb DV |
719 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
720 | int target, int refclk, intel_clock_t *match_clock, | |
721 | intel_clock_t *best_clock) | |
a0c4da24 | 722 | { |
f01b7962 | 723 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 724 | intel_clock_t clock; |
69e4f900 | 725 | unsigned int bestppm = 1000000; |
27e639bf VS |
726 | /* min update 19.2 MHz */ |
727 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 728 | bool found = false; |
a0c4da24 | 729 | |
6b4bf1c4 VS |
730 | target *= 5; /* fast clock */ |
731 | ||
732 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
733 | |
734 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 735 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 736 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 737 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 738 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 739 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 740 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 741 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
742 | unsigned int ppm, diff; |
743 | ||
6b4bf1c4 VS |
744 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
745 | refclk * clock.m1); | |
746 | ||
747 | vlv_clock(refclk, &clock); | |
43b0ac53 | 748 | |
f01b7962 VS |
749 | if (!intel_PLL_is_valid(dev, limit, |
750 | &clock)) | |
43b0ac53 VS |
751 | continue; |
752 | ||
6b4bf1c4 VS |
753 | diff = abs(clock.dot - target); |
754 | ppm = div_u64(1000000ULL * diff, target); | |
755 | ||
756 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 757 | bestppm = 0; |
6b4bf1c4 | 758 | *best_clock = clock; |
49e497ef | 759 | found = true; |
43b0ac53 | 760 | } |
6b4bf1c4 | 761 | |
c686122c | 762 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 763 | bestppm = ppm; |
6b4bf1c4 | 764 | *best_clock = clock; |
49e497ef | 765 | found = true; |
a0c4da24 JB |
766 | } |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
a0c4da24 | 771 | |
49e497ef | 772 | return found; |
a0c4da24 | 773 | } |
a4fc5ed6 | 774 | |
ef9348c8 CML |
775 | static bool |
776 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
777 | int target, int refclk, intel_clock_t *match_clock, | |
778 | intel_clock_t *best_clock) | |
779 | { | |
780 | struct drm_device *dev = crtc->dev; | |
781 | intel_clock_t clock; | |
782 | uint64_t m2; | |
783 | int found = false; | |
784 | ||
785 | memset(best_clock, 0, sizeof(*best_clock)); | |
786 | ||
787 | /* | |
788 | * Based on hardware doc, the n always set to 1, and m1 always | |
789 | * set to 2. If requires to support 200Mhz refclk, we need to | |
790 | * revisit this because n may not 1 anymore. | |
791 | */ | |
792 | clock.n = 1, clock.m1 = 2; | |
793 | target *= 5; /* fast clock */ | |
794 | ||
795 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
796 | for (clock.p2 = limit->p2.p2_fast; | |
797 | clock.p2 >= limit->p2.p2_slow; | |
798 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
799 | ||
800 | clock.p = clock.p1 * clock.p2; | |
801 | ||
802 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
803 | clock.n) << 22, refclk * clock.m1); | |
804 | ||
805 | if (m2 > INT_MAX/clock.m1) | |
806 | continue; | |
807 | ||
808 | clock.m2 = m2; | |
809 | ||
810 | chv_clock(refclk, &clock); | |
811 | ||
812 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
813 | continue; | |
814 | ||
815 | /* based on hardware requirement, prefer bigger p | |
816 | */ | |
817 | if (clock.p > best_clock->p) { | |
818 | *best_clock = clock; | |
819 | found = true; | |
820 | } | |
821 | } | |
822 | } | |
823 | ||
824 | return found; | |
825 | } | |
826 | ||
20ddf665 VS |
827 | bool intel_crtc_active(struct drm_crtc *crtc) |
828 | { | |
829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
830 | ||
831 | /* Be paranoid as we can arrive here with only partial | |
832 | * state retrieved from the hardware during setup. | |
833 | * | |
241bfc38 | 834 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
835 | * as Haswell has gained clock readout/fastboot support. |
836 | * | |
66e514c1 | 837 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
838 | * properly reconstruct framebuffers. |
839 | */ | |
f4510a27 | 840 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 841 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
842 | } |
843 | ||
a5c961d1 PZ |
844 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
845 | enum pipe pipe) | |
846 | { | |
847 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
849 | ||
3b117c8f | 850 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
851 | } |
852 | ||
57e22f4a | 853 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
854 | { |
855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 856 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
857 | |
858 | frame = I915_READ(frame_reg); | |
859 | ||
860 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 861 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
862 | } |
863 | ||
9d0498a2 JB |
864 | /** |
865 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
866 | * @dev: drm device | |
867 | * @pipe: pipe to wait for | |
868 | * | |
869 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
870 | * mode setting code. | |
871 | */ | |
872 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 873 | { |
9d0498a2 | 874 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 875 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 876 | |
57e22f4a VS |
877 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
878 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
879 | return; |
880 | } | |
881 | ||
300387c0 CW |
882 | /* Clear existing vblank status. Note this will clear any other |
883 | * sticky status fields as well. | |
884 | * | |
885 | * This races with i915_driver_irq_handler() with the result | |
886 | * that either function could miss a vblank event. Here it is not | |
887 | * fatal, as we will either wait upon the next vblank interrupt or | |
888 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
889 | * called during modeset at which time the GPU should be idle and | |
890 | * should *not* be performing page flips and thus not waiting on | |
891 | * vblanks... | |
892 | * Currently, the result of us stealing a vblank from the irq | |
893 | * handler is that a single frame will be skipped during swapbuffers. | |
894 | */ | |
895 | I915_WRITE(pipestat_reg, | |
896 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
897 | ||
9d0498a2 | 898 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
899 | if (wait_for(I915_READ(pipestat_reg) & |
900 | PIPE_VBLANK_INTERRUPT_STATUS, | |
901 | 50)) | |
9d0498a2 JB |
902 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
903 | } | |
904 | ||
fbf49ea2 VS |
905 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
906 | { | |
907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
908 | u32 reg = PIPEDSL(pipe); | |
909 | u32 line1, line2; | |
910 | u32 line_mask; | |
911 | ||
912 | if (IS_GEN2(dev)) | |
913 | line_mask = DSL_LINEMASK_GEN2; | |
914 | else | |
915 | line_mask = DSL_LINEMASK_GEN3; | |
916 | ||
917 | line1 = I915_READ(reg) & line_mask; | |
918 | mdelay(5); | |
919 | line2 = I915_READ(reg) & line_mask; | |
920 | ||
921 | return line1 == line2; | |
922 | } | |
923 | ||
ab7ad7f6 KP |
924 | /* |
925 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
926 | * @dev: drm device |
927 | * @pipe: pipe to wait for | |
928 | * | |
929 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
930 | * spinning on the vblank interrupt status bit, since we won't actually | |
931 | * see an interrupt when the pipe is disabled. | |
932 | * | |
ab7ad7f6 KP |
933 | * On Gen4 and above: |
934 | * wait for the pipe register state bit to turn off | |
935 | * | |
936 | * Otherwise: | |
937 | * wait for the display line value to settle (it usually | |
938 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 939 | * |
9d0498a2 | 940 | */ |
58e10eb9 | 941 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
942 | { |
943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
944 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
945 | pipe); | |
ab7ad7f6 KP |
946 | |
947 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 948 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
949 | |
950 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
951 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
952 | 100)) | |
284637d9 | 953 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 954 | } else { |
ab7ad7f6 | 955 | /* Wait for the display line to settle */ |
fbf49ea2 | 956 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 957 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 958 | } |
79e53945 JB |
959 | } |
960 | ||
b0ea7d37 DL |
961 | /* |
962 | * ibx_digital_port_connected - is the specified port connected? | |
963 | * @dev_priv: i915 private structure | |
964 | * @port: the port to test | |
965 | * | |
966 | * Returns true if @port is connected, false otherwise. | |
967 | */ | |
968 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
969 | struct intel_digital_port *port) | |
970 | { | |
971 | u32 bit; | |
972 | ||
c36346e3 | 973 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 974 | switch (port->port) { |
c36346e3 DL |
975 | case PORT_B: |
976 | bit = SDE_PORTB_HOTPLUG; | |
977 | break; | |
978 | case PORT_C: | |
979 | bit = SDE_PORTC_HOTPLUG; | |
980 | break; | |
981 | case PORT_D: | |
982 | bit = SDE_PORTD_HOTPLUG; | |
983 | break; | |
984 | default: | |
985 | return true; | |
986 | } | |
987 | } else { | |
eba905b2 | 988 | switch (port->port) { |
c36346e3 DL |
989 | case PORT_B: |
990 | bit = SDE_PORTB_HOTPLUG_CPT; | |
991 | break; | |
992 | case PORT_C: | |
993 | bit = SDE_PORTC_HOTPLUG_CPT; | |
994 | break; | |
995 | case PORT_D: | |
996 | bit = SDE_PORTD_HOTPLUG_CPT; | |
997 | break; | |
998 | default: | |
999 | return true; | |
1000 | } | |
b0ea7d37 DL |
1001 | } |
1002 | ||
1003 | return I915_READ(SDEISR) & bit; | |
1004 | } | |
1005 | ||
b24e7179 JB |
1006 | static const char *state_string(bool enabled) |
1007 | { | |
1008 | return enabled ? "on" : "off"; | |
1009 | } | |
1010 | ||
1011 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1012 | void assert_pll(struct drm_i915_private *dev_priv, |
1013 | enum pipe pipe, bool state) | |
b24e7179 JB |
1014 | { |
1015 | int reg; | |
1016 | u32 val; | |
1017 | bool cur_state; | |
1018 | ||
1019 | reg = DPLL(pipe); | |
1020 | val = I915_READ(reg); | |
1021 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1022 | WARN(cur_state != state, | |
1023 | "PLL state assertion failure (expected %s, current %s)\n", | |
1024 | state_string(state), state_string(cur_state)); | |
1025 | } | |
b24e7179 | 1026 | |
23538ef1 JN |
1027 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1028 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1029 | { | |
1030 | u32 val; | |
1031 | bool cur_state; | |
1032 | ||
1033 | mutex_lock(&dev_priv->dpio_lock); | |
1034 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1035 | mutex_unlock(&dev_priv->dpio_lock); | |
1036 | ||
1037 | cur_state = val & DSI_PLL_VCO_EN; | |
1038 | WARN(cur_state != state, | |
1039 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1040 | state_string(state), state_string(cur_state)); | |
1041 | } | |
1042 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1043 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1044 | ||
55607e8a | 1045 | struct intel_shared_dpll * |
e2b78267 DV |
1046 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1047 | { | |
1048 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1049 | ||
a43f6e0f | 1050 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1051 | return NULL; |
1052 | ||
a43f6e0f | 1053 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1054 | } |
1055 | ||
040484af | 1056 | /* For ILK+ */ |
55607e8a DV |
1057 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1058 | struct intel_shared_dpll *pll, | |
1059 | bool state) | |
040484af | 1060 | { |
040484af | 1061 | bool cur_state; |
5358901f | 1062 | struct intel_dpll_hw_state hw_state; |
040484af | 1063 | |
9d82aa17 ED |
1064 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1065 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1066 | return; | |
1067 | } | |
1068 | ||
92b27b08 | 1069 | if (WARN (!pll, |
46edb027 | 1070 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1071 | return; |
ee7b9f93 | 1072 | |
5358901f | 1073 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1074 | WARN(cur_state != state, |
5358901f DV |
1075 | "%s assertion failure (expected %s, current %s)\n", |
1076 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1077 | } |
040484af JB |
1078 | |
1079 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1080 | enum pipe pipe, bool state) | |
1081 | { | |
1082 | int reg; | |
1083 | u32 val; | |
1084 | bool cur_state; | |
ad80a810 PZ |
1085 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1086 | pipe); | |
040484af | 1087 | |
affa9354 PZ |
1088 | if (HAS_DDI(dev_priv->dev)) { |
1089 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1090 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1091 | val = I915_READ(reg); |
ad80a810 | 1092 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1093 | } else { |
1094 | reg = FDI_TX_CTL(pipe); | |
1095 | val = I915_READ(reg); | |
1096 | cur_state = !!(val & FDI_TX_ENABLE); | |
1097 | } | |
040484af JB |
1098 | WARN(cur_state != state, |
1099 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1100 | state_string(state), state_string(cur_state)); | |
1101 | } | |
1102 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1103 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1104 | ||
1105 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1106 | enum pipe pipe, bool state) | |
1107 | { | |
1108 | int reg; | |
1109 | u32 val; | |
1110 | bool cur_state; | |
1111 | ||
d63fa0dc PZ |
1112 | reg = FDI_RX_CTL(pipe); |
1113 | val = I915_READ(reg); | |
1114 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1115 | WARN(cur_state != state, |
1116 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1117 | state_string(state), state_string(cur_state)); | |
1118 | } | |
1119 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1120 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1121 | ||
1122 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1123 | enum pipe pipe) | |
1124 | { | |
1125 | int reg; | |
1126 | u32 val; | |
1127 | ||
1128 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1129 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1130 | return; |
1131 | ||
bf507ef7 | 1132 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1133 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1134 | return; |
1135 | ||
040484af JB |
1136 | reg = FDI_TX_CTL(pipe); |
1137 | val = I915_READ(reg); | |
1138 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1139 | } | |
1140 | ||
55607e8a DV |
1141 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1142 | enum pipe pipe, bool state) | |
040484af JB |
1143 | { |
1144 | int reg; | |
1145 | u32 val; | |
55607e8a | 1146 | bool cur_state; |
040484af JB |
1147 | |
1148 | reg = FDI_RX_CTL(pipe); | |
1149 | val = I915_READ(reg); | |
55607e8a DV |
1150 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1151 | WARN(cur_state != state, | |
1152 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1153 | state_string(state), state_string(cur_state)); | |
040484af JB |
1154 | } |
1155 | ||
ea0760cf JB |
1156 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1157 | enum pipe pipe) | |
1158 | { | |
1159 | int pp_reg, lvds_reg; | |
1160 | u32 val; | |
1161 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1162 | bool locked = true; |
ea0760cf JB |
1163 | |
1164 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1165 | pp_reg = PCH_PP_CONTROL; | |
1166 | lvds_reg = PCH_LVDS; | |
1167 | } else { | |
1168 | pp_reg = PP_CONTROL; | |
1169 | lvds_reg = LVDS; | |
1170 | } | |
1171 | ||
1172 | val = I915_READ(pp_reg); | |
1173 | if (!(val & PANEL_POWER_ON) || | |
1174 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1175 | locked = false; | |
1176 | ||
1177 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1178 | panel_pipe = PIPE_B; | |
1179 | ||
1180 | WARN(panel_pipe == pipe && locked, | |
1181 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1182 | pipe_name(pipe)); |
ea0760cf JB |
1183 | } |
1184 | ||
93ce0ba6 JN |
1185 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1186 | enum pipe pipe, bool state) | |
1187 | { | |
1188 | struct drm_device *dev = dev_priv->dev; | |
1189 | bool cur_state; | |
1190 | ||
d9d82081 | 1191 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1192 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1193 | else |
5efb3e28 | 1194 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1195 | |
1196 | WARN(cur_state != state, | |
1197 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1198 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1199 | } | |
1200 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1201 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1202 | ||
b840d907 JB |
1203 | void assert_pipe(struct drm_i915_private *dev_priv, |
1204 | enum pipe pipe, bool state) | |
b24e7179 JB |
1205 | { |
1206 | int reg; | |
1207 | u32 val; | |
63d7bbe9 | 1208 | bool cur_state; |
702e7a56 PZ |
1209 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1210 | pipe); | |
b24e7179 | 1211 | |
8e636784 DV |
1212 | /* if we need the pipe A quirk it must be always on */ |
1213 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1214 | state = true; | |
1215 | ||
da7e29bd | 1216 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1217 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1218 | cur_state = false; |
1219 | } else { | |
1220 | reg = PIPECONF(cpu_transcoder); | |
1221 | val = I915_READ(reg); | |
1222 | cur_state = !!(val & PIPECONF_ENABLE); | |
1223 | } | |
1224 | ||
63d7bbe9 JB |
1225 | WARN(cur_state != state, |
1226 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1227 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1228 | } |
1229 | ||
931872fc CW |
1230 | static void assert_plane(struct drm_i915_private *dev_priv, |
1231 | enum plane plane, bool state) | |
b24e7179 JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
931872fc | 1235 | bool cur_state; |
b24e7179 JB |
1236 | |
1237 | reg = DSPCNTR(plane); | |
1238 | val = I915_READ(reg); | |
931872fc CW |
1239 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1240 | WARN(cur_state != state, | |
1241 | "plane %c assertion failure (expected %s, current %s)\n", | |
1242 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1243 | } |
1244 | ||
931872fc CW |
1245 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1246 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1247 | ||
b24e7179 JB |
1248 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1249 | enum pipe pipe) | |
1250 | { | |
653e1026 | 1251 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1252 | int reg, i; |
1253 | u32 val; | |
1254 | int cur_pipe; | |
1255 | ||
653e1026 VS |
1256 | /* Primary planes are fixed to pipes on gen4+ */ |
1257 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1258 | reg = DSPCNTR(pipe); |
1259 | val = I915_READ(reg); | |
83f26f16 | 1260 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1261 | "plane %c assertion failure, should be disabled but not\n", |
1262 | plane_name(pipe)); | |
19ec1358 | 1263 | return; |
28c05794 | 1264 | } |
19ec1358 | 1265 | |
b24e7179 | 1266 | /* Need to check both planes against the pipe */ |
08e2a7de | 1267 | for_each_pipe(i) { |
b24e7179 JB |
1268 | reg = DSPCNTR(i); |
1269 | val = I915_READ(reg); | |
1270 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1271 | DISPPLANE_SEL_PIPE_SHIFT; | |
1272 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1273 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1274 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1275 | } |
1276 | } | |
1277 | ||
19332d7a JB |
1278 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1279 | enum pipe pipe) | |
1280 | { | |
20674eef | 1281 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1282 | int reg, sprite; |
19332d7a JB |
1283 | u32 val; |
1284 | ||
20674eef | 1285 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1286 | for_each_sprite(pipe, sprite) { |
1287 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1288 | val = I915_READ(reg); |
83f26f16 | 1289 | WARN(val & SP_ENABLE, |
20674eef | 1290 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1291 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1292 | } |
1293 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1294 | reg = SPRCTL(pipe); | |
19332d7a | 1295 | val = I915_READ(reg); |
83f26f16 | 1296 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1297 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1298 | plane_name(pipe), pipe_name(pipe)); |
1299 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1300 | reg = DVSCNTR(pipe); | |
19332d7a | 1301 | val = I915_READ(reg); |
83f26f16 | 1302 | WARN(val & DVS_ENABLE, |
06da8da2 | 1303 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1304 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1305 | } |
1306 | } | |
1307 | ||
89eff4be | 1308 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1309 | { |
1310 | u32 val; | |
1311 | bool enabled; | |
1312 | ||
89eff4be | 1313 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1314 | |
92f2584a JB |
1315 | val = I915_READ(PCH_DREF_CONTROL); |
1316 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1317 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1318 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1319 | } | |
1320 | ||
ab9412ba DV |
1321 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe) | |
92f2584a JB |
1323 | { |
1324 | int reg; | |
1325 | u32 val; | |
1326 | bool enabled; | |
1327 | ||
ab9412ba | 1328 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1329 | val = I915_READ(reg); |
1330 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1331 | WARN(enabled, |
1332 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1333 | pipe_name(pipe)); | |
92f2584a JB |
1334 | } |
1335 | ||
4e634389 KP |
1336 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1337 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1338 | { |
1339 | if ((val & DP_PORT_EN) == 0) | |
1340 | return false; | |
1341 | ||
1342 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1343 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1344 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1345 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1346 | return false; | |
44f37d1f CML |
1347 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1348 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1349 | return false; | |
f0575e92 KP |
1350 | } else { |
1351 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1352 | return false; | |
1353 | } | |
1354 | return true; | |
1355 | } | |
1356 | ||
1519b995 KP |
1357 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1358 | enum pipe pipe, u32 val) | |
1359 | { | |
dc0fa718 | 1360 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1361 | return false; |
1362 | ||
1363 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1364 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1365 | return false; |
44f37d1f CML |
1366 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1367 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1368 | return false; | |
1519b995 | 1369 | } else { |
dc0fa718 | 1370 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1371 | return false; |
1372 | } | |
1373 | return true; | |
1374 | } | |
1375 | ||
1376 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1377 | enum pipe pipe, u32 val) | |
1378 | { | |
1379 | if ((val & LVDS_PORT_EN) == 0) | |
1380 | return false; | |
1381 | ||
1382 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1383 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1384 | return false; | |
1385 | } else { | |
1386 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1387 | return false; | |
1388 | } | |
1389 | return true; | |
1390 | } | |
1391 | ||
1392 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1393 | enum pipe pipe, u32 val) | |
1394 | { | |
1395 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1396 | return false; | |
1397 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1398 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1399 | return false; | |
1400 | } else { | |
1401 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1402 | return false; | |
1403 | } | |
1404 | return true; | |
1405 | } | |
1406 | ||
291906f1 | 1407 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1408 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1409 | { |
47a05eca | 1410 | u32 val = I915_READ(reg); |
4e634389 | 1411 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1412 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1413 | reg, pipe_name(pipe)); |
de9a35ab | 1414 | |
75c5da27 DV |
1415 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1416 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1417 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1418 | } |
1419 | ||
1420 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1421 | enum pipe pipe, int reg) | |
1422 | { | |
47a05eca | 1423 | u32 val = I915_READ(reg); |
b70ad586 | 1424 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1425 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1426 | reg, pipe_name(pipe)); |
de9a35ab | 1427 | |
dc0fa718 | 1428 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1429 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1430 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1431 | } |
1432 | ||
1433 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1434 | enum pipe pipe) | |
1435 | { | |
1436 | int reg; | |
1437 | u32 val; | |
291906f1 | 1438 | |
f0575e92 KP |
1439 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1440 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1441 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1442 | |
1443 | reg = PCH_ADPA; | |
1444 | val = I915_READ(reg); | |
b70ad586 | 1445 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1446 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1447 | pipe_name(pipe)); |
291906f1 JB |
1448 | |
1449 | reg = PCH_LVDS; | |
1450 | val = I915_READ(reg); | |
b70ad586 | 1451 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1452 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1453 | pipe_name(pipe)); |
291906f1 | 1454 | |
e2debe91 PZ |
1455 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1456 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1457 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1458 | } |
1459 | ||
40e9cf64 JB |
1460 | static void intel_init_dpio(struct drm_device *dev) |
1461 | { | |
1462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1463 | ||
1464 | if (!IS_VALLEYVIEW(dev)) | |
1465 | return; | |
1466 | ||
a09caddd CML |
1467 | /* |
1468 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1469 | * CHV x1 PHY (DP/HDMI D) | |
1470 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1471 | */ | |
1472 | if (IS_CHERRYVIEW(dev)) { | |
1473 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1474 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1475 | } else { | |
1476 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1477 | } | |
5382f5f3 JB |
1478 | } |
1479 | ||
1480 | static void intel_reset_dpio(struct drm_device *dev) | |
1481 | { | |
1482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1483 | ||
1484 | if (!IS_VALLEYVIEW(dev)) | |
1485 | return; | |
1486 | ||
e5cbfbfb ID |
1487 | /* |
1488 | * Enable the CRI clock source so we can get at the display and the | |
1489 | * reference clock for VGA hotplug / manual detection. | |
1490 | */ | |
404faabc | 1491 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1492 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1493 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1494 | ||
076ed3b2 CML |
1495 | if (IS_CHERRYVIEW(dev)) { |
1496 | enum dpio_phy phy; | |
1497 | u32 val; | |
1498 | ||
1499 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1500 | /* Poll for phypwrgood signal */ | |
1501 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1502 | PHY_POWERGOOD(phy), 1)) | |
1503 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1504 | ||
1505 | /* | |
1506 | * Deassert common lane reset for PHY. | |
1507 | * | |
1508 | * This should only be done on init and resume from S3 | |
1509 | * with both PLLs disabled, or we risk losing DPIO and | |
1510 | * PLL synchronization. | |
1511 | */ | |
1512 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1513 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1514 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1515 | } | |
1516 | ||
1517 | } else { | |
1518 | /* | |
1519 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1520 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1521 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1522 | * b. The other bits such as sfr settings / modesel may all | |
1523 | * be set to 0. | |
1524 | * | |
1525 | * This should only be done on init and resume from S3 with | |
1526 | * both PLLs disabled, or we risk losing DPIO and PLL | |
1527 | * synchronization. | |
1528 | */ | |
1529 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1530 | } | |
40e9cf64 JB |
1531 | } |
1532 | ||
426115cf | 1533 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1534 | { |
426115cf DV |
1535 | struct drm_device *dev = crtc->base.dev; |
1536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1537 | int reg = DPLL(crtc->pipe); | |
1538 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1539 | |
426115cf | 1540 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1541 | |
1542 | /* No really, not for ILK+ */ | |
1543 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1544 | ||
1545 | /* PLL is protected by panel, make sure we can write it */ | |
1546 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1547 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1548 | |
426115cf DV |
1549 | I915_WRITE(reg, dpll); |
1550 | POSTING_READ(reg); | |
1551 | udelay(150); | |
1552 | ||
1553 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1554 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1555 | ||
1556 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1557 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1558 | |
1559 | /* We do this three times for luck */ | |
426115cf | 1560 | I915_WRITE(reg, dpll); |
87442f73 DV |
1561 | POSTING_READ(reg); |
1562 | udelay(150); /* wait for warmup */ | |
426115cf | 1563 | I915_WRITE(reg, dpll); |
87442f73 DV |
1564 | POSTING_READ(reg); |
1565 | udelay(150); /* wait for warmup */ | |
426115cf | 1566 | I915_WRITE(reg, dpll); |
87442f73 DV |
1567 | POSTING_READ(reg); |
1568 | udelay(150); /* wait for warmup */ | |
1569 | } | |
1570 | ||
9d556c99 CML |
1571 | static void chv_enable_pll(struct intel_crtc *crtc) |
1572 | { | |
1573 | struct drm_device *dev = crtc->base.dev; | |
1574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1575 | int pipe = crtc->pipe; | |
1576 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1577 | u32 tmp; |
1578 | ||
1579 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1580 | ||
1581 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1582 | ||
1583 | mutex_lock(&dev_priv->dpio_lock); | |
1584 | ||
1585 | /* Enable back the 10bit clock to display controller */ | |
1586 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1587 | tmp |= DPIO_DCLKP_EN; | |
1588 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1589 | ||
1590 | /* | |
1591 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1592 | */ | |
1593 | udelay(1); | |
1594 | ||
1595 | /* Enable PLL */ | |
a11b0703 | 1596 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1597 | |
1598 | /* Check PLL is locked */ | |
a11b0703 | 1599 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1600 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1601 | ||
a11b0703 VS |
1602 | /* not sure when this should be written */ |
1603 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1604 | POSTING_READ(DPLL_MD(pipe)); | |
1605 | ||
9d556c99 CML |
1606 | mutex_unlock(&dev_priv->dpio_lock); |
1607 | } | |
1608 | ||
66e3d5c0 | 1609 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1610 | { |
66e3d5c0 DV |
1611 | struct drm_device *dev = crtc->base.dev; |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1613 | int reg = DPLL(crtc->pipe); | |
1614 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1615 | |
66e3d5c0 | 1616 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1617 | |
63d7bbe9 | 1618 | /* No really, not for ILK+ */ |
3d13ef2e | 1619 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1620 | |
1621 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1622 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1623 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1624 | |
66e3d5c0 DV |
1625 | I915_WRITE(reg, dpll); |
1626 | ||
1627 | /* Wait for the clocks to stabilize. */ | |
1628 | POSTING_READ(reg); | |
1629 | udelay(150); | |
1630 | ||
1631 | if (INTEL_INFO(dev)->gen >= 4) { | |
1632 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1633 | crtc->config.dpll_hw_state.dpll_md); | |
1634 | } else { | |
1635 | /* The pixel multiplier can only be updated once the | |
1636 | * DPLL is enabled and the clocks are stable. | |
1637 | * | |
1638 | * So write it again. | |
1639 | */ | |
1640 | I915_WRITE(reg, dpll); | |
1641 | } | |
63d7bbe9 JB |
1642 | |
1643 | /* We do this three times for luck */ | |
66e3d5c0 | 1644 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1645 | POSTING_READ(reg); |
1646 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1647 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1648 | POSTING_READ(reg); |
1649 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1650 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1651 | POSTING_READ(reg); |
1652 | udelay(150); /* wait for warmup */ | |
1653 | } | |
1654 | ||
1655 | /** | |
50b44a44 | 1656 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1657 | * @dev_priv: i915 private structure |
1658 | * @pipe: pipe PLL to disable | |
1659 | * | |
1660 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1661 | * | |
1662 | * Note! This is for pre-ILK only. | |
1663 | */ | |
50b44a44 | 1664 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1665 | { |
63d7bbe9 JB |
1666 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1667 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1668 | return; | |
1669 | ||
1670 | /* Make sure the pipe isn't still relying on us */ | |
1671 | assert_pipe_disabled(dev_priv, pipe); | |
1672 | ||
50b44a44 DV |
1673 | I915_WRITE(DPLL(pipe), 0); |
1674 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1675 | } |
1676 | ||
f6071166 JB |
1677 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1678 | { | |
1679 | u32 val = 0; | |
1680 | ||
1681 | /* Make sure the pipe isn't still relying on us */ | |
1682 | assert_pipe_disabled(dev_priv, pipe); | |
1683 | ||
e5cbfbfb ID |
1684 | /* |
1685 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1686 | * The latter is needed for VGA hotplug / manual detection. | |
1687 | */ | |
f6071166 | 1688 | if (pipe == PIPE_B) |
e5cbfbfb | 1689 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1690 | I915_WRITE(DPLL(pipe), val); |
1691 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1692 | |
1693 | } | |
1694 | ||
1695 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1696 | { | |
d752048d | 1697 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1698 | u32 val; |
1699 | ||
a11b0703 VS |
1700 | /* Make sure the pipe isn't still relying on us */ |
1701 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1702 | |
a11b0703 VS |
1703 | /* Set PLL en = 0 */ |
1704 | val = DPLL_SSC_REF_CLOCK_CHV; | |
1705 | if (pipe != PIPE_A) | |
1706 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1707 | I915_WRITE(DPLL(pipe), val); | |
1708 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1709 | |
1710 | mutex_lock(&dev_priv->dpio_lock); | |
1711 | ||
1712 | /* Disable 10bit clock to display controller */ | |
1713 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1714 | val &= ~DPIO_DCLKP_EN; | |
1715 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1716 | ||
1717 | mutex_unlock(&dev_priv->dpio_lock); | |
f6071166 JB |
1718 | } |
1719 | ||
e4607fcf CML |
1720 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1721 | struct intel_digital_port *dport) | |
89b667f8 JB |
1722 | { |
1723 | u32 port_mask; | |
00fc31b7 | 1724 | int dpll_reg; |
89b667f8 | 1725 | |
e4607fcf CML |
1726 | switch (dport->port) { |
1727 | case PORT_B: | |
89b667f8 | 1728 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1729 | dpll_reg = DPLL(0); |
e4607fcf CML |
1730 | break; |
1731 | case PORT_C: | |
89b667f8 | 1732 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1733 | dpll_reg = DPLL(0); |
1734 | break; | |
1735 | case PORT_D: | |
1736 | port_mask = DPLL_PORTD_READY_MASK; | |
1737 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1738 | break; |
1739 | default: | |
1740 | BUG(); | |
1741 | } | |
89b667f8 | 1742 | |
00fc31b7 | 1743 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1744 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1745 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1746 | } |
1747 | ||
b14b1055 DV |
1748 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1749 | { | |
1750 | struct drm_device *dev = crtc->base.dev; | |
1751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1752 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1753 | ||
1754 | WARN_ON(!pll->refcount); | |
1755 | if (pll->active == 0) { | |
1756 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1757 | WARN_ON(pll->on); | |
1758 | assert_shared_dpll_disabled(dev_priv, pll); | |
1759 | ||
1760 | pll->mode_set(dev_priv, pll); | |
1761 | } | |
1762 | } | |
1763 | ||
92f2584a | 1764 | /** |
85b3894f | 1765 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1766 | * @dev_priv: i915 private structure |
1767 | * @pipe: pipe PLL to enable | |
1768 | * | |
1769 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1770 | * drives the transcoder clock. | |
1771 | */ | |
85b3894f | 1772 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1773 | { |
3d13ef2e DL |
1774 | struct drm_device *dev = crtc->base.dev; |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1776 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1777 | |
87a875bb | 1778 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1779 | return; |
1780 | ||
1781 | if (WARN_ON(pll->refcount == 0)) | |
1782 | return; | |
ee7b9f93 | 1783 | |
46edb027 DV |
1784 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1785 | pll->name, pll->active, pll->on, | |
e2b78267 | 1786 | crtc->base.base.id); |
92f2584a | 1787 | |
cdbd2316 DV |
1788 | if (pll->active++) { |
1789 | WARN_ON(!pll->on); | |
e9d6944e | 1790 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1791 | return; |
1792 | } | |
f4a091c7 | 1793 | WARN_ON(pll->on); |
ee7b9f93 | 1794 | |
46edb027 | 1795 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1796 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1797 | pll->on = true; |
92f2584a JB |
1798 | } |
1799 | ||
e2b78267 | 1800 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1801 | { |
3d13ef2e DL |
1802 | struct drm_device *dev = crtc->base.dev; |
1803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1804 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1805 | |
92f2584a | 1806 | /* PCH only available on ILK+ */ |
3d13ef2e | 1807 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1808 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1809 | return; |
92f2584a | 1810 | |
48da64a8 CW |
1811 | if (WARN_ON(pll->refcount == 0)) |
1812 | return; | |
7a419866 | 1813 | |
46edb027 DV |
1814 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1815 | pll->name, pll->active, pll->on, | |
e2b78267 | 1816 | crtc->base.base.id); |
7a419866 | 1817 | |
48da64a8 | 1818 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1819 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1820 | return; |
1821 | } | |
1822 | ||
e9d6944e | 1823 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1824 | WARN_ON(!pll->on); |
cdbd2316 | 1825 | if (--pll->active) |
7a419866 | 1826 | return; |
ee7b9f93 | 1827 | |
46edb027 | 1828 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1829 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1830 | pll->on = false; |
92f2584a JB |
1831 | } |
1832 | ||
b8a4f404 PZ |
1833 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1834 | enum pipe pipe) | |
040484af | 1835 | { |
23670b32 | 1836 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1837 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1839 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1840 | |
1841 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1842 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1843 | |
1844 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1845 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1846 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1847 | |
1848 | /* FDI must be feeding us bits for PCH ports */ | |
1849 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1850 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1851 | ||
23670b32 DV |
1852 | if (HAS_PCH_CPT(dev)) { |
1853 | /* Workaround: Set the timing override bit before enabling the | |
1854 | * pch transcoder. */ | |
1855 | reg = TRANS_CHICKEN2(pipe); | |
1856 | val = I915_READ(reg); | |
1857 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1858 | I915_WRITE(reg, val); | |
59c859d6 | 1859 | } |
23670b32 | 1860 | |
ab9412ba | 1861 | reg = PCH_TRANSCONF(pipe); |
040484af | 1862 | val = I915_READ(reg); |
5f7f726d | 1863 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1864 | |
1865 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1866 | /* | |
1867 | * make the BPC in transcoder be consistent with | |
1868 | * that in pipeconf reg. | |
1869 | */ | |
dfd07d72 DV |
1870 | val &= ~PIPECONF_BPC_MASK; |
1871 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1872 | } |
5f7f726d PZ |
1873 | |
1874 | val &= ~TRANS_INTERLACE_MASK; | |
1875 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1876 | if (HAS_PCH_IBX(dev_priv->dev) && |
1877 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1878 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1879 | else | |
1880 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1881 | else |
1882 | val |= TRANS_PROGRESSIVE; | |
1883 | ||
040484af JB |
1884 | I915_WRITE(reg, val | TRANS_ENABLE); |
1885 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1886 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1887 | } |
1888 | ||
8fb033d7 | 1889 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1890 | enum transcoder cpu_transcoder) |
040484af | 1891 | { |
8fb033d7 | 1892 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1893 | |
1894 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1895 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1896 | |
8fb033d7 | 1897 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1898 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1899 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1900 | |
223a6fdf PZ |
1901 | /* Workaround: set timing override bit. */ |
1902 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1903 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1904 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1905 | ||
25f3ef11 | 1906 | val = TRANS_ENABLE; |
937bb610 | 1907 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1908 | |
9a76b1c6 PZ |
1909 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1910 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1911 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1912 | else |
1913 | val |= TRANS_PROGRESSIVE; | |
1914 | ||
ab9412ba DV |
1915 | I915_WRITE(LPT_TRANSCONF, val); |
1916 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1917 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1918 | } |
1919 | ||
b8a4f404 PZ |
1920 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1921 | enum pipe pipe) | |
040484af | 1922 | { |
23670b32 DV |
1923 | struct drm_device *dev = dev_priv->dev; |
1924 | uint32_t reg, val; | |
040484af JB |
1925 | |
1926 | /* FDI relies on the transcoder */ | |
1927 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1928 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1929 | ||
291906f1 JB |
1930 | /* Ports must be off as well */ |
1931 | assert_pch_ports_disabled(dev_priv, pipe); | |
1932 | ||
ab9412ba | 1933 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1934 | val = I915_READ(reg); |
1935 | val &= ~TRANS_ENABLE; | |
1936 | I915_WRITE(reg, val); | |
1937 | /* wait for PCH transcoder off, transcoder state */ | |
1938 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1939 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1940 | |
1941 | if (!HAS_PCH_IBX(dev)) { | |
1942 | /* Workaround: Clear the timing override chicken bit again. */ | |
1943 | reg = TRANS_CHICKEN2(pipe); | |
1944 | val = I915_READ(reg); | |
1945 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1946 | I915_WRITE(reg, val); | |
1947 | } | |
040484af JB |
1948 | } |
1949 | ||
ab4d966c | 1950 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1951 | { |
8fb033d7 PZ |
1952 | u32 val; |
1953 | ||
ab9412ba | 1954 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1955 | val &= ~TRANS_ENABLE; |
ab9412ba | 1956 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1957 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1958 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1959 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1960 | |
1961 | /* Workaround: clear timing override bit. */ | |
1962 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1963 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1964 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1965 | } |
1966 | ||
b24e7179 | 1967 | /** |
309cfea8 | 1968 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1969 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1970 | * |
0372264a | 1971 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1972 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1973 | */ |
e1fdc473 | 1974 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1975 | { |
0372264a PZ |
1976 | struct drm_device *dev = crtc->base.dev; |
1977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1978 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1979 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1980 | pipe); | |
1a240d4d | 1981 | enum pipe pch_transcoder; |
b24e7179 JB |
1982 | int reg; |
1983 | u32 val; | |
1984 | ||
58c6eaa2 | 1985 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1986 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1987 | assert_sprites_disabled(dev_priv, pipe); |
1988 | ||
681e5811 | 1989 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1990 | pch_transcoder = TRANSCODER_A; |
1991 | else | |
1992 | pch_transcoder = pipe; | |
1993 | ||
b24e7179 JB |
1994 | /* |
1995 | * A pipe without a PLL won't actually be able to drive bits from | |
1996 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1997 | * need the check. | |
1998 | */ | |
1999 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2000 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2001 | assert_dsi_pll_enabled(dev_priv); |
2002 | else | |
2003 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2004 | else { |
30421c4f | 2005 | if (crtc->config.has_pch_encoder) { |
040484af | 2006 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2007 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2008 | assert_fdi_tx_pll_enabled(dev_priv, |
2009 | (enum pipe) cpu_transcoder); | |
040484af JB |
2010 | } |
2011 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2012 | } | |
b24e7179 | 2013 | |
702e7a56 | 2014 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2015 | val = I915_READ(reg); |
7ad25d48 PZ |
2016 | if (val & PIPECONF_ENABLE) { |
2017 | WARN_ON(!(pipe == PIPE_A && | |
2018 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2019 | return; |
7ad25d48 | 2020 | } |
00d70b15 CW |
2021 | |
2022 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2023 | POSTING_READ(reg); |
b24e7179 JB |
2024 | } |
2025 | ||
2026 | /** | |
309cfea8 | 2027 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2028 | * @dev_priv: i915 private structure |
2029 | * @pipe: pipe to disable | |
2030 | * | |
2031 | * Disable @pipe, making sure that various hardware specific requirements | |
2032 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2033 | * | |
2034 | * @pipe should be %PIPE_A or %PIPE_B. | |
2035 | * | |
2036 | * Will wait until the pipe has shut down before returning. | |
2037 | */ | |
2038 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2039 | enum pipe pipe) | |
2040 | { | |
702e7a56 PZ |
2041 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2042 | pipe); | |
b24e7179 JB |
2043 | int reg; |
2044 | u32 val; | |
2045 | ||
2046 | /* | |
2047 | * Make sure planes won't keep trying to pump pixels to us, | |
2048 | * or we might hang the display. | |
2049 | */ | |
2050 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2051 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2052 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2053 | |
2054 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2055 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2056 | return; | |
2057 | ||
702e7a56 | 2058 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2059 | val = I915_READ(reg); |
00d70b15 CW |
2060 | if ((val & PIPECONF_ENABLE) == 0) |
2061 | return; | |
2062 | ||
2063 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2064 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2065 | } | |
2066 | ||
d74362c9 KP |
2067 | /* |
2068 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2069 | * trigger in order to latch. The display address reg provides this. | |
2070 | */ | |
1dba99f4 VS |
2071 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2072 | enum plane plane) | |
d74362c9 | 2073 | { |
3d13ef2e DL |
2074 | struct drm_device *dev = dev_priv->dev; |
2075 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2076 | |
2077 | I915_WRITE(reg, I915_READ(reg)); | |
2078 | POSTING_READ(reg); | |
d74362c9 KP |
2079 | } |
2080 | ||
b24e7179 | 2081 | /** |
262ca2b0 | 2082 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2083 | * @dev_priv: i915 private structure |
2084 | * @plane: plane to enable | |
2085 | * @pipe: pipe being fed | |
2086 | * | |
2087 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2088 | */ | |
262ca2b0 MR |
2089 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2090 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2091 | { |
939c2fe8 VS |
2092 | struct intel_crtc *intel_crtc = |
2093 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2094 | int reg; |
2095 | u32 val; | |
2096 | ||
2097 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2098 | assert_pipe_enabled(dev_priv, pipe); | |
2099 | ||
98ec7739 VS |
2100 | if (intel_crtc->primary_enabled) |
2101 | return; | |
0037f71c | 2102 | |
4c445e0e | 2103 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2104 | |
b24e7179 JB |
2105 | reg = DSPCNTR(plane); |
2106 | val = I915_READ(reg); | |
10efa932 | 2107 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2108 | |
2109 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2110 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2111 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2112 | } | |
2113 | ||
b24e7179 | 2114 | /** |
262ca2b0 | 2115 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2116 | * @dev_priv: i915 private structure |
2117 | * @plane: plane to disable | |
2118 | * @pipe: pipe consuming the data | |
2119 | * | |
2120 | * Disable @plane; should be an independent operation. | |
2121 | */ | |
262ca2b0 MR |
2122 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2123 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2124 | { |
939c2fe8 VS |
2125 | struct intel_crtc *intel_crtc = |
2126 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2127 | int reg; |
2128 | u32 val; | |
2129 | ||
98ec7739 VS |
2130 | if (!intel_crtc->primary_enabled) |
2131 | return; | |
0037f71c | 2132 | |
4c445e0e | 2133 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2134 | |
b24e7179 JB |
2135 | reg = DSPCNTR(plane); |
2136 | val = I915_READ(reg); | |
10efa932 | 2137 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2138 | |
2139 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2140 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2141 | intel_wait_for_vblank(dev_priv->dev, pipe); |
2142 | } | |
2143 | ||
693db184 CW |
2144 | static bool need_vtd_wa(struct drm_device *dev) |
2145 | { | |
2146 | #ifdef CONFIG_INTEL_IOMMU | |
2147 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2148 | return true; | |
2149 | #endif | |
2150 | return false; | |
2151 | } | |
2152 | ||
a57ce0b2 JB |
2153 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2154 | { | |
2155 | int tile_height; | |
2156 | ||
2157 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2158 | return ALIGN(height, tile_height); | |
2159 | } | |
2160 | ||
127bd2ac | 2161 | int |
48b956c5 | 2162 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2163 | struct drm_i915_gem_object *obj, |
919926ae | 2164 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2165 | { |
ce453d81 | 2166 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2167 | u32 alignment; |
2168 | int ret; | |
2169 | ||
05394f39 | 2170 | switch (obj->tiling_mode) { |
6b95a207 | 2171 | case I915_TILING_NONE: |
534843da CW |
2172 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2173 | alignment = 128 * 1024; | |
a6c45cf0 | 2174 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2175 | alignment = 4 * 1024; |
2176 | else | |
2177 | alignment = 64 * 1024; | |
6b95a207 KH |
2178 | break; |
2179 | case I915_TILING_X: | |
2180 | /* pin() will align the object as required by fence */ | |
2181 | alignment = 0; | |
2182 | break; | |
2183 | case I915_TILING_Y: | |
80075d49 | 2184 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2185 | return -EINVAL; |
2186 | default: | |
2187 | BUG(); | |
2188 | } | |
2189 | ||
693db184 CW |
2190 | /* Note that the w/a also requires 64 PTE of padding following the |
2191 | * bo. We currently fill all unused PTE with the shadow page and so | |
2192 | * we should always have valid PTE following the scanout preventing | |
2193 | * the VT-d warning. | |
2194 | */ | |
2195 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2196 | alignment = 256 * 1024; | |
2197 | ||
ce453d81 | 2198 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2199 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2200 | if (ret) |
ce453d81 | 2201 | goto err_interruptible; |
6b95a207 KH |
2202 | |
2203 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2204 | * fence, whereas 965+ only requires a fence if using | |
2205 | * framebuffer compression. For simplicity, we always install | |
2206 | * a fence as the cost is not that onerous. | |
2207 | */ | |
06d98131 | 2208 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2209 | if (ret) |
2210 | goto err_unpin; | |
1690e1eb | 2211 | |
9a5a53b3 | 2212 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2213 | |
ce453d81 | 2214 | dev_priv->mm.interruptible = true; |
6b95a207 | 2215 | return 0; |
48b956c5 CW |
2216 | |
2217 | err_unpin: | |
cc98b413 | 2218 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2219 | err_interruptible: |
2220 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2221 | return ret; |
6b95a207 KH |
2222 | } |
2223 | ||
1690e1eb CW |
2224 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2225 | { | |
2226 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2227 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2228 | } |
2229 | ||
c2c75131 DV |
2230 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2231 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2232 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2233 | unsigned int tiling_mode, | |
2234 | unsigned int cpp, | |
2235 | unsigned int pitch) | |
c2c75131 | 2236 | { |
bc752862 CW |
2237 | if (tiling_mode != I915_TILING_NONE) { |
2238 | unsigned int tile_rows, tiles; | |
c2c75131 | 2239 | |
bc752862 CW |
2240 | tile_rows = *y / 8; |
2241 | *y %= 8; | |
c2c75131 | 2242 | |
bc752862 CW |
2243 | tiles = *x / (512/cpp); |
2244 | *x %= 512/cpp; | |
2245 | ||
2246 | return tile_rows * pitch * 8 + tiles * 4096; | |
2247 | } else { | |
2248 | unsigned int offset; | |
2249 | ||
2250 | offset = *y * pitch + *x * cpp; | |
2251 | *y = 0; | |
2252 | *x = (offset & 4095) / cpp; | |
2253 | return offset & -4096; | |
2254 | } | |
c2c75131 DV |
2255 | } |
2256 | ||
46f297fb JB |
2257 | int intel_format_to_fourcc(int format) |
2258 | { | |
2259 | switch (format) { | |
2260 | case DISPPLANE_8BPP: | |
2261 | return DRM_FORMAT_C8; | |
2262 | case DISPPLANE_BGRX555: | |
2263 | return DRM_FORMAT_XRGB1555; | |
2264 | case DISPPLANE_BGRX565: | |
2265 | return DRM_FORMAT_RGB565; | |
2266 | default: | |
2267 | case DISPPLANE_BGRX888: | |
2268 | return DRM_FORMAT_XRGB8888; | |
2269 | case DISPPLANE_RGBX888: | |
2270 | return DRM_FORMAT_XBGR8888; | |
2271 | case DISPPLANE_BGRX101010: | |
2272 | return DRM_FORMAT_XRGB2101010; | |
2273 | case DISPPLANE_RGBX101010: | |
2274 | return DRM_FORMAT_XBGR2101010; | |
2275 | } | |
2276 | } | |
2277 | ||
484b41dd | 2278 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2279 | struct intel_plane_config *plane_config) |
2280 | { | |
2281 | struct drm_device *dev = crtc->base.dev; | |
2282 | struct drm_i915_gem_object *obj = NULL; | |
2283 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2284 | u32 base = plane_config->base; | |
2285 | ||
ff2652ea CW |
2286 | if (plane_config->size == 0) |
2287 | return false; | |
2288 | ||
46f297fb JB |
2289 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2290 | plane_config->size); | |
2291 | if (!obj) | |
484b41dd | 2292 | return false; |
46f297fb JB |
2293 | |
2294 | if (plane_config->tiled) { | |
2295 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2296 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2297 | } |
2298 | ||
66e514c1 DA |
2299 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2300 | mode_cmd.width = crtc->base.primary->fb->width; | |
2301 | mode_cmd.height = crtc->base.primary->fb->height; | |
2302 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2303 | |
2304 | mutex_lock(&dev->struct_mutex); | |
2305 | ||
66e514c1 | 2306 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2307 | &mode_cmd, obj)) { |
46f297fb JB |
2308 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2309 | goto out_unref_obj; | |
2310 | } | |
2311 | ||
2312 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2313 | |
2314 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2315 | return true; | |
46f297fb JB |
2316 | |
2317 | out_unref_obj: | |
2318 | drm_gem_object_unreference(&obj->base); | |
2319 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2320 | return false; |
2321 | } | |
2322 | ||
2323 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2324 | struct intel_plane_config *plane_config) | |
2325 | { | |
2326 | struct drm_device *dev = intel_crtc->base.dev; | |
2327 | struct drm_crtc *c; | |
2328 | struct intel_crtc *i; | |
2329 | struct intel_framebuffer *fb; | |
2330 | ||
66e514c1 | 2331 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2332 | return; |
2333 | ||
2334 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2335 | return; | |
2336 | ||
66e514c1 DA |
2337 | kfree(intel_crtc->base.primary->fb); |
2338 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2339 | |
2340 | /* | |
2341 | * Failed to alloc the obj, check to see if we should share | |
2342 | * an fb with another CRTC instead | |
2343 | */ | |
70e1e0ec | 2344 | for_each_crtc(dev, c) { |
484b41dd JB |
2345 | i = to_intel_crtc(c); |
2346 | ||
2347 | if (c == &intel_crtc->base) | |
2348 | continue; | |
2349 | ||
66e514c1 | 2350 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2351 | continue; |
2352 | ||
66e514c1 | 2353 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2354 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2355 | drm_framebuffer_reference(c->primary->fb); |
2356 | intel_crtc->base.primary->fb = c->primary->fb; | |
484b41dd JB |
2357 | break; |
2358 | } | |
2359 | } | |
46f297fb JB |
2360 | } |
2361 | ||
29b9bde6 DV |
2362 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2363 | struct drm_framebuffer *fb, | |
2364 | int x, int y) | |
81255565 JB |
2365 | { |
2366 | struct drm_device *dev = crtc->dev; | |
2367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2369 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2370 | struct drm_i915_gem_object *obj; |
81255565 | 2371 | int plane = intel_crtc->plane; |
e506a0c6 | 2372 | unsigned long linear_offset; |
81255565 | 2373 | u32 dspcntr; |
5eddb70b | 2374 | u32 reg; |
81255565 | 2375 | |
81255565 JB |
2376 | intel_fb = to_intel_framebuffer(fb); |
2377 | obj = intel_fb->obj; | |
81255565 | 2378 | |
5eddb70b CW |
2379 | reg = DSPCNTR(plane); |
2380 | dspcntr = I915_READ(reg); | |
81255565 JB |
2381 | /* Mask out pixel format bits in case we change it */ |
2382 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2383 | switch (fb->pixel_format) { |
2384 | case DRM_FORMAT_C8: | |
81255565 JB |
2385 | dspcntr |= DISPPLANE_8BPP; |
2386 | break; | |
57779d06 VS |
2387 | case DRM_FORMAT_XRGB1555: |
2388 | case DRM_FORMAT_ARGB1555: | |
2389 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2390 | break; |
57779d06 VS |
2391 | case DRM_FORMAT_RGB565: |
2392 | dspcntr |= DISPPLANE_BGRX565; | |
2393 | break; | |
2394 | case DRM_FORMAT_XRGB8888: | |
2395 | case DRM_FORMAT_ARGB8888: | |
2396 | dspcntr |= DISPPLANE_BGRX888; | |
2397 | break; | |
2398 | case DRM_FORMAT_XBGR8888: | |
2399 | case DRM_FORMAT_ABGR8888: | |
2400 | dspcntr |= DISPPLANE_RGBX888; | |
2401 | break; | |
2402 | case DRM_FORMAT_XRGB2101010: | |
2403 | case DRM_FORMAT_ARGB2101010: | |
2404 | dspcntr |= DISPPLANE_BGRX101010; | |
2405 | break; | |
2406 | case DRM_FORMAT_XBGR2101010: | |
2407 | case DRM_FORMAT_ABGR2101010: | |
2408 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2409 | break; |
2410 | default: | |
baba133a | 2411 | BUG(); |
81255565 | 2412 | } |
57779d06 | 2413 | |
a6c45cf0 | 2414 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2415 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2416 | dspcntr |= DISPPLANE_TILED; |
2417 | else | |
2418 | dspcntr &= ~DISPPLANE_TILED; | |
2419 | } | |
2420 | ||
de1aa629 VS |
2421 | if (IS_G4X(dev)) |
2422 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2423 | ||
5eddb70b | 2424 | I915_WRITE(reg, dspcntr); |
81255565 | 2425 | |
e506a0c6 | 2426 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2427 | |
c2c75131 DV |
2428 | if (INTEL_INFO(dev)->gen >= 4) { |
2429 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2430 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2431 | fb->bits_per_pixel / 8, | |
2432 | fb->pitches[0]); | |
c2c75131 DV |
2433 | linear_offset -= intel_crtc->dspaddr_offset; |
2434 | } else { | |
e506a0c6 | 2435 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2436 | } |
e506a0c6 | 2437 | |
f343c5f6 BW |
2438 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2439 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2440 | fb->pitches[0]); | |
01f2c773 | 2441 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2442 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2443 | I915_WRITE(DSPSURF(plane), |
2444 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2445 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2446 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2447 | } else |
f343c5f6 | 2448 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2449 | POSTING_READ(reg); |
17638cd6 JB |
2450 | } |
2451 | ||
29b9bde6 DV |
2452 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2453 | struct drm_framebuffer *fb, | |
2454 | int x, int y) | |
17638cd6 JB |
2455 | { |
2456 | struct drm_device *dev = crtc->dev; | |
2457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2458 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2459 | struct intel_framebuffer *intel_fb; | |
2460 | struct drm_i915_gem_object *obj; | |
2461 | int plane = intel_crtc->plane; | |
e506a0c6 | 2462 | unsigned long linear_offset; |
17638cd6 JB |
2463 | u32 dspcntr; |
2464 | u32 reg; | |
2465 | ||
17638cd6 JB |
2466 | intel_fb = to_intel_framebuffer(fb); |
2467 | obj = intel_fb->obj; | |
2468 | ||
2469 | reg = DSPCNTR(plane); | |
2470 | dspcntr = I915_READ(reg); | |
2471 | /* Mask out pixel format bits in case we change it */ | |
2472 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2473 | switch (fb->pixel_format) { |
2474 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2475 | dspcntr |= DISPPLANE_8BPP; |
2476 | break; | |
57779d06 VS |
2477 | case DRM_FORMAT_RGB565: |
2478 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2479 | break; |
57779d06 VS |
2480 | case DRM_FORMAT_XRGB8888: |
2481 | case DRM_FORMAT_ARGB8888: | |
2482 | dspcntr |= DISPPLANE_BGRX888; | |
2483 | break; | |
2484 | case DRM_FORMAT_XBGR8888: | |
2485 | case DRM_FORMAT_ABGR8888: | |
2486 | dspcntr |= DISPPLANE_RGBX888; | |
2487 | break; | |
2488 | case DRM_FORMAT_XRGB2101010: | |
2489 | case DRM_FORMAT_ARGB2101010: | |
2490 | dspcntr |= DISPPLANE_BGRX101010; | |
2491 | break; | |
2492 | case DRM_FORMAT_XBGR2101010: | |
2493 | case DRM_FORMAT_ABGR2101010: | |
2494 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2495 | break; |
2496 | default: | |
baba133a | 2497 | BUG(); |
17638cd6 JB |
2498 | } |
2499 | ||
2500 | if (obj->tiling_mode != I915_TILING_NONE) | |
2501 | dspcntr |= DISPPLANE_TILED; | |
2502 | else | |
2503 | dspcntr &= ~DISPPLANE_TILED; | |
2504 | ||
b42c6009 | 2505 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2506 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2507 | else | |
2508 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2509 | |
2510 | I915_WRITE(reg, dspcntr); | |
2511 | ||
e506a0c6 | 2512 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2513 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2514 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2515 | fb->bits_per_pixel / 8, | |
2516 | fb->pitches[0]); | |
c2c75131 | 2517 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2518 | |
f343c5f6 BW |
2519 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2520 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2521 | fb->pitches[0]); | |
01f2c773 | 2522 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2523 | I915_WRITE(DSPSURF(plane), |
2524 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2525 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2526 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2527 | } else { | |
2528 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2529 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2530 | } | |
17638cd6 | 2531 | POSTING_READ(reg); |
17638cd6 JB |
2532 | } |
2533 | ||
2534 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2535 | static int | |
2536 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2537 | int x, int y, enum mode_set_atomic state) | |
2538 | { | |
2539 | struct drm_device *dev = crtc->dev; | |
2540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2541 | |
6b8e6ed0 CW |
2542 | if (dev_priv->display.disable_fbc) |
2543 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2544 | intel_increase_pllclock(crtc); |
81255565 | 2545 | |
29b9bde6 DV |
2546 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2547 | ||
2548 | return 0; | |
81255565 JB |
2549 | } |
2550 | ||
96a02917 VS |
2551 | void intel_display_handle_reset(struct drm_device *dev) |
2552 | { | |
2553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2554 | struct drm_crtc *crtc; | |
2555 | ||
2556 | /* | |
2557 | * Flips in the rings have been nuked by the reset, | |
2558 | * so complete all pending flips so that user space | |
2559 | * will get its events and not get stuck. | |
2560 | * | |
2561 | * Also update the base address of all primary | |
2562 | * planes to the the last fb to make sure we're | |
2563 | * showing the correct fb after a reset. | |
2564 | * | |
2565 | * Need to make two loops over the crtcs so that we | |
2566 | * don't try to grab a crtc mutex before the | |
2567 | * pending_flip_queue really got woken up. | |
2568 | */ | |
2569 | ||
70e1e0ec | 2570 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2572 | enum plane plane = intel_crtc->plane; | |
2573 | ||
2574 | intel_prepare_page_flip(dev, plane); | |
2575 | intel_finish_page_flip_plane(dev, plane); | |
2576 | } | |
2577 | ||
70e1e0ec | 2578 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2580 | ||
2581 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2582 | /* |
2583 | * FIXME: Once we have proper support for primary planes (and | |
2584 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2585 | * a NULL crtc->primary->fb. |
947fdaad | 2586 | */ |
f4510a27 | 2587 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2588 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2589 | crtc->primary->fb, |
262ca2b0 MR |
2590 | crtc->x, |
2591 | crtc->y); | |
96a02917 VS |
2592 | mutex_unlock(&crtc->mutex); |
2593 | } | |
2594 | } | |
2595 | ||
14667a4b CW |
2596 | static int |
2597 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2598 | { | |
2599 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2600 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2601 | bool was_interruptible = dev_priv->mm.interruptible; | |
2602 | int ret; | |
2603 | ||
14667a4b CW |
2604 | /* Big Hammer, we also need to ensure that any pending |
2605 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2606 | * current scanout is retired before unpinning the old | |
2607 | * framebuffer. | |
2608 | * | |
2609 | * This should only fail upon a hung GPU, in which case we | |
2610 | * can safely continue. | |
2611 | */ | |
2612 | dev_priv->mm.interruptible = false; | |
2613 | ret = i915_gem_object_finish_gpu(obj); | |
2614 | dev_priv->mm.interruptible = was_interruptible; | |
2615 | ||
2616 | return ret; | |
2617 | } | |
2618 | ||
7d5e3799 CW |
2619 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2620 | { | |
2621 | struct drm_device *dev = crtc->dev; | |
2622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2624 | unsigned long flags; | |
2625 | bool pending; | |
2626 | ||
2627 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2628 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2629 | return false; | |
2630 | ||
2631 | spin_lock_irqsave(&dev->event_lock, flags); | |
2632 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2633 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2634 | ||
2635 | return pending; | |
2636 | } | |
2637 | ||
5c3b82e2 | 2638 | static int |
3c4fdcfb | 2639 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2640 | struct drm_framebuffer *fb) |
79e53945 JB |
2641 | { |
2642 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2643 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2644 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2645 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2646 | int ret; |
79e53945 | 2647 | |
7d5e3799 CW |
2648 | if (intel_crtc_has_pending_flip(crtc)) { |
2649 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2650 | return -EBUSY; | |
2651 | } | |
2652 | ||
79e53945 | 2653 | /* no fb bound */ |
94352cf9 | 2654 | if (!fb) { |
a5071c2f | 2655 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2656 | return 0; |
2657 | } | |
2658 | ||
7eb552ae | 2659 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2660 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2661 | plane_name(intel_crtc->plane), | |
2662 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2663 | return -EINVAL; |
79e53945 JB |
2664 | } |
2665 | ||
5c3b82e2 | 2666 | mutex_lock(&dev->struct_mutex); |
265db958 | 2667 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2668 | to_intel_framebuffer(fb)->obj, |
919926ae | 2669 | NULL); |
8ac36ec1 | 2670 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2671 | if (ret != 0) { |
a5071c2f | 2672 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2673 | return ret; |
2674 | } | |
79e53945 | 2675 | |
bb2043de DL |
2676 | /* |
2677 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2678 | * that in compute_mode_changes we check the native mode (not the pfit | |
2679 | * mode) to see if we can flip rather than do a full mode set. In the | |
2680 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2681 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2682 | * sized surface. | |
2683 | * | |
2684 | * To fix this properly, we need to hoist the checks up into | |
2685 | * compute_mode_changes (or above), check the actual pfit state and | |
2686 | * whether the platform allows pfit disable with pipe active, and only | |
2687 | * then update the pipesrc and pfit state, even on the flip path. | |
2688 | */ | |
d330a953 | 2689 | if (i915.fastboot) { |
d7bf63f2 DL |
2690 | const struct drm_display_mode *adjusted_mode = |
2691 | &intel_crtc->config.adjusted_mode; | |
2692 | ||
4d6a3e63 | 2693 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2694 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2695 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2696 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2697 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2698 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2699 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2700 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2701 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2702 | } | |
0637d60d JB |
2703 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2704 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2705 | } |
2706 | ||
29b9bde6 | 2707 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2708 | |
f4510a27 MR |
2709 | old_fb = crtc->primary->fb; |
2710 | crtc->primary->fb = fb; | |
6c4c86f5 DV |
2711 | crtc->x = x; |
2712 | crtc->y = y; | |
94352cf9 | 2713 | |
b7f1de28 | 2714 | if (old_fb) { |
d7697eea DV |
2715 | if (intel_crtc->active && old_fb != fb) |
2716 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2717 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2718 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2719 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2720 | } |
652c393a | 2721 | |
8ac36ec1 | 2722 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2723 | intel_update_fbc(dev); |
4906557e | 2724 | intel_edp_psr_update(dev); |
5c3b82e2 | 2725 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2726 | |
5c3b82e2 | 2727 | return 0; |
79e53945 JB |
2728 | } |
2729 | ||
5e84e1a4 ZW |
2730 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2731 | { | |
2732 | struct drm_device *dev = crtc->dev; | |
2733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2734 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2735 | int pipe = intel_crtc->pipe; | |
2736 | u32 reg, temp; | |
2737 | ||
2738 | /* enable normal train */ | |
2739 | reg = FDI_TX_CTL(pipe); | |
2740 | temp = I915_READ(reg); | |
61e499bf | 2741 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2742 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2743 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2744 | } else { |
2745 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2746 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2747 | } |
5e84e1a4 ZW |
2748 | I915_WRITE(reg, temp); |
2749 | ||
2750 | reg = FDI_RX_CTL(pipe); | |
2751 | temp = I915_READ(reg); | |
2752 | if (HAS_PCH_CPT(dev)) { | |
2753 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2754 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2755 | } else { | |
2756 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2757 | temp |= FDI_LINK_TRAIN_NONE; | |
2758 | } | |
2759 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2760 | ||
2761 | /* wait one idle pattern time */ | |
2762 | POSTING_READ(reg); | |
2763 | udelay(1000); | |
357555c0 JB |
2764 | |
2765 | /* IVB wants error correction enabled */ | |
2766 | if (IS_IVYBRIDGE(dev)) | |
2767 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2768 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2769 | } |
2770 | ||
1fbc0d78 | 2771 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2772 | { |
1fbc0d78 DV |
2773 | return crtc->base.enabled && crtc->active && |
2774 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2775 | } |
2776 | ||
01a415fd DV |
2777 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2778 | { | |
2779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2780 | struct intel_crtc *pipe_B_crtc = | |
2781 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2782 | struct intel_crtc *pipe_C_crtc = | |
2783 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2784 | uint32_t temp; | |
2785 | ||
1e833f40 DV |
2786 | /* |
2787 | * When everything is off disable fdi C so that we could enable fdi B | |
2788 | * with all lanes. Note that we don't care about enabled pipes without | |
2789 | * an enabled pch encoder. | |
2790 | */ | |
2791 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2792 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2793 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2794 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2795 | ||
2796 | temp = I915_READ(SOUTH_CHICKEN1); | |
2797 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2798 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2799 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2800 | } | |
2801 | } | |
2802 | ||
8db9d77b ZW |
2803 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2804 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2805 | { | |
2806 | struct drm_device *dev = crtc->dev; | |
2807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2809 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2810 | u32 reg, temp, tries; |
8db9d77b | 2811 | |
1c8562f6 | 2812 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2813 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2814 | |
e1a44743 AJ |
2815 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2816 | for train result */ | |
5eddb70b CW |
2817 | reg = FDI_RX_IMR(pipe); |
2818 | temp = I915_READ(reg); | |
e1a44743 AJ |
2819 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2820 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2821 | I915_WRITE(reg, temp); |
2822 | I915_READ(reg); | |
e1a44743 AJ |
2823 | udelay(150); |
2824 | ||
8db9d77b | 2825 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2826 | reg = FDI_TX_CTL(pipe); |
2827 | temp = I915_READ(reg); | |
627eb5a3 DV |
2828 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2829 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2830 | temp &= ~FDI_LINK_TRAIN_NONE; |
2831 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2832 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2833 | |
5eddb70b CW |
2834 | reg = FDI_RX_CTL(pipe); |
2835 | temp = I915_READ(reg); | |
8db9d77b ZW |
2836 | temp &= ~FDI_LINK_TRAIN_NONE; |
2837 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2838 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2839 | ||
2840 | POSTING_READ(reg); | |
8db9d77b ZW |
2841 | udelay(150); |
2842 | ||
5b2adf89 | 2843 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2844 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2845 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2846 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2847 | |
5eddb70b | 2848 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2849 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2850 | temp = I915_READ(reg); |
8db9d77b ZW |
2851 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2852 | ||
2853 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2854 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2855 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2856 | break; |
2857 | } | |
8db9d77b | 2858 | } |
e1a44743 | 2859 | if (tries == 5) |
5eddb70b | 2860 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2861 | |
2862 | /* Train 2 */ | |
5eddb70b CW |
2863 | reg = FDI_TX_CTL(pipe); |
2864 | temp = I915_READ(reg); | |
8db9d77b ZW |
2865 | temp &= ~FDI_LINK_TRAIN_NONE; |
2866 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2867 | I915_WRITE(reg, temp); |
8db9d77b | 2868 | |
5eddb70b CW |
2869 | reg = FDI_RX_CTL(pipe); |
2870 | temp = I915_READ(reg); | |
8db9d77b ZW |
2871 | temp &= ~FDI_LINK_TRAIN_NONE; |
2872 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2873 | I915_WRITE(reg, temp); |
8db9d77b | 2874 | |
5eddb70b CW |
2875 | POSTING_READ(reg); |
2876 | udelay(150); | |
8db9d77b | 2877 | |
5eddb70b | 2878 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2879 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2880 | temp = I915_READ(reg); |
8db9d77b ZW |
2881 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2882 | ||
2883 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2884 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2885 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2886 | break; | |
2887 | } | |
8db9d77b | 2888 | } |
e1a44743 | 2889 | if (tries == 5) |
5eddb70b | 2890 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2891 | |
2892 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2893 | |
8db9d77b ZW |
2894 | } |
2895 | ||
0206e353 | 2896 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2897 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2898 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2899 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2900 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2901 | }; | |
2902 | ||
2903 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2904 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2905 | { | |
2906 | struct drm_device *dev = crtc->dev; | |
2907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2909 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2910 | u32 reg, temp, i, retry; |
8db9d77b | 2911 | |
e1a44743 AJ |
2912 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2913 | for train result */ | |
5eddb70b CW |
2914 | reg = FDI_RX_IMR(pipe); |
2915 | temp = I915_READ(reg); | |
e1a44743 AJ |
2916 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2917 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2918 | I915_WRITE(reg, temp); |
2919 | ||
2920 | POSTING_READ(reg); | |
e1a44743 AJ |
2921 | udelay(150); |
2922 | ||
8db9d77b | 2923 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2924 | reg = FDI_TX_CTL(pipe); |
2925 | temp = I915_READ(reg); | |
627eb5a3 DV |
2926 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2927 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2928 | temp &= ~FDI_LINK_TRAIN_NONE; |
2929 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2930 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2931 | /* SNB-B */ | |
2932 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2933 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2934 | |
d74cf324 DV |
2935 | I915_WRITE(FDI_RX_MISC(pipe), |
2936 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2937 | ||
5eddb70b CW |
2938 | reg = FDI_RX_CTL(pipe); |
2939 | temp = I915_READ(reg); | |
8db9d77b ZW |
2940 | if (HAS_PCH_CPT(dev)) { |
2941 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2942 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2943 | } else { | |
2944 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2945 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2946 | } | |
5eddb70b CW |
2947 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2948 | ||
2949 | POSTING_READ(reg); | |
8db9d77b ZW |
2950 | udelay(150); |
2951 | ||
0206e353 | 2952 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2953 | reg = FDI_TX_CTL(pipe); |
2954 | temp = I915_READ(reg); | |
8db9d77b ZW |
2955 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2956 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2957 | I915_WRITE(reg, temp); |
2958 | ||
2959 | POSTING_READ(reg); | |
8db9d77b ZW |
2960 | udelay(500); |
2961 | ||
fa37d39e SP |
2962 | for (retry = 0; retry < 5; retry++) { |
2963 | reg = FDI_RX_IIR(pipe); | |
2964 | temp = I915_READ(reg); | |
2965 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2966 | if (temp & FDI_RX_BIT_LOCK) { | |
2967 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2968 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2969 | break; | |
2970 | } | |
2971 | udelay(50); | |
8db9d77b | 2972 | } |
fa37d39e SP |
2973 | if (retry < 5) |
2974 | break; | |
8db9d77b ZW |
2975 | } |
2976 | if (i == 4) | |
5eddb70b | 2977 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2978 | |
2979 | /* Train 2 */ | |
5eddb70b CW |
2980 | reg = FDI_TX_CTL(pipe); |
2981 | temp = I915_READ(reg); | |
8db9d77b ZW |
2982 | temp &= ~FDI_LINK_TRAIN_NONE; |
2983 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2984 | if (IS_GEN6(dev)) { | |
2985 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2986 | /* SNB-B */ | |
2987 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2988 | } | |
5eddb70b | 2989 | I915_WRITE(reg, temp); |
8db9d77b | 2990 | |
5eddb70b CW |
2991 | reg = FDI_RX_CTL(pipe); |
2992 | temp = I915_READ(reg); | |
8db9d77b ZW |
2993 | if (HAS_PCH_CPT(dev)) { |
2994 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2995 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2996 | } else { | |
2997 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2998 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2999 | } | |
5eddb70b CW |
3000 | I915_WRITE(reg, temp); |
3001 | ||
3002 | POSTING_READ(reg); | |
8db9d77b ZW |
3003 | udelay(150); |
3004 | ||
0206e353 | 3005 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3006 | reg = FDI_TX_CTL(pipe); |
3007 | temp = I915_READ(reg); | |
8db9d77b ZW |
3008 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3009 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3010 | I915_WRITE(reg, temp); |
3011 | ||
3012 | POSTING_READ(reg); | |
8db9d77b ZW |
3013 | udelay(500); |
3014 | ||
fa37d39e SP |
3015 | for (retry = 0; retry < 5; retry++) { |
3016 | reg = FDI_RX_IIR(pipe); | |
3017 | temp = I915_READ(reg); | |
3018 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3019 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3020 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3021 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3022 | break; | |
3023 | } | |
3024 | udelay(50); | |
8db9d77b | 3025 | } |
fa37d39e SP |
3026 | if (retry < 5) |
3027 | break; | |
8db9d77b ZW |
3028 | } |
3029 | if (i == 4) | |
5eddb70b | 3030 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3031 | |
3032 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3033 | } | |
3034 | ||
357555c0 JB |
3035 | /* Manual link training for Ivy Bridge A0 parts */ |
3036 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3037 | { | |
3038 | struct drm_device *dev = crtc->dev; | |
3039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3040 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3041 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3042 | u32 reg, temp, i, j; |
357555c0 JB |
3043 | |
3044 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3045 | for train result */ | |
3046 | reg = FDI_RX_IMR(pipe); | |
3047 | temp = I915_READ(reg); | |
3048 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3049 | temp &= ~FDI_RX_BIT_LOCK; | |
3050 | I915_WRITE(reg, temp); | |
3051 | ||
3052 | POSTING_READ(reg); | |
3053 | udelay(150); | |
3054 | ||
01a415fd DV |
3055 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3056 | I915_READ(FDI_RX_IIR(pipe))); | |
3057 | ||
139ccd3f JB |
3058 | /* Try each vswing and preemphasis setting twice before moving on */ |
3059 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3060 | /* disable first in case we need to retry */ | |
3061 | reg = FDI_TX_CTL(pipe); | |
3062 | temp = I915_READ(reg); | |
3063 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3064 | temp &= ~FDI_TX_ENABLE; | |
3065 | I915_WRITE(reg, temp); | |
357555c0 | 3066 | |
139ccd3f JB |
3067 | reg = FDI_RX_CTL(pipe); |
3068 | temp = I915_READ(reg); | |
3069 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3070 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3071 | temp &= ~FDI_RX_ENABLE; | |
3072 | I915_WRITE(reg, temp); | |
357555c0 | 3073 | |
139ccd3f | 3074 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3075 | reg = FDI_TX_CTL(pipe); |
3076 | temp = I915_READ(reg); | |
139ccd3f JB |
3077 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3078 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3079 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3080 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3081 | temp |= snb_b_fdi_train_param[j/2]; |
3082 | temp |= FDI_COMPOSITE_SYNC; | |
3083 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3084 | |
139ccd3f JB |
3085 | I915_WRITE(FDI_RX_MISC(pipe), |
3086 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3087 | |
139ccd3f | 3088 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3089 | temp = I915_READ(reg); |
139ccd3f JB |
3090 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3091 | temp |= FDI_COMPOSITE_SYNC; | |
3092 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3093 | |
139ccd3f JB |
3094 | POSTING_READ(reg); |
3095 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3096 | |
139ccd3f JB |
3097 | for (i = 0; i < 4; i++) { |
3098 | reg = FDI_RX_IIR(pipe); | |
3099 | temp = I915_READ(reg); | |
3100 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3101 | |
139ccd3f JB |
3102 | if (temp & FDI_RX_BIT_LOCK || |
3103 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3104 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3105 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3106 | i); | |
3107 | break; | |
3108 | } | |
3109 | udelay(1); /* should be 0.5us */ | |
3110 | } | |
3111 | if (i == 4) { | |
3112 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3113 | continue; | |
3114 | } | |
357555c0 | 3115 | |
139ccd3f | 3116 | /* Train 2 */ |
357555c0 JB |
3117 | reg = FDI_TX_CTL(pipe); |
3118 | temp = I915_READ(reg); | |
139ccd3f JB |
3119 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3120 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3121 | I915_WRITE(reg, temp); | |
3122 | ||
3123 | reg = FDI_RX_CTL(pipe); | |
3124 | temp = I915_READ(reg); | |
3125 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3126 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3127 | I915_WRITE(reg, temp); |
3128 | ||
3129 | POSTING_READ(reg); | |
139ccd3f | 3130 | udelay(2); /* should be 1.5us */ |
357555c0 | 3131 | |
139ccd3f JB |
3132 | for (i = 0; i < 4; i++) { |
3133 | reg = FDI_RX_IIR(pipe); | |
3134 | temp = I915_READ(reg); | |
3135 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3136 | |
139ccd3f JB |
3137 | if (temp & FDI_RX_SYMBOL_LOCK || |
3138 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3139 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3140 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3141 | i); | |
3142 | goto train_done; | |
3143 | } | |
3144 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3145 | } |
139ccd3f JB |
3146 | if (i == 4) |
3147 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3148 | } |
357555c0 | 3149 | |
139ccd3f | 3150 | train_done: |
357555c0 JB |
3151 | DRM_DEBUG_KMS("FDI train done.\n"); |
3152 | } | |
3153 | ||
88cefb6c | 3154 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3155 | { |
88cefb6c | 3156 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3157 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3158 | int pipe = intel_crtc->pipe; |
5eddb70b | 3159 | u32 reg, temp; |
79e53945 | 3160 | |
c64e311e | 3161 | |
c98e9dcf | 3162 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3163 | reg = FDI_RX_CTL(pipe); |
3164 | temp = I915_READ(reg); | |
627eb5a3 DV |
3165 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3166 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3167 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3168 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3169 | ||
3170 | POSTING_READ(reg); | |
c98e9dcf JB |
3171 | udelay(200); |
3172 | ||
3173 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3174 | temp = I915_READ(reg); |
3175 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3176 | ||
3177 | POSTING_READ(reg); | |
c98e9dcf JB |
3178 | udelay(200); |
3179 | ||
20749730 PZ |
3180 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3181 | reg = FDI_TX_CTL(pipe); | |
3182 | temp = I915_READ(reg); | |
3183 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3184 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3185 | |
20749730 PZ |
3186 | POSTING_READ(reg); |
3187 | udelay(100); | |
6be4a607 | 3188 | } |
0e23b99d JB |
3189 | } |
3190 | ||
88cefb6c DV |
3191 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3192 | { | |
3193 | struct drm_device *dev = intel_crtc->base.dev; | |
3194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3195 | int pipe = intel_crtc->pipe; | |
3196 | u32 reg, temp; | |
3197 | ||
3198 | /* Switch from PCDclk to Rawclk */ | |
3199 | reg = FDI_RX_CTL(pipe); | |
3200 | temp = I915_READ(reg); | |
3201 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3202 | ||
3203 | /* Disable CPU FDI TX PLL */ | |
3204 | reg = FDI_TX_CTL(pipe); | |
3205 | temp = I915_READ(reg); | |
3206 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3207 | ||
3208 | POSTING_READ(reg); | |
3209 | udelay(100); | |
3210 | ||
3211 | reg = FDI_RX_CTL(pipe); | |
3212 | temp = I915_READ(reg); | |
3213 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3214 | ||
3215 | /* Wait for the clocks to turn off. */ | |
3216 | POSTING_READ(reg); | |
3217 | udelay(100); | |
3218 | } | |
3219 | ||
0fc932b8 JB |
3220 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3221 | { | |
3222 | struct drm_device *dev = crtc->dev; | |
3223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3225 | int pipe = intel_crtc->pipe; | |
3226 | u32 reg, temp; | |
3227 | ||
3228 | /* disable CPU FDI tx and PCH FDI rx */ | |
3229 | reg = FDI_TX_CTL(pipe); | |
3230 | temp = I915_READ(reg); | |
3231 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3232 | POSTING_READ(reg); | |
3233 | ||
3234 | reg = FDI_RX_CTL(pipe); | |
3235 | temp = I915_READ(reg); | |
3236 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3237 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3238 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3239 | ||
3240 | POSTING_READ(reg); | |
3241 | udelay(100); | |
3242 | ||
3243 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3244 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3245 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3246 | |
3247 | /* still set train pattern 1 */ | |
3248 | reg = FDI_TX_CTL(pipe); | |
3249 | temp = I915_READ(reg); | |
3250 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3251 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3252 | I915_WRITE(reg, temp); | |
3253 | ||
3254 | reg = FDI_RX_CTL(pipe); | |
3255 | temp = I915_READ(reg); | |
3256 | if (HAS_PCH_CPT(dev)) { | |
3257 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3258 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3259 | } else { | |
3260 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3261 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3262 | } | |
3263 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3264 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3265 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3266 | I915_WRITE(reg, temp); |
3267 | ||
3268 | POSTING_READ(reg); | |
3269 | udelay(100); | |
3270 | } | |
3271 | ||
5dce5b93 CW |
3272 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3273 | { | |
3274 | struct intel_crtc *crtc; | |
3275 | ||
3276 | /* Note that we don't need to be called with mode_config.lock here | |
3277 | * as our list of CRTC objects is static for the lifetime of the | |
3278 | * device and so cannot disappear as we iterate. Similarly, we can | |
3279 | * happily treat the predicates as racy, atomic checks as userspace | |
3280 | * cannot claim and pin a new fb without at least acquring the | |
3281 | * struct_mutex and so serialising with us. | |
3282 | */ | |
d3fcc808 | 3283 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3284 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3285 | continue; | |
3286 | ||
3287 | if (crtc->unpin_work) | |
3288 | intel_wait_for_vblank(dev, crtc->pipe); | |
3289 | ||
3290 | return true; | |
3291 | } | |
3292 | ||
3293 | return false; | |
3294 | } | |
3295 | ||
e6c3a2a6 CW |
3296 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3297 | { | |
0f91128d | 3298 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3299 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3300 | |
f4510a27 | 3301 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3302 | return; |
3303 | ||
2c10d571 DV |
3304 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3305 | ||
eed6d67d DV |
3306 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3307 | !intel_crtc_has_pending_flip(crtc), | |
3308 | 60*HZ) == 0); | |
5bb61643 | 3309 | |
0f91128d | 3310 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3311 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3312 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3313 | } |
3314 | ||
e615efe4 ED |
3315 | /* Program iCLKIP clock to the desired frequency */ |
3316 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3317 | { | |
3318 | struct drm_device *dev = crtc->dev; | |
3319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3320 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3321 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3322 | u32 temp; | |
3323 | ||
09153000 DV |
3324 | mutex_lock(&dev_priv->dpio_lock); |
3325 | ||
e615efe4 ED |
3326 | /* It is necessary to ungate the pixclk gate prior to programming |
3327 | * the divisors, and gate it back when it is done. | |
3328 | */ | |
3329 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3330 | ||
3331 | /* Disable SSCCTL */ | |
3332 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3333 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3334 | SBI_SSCCTL_DISABLE, | |
3335 | SBI_ICLK); | |
e615efe4 ED |
3336 | |
3337 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3338 | if (clock == 20000) { |
e615efe4 ED |
3339 | auxdiv = 1; |
3340 | divsel = 0x41; | |
3341 | phaseinc = 0x20; | |
3342 | } else { | |
3343 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3344 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3345 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3346 | * convert the virtual clock precision to KHz here for higher |
3347 | * precision. | |
3348 | */ | |
3349 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3350 | u32 iclk_pi_range = 64; | |
3351 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3352 | ||
12d7ceed | 3353 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3354 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3355 | pi_value = desired_divisor % iclk_pi_range; | |
3356 | ||
3357 | auxdiv = 0; | |
3358 | divsel = msb_divisor_value - 2; | |
3359 | phaseinc = pi_value; | |
3360 | } | |
3361 | ||
3362 | /* This should not happen with any sane values */ | |
3363 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3364 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3365 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3366 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3367 | ||
3368 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3369 | clock, |
e615efe4 ED |
3370 | auxdiv, |
3371 | divsel, | |
3372 | phasedir, | |
3373 | phaseinc); | |
3374 | ||
3375 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3376 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3377 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3378 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3379 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3380 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3381 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3382 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3383 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3384 | |
3385 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3386 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3387 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3388 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3389 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3390 | |
3391 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3392 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3393 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3394 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3395 | |
3396 | /* Wait for initialization time */ | |
3397 | udelay(24); | |
3398 | ||
3399 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3400 | |
3401 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3402 | } |
3403 | ||
275f01b2 DV |
3404 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3405 | enum pipe pch_transcoder) | |
3406 | { | |
3407 | struct drm_device *dev = crtc->base.dev; | |
3408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3409 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3410 | ||
3411 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3412 | I915_READ(HTOTAL(cpu_transcoder))); | |
3413 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3414 | I915_READ(HBLANK(cpu_transcoder))); | |
3415 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3416 | I915_READ(HSYNC(cpu_transcoder))); | |
3417 | ||
3418 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3419 | I915_READ(VTOTAL(cpu_transcoder))); | |
3420 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3421 | I915_READ(VBLANK(cpu_transcoder))); | |
3422 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3423 | I915_READ(VSYNC(cpu_transcoder))); | |
3424 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3425 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3426 | } | |
3427 | ||
1fbc0d78 DV |
3428 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3429 | { | |
3430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3431 | uint32_t temp; | |
3432 | ||
3433 | temp = I915_READ(SOUTH_CHICKEN1); | |
3434 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3435 | return; | |
3436 | ||
3437 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3438 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3439 | ||
3440 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3441 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3442 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3443 | POSTING_READ(SOUTH_CHICKEN1); | |
3444 | } | |
3445 | ||
3446 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3447 | { | |
3448 | struct drm_device *dev = intel_crtc->base.dev; | |
3449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3450 | ||
3451 | switch (intel_crtc->pipe) { | |
3452 | case PIPE_A: | |
3453 | break; | |
3454 | case PIPE_B: | |
3455 | if (intel_crtc->config.fdi_lanes > 2) | |
3456 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3457 | else | |
3458 | cpt_enable_fdi_bc_bifurcation(dev); | |
3459 | ||
3460 | break; | |
3461 | case PIPE_C: | |
3462 | cpt_enable_fdi_bc_bifurcation(dev); | |
3463 | ||
3464 | break; | |
3465 | default: | |
3466 | BUG(); | |
3467 | } | |
3468 | } | |
3469 | ||
f67a559d JB |
3470 | /* |
3471 | * Enable PCH resources required for PCH ports: | |
3472 | * - PCH PLLs | |
3473 | * - FDI training & RX/TX | |
3474 | * - update transcoder timings | |
3475 | * - DP transcoding bits | |
3476 | * - transcoder | |
3477 | */ | |
3478 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3479 | { |
3480 | struct drm_device *dev = crtc->dev; | |
3481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3483 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3484 | u32 reg, temp; |
2c07245f | 3485 | |
ab9412ba | 3486 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3487 | |
1fbc0d78 DV |
3488 | if (IS_IVYBRIDGE(dev)) |
3489 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3490 | ||
cd986abb DV |
3491 | /* Write the TU size bits before fdi link training, so that error |
3492 | * detection works. */ | |
3493 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3494 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3495 | ||
c98e9dcf | 3496 | /* For PCH output, training FDI link */ |
674cf967 | 3497 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3498 | |
3ad8a208 DV |
3499 | /* We need to program the right clock selection before writing the pixel |
3500 | * mutliplier into the DPLL. */ | |
303b81e0 | 3501 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3502 | u32 sel; |
4b645f14 | 3503 | |
c98e9dcf | 3504 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3505 | temp |= TRANS_DPLL_ENABLE(pipe); |
3506 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3507 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3508 | temp |= sel; |
3509 | else | |
3510 | temp &= ~sel; | |
c98e9dcf | 3511 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3512 | } |
5eddb70b | 3513 | |
3ad8a208 DV |
3514 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3515 | * transcoder, and we actually should do this to not upset any PCH | |
3516 | * transcoder that already use the clock when we share it. | |
3517 | * | |
3518 | * Note that enable_shared_dpll tries to do the right thing, but | |
3519 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3520 | * the right LVDS enable sequence. */ | |
85b3894f | 3521 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3522 | |
d9b6cb56 JB |
3523 | /* set transcoder timing, panel must allow it */ |
3524 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3525 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3526 | |
303b81e0 | 3527 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3528 | |
c98e9dcf JB |
3529 | /* For PCH DP, enable TRANS_DP_CTL */ |
3530 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3531 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3532 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3533 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3534 | reg = TRANS_DP_CTL(pipe); |
3535 | temp = I915_READ(reg); | |
3536 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3537 | TRANS_DP_SYNC_MASK | |
3538 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3539 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3540 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3541 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3542 | |
3543 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3544 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3545 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3546 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3547 | |
3548 | switch (intel_trans_dp_port_sel(crtc)) { | |
3549 | case PCH_DP_B: | |
5eddb70b | 3550 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3551 | break; |
3552 | case PCH_DP_C: | |
5eddb70b | 3553 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3554 | break; |
3555 | case PCH_DP_D: | |
5eddb70b | 3556 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3557 | break; |
3558 | default: | |
e95d41e1 | 3559 | BUG(); |
32f9d658 | 3560 | } |
2c07245f | 3561 | |
5eddb70b | 3562 | I915_WRITE(reg, temp); |
6be4a607 | 3563 | } |
b52eb4dc | 3564 | |
b8a4f404 | 3565 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3566 | } |
3567 | ||
1507e5bd PZ |
3568 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3569 | { | |
3570 | struct drm_device *dev = crtc->dev; | |
3571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3573 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3574 | |
ab9412ba | 3575 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3576 | |
8c52b5e8 | 3577 | lpt_program_iclkip(crtc); |
1507e5bd | 3578 | |
0540e488 | 3579 | /* Set transcoder timing. */ |
275f01b2 | 3580 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3581 | |
937bb610 | 3582 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3583 | } |
3584 | ||
e2b78267 | 3585 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3586 | { |
e2b78267 | 3587 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3588 | |
3589 | if (pll == NULL) | |
3590 | return; | |
3591 | ||
3592 | if (pll->refcount == 0) { | |
46edb027 | 3593 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3594 | return; |
3595 | } | |
3596 | ||
f4a091c7 DV |
3597 | if (--pll->refcount == 0) { |
3598 | WARN_ON(pll->on); | |
3599 | WARN_ON(pll->active); | |
3600 | } | |
3601 | ||
a43f6e0f | 3602 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3603 | } |
3604 | ||
b89a1d39 | 3605 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3606 | { |
e2b78267 DV |
3607 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3608 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3609 | enum intel_dpll_id i; | |
ee7b9f93 | 3610 | |
ee7b9f93 | 3611 | if (pll) { |
46edb027 DV |
3612 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3613 | crtc->base.base.id, pll->name); | |
e2b78267 | 3614 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3615 | } |
3616 | ||
98b6bd99 DV |
3617 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3618 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3619 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3620 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3621 | |
46edb027 DV |
3622 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3623 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3624 | |
f2a69f44 DV |
3625 | WARN_ON(pll->refcount); |
3626 | ||
98b6bd99 DV |
3627 | goto found; |
3628 | } | |
3629 | ||
e72f9fbf DV |
3630 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3631 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3632 | |
3633 | /* Only want to check enabled timings first */ | |
3634 | if (pll->refcount == 0) | |
3635 | continue; | |
3636 | ||
b89a1d39 DV |
3637 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3638 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3639 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3640 | crtc->base.base.id, |
46edb027 | 3641 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3642 | |
3643 | goto found; | |
3644 | } | |
3645 | } | |
3646 | ||
3647 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3648 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3649 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3650 | if (pll->refcount == 0) { |
46edb027 DV |
3651 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3652 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3653 | goto found; |
3654 | } | |
3655 | } | |
3656 | ||
3657 | return NULL; | |
3658 | ||
3659 | found: | |
f2a69f44 DV |
3660 | if (pll->refcount == 0) |
3661 | pll->hw_state = crtc->config.dpll_hw_state; | |
3662 | ||
a43f6e0f | 3663 | crtc->config.shared_dpll = i; |
46edb027 DV |
3664 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3665 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3666 | |
cdbd2316 | 3667 | pll->refcount++; |
e04c7350 | 3668 | |
ee7b9f93 JB |
3669 | return pll; |
3670 | } | |
3671 | ||
a1520318 | 3672 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3673 | { |
3674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3675 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3676 | u32 temp; |
3677 | ||
3678 | temp = I915_READ(dslreg); | |
3679 | udelay(500); | |
3680 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3681 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3682 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3683 | } |
3684 | } | |
3685 | ||
b074cec8 JB |
3686 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3687 | { | |
3688 | struct drm_device *dev = crtc->base.dev; | |
3689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3690 | int pipe = crtc->pipe; | |
3691 | ||
fd4daa9c | 3692 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3693 | /* Force use of hard-coded filter coefficients |
3694 | * as some pre-programmed values are broken, | |
3695 | * e.g. x201. | |
3696 | */ | |
3697 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3698 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3699 | PF_PIPE_SEL_IVB(pipe)); | |
3700 | else | |
3701 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3702 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3703 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3704 | } |
3705 | } | |
3706 | ||
bb53d4ae VS |
3707 | static void intel_enable_planes(struct drm_crtc *crtc) |
3708 | { | |
3709 | struct drm_device *dev = crtc->dev; | |
3710 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3711 | struct drm_plane *plane; |
bb53d4ae VS |
3712 | struct intel_plane *intel_plane; |
3713 | ||
af2b653b MR |
3714 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3715 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3716 | if (intel_plane->pipe == pipe) |
3717 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3718 | } |
bb53d4ae VS |
3719 | } |
3720 | ||
3721 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3722 | { | |
3723 | struct drm_device *dev = crtc->dev; | |
3724 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3725 | struct drm_plane *plane; |
bb53d4ae VS |
3726 | struct intel_plane *intel_plane; |
3727 | ||
af2b653b MR |
3728 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3729 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3730 | if (intel_plane->pipe == pipe) |
3731 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3732 | } |
bb53d4ae VS |
3733 | } |
3734 | ||
20bc8673 | 3735 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3736 | { |
3737 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3738 | ||
3739 | if (!crtc->config.ips_enabled) | |
3740 | return; | |
3741 | ||
3742 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3743 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3744 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3745 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3746 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3747 | if (IS_BROADWELL(crtc->base.dev)) { |
3748 | mutex_lock(&dev_priv->rps.hw_lock); | |
3749 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3750 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3751 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3752 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3753 | * mailbox." Moreover, the mailbox may return a bogus state, |
3754 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3755 | */ |
3756 | } else { | |
3757 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3758 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3759 | * is essentially intel_wait_for_vblank. If we don't have this | |
3760 | * and don't wait for vblanks until the end of crtc_enable, then | |
3761 | * the HW state readout code will complain that the expected | |
3762 | * IPS_CTL value is not the one we read. */ | |
3763 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3764 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3765 | } | |
d77e4531 PZ |
3766 | } |
3767 | ||
20bc8673 | 3768 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3769 | { |
3770 | struct drm_device *dev = crtc->base.dev; | |
3771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3772 | ||
3773 | if (!crtc->config.ips_enabled) | |
3774 | return; | |
3775 | ||
3776 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3777 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3778 | mutex_lock(&dev_priv->rps.hw_lock); |
3779 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3780 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3781 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3782 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3783 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3784 | } else { |
2a114cc1 | 3785 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3786 | POSTING_READ(IPS_CTL); |
3787 | } | |
d77e4531 PZ |
3788 | |
3789 | /* We need to wait for a vblank before we can disable the plane. */ | |
3790 | intel_wait_for_vblank(dev, crtc->pipe); | |
3791 | } | |
3792 | ||
3793 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3794 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3795 | { | |
3796 | struct drm_device *dev = crtc->dev; | |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3799 | enum pipe pipe = intel_crtc->pipe; | |
3800 | int palreg = PALETTE(pipe); | |
3801 | int i; | |
3802 | bool reenable_ips = false; | |
3803 | ||
3804 | /* The clocks have to be on to load the palette. */ | |
3805 | if (!crtc->enabled || !intel_crtc->active) | |
3806 | return; | |
3807 | ||
3808 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3809 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3810 | assert_dsi_pll_enabled(dev_priv); | |
3811 | else | |
3812 | assert_pll_enabled(dev_priv, pipe); | |
3813 | } | |
3814 | ||
3815 | /* use legacy palette for Ironlake */ | |
3816 | if (HAS_PCH_SPLIT(dev)) | |
3817 | palreg = LGC_PALETTE(pipe); | |
3818 | ||
3819 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3820 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3821 | */ | |
41e6fc4c | 3822 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3823 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3824 | GAMMA_MODE_MODE_SPLIT)) { | |
3825 | hsw_disable_ips(intel_crtc); | |
3826 | reenable_ips = true; | |
3827 | } | |
3828 | ||
3829 | for (i = 0; i < 256; i++) { | |
3830 | I915_WRITE(palreg + 4 * i, | |
3831 | (intel_crtc->lut_r[i] << 16) | | |
3832 | (intel_crtc->lut_g[i] << 8) | | |
3833 | intel_crtc->lut_b[i]); | |
3834 | } | |
3835 | ||
3836 | if (reenable_ips) | |
3837 | hsw_enable_ips(intel_crtc); | |
3838 | } | |
3839 | ||
d3eedb1a VS |
3840 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3841 | { | |
3842 | if (!enable && intel_crtc->overlay) { | |
3843 | struct drm_device *dev = intel_crtc->base.dev; | |
3844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3845 | ||
3846 | mutex_lock(&dev->struct_mutex); | |
3847 | dev_priv->mm.interruptible = false; | |
3848 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3849 | dev_priv->mm.interruptible = true; | |
3850 | mutex_unlock(&dev->struct_mutex); | |
3851 | } | |
3852 | ||
3853 | /* Let userspace switch the overlay on again. In most cases userspace | |
3854 | * has to recompute where to put it anyway. | |
3855 | */ | |
3856 | } | |
3857 | ||
3858 | /** | |
3859 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3860 | * cursor plane briefly if not already running after enabling the display | |
3861 | * plane. | |
3862 | * This workaround avoids occasional blank screens when self refresh is | |
3863 | * enabled. | |
3864 | */ | |
3865 | static void | |
3866 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3867 | { | |
3868 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3869 | ||
3870 | if ((cntl & CURSOR_MODE) == 0) { | |
3871 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3872 | ||
3873 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3874 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3875 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3876 | I915_WRITE(CURCNTR(pipe), cntl); | |
3877 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3878 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3879 | } | |
3880 | } | |
3881 | ||
3882 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
a5c4d7bc VS |
3883 | { |
3884 | struct drm_device *dev = crtc->dev; | |
3885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3887 | int pipe = intel_crtc->pipe; | |
3888 | int plane = intel_crtc->plane; | |
3889 | ||
3890 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); | |
3891 | intel_enable_planes(crtc); | |
d3eedb1a VS |
3892 | /* The fixup needs to happen before cursor is enabled */ |
3893 | if (IS_G4X(dev)) | |
3894 | g4x_fixup_plane(dev_priv, pipe); | |
a5c4d7bc | 3895 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 3896 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3897 | |
3898 | hsw_enable_ips(intel_crtc); | |
3899 | ||
3900 | mutex_lock(&dev->struct_mutex); | |
3901 | intel_update_fbc(dev); | |
71b1c373 | 3902 | intel_edp_psr_update(dev); |
a5c4d7bc VS |
3903 | mutex_unlock(&dev->struct_mutex); |
3904 | } | |
3905 | ||
d3eedb1a | 3906 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3907 | { |
3908 | struct drm_device *dev = crtc->dev; | |
3909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3910 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3911 | int pipe = intel_crtc->pipe; | |
3912 | int plane = intel_crtc->plane; | |
3913 | ||
3914 | intel_crtc_wait_for_pending_flips(crtc); | |
3915 | drm_vblank_off(dev, pipe); | |
3916 | ||
3917 | if (dev_priv->fbc.plane == plane) | |
3918 | intel_disable_fbc(dev); | |
3919 | ||
3920 | hsw_disable_ips(intel_crtc); | |
3921 | ||
d3eedb1a | 3922 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3923 | intel_crtc_update_cursor(crtc, false); |
3924 | intel_disable_planes(crtc); | |
3925 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
3926 | } | |
3927 | ||
f67a559d JB |
3928 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3929 | { | |
3930 | struct drm_device *dev = crtc->dev; | |
3931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3932 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3933 | struct intel_encoder *encoder; |
f67a559d | 3934 | int pipe = intel_crtc->pipe; |
29407aab | 3935 | enum plane plane = intel_crtc->plane; |
f67a559d | 3936 | |
08a48469 DV |
3937 | WARN_ON(!crtc->enabled); |
3938 | ||
f67a559d JB |
3939 | if (intel_crtc->active) |
3940 | return; | |
3941 | ||
b14b1055 DV |
3942 | if (intel_crtc->config.has_pch_encoder) |
3943 | intel_prepare_shared_dpll(intel_crtc); | |
3944 | ||
29407aab DV |
3945 | if (intel_crtc->config.has_dp_encoder) |
3946 | intel_dp_set_m_n(intel_crtc); | |
3947 | ||
3948 | intel_set_pipe_timings(intel_crtc); | |
3949 | ||
3950 | if (intel_crtc->config.has_pch_encoder) { | |
3951 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
3952 | &intel_crtc->config.fdi_m_n); | |
3953 | } | |
3954 | ||
3955 | ironlake_set_pipeconf(crtc); | |
3956 | ||
3957 | /* Set up the display plane register */ | |
3958 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
3959 | POSTING_READ(DSPCNTR(plane)); | |
3960 | ||
3961 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
3962 | crtc->x, crtc->y); | |
3963 | ||
f67a559d | 3964 | intel_crtc->active = true; |
8664281b PZ |
3965 | |
3966 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3967 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3968 | ||
f6736a1a | 3969 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3970 | if (encoder->pre_enable) |
3971 | encoder->pre_enable(encoder); | |
f67a559d | 3972 | |
5bfe2ac0 | 3973 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3974 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3975 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3976 | * enabling. */ | |
88cefb6c | 3977 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3978 | } else { |
3979 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3980 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3981 | } | |
f67a559d | 3982 | |
b074cec8 | 3983 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3984 | |
9c54c0dd JB |
3985 | /* |
3986 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3987 | * clocks enabled | |
3988 | */ | |
3989 | intel_crtc_load_lut(crtc); | |
3990 | ||
f37fcc2a | 3991 | intel_update_watermarks(crtc); |
e1fdc473 | 3992 | intel_enable_pipe(intel_crtc); |
f67a559d | 3993 | |
5bfe2ac0 | 3994 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3995 | ironlake_pch_enable(crtc); |
c98e9dcf | 3996 | |
fa5c73b1 DV |
3997 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3998 | encoder->enable(encoder); | |
61b77ddd DV |
3999 | |
4000 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4001 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4002 | |
d3eedb1a | 4003 | intel_crtc_enable_planes(crtc); |
a5c4d7bc | 4004 | |
6ce94100 DV |
4005 | /* |
4006 | * There seems to be a race in PCH platform hw (at least on some | |
4007 | * outputs) where an enabled pipe still completes any pageflip right | |
4008 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
4009 | * as the first vblank happend, everything works as expected. Hence just | |
4010 | * wait for one vblank before returning to avoid strange things | |
4011 | * happening. | |
4012 | */ | |
4013 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
4014 | } |
4015 | ||
42db64ef PZ |
4016 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4017 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4018 | { | |
f5adf94e | 4019 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4020 | } |
4021 | ||
e4916946 PZ |
4022 | /* |
4023 | * This implements the workaround described in the "notes" section of the mode | |
4024 | * set sequence documentation. When going from no pipes or single pipe to | |
4025 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4026 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4027 | */ | |
4028 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4029 | { | |
4030 | struct drm_device *dev = crtc->base.dev; | |
4031 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4032 | ||
4033 | /* We want to get the other_active_crtc only if there's only 1 other | |
4034 | * active crtc. */ | |
d3fcc808 | 4035 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4036 | if (!crtc_it->active || crtc_it == crtc) |
4037 | continue; | |
4038 | ||
4039 | if (other_active_crtc) | |
4040 | return; | |
4041 | ||
4042 | other_active_crtc = crtc_it; | |
4043 | } | |
4044 | if (!other_active_crtc) | |
4045 | return; | |
4046 | ||
4047 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4048 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4049 | } | |
4050 | ||
4f771f10 PZ |
4051 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4052 | { | |
4053 | struct drm_device *dev = crtc->dev; | |
4054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4056 | struct intel_encoder *encoder; | |
4057 | int pipe = intel_crtc->pipe; | |
229fca97 | 4058 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4059 | |
4060 | WARN_ON(!crtc->enabled); | |
4061 | ||
4062 | if (intel_crtc->active) | |
4063 | return; | |
4064 | ||
229fca97 DV |
4065 | if (intel_crtc->config.has_dp_encoder) |
4066 | intel_dp_set_m_n(intel_crtc); | |
4067 | ||
4068 | intel_set_pipe_timings(intel_crtc); | |
4069 | ||
4070 | if (intel_crtc->config.has_pch_encoder) { | |
4071 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4072 | &intel_crtc->config.fdi_m_n); | |
4073 | } | |
4074 | ||
4075 | haswell_set_pipeconf(crtc); | |
4076 | ||
4077 | intel_set_pipe_csc(crtc); | |
4078 | ||
4079 | /* Set up the display plane register */ | |
4080 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4081 | POSTING_READ(DSPCNTR(plane)); | |
4082 | ||
4083 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4084 | crtc->x, crtc->y); | |
4085 | ||
4f771f10 | 4086 | intel_crtc->active = true; |
8664281b PZ |
4087 | |
4088 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4089 | if (intel_crtc->config.has_pch_encoder) | |
4090 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4091 | ||
5bfe2ac0 | 4092 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4093 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4094 | |
4095 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4096 | if (encoder->pre_enable) | |
4097 | encoder->pre_enable(encoder); | |
4098 | ||
1f544388 | 4099 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4100 | |
b074cec8 | 4101 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4102 | |
4103 | /* | |
4104 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4105 | * clocks enabled | |
4106 | */ | |
4107 | intel_crtc_load_lut(crtc); | |
4108 | ||
1f544388 | 4109 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4110 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4111 | |
f37fcc2a | 4112 | intel_update_watermarks(crtc); |
e1fdc473 | 4113 | intel_enable_pipe(intel_crtc); |
42db64ef | 4114 | |
5bfe2ac0 | 4115 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4116 | lpt_pch_enable(crtc); |
4f771f10 | 4117 | |
8807e55b | 4118 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4119 | encoder->enable(encoder); |
8807e55b JN |
4120 | intel_opregion_notify_encoder(encoder, true); |
4121 | } | |
4f771f10 | 4122 | |
e4916946 PZ |
4123 | /* If we change the relative order between pipe/planes enabling, we need |
4124 | * to change the workaround. */ | |
4125 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4126 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4127 | } |
4128 | ||
3f8dce3a DV |
4129 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4130 | { | |
4131 | struct drm_device *dev = crtc->base.dev; | |
4132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4133 | int pipe = crtc->pipe; | |
4134 | ||
4135 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4136 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4137 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4138 | I915_WRITE(PF_CTL(pipe), 0); |
4139 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4140 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4141 | } | |
4142 | } | |
4143 | ||
6be4a607 JB |
4144 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4145 | { | |
4146 | struct drm_device *dev = crtc->dev; | |
4147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4149 | struct intel_encoder *encoder; |
6be4a607 | 4150 | int pipe = intel_crtc->pipe; |
5eddb70b | 4151 | u32 reg, temp; |
b52eb4dc | 4152 | |
f7abfe8b CW |
4153 | if (!intel_crtc->active) |
4154 | return; | |
4155 | ||
d3eedb1a | 4156 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4157 | |
ea9d758d DV |
4158 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4159 | encoder->disable(encoder); | |
4160 | ||
d925c59a DV |
4161 | if (intel_crtc->config.has_pch_encoder) |
4162 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4163 | ||
b24e7179 | 4164 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4165 | |
3f8dce3a | 4166 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4167 | |
bf49ec8c DV |
4168 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4169 | if (encoder->post_disable) | |
4170 | encoder->post_disable(encoder); | |
2c07245f | 4171 | |
d925c59a DV |
4172 | if (intel_crtc->config.has_pch_encoder) { |
4173 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4174 | |
d925c59a DV |
4175 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4176 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4177 | |
d925c59a DV |
4178 | if (HAS_PCH_CPT(dev)) { |
4179 | /* disable TRANS_DP_CTL */ | |
4180 | reg = TRANS_DP_CTL(pipe); | |
4181 | temp = I915_READ(reg); | |
4182 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4183 | TRANS_DP_PORT_SEL_MASK); | |
4184 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4185 | I915_WRITE(reg, temp); | |
4186 | ||
4187 | /* disable DPLL_SEL */ | |
4188 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4189 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4190 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4191 | } |
e3421a18 | 4192 | |
d925c59a | 4193 | /* disable PCH DPLL */ |
e72f9fbf | 4194 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4195 | |
d925c59a DV |
4196 | ironlake_fdi_pll_disable(intel_crtc); |
4197 | } | |
6b383a7f | 4198 | |
f7abfe8b | 4199 | intel_crtc->active = false; |
46ba614c | 4200 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4201 | |
4202 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4203 | intel_update_fbc(dev); |
71b1c373 | 4204 | intel_edp_psr_update(dev); |
d1ebd816 | 4205 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4206 | } |
1b3c7a47 | 4207 | |
4f771f10 | 4208 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4209 | { |
4f771f10 PZ |
4210 | struct drm_device *dev = crtc->dev; |
4211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4213 | struct intel_encoder *encoder; |
4214 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4215 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4216 | |
4f771f10 PZ |
4217 | if (!intel_crtc->active) |
4218 | return; | |
4219 | ||
d3eedb1a | 4220 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4221 | |
8807e55b JN |
4222 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4223 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4224 | encoder->disable(encoder); |
8807e55b | 4225 | } |
4f771f10 | 4226 | |
8664281b PZ |
4227 | if (intel_crtc->config.has_pch_encoder) |
4228 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4229 | intel_disable_pipe(dev_priv, pipe); |
4230 | ||
ad80a810 | 4231 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4232 | |
3f8dce3a | 4233 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4234 | |
1f544388 | 4235 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4236 | |
4237 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4238 | if (encoder->post_disable) | |
4239 | encoder->post_disable(encoder); | |
4240 | ||
88adfff1 | 4241 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4242 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4243 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4244 | intel_ddi_fdi_disable(crtc); |
83616634 | 4245 | } |
4f771f10 PZ |
4246 | |
4247 | intel_crtc->active = false; | |
46ba614c | 4248 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4249 | |
4250 | mutex_lock(&dev->struct_mutex); | |
4251 | intel_update_fbc(dev); | |
71b1c373 | 4252 | intel_edp_psr_update(dev); |
4f771f10 PZ |
4253 | mutex_unlock(&dev->struct_mutex); |
4254 | } | |
4255 | ||
ee7b9f93 JB |
4256 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4257 | { | |
4258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4259 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4260 | } |
4261 | ||
6441ab5f PZ |
4262 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4263 | { | |
4264 | intel_ddi_put_crtc_pll(crtc); | |
4265 | } | |
4266 | ||
2dd24552 JB |
4267 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4268 | { | |
4269 | struct drm_device *dev = crtc->base.dev; | |
4270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4271 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4272 | ||
328d8e82 | 4273 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4274 | return; |
4275 | ||
2dd24552 | 4276 | /* |
c0b03411 DV |
4277 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4278 | * according to register description and PRM. | |
2dd24552 | 4279 | */ |
c0b03411 DV |
4280 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4281 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4282 | |
b074cec8 JB |
4283 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4284 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4285 | |
4286 | /* Border color in case we don't scale up to the full screen. Black by | |
4287 | * default, change to something else for debugging. */ | |
4288 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4289 | } |
4290 | ||
77d22dca ID |
4291 | #define for_each_power_domain(domain, mask) \ |
4292 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4293 | if ((1 << (domain)) & (mask)) | |
4294 | ||
319be8ae ID |
4295 | enum intel_display_power_domain |
4296 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4297 | { | |
4298 | struct drm_device *dev = intel_encoder->base.dev; | |
4299 | struct intel_digital_port *intel_dig_port; | |
4300 | ||
4301 | switch (intel_encoder->type) { | |
4302 | case INTEL_OUTPUT_UNKNOWN: | |
4303 | /* Only DDI platforms should ever use this output type */ | |
4304 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4305 | case INTEL_OUTPUT_DISPLAYPORT: | |
4306 | case INTEL_OUTPUT_HDMI: | |
4307 | case INTEL_OUTPUT_EDP: | |
4308 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4309 | switch (intel_dig_port->port) { | |
4310 | case PORT_A: | |
4311 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4312 | case PORT_B: | |
4313 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4314 | case PORT_C: | |
4315 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4316 | case PORT_D: | |
4317 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4318 | default: | |
4319 | WARN_ON_ONCE(1); | |
4320 | return POWER_DOMAIN_PORT_OTHER; | |
4321 | } | |
4322 | case INTEL_OUTPUT_ANALOG: | |
4323 | return POWER_DOMAIN_PORT_CRT; | |
4324 | case INTEL_OUTPUT_DSI: | |
4325 | return POWER_DOMAIN_PORT_DSI; | |
4326 | default: | |
4327 | return POWER_DOMAIN_PORT_OTHER; | |
4328 | } | |
4329 | } | |
4330 | ||
4331 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4332 | { |
319be8ae ID |
4333 | struct drm_device *dev = crtc->dev; |
4334 | struct intel_encoder *intel_encoder; | |
4335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4336 | enum pipe pipe = intel_crtc->pipe; | |
4337 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4338 | unsigned long mask; |
4339 | enum transcoder transcoder; | |
4340 | ||
4341 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4342 | ||
4343 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4344 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4345 | if (pfit_enabled) | |
4346 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4347 | ||
319be8ae ID |
4348 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4349 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4350 | ||
77d22dca ID |
4351 | return mask; |
4352 | } | |
4353 | ||
4354 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4355 | bool enable) | |
4356 | { | |
4357 | if (dev_priv->power_domains.init_power_on == enable) | |
4358 | return; | |
4359 | ||
4360 | if (enable) | |
4361 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4362 | else | |
4363 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4364 | ||
4365 | dev_priv->power_domains.init_power_on = enable; | |
4366 | } | |
4367 | ||
4368 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4369 | { | |
4370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4371 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4372 | struct intel_crtc *crtc; | |
4373 | ||
4374 | /* | |
4375 | * First get all needed power domains, then put all unneeded, to avoid | |
4376 | * any unnecessary toggling of the power wells. | |
4377 | */ | |
d3fcc808 | 4378 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4379 | enum intel_display_power_domain domain; |
4380 | ||
4381 | if (!crtc->base.enabled) | |
4382 | continue; | |
4383 | ||
319be8ae | 4384 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4385 | |
4386 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4387 | intel_display_power_get(dev_priv, domain); | |
4388 | } | |
4389 | ||
d3fcc808 | 4390 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4391 | enum intel_display_power_domain domain; |
4392 | ||
4393 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4394 | intel_display_power_put(dev_priv, domain); | |
4395 | ||
4396 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4397 | } | |
4398 | ||
4399 | intel_display_set_init_power(dev_priv, false); | |
4400 | } | |
4401 | ||
586f49dc | 4402 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4403 | { |
586f49dc | 4404 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4405 | |
586f49dc JB |
4406 | /* Obtain SKU information */ |
4407 | mutex_lock(&dev_priv->dpio_lock); | |
4408 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4409 | CCK_FUSE_HPLL_FREQ_MASK; | |
4410 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4411 | |
586f49dc | 4412 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4413 | } |
4414 | ||
4415 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4416 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4417 | { | |
4418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4419 | u32 val, cmd; | |
4420 | ||
d60c4473 ID |
4421 | WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); |
4422 | dev_priv->vlv_cdclk_freq = cdclk; | |
4423 | ||
30a970c6 JB |
4424 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4425 | cmd = 2; | |
4426 | else if (cdclk == 266) | |
4427 | cmd = 1; | |
4428 | else | |
4429 | cmd = 0; | |
4430 | ||
4431 | mutex_lock(&dev_priv->rps.hw_lock); | |
4432 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4433 | val &= ~DSPFREQGUAR_MASK; | |
4434 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4435 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4436 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4437 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4438 | 50)) { | |
4439 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4440 | } | |
4441 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4442 | ||
4443 | if (cdclk == 400) { | |
4444 | u32 divider, vco; | |
4445 | ||
4446 | vco = valleyview_get_vco(dev_priv); | |
4447 | divider = ((vco << 1) / cdclk) - 1; | |
4448 | ||
4449 | mutex_lock(&dev_priv->dpio_lock); | |
4450 | /* adjust cdclk divider */ | |
4451 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4452 | val &= ~0xf; | |
4453 | val |= divider; | |
4454 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4455 | mutex_unlock(&dev_priv->dpio_lock); | |
4456 | } | |
4457 | ||
4458 | mutex_lock(&dev_priv->dpio_lock); | |
4459 | /* adjust self-refresh exit latency value */ | |
4460 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4461 | val &= ~0x7f; | |
4462 | ||
4463 | /* | |
4464 | * For high bandwidth configs, we set a higher latency in the bunit | |
4465 | * so that the core display fetch happens in time to avoid underruns. | |
4466 | */ | |
4467 | if (cdclk == 400) | |
4468 | val |= 4500 / 250; /* 4.5 usec */ | |
4469 | else | |
4470 | val |= 3000 / 250; /* 3.0 usec */ | |
4471 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4472 | mutex_unlock(&dev_priv->dpio_lock); | |
4473 | ||
4474 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4475 | intel_i2c_reset(dev); | |
4476 | } | |
4477 | ||
d60c4473 | 4478 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
30a970c6 JB |
4479 | { |
4480 | int cur_cdclk, vco; | |
4481 | int divider; | |
4482 | ||
4483 | vco = valleyview_get_vco(dev_priv); | |
4484 | ||
4485 | mutex_lock(&dev_priv->dpio_lock); | |
4486 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4487 | mutex_unlock(&dev_priv->dpio_lock); | |
4488 | ||
4489 | divider &= 0xf; | |
4490 | ||
4491 | cur_cdclk = (vco << 1) / (divider + 1); | |
4492 | ||
4493 | return cur_cdclk; | |
4494 | } | |
4495 | ||
4496 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4497 | int max_pixclk) | |
4498 | { | |
30a970c6 JB |
4499 | /* |
4500 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4501 | * 200MHz | |
4502 | * 267MHz | |
4503 | * 320MHz | |
4504 | * 400MHz | |
4505 | * So we check to see whether we're above 90% of the lower bin and | |
4506 | * adjust if needed. | |
4507 | */ | |
4508 | if (max_pixclk > 288000) { | |
4509 | return 400; | |
4510 | } else if (max_pixclk > 240000) { | |
4511 | return 320; | |
4512 | } else | |
4513 | return 266; | |
4514 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4515 | } | |
4516 | ||
2f2d7aa1 VS |
4517 | /* compute the max pixel clock for new configuration */ |
4518 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4519 | { |
4520 | struct drm_device *dev = dev_priv->dev; | |
4521 | struct intel_crtc *intel_crtc; | |
4522 | int max_pixclk = 0; | |
4523 | ||
d3fcc808 | 4524 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4525 | if (intel_crtc->new_enabled) |
30a970c6 | 4526 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4527 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4528 | } |
4529 | ||
4530 | return max_pixclk; | |
4531 | } | |
4532 | ||
4533 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4534 | unsigned *prepare_pipes) |
30a970c6 JB |
4535 | { |
4536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4537 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4538 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4539 | |
d60c4473 ID |
4540 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4541 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4542 | return; |
4543 | ||
2f2d7aa1 | 4544 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4545 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4546 | if (intel_crtc->base.enabled) |
4547 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4548 | } | |
4549 | ||
4550 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4551 | { | |
4552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4553 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4554 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4555 | ||
d60c4473 | 4556 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4557 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4558 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4559 | } |
4560 | ||
89b667f8 JB |
4561 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4562 | { | |
4563 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4564 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4565 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4566 | struct intel_encoder *encoder; | |
4567 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4568 | int plane = intel_crtc->plane; |
23538ef1 | 4569 | bool is_dsi; |
5b18e57c | 4570 | u32 dspcntr; |
89b667f8 JB |
4571 | |
4572 | WARN_ON(!crtc->enabled); | |
4573 | ||
4574 | if (intel_crtc->active) | |
4575 | return; | |
4576 | ||
bdd4b6a6 DV |
4577 | vlv_prepare_pll(intel_crtc); |
4578 | ||
5b18e57c DV |
4579 | /* Set up the display plane register */ |
4580 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4581 | ||
4582 | if (intel_crtc->config.has_dp_encoder) | |
4583 | intel_dp_set_m_n(intel_crtc); | |
4584 | ||
4585 | intel_set_pipe_timings(intel_crtc); | |
4586 | ||
4587 | /* pipesrc and dspsize control the size that is scaled from, | |
4588 | * which should always be the user's requested size. | |
4589 | */ | |
4590 | I915_WRITE(DSPSIZE(plane), | |
4591 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4592 | (intel_crtc->config.pipe_src_w - 1)); | |
4593 | I915_WRITE(DSPPOS(plane), 0); | |
4594 | ||
4595 | i9xx_set_pipeconf(intel_crtc); | |
4596 | ||
4597 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4598 | POSTING_READ(DSPCNTR(plane)); | |
4599 | ||
4600 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4601 | crtc->x, crtc->y); | |
4602 | ||
89b667f8 | 4603 | intel_crtc->active = true; |
89b667f8 | 4604 | |
89b667f8 JB |
4605 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4606 | if (encoder->pre_pll_enable) | |
4607 | encoder->pre_pll_enable(encoder); | |
4608 | ||
23538ef1 JN |
4609 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4610 | ||
9d556c99 CML |
4611 | if (!is_dsi) { |
4612 | if (IS_CHERRYVIEW(dev)) | |
4613 | chv_enable_pll(intel_crtc); | |
4614 | else | |
4615 | vlv_enable_pll(intel_crtc); | |
4616 | } | |
89b667f8 JB |
4617 | |
4618 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4619 | if (encoder->pre_enable) | |
4620 | encoder->pre_enable(encoder); | |
4621 | ||
2dd24552 JB |
4622 | i9xx_pfit_enable(intel_crtc); |
4623 | ||
63cbb074 VS |
4624 | intel_crtc_load_lut(crtc); |
4625 | ||
f37fcc2a | 4626 | intel_update_watermarks(crtc); |
e1fdc473 | 4627 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4628 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
be6a6f8e | 4629 | |
5004945f JN |
4630 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4631 | encoder->enable(encoder); | |
9ab0460b VS |
4632 | |
4633 | intel_crtc_enable_planes(crtc); | |
89b667f8 JB |
4634 | } |
4635 | ||
f13c2ef3 DV |
4636 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4637 | { | |
4638 | struct drm_device *dev = crtc->base.dev; | |
4639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4640 | ||
4641 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4642 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4643 | } | |
4644 | ||
0b8765c6 | 4645 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4646 | { |
4647 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4648 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4650 | struct intel_encoder *encoder; |
79e53945 | 4651 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4652 | int plane = intel_crtc->plane; |
4653 | u32 dspcntr; | |
79e53945 | 4654 | |
08a48469 DV |
4655 | WARN_ON(!crtc->enabled); |
4656 | ||
f7abfe8b CW |
4657 | if (intel_crtc->active) |
4658 | return; | |
4659 | ||
f13c2ef3 DV |
4660 | i9xx_set_pll_dividers(intel_crtc); |
4661 | ||
5b18e57c DV |
4662 | /* Set up the display plane register */ |
4663 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4664 | ||
4665 | if (pipe == 0) | |
4666 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4667 | else | |
4668 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4669 | ||
4670 | if (intel_crtc->config.has_dp_encoder) | |
4671 | intel_dp_set_m_n(intel_crtc); | |
4672 | ||
4673 | intel_set_pipe_timings(intel_crtc); | |
4674 | ||
4675 | /* pipesrc and dspsize control the size that is scaled from, | |
4676 | * which should always be the user's requested size. | |
4677 | */ | |
4678 | I915_WRITE(DSPSIZE(plane), | |
4679 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4680 | (intel_crtc->config.pipe_src_w - 1)); | |
4681 | I915_WRITE(DSPPOS(plane), 0); | |
4682 | ||
4683 | i9xx_set_pipeconf(intel_crtc); | |
4684 | ||
4685 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4686 | POSTING_READ(DSPCNTR(plane)); | |
4687 | ||
4688 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4689 | crtc->x, crtc->y); | |
4690 | ||
f7abfe8b | 4691 | intel_crtc->active = true; |
6b383a7f | 4692 | |
9d6d9f19 MK |
4693 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4694 | if (encoder->pre_enable) | |
4695 | encoder->pre_enable(encoder); | |
4696 | ||
f6736a1a DV |
4697 | i9xx_enable_pll(intel_crtc); |
4698 | ||
2dd24552 JB |
4699 | i9xx_pfit_enable(intel_crtc); |
4700 | ||
63cbb074 VS |
4701 | intel_crtc_load_lut(crtc); |
4702 | ||
f37fcc2a | 4703 | intel_update_watermarks(crtc); |
e1fdc473 | 4704 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4705 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
be6a6f8e | 4706 | |
fa5c73b1 DV |
4707 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4708 | encoder->enable(encoder); | |
9ab0460b VS |
4709 | |
4710 | intel_crtc_enable_planes(crtc); | |
0b8765c6 | 4711 | } |
79e53945 | 4712 | |
87476d63 DV |
4713 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4714 | { | |
4715 | struct drm_device *dev = crtc->base.dev; | |
4716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4717 | |
328d8e82 DV |
4718 | if (!crtc->config.gmch_pfit.control) |
4719 | return; | |
87476d63 | 4720 | |
328d8e82 | 4721 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4722 | |
328d8e82 DV |
4723 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4724 | I915_READ(PFIT_CONTROL)); | |
4725 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4726 | } |
4727 | ||
0b8765c6 JB |
4728 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4729 | { | |
4730 | struct drm_device *dev = crtc->dev; | |
4731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4733 | struct intel_encoder *encoder; |
0b8765c6 | 4734 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4735 | |
f7abfe8b CW |
4736 | if (!intel_crtc->active) |
4737 | return; | |
4738 | ||
9ab0460b VS |
4739 | intel_crtc_disable_planes(crtc); |
4740 | ||
ea9d758d DV |
4741 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4742 | encoder->disable(encoder); | |
4743 | ||
2d9d2b0b | 4744 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4745 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4746 | |
87476d63 | 4747 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4748 | |
89b667f8 JB |
4749 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4750 | if (encoder->post_disable) | |
4751 | encoder->post_disable(encoder); | |
4752 | ||
076ed3b2 CML |
4753 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4754 | if (IS_CHERRYVIEW(dev)) | |
4755 | chv_disable_pll(dev_priv, pipe); | |
4756 | else if (IS_VALLEYVIEW(dev)) | |
4757 | vlv_disable_pll(dev_priv, pipe); | |
4758 | else | |
4759 | i9xx_disable_pll(dev_priv, pipe); | |
4760 | } | |
0b8765c6 | 4761 | |
f7abfe8b | 4762 | intel_crtc->active = false; |
46ba614c | 4763 | intel_update_watermarks(crtc); |
f37fcc2a | 4764 | |
efa9624e | 4765 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4766 | intel_update_fbc(dev); |
71b1c373 | 4767 | intel_edp_psr_update(dev); |
efa9624e | 4768 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4769 | } |
4770 | ||
ee7b9f93 JB |
4771 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4772 | { | |
4773 | } | |
4774 | ||
976f8a20 DV |
4775 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4776 | bool enabled) | |
2c07245f ZW |
4777 | { |
4778 | struct drm_device *dev = crtc->dev; | |
4779 | struct drm_i915_master_private *master_priv; | |
4780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4781 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4782 | |
4783 | if (!dev->primary->master) | |
4784 | return; | |
4785 | ||
4786 | master_priv = dev->primary->master->driver_priv; | |
4787 | if (!master_priv->sarea_priv) | |
4788 | return; | |
4789 | ||
79e53945 JB |
4790 | switch (pipe) { |
4791 | case 0: | |
4792 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4793 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4794 | break; | |
4795 | case 1: | |
4796 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4797 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4798 | break; | |
4799 | default: | |
9db4a9c7 | 4800 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4801 | break; |
4802 | } | |
79e53945 JB |
4803 | } |
4804 | ||
976f8a20 DV |
4805 | /** |
4806 | * Sets the power management mode of the pipe and plane. | |
4807 | */ | |
4808 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4809 | { | |
4810 | struct drm_device *dev = crtc->dev; | |
4811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4812 | struct intel_encoder *intel_encoder; | |
4813 | bool enable = false; | |
4814 | ||
4815 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4816 | enable |= intel_encoder->connectors_active; | |
4817 | ||
4818 | if (enable) | |
4819 | dev_priv->display.crtc_enable(crtc); | |
4820 | else | |
4821 | dev_priv->display.crtc_disable(crtc); | |
4822 | ||
4823 | intel_crtc_update_sarea(crtc, enable); | |
4824 | } | |
4825 | ||
cdd59983 CW |
4826 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4827 | { | |
cdd59983 | 4828 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4829 | struct drm_connector *connector; |
ee7b9f93 | 4830 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 4831 | |
976f8a20 DV |
4832 | /* crtc should still be enabled when we disable it. */ |
4833 | WARN_ON(!crtc->enabled); | |
4834 | ||
4835 | dev_priv->display.crtc_disable(crtc); | |
4836 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4837 | dev_priv->display.off(crtc); |
4838 | ||
931872fc | 4839 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4840 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4841 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 | 4842 | |
f4510a27 | 4843 | if (crtc->primary->fb) { |
cdd59983 | 4844 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 4845 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj); |
cdd59983 | 4846 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4847 | crtc->primary->fb = NULL; |
976f8a20 DV |
4848 | } |
4849 | ||
4850 | /* Update computed state. */ | |
4851 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4852 | if (!connector->encoder || !connector->encoder->crtc) | |
4853 | continue; | |
4854 | ||
4855 | if (connector->encoder->crtc != crtc) | |
4856 | continue; | |
4857 | ||
4858 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4859 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4860 | } |
4861 | } | |
4862 | ||
ea5b213a | 4863 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4864 | { |
4ef69c7a | 4865 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4866 | |
ea5b213a CW |
4867 | drm_encoder_cleanup(encoder); |
4868 | kfree(intel_encoder); | |
7e7d76c3 JB |
4869 | } |
4870 | ||
9237329d | 4871 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4872 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4873 | * state of the entire output pipe. */ | |
9237329d | 4874 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4875 | { |
5ab432ef DV |
4876 | if (mode == DRM_MODE_DPMS_ON) { |
4877 | encoder->connectors_active = true; | |
4878 | ||
b2cabb0e | 4879 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4880 | } else { |
4881 | encoder->connectors_active = false; | |
4882 | ||
b2cabb0e | 4883 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4884 | } |
79e53945 JB |
4885 | } |
4886 | ||
0a91ca29 DV |
4887 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4888 | * internal consistency). */ | |
b980514c | 4889 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4890 | { |
0a91ca29 DV |
4891 | if (connector->get_hw_state(connector)) { |
4892 | struct intel_encoder *encoder = connector->encoder; | |
4893 | struct drm_crtc *crtc; | |
4894 | bool encoder_enabled; | |
4895 | enum pipe pipe; | |
4896 | ||
4897 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4898 | connector->base.base.id, | |
4899 | drm_get_connector_name(&connector->base)); | |
4900 | ||
4901 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4902 | "wrong connector dpms state\n"); | |
4903 | WARN(connector->base.encoder != &encoder->base, | |
4904 | "active connector not linked to encoder\n"); | |
4905 | WARN(!encoder->connectors_active, | |
4906 | "encoder->connectors_active not set\n"); | |
4907 | ||
4908 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4909 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4910 | if (WARN_ON(!encoder->base.crtc)) | |
4911 | return; | |
4912 | ||
4913 | crtc = encoder->base.crtc; | |
4914 | ||
4915 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4916 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4917 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4918 | "encoder active on the wrong pipe\n"); | |
4919 | } | |
79e53945 JB |
4920 | } |
4921 | ||
5ab432ef DV |
4922 | /* Even simpler default implementation, if there's really no special case to |
4923 | * consider. */ | |
4924 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4925 | { |
5ab432ef DV |
4926 | /* All the simple cases only support two dpms states. */ |
4927 | if (mode != DRM_MODE_DPMS_ON) | |
4928 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4929 | |
5ab432ef DV |
4930 | if (mode == connector->dpms) |
4931 | return; | |
4932 | ||
4933 | connector->dpms = mode; | |
4934 | ||
4935 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4936 | if (connector->encoder) |
4937 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4938 | |
b980514c | 4939 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4940 | } |
4941 | ||
f0947c37 DV |
4942 | /* Simple connector->get_hw_state implementation for encoders that support only |
4943 | * one connector and no cloning and hence the encoder state determines the state | |
4944 | * of the connector. */ | |
4945 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4946 | { |
24929352 | 4947 | enum pipe pipe = 0; |
f0947c37 | 4948 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4949 | |
f0947c37 | 4950 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4951 | } |
4952 | ||
1857e1da DV |
4953 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4954 | struct intel_crtc_config *pipe_config) | |
4955 | { | |
4956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4957 | struct intel_crtc *pipe_B_crtc = | |
4958 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4959 | ||
4960 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4961 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4962 | if (pipe_config->fdi_lanes > 4) { | |
4963 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4964 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4965 | return false; | |
4966 | } | |
4967 | ||
bafb6553 | 4968 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4969 | if (pipe_config->fdi_lanes > 2) { |
4970 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4971 | pipe_config->fdi_lanes); | |
4972 | return false; | |
4973 | } else { | |
4974 | return true; | |
4975 | } | |
4976 | } | |
4977 | ||
4978 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4979 | return true; | |
4980 | ||
4981 | /* Ivybridge 3 pipe is really complicated */ | |
4982 | switch (pipe) { | |
4983 | case PIPE_A: | |
4984 | return true; | |
4985 | case PIPE_B: | |
4986 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4987 | pipe_config->fdi_lanes > 2) { | |
4988 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4989 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4990 | return false; | |
4991 | } | |
4992 | return true; | |
4993 | case PIPE_C: | |
1e833f40 | 4994 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4995 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4996 | if (pipe_config->fdi_lanes > 2) { | |
4997 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4998 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4999 | return false; | |
5000 | } | |
5001 | } else { | |
5002 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5003 | return false; | |
5004 | } | |
5005 | return true; | |
5006 | default: | |
5007 | BUG(); | |
5008 | } | |
5009 | } | |
5010 | ||
e29c22c0 DV |
5011 | #define RETRY 1 |
5012 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5013 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5014 | { |
1857e1da | 5015 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5016 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5017 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5018 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5019 | |
e29c22c0 | 5020 | retry: |
877d48d5 DV |
5021 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5022 | * each output octet as 10 bits. The actual frequency | |
5023 | * is stored as a divider into a 100MHz clock, and the | |
5024 | * mode pixel clock is stored in units of 1KHz. | |
5025 | * Hence the bw of each lane in terms of the mode signal | |
5026 | * is: | |
5027 | */ | |
5028 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5029 | ||
241bfc38 | 5030 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5031 | |
2bd89a07 | 5032 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5033 | pipe_config->pipe_bpp); |
5034 | ||
5035 | pipe_config->fdi_lanes = lane; | |
5036 | ||
2bd89a07 | 5037 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5038 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5039 | |
e29c22c0 DV |
5040 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5041 | intel_crtc->pipe, pipe_config); | |
5042 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5043 | pipe_config->pipe_bpp -= 2*3; | |
5044 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5045 | pipe_config->pipe_bpp); | |
5046 | needs_recompute = true; | |
5047 | pipe_config->bw_constrained = true; | |
5048 | ||
5049 | goto retry; | |
5050 | } | |
5051 | ||
5052 | if (needs_recompute) | |
5053 | return RETRY; | |
5054 | ||
5055 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5056 | } |
5057 | ||
42db64ef PZ |
5058 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5059 | struct intel_crtc_config *pipe_config) | |
5060 | { | |
d330a953 | 5061 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5062 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5063 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5064 | } |
5065 | ||
a43f6e0f | 5066 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5067 | struct intel_crtc_config *pipe_config) |
79e53945 | 5068 | { |
a43f6e0f | 5069 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5070 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5071 | |
ad3a4479 | 5072 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5073 | if (INTEL_INFO(dev)->gen < 4) { |
5074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5075 | int clock_limit = | |
5076 | dev_priv->display.get_display_clock_speed(dev); | |
5077 | ||
5078 | /* | |
5079 | * Enable pixel doubling when the dot clock | |
5080 | * is > 90% of the (display) core speed. | |
5081 | * | |
b397c96b VS |
5082 | * GDG double wide on either pipe, |
5083 | * otherwise pipe A only. | |
cf532bb2 | 5084 | */ |
b397c96b | 5085 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5086 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5087 | clock_limit *= 2; |
cf532bb2 | 5088 | pipe_config->double_wide = true; |
ad3a4479 VS |
5089 | } |
5090 | ||
241bfc38 | 5091 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5092 | return -EINVAL; |
2c07245f | 5093 | } |
89749350 | 5094 | |
1d1d0e27 VS |
5095 | /* |
5096 | * Pipe horizontal size must be even in: | |
5097 | * - DVO ganged mode | |
5098 | * - LVDS dual channel mode | |
5099 | * - Double wide pipe | |
5100 | */ | |
5101 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5102 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5103 | pipe_config->pipe_src_w &= ~1; | |
5104 | ||
8693a824 DL |
5105 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5106 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5107 | */ |
5108 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5109 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5110 | return -EINVAL; |
44f46b42 | 5111 | |
bd080ee5 | 5112 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5113 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5114 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5115 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5116 | * for lvds. */ | |
5117 | pipe_config->pipe_bpp = 8*3; | |
5118 | } | |
5119 | ||
f5adf94e | 5120 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5121 | hsw_compute_ips_config(crtc, pipe_config); |
5122 | ||
5123 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
5124 | * clock survives for now. */ | |
5125 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5126 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 5127 | |
877d48d5 | 5128 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5129 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5130 | |
e29c22c0 | 5131 | return 0; |
79e53945 JB |
5132 | } |
5133 | ||
25eb05fc JB |
5134 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5135 | { | |
5136 | return 400000; /* FIXME */ | |
5137 | } | |
5138 | ||
e70236a8 JB |
5139 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5140 | { | |
5141 | return 400000; | |
5142 | } | |
79e53945 | 5143 | |
e70236a8 | 5144 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5145 | { |
e70236a8 JB |
5146 | return 333000; |
5147 | } | |
79e53945 | 5148 | |
e70236a8 JB |
5149 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5150 | { | |
5151 | return 200000; | |
5152 | } | |
79e53945 | 5153 | |
257a7ffc DV |
5154 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5155 | { | |
5156 | u16 gcfgc = 0; | |
5157 | ||
5158 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5159 | ||
5160 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5161 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5162 | return 267000; | |
5163 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5164 | return 333000; | |
5165 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5166 | return 444000; | |
5167 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5168 | return 200000; | |
5169 | default: | |
5170 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5171 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5172 | return 133000; | |
5173 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5174 | return 167000; | |
5175 | } | |
5176 | } | |
5177 | ||
e70236a8 JB |
5178 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5179 | { | |
5180 | u16 gcfgc = 0; | |
79e53945 | 5181 | |
e70236a8 JB |
5182 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5183 | ||
5184 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5185 | return 133000; | |
5186 | else { | |
5187 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5188 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5189 | return 333000; | |
5190 | default: | |
5191 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5192 | return 190000; | |
79e53945 | 5193 | } |
e70236a8 JB |
5194 | } |
5195 | } | |
5196 | ||
5197 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5198 | { | |
5199 | return 266000; | |
5200 | } | |
5201 | ||
5202 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5203 | { | |
5204 | u16 hpllcc = 0; | |
5205 | /* Assume that the hardware is in the high speed state. This | |
5206 | * should be the default. | |
5207 | */ | |
5208 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5209 | case GC_CLOCK_133_200: | |
5210 | case GC_CLOCK_100_200: | |
5211 | return 200000; | |
5212 | case GC_CLOCK_166_250: | |
5213 | return 250000; | |
5214 | case GC_CLOCK_100_133: | |
79e53945 | 5215 | return 133000; |
e70236a8 | 5216 | } |
79e53945 | 5217 | |
e70236a8 JB |
5218 | /* Shouldn't happen */ |
5219 | return 0; | |
5220 | } | |
79e53945 | 5221 | |
e70236a8 JB |
5222 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5223 | { | |
5224 | return 133000; | |
79e53945 JB |
5225 | } |
5226 | ||
2c07245f | 5227 | static void |
a65851af | 5228 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5229 | { |
a65851af VS |
5230 | while (*num > DATA_LINK_M_N_MASK || |
5231 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5232 | *num >>= 1; |
5233 | *den >>= 1; | |
5234 | } | |
5235 | } | |
5236 | ||
a65851af VS |
5237 | static void compute_m_n(unsigned int m, unsigned int n, |
5238 | uint32_t *ret_m, uint32_t *ret_n) | |
5239 | { | |
5240 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5241 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5242 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5243 | } | |
5244 | ||
e69d0bc1 DV |
5245 | void |
5246 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5247 | int pixel_clock, int link_clock, | |
5248 | struct intel_link_m_n *m_n) | |
2c07245f | 5249 | { |
e69d0bc1 | 5250 | m_n->tu = 64; |
a65851af VS |
5251 | |
5252 | compute_m_n(bits_per_pixel * pixel_clock, | |
5253 | link_clock * nlanes * 8, | |
5254 | &m_n->gmch_m, &m_n->gmch_n); | |
5255 | ||
5256 | compute_m_n(pixel_clock, link_clock, | |
5257 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5258 | } |
5259 | ||
a7615030 CW |
5260 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5261 | { | |
d330a953 JN |
5262 | if (i915.panel_use_ssc >= 0) |
5263 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5264 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5265 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5266 | } |
5267 | ||
c65d77d8 JB |
5268 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5269 | { | |
5270 | struct drm_device *dev = crtc->dev; | |
5271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5272 | int refclk; | |
5273 | ||
a0c4da24 | 5274 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5275 | refclk = 100000; |
a0c4da24 | 5276 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5277 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5278 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5279 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5280 | } else if (!IS_GEN2(dev)) { |
5281 | refclk = 96000; | |
5282 | } else { | |
5283 | refclk = 48000; | |
5284 | } | |
5285 | ||
5286 | return refclk; | |
5287 | } | |
5288 | ||
7429e9d4 | 5289 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5290 | { |
7df00d7a | 5291 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5292 | } |
f47709a9 | 5293 | |
7429e9d4 DV |
5294 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5295 | { | |
5296 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5297 | } |
5298 | ||
f47709a9 | 5299 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5300 | intel_clock_t *reduced_clock) |
5301 | { | |
f47709a9 | 5302 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5303 | u32 fp, fp2 = 0; |
5304 | ||
5305 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5306 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5307 | if (reduced_clock) |
7429e9d4 | 5308 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5309 | } else { |
7429e9d4 | 5310 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5311 | if (reduced_clock) |
7429e9d4 | 5312 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5313 | } |
5314 | ||
8bcc2795 | 5315 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5316 | |
f47709a9 DV |
5317 | crtc->lowfreq_avail = false; |
5318 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5319 | reduced_clock && i915.powersave) { |
8bcc2795 | 5320 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5321 | crtc->lowfreq_avail = true; |
a7516a05 | 5322 | } else { |
8bcc2795 | 5323 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5324 | } |
5325 | } | |
5326 | ||
5e69f97f CML |
5327 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5328 | pipe) | |
89b667f8 JB |
5329 | { |
5330 | u32 reg_val; | |
5331 | ||
5332 | /* | |
5333 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5334 | * and set it to a reasonable value instead. | |
5335 | */ | |
ab3c759a | 5336 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5337 | reg_val &= 0xffffff00; |
5338 | reg_val |= 0x00000030; | |
ab3c759a | 5339 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5340 | |
ab3c759a | 5341 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5342 | reg_val &= 0x8cffffff; |
5343 | reg_val = 0x8c000000; | |
ab3c759a | 5344 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5345 | |
ab3c759a | 5346 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5347 | reg_val &= 0xffffff00; |
ab3c759a | 5348 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5349 | |
ab3c759a | 5350 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5351 | reg_val &= 0x00ffffff; |
5352 | reg_val |= 0xb0000000; | |
ab3c759a | 5353 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5354 | } |
5355 | ||
b551842d DV |
5356 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5357 | struct intel_link_m_n *m_n) | |
5358 | { | |
5359 | struct drm_device *dev = crtc->base.dev; | |
5360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5361 | int pipe = crtc->pipe; | |
5362 | ||
e3b95f1e DV |
5363 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5364 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5365 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5366 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5367 | } |
5368 | ||
5369 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5370 | struct intel_link_m_n *m_n) | |
5371 | { | |
5372 | struct drm_device *dev = crtc->base.dev; | |
5373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5374 | int pipe = crtc->pipe; | |
5375 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5376 | ||
5377 | if (INTEL_INFO(dev)->gen >= 5) { | |
5378 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5379 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5380 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5381 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5382 | } else { | |
e3b95f1e DV |
5383 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5384 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5385 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5386 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5387 | } |
5388 | } | |
5389 | ||
03afc4a2 DV |
5390 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5391 | { | |
5392 | if (crtc->config.has_pch_encoder) | |
5393 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5394 | else | |
5395 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5396 | } | |
5397 | ||
f47709a9 | 5398 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5399 | { |
5400 | u32 dpll, dpll_md; | |
5401 | ||
5402 | /* | |
5403 | * Enable DPIO clock input. We should never disable the reference | |
5404 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5405 | * on it. | |
5406 | */ | |
5407 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5408 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5409 | /* We should never disable this, set it here for state tracking */ | |
5410 | if (crtc->pipe == PIPE_B) | |
5411 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5412 | dpll |= DPLL_VCO_ENABLE; | |
5413 | crtc->config.dpll_hw_state.dpll = dpll; | |
5414 | ||
5415 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5416 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5417 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5418 | } | |
5419 | ||
5420 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5421 | { |
f47709a9 | 5422 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5423 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5424 | int pipe = crtc->pipe; |
bdd4b6a6 | 5425 | u32 mdiv; |
a0c4da24 | 5426 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5427 | u32 coreclk, reg_val; |
a0c4da24 | 5428 | |
09153000 DV |
5429 | mutex_lock(&dev_priv->dpio_lock); |
5430 | ||
f47709a9 DV |
5431 | bestn = crtc->config.dpll.n; |
5432 | bestm1 = crtc->config.dpll.m1; | |
5433 | bestm2 = crtc->config.dpll.m2; | |
5434 | bestp1 = crtc->config.dpll.p1; | |
5435 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5436 | |
89b667f8 JB |
5437 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5438 | ||
5439 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5440 | if (pipe == PIPE_B) |
5e69f97f | 5441 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5442 | |
5443 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5444 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5445 | |
5446 | /* Disable target IRef on PLL */ | |
ab3c759a | 5447 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5448 | reg_val &= 0x00ffffff; |
ab3c759a | 5449 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5450 | |
5451 | /* Disable fast lock */ | |
ab3c759a | 5452 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5453 | |
5454 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5455 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5456 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5457 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5458 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5459 | |
5460 | /* | |
5461 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5462 | * but we don't support that). | |
5463 | * Note: don't use the DAC post divider as it seems unstable. | |
5464 | */ | |
5465 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5466 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5467 | |
a0c4da24 | 5468 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5469 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5470 | |
89b667f8 | 5471 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5472 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5473 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5474 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5475 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5476 | 0x009f0003); |
89b667f8 | 5477 | else |
ab3c759a | 5478 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5479 | 0x00d0000f); |
5480 | ||
5481 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5482 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5483 | /* Use SSC source */ | |
bdd4b6a6 | 5484 | if (pipe == PIPE_A) |
ab3c759a | 5485 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5486 | 0x0df40000); |
5487 | else | |
ab3c759a | 5488 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5489 | 0x0df70000); |
5490 | } else { /* HDMI or VGA */ | |
5491 | /* Use bend source */ | |
bdd4b6a6 | 5492 | if (pipe == PIPE_A) |
ab3c759a | 5493 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5494 | 0x0df70000); |
5495 | else | |
ab3c759a | 5496 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5497 | 0x0df40000); |
5498 | } | |
a0c4da24 | 5499 | |
ab3c759a | 5500 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5501 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5502 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5503 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5504 | coreclk |= 0x01000000; | |
ab3c759a | 5505 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5506 | |
ab3c759a | 5507 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5508 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5509 | } |
5510 | ||
9d556c99 CML |
5511 | static void chv_update_pll(struct intel_crtc *crtc) |
5512 | { | |
5513 | struct drm_device *dev = crtc->base.dev; | |
5514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5515 | int pipe = crtc->pipe; | |
5516 | int dpll_reg = DPLL(crtc->pipe); | |
5517 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5518 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5519 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5520 | int refclk; | |
5521 | ||
a11b0703 VS |
5522 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5523 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5524 | DPLL_VCO_ENABLE; | |
5525 | if (pipe != PIPE_A) | |
5526 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5527 | ||
5528 | crtc->config.dpll_hw_state.dpll_md = | |
5529 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5530 | |
5531 | bestn = crtc->config.dpll.n; | |
5532 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5533 | bestm1 = crtc->config.dpll.m1; | |
5534 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5535 | bestp1 = crtc->config.dpll.p1; | |
5536 | bestp2 = crtc->config.dpll.p2; | |
5537 | ||
5538 | /* | |
5539 | * Enable Refclk and SSC | |
5540 | */ | |
a11b0703 VS |
5541 | I915_WRITE(dpll_reg, |
5542 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5543 | ||
5544 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5545 | |
9d556c99 CML |
5546 | /* p1 and p2 divider */ |
5547 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5548 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5549 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5550 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5551 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5552 | ||
5553 | /* Feedback post-divider - m2 */ | |
5554 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5555 | ||
5556 | /* Feedback refclk divider - n and m1 */ | |
5557 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5558 | DPIO_CHV_M1_DIV_BY_2 | | |
5559 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5560 | ||
5561 | /* M2 fraction division */ | |
5562 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5563 | ||
5564 | /* M2 fraction division enable */ | |
5565 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5566 | DPIO_CHV_FRAC_DIV_EN | | |
5567 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5568 | ||
5569 | /* Loop filter */ | |
5570 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5571 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5572 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5573 | if (refclk == 100000) | |
5574 | intcoeff = 11; | |
5575 | else if (refclk == 38400) | |
5576 | intcoeff = 10; | |
5577 | else | |
5578 | intcoeff = 9; | |
5579 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5580 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5581 | ||
5582 | /* AFC Recal */ | |
5583 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5584 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5585 | DPIO_AFC_RECAL); | |
5586 | ||
5587 | mutex_unlock(&dev_priv->dpio_lock); | |
5588 | } | |
5589 | ||
f47709a9 DV |
5590 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5591 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5592 | int num_connectors) |
5593 | { | |
f47709a9 | 5594 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5595 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5596 | u32 dpll; |
5597 | bool is_sdvo; | |
f47709a9 | 5598 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5599 | |
f47709a9 | 5600 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5601 | |
f47709a9 DV |
5602 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5603 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5604 | |
5605 | dpll = DPLL_VGA_MODE_DIS; | |
5606 | ||
f47709a9 | 5607 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5608 | dpll |= DPLLB_MODE_LVDS; |
5609 | else | |
5610 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5611 | |
ef1b460d | 5612 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5613 | dpll |= (crtc->config.pixel_multiplier - 1) |
5614 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5615 | } |
198a037f DV |
5616 | |
5617 | if (is_sdvo) | |
4a33e48d | 5618 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5619 | |
f47709a9 | 5620 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5621 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5622 | |
5623 | /* compute bitmask from p1 value */ | |
5624 | if (IS_PINEVIEW(dev)) | |
5625 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5626 | else { | |
5627 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5628 | if (IS_G4X(dev) && reduced_clock) | |
5629 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5630 | } | |
5631 | switch (clock->p2) { | |
5632 | case 5: | |
5633 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5634 | break; | |
5635 | case 7: | |
5636 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5637 | break; | |
5638 | case 10: | |
5639 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5640 | break; | |
5641 | case 14: | |
5642 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5643 | break; | |
5644 | } | |
5645 | if (INTEL_INFO(dev)->gen >= 4) | |
5646 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5647 | ||
09ede541 | 5648 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5649 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5650 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5651 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5652 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5653 | else | |
5654 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5655 | ||
5656 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5657 | crtc->config.dpll_hw_state.dpll = dpll; |
5658 | ||
eb1cbe48 | 5659 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5660 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5661 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5662 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5663 | } |
5664 | } | |
5665 | ||
f47709a9 | 5666 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5667 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5668 | int num_connectors) |
5669 | { | |
f47709a9 | 5670 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5671 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5672 | u32 dpll; |
f47709a9 | 5673 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5674 | |
f47709a9 | 5675 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5676 | |
eb1cbe48 DV |
5677 | dpll = DPLL_VGA_MODE_DIS; |
5678 | ||
f47709a9 | 5679 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5680 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5681 | } else { | |
5682 | if (clock->p1 == 2) | |
5683 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5684 | else | |
5685 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5686 | if (clock->p2 == 4) | |
5687 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5688 | } | |
5689 | ||
4a33e48d DV |
5690 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5691 | dpll |= DPLL_DVO_2X_MODE; | |
5692 | ||
f47709a9 | 5693 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5694 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5695 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5696 | else | |
5697 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5698 | ||
5699 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5700 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5701 | } |
5702 | ||
8a654f3b | 5703 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5704 | { |
5705 | struct drm_device *dev = intel_crtc->base.dev; | |
5706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5707 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5708 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5709 | struct drm_display_mode *adjusted_mode = |
5710 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5711 | uint32_t crtc_vtotal, crtc_vblank_end; |
5712 | int vsyncshift = 0; | |
4d8a62ea DV |
5713 | |
5714 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5715 | * the hw state checker will get angry at the mismatch. */ | |
5716 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5717 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5718 | |
609aeaca | 5719 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5720 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5721 | crtc_vtotal -= 1; |
5722 | crtc_vblank_end -= 1; | |
609aeaca VS |
5723 | |
5724 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5725 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5726 | else | |
5727 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5728 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5729 | if (vsyncshift < 0) |
5730 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5731 | } |
5732 | ||
5733 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5734 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5735 | |
fe2b8f9d | 5736 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5737 | (adjusted_mode->crtc_hdisplay - 1) | |
5738 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5739 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5740 | (adjusted_mode->crtc_hblank_start - 1) | |
5741 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5742 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5743 | (adjusted_mode->crtc_hsync_start - 1) | |
5744 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5745 | ||
fe2b8f9d | 5746 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5747 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5748 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5749 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5750 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5751 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5752 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5753 | (adjusted_mode->crtc_vsync_start - 1) | |
5754 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5755 | ||
b5e508d4 PZ |
5756 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5757 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5758 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5759 | * bits. */ | |
5760 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5761 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5762 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5763 | ||
b0e77b9c PZ |
5764 | /* pipesrc controls the size that is scaled from, which should |
5765 | * always be the user's requested size. | |
5766 | */ | |
5767 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5768 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5769 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5770 | } |
5771 | ||
1bd1bd80 DV |
5772 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5773 | struct intel_crtc_config *pipe_config) | |
5774 | { | |
5775 | struct drm_device *dev = crtc->base.dev; | |
5776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5777 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5778 | uint32_t tmp; | |
5779 | ||
5780 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5781 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5782 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5783 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5784 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5785 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5786 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5787 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5788 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5789 | ||
5790 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5791 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5792 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5793 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5794 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5795 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5796 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5797 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5798 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5799 | ||
5800 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5801 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5802 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5803 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5804 | } | |
5805 | ||
5806 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5807 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5808 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5809 | ||
5810 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5811 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5812 | } |
5813 | ||
f6a83288 DV |
5814 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5815 | struct intel_crtc_config *pipe_config) | |
babea61d | 5816 | { |
f6a83288 DV |
5817 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5818 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5819 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5820 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5821 | |
f6a83288 DV |
5822 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5823 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5824 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5825 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5826 | |
f6a83288 | 5827 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5828 | |
f6a83288 DV |
5829 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5830 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5831 | } |
5832 | ||
84b046f3 DV |
5833 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5834 | { | |
5835 | struct drm_device *dev = intel_crtc->base.dev; | |
5836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5837 | uint32_t pipeconf; | |
5838 | ||
9f11a9e4 | 5839 | pipeconf = 0; |
84b046f3 | 5840 | |
67c72a12 DV |
5841 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5842 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5843 | pipeconf |= PIPECONF_ENABLE; | |
5844 | ||
cf532bb2 VS |
5845 | if (intel_crtc->config.double_wide) |
5846 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5847 | |
ff9ce46e DV |
5848 | /* only g4x and later have fancy bpc/dither controls */ |
5849 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5850 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5851 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5852 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5853 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5854 | |
ff9ce46e DV |
5855 | switch (intel_crtc->config.pipe_bpp) { |
5856 | case 18: | |
5857 | pipeconf |= PIPECONF_6BPC; | |
5858 | break; | |
5859 | case 24: | |
5860 | pipeconf |= PIPECONF_8BPC; | |
5861 | break; | |
5862 | case 30: | |
5863 | pipeconf |= PIPECONF_10BPC; | |
5864 | break; | |
5865 | default: | |
5866 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5867 | BUG(); | |
84b046f3 DV |
5868 | } |
5869 | } | |
5870 | ||
5871 | if (HAS_PIPE_CXSR(dev)) { | |
5872 | if (intel_crtc->lowfreq_avail) { | |
5873 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5874 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5875 | } else { | |
5876 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5877 | } |
5878 | } | |
5879 | ||
efc2cfff VS |
5880 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
5881 | if (INTEL_INFO(dev)->gen < 4 || | |
5882 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5883 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5884 | else | |
5885 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
5886 | } else | |
84b046f3 DV |
5887 | pipeconf |= PIPECONF_PROGRESSIVE; |
5888 | ||
9f11a9e4 DV |
5889 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5890 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5891 | |
84b046f3 DV |
5892 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5893 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5894 | } | |
5895 | ||
f564048e | 5896 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5897 | int x, int y, |
94352cf9 | 5898 | struct drm_framebuffer *fb) |
79e53945 JB |
5899 | { |
5900 | struct drm_device *dev = crtc->dev; | |
5901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 5903 | int refclk, num_connectors = 0; |
652c393a | 5904 | intel_clock_t clock, reduced_clock; |
a16af721 | 5905 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5906 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5907 | struct intel_encoder *encoder; |
d4906093 | 5908 | const intel_limit_t *limit; |
79e53945 | 5909 | |
6c2b7c12 | 5910 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5911 | switch (encoder->type) { |
79e53945 JB |
5912 | case INTEL_OUTPUT_LVDS: |
5913 | is_lvds = true; | |
5914 | break; | |
e9fd1c02 JN |
5915 | case INTEL_OUTPUT_DSI: |
5916 | is_dsi = true; | |
5917 | break; | |
79e53945 | 5918 | } |
43565a06 | 5919 | |
c751ce4f | 5920 | num_connectors++; |
79e53945 JB |
5921 | } |
5922 | ||
f2335330 | 5923 | if (is_dsi) |
5b18e57c | 5924 | return 0; |
f2335330 JN |
5925 | |
5926 | if (!intel_crtc->config.clock_set) { | |
5927 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5928 | |
e9fd1c02 JN |
5929 | /* |
5930 | * Returns a set of divisors for the desired target clock with | |
5931 | * the given refclk, or FALSE. The returned values represent | |
5932 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5933 | * 2) / p1 / p2. | |
5934 | */ | |
5935 | limit = intel_limit(crtc, refclk); | |
5936 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5937 | intel_crtc->config.port_clock, | |
5938 | refclk, NULL, &clock); | |
f2335330 | 5939 | if (!ok) { |
e9fd1c02 JN |
5940 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5941 | return -EINVAL; | |
5942 | } | |
79e53945 | 5943 | |
f2335330 JN |
5944 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5945 | /* | |
5946 | * Ensure we match the reduced clock's P to the target | |
5947 | * clock. If the clocks don't match, we can't switch | |
5948 | * the display clock by using the FP0/FP1. In such case | |
5949 | * we will disable the LVDS downclock feature. | |
5950 | */ | |
5951 | has_reduced_clock = | |
5952 | dev_priv->display.find_dpll(limit, crtc, | |
5953 | dev_priv->lvds_downclock, | |
5954 | refclk, &clock, | |
5955 | &reduced_clock); | |
5956 | } | |
5957 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5958 | intel_crtc->config.dpll.n = clock.n; |
5959 | intel_crtc->config.dpll.m1 = clock.m1; | |
5960 | intel_crtc->config.dpll.m2 = clock.m2; | |
5961 | intel_crtc->config.dpll.p1 = clock.p1; | |
5962 | intel_crtc->config.dpll.p2 = clock.p2; | |
5963 | } | |
7026d4ac | 5964 | |
e9fd1c02 | 5965 | if (IS_GEN2(dev)) { |
8a654f3b | 5966 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5967 | has_reduced_clock ? &reduced_clock : NULL, |
5968 | num_connectors); | |
9d556c99 CML |
5969 | } else if (IS_CHERRYVIEW(dev)) { |
5970 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 5971 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5972 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5973 | } else { |
f47709a9 | 5974 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5975 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 5976 | num_connectors); |
e9fd1c02 | 5977 | } |
79e53945 | 5978 | |
c8f7a0db | 5979 | return 0; |
f564048e EA |
5980 | } |
5981 | ||
2fa2fe9a DV |
5982 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5983 | struct intel_crtc_config *pipe_config) | |
5984 | { | |
5985 | struct drm_device *dev = crtc->base.dev; | |
5986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5987 | uint32_t tmp; | |
5988 | ||
dc9e7dec VS |
5989 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5990 | return; | |
5991 | ||
2fa2fe9a | 5992 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5993 | if (!(tmp & PFIT_ENABLE)) |
5994 | return; | |
2fa2fe9a | 5995 | |
06922821 | 5996 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5997 | if (INTEL_INFO(dev)->gen < 4) { |
5998 | if (crtc->pipe != PIPE_B) | |
5999 | return; | |
2fa2fe9a DV |
6000 | } else { |
6001 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6002 | return; | |
6003 | } | |
6004 | ||
06922821 | 6005 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6006 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6007 | if (INTEL_INFO(dev)->gen < 5) | |
6008 | pipe_config->gmch_pfit.lvds_border_bits = | |
6009 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6010 | } | |
6011 | ||
acbec814 JB |
6012 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6013 | struct intel_crtc_config *pipe_config) | |
6014 | { | |
6015 | struct drm_device *dev = crtc->base.dev; | |
6016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6017 | int pipe = pipe_config->cpu_transcoder; | |
6018 | intel_clock_t clock; | |
6019 | u32 mdiv; | |
662c6ecb | 6020 | int refclk = 100000; |
acbec814 JB |
6021 | |
6022 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 6023 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6024 | mutex_unlock(&dev_priv->dpio_lock); |
6025 | ||
6026 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6027 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6028 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6029 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6030 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6031 | ||
f646628b | 6032 | vlv_clock(refclk, &clock); |
acbec814 | 6033 | |
f646628b VS |
6034 | /* clock.dot is the fast clock */ |
6035 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6036 | } |
6037 | ||
1ad292b5 JB |
6038 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6039 | struct intel_plane_config *plane_config) | |
6040 | { | |
6041 | struct drm_device *dev = crtc->base.dev; | |
6042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6043 | u32 val, base, offset; | |
6044 | int pipe = crtc->pipe, plane = crtc->plane; | |
6045 | int fourcc, pixel_format; | |
6046 | int aligned_height; | |
6047 | ||
66e514c1 DA |
6048 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6049 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6050 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6051 | return; | |
6052 | } | |
6053 | ||
6054 | val = I915_READ(DSPCNTR(plane)); | |
6055 | ||
6056 | if (INTEL_INFO(dev)->gen >= 4) | |
6057 | if (val & DISPPLANE_TILED) | |
6058 | plane_config->tiled = true; | |
6059 | ||
6060 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6061 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6062 | crtc->base.primary->fb->pixel_format = fourcc; |
6063 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6064 | drm_format_plane_cpp(fourcc, 0) * 8; |
6065 | ||
6066 | if (INTEL_INFO(dev)->gen >= 4) { | |
6067 | if (plane_config->tiled) | |
6068 | offset = I915_READ(DSPTILEOFF(plane)); | |
6069 | else | |
6070 | offset = I915_READ(DSPLINOFF(plane)); | |
6071 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6072 | } else { | |
6073 | base = I915_READ(DSPADDR(plane)); | |
6074 | } | |
6075 | plane_config->base = base; | |
6076 | ||
6077 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6078 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6079 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6080 | |
6081 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 6082 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 6083 | |
66e514c1 | 6084 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6085 | plane_config->tiled); |
6086 | ||
66e514c1 | 6087 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
1ad292b5 JB |
6088 | aligned_height, PAGE_SIZE); |
6089 | ||
6090 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6091 | pipe, plane, crtc->base.primary->fb->width, |
6092 | crtc->base.primary->fb->height, | |
6093 | crtc->base.primary->fb->bits_per_pixel, base, | |
6094 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6095 | plane_config->size); |
6096 | ||
6097 | } | |
6098 | ||
70b23a98 VS |
6099 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6100 | struct intel_crtc_config *pipe_config) | |
6101 | { | |
6102 | struct drm_device *dev = crtc->base.dev; | |
6103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6104 | int pipe = pipe_config->cpu_transcoder; | |
6105 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6106 | intel_clock_t clock; | |
6107 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6108 | int refclk = 100000; | |
6109 | ||
6110 | mutex_lock(&dev_priv->dpio_lock); | |
6111 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6112 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6113 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6114 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6115 | mutex_unlock(&dev_priv->dpio_lock); | |
6116 | ||
6117 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6118 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6119 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6120 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6121 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6122 | ||
6123 | chv_clock(refclk, &clock); | |
6124 | ||
6125 | /* clock.dot is the fast clock */ | |
6126 | pipe_config->port_clock = clock.dot / 5; | |
6127 | } | |
6128 | ||
0e8ffe1b DV |
6129 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6130 | struct intel_crtc_config *pipe_config) | |
6131 | { | |
6132 | struct drm_device *dev = crtc->base.dev; | |
6133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6134 | uint32_t tmp; | |
6135 | ||
b5482bd0 ID |
6136 | if (!intel_display_power_enabled(dev_priv, |
6137 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6138 | return false; | |
6139 | ||
e143a21c | 6140 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6141 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6142 | |
0e8ffe1b DV |
6143 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6144 | if (!(tmp & PIPECONF_ENABLE)) | |
6145 | return false; | |
6146 | ||
42571aef VS |
6147 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6148 | switch (tmp & PIPECONF_BPC_MASK) { | |
6149 | case PIPECONF_6BPC: | |
6150 | pipe_config->pipe_bpp = 18; | |
6151 | break; | |
6152 | case PIPECONF_8BPC: | |
6153 | pipe_config->pipe_bpp = 24; | |
6154 | break; | |
6155 | case PIPECONF_10BPC: | |
6156 | pipe_config->pipe_bpp = 30; | |
6157 | break; | |
6158 | default: | |
6159 | break; | |
6160 | } | |
6161 | } | |
6162 | ||
b5a9fa09 DV |
6163 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6164 | pipe_config->limited_color_range = true; | |
6165 | ||
282740f7 VS |
6166 | if (INTEL_INFO(dev)->gen < 4) |
6167 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6168 | ||
1bd1bd80 DV |
6169 | intel_get_pipe_timings(crtc, pipe_config); |
6170 | ||
2fa2fe9a DV |
6171 | i9xx_get_pfit_config(crtc, pipe_config); |
6172 | ||
6c49f241 DV |
6173 | if (INTEL_INFO(dev)->gen >= 4) { |
6174 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6175 | pipe_config->pixel_multiplier = | |
6176 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6177 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6178 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6179 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6180 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6181 | pipe_config->pixel_multiplier = | |
6182 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6183 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6184 | } else { | |
6185 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6186 | * port and will be fixed up in the encoder->get_config | |
6187 | * function. */ | |
6188 | pipe_config->pixel_multiplier = 1; | |
6189 | } | |
8bcc2795 DV |
6190 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6191 | if (!IS_VALLEYVIEW(dev)) { | |
6192 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6193 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6194 | } else { |
6195 | /* Mask out read-only status bits. */ | |
6196 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6197 | DPLL_PORTC_READY_MASK | | |
6198 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6199 | } |
6c49f241 | 6200 | |
70b23a98 VS |
6201 | if (IS_CHERRYVIEW(dev)) |
6202 | chv_crtc_clock_get(crtc, pipe_config); | |
6203 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6204 | vlv_crtc_clock_get(crtc, pipe_config); |
6205 | else | |
6206 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6207 | |
0e8ffe1b DV |
6208 | return true; |
6209 | } | |
6210 | ||
dde86e2d | 6211 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6212 | { |
6213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6214 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6215 | struct intel_encoder *encoder; |
74cfd7ac | 6216 | u32 val, final; |
13d83a67 | 6217 | bool has_lvds = false; |
199e5d79 | 6218 | bool has_cpu_edp = false; |
199e5d79 | 6219 | bool has_panel = false; |
99eb6a01 KP |
6220 | bool has_ck505 = false; |
6221 | bool can_ssc = false; | |
13d83a67 JB |
6222 | |
6223 | /* We need to take the global config into account */ | |
199e5d79 KP |
6224 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6225 | base.head) { | |
6226 | switch (encoder->type) { | |
6227 | case INTEL_OUTPUT_LVDS: | |
6228 | has_panel = true; | |
6229 | has_lvds = true; | |
6230 | break; | |
6231 | case INTEL_OUTPUT_EDP: | |
6232 | has_panel = true; | |
2de6905f | 6233 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6234 | has_cpu_edp = true; |
6235 | break; | |
13d83a67 JB |
6236 | } |
6237 | } | |
6238 | ||
99eb6a01 | 6239 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6240 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6241 | can_ssc = has_ck505; |
6242 | } else { | |
6243 | has_ck505 = false; | |
6244 | can_ssc = true; | |
6245 | } | |
6246 | ||
2de6905f ID |
6247 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6248 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6249 | |
6250 | /* Ironlake: try to setup display ref clock before DPLL | |
6251 | * enabling. This is only under driver's control after | |
6252 | * PCH B stepping, previous chipset stepping should be | |
6253 | * ignoring this setting. | |
6254 | */ | |
74cfd7ac CW |
6255 | val = I915_READ(PCH_DREF_CONTROL); |
6256 | ||
6257 | /* As we must carefully and slowly disable/enable each source in turn, | |
6258 | * compute the final state we want first and check if we need to | |
6259 | * make any changes at all. | |
6260 | */ | |
6261 | final = val; | |
6262 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6263 | if (has_ck505) | |
6264 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6265 | else | |
6266 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6267 | ||
6268 | final &= ~DREF_SSC_SOURCE_MASK; | |
6269 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6270 | final &= ~DREF_SSC1_ENABLE; | |
6271 | ||
6272 | if (has_panel) { | |
6273 | final |= DREF_SSC_SOURCE_ENABLE; | |
6274 | ||
6275 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6276 | final |= DREF_SSC1_ENABLE; | |
6277 | ||
6278 | if (has_cpu_edp) { | |
6279 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6280 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6281 | else | |
6282 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6283 | } else | |
6284 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6285 | } else { | |
6286 | final |= DREF_SSC_SOURCE_DISABLE; | |
6287 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6288 | } | |
6289 | ||
6290 | if (final == val) | |
6291 | return; | |
6292 | ||
13d83a67 | 6293 | /* Always enable nonspread source */ |
74cfd7ac | 6294 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6295 | |
99eb6a01 | 6296 | if (has_ck505) |
74cfd7ac | 6297 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6298 | else |
74cfd7ac | 6299 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6300 | |
199e5d79 | 6301 | if (has_panel) { |
74cfd7ac CW |
6302 | val &= ~DREF_SSC_SOURCE_MASK; |
6303 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6304 | |
199e5d79 | 6305 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6306 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6307 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6308 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6309 | } else |
74cfd7ac | 6310 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6311 | |
6312 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6313 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6314 | POSTING_READ(PCH_DREF_CONTROL); |
6315 | udelay(200); | |
6316 | ||
74cfd7ac | 6317 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6318 | |
6319 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6320 | if (has_cpu_edp) { |
99eb6a01 | 6321 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6322 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6323 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6324 | } else |
74cfd7ac | 6325 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6326 | } else |
74cfd7ac | 6327 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6328 | |
74cfd7ac | 6329 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6330 | POSTING_READ(PCH_DREF_CONTROL); |
6331 | udelay(200); | |
6332 | } else { | |
6333 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6334 | ||
74cfd7ac | 6335 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6336 | |
6337 | /* Turn off CPU output */ | |
74cfd7ac | 6338 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6339 | |
74cfd7ac | 6340 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6341 | POSTING_READ(PCH_DREF_CONTROL); |
6342 | udelay(200); | |
6343 | ||
6344 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6345 | val &= ~DREF_SSC_SOURCE_MASK; |
6346 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6347 | |
6348 | /* Turn off SSC1 */ | |
74cfd7ac | 6349 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6350 | |
74cfd7ac | 6351 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6352 | POSTING_READ(PCH_DREF_CONTROL); |
6353 | udelay(200); | |
6354 | } | |
74cfd7ac CW |
6355 | |
6356 | BUG_ON(val != final); | |
13d83a67 JB |
6357 | } |
6358 | ||
f31f2d55 | 6359 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6360 | { |
f31f2d55 | 6361 | uint32_t tmp; |
dde86e2d | 6362 | |
0ff066a9 PZ |
6363 | tmp = I915_READ(SOUTH_CHICKEN2); |
6364 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6365 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6366 | |
0ff066a9 PZ |
6367 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6368 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6369 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6370 | |
0ff066a9 PZ |
6371 | tmp = I915_READ(SOUTH_CHICKEN2); |
6372 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6373 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6374 | |
0ff066a9 PZ |
6375 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6376 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6377 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6378 | } |
6379 | ||
6380 | /* WaMPhyProgramming:hsw */ | |
6381 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6382 | { | |
6383 | uint32_t tmp; | |
dde86e2d PZ |
6384 | |
6385 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6386 | tmp &= ~(0xFF << 24); | |
6387 | tmp |= (0x12 << 24); | |
6388 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6389 | ||
dde86e2d PZ |
6390 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6391 | tmp |= (1 << 11); | |
6392 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6393 | ||
6394 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6395 | tmp |= (1 << 11); | |
6396 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6397 | ||
dde86e2d PZ |
6398 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6399 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6400 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6401 | ||
6402 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6403 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6404 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6405 | ||
0ff066a9 PZ |
6406 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6407 | tmp &= ~(7 << 13); | |
6408 | tmp |= (5 << 13); | |
6409 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6410 | |
0ff066a9 PZ |
6411 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6412 | tmp &= ~(7 << 13); | |
6413 | tmp |= (5 << 13); | |
6414 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6415 | |
6416 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6417 | tmp &= ~0xFF; | |
6418 | tmp |= 0x1C; | |
6419 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6420 | ||
6421 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6422 | tmp &= ~0xFF; | |
6423 | tmp |= 0x1C; | |
6424 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6425 | ||
6426 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6427 | tmp &= ~(0xFF << 16); | |
6428 | tmp |= (0x1C << 16); | |
6429 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6430 | ||
6431 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6432 | tmp &= ~(0xFF << 16); | |
6433 | tmp |= (0x1C << 16); | |
6434 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6435 | ||
0ff066a9 PZ |
6436 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6437 | tmp |= (1 << 27); | |
6438 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6439 | |
0ff066a9 PZ |
6440 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6441 | tmp |= (1 << 27); | |
6442 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6443 | |
0ff066a9 PZ |
6444 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6445 | tmp &= ~(0xF << 28); | |
6446 | tmp |= (4 << 28); | |
6447 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6448 | |
0ff066a9 PZ |
6449 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6450 | tmp &= ~(0xF << 28); | |
6451 | tmp |= (4 << 28); | |
6452 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6453 | } |
6454 | ||
2fa86a1f PZ |
6455 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6456 | * Programming" based on the parameters passed: | |
6457 | * - Sequence to enable CLKOUT_DP | |
6458 | * - Sequence to enable CLKOUT_DP without spread | |
6459 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6460 | */ | |
6461 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6462 | bool with_fdi) | |
f31f2d55 PZ |
6463 | { |
6464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6465 | uint32_t reg, tmp; |
6466 | ||
6467 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6468 | with_spread = true; | |
6469 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6470 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6471 | with_fdi = false; | |
f31f2d55 PZ |
6472 | |
6473 | mutex_lock(&dev_priv->dpio_lock); | |
6474 | ||
6475 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6476 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6477 | tmp |= SBI_SSCCTL_PATHALT; | |
6478 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6479 | ||
6480 | udelay(24); | |
6481 | ||
2fa86a1f PZ |
6482 | if (with_spread) { |
6483 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6484 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6485 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6486 | |
2fa86a1f PZ |
6487 | if (with_fdi) { |
6488 | lpt_reset_fdi_mphy(dev_priv); | |
6489 | lpt_program_fdi_mphy(dev_priv); | |
6490 | } | |
6491 | } | |
dde86e2d | 6492 | |
2fa86a1f PZ |
6493 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6494 | SBI_GEN0 : SBI_DBUFF0; | |
6495 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6496 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6497 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6498 | |
6499 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6500 | } |
6501 | ||
47701c3b PZ |
6502 | /* Sequence to disable CLKOUT_DP */ |
6503 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6504 | { | |
6505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6506 | uint32_t reg, tmp; | |
6507 | ||
6508 | mutex_lock(&dev_priv->dpio_lock); | |
6509 | ||
6510 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6511 | SBI_GEN0 : SBI_DBUFF0; | |
6512 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6513 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6514 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6515 | ||
6516 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6517 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6518 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6519 | tmp |= SBI_SSCCTL_PATHALT; | |
6520 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6521 | udelay(32); | |
6522 | } | |
6523 | tmp |= SBI_SSCCTL_DISABLE; | |
6524 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6525 | } | |
6526 | ||
6527 | mutex_unlock(&dev_priv->dpio_lock); | |
6528 | } | |
6529 | ||
bf8fa3d3 PZ |
6530 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6531 | { | |
6532 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6533 | struct intel_encoder *encoder; | |
6534 | bool has_vga = false; | |
6535 | ||
6536 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6537 | switch (encoder->type) { | |
6538 | case INTEL_OUTPUT_ANALOG: | |
6539 | has_vga = true; | |
6540 | break; | |
6541 | } | |
6542 | } | |
6543 | ||
47701c3b PZ |
6544 | if (has_vga) |
6545 | lpt_enable_clkout_dp(dev, true, true); | |
6546 | else | |
6547 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6548 | } |
6549 | ||
dde86e2d PZ |
6550 | /* |
6551 | * Initialize reference clocks when the driver loads | |
6552 | */ | |
6553 | void intel_init_pch_refclk(struct drm_device *dev) | |
6554 | { | |
6555 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6556 | ironlake_init_pch_refclk(dev); | |
6557 | else if (HAS_PCH_LPT(dev)) | |
6558 | lpt_init_pch_refclk(dev); | |
6559 | } | |
6560 | ||
d9d444cb JB |
6561 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6562 | { | |
6563 | struct drm_device *dev = crtc->dev; | |
6564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6565 | struct intel_encoder *encoder; | |
d9d444cb JB |
6566 | int num_connectors = 0; |
6567 | bool is_lvds = false; | |
6568 | ||
6c2b7c12 | 6569 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6570 | switch (encoder->type) { |
6571 | case INTEL_OUTPUT_LVDS: | |
6572 | is_lvds = true; | |
6573 | break; | |
d9d444cb JB |
6574 | } |
6575 | num_connectors++; | |
6576 | } | |
6577 | ||
6578 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6579 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6580 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6581 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6582 | } |
6583 | ||
6584 | return 120000; | |
6585 | } | |
6586 | ||
6ff93609 | 6587 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6588 | { |
c8203565 | 6589 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6590 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6592 | uint32_t val; |
6593 | ||
78114071 | 6594 | val = 0; |
c8203565 | 6595 | |
965e0c48 | 6596 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6597 | case 18: |
dfd07d72 | 6598 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6599 | break; |
6600 | case 24: | |
dfd07d72 | 6601 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6602 | break; |
6603 | case 30: | |
dfd07d72 | 6604 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6605 | break; |
6606 | case 36: | |
dfd07d72 | 6607 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6608 | break; |
6609 | default: | |
cc769b62 PZ |
6610 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6611 | BUG(); | |
c8203565 PZ |
6612 | } |
6613 | ||
d8b32247 | 6614 | if (intel_crtc->config.dither) |
c8203565 PZ |
6615 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6616 | ||
6ff93609 | 6617 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6618 | val |= PIPECONF_INTERLACED_ILK; |
6619 | else | |
6620 | val |= PIPECONF_PROGRESSIVE; | |
6621 | ||
50f3b016 | 6622 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6623 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6624 | |
c8203565 PZ |
6625 | I915_WRITE(PIPECONF(pipe), val); |
6626 | POSTING_READ(PIPECONF(pipe)); | |
6627 | } | |
6628 | ||
86d3efce VS |
6629 | /* |
6630 | * Set up the pipe CSC unit. | |
6631 | * | |
6632 | * Currently only full range RGB to limited range RGB conversion | |
6633 | * is supported, but eventually this should handle various | |
6634 | * RGB<->YCbCr scenarios as well. | |
6635 | */ | |
50f3b016 | 6636 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6637 | { |
6638 | struct drm_device *dev = crtc->dev; | |
6639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6641 | int pipe = intel_crtc->pipe; | |
6642 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6643 | ||
6644 | /* | |
6645 | * TODO: Check what kind of values actually come out of the pipe | |
6646 | * with these coeff/postoff values and adjust to get the best | |
6647 | * accuracy. Perhaps we even need to take the bpc value into | |
6648 | * consideration. | |
6649 | */ | |
6650 | ||
50f3b016 | 6651 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6652 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6653 | ||
6654 | /* | |
6655 | * GY/GU and RY/RU should be the other way around according | |
6656 | * to BSpec, but reality doesn't agree. Just set them up in | |
6657 | * a way that results in the correct picture. | |
6658 | */ | |
6659 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6660 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6661 | ||
6662 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6663 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6664 | ||
6665 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6666 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6667 | ||
6668 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6669 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6670 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6671 | ||
6672 | if (INTEL_INFO(dev)->gen > 6) { | |
6673 | uint16_t postoff = 0; | |
6674 | ||
50f3b016 | 6675 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6676 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6677 | |
6678 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6679 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6680 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6681 | ||
6682 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6683 | } else { | |
6684 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6685 | ||
50f3b016 | 6686 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6687 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6688 | ||
6689 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6690 | } | |
6691 | } | |
6692 | ||
6ff93609 | 6693 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6694 | { |
756f85cf PZ |
6695 | struct drm_device *dev = crtc->dev; |
6696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6698 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6699 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6700 | uint32_t val; |
6701 | ||
3eff4faa | 6702 | val = 0; |
ee2b0b38 | 6703 | |
756f85cf | 6704 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6705 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6706 | ||
6ff93609 | 6707 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6708 | val |= PIPECONF_INTERLACED_ILK; |
6709 | else | |
6710 | val |= PIPECONF_PROGRESSIVE; | |
6711 | ||
702e7a56 PZ |
6712 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6713 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6714 | |
6715 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6716 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6717 | |
6718 | if (IS_BROADWELL(dev)) { | |
6719 | val = 0; | |
6720 | ||
6721 | switch (intel_crtc->config.pipe_bpp) { | |
6722 | case 18: | |
6723 | val |= PIPEMISC_DITHER_6_BPC; | |
6724 | break; | |
6725 | case 24: | |
6726 | val |= PIPEMISC_DITHER_8_BPC; | |
6727 | break; | |
6728 | case 30: | |
6729 | val |= PIPEMISC_DITHER_10_BPC; | |
6730 | break; | |
6731 | case 36: | |
6732 | val |= PIPEMISC_DITHER_12_BPC; | |
6733 | break; | |
6734 | default: | |
6735 | /* Case prevented by pipe_config_set_bpp. */ | |
6736 | BUG(); | |
6737 | } | |
6738 | ||
6739 | if (intel_crtc->config.dither) | |
6740 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6741 | ||
6742 | I915_WRITE(PIPEMISC(pipe), val); | |
6743 | } | |
ee2b0b38 PZ |
6744 | } |
6745 | ||
6591c6e4 | 6746 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6747 | intel_clock_t *clock, |
6748 | bool *has_reduced_clock, | |
6749 | intel_clock_t *reduced_clock) | |
6750 | { | |
6751 | struct drm_device *dev = crtc->dev; | |
6752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6753 | struct intel_encoder *intel_encoder; | |
6754 | int refclk; | |
d4906093 | 6755 | const intel_limit_t *limit; |
a16af721 | 6756 | bool ret, is_lvds = false; |
79e53945 | 6757 | |
6591c6e4 PZ |
6758 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6759 | switch (intel_encoder->type) { | |
79e53945 JB |
6760 | case INTEL_OUTPUT_LVDS: |
6761 | is_lvds = true; | |
6762 | break; | |
79e53945 JB |
6763 | } |
6764 | } | |
6765 | ||
d9d444cb | 6766 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6767 | |
d4906093 ML |
6768 | /* |
6769 | * Returns a set of divisors for the desired target clock with the given | |
6770 | * refclk, or FALSE. The returned values represent the clock equation: | |
6771 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6772 | */ | |
1b894b59 | 6773 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6774 | ret = dev_priv->display.find_dpll(limit, crtc, |
6775 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6776 | refclk, NULL, clock); |
6591c6e4 PZ |
6777 | if (!ret) |
6778 | return false; | |
cda4b7d3 | 6779 | |
ddc9003c | 6780 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6781 | /* |
6782 | * Ensure we match the reduced clock's P to the target clock. | |
6783 | * If the clocks don't match, we can't switch the display clock | |
6784 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6785 | * downclock feature. | |
6786 | */ | |
ee9300bb DV |
6787 | *has_reduced_clock = |
6788 | dev_priv->display.find_dpll(limit, crtc, | |
6789 | dev_priv->lvds_downclock, | |
6790 | refclk, clock, | |
6791 | reduced_clock); | |
652c393a | 6792 | } |
61e9653f | 6793 | |
6591c6e4 PZ |
6794 | return true; |
6795 | } | |
6796 | ||
d4b1931c PZ |
6797 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6798 | { | |
6799 | /* | |
6800 | * Account for spread spectrum to avoid | |
6801 | * oversubscribing the link. Max center spread | |
6802 | * is 2.5%; use 5% for safety's sake. | |
6803 | */ | |
6804 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6805 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6806 | } |
6807 | ||
7429e9d4 | 6808 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6809 | { |
7429e9d4 | 6810 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6811 | } |
6812 | ||
de13a2e3 | 6813 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6814 | u32 *fp, |
9a7c7890 | 6815 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6816 | { |
de13a2e3 | 6817 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6818 | struct drm_device *dev = crtc->dev; |
6819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6820 | struct intel_encoder *intel_encoder; |
6821 | uint32_t dpll; | |
6cc5f341 | 6822 | int factor, num_connectors = 0; |
09ede541 | 6823 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6824 | |
de13a2e3 PZ |
6825 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6826 | switch (intel_encoder->type) { | |
79e53945 JB |
6827 | case INTEL_OUTPUT_LVDS: |
6828 | is_lvds = true; | |
6829 | break; | |
6830 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6831 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6832 | is_sdvo = true; |
79e53945 | 6833 | break; |
79e53945 | 6834 | } |
43565a06 | 6835 | |
c751ce4f | 6836 | num_connectors++; |
79e53945 | 6837 | } |
79e53945 | 6838 | |
c1858123 | 6839 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6840 | factor = 21; |
6841 | if (is_lvds) { | |
6842 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6843 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6844 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6845 | factor = 25; |
09ede541 | 6846 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6847 | factor = 20; |
c1858123 | 6848 | |
7429e9d4 | 6849 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6850 | *fp |= FP_CB_TUNE; |
2c07245f | 6851 | |
9a7c7890 DV |
6852 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6853 | *fp2 |= FP_CB_TUNE; | |
6854 | ||
5eddb70b | 6855 | dpll = 0; |
2c07245f | 6856 | |
a07d6787 EA |
6857 | if (is_lvds) |
6858 | dpll |= DPLLB_MODE_LVDS; | |
6859 | else | |
6860 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6861 | |
ef1b460d DV |
6862 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6863 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6864 | |
6865 | if (is_sdvo) | |
4a33e48d | 6866 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6867 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6868 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6869 | |
a07d6787 | 6870 | /* compute bitmask from p1 value */ |
7429e9d4 | 6871 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6872 | /* also FPA1 */ |
7429e9d4 | 6873 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6874 | |
7429e9d4 | 6875 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6876 | case 5: |
6877 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6878 | break; | |
6879 | case 7: | |
6880 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6881 | break; | |
6882 | case 10: | |
6883 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6884 | break; | |
6885 | case 14: | |
6886 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6887 | break; | |
79e53945 JB |
6888 | } |
6889 | ||
b4c09f3b | 6890 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6891 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6892 | else |
6893 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6894 | ||
959e16d6 | 6895 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6896 | } |
6897 | ||
6898 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6899 | int x, int y, |
6900 | struct drm_framebuffer *fb) | |
6901 | { | |
6902 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 6903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
6904 | int num_connectors = 0; |
6905 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6906 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6907 | bool ok, has_reduced_clock = false; |
8b47047b | 6908 | bool is_lvds = false; |
de13a2e3 | 6909 | struct intel_encoder *encoder; |
e2b78267 | 6910 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
6911 | |
6912 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6913 | switch (encoder->type) { | |
6914 | case INTEL_OUTPUT_LVDS: | |
6915 | is_lvds = true; | |
6916 | break; | |
de13a2e3 PZ |
6917 | } |
6918 | ||
6919 | num_connectors++; | |
a07d6787 | 6920 | } |
79e53945 | 6921 | |
5dc5298b PZ |
6922 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6923 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6924 | |
ff9a6750 | 6925 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6926 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6927 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6928 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6929 | return -EINVAL; | |
79e53945 | 6930 | } |
f47709a9 DV |
6931 | /* Compat-code for transition, will disappear. */ |
6932 | if (!intel_crtc->config.clock_set) { | |
6933 | intel_crtc->config.dpll.n = clock.n; | |
6934 | intel_crtc->config.dpll.m1 = clock.m1; | |
6935 | intel_crtc->config.dpll.m2 = clock.m2; | |
6936 | intel_crtc->config.dpll.p1 = clock.p1; | |
6937 | intel_crtc->config.dpll.p2 = clock.p2; | |
6938 | } | |
79e53945 | 6939 | |
5dc5298b | 6940 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6941 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6942 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6943 | if (has_reduced_clock) |
7429e9d4 | 6944 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6945 | |
7429e9d4 | 6946 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6947 | &fp, &reduced_clock, |
6948 | has_reduced_clock ? &fp2 : NULL); | |
6949 | ||
959e16d6 | 6950 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6951 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6952 | if (has_reduced_clock) | |
6953 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6954 | else | |
6955 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6956 | ||
b89a1d39 | 6957 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6958 | if (pll == NULL) { |
84f44ce7 | 6959 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 6960 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
6961 | return -EINVAL; |
6962 | } | |
ee7b9f93 | 6963 | } else |
e72f9fbf | 6964 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6965 | |
d330a953 | 6966 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6967 | intel_crtc->lowfreq_avail = true; |
6968 | else | |
6969 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6970 | |
c8f7a0db | 6971 | return 0; |
79e53945 JB |
6972 | } |
6973 | ||
eb14cb74 VS |
6974 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6975 | struct intel_link_m_n *m_n) | |
6976 | { | |
6977 | struct drm_device *dev = crtc->base.dev; | |
6978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6979 | enum pipe pipe = crtc->pipe; | |
6980 | ||
6981 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6982 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6983 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6984 | & ~TU_SIZE_MASK; | |
6985 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6986 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6987 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6988 | } | |
6989 | ||
6990 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6991 | enum transcoder transcoder, | |
6992 | struct intel_link_m_n *m_n) | |
72419203 DV |
6993 | { |
6994 | struct drm_device *dev = crtc->base.dev; | |
6995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6996 | enum pipe pipe = crtc->pipe; |
72419203 | 6997 | |
eb14cb74 VS |
6998 | if (INTEL_INFO(dev)->gen >= 5) { |
6999 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7000 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7001 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7002 | & ~TU_SIZE_MASK; | |
7003 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7004 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7005 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7006 | } else { | |
7007 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7008 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7009 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7010 | & ~TU_SIZE_MASK; | |
7011 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7012 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7013 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7014 | } | |
7015 | } | |
7016 | ||
7017 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7018 | struct intel_crtc_config *pipe_config) | |
7019 | { | |
7020 | if (crtc->config.has_pch_encoder) | |
7021 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7022 | else | |
7023 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7024 | &pipe_config->dp_m_n); | |
7025 | } | |
72419203 | 7026 | |
eb14cb74 VS |
7027 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7028 | struct intel_crtc_config *pipe_config) | |
7029 | { | |
7030 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7031 | &pipe_config->fdi_m_n); | |
72419203 DV |
7032 | } |
7033 | ||
2fa2fe9a DV |
7034 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7035 | struct intel_crtc_config *pipe_config) | |
7036 | { | |
7037 | struct drm_device *dev = crtc->base.dev; | |
7038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7039 | uint32_t tmp; | |
7040 | ||
7041 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7042 | ||
7043 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7044 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7045 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7046 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7047 | |
7048 | /* We currently do not free assignements of panel fitters on | |
7049 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7050 | * differentiates them) so just WARN about this case for now. */ | |
7051 | if (IS_GEN7(dev)) { | |
7052 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7053 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7054 | } | |
2fa2fe9a | 7055 | } |
79e53945 JB |
7056 | } |
7057 | ||
4c6baa59 JB |
7058 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7059 | struct intel_plane_config *plane_config) | |
7060 | { | |
7061 | struct drm_device *dev = crtc->base.dev; | |
7062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7063 | u32 val, base, offset; | |
7064 | int pipe = crtc->pipe, plane = crtc->plane; | |
7065 | int fourcc, pixel_format; | |
7066 | int aligned_height; | |
7067 | ||
66e514c1 DA |
7068 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7069 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7070 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7071 | return; | |
7072 | } | |
7073 | ||
7074 | val = I915_READ(DSPCNTR(plane)); | |
7075 | ||
7076 | if (INTEL_INFO(dev)->gen >= 4) | |
7077 | if (val & DISPPLANE_TILED) | |
7078 | plane_config->tiled = true; | |
7079 | ||
7080 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7081 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7082 | crtc->base.primary->fb->pixel_format = fourcc; |
7083 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7084 | drm_format_plane_cpp(fourcc, 0) * 8; |
7085 | ||
7086 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7087 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7088 | offset = I915_READ(DSPOFFSET(plane)); | |
7089 | } else { | |
7090 | if (plane_config->tiled) | |
7091 | offset = I915_READ(DSPTILEOFF(plane)); | |
7092 | else | |
7093 | offset = I915_READ(DSPLINOFF(plane)); | |
7094 | } | |
7095 | plane_config->base = base; | |
7096 | ||
7097 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7098 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7099 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7100 | |
7101 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7102 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7103 | |
66e514c1 | 7104 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7105 | plane_config->tiled); |
7106 | ||
66e514c1 | 7107 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
4c6baa59 JB |
7108 | aligned_height, PAGE_SIZE); |
7109 | ||
7110 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7111 | pipe, plane, crtc->base.primary->fb->width, |
7112 | crtc->base.primary->fb->height, | |
7113 | crtc->base.primary->fb->bits_per_pixel, base, | |
7114 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7115 | plane_config->size); |
7116 | } | |
7117 | ||
0e8ffe1b DV |
7118 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7119 | struct intel_crtc_config *pipe_config) | |
7120 | { | |
7121 | struct drm_device *dev = crtc->base.dev; | |
7122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7123 | uint32_t tmp; | |
7124 | ||
e143a21c | 7125 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7126 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7127 | |
0e8ffe1b DV |
7128 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7129 | if (!(tmp & PIPECONF_ENABLE)) | |
7130 | return false; | |
7131 | ||
42571aef VS |
7132 | switch (tmp & PIPECONF_BPC_MASK) { |
7133 | case PIPECONF_6BPC: | |
7134 | pipe_config->pipe_bpp = 18; | |
7135 | break; | |
7136 | case PIPECONF_8BPC: | |
7137 | pipe_config->pipe_bpp = 24; | |
7138 | break; | |
7139 | case PIPECONF_10BPC: | |
7140 | pipe_config->pipe_bpp = 30; | |
7141 | break; | |
7142 | case PIPECONF_12BPC: | |
7143 | pipe_config->pipe_bpp = 36; | |
7144 | break; | |
7145 | default: | |
7146 | break; | |
7147 | } | |
7148 | ||
b5a9fa09 DV |
7149 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7150 | pipe_config->limited_color_range = true; | |
7151 | ||
ab9412ba | 7152 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7153 | struct intel_shared_dpll *pll; |
7154 | ||
88adfff1 DV |
7155 | pipe_config->has_pch_encoder = true; |
7156 | ||
627eb5a3 DV |
7157 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7158 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7159 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7160 | |
7161 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7162 | |
c0d43d62 | 7163 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7164 | pipe_config->shared_dpll = |
7165 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7166 | } else { |
7167 | tmp = I915_READ(PCH_DPLL_SEL); | |
7168 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7169 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7170 | else | |
7171 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7172 | } | |
66e985c0 DV |
7173 | |
7174 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7175 | ||
7176 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7177 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7178 | |
7179 | tmp = pipe_config->dpll_hw_state.dpll; | |
7180 | pipe_config->pixel_multiplier = | |
7181 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7182 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7183 | |
7184 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7185 | } else { |
7186 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7187 | } |
7188 | ||
1bd1bd80 DV |
7189 | intel_get_pipe_timings(crtc, pipe_config); |
7190 | ||
2fa2fe9a DV |
7191 | ironlake_get_pfit_config(crtc, pipe_config); |
7192 | ||
0e8ffe1b DV |
7193 | return true; |
7194 | } | |
7195 | ||
be256dc7 PZ |
7196 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7197 | { | |
7198 | struct drm_device *dev = dev_priv->dev; | |
7199 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7200 | struct intel_crtc *crtc; | |
be256dc7 | 7201 | |
d3fcc808 | 7202 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7203 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7204 | pipe_name(crtc->pipe)); |
7205 | ||
7206 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7207 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7208 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7209 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7210 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7211 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7212 | "CPU PWM1 enabled\n"); | |
7213 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7214 | "CPU PWM2 enabled\n"); | |
7215 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7216 | "PCH PWM1 enabled\n"); | |
7217 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7218 | "Utility pin enabled\n"); | |
7219 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7220 | ||
9926ada1 PZ |
7221 | /* |
7222 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7223 | * interrupts remain enabled. We used to check for that, but since it's | |
7224 | * gen-specific and since we only disable LCPLL after we fully disable | |
7225 | * the interrupts, the check below should be enough. | |
7226 | */ | |
7227 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7228 | } |
7229 | ||
3c4c9b81 PZ |
7230 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7231 | { | |
7232 | struct drm_device *dev = dev_priv->dev; | |
7233 | ||
7234 | if (IS_HASWELL(dev)) { | |
7235 | mutex_lock(&dev_priv->rps.hw_lock); | |
7236 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7237 | val)) | |
7238 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7239 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7240 | } else { | |
7241 | I915_WRITE(D_COMP, val); | |
7242 | } | |
7243 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7244 | } |
7245 | ||
7246 | /* | |
7247 | * This function implements pieces of two sequences from BSpec: | |
7248 | * - Sequence for display software to disable LCPLL | |
7249 | * - Sequence for display software to allow package C8+ | |
7250 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7251 | * register. Callers should take care of disabling all the display engine | |
7252 | * functions, doing the mode unset, fixing interrupts, etc. | |
7253 | */ | |
6ff58d53 PZ |
7254 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7255 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7256 | { |
7257 | uint32_t val; | |
7258 | ||
7259 | assert_can_disable_lcpll(dev_priv); | |
7260 | ||
7261 | val = I915_READ(LCPLL_CTL); | |
7262 | ||
7263 | if (switch_to_fclk) { | |
7264 | val |= LCPLL_CD_SOURCE_FCLK; | |
7265 | I915_WRITE(LCPLL_CTL, val); | |
7266 | ||
7267 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7268 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7269 | DRM_ERROR("Switching to FCLK failed\n"); | |
7270 | ||
7271 | val = I915_READ(LCPLL_CTL); | |
7272 | } | |
7273 | ||
7274 | val |= LCPLL_PLL_DISABLE; | |
7275 | I915_WRITE(LCPLL_CTL, val); | |
7276 | POSTING_READ(LCPLL_CTL); | |
7277 | ||
7278 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7279 | DRM_ERROR("LCPLL still locked\n"); | |
7280 | ||
7281 | val = I915_READ(D_COMP); | |
7282 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7283 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7284 | ndelay(100); |
7285 | ||
7286 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7287 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7288 | ||
7289 | if (allow_power_down) { | |
7290 | val = I915_READ(LCPLL_CTL); | |
7291 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7292 | I915_WRITE(LCPLL_CTL, val); | |
7293 | POSTING_READ(LCPLL_CTL); | |
7294 | } | |
7295 | } | |
7296 | ||
7297 | /* | |
7298 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7299 | * source. | |
7300 | */ | |
6ff58d53 | 7301 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7302 | { |
7303 | uint32_t val; | |
a8a8bd54 | 7304 | unsigned long irqflags; |
be256dc7 PZ |
7305 | |
7306 | val = I915_READ(LCPLL_CTL); | |
7307 | ||
7308 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7309 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7310 | return; | |
7311 | ||
a8a8bd54 PZ |
7312 | /* |
7313 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7314 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7315 | * | |
7316 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7317 | * the runtime PM resume sequence, so we can't just call | |
7318 | * gen6_gt_force_wake_get() because that function calls | |
7319 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7320 | * while we are on the resume sequence. So to solve this problem we have | |
7321 | * to call special forcewake code that doesn't touch runtime PM and | |
7322 | * doesn't enable the forcewake delayed work. | |
7323 | */ | |
7324 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7325 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7326 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7327 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7328 | |
be256dc7 PZ |
7329 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7330 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7331 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7332 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7333 | } |
7334 | ||
7335 | val = I915_READ(D_COMP); | |
7336 | val |= D_COMP_COMP_FORCE; | |
7337 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7338 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7339 | |
7340 | val = I915_READ(LCPLL_CTL); | |
7341 | val &= ~LCPLL_PLL_DISABLE; | |
7342 | I915_WRITE(LCPLL_CTL, val); | |
7343 | ||
7344 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7345 | DRM_ERROR("LCPLL not locked yet\n"); | |
7346 | ||
7347 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7348 | val = I915_READ(LCPLL_CTL); | |
7349 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7350 | I915_WRITE(LCPLL_CTL, val); | |
7351 | ||
7352 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7353 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7354 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7355 | } | |
215733fa | 7356 | |
a8a8bd54 PZ |
7357 | /* See the big comment above. */ |
7358 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7359 | if (--dev_priv->uncore.forcewake_count == 0) | |
7360 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7361 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7362 | } |
7363 | ||
765dab67 PZ |
7364 | /* |
7365 | * Package states C8 and deeper are really deep PC states that can only be | |
7366 | * reached when all the devices on the system allow it, so even if the graphics | |
7367 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7368 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7369 | * | |
7370 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7371 | * well is disabled and most interrupts are disabled, and these are also | |
7372 | * requirements for runtime PM. When these conditions are met, we manually do | |
7373 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7374 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7375 | * hang the machine. | |
7376 | * | |
7377 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7378 | * the state of some registers, so when we come back from PC8+ we need to | |
7379 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7380 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7381 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7382 | * because of the runtime PM support). | |
7383 | * | |
7384 | * For more, read "Display Sequences for Package C8" on the hardware | |
7385 | * documentation. | |
7386 | */ | |
a14cb6fc | 7387 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7388 | { |
c67a470b PZ |
7389 | struct drm_device *dev = dev_priv->dev; |
7390 | uint32_t val; | |
7391 | ||
c67a470b PZ |
7392 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7393 | ||
c67a470b PZ |
7394 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7395 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7396 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7397 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7398 | } | |
7399 | ||
7400 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7401 | hsw_disable_lcpll(dev_priv, true, true); |
7402 | } | |
7403 | ||
a14cb6fc | 7404 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7405 | { |
7406 | struct drm_device *dev = dev_priv->dev; | |
7407 | uint32_t val; | |
7408 | ||
c67a470b PZ |
7409 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7410 | ||
7411 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7412 | lpt_init_pch_refclk(dev); |
7413 | ||
7414 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7415 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7416 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7417 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7418 | } | |
7419 | ||
7420 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7421 | } |
7422 | ||
9a952a0d PZ |
7423 | static void snb_modeset_global_resources(struct drm_device *dev) |
7424 | { | |
7425 | modeset_update_crtc_power_domains(dev); | |
7426 | } | |
7427 | ||
4f074129 ID |
7428 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7429 | { | |
da723569 | 7430 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7431 | } |
7432 | ||
09b4ddf9 | 7433 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7434 | int x, int y, |
7435 | struct drm_framebuffer *fb) | |
7436 | { | |
09b4ddf9 | 7437 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7438 | |
566b734a | 7439 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7440 | return -EINVAL; |
566b734a | 7441 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7442 | |
644cef34 DV |
7443 | intel_crtc->lowfreq_avail = false; |
7444 | ||
c8f7a0db | 7445 | return 0; |
79e53945 JB |
7446 | } |
7447 | ||
0e8ffe1b DV |
7448 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7449 | struct intel_crtc_config *pipe_config) | |
7450 | { | |
7451 | struct drm_device *dev = crtc->base.dev; | |
7452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7453 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7454 | uint32_t tmp; |
7455 | ||
b5482bd0 ID |
7456 | if (!intel_display_power_enabled(dev_priv, |
7457 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7458 | return false; | |
7459 | ||
e143a21c | 7460 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7461 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7462 | ||
eccb140b DV |
7463 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7464 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7465 | enum pipe trans_edp_pipe; | |
7466 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7467 | default: | |
7468 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7469 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7470 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7471 | trans_edp_pipe = PIPE_A; | |
7472 | break; | |
7473 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7474 | trans_edp_pipe = PIPE_B; | |
7475 | break; | |
7476 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7477 | trans_edp_pipe = PIPE_C; | |
7478 | break; | |
7479 | } | |
7480 | ||
7481 | if (trans_edp_pipe == crtc->pipe) | |
7482 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7483 | } | |
7484 | ||
da7e29bd | 7485 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7486 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7487 | return false; |
7488 | ||
eccb140b | 7489 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7490 | if (!(tmp & PIPECONF_ENABLE)) |
7491 | return false; | |
7492 | ||
88adfff1 | 7493 | /* |
f196e6be | 7494 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7495 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7496 | * the PCH transcoder is on. | |
7497 | */ | |
eccb140b | 7498 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7499 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7500 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7501 | pipe_config->has_pch_encoder = true; |
7502 | ||
627eb5a3 DV |
7503 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7504 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7505 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7506 | |
7507 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7508 | } |
7509 | ||
1bd1bd80 DV |
7510 | intel_get_pipe_timings(crtc, pipe_config); |
7511 | ||
2fa2fe9a | 7512 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7513 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7514 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7515 | |
e59150dc JB |
7516 | if (IS_HASWELL(dev)) |
7517 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7518 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7519 | |
6c49f241 DV |
7520 | pipe_config->pixel_multiplier = 1; |
7521 | ||
0e8ffe1b DV |
7522 | return true; |
7523 | } | |
7524 | ||
1a91510d JN |
7525 | static struct { |
7526 | int clock; | |
7527 | u32 config; | |
7528 | } hdmi_audio_clock[] = { | |
7529 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7530 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7531 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7532 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7533 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7534 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7535 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7536 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7537 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7538 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7539 | }; | |
7540 | ||
7541 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7542 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7543 | { | |
7544 | int i; | |
7545 | ||
7546 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7547 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7548 | break; | |
7549 | } | |
7550 | ||
7551 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7552 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7553 | i = 1; | |
7554 | } | |
7555 | ||
7556 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7557 | hdmi_audio_clock[i].clock, | |
7558 | hdmi_audio_clock[i].config); | |
7559 | ||
7560 | return hdmi_audio_clock[i].config; | |
7561 | } | |
7562 | ||
3a9627f4 WF |
7563 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7564 | int reg_eldv, uint32_t bits_eldv, | |
7565 | int reg_elda, uint32_t bits_elda, | |
7566 | int reg_edid) | |
7567 | { | |
7568 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7569 | uint8_t *eld = connector->eld; | |
7570 | uint32_t i; | |
7571 | ||
7572 | i = I915_READ(reg_eldv); | |
7573 | i &= bits_eldv; | |
7574 | ||
7575 | if (!eld[0]) | |
7576 | return !i; | |
7577 | ||
7578 | if (!i) | |
7579 | return false; | |
7580 | ||
7581 | i = I915_READ(reg_elda); | |
7582 | i &= ~bits_elda; | |
7583 | I915_WRITE(reg_elda, i); | |
7584 | ||
7585 | for (i = 0; i < eld[2]; i++) | |
7586 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7587 | return false; | |
7588 | ||
7589 | return true; | |
7590 | } | |
7591 | ||
e0dac65e | 7592 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7593 | struct drm_crtc *crtc, |
7594 | struct drm_display_mode *mode) | |
e0dac65e WF |
7595 | { |
7596 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7597 | uint8_t *eld = connector->eld; | |
7598 | uint32_t eldv; | |
7599 | uint32_t len; | |
7600 | uint32_t i; | |
7601 | ||
7602 | i = I915_READ(G4X_AUD_VID_DID); | |
7603 | ||
7604 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7605 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7606 | else | |
7607 | eldv = G4X_ELDV_DEVCTG; | |
7608 | ||
3a9627f4 WF |
7609 | if (intel_eld_uptodate(connector, |
7610 | G4X_AUD_CNTL_ST, eldv, | |
7611 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7612 | G4X_HDMIW_HDMIEDID)) | |
7613 | return; | |
7614 | ||
e0dac65e WF |
7615 | i = I915_READ(G4X_AUD_CNTL_ST); |
7616 | i &= ~(eldv | G4X_ELD_ADDR); | |
7617 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7618 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7619 | ||
7620 | if (!eld[0]) | |
7621 | return; | |
7622 | ||
7623 | len = min_t(uint8_t, eld[2], len); | |
7624 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7625 | for (i = 0; i < len; i++) | |
7626 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7627 | ||
7628 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7629 | i |= eldv; | |
7630 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7631 | } | |
7632 | ||
83358c85 | 7633 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7634 | struct drm_crtc *crtc, |
7635 | struct drm_display_mode *mode) | |
83358c85 WX |
7636 | { |
7637 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7638 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7639 | uint32_t eldv; |
7640 | uint32_t i; | |
7641 | int len; | |
7642 | int pipe = to_intel_crtc(crtc)->pipe; | |
7643 | int tmp; | |
7644 | ||
7645 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7646 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7647 | int aud_config = HSW_AUD_CFG(pipe); | |
7648 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7649 | ||
83358c85 WX |
7650 | /* Audio output enable */ |
7651 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7652 | tmp = I915_READ(aud_cntrl_st2); | |
7653 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7654 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7655 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7656 | |
c7905792 | 7657 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7658 | |
7659 | /* Set ELD valid state */ | |
7660 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7661 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7662 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7663 | I915_WRITE(aud_cntrl_st2, tmp); | |
7664 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7665 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7666 | |
7667 | /* Enable HDMI mode */ | |
7668 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7669 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7670 | /* clear N_programing_enable and N_value_index */ |
7671 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7672 | I915_WRITE(aud_config, tmp); | |
7673 | ||
7674 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7675 | ||
7676 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7677 | ||
7678 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7679 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7680 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7681 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7682 | } else { |
7683 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7684 | } | |
83358c85 WX |
7685 | |
7686 | if (intel_eld_uptodate(connector, | |
7687 | aud_cntrl_st2, eldv, | |
7688 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7689 | hdmiw_hdmiedid)) | |
7690 | return; | |
7691 | ||
7692 | i = I915_READ(aud_cntrl_st2); | |
7693 | i &= ~eldv; | |
7694 | I915_WRITE(aud_cntrl_st2, i); | |
7695 | ||
7696 | if (!eld[0]) | |
7697 | return; | |
7698 | ||
7699 | i = I915_READ(aud_cntl_st); | |
7700 | i &= ~IBX_ELD_ADDRESS; | |
7701 | I915_WRITE(aud_cntl_st, i); | |
7702 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7703 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7704 | ||
7705 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7706 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7707 | for (i = 0; i < len; i++) | |
7708 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7709 | ||
7710 | i = I915_READ(aud_cntrl_st2); | |
7711 | i |= eldv; | |
7712 | I915_WRITE(aud_cntrl_st2, i); | |
7713 | ||
7714 | } | |
7715 | ||
e0dac65e | 7716 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7717 | struct drm_crtc *crtc, |
7718 | struct drm_display_mode *mode) | |
e0dac65e WF |
7719 | { |
7720 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7721 | uint8_t *eld = connector->eld; | |
7722 | uint32_t eldv; | |
7723 | uint32_t i; | |
7724 | int len; | |
7725 | int hdmiw_hdmiedid; | |
b6daa025 | 7726 | int aud_config; |
e0dac65e WF |
7727 | int aud_cntl_st; |
7728 | int aud_cntrl_st2; | |
9b138a83 | 7729 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7730 | |
b3f33cbf | 7731 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7732 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7733 | aud_config = IBX_AUD_CFG(pipe); | |
7734 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7735 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7736 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7737 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7738 | aud_config = VLV_AUD_CFG(pipe); | |
7739 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7740 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7741 | } else { |
9b138a83 WX |
7742 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7743 | aud_config = CPT_AUD_CFG(pipe); | |
7744 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7745 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7746 | } |
7747 | ||
9b138a83 | 7748 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7749 | |
9ca2fe73 ML |
7750 | if (IS_VALLEYVIEW(connector->dev)) { |
7751 | struct intel_encoder *intel_encoder; | |
7752 | struct intel_digital_port *intel_dig_port; | |
7753 | ||
7754 | intel_encoder = intel_attached_encoder(connector); | |
7755 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7756 | i = intel_dig_port->port; | |
7757 | } else { | |
7758 | i = I915_READ(aud_cntl_st); | |
7759 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7760 | /* DIP_Port_Select, 0x1 = PortB */ | |
7761 | } | |
7762 | ||
e0dac65e WF |
7763 | if (!i) { |
7764 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7765 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7766 | eldv = IBX_ELD_VALIDB; |
7767 | eldv |= IBX_ELD_VALIDB << 4; | |
7768 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7769 | } else { |
2582a850 | 7770 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7771 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7772 | } |
7773 | ||
3a9627f4 WF |
7774 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7775 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7776 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7777 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7778 | } else { |
7779 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7780 | } | |
e0dac65e | 7781 | |
3a9627f4 WF |
7782 | if (intel_eld_uptodate(connector, |
7783 | aud_cntrl_st2, eldv, | |
7784 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7785 | hdmiw_hdmiedid)) | |
7786 | return; | |
7787 | ||
e0dac65e WF |
7788 | i = I915_READ(aud_cntrl_st2); |
7789 | i &= ~eldv; | |
7790 | I915_WRITE(aud_cntrl_st2, i); | |
7791 | ||
7792 | if (!eld[0]) | |
7793 | return; | |
7794 | ||
e0dac65e | 7795 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7796 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7797 | I915_WRITE(aud_cntl_st, i); |
7798 | ||
7799 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7800 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7801 | for (i = 0; i < len; i++) | |
7802 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7803 | ||
7804 | i = I915_READ(aud_cntrl_st2); | |
7805 | i |= eldv; | |
7806 | I915_WRITE(aud_cntrl_st2, i); | |
7807 | } | |
7808 | ||
7809 | void intel_write_eld(struct drm_encoder *encoder, | |
7810 | struct drm_display_mode *mode) | |
7811 | { | |
7812 | struct drm_crtc *crtc = encoder->crtc; | |
7813 | struct drm_connector *connector; | |
7814 | struct drm_device *dev = encoder->dev; | |
7815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7816 | ||
7817 | connector = drm_select_eld(encoder, mode); | |
7818 | if (!connector) | |
7819 | return; | |
7820 | ||
7821 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7822 | connector->base.id, | |
7823 | drm_get_connector_name(connector), | |
7824 | connector->encoder->base.id, | |
7825 | drm_get_encoder_name(connector->encoder)); | |
7826 | ||
7827 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7828 | ||
7829 | if (dev_priv->display.write_eld) | |
34427052 | 7830 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7831 | } |
7832 | ||
560b85bb CW |
7833 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7834 | { | |
7835 | struct drm_device *dev = crtc->dev; | |
7836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7838 | bool visible = base != 0; | |
7839 | u32 cntl; | |
7840 | ||
7841 | if (intel_crtc->cursor_visible == visible) | |
7842 | return; | |
7843 | ||
9db4a9c7 | 7844 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7845 | if (visible) { |
7846 | /* On these chipsets we can only modify the base whilst | |
7847 | * the cursor is disabled. | |
7848 | */ | |
9db4a9c7 | 7849 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7850 | |
7851 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7852 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7853 | cntl |= CURSOR_ENABLE | | |
7854 | CURSOR_GAMMA_ENABLE | | |
7855 | CURSOR_FORMAT_ARGB; | |
7856 | } else | |
7857 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7858 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7859 | |
7860 | intel_crtc->cursor_visible = visible; | |
7861 | } | |
7862 | ||
7863 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7864 | { | |
7865 | struct drm_device *dev = crtc->dev; | |
7866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7867 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7868 | int pipe = intel_crtc->pipe; | |
7869 | bool visible = base != 0; | |
7870 | ||
7871 | if (intel_crtc->cursor_visible != visible) { | |
4726e0b0 | 7872 | int16_t width = intel_crtc->cursor_width; |
548f245b | 7873 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7874 | if (base) { |
7875 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4726e0b0 SK |
7876 | cntl |= MCURSOR_GAMMA_ENABLE; |
7877 | ||
7878 | switch (width) { | |
7879 | case 64: | |
7880 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7881 | break; | |
7882 | case 128: | |
7883 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7884 | break; | |
7885 | case 256: | |
7886 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7887 | break; | |
7888 | default: | |
7889 | WARN_ON(1); | |
7890 | return; | |
7891 | } | |
560b85bb CW |
7892 | cntl |= pipe << 28; /* Connect to correct pipe */ |
7893 | } else { | |
7894 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7895 | cntl |= CURSOR_MODE_DISABLE; | |
7896 | } | |
9db4a9c7 | 7897 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7898 | |
7899 | intel_crtc->cursor_visible = visible; | |
7900 | } | |
7901 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7902 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7903 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7904 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7905 | } |
7906 | ||
65a21cd6 JB |
7907 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7908 | { | |
7909 | struct drm_device *dev = crtc->dev; | |
7910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7912 | int pipe = intel_crtc->pipe; | |
7913 | bool visible = base != 0; | |
7914 | ||
7915 | if (intel_crtc->cursor_visible != visible) { | |
4726e0b0 | 7916 | int16_t width = intel_crtc->cursor_width; |
5efb3e28 | 7917 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
65a21cd6 JB |
7918 | if (base) { |
7919 | cntl &= ~CURSOR_MODE; | |
4726e0b0 SK |
7920 | cntl |= MCURSOR_GAMMA_ENABLE; |
7921 | switch (width) { | |
7922 | case 64: | |
7923 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7924 | break; | |
7925 | case 128: | |
7926 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7927 | break; | |
7928 | case 256: | |
7929 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7930 | break; | |
7931 | default: | |
7932 | WARN_ON(1); | |
7933 | return; | |
7934 | } | |
65a21cd6 JB |
7935 | } else { |
7936 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7937 | cntl |= CURSOR_MODE_DISABLE; | |
7938 | } | |
6bbfa1c5 | 7939 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7940 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7941 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7942 | } | |
5efb3e28 | 7943 | I915_WRITE(CURCNTR(pipe), cntl); |
65a21cd6 JB |
7944 | |
7945 | intel_crtc->cursor_visible = visible; | |
7946 | } | |
7947 | /* and commit changes on next vblank */ | |
5efb3e28 VS |
7948 | POSTING_READ(CURCNTR(pipe)); |
7949 | I915_WRITE(CURBASE(pipe), base); | |
7950 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
7951 | } |
7952 | ||
cda4b7d3 | 7953 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7954 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7955 | bool on) | |
cda4b7d3 CW |
7956 | { |
7957 | struct drm_device *dev = crtc->dev; | |
7958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7959 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7960 | int pipe = intel_crtc->pipe; | |
7961 | int x = intel_crtc->cursor_x; | |
7962 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7963 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7964 | bool visible; |
7965 | ||
d6e4db15 | 7966 | if (on) |
cda4b7d3 | 7967 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7968 | |
d6e4db15 VS |
7969 | if (x >= intel_crtc->config.pipe_src_w) |
7970 | base = 0; | |
7971 | ||
7972 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7973 | base = 0; |
7974 | ||
7975 | if (x < 0) { | |
efc9064e | 7976 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7977 | base = 0; |
7978 | ||
7979 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7980 | x = -x; | |
7981 | } | |
7982 | pos |= x << CURSOR_X_SHIFT; | |
7983 | ||
7984 | if (y < 0) { | |
efc9064e | 7985 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7986 | base = 0; |
7987 | ||
7988 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7989 | y = -y; | |
7990 | } | |
7991 | pos |= y << CURSOR_Y_SHIFT; | |
7992 | ||
7993 | visible = base != 0; | |
560b85bb | 7994 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7995 | return; |
7996 | ||
5efb3e28 VS |
7997 | I915_WRITE(CURPOS(pipe), pos); |
7998 | ||
7999 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8000 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8001 | else if (IS_845G(dev) || IS_I865G(dev)) |
8002 | i845_update_cursor(crtc, base); | |
8003 | else | |
8004 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8005 | } |
8006 | ||
79e53945 | 8007 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 8008 | struct drm_file *file, |
79e53945 JB |
8009 | uint32_t handle, |
8010 | uint32_t width, uint32_t height) | |
8011 | { | |
8012 | struct drm_device *dev = crtc->dev; | |
8013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 8015 | struct drm_i915_gem_object *obj; |
64f962e3 | 8016 | unsigned old_width; |
cda4b7d3 | 8017 | uint32_t addr; |
3f8bc370 | 8018 | int ret; |
79e53945 | 8019 | |
79e53945 JB |
8020 | /* if we want to turn off the cursor ignore width and height */ |
8021 | if (!handle) { | |
28c97730 | 8022 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8023 | addr = 0; |
05394f39 | 8024 | obj = NULL; |
5004417d | 8025 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8026 | goto finish; |
79e53945 JB |
8027 | } |
8028 | ||
4726e0b0 SK |
8029 | /* Check for which cursor types we support */ |
8030 | if (!((width == 64 && height == 64) || | |
8031 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8032 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8033 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8034 | return -EINVAL; |
8035 | } | |
8036 | ||
05394f39 | 8037 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 8038 | if (&obj->base == NULL) |
79e53945 JB |
8039 | return -ENOENT; |
8040 | ||
05394f39 | 8041 | if (obj->base.size < width * height * 4) { |
3b25b31f | 8042 | DRM_DEBUG_KMS("buffer is to small\n"); |
34b8686e DA |
8043 | ret = -ENOMEM; |
8044 | goto fail; | |
79e53945 JB |
8045 | } |
8046 | ||
71acb5eb | 8047 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8048 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8049 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8050 | unsigned alignment; |
8051 | ||
d9e86c0e | 8052 | if (obj->tiling_mode) { |
3b25b31f | 8053 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8054 | ret = -EINVAL; |
8055 | goto fail_locked; | |
8056 | } | |
8057 | ||
693db184 CW |
8058 | /* Note that the w/a also requires 2 PTE of padding following |
8059 | * the bo. We currently fill all unused PTE with the shadow | |
8060 | * page and so we should always have valid PTE following the | |
8061 | * cursor preventing the VT-d warning. | |
8062 | */ | |
8063 | alignment = 0; | |
8064 | if (need_vtd_wa(dev)) | |
8065 | alignment = 64*1024; | |
8066 | ||
8067 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8068 | if (ret) { |
3b25b31f | 8069 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8070 | goto fail_locked; |
e7b526bb CW |
8071 | } |
8072 | ||
d9e86c0e CW |
8073 | ret = i915_gem_object_put_fence(obj); |
8074 | if (ret) { | |
3b25b31f | 8075 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8076 | goto fail_unpin; |
8077 | } | |
8078 | ||
f343c5f6 | 8079 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8080 | } else { |
6eeefaf3 | 8081 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 8082 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
8083 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
8084 | align); | |
71acb5eb | 8085 | if (ret) { |
3b25b31f | 8086 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8087 | goto fail_locked; |
71acb5eb | 8088 | } |
05394f39 | 8089 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
8090 | } |
8091 | ||
a6c45cf0 | 8092 | if (IS_GEN2(dev)) |
14b60391 JB |
8093 | I915_WRITE(CURSIZE, (height << 12) | width); |
8094 | ||
3f8bc370 | 8095 | finish: |
3f8bc370 | 8096 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 8097 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 8098 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
8099 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
8100 | } else | |
cc98b413 | 8101 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 8102 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 8103 | } |
80824003 | 8104 | |
7f9872e0 | 8105 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8106 | |
64f962e3 CW |
8107 | old_width = intel_crtc->cursor_width; |
8108 | ||
3f8bc370 | 8109 | intel_crtc->cursor_addr = addr; |
05394f39 | 8110 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8111 | intel_crtc->cursor_width = width; |
8112 | intel_crtc->cursor_height = height; | |
8113 | ||
64f962e3 CW |
8114 | if (intel_crtc->active) { |
8115 | if (old_width != width) | |
8116 | intel_update_watermarks(crtc); | |
f2f5f771 | 8117 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8118 | } |
3f8bc370 | 8119 | |
79e53945 | 8120 | return 0; |
e7b526bb | 8121 | fail_unpin: |
cc98b413 | 8122 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8123 | fail_locked: |
34b8686e | 8124 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8125 | fail: |
05394f39 | 8126 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8127 | return ret; |
79e53945 JB |
8128 | } |
8129 | ||
8130 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
8131 | { | |
79e53945 | 8132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8133 | |
92e76c8c VS |
8134 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
8135 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 8136 | |
f2f5f771 VS |
8137 | if (intel_crtc->active) |
8138 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
8139 | |
8140 | return 0; | |
b8c00ac5 DA |
8141 | } |
8142 | ||
79e53945 | 8143 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8144 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8145 | { |
7203425a | 8146 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8148 | |
7203425a | 8149 | for (i = start; i < end; i++) { |
79e53945 JB |
8150 | intel_crtc->lut_r[i] = red[i] >> 8; |
8151 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8152 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8153 | } | |
8154 | ||
8155 | intel_crtc_load_lut(crtc); | |
8156 | } | |
8157 | ||
79e53945 JB |
8158 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8159 | static struct drm_display_mode load_detect_mode = { | |
8160 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8161 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8162 | }; | |
8163 | ||
a8bb6818 DV |
8164 | struct drm_framebuffer * |
8165 | __intel_framebuffer_create(struct drm_device *dev, | |
8166 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8167 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8168 | { |
8169 | struct intel_framebuffer *intel_fb; | |
8170 | int ret; | |
8171 | ||
8172 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8173 | if (!intel_fb) { | |
8174 | drm_gem_object_unreference_unlocked(&obj->base); | |
8175 | return ERR_PTR(-ENOMEM); | |
8176 | } | |
8177 | ||
8178 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8179 | if (ret) |
8180 | goto err; | |
d2dff872 CW |
8181 | |
8182 | return &intel_fb->base; | |
dd4916c5 DV |
8183 | err: |
8184 | drm_gem_object_unreference_unlocked(&obj->base); | |
8185 | kfree(intel_fb); | |
8186 | ||
8187 | return ERR_PTR(ret); | |
d2dff872 CW |
8188 | } |
8189 | ||
b5ea642a | 8190 | static struct drm_framebuffer * |
a8bb6818 DV |
8191 | intel_framebuffer_create(struct drm_device *dev, |
8192 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8193 | struct drm_i915_gem_object *obj) | |
8194 | { | |
8195 | struct drm_framebuffer *fb; | |
8196 | int ret; | |
8197 | ||
8198 | ret = i915_mutex_lock_interruptible(dev); | |
8199 | if (ret) | |
8200 | return ERR_PTR(ret); | |
8201 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8202 | mutex_unlock(&dev->struct_mutex); | |
8203 | ||
8204 | return fb; | |
8205 | } | |
8206 | ||
d2dff872 CW |
8207 | static u32 |
8208 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8209 | { | |
8210 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8211 | return ALIGN(pitch, 64); | |
8212 | } | |
8213 | ||
8214 | static u32 | |
8215 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8216 | { | |
8217 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
8218 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
8219 | } | |
8220 | ||
8221 | static struct drm_framebuffer * | |
8222 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8223 | struct drm_display_mode *mode, | |
8224 | int depth, int bpp) | |
8225 | { | |
8226 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8227 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8228 | |
8229 | obj = i915_gem_alloc_object(dev, | |
8230 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8231 | if (obj == NULL) | |
8232 | return ERR_PTR(-ENOMEM); | |
8233 | ||
8234 | mode_cmd.width = mode->hdisplay; | |
8235 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8236 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8237 | bpp); | |
5ca0c34a | 8238 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8239 | |
8240 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8241 | } | |
8242 | ||
8243 | static struct drm_framebuffer * | |
8244 | mode_fits_in_fbdev(struct drm_device *dev, | |
8245 | struct drm_display_mode *mode) | |
8246 | { | |
4520f53a | 8247 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8248 | struct drm_i915_private *dev_priv = dev->dev_private; |
8249 | struct drm_i915_gem_object *obj; | |
8250 | struct drm_framebuffer *fb; | |
8251 | ||
4c0e5528 | 8252 | if (!dev_priv->fbdev) |
d2dff872 CW |
8253 | return NULL; |
8254 | ||
4c0e5528 | 8255 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8256 | return NULL; |
8257 | ||
4c0e5528 DV |
8258 | obj = dev_priv->fbdev->fb->obj; |
8259 | BUG_ON(!obj); | |
8260 | ||
8bcd4553 | 8261 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8262 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8263 | fb->bits_per_pixel)) | |
d2dff872 CW |
8264 | return NULL; |
8265 | ||
01f2c773 | 8266 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8267 | return NULL; |
8268 | ||
8269 | return fb; | |
4520f53a DV |
8270 | #else |
8271 | return NULL; | |
8272 | #endif | |
d2dff872 CW |
8273 | } |
8274 | ||
d2434ab7 | 8275 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8276 | struct drm_display_mode *mode, |
8261b191 | 8277 | struct intel_load_detect_pipe *old) |
79e53945 JB |
8278 | { |
8279 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8280 | struct intel_encoder *intel_encoder = |
8281 | intel_attached_encoder(connector); | |
79e53945 | 8282 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8283 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8284 | struct drm_crtc *crtc = NULL; |
8285 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8286 | struct drm_framebuffer *fb; |
79e53945 JB |
8287 | int i = -1; |
8288 | ||
d2dff872 CW |
8289 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8290 | connector->base.id, drm_get_connector_name(connector), | |
8291 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8292 | ||
79e53945 JB |
8293 | /* |
8294 | * Algorithm gets a little messy: | |
7a5e4805 | 8295 | * |
79e53945 JB |
8296 | * - if the connector already has an assigned crtc, use it (but make |
8297 | * sure it's on first) | |
7a5e4805 | 8298 | * |
79e53945 JB |
8299 | * - try to find the first unused crtc that can drive this connector, |
8300 | * and use that if we find one | |
79e53945 JB |
8301 | */ |
8302 | ||
8303 | /* See if we already have a CRTC for this connector */ | |
8304 | if (encoder->crtc) { | |
8305 | crtc = encoder->crtc; | |
8261b191 | 8306 | |
7b24056b DV |
8307 | mutex_lock(&crtc->mutex); |
8308 | ||
24218aac | 8309 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8310 | old->load_detect_temp = false; |
8311 | ||
8312 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8313 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8314 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8315 | |
7173188d | 8316 | return true; |
79e53945 JB |
8317 | } |
8318 | ||
8319 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8320 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8321 | i++; |
8322 | if (!(encoder->possible_crtcs & (1 << i))) | |
8323 | continue; | |
8324 | if (!possible_crtc->enabled) { | |
8325 | crtc = possible_crtc; | |
8326 | break; | |
8327 | } | |
79e53945 JB |
8328 | } |
8329 | ||
8330 | /* | |
8331 | * If we didn't find an unused CRTC, don't use any. | |
8332 | */ | |
8333 | if (!crtc) { | |
7173188d CW |
8334 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
8335 | return false; | |
79e53945 JB |
8336 | } |
8337 | ||
7b24056b | 8338 | mutex_lock(&crtc->mutex); |
fc303101 DV |
8339 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8340 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8341 | |
8342 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8343 | intel_crtc->new_enabled = true; |
8344 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8345 | old->dpms_mode = connector->dpms; |
8261b191 | 8346 | old->load_detect_temp = true; |
d2dff872 | 8347 | old->release_fb = NULL; |
79e53945 | 8348 | |
6492711d CW |
8349 | if (!mode) |
8350 | mode = &load_detect_mode; | |
79e53945 | 8351 | |
d2dff872 CW |
8352 | /* We need a framebuffer large enough to accommodate all accesses |
8353 | * that the plane may generate whilst we perform load detection. | |
8354 | * We can not rely on the fbcon either being present (we get called | |
8355 | * during its initialisation to detect all boot displays, or it may | |
8356 | * not even exist) or that it is large enough to satisfy the | |
8357 | * requested mode. | |
8358 | */ | |
94352cf9 DV |
8359 | fb = mode_fits_in_fbdev(dev, mode); |
8360 | if (fb == NULL) { | |
d2dff872 | 8361 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8362 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8363 | old->release_fb = fb; | |
d2dff872 CW |
8364 | } else |
8365 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8366 | if (IS_ERR(fb)) { |
d2dff872 | 8367 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8368 | goto fail; |
79e53945 | 8369 | } |
79e53945 | 8370 | |
c0c36b94 | 8371 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8372 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8373 | if (old->release_fb) |
8374 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8375 | goto fail; |
79e53945 | 8376 | } |
7173188d | 8377 | |
79e53945 | 8378 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8379 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8380 | return true; |
412b61d8 VS |
8381 | |
8382 | fail: | |
8383 | intel_crtc->new_enabled = crtc->enabled; | |
8384 | if (intel_crtc->new_enabled) | |
8385 | intel_crtc->new_config = &intel_crtc->config; | |
8386 | else | |
8387 | intel_crtc->new_config = NULL; | |
8388 | mutex_unlock(&crtc->mutex); | |
8389 | return false; | |
79e53945 JB |
8390 | } |
8391 | ||
d2434ab7 | 8392 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 8393 | struct intel_load_detect_pipe *old) |
79e53945 | 8394 | { |
d2434ab7 DV |
8395 | struct intel_encoder *intel_encoder = |
8396 | intel_attached_encoder(connector); | |
4ef69c7a | 8397 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8398 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8400 | |
d2dff872 CW |
8401 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8402 | connector->base.id, drm_get_connector_name(connector), | |
8403 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8404 | ||
8261b191 | 8405 | if (old->load_detect_temp) { |
fc303101 DV |
8406 | to_intel_connector(connector)->new_encoder = NULL; |
8407 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8408 | intel_crtc->new_enabled = false; |
8409 | intel_crtc->new_config = NULL; | |
fc303101 | 8410 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8411 | |
36206361 DV |
8412 | if (old->release_fb) { |
8413 | drm_framebuffer_unregister_private(old->release_fb); | |
8414 | drm_framebuffer_unreference(old->release_fb); | |
8415 | } | |
d2dff872 | 8416 | |
67c96400 | 8417 | mutex_unlock(&crtc->mutex); |
0622a53c | 8418 | return; |
79e53945 JB |
8419 | } |
8420 | ||
c751ce4f | 8421 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8422 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8423 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
8424 | |
8425 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
8426 | } |
8427 | ||
da4a1efa VS |
8428 | static int i9xx_pll_refclk(struct drm_device *dev, |
8429 | const struct intel_crtc_config *pipe_config) | |
8430 | { | |
8431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8432 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8433 | ||
8434 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8435 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8436 | else if (HAS_PCH_SPLIT(dev)) |
8437 | return 120000; | |
8438 | else if (!IS_GEN2(dev)) | |
8439 | return 96000; | |
8440 | else | |
8441 | return 48000; | |
8442 | } | |
8443 | ||
79e53945 | 8444 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8445 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8446 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8447 | { |
f1f644dc | 8448 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8449 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8450 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8451 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8452 | u32 fp; |
8453 | intel_clock_t clock; | |
da4a1efa | 8454 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8455 | |
8456 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8457 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8458 | else |
293623f7 | 8459 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8460 | |
8461 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8462 | if (IS_PINEVIEW(dev)) { |
8463 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8464 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8465 | } else { |
8466 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8467 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8468 | } | |
8469 | ||
a6c45cf0 | 8470 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8471 | if (IS_PINEVIEW(dev)) |
8472 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8473 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8474 | else |
8475 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8476 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8477 | ||
8478 | switch (dpll & DPLL_MODE_MASK) { | |
8479 | case DPLLB_MODE_DAC_SERIAL: | |
8480 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8481 | 5 : 10; | |
8482 | break; | |
8483 | case DPLLB_MODE_LVDS: | |
8484 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8485 | 7 : 14; | |
8486 | break; | |
8487 | default: | |
28c97730 | 8488 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8489 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8490 | return; |
79e53945 JB |
8491 | } |
8492 | ||
ac58c3f0 | 8493 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8494 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8495 | else |
da4a1efa | 8496 | i9xx_clock(refclk, &clock); |
79e53945 | 8497 | } else { |
0fb58223 | 8498 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8499 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8500 | |
8501 | if (is_lvds) { | |
8502 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8503 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8504 | |
8505 | if (lvds & LVDS_CLKB_POWER_UP) | |
8506 | clock.p2 = 7; | |
8507 | else | |
8508 | clock.p2 = 14; | |
79e53945 JB |
8509 | } else { |
8510 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8511 | clock.p1 = 2; | |
8512 | else { | |
8513 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8514 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8515 | } | |
8516 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8517 | clock.p2 = 4; | |
8518 | else | |
8519 | clock.p2 = 2; | |
79e53945 | 8520 | } |
da4a1efa VS |
8521 | |
8522 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8523 | } |
8524 | ||
18442d08 VS |
8525 | /* |
8526 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8527 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8528 | * encoder's get_config() function. |
8529 | */ | |
8530 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8531 | } |
8532 | ||
6878da05 VS |
8533 | int intel_dotclock_calculate(int link_freq, |
8534 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8535 | { |
f1f644dc JB |
8536 | /* |
8537 | * The calculation for the data clock is: | |
1041a02f | 8538 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8539 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8540 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8541 | * |
8542 | * and the link clock is simpler: | |
1041a02f | 8543 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8544 | */ |
8545 | ||
6878da05 VS |
8546 | if (!m_n->link_n) |
8547 | return 0; | |
f1f644dc | 8548 | |
6878da05 VS |
8549 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8550 | } | |
f1f644dc | 8551 | |
18442d08 VS |
8552 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8553 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8554 | { |
8555 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8556 | |
18442d08 VS |
8557 | /* read out port_clock from the DPLL */ |
8558 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8559 | |
f1f644dc | 8560 | /* |
18442d08 | 8561 | * This value does not include pixel_multiplier. |
241bfc38 | 8562 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8563 | * agree once we know their relationship in the encoder's |
8564 | * get_config() function. | |
79e53945 | 8565 | */ |
241bfc38 | 8566 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8567 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8568 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8569 | } |
8570 | ||
8571 | /** Returns the currently programmed mode of the given pipe. */ | |
8572 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8573 | struct drm_crtc *crtc) | |
8574 | { | |
548f245b | 8575 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8577 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8578 | struct drm_display_mode *mode; |
f1f644dc | 8579 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8580 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8581 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8582 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8583 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8584 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8585 | |
8586 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8587 | if (!mode) | |
8588 | return NULL; | |
8589 | ||
f1f644dc JB |
8590 | /* |
8591 | * Construct a pipe_config sufficient for getting the clock info | |
8592 | * back out of crtc_clock_get. | |
8593 | * | |
8594 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8595 | * to use a real value here instead. | |
8596 | */ | |
293623f7 | 8597 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8598 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8599 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8600 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8601 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8602 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8603 | ||
773ae034 | 8604 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8605 | mode->hdisplay = (htot & 0xffff) + 1; |
8606 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8607 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8608 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8609 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8610 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8611 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8612 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8613 | ||
8614 | drm_mode_set_name(mode); | |
79e53945 JB |
8615 | |
8616 | return mode; | |
8617 | } | |
8618 | ||
3dec0095 | 8619 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8620 | { |
8621 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8622 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a JB |
8623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8624 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8625 | int dpll_reg = DPLL(pipe); |
8626 | int dpll; | |
652c393a | 8627 | |
bad720ff | 8628 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8629 | return; |
8630 | ||
8631 | if (!dev_priv->lvds_downclock_avail) | |
8632 | return; | |
8633 | ||
dbdc6479 | 8634 | dpll = I915_READ(dpll_reg); |
652c393a | 8635 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8636 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8637 | |
8ac5a6d5 | 8638 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8639 | |
8640 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8641 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8642 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8643 | |
652c393a JB |
8644 | dpll = I915_READ(dpll_reg); |
8645 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8646 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8647 | } |
652c393a JB |
8648 | } |
8649 | ||
8650 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8651 | { | |
8652 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8653 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8655 | |
bad720ff | 8656 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8657 | return; |
8658 | ||
8659 | if (!dev_priv->lvds_downclock_avail) | |
8660 | return; | |
8661 | ||
8662 | /* | |
8663 | * Since this is called by a timer, we should never get here in | |
8664 | * the manual case. | |
8665 | */ | |
8666 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8667 | int pipe = intel_crtc->pipe; |
8668 | int dpll_reg = DPLL(pipe); | |
8669 | int dpll; | |
f6e5b160 | 8670 | |
44d98a61 | 8671 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8672 | |
8ac5a6d5 | 8673 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8674 | |
dc257cf1 | 8675 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8676 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8677 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8678 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8679 | dpll = I915_READ(dpll_reg); |
8680 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8681 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8682 | } |
8683 | ||
8684 | } | |
8685 | ||
f047e395 CW |
8686 | void intel_mark_busy(struct drm_device *dev) |
8687 | { | |
c67a470b PZ |
8688 | struct drm_i915_private *dev_priv = dev->dev_private; |
8689 | ||
f62a0076 CW |
8690 | if (dev_priv->mm.busy) |
8691 | return; | |
8692 | ||
43694d69 | 8693 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8694 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8695 | dev_priv->mm.busy = true; |
f047e395 CW |
8696 | } |
8697 | ||
8698 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8699 | { |
c67a470b | 8700 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8701 | struct drm_crtc *crtc; |
652c393a | 8702 | |
f62a0076 CW |
8703 | if (!dev_priv->mm.busy) |
8704 | return; | |
8705 | ||
8706 | dev_priv->mm.busy = false; | |
8707 | ||
d330a953 | 8708 | if (!i915.powersave) |
bb4cdd53 | 8709 | goto out; |
652c393a | 8710 | |
70e1e0ec | 8711 | for_each_crtc(dev, crtc) { |
f4510a27 | 8712 | if (!crtc->primary->fb) |
652c393a JB |
8713 | continue; |
8714 | ||
725a5b54 | 8715 | intel_decrease_pllclock(crtc); |
652c393a | 8716 | } |
b29c19b6 | 8717 | |
3d13ef2e | 8718 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8719 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8720 | |
8721 | out: | |
43694d69 | 8722 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8723 | } |
8724 | ||
c65355bb CW |
8725 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8726 | struct intel_ring_buffer *ring) | |
652c393a | 8727 | { |
f047e395 CW |
8728 | struct drm_device *dev = obj->base.dev; |
8729 | struct drm_crtc *crtc; | |
652c393a | 8730 | |
d330a953 | 8731 | if (!i915.powersave) |
acb87dfb CW |
8732 | return; |
8733 | ||
70e1e0ec | 8734 | for_each_crtc(dev, crtc) { |
f4510a27 | 8735 | if (!crtc->primary->fb) |
652c393a JB |
8736 | continue; |
8737 | ||
f4510a27 | 8738 | if (to_intel_framebuffer(crtc->primary->fb)->obj != obj) |
c65355bb CW |
8739 | continue; |
8740 | ||
8741 | intel_increase_pllclock(crtc); | |
8742 | if (ring && intel_fbc_enabled(dev)) | |
8743 | ring->fbc_dirty = true; | |
652c393a JB |
8744 | } |
8745 | } | |
8746 | ||
79e53945 JB |
8747 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8748 | { | |
8749 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8750 | struct drm_device *dev = crtc->dev; |
8751 | struct intel_unpin_work *work; | |
8752 | unsigned long flags; | |
8753 | ||
8754 | spin_lock_irqsave(&dev->event_lock, flags); | |
8755 | work = intel_crtc->unpin_work; | |
8756 | intel_crtc->unpin_work = NULL; | |
8757 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8758 | ||
8759 | if (work) { | |
8760 | cancel_work_sync(&work->work); | |
8761 | kfree(work); | |
8762 | } | |
79e53945 | 8763 | |
40ccc72b MK |
8764 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8765 | ||
79e53945 | 8766 | drm_crtc_cleanup(crtc); |
67e77c5a | 8767 | |
79e53945 JB |
8768 | kfree(intel_crtc); |
8769 | } | |
8770 | ||
6b95a207 KH |
8771 | static void intel_unpin_work_fn(struct work_struct *__work) |
8772 | { | |
8773 | struct intel_unpin_work *work = | |
8774 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8775 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8776 | |
b4a98e57 | 8777 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8778 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8779 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8780 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8781 | |
b4a98e57 CW |
8782 | intel_update_fbc(dev); |
8783 | mutex_unlock(&dev->struct_mutex); | |
8784 | ||
8785 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8786 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8787 | ||
6b95a207 KH |
8788 | kfree(work); |
8789 | } | |
8790 | ||
1afe3e9d | 8791 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8792 | struct drm_crtc *crtc) |
6b95a207 | 8793 | { |
fbee40df | 8794 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8796 | struct intel_unpin_work *work; | |
6b95a207 KH |
8797 | unsigned long flags; |
8798 | ||
8799 | /* Ignore early vblank irqs */ | |
8800 | if (intel_crtc == NULL) | |
8801 | return; | |
8802 | ||
8803 | spin_lock_irqsave(&dev->event_lock, flags); | |
8804 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8805 | |
8806 | /* Ensure we don't miss a work->pending update ... */ | |
8807 | smp_rmb(); | |
8808 | ||
8809 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8810 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8811 | return; | |
8812 | } | |
8813 | ||
e7d841ca CW |
8814 | /* and that the unpin work is consistent wrt ->pending. */ |
8815 | smp_rmb(); | |
8816 | ||
6b95a207 | 8817 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8818 | |
45a066eb RC |
8819 | if (work->event) |
8820 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8821 | |
0af7e4df MK |
8822 | drm_vblank_put(dev, intel_crtc->pipe); |
8823 | ||
6b95a207 KH |
8824 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8825 | ||
2c10d571 | 8826 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8827 | |
8828 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8829 | |
8830 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8831 | } |
8832 | ||
1afe3e9d JB |
8833 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8834 | { | |
fbee40df | 8835 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8836 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8837 | ||
49b14a5c | 8838 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8839 | } |
8840 | ||
8841 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8842 | { | |
fbee40df | 8843 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8844 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8845 | ||
49b14a5c | 8846 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8847 | } |
8848 | ||
6b95a207 KH |
8849 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8850 | { | |
fbee40df | 8851 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8852 | struct intel_crtc *intel_crtc = |
8853 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8854 | unsigned long flags; | |
8855 | ||
e7d841ca CW |
8856 | /* NB: An MMIO update of the plane base pointer will also |
8857 | * generate a page-flip completion irq, i.e. every modeset | |
8858 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8859 | */ | |
6b95a207 | 8860 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8861 | if (intel_crtc->unpin_work) |
8862 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8863 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8864 | } | |
8865 | ||
eba905b2 | 8866 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
8867 | { |
8868 | /* Ensure that the work item is consistent when activating it ... */ | |
8869 | smp_wmb(); | |
8870 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8871 | /* and that it is marked active as soon as the irq could fire. */ | |
8872 | smp_wmb(); | |
8873 | } | |
8874 | ||
8c9f3aaf JB |
8875 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8876 | struct drm_crtc *crtc, | |
8877 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8878 | struct drm_i915_gem_object *obj, |
8879 | uint32_t flags) | |
8c9f3aaf JB |
8880 | { |
8881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8882 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8883 | u32 flip_mask; |
6d90c952 | 8884 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8885 | int ret; |
8886 | ||
6d90c952 | 8887 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8888 | if (ret) |
83d4092b | 8889 | goto err; |
8c9f3aaf | 8890 | |
6d90c952 | 8891 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8892 | if (ret) |
83d4092b | 8893 | goto err_unpin; |
8c9f3aaf JB |
8894 | |
8895 | /* Can't queue multiple flips, so wait for the previous | |
8896 | * one to finish before executing the next. | |
8897 | */ | |
8898 | if (intel_crtc->plane) | |
8899 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8900 | else | |
8901 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8902 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8903 | intel_ring_emit(ring, MI_NOOP); | |
8904 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8905 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8906 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8907 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8908 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8909 | |
8910 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8911 | __intel_ring_advance(ring); |
83d4092b CW |
8912 | return 0; |
8913 | ||
8914 | err_unpin: | |
8915 | intel_unpin_fb_obj(obj); | |
8916 | err: | |
8c9f3aaf JB |
8917 | return ret; |
8918 | } | |
8919 | ||
8920 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8921 | struct drm_crtc *crtc, | |
8922 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8923 | struct drm_i915_gem_object *obj, |
8924 | uint32_t flags) | |
8c9f3aaf JB |
8925 | { |
8926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8928 | u32 flip_mask; |
6d90c952 | 8929 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8930 | int ret; |
8931 | ||
6d90c952 | 8932 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8933 | if (ret) |
83d4092b | 8934 | goto err; |
8c9f3aaf | 8935 | |
6d90c952 | 8936 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8937 | if (ret) |
83d4092b | 8938 | goto err_unpin; |
8c9f3aaf JB |
8939 | |
8940 | if (intel_crtc->plane) | |
8941 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8942 | else | |
8943 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8944 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8945 | intel_ring_emit(ring, MI_NOOP); | |
8946 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8947 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8948 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8949 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8950 | intel_ring_emit(ring, MI_NOOP); |
8951 | ||
e7d841ca | 8952 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8953 | __intel_ring_advance(ring); |
83d4092b CW |
8954 | return 0; |
8955 | ||
8956 | err_unpin: | |
8957 | intel_unpin_fb_obj(obj); | |
8958 | err: | |
8c9f3aaf JB |
8959 | return ret; |
8960 | } | |
8961 | ||
8962 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8963 | struct drm_crtc *crtc, | |
8964 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8965 | struct drm_i915_gem_object *obj, |
8966 | uint32_t flags) | |
8c9f3aaf JB |
8967 | { |
8968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8969 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8970 | uint32_t pf, pipesrc; | |
6d90c952 | 8971 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8972 | int ret; |
8973 | ||
6d90c952 | 8974 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8975 | if (ret) |
83d4092b | 8976 | goto err; |
8c9f3aaf | 8977 | |
6d90c952 | 8978 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8979 | if (ret) |
83d4092b | 8980 | goto err_unpin; |
8c9f3aaf JB |
8981 | |
8982 | /* i965+ uses the linear or tiled offsets from the | |
8983 | * Display Registers (which do not change across a page-flip) | |
8984 | * so we need only reprogram the base address. | |
8985 | */ | |
6d90c952 DV |
8986 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8987 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8988 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8989 | intel_ring_emit(ring, |
f343c5f6 | 8990 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8991 | obj->tiling_mode); |
8c9f3aaf JB |
8992 | |
8993 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8994 | * untested on non-native modes, so ignore it for now. | |
8995 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8996 | */ | |
8997 | pf = 0; | |
8998 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8999 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9000 | |
9001 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9002 | __intel_ring_advance(ring); |
83d4092b CW |
9003 | return 0; |
9004 | ||
9005 | err_unpin: | |
9006 | intel_unpin_fb_obj(obj); | |
9007 | err: | |
8c9f3aaf JB |
9008 | return ret; |
9009 | } | |
9010 | ||
9011 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9012 | struct drm_crtc *crtc, | |
9013 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9014 | struct drm_i915_gem_object *obj, |
9015 | uint32_t flags) | |
8c9f3aaf JB |
9016 | { |
9017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 9019 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
9020 | uint32_t pf, pipesrc; |
9021 | int ret; | |
9022 | ||
6d90c952 | 9023 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 9024 | if (ret) |
83d4092b | 9025 | goto err; |
8c9f3aaf | 9026 | |
6d90c952 | 9027 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9028 | if (ret) |
83d4092b | 9029 | goto err_unpin; |
8c9f3aaf | 9030 | |
6d90c952 DV |
9031 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9032 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9033 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 9034 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 9035 | |
dc257cf1 DV |
9036 | /* Contrary to the suggestions in the documentation, |
9037 | * "Enable Panel Fitter" does not seem to be required when page | |
9038 | * flipping with a non-native mode, and worse causes a normal | |
9039 | * modeset to fail. | |
9040 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9041 | */ | |
9042 | pf = 0; | |
8c9f3aaf | 9043 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9044 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9045 | |
9046 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9047 | __intel_ring_advance(ring); |
83d4092b CW |
9048 | return 0; |
9049 | ||
9050 | err_unpin: | |
9051 | intel_unpin_fb_obj(obj); | |
9052 | err: | |
8c9f3aaf JB |
9053 | return ret; |
9054 | } | |
9055 | ||
7c9017e5 JB |
9056 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9057 | struct drm_crtc *crtc, | |
9058 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9059 | struct drm_i915_gem_object *obj, |
9060 | uint32_t flags) | |
7c9017e5 JB |
9061 | { |
9062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 9064 | struct intel_ring_buffer *ring; |
cb05d8de | 9065 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9066 | int len, ret; |
9067 | ||
9068 | ring = obj->ring; | |
1c5fd085 | 9069 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 9070 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
9071 | |
9072 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
9073 | if (ret) | |
83d4092b | 9074 | goto err; |
7c9017e5 | 9075 | |
eba905b2 | 9076 | switch (intel_crtc->plane) { |
cb05d8de DV |
9077 | case PLANE_A: |
9078 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9079 | break; | |
9080 | case PLANE_B: | |
9081 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9082 | break; | |
9083 | case PLANE_C: | |
9084 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9085 | break; | |
9086 | default: | |
9087 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
9088 | ret = -ENODEV; | |
ab3951eb | 9089 | goto err_unpin; |
cb05d8de DV |
9090 | } |
9091 | ||
ffe74d75 | 9092 | len = 4; |
f476828a | 9093 | if (ring->id == RCS) { |
ffe74d75 | 9094 | len += 6; |
f476828a DL |
9095 | /* |
9096 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9097 | * 48bits addresses, and we need a NOOP for the batch size to | |
9098 | * stay even. | |
9099 | */ | |
9100 | if (IS_GEN8(dev)) | |
9101 | len += 2; | |
9102 | } | |
ffe74d75 | 9103 | |
f66fab8e VS |
9104 | /* |
9105 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9106 | * "The full packet must be contained within the same cache line." | |
9107 | * | |
9108 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9109 | * cacheline, if we ever start emitting more commands before | |
9110 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9111 | * then do the cacheline alignment, and finally emit the | |
9112 | * MI_DISPLAY_FLIP. | |
9113 | */ | |
9114 | ret = intel_ring_cacheline_align(ring); | |
9115 | if (ret) | |
9116 | goto err_unpin; | |
9117 | ||
ffe74d75 | 9118 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9119 | if (ret) |
83d4092b | 9120 | goto err_unpin; |
7c9017e5 | 9121 | |
ffe74d75 CW |
9122 | /* Unmask the flip-done completion message. Note that the bspec says that |
9123 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9124 | * more than one flip event at any time (or ensure that one flip message | |
9125 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9126 | * Experimentation says that BCS works despite DERRMR masking all | |
9127 | * flip-done completion events and that unmasking all planes at once | |
9128 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9129 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9130 | */ | |
9131 | if (ring->id == RCS) { | |
9132 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9133 | intel_ring_emit(ring, DERRMR); | |
9134 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9135 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9136 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9137 | if (IS_GEN8(dev)) |
9138 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9139 | MI_SRM_LRM_GLOBAL_GTT); | |
9140 | else | |
9141 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9142 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9143 | intel_ring_emit(ring, DERRMR); |
9144 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9145 | if (IS_GEN8(dev)) { |
9146 | intel_ring_emit(ring, 0); | |
9147 | intel_ring_emit(ring, MI_NOOP); | |
9148 | } | |
ffe74d75 CW |
9149 | } |
9150 | ||
cb05d8de | 9151 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9152 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 9153 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 9154 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9155 | |
9156 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9157 | __intel_ring_advance(ring); |
83d4092b CW |
9158 | return 0; |
9159 | ||
9160 | err_unpin: | |
9161 | intel_unpin_fb_obj(obj); | |
9162 | err: | |
7c9017e5 JB |
9163 | return ret; |
9164 | } | |
9165 | ||
8c9f3aaf JB |
9166 | static int intel_default_queue_flip(struct drm_device *dev, |
9167 | struct drm_crtc *crtc, | |
9168 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9169 | struct drm_i915_gem_object *obj, |
9170 | uint32_t flags) | |
8c9f3aaf JB |
9171 | { |
9172 | return -ENODEV; | |
9173 | } | |
9174 | ||
6b95a207 KH |
9175 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9176 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9177 | struct drm_pending_vblank_event *event, |
9178 | uint32_t page_flip_flags) | |
6b95a207 KH |
9179 | { |
9180 | struct drm_device *dev = crtc->dev; | |
9181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9182 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9183 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 KH |
9184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9185 | struct intel_unpin_work *work; | |
8c9f3aaf | 9186 | unsigned long flags; |
52e68630 | 9187 | int ret; |
6b95a207 | 9188 | |
e6a595d2 | 9189 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9190 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9191 | return -EINVAL; |
9192 | ||
9193 | /* | |
9194 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9195 | * Note that pitch changes could also affect these register. | |
9196 | */ | |
9197 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9198 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9199 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9200 | return -EINVAL; |
9201 | ||
f900db47 CW |
9202 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9203 | goto out_hang; | |
9204 | ||
b14c5679 | 9205 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9206 | if (work == NULL) |
9207 | return -ENOMEM; | |
9208 | ||
6b95a207 | 9209 | work->event = event; |
b4a98e57 | 9210 | work->crtc = crtc; |
4a35f83b | 9211 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9212 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9213 | ||
7317c75e JB |
9214 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
9215 | if (ret) | |
9216 | goto free_work; | |
9217 | ||
6b95a207 KH |
9218 | /* We borrow the event spin lock for protecting unpin_work */ |
9219 | spin_lock_irqsave(&dev->event_lock, flags); | |
9220 | if (intel_crtc->unpin_work) { | |
9221 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9222 | kfree(work); | |
7317c75e | 9223 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
9224 | |
9225 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9226 | return -EBUSY; |
9227 | } | |
9228 | intel_crtc->unpin_work = work; | |
9229 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9230 | ||
b4a98e57 CW |
9231 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9232 | flush_workqueue(dev_priv->wq); | |
9233 | ||
79158103 CW |
9234 | ret = i915_mutex_lock_interruptible(dev); |
9235 | if (ret) | |
9236 | goto cleanup; | |
6b95a207 | 9237 | |
75dfca80 | 9238 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9239 | drm_gem_object_reference(&work->old_fb_obj->base); |
9240 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9241 | |
f4510a27 | 9242 | crtc->primary->fb = fb; |
96b099fd | 9243 | |
e1f99ce6 | 9244 | work->pending_flip_obj = obj; |
e1f99ce6 | 9245 | |
4e5359cd SF |
9246 | work->enable_stall_check = true; |
9247 | ||
b4a98e57 | 9248 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9249 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9250 | |
ed8d1975 | 9251 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
9252 | if (ret) |
9253 | goto cleanup_pending; | |
6b95a207 | 9254 | |
7782de3b | 9255 | intel_disable_fbc(dev); |
c65355bb | 9256 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
9257 | mutex_unlock(&dev->struct_mutex); |
9258 | ||
e5510fac JB |
9259 | trace_i915_flip_request(intel_crtc->plane, obj); |
9260 | ||
6b95a207 | 9261 | return 0; |
96b099fd | 9262 | |
8c9f3aaf | 9263 | cleanup_pending: |
b4a98e57 | 9264 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9265 | crtc->primary->fb = old_fb; |
05394f39 CW |
9266 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9267 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9268 | mutex_unlock(&dev->struct_mutex); |
9269 | ||
79158103 | 9270 | cleanup: |
96b099fd CW |
9271 | spin_lock_irqsave(&dev->event_lock, flags); |
9272 | intel_crtc->unpin_work = NULL; | |
9273 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9274 | ||
7317c75e JB |
9275 | drm_vblank_put(dev, intel_crtc->pipe); |
9276 | free_work: | |
96b099fd CW |
9277 | kfree(work); |
9278 | ||
f900db47 CW |
9279 | if (ret == -EIO) { |
9280 | out_hang: | |
9281 | intel_crtc_wait_for_pending_flips(crtc); | |
9282 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9283 | if (ret == 0 && event) | |
9284 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
9285 | } | |
96b099fd | 9286 | return ret; |
6b95a207 KH |
9287 | } |
9288 | ||
f6e5b160 | 9289 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9290 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9291 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9292 | }; |
9293 | ||
9a935856 DV |
9294 | /** |
9295 | * intel_modeset_update_staged_output_state | |
9296 | * | |
9297 | * Updates the staged output configuration state, e.g. after we've read out the | |
9298 | * current hw state. | |
9299 | */ | |
9300 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9301 | { |
7668851f | 9302 | struct intel_crtc *crtc; |
9a935856 DV |
9303 | struct intel_encoder *encoder; |
9304 | struct intel_connector *connector; | |
f6e5b160 | 9305 | |
9a935856 DV |
9306 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9307 | base.head) { | |
9308 | connector->new_encoder = | |
9309 | to_intel_encoder(connector->base.encoder); | |
9310 | } | |
f6e5b160 | 9311 | |
9a935856 DV |
9312 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9313 | base.head) { | |
9314 | encoder->new_crtc = | |
9315 | to_intel_crtc(encoder->base.crtc); | |
9316 | } | |
7668851f | 9317 | |
d3fcc808 | 9318 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9319 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9320 | |
9321 | if (crtc->new_enabled) | |
9322 | crtc->new_config = &crtc->config; | |
9323 | else | |
9324 | crtc->new_config = NULL; | |
7668851f | 9325 | } |
f6e5b160 CW |
9326 | } |
9327 | ||
9a935856 DV |
9328 | /** |
9329 | * intel_modeset_commit_output_state | |
9330 | * | |
9331 | * This function copies the stage display pipe configuration to the real one. | |
9332 | */ | |
9333 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9334 | { | |
7668851f | 9335 | struct intel_crtc *crtc; |
9a935856 DV |
9336 | struct intel_encoder *encoder; |
9337 | struct intel_connector *connector; | |
f6e5b160 | 9338 | |
9a935856 DV |
9339 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9340 | base.head) { | |
9341 | connector->base.encoder = &connector->new_encoder->base; | |
9342 | } | |
f6e5b160 | 9343 | |
9a935856 DV |
9344 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9345 | base.head) { | |
9346 | encoder->base.crtc = &encoder->new_crtc->base; | |
9347 | } | |
7668851f | 9348 | |
d3fcc808 | 9349 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9350 | crtc->base.enabled = crtc->new_enabled; |
9351 | } | |
9a935856 DV |
9352 | } |
9353 | ||
050f7aeb | 9354 | static void |
eba905b2 | 9355 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9356 | struct intel_crtc_config *pipe_config) |
9357 | { | |
9358 | int bpp = pipe_config->pipe_bpp; | |
9359 | ||
9360 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9361 | connector->base.base.id, | |
9362 | drm_get_connector_name(&connector->base)); | |
9363 | ||
9364 | /* Don't use an invalid EDID bpc value */ | |
9365 | if (connector->base.display_info.bpc && | |
9366 | connector->base.display_info.bpc * 3 < bpp) { | |
9367 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9368 | bpp, connector->base.display_info.bpc*3); | |
9369 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9370 | } | |
9371 | ||
9372 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9373 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9374 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9375 | bpp); | |
9376 | pipe_config->pipe_bpp = 24; | |
9377 | } | |
9378 | } | |
9379 | ||
4e53c2e0 | 9380 | static int |
050f7aeb DV |
9381 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9382 | struct drm_framebuffer *fb, | |
9383 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9384 | { |
050f7aeb DV |
9385 | struct drm_device *dev = crtc->base.dev; |
9386 | struct intel_connector *connector; | |
4e53c2e0 DV |
9387 | int bpp; |
9388 | ||
d42264b1 DV |
9389 | switch (fb->pixel_format) { |
9390 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9391 | bpp = 8*3; /* since we go through a colormap */ |
9392 | break; | |
d42264b1 DV |
9393 | case DRM_FORMAT_XRGB1555: |
9394 | case DRM_FORMAT_ARGB1555: | |
9395 | /* checked in intel_framebuffer_init already */ | |
9396 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9397 | return -EINVAL; | |
9398 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9399 | bpp = 6*3; /* min is 18bpp */ |
9400 | break; | |
d42264b1 DV |
9401 | case DRM_FORMAT_XBGR8888: |
9402 | case DRM_FORMAT_ABGR8888: | |
9403 | /* checked in intel_framebuffer_init already */ | |
9404 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9405 | return -EINVAL; | |
9406 | case DRM_FORMAT_XRGB8888: | |
9407 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9408 | bpp = 8*3; |
9409 | break; | |
d42264b1 DV |
9410 | case DRM_FORMAT_XRGB2101010: |
9411 | case DRM_FORMAT_ARGB2101010: | |
9412 | case DRM_FORMAT_XBGR2101010: | |
9413 | case DRM_FORMAT_ABGR2101010: | |
9414 | /* checked in intel_framebuffer_init already */ | |
9415 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9416 | return -EINVAL; |
4e53c2e0 DV |
9417 | bpp = 10*3; |
9418 | break; | |
baba133a | 9419 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9420 | default: |
9421 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9422 | return -EINVAL; | |
9423 | } | |
9424 | ||
4e53c2e0 DV |
9425 | pipe_config->pipe_bpp = bpp; |
9426 | ||
9427 | /* Clamp display bpp to EDID value */ | |
9428 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9429 | base.head) { |
1b829e05 DV |
9430 | if (!connector->new_encoder || |
9431 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9432 | continue; |
9433 | ||
050f7aeb | 9434 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9435 | } |
9436 | ||
9437 | return bpp; | |
9438 | } | |
9439 | ||
644db711 DV |
9440 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9441 | { | |
9442 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9443 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9444 | mode->crtc_clock, |
644db711 DV |
9445 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9446 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9447 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9448 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9449 | } | |
9450 | ||
c0b03411 DV |
9451 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9452 | struct intel_crtc_config *pipe_config, | |
9453 | const char *context) | |
9454 | { | |
9455 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9456 | context, pipe_name(crtc->pipe)); | |
9457 | ||
9458 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9459 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9460 | pipe_config->pipe_bpp, pipe_config->dither); | |
9461 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9462 | pipe_config->has_pch_encoder, | |
9463 | pipe_config->fdi_lanes, | |
9464 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9465 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9466 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9467 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9468 | pipe_config->has_dp_encoder, | |
9469 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9470 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9471 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9472 | DRM_DEBUG_KMS("requested mode:\n"); |
9473 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9474 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9475 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9476 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9477 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9478 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9479 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9480 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9481 | pipe_config->gmch_pfit.control, | |
9482 | pipe_config->gmch_pfit.pgm_ratios, | |
9483 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9484 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9485 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9486 | pipe_config->pch_pfit.size, |
9487 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9488 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9489 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9490 | } |
9491 | ||
bc079e8b VS |
9492 | static bool encoders_cloneable(const struct intel_encoder *a, |
9493 | const struct intel_encoder *b) | |
accfc0c5 | 9494 | { |
bc079e8b VS |
9495 | /* masks could be asymmetric, so check both ways */ |
9496 | return a == b || (a->cloneable & (1 << b->type) && | |
9497 | b->cloneable & (1 << a->type)); | |
9498 | } | |
9499 | ||
9500 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9501 | struct intel_encoder *encoder) | |
9502 | { | |
9503 | struct drm_device *dev = crtc->base.dev; | |
9504 | struct intel_encoder *source_encoder; | |
9505 | ||
9506 | list_for_each_entry(source_encoder, | |
9507 | &dev->mode_config.encoder_list, base.head) { | |
9508 | if (source_encoder->new_crtc != crtc) | |
9509 | continue; | |
9510 | ||
9511 | if (!encoders_cloneable(encoder, source_encoder)) | |
9512 | return false; | |
9513 | } | |
9514 | ||
9515 | return true; | |
9516 | } | |
9517 | ||
9518 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9519 | { | |
9520 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9521 | struct intel_encoder *encoder; |
9522 | ||
bc079e8b VS |
9523 | list_for_each_entry(encoder, |
9524 | &dev->mode_config.encoder_list, base.head) { | |
9525 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9526 | continue; |
9527 | ||
bc079e8b VS |
9528 | if (!check_single_encoder_cloning(crtc, encoder)) |
9529 | return false; | |
accfc0c5 DV |
9530 | } |
9531 | ||
bc079e8b | 9532 | return true; |
accfc0c5 DV |
9533 | } |
9534 | ||
b8cecdf5 DV |
9535 | static struct intel_crtc_config * |
9536 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9537 | struct drm_framebuffer *fb, |
b8cecdf5 | 9538 | struct drm_display_mode *mode) |
ee7b9f93 | 9539 | { |
7758a113 | 9540 | struct drm_device *dev = crtc->dev; |
7758a113 | 9541 | struct intel_encoder *encoder; |
b8cecdf5 | 9542 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9543 | int plane_bpp, ret = -EINVAL; |
9544 | bool retry = true; | |
ee7b9f93 | 9545 | |
bc079e8b | 9546 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9547 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9548 | return ERR_PTR(-EINVAL); | |
9549 | } | |
9550 | ||
b8cecdf5 DV |
9551 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9552 | if (!pipe_config) | |
7758a113 DV |
9553 | return ERR_PTR(-ENOMEM); |
9554 | ||
b8cecdf5 DV |
9555 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9556 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9557 | |
e143a21c DV |
9558 | pipe_config->cpu_transcoder = |
9559 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9560 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9561 | |
2960bc9c ID |
9562 | /* |
9563 | * Sanitize sync polarity flags based on requested ones. If neither | |
9564 | * positive or negative polarity is requested, treat this as meaning | |
9565 | * negative polarity. | |
9566 | */ | |
9567 | if (!(pipe_config->adjusted_mode.flags & | |
9568 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9569 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9570 | ||
9571 | if (!(pipe_config->adjusted_mode.flags & | |
9572 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9573 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9574 | ||
050f7aeb DV |
9575 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9576 | * plane pixel format and any sink constraints into account. Returns the | |
9577 | * source plane bpp so that dithering can be selected on mismatches | |
9578 | * after encoders and crtc also have had their say. */ | |
9579 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9580 | fb, pipe_config); | |
4e53c2e0 DV |
9581 | if (plane_bpp < 0) |
9582 | goto fail; | |
9583 | ||
e41a56be VS |
9584 | /* |
9585 | * Determine the real pipe dimensions. Note that stereo modes can | |
9586 | * increase the actual pipe size due to the frame doubling and | |
9587 | * insertion of additional space for blanks between the frame. This | |
9588 | * is stored in the crtc timings. We use the requested mode to do this | |
9589 | * computation to clearly distinguish it from the adjusted mode, which | |
9590 | * can be changed by the connectors in the below retry loop. | |
9591 | */ | |
9592 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9593 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9594 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9595 | ||
e29c22c0 | 9596 | encoder_retry: |
ef1b460d | 9597 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9598 | pipe_config->port_clock = 0; |
ef1b460d | 9599 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9600 | |
135c81b8 | 9601 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9602 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9603 | |
7758a113 DV |
9604 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9605 | * adjust it according to limitations or connector properties, and also | |
9606 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9607 | */ |
7758a113 DV |
9608 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9609 | base.head) { | |
47f1c6c9 | 9610 | |
7758a113 DV |
9611 | if (&encoder->new_crtc->base != crtc) |
9612 | continue; | |
7ae89233 | 9613 | |
efea6e8e DV |
9614 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9615 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9616 | goto fail; |
9617 | } | |
ee7b9f93 | 9618 | } |
47f1c6c9 | 9619 | |
ff9a6750 DV |
9620 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9621 | * done afterwards in case the encoder adjusts the mode. */ | |
9622 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9623 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9624 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9625 | |
a43f6e0f | 9626 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9627 | if (ret < 0) { |
7758a113 DV |
9628 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9629 | goto fail; | |
ee7b9f93 | 9630 | } |
e29c22c0 DV |
9631 | |
9632 | if (ret == RETRY) { | |
9633 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9634 | ret = -EINVAL; | |
9635 | goto fail; | |
9636 | } | |
9637 | ||
9638 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9639 | retry = false; | |
9640 | goto encoder_retry; | |
9641 | } | |
9642 | ||
4e53c2e0 DV |
9643 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9644 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9645 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9646 | ||
b8cecdf5 | 9647 | return pipe_config; |
7758a113 | 9648 | fail: |
b8cecdf5 | 9649 | kfree(pipe_config); |
e29c22c0 | 9650 | return ERR_PTR(ret); |
ee7b9f93 | 9651 | } |
47f1c6c9 | 9652 | |
e2e1ed41 DV |
9653 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9654 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9655 | static void | |
9656 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9657 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9658 | { |
9659 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9660 | struct drm_device *dev = crtc->dev; |
9661 | struct intel_encoder *encoder; | |
9662 | struct intel_connector *connector; | |
9663 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9664 | |
e2e1ed41 | 9665 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9666 | |
e2e1ed41 DV |
9667 | /* Check which crtcs have changed outputs connected to them, these need |
9668 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9669 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9670 | * bit set at most. */ | |
9671 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9672 | base.head) { | |
9673 | if (connector->base.encoder == &connector->new_encoder->base) | |
9674 | continue; | |
79e53945 | 9675 | |
e2e1ed41 DV |
9676 | if (connector->base.encoder) { |
9677 | tmp_crtc = connector->base.encoder->crtc; | |
9678 | ||
9679 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9680 | } | |
9681 | ||
9682 | if (connector->new_encoder) | |
9683 | *prepare_pipes |= | |
9684 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9685 | } |
9686 | ||
e2e1ed41 DV |
9687 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9688 | base.head) { | |
9689 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9690 | continue; | |
9691 | ||
9692 | if (encoder->base.crtc) { | |
9693 | tmp_crtc = encoder->base.crtc; | |
9694 | ||
9695 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9696 | } | |
9697 | ||
9698 | if (encoder->new_crtc) | |
9699 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9700 | } |
9701 | ||
7668851f | 9702 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 9703 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9704 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9705 | continue; |
7e7d76c3 | 9706 | |
7668851f | 9707 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9708 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9709 | else |
9710 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9711 | } |
9712 | ||
e2e1ed41 DV |
9713 | |
9714 | /* set_mode is also used to update properties on life display pipes. */ | |
9715 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9716 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9717 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9718 | ||
b6c5164d DV |
9719 | /* |
9720 | * For simplicity do a full modeset on any pipe where the output routing | |
9721 | * changed. We could be more clever, but that would require us to be | |
9722 | * more careful with calling the relevant encoder->mode_set functions. | |
9723 | */ | |
e2e1ed41 DV |
9724 | if (*prepare_pipes) |
9725 | *modeset_pipes = *prepare_pipes; | |
9726 | ||
9727 | /* ... and mask these out. */ | |
9728 | *modeset_pipes &= ~(*disable_pipes); | |
9729 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9730 | |
9731 | /* | |
9732 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9733 | * obies this rule, but the modeset restore mode of | |
9734 | * intel_modeset_setup_hw_state does not. | |
9735 | */ | |
9736 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9737 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9738 | |
9739 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9740 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9741 | } |
79e53945 | 9742 | |
ea9d758d | 9743 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9744 | { |
ea9d758d | 9745 | struct drm_encoder *encoder; |
f6e5b160 | 9746 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9747 | |
ea9d758d DV |
9748 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9749 | if (encoder->crtc == crtc) | |
9750 | return true; | |
9751 | ||
9752 | return false; | |
9753 | } | |
9754 | ||
9755 | static void | |
9756 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9757 | { | |
9758 | struct intel_encoder *intel_encoder; | |
9759 | struct intel_crtc *intel_crtc; | |
9760 | struct drm_connector *connector; | |
9761 | ||
9762 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9763 | base.head) { | |
9764 | if (!intel_encoder->base.crtc) | |
9765 | continue; | |
9766 | ||
9767 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9768 | ||
9769 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9770 | intel_encoder->connectors_active = false; | |
9771 | } | |
9772 | ||
9773 | intel_modeset_commit_output_state(dev); | |
9774 | ||
7668851f | 9775 | /* Double check state. */ |
d3fcc808 | 9776 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9777 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9778 | WARN_ON(intel_crtc->new_config && |
9779 | intel_crtc->new_config != &intel_crtc->config); | |
9780 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9781 | } |
9782 | ||
9783 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9784 | if (!connector->encoder || !connector->encoder->crtc) | |
9785 | continue; | |
9786 | ||
9787 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9788 | ||
9789 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9790 | struct drm_property *dpms_property = |
9791 | dev->mode_config.dpms_property; | |
9792 | ||
ea9d758d | 9793 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9794 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9795 | dpms_property, |
9796 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9797 | |
9798 | intel_encoder = to_intel_encoder(connector->encoder); | |
9799 | intel_encoder->connectors_active = true; | |
9800 | } | |
9801 | } | |
9802 | ||
9803 | } | |
9804 | ||
3bd26263 | 9805 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9806 | { |
3bd26263 | 9807 | int diff; |
f1f644dc JB |
9808 | |
9809 | if (clock1 == clock2) | |
9810 | return true; | |
9811 | ||
9812 | if (!clock1 || !clock2) | |
9813 | return false; | |
9814 | ||
9815 | diff = abs(clock1 - clock2); | |
9816 | ||
9817 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9818 | return true; | |
9819 | ||
9820 | return false; | |
9821 | } | |
9822 | ||
25c5b266 DV |
9823 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9824 | list_for_each_entry((intel_crtc), \ | |
9825 | &(dev)->mode_config.crtc_list, \ | |
9826 | base.head) \ | |
0973f18f | 9827 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9828 | |
0e8ffe1b | 9829 | static bool |
2fa2fe9a DV |
9830 | intel_pipe_config_compare(struct drm_device *dev, |
9831 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9832 | struct intel_crtc_config *pipe_config) |
9833 | { | |
66e985c0 DV |
9834 | #define PIPE_CONF_CHECK_X(name) \ |
9835 | if (current_config->name != pipe_config->name) { \ | |
9836 | DRM_ERROR("mismatch in " #name " " \ | |
9837 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9838 | current_config->name, \ | |
9839 | pipe_config->name); \ | |
9840 | return false; \ | |
9841 | } | |
9842 | ||
08a24034 DV |
9843 | #define PIPE_CONF_CHECK_I(name) \ |
9844 | if (current_config->name != pipe_config->name) { \ | |
9845 | DRM_ERROR("mismatch in " #name " " \ | |
9846 | "(expected %i, found %i)\n", \ | |
9847 | current_config->name, \ | |
9848 | pipe_config->name); \ | |
9849 | return false; \ | |
88adfff1 DV |
9850 | } |
9851 | ||
1bd1bd80 DV |
9852 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9853 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9854 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9855 | "(expected %i, found %i)\n", \ |
9856 | current_config->name & (mask), \ | |
9857 | pipe_config->name & (mask)); \ | |
9858 | return false; \ | |
9859 | } | |
9860 | ||
5e550656 VS |
9861 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9862 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9863 | DRM_ERROR("mismatch in " #name " " \ | |
9864 | "(expected %i, found %i)\n", \ | |
9865 | current_config->name, \ | |
9866 | pipe_config->name); \ | |
9867 | return false; \ | |
9868 | } | |
9869 | ||
bb760063 DV |
9870 | #define PIPE_CONF_QUIRK(quirk) \ |
9871 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9872 | ||
eccb140b DV |
9873 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9874 | ||
08a24034 DV |
9875 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9876 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9877 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9878 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9879 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9880 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9881 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9882 | |
eb14cb74 VS |
9883 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9884 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9885 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9886 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9887 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9888 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9889 | ||
1bd1bd80 DV |
9890 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9891 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9892 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9893 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9894 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9895 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9896 | ||
9897 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9898 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9899 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9900 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9901 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9902 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9903 | ||
c93f54cf | 9904 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 9905 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
9906 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
9907 | IS_VALLEYVIEW(dev)) | |
9908 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 9909 | |
9ed109a7 DV |
9910 | PIPE_CONF_CHECK_I(has_audio); |
9911 | ||
1bd1bd80 DV |
9912 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9913 | DRM_MODE_FLAG_INTERLACE); | |
9914 | ||
bb760063 DV |
9915 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9916 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9917 | DRM_MODE_FLAG_PHSYNC); | |
9918 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9919 | DRM_MODE_FLAG_NHSYNC); | |
9920 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9921 | DRM_MODE_FLAG_PVSYNC); | |
9922 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9923 | DRM_MODE_FLAG_NVSYNC); | |
9924 | } | |
045ac3b5 | 9925 | |
37327abd VS |
9926 | PIPE_CONF_CHECK_I(pipe_src_w); |
9927 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9928 | |
9953599b DV |
9929 | /* |
9930 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
9931 | * screen. Since we don't yet re-compute the pipe config when moving | |
9932 | * just the lvds port away to another pipe the sw tracking won't match. | |
9933 | * | |
9934 | * Proper atomic modesets with recomputed global state will fix this. | |
9935 | * Until then just don't check gmch state for inherited modes. | |
9936 | */ | |
9937 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
9938 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
9939 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9940 | if (INTEL_INFO(dev)->gen < 4) | |
9941 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9942 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
9943 | } | |
9944 | ||
fd4daa9c CW |
9945 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9946 | if (current_config->pch_pfit.enabled) { | |
9947 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9948 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9949 | } | |
2fa2fe9a | 9950 | |
e59150dc JB |
9951 | /* BDW+ don't expose a synchronous way to read the state */ |
9952 | if (IS_HASWELL(dev)) | |
9953 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9954 | |
282740f7 VS |
9955 | PIPE_CONF_CHECK_I(double_wide); |
9956 | ||
c0d43d62 | 9957 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9958 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9959 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9960 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9961 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9962 | |
42571aef VS |
9963 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9964 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9965 | ||
a9a7e98a JB |
9966 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9967 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9968 | |
66e985c0 | 9969 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9970 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9971 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9972 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9973 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9974 | |
0e8ffe1b DV |
9975 | return true; |
9976 | } | |
9977 | ||
91d1b4bd DV |
9978 | static void |
9979 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9980 | { |
8af6cf88 DV |
9981 | struct intel_connector *connector; |
9982 | ||
9983 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9984 | base.head) { | |
9985 | /* This also checks the encoder/connector hw state with the | |
9986 | * ->get_hw_state callbacks. */ | |
9987 | intel_connector_check_state(connector); | |
9988 | ||
9989 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9990 | "connector's staged encoder doesn't match current encoder\n"); | |
9991 | } | |
91d1b4bd DV |
9992 | } |
9993 | ||
9994 | static void | |
9995 | check_encoder_state(struct drm_device *dev) | |
9996 | { | |
9997 | struct intel_encoder *encoder; | |
9998 | struct intel_connector *connector; | |
8af6cf88 DV |
9999 | |
10000 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10001 | base.head) { | |
10002 | bool enabled = false; | |
10003 | bool active = false; | |
10004 | enum pipe pipe, tracked_pipe; | |
10005 | ||
10006 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10007 | encoder->base.base.id, | |
10008 | drm_get_encoder_name(&encoder->base)); | |
10009 | ||
10010 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10011 | "encoder's stage crtc doesn't match current crtc\n"); | |
10012 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10013 | "encoder's active_connectors set, but no crtc\n"); | |
10014 | ||
10015 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10016 | base.head) { | |
10017 | if (connector->base.encoder != &encoder->base) | |
10018 | continue; | |
10019 | enabled = true; | |
10020 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10021 | active = true; | |
10022 | } | |
10023 | WARN(!!encoder->base.crtc != enabled, | |
10024 | "encoder's enabled state mismatch " | |
10025 | "(expected %i, found %i)\n", | |
10026 | !!encoder->base.crtc, enabled); | |
10027 | WARN(active && !encoder->base.crtc, | |
10028 | "active encoder with no crtc\n"); | |
10029 | ||
10030 | WARN(encoder->connectors_active != active, | |
10031 | "encoder's computed active state doesn't match tracked active state " | |
10032 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10033 | ||
10034 | active = encoder->get_hw_state(encoder, &pipe); | |
10035 | WARN(active != encoder->connectors_active, | |
10036 | "encoder's hw state doesn't match sw tracking " | |
10037 | "(expected %i, found %i)\n", | |
10038 | encoder->connectors_active, active); | |
10039 | ||
10040 | if (!encoder->base.crtc) | |
10041 | continue; | |
10042 | ||
10043 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10044 | WARN(active && pipe != tracked_pipe, | |
10045 | "active encoder's pipe doesn't match" | |
10046 | "(expected %i, found %i)\n", | |
10047 | tracked_pipe, pipe); | |
10048 | ||
10049 | } | |
91d1b4bd DV |
10050 | } |
10051 | ||
10052 | static void | |
10053 | check_crtc_state(struct drm_device *dev) | |
10054 | { | |
fbee40df | 10055 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10056 | struct intel_crtc *crtc; |
10057 | struct intel_encoder *encoder; | |
10058 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10059 | |
d3fcc808 | 10060 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10061 | bool enabled = false; |
10062 | bool active = false; | |
10063 | ||
045ac3b5 JB |
10064 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10065 | ||
8af6cf88 DV |
10066 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10067 | crtc->base.base.id); | |
10068 | ||
10069 | WARN(crtc->active && !crtc->base.enabled, | |
10070 | "active crtc, but not enabled in sw tracking\n"); | |
10071 | ||
10072 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10073 | base.head) { | |
10074 | if (encoder->base.crtc != &crtc->base) | |
10075 | continue; | |
10076 | enabled = true; | |
10077 | if (encoder->connectors_active) | |
10078 | active = true; | |
10079 | } | |
6c49f241 | 10080 | |
8af6cf88 DV |
10081 | WARN(active != crtc->active, |
10082 | "crtc's computed active state doesn't match tracked active state " | |
10083 | "(expected %i, found %i)\n", active, crtc->active); | |
10084 | WARN(enabled != crtc->base.enabled, | |
10085 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10086 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10087 | ||
0e8ffe1b DV |
10088 | active = dev_priv->display.get_pipe_config(crtc, |
10089 | &pipe_config); | |
d62cf62a DV |
10090 | |
10091 | /* hw state is inconsistent with the pipe A quirk */ | |
10092 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10093 | active = crtc->active; | |
10094 | ||
6c49f241 DV |
10095 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10096 | base.head) { | |
3eaba51c | 10097 | enum pipe pipe; |
6c49f241 DV |
10098 | if (encoder->base.crtc != &crtc->base) |
10099 | continue; | |
1d37b689 | 10100 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10101 | encoder->get_config(encoder, &pipe_config); |
10102 | } | |
10103 | ||
0e8ffe1b DV |
10104 | WARN(crtc->active != active, |
10105 | "crtc active state doesn't match with hw state " | |
10106 | "(expected %i, found %i)\n", crtc->active, active); | |
10107 | ||
c0b03411 DV |
10108 | if (active && |
10109 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10110 | WARN(1, "pipe state doesn't match!\n"); | |
10111 | intel_dump_pipe_config(crtc, &pipe_config, | |
10112 | "[hw state]"); | |
10113 | intel_dump_pipe_config(crtc, &crtc->config, | |
10114 | "[sw state]"); | |
10115 | } | |
8af6cf88 DV |
10116 | } |
10117 | } | |
10118 | ||
91d1b4bd DV |
10119 | static void |
10120 | check_shared_dpll_state(struct drm_device *dev) | |
10121 | { | |
fbee40df | 10122 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10123 | struct intel_crtc *crtc; |
10124 | struct intel_dpll_hw_state dpll_hw_state; | |
10125 | int i; | |
5358901f DV |
10126 | |
10127 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10128 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10129 | int enabled_crtcs = 0, active_crtcs = 0; | |
10130 | bool active; | |
10131 | ||
10132 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10133 | ||
10134 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10135 | ||
10136 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10137 | ||
10138 | WARN(pll->active > pll->refcount, | |
10139 | "more active pll users than references: %i vs %i\n", | |
10140 | pll->active, pll->refcount); | |
10141 | WARN(pll->active && !pll->on, | |
10142 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10143 | WARN(pll->on && !pll->active, |
10144 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10145 | WARN(pll->on != active, |
10146 | "pll on state mismatch (expected %i, found %i)\n", | |
10147 | pll->on, active); | |
10148 | ||
d3fcc808 | 10149 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10150 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10151 | enabled_crtcs++; | |
10152 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10153 | active_crtcs++; | |
10154 | } | |
10155 | WARN(pll->active != active_crtcs, | |
10156 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10157 | pll->active, active_crtcs); | |
10158 | WARN(pll->refcount != enabled_crtcs, | |
10159 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10160 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10161 | |
10162 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10163 | sizeof(dpll_hw_state)), | |
10164 | "pll hw state mismatch\n"); | |
5358901f | 10165 | } |
8af6cf88 DV |
10166 | } |
10167 | ||
91d1b4bd DV |
10168 | void |
10169 | intel_modeset_check_state(struct drm_device *dev) | |
10170 | { | |
10171 | check_connector_state(dev); | |
10172 | check_encoder_state(dev); | |
10173 | check_crtc_state(dev); | |
10174 | check_shared_dpll_state(dev); | |
10175 | } | |
10176 | ||
18442d08 VS |
10177 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10178 | int dotclock) | |
10179 | { | |
10180 | /* | |
10181 | * FDI already provided one idea for the dotclock. | |
10182 | * Yell if the encoder disagrees. | |
10183 | */ | |
241bfc38 | 10184 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10185 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10186 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10187 | } |
10188 | ||
f30da187 DV |
10189 | static int __intel_set_mode(struct drm_crtc *crtc, |
10190 | struct drm_display_mode *mode, | |
10191 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10192 | { |
10193 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10194 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10195 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10196 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10197 | struct intel_crtc *intel_crtc; |
10198 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10199 | int ret = 0; |
a6778b3c | 10200 | |
4b4b9238 | 10201 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10202 | if (!saved_mode) |
10203 | return -ENOMEM; | |
a6778b3c | 10204 | |
e2e1ed41 | 10205 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10206 | &prepare_pipes, &disable_pipes); |
10207 | ||
3ac18232 | 10208 | *saved_mode = crtc->mode; |
a6778b3c | 10209 | |
25c5b266 DV |
10210 | /* Hack: Because we don't (yet) support global modeset on multiple |
10211 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10212 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10213 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10214 | * changing their mode at the same time. */ | |
25c5b266 | 10215 | if (modeset_pipes) { |
4e53c2e0 | 10216 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10217 | if (IS_ERR(pipe_config)) { |
10218 | ret = PTR_ERR(pipe_config); | |
10219 | pipe_config = NULL; | |
10220 | ||
3ac18232 | 10221 | goto out; |
25c5b266 | 10222 | } |
c0b03411 DV |
10223 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10224 | "[modeset]"); | |
50741abc | 10225 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10226 | } |
a6778b3c | 10227 | |
30a970c6 JB |
10228 | /* |
10229 | * See if the config requires any additional preparation, e.g. | |
10230 | * to adjust global state with pipes off. We need to do this | |
10231 | * here so we can get the modeset_pipe updated config for the new | |
10232 | * mode set on this crtc. For other crtcs we need to use the | |
10233 | * adjusted_mode bits in the crtc directly. | |
10234 | */ | |
c164f833 | 10235 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10236 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10237 | |
c164f833 VS |
10238 | /* may have added more to prepare_pipes than we should */ |
10239 | prepare_pipes &= ~disable_pipes; | |
10240 | } | |
10241 | ||
460da916 DV |
10242 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10243 | intel_crtc_disable(&intel_crtc->base); | |
10244 | ||
ea9d758d DV |
10245 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10246 | if (intel_crtc->base.enabled) | |
10247 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10248 | } | |
a6778b3c | 10249 | |
6c4c86f5 DV |
10250 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10251 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10252 | */ |
b8cecdf5 | 10253 | if (modeset_pipes) { |
25c5b266 | 10254 | crtc->mode = *mode; |
b8cecdf5 DV |
10255 | /* mode_set/enable/disable functions rely on a correct pipe |
10256 | * config. */ | |
10257 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10258 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10259 | |
10260 | /* | |
10261 | * Calculate and store various constants which | |
10262 | * are later needed by vblank and swap-completion | |
10263 | * timestamping. They are derived from true hwmode. | |
10264 | */ | |
10265 | drm_calc_timestamping_constants(crtc, | |
10266 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10267 | } |
7758a113 | 10268 | |
ea9d758d DV |
10269 | /* Only after disabling all output pipelines that will be changed can we |
10270 | * update the the output configuration. */ | |
10271 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10272 | |
47fab737 DV |
10273 | if (dev_priv->display.modeset_global_resources) |
10274 | dev_priv->display.modeset_global_resources(dev); | |
10275 | ||
a6778b3c DV |
10276 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10277 | * on the DPLL. | |
f6e5b160 | 10278 | */ |
25c5b266 | 10279 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4c10794f DV |
10280 | struct drm_framebuffer *old_fb; |
10281 | ||
10282 | mutex_lock(&dev->struct_mutex); | |
10283 | ret = intel_pin_and_fence_fb_obj(dev, | |
10284 | to_intel_framebuffer(fb)->obj, | |
10285 | NULL); | |
10286 | if (ret != 0) { | |
10287 | DRM_ERROR("pin & fence failed\n"); | |
10288 | mutex_unlock(&dev->struct_mutex); | |
10289 | goto done; | |
10290 | } | |
10291 | old_fb = crtc->primary->fb; | |
10292 | if (old_fb) | |
10293 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); | |
10294 | mutex_unlock(&dev->struct_mutex); | |
10295 | ||
10296 | crtc->primary->fb = fb; | |
10297 | crtc->x = x; | |
10298 | crtc->y = y; | |
10299 | ||
4271b753 DV |
10300 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10301 | x, y, fb); | |
c0c36b94 CW |
10302 | if (ret) |
10303 | goto done; | |
a6778b3c DV |
10304 | } |
10305 | ||
10306 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
10307 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
10308 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 10309 | |
a6778b3c DV |
10310 | /* FIXME: add subpixel order */ |
10311 | done: | |
4b4b9238 | 10312 | if (ret && crtc->enabled) |
3ac18232 | 10313 | crtc->mode = *saved_mode; |
a6778b3c | 10314 | |
3ac18232 | 10315 | out: |
b8cecdf5 | 10316 | kfree(pipe_config); |
3ac18232 | 10317 | kfree(saved_mode); |
a6778b3c | 10318 | return ret; |
f6e5b160 CW |
10319 | } |
10320 | ||
e7457a9a DL |
10321 | static int intel_set_mode(struct drm_crtc *crtc, |
10322 | struct drm_display_mode *mode, | |
10323 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10324 | { |
10325 | int ret; | |
10326 | ||
10327 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10328 | ||
10329 | if (ret == 0) | |
10330 | intel_modeset_check_state(crtc->dev); | |
10331 | ||
10332 | return ret; | |
10333 | } | |
10334 | ||
c0c36b94 CW |
10335 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10336 | { | |
f4510a27 | 10337 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10338 | } |
10339 | ||
25c5b266 DV |
10340 | #undef for_each_intel_crtc_masked |
10341 | ||
d9e55608 DV |
10342 | static void intel_set_config_free(struct intel_set_config *config) |
10343 | { | |
10344 | if (!config) | |
10345 | return; | |
10346 | ||
1aa4b628 DV |
10347 | kfree(config->save_connector_encoders); |
10348 | kfree(config->save_encoder_crtcs); | |
7668851f | 10349 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10350 | kfree(config); |
10351 | } | |
10352 | ||
85f9eb71 DV |
10353 | static int intel_set_config_save_state(struct drm_device *dev, |
10354 | struct intel_set_config *config) | |
10355 | { | |
7668851f | 10356 | struct drm_crtc *crtc; |
85f9eb71 DV |
10357 | struct drm_encoder *encoder; |
10358 | struct drm_connector *connector; | |
10359 | int count; | |
10360 | ||
7668851f VS |
10361 | config->save_crtc_enabled = |
10362 | kcalloc(dev->mode_config.num_crtc, | |
10363 | sizeof(bool), GFP_KERNEL); | |
10364 | if (!config->save_crtc_enabled) | |
10365 | return -ENOMEM; | |
10366 | ||
1aa4b628 DV |
10367 | config->save_encoder_crtcs = |
10368 | kcalloc(dev->mode_config.num_encoder, | |
10369 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10370 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10371 | return -ENOMEM; |
10372 | ||
1aa4b628 DV |
10373 | config->save_connector_encoders = |
10374 | kcalloc(dev->mode_config.num_connector, | |
10375 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10376 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10377 | return -ENOMEM; |
10378 | ||
10379 | /* Copy data. Note that driver private data is not affected. | |
10380 | * Should anything bad happen only the expected state is | |
10381 | * restored, not the drivers personal bookkeeping. | |
10382 | */ | |
7668851f | 10383 | count = 0; |
70e1e0ec | 10384 | for_each_crtc(dev, crtc) { |
7668851f VS |
10385 | config->save_crtc_enabled[count++] = crtc->enabled; |
10386 | } | |
10387 | ||
85f9eb71 DV |
10388 | count = 0; |
10389 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10390 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10391 | } |
10392 | ||
10393 | count = 0; | |
10394 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10395 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10396 | } |
10397 | ||
10398 | return 0; | |
10399 | } | |
10400 | ||
10401 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10402 | struct intel_set_config *config) | |
10403 | { | |
7668851f | 10404 | struct intel_crtc *crtc; |
9a935856 DV |
10405 | struct intel_encoder *encoder; |
10406 | struct intel_connector *connector; | |
85f9eb71 DV |
10407 | int count; |
10408 | ||
7668851f | 10409 | count = 0; |
d3fcc808 | 10410 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10411 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10412 | |
10413 | if (crtc->new_enabled) | |
10414 | crtc->new_config = &crtc->config; | |
10415 | else | |
10416 | crtc->new_config = NULL; | |
7668851f VS |
10417 | } |
10418 | ||
85f9eb71 | 10419 | count = 0; |
9a935856 DV |
10420 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10421 | encoder->new_crtc = | |
10422 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10423 | } |
10424 | ||
10425 | count = 0; | |
9a935856 DV |
10426 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10427 | connector->new_encoder = | |
10428 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10429 | } |
10430 | } | |
10431 | ||
e3de42b6 | 10432 | static bool |
2e57f47d | 10433 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10434 | { |
10435 | int i; | |
10436 | ||
2e57f47d CW |
10437 | if (set->num_connectors == 0) |
10438 | return false; | |
10439 | ||
10440 | if (WARN_ON(set->connectors == NULL)) | |
10441 | return false; | |
10442 | ||
10443 | for (i = 0; i < set->num_connectors; i++) | |
10444 | if (set->connectors[i]->encoder && | |
10445 | set->connectors[i]->encoder->crtc == set->crtc && | |
10446 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10447 | return true; |
10448 | ||
10449 | return false; | |
10450 | } | |
10451 | ||
5e2b584e DV |
10452 | static void |
10453 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10454 | struct intel_set_config *config) | |
10455 | { | |
10456 | ||
10457 | /* We should be able to check here if the fb has the same properties | |
10458 | * and then just flip_or_move it */ | |
2e57f47d CW |
10459 | if (is_crtc_connector_off(set)) { |
10460 | config->mode_changed = true; | |
f4510a27 | 10461 | } else if (set->crtc->primary->fb != set->fb) { |
5e2b584e | 10462 | /* If we have no fb then treat it as a full mode set */ |
f4510a27 | 10463 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10464 | struct intel_crtc *intel_crtc = |
10465 | to_intel_crtc(set->crtc); | |
10466 | ||
d330a953 | 10467 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
10468 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10469 | config->fb_changed = true; | |
10470 | } else { | |
10471 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10472 | config->mode_changed = true; | |
10473 | } | |
5e2b584e DV |
10474 | } else if (set->fb == NULL) { |
10475 | config->mode_changed = true; | |
72f4901e | 10476 | } else if (set->fb->pixel_format != |
f4510a27 | 10477 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10478 | config->mode_changed = true; |
e3de42b6 | 10479 | } else { |
5e2b584e | 10480 | config->fb_changed = true; |
e3de42b6 | 10481 | } |
5e2b584e DV |
10482 | } |
10483 | ||
835c5873 | 10484 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10485 | config->fb_changed = true; |
10486 | ||
10487 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10488 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10489 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10490 | drm_mode_debug_printmodeline(set->mode); | |
10491 | config->mode_changed = true; | |
10492 | } | |
a1d95703 CW |
10493 | |
10494 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10495 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10496 | } |
10497 | ||
2e431051 | 10498 | static int |
9a935856 DV |
10499 | intel_modeset_stage_output_state(struct drm_device *dev, |
10500 | struct drm_mode_set *set, | |
10501 | struct intel_set_config *config) | |
50f56119 | 10502 | { |
9a935856 DV |
10503 | struct intel_connector *connector; |
10504 | struct intel_encoder *encoder; | |
7668851f | 10505 | struct intel_crtc *crtc; |
f3f08572 | 10506 | int ro; |
50f56119 | 10507 | |
9abdda74 | 10508 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10509 | * of connectors. For paranoia, double-check this. */ |
10510 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10511 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
10512 | ||
9a935856 DV |
10513 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10514 | base.head) { | |
10515 | /* Otherwise traverse passed in connector list and get encoders | |
10516 | * for them. */ | |
50f56119 | 10517 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
10518 | if (set->connectors[ro] == &connector->base) { |
10519 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
10520 | break; |
10521 | } | |
10522 | } | |
10523 | ||
9a935856 DV |
10524 | /* If we disable the crtc, disable all its connectors. Also, if |
10525 | * the connector is on the changing crtc but not on the new | |
10526 | * connector list, disable it. */ | |
10527 | if ((!set->fb || ro == set->num_connectors) && | |
10528 | connector->base.encoder && | |
10529 | connector->base.encoder->crtc == set->crtc) { | |
10530 | connector->new_encoder = NULL; | |
10531 | ||
10532 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
10533 | connector->base.base.id, | |
10534 | drm_get_connector_name(&connector->base)); | |
10535 | } | |
10536 | ||
10537 | ||
10538 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 10539 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 10540 | config->mode_changed = true; |
50f56119 DV |
10541 | } |
10542 | } | |
9a935856 | 10543 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 10544 | |
9a935856 | 10545 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
10546 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10547 | base.head) { | |
7668851f VS |
10548 | struct drm_crtc *new_crtc; |
10549 | ||
9a935856 | 10550 | if (!connector->new_encoder) |
50f56119 DV |
10551 | continue; |
10552 | ||
9a935856 | 10553 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10554 | |
10555 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10556 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10557 | new_crtc = set->crtc; |
10558 | } | |
10559 | ||
10560 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10561 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10562 | new_crtc)) { | |
5e2b584e | 10563 | return -EINVAL; |
50f56119 | 10564 | } |
9a935856 DV |
10565 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10566 | ||
10567 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10568 | connector->base.base.id, | |
10569 | drm_get_connector_name(&connector->base), | |
10570 | new_crtc->base.id); | |
10571 | } | |
10572 | ||
10573 | /* Check for any encoders that needs to be disabled. */ | |
10574 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10575 | base.head) { | |
5a65f358 | 10576 | int num_connectors = 0; |
9a935856 DV |
10577 | list_for_each_entry(connector, |
10578 | &dev->mode_config.connector_list, | |
10579 | base.head) { | |
10580 | if (connector->new_encoder == encoder) { | |
10581 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10582 | num_connectors++; |
9a935856 DV |
10583 | } |
10584 | } | |
5a65f358 PZ |
10585 | |
10586 | if (num_connectors == 0) | |
10587 | encoder->new_crtc = NULL; | |
10588 | else if (num_connectors > 1) | |
10589 | return -EINVAL; | |
10590 | ||
9a935856 DV |
10591 | /* Only now check for crtc changes so we don't miss encoders |
10592 | * that will be disabled. */ | |
10593 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10594 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10595 | config->mode_changed = true; |
50f56119 DV |
10596 | } |
10597 | } | |
9a935856 | 10598 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10599 | |
d3fcc808 | 10600 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
10601 | crtc->new_enabled = false; |
10602 | ||
10603 | list_for_each_entry(encoder, | |
10604 | &dev->mode_config.encoder_list, | |
10605 | base.head) { | |
10606 | if (encoder->new_crtc == crtc) { | |
10607 | crtc->new_enabled = true; | |
10608 | break; | |
10609 | } | |
10610 | } | |
10611 | ||
10612 | if (crtc->new_enabled != crtc->base.enabled) { | |
10613 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10614 | crtc->new_enabled ? "en" : "dis"); | |
10615 | config->mode_changed = true; | |
10616 | } | |
7bd0a8e7 VS |
10617 | |
10618 | if (crtc->new_enabled) | |
10619 | crtc->new_config = &crtc->config; | |
10620 | else | |
10621 | crtc->new_config = NULL; | |
7668851f VS |
10622 | } |
10623 | ||
2e431051 DV |
10624 | return 0; |
10625 | } | |
10626 | ||
7d00a1f5 VS |
10627 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10628 | { | |
10629 | struct drm_device *dev = crtc->base.dev; | |
10630 | struct intel_encoder *encoder; | |
10631 | struct intel_connector *connector; | |
10632 | ||
10633 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10634 | pipe_name(crtc->pipe)); | |
10635 | ||
10636 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10637 | if (connector->new_encoder && | |
10638 | connector->new_encoder->new_crtc == crtc) | |
10639 | connector->new_encoder = NULL; | |
10640 | } | |
10641 | ||
10642 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10643 | if (encoder->new_crtc == crtc) | |
10644 | encoder->new_crtc = NULL; | |
10645 | } | |
10646 | ||
10647 | crtc->new_enabled = false; | |
7bd0a8e7 | 10648 | crtc->new_config = NULL; |
7d00a1f5 VS |
10649 | } |
10650 | ||
2e431051 DV |
10651 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10652 | { | |
10653 | struct drm_device *dev; | |
2e431051 DV |
10654 | struct drm_mode_set save_set; |
10655 | struct intel_set_config *config; | |
10656 | int ret; | |
2e431051 | 10657 | |
8d3e375e DV |
10658 | BUG_ON(!set); |
10659 | BUG_ON(!set->crtc); | |
10660 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10661 | |
7e53f3a4 DV |
10662 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10663 | BUG_ON(!set->mode && set->fb); | |
10664 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10665 | |
2e431051 DV |
10666 | if (set->fb) { |
10667 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10668 | set->crtc->base.id, set->fb->base.id, | |
10669 | (int)set->num_connectors, set->x, set->y); | |
10670 | } else { | |
10671 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10672 | } |
10673 | ||
10674 | dev = set->crtc->dev; | |
10675 | ||
10676 | ret = -ENOMEM; | |
10677 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10678 | if (!config) | |
10679 | goto out_config; | |
10680 | ||
10681 | ret = intel_set_config_save_state(dev, config); | |
10682 | if (ret) | |
10683 | goto out_config; | |
10684 | ||
10685 | save_set.crtc = set->crtc; | |
10686 | save_set.mode = &set->crtc->mode; | |
10687 | save_set.x = set->crtc->x; | |
10688 | save_set.y = set->crtc->y; | |
f4510a27 | 10689 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
10690 | |
10691 | /* Compute whether we need a full modeset, only an fb base update or no | |
10692 | * change at all. In the future we might also check whether only the | |
10693 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10694 | * such cases. */ | |
10695 | intel_set_config_compute_mode_changes(set, config); | |
10696 | ||
9a935856 | 10697 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10698 | if (ret) |
10699 | goto fail; | |
10700 | ||
5e2b584e | 10701 | if (config->mode_changed) { |
c0c36b94 CW |
10702 | ret = intel_set_mode(set->crtc, set->mode, |
10703 | set->x, set->y, set->fb); | |
5e2b584e | 10704 | } else if (config->fb_changed) { |
4878cae2 VS |
10705 | intel_crtc_wait_for_pending_flips(set->crtc); |
10706 | ||
4f660f49 | 10707 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10708 | set->x, set->y, set->fb); |
7ca51a3a JB |
10709 | /* |
10710 | * In the fastboot case this may be our only check of the | |
10711 | * state after boot. It would be better to only do it on | |
10712 | * the first update, but we don't have a nice way of doing that | |
10713 | * (and really, set_config isn't used much for high freq page | |
10714 | * flipping, so increasing its cost here shouldn't be a big | |
10715 | * deal). | |
10716 | */ | |
d330a953 | 10717 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10718 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10719 | } |
10720 | ||
2d05eae1 | 10721 | if (ret) { |
bf67dfeb DV |
10722 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10723 | set->crtc->base.id, ret); | |
50f56119 | 10724 | fail: |
2d05eae1 | 10725 | intel_set_config_restore_state(dev, config); |
50f56119 | 10726 | |
7d00a1f5 VS |
10727 | /* |
10728 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10729 | * force the pipe off to avoid oopsing in the modeset code | |
10730 | * due to fb==NULL. This should only happen during boot since | |
10731 | * we don't yet reconstruct the FB from the hardware state. | |
10732 | */ | |
10733 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10734 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10735 | ||
2d05eae1 CW |
10736 | /* Try to restore the config */ |
10737 | if (config->mode_changed && | |
10738 | intel_set_mode(save_set.crtc, save_set.mode, | |
10739 | save_set.x, save_set.y, save_set.fb)) | |
10740 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10741 | } | |
50f56119 | 10742 | |
d9e55608 DV |
10743 | out_config: |
10744 | intel_set_config_free(config); | |
50f56119 DV |
10745 | return ret; |
10746 | } | |
f6e5b160 CW |
10747 | |
10748 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10749 | .cursor_set = intel_crtc_cursor_set, |
10750 | .cursor_move = intel_crtc_cursor_move, | |
10751 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10752 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10753 | .destroy = intel_crtc_destroy, |
10754 | .page_flip = intel_crtc_page_flip, | |
10755 | }; | |
10756 | ||
79f689aa PZ |
10757 | static void intel_cpu_pll_init(struct drm_device *dev) |
10758 | { | |
affa9354 | 10759 | if (HAS_DDI(dev)) |
79f689aa PZ |
10760 | intel_ddi_pll_init(dev); |
10761 | } | |
10762 | ||
5358901f DV |
10763 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10764 | struct intel_shared_dpll *pll, | |
10765 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10766 | { |
5358901f | 10767 | uint32_t val; |
ee7b9f93 | 10768 | |
5358901f | 10769 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10770 | hw_state->dpll = val; |
10771 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10772 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10773 | |
10774 | return val & DPLL_VCO_ENABLE; | |
10775 | } | |
10776 | ||
15bdd4cf DV |
10777 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10778 | struct intel_shared_dpll *pll) | |
10779 | { | |
10780 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10781 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10782 | } | |
10783 | ||
e7b903d2 DV |
10784 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10785 | struct intel_shared_dpll *pll) | |
10786 | { | |
e7b903d2 | 10787 | /* PCH refclock must be enabled first */ |
89eff4be | 10788 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10789 | |
15bdd4cf DV |
10790 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10791 | ||
10792 | /* Wait for the clocks to stabilize. */ | |
10793 | POSTING_READ(PCH_DPLL(pll->id)); | |
10794 | udelay(150); | |
10795 | ||
10796 | /* The pixel multiplier can only be updated once the | |
10797 | * DPLL is enabled and the clocks are stable. | |
10798 | * | |
10799 | * So write it again. | |
10800 | */ | |
10801 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10802 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10803 | udelay(200); |
10804 | } | |
10805 | ||
10806 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10807 | struct intel_shared_dpll *pll) | |
10808 | { | |
10809 | struct drm_device *dev = dev_priv->dev; | |
10810 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10811 | |
10812 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 10813 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
10814 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
10815 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10816 | } |
10817 | ||
15bdd4cf DV |
10818 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10819 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10820 | udelay(200); |
10821 | } | |
10822 | ||
46edb027 DV |
10823 | static char *ibx_pch_dpll_names[] = { |
10824 | "PCH DPLL A", | |
10825 | "PCH DPLL B", | |
10826 | }; | |
10827 | ||
7c74ade1 | 10828 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10829 | { |
e7b903d2 | 10830 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10831 | int i; |
10832 | ||
7c74ade1 | 10833 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10834 | |
e72f9fbf | 10835 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10836 | dev_priv->shared_dplls[i].id = i; |
10837 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10838 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10839 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10840 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10841 | dev_priv->shared_dplls[i].get_hw_state = |
10842 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10843 | } |
10844 | } | |
10845 | ||
7c74ade1 DV |
10846 | static void intel_shared_dpll_init(struct drm_device *dev) |
10847 | { | |
e7b903d2 | 10848 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10849 | |
10850 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10851 | ibx_pch_dpll_init(dev); | |
10852 | else | |
10853 | dev_priv->num_shared_dpll = 0; | |
10854 | ||
10855 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10856 | } |
10857 | ||
b358d0a6 | 10858 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10859 | { |
fbee40df | 10860 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
10861 | struct intel_crtc *intel_crtc; |
10862 | int i; | |
10863 | ||
955382f3 | 10864 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10865 | if (intel_crtc == NULL) |
10866 | return; | |
10867 | ||
10868 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10869 | ||
10870 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10871 | for (i = 0; i < 256; i++) { |
10872 | intel_crtc->lut_r[i] = i; | |
10873 | intel_crtc->lut_g[i] = i; | |
10874 | intel_crtc->lut_b[i] = i; | |
10875 | } | |
10876 | ||
1f1c2e24 VS |
10877 | /* |
10878 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10879 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10880 | */ | |
80824003 JB |
10881 | intel_crtc->pipe = pipe; |
10882 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10883 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10884 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10885 | intel_crtc->plane = !pipe; |
80824003 JB |
10886 | } |
10887 | ||
8d7849db VS |
10888 | init_waitqueue_head(&intel_crtc->vbl_wait); |
10889 | ||
22fd0fab JB |
10890 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10891 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10892 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10893 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10894 | ||
79e53945 | 10895 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10896 | } |
10897 | ||
752aa88a JB |
10898 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10899 | { | |
10900 | struct drm_encoder *encoder = connector->base.encoder; | |
10901 | ||
10902 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10903 | ||
10904 | if (!encoder) | |
10905 | return INVALID_PIPE; | |
10906 | ||
10907 | return to_intel_crtc(encoder->crtc)->pipe; | |
10908 | } | |
10909 | ||
08d7b3d1 | 10910 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10911 | struct drm_file *file) |
08d7b3d1 | 10912 | { |
08d7b3d1 | 10913 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10914 | struct drm_mode_object *drmmode_obj; |
10915 | struct intel_crtc *crtc; | |
08d7b3d1 | 10916 | |
1cff8f6b DV |
10917 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10918 | return -ENODEV; | |
08d7b3d1 | 10919 | |
c05422d5 DV |
10920 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10921 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10922 | |
c05422d5 | 10923 | if (!drmmode_obj) { |
08d7b3d1 | 10924 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10925 | return -ENOENT; |
08d7b3d1 CW |
10926 | } |
10927 | ||
c05422d5 DV |
10928 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10929 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10930 | |
c05422d5 | 10931 | return 0; |
08d7b3d1 CW |
10932 | } |
10933 | ||
66a9278e | 10934 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10935 | { |
66a9278e DV |
10936 | struct drm_device *dev = encoder->base.dev; |
10937 | struct intel_encoder *source_encoder; | |
79e53945 | 10938 | int index_mask = 0; |
79e53945 JB |
10939 | int entry = 0; |
10940 | ||
66a9278e DV |
10941 | list_for_each_entry(source_encoder, |
10942 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 10943 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
10944 | index_mask |= (1 << entry); |
10945 | ||
79e53945 JB |
10946 | entry++; |
10947 | } | |
4ef69c7a | 10948 | |
79e53945 JB |
10949 | return index_mask; |
10950 | } | |
10951 | ||
4d302442 CW |
10952 | static bool has_edp_a(struct drm_device *dev) |
10953 | { | |
10954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10955 | ||
10956 | if (!IS_MOBILE(dev)) | |
10957 | return false; | |
10958 | ||
10959 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10960 | return false; | |
10961 | ||
e3589908 | 10962 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10963 | return false; |
10964 | ||
10965 | return true; | |
10966 | } | |
10967 | ||
ba0fbca4 DL |
10968 | const char *intel_output_name(int output) |
10969 | { | |
10970 | static const char *names[] = { | |
10971 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10972 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10973 | [INTEL_OUTPUT_DVO] = "DVO", | |
10974 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10975 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10976 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10977 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10978 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10979 | [INTEL_OUTPUT_EDP] = "eDP", | |
10980 | [INTEL_OUTPUT_DSI] = "DSI", | |
10981 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10982 | }; | |
10983 | ||
10984 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10985 | return "Invalid"; | |
10986 | ||
10987 | return names[output]; | |
10988 | } | |
10989 | ||
79e53945 JB |
10990 | static void intel_setup_outputs(struct drm_device *dev) |
10991 | { | |
725e30ad | 10992 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10993 | struct intel_encoder *encoder; |
cb0953d7 | 10994 | bool dpd_is_edp = false; |
79e53945 | 10995 | |
c9093354 | 10996 | intel_lvds_init(dev); |
79e53945 | 10997 | |
7895a81d | 10998 | if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev)) |
79935fca | 10999 | intel_crt_init(dev); |
cb0953d7 | 11000 | |
affa9354 | 11001 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
11002 | int found; |
11003 | ||
11004 | /* Haswell uses DDI functions to detect digital outputs */ | |
11005 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
11006 | /* DDI A only supports eDP */ | |
11007 | if (found) | |
11008 | intel_ddi_init(dev, PORT_A); | |
11009 | ||
11010 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
11011 | * register */ | |
11012 | found = I915_READ(SFUSE_STRAP); | |
11013 | ||
11014 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
11015 | intel_ddi_init(dev, PORT_B); | |
11016 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
11017 | intel_ddi_init(dev, PORT_C); | |
11018 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
11019 | intel_ddi_init(dev, PORT_D); | |
11020 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 11021 | int found; |
5d8a7752 | 11022 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
11023 | |
11024 | if (has_edp_a(dev)) | |
11025 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 11026 | |
dc0fa718 | 11027 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 11028 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 11029 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 11030 | if (!found) |
e2debe91 | 11031 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 11032 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 11033 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
11034 | } |
11035 | ||
dc0fa718 | 11036 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 11037 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 11038 | |
dc0fa718 | 11039 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 11040 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 11041 | |
5eb08b69 | 11042 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 11043 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 11044 | |
270b3042 | 11045 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 11046 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 11047 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
11048 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11049 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
11050 | PORT_B); | |
11051 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
11052 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
11053 | } | |
11054 | ||
6f6005a5 JB |
11055 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11056 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
11057 | PORT_C); | |
11058 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 11059 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 11060 | } |
19c03924 | 11061 | |
9418c1f1 VS |
11062 | if (IS_CHERRYVIEW(dev)) { |
11063 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
11064 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
11065 | PORT_D); | |
11066 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
11067 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
11068 | } | |
11069 | } | |
11070 | ||
3cfca973 | 11071 | intel_dsi_init(dev); |
103a196f | 11072 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 11073 | bool found = false; |
7d57382e | 11074 | |
e2debe91 | 11075 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11076 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 11077 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
11078 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11079 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 11080 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 11081 | } |
27185ae1 | 11082 | |
e7281eab | 11083 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11084 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 11085 | } |
13520b05 KH |
11086 | |
11087 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 11088 | |
e2debe91 | 11089 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11090 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11091 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11092 | } |
27185ae1 | 11093 | |
e2debe91 | 11094 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11095 | |
b01f2c3a JB |
11096 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11097 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11098 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11099 | } |
e7281eab | 11100 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11101 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11102 | } |
27185ae1 | 11103 | |
b01f2c3a | 11104 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11105 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11106 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11107 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11108 | intel_dvo_init(dev); |
11109 | ||
103a196f | 11110 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11111 | intel_tv_init(dev); |
11112 | ||
4ef69c7a CW |
11113 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11114 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11115 | encoder->base.possible_clones = | |
66a9278e | 11116 | intel_encoder_clones(encoder); |
79e53945 | 11117 | } |
47356eb6 | 11118 | |
dde86e2d | 11119 | intel_init_pch_refclk(dev); |
270b3042 DV |
11120 | |
11121 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11122 | } |
11123 | ||
11124 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11125 | { | |
11126 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 11127 | |
ef2d633e DV |
11128 | drm_framebuffer_cleanup(fb); |
11129 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
11130 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
11131 | kfree(intel_fb); |
11132 | } | |
11133 | ||
11134 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11135 | struct drm_file *file, |
79e53945 JB |
11136 | unsigned int *handle) |
11137 | { | |
11138 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11139 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11140 | |
05394f39 | 11141 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11142 | } |
11143 | ||
11144 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11145 | .destroy = intel_user_framebuffer_destroy, | |
11146 | .create_handle = intel_user_framebuffer_create_handle, | |
11147 | }; | |
11148 | ||
b5ea642a DV |
11149 | static int intel_framebuffer_init(struct drm_device *dev, |
11150 | struct intel_framebuffer *intel_fb, | |
11151 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11152 | struct drm_i915_gem_object *obj) | |
79e53945 | 11153 | { |
a57ce0b2 | 11154 | int aligned_height; |
a35cdaa0 | 11155 | int pitch_limit; |
79e53945 JB |
11156 | int ret; |
11157 | ||
dd4916c5 DV |
11158 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11159 | ||
c16ed4be CW |
11160 | if (obj->tiling_mode == I915_TILING_Y) { |
11161 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 11162 | return -EINVAL; |
c16ed4be | 11163 | } |
57cd6508 | 11164 | |
c16ed4be CW |
11165 | if (mode_cmd->pitches[0] & 63) { |
11166 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
11167 | mode_cmd->pitches[0]); | |
57cd6508 | 11168 | return -EINVAL; |
c16ed4be | 11169 | } |
57cd6508 | 11170 | |
a35cdaa0 CW |
11171 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
11172 | pitch_limit = 32*1024; | |
11173 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
11174 | if (obj->tiling_mode) | |
11175 | pitch_limit = 16*1024; | |
11176 | else | |
11177 | pitch_limit = 32*1024; | |
11178 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
11179 | if (obj->tiling_mode) | |
11180 | pitch_limit = 8*1024; | |
11181 | else | |
11182 | pitch_limit = 16*1024; | |
11183 | } else | |
11184 | /* XXX DSPC is limited to 4k tiled */ | |
11185 | pitch_limit = 8*1024; | |
11186 | ||
11187 | if (mode_cmd->pitches[0] > pitch_limit) { | |
11188 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
11189 | obj->tiling_mode ? "tiled" : "linear", | |
11190 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 11191 | return -EINVAL; |
c16ed4be | 11192 | } |
5d7bd705 VS |
11193 | |
11194 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
11195 | mode_cmd->pitches[0] != obj->stride) { |
11196 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
11197 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 11198 | return -EINVAL; |
c16ed4be | 11199 | } |
5d7bd705 | 11200 | |
57779d06 | 11201 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 11202 | switch (mode_cmd->pixel_format) { |
57779d06 | 11203 | case DRM_FORMAT_C8: |
04b3924d VS |
11204 | case DRM_FORMAT_RGB565: |
11205 | case DRM_FORMAT_XRGB8888: | |
11206 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
11207 | break; |
11208 | case DRM_FORMAT_XRGB1555: | |
11209 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 11210 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
11211 | DRM_DEBUG("unsupported pixel format: %s\n", |
11212 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11213 | return -EINVAL; |
c16ed4be | 11214 | } |
57779d06 VS |
11215 | break; |
11216 | case DRM_FORMAT_XBGR8888: | |
11217 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
11218 | case DRM_FORMAT_XRGB2101010: |
11219 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
11220 | case DRM_FORMAT_XBGR2101010: |
11221 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 11222 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
11223 | DRM_DEBUG("unsupported pixel format: %s\n", |
11224 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11225 | return -EINVAL; |
c16ed4be | 11226 | } |
b5626747 | 11227 | break; |
04b3924d VS |
11228 | case DRM_FORMAT_YUYV: |
11229 | case DRM_FORMAT_UYVY: | |
11230 | case DRM_FORMAT_YVYU: | |
11231 | case DRM_FORMAT_VYUY: | |
c16ed4be | 11232 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
11233 | DRM_DEBUG("unsupported pixel format: %s\n", |
11234 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11235 | return -EINVAL; |
c16ed4be | 11236 | } |
57cd6508 CW |
11237 | break; |
11238 | default: | |
4ee62c76 VS |
11239 | DRM_DEBUG("unsupported pixel format: %s\n", |
11240 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
11241 | return -EINVAL; |
11242 | } | |
11243 | ||
90f9a336 VS |
11244 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11245 | if (mode_cmd->offsets[0] != 0) | |
11246 | return -EINVAL; | |
11247 | ||
a57ce0b2 JB |
11248 | aligned_height = intel_align_height(dev, mode_cmd->height, |
11249 | obj->tiling_mode); | |
53155c0a DV |
11250 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11251 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
11252 | return -EINVAL; | |
11253 | ||
c7d73f6a DV |
11254 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11255 | intel_fb->obj = obj; | |
80075d49 | 11256 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 11257 | |
79e53945 JB |
11258 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11259 | if (ret) { | |
11260 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
11261 | return ret; | |
11262 | } | |
11263 | ||
79e53945 JB |
11264 | return 0; |
11265 | } | |
11266 | ||
79e53945 JB |
11267 | static struct drm_framebuffer * |
11268 | intel_user_framebuffer_create(struct drm_device *dev, | |
11269 | struct drm_file *filp, | |
308e5bcb | 11270 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 11271 | { |
05394f39 | 11272 | struct drm_i915_gem_object *obj; |
79e53945 | 11273 | |
308e5bcb JB |
11274 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
11275 | mode_cmd->handles[0])); | |
c8725226 | 11276 | if (&obj->base == NULL) |
cce13ff7 | 11277 | return ERR_PTR(-ENOENT); |
79e53945 | 11278 | |
d2dff872 | 11279 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
11280 | } |
11281 | ||
4520f53a | 11282 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 11283 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
11284 | { |
11285 | } | |
11286 | #endif | |
11287 | ||
79e53945 | 11288 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 11289 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 11290 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
11291 | }; |
11292 | ||
e70236a8 JB |
11293 | /* Set up chip specific display functions */ |
11294 | static void intel_init_display(struct drm_device *dev) | |
11295 | { | |
11296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11297 | ||
ee9300bb DV |
11298 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11299 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
11300 | else if (IS_CHERRYVIEW(dev)) |
11301 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
11302 | else if (IS_VALLEYVIEW(dev)) |
11303 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
11304 | else if (IS_PINEVIEW(dev)) | |
11305 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
11306 | else | |
11307 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
11308 | ||
affa9354 | 11309 | if (HAS_DDI(dev)) { |
0e8ffe1b | 11310 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 11311 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 11312 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
11313 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11314 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 11315 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
11316 | dev_priv->display.update_primary_plane = |
11317 | ironlake_update_primary_plane; | |
09b4ddf9 | 11318 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 11319 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 11320 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 11321 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
11322 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11323 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 11324 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
11325 | dev_priv->display.update_primary_plane = |
11326 | ironlake_update_primary_plane; | |
89b667f8 JB |
11327 | } else if (IS_VALLEYVIEW(dev)) { |
11328 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 11329 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
11330 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11331 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
11332 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
11333 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
11334 | dev_priv->display.update_primary_plane = |
11335 | i9xx_update_primary_plane; | |
f564048e | 11336 | } else { |
0e8ffe1b | 11337 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 11338 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 11339 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
11340 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
11341 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 11342 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
11343 | dev_priv->display.update_primary_plane = |
11344 | i9xx_update_primary_plane; | |
f564048e | 11345 | } |
e70236a8 | 11346 | |
e70236a8 | 11347 | /* Returns the core display clock speed */ |
25eb05fc JB |
11348 | if (IS_VALLEYVIEW(dev)) |
11349 | dev_priv->display.get_display_clock_speed = | |
11350 | valleyview_get_display_clock_speed; | |
11351 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
11352 | dev_priv->display.get_display_clock_speed = |
11353 | i945_get_display_clock_speed; | |
11354 | else if (IS_I915G(dev)) | |
11355 | dev_priv->display.get_display_clock_speed = | |
11356 | i915_get_display_clock_speed; | |
257a7ffc | 11357 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
11358 | dev_priv->display.get_display_clock_speed = |
11359 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
11360 | else if (IS_PINEVIEW(dev)) |
11361 | dev_priv->display.get_display_clock_speed = | |
11362 | pnv_get_display_clock_speed; | |
e70236a8 JB |
11363 | else if (IS_I915GM(dev)) |
11364 | dev_priv->display.get_display_clock_speed = | |
11365 | i915gm_get_display_clock_speed; | |
11366 | else if (IS_I865G(dev)) | |
11367 | dev_priv->display.get_display_clock_speed = | |
11368 | i865_get_display_clock_speed; | |
f0f8a9ce | 11369 | else if (IS_I85X(dev)) |
e70236a8 JB |
11370 | dev_priv->display.get_display_clock_speed = |
11371 | i855_get_display_clock_speed; | |
11372 | else /* 852, 830 */ | |
11373 | dev_priv->display.get_display_clock_speed = | |
11374 | i830_get_display_clock_speed; | |
11375 | ||
7f8a8569 | 11376 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 11377 | if (IS_GEN5(dev)) { |
674cf967 | 11378 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 11379 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 11380 | } else if (IS_GEN6(dev)) { |
674cf967 | 11381 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 11382 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
11383 | dev_priv->display.modeset_global_resources = |
11384 | snb_modeset_global_resources; | |
357555c0 JB |
11385 | } else if (IS_IVYBRIDGE(dev)) { |
11386 | /* FIXME: detect B0+ stepping and use auto training */ | |
11387 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 11388 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
11389 | dev_priv->display.modeset_global_resources = |
11390 | ivb_modeset_global_resources; | |
4e0bbc31 | 11391 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 11392 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 11393 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
11394 | dev_priv->display.modeset_global_resources = |
11395 | haswell_modeset_global_resources; | |
a0e63c22 | 11396 | } |
6067aaea | 11397 | } else if (IS_G4X(dev)) { |
e0dac65e | 11398 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
11399 | } else if (IS_VALLEYVIEW(dev)) { |
11400 | dev_priv->display.modeset_global_resources = | |
11401 | valleyview_modeset_global_resources; | |
9ca2fe73 | 11402 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 11403 | } |
8c9f3aaf JB |
11404 | |
11405 | /* Default just returns -ENODEV to indicate unsupported */ | |
11406 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
11407 | ||
11408 | switch (INTEL_INFO(dev)->gen) { | |
11409 | case 2: | |
11410 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
11411 | break; | |
11412 | ||
11413 | case 3: | |
11414 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
11415 | break; | |
11416 | ||
11417 | case 4: | |
11418 | case 5: | |
11419 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
11420 | break; | |
11421 | ||
11422 | case 6: | |
11423 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
11424 | break; | |
7c9017e5 | 11425 | case 7: |
4e0bbc31 | 11426 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
11427 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11428 | break; | |
8c9f3aaf | 11429 | } |
7bd688cd JN |
11430 | |
11431 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
11432 | } |
11433 | ||
b690e96c JB |
11434 | /* |
11435 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
11436 | * resume, or other times. This quirk makes sure that's the case for | |
11437 | * affected systems. | |
11438 | */ | |
0206e353 | 11439 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
11440 | { |
11441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11442 | ||
11443 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 11444 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
11445 | } |
11446 | ||
435793df KP |
11447 | /* |
11448 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
11449 | */ | |
11450 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
11451 | { | |
11452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11453 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 11454 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
11455 | } |
11456 | ||
4dca20ef | 11457 | /* |
5a15ab5b CE |
11458 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11459 | * brightness value | |
4dca20ef CE |
11460 | */ |
11461 | static void quirk_invert_brightness(struct drm_device *dev) | |
11462 | { | |
11463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11464 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 11465 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
11466 | } |
11467 | ||
b690e96c JB |
11468 | struct intel_quirk { |
11469 | int device; | |
11470 | int subsystem_vendor; | |
11471 | int subsystem_device; | |
11472 | void (*hook)(struct drm_device *dev); | |
11473 | }; | |
11474 | ||
5f85f176 EE |
11475 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11476 | struct intel_dmi_quirk { | |
11477 | void (*hook)(struct drm_device *dev); | |
11478 | const struct dmi_system_id (*dmi_id_list)[]; | |
11479 | }; | |
11480 | ||
11481 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
11482 | { | |
11483 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
11484 | return 1; | |
11485 | } | |
11486 | ||
11487 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
11488 | { | |
11489 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
11490 | { | |
11491 | .callback = intel_dmi_reverse_brightness, | |
11492 | .ident = "NCR Corporation", | |
11493 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
11494 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
11495 | }, | |
11496 | }, | |
11497 | { } /* terminating entry */ | |
11498 | }, | |
11499 | .hook = quirk_invert_brightness, | |
11500 | }, | |
11501 | }; | |
11502 | ||
c43b5634 | 11503 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 11504 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 11505 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 11506 | |
b690e96c JB |
11507 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11508 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
11509 | ||
b690e96c JB |
11510 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11511 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
11512 | ||
a4945f95 | 11513 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 11514 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
11515 | |
11516 | /* Lenovo U160 cannot use SSC on LVDS */ | |
11517 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
11518 | |
11519 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
11520 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 11521 | |
be505f64 AH |
11522 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11523 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
11524 | ||
11525 | /* Acer/eMachines G725 */ | |
11526 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
11527 | ||
11528 | /* Acer/eMachines e725 */ | |
11529 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
11530 | ||
11531 | /* Acer/Packard Bell NCL20 */ | |
11532 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
11533 | ||
11534 | /* Acer Aspire 4736Z */ | |
11535 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
11536 | |
11537 | /* Acer Aspire 5336 */ | |
11538 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
11539 | }; |
11540 | ||
11541 | static void intel_init_quirks(struct drm_device *dev) | |
11542 | { | |
11543 | struct pci_dev *d = dev->pdev; | |
11544 | int i; | |
11545 | ||
11546 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
11547 | struct intel_quirk *q = &intel_quirks[i]; | |
11548 | ||
11549 | if (d->device == q->device && | |
11550 | (d->subsystem_vendor == q->subsystem_vendor || | |
11551 | q->subsystem_vendor == PCI_ANY_ID) && | |
11552 | (d->subsystem_device == q->subsystem_device || | |
11553 | q->subsystem_device == PCI_ANY_ID)) | |
11554 | q->hook(dev); | |
11555 | } | |
5f85f176 EE |
11556 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
11557 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
11558 | intel_dmi_quirks[i].hook(dev); | |
11559 | } | |
b690e96c JB |
11560 | } |
11561 | ||
9cce37f4 JB |
11562 | /* Disable the VGA plane that we never use */ |
11563 | static void i915_disable_vga(struct drm_device *dev) | |
11564 | { | |
11565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11566 | u8 sr1; | |
766aa1c4 | 11567 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 11568 | |
2b37c616 | 11569 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 11570 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 11571 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
11572 | sr1 = inb(VGA_SR_DATA); |
11573 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
11574 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
11575 | udelay(300); | |
11576 | ||
11577 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
11578 | POSTING_READ(vga_reg); | |
11579 | } | |
11580 | ||
f817586c DV |
11581 | void intel_modeset_init_hw(struct drm_device *dev) |
11582 | { | |
a8f78b58 ED |
11583 | intel_prepare_ddi(dev); |
11584 | ||
f817586c DV |
11585 | intel_init_clock_gating(dev); |
11586 | ||
5382f5f3 | 11587 | intel_reset_dpio(dev); |
40e9cf64 | 11588 | |
8090c6b9 | 11589 | intel_enable_gt_powersave(dev); |
f817586c DV |
11590 | } |
11591 | ||
7d708ee4 ID |
11592 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11593 | { | |
11594 | intel_suspend_hw(dev); | |
11595 | } | |
11596 | ||
79e53945 JB |
11597 | void intel_modeset_init(struct drm_device *dev) |
11598 | { | |
652c393a | 11599 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 11600 | int sprite, ret; |
8cc87b75 | 11601 | enum pipe pipe; |
46f297fb | 11602 | struct intel_crtc *crtc; |
79e53945 JB |
11603 | |
11604 | drm_mode_config_init(dev); | |
11605 | ||
11606 | dev->mode_config.min_width = 0; | |
11607 | dev->mode_config.min_height = 0; | |
11608 | ||
019d96cb DA |
11609 | dev->mode_config.preferred_depth = 24; |
11610 | dev->mode_config.prefer_shadow = 1; | |
11611 | ||
e6ecefaa | 11612 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11613 | |
b690e96c JB |
11614 | intel_init_quirks(dev); |
11615 | ||
1fa61106 ED |
11616 | intel_init_pm(dev); |
11617 | ||
e3c74757 BW |
11618 | if (INTEL_INFO(dev)->num_pipes == 0) |
11619 | return; | |
11620 | ||
e70236a8 JB |
11621 | intel_init_display(dev); |
11622 | ||
a6c45cf0 CW |
11623 | if (IS_GEN2(dev)) { |
11624 | dev->mode_config.max_width = 2048; | |
11625 | dev->mode_config.max_height = 2048; | |
11626 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11627 | dev->mode_config.max_width = 4096; |
11628 | dev->mode_config.max_height = 4096; | |
79e53945 | 11629 | } else { |
a6c45cf0 CW |
11630 | dev->mode_config.max_width = 8192; |
11631 | dev->mode_config.max_height = 8192; | |
79e53945 | 11632 | } |
068be561 DL |
11633 | |
11634 | if (IS_GEN2(dev)) { | |
11635 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
11636 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
11637 | } else { | |
11638 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
11639 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
11640 | } | |
11641 | ||
5d4545ae | 11642 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11643 | |
28c97730 | 11644 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11645 | INTEL_INFO(dev)->num_pipes, |
11646 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11647 | |
8cc87b75 DL |
11648 | for_each_pipe(pipe) { |
11649 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
11650 | for_each_sprite(pipe, sprite) { |
11651 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 11652 | if (ret) |
06da8da2 | 11653 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 11654 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 11655 | } |
79e53945 JB |
11656 | } |
11657 | ||
f42bb70d | 11658 | intel_init_dpio(dev); |
5382f5f3 | 11659 | intel_reset_dpio(dev); |
f42bb70d | 11660 | |
79f689aa | 11661 | intel_cpu_pll_init(dev); |
e72f9fbf | 11662 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11663 | |
9cce37f4 JB |
11664 | /* Just disable it once at startup */ |
11665 | i915_disable_vga(dev); | |
79e53945 | 11666 | intel_setup_outputs(dev); |
11be49eb CW |
11667 | |
11668 | /* Just in case the BIOS is doing something questionable. */ | |
11669 | intel_disable_fbc(dev); | |
fa9fa083 | 11670 | |
8b687df4 | 11671 | mutex_lock(&dev->mode_config.mutex); |
fa9fa083 | 11672 | intel_modeset_setup_hw_state(dev, false); |
8b687df4 | 11673 | mutex_unlock(&dev->mode_config.mutex); |
46f297fb | 11674 | |
d3fcc808 | 11675 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
11676 | if (!crtc->active) |
11677 | continue; | |
11678 | ||
46f297fb | 11679 | /* |
46f297fb JB |
11680 | * Note that reserving the BIOS fb up front prevents us |
11681 | * from stuffing other stolen allocations like the ring | |
11682 | * on top. This prevents some ugliness at boot time, and | |
11683 | * can even allow for smooth boot transitions if the BIOS | |
11684 | * fb is large enough for the active pipe configuration. | |
11685 | */ | |
11686 | if (dev_priv->display.get_plane_config) { | |
11687 | dev_priv->display.get_plane_config(crtc, | |
11688 | &crtc->plane_config); | |
11689 | /* | |
11690 | * If the fb is shared between multiple heads, we'll | |
11691 | * just get the first one. | |
11692 | */ | |
484b41dd | 11693 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 11694 | } |
46f297fb | 11695 | } |
2c7111db CW |
11696 | } |
11697 | ||
24929352 DV |
11698 | static void |
11699 | intel_connector_break_all_links(struct intel_connector *connector) | |
11700 | { | |
11701 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11702 | connector->base.encoder = NULL; | |
11703 | connector->encoder->connectors_active = false; | |
11704 | connector->encoder->base.crtc = NULL; | |
11705 | } | |
11706 | ||
7fad798e DV |
11707 | static void intel_enable_pipe_a(struct drm_device *dev) |
11708 | { | |
11709 | struct intel_connector *connector; | |
11710 | struct drm_connector *crt = NULL; | |
11711 | struct intel_load_detect_pipe load_detect_temp; | |
11712 | ||
11713 | /* We can't just switch on the pipe A, we need to set things up with a | |
11714 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11715 | * by enabling the load detect pipe once. */ | |
11716 | list_for_each_entry(connector, | |
11717 | &dev->mode_config.connector_list, | |
11718 | base.head) { | |
11719 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11720 | crt = &connector->base; | |
11721 | break; | |
11722 | } | |
11723 | } | |
11724 | ||
11725 | if (!crt) | |
11726 | return; | |
11727 | ||
11728 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11729 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11730 | ||
652c393a | 11731 | |
7fad798e DV |
11732 | } |
11733 | ||
fa555837 DV |
11734 | static bool |
11735 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11736 | { | |
7eb552ae BW |
11737 | struct drm_device *dev = crtc->base.dev; |
11738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11739 | u32 reg, val; |
11740 | ||
7eb552ae | 11741 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11742 | return true; |
11743 | ||
11744 | reg = DSPCNTR(!crtc->plane); | |
11745 | val = I915_READ(reg); | |
11746 | ||
11747 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11748 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11749 | return false; | |
11750 | ||
11751 | return true; | |
11752 | } | |
11753 | ||
24929352 DV |
11754 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11755 | { | |
11756 | struct drm_device *dev = crtc->base.dev; | |
11757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11758 | u32 reg; |
24929352 | 11759 | |
24929352 | 11760 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11761 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11762 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11763 | ||
11764 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11765 | * disable the crtc (and hence change the state) if it is wrong. Note |
11766 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11767 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11768 | struct intel_connector *connector; |
11769 | bool plane; | |
11770 | ||
24929352 DV |
11771 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11772 | crtc->base.base.id); | |
11773 | ||
11774 | /* Pipe has the wrong plane attached and the plane is active. | |
11775 | * Temporarily change the plane mapping and disable everything | |
11776 | * ... */ | |
11777 | plane = crtc->plane; | |
11778 | crtc->plane = !plane; | |
11779 | dev_priv->display.crtc_disable(&crtc->base); | |
11780 | crtc->plane = plane; | |
11781 | ||
11782 | /* ... and break all links. */ | |
11783 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11784 | base.head) { | |
11785 | if (connector->encoder->base.crtc != &crtc->base) | |
11786 | continue; | |
11787 | ||
11788 | intel_connector_break_all_links(connector); | |
11789 | } | |
11790 | ||
11791 | WARN_ON(crtc->active); | |
11792 | crtc->base.enabled = false; | |
11793 | } | |
24929352 | 11794 | |
7fad798e DV |
11795 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11796 | crtc->pipe == PIPE_A && !crtc->active) { | |
11797 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11798 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11799 | * call below we restore the pipe to the right state, but leave | |
11800 | * the required bits on. */ | |
11801 | intel_enable_pipe_a(dev); | |
11802 | } | |
11803 | ||
24929352 DV |
11804 | /* Adjust the state of the output pipe according to whether we |
11805 | * have active connectors/encoders. */ | |
11806 | intel_crtc_update_dpms(&crtc->base); | |
11807 | ||
11808 | if (crtc->active != crtc->base.enabled) { | |
11809 | struct intel_encoder *encoder; | |
11810 | ||
11811 | /* This can happen either due to bugs in the get_hw_state | |
11812 | * functions or because the pipe is force-enabled due to the | |
11813 | * pipe A quirk. */ | |
11814 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11815 | crtc->base.base.id, | |
11816 | crtc->base.enabled ? "enabled" : "disabled", | |
11817 | crtc->active ? "enabled" : "disabled"); | |
11818 | ||
11819 | crtc->base.enabled = crtc->active; | |
11820 | ||
11821 | /* Because we only establish the connector -> encoder -> | |
11822 | * crtc links if something is active, this means the | |
11823 | * crtc is now deactivated. Break the links. connector | |
11824 | * -> encoder links are only establish when things are | |
11825 | * actually up, hence no need to break them. */ | |
11826 | WARN_ON(crtc->active); | |
11827 | ||
11828 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11829 | WARN_ON(encoder->connectors_active); | |
11830 | encoder->base.crtc = NULL; | |
11831 | } | |
11832 | } | |
4cc31489 DV |
11833 | if (crtc->active) { |
11834 | /* | |
11835 | * We start out with underrun reporting disabled to avoid races. | |
11836 | * For correct bookkeeping mark this on active crtcs. | |
11837 | * | |
11838 | * No protection against concurrent access is required - at | |
11839 | * worst a fifo underrun happens which also sets this to false. | |
11840 | */ | |
11841 | crtc->cpu_fifo_underrun_disabled = true; | |
11842 | crtc->pch_fifo_underrun_disabled = true; | |
11843 | } | |
24929352 DV |
11844 | } |
11845 | ||
11846 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11847 | { | |
11848 | struct intel_connector *connector; | |
11849 | struct drm_device *dev = encoder->base.dev; | |
11850 | ||
11851 | /* We need to check both for a crtc link (meaning that the | |
11852 | * encoder is active and trying to read from a pipe) and the | |
11853 | * pipe itself being active. */ | |
11854 | bool has_active_crtc = encoder->base.crtc && | |
11855 | to_intel_crtc(encoder->base.crtc)->active; | |
11856 | ||
11857 | if (encoder->connectors_active && !has_active_crtc) { | |
11858 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11859 | encoder->base.base.id, | |
11860 | drm_get_encoder_name(&encoder->base)); | |
11861 | ||
11862 | /* Connector is active, but has no active pipe. This is | |
11863 | * fallout from our resume register restoring. Disable | |
11864 | * the encoder manually again. */ | |
11865 | if (encoder->base.crtc) { | |
11866 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11867 | encoder->base.base.id, | |
11868 | drm_get_encoder_name(&encoder->base)); | |
11869 | encoder->disable(encoder); | |
11870 | } | |
11871 | ||
11872 | /* Inconsistent output/port/pipe state happens presumably due to | |
11873 | * a bug in one of the get_hw_state functions. Or someplace else | |
11874 | * in our code, like the register restore mess on resume. Clamp | |
11875 | * things to off as a safer default. */ | |
11876 | list_for_each_entry(connector, | |
11877 | &dev->mode_config.connector_list, | |
11878 | base.head) { | |
11879 | if (connector->encoder != encoder) | |
11880 | continue; | |
11881 | ||
11882 | intel_connector_break_all_links(connector); | |
11883 | } | |
11884 | } | |
11885 | /* Enabled encoders without active connectors will be fixed in | |
11886 | * the crtc fixup. */ | |
11887 | } | |
11888 | ||
04098753 | 11889 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
11890 | { |
11891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11892 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11893 | |
04098753 ID |
11894 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
11895 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
11896 | i915_disable_vga(dev); | |
11897 | } | |
11898 | } | |
11899 | ||
11900 | void i915_redisable_vga(struct drm_device *dev) | |
11901 | { | |
11902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11903 | ||
8dc8a27c PZ |
11904 | /* This function can be called both from intel_modeset_setup_hw_state or |
11905 | * at a very early point in our resume sequence, where the power well | |
11906 | * structures are not yet restored. Since this function is at a very | |
11907 | * paranoid "someone might have enabled VGA while we were not looking" | |
11908 | * level, just check if the power well is enabled instead of trying to | |
11909 | * follow the "don't touch the power well if we don't need it" policy | |
11910 | * the rest of the driver uses. */ | |
04098753 | 11911 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
11912 | return; |
11913 | ||
04098753 | 11914 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
11915 | } |
11916 | ||
98ec7739 VS |
11917 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
11918 | { | |
11919 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
11920 | ||
11921 | if (!crtc->active) | |
11922 | return false; | |
11923 | ||
11924 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
11925 | } | |
11926 | ||
30e984df | 11927 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11928 | { |
11929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11930 | enum pipe pipe; | |
24929352 DV |
11931 | struct intel_crtc *crtc; |
11932 | struct intel_encoder *encoder; | |
11933 | struct intel_connector *connector; | |
5358901f | 11934 | int i; |
24929352 | 11935 | |
d3fcc808 | 11936 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 11937 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11938 | |
9953599b DV |
11939 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
11940 | ||
0e8ffe1b DV |
11941 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11942 | &crtc->config); | |
24929352 DV |
11943 | |
11944 | crtc->base.enabled = crtc->active; | |
98ec7739 | 11945 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
11946 | |
11947 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11948 | crtc->base.base.id, | |
11949 | crtc->active ? "enabled" : "disabled"); | |
11950 | } | |
11951 | ||
5358901f | 11952 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11953 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11954 | intel_ddi_setup_hw_pll_state(dev); |
11955 | ||
5358901f DV |
11956 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11957 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11958 | ||
11959 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11960 | pll->active = 0; | |
d3fcc808 | 11961 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
11962 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
11963 | pll->active++; | |
11964 | } | |
11965 | pll->refcount = pll->active; | |
11966 | ||
35c95375 DV |
11967 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11968 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11969 | } |
11970 | ||
24929352 DV |
11971 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11972 | base.head) { | |
11973 | pipe = 0; | |
11974 | ||
11975 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11976 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11977 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11978 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11979 | } else { |
11980 | encoder->base.crtc = NULL; | |
11981 | } | |
11982 | ||
11983 | encoder->connectors_active = false; | |
6f2bcceb | 11984 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11985 | encoder->base.base.id, |
11986 | drm_get_encoder_name(&encoder->base), | |
11987 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11988 | pipe_name(pipe)); |
24929352 DV |
11989 | } |
11990 | ||
11991 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11992 | base.head) { | |
11993 | if (connector->get_hw_state(connector)) { | |
11994 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11995 | connector->encoder->connectors_active = true; | |
11996 | connector->base.encoder = &connector->encoder->base; | |
11997 | } else { | |
11998 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11999 | connector->base.encoder = NULL; | |
12000 | } | |
12001 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
12002 | connector->base.base.id, | |
12003 | drm_get_connector_name(&connector->base), | |
12004 | connector->base.encoder ? "enabled" : "disabled"); | |
12005 | } | |
30e984df DV |
12006 | } |
12007 | ||
12008 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
12009 | * and i915 state tracking structures. */ | |
12010 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
12011 | bool force_restore) | |
12012 | { | |
12013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12014 | enum pipe pipe; | |
30e984df DV |
12015 | struct intel_crtc *crtc; |
12016 | struct intel_encoder *encoder; | |
35c95375 | 12017 | int i; |
30e984df DV |
12018 | |
12019 | intel_modeset_readout_hw_state(dev); | |
24929352 | 12020 | |
babea61d JB |
12021 | /* |
12022 | * Now that we have the config, copy it to each CRTC struct | |
12023 | * Note that this could go away if we move to using crtc_config | |
12024 | * checking everywhere. | |
12025 | */ | |
d3fcc808 | 12026 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 12027 | if (crtc->active && i915.fastboot) { |
f6a83288 | 12028 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
12029 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12030 | crtc->base.base.id); | |
12031 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
12032 | } | |
12033 | } | |
12034 | ||
24929352 DV |
12035 | /* HW state is read out, now we need to sanitize this mess. */ |
12036 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
12037 | base.head) { | |
12038 | intel_sanitize_encoder(encoder); | |
12039 | } | |
12040 | ||
12041 | for_each_pipe(pipe) { | |
12042 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
12043 | intel_sanitize_crtc(crtc); | |
c0b03411 | 12044 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 12045 | } |
9a935856 | 12046 | |
35c95375 DV |
12047 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12048 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12049 | ||
12050 | if (!pll->on || pll->active) | |
12051 | continue; | |
12052 | ||
12053 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
12054 | ||
12055 | pll->disable(dev_priv, pll); | |
12056 | pll->on = false; | |
12057 | } | |
12058 | ||
96f90c54 | 12059 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
12060 | ilk_wm_get_hw_state(dev); |
12061 | ||
45e2b5f6 | 12062 | if (force_restore) { |
7d0bc1ea VS |
12063 | i915_redisable_vga(dev); |
12064 | ||
f30da187 DV |
12065 | /* |
12066 | * We need to use raw interfaces for restoring state to avoid | |
12067 | * checking (bogus) intermediate states. | |
12068 | */ | |
45e2b5f6 | 12069 | for_each_pipe(pipe) { |
b5644d05 JB |
12070 | struct drm_crtc *crtc = |
12071 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
12072 | |
12073 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 12074 | crtc->primary->fb); |
45e2b5f6 DV |
12075 | } |
12076 | } else { | |
12077 | intel_modeset_update_staged_output_state(dev); | |
12078 | } | |
8af6cf88 DV |
12079 | |
12080 | intel_modeset_check_state(dev); | |
2c7111db CW |
12081 | } |
12082 | ||
12083 | void intel_modeset_gem_init(struct drm_device *dev) | |
12084 | { | |
484b41dd JB |
12085 | struct drm_crtc *c; |
12086 | struct intel_framebuffer *fb; | |
12087 | ||
ae48434c ID |
12088 | mutex_lock(&dev->struct_mutex); |
12089 | intel_init_gt_powersave(dev); | |
12090 | mutex_unlock(&dev->struct_mutex); | |
12091 | ||
1833b134 | 12092 | intel_modeset_init_hw(dev); |
02e792fb DV |
12093 | |
12094 | intel_setup_overlay(dev); | |
484b41dd JB |
12095 | |
12096 | /* | |
12097 | * Make sure any fbs we allocated at startup are properly | |
12098 | * pinned & fenced. When we do the allocation it's too early | |
12099 | * for this. | |
12100 | */ | |
12101 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12102 | for_each_crtc(dev, c) { |
66e514c1 | 12103 | if (!c->primary->fb) |
484b41dd JB |
12104 | continue; |
12105 | ||
66e514c1 | 12106 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12107 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12108 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12109 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12110 | drm_framebuffer_unreference(c->primary->fb); |
12111 | c->primary->fb = NULL; | |
484b41dd JB |
12112 | } |
12113 | } | |
12114 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12115 | } |
12116 | ||
4932e2c3 ID |
12117 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12118 | { | |
12119 | struct drm_connector *connector = &intel_connector->base; | |
12120 | ||
12121 | intel_panel_destroy_backlight(connector); | |
12122 | drm_sysfs_connector_remove(connector); | |
12123 | } | |
12124 | ||
79e53945 JB |
12125 | void intel_modeset_cleanup(struct drm_device *dev) |
12126 | { | |
652c393a JB |
12127 | struct drm_i915_private *dev_priv = dev->dev_private; |
12128 | struct drm_crtc *crtc; | |
d9255d57 | 12129 | struct drm_connector *connector; |
652c393a | 12130 | |
fd0c0642 DV |
12131 | /* |
12132 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12133 | * Too much stuff here (turning of rps, connectors, ...) would | |
12134 | * experience fancy races otherwise. | |
12135 | */ | |
12136 | drm_irq_uninstall(dev); | |
12137 | cancel_work_sync(&dev_priv->hotplug_work); | |
12138 | /* | |
12139 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
12140 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
12141 | */ | |
f87ea761 | 12142 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 12143 | |
652c393a JB |
12144 | mutex_lock(&dev->struct_mutex); |
12145 | ||
723bfd70 JB |
12146 | intel_unregister_dsm_handler(); |
12147 | ||
70e1e0ec | 12148 | for_each_crtc(dev, crtc) { |
652c393a | 12149 | /* Skip inactive CRTCs */ |
f4510a27 | 12150 | if (!crtc->primary->fb) |
652c393a JB |
12151 | continue; |
12152 | ||
3dec0095 | 12153 | intel_increase_pllclock(crtc); |
652c393a JB |
12154 | } |
12155 | ||
973d04f9 | 12156 | intel_disable_fbc(dev); |
e70236a8 | 12157 | |
8090c6b9 | 12158 | intel_disable_gt_powersave(dev); |
0cdab21f | 12159 | |
930ebb46 DV |
12160 | ironlake_teardown_rc6(dev); |
12161 | ||
69341a5e KH |
12162 | mutex_unlock(&dev->struct_mutex); |
12163 | ||
1630fe75 CW |
12164 | /* flush any delayed tasks or pending work */ |
12165 | flush_scheduled_work(); | |
12166 | ||
db31af1d JN |
12167 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12168 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
12169 | struct intel_connector *intel_connector; |
12170 | ||
12171 | intel_connector = to_intel_connector(connector); | |
12172 | intel_connector->unregister(intel_connector); | |
db31af1d | 12173 | } |
d9255d57 | 12174 | |
79e53945 | 12175 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
12176 | |
12177 | intel_cleanup_overlay(dev); | |
ae48434c ID |
12178 | |
12179 | mutex_lock(&dev->struct_mutex); | |
12180 | intel_cleanup_gt_powersave(dev); | |
12181 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12182 | } |
12183 | ||
f1c79df3 ZW |
12184 | /* |
12185 | * Return which encoder is currently attached for connector. | |
12186 | */ | |
df0e9248 | 12187 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 12188 | { |
df0e9248 CW |
12189 | return &intel_attached_encoder(connector)->base; |
12190 | } | |
f1c79df3 | 12191 | |
df0e9248 CW |
12192 | void intel_connector_attach_encoder(struct intel_connector *connector, |
12193 | struct intel_encoder *encoder) | |
12194 | { | |
12195 | connector->encoder = encoder; | |
12196 | drm_mode_connector_attach_encoder(&connector->base, | |
12197 | &encoder->base); | |
79e53945 | 12198 | } |
28d52043 DA |
12199 | |
12200 | /* | |
12201 | * set vga decode state - true == enable VGA decode | |
12202 | */ | |
12203 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
12204 | { | |
12205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 12206 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
12207 | u16 gmch_ctrl; |
12208 | ||
75fa041d CW |
12209 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
12210 | DRM_ERROR("failed to read control word\n"); | |
12211 | return -EIO; | |
12212 | } | |
12213 | ||
c0cc8a55 CW |
12214 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
12215 | return 0; | |
12216 | ||
28d52043 DA |
12217 | if (state) |
12218 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
12219 | else | |
12220 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
12221 | |
12222 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
12223 | DRM_ERROR("failed to write control word\n"); | |
12224 | return -EIO; | |
12225 | } | |
12226 | ||
28d52043 DA |
12227 | return 0; |
12228 | } | |
c4a1d9e4 | 12229 | |
c4a1d9e4 | 12230 | struct intel_display_error_state { |
ff57f1b0 PZ |
12231 | |
12232 | u32 power_well_driver; | |
12233 | ||
63b66e5b CW |
12234 | int num_transcoders; |
12235 | ||
c4a1d9e4 CW |
12236 | struct intel_cursor_error_state { |
12237 | u32 control; | |
12238 | u32 position; | |
12239 | u32 base; | |
12240 | u32 size; | |
52331309 | 12241 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12242 | |
12243 | struct intel_pipe_error_state { | |
ddf9c536 | 12244 | bool power_domain_on; |
c4a1d9e4 | 12245 | u32 source; |
f301b1e1 | 12246 | u32 stat; |
52331309 | 12247 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12248 | |
12249 | struct intel_plane_error_state { | |
12250 | u32 control; | |
12251 | u32 stride; | |
12252 | u32 size; | |
12253 | u32 pos; | |
12254 | u32 addr; | |
12255 | u32 surface; | |
12256 | u32 tile_offset; | |
52331309 | 12257 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
12258 | |
12259 | struct intel_transcoder_error_state { | |
ddf9c536 | 12260 | bool power_domain_on; |
63b66e5b CW |
12261 | enum transcoder cpu_transcoder; |
12262 | ||
12263 | u32 conf; | |
12264 | ||
12265 | u32 htotal; | |
12266 | u32 hblank; | |
12267 | u32 hsync; | |
12268 | u32 vtotal; | |
12269 | u32 vblank; | |
12270 | u32 vsync; | |
12271 | } transcoder[4]; | |
c4a1d9e4 CW |
12272 | }; |
12273 | ||
12274 | struct intel_display_error_state * | |
12275 | intel_display_capture_error_state(struct drm_device *dev) | |
12276 | { | |
fbee40df | 12277 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 12278 | struct intel_display_error_state *error; |
63b66e5b CW |
12279 | int transcoders[] = { |
12280 | TRANSCODER_A, | |
12281 | TRANSCODER_B, | |
12282 | TRANSCODER_C, | |
12283 | TRANSCODER_EDP, | |
12284 | }; | |
c4a1d9e4 CW |
12285 | int i; |
12286 | ||
63b66e5b CW |
12287 | if (INTEL_INFO(dev)->num_pipes == 0) |
12288 | return NULL; | |
12289 | ||
9d1cb914 | 12290 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
12291 | if (error == NULL) |
12292 | return NULL; | |
12293 | ||
190be112 | 12294 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
12295 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12296 | ||
52331309 | 12297 | for_each_pipe(i) { |
ddf9c536 | 12298 | error->pipe[i].power_domain_on = |
da7e29bd ID |
12299 | intel_display_power_enabled_sw(dev_priv, |
12300 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 12301 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
12302 | continue; |
12303 | ||
5efb3e28 VS |
12304 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12305 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
12306 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
12307 | |
12308 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
12309 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 12310 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 12311 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
12312 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12313 | } | |
ca291363 PZ |
12314 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12315 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
12316 | if (INTEL_INFO(dev)->gen >= 4) { |
12317 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
12318 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
12319 | } | |
12320 | ||
c4a1d9e4 | 12321 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
12322 | |
12323 | if (!HAS_PCH_SPLIT(dev)) | |
12324 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
12325 | } |
12326 | ||
12327 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
12328 | if (HAS_DDI(dev_priv->dev)) | |
12329 | error->num_transcoders++; /* Account for eDP. */ | |
12330 | ||
12331 | for (i = 0; i < error->num_transcoders; i++) { | |
12332 | enum transcoder cpu_transcoder = transcoders[i]; | |
12333 | ||
ddf9c536 | 12334 | error->transcoder[i].power_domain_on = |
da7e29bd | 12335 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 12336 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 12337 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
12338 | continue; |
12339 | ||
63b66e5b CW |
12340 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
12341 | ||
12342 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
12343 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
12344 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
12345 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
12346 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
12347 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
12348 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
12349 | } |
12350 | ||
12351 | return error; | |
12352 | } | |
12353 | ||
edc3d884 MK |
12354 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
12355 | ||
c4a1d9e4 | 12356 | void |
edc3d884 | 12357 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
12358 | struct drm_device *dev, |
12359 | struct intel_display_error_state *error) | |
12360 | { | |
12361 | int i; | |
12362 | ||
63b66e5b CW |
12363 | if (!error) |
12364 | return; | |
12365 | ||
edc3d884 | 12366 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 12367 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 12368 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 12369 | error->power_well_driver); |
52331309 | 12370 | for_each_pipe(i) { |
edc3d884 | 12371 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
12372 | err_printf(m, " Power: %s\n", |
12373 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 12374 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 12375 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
12376 | |
12377 | err_printf(m, "Plane [%d]:\n", i); | |
12378 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
12379 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 12380 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
12381 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
12382 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 12383 | } |
4b71a570 | 12384 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 12385 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 12386 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
12387 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
12388 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
12389 | } |
12390 | ||
edc3d884 MK |
12391 | err_printf(m, "Cursor [%d]:\n", i); |
12392 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
12393 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
12394 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 12395 | } |
63b66e5b CW |
12396 | |
12397 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 12398 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 12399 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
12400 | err_printf(m, " Power: %s\n", |
12401 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
12402 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
12403 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
12404 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
12405 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
12406 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
12407 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
12408 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
12409 | } | |
c4a1d9e4 | 12410 | } |