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drm/i915: clean up pipe bpp confusion
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
92f2584a
JB		 1291static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1292{
1293 u32 val;
1294 bool enabled;
1295
9d82aa17
ED		 1296 if (HAS_PCH_LPT(dev_priv->dev)) {
1297 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1298 return;
1299 }
1300
92f2584a
JB		 1301 val = I915_READ(PCH_DREF_CONTROL);
1302 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1303 DREF_SUPERSPREAD_SOURCE_MASK));
1304 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305}
1306
1307static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 int reg;
1311 u32 val;
1312 bool enabled;
1313
1314 reg = TRANSCONF(pipe);
1315 val = I915_READ(reg);
1316 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1317 WARN(enabled,
1318 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1319 pipe_name(pipe));
92f2584a
JB		 1320}
1321
4e634389
KP		 1322static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1324{
1325 if ((val & DP_PORT_EN) == 0)
1326 return false;
1327
1328 if (HAS_PCH_CPT(dev_priv->dev)) {
1329 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1330 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1331 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332 return false;
1333 } else {
1334 if ((val & DP_PIPE_MASK) != (pipe << 30))
1335 return false;
1336 }
1337 return true;
1338}
1339
1519b995
KP		 1340static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
dc0fa718 1343 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1347 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1348 return false;
1349 } else {
dc0fa718 1350 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & LVDS_PORT_EN) == 0)
1360 return false;
1361
1362 if (HAS_PCH_CPT(dev_priv->dev)) {
1363 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364 return false;
1365 } else {
1366 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1367 return false;
1368 }
1369 return true;
1370}
1371
1372static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 val)
1374{
1375 if ((val & ADPA_DAC_ENABLE) == 0)
1376 return false;
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379 return false;
1380 } else {
1381 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1382 return false;
1383 }
1384 return true;
1385}
1386
291906f1 1387static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1388 enum pipe pipe, int reg, u32 port_sel)
291906f1 1389{
47a05eca 1390 u32 val = I915_READ(reg);
4e634389 1391 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1392 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1396 && (val & DP_PIPEB_SELECT),
de9a35ab 1397 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, int reg)
1402{
47a05eca 1403 u32 val = I915_READ(reg);
b70ad586 1404 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1405 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1406 reg, pipe_name(pipe));
de9a35ab 1407
dc0fa718 1408 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1409 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1410 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1411}
1412
1413static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415{
1416 int reg;
1417 u32 val;
291906f1 1418
f0575e92
KP		 1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1420 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1421 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1422
1423 reg = PCH_ADPA;
1424 val = I915_READ(reg);
b70ad586 1425 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1426 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1427 pipe_name(pipe));
291906f1
JB		 1428
1429 reg = PCH_LVDS;
1430 val = I915_READ(reg);
b70ad586 1431 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1432 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1433 pipe_name(pipe));
291906f1 1434
e2debe91
PZ		 1435 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1436 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1437 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1438}
1439
63d7bbe9
JB		 1440/**
1441 * intel_enable_pll - enable a PLL
1442 * @dev_priv: i915 private structure
1443 * @pipe: pipe PLL to enable
1444 *
1445 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1446 * make sure the PLL reg is writable first though, since the panel write
1447 * protect mechanism may be enabled.
1448 *
1449 * Note! This is for pre-ILK only.
7434a255
TR		 1450 *
1451 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1452 */
1453static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1454{
1455 int reg;
1456 u32 val;
1457
1458 /* No really, not for ILK+ */
a0c4da24 1459 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1460
1461 /* PLL is protected by panel, make sure we can write it */
1462 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1463 assert_panel_unlocked(dev_priv, pipe);
1464
1465 reg = DPLL(pipe);
1466 val = I915_READ(reg);
1467 val |= DPLL_VCO_ENABLE;
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, val);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, val);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
1482 * intel_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491{
1492 int reg;
1493 u32 val;
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 /* Make sure the pipe isn't still relying on us */
1500 assert_pipe_disabled(dev_priv, pipe);
1501
1502 reg = DPLL(pipe);
1503 val = I915_READ(reg);
1504 val &= ~DPLL_VCO_ENABLE;
1505 I915_WRITE(reg, val);
1506 POSTING_READ(reg);
1507}
1508
a416edef
ED		 1509/* SBI access */
1510static void
988d6ee8
PZ		 1511intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1512 enum intel_sbi_destination destination)
a416edef 1513{
988d6ee8 1514 u32 tmp;
a416edef 1515
09153000 1516 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1517
39fb50f6 1518 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1519 100)) {
1520 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1521 return;
a416edef
ED		 1522 }
1523
988d6ee8
PZ		 1524 I915_WRITE(SBI_ADDR, (reg << 16));
1525 I915_WRITE(SBI_DATA, value);
1526
1527 if (destination == SBI_ICLK)
1528 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1529 else
1530 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1531 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1532
39fb50f6 1533 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1534 100)) {
1535 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1536 return;
a416edef 1537 }
a416edef
ED		 1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef 1543{
39fb50f6 1544 u32 value = 0;
09153000 1545 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1546
39fb50f6 1547 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1548 100)) {
1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1550 return 0;
a416edef
ED		 1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1564 return 0;
a416edef
ED		 1565 }
1566
09153000 1567 return I915_READ(SBI_DATA);
a416edef
ED		 1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
dfd07d72
DV		 1699 val &= ~PIPECONF_BPC_MASK;
1700 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1727 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
1a240d4d 1815 enum pipe pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
681e5811 1819 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1835 assert_fdi_tx_pll_enabled(dev_priv,
1836 (enum pipe) cpu_transcoder);
040484af
JB		 1837 }
1838 /* FIXME: assert CPU port conditions for SNB+ */
1839 }
b24e7179 1840
702e7a56 1841 reg = PIPECONF(cpu_transcoder);
b24e7179 1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & PIPECONF_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1847 intel_wait_for_vblank(dev_priv->dev, pipe);
1848}
1849
1850/**
309cfea8 1851 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1852 * @dev_priv: i915 private structure
1853 * @pipe: pipe to disable
1854 *
1855 * Disable @pipe, making sure that various hardware specific requirements
1856 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 *
1858 * @pipe should be %PIPE_A or %PIPE_B.
1859 *
1860 * Will wait until the pipe has shut down before returning.
1861 */
1862static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1863 enum pipe pipe)
1864{
702e7a56
PZ		 1865 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1866 pipe);
b24e7179
JB		 1867 int reg;
1868 u32 val;
1869
1870 /*
1871 * Make sure planes won't keep trying to pump pixels to us,
1872 * or we might hang the display.
1873 */
1874 assert_planes_disabled(dev_priv, pipe);
1875
1876 /* Don't disable pipe A or pipe A PLLs if needed */
1877 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1878 return;
1879
702e7a56 1880 reg = PIPECONF(cpu_transcoder);
b24e7179 1881 val = I915_READ(reg);
00d70b15
CW		 1882 if ((val & PIPECONF_ENABLE) == 0)
1883 return;
1884
1885 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1886 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1887}
1888
d74362c9
KP		 1889/*
1890 * Plane regs are double buffered, going from enabled->disabled needs a
1891 * trigger in order to latch. The display address reg provides this.
1892 */
6f1d69b0 1893void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1894 enum plane plane)
1895{
14f86147
DL		 1896 if (dev_priv->info->gen >= 4)
1897 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1898 else
1899 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1900}
1901
b24e7179
JB		 1902/**
1903 * intel_enable_plane - enable a display plane on a given pipe
1904 * @dev_priv: i915 private structure
1905 * @plane: plane to enable
1906 * @pipe: pipe being fed
1907 *
1908 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 */
1910static void intel_enable_plane(struct drm_i915_private *dev_priv,
1911 enum plane plane, enum pipe pipe)
1912{
1913 int reg;
1914 u32 val;
1915
1916 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1917 assert_pipe_enabled(dev_priv, pipe);
1918
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
00d70b15
CW		 1921 if (val & DISPLAY_PLANE_ENABLE)
1922 return;
1923
1924 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1925 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1927}
1928
b24e7179
JB		 1929/**
1930 * intel_disable_plane - disable a display plane
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to disable
1933 * @pipe: pipe consuming the data
1934 *
1935 * Disable @plane; should be an independent operation.
1936 */
1937static void intel_disable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 reg = DSPCNTR(plane);
1944 val = I915_READ(reg);
00d70b15
CW		 1945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1946 return;
1947
1948 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1949 intel_flush_display_plane(dev_priv, plane);
1950 intel_wait_for_vblank(dev_priv->dev, pipe);
1951}
1952
693db184
CW		 1953static bool need_vtd_wa(struct drm_device *dev)
1954{
1955#ifdef CONFIG_INTEL_IOMMU
1956 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1957 return true;
1958#endif
1959 return false;
1960}
1961
127bd2ac 1962int
48b956c5 1963intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1964 struct drm_i915_gem_object *obj,
919926ae 1965 struct intel_ring_buffer *pipelined)
6b95a207 1966{
ce453d81 1967 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1968 u32 alignment;
1969 int ret;
1970
05394f39 1971 switch (obj->tiling_mode) {
6b95a207 1972 case I915_TILING_NONE:
534843da
CW		 1973 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1974 alignment = 128 * 1024;
a6c45cf0 1975 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1976 alignment = 4 * 1024;
1977 else
1978 alignment = 64 * 1024;
6b95a207
KH		 1979 break;
1980 case I915_TILING_X:
1981 /* pin() will align the object as required by fence */
1982 alignment = 0;
1983 break;
1984 case I915_TILING_Y:
1985 /* FIXME: Is this true? */
1986 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1987 return -EINVAL;
1988 default:
1989 BUG();
1990 }
1991
693db184
CW		 1992 /* Note that the w/a also requires 64 PTE of padding following the
1993 * bo. We currently fill all unused PTE with the shadow page and so
1994 * we should always have valid PTE following the scanout preventing
1995 * the VT-d warning.
1996 */
1997 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1998 alignment = 256 * 1024;
1999
ce453d81 2000 dev_priv->mm.interruptible = false;
2da3b9b9 2001 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2002 if (ret)
ce453d81 2003 goto err_interruptible;
6b95a207
KH		 2004
2005 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2006 * fence, whereas 965+ only requires a fence if using
2007 * framebuffer compression. For simplicity, we always install
2008 * a fence as the cost is not that onerous.
2009 */
06d98131 2010 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2011 if (ret)
2012 goto err_unpin;
1690e1eb 2013
9a5a53b3 2014 i915_gem_object_pin_fence(obj);
6b95a207 2015
ce453d81 2016 dev_priv->mm.interruptible = true;
6b95a207 2017 return 0;
48b956c5
CW		 2018
2019err_unpin:
2020 i915_gem_object_unpin(obj);
ce453d81
CW		 2021err_interruptible:
2022 dev_priv->mm.interruptible = true;
48b956c5 2023 return ret;
6b95a207
KH		 2024}
2025
1690e1eb
CW		 2026void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2027{
2028 i915_gem_object_unpin_fence(obj);
2029 i915_gem_object_unpin(obj);
2030}
2031
c2c75131
DV		 2032/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2033 * is assumed to be a power-of-two. */
bc752862
CW		 2034unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2035 unsigned int tiling_mode,
2036 unsigned int cpp,
2037 unsigned int pitch)
c2c75131 2038{
bc752862
CW		 2039 if (tiling_mode != I915_TILING_NONE) {
2040 unsigned int tile_rows, tiles;
c2c75131 2041
bc752862
CW		 2042 tile_rows = *y / 8;
2043 *y %= 8;
c2c75131 2044
bc752862
CW		 2045 tiles = *x / (512/cpp);
2046 *x %= 512/cpp;
2047
2048 return tile_rows * pitch * 8 + tiles * 4096;
2049 } else {
2050 unsigned int offset;
2051
2052 offset = *y * pitch + *x * cpp;
2053 *y = 0;
2054 *x = (offset & 4095) / cpp;
2055 return offset & -4096;
2056 }
c2c75131
DV		 2057}
2058
17638cd6
JB		 2059static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2060 int x, int y)
81255565
JB		 2061{
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
05394f39 2066 struct drm_i915_gem_object *obj;
81255565 2067 int plane = intel_crtc->plane;
e506a0c6 2068 unsigned long linear_offset;
81255565 2069 u32 dspcntr;
5eddb70b 2070 u32 reg;
81255565
JB		 2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
2075 break;
2076 default:
2077 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2078 return -EINVAL;
2079 }
2080
2081 intel_fb = to_intel_framebuffer(fb);
2082 obj = intel_fb->obj;
81255565 2083
5eddb70b
CW		 2084 reg = DSPCNTR(plane);
2085 dspcntr = I915_READ(reg);
81255565
JB		 2086 /* Mask out pixel format bits in case we change it */
2087 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2088 switch (fb->pixel_format) {
2089 case DRM_FORMAT_C8:
81255565
JB		 2090 dspcntr |= DISPPLANE_8BPP;
2091 break;
57779d06
VS		 2092 case DRM_FORMAT_XRGB1555:
2093 case DRM_FORMAT_ARGB1555:
2094 dspcntr |= DISPPLANE_BGRX555;
81255565 2095 break;
57779d06
VS		 2096 case DRM_FORMAT_RGB565:
2097 dspcntr |= DISPPLANE_BGRX565;
2098 break;
2099 case DRM_FORMAT_XRGB8888:
2100 case DRM_FORMAT_ARGB8888:
2101 dspcntr |= DISPPLANE_BGRX888;
2102 break;
2103 case DRM_FORMAT_XBGR8888:
2104 case DRM_FORMAT_ABGR8888:
2105 dspcntr |= DISPPLANE_RGBX888;
2106 break;
2107 case DRM_FORMAT_XRGB2101010:
2108 case DRM_FORMAT_ARGB2101010:
2109 dspcntr |= DISPPLANE_BGRX101010;
2110 break;
2111 case DRM_FORMAT_XBGR2101010:
2112 case DRM_FORMAT_ABGR2101010:
2113 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2114 break;
2115 default:
baba133a 2116 BUG();
81255565 2117 }
57779d06 2118
a6c45cf0 2119 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2120 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2121 dspcntr |= DISPPLANE_TILED;
2122 else
2123 dspcntr &= ~DISPPLANE_TILED;
2124 }
2125
5eddb70b 2126 I915_WRITE(reg, dspcntr);
81255565 2127
e506a0c6 2128 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2129
c2c75131
DV		 2130 if (INTEL_INFO(dev)->gen >= 4) {
2131 intel_crtc->dspaddr_offset =
bc752862
CW		 2132 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2133 fb->bits_per_pixel / 8,
2134 fb->pitches[0]);
c2c75131
DV		 2135 linear_offset -= intel_crtc->dspaddr_offset;
2136 } else {
e506a0c6 2137 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2138 }
e506a0c6
DV		 2139
2140 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2141 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2142 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2143 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2144 I915_MODIFY_DISPBASE(DSPSURF(plane),
2145 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2146 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2147 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2148 } else
e506a0c6 2149 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2150 POSTING_READ(reg);
81255565 2151
17638cd6
JB		 2152 return 0;
2153}
2154
2155static int ironlake_update_plane(struct drm_crtc *crtc,
2156 struct drm_framebuffer *fb, int x, int y)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161 struct intel_framebuffer *intel_fb;
2162 struct drm_i915_gem_object *obj;
2163 int plane = intel_crtc->plane;
e506a0c6 2164 unsigned long linear_offset;
17638cd6
JB		 2165 u32 dspcntr;
2166 u32 reg;
2167
2168 switch (plane) {
2169 case 0:
2170 case 1:
27f8227b 2171 case 2:
17638cd6
JB		 2172 break;
2173 default:
2174 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2175 return -EINVAL;
2176 }
2177
2178 intel_fb = to_intel_framebuffer(fb);
2179 obj = intel_fb->obj;
2180
2181 reg = DSPCNTR(plane);
2182 dspcntr = I915_READ(reg);
2183 /* Mask out pixel format bits in case we change it */
2184 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2185 switch (fb->pixel_format) {
2186 case DRM_FORMAT_C8:
17638cd6
JB		 2187 dspcntr |= DISPPLANE_8BPP;
2188 break;
57779d06
VS		 2189 case DRM_FORMAT_RGB565:
2190 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2191 break;
57779d06
VS		 2192 case DRM_FORMAT_XRGB8888:
2193 case DRM_FORMAT_ARGB8888:
2194 dspcntr |= DISPPLANE_BGRX888;
2195 break;
2196 case DRM_FORMAT_XBGR8888:
2197 case DRM_FORMAT_ABGR8888:
2198 dspcntr |= DISPPLANE_RGBX888;
2199 break;
2200 case DRM_FORMAT_XRGB2101010:
2201 case DRM_FORMAT_ARGB2101010:
2202 dspcntr |= DISPPLANE_BGRX101010;
2203 break;
2204 case DRM_FORMAT_XBGR2101010:
2205 case DRM_FORMAT_ABGR2101010:
2206 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2207 break;
2208 default:
baba133a 2209 BUG();
17638cd6
JB		 2210 }
2211
2212 if (obj->tiling_mode != I915_TILING_NONE)
2213 dspcntr |= DISPPLANE_TILED;
2214 else
2215 dspcntr &= ~DISPPLANE_TILED;
2216
2217 /* must disable */
2218 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2219
2220 I915_WRITE(reg, dspcntr);
2221
e506a0c6 2222 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2223 intel_crtc->dspaddr_offset =
bc752862
CW		 2224 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2225 fb->bits_per_pixel / 8,
2226 fb->pitches[0]);
c2c75131 2227 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2228
e506a0c6
DV		 2229 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2230 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2231 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2232 I915_MODIFY_DISPBASE(DSPSURF(plane),
2233 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2234 if (IS_HASWELL(dev)) {
2235 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2236 } else {
2237 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2238 I915_WRITE(DSPLINOFF(plane), linear_offset);
2239 }
17638cd6
JB		 2240 POSTING_READ(reg);
2241
2242 return 0;
2243}
2244
2245/* Assume fb object is pinned & idle & fenced and just update base pointers */
2246static int
2247intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2248 int x, int y, enum mode_set_atomic state)
2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2252
6b8e6ed0
CW		 2253 if (dev_priv->display.disable_fbc)
2254 dev_priv->display.disable_fbc(dev);
3dec0095 2255 intel_increase_pllclock(crtc);
81255565 2256
6b8e6ed0 2257 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2258}
2259
96a02917
VS		 2260void intel_display_handle_reset(struct drm_device *dev)
2261{
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct drm_crtc *crtc;
2264
2265 /*
2266 * Flips in the rings have been nuked by the reset,
2267 * so complete all pending flips so that user space
2268 * will get its events and not get stuck.
2269 *
2270 * Also update the base address of all primary
2271 * planes to the the last fb to make sure we're
2272 * showing the correct fb after a reset.
2273 *
2274 * Need to make two loops over the crtcs so that we
2275 * don't try to grab a crtc mutex before the
2276 * pending_flip_queue really got woken up.
2277 */
2278
2279 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281 enum plane plane = intel_crtc->plane;
2282
2283 intel_prepare_page_flip(dev, plane);
2284 intel_finish_page_flip_plane(dev, plane);
2285 }
2286
2287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289
2290 mutex_lock(&crtc->mutex);
2291 if (intel_crtc->active)
2292 dev_priv->display.update_plane(crtc, crtc->fb,
2293 crtc->x, crtc->y);
2294 mutex_unlock(&crtc->mutex);
2295 }
2296}
2297
14667a4b
CW		 2298static int
2299intel_finish_fb(struct drm_framebuffer *old_fb)
2300{
2301 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2303 bool was_interruptible = dev_priv->mm.interruptible;
2304 int ret;
2305
14667a4b
CW		 2306 /* Big Hammer, we also need to ensure that any pending
2307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2308 * current scanout is retired before unpinning the old
2309 * framebuffer.
2310 *
2311 * This should only fail upon a hung GPU, in which case we
2312 * can safely continue.
2313 */
2314 dev_priv->mm.interruptible = false;
2315 ret = i915_gem_object_finish_gpu(obj);
2316 dev_priv->mm.interruptible = was_interruptible;
2317
2318 return ret;
2319}
2320
198598d0
VS		 2321static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2322{
2323 struct drm_device *dev = crtc->dev;
2324 struct drm_i915_master_private *master_priv;
2325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2326
2327 if (!dev->primary->master)
2328 return;
2329
2330 master_priv = dev->primary->master->driver_priv;
2331 if (!master_priv->sarea_priv)
2332 return;
2333
2334 switch (intel_crtc->pipe) {
2335 case 0:
2336 master_priv->sarea_priv->pipeA_x = x;
2337 master_priv->sarea_priv->pipeA_y = y;
2338 break;
2339 case 1:
2340 master_priv->sarea_priv->pipeB_x = x;
2341 master_priv->sarea_priv->pipeB_y = y;
2342 break;
2343 default:
2344 break;
2345 }
2346}
2347
5c3b82e2 2348static int
3c4fdcfb 2349intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2350 struct drm_framebuffer *fb)
79e53945
JB		 2351{
2352 struct drm_device *dev = crtc->dev;
6b8e6ed0 2353 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2355 struct drm_framebuffer *old_fb;
5c3b82e2 2356 int ret;
79e53945
JB		 2357
2358 /* no fb bound */
94352cf9 2359 if (!fb) {
a5071c2f 2360 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2361 return 0;
2362 }
2363
7eb552ae 2364 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2365 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2366 intel_crtc->plane,
7eb552ae 2367 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2368 return -EINVAL;
79e53945
JB		 2369 }
2370
5c3b82e2 2371 mutex_lock(&dev->struct_mutex);
265db958 2372 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2373 to_intel_framebuffer(fb)->obj,
919926ae 2374 NULL);
5c3b82e2
CW		 2375 if (ret != 0) {
2376 mutex_unlock(&dev->struct_mutex);
a5071c2f 2377 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2378 return ret;
2379 }
79e53945 2380
94352cf9 2381 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2382 if (ret) {
94352cf9 2383 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2384 mutex_unlock(&dev->struct_mutex);
a5071c2f 2385 DRM_ERROR("failed to update base address\n");
4e6cfefc 2386 return ret;
79e53945 2387 }
3c4fdcfb 2388
94352cf9
DV		 2389 old_fb = crtc->fb;
2390 crtc->fb = fb;
6c4c86f5
DV		 2391 crtc->x = x;
2392 crtc->y = y;
94352cf9 2393
b7f1de28
CW		 2394 if (old_fb) {
2395 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2396 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2397 }
652c393a 2398
6b8e6ed0 2399 intel_update_fbc(dev);
5c3b82e2 2400 mutex_unlock(&dev->struct_mutex);
79e53945 2401
198598d0 2402 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2403
2404 return 0;
79e53945
JB		 2405}
2406
5e84e1a4
ZW		 2407static void intel_fdi_normal_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
2413 u32 reg, temp;
2414
2415 /* enable normal train */
2416 reg = FDI_TX_CTL(pipe);
2417 temp = I915_READ(reg);
61e499bf 2418 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2419 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2420 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2421 } else {
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2424 }
5e84e1a4
ZW		 2425 I915_WRITE(reg, temp);
2426
2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 if (HAS_PCH_CPT(dev)) {
2430 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2431 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2432 } else {
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_NONE;
2435 }
2436 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2437
2438 /* wait one idle pattern time */
2439 POSTING_READ(reg);
2440 udelay(1000);
357555c0
JB		 2441
2442 /* IVB wants error correction enabled */
2443 if (IS_IVYBRIDGE(dev))
2444 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2445 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2446}
2447
01a415fd
DV		 2448static void ivb_modeset_global_resources(struct drm_device *dev)
2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct intel_crtc *pipe_B_crtc =
2452 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2453 struct intel_crtc *pipe_C_crtc =
2454 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2455 uint32_t temp;
2456
2457 /* When everything is off disable fdi C so that we could enable fdi B
2458 * with all lanes. XXX: This misses the case where a pipe is not using
2459 * any pch resources and so doesn't need any fdi lanes. */
2460 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2461 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2462 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2463
2464 temp = I915_READ(SOUTH_CHICKEN1);
2465 temp &= ~FDI_BC_BIFURCATION_SELECT;
2466 DRM_DEBUG_KMS("disabling fdi C rx\n");
2467 I915_WRITE(SOUTH_CHICKEN1, temp);
2468 }
2469}
2470
8db9d77b
ZW		 2471/* The FDI link training functions for ILK/Ibexpeak. */
2472static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2473{
2474 struct drm_device *dev = crtc->dev;
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2477 int pipe = intel_crtc->pipe;
0fc932b8 2478 int plane = intel_crtc->plane;
5eddb70b 2479 u32 reg, temp, tries;
8db9d77b 2480
0fc932b8
JB		 2481 /* FDI needs bits from pipe & plane first */
2482 assert_pipe_enabled(dev_priv, pipe);
2483 assert_plane_enabled(dev_priv, plane);
2484
e1a44743
AJ		 2485 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2486 for train result */
5eddb70b
CW		 2487 reg = FDI_RX_IMR(pipe);
2488 temp = I915_READ(reg);
e1a44743
AJ		 2489 temp &= ~FDI_RX_SYMBOL_LOCK;
2490 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2491 I915_WRITE(reg, temp);
2492 I915_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2502 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2503
5eddb70b
CW		 2504 reg = FDI_RX_CTL(pipe);
2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 temp &= ~FDI_LINK_TRAIN_NONE;
2507 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2508 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2509
2510 POSTING_READ(reg);
8db9d77b
ZW		 2511 udelay(150);
2512
5b2adf89 2513 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2514 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2515 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2516 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2517
5eddb70b 2518 reg = FDI_RX_IIR(pipe);
e1a44743 2519 for (tries = 0; tries < 5; tries++) {
5eddb70b 2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523 if ((temp & FDI_RX_BIT_LOCK)) {
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2526 break;
2527 }
8db9d77b 2528 }
e1a44743 2529 if (tries == 5)
5eddb70b 2530 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2531
2532 /* Train 2 */
5eddb70b
CW		 2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2537 I915_WRITE(reg, temp);
8db9d77b 2538
5eddb70b
CW		 2539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2543 I915_WRITE(reg, temp);
8db9d77b 2544
5eddb70b
CW		 2545 POSTING_READ(reg);
2546 udelay(150);
8db9d77b 2547
5eddb70b 2548 reg = FDI_RX_IIR(pipe);
e1a44743 2549 for (tries = 0; tries < 5; tries++) {
5eddb70b 2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2552
2553 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2554 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2555 DRM_DEBUG_KMS("FDI train 2 done.\n");
2556 break;
2557 }
8db9d77b 2558 }
e1a44743 2559 if (tries == 5)
5eddb70b 2560 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2561
2562 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2563
8db9d77b
ZW		 2564}
2565
0206e353 2566static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2567 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2568 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2569 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2570 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2571};
2572
2573/* The FDI link training functions for SNB/Cougarpoint. */
2574static void gen6_fdi_link_train(struct drm_crtc *crtc)
2575{
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 int pipe = intel_crtc->pipe;
fa37d39e 2580 u32 reg, temp, i, retry;
8db9d77b 2581
e1a44743
AJ		 2582 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2583 for train result */
5eddb70b
CW		 2584 reg = FDI_RX_IMR(pipe);
2585 temp = I915_READ(reg);
e1a44743
AJ		 2586 temp &= ~FDI_RX_SYMBOL_LOCK;
2587 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
e1a44743
AJ		 2591 udelay(150);
2592
8db9d77b 2593 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2594 reg = FDI_TX_CTL(pipe);
2595 temp = I915_READ(reg);
77ffb597
AJ		 2596 temp &= ~(7 << 19);
2597 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2601 /* SNB-B */
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2603 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2604
d74cf324
DV		 2605 I915_WRITE(FDI_RX_MISC(pipe),
2606 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2607
5eddb70b
CW		 2608 reg = FDI_RX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 if (HAS_PCH_CPT(dev)) {
2611 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2612 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2613 } else {
2614 temp &= ~FDI_LINK_TRAIN_NONE;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1;
2616 }
5eddb70b
CW		 2617 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2618
2619 POSTING_READ(reg);
8db9d77b
ZW		 2620 udelay(150);
2621
0206e353 2622 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
8db9d77b
ZW		 2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2627 I915_WRITE(reg, temp);
2628
2629 POSTING_READ(reg);
8db9d77b
ZW		 2630 udelay(500);
2631
fa37d39e
SP		 2632 for (retry = 0; retry < 5; retry++) {
2633 reg = FDI_RX_IIR(pipe);
2634 temp = I915_READ(reg);
2635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2636 if (temp & FDI_RX_BIT_LOCK) {
2637 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2638 DRM_DEBUG_KMS("FDI train 1 done.\n");
2639 break;
2640 }
2641 udelay(50);
8db9d77b 2642 }
fa37d39e
SP		 2643 if (retry < 5)
2644 break;
8db9d77b
ZW		 2645 }
2646 if (i == 4)
5eddb70b 2647 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2648
2649 /* Train 2 */
5eddb70b
CW		 2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
8db9d77b
ZW		 2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 if (IS_GEN6(dev)) {
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 /* SNB-B */
2657 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2658 }
5eddb70b 2659 I915_WRITE(reg, temp);
8db9d77b 2660
5eddb70b
CW		 2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
8db9d77b
ZW		 2663 if (HAS_PCH_CPT(dev)) {
2664 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2665 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2666 } else {
2667 temp &= ~FDI_LINK_TRAIN_NONE;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2;
2669 }
5eddb70b
CW		 2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
8db9d77b
ZW		 2673 udelay(150);
2674
0206e353 2675 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2676 reg = FDI_TX_CTL(pipe);
2677 temp = I915_READ(reg);
8db9d77b
ZW		 2678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2679 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2680 I915_WRITE(reg, temp);
2681
2682 POSTING_READ(reg);
8db9d77b
ZW		 2683 udelay(500);
2684
fa37d39e
SP		 2685 for (retry = 0; retry < 5; retry++) {
2686 reg = FDI_RX_IIR(pipe);
2687 temp = I915_READ(reg);
2688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689 if (temp & FDI_RX_SYMBOL_LOCK) {
2690 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2691 DRM_DEBUG_KMS("FDI train 2 done.\n");
2692 break;
2693 }
2694 udelay(50);
8db9d77b 2695 }
fa37d39e
SP		 2696 if (retry < 5)
2697 break;
8db9d77b
ZW		 2698 }
2699 if (i == 4)
5eddb70b 2700 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2701
2702 DRM_DEBUG_KMS("FDI train done.\n");
2703}
2704
357555c0
JB		 2705/* Manual link training for Ivy Bridge A0 parts */
2706static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2707{
2708 struct drm_device *dev = crtc->dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2711 int pipe = intel_crtc->pipe;
2712 u32 reg, temp, i;
2713
2714 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2715 for train result */
2716 reg = FDI_RX_IMR(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~FDI_RX_SYMBOL_LOCK;
2719 temp &= ~FDI_RX_BIT_LOCK;
2720 I915_WRITE(reg, temp);
2721
2722 POSTING_READ(reg);
2723 udelay(150);
2724
01a415fd
DV		 2725 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2726 I915_READ(FDI_RX_IIR(pipe)));
2727
357555c0
JB		 2728 /* enable CPU FDI TX and PCH FDI RX */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~(7 << 19);
2732 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2733 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2737 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2739
d74cf324
DV		 2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2742
357555c0
JB		 2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~FDI_LINK_TRAIN_AUTO;
2746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2747 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2748 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2749 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750
2751 POSTING_READ(reg);
2752 udelay(150);
2753
0206e353 2754 for (i = 0; i < 4; i++) {
357555c0
JB		 2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= snb_b_fdi_train_param[i];
2759 I915_WRITE(reg, temp);
2760
2761 POSTING_READ(reg);
2762 udelay(500);
2763
2764 reg = FDI_RX_IIR(pipe);
2765 temp = I915_READ(reg);
2766 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2767
2768 if (temp & FDI_RX_BIT_LOCK ||
2769 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2770 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2771 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2772 break;
2773 }
2774 }
2775 if (i == 4)
2776 DRM_ERROR("FDI train 1 fail!\n");
2777
2778 /* Train 2 */
2779 reg = FDI_TX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2783 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2785 I915_WRITE(reg, temp);
2786
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791 I915_WRITE(reg, temp);
2792
2793 POSTING_READ(reg);
2794 udelay(150);
2795
0206e353 2796 for (i = 0; i < 4; i++) {
357555c0
JB		 2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2800 temp |= snb_b_fdi_train_param[i];
2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(500);
2805
2806 reg = FDI_RX_IIR(pipe);
2807 temp = I915_READ(reg);
2808 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2809
2810 if (temp & FDI_RX_SYMBOL_LOCK) {
2811 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2812 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2813 break;
2814 }
2815 }
2816 if (i == 4)
2817 DRM_ERROR("FDI train 2 fail!\n");
2818
2819 DRM_DEBUG_KMS("FDI train done.\n");
2820}
2821
88cefb6c 2822static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2823{
88cefb6c 2824 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2825 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2826 int pipe = intel_crtc->pipe;
5eddb70b 2827 u32 reg, temp;
79e53945 2828
c64e311e 2829
c98e9dcf 2830 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2831 reg = FDI_RX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2834 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2836 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2837
2838 POSTING_READ(reg);
c98e9dcf
JB		 2839 udelay(200);
2840
2841 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp | FDI_PCDCLK);
2844
2845 POSTING_READ(reg);
c98e9dcf
JB		 2846 udelay(200);
2847
20749730
PZ		 2848 /* Enable CPU FDI TX PLL, always on for Ironlake */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2852 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2853
20749730
PZ		 2854 POSTING_READ(reg);
2855 udelay(100);
6be4a607 2856 }
0e23b99d
JB		 2857}
2858
88cefb6c
DV		 2859static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2860{
2861 struct drm_device *dev = intel_crtc->base.dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 int pipe = intel_crtc->pipe;
2864 u32 reg, temp;
2865
2866 /* Switch from PCDclk to Rawclk */
2867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2870
2871 /* Disable CPU FDI TX PLL */
2872 reg = FDI_TX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2875
2876 POSTING_READ(reg);
2877 udelay(100);
2878
2879 reg = FDI_RX_CTL(pipe);
2880 temp = I915_READ(reg);
2881 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2882
2883 /* Wait for the clocks to turn off. */
2884 POSTING_READ(reg);
2885 udelay(100);
2886}
2887
0fc932b8
JB		 2888static void ironlake_fdi_disable(struct drm_crtc *crtc)
2889{
2890 struct drm_device *dev = crtc->dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2893 int pipe = intel_crtc->pipe;
2894 u32 reg, temp;
2895
2896 /* disable CPU FDI tx and PCH FDI rx */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2900 POSTING_READ(reg);
2901
2902 reg = FDI_RX_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~(0x7 << 16);
dfd07d72 2905 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2906 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2907
2908 POSTING_READ(reg);
2909 udelay(100);
2910
2911 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2912 if (HAS_PCH_IBX(dev)) {
2913 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2914 }
0fc932b8
JB		 2915
2916 /* still set train pattern 1 */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_NONE;
2920 temp |= FDI_LINK_TRAIN_PATTERN_1;
2921 I915_WRITE(reg, temp);
2922
2923 reg = FDI_RX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 if (HAS_PCH_CPT(dev)) {
2926 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2928 } else {
2929 temp &= ~FDI_LINK_TRAIN_NONE;
2930 temp |= FDI_LINK_TRAIN_PATTERN_1;
2931 }
2932 /* BPC in FDI rx is consistent with that in PIPECONF */
2933 temp &= ~(0x07 << 16);
dfd07d72 2934 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2935 I915_WRITE(reg, temp);
2936
2937 POSTING_READ(reg);
2938 udelay(100);
2939}
2940
5bb61643
CW		 2941static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2942{
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2946 unsigned long flags;
2947 bool pending;
2948
10d83730
VS		 2949 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2950 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2951 return false;
2952
2953 spin_lock_irqsave(&dev->event_lock, flags);
2954 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2955 spin_unlock_irqrestore(&dev->event_lock, flags);
2956
2957 return pending;
2958}
2959
e6c3a2a6
CW		 2960static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2961{
0f91128d 2962 struct drm_device *dev = crtc->dev;
5bb61643 2963 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2964
2965 if (crtc->fb == NULL)
2966 return;
2967
2c10d571
DV		 2968 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2969
5bb61643
CW		 2970 wait_event(dev_priv->pending_flip_queue,
2971 !intel_crtc_has_pending_flip(crtc));
2972
0f91128d
CW		 2973 mutex_lock(&dev->struct_mutex);
2974 intel_finish_fb(crtc->fb);
2975 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2976}
2977
fc316cbe
PZ		 2978static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2979{
2980 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2981}
2982
e615efe4
ED		 2983/* Program iCLKIP clock to the desired frequency */
2984static void lpt_program_iclkip(struct drm_crtc *crtc)
2985{
2986 struct drm_device *dev = crtc->dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2989 u32 temp;
2990
09153000
DV		 2991 mutex_lock(&dev_priv->dpio_lock);
2992
e615efe4
ED		 2993 /* It is necessary to ungate the pixclk gate prior to programming
2994 * the divisors, and gate it back when it is done.
2995 */
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2997
2998 /* Disable SSCCTL */
2999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3001 SBI_SSCCTL_DISABLE,
3002 SBI_ICLK);
e615efe4
ED		 3003
3004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3005 if (crtc->mode.clock == 20000) {
3006 auxdiv = 1;
3007 divsel = 0x41;
3008 phaseinc = 0x20;
3009 } else {
3010 /* The iCLK virtual clock root frequency is in MHz,
3011 * but the crtc->mode.clock in in KHz. To get the divisors,
3012 * it is necessary to divide one by another, so we
3013 * convert the virtual clock precision to KHz here for higher
3014 * precision.
3015 */
3016 u32 iclk_virtual_root_freq = 172800 * 1000;
3017 u32 iclk_pi_range = 64;
3018 u32 desired_divisor, msb_divisor_value, pi_value;
3019
3020 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3021 msb_divisor_value = desired_divisor / iclk_pi_range;
3022 pi_value = desired_divisor % iclk_pi_range;
3023
3024 auxdiv = 0;
3025 divsel = msb_divisor_value - 2;
3026 phaseinc = pi_value;
3027 }
3028
3029 /* This should not happen with any sane values */
3030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3034
3035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3036 crtc->mode.clock,
3037 auxdiv,
3038 divsel,
3039 phasedir,
3040 phaseinc);
3041
3042 /* Program SSCDIVINTPHASE6 */
988d6ee8 3043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3051
3052 /* Program SSCAUXDIV */
988d6ee8 3053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3057
3058 /* Enable modulator and associated divider */
988d6ee8 3059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3060 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3062
3063 /* Wait for initialization time */
3064 udelay(24);
3065
3066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3067
3068 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3069}
3070
f67a559d
JB		 3071/*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3080{
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
ee7b9f93 3085 u32 reg, temp;
2c07245f 3086
e7e164db
CW		 3087 assert_transcoder_disabled(dev_priv, pipe);
3088
cd986abb
DV		 3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
c98e9dcf 3094 /* For PCH output, training FDI link */
674cf967 3095 dev_priv->display.fdi_link_train(crtc);
2c07245f 3096
572deb37
DV		 3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3100 *
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
b6b4e185 3104 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3105
303b81e0 3106 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3107 u32 sel;
4b645f14 3108
c98e9dcf 3109 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3110 switch (pipe) {
3111 default:
3112 case 0:
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3115 break;
3116 case 1:
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3119 break;
3120 case 2:
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3123 break;
d64311ab 3124 }
ee7b9f93
JB		 3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126 temp |= sel;
3127 else
3128 temp &= ~sel;
c98e9dcf 3129 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3130 }
5eddb70b 3131
d9b6cb56
JB		 3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3137
5eddb70b
CW		 3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3142
303b81e0 3143 intel_fdi_normal_train(crtc);
5e84e1a4 3144
c98e9dcf
JB		 3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3153 TRANS_DP_SYNC_MASK |
3154 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
9325c9f0 3157 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3158
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3163
3164 switch (intel_trans_dp_port_sel(crtc)) {
3165 case PCH_DP_B:
5eddb70b 3166 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3167 break;
3168 case PCH_DP_C:
5eddb70b 3169 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3170 break;
3171 case PCH_DP_D:
5eddb70b 3172 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3173 break;
3174 default:
e95d41e1 3175 BUG();
32f9d658 3176 }
2c07245f 3177
5eddb70b 3178 I915_WRITE(reg, temp);
6be4a607 3179 }
b52eb4dc 3180
b8a4f404 3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3182}
3183
1507e5bd
PZ		 3184static void lpt_pch_enable(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3190
daed2dbb 3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3192
8c52b5e8 3193 lpt_program_iclkip(crtc);
1507e5bd 3194
0540e488 3195 /* Set transcoder timing. */
daed2dbb
PZ		 3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3199
daed2dbb
PZ		 3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3204
937bb610 3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3206}
3207
ee7b9f93
JB		 3208static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209{
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212 if (pll == NULL)
3213 return;
3214
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3217 return;
3218 }
3219
3220 --pll->refcount;
3221 intel_crtc->pch_pll = NULL;
3222}
3223
3224static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225{
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3228 int i;
3229
3230 pll = intel_crtc->pch_pll;
3231 if (pll) {
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3234 goto prepare;
3235 }
3236
98b6bd99
DV		 3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3241
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3244
3245 goto found;
3246 }
3247
ee7b9f93
JB		 3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3253 continue;
3254
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3260
3261 goto found;
3262 }
3263 }
3264
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3271 goto found;
3272 }
3273 }
3274
3275 return NULL;
3276
3277found:
3278 intel_crtc->pch_pll = pll;
3279 pll->refcount++;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3283
e04c7350
CW		 3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3286 POSTING_READ(pll->pll_reg);
3287 udelay(150);
e04c7350
CW		 3288
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3291 pll->on = false;
3292 return pll;
3293}
3294
d4270e57
JB		 3295void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296{
3297 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3298 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3299 u32 temp;
3300
3301 temp = I915_READ(dslreg);
3302 udelay(500);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306 }
3307}
3308
f67a559d
JB		 3309static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3314 struct intel_encoder *encoder;
f67a559d
JB		 3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3317 u32 temp;
f67a559d 3318
08a48469
DV		 3319 WARN_ON(!crtc->enabled);
3320
f67a559d
JB		 3321 if (intel_crtc->active)
3322 return;
3323
3324 intel_crtc->active = true;
3325 intel_update_watermarks(dev);
3326
3327 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3328 temp = I915_READ(PCH_LVDS);
3329 if ((temp & LVDS_PORT_EN) == 0)
3330 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3331 }
3332
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3335 /* Note: FDI PLL enabling _must_ be done before we enable the
3336 * cpu pipes, hence this is separate from all the other fdi/pch
3337 * enabling. */
88cefb6c 3338 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3339 } else {
3340 assert_fdi_tx_disabled(dev_priv, pipe);
3341 assert_fdi_rx_disabled(dev_priv, pipe);
3342 }
f67a559d 3343
bf49ec8c
DV		 3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 if (encoder->pre_enable)
3346 encoder->pre_enable(encoder);
f67a559d
JB		 3347
3348 /* Enable panel fitting for LVDS */
3349 if (dev_priv->pch_pf_size &&
547dc041
JN		 3350 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3352 /* Force use of hard-coded filter coefficients
3353 * as some pre-programmed values are broken,
3354 * e.g. x201.
3355 */
13888d78
PZ		 3356 if (IS_IVYBRIDGE(dev))
3357 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358 PF_PIPE_SEL_IVB(pipe));
3359 else
3360 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3361 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3363 }
3364
9c54c0dd
JB		 3365 /*
3366 * On ILK+ LUT must be loaded before the pipe is running but with
3367 * clocks enabled
3368 */
3369 intel_crtc_load_lut(crtc);
3370
5bfe2ac0
DV		 3371 intel_enable_pipe(dev_priv, pipe,
3372 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3373 intel_enable_plane(dev_priv, plane, pipe);
3374
5bfe2ac0 3375 if (intel_crtc->config.has_pch_encoder)
f67a559d 3376 ironlake_pch_enable(crtc);
c98e9dcf 3377
d1ebd816 3378 mutex_lock(&dev->struct_mutex);
bed4a673 3379 intel_update_fbc(dev);
d1ebd816
BW		 3380 mutex_unlock(&dev->struct_mutex);
3381
6b383a7f 3382 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3383
fa5c73b1
DV		 3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 encoder->enable(encoder);
61b77ddd
DV		 3386
3387 if (HAS_PCH_CPT(dev))
3388 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3389
3390 /*
3391 * There seems to be a race in PCH platform hw (at least on some
3392 * outputs) where an enabled pipe still completes any pageflip right
3393 * away (as if the pipe is off) instead of waiting for vblank. As soon
3394 * as the first vblank happend, everything works as expected. Hence just
3395 * wait for one vblank before returning to avoid strange things
3396 * happening.
3397 */
3398 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3399}
3400
4f771f10
PZ		 3401static void haswell_crtc_enable(struct drm_crtc *crtc)
3402{
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406 struct intel_encoder *encoder;
3407 int pipe = intel_crtc->pipe;
3408 int plane = intel_crtc->plane;
4f771f10
PZ		 3409
3410 WARN_ON(!crtc->enabled);
3411
3412 if (intel_crtc->active)
3413 return;
3414
3415 intel_crtc->active = true;
3416 intel_update_watermarks(dev);
3417
5bfe2ac0 3418 if (intel_crtc->config.has_pch_encoder)
04945641 3419 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3420
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 if (encoder->pre_enable)
3423 encoder->pre_enable(encoder);
3424
1f544388 3425 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3426
1f544388 3427 /* Enable panel fitting for eDP */
547dc041
JN		 3428 if (dev_priv->pch_pf_size &&
3429 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3430 /* Force use of hard-coded filter coefficients
3431 * as some pre-programmed values are broken,
3432 * e.g. x201.
3433 */
54075a7d
PZ		 3434 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3435 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3436 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3437 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3438 }
3439
3440 /*
3441 * On ILK+ LUT must be loaded before the pipe is running but with
3442 * clocks enabled
3443 */
3444 intel_crtc_load_lut(crtc);
3445
1f544388 3446 intel_ddi_set_pipe_settings(crtc);
8228c251 3447 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3448
5bfe2ac0
DV		 3449 intel_enable_pipe(dev_priv, pipe,
3450 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3451 intel_enable_plane(dev_priv, plane, pipe);
3452
5bfe2ac0 3453 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3454 lpt_pch_enable(crtc);
4f771f10
PZ		 3455
3456 mutex_lock(&dev->struct_mutex);
3457 intel_update_fbc(dev);
3458 mutex_unlock(&dev->struct_mutex);
3459
3460 intel_crtc_update_cursor(crtc, true);
3461
3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->enable(encoder);
3464
4f771f10
PZ		 3465 /*
3466 * There seems to be a race in PCH platform hw (at least on some
3467 * outputs) where an enabled pipe still completes any pageflip right
3468 * away (as if the pipe is off) instead of waiting for vblank. As soon
3469 * as the first vblank happend, everything works as expected. Hence just
3470 * wait for one vblank before returning to avoid strange things
3471 * happening.
3472 */
3473 intel_wait_for_vblank(dev, intel_crtc->pipe);
3474}
3475
6be4a607
JB		 3476static void ironlake_crtc_disable(struct drm_crtc *crtc)
3477{
3478 struct drm_device *dev = crtc->dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3481 struct intel_encoder *encoder;
6be4a607
JB		 3482 int pipe = intel_crtc->pipe;
3483 int plane = intel_crtc->plane;
5eddb70b 3484 u32 reg, temp;
b52eb4dc 3485
ef9c3aee 3486
f7abfe8b
CW		 3487 if (!intel_crtc->active)
3488 return;
3489
ea9d758d
DV		 3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 encoder->disable(encoder);
3492
e6c3a2a6 3493 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3494 drm_vblank_off(dev, pipe);
6b383a7f 3495 intel_crtc_update_cursor(crtc, false);
5eddb70b 3496
b24e7179 3497 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3498
973d04f9
CW		 3499 if (dev_priv->cfb_plane == plane)
3500 intel_disable_fbc(dev);
2c07245f 3501
b24e7179 3502 intel_disable_pipe(dev_priv, pipe);
32f9d658 3503
6be4a607 3504 /* Disable PF */
9db4a9c7
JB		 3505 I915_WRITE(PF_CTL(pipe), 0);
3506 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3507
bf49ec8c
DV		 3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 if (encoder->post_disable)
3510 encoder->post_disable(encoder);
2c07245f 3511
0fc932b8 3512 ironlake_fdi_disable(crtc);
249c0e64 3513
b8a4f404 3514 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3515
6be4a607
JB		 3516 if (HAS_PCH_CPT(dev)) {
3517 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3518 reg = TRANS_DP_CTL(pipe);
3519 temp = I915_READ(reg);
3520 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3521 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3522 I915_WRITE(reg, temp);
6be4a607
JB		 3523
3524 /* disable DPLL_SEL */
3525 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3526 switch (pipe) {
3527 case 0:
d64311ab 3528 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3529 break;
3530 case 1:
6be4a607 3531 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3532 break;
3533 case 2:
4b645f14 3534 /* C shares PLL A or B */
d64311ab 3535 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3536 break;
3537 default:
3538 BUG(); /* wtf */
3539 }
6be4a607 3540 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3541 }
e3421a18 3542
6be4a607 3543 /* disable PCH DPLL */
ee7b9f93 3544 intel_disable_pch_pll(intel_crtc);
8db9d77b 3545
88cefb6c 3546 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3547
f7abfe8b 3548 intel_crtc->active = false;
6b383a7f 3549 intel_update_watermarks(dev);
d1ebd816
BW		 3550
3551 mutex_lock(&dev->struct_mutex);
6b383a7f 3552 intel_update_fbc(dev);
d1ebd816 3553 mutex_unlock(&dev->struct_mutex);
6be4a607 3554}
1b3c7a47 3555
4f771f10 3556static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3557{
4f771f10
PZ		 3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3561 struct intel_encoder *encoder;
3562 int pipe = intel_crtc->pipe;
3563 int plane = intel_crtc->plane;
ad80a810 3564 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3565 bool is_pch_port;
ee7b9f93 3566
4f771f10
PZ		 3567 if (!intel_crtc->active)
3568 return;
3569
83616634
PZ		 3570 is_pch_port = haswell_crtc_driving_pch(crtc);
3571
4f771f10
PZ		 3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 encoder->disable(encoder);
3574
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577 intel_crtc_update_cursor(crtc, false);
3578
3579 intel_disable_plane(dev_priv, plane, pipe);
3580
3581 if (dev_priv->cfb_plane == plane)
3582 intel_disable_fbc(dev);
3583
3584 intel_disable_pipe(dev_priv, pipe);
3585
ad80a810 3586 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3587
3588 /* Disable PF */
3589 I915_WRITE(PF_CTL(pipe), 0);
3590 I915_WRITE(PF_WIN_SZ(pipe), 0);
3591
1f544388 3592 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3593
3594 for_each_encoder_on_crtc(dev, crtc, encoder)
3595 if (encoder->post_disable)
3596 encoder->post_disable(encoder);
3597
83616634 3598 if (is_pch_port) {
ab4d966c 3599 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3600 intel_ddi_fdi_disable(crtc);
83616634 3601 }
4f771f10
PZ		 3602
3603 intel_crtc->active = false;
3604 intel_update_watermarks(dev);
3605
3606 mutex_lock(&dev->struct_mutex);
3607 intel_update_fbc(dev);
3608 mutex_unlock(&dev->struct_mutex);
3609}
3610
ee7b9f93
JB		 3611static void ironlake_crtc_off(struct drm_crtc *crtc)
3612{
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 intel_put_pch_pll(intel_crtc);
3615}
3616
6441ab5f
PZ		 3617static void haswell_crtc_off(struct drm_crtc *crtc)
3618{
a5c961d1
PZ		 3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620
3621 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3622 * start using it. */
1a240d4d 3623 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3624
6441ab5f
PZ		 3625 intel_ddi_put_crtc_pll(crtc);
3626}
3627
02e792fb
DV		 3628static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3629{
02e792fb 3630 if (!enable && intel_crtc->overlay) {
23f09ce3 3631 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3632 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3633
23f09ce3 3634 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3635 dev_priv->mm.interruptible = false;
3636 (void) intel_overlay_switch_off(intel_crtc->overlay);
3637 dev_priv->mm.interruptible = true;
23f09ce3 3638 mutex_unlock(&dev->struct_mutex);
02e792fb 3639 }
02e792fb 3640
5dcdbcb0
CW		 3641 /* Let userspace switch the overlay on again. In most cases userspace
3642 * has to recompute where to put it anyway.
3643 */
02e792fb
DV		 3644}
3645
61bc95c1
EE		 3646/**
3647 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3648 * cursor plane briefly if not already running after enabling the display
3649 * plane.
3650 * This workaround avoids occasional blank screens when self refresh is
3651 * enabled.
3652 */
3653static void
3654g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3655{
3656 u32 cntl = I915_READ(CURCNTR(pipe));
3657
3658 if ((cntl & CURSOR_MODE) == 0) {
3659 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3660
3661 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3662 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3663 intel_wait_for_vblank(dev_priv->dev, pipe);
3664 I915_WRITE(CURCNTR(pipe), cntl);
3665 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3666 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3667 }
3668}
3669
0b8765c6 3670static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3671{
3672 struct drm_device *dev = crtc->dev;
79e53945
JB		 3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3675 struct intel_encoder *encoder;
79e53945 3676 int pipe = intel_crtc->pipe;
80824003 3677 int plane = intel_crtc->plane;
79e53945 3678
08a48469
DV		 3679 WARN_ON(!crtc->enabled);
3680
f7abfe8b
CW		 3681 if (intel_crtc->active)
3682 return;
3683
3684 intel_crtc->active = true;
6b383a7f
CW		 3685 intel_update_watermarks(dev);
3686
63d7bbe9 3687 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3688
3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_enable)
3691 encoder->pre_enable(encoder);
3692
040484af 3693 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3694 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3695 if (IS_G4X(dev))
3696 g4x_fixup_plane(dev_priv, pipe);
79e53945 3697
0b8765c6 3698 intel_crtc_load_lut(crtc);
bed4a673 3699 intel_update_fbc(dev);
79e53945 3700
0b8765c6
JB		 3701 /* Give the overlay scaler a chance to enable if it's on this pipe */
3702 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3703 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3704
fa5c73b1
DV		 3705 for_each_encoder_on_crtc(dev, crtc, encoder)
3706 encoder->enable(encoder);
0b8765c6 3707}
79e53945 3708
0b8765c6
JB		 3709static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
0b8765c6
JB		 3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
24a1f16d 3717 u32 pctl;
b690e96c 3718
ef9c3aee 3719
f7abfe8b
CW		 3720 if (!intel_crtc->active)
3721 return;
3722
ea9d758d
DV		 3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->disable(encoder);
3725
0b8765c6 3726 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3727 intel_crtc_wait_for_pending_flips(crtc);
3728 drm_vblank_off(dev, pipe);
0b8765c6 3729 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3730 intel_crtc_update_cursor(crtc, false);
0b8765c6 3731
973d04f9
CW		 3732 if (dev_priv->cfb_plane == plane)
3733 intel_disable_fbc(dev);
79e53945 3734
b24e7179 3735 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3736 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3737
3738 /* Disable pannel fitter if it is on this pipe. */
3739 pctl = I915_READ(PFIT_CONTROL);
3740 if ((pctl & PFIT_ENABLE) &&
3741 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3742 I915_WRITE(PFIT_CONTROL, 0);
3743
63d7bbe9 3744 intel_disable_pll(dev_priv, pipe);
0b8765c6 3745
f7abfe8b 3746 intel_crtc->active = false;
6b383a7f
CW		 3747 intel_update_fbc(dev);
3748 intel_update_watermarks(dev);
0b8765c6
JB		 3749}
3750
ee7b9f93
JB		 3751static void i9xx_crtc_off(struct drm_crtc *crtc)
3752{
3753}
3754
976f8a20
DV		 3755static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756 bool enabled)
2c07245f
ZW		 3757{
3758 struct drm_device *dev = crtc->dev;
3759 struct drm_i915_master_private *master_priv;
3760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761 int pipe = intel_crtc->pipe;
79e53945
JB		 3762
3763 if (!dev->primary->master)
3764 return;
3765
3766 master_priv = dev->primary->master->driver_priv;
3767 if (!master_priv->sarea_priv)
3768 return;
3769
79e53945
JB		 3770 switch (pipe) {
3771 case 0:
3772 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 case 1:
3776 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778 break;
3779 default:
9db4a9c7 3780 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3781 break;
3782 }
79e53945
JB		 3783}
3784
976f8a20
DV		 3785/**
3786 * Sets the power management mode of the pipe and plane.
3787 */
3788void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_encoder *intel_encoder;
3793 bool enable = false;
3794
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796 enable |= intel_encoder->connectors_active;
3797
3798 if (enable)
3799 dev_priv->display.crtc_enable(crtc);
3800 else
3801 dev_priv->display.crtc_disable(crtc);
3802
3803 intel_crtc_update_sarea(crtc, enable);
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3812
976f8a20
DV		 3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3815
7b9f35a6 3816 intel_crtc->eld_vld = false;
976f8a20
DV		 3817 dev_priv->display.crtc_disable(crtc);
3818 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3819 dev_priv->display.off(crtc);
3820
931872fc
CW		 3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3823
3824 if (crtc->fb) {
3825 mutex_lock(&dev->struct_mutex);
1690e1eb 3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3827 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3828 crtc->fb = NULL;
3829 }
3830
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3834 continue;
3835
3836 if (connector->encoder->crtc != crtc)
3837 continue;
3838
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3841 }
3842}
3843
a261b246 3844void intel_modeset_disable(struct drm_device *dev)
79e53945 3845{
a261b246
DV		 3846 struct drm_crtc *crtc;
3847
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849 if (crtc->enabled)
3850 intel_crtc_disable(crtc);
3851 }
79e53945
JB		 3852}
3853
ea5b213a 3854void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3855{
4ef69c7a 3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3857
ea5b213a
CW		 3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
7e7d76c3
JB		 3860}
3861
5ab432ef
DV		 3862/* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3866{
5ab432ef
DV		 3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
b2cabb0e 3870 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3871 } else {
3872 encoder->connectors_active = false;
3873
b2cabb0e 3874 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3875 }
79e53945
JB		 3876}
3877
0a91ca29
DV		 3878/* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
b980514c 3880static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3881{
0a91ca29
DV		 3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
79e53945
JB		 3911}
3912
5ab432ef
DV		 3913/* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3916{
5ab432ef 3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3918
5ab432ef
DV		 3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
d4270e57 3922
5ab432ef
DV		 3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
8af6cf88 3932 WARN_ON(encoder->connectors_active != false);
0a91ca29 3933
b980514c 3934 intel_modeset_check_state(connector->dev);
79e53945
JB		 3935}
3936
f0947c37
DV		 3937/* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3941{
24929352 3942 enum pipe pipe = 0;
f0947c37 3943 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3944
f0947c37 3945 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3946}
3947
b8cecdf5
DV		 3948static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3949 struct intel_crtc_config *pipe_config)
79e53945 3950{
2c07245f 3951 struct drm_device *dev = crtc->dev;
b8cecdf5 3952 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3953
bad720ff 3954 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3955 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3956 if (pipe_config->requested_mode.clock * 3
3957 > IRONLAKE_FDI_FREQ * 4)
2377b741 3958 return false;
2c07245f 3959 }
89749350 3960
f9bef081
DV		 3961 /* All interlaced capable intel hw wants timings in frames. Note though
3962 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963 * timings, so we need to be careful not to clobber these.*/
7ae89233 3964 if (!pipe_config->timings_set)
f9bef081 3965 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3966
44f46b42
CW		 3967 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968 * with a hsync front porch of 0.
3969 */
3970 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3972 return false;
3973
5d2d38dd
DV		 3974 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3975 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3976 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3977 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3978 * for lvds. */
3979 pipe_config->pipe_bpp = 8*3;
3980 }
3981
79e53945
JB		 3982 return true;
3983}
3984
25eb05fc
JB		 3985static int valleyview_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 400000; /* FIXME */
3988}
3989
e70236a8
JB		 3990static int i945_get_display_clock_speed(struct drm_device *dev)
3991{
3992 return 400000;
3993}
79e53945 3994
e70236a8 3995static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3996{
e70236a8
JB		 3997 return 333000;
3998}
79e53945 3999
e70236a8
JB		 4000static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4001{
4002 return 200000;
4003}
79e53945 4004
e70236a8
JB		 4005static int i915gm_get_display_clock_speed(struct drm_device *dev)
4006{
4007 u16 gcfgc = 0;
79e53945 4008
e70236a8
JB		 4009 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4010
4011 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4012 return 133000;
4013 else {
4014 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4015 case GC_DISPLAY_CLOCK_333_MHZ:
4016 return 333000;
4017 default:
4018 case GC_DISPLAY_CLOCK_190_200_MHZ:
4019 return 190000;
79e53945 4020 }
e70236a8
JB		 4021 }
4022}
4023
4024static int i865_get_display_clock_speed(struct drm_device *dev)
4025{
4026 return 266000;
4027}
4028
4029static int i855_get_display_clock_speed(struct drm_device *dev)
4030{
4031 u16 hpllcc = 0;
4032 /* Assume that the hardware is in the high speed state. This
4033 * should be the default.
4034 */
4035 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4036 case GC_CLOCK_133_200:
4037 case GC_CLOCK_100_200:
4038 return 200000;
4039 case GC_CLOCK_166_250:
4040 return 250000;
4041 case GC_CLOCK_100_133:
79e53945 4042 return 133000;
e70236a8 4043 }
79e53945 4044
e70236a8
JB		 4045 /* Shouldn't happen */
4046 return 0;
4047}
79e53945 4048
e70236a8
JB		 4049static int i830_get_display_clock_speed(struct drm_device *dev)
4050{
4051 return 133000;
79e53945
JB		 4052}
4053
2c07245f 4054static void
e69d0bc1 4055intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4056{
4057 while (*num > 0xffffff || *den > 0xffffff) {
4058 *num >>= 1;
4059 *den >>= 1;
4060 }
4061}
4062
e69d0bc1
DV		 4063void
4064intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4065 int pixel_clock, int link_clock,
4066 struct intel_link_m_n *m_n)
2c07245f 4067{
e69d0bc1 4068 m_n->tu = 64;
22ed1113
CW		 4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4071 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4072 m_n->link_m = pixel_clock;
4073 m_n->link_n = link_clock;
e69d0bc1 4074 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4075}
4076
a7615030
CW		 4077static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4078{
72bbe58c
KP		 4079 if (i915_panel_use_ssc >= 0)
4080 return i915_panel_use_ssc != 0;
4081 return dev_priv->lvds_use_ssc
435793df 4082 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4083}
4084
a0c4da24
JB		 4085static int vlv_get_refclk(struct drm_crtc *crtc)
4086{
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 int refclk = 27000; /* for DP & HDMI */
4090
4091 return 100000; /* only one validated so far */
4092
4093 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4094 refclk = 96000;
4095 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4096 if (intel_panel_use_ssc(dev_priv))
4097 refclk = 100000;
4098 else
4099 refclk = 96000;
4100 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4101 refclk = 100000;
4102 }
4103
4104 return refclk;
4105}
4106
c65d77d8
JB		 4107static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4108{
4109 struct drm_device *dev = crtc->dev;
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4111 int refclk;
4112
a0c4da24
JB		 4113 if (IS_VALLEYVIEW(dev)) {
4114 refclk = vlv_get_refclk(crtc);
4115 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4116 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4117 refclk = dev_priv->lvds_ssc_freq * 1000;
4118 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4119 refclk / 1000);
4120 } else if (!IS_GEN2(dev)) {
4121 refclk = 96000;
4122 } else {
4123 refclk = 48000;
4124 }
4125
4126 return refclk;
4127}
4128
4129static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4130 intel_clock_t *clock)
4131{
4132 /* SDVO TV has fixed PLL values depend on its clock range,
4133 this mirrors vbios setting. */
4134 if (adjusted_mode->clock >= 100000
4135 && adjusted_mode->clock < 140500) {
4136 clock->p1 = 2;
4137 clock->p2 = 10;
4138 clock->n = 3;
4139 clock->m1 = 16;
4140 clock->m2 = 8;
4141 } else if (adjusted_mode->clock >= 140500
4142 && adjusted_mode->clock <= 200000) {
4143 clock->p1 = 1;
4144 clock->p2 = 10;
4145 clock->n = 6;
4146 clock->m1 = 12;
4147 clock->m2 = 8;
4148 }
4149}
4150
a7516a05
JB		 4151static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4152 intel_clock_t *clock,
4153 intel_clock_t *reduced_clock)
4154{
4155 struct drm_device *dev = crtc->dev;
4156 struct drm_i915_private *dev_priv = dev->dev_private;
4157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4158 int pipe = intel_crtc->pipe;
4159 u32 fp, fp2 = 0;
4160
4161 if (IS_PINEVIEW(dev)) {
4162 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4163 if (reduced_clock)
4164 fp2 = (1 << reduced_clock->n) << 16 |
4165 reduced_clock->m1 << 8 | reduced_clock->m2;
4166 } else {
4167 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4168 if (reduced_clock)
4169 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4170 reduced_clock->m2;
4171 }
4172
4173 I915_WRITE(FP0(pipe), fp);
4174
4175 intel_crtc->lowfreq_avail = false;
4176 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4177 reduced_clock && i915_powersave) {
4178 I915_WRITE(FP1(pipe), fp2);
4179 intel_crtc->lowfreq_avail = true;
4180 } else {
4181 I915_WRITE(FP1(pipe), fp);
4182 }
4183}
4184
a0c4da24 4185static void vlv_update_pll(struct drm_crtc *crtc,
a0c4da24 4186 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4187 int num_connectors)
a0c4da24
JB		 4188{
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4192 struct drm_display_mode *adjusted_mode =
4193 &intel_crtc->config.adjusted_mode;
4194 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
a0c4da24
JB		 4195 int pipe = intel_crtc->pipe;
4196 u32 dpll, mdiv, pdiv;
4197 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4198 bool is_sdvo;
4199 u32 temp;
a0c4da24 4200
09153000
DV		 4201 mutex_lock(&dev_priv->dpio_lock);
4202
2a8f64ca
VP		 4203 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4204 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4205
2a8f64ca
VP		 4206 dpll = DPLL_VGA_MODE_DIS;
4207 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4208 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4209 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4210
4211 I915_WRITE(DPLL(pipe), dpll);
4212 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4213
4214 bestn = clock->n;
4215 bestm1 = clock->m1;
4216 bestm2 = clock->m2;
4217 bestp1 = clock->p1;
4218 bestp2 = clock->p2;
4219
2a8f64ca
VP		 4220 /*
4221 * In Valleyview PLL and program lane counter registers are exposed
4222 * through DPIO interface
4223 */
a0c4da24
JB		 4224 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4225 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4226 mdiv |= ((bestn << DPIO_N_SHIFT));
4227 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4228 mdiv |= (1 << DPIO_K_SHIFT);
4229 mdiv |= DPIO_ENABLE_CALIBRATION;
4230 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4231
4232 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4233
2a8f64ca 4234 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4235 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4236 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4237 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4238 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4239
2a8f64ca 4240 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4241
4242 dpll |= DPLL_VCO_ENABLE;
4243 I915_WRITE(DPLL(pipe), dpll);
4244 POSTING_READ(DPLL(pipe));
4245 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4246 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4247
2a8f64ca
VP		 4248 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4249
4250 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4251 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4252
4253 I915_WRITE(DPLL(pipe), dpll);
4254
4255 /* Wait for the clocks to stabilize. */
4256 POSTING_READ(DPLL(pipe));
4257 udelay(150);
a0c4da24 4258
2a8f64ca
VP		 4259 temp = 0;
4260 if (is_sdvo) {
6cc5f341
DV		 4261 temp = 0;
4262 if (intel_crtc->config.pixel_multiplier > 1) {
4263 temp = (intel_crtc->config.pixel_multiplier - 1)
4264 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4265 }
a0c4da24 4266 }
2a8f64ca
VP		 4267 I915_WRITE(DPLL_MD(pipe), temp);
4268 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4269
2a8f64ca
VP		 4270 /* Now program lane control registers */
4271 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4272 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4273 {
4274 temp = 0x1000C4;
4275 if(pipe == 1)
4276 temp |= (1 << 21);
4277 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4278 }
4279 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4280 {
4281 temp = 0x1000C4;
4282 if(pipe == 1)
4283 temp |= (1 << 21);
4284 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4285 }
09153000
DV		 4286
4287 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4288}
4289
eb1cbe48 4290static void i9xx_update_pll(struct drm_crtc *crtc,
eb1cbe48
DV		 4291 intel_clock_t *clock, intel_clock_t *reduced_clock,
4292 int num_connectors)
4293{
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 4297 struct drm_display_mode *adjusted_mode =
4298 &intel_crtc->config.adjusted_mode;
4299 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
dafd226c 4300 struct intel_encoder *encoder;
eb1cbe48
DV		 4301 int pipe = intel_crtc->pipe;
4302 u32 dpll;
4303 bool is_sdvo;
4304
2a8f64ca
VP		 4305 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4306
eb1cbe48
DV		 4307 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4308 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4309
4310 dpll = DPLL_VGA_MODE_DIS;
4311
4312 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4313 dpll |= DPLLB_MODE_LVDS;
4314 else
4315 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4316
eb1cbe48 4317 if (is_sdvo) {
6cc5f341
DV		 4318 if ((intel_crtc->config.pixel_multiplier > 1) &&
4319 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4320 dpll |= (intel_crtc->config.pixel_multiplier - 1)
4321 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4322 }
4323 dpll |= DPLL_DVO_HIGH_SPEED;
4324 }
4325 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4326 dpll |= DPLL_DVO_HIGH_SPEED;
4327
4328 /* compute bitmask from p1 value */
4329 if (IS_PINEVIEW(dev))
4330 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4331 else {
4332 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4333 if (IS_G4X(dev) && reduced_clock)
4334 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4335 }
4336 switch (clock->p2) {
4337 case 5:
4338 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4339 break;
4340 case 7:
4341 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4342 break;
4343 case 10:
4344 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4345 break;
4346 case 14:
4347 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4348 break;
4349 }
4350 if (INTEL_INFO(dev)->gen >= 4)
4351 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4352
4353 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4354 dpll |= PLL_REF_INPUT_TVCLKINBC;
4355 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4356 /* XXX: just matching BIOS for now */
4357 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4358 dpll |= 3;
4359 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4360 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4361 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4362 else
4363 dpll |= PLL_REF_INPUT_DREFCLK;
4364
4365 dpll |= DPLL_VCO_ENABLE;
4366 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4367 POSTING_READ(DPLL(pipe));
4368 udelay(150);
4369
dafd226c
DV		 4370 for_each_encoder_on_crtc(dev, crtc, encoder)
4371 if (encoder->pre_pll_enable)
4372 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4373
4374 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4375 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4376
4377 I915_WRITE(DPLL(pipe), dpll);
4378
4379 /* Wait for the clocks to stabilize. */
4380 POSTING_READ(DPLL(pipe));
4381 udelay(150);
4382
4383 if (INTEL_INFO(dev)->gen >= 4) {
4384 u32 temp = 0;
4385 if (is_sdvo) {
6cc5f341
DV		 4386 temp = 0;
4387 if (intel_crtc->config.pixel_multiplier > 1) {
4388 temp = (intel_crtc->config.pixel_multiplier - 1)
4389 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4390 }
eb1cbe48
DV		 4391 }
4392 I915_WRITE(DPLL_MD(pipe), temp);
4393 } else {
4394 /* The pixel multiplier can only be updated once the
4395 * DPLL is enabled and the clocks are stable.
4396 *
4397 * So write it again.
4398 */
4399 I915_WRITE(DPLL(pipe), dpll);
4400 }
4401}
4402
4403static void i8xx_update_pll(struct drm_crtc *crtc,
4404 struct drm_display_mode *adjusted_mode,
2a8f64ca 4405 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4406 int num_connectors)
4407{
4408 struct drm_device *dev = crtc->dev;
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4411 struct intel_encoder *encoder;
eb1cbe48
DV		 4412 int pipe = intel_crtc->pipe;
4413 u32 dpll;
4414
2a8f64ca
VP		 4415 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4416
eb1cbe48
DV		 4417 dpll = DPLL_VGA_MODE_DIS;
4418
4419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4420 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4421 } else {
4422 if (clock->p1 == 2)
4423 dpll |= PLL_P1_DIVIDE_BY_TWO;
4424 else
4425 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4426 if (clock->p2 == 4)
4427 dpll |= PLL_P2_DIVIDE_BY_4;
4428 }
4429
83f377ab 4430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4431 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4432 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4433 else
4434 dpll |= PLL_REF_INPUT_DREFCLK;
4435
4436 dpll |= DPLL_VCO_ENABLE;
4437 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4438 POSTING_READ(DPLL(pipe));
4439 udelay(150);
4440
dafd226c
DV		 4441 for_each_encoder_on_crtc(dev, crtc, encoder)
4442 if (encoder->pre_pll_enable)
4443 encoder->pre_pll_enable(encoder);
eb1cbe48 4444
5b5896e4
DV		 4445 I915_WRITE(DPLL(pipe), dpll);
4446
4447 /* Wait for the clocks to stabilize. */
4448 POSTING_READ(DPLL(pipe));
4449 udelay(150);
4450
eb1cbe48
DV		 4451 /* The pixel multiplier can only be updated once the
4452 * DPLL is enabled and the clocks are stable.
4453 *
4454 * So write it again.
4455 */
4456 I915_WRITE(DPLL(pipe), dpll);
4457}
4458
b0e77b9c
PZ		 4459static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4460 struct drm_display_mode *mode,
4461 struct drm_display_mode *adjusted_mode)
4462{
4463 struct drm_device *dev = intel_crtc->base.dev;
4464 struct drm_i915_private *dev_priv = dev->dev_private;
4465 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4466 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4467 uint32_t vsyncshift;
4468
4469 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4470 /* the chip adds 2 halflines automatically */
4471 adjusted_mode->crtc_vtotal -= 1;
4472 adjusted_mode->crtc_vblank_end -= 1;
4473 vsyncshift = adjusted_mode->crtc_hsync_start
4474 - adjusted_mode->crtc_htotal / 2;
4475 } else {
4476 vsyncshift = 0;
4477 }
4478
4479 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4480 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4481
fe2b8f9d 4482 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4483 (adjusted_mode->crtc_hdisplay - 1) |
4484 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4485 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4486 (adjusted_mode->crtc_hblank_start - 1) |
4487 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4488 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4489 (adjusted_mode->crtc_hsync_start - 1) |
4490 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4491
fe2b8f9d 4492 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4493 (adjusted_mode->crtc_vdisplay - 1) |
4494 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4495 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4496 (adjusted_mode->crtc_vblank_start - 1) |
4497 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4498 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4499 (adjusted_mode->crtc_vsync_start - 1) |
4500 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4501
b5e508d4
PZ		 4502 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4503 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4504 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4505 * bits. */
4506 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4507 (pipe == PIPE_B || pipe == PIPE_C))
4508 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4509
b0e77b9c
PZ		 4510 /* pipesrc controls the size that is scaled from, which should
4511 * always be the user's requested size.
4512 */
4513 I915_WRITE(PIPESRC(pipe),
4514 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4515}
4516
f564048e 4517static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4518 int x, int y,
94352cf9 4519 struct drm_framebuffer *fb)
79e53945
JB		 4520{
4521 struct drm_device *dev = crtc->dev;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4524 struct drm_display_mode *adjusted_mode =
4525 &intel_crtc->config.adjusted_mode;
4526 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4527 int pipe = intel_crtc->pipe;
80824003 4528 int plane = intel_crtc->plane;
c751ce4f 4529 int refclk, num_connectors = 0;
652c393a 4530 intel_clock_t clock, reduced_clock;
b0e77b9c 4531 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4532 bool ok, has_reduced_clock = false, is_sdvo = false;
4533 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4534 struct intel_encoder *encoder;
d4906093 4535 const intel_limit_t *limit;
5c3b82e2 4536 int ret;
79e53945 4537
6c2b7c12 4538 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4539 switch (encoder->type) {
79e53945
JB		 4540 case INTEL_OUTPUT_LVDS:
4541 is_lvds = true;
4542 break;
4543 case INTEL_OUTPUT_SDVO:
7d57382e 4544 case INTEL_OUTPUT_HDMI:
79e53945 4545 is_sdvo = true;
5eddb70b 4546 if (encoder->needs_tv_clock)
e2f0ba97 4547 is_tv = true;
79e53945 4548 break;
79e53945
JB		 4549 case INTEL_OUTPUT_TVOUT:
4550 is_tv = true;
4551 break;
a4fc5ed6
KP		 4552 case INTEL_OUTPUT_DISPLAYPORT:
4553 is_dp = true;
4554 break;
79e53945 4555 }
43565a06 4556
c751ce4f 4557 num_connectors++;
79e53945
JB		 4558 }
4559
c65d77d8 4560 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4561
d4906093
ML		 4562 /*
4563 * Returns a set of divisors for the desired target clock with the given
4564 * refclk, or FALSE. The returned values represent the clock equation:
4565 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4566 */
1b894b59 4567 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4568 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4569 &clock);
79e53945
JB		 4570 if (!ok) {
4571 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4572 return -EINVAL;
79e53945
JB		 4573 }
4574
cda4b7d3 4575 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4576 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4577
ddc9003c 4578 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4579 /*
4580 * Ensure we match the reduced clock's P to the target clock.
4581 * If the clocks don't match, we can't switch the display clock
4582 * by using the FP0/FP1. In such case we will disable the LVDS
4583 * downclock feature.
4584 */
ddc9003c 4585 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4586 dev_priv->lvds_downclock,
4587 refclk,
cec2f356 4588 &clock,
5eddb70b 4589 &reduced_clock);
7026d4ac
ZW		 4590 }
4591
c65d77d8
JB		 4592 if (is_sdvo && is_tv)
4593 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4594
eb1cbe48 4595 if (IS_GEN2(dev))
2a8f64ca
VP		 4596 i8xx_update_pll(crtc, adjusted_mode, &clock,
4597 has_reduced_clock ? &reduced_clock : NULL,
4598 num_connectors);
a0c4da24 4599 else if (IS_VALLEYVIEW(dev))
6cc5f341 4600 vlv_update_pll(crtc, &clock,
2a8f64ca
VP		 4601 has_reduced_clock ? &reduced_clock : NULL,
4602 num_connectors);
79e53945 4603 else
6cc5f341 4604 i9xx_update_pll(crtc, &clock,
eb1cbe48
DV		 4605 has_reduced_clock ? &reduced_clock : NULL,
4606 num_connectors);
79e53945
JB		 4607
4608 /* setup pipeconf */
5eddb70b 4609 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4610
4611 /* Set up the display plane register */
4612 dspcntr = DISPPLANE_GAMMA_ENABLE;
4613
da6ecc5d
JB		 4614 if (!IS_VALLEYVIEW(dev)) {
4615 if (pipe == 0)
4616 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4617 else
4618 dspcntr |= DISPPLANE_SEL_PIPE_B;
4619 }
79e53945 4620
a6c45cf0 4621 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4622 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4623 * core speed.
4624 *
4625 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4626 * pipe == 0 check?
4627 */
e70236a8
JB		 4628 if (mode->clock >
4629 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4630 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4631 else
5eddb70b 4632 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4633 }
4634
3b5c78a3 4635 /* default to 8bpc */
dfd07d72 4636 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4637 if (is_dp) {
965e0c48 4638 if (intel_crtc->config.dither) {
dfd07d72 4639 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4640 PIPECONF_DITHER_EN |
4641 PIPECONF_DITHER_TYPE_SP;
4642 }
4643 }
4644
19c03924 4645 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
965e0c48 4646 if (intel_crtc->config.dither) {
dfd07d72 4647 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4648 PIPECONF_ENABLE |
4649 I965_PIPECONF_ACTIVE;
4650 }
4651 }
4652
28c97730 4653 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4654 drm_mode_debug_printmodeline(mode);
4655
a7516a05
JB		 4656 if (HAS_PIPE_CXSR(dev)) {
4657 if (intel_crtc->lowfreq_avail) {
28c97730 4658 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4659 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4660 } else {
28c97730 4661 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4662 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4663 }
4664 }
4665
617cf884 4666 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4667 if (!IS_GEN2(dev) &&
b0e77b9c 4668 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4669 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4670 else
617cf884 4671 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4672
b0e77b9c 4673 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4674
4675 /* pipesrc and dspsize control the size that is scaled from,
4676 * which should always be the user's requested size.
79e53945 4677 */
929c77fb
EA		 4678 I915_WRITE(DSPSIZE(plane),
4679 ((mode->vdisplay - 1) << 16) |
4680 (mode->hdisplay - 1));
4681 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4682
f564048e
EA		 4683 I915_WRITE(PIPECONF(pipe), pipeconf);
4684 POSTING_READ(PIPECONF(pipe));
929c77fb 4685 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4686
4687 intel_wait_for_vblank(dev, pipe);
4688
f564048e
EA		 4689 I915_WRITE(DSPCNTR(plane), dspcntr);
4690 POSTING_READ(DSPCNTR(plane));
4691
94352cf9 4692 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4693
4694 intel_update_watermarks(dev);
4695
f564048e
EA		 4696 return ret;
4697}
4698
dde86e2d 4699static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4700{
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4703 struct intel_encoder *encoder;
13d83a67
JB		 4704 u32 temp;
4705 bool has_lvds = false;
199e5d79
KP		 4706 bool has_cpu_edp = false;
4707 bool has_pch_edp = false;
4708 bool has_panel = false;
99eb6a01
KP		 4709 bool has_ck505 = false;
4710 bool can_ssc = false;
13d83a67
JB		 4711
4712 /* We need to take the global config into account */
199e5d79
KP		 4713 list_for_each_entry(encoder, &mode_config->encoder_list,
4714 base.head) {
4715 switch (encoder->type) {
4716 case INTEL_OUTPUT_LVDS:
4717 has_panel = true;
4718 has_lvds = true;
4719 break;
4720 case INTEL_OUTPUT_EDP:
4721 has_panel = true;
4722 if (intel_encoder_is_pch_edp(&encoder->base))
4723 has_pch_edp = true;
4724 else
4725 has_cpu_edp = true;
4726 break;
13d83a67
JB		 4727 }
4728 }
4729
99eb6a01
KP		 4730 if (HAS_PCH_IBX(dev)) {
4731 has_ck505 = dev_priv->display_clock_mode;
4732 can_ssc = has_ck505;
4733 } else {
4734 has_ck505 = false;
4735 can_ssc = true;
4736 }
4737
4738 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4739 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4740 has_ck505);
13d83a67
JB		 4741
4742 /* Ironlake: try to setup display ref clock before DPLL
4743 * enabling. This is only under driver's control after
4744 * PCH B stepping, previous chipset stepping should be
4745 * ignoring this setting.
4746 */
4747 temp = I915_READ(PCH_DREF_CONTROL);
4748 /* Always enable nonspread source */
4749 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4750
99eb6a01
KP		 4751 if (has_ck505)
4752 temp |= DREF_NONSPREAD_CK505_ENABLE;
4753 else
4754 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4755
199e5d79
KP		 4756 if (has_panel) {
4757 temp &= ~DREF_SSC_SOURCE_MASK;
4758 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4759
199e5d79 4760 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4761 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4762 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4763 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4764 } else
4765 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4766
4767 /* Get SSC going before enabling the outputs */
4768 I915_WRITE(PCH_DREF_CONTROL, temp);
4769 POSTING_READ(PCH_DREF_CONTROL);
4770 udelay(200);
4771
13d83a67
JB		 4772 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4773
4774 /* Enable CPU source on CPU attached eDP */
199e5d79 4775 if (has_cpu_edp) {
99eb6a01 4776 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4777 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4778 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4779 }
13d83a67
JB		 4780 else
4781 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4782 } else
4783 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4784
4785 I915_WRITE(PCH_DREF_CONTROL, temp);
4786 POSTING_READ(PCH_DREF_CONTROL);
4787 udelay(200);
4788 } else {
4789 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4790
4791 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4792
4793 /* Turn off CPU output */
4794 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4795
4796 I915_WRITE(PCH_DREF_CONTROL, temp);
4797 POSTING_READ(PCH_DREF_CONTROL);
4798 udelay(200);
4799
4800 /* Turn off the SSC source */
4801 temp &= ~DREF_SSC_SOURCE_MASK;
4802 temp |= DREF_SSC_SOURCE_DISABLE;
4803
4804 /* Turn off SSC1 */
4805 temp &= ~ DREF_SSC1_ENABLE;
4806
13d83a67
JB		 4807 I915_WRITE(PCH_DREF_CONTROL, temp);
4808 POSTING_READ(PCH_DREF_CONTROL);
4809 udelay(200);
4810 }
4811}
4812
dde86e2d
PZ		 4813/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4814static void lpt_init_pch_refclk(struct drm_device *dev)
4815{
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 struct drm_mode_config *mode_config = &dev->mode_config;
4818 struct intel_encoder *encoder;
4819 bool has_vga = false;
4820 bool is_sdv = false;
4821 u32 tmp;
4822
4823 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4824 switch (encoder->type) {
4825 case INTEL_OUTPUT_ANALOG:
4826 has_vga = true;
4827 break;
4828 }
4829 }
4830
4831 if (!has_vga)
4832 return;
4833
c00db246
DV		 4834 mutex_lock(&dev_priv->dpio_lock);
4835
dde86e2d
PZ		 4836 /* XXX: Rip out SDV support once Haswell ships for real. */
4837 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4838 is_sdv = true;
4839
4840 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4841 tmp &= ~SBI_SSCCTL_DISABLE;
4842 tmp |= SBI_SSCCTL_PATHALT;
4843 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4844
4845 udelay(24);
4846
4847 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4848 tmp &= ~SBI_SSCCTL_PATHALT;
4849 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4850
4851 if (!is_sdv) {
4852 tmp = I915_READ(SOUTH_CHICKEN2);
4853 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4854 I915_WRITE(SOUTH_CHICKEN2, tmp);
4855
4856 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4857 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4858 DRM_ERROR("FDI mPHY reset assert timeout\n");
4859
4860 tmp = I915_READ(SOUTH_CHICKEN2);
4861 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4862 I915_WRITE(SOUTH_CHICKEN2, tmp);
4863
4864 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4865 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4866 100))
4867 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4868 }
4869
4870 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4871 tmp &= ~(0xFF << 24);
4872 tmp |= (0x12 << 24);
4873 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4874
4875 if (!is_sdv) {
4876 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4877 tmp &= ~(0x3 << 6);
4878 tmp |= (1 << 6) | (1 << 0);
4879 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4880 }
4881
4882 if (is_sdv) {
4883 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4884 tmp |= 0x7FFF;
4885 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4886 }
4887
4888 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4889 tmp |= (1 << 11);
4890 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4891
4892 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4893 tmp |= (1 << 11);
4894 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4895
4896 if (is_sdv) {
4897 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4898 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4899 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4900
4901 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4902 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4903 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4904
4905 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4906 tmp |= (0x3F << 8);
4907 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4908
4909 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4910 tmp |= (0x3F << 8);
4911 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4912 }
4913
4914 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4915 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4916 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4917
4918 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4919 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4920 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4921
4922 if (!is_sdv) {
4923 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4924 tmp &= ~(7 << 13);
4925 tmp |= (5 << 13);
4926 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4927
4928 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4929 tmp &= ~(7 << 13);
4930 tmp |= (5 << 13);
4931 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4932 }
4933
4934 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4935 tmp &= ~0xFF;
4936 tmp |= 0x1C;
4937 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4938
4939 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4940 tmp &= ~0xFF;
4941 tmp |= 0x1C;
4942 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4943
4944 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4945 tmp &= ~(0xFF << 16);
4946 tmp |= (0x1C << 16);
4947 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4948
4949 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4950 tmp &= ~(0xFF << 16);
4951 tmp |= (0x1C << 16);
4952 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4953
4954 if (!is_sdv) {
4955 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4956 tmp |= (1 << 27);
4957 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
4958
4959 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
4960 tmp |= (1 << 27);
4961 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
4962
4963 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
4964 tmp &= ~(0xF << 28);
4965 tmp |= (4 << 28);
4966 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
4967
4968 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
4969 tmp &= ~(0xF << 28);
4970 tmp |= (4 << 28);
4971 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
4972 }
4973
4974 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
4975 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
4976 tmp |= SBI_DBUFF0_ENABLE;
4977 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 4978
4979 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 4980}
4981
4982/*
4983 * Initialize reference clocks when the driver loads
4984 */
4985void intel_init_pch_refclk(struct drm_device *dev)
4986{
4987 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4988 ironlake_init_pch_refclk(dev);
4989 else if (HAS_PCH_LPT(dev))
4990 lpt_init_pch_refclk(dev);
4991}
4992
d9d444cb
JB		 4993static int ironlake_get_refclk(struct drm_crtc *crtc)
4994{
4995 struct drm_device *dev = crtc->dev;
4996 struct drm_i915_private *dev_priv = dev->dev_private;
4997 struct intel_encoder *encoder;
d9d444cb
JB		 4998 struct intel_encoder *edp_encoder = NULL;
4999 int num_connectors = 0;
5000 bool is_lvds = false;
5001
6c2b7c12 5002 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5003 switch (encoder->type) {
5004 case INTEL_OUTPUT_LVDS:
5005 is_lvds = true;
5006 break;
5007 case INTEL_OUTPUT_EDP:
5008 edp_encoder = encoder;
5009 break;
5010 }
5011 num_connectors++;
5012 }
5013
5014 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5015 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5016 dev_priv->lvds_ssc_freq);
5017 return dev_priv->lvds_ssc_freq * 1000;
5018 }
5019
5020 return 120000;
5021}
5022
c8203565 5023static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5024 struct drm_display_mode *adjusted_mode,
c8203565 5025 bool dither)
79e53945 5026{
c8203565 5027 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5029 int pipe = intel_crtc->pipe;
c8203565
PZ		 5030 uint32_t val;
5031
5032 val = I915_READ(PIPECONF(pipe));
5033
dfd07d72 5034 val &= ~PIPECONF_BPC_MASK;
965e0c48 5035 switch (intel_crtc->config.pipe_bpp) {
c8203565 5036 case 18:
dfd07d72 5037 val |= PIPECONF_6BPC;
c8203565
PZ		 5038 break;
5039 case 24:
dfd07d72 5040 val |= PIPECONF_8BPC;
c8203565
PZ		 5041 break;
5042 case 30:
dfd07d72 5043 val |= PIPECONF_10BPC;
c8203565
PZ		 5044 break;
5045 case 36:
dfd07d72 5046 val |= PIPECONF_12BPC;
c8203565
PZ		 5047 break;
5048 default:
cc769b62
PZ		 5049 /* Case prevented by intel_choose_pipe_bpp_dither. */
5050 BUG();
c8203565
PZ		 5051 }
5052
5053 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5054 if (dither)
5055 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5056
5057 val &= ~PIPECONF_INTERLACE_MASK;
5058 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5059 val |= PIPECONF_INTERLACED_ILK;
5060 else
5061 val |= PIPECONF_PROGRESSIVE;
5062
50f3b016 5063 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5064 val |= PIPECONF_COLOR_RANGE_SELECT;
5065 else
5066 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5067
c8203565
PZ		 5068 I915_WRITE(PIPECONF(pipe), val);
5069 POSTING_READ(PIPECONF(pipe));
5070}
5071
86d3efce
VS		 5072/*
5073 * Set up the pipe CSC unit.
5074 *
5075 * Currently only full range RGB to limited range RGB conversion
5076 * is supported, but eventually this should handle various
5077 * RGB<->YCbCr scenarios as well.
5078 */
50f3b016 5079static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5080{
5081 struct drm_device *dev = crtc->dev;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
5083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5084 int pipe = intel_crtc->pipe;
5085 uint16_t coeff = 0x7800; /* 1.0 */
5086
5087 /*
5088 * TODO: Check what kind of values actually come out of the pipe
5089 * with these coeff/postoff values and adjust to get the best
5090 * accuracy. Perhaps we even need to take the bpc value into
5091 * consideration.
5092 */
5093
50f3b016 5094 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5095 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5096
5097 /*
5098 * GY/GU and RY/RU should be the other way around according
5099 * to BSpec, but reality doesn't agree. Just set them up in
5100 * a way that results in the correct picture.
5101 */
5102 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5103 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5104
5105 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5106 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5107
5108 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5109 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5110
5111 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5112 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5113 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5114
5115 if (INTEL_INFO(dev)->gen > 6) {
5116 uint16_t postoff = 0;
5117
50f3b016 5118 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5119 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5120
5121 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5122 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5123 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5124
5125 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5126 } else {
5127 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5128
50f3b016 5129 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5130 mode |= CSC_BLACK_SCREEN_OFFSET;
5131
5132 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5133 }
5134}
5135
ee2b0b38
PZ		 5136static void haswell_set_pipeconf(struct drm_crtc *crtc,
5137 struct drm_display_mode *adjusted_mode,
5138 bool dither)
5139{
5140 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5142 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5143 uint32_t val;
5144
702e7a56 5145 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5146
5147 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5148 if (dither)
5149 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5150
5151 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5152 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5153 val |= PIPECONF_INTERLACED_ILK;
5154 else
5155 val |= PIPECONF_PROGRESSIVE;
5156
702e7a56
PZ		 5157 I915_WRITE(PIPECONF(cpu_transcoder), val);
5158 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5159}
5160
6591c6e4
PZ		 5161static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5162 struct drm_display_mode *adjusted_mode,
5163 intel_clock_t *clock,
5164 bool *has_reduced_clock,
5165 intel_clock_t *reduced_clock)
5166{
5167 struct drm_device *dev = crtc->dev;
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 struct intel_encoder *intel_encoder;
5170 int refclk;
d4906093 5171 const intel_limit_t *limit;
6591c6e4 5172 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5173
6591c6e4
PZ		 5174 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5175 switch (intel_encoder->type) {
79e53945
JB		 5176 case INTEL_OUTPUT_LVDS:
5177 is_lvds = true;
5178 break;
5179 case INTEL_OUTPUT_SDVO:
7d57382e 5180 case INTEL_OUTPUT_HDMI:
79e53945 5181 is_sdvo = true;
6591c6e4 5182 if (intel_encoder->needs_tv_clock)
e2f0ba97 5183 is_tv = true;
79e53945 5184 break;
79e53945
JB		 5185 case INTEL_OUTPUT_TVOUT:
5186 is_tv = true;
5187 break;
79e53945
JB		 5188 }
5189 }
5190
d9d444cb 5191 refclk = ironlake_get_refclk(crtc);
79e53945 5192
d4906093
ML		 5193 /*
5194 * Returns a set of divisors for the desired target clock with the given
5195 * refclk, or FALSE. The returned values represent the clock equation:
5196 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5197 */
1b894b59 5198 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5199 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5200 clock);
5201 if (!ret)
5202 return false;
cda4b7d3 5203
ddc9003c 5204 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5205 /*
5206 * Ensure we match the reduced clock's P to the target clock.
5207 * If the clocks don't match, we can't switch the display clock
5208 * by using the FP0/FP1. In such case we will disable the LVDS
5209 * downclock feature.
5210 */
6591c6e4
PZ		 5211 *has_reduced_clock = limit->find_pll(limit, crtc,
5212 dev_priv->lvds_downclock,
5213 refclk,
5214 clock,
5215 reduced_clock);
652c393a 5216 }
61e9653f
DV		 5217
5218 if (is_sdvo && is_tv)
6591c6e4
PZ		 5219 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5220
5221 return true;
5222}
5223
01a415fd
DV		 5224static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5225{
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227 uint32_t temp;
5228
5229 temp = I915_READ(SOUTH_CHICKEN1);
5230 if (temp & FDI_BC_BIFURCATION_SELECT)
5231 return;
5232
5233 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5234 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5235
5236 temp |= FDI_BC_BIFURCATION_SELECT;
5237 DRM_DEBUG_KMS("enabling fdi C rx\n");
5238 I915_WRITE(SOUTH_CHICKEN1, temp);
5239 POSTING_READ(SOUTH_CHICKEN1);
5240}
5241
5242static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5243{
5244 struct drm_device *dev = intel_crtc->base.dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct intel_crtc *pipe_B_crtc =
5247 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5248
5249 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5250 intel_crtc->pipe, intel_crtc->fdi_lanes);
5251 if (intel_crtc->fdi_lanes > 4) {
5252 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5253 intel_crtc->pipe, intel_crtc->fdi_lanes);
5254 /* Clamp lanes to avoid programming the hw with bogus values. */
5255 intel_crtc->fdi_lanes = 4;
5256
5257 return false;
5258 }
5259
7eb552ae 5260 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5261 return true;
5262
5263 switch (intel_crtc->pipe) {
5264 case PIPE_A:
5265 return true;
5266 case PIPE_B:
5267 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5268 intel_crtc->fdi_lanes > 2) {
5269 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5270 intel_crtc->pipe, intel_crtc->fdi_lanes);
5271 /* Clamp lanes to avoid programming the hw with bogus values. */
5272 intel_crtc->fdi_lanes = 2;
5273
5274 return false;
5275 }
5276
5277 if (intel_crtc->fdi_lanes > 2)
5278 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5279 else
5280 cpt_enable_fdi_bc_bifurcation(dev);
5281
5282 return true;
5283 case PIPE_C:
5284 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5285 if (intel_crtc->fdi_lanes > 2) {
5286 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5287 intel_crtc->pipe, intel_crtc->fdi_lanes);
5288 /* Clamp lanes to avoid programming the hw with bogus values. */
5289 intel_crtc->fdi_lanes = 2;
5290
5291 return false;
5292 }
5293 } else {
5294 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5295 return false;
5296 }
5297
5298 cpt_enable_fdi_bc_bifurcation(dev);
5299
5300 return true;
5301 default:
5302 BUG();
5303 }
5304}
5305
d4b1931c
PZ		 5306int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5307{
5308 /*
5309 * Account for spread spectrum to avoid
5310 * oversubscribing the link. Max center spread
5311 * is 2.5%; use 5% for safety's sake.
5312 */
5313 u32 bps = target_clock * bpp * 21 / 20;
5314 return bps / (link_bw * 8) + 1;
5315}
5316
6cc5f341 5317static void ironlake_set_m_n(struct drm_crtc *crtc)
79e53945
JB		 5318{
5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5322 struct drm_display_mode *adjusted_mode =
5323 &intel_crtc->config.adjusted_mode;
5324 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
afe2fcf5 5325 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5326 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5327 struct intel_link_m_n m_n = {0};
6cc5f341 5328 int target_clock, lane, link_bw;
f48d8f23 5329 bool is_dp = false, is_cpu_edp = false;
79e53945 5330
f48d8f23
PZ		 5331 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5332 switch (intel_encoder->type) {
a4fc5ed6
KP		 5333 case INTEL_OUTPUT_DISPLAYPORT:
5334 is_dp = true;
5335 break;
32f9d658 5336 case INTEL_OUTPUT_EDP:
e3aef172 5337 is_dp = true;
f48d8f23 5338 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5339 is_cpu_edp = true;
f48d8f23 5340 edp_encoder = intel_encoder;
32f9d658 5341 break;
79e53945 5342 }
79e53945 5343 }
61e9653f 5344
2c07245f 5345 /* FDI link */
8febb297
EA		 5346 lane = 0;
5347 /* CPU eDP doesn't require FDI link, so just set DP M/N
5348 according to current link config */
e3aef172 5349 if (is_cpu_edp) {
e3aef172 5350 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5351 } else {
8febb297
EA		 5352 /* FDI is a binary signal running at ~2.7GHz, encoding
5353 * each output octet as 10 bits. The actual frequency
5354 * is stored as a divider into a 100MHz clock, and the
5355 * mode pixel clock is stored in units of 1KHz.
5356 * Hence the bw of each lane in terms of the mode signal
5357 * is:
5358 */
5359 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5360 }
58a27471 5361
94bf2ced
DV		 5362 /* [e]DP over FDI requires target mode clock instead of link clock. */
5363 if (edp_encoder)
5364 target_clock = intel_edp_target_clock(edp_encoder, mode);
5365 else if (is_dp)
5366 target_clock = mode->clock;
5367 else
5368 target_clock = adjusted_mode->clock;
5369
d4b1931c
PZ		 5370 if (!lane)
5371 lane = ironlake_get_lanes_required(target_clock, link_bw,
965e0c48 5372 intel_crtc->config.pipe_bpp);
2c07245f 5373
8febb297
EA		 5374 intel_crtc->fdi_lanes = lane;
5375
6cc5f341
DV		 5376 if (intel_crtc->config.pixel_multiplier > 1)
5377 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5378 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5379 link_bw, &m_n);
8febb297 5380
afe2fcf5
PZ		 5381 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5382 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5383 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5384 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5385}
5386
de13a2e3 5387static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5388 intel_clock_t *clock, u32 fp)
79e53945 5389{
de13a2e3 5390 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5391 struct drm_device *dev = crtc->dev;
5392 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5393 struct intel_encoder *intel_encoder;
5394 uint32_t dpll;
6cc5f341 5395 int factor, num_connectors = 0;
de13a2e3
PZ		 5396 bool is_lvds = false, is_sdvo = false, is_tv = false;
5397 bool is_dp = false, is_cpu_edp = false;
79e53945 5398
de13a2e3
PZ		 5399 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5400 switch (intel_encoder->type) {
79e53945
JB		 5401 case INTEL_OUTPUT_LVDS:
5402 is_lvds = true;
5403 break;
5404 case INTEL_OUTPUT_SDVO:
7d57382e 5405 case INTEL_OUTPUT_HDMI:
79e53945 5406 is_sdvo = true;
de13a2e3 5407 if (intel_encoder->needs_tv_clock)
e2f0ba97 5408 is_tv = true;
79e53945 5409 break;
79e53945
JB		 5410 case INTEL_OUTPUT_TVOUT:
5411 is_tv = true;
5412 break;
a4fc5ed6
KP		 5413 case INTEL_OUTPUT_DISPLAYPORT:
5414 is_dp = true;
5415 break;
32f9d658 5416 case INTEL_OUTPUT_EDP:
e3aef172 5417 is_dp = true;
de13a2e3 5418 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5419 is_cpu_edp = true;
32f9d658 5420 break;
79e53945 5421 }
43565a06 5422
c751ce4f 5423 num_connectors++;
79e53945 5424 }
79e53945 5425
c1858123 5426 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5427 factor = 21;
5428 if (is_lvds) {
5429 if ((intel_panel_use_ssc(dev_priv) &&
5430 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5431 intel_is_dual_link_lvds(dev))
8febb297
EA		 5432 factor = 25;
5433 } else if (is_sdvo && is_tv)
5434 factor = 20;
c1858123 5435
de13a2e3 5436 if (clock->m < factor * clock->n)
8febb297 5437 fp |= FP_CB_TUNE;
2c07245f 5438
5eddb70b 5439 dpll = 0;
2c07245f 5440
a07d6787
EA		 5441 if (is_lvds)
5442 dpll |= DPLLB_MODE_LVDS;
5443 else
5444 dpll |= DPLLB_MODE_DAC_SERIAL;
5445 if (is_sdvo) {
6cc5f341
DV		 5446 if (intel_crtc->config.pixel_multiplier > 1) {
5447 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5448 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5449 }
a07d6787
EA		 5450 dpll |= DPLL_DVO_HIGH_SPEED;
5451 }
e3aef172 5452 if (is_dp && !is_cpu_edp)
a07d6787 5453 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5454
a07d6787 5455 /* compute bitmask from p1 value */
de13a2e3 5456 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5457 /* also FPA1 */
de13a2e3 5458 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5459
de13a2e3 5460 switch (clock->p2) {
a07d6787
EA		 5461 case 5:
5462 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5463 break;
5464 case 7:
5465 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5466 break;
5467 case 10:
5468 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5469 break;
5470 case 14:
5471 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5472 break;
79e53945
JB		 5473 }
5474
43565a06
KH		 5475 if (is_sdvo && is_tv)
5476 dpll |= PLL_REF_INPUT_TVCLKINBC;
5477 else if (is_tv)
79e53945 5478 /* XXX: just matching BIOS for now */
43565a06 5479 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5480 dpll |= 3;
a7615030 5481 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5482 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5483 else
5484 dpll |= PLL_REF_INPUT_DREFCLK;
5485
de13a2e3
PZ		 5486 return dpll;
5487}
5488
5489static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5490 int x, int y,
5491 struct drm_framebuffer *fb)
5492{
5493 struct drm_device *dev = crtc->dev;
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5496 struct drm_display_mode *adjusted_mode =
5497 &intel_crtc->config.adjusted_mode;
5498 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5499 int pipe = intel_crtc->pipe;
5500 int plane = intel_crtc->plane;
5501 int num_connectors = 0;
5502 intel_clock_t clock, reduced_clock;
5503 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5504 bool ok, has_reduced_clock = false;
5505 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5506 struct intel_encoder *encoder;
de13a2e3 5507 int ret;
01a415fd 5508 bool dither, fdi_config_ok;
de13a2e3
PZ		 5509
5510 for_each_encoder_on_crtc(dev, crtc, encoder) {
5511 switch (encoder->type) {
5512 case INTEL_OUTPUT_LVDS:
5513 is_lvds = true;
5514 break;
de13a2e3
PZ		 5515 case INTEL_OUTPUT_DISPLAYPORT:
5516 is_dp = true;
5517 break;
5518 case INTEL_OUTPUT_EDP:
5519 is_dp = true;
e2f12b07 5520 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5521 is_cpu_edp = true;
5522 break;
5523 }
5524
5525 num_connectors++;
a07d6787 5526 }
79e53945 5527
5dc5298b
PZ		 5528 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5529 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5530
de13a2e3
PZ		 5531 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5532 &has_reduced_clock, &reduced_clock);
5533 if (!ok) {
5534 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5535 return -EINVAL;
79e53945
JB		 5536 }
5537
de13a2e3
PZ		 5538 /* Ensure that the cursor is valid for the new mode before changing... */
5539 intel_crtc_update_cursor(crtc, true);
5540
5541 /* determine panel color depth */
4e53c2e0 5542 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5543 if (is_lvds && dev_priv->lvds_dither)
5544 dither = true;
5545
5546 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5547 if (has_reduced_clock)
5548 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5549 reduced_clock.m2;
5550
6cc5f341 5551 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5552
f7cb34d4 5553 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5554 drm_mode_debug_printmodeline(mode);
5555
5dc5298b
PZ		 5556 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5557 if (!is_cpu_edp) {
ee7b9f93 5558 struct intel_pch_pll *pll;
4b645f14 5559
ee7b9f93
JB		 5560 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5561 if (pll == NULL) {
5562 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5563 pipe);
4b645f14
JB		 5564 return -EINVAL;
5565 }
ee7b9f93
JB		 5566 } else
5567 intel_put_pch_pll(intel_crtc);
79e53945 5568
2f0c2ad1 5569 if (is_dp && !is_cpu_edp)
a4fc5ed6 5570 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5571
dafd226c
DV		 5572 for_each_encoder_on_crtc(dev, crtc, encoder)
5573 if (encoder->pre_pll_enable)
5574 encoder->pre_pll_enable(encoder);
79e53945 5575
ee7b9f93
JB		 5576 if (intel_crtc->pch_pll) {
5577 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5578
32f9d658 5579 /* Wait for the clocks to stabilize. */
ee7b9f93 5580 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5581 udelay(150);
5582
8febb297
EA		 5583 /* The pixel multiplier can only be updated once the
5584 * DPLL is enabled and the clocks are stable.
5585 *
5586 * So write it again.
5587 */
ee7b9f93 5588 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5589 }
79e53945 5590
5eddb70b 5591 intel_crtc->lowfreq_avail = false;
ee7b9f93 5592 if (intel_crtc->pch_pll) {
4b645f14 5593 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5594 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5595 intel_crtc->lowfreq_avail = true;
4b645f14 5596 } else {
ee7b9f93 5597 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5598 }
5599 }
5600
b0e77b9c 5601 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5602
01a415fd
DV		 5603 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5604 * ironlake_check_fdi_lanes. */
6cc5f341 5605 ironlake_set_m_n(crtc);
2c07245f 5606
01a415fd 5607 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5608
c8203565 5609 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5610
9d0498a2 5611 intel_wait_for_vblank(dev, pipe);
79e53945 5612
a1f9e77e
PZ		 5613 /* Set up the display plane register */
5614 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5615 POSTING_READ(DSPCNTR(plane));
79e53945 5616
94352cf9 5617 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5618
5619 intel_update_watermarks(dev);
5620
1f8eeabf
ED		 5621 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5622
01a415fd 5623 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5624}
5625
d6dd9eb1
DV		 5626static void haswell_modeset_global_resources(struct drm_device *dev)
5627{
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 bool enable = false;
5630 struct intel_crtc *crtc;
5631 struct intel_encoder *encoder;
5632
5633 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5634 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5635 enable = true;
5636 /* XXX: Should check for edp transcoder here, but thanks to init
5637 * sequence that's not yet available. Just in case desktop eDP
5638 * on PORT D is possible on haswell, too. */
5639 }
5640
5641 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5642 base.head) {
5643 if (encoder->type != INTEL_OUTPUT_EDP &&
5644 encoder->connectors_active)
5645 enable = true;
5646 }
5647
5648 /* Even the eDP panel fitter is outside the always-on well. */
5649 if (dev_priv->pch_pf_size)
5650 enable = true;
5651
5652 intel_set_power_well(dev, enable);
5653}
5654
09b4ddf9 5655static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5656 int x, int y,
5657 struct drm_framebuffer *fb)
5658{
5659 struct drm_device *dev = crtc->dev;
5660 struct drm_i915_private *dev_priv = dev->dev_private;
5661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5662 struct drm_display_mode *adjusted_mode =
5663 &intel_crtc->config.adjusted_mode;
5664 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5665 int pipe = intel_crtc->pipe;
5666 int plane = intel_crtc->plane;
5667 int num_connectors = 0;
ed7ef439 5668 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5669 struct intel_encoder *encoder;
09b4ddf9
PZ		 5670 int ret;
5671 bool dither;
5672
5673 for_each_encoder_on_crtc(dev, crtc, encoder) {
5674 switch (encoder->type) {
09b4ddf9
PZ		 5675 case INTEL_OUTPUT_DISPLAYPORT:
5676 is_dp = true;
5677 break;
5678 case INTEL_OUTPUT_EDP:
5679 is_dp = true;
5680 if (!intel_encoder_is_pch_edp(&encoder->base))
5681 is_cpu_edp = true;
5682 break;
5683 }
5684
5685 num_connectors++;
5686 }
5687
5dc5298b
PZ		 5688 /* We are not sure yet this won't happen. */
5689 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5690 INTEL_PCH_TYPE(dev));
5691
5692 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5693 num_connectors, pipe_name(pipe));
5694
702e7a56 5695 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5696 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5697
5698 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5699
6441ab5f
PZ		 5700 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5701 return -EINVAL;
5702
09b4ddf9
PZ		 5703 /* Ensure that the cursor is valid for the new mode before changing... */
5704 intel_crtc_update_cursor(crtc, true);
5705
5706 /* determine panel color depth */
4e53c2e0 5707 dither = intel_crtc->config.dither;
09b4ddf9 5708
09b4ddf9
PZ		 5709 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5710 drm_mode_debug_printmodeline(mode);
5711
ed7ef439 5712 if (is_dp && !is_cpu_edp)
09b4ddf9 5713 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5714
5715 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5716
5717 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5718
1eb8dfec 5719 if (!is_dp || is_cpu_edp)
6cc5f341 5720 ironlake_set_m_n(crtc);
09b4ddf9 5721
ee2b0b38 5722 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5723
50f3b016 5724 intel_set_pipe_csc(crtc);
86d3efce 5725
09b4ddf9 5726 /* Set up the display plane register */
86d3efce 5727 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5728 POSTING_READ(DSPCNTR(plane));
5729
5730 ret = intel_pipe_set_base(crtc, x, y, fb);
5731
5732 intel_update_watermarks(dev);
5733
5734 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5735
1f803ee5 5736 return ret;
79e53945
JB		 5737}
5738
f564048e 5739static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5740 int x, int y,
94352cf9 5741 struct drm_framebuffer *fb)
f564048e
EA		 5742{
5743 struct drm_device *dev = crtc->dev;
5744 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5745 struct drm_encoder_helper_funcs *encoder_funcs;
5746 struct intel_encoder *encoder;
0b701d27 5747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5748 struct drm_display_mode *adjusted_mode =
5749 &intel_crtc->config.adjusted_mode;
5750 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5751 int pipe = intel_crtc->pipe;
f564048e
EA		 5752 int ret;
5753
cc464b2a
PZ		 5754 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5755 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5756 else
5757 intel_crtc->cpu_transcoder = pipe;
5758
0b701d27 5759 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5760
b8cecdf5
DV		 5761 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5762
79e53945 5763 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5764
9256aa19
DV		 5765 if (ret != 0)
5766 return ret;
5767
5768 for_each_encoder_on_crtc(dev, crtc, encoder) {
5769 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5770 encoder->base.base.id,
5771 drm_get_encoder_name(&encoder->base),
5772 mode->base.id, mode->name);
6cc5f341
DV		 5773 if (encoder->mode_set) {
5774 encoder->mode_set(encoder);
5775 } else {
5776 encoder_funcs = encoder->base.helper_private;
5777 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5778 }
9256aa19
DV		 5779 }
5780
5781 return 0;
79e53945
JB		 5782}
5783
3a9627f4
WF		 5784static bool intel_eld_uptodate(struct drm_connector *connector,
5785 int reg_eldv, uint32_t bits_eldv,
5786 int reg_elda, uint32_t bits_elda,
5787 int reg_edid)
5788{
5789 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5790 uint8_t *eld = connector->eld;
5791 uint32_t i;
5792
5793 i = I915_READ(reg_eldv);
5794 i &= bits_eldv;
5795
5796 if (!eld[0])
5797 return !i;
5798
5799 if (!i)
5800 return false;
5801
5802 i = I915_READ(reg_elda);
5803 i &= ~bits_elda;
5804 I915_WRITE(reg_elda, i);
5805
5806 for (i = 0; i < eld[2]; i++)
5807 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5808 return false;
5809
5810 return true;
5811}
5812
e0dac65e
WF		 5813static void g4x_write_eld(struct drm_connector *connector,
5814 struct drm_crtc *crtc)
5815{
5816 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5817 uint8_t *eld = connector->eld;
5818 uint32_t eldv;
5819 uint32_t len;
5820 uint32_t i;
5821
5822 i = I915_READ(G4X_AUD_VID_DID);
5823
5824 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5825 eldv = G4X_ELDV_DEVCL_DEVBLC;
5826 else
5827 eldv = G4X_ELDV_DEVCTG;
5828
3a9627f4
WF		 5829 if (intel_eld_uptodate(connector,
5830 G4X_AUD_CNTL_ST, eldv,
5831 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5832 G4X_HDMIW_HDMIEDID))
5833 return;
5834
e0dac65e
WF		 5835 i = I915_READ(G4X_AUD_CNTL_ST);
5836 i &= ~(eldv | G4X_ELD_ADDR);
5837 len = (i >> 9) & 0x1f; /* ELD buffer size */
5838 I915_WRITE(G4X_AUD_CNTL_ST, i);
5839
5840 if (!eld[0])
5841 return;
5842
5843 len = min_t(uint8_t, eld[2], len);
5844 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5845 for (i = 0; i < len; i++)
5846 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5847
5848 i = I915_READ(G4X_AUD_CNTL_ST);
5849 i |= eldv;
5850 I915_WRITE(G4X_AUD_CNTL_ST, i);
5851}
5852
83358c85
WX		 5853static void haswell_write_eld(struct drm_connector *connector,
5854 struct drm_crtc *crtc)
5855{
5856 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5857 uint8_t *eld = connector->eld;
5858 struct drm_device *dev = crtc->dev;
7b9f35a6 5859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5860 uint32_t eldv;
5861 uint32_t i;
5862 int len;
5863 int pipe = to_intel_crtc(crtc)->pipe;
5864 int tmp;
5865
5866 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5867 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5868 int aud_config = HSW_AUD_CFG(pipe);
5869 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5870
5871
5872 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5873
5874 /* Audio output enable */
5875 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5876 tmp = I915_READ(aud_cntrl_st2);
5877 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5878 I915_WRITE(aud_cntrl_st2, tmp);
5879
5880 /* Wait for 1 vertical blank */
5881 intel_wait_for_vblank(dev, pipe);
5882
5883 /* Set ELD valid state */
5884 tmp = I915_READ(aud_cntrl_st2);
5885 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5886 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5887 I915_WRITE(aud_cntrl_st2, tmp);
5888 tmp = I915_READ(aud_cntrl_st2);
5889 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5890
5891 /* Enable HDMI mode */
5892 tmp = I915_READ(aud_config);
5893 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5894 /* clear N_programing_enable and N_value_index */
5895 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5896 I915_WRITE(aud_config, tmp);
5897
5898 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5899
5900 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5901 intel_crtc->eld_vld = true;
83358c85
WX		 5902
5903 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5904 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5905 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5906 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5907 } else
5908 I915_WRITE(aud_config, 0);
5909
5910 if (intel_eld_uptodate(connector,
5911 aud_cntrl_st2, eldv,
5912 aud_cntl_st, IBX_ELD_ADDRESS,
5913 hdmiw_hdmiedid))
5914 return;
5915
5916 i = I915_READ(aud_cntrl_st2);
5917 i &= ~eldv;
5918 I915_WRITE(aud_cntrl_st2, i);
5919
5920 if (!eld[0])
5921 return;
5922
5923 i = I915_READ(aud_cntl_st);
5924 i &= ~IBX_ELD_ADDRESS;
5925 I915_WRITE(aud_cntl_st, i);
5926 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5927 DRM_DEBUG_DRIVER("port num:%d\n", i);
5928
5929 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5930 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5931 for (i = 0; i < len; i++)
5932 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5933
5934 i = I915_READ(aud_cntrl_st2);
5935 i |= eldv;
5936 I915_WRITE(aud_cntrl_st2, i);
5937
5938}
5939
e0dac65e
WF		 5940static void ironlake_write_eld(struct drm_connector *connector,
5941 struct drm_crtc *crtc)
5942{
5943 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5944 uint8_t *eld = connector->eld;
5945 uint32_t eldv;
5946 uint32_t i;
5947 int len;
5948 int hdmiw_hdmiedid;
b6daa025 5949 int aud_config;
e0dac65e
WF		 5950 int aud_cntl_st;
5951 int aud_cntrl_st2;
9b138a83 5952 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5953
b3f33cbf 5954 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5955 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5956 aud_config = IBX_AUD_CFG(pipe);
5957 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5958 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5959 } else {
9b138a83
WX		 5960 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5961 aud_config = CPT_AUD_CFG(pipe);
5962 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5963 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5964 }
5965
9b138a83 5966 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5967
5968 i = I915_READ(aud_cntl_st);
9b138a83 5969 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5970 if (!i) {
5971 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5972 /* operate blindly on all ports */
1202b4c6
WF		 5973 eldv = IBX_ELD_VALIDB;
5974 eldv |= IBX_ELD_VALIDB << 4;
5975 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5976 } else {
5977 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5978 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5979 }
5980
3a9627f4
WF		 5981 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5982 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5983 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5984 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5985 } else
5986 I915_WRITE(aud_config, 0);
e0dac65e 5987
3a9627f4
WF		 5988 if (intel_eld_uptodate(connector,
5989 aud_cntrl_st2, eldv,
5990 aud_cntl_st, IBX_ELD_ADDRESS,
5991 hdmiw_hdmiedid))
5992 return;
5993
e0dac65e
WF		 5994 i = I915_READ(aud_cntrl_st2);
5995 i &= ~eldv;
5996 I915_WRITE(aud_cntrl_st2, i);
5997
5998 if (!eld[0])
5999 return;
6000
e0dac65e 6001 i = I915_READ(aud_cntl_st);
1202b4c6 6002 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6003 I915_WRITE(aud_cntl_st, i);
6004
6005 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6006 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6007 for (i = 0; i < len; i++)
6008 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6009
6010 i = I915_READ(aud_cntrl_st2);
6011 i |= eldv;
6012 I915_WRITE(aud_cntrl_st2, i);
6013}
6014
6015void intel_write_eld(struct drm_encoder *encoder,
6016 struct drm_display_mode *mode)
6017{
6018 struct drm_crtc *crtc = encoder->crtc;
6019 struct drm_connector *connector;
6020 struct drm_device *dev = encoder->dev;
6021 struct drm_i915_private *dev_priv = dev->dev_private;
6022
6023 connector = drm_select_eld(encoder, mode);
6024 if (!connector)
6025 return;
6026
6027 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6028 connector->base.id,
6029 drm_get_connector_name(connector),
6030 connector->encoder->base.id,
6031 drm_get_encoder_name(connector->encoder));
6032
6033 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6034
6035 if (dev_priv->display.write_eld)
6036 dev_priv->display.write_eld(connector, crtc);
6037}
6038
79e53945
JB		 6039/** Loads the palette/gamma unit for the CRTC with the prepared values */
6040void intel_crtc_load_lut(struct drm_crtc *crtc)
6041{
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6045 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6046 int i;
6047
6048 /* The clocks have to be on to load the palette. */
aed3f09d 6049 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6050 return;
6051
f2b115e6 6052 /* use legacy palette for Ironlake */
bad720ff 6053 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6054 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6055
79e53945
JB		 6056 for (i = 0; i < 256; i++) {
6057 I915_WRITE(palreg + 4 * i,
6058 (intel_crtc->lut_r[i] << 16) |
6059 (intel_crtc->lut_g[i] << 8) |
6060 intel_crtc->lut_b[i]);
6061 }
6062}
6063
560b85bb
CW		 6064static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6065{
6066 struct drm_device *dev = crtc->dev;
6067 struct drm_i915_private *dev_priv = dev->dev_private;
6068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6069 bool visible = base != 0;
6070 u32 cntl;
6071
6072 if (intel_crtc->cursor_visible == visible)
6073 return;
6074
9db4a9c7 6075 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6076 if (visible) {
6077 /* On these chipsets we can only modify the base whilst
6078 * the cursor is disabled.
6079 */
9db4a9c7 6080 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6081
6082 cntl &= ~(CURSOR_FORMAT_MASK);
6083 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6084 cntl |= CURSOR_ENABLE |
6085 CURSOR_GAMMA_ENABLE |
6086 CURSOR_FORMAT_ARGB;
6087 } else
6088 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6089 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6090
6091 intel_crtc->cursor_visible = visible;
6092}
6093
6094static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6095{
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099 int pipe = intel_crtc->pipe;
6100 bool visible = base != 0;
6101
6102 if (intel_crtc->cursor_visible != visible) {
548f245b 6103 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6104 if (base) {
6105 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6106 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6107 cntl |= pipe << 28; /* Connect to correct pipe */
6108 } else {
6109 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6110 cntl |= CURSOR_MODE_DISABLE;
6111 }
9db4a9c7 6112 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6113
6114 intel_crtc->cursor_visible = visible;
6115 }
6116 /* and commit changes on next vblank */
9db4a9c7 6117 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6118}
6119
65a21cd6
JB		 6120static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6121{
6122 struct drm_device *dev = crtc->dev;
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125 int pipe = intel_crtc->pipe;
6126 bool visible = base != 0;
6127
6128 if (intel_crtc->cursor_visible != visible) {
6129 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6130 if (base) {
6131 cntl &= ~CURSOR_MODE;
6132 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6133 } else {
6134 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6135 cntl |= CURSOR_MODE_DISABLE;
6136 }
86d3efce
VS		 6137 if (IS_HASWELL(dev))
6138 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6139 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6140
6141 intel_crtc->cursor_visible = visible;
6142 }
6143 /* and commit changes on next vblank */
6144 I915_WRITE(CURBASE_IVB(pipe), base);
6145}
6146
cda4b7d3 6147/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6148static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6149 bool on)
cda4b7d3
CW		 6150{
6151 struct drm_device *dev = crtc->dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154 int pipe = intel_crtc->pipe;
6155 int x = intel_crtc->cursor_x;
6156 int y = intel_crtc->cursor_y;
560b85bb 6157 u32 base, pos;
cda4b7d3
CW		 6158 bool visible;
6159
6160 pos = 0;
6161
6b383a7f 6162 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6163 base = intel_crtc->cursor_addr;
6164 if (x > (int) crtc->fb->width)
6165 base = 0;
6166
6167 if (y > (int) crtc->fb->height)
6168 base = 0;
6169 } else
6170 base = 0;
6171
6172 if (x < 0) {
6173 if (x + intel_crtc->cursor_width < 0)
6174 base = 0;
6175
6176 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6177 x = -x;
6178 }
6179 pos |= x << CURSOR_X_SHIFT;
6180
6181 if (y < 0) {
6182 if (y + intel_crtc->cursor_height < 0)
6183 base = 0;
6184
6185 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6186 y = -y;
6187 }
6188 pos |= y << CURSOR_Y_SHIFT;
6189
6190 visible = base != 0;
560b85bb 6191 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6192 return;
6193
0cd83aa9 6194 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6195 I915_WRITE(CURPOS_IVB(pipe), pos);
6196 ivb_update_cursor(crtc, base);
6197 } else {
6198 I915_WRITE(CURPOS(pipe), pos);
6199 if (IS_845G(dev) || IS_I865G(dev))
6200 i845_update_cursor(crtc, base);
6201 else
6202 i9xx_update_cursor(crtc, base);
6203 }
cda4b7d3
CW		 6204}
6205
79e53945 6206static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6207 struct drm_file *file,
79e53945
JB		 6208 uint32_t handle,
6209 uint32_t width, uint32_t height)
6210{
6211 struct drm_device *dev = crtc->dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6214 struct drm_i915_gem_object *obj;
cda4b7d3 6215 uint32_t addr;
3f8bc370 6216 int ret;
79e53945 6217
79e53945
JB		 6218 /* if we want to turn off the cursor ignore width and height */
6219 if (!handle) {
28c97730 6220 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6221 addr = 0;
05394f39 6222 obj = NULL;
5004417d 6223 mutex_lock(&dev->struct_mutex);
3f8bc370 6224 goto finish;
79e53945
JB		 6225 }
6226
6227 /* Currently we only support 64x64 cursors */
6228 if (width != 64 || height != 64) {
6229 DRM_ERROR("we currently only support 64x64 cursors\n");
6230 return -EINVAL;
6231 }
6232
05394f39 6233 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6234 if (&obj->base == NULL)
79e53945
JB		 6235 return -ENOENT;
6236
05394f39 6237 if (obj->base.size < width * height * 4) {
79e53945 6238 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6239 ret = -ENOMEM;
6240 goto fail;
79e53945
JB		 6241 }
6242
71acb5eb 6243 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6244 mutex_lock(&dev->struct_mutex);
b295d1b6 6245 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6246 unsigned alignment;
6247
d9e86c0e
CW		 6248 if (obj->tiling_mode) {
6249 DRM_ERROR("cursor cannot be tiled\n");
6250 ret = -EINVAL;
6251 goto fail_locked;
6252 }
6253
693db184
CW		 6254 /* Note that the w/a also requires 2 PTE of padding following
6255 * the bo. We currently fill all unused PTE with the shadow
6256 * page and so we should always have valid PTE following the
6257 * cursor preventing the VT-d warning.
6258 */
6259 alignment = 0;
6260 if (need_vtd_wa(dev))
6261 alignment = 64*1024;
6262
6263 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6264 if (ret) {
6265 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6266 goto fail_locked;
e7b526bb
CW		 6267 }
6268
d9e86c0e
CW		 6269 ret = i915_gem_object_put_fence(obj);
6270 if (ret) {
2da3b9b9 6271 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6272 goto fail_unpin;
6273 }
6274
05394f39 6275 addr = obj->gtt_offset;
71acb5eb 6276 } else {
6eeefaf3 6277 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6278 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6279 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6280 align);
71acb5eb
DA		 6281 if (ret) {
6282 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6283 goto fail_locked;
71acb5eb 6284 }
05394f39 6285 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6286 }
6287
a6c45cf0 6288 if (IS_GEN2(dev))
14b60391
JB		 6289 I915_WRITE(CURSIZE, (height << 12) | width);
6290
3f8bc370 6291 finish:
3f8bc370 6292 if (intel_crtc->cursor_bo) {
b295d1b6 6293 if (dev_priv->info->cursor_needs_physical) {
05394f39 6294 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6295 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6296 } else
6297 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6298 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6299 }
80824003 6300
7f9872e0 6301 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6302
6303 intel_crtc->cursor_addr = addr;
05394f39 6304 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6305 intel_crtc->cursor_width = width;
6306 intel_crtc->cursor_height = height;
6307
6b383a7f 6308 intel_crtc_update_cursor(crtc, true);
3f8bc370 6309
79e53945 6310 return 0;
e7b526bb 6311fail_unpin:
05394f39 6312 i915_gem_object_unpin(obj);
7f9872e0 6313fail_locked:
34b8686e 6314 mutex_unlock(&dev->struct_mutex);
bc9025bd 6315fail:
05394f39 6316 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6317 return ret;
79e53945
JB		 6318}
6319
6320static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6321{
79e53945 6322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6323
cda4b7d3
CW		 6324 intel_crtc->cursor_x = x;
6325 intel_crtc->cursor_y = y;
652c393a 6326
6b383a7f 6327 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6328
6329 return 0;
6330}
6331
6332/** Sets the color ramps on behalf of RandR */
6333void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6334 u16 blue, int regno)
6335{
6336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6337
6338 intel_crtc->lut_r[regno] = red >> 8;
6339 intel_crtc->lut_g[regno] = green >> 8;
6340 intel_crtc->lut_b[regno] = blue >> 8;
6341}
6342
b8c00ac5
DA		 6343void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6344 u16 *blue, int regno)
6345{
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347
6348 *red = intel_crtc->lut_r[regno] << 8;
6349 *green = intel_crtc->lut_g[regno] << 8;
6350 *blue = intel_crtc->lut_b[regno] << 8;
6351}
6352
79e53945 6353static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6354 u16 *blue, uint32_t start, uint32_t size)
79e53945 6355{
7203425a 6356 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6358
7203425a 6359 for (i = start; i < end; i++) {
79e53945
JB		 6360 intel_crtc->lut_r[i] = red[i] >> 8;
6361 intel_crtc->lut_g[i] = green[i] >> 8;
6362 intel_crtc->lut_b[i] = blue[i] >> 8;
6363 }
6364
6365 intel_crtc_load_lut(crtc);
6366}
6367
79e53945
JB		 6368/* VESA 640x480x72Hz mode to set on the pipe */
6369static struct drm_display_mode load_detect_mode = {
6370 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6371 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6372};
6373
d2dff872
CW		 6374static struct drm_framebuffer *
6375intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6376 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6377 struct drm_i915_gem_object *obj)
6378{
6379 struct intel_framebuffer *intel_fb;
6380 int ret;
6381
6382 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6383 if (!intel_fb) {
6384 drm_gem_object_unreference_unlocked(&obj->base);
6385 return ERR_PTR(-ENOMEM);
6386 }
6387
6388 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6389 if (ret) {
6390 drm_gem_object_unreference_unlocked(&obj->base);
6391 kfree(intel_fb);
6392 return ERR_PTR(ret);
6393 }
6394
6395 return &intel_fb->base;
6396}
6397
6398static u32
6399intel_framebuffer_pitch_for_width(int width, int bpp)
6400{
6401 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6402 return ALIGN(pitch, 64);
6403}
6404
6405static u32
6406intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6407{
6408 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6409 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6410}
6411
6412static struct drm_framebuffer *
6413intel_framebuffer_create_for_mode(struct drm_device *dev,
6414 struct drm_display_mode *mode,
6415 int depth, int bpp)
6416{
6417 struct drm_i915_gem_object *obj;
0fed39bd 6418 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6419
6420 obj = i915_gem_alloc_object(dev,
6421 intel_framebuffer_size_for_mode(mode, bpp));
6422 if (obj == NULL)
6423 return ERR_PTR(-ENOMEM);
6424
6425 mode_cmd.width = mode->hdisplay;
6426 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6427 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6428 bpp);
5ca0c34a 6429 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6430
6431 return intel_framebuffer_create(dev, &mode_cmd, obj);
6432}
6433
6434static struct drm_framebuffer *
6435mode_fits_in_fbdev(struct drm_device *dev,
6436 struct drm_display_mode *mode)
6437{
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 struct drm_i915_gem_object *obj;
6440 struct drm_framebuffer *fb;
6441
6442 if (dev_priv->fbdev == NULL)
6443 return NULL;
6444
6445 obj = dev_priv->fbdev->ifb.obj;
6446 if (obj == NULL)
6447 return NULL;
6448
6449 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6450 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6451 fb->bits_per_pixel))
d2dff872
CW		 6452 return NULL;
6453
01f2c773 6454 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6455 return NULL;
6456
6457 return fb;
6458}
6459
d2434ab7 6460bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6461 struct drm_display_mode *mode,
8261b191 6462 struct intel_load_detect_pipe *old)
79e53945
JB		 6463{
6464 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6465 struct intel_encoder *intel_encoder =
6466 intel_attached_encoder(connector);
79e53945 6467 struct drm_crtc *possible_crtc;
4ef69c7a 6468 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6469 struct drm_crtc *crtc = NULL;
6470 struct drm_device *dev = encoder->dev;
94352cf9 6471 struct drm_framebuffer *fb;
79e53945
JB		 6472 int i = -1;
6473
d2dff872
CW		 6474 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6475 connector->base.id, drm_get_connector_name(connector),
6476 encoder->base.id, drm_get_encoder_name(encoder));
6477
79e53945
JB		 6478 /*
6479 * Algorithm gets a little messy:
7a5e4805 6480 *
79e53945
JB		 6481 * - if the connector already has an assigned crtc, use it (but make
6482 * sure it's on first)
7a5e4805 6483 *
79e53945
JB		 6484 * - try to find the first unused crtc that can drive this connector,
6485 * and use that if we find one
79e53945
JB		 6486 */
6487
6488 /* See if we already have a CRTC for this connector */
6489 if (encoder->crtc) {
6490 crtc = encoder->crtc;
8261b191 6491
7b24056b
DV		 6492 mutex_lock(&crtc->mutex);
6493
24218aac 6494 old->dpms_mode = connector->dpms;
8261b191
CW		 6495 old->load_detect_temp = false;
6496
6497 /* Make sure the crtc and connector are running */
24218aac
DV		 6498 if (connector->dpms != DRM_MODE_DPMS_ON)
6499 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6500
7173188d 6501 return true;
79e53945
JB		 6502 }
6503
6504 /* Find an unused one (if possible) */
6505 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6506 i++;
6507 if (!(encoder->possible_crtcs & (1 << i)))
6508 continue;
6509 if (!possible_crtc->enabled) {
6510 crtc = possible_crtc;
6511 break;
6512 }
79e53945
JB		 6513 }
6514
6515 /*
6516 * If we didn't find an unused CRTC, don't use any.
6517 */
6518 if (!crtc) {
7173188d
CW		 6519 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6520 return false;
79e53945
JB		 6521 }
6522
7b24056b 6523 mutex_lock(&crtc->mutex);
fc303101
DV		 6524 intel_encoder->new_crtc = to_intel_crtc(crtc);
6525 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6526
6527 intel_crtc = to_intel_crtc(crtc);
24218aac 6528 old->dpms_mode = connector->dpms;
8261b191 6529 old->load_detect_temp = true;
d2dff872 6530 old->release_fb = NULL;
79e53945 6531
6492711d
CW		 6532 if (!mode)
6533 mode = &load_detect_mode;
79e53945 6534
d2dff872
CW		 6535 /* We need a framebuffer large enough to accommodate all accesses
6536 * that the plane may generate whilst we perform load detection.
6537 * We can not rely on the fbcon either being present (we get called
6538 * during its initialisation to detect all boot displays, or it may
6539 * not even exist) or that it is large enough to satisfy the
6540 * requested mode.
6541 */
94352cf9
DV		 6542 fb = mode_fits_in_fbdev(dev, mode);
6543 if (fb == NULL) {
d2dff872 6544 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6545 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6546 old->release_fb = fb;
d2dff872
CW		 6547 } else
6548 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6549 if (IS_ERR(fb)) {
d2dff872 6550 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6551 mutex_unlock(&crtc->mutex);
0e8b3d3e 6552 return false;
79e53945 6553 }
79e53945 6554
c0c36b94 6555 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6556 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6557 if (old->release_fb)
6558 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6559 mutex_unlock(&crtc->mutex);
0e8b3d3e 6560 return false;
79e53945 6561 }
7173188d 6562
79e53945 6563 /* let the connector get through one full cycle before testing */
9d0498a2 6564 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6565 return true;
79e53945
JB		 6566}
6567
d2434ab7 6568void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6569 struct intel_load_detect_pipe *old)
79e53945 6570{
d2434ab7
DV		 6571 struct intel_encoder *intel_encoder =
6572 intel_attached_encoder(connector);
4ef69c7a 6573 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6574 struct drm_crtc *crtc = encoder->crtc;
79e53945 6575
d2dff872
CW		 6576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6577 connector->base.id, drm_get_connector_name(connector),
6578 encoder->base.id, drm_get_encoder_name(encoder));
6579
8261b191 6580 if (old->load_detect_temp) {
fc303101
DV		 6581 to_intel_connector(connector)->new_encoder = NULL;
6582 intel_encoder->new_crtc = NULL;
6583 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6584
36206361
DV		 6585 if (old->release_fb) {
6586 drm_framebuffer_unregister_private(old->release_fb);
6587 drm_framebuffer_unreference(old->release_fb);
6588 }
d2dff872 6589
67c96400 6590 mutex_unlock(&crtc->mutex);
0622a53c 6591 return;
79e53945
JB		 6592 }
6593
c751ce4f 6594 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6595 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6596 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6597
6598 mutex_unlock(&crtc->mutex);
79e53945
JB		 6599}
6600
6601/* Returns the clock of the currently programmed mode of the given pipe. */
6602static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6603{
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6606 int pipe = intel_crtc->pipe;
548f245b 6607 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6608 u32 fp;
6609 intel_clock_t clock;
6610
6611 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6612 fp = I915_READ(FP0(pipe));
79e53945 6613 else
39adb7a5 6614 fp = I915_READ(FP1(pipe));
79e53945
JB		 6615
6616 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6617 if (IS_PINEVIEW(dev)) {
6618 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6619 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6620 } else {
6621 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6622 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6623 }
6624
a6c45cf0 6625 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6626 if (IS_PINEVIEW(dev))
6627 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6628 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6629 else
6630 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6631 DPLL_FPA01_P1_POST_DIV_SHIFT);
6632
6633 switch (dpll & DPLL_MODE_MASK) {
6634 case DPLLB_MODE_DAC_SERIAL:
6635 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6636 5 : 10;
6637 break;
6638 case DPLLB_MODE_LVDS:
6639 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6640 7 : 14;
6641 break;
6642 default:
28c97730 6643 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6644 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6645 return 0;
6646 }
6647
6648 /* XXX: Handle the 100Mhz refclk */
2177832f 6649 intel_clock(dev, 96000, &clock);
79e53945
JB		 6650 } else {
6651 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6652
6653 if (is_lvds) {
6654 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6655 DPLL_FPA01_P1_POST_DIV_SHIFT);
6656 clock.p2 = 14;
6657
6658 if ((dpll & PLL_REF_INPUT_MASK) ==
6659 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6660 /* XXX: might not be 66MHz */
2177832f 6661 intel_clock(dev, 66000, &clock);
79e53945 6662 } else
2177832f 6663 intel_clock(dev, 48000, &clock);
79e53945
JB		 6664 } else {
6665 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6666 clock.p1 = 2;
6667 else {
6668 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6669 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6670 }
6671 if (dpll & PLL_P2_DIVIDE_BY_4)
6672 clock.p2 = 4;
6673 else
6674 clock.p2 = 2;
6675
2177832f 6676 intel_clock(dev, 48000, &clock);
79e53945
JB		 6677 }
6678 }
6679
6680 /* XXX: It would be nice to validate the clocks, but we can't reuse
6681 * i830PllIsValid() because it relies on the xf86_config connector
6682 * configuration being accurate, which it isn't necessarily.
6683 */
6684
6685 return clock.dot;
6686}
6687
6688/** Returns the currently programmed mode of the given pipe. */
6689struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6690 struct drm_crtc *crtc)
6691{
548f245b 6692 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6694 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6695 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6696 int htot = I915_READ(HTOTAL(cpu_transcoder));
6697 int hsync = I915_READ(HSYNC(cpu_transcoder));
6698 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6699 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6700
6701 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6702 if (!mode)
6703 return NULL;
6704
6705 mode->clock = intel_crtc_clock_get(dev, crtc);
6706 mode->hdisplay = (htot & 0xffff) + 1;
6707 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6708 mode->hsync_start = (hsync & 0xffff) + 1;
6709 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6710 mode->vdisplay = (vtot & 0xffff) + 1;
6711 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6712 mode->vsync_start = (vsync & 0xffff) + 1;
6713 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6714
6715 drm_mode_set_name(mode);
79e53945
JB		 6716
6717 return mode;
6718}
6719
3dec0095 6720static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6721{
6722 struct drm_device *dev = crtc->dev;
6723 drm_i915_private_t *dev_priv = dev->dev_private;
6724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6725 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6726 int dpll_reg = DPLL(pipe);
6727 int dpll;
652c393a 6728
bad720ff 6729 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6730 return;
6731
6732 if (!dev_priv->lvds_downclock_avail)
6733 return;
6734
dbdc6479 6735 dpll = I915_READ(dpll_reg);
652c393a 6736 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6737 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6738
8ac5a6d5 6739 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6740
6741 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6742 I915_WRITE(dpll_reg, dpll);
9d0498a2 6743 intel_wait_for_vblank(dev, pipe);
dbdc6479 6744
652c393a
JB		 6745 dpll = I915_READ(dpll_reg);
6746 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6747 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6748 }
652c393a
JB		 6749}
6750
6751static void intel_decrease_pllclock(struct drm_crtc *crtc)
6752{
6753 struct drm_device *dev = crtc->dev;
6754 drm_i915_private_t *dev_priv = dev->dev_private;
6755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6756
bad720ff 6757 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6758 return;
6759
6760 if (!dev_priv->lvds_downclock_avail)
6761 return;
6762
6763 /*
6764 * Since this is called by a timer, we should never get here in
6765 * the manual case.
6766 */
6767 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6768 int pipe = intel_crtc->pipe;
6769 int dpll_reg = DPLL(pipe);
6770 int dpll;
f6e5b160 6771
44d98a61 6772 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6773
8ac5a6d5 6774 assert_panel_unlocked(dev_priv, pipe);
652c393a 6775
dc257cf1 6776 dpll = I915_READ(dpll_reg);
652c393a
JB		 6777 dpll |= DISPLAY_RATE_SELECT_FPA1;
6778 I915_WRITE(dpll_reg, dpll);
9d0498a2 6779 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6780 dpll = I915_READ(dpll_reg);
6781 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6782 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6783 }
6784
6785}
6786
f047e395
CW		 6787void intel_mark_busy(struct drm_device *dev)
6788{
f047e395
CW		 6789 i915_update_gfx_val(dev->dev_private);
6790}
6791
6792void intel_mark_idle(struct drm_device *dev)
652c393a 6793{
652c393a 6794 struct drm_crtc *crtc;
652c393a
JB		 6795
6796 if (!i915_powersave)
6797 return;
6798
652c393a 6799 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6800 if (!crtc->fb)
6801 continue;
6802
725a5b54 6803 intel_decrease_pllclock(crtc);
652c393a 6804 }
652c393a
JB		 6805}
6806
725a5b54 6807void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6808{
f047e395
CW		 6809 struct drm_device *dev = obj->base.dev;
6810 struct drm_crtc *crtc;
652c393a 6811
f047e395 6812 if (!i915_powersave)
acb87dfb
CW		 6813 return;
6814
652c393a
JB		 6815 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6816 if (!crtc->fb)
6817 continue;
6818
f047e395 6819 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6820 intel_increase_pllclock(crtc);
652c393a
JB		 6821 }
6822}
6823
79e53945
JB		 6824static void intel_crtc_destroy(struct drm_crtc *crtc)
6825{
6826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6827 struct drm_device *dev = crtc->dev;
6828 struct intel_unpin_work *work;
6829 unsigned long flags;
6830
6831 spin_lock_irqsave(&dev->event_lock, flags);
6832 work = intel_crtc->unpin_work;
6833 intel_crtc->unpin_work = NULL;
6834 spin_unlock_irqrestore(&dev->event_lock, flags);
6835
6836 if (work) {
6837 cancel_work_sync(&work->work);
6838 kfree(work);
6839 }
79e53945
JB		 6840
6841 drm_crtc_cleanup(crtc);
67e77c5a 6842
79e53945
JB		 6843 kfree(intel_crtc);
6844}
6845
6b95a207
KH		 6846static void intel_unpin_work_fn(struct work_struct *__work)
6847{
6848 struct intel_unpin_work *work =
6849 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6850 struct drm_device *dev = work->crtc->dev;
6b95a207 6851
b4a98e57 6852 mutex_lock(&dev->struct_mutex);
1690e1eb 6853 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6854 drm_gem_object_unreference(&work->pending_flip_obj->base);
6855 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6856
b4a98e57
CW		 6857 intel_update_fbc(dev);
6858 mutex_unlock(&dev->struct_mutex);
6859
6860 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6861 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6862
6b95a207
KH		 6863 kfree(work);
6864}
6865
1afe3e9d 6866static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6867 struct drm_crtc *crtc)
6b95a207
KH		 6868{
6869 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 struct intel_unpin_work *work;
6b95a207
KH		 6872 unsigned long flags;
6873
6874 /* Ignore early vblank irqs */
6875 if (intel_crtc == NULL)
6876 return;
6877
6878 spin_lock_irqsave(&dev->event_lock, flags);
6879 work = intel_crtc->unpin_work;
e7d841ca
CW		 6880
6881 /* Ensure we don't miss a work->pending update ... */
6882 smp_rmb();
6883
6884 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6885 spin_unlock_irqrestore(&dev->event_lock, flags);
6886 return;
6887 }
6888
e7d841ca
CW		 6889 /* and that the unpin work is consistent wrt ->pending. */
6890 smp_rmb();
6891
6b95a207 6892 intel_crtc->unpin_work = NULL;
6b95a207 6893
45a066eb
RC		 6894 if (work->event)
6895 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6896
0af7e4df
MK		 6897 drm_vblank_put(dev, intel_crtc->pipe);
6898
6b95a207
KH		 6899 spin_unlock_irqrestore(&dev->event_lock, flags);
6900
2c10d571 6901 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6902
6903 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6904
6905 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6906}
6907
1afe3e9d
JB		 6908void intel_finish_page_flip(struct drm_device *dev, int pipe)
6909{
6910 drm_i915_private_t *dev_priv = dev->dev_private;
6911 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6912
49b14a5c 6913 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6914}
6915
6916void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6917{
6918 drm_i915_private_t *dev_priv = dev->dev_private;
6919 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6920
49b14a5c 6921 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6922}
6923
6b95a207
KH		 6924void intel_prepare_page_flip(struct drm_device *dev, int plane)
6925{
6926 drm_i915_private_t *dev_priv = dev->dev_private;
6927 struct intel_crtc *intel_crtc =
6928 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6929 unsigned long flags;
6930
e7d841ca
CW		 6931 /* NB: An MMIO update of the plane base pointer will also
6932 * generate a page-flip completion irq, i.e. every modeset
6933 * is also accompanied by a spurious intel_prepare_page_flip().
6934 */
6b95a207 6935 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6936 if (intel_crtc->unpin_work)
6937 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6938 spin_unlock_irqrestore(&dev->event_lock, flags);
6939}
6940
e7d841ca
CW		 6941inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6942{
6943 /* Ensure that the work item is consistent when activating it ... */
6944 smp_wmb();
6945 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6946 /* and that it is marked active as soon as the irq could fire. */
6947 smp_wmb();
6948}
6949
8c9f3aaf
JB		 6950static int intel_gen2_queue_flip(struct drm_device *dev,
6951 struct drm_crtc *crtc,
6952 struct drm_framebuffer *fb,
6953 struct drm_i915_gem_object *obj)
6954{
6955 struct drm_i915_private *dev_priv = dev->dev_private;
6956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6957 u32 flip_mask;
6d90c952 6958 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6959 int ret;
6960
6d90c952 6961 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6962 if (ret)
83d4092b 6963 goto err;
8c9f3aaf 6964
6d90c952 6965 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6966 if (ret)
83d4092b 6967 goto err_unpin;
8c9f3aaf
JB		 6968
6969 /* Can't queue multiple flips, so wait for the previous
6970 * one to finish before executing the next.
6971 */
6972 if (intel_crtc->plane)
6973 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6974 else
6975 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6976 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6977 intel_ring_emit(ring, MI_NOOP);
6978 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6979 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6980 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6981 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 6982 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 6983
6984 intel_mark_page_flip_active(intel_crtc);
6d90c952 6985 intel_ring_advance(ring);
83d4092b
CW		 6986 return 0;
6987
6988err_unpin:
6989 intel_unpin_fb_obj(obj);
6990err:
8c9f3aaf
JB		 6991 return ret;
6992}
6993
6994static int intel_gen3_queue_flip(struct drm_device *dev,
6995 struct drm_crtc *crtc,
6996 struct drm_framebuffer *fb,
6997 struct drm_i915_gem_object *obj)
6998{
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7001 u32 flip_mask;
6d90c952 7002 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7003 int ret;
7004
6d90c952 7005 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7006 if (ret)
83d4092b 7007 goto err;
8c9f3aaf 7008
6d90c952 7009 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7010 if (ret)
83d4092b 7011 goto err_unpin;
8c9f3aaf
JB		 7012
7013 if (intel_crtc->plane)
7014 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7015 else
7016 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7017 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7018 intel_ring_emit(ring, MI_NOOP);
7019 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7020 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7021 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7022 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7023 intel_ring_emit(ring, MI_NOOP);
7024
e7d841ca 7025 intel_mark_page_flip_active(intel_crtc);
6d90c952 7026 intel_ring_advance(ring);
83d4092b
CW		 7027 return 0;
7028
7029err_unpin:
7030 intel_unpin_fb_obj(obj);
7031err:
8c9f3aaf
JB		 7032 return ret;
7033}
7034
7035static int intel_gen4_queue_flip(struct drm_device *dev,
7036 struct drm_crtc *crtc,
7037 struct drm_framebuffer *fb,
7038 struct drm_i915_gem_object *obj)
7039{
7040 struct drm_i915_private *dev_priv = dev->dev_private;
7041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7042 uint32_t pf, pipesrc;
6d90c952 7043 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7044 int ret;
7045
6d90c952 7046 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7047 if (ret)
83d4092b 7048 goto err;
8c9f3aaf 7049
6d90c952 7050 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7051 if (ret)
83d4092b 7052 goto err_unpin;
8c9f3aaf
JB		 7053
7054 /* i965+ uses the linear or tiled offsets from the
7055 * Display Registers (which do not change across a page-flip)
7056 * so we need only reprogram the base address.
7057 */
6d90c952
DV		 7058 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7059 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7060 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7061 intel_ring_emit(ring,
7062 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7063 obj->tiling_mode);
8c9f3aaf
JB		 7064
7065 /* XXX Enabling the panel-fitter across page-flip is so far
7066 * untested on non-native modes, so ignore it for now.
7067 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7068 */
7069 pf = 0;
7070 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7071 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7072
7073 intel_mark_page_flip_active(intel_crtc);
6d90c952 7074 intel_ring_advance(ring);
83d4092b
CW		 7075 return 0;
7076
7077err_unpin:
7078 intel_unpin_fb_obj(obj);
7079err:
8c9f3aaf
JB		 7080 return ret;
7081}
7082
7083static int intel_gen6_queue_flip(struct drm_device *dev,
7084 struct drm_crtc *crtc,
7085 struct drm_framebuffer *fb,
7086 struct drm_i915_gem_object *obj)
7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7090 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7091 uint32_t pf, pipesrc;
7092 int ret;
7093
6d90c952 7094 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7095 if (ret)
83d4092b 7096 goto err;
8c9f3aaf 7097
6d90c952 7098 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7099 if (ret)
83d4092b 7100 goto err_unpin;
8c9f3aaf 7101
6d90c952
DV		 7102 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7103 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7104 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7105 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7106
dc257cf1
DV		 7107 /* Contrary to the suggestions in the documentation,
7108 * "Enable Panel Fitter" does not seem to be required when page
7109 * flipping with a non-native mode, and worse causes a normal
7110 * modeset to fail.
7111 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7112 */
7113 pf = 0;
8c9f3aaf 7114 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7115 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7116
7117 intel_mark_page_flip_active(intel_crtc);
6d90c952 7118 intel_ring_advance(ring);
83d4092b
CW		 7119 return 0;
7120
7121err_unpin:
7122 intel_unpin_fb_obj(obj);
7123err:
8c9f3aaf
JB		 7124 return ret;
7125}
7126
7c9017e5
JB		 7127/*
7128 * On gen7 we currently use the blit ring because (in early silicon at least)
7129 * the render ring doesn't give us interrpts for page flip completion, which
7130 * means clients will hang after the first flip is queued. Fortunately the
7131 * blit ring generates interrupts properly, so use it instead.
7132 */
7133static int intel_gen7_queue_flip(struct drm_device *dev,
7134 struct drm_crtc *crtc,
7135 struct drm_framebuffer *fb,
7136 struct drm_i915_gem_object *obj)
7137{
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7141 uint32_t plane_bit = 0;
7c9017e5
JB		 7142 int ret;
7143
7144 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7145 if (ret)
83d4092b 7146 goto err;
7c9017e5 7147
cb05d8de
DV		 7148 switch(intel_crtc->plane) {
7149 case PLANE_A:
7150 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7151 break;
7152 case PLANE_B:
7153 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7154 break;
7155 case PLANE_C:
7156 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7157 break;
7158 default:
7159 WARN_ONCE(1, "unknown plane in flip command\n");
7160 ret = -ENODEV;
ab3951eb 7161 goto err_unpin;
cb05d8de
DV		 7162 }
7163
7c9017e5
JB		 7164 ret = intel_ring_begin(ring, 4);
7165 if (ret)
83d4092b 7166 goto err_unpin;
7c9017e5 7167
cb05d8de 7168 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7169 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7170 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7171 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7172
7173 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7174 intel_ring_advance(ring);
83d4092b
CW		 7175 return 0;
7176
7177err_unpin:
7178 intel_unpin_fb_obj(obj);
7179err:
7c9017e5
JB		 7180 return ret;
7181}
7182
8c9f3aaf
JB		 7183static int intel_default_queue_flip(struct drm_device *dev,
7184 struct drm_crtc *crtc,
7185 struct drm_framebuffer *fb,
7186 struct drm_i915_gem_object *obj)
7187{
7188 return -ENODEV;
7189}
7190
6b95a207
KH		 7191static int intel_crtc_page_flip(struct drm_crtc *crtc,
7192 struct drm_framebuffer *fb,
7193 struct drm_pending_vblank_event *event)
7194{
7195 struct drm_device *dev = crtc->dev;
7196 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7197 struct drm_framebuffer *old_fb = crtc->fb;
7198 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7200 struct intel_unpin_work *work;
8c9f3aaf 7201 unsigned long flags;
52e68630 7202 int ret;
6b95a207 7203
e6a595d2
VS		 7204 /* Can't change pixel format via MI display flips. */
7205 if (fb->pixel_format != crtc->fb->pixel_format)
7206 return -EINVAL;
7207
7208 /*
7209 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7210 * Note that pitch changes could also affect these register.
7211 */
7212 if (INTEL_INFO(dev)->gen > 3 &&
7213 (fb->offsets[0] != crtc->fb->offsets[0] ||
7214 fb->pitches[0] != crtc->fb->pitches[0]))
7215 return -EINVAL;
7216
6b95a207
KH		 7217 work = kzalloc(sizeof *work, GFP_KERNEL);
7218 if (work == NULL)
7219 return -ENOMEM;
7220
6b95a207 7221 work->event = event;
b4a98e57 7222 work->crtc = crtc;
4a35f83b 7223 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7224 INIT_WORK(&work->work, intel_unpin_work_fn);
7225
7317c75e
JB		 7226 ret = drm_vblank_get(dev, intel_crtc->pipe);
7227 if (ret)
7228 goto free_work;
7229
6b95a207
KH		 7230 /* We borrow the event spin lock for protecting unpin_work */
7231 spin_lock_irqsave(&dev->event_lock, flags);
7232 if (intel_crtc->unpin_work) {
7233 spin_unlock_irqrestore(&dev->event_lock, flags);
7234 kfree(work);
7317c75e 7235 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7236
7237 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7238 return -EBUSY;
7239 }
7240 intel_crtc->unpin_work = work;
7241 spin_unlock_irqrestore(&dev->event_lock, flags);
7242
b4a98e57
CW		 7243 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7244 flush_workqueue(dev_priv->wq);
7245
79158103
CW		 7246 ret = i915_mutex_lock_interruptible(dev);
7247 if (ret)
7248 goto cleanup;
6b95a207 7249
75dfca80 7250 /* Reference the objects for the scheduled work. */
05394f39
CW		 7251 drm_gem_object_reference(&work->old_fb_obj->base);
7252 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7253
7254 crtc->fb = fb;
96b099fd 7255
e1f99ce6 7256 work->pending_flip_obj = obj;
e1f99ce6 7257
4e5359cd
SF		 7258 work->enable_stall_check = true;
7259
b4a98e57 7260 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7261 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7262
8c9f3aaf
JB		 7263 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7264 if (ret)
7265 goto cleanup_pending;
6b95a207 7266
7782de3b 7267 intel_disable_fbc(dev);
f047e395 7268 intel_mark_fb_busy(obj);
6b95a207
KH		 7269 mutex_unlock(&dev->struct_mutex);
7270
e5510fac
JB		 7271 trace_i915_flip_request(intel_crtc->plane, obj);
7272
6b95a207 7273 return 0;
96b099fd 7274
8c9f3aaf 7275cleanup_pending:
b4a98e57 7276 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7277 crtc->fb = old_fb;
05394f39
CW		 7278 drm_gem_object_unreference(&work->old_fb_obj->base);
7279 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7280 mutex_unlock(&dev->struct_mutex);
7281
79158103 7282cleanup:
96b099fd
CW		 7283 spin_lock_irqsave(&dev->event_lock, flags);
7284 intel_crtc->unpin_work = NULL;
7285 spin_unlock_irqrestore(&dev->event_lock, flags);
7286
7317c75e
JB		 7287 drm_vblank_put(dev, intel_crtc->pipe);
7288free_work:
96b099fd
CW		 7289 kfree(work);
7290
7291 return ret;
6b95a207
KH		 7292}
7293
f6e5b160 7294static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7295 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7296 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7297};
7298
6ed0f796 7299bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7300{
6ed0f796
DV		 7301 struct intel_encoder *other_encoder;
7302 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7303
6ed0f796
DV		 7304 if (WARN_ON(!crtc))
7305 return false;
7306
7307 list_for_each_entry(other_encoder,
7308 &crtc->dev->mode_config.encoder_list,
7309 base.head) {
7310
7311 if (&other_encoder->new_crtc->base != crtc ||
7312 encoder == other_encoder)
7313 continue;
7314 else
7315 return true;
f47166d2
CW		 7316 }
7317
6ed0f796
DV		 7318 return false;
7319}
47f1c6c9 7320
50f56119
DV		 7321static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7322 struct drm_crtc *crtc)
7323{
7324 struct drm_device *dev;
7325 struct drm_crtc *tmp;
7326 int crtc_mask = 1;
47f1c6c9 7327
50f56119 7328 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7329
50f56119 7330 dev = crtc->dev;
47f1c6c9 7331
50f56119
DV		 7332 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7333 if (tmp == crtc)
7334 break;
7335 crtc_mask <<= 1;
7336 }
47f1c6c9 7337
50f56119
DV		 7338 if (encoder->possible_crtcs & crtc_mask)
7339 return true;
7340 return false;
47f1c6c9 7341}
79e53945 7342
9a935856
DV		 7343/**
7344 * intel_modeset_update_staged_output_state
7345 *
7346 * Updates the staged output configuration state, e.g. after we've read out the
7347 * current hw state.
7348 */
7349static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7350{
9a935856
DV		 7351 struct intel_encoder *encoder;
7352 struct intel_connector *connector;
f6e5b160 7353
9a935856
DV		 7354 list_for_each_entry(connector, &dev->mode_config.connector_list,
7355 base.head) {
7356 connector->new_encoder =
7357 to_intel_encoder(connector->base.encoder);
7358 }
f6e5b160 7359
9a935856
DV		 7360 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7361 base.head) {
7362 encoder->new_crtc =
7363 to_intel_crtc(encoder->base.crtc);
7364 }
f6e5b160
CW		 7365}
7366
9a935856
DV		 7367/**
7368 * intel_modeset_commit_output_state
7369 *
7370 * This function copies the stage display pipe configuration to the real one.
7371 */
7372static void intel_modeset_commit_output_state(struct drm_device *dev)
7373{
7374 struct intel_encoder *encoder;
7375 struct intel_connector *connector;
f6e5b160 7376
9a935856
DV		 7377 list_for_each_entry(connector, &dev->mode_config.connector_list,
7378 base.head) {
7379 connector->base.encoder = &connector->new_encoder->base;
7380 }
f6e5b160 7381
9a935856
DV		 7382 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7383 base.head) {
7384 encoder->base.crtc = &encoder->new_crtc->base;
7385 }
7386}
7387
4e53c2e0
DV		 7388static int
7389pipe_config_set_bpp(struct drm_crtc *crtc,
7390 struct drm_framebuffer *fb,
7391 struct intel_crtc_config *pipe_config)
7392{
7393 struct drm_device *dev = crtc->dev;
7394 struct drm_connector *connector;
7395 int bpp;
7396
7397 switch (fb->depth) {
7398 case 8:
7399 bpp = 8*3; /* since we go through a colormap */
7400 break;
7401 case 15:
7402 case 16:
7403 bpp = 6*3; /* min is 18bpp */
7404 break;
7405 case 24:
7406 bpp = 8*3;
7407 break;
7408 case 30:
baba133a
DV		 7409 if (INTEL_INFO(dev)->gen < 4) {
7410 DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n");
7411 return -EINVAL;
7412 }
7413
4e53c2e0
DV		 7414 bpp = 10*3;
7415 break;
baba133a 7416 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7417 default:
7418 DRM_DEBUG_KMS("unsupported depth\n");
7419 return -EINVAL;
7420 }
7421
4e53c2e0
DV		 7422 pipe_config->pipe_bpp = bpp;
7423
7424 /* Clamp display bpp to EDID value */
7425 list_for_each_entry(connector, &dev->mode_config.connector_list,
7426 head) {
7427 if (connector->encoder && connector->encoder->crtc != crtc)
7428 continue;
7429
7430 /* Don't use an invalid EDID bpc value */
7431 if (connector->display_info.bpc &&
7432 connector->display_info.bpc * 3 < bpp) {
7433 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7434 bpp, connector->display_info.bpc*3);
7435 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7436 }
7437 }
7438
7439 return bpp;
7440}
7441
b8cecdf5
DV		 7442static struct intel_crtc_config *
7443intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7444 struct drm_framebuffer *fb,
b8cecdf5 7445 struct drm_display_mode *mode)
ee7b9f93 7446{
7758a113 7447 struct drm_device *dev = crtc->dev;
7758a113
DV		 7448 struct drm_encoder_helper_funcs *encoder_funcs;
7449 struct intel_encoder *encoder;
b8cecdf5 7450 struct intel_crtc_config *pipe_config;
4e53c2e0 7451 int plane_bpp;
ee7b9f93 7452
b8cecdf5
DV		 7453 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7454 if (!pipe_config)
7758a113
DV		 7455 return ERR_PTR(-ENOMEM);
7456
b8cecdf5
DV		 7457 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7458 drm_mode_copy(&pipe_config->requested_mode, mode);
7459
4e53c2e0
DV		 7460 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7461 if (plane_bpp < 0)
7462 goto fail;
7463
7758a113
DV		 7464 /* Pass our mode to the connectors and the CRTC to give them a chance to
7465 * adjust it according to limitations or connector properties, and also
7466 * a chance to reject the mode entirely.
47f1c6c9 7467 */
7758a113
DV		 7468 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7469 base.head) {
47f1c6c9 7470
7758a113
DV		 7471 if (&encoder->new_crtc->base != crtc)
7472 continue;
7ae89233
DV		 7473
7474 if (encoder->compute_config) {
7475 if (!(encoder->compute_config(encoder, pipe_config))) {
7476 DRM_DEBUG_KMS("Encoder config failure\n");
7477 goto fail;
7478 }
7479
7480 continue;
7481 }
7482
7758a113 7483 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7484 if (!(encoder_funcs->mode_fixup(&encoder->base,
7485 &pipe_config->requested_mode,
7486 &pipe_config->adjusted_mode))) {
7758a113
DV		 7487 DRM_DEBUG_KMS("Encoder fixup failed\n");
7488 goto fail;
7489 }
ee7b9f93 7490 }
47f1c6c9 7491
b8cecdf5 7492 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7493 DRM_DEBUG_KMS("CRTC fixup failed\n");
7494 goto fail;
ee7b9f93 7495 }
7758a113 7496 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7497
4e53c2e0
DV		 7498 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7499 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7500 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7501
b8cecdf5 7502 return pipe_config;
7758a113 7503fail:
b8cecdf5 7504 kfree(pipe_config);
7758a113 7505 return ERR_PTR(-EINVAL);
ee7b9f93 7506}
47f1c6c9 7507
e2e1ed41
DV		 7508/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7509 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7510static void
7511intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7512 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7513{
7514 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7515 struct drm_device *dev = crtc->dev;
7516 struct intel_encoder *encoder;
7517 struct intel_connector *connector;
7518 struct drm_crtc *tmp_crtc;
79e53945 7519
e2e1ed41 7520 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7521
e2e1ed41
DV		 7522 /* Check which crtcs have changed outputs connected to them, these need
7523 * to be part of the prepare_pipes mask. We don't (yet) support global
7524 * modeset across multiple crtcs, so modeset_pipes will only have one
7525 * bit set at most. */
7526 list_for_each_entry(connector, &dev->mode_config.connector_list,
7527 base.head) {
7528 if (connector->base.encoder == &connector->new_encoder->base)
7529 continue;
79e53945 7530
e2e1ed41
DV		 7531 if (connector->base.encoder) {
7532 tmp_crtc = connector->base.encoder->crtc;
7533
7534 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7535 }
7536
7537 if (connector->new_encoder)
7538 *prepare_pipes |=
7539 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7540 }
7541
e2e1ed41
DV		 7542 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7543 base.head) {
7544 if (encoder->base.crtc == &encoder->new_crtc->base)
7545 continue;
7546
7547 if (encoder->base.crtc) {
7548 tmp_crtc = encoder->base.crtc;
7549
7550 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7551 }
7552
7553 if (encoder->new_crtc)
7554 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7555 }
7556
e2e1ed41
DV		 7557 /* Check for any pipes that will be fully disabled ... */
7558 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7559 base.head) {
7560 bool used = false;
22fd0fab 7561
e2e1ed41
DV		 7562 /* Don't try to disable disabled crtcs. */
7563 if (!intel_crtc->base.enabled)
7564 continue;
7e7d76c3 7565
e2e1ed41
DV		 7566 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7567 base.head) {
7568 if (encoder->new_crtc == intel_crtc)
7569 used = true;
7570 }
7571
7572 if (!used)
7573 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7574 }
7575
e2e1ed41
DV		 7576
7577 /* set_mode is also used to update properties on life display pipes. */
7578 intel_crtc = to_intel_crtc(crtc);
7579 if (crtc->enabled)
7580 *prepare_pipes |= 1 << intel_crtc->pipe;
7581
7582 /* We only support modeset on one single crtc, hence we need to do that
7583 * only for the passed in crtc iff we change anything else than just
7584 * disable crtcs.
7585 *
7586 * This is actually not true, to be fully compatible with the old crtc
7587 * helper we automatically disable _any_ output (i.e. doesn't need to be
7588 * connected to the crtc we're modesetting on) if it's disconnected.
7589 * Which is a rather nutty api (since changed the output configuration
7590 * without userspace's explicit request can lead to confusion), but
7591 * alas. Hence we currently need to modeset on all pipes we prepare. */
7592 if (*prepare_pipes)
7593 *modeset_pipes = *prepare_pipes;
7594
7595 /* ... and mask these out. */
7596 *modeset_pipes &= ~(*disable_pipes);
7597 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7598}
79e53945 7599
ea9d758d 7600static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7601{
ea9d758d 7602 struct drm_encoder *encoder;
f6e5b160 7603 struct drm_device *dev = crtc->dev;
f6e5b160 7604
ea9d758d
DV		 7605 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7606 if (encoder->crtc == crtc)
7607 return true;
7608
7609 return false;
7610}
7611
7612static void
7613intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7614{
7615 struct intel_encoder *intel_encoder;
7616 struct intel_crtc *intel_crtc;
7617 struct drm_connector *connector;
7618
7619 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7620 base.head) {
7621 if (!intel_encoder->base.crtc)
7622 continue;
7623
7624 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7625
7626 if (prepare_pipes & (1 << intel_crtc->pipe))
7627 intel_encoder->connectors_active = false;
7628 }
7629
7630 intel_modeset_commit_output_state(dev);
7631
7632 /* Update computed state. */
7633 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7634 base.head) {
7635 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7636 }
7637
7638 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7639 if (!connector->encoder || !connector->encoder->crtc)
7640 continue;
7641
7642 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7643
7644 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7645 struct drm_property *dpms_property =
7646 dev->mode_config.dpms_property;
7647
ea9d758d 7648 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7649 drm_object_property_set_value(&connector->base,
68d34720
DV		 7650 dpms_property,
7651 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7652
7653 intel_encoder = to_intel_encoder(connector->encoder);
7654 intel_encoder->connectors_active = true;
7655 }
7656 }
7657
7658}
7659
25c5b266
DV		 7660#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7661 list_for_each_entry((intel_crtc), \
7662 &(dev)->mode_config.crtc_list, \
7663 base.head) \
7664 if (mask & (1 <<(intel_crtc)->pipe)) \
7665
b980514c 7666void
8af6cf88
DV		 7667intel_modeset_check_state(struct drm_device *dev)
7668{
7669 struct intel_crtc *crtc;
7670 struct intel_encoder *encoder;
7671 struct intel_connector *connector;
7672
7673 list_for_each_entry(connector, &dev->mode_config.connector_list,
7674 base.head) {
7675 /* This also checks the encoder/connector hw state with the
7676 * ->get_hw_state callbacks. */
7677 intel_connector_check_state(connector);
7678
7679 WARN(&connector->new_encoder->base != connector->base.encoder,
7680 "connector's staged encoder doesn't match current encoder\n");
7681 }
7682
7683 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7684 base.head) {
7685 bool enabled = false;
7686 bool active = false;
7687 enum pipe pipe, tracked_pipe;
7688
7689 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7690 encoder->base.base.id,
7691 drm_get_encoder_name(&encoder->base));
7692
7693 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7694 "encoder's stage crtc doesn't match current crtc\n");
7695 WARN(encoder->connectors_active && !encoder->base.crtc,
7696 "encoder's active_connectors set, but no crtc\n");
7697
7698 list_for_each_entry(connector, &dev->mode_config.connector_list,
7699 base.head) {
7700 if (connector->base.encoder != &encoder->base)
7701 continue;
7702 enabled = true;
7703 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7704 active = true;
7705 }
7706 WARN(!!encoder->base.crtc != enabled,
7707 "encoder's enabled state mismatch "
7708 "(expected %i, found %i)\n",
7709 !!encoder->base.crtc, enabled);
7710 WARN(active && !encoder->base.crtc,
7711 "active encoder with no crtc\n");
7712
7713 WARN(encoder->connectors_active != active,
7714 "encoder's computed active state doesn't match tracked active state "
7715 "(expected %i, found %i)\n", active, encoder->connectors_active);
7716
7717 active = encoder->get_hw_state(encoder, &pipe);
7718 WARN(active != encoder->connectors_active,
7719 "encoder's hw state doesn't match sw tracking "
7720 "(expected %i, found %i)\n",
7721 encoder->connectors_active, active);
7722
7723 if (!encoder->base.crtc)
7724 continue;
7725
7726 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7727 WARN(active && pipe != tracked_pipe,
7728 "active encoder's pipe doesn't match"
7729 "(expected %i, found %i)\n",
7730 tracked_pipe, pipe);
7731
7732 }
7733
7734 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7735 base.head) {
7736 bool enabled = false;
7737 bool active = false;
7738
7739 DRM_DEBUG_KMS("[CRTC:%d]\n",
7740 crtc->base.base.id);
7741
7742 WARN(crtc->active && !crtc->base.enabled,
7743 "active crtc, but not enabled in sw tracking\n");
7744
7745 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7746 base.head) {
7747 if (encoder->base.crtc != &crtc->base)
7748 continue;
7749 enabled = true;
7750 if (encoder->connectors_active)
7751 active = true;
7752 }
7753 WARN(active != crtc->active,
7754 "crtc's computed active state doesn't match tracked active state "
7755 "(expected %i, found %i)\n", active, crtc->active);
7756 WARN(enabled != crtc->base.enabled,
7757 "crtc's computed enabled state doesn't match tracked enabled state "
7758 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7759
7760 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7761 }
7762}
7763
c0c36b94
CW		 7764int intel_set_mode(struct drm_crtc *crtc,
7765 struct drm_display_mode *mode,
7766 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7767{
7768 struct drm_device *dev = crtc->dev;
dbf2b54e 7769 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7770 struct drm_display_mode *saved_mode, *saved_hwmode;
7771 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7772 struct intel_crtc *intel_crtc;
7773 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7774 int ret = 0;
a6778b3c 7775
3ac18232 7776 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7777 if (!saved_mode)
7778 return -ENOMEM;
3ac18232 7779 saved_hwmode = saved_mode + 1;
a6778b3c 7780
e2e1ed41 7781 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7782 &prepare_pipes, &disable_pipes);
7783
3ac18232
TG		 7784 *saved_hwmode = crtc->hwmode;
7785 *saved_mode = crtc->mode;
a6778b3c 7786
25c5b266
DV		 7787 /* Hack: Because we don't (yet) support global modeset on multiple
7788 * crtcs, we don't keep track of the new mode for more than one crtc.
7789 * Hence simply check whether any bit is set in modeset_pipes in all the
7790 * pieces of code that are not yet converted to deal with mutliple crtcs
7791 * changing their mode at the same time. */
25c5b266 7792 if (modeset_pipes) {
4e53c2e0 7793 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7794 if (IS_ERR(pipe_config)) {
7795 ret = PTR_ERR(pipe_config);
7796 pipe_config = NULL;
7797
3ac18232 7798 goto out;
25c5b266 7799 }
25c5b266 7800 }
a6778b3c 7801
460da916
DV		 7802 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7803 modeset_pipes, prepare_pipes, disable_pipes);
7804
7805 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7806 intel_crtc_disable(&intel_crtc->base);
7807
ea9d758d
DV		 7808 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7809 if (intel_crtc->base.enabled)
7810 dev_priv->display.crtc_disable(&intel_crtc->base);
7811 }
a6778b3c 7812
6c4c86f5
DV		 7813 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7814 * to set it here already despite that we pass it down the callchain.
f6e5b160 7815 */
b8cecdf5 7816 if (modeset_pipes) {
25c5b266 7817 crtc->mode = *mode;
b8cecdf5
DV		 7818 /* mode_set/enable/disable functions rely on a correct pipe
7819 * config. */
7820 to_intel_crtc(crtc)->config = *pipe_config;
7821 }
7758a113 7822
ea9d758d
DV		 7823 /* Only after disabling all output pipelines that will be changed can we
7824 * update the the output configuration. */
7825 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7826
47fab737
DV		 7827 if (dev_priv->display.modeset_global_resources)
7828 dev_priv->display.modeset_global_resources(dev);
7829
a6778b3c
DV		 7830 /* Set up the DPLL and any encoders state that needs to adjust or depend
7831 * on the DPLL.
f6e5b160 7832 */
25c5b266 7833 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7834 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7835 x, y, fb);
7836 if (ret)
7837 goto done;
a6778b3c
DV		 7838 }
7839
7840 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7841 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7842 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7843
25c5b266
DV		 7844 if (modeset_pipes) {
7845 /* Store real post-adjustment hardware mode. */
b8cecdf5 7846 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 7847
25c5b266
DV		 7848 /* Calculate and store various constants which
7849 * are later needed by vblank and swap-completion
7850 * timestamping. They are derived from true hwmode.
7851 */
7852 drm_calc_timestamping_constants(crtc);
7853 }
a6778b3c
DV		 7854
7855 /* FIXME: add subpixel order */
7856done:
c0c36b94 7857 if (ret && crtc->enabled) {
3ac18232
TG		 7858 crtc->hwmode = *saved_hwmode;
7859 crtc->mode = *saved_mode;
8af6cf88
DV		 7860 } else {
7861 intel_modeset_check_state(dev);
a6778b3c
DV		 7862 }
7863
3ac18232 7864out:
b8cecdf5 7865 kfree(pipe_config);
3ac18232 7866 kfree(saved_mode);
a6778b3c 7867 return ret;
f6e5b160
CW		 7868}
7869
c0c36b94
CW		 7870void intel_crtc_restore_mode(struct drm_crtc *crtc)
7871{
7872 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7873}
7874
25c5b266
DV		 7875#undef for_each_intel_crtc_masked
7876
d9e55608
DV		 7877static void intel_set_config_free(struct intel_set_config *config)
7878{
7879 if (!config)
7880 return;
7881
1aa4b628
DV		 7882 kfree(config->save_connector_encoders);
7883 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7884 kfree(config);
7885}
7886
85f9eb71
DV		 7887static int intel_set_config_save_state(struct drm_device *dev,
7888 struct intel_set_config *config)
7889{
85f9eb71
DV		 7890 struct drm_encoder *encoder;
7891 struct drm_connector *connector;
7892 int count;
7893
1aa4b628
DV		 7894 config->save_encoder_crtcs =
7895 kcalloc(dev->mode_config.num_encoder,
7896 sizeof(struct drm_crtc *), GFP_KERNEL);
7897 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7898 return -ENOMEM;
7899
1aa4b628
DV		 7900 config->save_connector_encoders =
7901 kcalloc(dev->mode_config.num_connector,
7902 sizeof(struct drm_encoder *), GFP_KERNEL);
7903 if (!config->save_connector_encoders)
85f9eb71
DV		 7904 return -ENOMEM;
7905
7906 /* Copy data. Note that driver private data is not affected.
7907 * Should anything bad happen only the expected state is
7908 * restored, not the drivers personal bookkeeping.
7909 */
85f9eb71
DV		 7910 count = 0;
7911 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7912 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7913 }
7914
7915 count = 0;
7916 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7917 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7918 }
7919
7920 return 0;
7921}
7922
7923static void intel_set_config_restore_state(struct drm_device *dev,
7924 struct intel_set_config *config)
7925{
9a935856
DV		 7926 struct intel_encoder *encoder;
7927 struct intel_connector *connector;
85f9eb71
DV		 7928 int count;
7929
85f9eb71 7930 count = 0;
9a935856
DV		 7931 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7932 encoder->new_crtc =
7933 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7934 }
7935
7936 count = 0;
9a935856
DV		 7937 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7938 connector->new_encoder =
7939 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7940 }
7941}
7942
5e2b584e
DV		 7943static void
7944intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7945 struct intel_set_config *config)
7946{
7947
7948 /* We should be able to check here if the fb has the same properties
7949 * and then just flip_or_move it */
7950 if (set->crtc->fb != set->fb) {
7951 /* If we have no fb then treat it as a full mode set */
7952 if (set->crtc->fb == NULL) {
7953 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7954 config->mode_changed = true;
7955 } else if (set->fb == NULL) {
7956 config->mode_changed = true;
7957 } else if (set->fb->depth != set->crtc->fb->depth) {
7958 config->mode_changed = true;
7959 } else if (set->fb->bits_per_pixel !=
7960 set->crtc->fb->bits_per_pixel) {
7961 config->mode_changed = true;
7962 } else
7963 config->fb_changed = true;
7964 }
7965
835c5873 7966 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7967 config->fb_changed = true;
7968
7969 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7970 DRM_DEBUG_KMS("modes are different, full mode set\n");
7971 drm_mode_debug_printmodeline(&set->crtc->mode);
7972 drm_mode_debug_printmodeline(set->mode);
7973 config->mode_changed = true;
7974 }
7975}
7976
2e431051 7977static int
9a935856
DV		 7978intel_modeset_stage_output_state(struct drm_device *dev,
7979 struct drm_mode_set *set,
7980 struct intel_set_config *config)
50f56119 7981{
85f9eb71 7982 struct drm_crtc *new_crtc;
9a935856
DV		 7983 struct intel_connector *connector;
7984 struct intel_encoder *encoder;
2e431051 7985 int count, ro;
50f56119 7986
9abdda74 7987 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7988 * of connectors. For paranoia, double-check this. */
7989 WARN_ON(!set->fb && (set->num_connectors != 0));
7990 WARN_ON(set->fb && (set->num_connectors == 0));
7991
50f56119 7992 count = 0;
9a935856
DV		 7993 list_for_each_entry(connector, &dev->mode_config.connector_list,
7994 base.head) {
7995 /* Otherwise traverse passed in connector list and get encoders
7996 * for them. */
50f56119 7997 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7998 if (set->connectors[ro] == &connector->base) {
7999 connector->new_encoder = connector->encoder;
50f56119
DV		 8000 break;
8001 }
8002 }
8003
9a935856
DV		 8004 /* If we disable the crtc, disable all its connectors. Also, if
8005 * the connector is on the changing crtc but not on the new
8006 * connector list, disable it. */
8007 if ((!set->fb || ro == set->num_connectors) &&
8008 connector->base.encoder &&
8009 connector->base.encoder->crtc == set->crtc) {
8010 connector->new_encoder = NULL;
8011
8012 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8013 connector->base.base.id,
8014 drm_get_connector_name(&connector->base));
8015 }
8016
8017
8018 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8019 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8020 config->mode_changed = true;
50f56119
DV		 8021 }
8022 }
9a935856 8023 /* connector->new_encoder is now updated for all connectors. */
50f56119 8024
9a935856 8025 /* Update crtc of enabled connectors. */
50f56119 8026 count = 0;
9a935856
DV		 8027 list_for_each_entry(connector, &dev->mode_config.connector_list,
8028 base.head) {
8029 if (!connector->new_encoder)
50f56119
DV		 8030 continue;
8031
9a935856 8032 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8033
8034 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8035 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8036 new_crtc = set->crtc;
8037 }
8038
8039 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8040 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8041 new_crtc)) {
5e2b584e 8042 return -EINVAL;
50f56119 8043 }
9a935856
DV		 8044 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8045
8046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8047 connector->base.base.id,
8048 drm_get_connector_name(&connector->base),
8049 new_crtc->base.id);
8050 }
8051
8052 /* Check for any encoders that needs to be disabled. */
8053 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8054 base.head) {
8055 list_for_each_entry(connector,
8056 &dev->mode_config.connector_list,
8057 base.head) {
8058 if (connector->new_encoder == encoder) {
8059 WARN_ON(!connector->new_encoder->new_crtc);
8060
8061 goto next_encoder;
8062 }
8063 }
8064 encoder->new_crtc = NULL;
8065next_encoder:
8066 /* Only now check for crtc changes so we don't miss encoders
8067 * that will be disabled. */
8068 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8069 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8070 config->mode_changed = true;
50f56119
DV		 8071 }
8072 }
9a935856 8073 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8074
2e431051
DV		 8075 return 0;
8076}
8077
8078static int intel_crtc_set_config(struct drm_mode_set *set)
8079{
8080 struct drm_device *dev;
2e431051
DV		 8081 struct drm_mode_set save_set;
8082 struct intel_set_config *config;
8083 int ret;
2e431051 8084
8d3e375e
DV		 8085 BUG_ON(!set);
8086 BUG_ON(!set->crtc);
8087 BUG_ON(!set->crtc->helper_private);
2e431051 8088
7e53f3a4
DV		 8089 /* Enforce sane interface api - has been abused by the fb helper. */
8090 BUG_ON(!set->mode && set->fb);
8091 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8092
2e431051
DV		 8093 if (set->fb) {
8094 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8095 set->crtc->base.id, set->fb->base.id,
8096 (int)set->num_connectors, set->x, set->y);
8097 } else {
8098 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8099 }
8100
8101 dev = set->crtc->dev;
8102
8103 ret = -ENOMEM;
8104 config = kzalloc(sizeof(*config), GFP_KERNEL);
8105 if (!config)
8106 goto out_config;
8107
8108 ret = intel_set_config_save_state(dev, config);
8109 if (ret)
8110 goto out_config;
8111
8112 save_set.crtc = set->crtc;
8113 save_set.mode = &set->crtc->mode;
8114 save_set.x = set->crtc->x;
8115 save_set.y = set->crtc->y;
8116 save_set.fb = set->crtc->fb;
8117
8118 /* Compute whether we need a full modeset, only an fb base update or no
8119 * change at all. In the future we might also check whether only the
8120 * mode changed, e.g. for LVDS where we only change the panel fitter in
8121 * such cases. */
8122 intel_set_config_compute_mode_changes(set, config);
8123
9a935856 8124 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8125 if (ret)
8126 goto fail;
8127
5e2b584e 8128 if (config->mode_changed) {
87f1faa6 8129 if (set->mode) {
50f56119
DV		 8130 DRM_DEBUG_KMS("attempting to set mode from"
8131 " userspace\n");
8132 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8133 }
8134
c0c36b94
CW		 8135 ret = intel_set_mode(set->crtc, set->mode,
8136 set->x, set->y, set->fb);
8137 if (ret) {
8138 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8139 set->crtc->base.id, ret);
87f1faa6
DV		 8140 goto fail;
8141 }
5e2b584e 8142 } else if (config->fb_changed) {
4878cae2
VS		 8143 intel_crtc_wait_for_pending_flips(set->crtc);
8144
4f660f49 8145 ret = intel_pipe_set_base(set->crtc,
94352cf9 8146 set->x, set->y, set->fb);
50f56119
DV		 8147 }
8148
d9e55608
DV		 8149 intel_set_config_free(config);
8150
50f56119
DV		 8151 return 0;
8152
8153fail:
85f9eb71 8154 intel_set_config_restore_state(dev, config);
50f56119
DV		 8155
8156 /* Try to restore the config */
5e2b584e 8157 if (config->mode_changed &&
c0c36b94
CW		 8158 intel_set_mode(save_set.crtc, save_set.mode,
8159 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8160 DRM_ERROR("failed to restore config after modeset failure\n");
8161
d9e55608
DV		 8162out_config:
8163 intel_set_config_free(config);
50f56119
DV		 8164 return ret;
8165}
f6e5b160
CW		 8166
8167static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8168 .cursor_set = intel_crtc_cursor_set,
8169 .cursor_move = intel_crtc_cursor_move,
8170 .gamma_set = intel_crtc_gamma_set,
50f56119 8171 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8172 .destroy = intel_crtc_destroy,
8173 .page_flip = intel_crtc_page_flip,
8174};
8175
79f689aa
PZ		 8176static void intel_cpu_pll_init(struct drm_device *dev)
8177{
affa9354 8178 if (HAS_DDI(dev))
79f689aa
PZ		 8179 intel_ddi_pll_init(dev);
8180}
8181
ee7b9f93
JB		 8182static void intel_pch_pll_init(struct drm_device *dev)
8183{
8184 drm_i915_private_t *dev_priv = dev->dev_private;
8185 int i;
8186
8187 if (dev_priv->num_pch_pll == 0) {
8188 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8189 return;
8190 }
8191
8192 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8193 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8194 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8195 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8196 }
8197}
8198
b358d0a6 8199static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8200{
22fd0fab 8201 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8202 struct intel_crtc *intel_crtc;
8203 int i;
8204
8205 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8206 if (intel_crtc == NULL)
8207 return;
8208
8209 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8210
8211 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8212 for (i = 0; i < 256; i++) {
8213 intel_crtc->lut_r[i] = i;
8214 intel_crtc->lut_g[i] = i;
8215 intel_crtc->lut_b[i] = i;
8216 }
8217
80824003
JB		 8218 /* Swap pipes & planes for FBC on pre-965 */
8219 intel_crtc->pipe = pipe;
8220 intel_crtc->plane = pipe;
a5c961d1 8221 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8222 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8223 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8224 intel_crtc->plane = !pipe;
80824003
JB		 8225 }
8226
22fd0fab
JB		 8227 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8228 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8229 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8230 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8231
79e53945 8232 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8233}
8234
08d7b3d1 8235int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8236 struct drm_file *file)
08d7b3d1 8237{
08d7b3d1 8238 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8239 struct drm_mode_object *drmmode_obj;
8240 struct intel_crtc *crtc;
08d7b3d1 8241
1cff8f6b
DV		 8242 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8243 return -ENODEV;
08d7b3d1 8244
c05422d5
DV		 8245 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8246 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8247
c05422d5 8248 if (!drmmode_obj) {
08d7b3d1
CW		 8249 DRM_ERROR("no such CRTC id\n");
8250 return -EINVAL;
8251 }
8252
c05422d5
DV		 8253 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8254 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8255
c05422d5 8256 return 0;
08d7b3d1
CW		 8257}
8258
66a9278e 8259static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8260{
66a9278e
DV		 8261 struct drm_device *dev = encoder->base.dev;
8262 struct intel_encoder *source_encoder;
79e53945 8263 int index_mask = 0;
79e53945
JB		 8264 int entry = 0;
8265
66a9278e
DV		 8266 list_for_each_entry(source_encoder,
8267 &dev->mode_config.encoder_list, base.head) {
8268
8269 if (encoder == source_encoder)
79e53945 8270 index_mask |= (1 << entry);
66a9278e
DV		 8271
8272 /* Intel hw has only one MUX where enocoders could be cloned. */
8273 if (encoder->cloneable && source_encoder->cloneable)
8274 index_mask |= (1 << entry);
8275
79e53945
JB		 8276 entry++;
8277 }
4ef69c7a 8278
79e53945
JB		 8279 return index_mask;
8280}
8281
4d302442
CW		 8282static bool has_edp_a(struct drm_device *dev)
8283{
8284 struct drm_i915_private *dev_priv = dev->dev_private;
8285
8286 if (!IS_MOBILE(dev))
8287 return false;
8288
8289 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8290 return false;
8291
8292 if (IS_GEN5(dev) &&
8293 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8294 return false;
8295
8296 return true;
8297}
8298
79e53945
JB		 8299static void intel_setup_outputs(struct drm_device *dev)
8300{
725e30ad 8301 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8302 struct intel_encoder *encoder;
cb0953d7 8303 bool dpd_is_edp = false;
f3cfcba6 8304 bool has_lvds;
79e53945 8305
f3cfcba6 8306 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8307 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8308 /* disable the panel fitter on everything but LVDS */
8309 I915_WRITE(PFIT_CONTROL, 0);
8310 }
79e53945 8311
affa9354 8312 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8313 intel_crt_init(dev);
cb0953d7 8314
affa9354 8315 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8316 int found;
8317
8318 /* Haswell uses DDI functions to detect digital outputs */
8319 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8320 /* DDI A only supports eDP */
8321 if (found)
8322 intel_ddi_init(dev, PORT_A);
8323
8324 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8325 * register */
8326 found = I915_READ(SFUSE_STRAP);
8327
8328 if (found & SFUSE_STRAP_DDIB_DETECTED)
8329 intel_ddi_init(dev, PORT_B);
8330 if (found & SFUSE_STRAP_DDIC_DETECTED)
8331 intel_ddi_init(dev, PORT_C);
8332 if (found & SFUSE_STRAP_DDID_DETECTED)
8333 intel_ddi_init(dev, PORT_D);
8334 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8335 int found;
270b3042
DV		 8336 dpd_is_edp = intel_dpd_is_edp(dev);
8337
8338 if (has_edp_a(dev))
8339 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8340
dc0fa718 8341 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8342 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8343 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8344 if (!found)
e2debe91 8345 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8346 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8347 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8348 }
8349
dc0fa718 8350 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8351 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8352
dc0fa718 8353 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8354 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8355
5eb08b69 8356 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8357 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8358
270b3042 8359 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8360 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8361 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8362 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8363 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8364 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8365
dc0fa718 8366 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8367 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8368 PORT_B);
67cfc203
VS		 8369 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8370 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8371 }
103a196f 8372 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8373 bool found = false;
7d57382e 8374
e2debe91 8375 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8376 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8377 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8378 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8379 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8380 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8381 }
27185ae1 8382
b01f2c3a
JB		 8383 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8384 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8385 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8386 }
725e30ad 8387 }
13520b05
KH		 8388
8389 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8390
e2debe91 8391 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8392 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8393 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8394 }
27185ae1 8395
e2debe91 8396 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8397
b01f2c3a
JB		 8398 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8399 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8400 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8401 }
8402 if (SUPPORTS_INTEGRATED_DP(dev)) {
8403 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8404 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8405 }
725e30ad 8406 }
27185ae1 8407
b01f2c3a
JB		 8408 if (SUPPORTS_INTEGRATED_DP(dev) &&
8409 (I915_READ(DP_D) & DP_DETECTED)) {
8410 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8411 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8412 }
bad720ff 8413 } else if (IS_GEN2(dev))
79e53945
JB		 8414 intel_dvo_init(dev);
8415
103a196f 8416 if (SUPPORTS_TV(dev))
79e53945
JB		 8417 intel_tv_init(dev);
8418
4ef69c7a
CW		 8419 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8420 encoder->base.possible_crtcs = encoder->crtc_mask;
8421 encoder->base.possible_clones =
66a9278e 8422 intel_encoder_clones(encoder);
79e53945 8423 }
47356eb6 8424
dde86e2d 8425 intel_init_pch_refclk(dev);
270b3042
DV		 8426
8427 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8428}
8429
8430static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8431{
8432 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8433
8434 drm_framebuffer_cleanup(fb);
05394f39 8435 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8436
8437 kfree(intel_fb);
8438}
8439
8440static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8441 struct drm_file *file,
79e53945
JB		 8442 unsigned int *handle)
8443{
8444 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8445 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8446
05394f39 8447 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8448}
8449
8450static const struct drm_framebuffer_funcs intel_fb_funcs = {
8451 .destroy = intel_user_framebuffer_destroy,
8452 .create_handle = intel_user_framebuffer_create_handle,
8453};
8454
38651674
DA		 8455int intel_framebuffer_init(struct drm_device *dev,
8456 struct intel_framebuffer *intel_fb,
308e5bcb 8457 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8458 struct drm_i915_gem_object *obj)
79e53945 8459{
79e53945
JB		 8460 int ret;
8461
c16ed4be
CW		 8462 if (obj->tiling_mode == I915_TILING_Y) {
8463 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8464 return -EINVAL;
c16ed4be 8465 }
57cd6508 8466
c16ed4be
CW		 8467 if (mode_cmd->pitches[0] & 63) {
8468 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8469 mode_cmd->pitches[0]);
57cd6508 8470 return -EINVAL;
c16ed4be 8471 }
57cd6508 8472
5d7bd705 8473 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8474 if (mode_cmd->pitches[0] > 32768) {
8475 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8476 mode_cmd->pitches[0]);
5d7bd705 8477 return -EINVAL;
c16ed4be 8478 }
5d7bd705
VS		 8479
8480 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8481 mode_cmd->pitches[0] != obj->stride) {
8482 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8483 mode_cmd->pitches[0], obj->stride);
5d7bd705 8484 return -EINVAL;
c16ed4be 8485 }
5d7bd705 8486
57779d06 8487 /* Reject formats not supported by any plane early. */
308e5bcb 8488 switch (mode_cmd->pixel_format) {
57779d06 8489 case DRM_FORMAT_C8:
04b3924d
VS		 8490 case DRM_FORMAT_RGB565:
8491 case DRM_FORMAT_XRGB8888:
8492 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8493 break;
8494 case DRM_FORMAT_XRGB1555:
8495 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8496 if (INTEL_INFO(dev)->gen > 3) {
8497 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8498 return -EINVAL;
c16ed4be 8499 }
57779d06
VS		 8500 break;
8501 case DRM_FORMAT_XBGR8888:
8502 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8503 case DRM_FORMAT_XRGB2101010:
8504 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8505 case DRM_FORMAT_XBGR2101010:
8506 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8507 if (INTEL_INFO(dev)->gen < 4) {
8508 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8509 return -EINVAL;
c16ed4be 8510 }
b5626747 8511 break;
04b3924d
VS		 8512 case DRM_FORMAT_YUYV:
8513 case DRM_FORMAT_UYVY:
8514 case DRM_FORMAT_YVYU:
8515 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8516 if (INTEL_INFO(dev)->gen < 5) {
8517 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8518 return -EINVAL;
c16ed4be 8519 }
57cd6508
CW		 8520 break;
8521 default:
c16ed4be 8522 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8523 return -EINVAL;
8524 }
8525
90f9a336
VS		 8526 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8527 if (mode_cmd->offsets[0] != 0)
8528 return -EINVAL;
8529
c7d73f6a
DV		 8530 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8531 intel_fb->obj = obj;
8532
79e53945
JB		 8533 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8534 if (ret) {
8535 DRM_ERROR("framebuffer init failed %d\n", ret);
8536 return ret;
8537 }
8538
79e53945
JB		 8539 return 0;
8540}
8541
79e53945
JB		 8542static struct drm_framebuffer *
8543intel_user_framebuffer_create(struct drm_device *dev,
8544 struct drm_file *filp,
308e5bcb 8545 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8546{
05394f39 8547 struct drm_i915_gem_object *obj;
79e53945 8548
308e5bcb
JB		 8549 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8550 mode_cmd->handles[0]));
c8725226 8551 if (&obj->base == NULL)
cce13ff7 8552 return ERR_PTR(-ENOENT);
79e53945 8553
d2dff872 8554 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8555}
8556
79e53945 8557static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8558 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8559 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8560};
8561
e70236a8
JB		 8562/* Set up chip specific display functions */
8563static void intel_init_display(struct drm_device *dev)
8564{
8565 struct drm_i915_private *dev_priv = dev->dev_private;
8566
affa9354 8567 if (HAS_DDI(dev)) {
09b4ddf9 8568 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8569 dev_priv->display.crtc_enable = haswell_crtc_enable;
8570 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8571 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8572 dev_priv->display.update_plane = ironlake_update_plane;
8573 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8574 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8575 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8576 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8577 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8578 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8579 } else {
f564048e 8580 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8581 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8582 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8583 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8584 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8585 }
e70236a8 8586
e70236a8 8587 /* Returns the core display clock speed */
25eb05fc
JB		 8588 if (IS_VALLEYVIEW(dev))
8589 dev_priv->display.get_display_clock_speed =
8590 valleyview_get_display_clock_speed;
8591 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8592 dev_priv->display.get_display_clock_speed =
8593 i945_get_display_clock_speed;
8594 else if (IS_I915G(dev))
8595 dev_priv->display.get_display_clock_speed =
8596 i915_get_display_clock_speed;
f2b115e6 8597 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8598 dev_priv->display.get_display_clock_speed =
8599 i9xx_misc_get_display_clock_speed;
8600 else if (IS_I915GM(dev))
8601 dev_priv->display.get_display_clock_speed =
8602 i915gm_get_display_clock_speed;
8603 else if (IS_I865G(dev))
8604 dev_priv->display.get_display_clock_speed =
8605 i865_get_display_clock_speed;
f0f8a9ce 8606 else if (IS_I85X(dev))
e70236a8
JB		 8607 dev_priv->display.get_display_clock_speed =
8608 i855_get_display_clock_speed;
8609 else /* 852, 830 */
8610 dev_priv->display.get_display_clock_speed =
8611 i830_get_display_clock_speed;
8612
7f8a8569 8613 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8614 if (IS_GEN5(dev)) {
674cf967 8615 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8616 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8617 } else if (IS_GEN6(dev)) {
674cf967 8618 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8619 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8620 } else if (IS_IVYBRIDGE(dev)) {
8621 /* FIXME: detect B0+ stepping and use auto training */
8622 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8623 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8624 dev_priv->display.modeset_global_resources =
8625 ivb_modeset_global_resources;
c82e4d26
ED		 8626 } else if (IS_HASWELL(dev)) {
8627 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8628 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8629 dev_priv->display.modeset_global_resources =
8630 haswell_modeset_global_resources;
a0e63c22 8631 }
6067aaea 8632 } else if (IS_G4X(dev)) {
e0dac65e 8633 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8634 }
8c9f3aaf
JB		 8635
8636 /* Default just returns -ENODEV to indicate unsupported */
8637 dev_priv->display.queue_flip = intel_default_queue_flip;
8638
8639 switch (INTEL_INFO(dev)->gen) {
8640 case 2:
8641 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8642 break;
8643
8644 case 3:
8645 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8646 break;
8647
8648 case 4:
8649 case 5:
8650 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8651 break;
8652
8653 case 6:
8654 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8655 break;
7c9017e5
JB		 8656 case 7:
8657 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8658 break;
8c9f3aaf 8659 }
e70236a8
JB		 8660}
8661
b690e96c
JB		 8662/*
8663 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8664 * resume, or other times. This quirk makes sure that's the case for
8665 * affected systems.
8666 */
0206e353 8667static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8668{
8669 struct drm_i915_private *dev_priv = dev->dev_private;
8670
8671 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8672 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8673}
8674
435793df
KP		 8675/*
8676 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8677 */
8678static void quirk_ssc_force_disable(struct drm_device *dev)
8679{
8680 struct drm_i915_private *dev_priv = dev->dev_private;
8681 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8682 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8683}
8684
4dca20ef 8685/*
5a15ab5b
CE		 8686 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8687 * brightness value
4dca20ef
CE		 8688 */
8689static void quirk_invert_brightness(struct drm_device *dev)
8690{
8691 struct drm_i915_private *dev_priv = dev->dev_private;
8692 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8693 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8694}
8695
b690e96c
JB		 8696struct intel_quirk {
8697 int device;
8698 int subsystem_vendor;
8699 int subsystem_device;
8700 void (*hook)(struct drm_device *dev);
8701};
8702
5f85f176
EE		 8703/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8704struct intel_dmi_quirk {
8705 void (*hook)(struct drm_device *dev);
8706 const struct dmi_system_id (*dmi_id_list)[];
8707};
8708
8709static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8710{
8711 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8712 return 1;
8713}
8714
8715static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8716 {
8717 .dmi_id_list = &(const struct dmi_system_id[]) {
8718 {
8719 .callback = intel_dmi_reverse_brightness,
8720 .ident = "NCR Corporation",
8721 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8722 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8723 },
8724 },
8725 { } /* terminating entry */
8726 },
8727 .hook = quirk_invert_brightness,
8728 },
8729};
8730
c43b5634 8731static struct intel_quirk intel_quirks[] = {
b690e96c 8732 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8733 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8734
b690e96c
JB		 8735 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8736 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8737
b690e96c
JB		 8738 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8739 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8740
ccd0d36e 8741 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8742 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8743 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8744
8745 /* Lenovo U160 cannot use SSC on LVDS */
8746 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8747
8748 /* Sony Vaio Y cannot use SSC on LVDS */
8749 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8750
8751 /* Acer Aspire 5734Z must invert backlight brightness */
8752 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8753
8754 /* Acer/eMachines G725 */
8755 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8756
8757 /* Acer/eMachines e725 */
8758 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8759
8760 /* Acer/Packard Bell NCL20 */
8761 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8762
8763 /* Acer Aspire 4736Z */
8764 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8765};
8766
8767static void intel_init_quirks(struct drm_device *dev)
8768{
8769 struct pci_dev *d = dev->pdev;
8770 int i;
8771
8772 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8773 struct intel_quirk *q = &intel_quirks[i];
8774
8775 if (d->device == q->device &&
8776 (d->subsystem_vendor == q->subsystem_vendor ||
8777 q->subsystem_vendor == PCI_ANY_ID) &&
8778 (d->subsystem_device == q->subsystem_device ||
8779 q->subsystem_device == PCI_ANY_ID))
8780 q->hook(dev);
8781 }
5f85f176
EE		 8782 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8783 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8784 intel_dmi_quirks[i].hook(dev);
8785 }
b690e96c
JB		 8786}
8787
9cce37f4
JB		 8788/* Disable the VGA plane that we never use */
8789static void i915_disable_vga(struct drm_device *dev)
8790{
8791 struct drm_i915_private *dev_priv = dev->dev_private;
8792 u8 sr1;
766aa1c4 8793 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8794
8795 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8796 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8797 sr1 = inb(VGA_SR_DATA);
8798 outb(sr1 | 1<<5, VGA_SR_DATA);
8799 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8800 udelay(300);
8801
8802 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8803 POSTING_READ(vga_reg);
8804}
8805
f817586c
DV		 8806void intel_modeset_init_hw(struct drm_device *dev)
8807{
fa42e23c 8808 intel_init_power_well(dev);
0232e927 8809
a8f78b58
ED		 8810 intel_prepare_ddi(dev);
8811
f817586c
DV		 8812 intel_init_clock_gating(dev);
8813
79f5b2c7 8814 mutex_lock(&dev->struct_mutex);
8090c6b9 8815 intel_enable_gt_powersave(dev);
79f5b2c7 8816 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8817}
8818
79e53945
JB		 8819void intel_modeset_init(struct drm_device *dev)
8820{
652c393a 8821 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8822 int i, ret;
79e53945
JB		 8823
8824 drm_mode_config_init(dev);
8825
8826 dev->mode_config.min_width = 0;
8827 dev->mode_config.min_height = 0;
8828
019d96cb
DA		 8829 dev->mode_config.preferred_depth = 24;
8830 dev->mode_config.prefer_shadow = 1;
8831
e6ecefaa 8832 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8833
b690e96c
JB		 8834 intel_init_quirks(dev);
8835
1fa61106
ED		 8836 intel_init_pm(dev);
8837
e70236a8
JB		 8838 intel_init_display(dev);
8839
a6c45cf0
CW		 8840 if (IS_GEN2(dev)) {
8841 dev->mode_config.max_width = 2048;
8842 dev->mode_config.max_height = 2048;
8843 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8844 dev->mode_config.max_width = 4096;
8845 dev->mode_config.max_height = 4096;
79e53945 8846 } else {
a6c45cf0
CW		 8847 dev->mode_config.max_width = 8192;
8848 dev->mode_config.max_height = 8192;
79e53945 8849 }
5d4545ae 8850 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8851
28c97730 8852 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 8853 INTEL_INFO(dev)->num_pipes,
8854 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 8855
7eb552ae 8856 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 8857 intel_crtc_init(dev, i);
00c2064b
JB		 8858 ret = intel_plane_init(dev, i);
8859 if (ret)
8860 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8861 }
8862
79f689aa 8863 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8864 intel_pch_pll_init(dev);
8865
9cce37f4
JB		 8866 /* Just disable it once at startup */
8867 i915_disable_vga(dev);
79e53945 8868 intel_setup_outputs(dev);
11be49eb
CW		 8869
8870 /* Just in case the BIOS is doing something questionable. */
8871 intel_disable_fbc(dev);
2c7111db
CW		 8872}
8873
24929352
DV		 8874static void
8875intel_connector_break_all_links(struct intel_connector *connector)
8876{
8877 connector->base.dpms = DRM_MODE_DPMS_OFF;
8878 connector->base.encoder = NULL;
8879 connector->encoder->connectors_active = false;
8880 connector->encoder->base.crtc = NULL;
8881}
8882
7fad798e
DV		 8883static void intel_enable_pipe_a(struct drm_device *dev)
8884{
8885 struct intel_connector *connector;
8886 struct drm_connector *crt = NULL;
8887 struct intel_load_detect_pipe load_detect_temp;
8888
8889 /* We can't just switch on the pipe A, we need to set things up with a
8890 * proper mode and output configuration. As a gross hack, enable pipe A
8891 * by enabling the load detect pipe once. */
8892 list_for_each_entry(connector,
8893 &dev->mode_config.connector_list,
8894 base.head) {
8895 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8896 crt = &connector->base;
8897 break;
8898 }
8899 }
8900
8901 if (!crt)
8902 return;
8903
8904 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8905 intel_release_load_detect_pipe(crt, &load_detect_temp);
8906
652c393a 8907
7fad798e
DV		 8908}
8909
fa555837
DV		 8910static bool
8911intel_check_plane_mapping(struct intel_crtc *crtc)
8912{
7eb552ae
BW		 8913 struct drm_device *dev = crtc->base.dev;
8914 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 8915 u32 reg, val;
8916
7eb552ae 8917 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 8918 return true;
8919
8920 reg = DSPCNTR(!crtc->plane);
8921 val = I915_READ(reg);
8922
8923 if ((val & DISPLAY_PLANE_ENABLE) &&
8924 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8925 return false;
8926
8927 return true;
8928}
8929
24929352
DV		 8930static void intel_sanitize_crtc(struct intel_crtc *crtc)
8931{
8932 struct drm_device *dev = crtc->base.dev;
8933 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8934 u32 reg;
24929352 8935
24929352 8936 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8937 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8938 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8939
8940 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8941 * disable the crtc (and hence change the state) if it is wrong. Note
8942 * that gen4+ has a fixed plane -> pipe mapping. */
8943 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8944 struct intel_connector *connector;
8945 bool plane;
8946
24929352
DV		 8947 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8948 crtc->base.base.id);
8949
8950 /* Pipe has the wrong plane attached and the plane is active.
8951 * Temporarily change the plane mapping and disable everything
8952 * ... */
8953 plane = crtc->plane;
8954 crtc->plane = !plane;
8955 dev_priv->display.crtc_disable(&crtc->base);
8956 crtc->plane = plane;
8957
8958 /* ... and break all links. */
8959 list_for_each_entry(connector, &dev->mode_config.connector_list,
8960 base.head) {
8961 if (connector->encoder->base.crtc != &crtc->base)
8962 continue;
8963
8964 intel_connector_break_all_links(connector);
8965 }
8966
8967 WARN_ON(crtc->active);
8968 crtc->base.enabled = false;
8969 }
24929352 8970
7fad798e
DV		 8971 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8972 crtc->pipe == PIPE_A && !crtc->active) {
8973 /* BIOS forgot to enable pipe A, this mostly happens after
8974 * resume. Force-enable the pipe to fix this, the update_dpms
8975 * call below we restore the pipe to the right state, but leave
8976 * the required bits on. */
8977 intel_enable_pipe_a(dev);
8978 }
8979
24929352
DV		 8980 /* Adjust the state of the output pipe according to whether we
8981 * have active connectors/encoders. */
8982 intel_crtc_update_dpms(&crtc->base);
8983
8984 if (crtc->active != crtc->base.enabled) {
8985 struct intel_encoder *encoder;
8986
8987 /* This can happen either due to bugs in the get_hw_state
8988 * functions or because the pipe is force-enabled due to the
8989 * pipe A quirk. */
8990 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8991 crtc->base.base.id,
8992 crtc->base.enabled ? "enabled" : "disabled",
8993 crtc->active ? "enabled" : "disabled");
8994
8995 crtc->base.enabled = crtc->active;
8996
8997 /* Because we only establish the connector -> encoder ->
8998 * crtc links if something is active, this means the
8999 * crtc is now deactivated. Break the links. connector
9000 * -> encoder links are only establish when things are
9001 * actually up, hence no need to break them. */
9002 WARN_ON(crtc->active);
9003
9004 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9005 WARN_ON(encoder->connectors_active);
9006 encoder->base.crtc = NULL;
9007 }
9008 }
9009}
9010
9011static void intel_sanitize_encoder(struct intel_encoder *encoder)
9012{
9013 struct intel_connector *connector;
9014 struct drm_device *dev = encoder->base.dev;
9015
9016 /* We need to check both for a crtc link (meaning that the
9017 * encoder is active and trying to read from a pipe) and the
9018 * pipe itself being active. */
9019 bool has_active_crtc = encoder->base.crtc &&
9020 to_intel_crtc(encoder->base.crtc)->active;
9021
9022 if (encoder->connectors_active && !has_active_crtc) {
9023 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9024 encoder->base.base.id,
9025 drm_get_encoder_name(&encoder->base));
9026
9027 /* Connector is active, but has no active pipe. This is
9028 * fallout from our resume register restoring. Disable
9029 * the encoder manually again. */
9030 if (encoder->base.crtc) {
9031 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9032 encoder->base.base.id,
9033 drm_get_encoder_name(&encoder->base));
9034 encoder->disable(encoder);
9035 }
9036
9037 /* Inconsistent output/port/pipe state happens presumably due to
9038 * a bug in one of the get_hw_state functions. Or someplace else
9039 * in our code, like the register restore mess on resume. Clamp
9040 * things to off as a safer default. */
9041 list_for_each_entry(connector,
9042 &dev->mode_config.connector_list,
9043 base.head) {
9044 if (connector->encoder != encoder)
9045 continue;
9046
9047 intel_connector_break_all_links(connector);
9048 }
9049 }
9050 /* Enabled encoders without active connectors will be fixed in
9051 * the crtc fixup. */
9052}
9053
44cec740 9054void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9055{
9056 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9057 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9058
9059 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9060 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9061 i915_disable_vga(dev);
0fde901f
KM		 9062 }
9063}
9064
24929352
DV		 9065/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9066 * and i915 state tracking structures. */
45e2b5f6
DV		 9067void intel_modeset_setup_hw_state(struct drm_device *dev,
9068 bool force_restore)
24929352
DV		 9069{
9070 struct drm_i915_private *dev_priv = dev->dev_private;
9071 enum pipe pipe;
9072 u32 tmp;
b5644d05 9073 struct drm_plane *plane;
24929352
DV		 9074 struct intel_crtc *crtc;
9075 struct intel_encoder *encoder;
9076 struct intel_connector *connector;
9077
affa9354 9078 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9079 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9080
9081 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9082 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9083 case TRANS_DDI_EDP_INPUT_A_ON:
9084 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9085 pipe = PIPE_A;
9086 break;
9087 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9088 pipe = PIPE_B;
9089 break;
9090 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9091 pipe = PIPE_C;
9092 break;
aaa148ec
DL		 9093 default:
9094 /* A bogus value has been programmed, disable
9095 * the transcoder */
9096 WARN(1, "Bogus eDP source %08x\n", tmp);
9097 intel_ddi_disable_transcoder_func(dev_priv,
9098 TRANSCODER_EDP);
9099 goto setup_pipes;
e28d54cb
PZ		 9100 }
9101
9102 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9103 crtc->cpu_transcoder = TRANSCODER_EDP;
9104
9105 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9106 pipe_name(pipe));
9107 }
9108 }
9109
aaa148ec 9110setup_pipes:
24929352
DV		 9111 for_each_pipe(pipe) {
9112 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9113
702e7a56 9114 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9115 if (tmp & PIPECONF_ENABLE)
9116 crtc->active = true;
9117 else
9118 crtc->active = false;
9119
9120 crtc->base.enabled = crtc->active;
9121
9122 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9123 crtc->base.base.id,
9124 crtc->active ? "enabled" : "disabled");
9125 }
9126
affa9354 9127 if (HAS_DDI(dev))
6441ab5f
PZ		 9128 intel_ddi_setup_hw_pll_state(dev);
9129
24929352
DV		 9130 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9131 base.head) {
9132 pipe = 0;
9133
9134 if (encoder->get_hw_state(encoder, &pipe)) {
9135 encoder->base.crtc =
9136 dev_priv->pipe_to_crtc_mapping[pipe];
9137 } else {
9138 encoder->base.crtc = NULL;
9139 }
9140
9141 encoder->connectors_active = false;
9142 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9143 encoder->base.base.id,
9144 drm_get_encoder_name(&encoder->base),
9145 encoder->base.crtc ? "enabled" : "disabled",
9146 pipe);
9147 }
9148
9149 list_for_each_entry(connector, &dev->mode_config.connector_list,
9150 base.head) {
9151 if (connector->get_hw_state(connector)) {
9152 connector->base.dpms = DRM_MODE_DPMS_ON;
9153 connector->encoder->connectors_active = true;
9154 connector->base.encoder = &connector->encoder->base;
9155 } else {
9156 connector->base.dpms = DRM_MODE_DPMS_OFF;
9157 connector->base.encoder = NULL;
9158 }
9159 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9160 connector->base.base.id,
9161 drm_get_connector_name(&connector->base),
9162 connector->base.encoder ? "enabled" : "disabled");
9163 }
9164
9165 /* HW state is read out, now we need to sanitize this mess. */
9166 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9167 base.head) {
9168 intel_sanitize_encoder(encoder);
9169 }
9170
9171 for_each_pipe(pipe) {
9172 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9173 intel_sanitize_crtc(crtc);
9174 }
9a935856 9175
45e2b5f6
DV		 9176 if (force_restore) {
9177 for_each_pipe(pipe) {
b5644d05
JB		 9178 struct drm_crtc *crtc =
9179 dev_priv->pipe_to_crtc_mapping[pipe];
9180 intel_crtc_restore_mode(crtc);
45e2b5f6 9181 }
b5644d05
JB		 9182 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9183 intel_plane_restore(plane);
0fde901f
KM		 9184
9185 i915_redisable_vga(dev);
45e2b5f6
DV		 9186 } else {
9187 intel_modeset_update_staged_output_state(dev);
9188 }
8af6cf88
DV		 9189
9190 intel_modeset_check_state(dev);
2e938892
DV		 9191
9192 drm_mode_config_reset(dev);
2c7111db
CW		 9193}
9194
9195void intel_modeset_gem_init(struct drm_device *dev)
9196{
1833b134 9197 intel_modeset_init_hw(dev);
02e792fb
DV		 9198
9199 intel_setup_overlay(dev);
24929352 9200
45e2b5f6 9201 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9202}
9203
9204void intel_modeset_cleanup(struct drm_device *dev)
9205{
652c393a
JB		 9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 struct drm_crtc *crtc;
9208 struct intel_crtc *intel_crtc;
9209
f87ea761 9210 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9211 mutex_lock(&dev->struct_mutex);
9212
723bfd70
JB		 9213 intel_unregister_dsm_handler();
9214
9215
652c393a
JB		 9216 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9217 /* Skip inactive CRTCs */
9218 if (!crtc->fb)
9219 continue;
9220
9221 intel_crtc = to_intel_crtc(crtc);
3dec0095 9222 intel_increase_pllclock(crtc);
652c393a
JB		 9223 }
9224
973d04f9 9225 intel_disable_fbc(dev);
e70236a8 9226
8090c6b9 9227 intel_disable_gt_powersave(dev);
0cdab21f 9228
930ebb46
DV		 9229 ironlake_teardown_rc6(dev);
9230
57f350b6
JB		 9231 if (IS_VALLEYVIEW(dev))
9232 vlv_init_dpio(dev);
9233
69341a5e
KH		 9234 mutex_unlock(&dev->struct_mutex);
9235
6c0d9350
DV		 9236 /* Disable the irq before mode object teardown, for the irq might
9237 * enqueue unpin/hotplug work. */
9238 drm_irq_uninstall(dev);
9239 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9240 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9241
1630fe75
CW		 9242 /* flush any delayed tasks or pending work */
9243 flush_scheduled_work();
9244
79e53945 9245 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9246
9247 intel_cleanup_overlay(dev);
79e53945
JB		 9248}
9249
f1c79df3
ZW		 9250/*
9251 * Return which encoder is currently attached for connector.
9252 */
df0e9248 9253struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9254{
df0e9248
CW		 9255 return &intel_attached_encoder(connector)->base;
9256}
f1c79df3 9257
df0e9248
CW		 9258void intel_connector_attach_encoder(struct intel_connector *connector,
9259 struct intel_encoder *encoder)
9260{
9261 connector->encoder = encoder;
9262 drm_mode_connector_attach_encoder(&connector->base,
9263 &encoder->base);
79e53945 9264}
28d52043
DA		 9265
9266/*
9267 * set vga decode state - true == enable VGA decode
9268 */
9269int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9270{
9271 struct drm_i915_private *dev_priv = dev->dev_private;
9272 u16 gmch_ctrl;
9273
9274 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9275 if (state)
9276 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9277 else
9278 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9279 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9280 return 0;
9281}
c4a1d9e4
CW		 9282
9283#ifdef CONFIG_DEBUG_FS
9284#include <linux/seq_file.h>
9285
9286struct intel_display_error_state {
9287 struct intel_cursor_error_state {
9288 u32 control;
9289 u32 position;
9290 u32 base;
9291 u32 size;
52331309 9292 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9293
9294 struct intel_pipe_error_state {
9295 u32 conf;
9296 u32 source;
9297
9298 u32 htotal;
9299 u32 hblank;
9300 u32 hsync;
9301 u32 vtotal;
9302 u32 vblank;
9303 u32 vsync;
52331309 9304 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9305
9306 struct intel_plane_error_state {
9307 u32 control;
9308 u32 stride;
9309 u32 size;
9310 u32 pos;
9311 u32 addr;
9312 u32 surface;
9313 u32 tile_offset;
52331309 9314 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9315};
9316
9317struct intel_display_error_state *
9318intel_display_capture_error_state(struct drm_device *dev)
9319{
0206e353 9320 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9321 struct intel_display_error_state *error;
702e7a56 9322 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9323 int i;
9324
9325 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9326 if (error == NULL)
9327 return NULL;
9328
52331309 9329 for_each_pipe(i) {
702e7a56
PZ		 9330 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9331
a18c4c3d
PZ		 9332 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9333 error->cursor[i].control = I915_READ(CURCNTR(i));
9334 error->cursor[i].position = I915_READ(CURPOS(i));
9335 error->cursor[i].base = I915_READ(CURBASE(i));
9336 } else {
9337 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9338 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9339 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9340 }
c4a1d9e4
CW		 9341
9342 error->plane[i].control = I915_READ(DSPCNTR(i));
9343 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9344 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9345 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9346 error->plane[i].pos = I915_READ(DSPPOS(i));
9347 }
ca291363
PZ		 9348 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9349 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9350 if (INTEL_INFO(dev)->gen >= 4) {
9351 error->plane[i].surface = I915_READ(DSPSURF(i));
9352 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9353 }
9354
702e7a56 9355 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9356 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9357 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9358 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9359 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9360 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9361 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9362 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9363 }
9364
9365 return error;
9366}
9367
9368void
9369intel_display_print_error_state(struct seq_file *m,
9370 struct drm_device *dev,
9371 struct intel_display_error_state *error)
9372{
9373 int i;
9374
7eb552ae 9375 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9376 for_each_pipe(i) {
c4a1d9e4
CW		 9377 seq_printf(m, "Pipe [%d]:\n", i);
9378 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9379 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9380 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9381 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9382 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9383 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9384 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9385 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9386
9387 seq_printf(m, "Plane [%d]:\n", i);
9388 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9389 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9390 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9391 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9392 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9393 }
4b71a570 9394 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9395 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9396 if (INTEL_INFO(dev)->gen >= 4) {
9397 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9398 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9399 }
9400
9401 seq_printf(m, "Cursor [%d]:\n", i);
9402 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9403 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9404 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9405 }
9406}
9407#endif
Linux kernel - Deliverables
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