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drm/i915: mask the video DIP frequency when changing it
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
9d0498a2
JB		 787/**
788 * intel_wait_for_vblank - wait for vblank on a given pipe
789 * @dev: drm device
790 * @pipe: pipe to wait for
791 *
792 * Wait for vblank to occur on a given pipe. Needed for various bits of
793 * mode setting code.
794 */
795void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 796{
9d0498a2 797 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 798 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 799
300387c0
CW		 800 /* Clear existing vblank status. Note this will clear any other
801 * sticky status fields as well.
802 *
803 * This races with i915_driver_irq_handler() with the result
804 * that either function could miss a vblank event. Here it is not
805 * fatal, as we will either wait upon the next vblank interrupt or
806 * timeout. Generally speaking intel_wait_for_vblank() is only
807 * called during modeset at which time the GPU should be idle and
808 * should *not* be performing page flips and thus not waiting on
809 * vblanks...
810 * Currently, the result of us stealing a vblank from the irq
811 * handler is that a single frame will be skipped during swapbuffers.
812 */
813 I915_WRITE(pipestat_reg,
814 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
815
9d0498a2 816 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 817 if (wait_for(I915_READ(pipestat_reg) &
818 PIPE_VBLANK_INTERRUPT_STATUS,
819 50))
9d0498a2
JB		 820 DRM_DEBUG_KMS("vblank wait timed out\n");
821}
822
ab7ad7f6
KP		 823/*
824 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 825 * @dev: drm device
826 * @pipe: pipe to wait for
827 *
828 * After disabling a pipe, we can't wait for vblank in the usual way,
829 * spinning on the vblank interrupt status bit, since we won't actually
830 * see an interrupt when the pipe is disabled.
831 *
ab7ad7f6
KP		 832 * On Gen4 and above:
833 * wait for the pipe register state bit to turn off
834 *
835 * Otherwise:
836 * wait for the display line value to settle (it usually
837 * ends up stopping at the start of the next frame).
58e10eb9 838 *
9d0498a2 839 */
58e10eb9 840void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 841{
842 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 843
844 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 845 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 846
847 /* Wait for the Pipe State to go off */
58e10eb9
CW		 848 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
849 100))
ab7ad7f6
KP		 850 DRM_DEBUG_KMS("pipe_off wait timed out\n");
851 } else {
837ba00f 852 u32 last_line, line_mask;
58e10eb9 853 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 854 unsigned long timeout = jiffies + msecs_to_jiffies(100);
855
837ba00f
PZ		 856 if (IS_GEN2(dev))
857 line_mask = DSL_LINEMASK_GEN2;
858 else
859 line_mask = DSL_LINEMASK_GEN3;
860
ab7ad7f6
KP		 861 /* Wait for the display line to settle */
862 do {
837ba00f 863 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 864 mdelay(5);
837ba00f 865 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 866 time_after(timeout, jiffies));
867 if (time_after(jiffies, timeout))
868 DRM_DEBUG_KMS("pipe_off wait timed out\n");
869 }
79e53945
JB		 870}
871
b24e7179
JB		 872static const char *state_string(bool enabled)
873{
874 return enabled ? "on" : "off";
875}
876
877/* Only for pre-ILK configs */
878static void assert_pll(struct drm_i915_private *dev_priv,
879 enum pipe pipe, bool state)
880{
881 int reg;
882 u32 val;
883 bool cur_state;
884
885 reg = DPLL(pipe);
886 val = I915_READ(reg);
887 cur_state = !!(val & DPLL_VCO_ENABLE);
888 WARN(cur_state != state,
889 "PLL state assertion failure (expected %s, current %s)\n",
890 state_string(state), state_string(cur_state));
891}
892#define assert_pll_enabled(d, p) assert_pll(d, p, true)
893#define assert_pll_disabled(d, p) assert_pll(d, p, false)
894
040484af
JB		 895/* For ILK+ */
896static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 897 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 898{
899 int reg;
900 u32 val;
901 bool cur_state;
902
ee7b9f93
JB		 903 if (!intel_crtc->pch_pll) {
904 WARN(1, "asserting PCH PLL enabled with no PLL\n");
905 return;
906 }
907
d3ccbe86
JB		 908 if (HAS_PCH_CPT(dev_priv->dev)) {
909 u32 pch_dpll;
910
911 pch_dpll = I915_READ(PCH_DPLL_SEL);
912
913 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 914 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
915 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 916 }
917
ee7b9f93 918 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 919 val = I915_READ(reg);
920 cur_state = !!(val & DPLL_VCO_ENABLE);
921 WARN(cur_state != state,
922 "PCH PLL state assertion failure (expected %s, current %s)\n",
923 state_string(state), state_string(cur_state));
924}
925#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
926#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
927
928static void assert_fdi_tx(struct drm_i915_private *dev_priv,
929 enum pipe pipe, bool state)
930{
931 int reg;
932 u32 val;
933 bool cur_state;
934
935 reg = FDI_TX_CTL(pipe);
936 val = I915_READ(reg);
937 cur_state = !!(val & FDI_TX_ENABLE);
938 WARN(cur_state != state,
939 "FDI TX state assertion failure (expected %s, current %s)\n",
940 state_string(state), state_string(cur_state));
941}
942#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
943#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
944
945static void assert_fdi_rx(struct drm_i915_private *dev_priv,
946 enum pipe pipe, bool state)
947{
948 int reg;
949 u32 val;
950 bool cur_state;
951
952 reg = FDI_RX_CTL(pipe);
953 val = I915_READ(reg);
954 cur_state = !!(val & FDI_RX_ENABLE);
955 WARN(cur_state != state,
956 "FDI RX state assertion failure (expected %s, current %s)\n",
957 state_string(state), state_string(cur_state));
958}
959#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
960#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
961
962static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
963 enum pipe pipe)
964{
965 int reg;
966 u32 val;
967
968 /* ILK FDI PLL is always enabled */
969 if (dev_priv->info->gen == 5)
970 return;
971
972 reg = FDI_TX_CTL(pipe);
973 val = I915_READ(reg);
974 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
975}
976
977static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979{
980 int reg;
981 u32 val;
982
983 reg = FDI_RX_CTL(pipe);
984 val = I915_READ(reg);
985 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
986}
987
ea0760cf
JB		 988static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
989 enum pipe pipe)
990{
991 int pp_reg, lvds_reg;
992 u32 val;
993 enum pipe panel_pipe = PIPE_A;
0de3b485 994 bool locked = true;
ea0760cf
JB		 995
996 if (HAS_PCH_SPLIT(dev_priv->dev)) {
997 pp_reg = PCH_PP_CONTROL;
998 lvds_reg = PCH_LVDS;
999 } else {
1000 pp_reg = PP_CONTROL;
1001 lvds_reg = LVDS;
1002 }
1003
1004 val = I915_READ(pp_reg);
1005 if (!(val & PANEL_POWER_ON) ||
1006 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1007 locked = false;
1008
1009 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1010 panel_pipe = PIPE_B;
1011
1012 WARN(panel_pipe == pipe && locked,
1013 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1014 pipe_name(pipe));
ea0760cf
JB		 1015}
1016
b840d907
JB		 1017void assert_pipe(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
b24e7179
JB		 1019{
1020 int reg;
1021 u32 val;
63d7bbe9 1022 bool cur_state;
b24e7179 1023
8e636784
DV		 1024 /* if we need the pipe A quirk it must be always on */
1025 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1026 state = true;
1027
b24e7179
JB		 1028 reg = PIPECONF(pipe);
1029 val = I915_READ(reg);
63d7bbe9
JB		 1030 cur_state = !!(val & PIPECONF_ENABLE);
1031 WARN(cur_state != state,
1032 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1033 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1034}
1035
931872fc
CW		 1036static void assert_plane(struct drm_i915_private *dev_priv,
1037 enum plane plane, bool state)
b24e7179
JB		 1038{
1039 int reg;
1040 u32 val;
931872fc 1041 bool cur_state;
b24e7179
JB		 1042
1043 reg = DSPCNTR(plane);
1044 val = I915_READ(reg);
931872fc
CW		 1045 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1046 WARN(cur_state != state,
1047 "plane %c assertion failure (expected %s, current %s)\n",
1048 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1049}
1050
931872fc
CW		 1051#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1052#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1053
b24e7179
JB		 1054static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int reg, i;
1058 u32 val;
1059 int cur_pipe;
1060
19ec1358 1061 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 reg = DSPCNTR(pipe);
1064 val = I915_READ(reg);
1065 WARN((val & DISPLAY_PLANE_ENABLE),
1066 "plane %c assertion failure, should be disabled but not\n",
1067 plane_name(pipe));
19ec1358 1068 return;
28c05794 1069 }
19ec1358 1070
b24e7179
JB		 1071 /* Need to check both planes against the pipe */
1072 for (i = 0; i < 2; i++) {
1073 reg = DSPCNTR(i);
1074 val = I915_READ(reg);
1075 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1076 DISPPLANE_SEL_PIPE_SHIFT;
1077 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1078 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1079 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1080 }
1081}
1082
92f2584a
JB		 1083static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1084{
1085 u32 val;
1086 bool enabled;
1087
1088 val = I915_READ(PCH_DREF_CONTROL);
1089 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1090 DREF_SUPERSPREAD_SOURCE_MASK));
1091 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1092}
1093
1094static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1095 enum pipe pipe)
1096{
1097 int reg;
1098 u32 val;
1099 bool enabled;
1100
1101 reg = TRANSCONF(pipe);
1102 val = I915_READ(reg);
1103 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1104 WARN(enabled,
1105 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1106 pipe_name(pipe));
92f2584a
JB		 1107}
1108
4e634389
KP		 1109static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1111{
1112 if ((val & DP_PORT_EN) == 0)
1113 return false;
1114
1115 if (HAS_PCH_CPT(dev_priv->dev)) {
1116 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1117 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1118 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1119 return false;
1120 } else {
1121 if ((val & DP_PIPE_MASK) != (pipe << 30))
1122 return false;
1123 }
1124 return true;
1125}
1126
1519b995
KP		 1127static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, u32 val)
1129{
1130 if ((val & PORT_ENABLE) == 0)
1131 return false;
1132
1133 if (HAS_PCH_CPT(dev_priv->dev)) {
1134 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1135 return false;
1136 } else {
1137 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1138 return false;
1139 }
1140 return true;
1141}
1142
1143static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, u32 val)
1145{
1146 if ((val & LVDS_PORT_EN) == 0)
1147 return false;
1148
1149 if (HAS_PCH_CPT(dev_priv->dev)) {
1150 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1151 return false;
1152 } else {
1153 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1154 return false;
1155 }
1156 return true;
1157}
1158
1159static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, u32 val)
1161{
1162 if ((val & ADPA_DAC_ENABLE) == 0)
1163 return false;
1164 if (HAS_PCH_CPT(dev_priv->dev)) {
1165 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1166 return false;
1167 } else {
1168 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1169 return false;
1170 }
1171 return true;
1172}
1173
291906f1 1174static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1175 enum pipe pipe, int reg, u32 port_sel)
291906f1 1176{
47a05eca 1177 u32 val = I915_READ(reg);
4e634389 1178 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1179 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1180 reg, pipe_name(pipe));
291906f1
JB		 1181}
1182
1183static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, int reg)
1185{
47a05eca 1186 u32 val = I915_READ(reg);
1519b995 1187 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1188 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1189 reg, pipe_name(pipe));
291906f1
JB		 1190}
1191
1192static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194{
1195 int reg;
1196 u32 val;
291906f1 1197
f0575e92
KP		 1198 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1199 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1200 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1201
1202 reg = PCH_ADPA;
1203 val = I915_READ(reg);
1519b995 1204 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1205 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1206 pipe_name(pipe));
291906f1
JB		 1207
1208 reg = PCH_LVDS;
1209 val = I915_READ(reg);
1519b995 1210 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1211 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1212 pipe_name(pipe));
291906f1
JB		 1213
1214 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1215 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1216 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1217}
1218
63d7bbe9
JB		 1219/**
1220 * intel_enable_pll - enable a PLL
1221 * @dev_priv: i915 private structure
1222 * @pipe: pipe PLL to enable
1223 *
1224 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1225 * make sure the PLL reg is writable first though, since the panel write
1226 * protect mechanism may be enabled.
1227 *
1228 * Note! This is for pre-ILK only.
1229 */
1230static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1231{
1232 int reg;
1233 u32 val;
1234
1235 /* No really, not for ILK+ */
1236 BUG_ON(dev_priv->info->gen >= 5);
1237
1238 /* PLL is protected by panel, make sure we can write it */
1239 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1240 assert_panel_unlocked(dev_priv, pipe);
1241
1242 reg = DPLL(pipe);
1243 val = I915_READ(reg);
1244 val |= DPLL_VCO_ENABLE;
1245
1246 /* We do this three times for luck */
1247 I915_WRITE(reg, val);
1248 POSTING_READ(reg);
1249 udelay(150); /* wait for warmup */
1250 I915_WRITE(reg, val);
1251 POSTING_READ(reg);
1252 udelay(150); /* wait for warmup */
1253 I915_WRITE(reg, val);
1254 POSTING_READ(reg);
1255 udelay(150); /* wait for warmup */
1256}
1257
1258/**
1259 * intel_disable_pll - disable a PLL
1260 * @dev_priv: i915 private structure
1261 * @pipe: pipe PLL to disable
1262 *
1263 * Disable the PLL for @pipe, making sure the pipe is off first.
1264 *
1265 * Note! This is for pre-ILK only.
1266 */
1267static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1268{
1269 int reg;
1270 u32 val;
1271
1272 /* Don't disable pipe A or pipe A PLLs if needed */
1273 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1274 return;
1275
1276 /* Make sure the pipe isn't still relying on us */
1277 assert_pipe_disabled(dev_priv, pipe);
1278
1279 reg = DPLL(pipe);
1280 val = I915_READ(reg);
1281 val &= ~DPLL_VCO_ENABLE;
1282 I915_WRITE(reg, val);
1283 POSTING_READ(reg);
1284}
1285
92f2584a
JB		 1286/**
1287 * intel_enable_pch_pll - enable PCH PLL
1288 * @dev_priv: i915 private structure
1289 * @pipe: pipe PLL to enable
1290 *
1291 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1292 * drives the transcoder clock.
1293 */
ee7b9f93 1294static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1295{
ee7b9f93
JB		 1296 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1297 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a
JB		 1298 int reg;
1299 u32 val;
1300
1301 /* PCH only available on ILK+ */
1302 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1303 BUG_ON(pll == NULL);
1304 BUG_ON(pll->refcount == 0);
1305
1306 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1307 pll->pll_reg, pll->active, pll->on,
1308 intel_crtc->base.base.id);
92f2584a
JB		 1309
1310 /* PCH refclock must be enabled first */
1311 assert_pch_refclk_enabled(dev_priv);
1312
ee7b9f93
JB		 1313 if (pll->active++ && pll->on) {
1314 assert_pch_pll_enabled(dev_priv, intel_crtc);
1315 return;
1316 }
1317
1318 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1319
1320 reg = pll->pll_reg;
92f2584a
JB		 1321 val = I915_READ(reg);
1322 val |= DPLL_VCO_ENABLE;
1323 I915_WRITE(reg, val);
1324 POSTING_READ(reg);
1325 udelay(200);
ee7b9f93
JB		 1326
1327 pll->on = true;
92f2584a
JB		 1328}
1329
ee7b9f93 1330static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1331{
ee7b9f93
JB		 1332 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1333 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1334 int reg;
ee7b9f93 1335 u32 val;
4c609cb8 1336
92f2584a
JB		 1337 /* PCH only available on ILK+ */
1338 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1339 if (pll == NULL)
1340 return;
92f2584a 1341
ee7b9f93 1342 BUG_ON(pll->refcount == 0);
7a419866 1343
ee7b9f93
JB		 1344 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1345 pll->pll_reg, pll->active, pll->on,
1346 intel_crtc->base.base.id);
7a419866 1347
ee7b9f93
JB		 1348 BUG_ON(pll->active == 0);
1349 if (--pll->active) {
1350 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1351 return;
ee7b9f93
JB		 1352 }
1353
1354 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1355
1356 /* Make sure transcoder isn't still depending on us */
1357 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1358
ee7b9f93 1359 reg = pll->pll_reg;
92f2584a
JB		 1360 val = I915_READ(reg);
1361 val &= ~DPLL_VCO_ENABLE;
1362 I915_WRITE(reg, val);
1363 POSTING_READ(reg);
1364 udelay(200);
ee7b9f93
JB		 1365
1366 pll->on = false;
92f2584a
JB		 1367}
1368
040484af
JB		 1369static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1370 enum pipe pipe)
1371{
1372 int reg;
5f7f726d 1373 u32 val, pipeconf_val;
7c26e5c6 1374 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1375
1376 /* PCH only available on ILK+ */
1377 BUG_ON(dev_priv->info->gen < 5);
1378
1379 /* Make sure PCH DPLL is enabled */
ee7b9f93 1380 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1381
1382 /* FDI must be feeding us bits for PCH ports */
1383 assert_fdi_tx_enabled(dev_priv, pipe);
1384 assert_fdi_rx_enabled(dev_priv, pipe);
1385
1386 reg = TRANSCONF(pipe);
1387 val = I915_READ(reg);
5f7f726d 1388 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1389
1390 if (HAS_PCH_IBX(dev_priv->dev)) {
1391 /*
1392 * make the BPC in transcoder be consistent with
1393 * that in pipeconf reg.
1394 */
1395 val &= ~PIPE_BPC_MASK;
5f7f726d 1396 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1397 }
5f7f726d
PZ		 1398
1399 val &= ~TRANS_INTERLACE_MASK;
1400 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1401 if (HAS_PCH_IBX(dev_priv->dev) &&
1402 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1403 val |= TRANS_LEGACY_INTERLACED_ILK;
1404 else
1405 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1406 else
1407 val |= TRANS_PROGRESSIVE;
1408
040484af
JB		 1409 I915_WRITE(reg, val | TRANS_ENABLE);
1410 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1411 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1412}
1413
1414static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1415 enum pipe pipe)
1416{
1417 int reg;
1418 u32 val;
1419
1420 /* FDI relies on the transcoder */
1421 assert_fdi_tx_disabled(dev_priv, pipe);
1422 assert_fdi_rx_disabled(dev_priv, pipe);
1423
291906f1
JB		 1424 /* Ports must be off as well */
1425 assert_pch_ports_disabled(dev_priv, pipe);
1426
040484af
JB		 1427 reg = TRANSCONF(pipe);
1428 val = I915_READ(reg);
1429 val &= ~TRANS_ENABLE;
1430 I915_WRITE(reg, val);
1431 /* wait for PCH transcoder off, transcoder state */
1432 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1433 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1434}
1435
b24e7179 1436/**
309cfea8 1437 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1438 * @dev_priv: i915 private structure
1439 * @pipe: pipe to enable
040484af 1440 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1441 *
1442 * Enable @pipe, making sure that various hardware specific requirements
1443 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1444 *
1445 * @pipe should be %PIPE_A or %PIPE_B.
1446 *
1447 * Will wait until the pipe is actually running (i.e. first vblank) before
1448 * returning.
1449 */
040484af
JB		 1450static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1451 bool pch_port)
b24e7179
JB		 1452{
1453 int reg;
1454 u32 val;
1455
1456 /*
1457 * A pipe without a PLL won't actually be able to drive bits from
1458 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1459 * need the check.
1460 */
1461 if (!HAS_PCH_SPLIT(dev_priv->dev))
1462 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1463 else {
1464 if (pch_port) {
1465 /* if driving the PCH, we need FDI enabled */
1466 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1467 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1468 }
1469 /* FIXME: assert CPU port conditions for SNB+ */
1470 }
b24e7179
JB		 1471
1472 reg = PIPECONF(pipe);
1473 val = I915_READ(reg);
00d70b15
CW		 1474 if (val & PIPECONF_ENABLE)
1475 return;
1476
1477 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1478 intel_wait_for_vblank(dev_priv->dev, pipe);
1479}
1480
1481/**
309cfea8 1482 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to disable
1485 *
1486 * Disable @pipe, making sure that various hardware specific requirements
1487 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1488 *
1489 * @pipe should be %PIPE_A or %PIPE_B.
1490 *
1491 * Will wait until the pipe has shut down before returning.
1492 */
1493static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495{
1496 int reg;
1497 u32 val;
1498
1499 /*
1500 * Make sure planes won't keep trying to pump pixels to us,
1501 * or we might hang the display.
1502 */
1503 assert_planes_disabled(dev_priv, pipe);
1504
1505 /* Don't disable pipe A or pipe A PLLs if needed */
1506 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1507 return;
1508
1509 reg = PIPECONF(pipe);
1510 val = I915_READ(reg);
00d70b15
CW		 1511 if ((val & PIPECONF_ENABLE) == 0)
1512 return;
1513
1514 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1515 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1516}
1517
d74362c9
KP		 1518/*
1519 * Plane regs are double buffered, going from enabled->disabled needs a
1520 * trigger in order to latch. The display address reg provides this.
1521 */
6f1d69b0 1522void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1523 enum plane plane)
1524{
1525 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1526 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1527}
1528
b24e7179
JB		 1529/**
1530 * intel_enable_plane - enable a display plane on a given pipe
1531 * @dev_priv: i915 private structure
1532 * @plane: plane to enable
1533 * @pipe: pipe being fed
1534 *
1535 * Enable @plane on @pipe, making sure that @pipe is running first.
1536 */
1537static void intel_enable_plane(struct drm_i915_private *dev_priv,
1538 enum plane plane, enum pipe pipe)
1539{
1540 int reg;
1541 u32 val;
1542
1543 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1544 assert_pipe_enabled(dev_priv, pipe);
1545
1546 reg = DSPCNTR(plane);
1547 val = I915_READ(reg);
00d70b15
CW		 1548 if (val & DISPLAY_PLANE_ENABLE)
1549 return;
1550
1551 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1552 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1553 intel_wait_for_vblank(dev_priv->dev, pipe);
1554}
1555
b24e7179
JB		 1556/**
1557 * intel_disable_plane - disable a display plane
1558 * @dev_priv: i915 private structure
1559 * @plane: plane to disable
1560 * @pipe: pipe consuming the data
1561 *
1562 * Disable @plane; should be an independent operation.
1563 */
1564static void intel_disable_plane(struct drm_i915_private *dev_priv,
1565 enum plane plane, enum pipe pipe)
1566{
1567 int reg;
1568 u32 val;
1569
1570 reg = DSPCNTR(plane);
1571 val = I915_READ(reg);
00d70b15
CW		 1572 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1573 return;
1574
1575 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1576 intel_flush_display_plane(dev_priv, plane);
1577 intel_wait_for_vblank(dev_priv->dev, pipe);
1578}
1579
47a05eca 1580static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1581 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1582{
1583 u32 val = I915_READ(reg);
4e634389 1584 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1585 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1586 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1587 }
47a05eca
JB		 1588}
1589
1590static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1591 enum pipe pipe, int reg)
1592{
1593 u32 val = I915_READ(reg);
1519b995 1594 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1595 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1596 reg, pipe);
47a05eca 1597 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1598 }
47a05eca
JB		 1599}
1600
1601/* Disable any ports connected to this transcoder */
1602static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1603 enum pipe pipe)
1604{
1605 u32 reg, val;
1606
1607 val = I915_READ(PCH_PP_CONTROL);
1608 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1609
f0575e92
KP		 1610 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1611 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1612 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1613
1614 reg = PCH_ADPA;
1615 val = I915_READ(reg);
1519b995 1616 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1617 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1618
1619 reg = PCH_LVDS;
1620 val = I915_READ(reg);
1519b995
KP		 1621 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1622 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1623 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1624 POSTING_READ(reg);
1625 udelay(100);
1626 }
1627
1628 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1629 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1630 disable_pch_hdmi(dev_priv, pipe, HDMID);
1631}
1632
127bd2ac 1633int
48b956c5 1634intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1635 struct drm_i915_gem_object *obj,
919926ae 1636 struct intel_ring_buffer *pipelined)
6b95a207 1637{
ce453d81 1638 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1639 u32 alignment;
1640 int ret;
1641
05394f39 1642 switch (obj->tiling_mode) {
6b95a207 1643 case I915_TILING_NONE:
534843da
CW		 1644 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1645 alignment = 128 * 1024;
a6c45cf0 1646 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1647 alignment = 4 * 1024;
1648 else
1649 alignment = 64 * 1024;
6b95a207
KH		 1650 break;
1651 case I915_TILING_X:
1652 /* pin() will align the object as required by fence */
1653 alignment = 0;
1654 break;
1655 case I915_TILING_Y:
1656 /* FIXME: Is this true? */
1657 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1658 return -EINVAL;
1659 default:
1660 BUG();
1661 }
1662
ce453d81 1663 dev_priv->mm.interruptible = false;
2da3b9b9 1664 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1665 if (ret)
ce453d81 1666 goto err_interruptible;
6b95a207
KH		 1667
1668 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1669 * fence, whereas 965+ only requires a fence if using
1670 * framebuffer compression. For simplicity, we always install
1671 * a fence as the cost is not that onerous.
1672 */
06d98131 1673 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1674 if (ret)
1675 goto err_unpin;
1690e1eb 1676
9a5a53b3 1677 i915_gem_object_pin_fence(obj);
6b95a207 1678
ce453d81 1679 dev_priv->mm.interruptible = true;
6b95a207 1680 return 0;
48b956c5
CW		 1681
1682err_unpin:
1683 i915_gem_object_unpin(obj);
ce453d81
CW		 1684err_interruptible:
1685 dev_priv->mm.interruptible = true;
48b956c5 1686 return ret;
6b95a207
KH		 1687}
1688
1690e1eb
CW		 1689void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1690{
1691 i915_gem_object_unpin_fence(obj);
1692 i915_gem_object_unpin(obj);
1693}
1694
17638cd6
JB		 1695static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1696 int x, int y)
81255565
JB		 1697{
1698 struct drm_device *dev = crtc->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1701 struct intel_framebuffer *intel_fb;
05394f39 1702 struct drm_i915_gem_object *obj;
81255565
JB		 1703 int plane = intel_crtc->plane;
1704 unsigned long Start, Offset;
81255565 1705 u32 dspcntr;
5eddb70b 1706 u32 reg;
81255565
JB		 1707
1708 switch (plane) {
1709 case 0:
1710 case 1:
1711 break;
1712 default:
1713 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1714 return -EINVAL;
1715 }
1716
1717 intel_fb = to_intel_framebuffer(fb);
1718 obj = intel_fb->obj;
81255565 1719
5eddb70b
CW		 1720 reg = DSPCNTR(plane);
1721 dspcntr = I915_READ(reg);
81255565
JB		 1722 /* Mask out pixel format bits in case we change it */
1723 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1724 switch (fb->bits_per_pixel) {
1725 case 8:
1726 dspcntr |= DISPPLANE_8BPP;
1727 break;
1728 case 16:
1729 if (fb->depth == 15)
1730 dspcntr |= DISPPLANE_15_16BPP;
1731 else
1732 dspcntr |= DISPPLANE_16BPP;
1733 break;
1734 case 24:
1735 case 32:
1736 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1737 break;
1738 default:
17638cd6 1739 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1740 return -EINVAL;
1741 }
a6c45cf0 1742 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1743 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1744 dspcntr |= DISPPLANE_TILED;
1745 else
1746 dspcntr &= ~DISPPLANE_TILED;
1747 }
1748
5eddb70b 1749 I915_WRITE(reg, dspcntr);
81255565 1750
05394f39 1751 Start = obj->gtt_offset;
01f2c773 1752 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1753
4e6cfefc 1754 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1755 Start, Offset, x, y, fb->pitches[0]);
1756 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1757 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1758 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1760 I915_WRITE(DSPADDR(plane), Offset);
1761 } else
1762 I915_WRITE(DSPADDR(plane), Start + Offset);
1763 POSTING_READ(reg);
81255565 1764
17638cd6
JB		 1765 return 0;
1766}
1767
1768static int ironlake_update_plane(struct drm_crtc *crtc,
1769 struct drm_framebuffer *fb, int x, int y)
1770{
1771 struct drm_device *dev = crtc->dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1774 struct intel_framebuffer *intel_fb;
1775 struct drm_i915_gem_object *obj;
1776 int plane = intel_crtc->plane;
1777 unsigned long Start, Offset;
1778 u32 dspcntr;
1779 u32 reg;
1780
1781 switch (plane) {
1782 case 0:
1783 case 1:
27f8227b 1784 case 2:
17638cd6
JB		 1785 break;
1786 default:
1787 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1788 return -EINVAL;
1789 }
1790
1791 intel_fb = to_intel_framebuffer(fb);
1792 obj = intel_fb->obj;
1793
1794 reg = DSPCNTR(plane);
1795 dspcntr = I915_READ(reg);
1796 /* Mask out pixel format bits in case we change it */
1797 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1798 switch (fb->bits_per_pixel) {
1799 case 8:
1800 dspcntr |= DISPPLANE_8BPP;
1801 break;
1802 case 16:
1803 if (fb->depth != 16)
1804 return -EINVAL;
1805
1806 dspcntr |= DISPPLANE_16BPP;
1807 break;
1808 case 24:
1809 case 32:
1810 if (fb->depth == 24)
1811 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1812 else if (fb->depth == 30)
1813 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1814 else
1815 return -EINVAL;
1816 break;
1817 default:
1818 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1819 return -EINVAL;
1820 }
1821
1822 if (obj->tiling_mode != I915_TILING_NONE)
1823 dspcntr |= DISPPLANE_TILED;
1824 else
1825 dspcntr &= ~DISPPLANE_TILED;
1826
1827 /* must disable */
1828 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1829
1830 I915_WRITE(reg, dspcntr);
1831
1832 Start = obj->gtt_offset;
01f2c773 1833 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1834
1835 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1836 Start, Offset, x, y, fb->pitches[0]);
1837 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1838 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1839 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1840 I915_WRITE(DSPADDR(plane), Offset);
1841 POSTING_READ(reg);
1842
1843 return 0;
1844}
1845
1846/* Assume fb object is pinned & idle & fenced and just update base pointers */
1847static int
1848intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1849 int x, int y, enum mode_set_atomic state)
1850{
1851 struct drm_device *dev = crtc->dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1853
6b8e6ed0
CW		 1854 if (dev_priv->display.disable_fbc)
1855 dev_priv->display.disable_fbc(dev);
3dec0095 1856 intel_increase_pllclock(crtc);
81255565 1857
6b8e6ed0 1858 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1859}
1860
14667a4b
CW		 1861static int
1862intel_finish_fb(struct drm_framebuffer *old_fb)
1863{
1864 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1865 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1866 bool was_interruptible = dev_priv->mm.interruptible;
1867 int ret;
1868
1869 wait_event(dev_priv->pending_flip_queue,
1870 atomic_read(&dev_priv->mm.wedged) ||
1871 atomic_read(&obj->pending_flip) == 0);
1872
1873 /* Big Hammer, we also need to ensure that any pending
1874 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1875 * current scanout is retired before unpinning the old
1876 * framebuffer.
1877 *
1878 * This should only fail upon a hung GPU, in which case we
1879 * can safely continue.
1880 */
1881 dev_priv->mm.interruptible = false;
1882 ret = i915_gem_object_finish_gpu(obj);
1883 dev_priv->mm.interruptible = was_interruptible;
1884
1885 return ret;
1886}
1887
5c3b82e2 1888static int
3c4fdcfb
KH		 1889intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1890 struct drm_framebuffer *old_fb)
79e53945
JB		 1891{
1892 struct drm_device *dev = crtc->dev;
6b8e6ed0 1893 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1894 struct drm_i915_master_private *master_priv;
1895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1896 int ret;
79e53945
JB		 1897
1898 /* no fb bound */
1899 if (!crtc->fb) {
a5071c2f 1900 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 1901 return 0;
1902 }
1903
265db958 1904 switch (intel_crtc->plane) {
5c3b82e2
CW		 1905 case 0:
1906 case 1:
1907 break;
27f8227b
JB		 1908 case 2:
1909 if (IS_IVYBRIDGE(dev))
1910 break;
1911 /* fall through otherwise */
5c3b82e2 1912 default:
a5071c2f 1913 DRM_ERROR("no plane for crtc\n");
5c3b82e2 1914 return -EINVAL;
79e53945
JB		 1915 }
1916
5c3b82e2 1917 mutex_lock(&dev->struct_mutex);
265db958
CW		 1918 ret = intel_pin_and_fence_fb_obj(dev,
1919 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1920 NULL);
5c3b82e2
CW		 1921 if (ret != 0) {
1922 mutex_unlock(&dev->struct_mutex);
a5071c2f 1923 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 1924 return ret;
1925 }
79e53945 1926
14667a4b
CW		 1927 if (old_fb)
1928 intel_finish_fb(old_fb);
265db958 1929
6b8e6ed0 1930 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 1931 if (ret) {
1690e1eb 1932 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1933 mutex_unlock(&dev->struct_mutex);
a5071c2f 1934 DRM_ERROR("failed to update base address\n");
4e6cfefc 1935 return ret;
79e53945 1936 }
3c4fdcfb 1937
b7f1de28
CW		 1938 if (old_fb) {
1939 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 1940 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1941 }
652c393a 1942
6b8e6ed0 1943 intel_update_fbc(dev);
5c3b82e2 1944 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1945
1946 if (!dev->primary->master)
5c3b82e2 1947 return 0;
79e53945
JB		 1948
1949 master_priv = dev->primary->master->driver_priv;
1950 if (!master_priv->sarea_priv)
5c3b82e2 1951 return 0;
79e53945 1952
265db958 1953 if (intel_crtc->pipe) {
79e53945
JB		 1954 master_priv->sarea_priv->pipeB_x = x;
1955 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 1956 } else {
1957 master_priv->sarea_priv->pipeA_x = x;
1958 master_priv->sarea_priv->pipeA_y = y;
79e53945 1959 }
5c3b82e2
CW		 1960
1961 return 0;
79e53945
JB		 1962}
1963
5eddb70b 1964static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 1965{
1966 struct drm_device *dev = crtc->dev;
1967 struct drm_i915_private *dev_priv = dev->dev_private;
1968 u32 dpa_ctl;
1969
28c97730 1970 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 1971 dpa_ctl = I915_READ(DP_A);
1972 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1973
1974 if (clock < 200000) {
1975 u32 temp;
1976 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1977 /* workaround for 160Mhz:
1978 1) program 0x4600c bits 15:0 = 0x8124
1979 2) program 0x46010 bit 0 = 1
1980 3) program 0x46034 bit 24 = 1
1981 4) program 0x64000 bit 14 = 1
1982 */
1983 temp = I915_READ(0x4600c);
1984 temp &= 0xffff0000;
1985 I915_WRITE(0x4600c, temp | 0x8124);
1986
1987 temp = I915_READ(0x46010);
1988 I915_WRITE(0x46010, temp | 1);
1989
1990 temp = I915_READ(0x46034);
1991 I915_WRITE(0x46034, temp | (1 << 24));
1992 } else {
1993 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1994 }
1995 I915_WRITE(DP_A, dpa_ctl);
1996
5eddb70b 1997 POSTING_READ(DP_A);
32f9d658
ZW		 1998 udelay(500);
1999}
2000
5e84e1a4
ZW		 2001static void intel_fdi_normal_train(struct drm_crtc *crtc)
2002{
2003 struct drm_device *dev = crtc->dev;
2004 struct drm_i915_private *dev_priv = dev->dev_private;
2005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2006 int pipe = intel_crtc->pipe;
2007 u32 reg, temp;
2008
2009 /* enable normal train */
2010 reg = FDI_TX_CTL(pipe);
2011 temp = I915_READ(reg);
61e499bf 2012 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2013 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2014 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2015 } else {
2016 temp &= ~FDI_LINK_TRAIN_NONE;
2017 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2018 }
5e84e1a4
ZW		 2019 I915_WRITE(reg, temp);
2020
2021 reg = FDI_RX_CTL(pipe);
2022 temp = I915_READ(reg);
2023 if (HAS_PCH_CPT(dev)) {
2024 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2025 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2026 } else {
2027 temp &= ~FDI_LINK_TRAIN_NONE;
2028 temp |= FDI_LINK_TRAIN_NONE;
2029 }
2030 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2031
2032 /* wait one idle pattern time */
2033 POSTING_READ(reg);
2034 udelay(1000);
357555c0
JB		 2035
2036 /* IVB wants error correction enabled */
2037 if (IS_IVYBRIDGE(dev))
2038 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2039 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2040}
2041
291427f5
JB		 2042static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 u32 flags = I915_READ(SOUTH_CHICKEN1);
2046
2047 flags |= FDI_PHASE_SYNC_OVR(pipe);
2048 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2049 flags |= FDI_PHASE_SYNC_EN(pipe);
2050 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2051 POSTING_READ(SOUTH_CHICKEN1);
2052}
2053
8db9d77b
ZW		 2054/* The FDI link training functions for ILK/Ibexpeak. */
2055static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2056{
2057 struct drm_device *dev = crtc->dev;
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2060 int pipe = intel_crtc->pipe;
0fc932b8 2061 int plane = intel_crtc->plane;
5eddb70b 2062 u32 reg, temp, tries;
8db9d77b 2063
0fc932b8
JB		 2064 /* FDI needs bits from pipe & plane first */
2065 assert_pipe_enabled(dev_priv, pipe);
2066 assert_plane_enabled(dev_priv, plane);
2067
e1a44743
AJ		 2068 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2069 for train result */
5eddb70b
CW		 2070 reg = FDI_RX_IMR(pipe);
2071 temp = I915_READ(reg);
e1a44743
AJ		 2072 temp &= ~FDI_RX_SYMBOL_LOCK;
2073 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2074 I915_WRITE(reg, temp);
2075 I915_READ(reg);
e1a44743
AJ		 2076 udelay(150);
2077
8db9d77b 2078 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2079 reg = FDI_TX_CTL(pipe);
2080 temp = I915_READ(reg);
77ffb597
AJ		 2081 temp &= ~(7 << 19);
2082 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2083 temp &= ~FDI_LINK_TRAIN_NONE;
2084 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2085 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2086
5eddb70b
CW		 2087 reg = FDI_RX_CTL(pipe);
2088 temp = I915_READ(reg);
8db9d77b
ZW		 2089 temp &= ~FDI_LINK_TRAIN_NONE;
2090 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2091 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2092
2093 POSTING_READ(reg);
8db9d77b
ZW		 2094 udelay(150);
2095
5b2adf89 2096 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2097 if (HAS_PCH_IBX(dev)) {
2098 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2099 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2100 FDI_RX_PHASE_SYNC_POINTER_EN);
2101 }
5b2adf89 2102
5eddb70b 2103 reg = FDI_RX_IIR(pipe);
e1a44743 2104 for (tries = 0; tries < 5; tries++) {
5eddb70b 2105 temp = I915_READ(reg);
8db9d77b
ZW		 2106 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2107
2108 if ((temp & FDI_RX_BIT_LOCK)) {
2109 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2110 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2111 break;
2112 }
8db9d77b 2113 }
e1a44743 2114 if (tries == 5)
5eddb70b 2115 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2116
2117 /* Train 2 */
5eddb70b
CW		 2118 reg = FDI_TX_CTL(pipe);
2119 temp = I915_READ(reg);
8db9d77b
ZW		 2120 temp &= ~FDI_LINK_TRAIN_NONE;
2121 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2122 I915_WRITE(reg, temp);
8db9d77b 2123
5eddb70b
CW		 2124 reg = FDI_RX_CTL(pipe);
2125 temp = I915_READ(reg);
8db9d77b
ZW		 2126 temp &= ~FDI_LINK_TRAIN_NONE;
2127 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2128 I915_WRITE(reg, temp);
8db9d77b 2129
5eddb70b
CW		 2130 POSTING_READ(reg);
2131 udelay(150);
8db9d77b 2132
5eddb70b 2133 reg = FDI_RX_IIR(pipe);
e1a44743 2134 for (tries = 0; tries < 5; tries++) {
5eddb70b 2135 temp = I915_READ(reg);
8db9d77b
ZW		 2136 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2137
2138 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2139 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2140 DRM_DEBUG_KMS("FDI train 2 done.\n");
2141 break;
2142 }
8db9d77b 2143 }
e1a44743 2144 if (tries == 5)
5eddb70b 2145 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2146
2147 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2148
8db9d77b
ZW		 2149}
2150
0206e353 2151static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2152 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2153 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2154 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2155 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2156};
2157
2158/* The FDI link training functions for SNB/Cougarpoint. */
2159static void gen6_fdi_link_train(struct drm_crtc *crtc)
2160{
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164 int pipe = intel_crtc->pipe;
fa37d39e 2165 u32 reg, temp, i, retry;
8db9d77b 2166
e1a44743
AJ		 2167 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2168 for train result */
5eddb70b
CW		 2169 reg = FDI_RX_IMR(pipe);
2170 temp = I915_READ(reg);
e1a44743
AJ		 2171 temp &= ~FDI_RX_SYMBOL_LOCK;
2172 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2173 I915_WRITE(reg, temp);
2174
2175 POSTING_READ(reg);
e1a44743
AJ		 2176 udelay(150);
2177
8db9d77b 2178 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2179 reg = FDI_TX_CTL(pipe);
2180 temp = I915_READ(reg);
77ffb597
AJ		 2181 temp &= ~(7 << 19);
2182 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2183 temp &= ~FDI_LINK_TRAIN_NONE;
2184 temp |= FDI_LINK_TRAIN_PATTERN_1;
2185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2186 /* SNB-B */
2187 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2188 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2189
5eddb70b
CW		 2190 reg = FDI_RX_CTL(pipe);
2191 temp = I915_READ(reg);
8db9d77b
ZW		 2192 if (HAS_PCH_CPT(dev)) {
2193 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2194 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2195 } else {
2196 temp &= ~FDI_LINK_TRAIN_NONE;
2197 temp |= FDI_LINK_TRAIN_PATTERN_1;
2198 }
5eddb70b
CW		 2199 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2200
2201 POSTING_READ(reg);
8db9d77b
ZW		 2202 udelay(150);
2203
291427f5
JB		 2204 if (HAS_PCH_CPT(dev))
2205 cpt_phase_pointer_enable(dev, pipe);
2206
0206e353 2207 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2208 reg = FDI_TX_CTL(pipe);
2209 temp = I915_READ(reg);
8db9d77b
ZW		 2210 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2211 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2212 I915_WRITE(reg, temp);
2213
2214 POSTING_READ(reg);
8db9d77b
ZW		 2215 udelay(500);
2216
fa37d39e
SP		 2217 for (retry = 0; retry < 5; retry++) {
2218 reg = FDI_RX_IIR(pipe);
2219 temp = I915_READ(reg);
2220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2221 if (temp & FDI_RX_BIT_LOCK) {
2222 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2223 DRM_DEBUG_KMS("FDI train 1 done.\n");
2224 break;
2225 }
2226 udelay(50);
8db9d77b 2227 }
fa37d39e
SP		 2228 if (retry < 5)
2229 break;
8db9d77b
ZW		 2230 }
2231 if (i == 4)
5eddb70b 2232 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2233
2234 /* Train 2 */
5eddb70b
CW		 2235 reg = FDI_TX_CTL(pipe);
2236 temp = I915_READ(reg);
8db9d77b
ZW		 2237 temp &= ~FDI_LINK_TRAIN_NONE;
2238 temp |= FDI_LINK_TRAIN_PATTERN_2;
2239 if (IS_GEN6(dev)) {
2240 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2241 /* SNB-B */
2242 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2243 }
5eddb70b 2244 I915_WRITE(reg, temp);
8db9d77b 2245
5eddb70b
CW		 2246 reg = FDI_RX_CTL(pipe);
2247 temp = I915_READ(reg);
8db9d77b
ZW		 2248 if (HAS_PCH_CPT(dev)) {
2249 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2250 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2251 } else {
2252 temp &= ~FDI_LINK_TRAIN_NONE;
2253 temp |= FDI_LINK_TRAIN_PATTERN_2;
2254 }
5eddb70b
CW		 2255 I915_WRITE(reg, temp);
2256
2257 POSTING_READ(reg);
8db9d77b
ZW		 2258 udelay(150);
2259
0206e353 2260 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2261 reg = FDI_TX_CTL(pipe);
2262 temp = I915_READ(reg);
8db9d77b
ZW		 2263 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2264 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2265 I915_WRITE(reg, temp);
2266
2267 POSTING_READ(reg);
8db9d77b
ZW		 2268 udelay(500);
2269
fa37d39e
SP		 2270 for (retry = 0; retry < 5; retry++) {
2271 reg = FDI_RX_IIR(pipe);
2272 temp = I915_READ(reg);
2273 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2274 if (temp & FDI_RX_SYMBOL_LOCK) {
2275 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2276 DRM_DEBUG_KMS("FDI train 2 done.\n");
2277 break;
2278 }
2279 udelay(50);
8db9d77b 2280 }
fa37d39e
SP		 2281 if (retry < 5)
2282 break;
8db9d77b
ZW		 2283 }
2284 if (i == 4)
5eddb70b 2285 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2286
2287 DRM_DEBUG_KMS("FDI train done.\n");
2288}
2289
357555c0
JB		 2290/* Manual link training for Ivy Bridge A0 parts */
2291static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2292{
2293 struct drm_device *dev = crtc->dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 int pipe = intel_crtc->pipe;
2297 u32 reg, temp, i;
2298
2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
2305 I915_WRITE(reg, temp);
2306
2307 POSTING_READ(reg);
2308 udelay(150);
2309
2310 /* enable CPU FDI TX and PCH FDI RX */
2311 reg = FDI_TX_CTL(pipe);
2312 temp = I915_READ(reg);
2313 temp &= ~(7 << 19);
2314 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2315 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2316 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2317 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2318 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2319 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2320 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2321
2322 reg = FDI_RX_CTL(pipe);
2323 temp = I915_READ(reg);
2324 temp &= ~FDI_LINK_TRAIN_AUTO;
2325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2326 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2327 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2328 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2329
2330 POSTING_READ(reg);
2331 udelay(150);
2332
291427f5
JB		 2333 if (HAS_PCH_CPT(dev))
2334 cpt_phase_pointer_enable(dev, pipe);
2335
0206e353 2336 for (i = 0; i < 4; i++) {
357555c0
JB		 2337 reg = FDI_TX_CTL(pipe);
2338 temp = I915_READ(reg);
2339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2340 temp |= snb_b_fdi_train_param[i];
2341 I915_WRITE(reg, temp);
2342
2343 POSTING_READ(reg);
2344 udelay(500);
2345
2346 reg = FDI_RX_IIR(pipe);
2347 temp = I915_READ(reg);
2348 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2349
2350 if (temp & FDI_RX_BIT_LOCK ||
2351 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2352 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2353 DRM_DEBUG_KMS("FDI train 1 done.\n");
2354 break;
2355 }
2356 }
2357 if (i == 4)
2358 DRM_ERROR("FDI train 1 fail!\n");
2359
2360 /* Train 2 */
2361 reg = FDI_TX_CTL(pipe);
2362 temp = I915_READ(reg);
2363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2364 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2366 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2367 I915_WRITE(reg, temp);
2368
2369 reg = FDI_RX_CTL(pipe);
2370 temp = I915_READ(reg);
2371 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2372 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2373 I915_WRITE(reg, temp);
2374
2375 POSTING_READ(reg);
2376 udelay(150);
2377
0206e353 2378 for (i = 0; i < 4; i++) {
357555c0
JB		 2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
2381 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382 temp |= snb_b_fdi_train_param[i];
2383 I915_WRITE(reg, temp);
2384
2385 POSTING_READ(reg);
2386 udelay(500);
2387
2388 reg = FDI_RX_IIR(pipe);
2389 temp = I915_READ(reg);
2390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392 if (temp & FDI_RX_SYMBOL_LOCK) {
2393 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2394 DRM_DEBUG_KMS("FDI train 2 done.\n");
2395 break;
2396 }
2397 }
2398 if (i == 4)
2399 DRM_ERROR("FDI train 2 fail!\n");
2400
2401 DRM_DEBUG_KMS("FDI train done.\n");
2402}
2403
2404static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
5eddb70b 2410 u32 reg, temp;
79e53945 2411
c64e311e 2412 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2413 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2414 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2415
c98e9dcf 2416 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2417 reg = FDI_RX_CTL(pipe);
2418 temp = I915_READ(reg);
2419 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2420 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2421 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2422 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2423
2424 POSTING_READ(reg);
c98e9dcf
JB		 2425 udelay(200);
2426
2427 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2428 temp = I915_READ(reg);
2429 I915_WRITE(reg, temp | FDI_PCDCLK);
2430
2431 POSTING_READ(reg);
c98e9dcf
JB		 2432 udelay(200);
2433
2434 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
c98e9dcf 2437 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2438 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2439
2440 POSTING_READ(reg);
c98e9dcf 2441 udelay(100);
6be4a607 2442 }
0e23b99d
JB		 2443}
2444
291427f5
JB		 2445static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2446{
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 u32 flags = I915_READ(SOUTH_CHICKEN1);
2449
2450 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2451 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2452 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2453 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2454 POSTING_READ(SOUTH_CHICKEN1);
2455}
0fc932b8
JB		 2456static void ironlake_fdi_disable(struct drm_crtc *crtc)
2457{
2458 struct drm_device *dev = crtc->dev;
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461 int pipe = intel_crtc->pipe;
2462 u32 reg, temp;
2463
2464 /* disable CPU FDI tx and PCH FDI rx */
2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2468 POSTING_READ(reg);
2469
2470 reg = FDI_RX_CTL(pipe);
2471 temp = I915_READ(reg);
2472 temp &= ~(0x7 << 16);
2473 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2474 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2475
2476 POSTING_READ(reg);
2477 udelay(100);
2478
2479 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2480 if (HAS_PCH_IBX(dev)) {
2481 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2482 I915_WRITE(FDI_RX_CHICKEN(pipe),
2483 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2484 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2485 } else if (HAS_PCH_CPT(dev)) {
2486 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2487 }
0fc932b8
JB		 2488
2489 /* still set train pattern 1 */
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~FDI_LINK_TRAIN_NONE;
2493 temp |= FDI_LINK_TRAIN_PATTERN_1;
2494 I915_WRITE(reg, temp);
2495
2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501 } else {
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 }
2505 /* BPC in FDI rx is consistent with that in PIPECONF */
2506 temp &= ~(0x07 << 16);
2507 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2508 I915_WRITE(reg, temp);
2509
2510 POSTING_READ(reg);
2511 udelay(100);
2512}
2513
e6c3a2a6
CW		 2514static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2515{
0f91128d 2516 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2517
2518 if (crtc->fb == NULL)
2519 return;
2520
0f91128d
CW		 2521 mutex_lock(&dev->struct_mutex);
2522 intel_finish_fb(crtc->fb);
2523 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2524}
2525
040484af
JB		 2526static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2527{
2528 struct drm_device *dev = crtc->dev;
2529 struct drm_mode_config *mode_config = &dev->mode_config;
2530 struct intel_encoder *encoder;
2531
2532 /*
2533 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2534 * must be driven by its own crtc; no sharing is possible.
2535 */
2536 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2537 if (encoder->base.crtc != crtc)
2538 continue;
2539
2540 switch (encoder->type) {
2541 case INTEL_OUTPUT_EDP:
2542 if (!intel_encoder_is_pch_edp(&encoder->base))
2543 return false;
2544 continue;
2545 }
2546 }
2547
2548 return true;
2549}
2550
f67a559d
JB		 2551/*
2552 * Enable PCH resources required for PCH ports:
2553 * - PCH PLLs
2554 * - FDI training & RX/TX
2555 * - update transcoder timings
2556 * - DP transcoding bits
2557 * - transcoder
2558 */
2559static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2560{
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
ee7b9f93 2565 u32 reg, temp;
2c07245f 2566
c98e9dcf 2567 /* For PCH output, training FDI link */
674cf967 2568 dev_priv->display.fdi_link_train(crtc);
2c07245f 2569
ee7b9f93 2570 intel_enable_pch_pll(intel_crtc);
8db9d77b 2571
c98e9dcf 2572 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2573 u32 sel;
4b645f14 2574
c98e9dcf 2575 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2576 switch (pipe) {
2577 default:
2578 case 0:
2579 temp |= TRANSA_DPLL_ENABLE;
2580 sel = TRANSA_DPLLB_SEL;
2581 break;
2582 case 1:
2583 temp |= TRANSB_DPLL_ENABLE;
2584 sel = TRANSB_DPLLB_SEL;
2585 break;
2586 case 2:
2587 temp |= TRANSC_DPLL_ENABLE;
2588 sel = TRANSC_DPLLB_SEL;
2589 break;
d64311ab 2590 }
ee7b9f93
JB		 2591 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2592 temp |= sel;
2593 else
2594 temp &= ~sel;
c98e9dcf 2595 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2596 }
5eddb70b 2597
d9b6cb56
JB		 2598 /* set transcoder timing, panel must allow it */
2599 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2600 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2601 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2602 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2603
5eddb70b
CW		 2604 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2605 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2606 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2607 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2608
5e84e1a4
ZW		 2609 intel_fdi_normal_train(crtc);
2610
c98e9dcf
JB		 2611 /* For PCH DP, enable TRANS_DP_CTL */
2612 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2613 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2614 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2615 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2616 reg = TRANS_DP_CTL(pipe);
2617 temp = I915_READ(reg);
2618 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2619 TRANS_DP_SYNC_MASK |
2620 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2621 temp |= (TRANS_DP_OUTPUT_ENABLE |
2622 TRANS_DP_ENH_FRAMING);
9325c9f0 2623 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2624
2625 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2626 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2627 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2628 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2629
2630 switch (intel_trans_dp_port_sel(crtc)) {
2631 case PCH_DP_B:
5eddb70b 2632 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2633 break;
2634 case PCH_DP_C:
5eddb70b 2635 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2636 break;
2637 case PCH_DP_D:
5eddb70b 2638 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2639 break;
2640 default:
2641 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2642 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2643 break;
32f9d658 2644 }
2c07245f 2645
5eddb70b 2646 I915_WRITE(reg, temp);
6be4a607 2647 }
b52eb4dc 2648
040484af 2649 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2650}
2651
ee7b9f93
JB		 2652static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2653{
2654 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2655
2656 if (pll == NULL)
2657 return;
2658
2659 if (pll->refcount == 0) {
2660 WARN(1, "bad PCH PLL refcount\n");
2661 return;
2662 }
2663
2664 --pll->refcount;
2665 intel_crtc->pch_pll = NULL;
2666}
2667
2668static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2669{
2670 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2671 struct intel_pch_pll *pll;
2672 int i;
2673
2674 pll = intel_crtc->pch_pll;
2675 if (pll) {
2676 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2677 intel_crtc->base.base.id, pll->pll_reg);
2678 goto prepare;
2679 }
2680
2681 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2682 pll = &dev_priv->pch_plls[i];
2683
2684 /* Only want to check enabled timings first */
2685 if (pll->refcount == 0)
2686 continue;
2687
2688 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2689 fp == I915_READ(pll->fp0_reg)) {
2690 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2691 intel_crtc->base.base.id,
2692 pll->pll_reg, pll->refcount, pll->active);
2693
2694 goto found;
2695 }
2696 }
2697
2698 /* Ok no matching timings, maybe there's a free one? */
2699 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2700 pll = &dev_priv->pch_plls[i];
2701 if (pll->refcount == 0) {
2702 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2703 intel_crtc->base.base.id, pll->pll_reg);
2704 goto found;
2705 }
2706 }
2707
2708 return NULL;
2709
2710found:
2711 intel_crtc->pch_pll = pll;
2712 pll->refcount++;
2713 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2714prepare: /* separate function? */
2715 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2716
e04c7350
CW		 2717 /* Wait for the clocks to stabilize before rewriting the regs */
2718 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2719 POSTING_READ(pll->pll_reg);
2720 udelay(150);
e04c7350
CW		 2721
2722 I915_WRITE(pll->fp0_reg, fp);
2723 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2724 pll->on = false;
2725 return pll;
2726}
2727
d4270e57
JB		 2728void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2729{
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2732 u32 temp;
2733
2734 temp = I915_READ(dslreg);
2735 udelay(500);
2736 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2737 /* Without this, mode sets may fail silently on FDI */
2738 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2739 udelay(250);
2740 I915_WRITE(tc2reg, 0);
2741 if (wait_for(I915_READ(dslreg) != temp, 5))
2742 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2743 }
2744}
2745
f67a559d
JB		 2746static void ironlake_crtc_enable(struct drm_crtc *crtc)
2747{
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751 int pipe = intel_crtc->pipe;
2752 int plane = intel_crtc->plane;
2753 u32 temp;
2754 bool is_pch_port;
2755
2756 if (intel_crtc->active)
2757 return;
2758
2759 intel_crtc->active = true;
2760 intel_update_watermarks(dev);
2761
2762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2763 temp = I915_READ(PCH_LVDS);
2764 if ((temp & LVDS_PORT_EN) == 0)
2765 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2766 }
2767
2768 is_pch_port = intel_crtc_driving_pch(crtc);
2769
2770 if (is_pch_port)
357555c0 2771 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2772 else
2773 ironlake_fdi_disable(crtc);
2774
2775 /* Enable panel fitting for LVDS */
2776 if (dev_priv->pch_pf_size &&
2777 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2778 /* Force use of hard-coded filter coefficients
2779 * as some pre-programmed values are broken,
2780 * e.g. x201.
2781 */
9db4a9c7
JB		 2782 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2783 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2784 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2785 }
2786
9c54c0dd
JB		 2787 /*
2788 * On ILK+ LUT must be loaded before the pipe is running but with
2789 * clocks enabled
2790 */
2791 intel_crtc_load_lut(crtc);
2792
f67a559d
JB		 2793 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2794 intel_enable_plane(dev_priv, plane, pipe);
2795
2796 if (is_pch_port)
2797 ironlake_pch_enable(crtc);
c98e9dcf 2798
d1ebd816 2799 mutex_lock(&dev->struct_mutex);
bed4a673 2800 intel_update_fbc(dev);
d1ebd816
BW		 2801 mutex_unlock(&dev->struct_mutex);
2802
6b383a7f 2803 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2804}
2805
2806static void ironlake_crtc_disable(struct drm_crtc *crtc)
2807{
2808 struct drm_device *dev = crtc->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2811 int pipe = intel_crtc->pipe;
2812 int plane = intel_crtc->plane;
5eddb70b 2813 u32 reg, temp;
b52eb4dc 2814
f7abfe8b
CW		 2815 if (!intel_crtc->active)
2816 return;
2817
e6c3a2a6 2818 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2819 drm_vblank_off(dev, pipe);
6b383a7f 2820 intel_crtc_update_cursor(crtc, false);
5eddb70b 2821
b24e7179 2822 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2823
973d04f9
CW		 2824 if (dev_priv->cfb_plane == plane)
2825 intel_disable_fbc(dev);
2c07245f 2826
b24e7179 2827 intel_disable_pipe(dev_priv, pipe);
32f9d658 2828
6be4a607 2829 /* Disable PF */
9db4a9c7
JB		 2830 I915_WRITE(PF_CTL(pipe), 0);
2831 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2832
0fc932b8 2833 ironlake_fdi_disable(crtc);
2c07245f 2834
47a05eca
JB		 2835 /* This is a horrible layering violation; we should be doing this in
2836 * the connector/encoder ->prepare instead, but we don't always have
2837 * enough information there about the config to know whether it will
2838 * actually be necessary or just cause undesired flicker.
2839 */
2840 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2841
040484af 2842 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2843
6be4a607
JB		 2844 if (HAS_PCH_CPT(dev)) {
2845 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2846 reg = TRANS_DP_CTL(pipe);
2847 temp = I915_READ(reg);
2848 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2849 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2850 I915_WRITE(reg, temp);
6be4a607
JB		 2851
2852 /* disable DPLL_SEL */
2853 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2854 switch (pipe) {
2855 case 0:
d64311ab 2856 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 2857 break;
2858 case 1:
6be4a607 2859 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2860 break;
2861 case 2:
4b645f14 2862 /* C shares PLL A or B */
d64311ab 2863 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 2864 break;
2865 default:
2866 BUG(); /* wtf */
2867 }
6be4a607 2868 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2869 }
e3421a18 2870
6be4a607 2871 /* disable PCH DPLL */
ee7b9f93 2872 intel_disable_pch_pll(intel_crtc);
8db9d77b 2873
6be4a607 2874 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2875 reg = FDI_RX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2878
6be4a607 2879 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2883
2884 POSTING_READ(reg);
6be4a607 2885 udelay(100);
8db9d77b 2886
5eddb70b
CW		 2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2890
6be4a607 2891 /* Wait for the clocks to turn off. */
5eddb70b 2892 POSTING_READ(reg);
6be4a607 2893 udelay(100);
6b383a7f 2894
f7abfe8b 2895 intel_crtc->active = false;
6b383a7f 2896 intel_update_watermarks(dev);
d1ebd816
BW		 2897
2898 mutex_lock(&dev->struct_mutex);
6b383a7f 2899 intel_update_fbc(dev);
d1ebd816 2900 mutex_unlock(&dev->struct_mutex);
6be4a607 2901}
1b3c7a47 2902
6be4a607
JB		 2903static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2904{
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
2907 int plane = intel_crtc->plane;
8db9d77b 2908
6be4a607
JB		 2909 /* XXX: When our outputs are all unaware of DPMS modes other than off
2910 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2911 */
2912 switch (mode) {
2913 case DRM_MODE_DPMS_ON:
2914 case DRM_MODE_DPMS_STANDBY:
2915 case DRM_MODE_DPMS_SUSPEND:
2916 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2917 ironlake_crtc_enable(crtc);
2918 break;
1b3c7a47 2919
6be4a607
JB		 2920 case DRM_MODE_DPMS_OFF:
2921 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2922 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2923 break;
2924 }
2925}
2926
ee7b9f93
JB		 2927static void ironlake_crtc_off(struct drm_crtc *crtc)
2928{
2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930 intel_put_pch_pll(intel_crtc);
2931}
2932
02e792fb
DV		 2933static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2934{
02e792fb 2935 if (!enable && intel_crtc->overlay) {
23f09ce3 2936 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2937 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2938
23f09ce3 2939 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2940 dev_priv->mm.interruptible = false;
2941 (void) intel_overlay_switch_off(intel_crtc->overlay);
2942 dev_priv->mm.interruptible = true;
23f09ce3 2943 mutex_unlock(&dev->struct_mutex);
02e792fb 2944 }
02e792fb 2945
5dcdbcb0
CW		 2946 /* Let userspace switch the overlay on again. In most cases userspace
2947 * has to recompute where to put it anyway.
2948 */
02e792fb
DV		 2949}
2950
0b8765c6 2951static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2952{
2953 struct drm_device *dev = crtc->dev;
79e53945
JB		 2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 int pipe = intel_crtc->pipe;
80824003 2957 int plane = intel_crtc->plane;
79e53945 2958
f7abfe8b
CW		 2959 if (intel_crtc->active)
2960 return;
2961
2962 intel_crtc->active = true;
6b383a7f
CW		 2963 intel_update_watermarks(dev);
2964
63d7bbe9 2965 intel_enable_pll(dev_priv, pipe);
040484af 2966 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2967 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2968
0b8765c6 2969 intel_crtc_load_lut(crtc);
bed4a673 2970 intel_update_fbc(dev);
79e53945 2971
0b8765c6
JB		 2972 /* Give the overlay scaler a chance to enable if it's on this pipe */
2973 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2974 intel_crtc_update_cursor(crtc, true);
0b8765c6 2975}
79e53945 2976
0b8765c6
JB		 2977static void i9xx_crtc_disable(struct drm_crtc *crtc)
2978{
2979 struct drm_device *dev = crtc->dev;
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2982 int pipe = intel_crtc->pipe;
2983 int plane = intel_crtc->plane;
b690e96c 2984
f7abfe8b
CW		 2985 if (!intel_crtc->active)
2986 return;
2987
0b8765c6 2988 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2989 intel_crtc_wait_for_pending_flips(crtc);
2990 drm_vblank_off(dev, pipe);
0b8765c6 2991 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2992 intel_crtc_update_cursor(crtc, false);
0b8765c6 2993
973d04f9
CW		 2994 if (dev_priv->cfb_plane == plane)
2995 intel_disable_fbc(dev);
79e53945 2996
b24e7179 2997 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2998 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2999 intel_disable_pll(dev_priv, pipe);
0b8765c6 3000
f7abfe8b 3001 intel_crtc->active = false;
6b383a7f
CW		 3002 intel_update_fbc(dev);
3003 intel_update_watermarks(dev);
0b8765c6
JB		 3004}
3005
3006static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3007{
3008 /* XXX: When our outputs are all unaware of DPMS modes other than off
3009 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3010 */
3011 switch (mode) {
3012 case DRM_MODE_DPMS_ON:
3013 case DRM_MODE_DPMS_STANDBY:
3014 case DRM_MODE_DPMS_SUSPEND:
3015 i9xx_crtc_enable(crtc);
3016 break;
3017 case DRM_MODE_DPMS_OFF:
3018 i9xx_crtc_disable(crtc);
79e53945
JB		 3019 break;
3020 }
2c07245f
ZW		 3021}
3022
ee7b9f93
JB		 3023static void i9xx_crtc_off(struct drm_crtc *crtc)
3024{
3025}
3026
2c07245f
ZW		 3027/**
3028 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3029 */
3030static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3031{
3032 struct drm_device *dev = crtc->dev;
e70236a8 3033 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3034 struct drm_i915_master_private *master_priv;
3035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3036 int pipe = intel_crtc->pipe;
3037 bool enabled;
3038
032d2a0d
CW		 3039 if (intel_crtc->dpms_mode == mode)
3040 return;
3041
65655d4a 3042 intel_crtc->dpms_mode = mode;
debcaddc 3043
e70236a8 3044 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3045
3046 if (!dev->primary->master)
3047 return;
3048
3049 master_priv = dev->primary->master->driver_priv;
3050 if (!master_priv->sarea_priv)
3051 return;
3052
3053 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3054
3055 switch (pipe) {
3056 case 0:
3057 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3058 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3059 break;
3060 case 1:
3061 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3062 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3063 break;
3064 default:
9db4a9c7 3065 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3066 break;
3067 }
79e53945
JB		 3068}
3069
cdd59983
CW		 3070static void intel_crtc_disable(struct drm_crtc *crtc)
3071{
3072 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3073 struct drm_device *dev = crtc->dev;
ee7b9f93 3074 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3075
3076 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3077 dev_priv->display.off(crtc);
3078
931872fc
CW		 3079 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3080 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3081
3082 if (crtc->fb) {
3083 mutex_lock(&dev->struct_mutex);
1690e1eb 3084 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3085 mutex_unlock(&dev->struct_mutex);
3086 }
3087}
3088
7e7d76c3
JB		 3089/* Prepare for a mode set.
3090 *
3091 * Note we could be a lot smarter here. We need to figure out which outputs
3092 * will be enabled, which disabled (in short, how the config will changes)
3093 * and perform the minimum necessary steps to accomplish that, e.g. updating
3094 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3095 * panel fitting is in the proper state, etc.
3096 */
3097static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3098{
7e7d76c3 3099 i9xx_crtc_disable(crtc);
79e53945
JB		 3100}
3101
7e7d76c3 3102static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3103{
7e7d76c3 3104 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3105}
3106
3107static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3108{
7e7d76c3 3109 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3110}
3111
3112static void ironlake_crtc_commit(struct drm_crtc *crtc)
3113{
7e7d76c3 3114 ironlake_crtc_enable(crtc);
79e53945
JB		 3115}
3116
0206e353 3117void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3118{
3119 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3120 /* lvds has its own version of prepare see intel_lvds_prepare */
3121 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3122}
3123
0206e353 3124void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3125{
3126 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3127 struct drm_device *dev = encoder->dev;
3128 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3129 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3130
79e53945
JB		 3131 /* lvds has its own version of commit see intel_lvds_commit */
3132 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3133
3134 if (HAS_PCH_CPT(dev))
3135 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3136}
3137
ea5b213a
CW		 3138void intel_encoder_destroy(struct drm_encoder *encoder)
3139{
4ef69c7a 3140 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3141
ea5b213a
CW		 3142 drm_encoder_cleanup(encoder);
3143 kfree(intel_encoder);
3144}
3145
79e53945
JB		 3146static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3147 struct drm_display_mode *mode,
3148 struct drm_display_mode *adjusted_mode)
3149{
2c07245f 3150 struct drm_device *dev = crtc->dev;
89749350 3151
bad720ff 3152 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3153 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3154 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3155 return false;
2c07245f 3156 }
89749350 3157
f9bef081
DV		 3158 /* All interlaced capable intel hw wants timings in frames. Note though
3159 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3160 * timings, so we need to be careful not to clobber these.*/
3161 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3162 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3163
79e53945
JB		 3164 return true;
3165}
3166
25eb05fc
JB		 3167static int valleyview_get_display_clock_speed(struct drm_device *dev)
3168{
3169 return 400000; /* FIXME */
3170}
3171
e70236a8
JB		 3172static int i945_get_display_clock_speed(struct drm_device *dev)
3173{
3174 return 400000;
3175}
79e53945 3176
e70236a8 3177static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3178{
e70236a8
JB		 3179 return 333000;
3180}
79e53945 3181
e70236a8
JB		 3182static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3183{
3184 return 200000;
3185}
79e53945 3186
e70236a8
JB		 3187static int i915gm_get_display_clock_speed(struct drm_device *dev)
3188{
3189 u16 gcfgc = 0;
79e53945 3190
e70236a8
JB		 3191 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3192
3193 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3194 return 133000;
3195 else {
3196 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3197 case GC_DISPLAY_CLOCK_333_MHZ:
3198 return 333000;
3199 default:
3200 case GC_DISPLAY_CLOCK_190_200_MHZ:
3201 return 190000;
79e53945 3202 }
e70236a8
JB		 3203 }
3204}
3205
3206static int i865_get_display_clock_speed(struct drm_device *dev)
3207{
3208 return 266000;
3209}
3210
3211static int i855_get_display_clock_speed(struct drm_device *dev)
3212{
3213 u16 hpllcc = 0;
3214 /* Assume that the hardware is in the high speed state. This
3215 * should be the default.
3216 */
3217 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3218 case GC_CLOCK_133_200:
3219 case GC_CLOCK_100_200:
3220 return 200000;
3221 case GC_CLOCK_166_250:
3222 return 250000;
3223 case GC_CLOCK_100_133:
79e53945 3224 return 133000;
e70236a8 3225 }
79e53945 3226
e70236a8
JB		 3227 /* Shouldn't happen */
3228 return 0;
3229}
79e53945 3230
e70236a8
JB		 3231static int i830_get_display_clock_speed(struct drm_device *dev)
3232{
3233 return 133000;
79e53945
JB		 3234}
3235
2c07245f
ZW		 3236struct fdi_m_n {
3237 u32 tu;
3238 u32 gmch_m;
3239 u32 gmch_n;
3240 u32 link_m;
3241 u32 link_n;
3242};
3243
3244static void
3245fdi_reduce_ratio(u32 *num, u32 *den)
3246{
3247 while (*num > 0xffffff || *den > 0xffffff) {
3248 *num >>= 1;
3249 *den >>= 1;
3250 }
3251}
3252
2c07245f 3253static void
f2b115e6
AJ		 3254ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3255 int link_clock, struct fdi_m_n *m_n)
2c07245f 3256{
2c07245f
ZW		 3257 m_n->tu = 64; /* default size */
3258
22ed1113
CW		 3259 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3260 m_n->gmch_m = bits_per_pixel * pixel_clock;
3261 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3262 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3263
22ed1113
CW		 3264 m_n->link_m = pixel_clock;
3265 m_n->link_n = link_clock;
2c07245f
ZW		 3266 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3267}
3268
a7615030
CW		 3269static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3270{
72bbe58c
KP		 3271 if (i915_panel_use_ssc >= 0)
3272 return i915_panel_use_ssc != 0;
3273 return dev_priv->lvds_use_ssc
435793df 3274 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3275}
3276
5a354204
JB		 3277/**
3278 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3279 * @crtc: CRTC structure
3b5c78a3 3280 * @mode: requested mode
5a354204
JB		 3281 *
3282 * A pipe may be connected to one or more outputs. Based on the depth of the
3283 * attached framebuffer, choose a good color depth to use on the pipe.
3284 *
3285 * If possible, match the pipe depth to the fb depth. In some cases, this
3286 * isn't ideal, because the connected output supports a lesser or restricted
3287 * set of depths. Resolve that here:
3288 * LVDS typically supports only 6bpc, so clamp down in that case
3289 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3290 * Displays may support a restricted set as well, check EDID and clamp as
3291 * appropriate.
3b5c78a3 3292 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3293 *
3294 * RETURNS:
3295 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3296 * true if they don't match).
3297 */
3298static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3299 unsigned int *pipe_bpp,
3300 struct drm_display_mode *mode)
5a354204
JB		 3301{
3302 struct drm_device *dev = crtc->dev;
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 struct drm_encoder *encoder;
3305 struct drm_connector *connector;
3306 unsigned int display_bpc = UINT_MAX, bpc;
3307
3308 /* Walk the encoders & connectors on this crtc, get min bpc */
3309 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3310 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3311
3312 if (encoder->crtc != crtc)
3313 continue;
3314
3315 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3316 unsigned int lvds_bpc;
3317
3318 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3319 LVDS_A3_POWER_UP)
3320 lvds_bpc = 8;
3321 else
3322 lvds_bpc = 6;
3323
3324 if (lvds_bpc < display_bpc) {
82820490 3325 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3326 display_bpc = lvds_bpc;
3327 }
3328 continue;
3329 }
3330
3331 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3332 /* Use VBT settings if we have an eDP panel */
3333 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3334
3335 if (edp_bpc < display_bpc) {
82820490 3336 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3337 display_bpc = edp_bpc;
3338 }
3339 continue;
3340 }
3341
3342 /* Not one of the known troublemakers, check the EDID */
3343 list_for_each_entry(connector, &dev->mode_config.connector_list,
3344 head) {
3345 if (connector->encoder != encoder)
3346 continue;
3347
62ac41a6
JB		 3348 /* Don't use an invalid EDID bpc value */
3349 if (connector->display_info.bpc &&
3350 connector->display_info.bpc < display_bpc) {
82820490 3351 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3352 display_bpc = connector->display_info.bpc;
3353 }
3354 }
3355
3356 /*
3357 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3358 * through, clamp it down. (Note: >12bpc will be caught below.)
3359 */
3360 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3361 if (display_bpc > 8 && display_bpc < 12) {
82820490 3362 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3363 display_bpc = 12;
3364 } else {
82820490 3365 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3366 display_bpc = 8;
3367 }
3368 }
3369 }
3370
3b5c78a3
AJ		 3371 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3372 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3373 display_bpc = 6;
3374 }
3375
5a354204
JB		 3376 /*
3377 * We could just drive the pipe at the highest bpc all the time and
3378 * enable dithering as needed, but that costs bandwidth. So choose
3379 * the minimum value that expresses the full color range of the fb but
3380 * also stays within the max display bpc discovered above.
3381 */
3382
3383 switch (crtc->fb->depth) {
3384 case 8:
3385 bpc = 8; /* since we go through a colormap */
3386 break;
3387 case 15:
3388 case 16:
3389 bpc = 6; /* min is 18bpp */
3390 break;
3391 case 24:
578393cd 3392 bpc = 8;
5a354204
JB		 3393 break;
3394 case 30:
578393cd 3395 bpc = 10;
5a354204
JB		 3396 break;
3397 case 48:
578393cd 3398 bpc = 12;
5a354204
JB		 3399 break;
3400 default:
3401 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3402 bpc = min((unsigned int)8, display_bpc);
3403 break;
3404 }
3405
578393cd
KP		 3406 display_bpc = min(display_bpc, bpc);
3407
82820490
AJ		 3408 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3409 bpc, display_bpc);
5a354204 3410
578393cd 3411 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3412
3413 return display_bpc != bpc;
3414}
3415
c65d77d8
JB		 3416static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3417{
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 int refclk;
3421
3422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3423 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3424 refclk = dev_priv->lvds_ssc_freq * 1000;
3425 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3426 refclk / 1000);
3427 } else if (!IS_GEN2(dev)) {
3428 refclk = 96000;
3429 } else {
3430 refclk = 48000;
3431 }
3432
3433 return refclk;
3434}
3435
3436static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3437 intel_clock_t *clock)
3438{
3439 /* SDVO TV has fixed PLL values depend on its clock range,
3440 this mirrors vbios setting. */
3441 if (adjusted_mode->clock >= 100000
3442 && adjusted_mode->clock < 140500) {
3443 clock->p1 = 2;
3444 clock->p2 = 10;
3445 clock->n = 3;
3446 clock->m1 = 16;
3447 clock->m2 = 8;
3448 } else if (adjusted_mode->clock >= 140500
3449 && adjusted_mode->clock <= 200000) {
3450 clock->p1 = 1;
3451 clock->p2 = 10;
3452 clock->n = 6;
3453 clock->m1 = 12;
3454 clock->m2 = 8;
3455 }
3456}
3457
a7516a05
JB		 3458static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3459 intel_clock_t *clock,
3460 intel_clock_t *reduced_clock)
3461{
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 int pipe = intel_crtc->pipe;
3466 u32 fp, fp2 = 0;
3467
3468 if (IS_PINEVIEW(dev)) {
3469 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3470 if (reduced_clock)
3471 fp2 = (1 << reduced_clock->n) << 16 |
3472 reduced_clock->m1 << 8 | reduced_clock->m2;
3473 } else {
3474 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3475 if (reduced_clock)
3476 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3477 reduced_clock->m2;
3478 }
3479
3480 I915_WRITE(FP0(pipe), fp);
3481
3482 intel_crtc->lowfreq_avail = false;
3483 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3484 reduced_clock && i915_powersave) {
3485 I915_WRITE(FP1(pipe), fp2);
3486 intel_crtc->lowfreq_avail = true;
3487 } else {
3488 I915_WRITE(FP1(pipe), fp);
3489 }
3490}
3491
93e537a1
DV		 3492static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3493 struct drm_display_mode *adjusted_mode)
3494{
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 int pipe = intel_crtc->pipe;
284d5df5 3499 u32 temp;
93e537a1
DV		 3500
3501 temp = I915_READ(LVDS);
3502 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3503 if (pipe == 1) {
3504 temp |= LVDS_PIPEB_SELECT;
3505 } else {
3506 temp &= ~LVDS_PIPEB_SELECT;
3507 }
3508 /* set the corresponsding LVDS_BORDER bit */
3509 temp |= dev_priv->lvds_border_bits;
3510 /* Set the B0-B3 data pairs corresponding to whether we're going to
3511 * set the DPLLs for dual-channel mode or not.
3512 */
3513 if (clock->p2 == 7)
3514 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3515 else
3516 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3517
3518 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3519 * appropriately here, but we need to look more thoroughly into how
3520 * panels behave in the two modes.
3521 */
3522 /* set the dithering flag on LVDS as needed */
3523 if (INTEL_INFO(dev)->gen >= 4) {
3524 if (dev_priv->lvds_dither)
3525 temp |= LVDS_ENABLE_DITHER;
3526 else
3527 temp &= ~LVDS_ENABLE_DITHER;
3528 }
284d5df5 3529 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3530 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3531 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3532 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3533 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3534 I915_WRITE(LVDS, temp);
3535}
3536
eb1cbe48
DV		 3537static void i9xx_update_pll(struct drm_crtc *crtc,
3538 struct drm_display_mode *mode,
3539 struct drm_display_mode *adjusted_mode,
3540 intel_clock_t *clock, intel_clock_t *reduced_clock,
3541 int num_connectors)
3542{
3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 int pipe = intel_crtc->pipe;
3547 u32 dpll;
3548 bool is_sdvo;
3549
3550 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3551 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3552
3553 dpll = DPLL_VGA_MODE_DIS;
3554
3555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3556 dpll |= DPLLB_MODE_LVDS;
3557 else
3558 dpll |= DPLLB_MODE_DAC_SERIAL;
3559 if (is_sdvo) {
3560 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3561 if (pixel_multiplier > 1) {
3562 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3563 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3564 }
3565 dpll |= DPLL_DVO_HIGH_SPEED;
3566 }
3567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3568 dpll |= DPLL_DVO_HIGH_SPEED;
3569
3570 /* compute bitmask from p1 value */
3571 if (IS_PINEVIEW(dev))
3572 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3573 else {
3574 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3575 if (IS_G4X(dev) && reduced_clock)
3576 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3577 }
3578 switch (clock->p2) {
3579 case 5:
3580 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3581 break;
3582 case 7:
3583 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3584 break;
3585 case 10:
3586 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3587 break;
3588 case 14:
3589 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3590 break;
3591 }
3592 if (INTEL_INFO(dev)->gen >= 4)
3593 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3594
3595 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3596 dpll |= PLL_REF_INPUT_TVCLKINBC;
3597 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3598 /* XXX: just matching BIOS for now */
3599 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3600 dpll |= 3;
3601 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3602 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3604 else
3605 dpll |= PLL_REF_INPUT_DREFCLK;
3606
3607 dpll |= DPLL_VCO_ENABLE;
3608 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3609 POSTING_READ(DPLL(pipe));
3610 udelay(150);
3611
3612 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3613 * This is an exception to the general rule that mode_set doesn't turn
3614 * things on.
3615 */
3616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3617 intel_update_lvds(crtc, clock, adjusted_mode);
3618
3619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3620 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3621
3622 I915_WRITE(DPLL(pipe), dpll);
3623
3624 /* Wait for the clocks to stabilize. */
3625 POSTING_READ(DPLL(pipe));
3626 udelay(150);
3627
3628 if (INTEL_INFO(dev)->gen >= 4) {
3629 u32 temp = 0;
3630 if (is_sdvo) {
3631 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3632 if (temp > 1)
3633 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3634 else
3635 temp = 0;
3636 }
3637 I915_WRITE(DPLL_MD(pipe), temp);
3638 } else {
3639 /* The pixel multiplier can only be updated once the
3640 * DPLL is enabled and the clocks are stable.
3641 *
3642 * So write it again.
3643 */
3644 I915_WRITE(DPLL(pipe), dpll);
3645 }
3646}
3647
3648static void i8xx_update_pll(struct drm_crtc *crtc,
3649 struct drm_display_mode *adjusted_mode,
3650 intel_clock_t *clock,
3651 int num_connectors)
3652{
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 int pipe = intel_crtc->pipe;
3657 u32 dpll;
3658
3659 dpll = DPLL_VGA_MODE_DIS;
3660
3661 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3662 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3663 } else {
3664 if (clock->p1 == 2)
3665 dpll |= PLL_P1_DIVIDE_BY_TWO;
3666 else
3667 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3668 if (clock->p2 == 4)
3669 dpll |= PLL_P2_DIVIDE_BY_4;
3670 }
3671
3672 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3673 /* XXX: just matching BIOS for now */
3674 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3675 dpll |= 3;
3676 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3677 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3678 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3679 else
3680 dpll |= PLL_REF_INPUT_DREFCLK;
3681
3682 dpll |= DPLL_VCO_ENABLE;
3683 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3684 POSTING_READ(DPLL(pipe));
3685 udelay(150);
3686
3687 I915_WRITE(DPLL(pipe), dpll);
3688
3689 /* Wait for the clocks to stabilize. */
3690 POSTING_READ(DPLL(pipe));
3691 udelay(150);
3692
3693 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3694 * This is an exception to the general rule that mode_set doesn't turn
3695 * things on.
3696 */
3697 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3698 intel_update_lvds(crtc, clock, adjusted_mode);
3699
3700 /* The pixel multiplier can only be updated once the
3701 * DPLL is enabled and the clocks are stable.
3702 *
3703 * So write it again.
3704 */
3705 I915_WRITE(DPLL(pipe), dpll);
3706}
3707
f564048e
EA		 3708static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3709 struct drm_display_mode *mode,
3710 struct drm_display_mode *adjusted_mode,
3711 int x, int y,
3712 struct drm_framebuffer *old_fb)
79e53945
JB		 3713{
3714 struct drm_device *dev = crtc->dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717 int pipe = intel_crtc->pipe;
80824003 3718 int plane = intel_crtc->plane;
c751ce4f 3719 int refclk, num_connectors = 0;
652c393a 3720 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3721 u32 dspcntr, pipeconf, vsyncshift;
3722 bool ok, has_reduced_clock = false, is_sdvo = false;
3723 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3724 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3725 struct intel_encoder *encoder;
d4906093 3726 const intel_limit_t *limit;
5c3b82e2 3727 int ret;
79e53945 3728
5eddb70b
CW		 3729 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3730 if (encoder->base.crtc != crtc)
79e53945
JB		 3731 continue;
3732
5eddb70b 3733 switch (encoder->type) {
79e53945
JB		 3734 case INTEL_OUTPUT_LVDS:
3735 is_lvds = true;
3736 break;
3737 case INTEL_OUTPUT_SDVO:
7d57382e 3738 case INTEL_OUTPUT_HDMI:
79e53945 3739 is_sdvo = true;
5eddb70b 3740 if (encoder->needs_tv_clock)
e2f0ba97 3741 is_tv = true;
79e53945 3742 break;
79e53945
JB		 3743 case INTEL_OUTPUT_TVOUT:
3744 is_tv = true;
3745 break;
a4fc5ed6
KP		 3746 case INTEL_OUTPUT_DISPLAYPORT:
3747 is_dp = true;
3748 break;
79e53945 3749 }
43565a06 3750
c751ce4f 3751 num_connectors++;
79e53945
JB		 3752 }
3753
c65d77d8 3754 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3755
d4906093
ML		 3756 /*
3757 * Returns a set of divisors for the desired target clock with the given
3758 * refclk, or FALSE. The returned values represent the clock equation:
3759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3760 */
1b894b59 3761 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3762 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3763 &clock);
79e53945
JB		 3764 if (!ok) {
3765 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3766 return -EINVAL;
79e53945
JB		 3767 }
3768
cda4b7d3 3769 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3770 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3771
ddc9003c 3772 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3773 /*
3774 * Ensure we match the reduced clock's P to the target clock.
3775 * If the clocks don't match, we can't switch the display clock
3776 * by using the FP0/FP1. In such case we will disable the LVDS
3777 * downclock feature.
3778 */
ddc9003c 3779 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 3780 dev_priv->lvds_downclock,
3781 refclk,
cec2f356 3782 &clock,
5eddb70b 3783 &reduced_clock);
7026d4ac
ZW		 3784 }
3785
c65d77d8
JB		 3786 if (is_sdvo && is_tv)
3787 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 3788
a7516a05
JB		 3789 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3790 &reduced_clock : NULL);
79e53945 3791
eb1cbe48
DV		 3792 if (IS_GEN2(dev))
3793 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 3794 else
eb1cbe48
DV		 3795 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3796 has_reduced_clock ? &reduced_clock : NULL,
3797 num_connectors);
79e53945
JB		 3798
3799 /* setup pipeconf */
5eddb70b 3800 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 3801
3802 /* Set up the display plane register */
3803 dspcntr = DISPPLANE_GAMMA_ENABLE;
3804
929c77fb
EA		 3805 if (pipe == 0)
3806 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3807 else
3808 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 3809
a6c45cf0 3810 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 3811 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3812 * core speed.
3813 *
3814 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3815 * pipe == 0 check?
3816 */
e70236a8
JB		 3817 if (mode->clock >
3818 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3819 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3820 else
5eddb70b 3821 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 3822 }
3823
3b5c78a3
AJ		 3824 /* default to 8bpc */
3825 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3826 if (is_dp) {
3827 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3828 pipeconf |= PIPECONF_BPP_6 |
3829 PIPECONF_DITHER_EN |
3830 PIPECONF_DITHER_TYPE_SP;
3831 }
3832 }
3833
28c97730 3834 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 3835 drm_mode_debug_printmodeline(mode);
3836
a7516a05
JB		 3837 if (HAS_PIPE_CXSR(dev)) {
3838 if (intel_crtc->lowfreq_avail) {
28c97730 3839 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 3840 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 3841 } else {
28c97730 3842 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 3843 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3844 }
3845 }
3846
617cf884 3847 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 3848 if (!IS_GEN2(dev) &&
3849 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 3850 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3851 /* the chip adds 2 halflines automatically */
734b4157 3852 adjusted_mode->crtc_vtotal -= 1;
734b4157 3853 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 3854 vsyncshift = adjusted_mode->crtc_hsync_start
3855 - adjusted_mode->crtc_htotal/2;
3856 } else {
617cf884 3857 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 3858 vsyncshift = 0;
3859 }
3860
3861 if (!IS_GEN3(dev))
3862 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 3863
5eddb70b
CW		 3864 I915_WRITE(HTOTAL(pipe),
3865 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 3866 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 3867 I915_WRITE(HBLANK(pipe),
3868 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 3869 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 3870 I915_WRITE(HSYNC(pipe),
3871 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 3872 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 3873
3874 I915_WRITE(VTOTAL(pipe),
3875 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 3876 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 3877 I915_WRITE(VBLANK(pipe),
3878 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 3879 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 3880 I915_WRITE(VSYNC(pipe),
3881 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 3882 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 3883
3884 /* pipesrc and dspsize control the size that is scaled from,
3885 * which should always be the user's requested size.
79e53945 3886 */
929c77fb
EA		 3887 I915_WRITE(DSPSIZE(plane),
3888 ((mode->vdisplay - 1) << 16) |
3889 (mode->hdisplay - 1));
3890 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 3891 I915_WRITE(PIPESRC(pipe),
3892 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 3893
f564048e
EA		 3894 I915_WRITE(PIPECONF(pipe), pipeconf);
3895 POSTING_READ(PIPECONF(pipe));
929c77fb 3896 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 3897
3898 intel_wait_for_vblank(dev, pipe);
3899
f564048e
EA		 3900 I915_WRITE(DSPCNTR(plane), dspcntr);
3901 POSTING_READ(DSPCNTR(plane));
3902
3903 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3904
3905 intel_update_watermarks(dev);
3906
f564048e
EA		 3907 return ret;
3908}
3909
9fb526db
KP		 3910/*
3911 * Initialize reference clocks when the driver loads
3912 */
3913void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 3914{
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 3917 struct intel_encoder *encoder;
13d83a67
JB		 3918 u32 temp;
3919 bool has_lvds = false;
199e5d79
KP		 3920 bool has_cpu_edp = false;
3921 bool has_pch_edp = false;
3922 bool has_panel = false;
99eb6a01
KP		 3923 bool has_ck505 = false;
3924 bool can_ssc = false;
13d83a67
JB		 3925
3926 /* We need to take the global config into account */
199e5d79
KP		 3927 list_for_each_entry(encoder, &mode_config->encoder_list,
3928 base.head) {
3929 switch (encoder->type) {
3930 case INTEL_OUTPUT_LVDS:
3931 has_panel = true;
3932 has_lvds = true;
3933 break;
3934 case INTEL_OUTPUT_EDP:
3935 has_panel = true;
3936 if (intel_encoder_is_pch_edp(&encoder->base))
3937 has_pch_edp = true;
3938 else
3939 has_cpu_edp = true;
3940 break;
13d83a67
JB		 3941 }
3942 }
3943
99eb6a01
KP		 3944 if (HAS_PCH_IBX(dev)) {
3945 has_ck505 = dev_priv->display_clock_mode;
3946 can_ssc = has_ck505;
3947 } else {
3948 has_ck505 = false;
3949 can_ssc = true;
3950 }
3951
3952 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3953 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3954 has_ck505);
13d83a67
JB		 3955
3956 /* Ironlake: try to setup display ref clock before DPLL
3957 * enabling. This is only under driver's control after
3958 * PCH B stepping, previous chipset stepping should be
3959 * ignoring this setting.
3960 */
3961 temp = I915_READ(PCH_DREF_CONTROL);
3962 /* Always enable nonspread source */
3963 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 3964
99eb6a01
KP		 3965 if (has_ck505)
3966 temp |= DREF_NONSPREAD_CK505_ENABLE;
3967 else
3968 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 3969
199e5d79
KP		 3970 if (has_panel) {
3971 temp &= ~DREF_SSC_SOURCE_MASK;
3972 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 3973
199e5d79 3974 /* SSC must be turned on before enabling the CPU output */
99eb6a01 3975 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 3976 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 3977 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 3978 } else
3979 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 3980
3981 /* Get SSC going before enabling the outputs */
3982 I915_WRITE(PCH_DREF_CONTROL, temp);
3983 POSTING_READ(PCH_DREF_CONTROL);
3984 udelay(200);
3985
13d83a67
JB		 3986 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3987
3988 /* Enable CPU source on CPU attached eDP */
199e5d79 3989 if (has_cpu_edp) {
99eb6a01 3990 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 3991 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 3992 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 3993 }
13d83a67
JB		 3994 else
3995 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 3996 } else
3997 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3998
3999 I915_WRITE(PCH_DREF_CONTROL, temp);
4000 POSTING_READ(PCH_DREF_CONTROL);
4001 udelay(200);
4002 } else {
4003 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4004
4005 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4006
4007 /* Turn off CPU output */
4008 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4009
4010 I915_WRITE(PCH_DREF_CONTROL, temp);
4011 POSTING_READ(PCH_DREF_CONTROL);
4012 udelay(200);
4013
4014 /* Turn off the SSC source */
4015 temp &= ~DREF_SSC_SOURCE_MASK;
4016 temp |= DREF_SSC_SOURCE_DISABLE;
4017
4018 /* Turn off SSC1 */
4019 temp &= ~ DREF_SSC1_ENABLE;
4020
13d83a67
JB		 4021 I915_WRITE(PCH_DREF_CONTROL, temp);
4022 POSTING_READ(PCH_DREF_CONTROL);
4023 udelay(200);
4024 }
4025}
4026
d9d444cb
JB		 4027static int ironlake_get_refclk(struct drm_crtc *crtc)
4028{
4029 struct drm_device *dev = crtc->dev;
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_encoder *encoder;
4032 struct drm_mode_config *mode_config = &dev->mode_config;
4033 struct intel_encoder *edp_encoder = NULL;
4034 int num_connectors = 0;
4035 bool is_lvds = false;
4036
4037 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4038 if (encoder->base.crtc != crtc)
4039 continue;
4040
4041 switch (encoder->type) {
4042 case INTEL_OUTPUT_LVDS:
4043 is_lvds = true;
4044 break;
4045 case INTEL_OUTPUT_EDP:
4046 edp_encoder = encoder;
4047 break;
4048 }
4049 num_connectors++;
4050 }
4051
4052 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4053 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4054 dev_priv->lvds_ssc_freq);
4055 return dev_priv->lvds_ssc_freq * 1000;
4056 }
4057
4058 return 120000;
4059}
4060
f564048e
EA		 4061static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4062 struct drm_display_mode *mode,
4063 struct drm_display_mode *adjusted_mode,
4064 int x, int y,
4065 struct drm_framebuffer *old_fb)
79e53945
JB		 4066{
4067 struct drm_device *dev = crtc->dev;
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4070 int pipe = intel_crtc->pipe;
80824003 4071 int plane = intel_crtc->plane;
c751ce4f 4072 int refclk, num_connectors = 0;
652c393a 4073 intel_clock_t clock, reduced_clock;
5eddb70b 4074 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4075 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4076 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4077 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4078 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4079 const intel_limit_t *limit;
5c3b82e2 4080 int ret;
2c07245f 4081 struct fdi_m_n m_n = {0};
fae14981 4082 u32 temp;
5a354204
JB		 4083 int target_clock, pixel_multiplier, lane, link_bw, factor;
4084 unsigned int pipe_bpp;
4085 bool dither;
e3aef172 4086 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4087
5eddb70b
CW		 4088 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4089 if (encoder->base.crtc != crtc)
79e53945
JB		 4090 continue;
4091
5eddb70b 4092 switch (encoder->type) {
79e53945
JB		 4093 case INTEL_OUTPUT_LVDS:
4094 is_lvds = true;
4095 break;
4096 case INTEL_OUTPUT_SDVO:
7d57382e 4097 case INTEL_OUTPUT_HDMI:
79e53945 4098 is_sdvo = true;
5eddb70b 4099 if (encoder->needs_tv_clock)
e2f0ba97 4100 is_tv = true;
79e53945 4101 break;
79e53945
JB		 4102 case INTEL_OUTPUT_TVOUT:
4103 is_tv = true;
4104 break;
4105 case INTEL_OUTPUT_ANALOG:
4106 is_crt = true;
4107 break;
a4fc5ed6
KP		 4108 case INTEL_OUTPUT_DISPLAYPORT:
4109 is_dp = true;
4110 break;
32f9d658 4111 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4112 is_dp = true;
4113 if (intel_encoder_is_pch_edp(&encoder->base))
4114 is_pch_edp = true;
4115 else
4116 is_cpu_edp = true;
4117 edp_encoder = encoder;
32f9d658 4118 break;
79e53945 4119 }
43565a06 4120
c751ce4f 4121 num_connectors++;
79e53945
JB		 4122 }
4123
d9d444cb 4124 refclk = ironlake_get_refclk(crtc);
79e53945 4125
d4906093
ML		 4126 /*
4127 * Returns a set of divisors for the desired target clock with the given
4128 * refclk, or FALSE. The returned values represent the clock equation:
4129 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4130 */
1b894b59 4131 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4132 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4133 &clock);
79e53945
JB		 4134 if (!ok) {
4135 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4136 return -EINVAL;
79e53945
JB		 4137 }
4138
cda4b7d3 4139 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4140 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4141
ddc9003c 4142 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4143 /*
4144 * Ensure we match the reduced clock's P to the target clock.
4145 * If the clocks don't match, we can't switch the display clock
4146 * by using the FP0/FP1. In such case we will disable the LVDS
4147 * downclock feature.
4148 */
ddc9003c 4149 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4150 dev_priv->lvds_downclock,
4151 refclk,
cec2f356 4152 &clock,
5eddb70b 4153 &reduced_clock);
652c393a 4154 }
7026d4ac
ZW		 4155 /* SDVO TV has fixed PLL values depend on its clock range,
4156 this mirrors vbios setting. */
4157 if (is_sdvo && is_tv) {
4158 if (adjusted_mode->clock >= 100000
5eddb70b 4159 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4160 clock.p1 = 2;
4161 clock.p2 = 10;
4162 clock.n = 3;
4163 clock.m1 = 16;
4164 clock.m2 = 8;
4165 } else if (adjusted_mode->clock >= 140500
5eddb70b 4166 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4167 clock.p1 = 1;
4168 clock.p2 = 10;
4169 clock.n = 6;
4170 clock.m1 = 12;
4171 clock.m2 = 8;
4172 }
4173 }
4174
2c07245f 4175 /* FDI link */
8febb297
EA		 4176 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4177 lane = 0;
4178 /* CPU eDP doesn't require FDI link, so just set DP M/N
4179 according to current link config */
e3aef172 4180 if (is_cpu_edp) {
8febb297 4181 target_clock = mode->clock;
e3aef172 4182 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4183 } else {
4184 /* [e]DP over FDI requires target mode clock
4185 instead of link clock */
e3aef172 4186 if (is_dp)
5eb08b69 4187 target_clock = mode->clock;
8febb297
EA		 4188 else
4189 target_clock = adjusted_mode->clock;
4190
4191 /* FDI is a binary signal running at ~2.7GHz, encoding
4192 * each output octet as 10 bits. The actual frequency
4193 * is stored as a divider into a 100MHz clock, and the
4194 * mode pixel clock is stored in units of 1KHz.
4195 * Hence the bw of each lane in terms of the mode signal
4196 * is:
4197 */
4198 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4199 }
58a27471 4200
8febb297
EA		 4201 /* determine panel color depth */
4202 temp = I915_READ(PIPECONF(pipe));
4203 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4204 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4205 switch (pipe_bpp) {
4206 case 18:
4207 temp |= PIPE_6BPC;
8febb297 4208 break;
5a354204
JB		 4209 case 24:
4210 temp |= PIPE_8BPC;
8febb297 4211 break;
5a354204
JB		 4212 case 30:
4213 temp |= PIPE_10BPC;
8febb297 4214 break;
5a354204
JB		 4215 case 36:
4216 temp |= PIPE_12BPC;
8febb297
EA		 4217 break;
4218 default:
62ac41a6
JB		 4219 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4220 pipe_bpp);
5a354204
JB		 4221 temp |= PIPE_8BPC;
4222 pipe_bpp = 24;
4223 break;
8febb297 4224 }
77ffb597 4225
5a354204
JB		 4226 intel_crtc->bpp = pipe_bpp;
4227 I915_WRITE(PIPECONF(pipe), temp);
4228
8febb297
EA		 4229 if (!lane) {
4230 /*
4231 * Account for spread spectrum to avoid
4232 * oversubscribing the link. Max center spread
4233 * is 2.5%; use 5% for safety's sake.
4234 */
5a354204 4235 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4236 lane = bps / (link_bw * 8) + 1;
5eb08b69 4237 }
2c07245f 4238
8febb297
EA		 4239 intel_crtc->fdi_lanes = lane;
4240
4241 if (pixel_multiplier > 1)
4242 link_bw *= pixel_multiplier;
5a354204
JB		 4243 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4244 &m_n);
8febb297 4245
a07d6787
EA		 4246 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4247 if (has_reduced_clock)
4248 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4249 reduced_clock.m2;
79e53945 4250
c1858123 4251 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4252 factor = 21;
4253 if (is_lvds) {
4254 if ((intel_panel_use_ssc(dev_priv) &&
4255 dev_priv->lvds_ssc_freq == 100) ||
4256 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4257 factor = 25;
4258 } else if (is_sdvo && is_tv)
4259 factor = 20;
c1858123 4260
cb0e0931 4261 if (clock.m < factor * clock.n)
8febb297 4262 fp |= FP_CB_TUNE;
2c07245f 4263
5eddb70b 4264 dpll = 0;
2c07245f 4265
a07d6787
EA		 4266 if (is_lvds)
4267 dpll |= DPLLB_MODE_LVDS;
4268 else
4269 dpll |= DPLLB_MODE_DAC_SERIAL;
4270 if (is_sdvo) {
4271 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4272 if (pixel_multiplier > 1) {
4273 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4274 }
a07d6787
EA		 4275 dpll |= DPLL_DVO_HIGH_SPEED;
4276 }
e3aef172 4277 if (is_dp && !is_cpu_edp)
a07d6787 4278 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4279
a07d6787
EA		 4280 /* compute bitmask from p1 value */
4281 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4282 /* also FPA1 */
4283 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4284
4285 switch (clock.p2) {
4286 case 5:
4287 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4288 break;
4289 case 7:
4290 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4291 break;
4292 case 10:
4293 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4294 break;
4295 case 14:
4296 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4297 break;
79e53945
JB		 4298 }
4299
43565a06
KH		 4300 if (is_sdvo && is_tv)
4301 dpll |= PLL_REF_INPUT_TVCLKINBC;
4302 else if (is_tv)
79e53945 4303 /* XXX: just matching BIOS for now */
43565a06 4304 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4305 dpll |= 3;
a7615030 4306 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4307 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4308 else
4309 dpll |= PLL_REF_INPUT_DREFCLK;
4310
4311 /* setup pipeconf */
5eddb70b 4312 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4313
4314 /* Set up the display plane register */
4315 dspcntr = DISPPLANE_GAMMA_ENABLE;
4316
f7cb34d4 4317 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4318 drm_mode_debug_printmodeline(mode);
4319
ee7b9f93
JB		 4320 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4321 if (!is_cpu_edp) {
4322 struct intel_pch_pll *pll;
4b645f14 4323
ee7b9f93
JB		 4324 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4325 if (pll == NULL) {
4326 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4327 pipe);
4b645f14
JB		 4328 return -EINVAL;
4329 }
ee7b9f93
JB		 4330 } else
4331 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4332
4333 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4334 * This is an exception to the general rule that mode_set doesn't turn
4335 * things on.
4336 */
4337 if (is_lvds) {
fae14981 4338 temp = I915_READ(PCH_LVDS);
5eddb70b 4339 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4340 if (HAS_PCH_CPT(dev)) {
4341 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4342 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4343 } else {
4344 if (pipe == 1)
4345 temp |= LVDS_PIPEB_SELECT;
4346 else
4347 temp &= ~LVDS_PIPEB_SELECT;
4348 }
4b645f14 4349
a3e17eb8 4350 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4351 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4352 /* Set the B0-B3 data pairs corresponding to whether we're going to
4353 * set the DPLLs for dual-channel mode or not.
4354 */
4355 if (clock.p2 == 7)
5eddb70b 4356 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4357 else
5eddb70b 4358 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4359
4360 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4361 * appropriately here, but we need to look more thoroughly into how
4362 * panels behave in the two modes.
4363 */
284d5df5 4364 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4365 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4366 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4367 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4368 temp |= LVDS_VSYNC_POLARITY;
fae14981 4369 I915_WRITE(PCH_LVDS, temp);
79e53945 4370 }
434ed097 4371
8febb297
EA		 4372 pipeconf &= ~PIPECONF_DITHER_EN;
4373 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4374 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4375 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4376 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4377 }
e3aef172 4378 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4379 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4380 } else {
8db9d77b 4381 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4382 I915_WRITE(TRANSDATA_M1(pipe), 0);
4383 I915_WRITE(TRANSDATA_N1(pipe), 0);
4384 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4385 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4386 }
79e53945 4387
ee7b9f93
JB		 4388 if (intel_crtc->pch_pll) {
4389 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4390
32f9d658 4391 /* Wait for the clocks to stabilize. */
ee7b9f93 4392 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4393 udelay(150);
4394
8febb297
EA		 4395 /* The pixel multiplier can only be updated once the
4396 * DPLL is enabled and the clocks are stable.
4397 *
4398 * So write it again.
4399 */
ee7b9f93 4400 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4401 }
79e53945 4402
5eddb70b 4403 intel_crtc->lowfreq_avail = false;
ee7b9f93 4404 if (intel_crtc->pch_pll) {
4b645f14 4405 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4406 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4407 intel_crtc->lowfreq_avail = true;
4408 if (HAS_PIPE_CXSR(dev)) {
4409 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4410 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4411 }
4412 } else {
ee7b9f93 4413 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4414 if (HAS_PIPE_CXSR(dev)) {
4415 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4416 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4417 }
652c393a
JB		 4418 }
4419 }
4420
617cf884 4421 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4422 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4423 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4424 /* the chip adds 2 halflines automatically */
734b4157 4425 adjusted_mode->crtc_vtotal -= 1;
734b4157 4426 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4427 I915_WRITE(VSYNCSHIFT(pipe),
4428 adjusted_mode->crtc_hsync_start
4429 - adjusted_mode->crtc_htotal/2);
4430 } else {
617cf884 4431 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4432 I915_WRITE(VSYNCSHIFT(pipe), 0);
4433 }
734b4157 4434
5eddb70b
CW		 4435 I915_WRITE(HTOTAL(pipe),
4436 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4437 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4438 I915_WRITE(HBLANK(pipe),
4439 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4440 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4441 I915_WRITE(HSYNC(pipe),
4442 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4443 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4444
4445 I915_WRITE(VTOTAL(pipe),
4446 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4447 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4448 I915_WRITE(VBLANK(pipe),
4449 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4450 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4451 I915_WRITE(VSYNC(pipe),
4452 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4453 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4454
8febb297
EA		 4455 /* pipesrc controls the size that is scaled from, which should
4456 * always be the user's requested size.
79e53945 4457 */
5eddb70b
CW		 4458 I915_WRITE(PIPESRC(pipe),
4459 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4460
8febb297
EA		 4461 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4462 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4463 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4464 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4465
e3aef172 4466 if (is_cpu_edp)
8febb297 4467 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4468
5eddb70b
CW		 4469 I915_WRITE(PIPECONF(pipe), pipeconf);
4470 POSTING_READ(PIPECONF(pipe));
79e53945 4471
9d0498a2 4472 intel_wait_for_vblank(dev, pipe);
79e53945 4473
5eddb70b 4474 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4475 POSTING_READ(DSPCNTR(plane));
79e53945 4476
5c3b82e2 4477 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4478
4479 intel_update_watermarks(dev);
4480
1f803ee5 4481 return ret;
79e53945
JB		 4482}
4483
f564048e
EA		 4484static int intel_crtc_mode_set(struct drm_crtc *crtc,
4485 struct drm_display_mode *mode,
4486 struct drm_display_mode *adjusted_mode,
4487 int x, int y,
4488 struct drm_framebuffer *old_fb)
4489{
4490 struct drm_device *dev = crtc->dev;
4491 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4493 int pipe = intel_crtc->pipe;
f564048e
EA		 4494 int ret;
4495
0b701d27 4496 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4497
f564048e
EA		 4498 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4499 x, y, old_fb);
79e53945 4500 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4501
d8e70a25
JB		 4502 if (ret)
4503 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4504 else
4505 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4506
1f803ee5 4507 return ret;
79e53945
JB		 4508}
4509
3a9627f4
WF		 4510static bool intel_eld_uptodate(struct drm_connector *connector,
4511 int reg_eldv, uint32_t bits_eldv,
4512 int reg_elda, uint32_t bits_elda,
4513 int reg_edid)
4514{
4515 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4516 uint8_t *eld = connector->eld;
4517 uint32_t i;
4518
4519 i = I915_READ(reg_eldv);
4520 i &= bits_eldv;
4521
4522 if (!eld[0])
4523 return !i;
4524
4525 if (!i)
4526 return false;
4527
4528 i = I915_READ(reg_elda);
4529 i &= ~bits_elda;
4530 I915_WRITE(reg_elda, i);
4531
4532 for (i = 0; i < eld[2]; i++)
4533 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4534 return false;
4535
4536 return true;
4537}
4538
e0dac65e
WF		 4539static void g4x_write_eld(struct drm_connector *connector,
4540 struct drm_crtc *crtc)
4541{
4542 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4543 uint8_t *eld = connector->eld;
4544 uint32_t eldv;
4545 uint32_t len;
4546 uint32_t i;
4547
4548 i = I915_READ(G4X_AUD_VID_DID);
4549
4550 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4551 eldv = G4X_ELDV_DEVCL_DEVBLC;
4552 else
4553 eldv = G4X_ELDV_DEVCTG;
4554
3a9627f4
WF		 4555 if (intel_eld_uptodate(connector,
4556 G4X_AUD_CNTL_ST, eldv,
4557 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4558 G4X_HDMIW_HDMIEDID))
4559 return;
4560
e0dac65e
WF		 4561 i = I915_READ(G4X_AUD_CNTL_ST);
4562 i &= ~(eldv | G4X_ELD_ADDR);
4563 len = (i >> 9) & 0x1f; /* ELD buffer size */
4564 I915_WRITE(G4X_AUD_CNTL_ST, i);
4565
4566 if (!eld[0])
4567 return;
4568
4569 len = min_t(uint8_t, eld[2], len);
4570 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4571 for (i = 0; i < len; i++)
4572 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4573
4574 i = I915_READ(G4X_AUD_CNTL_ST);
4575 i |= eldv;
4576 I915_WRITE(G4X_AUD_CNTL_ST, i);
4577}
4578
4579static void ironlake_write_eld(struct drm_connector *connector,
4580 struct drm_crtc *crtc)
4581{
4582 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4583 uint8_t *eld = connector->eld;
4584 uint32_t eldv;
4585 uint32_t i;
4586 int len;
4587 int hdmiw_hdmiedid;
b6daa025 4588 int aud_config;
e0dac65e
WF		 4589 int aud_cntl_st;
4590 int aud_cntrl_st2;
4591
b3f33cbf 4592 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4593 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4594 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4595 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4596 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4597 } else {
1202b4c6 4598 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4599 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4600 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4601 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4602 }
4603
4604 i = to_intel_crtc(crtc)->pipe;
4605 hdmiw_hdmiedid += i * 0x100;
4606 aud_cntl_st += i * 0x100;
b6daa025 4607 aud_config += i * 0x100;
e0dac65e
WF		 4608
4609 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4610
4611 i = I915_READ(aud_cntl_st);
4612 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4613 if (!i) {
4614 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4615 /* operate blindly on all ports */
1202b4c6
WF		 4616 eldv = IBX_ELD_VALIDB;
4617 eldv |= IBX_ELD_VALIDB << 4;
4618 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4619 } else {
4620 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4621 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4622 }
4623
3a9627f4
WF		 4624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4625 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4626 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4627 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4628 } else
4629 I915_WRITE(aud_config, 0);
e0dac65e 4630
3a9627f4
WF		 4631 if (intel_eld_uptodate(connector,
4632 aud_cntrl_st2, eldv,
4633 aud_cntl_st, IBX_ELD_ADDRESS,
4634 hdmiw_hdmiedid))
4635 return;
4636
e0dac65e
WF		 4637 i = I915_READ(aud_cntrl_st2);
4638 i &= ~eldv;
4639 I915_WRITE(aud_cntrl_st2, i);
4640
4641 if (!eld[0])
4642 return;
4643
e0dac65e 4644 i = I915_READ(aud_cntl_st);
1202b4c6 4645 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4646 I915_WRITE(aud_cntl_st, i);
4647
4648 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4649 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4650 for (i = 0; i < len; i++)
4651 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4652
4653 i = I915_READ(aud_cntrl_st2);
4654 i |= eldv;
4655 I915_WRITE(aud_cntrl_st2, i);
4656}
4657
4658void intel_write_eld(struct drm_encoder *encoder,
4659 struct drm_display_mode *mode)
4660{
4661 struct drm_crtc *crtc = encoder->crtc;
4662 struct drm_connector *connector;
4663 struct drm_device *dev = encoder->dev;
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 connector = drm_select_eld(encoder, mode);
4667 if (!connector)
4668 return;
4669
4670 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4671 connector->base.id,
4672 drm_get_connector_name(connector),
4673 connector->encoder->base.id,
4674 drm_get_encoder_name(connector->encoder));
4675
4676 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4677
4678 if (dev_priv->display.write_eld)
4679 dev_priv->display.write_eld(connector, crtc);
4680}
4681
79e53945
JB		 4682/** Loads the palette/gamma unit for the CRTC with the prepared values */
4683void intel_crtc_load_lut(struct drm_crtc *crtc)
4684{
4685 struct drm_device *dev = crtc->dev;
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4688 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4689 int i;
4690
4691 /* The clocks have to be on to load the palette. */
aed3f09d 4692 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4693 return;
4694
f2b115e6 4695 /* use legacy palette for Ironlake */
bad720ff 4696 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4697 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4698
79e53945
JB		 4699 for (i = 0; i < 256; i++) {
4700 I915_WRITE(palreg + 4 * i,
4701 (intel_crtc->lut_r[i] << 16) |
4702 (intel_crtc->lut_g[i] << 8) |
4703 intel_crtc->lut_b[i]);
4704 }
4705}
4706
560b85bb
CW		 4707static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4708{
4709 struct drm_device *dev = crtc->dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 bool visible = base != 0;
4713 u32 cntl;
4714
4715 if (intel_crtc->cursor_visible == visible)
4716 return;
4717
9db4a9c7 4718 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4719 if (visible) {
4720 /* On these chipsets we can only modify the base whilst
4721 * the cursor is disabled.
4722 */
9db4a9c7 4723 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4724
4725 cntl &= ~(CURSOR_FORMAT_MASK);
4726 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4727 cntl |= CURSOR_ENABLE |
4728 CURSOR_GAMMA_ENABLE |
4729 CURSOR_FORMAT_ARGB;
4730 } else
4731 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4732 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4733
4734 intel_crtc->cursor_visible = visible;
4735}
4736
4737static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4738{
4739 struct drm_device *dev = crtc->dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4742 int pipe = intel_crtc->pipe;
4743 bool visible = base != 0;
4744
4745 if (intel_crtc->cursor_visible != visible) {
548f245b 4746 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4747 if (base) {
4748 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4749 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4750 cntl |= pipe << 28; /* Connect to correct pipe */
4751 } else {
4752 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4753 cntl |= CURSOR_MODE_DISABLE;
4754 }
9db4a9c7 4755 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4756
4757 intel_crtc->cursor_visible = visible;
4758 }
4759 /* and commit changes on next vblank */
9db4a9c7 4760 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4761}
4762
65a21cd6
JB		 4763static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4764{
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
4769 bool visible = base != 0;
4770
4771 if (intel_crtc->cursor_visible != visible) {
4772 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4773 if (base) {
4774 cntl &= ~CURSOR_MODE;
4775 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4776 } else {
4777 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4778 cntl |= CURSOR_MODE_DISABLE;
4779 }
4780 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4781
4782 intel_crtc->cursor_visible = visible;
4783 }
4784 /* and commit changes on next vblank */
4785 I915_WRITE(CURBASE_IVB(pipe), base);
4786}
4787
cda4b7d3 4788/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 4789static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4790 bool on)
cda4b7d3
CW		 4791{
4792 struct drm_device *dev = crtc->dev;
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4795 int pipe = intel_crtc->pipe;
4796 int x = intel_crtc->cursor_x;
4797 int y = intel_crtc->cursor_y;
560b85bb 4798 u32 base, pos;
cda4b7d3
CW		 4799 bool visible;
4800
4801 pos = 0;
4802
6b383a7f 4803 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 4804 base = intel_crtc->cursor_addr;
4805 if (x > (int) crtc->fb->width)
4806 base = 0;
4807
4808 if (y > (int) crtc->fb->height)
4809 base = 0;
4810 } else
4811 base = 0;
4812
4813 if (x < 0) {
4814 if (x + intel_crtc->cursor_width < 0)
4815 base = 0;
4816
4817 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4818 x = -x;
4819 }
4820 pos |= x << CURSOR_X_SHIFT;
4821
4822 if (y < 0) {
4823 if (y + intel_crtc->cursor_height < 0)
4824 base = 0;
4825
4826 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4827 y = -y;
4828 }
4829 pos |= y << CURSOR_Y_SHIFT;
4830
4831 visible = base != 0;
560b85bb 4832 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 4833 return;
4834
0cd83aa9 4835 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 4836 I915_WRITE(CURPOS_IVB(pipe), pos);
4837 ivb_update_cursor(crtc, base);
4838 } else {
4839 I915_WRITE(CURPOS(pipe), pos);
4840 if (IS_845G(dev) || IS_I865G(dev))
4841 i845_update_cursor(crtc, base);
4842 else
4843 i9xx_update_cursor(crtc, base);
4844 }
cda4b7d3
CW		 4845}
4846
79e53945 4847static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4848 struct drm_file *file,
79e53945
JB		 4849 uint32_t handle,
4850 uint32_t width, uint32_t height)
4851{
4852 struct drm_device *dev = crtc->dev;
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4855 struct drm_i915_gem_object *obj;
cda4b7d3 4856 uint32_t addr;
3f8bc370 4857 int ret;
79e53945 4858
28c97730 4859 DRM_DEBUG_KMS("\n");
79e53945
JB		 4860
4861 /* if we want to turn off the cursor ignore width and height */
4862 if (!handle) {
28c97730 4863 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4864 addr = 0;
05394f39 4865 obj = NULL;
5004417d 4866 mutex_lock(&dev->struct_mutex);
3f8bc370 4867 goto finish;
79e53945
JB		 4868 }
4869
4870 /* Currently we only support 64x64 cursors */
4871 if (width != 64 || height != 64) {
4872 DRM_ERROR("we currently only support 64x64 cursors\n");
4873 return -EINVAL;
4874 }
4875
05394f39 4876 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 4877 if (&obj->base == NULL)
79e53945
JB		 4878 return -ENOENT;
4879
05394f39 4880 if (obj->base.size < width * height * 4) {
79e53945 4881 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 4882 ret = -ENOMEM;
4883 goto fail;
79e53945
JB		 4884 }
4885
71acb5eb 4886 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 4887 mutex_lock(&dev->struct_mutex);
b295d1b6 4888 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 4889 if (obj->tiling_mode) {
4890 DRM_ERROR("cursor cannot be tiled\n");
4891 ret = -EINVAL;
4892 goto fail_locked;
4893 }
4894
2da3b9b9 4895 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 4896 if (ret) {
4897 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 4898 goto fail_locked;
e7b526bb
CW		 4899 }
4900
d9e86c0e
CW		 4901 ret = i915_gem_object_put_fence(obj);
4902 if (ret) {
2da3b9b9 4903 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 4904 goto fail_unpin;
4905 }
4906
05394f39 4907 addr = obj->gtt_offset;
71acb5eb 4908 } else {
6eeefaf3 4909 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 4910 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 4911 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4912 align);
71acb5eb
DA		 4913 if (ret) {
4914 DRM_ERROR("failed to attach phys object\n");
7f9872e0 4915 goto fail_locked;
71acb5eb 4916 }
05394f39 4917 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 4918 }
4919
a6c45cf0 4920 if (IS_GEN2(dev))
14b60391
JB		 4921 I915_WRITE(CURSIZE, (height << 12) | width);
4922
3f8bc370 4923 finish:
3f8bc370 4924 if (intel_crtc->cursor_bo) {
b295d1b6 4925 if (dev_priv->info->cursor_needs_physical) {
05394f39 4926 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 4927 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4928 } else
4929 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 4930 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 4931 }
80824003 4932
7f9872e0 4933 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 4934
4935 intel_crtc->cursor_addr = addr;
05394f39 4936 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 4937 intel_crtc->cursor_width = width;
4938 intel_crtc->cursor_height = height;
4939
6b383a7f 4940 intel_crtc_update_cursor(crtc, true);
3f8bc370 4941
79e53945 4942 return 0;
e7b526bb 4943fail_unpin:
05394f39 4944 i915_gem_object_unpin(obj);
7f9872e0 4945fail_locked:
34b8686e 4946 mutex_unlock(&dev->struct_mutex);
bc9025bd 4947fail:
05394f39 4948 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 4949 return ret;
79e53945
JB		 4950}
4951
4952static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4953{
79e53945 4954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 4955
cda4b7d3
CW		 4956 intel_crtc->cursor_x = x;
4957 intel_crtc->cursor_y = y;
652c393a 4958
6b383a7f 4959 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 4960
4961 return 0;
4962}
4963
4964/** Sets the color ramps on behalf of RandR */
4965void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4966 u16 blue, int regno)
4967{
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969
4970 intel_crtc->lut_r[regno] = red >> 8;
4971 intel_crtc->lut_g[regno] = green >> 8;
4972 intel_crtc->lut_b[regno] = blue >> 8;
4973}
4974
b8c00ac5
DA		 4975void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4976 u16 *blue, int regno)
4977{
4978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4979
4980 *red = intel_crtc->lut_r[regno] << 8;
4981 *green = intel_crtc->lut_g[regno] << 8;
4982 *blue = intel_crtc->lut_b[regno] << 8;
4983}
4984
79e53945 4985static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 4986 u16 *blue, uint32_t start, uint32_t size)
79e53945 4987{
7203425a 4988 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 4989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 4990
7203425a 4991 for (i = start; i < end; i++) {
79e53945
JB		 4992 intel_crtc->lut_r[i] = red[i] >> 8;
4993 intel_crtc->lut_g[i] = green[i] >> 8;
4994 intel_crtc->lut_b[i] = blue[i] >> 8;
4995 }
4996
4997 intel_crtc_load_lut(crtc);
4998}
4999
5000/**
5001 * Get a pipe with a simple mode set on it for doing load-based monitor
5002 * detection.
5003 *
5004 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5005 * its requirements. The pipe will be connected to no other encoders.
79e53945 5006 *
c751ce4f 5007 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5008 * configured for it. In the future, it could choose to temporarily disable
5009 * some outputs to free up a pipe for its use.
5010 *
5011 * \return crtc, or NULL if no pipes are available.
5012 */
5013
5014/* VESA 640x480x72Hz mode to set on the pipe */
5015static struct drm_display_mode load_detect_mode = {
5016 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5017 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5018};
5019
d2dff872
CW		 5020static struct drm_framebuffer *
5021intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5022 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5023 struct drm_i915_gem_object *obj)
5024{
5025 struct intel_framebuffer *intel_fb;
5026 int ret;
5027
5028 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5029 if (!intel_fb) {
5030 drm_gem_object_unreference_unlocked(&obj->base);
5031 return ERR_PTR(-ENOMEM);
5032 }
5033
5034 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5035 if (ret) {
5036 drm_gem_object_unreference_unlocked(&obj->base);
5037 kfree(intel_fb);
5038 return ERR_PTR(ret);
5039 }
5040
5041 return &intel_fb->base;
5042}
5043
5044static u32
5045intel_framebuffer_pitch_for_width(int width, int bpp)
5046{
5047 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5048 return ALIGN(pitch, 64);
5049}
5050
5051static u32
5052intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5053{
5054 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5055 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5056}
5057
5058static struct drm_framebuffer *
5059intel_framebuffer_create_for_mode(struct drm_device *dev,
5060 struct drm_display_mode *mode,
5061 int depth, int bpp)
5062{
5063 struct drm_i915_gem_object *obj;
308e5bcb 5064 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5065
5066 obj = i915_gem_alloc_object(dev,
5067 intel_framebuffer_size_for_mode(mode, bpp));
5068 if (obj == NULL)
5069 return ERR_PTR(-ENOMEM);
5070
5071 mode_cmd.width = mode->hdisplay;
5072 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5073 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5074 bpp);
5ca0c34a 5075 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5076
5077 return intel_framebuffer_create(dev, &mode_cmd, obj);
5078}
5079
5080static struct drm_framebuffer *
5081mode_fits_in_fbdev(struct drm_device *dev,
5082 struct drm_display_mode *mode)
5083{
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct drm_i915_gem_object *obj;
5086 struct drm_framebuffer *fb;
5087
5088 if (dev_priv->fbdev == NULL)
5089 return NULL;
5090
5091 obj = dev_priv->fbdev->ifb.obj;
5092 if (obj == NULL)
5093 return NULL;
5094
5095 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5096 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5097 fb->bits_per_pixel))
d2dff872
CW		 5098 return NULL;
5099
01f2c773 5100 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5101 return NULL;
5102
5103 return fb;
5104}
5105
7173188d
CW		 5106bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5107 struct drm_connector *connector,
5108 struct drm_display_mode *mode,
8261b191 5109 struct intel_load_detect_pipe *old)
79e53945
JB		 5110{
5111 struct intel_crtc *intel_crtc;
5112 struct drm_crtc *possible_crtc;
4ef69c7a 5113 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5114 struct drm_crtc *crtc = NULL;
5115 struct drm_device *dev = encoder->dev;
d2dff872 5116 struct drm_framebuffer *old_fb;
79e53945
JB		 5117 int i = -1;
5118
d2dff872
CW		 5119 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5120 connector->base.id, drm_get_connector_name(connector),
5121 encoder->base.id, drm_get_encoder_name(encoder));
5122
79e53945
JB		 5123 /*
5124 * Algorithm gets a little messy:
7a5e4805 5125 *
79e53945
JB		 5126 * - if the connector already has an assigned crtc, use it (but make
5127 * sure it's on first)
7a5e4805 5128 *
79e53945
JB		 5129 * - try to find the first unused crtc that can drive this connector,
5130 * and use that if we find one
79e53945
JB		 5131 */
5132
5133 /* See if we already have a CRTC for this connector */
5134 if (encoder->crtc) {
5135 crtc = encoder->crtc;
8261b191 5136
79e53945 5137 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5138 old->dpms_mode = intel_crtc->dpms_mode;
5139 old->load_detect_temp = false;
5140
5141 /* Make sure the crtc and connector are running */
79e53945 5142 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5143 struct drm_encoder_helper_funcs *encoder_funcs;
5144 struct drm_crtc_helper_funcs *crtc_funcs;
5145
79e53945
JB		 5146 crtc_funcs = crtc->helper_private;
5147 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5148
5149 encoder_funcs = encoder->helper_private;
79e53945
JB		 5150 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5151 }
8261b191 5152
7173188d 5153 return true;
79e53945
JB		 5154 }
5155
5156 /* Find an unused one (if possible) */
5157 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5158 i++;
5159 if (!(encoder->possible_crtcs & (1 << i)))
5160 continue;
5161 if (!possible_crtc->enabled) {
5162 crtc = possible_crtc;
5163 break;
5164 }
79e53945
JB		 5165 }
5166
5167 /*
5168 * If we didn't find an unused CRTC, don't use any.
5169 */
5170 if (!crtc) {
7173188d
CW		 5171 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5172 return false;
79e53945
JB		 5173 }
5174
5175 encoder->crtc = crtc;
c1c43977 5176 connector->encoder = encoder;
79e53945
JB		 5177
5178 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5179 old->dpms_mode = intel_crtc->dpms_mode;
5180 old->load_detect_temp = true;
d2dff872 5181 old->release_fb = NULL;
79e53945 5182
6492711d
CW		 5183 if (!mode)
5184 mode = &load_detect_mode;
79e53945 5185
d2dff872
CW		 5186 old_fb = crtc->fb;
5187
5188 /* We need a framebuffer large enough to accommodate all accesses
5189 * that the plane may generate whilst we perform load detection.
5190 * We can not rely on the fbcon either being present (we get called
5191 * during its initialisation to detect all boot displays, or it may
5192 * not even exist) or that it is large enough to satisfy the
5193 * requested mode.
5194 */
5195 crtc->fb = mode_fits_in_fbdev(dev, mode);
5196 if (crtc->fb == NULL) {
5197 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5198 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5199 old->release_fb = crtc->fb;
5200 } else
5201 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5202 if (IS_ERR(crtc->fb)) {
5203 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5204 crtc->fb = old_fb;
5205 return false;
79e53945 5206 }
79e53945 5207
d2dff872 5208 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5209 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5210 if (old->release_fb)
5211 old->release_fb->funcs->destroy(old->release_fb);
5212 crtc->fb = old_fb;
6492711d 5213 return false;
79e53945 5214 }
7173188d 5215
79e53945 5216 /* let the connector get through one full cycle before testing */
9d0498a2 5217 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5218
7173188d 5219 return true;
79e53945
JB		 5220}
5221
c1c43977 5222void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5223 struct drm_connector *connector,
5224 struct intel_load_detect_pipe *old)
79e53945 5225{
4ef69c7a 5226 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5227 struct drm_device *dev = encoder->dev;
5228 struct drm_crtc *crtc = encoder->crtc;
5229 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5230 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5231
d2dff872
CW		 5232 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5233 connector->base.id, drm_get_connector_name(connector),
5234 encoder->base.id, drm_get_encoder_name(encoder));
5235
8261b191 5236 if (old->load_detect_temp) {
c1c43977 5237 connector->encoder = NULL;
79e53945 5238 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5239
5240 if (old->release_fb)
5241 old->release_fb->funcs->destroy(old->release_fb);
5242
0622a53c 5243 return;
79e53945
JB		 5244 }
5245
c751ce4f 5246 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5247 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5248 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5249 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5250 }
5251}
5252
5253/* Returns the clock of the currently programmed mode of the given pipe. */
5254static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5255{
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258 int pipe = intel_crtc->pipe;
548f245b 5259 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5260 u32 fp;
5261 intel_clock_t clock;
5262
5263 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5264 fp = I915_READ(FP0(pipe));
79e53945 5265 else
39adb7a5 5266 fp = I915_READ(FP1(pipe));
79e53945
JB		 5267
5268 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5269 if (IS_PINEVIEW(dev)) {
5270 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5271 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5272 } else {
5273 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5274 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5275 }
5276
a6c45cf0 5277 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5278 if (IS_PINEVIEW(dev))
5279 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5280 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5281 else
5282 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5283 DPLL_FPA01_P1_POST_DIV_SHIFT);
5284
5285 switch (dpll & DPLL_MODE_MASK) {
5286 case DPLLB_MODE_DAC_SERIAL:
5287 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5288 5 : 10;
5289 break;
5290 case DPLLB_MODE_LVDS:
5291 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5292 7 : 14;
5293 break;
5294 default:
28c97730 5295 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5296 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5297 return 0;
5298 }
5299
5300 /* XXX: Handle the 100Mhz refclk */
2177832f 5301 intel_clock(dev, 96000, &clock);
79e53945
JB		 5302 } else {
5303 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5304
5305 if (is_lvds) {
5306 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5307 DPLL_FPA01_P1_POST_DIV_SHIFT);
5308 clock.p2 = 14;
5309
5310 if ((dpll & PLL_REF_INPUT_MASK) ==
5311 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5312 /* XXX: might not be 66MHz */
2177832f 5313 intel_clock(dev, 66000, &clock);
79e53945 5314 } else
2177832f 5315 intel_clock(dev, 48000, &clock);
79e53945
JB		 5316 } else {
5317 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5318 clock.p1 = 2;
5319 else {
5320 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5321 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5322 }
5323 if (dpll & PLL_P2_DIVIDE_BY_4)
5324 clock.p2 = 4;
5325 else
5326 clock.p2 = 2;
5327
2177832f 5328 intel_clock(dev, 48000, &clock);
79e53945
JB		 5329 }
5330 }
5331
5332 /* XXX: It would be nice to validate the clocks, but we can't reuse
5333 * i830PllIsValid() because it relies on the xf86_config connector
5334 * configuration being accurate, which it isn't necessarily.
5335 */
5336
5337 return clock.dot;
5338}
5339
5340/** Returns the currently programmed mode of the given pipe. */
5341struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5342 struct drm_crtc *crtc)
5343{
548f245b 5344 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5346 int pipe = intel_crtc->pipe;
5347 struct drm_display_mode *mode;
548f245b
JB		 5348 int htot = I915_READ(HTOTAL(pipe));
5349 int hsync = I915_READ(HSYNC(pipe));
5350 int vtot = I915_READ(VTOTAL(pipe));
5351 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5352
5353 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5354 if (!mode)
5355 return NULL;
5356
5357 mode->clock = intel_crtc_clock_get(dev, crtc);
5358 mode->hdisplay = (htot & 0xffff) + 1;
5359 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5360 mode->hsync_start = (hsync & 0xffff) + 1;
5361 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5362 mode->vdisplay = (vtot & 0xffff) + 1;
5363 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5364 mode->vsync_start = (vsync & 0xffff) + 1;
5365 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5366
5367 drm_mode_set_name(mode);
79e53945
JB		 5368
5369 return mode;
5370}
5371
652c393a
JB		 5372#define GPU_IDLE_TIMEOUT 500 /* ms */
5373
5374/* When this timer fires, we've been idle for awhile */
5375static void intel_gpu_idle_timer(unsigned long arg)
5376{
5377 struct drm_device *dev = (struct drm_device *)arg;
5378 drm_i915_private_t *dev_priv = dev->dev_private;
5379
ff7ea4c0
CW		 5380 if (!list_empty(&dev_priv->mm.active_list)) {
5381 /* Still processing requests, so just re-arm the timer. */
5382 mod_timer(&dev_priv->idle_timer, jiffies +
5383 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5384 return;
5385 }
652c393a 5386
ff7ea4c0 5387 dev_priv->busy = false;
01dfba93 5388 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5389}
5390
652c393a
JB		 5391#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5392
5393static void intel_crtc_idle_timer(unsigned long arg)
5394{
5395 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5396 struct drm_crtc *crtc = &intel_crtc->base;
5397 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5398 struct intel_framebuffer *intel_fb;
652c393a 5399
ff7ea4c0
CW		 5400 intel_fb = to_intel_framebuffer(crtc->fb);
5401 if (intel_fb && intel_fb->obj->active) {
5402 /* The framebuffer is still being accessed by the GPU. */
5403 mod_timer(&intel_crtc->idle_timer, jiffies +
5404 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5405 return;
5406 }
652c393a 5407
ff7ea4c0 5408 intel_crtc->busy = false;
01dfba93 5409 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5410}
5411
3dec0095 5412static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5413{
5414 struct drm_device *dev = crtc->dev;
5415 drm_i915_private_t *dev_priv = dev->dev_private;
5416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5418 int dpll_reg = DPLL(pipe);
5419 int dpll;
652c393a 5420
bad720ff 5421 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5422 return;
5423
5424 if (!dev_priv->lvds_downclock_avail)
5425 return;
5426
dbdc6479 5427 dpll = I915_READ(dpll_reg);
652c393a 5428 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5429 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5430
8ac5a6d5 5431 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5432
5433 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5434 I915_WRITE(dpll_reg, dpll);
9d0498a2 5435 intel_wait_for_vblank(dev, pipe);
dbdc6479 5436
652c393a
JB		 5437 dpll = I915_READ(dpll_reg);
5438 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5439 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5440 }
5441
5442 /* Schedule downclock */
3dec0095
DV		 5443 mod_timer(&intel_crtc->idle_timer, jiffies +
5444 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5445}
5446
5447static void intel_decrease_pllclock(struct drm_crtc *crtc)
5448{
5449 struct drm_device *dev = crtc->dev;
5450 drm_i915_private_t *dev_priv = dev->dev_private;
5451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5452
bad720ff 5453 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5454 return;
5455
5456 if (!dev_priv->lvds_downclock_avail)
5457 return;
5458
5459 /*
5460 * Since this is called by a timer, we should never get here in
5461 * the manual case.
5462 */
5463 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5464 int pipe = intel_crtc->pipe;
5465 int dpll_reg = DPLL(pipe);
5466 int dpll;
f6e5b160 5467
44d98a61 5468 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5469
8ac5a6d5 5470 assert_panel_unlocked(dev_priv, pipe);
652c393a 5471
dc257cf1 5472 dpll = I915_READ(dpll_reg);
652c393a
JB		 5473 dpll |= DISPLAY_RATE_SELECT_FPA1;
5474 I915_WRITE(dpll_reg, dpll);
9d0498a2 5475 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5476 dpll = I915_READ(dpll_reg);
5477 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5478 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5479 }
5480
5481}
5482
5483/**
5484 * intel_idle_update - adjust clocks for idleness
5485 * @work: work struct
5486 *
5487 * Either the GPU or display (or both) went idle. Check the busy status
5488 * here and adjust the CRTC and GPU clocks as necessary.
5489 */
5490static void intel_idle_update(struct work_struct *work)
5491{
5492 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5493 idle_work);
5494 struct drm_device *dev = dev_priv->dev;
5495 struct drm_crtc *crtc;
5496 struct intel_crtc *intel_crtc;
5497
5498 if (!i915_powersave)
5499 return;
5500
5501 mutex_lock(&dev->struct_mutex);
5502
7648fa99
JB		 5503 i915_update_gfx_val(dev_priv);
5504
652c393a
JB		 5505 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5506 /* Skip inactive CRTCs */
5507 if (!crtc->fb)
5508 continue;
5509
5510 intel_crtc = to_intel_crtc(crtc);
5511 if (!intel_crtc->busy)
5512 intel_decrease_pllclock(crtc);
5513 }
5514
45ac22c8 5515
652c393a
JB		 5516 mutex_unlock(&dev->struct_mutex);
5517}
5518
5519/**
5520 * intel_mark_busy - mark the GPU and possibly the display busy
5521 * @dev: drm device
5522 * @obj: object we're operating on
5523 *
5524 * Callers can use this function to indicate that the GPU is busy processing
5525 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5526 * buffer), we'll also mark the display as busy, so we know to increase its
5527 * clock frequency.
5528 */
05394f39 5529void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5530{
5531 drm_i915_private_t *dev_priv = dev->dev_private;
5532 struct drm_crtc *crtc = NULL;
5533 struct intel_framebuffer *intel_fb;
5534 struct intel_crtc *intel_crtc;
5535
5e17ee74
ZW		 5536 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5537 return;
5538
9104183d
CW		 5539 if (!dev_priv->busy) {
5540 intel_sanitize_pm(dev);
28cf798f 5541 dev_priv->busy = true;
9104183d 5542 } else
28cf798f
CW		 5543 mod_timer(&dev_priv->idle_timer, jiffies +
5544 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 5545
5546 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5547 if (!crtc->fb)
5548 continue;
5549
5550 intel_crtc = to_intel_crtc(crtc);
5551 intel_fb = to_intel_framebuffer(crtc->fb);
5552 if (intel_fb->obj == obj) {
5553 if (!intel_crtc->busy) {
5554 /* Non-busy -> busy, upclock */
3dec0095 5555 intel_increase_pllclock(crtc);
652c393a
JB		 5556 intel_crtc->busy = true;
5557 } else {
5558 /* Busy -> busy, put off timer */
5559 mod_timer(&intel_crtc->idle_timer, jiffies +
5560 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5561 }
5562 }
5563 }
5564}
5565
79e53945
JB		 5566static void intel_crtc_destroy(struct drm_crtc *crtc)
5567{
5568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5569 struct drm_device *dev = crtc->dev;
5570 struct intel_unpin_work *work;
5571 unsigned long flags;
5572
5573 spin_lock_irqsave(&dev->event_lock, flags);
5574 work = intel_crtc->unpin_work;
5575 intel_crtc->unpin_work = NULL;
5576 spin_unlock_irqrestore(&dev->event_lock, flags);
5577
5578 if (work) {
5579 cancel_work_sync(&work->work);
5580 kfree(work);
5581 }
79e53945
JB		 5582
5583 drm_crtc_cleanup(crtc);
67e77c5a 5584
79e53945
JB		 5585 kfree(intel_crtc);
5586}
5587
6b95a207
KH		 5588static void intel_unpin_work_fn(struct work_struct *__work)
5589{
5590 struct intel_unpin_work *work =
5591 container_of(__work, struct intel_unpin_work, work);
5592
5593 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5594 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5595 drm_gem_object_unreference(&work->pending_flip_obj->base);
5596 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5597
7782de3b 5598 intel_update_fbc(work->dev);
6b95a207
KH		 5599 mutex_unlock(&work->dev->struct_mutex);
5600 kfree(work);
5601}
5602
1afe3e9d 5603static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5604 struct drm_crtc *crtc)
6b95a207
KH		 5605{
5606 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5608 struct intel_unpin_work *work;
05394f39 5609 struct drm_i915_gem_object *obj;
6b95a207 5610 struct drm_pending_vblank_event *e;
49b14a5c 5611 struct timeval tnow, tvbl;
6b95a207
KH		 5612 unsigned long flags;
5613
5614 /* Ignore early vblank irqs */
5615 if (intel_crtc == NULL)
5616 return;
5617
49b14a5c
MK		 5618 do_gettimeofday(&tnow);
5619
6b95a207
KH		 5620 spin_lock_irqsave(&dev->event_lock, flags);
5621 work = intel_crtc->unpin_work;
5622 if (work == NULL || !work->pending) {
5623 spin_unlock_irqrestore(&dev->event_lock, flags);
5624 return;
5625 }
5626
5627 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5628
5629 if (work->event) {
5630 e = work->event;
49b14a5c 5631 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5632
5633 /* Called before vblank count and timestamps have
5634 * been updated for the vblank interval of flip
5635 * completion? Need to increment vblank count and
5636 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5637 * to account for this. We assume this happened if we
5638 * get called over 0.9 frame durations after the last
5639 * timestamped vblank.
5640 *
5641 * This calculation can not be used with vrefresh rates
5642 * below 5Hz (10Hz to be on the safe side) without
5643 * promoting to 64 integers.
0af7e4df 5644 */
49b14a5c
MK		 5645 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5646 9 * crtc->framedur_ns) {
0af7e4df 5647 e->event.sequence++;
49b14a5c
MK		 5648 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5649 crtc->framedur_ns);
0af7e4df
MK		 5650 }
5651
49b14a5c
MK		 5652 e->event.tv_sec = tvbl.tv_sec;
5653 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5654
6b95a207
KH		 5655 list_add_tail(&e->base.link,
5656 &e->base.file_priv->event_list);
5657 wake_up_interruptible(&e->base.file_priv->event_wait);
5658 }
5659
0af7e4df
MK		 5660 drm_vblank_put(dev, intel_crtc->pipe);
5661
6b95a207
KH		 5662 spin_unlock_irqrestore(&dev->event_lock, flags);
5663
05394f39 5664 obj = work->old_fb_obj;
d9e86c0e 5665
e59f2bac 5666 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5667 &obj->pending_flip.counter);
5668 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5669 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5670
6b95a207 5671 schedule_work(&work->work);
e5510fac
JB		 5672
5673 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5674}
5675
1afe3e9d
JB		 5676void intel_finish_page_flip(struct drm_device *dev, int pipe)
5677{
5678 drm_i915_private_t *dev_priv = dev->dev_private;
5679 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5680
49b14a5c 5681 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5682}
5683
5684void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5685{
5686 drm_i915_private_t *dev_priv = dev->dev_private;
5687 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5688
49b14a5c 5689 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5690}
5691
6b95a207
KH		 5692void intel_prepare_page_flip(struct drm_device *dev, int plane)
5693{
5694 drm_i915_private_t *dev_priv = dev->dev_private;
5695 struct intel_crtc *intel_crtc =
5696 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5697 unsigned long flags;
5698
5699 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5700 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5701 if ((++intel_crtc->unpin_work->pending) > 1)
5702 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5703 } else {
5704 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5705 }
6b95a207
KH		 5706 spin_unlock_irqrestore(&dev->event_lock, flags);
5707}
5708
8c9f3aaf
JB		 5709static int intel_gen2_queue_flip(struct drm_device *dev,
5710 struct drm_crtc *crtc,
5711 struct drm_framebuffer *fb,
5712 struct drm_i915_gem_object *obj)
5713{
5714 struct drm_i915_private *dev_priv = dev->dev_private;
5715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5716 unsigned long offset;
5717 u32 flip_mask;
6d90c952 5718 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5719 int ret;
5720
6d90c952 5721 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5722 if (ret)
83d4092b 5723 goto err;
8c9f3aaf
JB		 5724
5725 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5726 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5727
6d90c952 5728 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5729 if (ret)
83d4092b 5730 goto err_unpin;
8c9f3aaf
JB		 5731
5732 /* Can't queue multiple flips, so wait for the previous
5733 * one to finish before executing the next.
5734 */
5735 if (intel_crtc->plane)
5736 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5737 else
5738 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5739 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5740 intel_ring_emit(ring, MI_NOOP);
5741 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5742 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5743 intel_ring_emit(ring, fb->pitches[0]);
5744 intel_ring_emit(ring, obj->gtt_offset + offset);
5745 intel_ring_emit(ring, 0); /* aux display base address, unused */
5746 intel_ring_advance(ring);
83d4092b
CW		 5747 return 0;
5748
5749err_unpin:
5750 intel_unpin_fb_obj(obj);
5751err:
8c9f3aaf
JB		 5752 return ret;
5753}
5754
5755static int intel_gen3_queue_flip(struct drm_device *dev,
5756 struct drm_crtc *crtc,
5757 struct drm_framebuffer *fb,
5758 struct drm_i915_gem_object *obj)
5759{
5760 struct drm_i915_private *dev_priv = dev->dev_private;
5761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5762 unsigned long offset;
5763 u32 flip_mask;
6d90c952 5764 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5765 int ret;
5766
6d90c952 5767 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5768 if (ret)
83d4092b 5769 goto err;
8c9f3aaf
JB		 5770
5771 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5772 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5773
6d90c952 5774 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5775 if (ret)
83d4092b 5776 goto err_unpin;
8c9f3aaf
JB		 5777
5778 if (intel_crtc->plane)
5779 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5780 else
5781 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5782 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5783 intel_ring_emit(ring, MI_NOOP);
5784 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5785 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5786 intel_ring_emit(ring, fb->pitches[0]);
5787 intel_ring_emit(ring, obj->gtt_offset + offset);
5788 intel_ring_emit(ring, MI_NOOP);
5789
5790 intel_ring_advance(ring);
83d4092b
CW		 5791 return 0;
5792
5793err_unpin:
5794 intel_unpin_fb_obj(obj);
5795err:
8c9f3aaf
JB		 5796 return ret;
5797}
5798
5799static int intel_gen4_queue_flip(struct drm_device *dev,
5800 struct drm_crtc *crtc,
5801 struct drm_framebuffer *fb,
5802 struct drm_i915_gem_object *obj)
5803{
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5806 uint32_t pf, pipesrc;
6d90c952 5807 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5808 int ret;
5809
6d90c952 5810 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5811 if (ret)
83d4092b 5812 goto err;
8c9f3aaf 5813
6d90c952 5814 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5815 if (ret)
83d4092b 5816 goto err_unpin;
8c9f3aaf
JB		 5817
5818 /* i965+ uses the linear or tiled offsets from the
5819 * Display Registers (which do not change across a page-flip)
5820 * so we need only reprogram the base address.
5821 */
6d90c952
DV		 5822 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5823 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5824 intel_ring_emit(ring, fb->pitches[0]);
5825 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 5826
5827 /* XXX Enabling the panel-fitter across page-flip is so far
5828 * untested on non-native modes, so ignore it for now.
5829 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5830 */
5831 pf = 0;
5832 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5833 intel_ring_emit(ring, pf | pipesrc);
5834 intel_ring_advance(ring);
83d4092b
CW		 5835 return 0;
5836
5837err_unpin:
5838 intel_unpin_fb_obj(obj);
5839err:
8c9f3aaf
JB		 5840 return ret;
5841}
5842
5843static int intel_gen6_queue_flip(struct drm_device *dev,
5844 struct drm_crtc *crtc,
5845 struct drm_framebuffer *fb,
5846 struct drm_i915_gem_object *obj)
5847{
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 5850 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5851 uint32_t pf, pipesrc;
5852 int ret;
5853
6d90c952 5854 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5855 if (ret)
83d4092b 5856 goto err;
8c9f3aaf 5857
6d90c952 5858 ret = intel_ring_begin(ring, 4);
8c9f3aaf 5859 if (ret)
83d4092b 5860 goto err_unpin;
8c9f3aaf 5861
6d90c952
DV		 5862 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5863 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5864 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5865 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 5866
dc257cf1
DV		 5867 /* Contrary to the suggestions in the documentation,
5868 * "Enable Panel Fitter" does not seem to be required when page
5869 * flipping with a non-native mode, and worse causes a normal
5870 * modeset to fail.
5871 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5872 */
5873 pf = 0;
8c9f3aaf 5874 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 5875 intel_ring_emit(ring, pf | pipesrc);
5876 intel_ring_advance(ring);
83d4092b
CW		 5877 return 0;
5878
5879err_unpin:
5880 intel_unpin_fb_obj(obj);
5881err:
8c9f3aaf
JB		 5882 return ret;
5883}
5884
7c9017e5
JB		 5885/*
5886 * On gen7 we currently use the blit ring because (in early silicon at least)
5887 * the render ring doesn't give us interrpts for page flip completion, which
5888 * means clients will hang after the first flip is queued. Fortunately the
5889 * blit ring generates interrupts properly, so use it instead.
5890 */
5891static int intel_gen7_queue_flip(struct drm_device *dev,
5892 struct drm_crtc *crtc,
5893 struct drm_framebuffer *fb,
5894 struct drm_i915_gem_object *obj)
5895{
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5898 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5899 int ret;
5900
5901 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5902 if (ret)
83d4092b 5903 goto err;
7c9017e5
JB		 5904
5905 ret = intel_ring_begin(ring, 4);
5906 if (ret)
83d4092b 5907 goto err_unpin;
7c9017e5
JB		 5908
5909 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 5910 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 5911 intel_ring_emit(ring, (obj->gtt_offset));
5912 intel_ring_emit(ring, (MI_NOOP));
5913 intel_ring_advance(ring);
83d4092b
CW		 5914 return 0;
5915
5916err_unpin:
5917 intel_unpin_fb_obj(obj);
5918err:
7c9017e5
JB		 5919 return ret;
5920}
5921
8c9f3aaf
JB		 5922static int intel_default_queue_flip(struct drm_device *dev,
5923 struct drm_crtc *crtc,
5924 struct drm_framebuffer *fb,
5925 struct drm_i915_gem_object *obj)
5926{
5927 return -ENODEV;
5928}
5929
6b95a207
KH		 5930static int intel_crtc_page_flip(struct drm_crtc *crtc,
5931 struct drm_framebuffer *fb,
5932 struct drm_pending_vblank_event *event)
5933{
5934 struct drm_device *dev = crtc->dev;
5935 struct drm_i915_private *dev_priv = dev->dev_private;
5936 struct intel_framebuffer *intel_fb;
05394f39 5937 struct drm_i915_gem_object *obj;
6b95a207
KH		 5938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5939 struct intel_unpin_work *work;
8c9f3aaf 5940 unsigned long flags;
52e68630 5941 int ret;
6b95a207
KH		 5942
5943 work = kzalloc(sizeof *work, GFP_KERNEL);
5944 if (work == NULL)
5945 return -ENOMEM;
5946
6b95a207
KH		 5947 work->event = event;
5948 work->dev = crtc->dev;
5949 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 5950 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 5951 INIT_WORK(&work->work, intel_unpin_work_fn);
5952
7317c75e
JB		 5953 ret = drm_vblank_get(dev, intel_crtc->pipe);
5954 if (ret)
5955 goto free_work;
5956
6b95a207
KH		 5957 /* We borrow the event spin lock for protecting unpin_work */
5958 spin_lock_irqsave(&dev->event_lock, flags);
5959 if (intel_crtc->unpin_work) {
5960 spin_unlock_irqrestore(&dev->event_lock, flags);
5961 kfree(work);
7317c75e 5962 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 5963
5964 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 5965 return -EBUSY;
5966 }
5967 intel_crtc->unpin_work = work;
5968 spin_unlock_irqrestore(&dev->event_lock, flags);
5969
5970 intel_fb = to_intel_framebuffer(fb);
5971 obj = intel_fb->obj;
5972
468f0b44 5973 mutex_lock(&dev->struct_mutex);
6b95a207 5974
75dfca80 5975 /* Reference the objects for the scheduled work. */
05394f39
CW		 5976 drm_gem_object_reference(&work->old_fb_obj->base);
5977 drm_gem_object_reference(&obj->base);
6b95a207
KH		 5978
5979 crtc->fb = fb;
96b099fd 5980
e1f99ce6 5981 work->pending_flip_obj = obj;
e1f99ce6 5982
4e5359cd
SF		 5983 work->enable_stall_check = true;
5984
e1f99ce6
CW		 5985 /* Block clients from rendering to the new back buffer until
5986 * the flip occurs and the object is no longer visible.
5987 */
05394f39 5988 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 5989
8c9f3aaf
JB		 5990 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5991 if (ret)
5992 goto cleanup_pending;
6b95a207 5993
7782de3b 5994 intel_disable_fbc(dev);
6b95a207
KH		 5995 mutex_unlock(&dev->struct_mutex);
5996
e5510fac
JB		 5997 trace_i915_flip_request(intel_crtc->plane, obj);
5998
6b95a207 5999 return 0;
96b099fd 6000
8c9f3aaf
JB		 6001cleanup_pending:
6002 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6003 drm_gem_object_unreference(&work->old_fb_obj->base);
6004 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6005 mutex_unlock(&dev->struct_mutex);
6006
6007 spin_lock_irqsave(&dev->event_lock, flags);
6008 intel_crtc->unpin_work = NULL;
6009 spin_unlock_irqrestore(&dev->event_lock, flags);
6010
7317c75e
JB		 6011 drm_vblank_put(dev, intel_crtc->pipe);
6012free_work:
96b099fd
CW		 6013 kfree(work);
6014
6015 return ret;
6b95a207
KH		 6016}
6017
47f1c6c9
CW		 6018static void intel_sanitize_modesetting(struct drm_device *dev,
6019 int pipe, int plane)
6020{
6021 struct drm_i915_private *dev_priv = dev->dev_private;
6022 u32 reg, val;
6023
f47166d2
CW		 6024 /* Clear any frame start delays used for debugging left by the BIOS */
6025 for_each_pipe(pipe) {
6026 reg = PIPECONF(pipe);
6027 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6028 }
6029
47f1c6c9
CW		 6030 if (HAS_PCH_SPLIT(dev))
6031 return;
6032
6033 /* Who knows what state these registers were left in by the BIOS or
6034 * grub?
6035 *
6036 * If we leave the registers in a conflicting state (e.g. with the
6037 * display plane reading from the other pipe than the one we intend
6038 * to use) then when we attempt to teardown the active mode, we will
6039 * not disable the pipes and planes in the correct order -- leaving
6040 * a plane reading from a disabled pipe and possibly leading to
6041 * undefined behaviour.
6042 */
6043
6044 reg = DSPCNTR(plane);
6045 val = I915_READ(reg);
6046
6047 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6048 return;
6049 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6050 return;
6051
6052 /* This display plane is active and attached to the other CPU pipe. */
6053 pipe = !pipe;
6054
6055 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6056 intel_disable_plane(dev_priv, plane, pipe);
6057 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6058}
79e53945 6059
f6e5b160
CW		 6060static void intel_crtc_reset(struct drm_crtc *crtc)
6061{
6062 struct drm_device *dev = crtc->dev;
6063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6064
6065 /* Reset flags back to the 'unknown' status so that they
6066 * will be correctly set on the initial modeset.
6067 */
6068 intel_crtc->dpms_mode = -1;
6069
6070 /* We need to fix up any BIOS configuration that conflicts with
6071 * our expectations.
6072 */
6073 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6074}
6075
6076static struct drm_crtc_helper_funcs intel_helper_funcs = {
6077 .dpms = intel_crtc_dpms,
6078 .mode_fixup = intel_crtc_mode_fixup,
6079 .mode_set = intel_crtc_mode_set,
6080 .mode_set_base = intel_pipe_set_base,
6081 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6082 .load_lut = intel_crtc_load_lut,
6083 .disable = intel_crtc_disable,
6084};
6085
6086static const struct drm_crtc_funcs intel_crtc_funcs = {
6087 .reset = intel_crtc_reset,
6088 .cursor_set = intel_crtc_cursor_set,
6089 .cursor_move = intel_crtc_cursor_move,
6090 .gamma_set = intel_crtc_gamma_set,
6091 .set_config = drm_crtc_helper_set_config,
6092 .destroy = intel_crtc_destroy,
6093 .page_flip = intel_crtc_page_flip,
6094};
6095
ee7b9f93
JB		 6096static void intel_pch_pll_init(struct drm_device *dev)
6097{
6098 drm_i915_private_t *dev_priv = dev->dev_private;
6099 int i;
6100
6101 if (dev_priv->num_pch_pll == 0) {
6102 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6103 return;
6104 }
6105
6106 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6107 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6108 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6109 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6110 }
6111}
6112
b358d0a6 6113static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6114{
22fd0fab 6115 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6116 struct intel_crtc *intel_crtc;
6117 int i;
6118
6119 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6120 if (intel_crtc == NULL)
6121 return;
6122
6123 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6124
6125 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6126 for (i = 0; i < 256; i++) {
6127 intel_crtc->lut_r[i] = i;
6128 intel_crtc->lut_g[i] = i;
6129 intel_crtc->lut_b[i] = i;
6130 }
6131
80824003
JB		 6132 /* Swap pipes & planes for FBC on pre-965 */
6133 intel_crtc->pipe = pipe;
6134 intel_crtc->plane = pipe;
e2e767ab 6135 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6136 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6137 intel_crtc->plane = !pipe;
80824003
JB		 6138 }
6139
22fd0fab
JB		 6140 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6141 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6142 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6143 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6144
5d1d0cc8 6145 intel_crtc_reset(&intel_crtc->base);
04dbff52 6146 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6147 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6148
6149 if (HAS_PCH_SPLIT(dev)) {
6150 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6151 intel_helper_funcs.commit = ironlake_crtc_commit;
6152 } else {
6153 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6154 intel_helper_funcs.commit = i9xx_crtc_commit;
6155 }
6156
79e53945
JB		 6157 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6158
652c393a
JB		 6159 intel_crtc->busy = false;
6160
6161 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6162 (unsigned long)intel_crtc);
79e53945
JB		 6163}
6164
08d7b3d1 6165int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6166 struct drm_file *file)
08d7b3d1 6167{
08d7b3d1 6168 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6169 struct drm_mode_object *drmmode_obj;
6170 struct intel_crtc *crtc;
08d7b3d1 6171
1cff8f6b
DV		 6172 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6173 return -ENODEV;
08d7b3d1 6174
c05422d5
DV		 6175 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6176 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6177
c05422d5 6178 if (!drmmode_obj) {
08d7b3d1
CW		 6179 DRM_ERROR("no such CRTC id\n");
6180 return -EINVAL;
6181 }
6182
c05422d5
DV		 6183 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6184 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6185
c05422d5 6186 return 0;
08d7b3d1
CW		 6187}
6188
c5e4df33 6189static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6190{
4ef69c7a 6191 struct intel_encoder *encoder;
79e53945 6192 int index_mask = 0;
79e53945
JB		 6193 int entry = 0;
6194
4ef69c7a
CW		 6195 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6196 if (type_mask & encoder->clone_mask)
79e53945
JB		 6197 index_mask |= (1 << entry);
6198 entry++;
6199 }
4ef69c7a 6200
79e53945
JB		 6201 return index_mask;
6202}
6203
4d302442
CW		 6204static bool has_edp_a(struct drm_device *dev)
6205{
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207
6208 if (!IS_MOBILE(dev))
6209 return false;
6210
6211 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6212 return false;
6213
6214 if (IS_GEN5(dev) &&
6215 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6216 return false;
6217
6218 return true;
6219}
6220
79e53945
JB		 6221static void intel_setup_outputs(struct drm_device *dev)
6222{
725e30ad 6223 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6224 struct intel_encoder *encoder;
cb0953d7 6225 bool dpd_is_edp = false;
f3cfcba6 6226 bool has_lvds;
79e53945 6227
f3cfcba6 6228 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6229 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6230 /* disable the panel fitter on everything but LVDS */
6231 I915_WRITE(PFIT_CONTROL, 0);
6232 }
79e53945 6233
bad720ff 6234 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6235 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6236
4d302442 6237 if (has_edp_a(dev))
32f9d658
ZW		 6238 intel_dp_init(dev, DP_A);
6239
cb0953d7
AJ		 6240 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6241 intel_dp_init(dev, PCH_DP_D);
6242 }
6243
6244 intel_crt_init(dev);
6245
6246 if (HAS_PCH_SPLIT(dev)) {
6247 int found;
6248
30ad48b7 6249 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6250 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6251 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6252 if (!found)
6253 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6254 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6255 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6256 }
6257
6258 if (I915_READ(HDMIC) & PORT_DETECTED)
6259 intel_hdmi_init(dev, HDMIC);
6260
6261 if (I915_READ(HDMID) & PORT_DETECTED)
6262 intel_hdmi_init(dev, HDMID);
6263
5eb08b69
ZW		 6264 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6265 intel_dp_init(dev, PCH_DP_C);
6266
cb0953d7 6267 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6268 intel_dp_init(dev, PCH_DP_D);
6269
103a196f 6270 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6271 bool found = false;
7d57382e 6272
725e30ad 6273 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6274 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6275 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6276 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6277 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6278 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6279 }
27185ae1 6280
b01f2c3a
JB		 6281 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6282 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6283 intel_dp_init(dev, DP_B);
b01f2c3a 6284 }
725e30ad 6285 }
13520b05
KH		 6286
6287 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6288
b01f2c3a
JB		 6289 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6290 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6291 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6292 }
27185ae1
ML		 6293
6294 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6295
b01f2c3a
JB		 6296 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6297 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6298 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6299 }
6300 if (SUPPORTS_INTEGRATED_DP(dev)) {
6301 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6302 intel_dp_init(dev, DP_C);
b01f2c3a 6303 }
725e30ad 6304 }
27185ae1 6305
b01f2c3a
JB		 6306 if (SUPPORTS_INTEGRATED_DP(dev) &&
6307 (I915_READ(DP_D) & DP_DETECTED)) {
6308 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6309 intel_dp_init(dev, DP_D);
b01f2c3a 6310 }
bad720ff 6311 } else if (IS_GEN2(dev))
79e53945
JB		 6312 intel_dvo_init(dev);
6313
103a196f 6314 if (SUPPORTS_TV(dev))
79e53945
JB		 6315 intel_tv_init(dev);
6316
4ef69c7a
CW		 6317 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6318 encoder->base.possible_crtcs = encoder->crtc_mask;
6319 encoder->base.possible_clones =
6320 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6321 }
47356eb6 6322
2c7111db
CW		 6323 /* disable all the possible outputs/crtcs before entering KMS mode */
6324 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6325
6326 if (HAS_PCH_SPLIT(dev))
6327 ironlake_init_pch_refclk(dev);
79e53945
JB		 6328}
6329
6330static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6331{
6332 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6333
6334 drm_framebuffer_cleanup(fb);
05394f39 6335 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6336
6337 kfree(intel_fb);
6338}
6339
6340static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6341 struct drm_file *file,
79e53945
JB		 6342 unsigned int *handle)
6343{
6344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6345 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6346
05394f39 6347 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6348}
6349
6350static const struct drm_framebuffer_funcs intel_fb_funcs = {
6351 .destroy = intel_user_framebuffer_destroy,
6352 .create_handle = intel_user_framebuffer_create_handle,
6353};
6354
38651674
DA		 6355int intel_framebuffer_init(struct drm_device *dev,
6356 struct intel_framebuffer *intel_fb,
308e5bcb 6357 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6358 struct drm_i915_gem_object *obj)
79e53945 6359{
79e53945
JB		 6360 int ret;
6361
05394f39 6362 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6363 return -EINVAL;
6364
308e5bcb 6365 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6366 return -EINVAL;
6367
308e5bcb 6368 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6369 case DRM_FORMAT_RGB332:
6370 case DRM_FORMAT_RGB565:
6371 case DRM_FORMAT_XRGB8888:
b250da79 6372 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6373 case DRM_FORMAT_ARGB8888:
6374 case DRM_FORMAT_XRGB2101010:
6375 case DRM_FORMAT_ARGB2101010:
308e5bcb 6376 /* RGB formats are common across chipsets */
b5626747 6377 break;
04b3924d
VS		 6378 case DRM_FORMAT_YUYV:
6379 case DRM_FORMAT_UYVY:
6380 case DRM_FORMAT_YVYU:
6381 case DRM_FORMAT_VYUY:
57cd6508
CW		 6382 break;
6383 default:
aca25848
ED		 6384 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6385 mode_cmd->pixel_format);
57cd6508
CW		 6386 return -EINVAL;
6387 }
6388
79e53945
JB		 6389 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6390 if (ret) {
6391 DRM_ERROR("framebuffer init failed %d\n", ret);
6392 return ret;
6393 }
6394
6395 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6396 intel_fb->obj = obj;
79e53945
JB		 6397 return 0;
6398}
6399
79e53945
JB		 6400static struct drm_framebuffer *
6401intel_user_framebuffer_create(struct drm_device *dev,
6402 struct drm_file *filp,
308e5bcb 6403 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6404{
05394f39 6405 struct drm_i915_gem_object *obj;
79e53945 6406
308e5bcb
JB		 6407 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6408 mode_cmd->handles[0]));
c8725226 6409 if (&obj->base == NULL)
cce13ff7 6410 return ERR_PTR(-ENOENT);
79e53945 6411
d2dff872 6412 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6413}
6414
79e53945 6415static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6416 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6417 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6418};
6419
e70236a8
JB		 6420/* Set up chip specific display functions */
6421static void intel_init_display(struct drm_device *dev)
6422{
6423 struct drm_i915_private *dev_priv = dev->dev_private;
6424
6425 /* We always want a DPMS function */
f564048e 6426 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6427 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6428 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6429 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6430 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6431 } else {
e70236a8 6432 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6433 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6434 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6435 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6436 }
e70236a8 6437
e70236a8 6438 /* Returns the core display clock speed */
25eb05fc
JB		 6439 if (IS_VALLEYVIEW(dev))
6440 dev_priv->display.get_display_clock_speed =
6441 valleyview_get_display_clock_speed;
6442 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6443 dev_priv->display.get_display_clock_speed =
6444 i945_get_display_clock_speed;
6445 else if (IS_I915G(dev))
6446 dev_priv->display.get_display_clock_speed =
6447 i915_get_display_clock_speed;
f2b115e6 6448 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6449 dev_priv->display.get_display_clock_speed =
6450 i9xx_misc_get_display_clock_speed;
6451 else if (IS_I915GM(dev))
6452 dev_priv->display.get_display_clock_speed =
6453 i915gm_get_display_clock_speed;
6454 else if (IS_I865G(dev))
6455 dev_priv->display.get_display_clock_speed =
6456 i865_get_display_clock_speed;
f0f8a9ce 6457 else if (IS_I85X(dev))
e70236a8
JB		 6458 dev_priv->display.get_display_clock_speed =
6459 i855_get_display_clock_speed;
6460 else /* 852, 830 */
6461 dev_priv->display.get_display_clock_speed =
6462 i830_get_display_clock_speed;
6463
7f8a8569 6464 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6465 if (IS_GEN5(dev)) {
674cf967 6466 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6467 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6468 } else if (IS_GEN6(dev)) {
674cf967 6469 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6470 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6471 } else if (IS_IVYBRIDGE(dev)) {
6472 /* FIXME: detect B0+ stepping and use auto training */
6473 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6474 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6475 } else
6476 dev_priv->display.update_wm = NULL;
ceb04246 6477 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6478 dev_priv->display.force_wake_get = vlv_force_wake_get;
6479 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6480 } else if (IS_G4X(dev)) {
e0dac65e 6481 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6482 }
8c9f3aaf
JB		 6483
6484 /* Default just returns -ENODEV to indicate unsupported */
6485 dev_priv->display.queue_flip = intel_default_queue_flip;
6486
6487 switch (INTEL_INFO(dev)->gen) {
6488 case 2:
6489 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6490 break;
6491
6492 case 3:
6493 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6494 break;
6495
6496 case 4:
6497 case 5:
6498 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6499 break;
6500
6501 case 6:
6502 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6503 break;
7c9017e5
JB		 6504 case 7:
6505 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6506 break;
8c9f3aaf 6507 }
e70236a8
JB		 6508}
6509
b690e96c
JB		 6510/*
6511 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6512 * resume, or other times. This quirk makes sure that's the case for
6513 * affected systems.
6514 */
0206e353 6515static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6516{
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518
6519 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6520 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6521}
6522
435793df
KP		 6523/*
6524 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6525 */
6526static void quirk_ssc_force_disable(struct drm_device *dev)
6527{
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6530 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6531}
6532
4dca20ef 6533/*
5a15ab5b
CE		 6534 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6535 * brightness value
4dca20ef
CE		 6536 */
6537static void quirk_invert_brightness(struct drm_device *dev)
6538{
6539 struct drm_i915_private *dev_priv = dev->dev_private;
6540 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6541 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6542}
6543
b690e96c
JB		 6544struct intel_quirk {
6545 int device;
6546 int subsystem_vendor;
6547 int subsystem_device;
6548 void (*hook)(struct drm_device *dev);
6549};
6550
c43b5634 6551static struct intel_quirk intel_quirks[] = {
b690e96c 6552 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6553 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6554
6555 /* Thinkpad R31 needs pipe A force quirk */
6556 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6557 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6558 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6559
6560 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6561 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6562 /* ThinkPad X40 needs pipe A force quirk */
6563
6564 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6565 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6566
6567 /* 855 & before need to leave pipe A & dpll A up */
6568 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6569 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6570
6571 /* Lenovo U160 cannot use SSC on LVDS */
6572 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6573
6574 /* Sony Vaio Y cannot use SSC on LVDS */
6575 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6576
6577 /* Acer Aspire 5734Z must invert backlight brightness */
6578 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6579};
6580
6581static void intel_init_quirks(struct drm_device *dev)
6582{
6583 struct pci_dev *d = dev->pdev;
6584 int i;
6585
6586 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6587 struct intel_quirk *q = &intel_quirks[i];
6588
6589 if (d->device == q->device &&
6590 (d->subsystem_vendor == q->subsystem_vendor ||
6591 q->subsystem_vendor == PCI_ANY_ID) &&
6592 (d->subsystem_device == q->subsystem_device ||
6593 q->subsystem_device == PCI_ANY_ID))
6594 q->hook(dev);
6595 }
6596}
6597
9cce37f4
JB		 6598/* Disable the VGA plane that we never use */
6599static void i915_disable_vga(struct drm_device *dev)
6600{
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6602 u8 sr1;
6603 u32 vga_reg;
6604
6605 if (HAS_PCH_SPLIT(dev))
6606 vga_reg = CPU_VGACNTRL;
6607 else
6608 vga_reg = VGACNTRL;
6609
6610 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6611 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6612 sr1 = inb(VGA_SR_DATA);
6613 outb(sr1 | 1<<5, VGA_SR_DATA);
6614 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6615 udelay(300);
6616
6617 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6618 POSTING_READ(vga_reg);
6619}
6620
f82cfb6b
JB		 6621static void ivb_pch_pwm_override(struct drm_device *dev)
6622{
6623 struct drm_i915_private *dev_priv = dev->dev_private;
6624
6625 /*
6626 * IVB has CPU eDP backlight regs too, set things up to let the
6627 * PCH regs control the backlight
6628 */
6629 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6630 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6631 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6632}
6633
f817586c
DV		 6634void intel_modeset_init_hw(struct drm_device *dev)
6635{
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637
6638 intel_init_clock_gating(dev);
6639
6640 if (IS_IRONLAKE_M(dev)) {
6641 ironlake_enable_drps(dev);
6642 intel_init_emon(dev);
6643 }
6644
b6834bd6 6645 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6646 gen6_enable_rps(dev_priv);
6647 gen6_update_ring_freq(dev_priv);
6648 }
f82cfb6b
JB		 6649
6650 if (IS_IVYBRIDGE(dev))
6651 ivb_pch_pwm_override(dev);
f817586c
DV		 6652}
6653
79e53945
JB		 6654void intel_modeset_init(struct drm_device *dev)
6655{
652c393a 6656 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6657 int i, ret;
79e53945
JB		 6658
6659 drm_mode_config_init(dev);
6660
6661 dev->mode_config.min_width = 0;
6662 dev->mode_config.min_height = 0;
6663
019d96cb
DA		 6664 dev->mode_config.preferred_depth = 24;
6665 dev->mode_config.prefer_shadow = 1;
6666
79e53945
JB		 6667 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6668
b690e96c
JB		 6669 intel_init_quirks(dev);
6670
1fa61106
ED		 6671 intel_init_pm(dev);
6672
e70236a8
JB		 6673 intel_init_display(dev);
6674
a6c45cf0
CW		 6675 if (IS_GEN2(dev)) {
6676 dev->mode_config.max_width = 2048;
6677 dev->mode_config.max_height = 2048;
6678 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6679 dev->mode_config.max_width = 4096;
6680 dev->mode_config.max_height = 4096;
79e53945 6681 } else {
a6c45cf0
CW		 6682 dev->mode_config.max_width = 8192;
6683 dev->mode_config.max_height = 8192;
79e53945 6684 }
35c3047a 6685 dev->mode_config.fb_base = dev->agp->base;
79e53945 6686
28c97730 6687 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6688 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6689
a3524f1b 6690 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6691 intel_crtc_init(dev, i);
00c2064b
JB		 6692 ret = intel_plane_init(dev, i);
6693 if (ret)
6694 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6695 }
6696
ee7b9f93
JB		 6697 intel_pch_pll_init(dev);
6698
9cce37f4
JB		 6699 /* Just disable it once at startup */
6700 i915_disable_vga(dev);
79e53945 6701 intel_setup_outputs(dev);
652c393a 6702
f817586c 6703 intel_modeset_init_hw(dev);
3b8d8d91 6704
652c393a
JB		 6705 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6706 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6707 (unsigned long)dev);
2c7111db
CW		 6708}
6709
6710void intel_modeset_gem_init(struct drm_device *dev)
6711{
6712 if (IS_IRONLAKE_M(dev))
6713 ironlake_enable_rc6(dev);
02e792fb
DV		 6714
6715 intel_setup_overlay(dev);
79e53945
JB		 6716}
6717
6718void intel_modeset_cleanup(struct drm_device *dev)
6719{
652c393a
JB		 6720 struct drm_i915_private *dev_priv = dev->dev_private;
6721 struct drm_crtc *crtc;
6722 struct intel_crtc *intel_crtc;
6723
f87ea761 6724 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6725 mutex_lock(&dev->struct_mutex);
6726
723bfd70
JB		 6727 intel_unregister_dsm_handler();
6728
6729
652c393a
JB		 6730 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6731 /* Skip inactive CRTCs */
6732 if (!crtc->fb)
6733 continue;
6734
6735 intel_crtc = to_intel_crtc(crtc);
3dec0095 6736 intel_increase_pllclock(crtc);
652c393a
JB		 6737 }
6738
973d04f9 6739 intel_disable_fbc(dev);
e70236a8 6740
f97108d1
JB		 6741 if (IS_IRONLAKE_M(dev))
6742 ironlake_disable_drps(dev);
b6834bd6 6743 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6744 gen6_disable_rps(dev);
f97108d1 6745
d5bb081b
JB		 6746 if (IS_IRONLAKE_M(dev))
6747 ironlake_disable_rc6(dev);
0cdab21f 6748
57f350b6
JB		 6749 if (IS_VALLEYVIEW(dev))
6750 vlv_init_dpio(dev);
6751
69341a5e
KH		 6752 mutex_unlock(&dev->struct_mutex);
6753
6c0d9350
DV		 6754 /* Disable the irq before mode object teardown, for the irq might
6755 * enqueue unpin/hotplug work. */
6756 drm_irq_uninstall(dev);
6757 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6758 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6759
1630fe75
CW		 6760 /* flush any delayed tasks or pending work */
6761 flush_scheduled_work();
6762
3dec0095
DV		 6763 /* Shut off idle work before the crtcs get freed. */
6764 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6765 intel_crtc = to_intel_crtc(crtc);
6766 del_timer_sync(&intel_crtc->idle_timer);
6767 }
6768 del_timer_sync(&dev_priv->idle_timer);
6769 cancel_work_sync(&dev_priv->idle_work);
6770
79e53945
JB		 6771 drm_mode_config_cleanup(dev);
6772}
6773
f1c79df3
ZW		 6774/*
6775 * Return which encoder is currently attached for connector.
6776 */
df0e9248 6777struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6778{
df0e9248
CW		 6779 return &intel_attached_encoder(connector)->base;
6780}
f1c79df3 6781
df0e9248
CW		 6782void intel_connector_attach_encoder(struct intel_connector *connector,
6783 struct intel_encoder *encoder)
6784{
6785 connector->encoder = encoder;
6786 drm_mode_connector_attach_encoder(&connector->base,
6787 &encoder->base);
79e53945 6788}
28d52043
DA		 6789
6790/*
6791 * set vga decode state - true == enable VGA decode
6792 */
6793int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6794{
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 u16 gmch_ctrl;
6797
6798 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6799 if (state)
6800 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6801 else
6802 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6803 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6804 return 0;
6805}
c4a1d9e4
CW		 6806
6807#ifdef CONFIG_DEBUG_FS
6808#include <linux/seq_file.h>
6809
6810struct intel_display_error_state {
6811 struct intel_cursor_error_state {
6812 u32 control;
6813 u32 position;
6814 u32 base;
6815 u32 size;
6816 } cursor[2];
6817
6818 struct intel_pipe_error_state {
6819 u32 conf;
6820 u32 source;
6821
6822 u32 htotal;
6823 u32 hblank;
6824 u32 hsync;
6825 u32 vtotal;
6826 u32 vblank;
6827 u32 vsync;
6828 } pipe[2];
6829
6830 struct intel_plane_error_state {
6831 u32 control;
6832 u32 stride;
6833 u32 size;
6834 u32 pos;
6835 u32 addr;
6836 u32 surface;
6837 u32 tile_offset;
6838 } plane[2];
6839};
6840
6841struct intel_display_error_state *
6842intel_display_capture_error_state(struct drm_device *dev)
6843{
0206e353 6844 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 6845 struct intel_display_error_state *error;
6846 int i;
6847
6848 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6849 if (error == NULL)
6850 return NULL;
6851
6852 for (i = 0; i < 2; i++) {
6853 error->cursor[i].control = I915_READ(CURCNTR(i));
6854 error->cursor[i].position = I915_READ(CURPOS(i));
6855 error->cursor[i].base = I915_READ(CURBASE(i));
6856
6857 error->plane[i].control = I915_READ(DSPCNTR(i));
6858 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6859 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 6860 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 6861 error->plane[i].addr = I915_READ(DSPADDR(i));
6862 if (INTEL_INFO(dev)->gen >= 4) {
6863 error->plane[i].surface = I915_READ(DSPSURF(i));
6864 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6865 }
6866
6867 error->pipe[i].conf = I915_READ(PIPECONF(i));
6868 error->pipe[i].source = I915_READ(PIPESRC(i));
6869 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6870 error->pipe[i].hblank = I915_READ(HBLANK(i));
6871 error->pipe[i].hsync = I915_READ(HSYNC(i));
6872 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6873 error->pipe[i].vblank = I915_READ(VBLANK(i));
6874 error->pipe[i].vsync = I915_READ(VSYNC(i));
6875 }
6876
6877 return error;
6878}
6879
6880void
6881intel_display_print_error_state(struct seq_file *m,
6882 struct drm_device *dev,
6883 struct intel_display_error_state *error)
6884{
6885 int i;
6886
6887 for (i = 0; i < 2; i++) {
6888 seq_printf(m, "Pipe [%d]:\n", i);
6889 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6890 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6891 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6892 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6893 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6894 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6895 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6896 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6897
6898 seq_printf(m, "Plane [%d]:\n", i);
6899 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6900 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6901 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6902 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6903 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6904 if (INTEL_INFO(dev)->gen >= 4) {
6905 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6906 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6907 }
6908
6909 seq_printf(m, "Cursor [%d]:\n", i);
6910 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6911 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6912 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6913 }
6914}
6915#endif
Linux kernel - Deliverables
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