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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
021357ac CW |
345 | static inline u32 /* units of 100MHz */ |
346 | intel_fdi_link_freq(struct drm_device *dev) | |
347 | { | |
348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
349 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
350 | } | |
351 | ||
e4b36699 | 352 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
353 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
354 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
355 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
356 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
357 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
358 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
359 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
360 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
361 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
362 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 363 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
364 | }; |
365 | ||
366 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
367 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
368 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
369 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
370 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
371 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
372 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
373 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
374 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
375 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
376 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 377 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
378 | }; |
379 | ||
380 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
381 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
382 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
383 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
384 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
385 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
386 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
387 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
388 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
389 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
390 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 391 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
392 | }; |
393 | ||
394 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
395 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
396 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
397 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
398 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
399 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
400 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
401 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
402 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
403 | /* The single-channel range is 25-112Mhz, and dual-channel | |
404 | * is 80-224Mhz. Prefer single channel as much as possible. | |
405 | */ | |
406 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
407 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 408 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
409 | }; |
410 | ||
044c7c41 | 411 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 412 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
413 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
414 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
415 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
416 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
417 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
418 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
419 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
420 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
421 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
422 | .p2_slow = G4X_P2_SDVO_SLOW, | |
423 | .p2_fast = G4X_P2_SDVO_FAST | |
424 | }, | |
d4906093 | 425 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
426 | }; |
427 | ||
428 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
429 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
430 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
431 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
432 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
433 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
434 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
435 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
436 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
437 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
438 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
439 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
440 | }, | |
d4906093 | 441 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
445 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
446 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
447 | .vco = { .min = G4X_VCO_MIN, | |
448 | .max = G4X_VCO_MAX }, | |
449 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
450 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
451 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
452 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
453 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
454 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
455 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
456 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
457 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
458 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
459 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
460 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
461 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
462 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
463 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
464 | }, | |
d4906093 | 465 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
466 | }; |
467 | ||
468 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
469 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
470 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
471 | .vco = { .min = G4X_VCO_MIN, | |
472 | .max = G4X_VCO_MAX }, | |
473 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
474 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
475 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
476 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
477 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
478 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
479 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
480 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
481 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
482 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
483 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
484 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
485 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
486 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
487 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
488 | }, | |
d4906093 | 489 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
490 | }; |
491 | ||
492 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
493 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
494 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
495 | .vco = { .min = G4X_VCO_MIN, | |
496 | .max = G4X_VCO_MAX}, | |
497 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
498 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
499 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
500 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
501 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
502 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
503 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
504 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
505 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
506 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
507 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
508 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
509 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
510 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
511 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
512 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
513 | }; |
514 | ||
f2b115e6 | 515 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 516 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
517 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
518 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
519 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
520 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
521 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
522 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
523 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
524 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
525 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 526 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
527 | }; |
528 | ||
f2b115e6 | 529 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 530 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
531 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
532 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
533 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
534 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
535 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
536 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 537 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 538 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
539 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
540 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 541 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
542 | }; |
543 | ||
b91ad0ec | 544 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
545 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
546 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
547 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
548 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
549 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
550 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
551 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
552 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 553 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
554 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
555 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 556 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
557 | }; |
558 | ||
b91ad0ec | 559 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
560 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
561 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
562 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
563 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
564 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
565 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
566 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
567 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 568 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
569 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
570 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
571 | .find_pll = intel_g4x_find_best_PLL, | |
572 | }; | |
573 | ||
574 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
575 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
576 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
577 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
578 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
579 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
580 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
581 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
582 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
583 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
584 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
585 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
586 | .find_pll = intel_g4x_find_best_PLL, | |
587 | }; | |
588 | ||
589 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
590 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
591 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
592 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
593 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
594 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
595 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
596 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
597 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
598 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
599 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
600 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
601 | .find_pll = intel_g4x_find_best_PLL, | |
602 | }; | |
603 | ||
604 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
605 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
606 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
607 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
608 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
609 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
610 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
611 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
612 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
613 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
614 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
615 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
616 | .find_pll = intel_g4x_find_best_PLL, |
617 | }; | |
618 | ||
619 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
620 | .dot = { .min = IRONLAKE_DOT_MIN, | |
621 | .max = IRONLAKE_DOT_MAX }, | |
622 | .vco = { .min = IRONLAKE_VCO_MIN, | |
623 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
624 | .n = { .min = IRONLAKE_DP_N_MIN, |
625 | .max = IRONLAKE_DP_N_MAX }, | |
626 | .m = { .min = IRONLAKE_DP_M_MIN, | |
627 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
628 | .m1 = { .min = IRONLAKE_M1_MIN, |
629 | .max = IRONLAKE_M1_MAX }, | |
630 | .m2 = { .min = IRONLAKE_M2_MIN, | |
631 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
632 | .p = { .min = IRONLAKE_DP_P_MIN, |
633 | .max = IRONLAKE_DP_P_MAX }, | |
634 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
635 | .max = IRONLAKE_DP_P1_MAX}, | |
636 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
637 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
638 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 639 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
640 | }; |
641 | ||
f2b115e6 | 642 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) |
2c07245f | 643 | { |
b91ad0ec ZW |
644 | struct drm_device *dev = crtc->dev; |
645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 646 | const intel_limit_t *limit; |
b91ad0ec ZW |
647 | int refclk = 120; |
648 | ||
649 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
650 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) | |
651 | refclk = 100; | |
652 | ||
653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == | |
654 | LVDS_CLKB_POWER_UP) { | |
655 | /* LVDS dual channel */ | |
656 | if (refclk == 100) | |
657 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
658 | else | |
659 | limit = &intel_limits_ironlake_dual_lvds; | |
660 | } else { | |
661 | if (refclk == 100) | |
662 | limit = &intel_limits_ironlake_single_lvds_100m; | |
663 | else | |
664 | limit = &intel_limits_ironlake_single_lvds; | |
665 | } | |
666 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
667 | HAS_eDP) |
668 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 669 | else |
b91ad0ec | 670 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
671 | |
672 | return limit; | |
673 | } | |
674 | ||
044c7c41 ML |
675 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
676 | { | |
677 | struct drm_device *dev = crtc->dev; | |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | const intel_limit_t *limit; | |
680 | ||
681 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
682 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
683 | LVDS_CLKB_POWER_UP) | |
684 | /* LVDS with dual channel */ | |
e4b36699 | 685 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
686 | else |
687 | /* LVDS with dual channel */ | |
e4b36699 | 688 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
689 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 691 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 693 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 694 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 695 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 696 | } else /* The option is for other outputs */ |
e4b36699 | 697 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
698 | |
699 | return limit; | |
700 | } | |
701 | ||
79e53945 JB |
702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
703 | { | |
704 | struct drm_device *dev = crtc->dev; | |
705 | const intel_limit_t *limit; | |
706 | ||
bad720ff | 707 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 708 | limit = intel_ironlake_limit(crtc); |
2c07245f | 709 | else if (IS_G4X(dev)) { |
044c7c41 | 710 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 711 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 713 | limit = &intel_limits_pineview_lvds; |
2177832f | 714 | else |
f2b115e6 | 715 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
716 | } else if (!IS_GEN2(dev)) { |
717 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
718 | limit = &intel_limits_i9xx_lvds; | |
719 | else | |
720 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
721 | } else { |
722 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 723 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 724 | else |
e4b36699 | 725 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
726 | } |
727 | return limit; | |
728 | } | |
729 | ||
f2b115e6 AJ |
730 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
731 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 732 | { |
2177832f SL |
733 | clock->m = clock->m2 + 2; |
734 | clock->p = clock->p1 * clock->p2; | |
735 | clock->vco = refclk * clock->m / clock->n; | |
736 | clock->dot = clock->vco / clock->p; | |
737 | } | |
738 | ||
739 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
740 | { | |
f2b115e6 AJ |
741 | if (IS_PINEVIEW(dev)) { |
742 | pineview_clock(refclk, clock); | |
2177832f SL |
743 | return; |
744 | } | |
79e53945 JB |
745 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
746 | clock->p = clock->p1 * clock->p2; | |
747 | clock->vco = refclk * clock->m / (clock->n + 2); | |
748 | clock->dot = clock->vco / clock->p; | |
749 | } | |
750 | ||
79e53945 JB |
751 | /** |
752 | * Returns whether any output on the specified pipe is of the specified type | |
753 | */ | |
4ef69c7a | 754 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 755 | { |
4ef69c7a CW |
756 | struct drm_device *dev = crtc->dev; |
757 | struct drm_mode_config *mode_config = &dev->mode_config; | |
758 | struct intel_encoder *encoder; | |
759 | ||
760 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
761 | if (encoder->base.crtc == crtc && encoder->type == type) | |
762 | return true; | |
763 | ||
764 | return false; | |
79e53945 JB |
765 | } |
766 | ||
7c04d1d9 | 767 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
768 | /** |
769 | * Returns whether the given set of divisors are valid for a given refclk with | |
770 | * the given connectors. | |
771 | */ | |
772 | ||
773 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
774 | { | |
775 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 776 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
777 | |
778 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
779 | INTELPllInvalid ("p1 out of range\n"); | |
780 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
781 | INTELPllInvalid ("p out of range\n"); | |
782 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
783 | INTELPllInvalid ("m2 out of range\n"); | |
784 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
785 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 786 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
787 | INTELPllInvalid ("m1 <= m2\n"); |
788 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
789 | INTELPllInvalid ("m out of range\n"); | |
790 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
791 | INTELPllInvalid ("n out of range\n"); | |
792 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
793 | INTELPllInvalid ("vco out of range\n"); | |
794 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
795 | * connector, etc., rather than just a single range. | |
796 | */ | |
797 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
798 | INTELPllInvalid ("dot out of range\n"); | |
799 | ||
800 | return true; | |
801 | } | |
802 | ||
d4906093 ML |
803 | static bool |
804 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
805 | int target, int refclk, intel_clock_t *best_clock) | |
806 | ||
79e53945 JB |
807 | { |
808 | struct drm_device *dev = crtc->dev; | |
809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
810 | intel_clock_t clock; | |
79e53945 JB |
811 | int err = target; |
812 | ||
bc5e5718 | 813 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 814 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
815 | /* |
816 | * For LVDS, if the panel is on, just rely on its current | |
817 | * settings for dual-channel. We haven't figured out how to | |
818 | * reliably set up different single/dual channel state, if we | |
819 | * even can. | |
820 | */ | |
821 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
822 | LVDS_CLKB_POWER_UP) | |
823 | clock.p2 = limit->p2.p2_fast; | |
824 | else | |
825 | clock.p2 = limit->p2.p2_slow; | |
826 | } else { | |
827 | if (target < limit->p2.dot_limit) | |
828 | clock.p2 = limit->p2.p2_slow; | |
829 | else | |
830 | clock.p2 = limit->p2.p2_fast; | |
831 | } | |
832 | ||
833 | memset (best_clock, 0, sizeof (*best_clock)); | |
834 | ||
42158660 ZY |
835 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
836 | clock.m1++) { | |
837 | for (clock.m2 = limit->m2.min; | |
838 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
839 | /* m1 is always 0 in Pineview */ |
840 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
841 | break; |
842 | for (clock.n = limit->n.min; | |
843 | clock.n <= limit->n.max; clock.n++) { | |
844 | for (clock.p1 = limit->p1.min; | |
845 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
846 | int this_err; |
847 | ||
2177832f | 848 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
849 | |
850 | if (!intel_PLL_is_valid(crtc, &clock)) | |
851 | continue; | |
852 | ||
853 | this_err = abs(clock.dot - target); | |
854 | if (this_err < err) { | |
855 | *best_clock = clock; | |
856 | err = this_err; | |
857 | } | |
858 | } | |
859 | } | |
860 | } | |
861 | } | |
862 | ||
863 | return (err != target); | |
864 | } | |
865 | ||
d4906093 ML |
866 | static bool |
867 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
868 | int target, int refclk, intel_clock_t *best_clock) | |
869 | { | |
870 | struct drm_device *dev = crtc->dev; | |
871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
872 | intel_clock_t clock; | |
873 | int max_n; | |
874 | bool found; | |
6ba770dc AJ |
875 | /* approximately equals target * 0.00585 */ |
876 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
877 | found = false; |
878 | ||
879 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
880 | int lvds_reg; |
881 | ||
c619eed4 | 882 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
883 | lvds_reg = PCH_LVDS; |
884 | else | |
885 | lvds_reg = LVDS; | |
886 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
887 | LVDS_CLKB_POWER_UP) |
888 | clock.p2 = limit->p2.p2_fast; | |
889 | else | |
890 | clock.p2 = limit->p2.p2_slow; | |
891 | } else { | |
892 | if (target < limit->p2.dot_limit) | |
893 | clock.p2 = limit->p2.p2_slow; | |
894 | else | |
895 | clock.p2 = limit->p2.p2_fast; | |
896 | } | |
897 | ||
898 | memset(best_clock, 0, sizeof(*best_clock)); | |
899 | max_n = limit->n.max; | |
f77f13e2 | 900 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 901 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 902 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
903 | for (clock.m1 = limit->m1.max; |
904 | clock.m1 >= limit->m1.min; clock.m1--) { | |
905 | for (clock.m2 = limit->m2.max; | |
906 | clock.m2 >= limit->m2.min; clock.m2--) { | |
907 | for (clock.p1 = limit->p1.max; | |
908 | clock.p1 >= limit->p1.min; clock.p1--) { | |
909 | int this_err; | |
910 | ||
2177832f | 911 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
912 | if (!intel_PLL_is_valid(crtc, &clock)) |
913 | continue; | |
914 | this_err = abs(clock.dot - target) ; | |
915 | if (this_err < err_most) { | |
916 | *best_clock = clock; | |
917 | err_most = this_err; | |
918 | max_n = clock.n; | |
919 | found = true; | |
920 | } | |
921 | } | |
922 | } | |
923 | } | |
924 | } | |
2c07245f ZW |
925 | return found; |
926 | } | |
927 | ||
5eb08b69 | 928 | static bool |
f2b115e6 AJ |
929 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
930 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
931 | { |
932 | struct drm_device *dev = crtc->dev; | |
933 | intel_clock_t clock; | |
4547668a ZY |
934 | |
935 | /* return directly when it is eDP */ | |
936 | if (HAS_eDP) | |
937 | return true; | |
938 | ||
5eb08b69 ZW |
939 | if (target < 200000) { |
940 | clock.n = 1; | |
941 | clock.p1 = 2; | |
942 | clock.p2 = 10; | |
943 | clock.m1 = 12; | |
944 | clock.m2 = 9; | |
945 | } else { | |
946 | clock.n = 2; | |
947 | clock.p1 = 1; | |
948 | clock.p2 = 10; | |
949 | clock.m1 = 14; | |
950 | clock.m2 = 8; | |
951 | } | |
952 | intel_clock(dev, refclk, &clock); | |
953 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
954 | return true; | |
955 | } | |
956 | ||
a4fc5ed6 KP |
957 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
958 | static bool | |
959 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
960 | int target, int refclk, intel_clock_t *best_clock) | |
961 | { | |
5eddb70b CW |
962 | intel_clock_t clock; |
963 | if (target < 200000) { | |
964 | clock.p1 = 2; | |
965 | clock.p2 = 10; | |
966 | clock.n = 2; | |
967 | clock.m1 = 23; | |
968 | clock.m2 = 8; | |
969 | } else { | |
970 | clock.p1 = 1; | |
971 | clock.p2 = 10; | |
972 | clock.n = 1; | |
973 | clock.m1 = 14; | |
974 | clock.m2 = 2; | |
975 | } | |
976 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
977 | clock.p = (clock.p1 * clock.p2); | |
978 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
979 | clock.vco = 0; | |
980 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
981 | return true; | |
a4fc5ed6 KP |
982 | } |
983 | ||
9d0498a2 JB |
984 | /** |
985 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
986 | * @dev: drm device | |
987 | * @pipe: pipe to wait for | |
988 | * | |
989 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
990 | * mode setting code. | |
991 | */ | |
992 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 993 | { |
9d0498a2 JB |
994 | struct drm_i915_private *dev_priv = dev->dev_private; |
995 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); | |
996 | ||
300387c0 CW |
997 | /* Clear existing vblank status. Note this will clear any other |
998 | * sticky status fields as well. | |
999 | * | |
1000 | * This races with i915_driver_irq_handler() with the result | |
1001 | * that either function could miss a vblank event. Here it is not | |
1002 | * fatal, as we will either wait upon the next vblank interrupt or | |
1003 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
1004 | * called during modeset at which time the GPU should be idle and | |
1005 | * should *not* be performing page flips and thus not waiting on | |
1006 | * vblanks... | |
1007 | * Currently, the result of us stealing a vblank from the irq | |
1008 | * handler is that a single frame will be skipped during swapbuffers. | |
1009 | */ | |
1010 | I915_WRITE(pipestat_reg, | |
1011 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1012 | ||
9d0498a2 | 1013 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1014 | if (wait_for(I915_READ(pipestat_reg) & |
1015 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1016 | 50)) | |
9d0498a2 JB |
1017 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1018 | } | |
1019 | ||
1020 | /** | |
1021 | * intel_wait_for_vblank_off - wait for vblank after disabling a pipe | |
1022 | * @dev: drm device | |
1023 | * @pipe: pipe to wait for | |
1024 | * | |
1025 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1026 | * spinning on the vblank interrupt status bit, since we won't actually | |
1027 | * see an interrupt when the pipe is disabled. | |
1028 | * | |
1029 | * So this function waits for the display line value to settle (it | |
1030 | * usually ends up stopping at the start of the next frame). | |
1031 | */ | |
1032 | void intel_wait_for_vblank_off(struct drm_device *dev, int pipe) | |
1033 | { | |
1034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1035 | int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL); | |
1036 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | |
ec5da01e | 1037 | u32 last_line, line; |
9d0498a2 JB |
1038 | |
1039 | /* Wait for the display line to settle */ | |
ec5da01e | 1040 | line = I915_READ(pipedsl_reg) & DSL_LINEMASK; |
9d0498a2 | 1041 | do { |
ec5da01e CW |
1042 | last_line = line; |
1043 | MSLEEP(5); | |
1044 | line = I915_READ(pipedsl_reg) & DSL_LINEMASK; | |
1045 | } while (line != last_line && time_after(timeout, jiffies)); | |
9d0498a2 | 1046 | |
ec5da01e | 1047 | if (line != last_line) |
9d0498a2 | 1048 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
79e53945 JB |
1049 | } |
1050 | ||
80824003 JB |
1051 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1052 | { | |
1053 | struct drm_device *dev = crtc->dev; | |
1054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1055 | struct drm_framebuffer *fb = crtc->fb; | |
1056 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1057 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
80824003 JB |
1058 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1059 | int plane, i; | |
1060 | u32 fbc_ctl, fbc_ctl2; | |
1061 | ||
bed4a673 CW |
1062 | if (fb->pitch == dev_priv->cfb_pitch && |
1063 | obj_priv->fence_reg == dev_priv->cfb_fence && | |
1064 | intel_crtc->plane == dev_priv->cfb_plane && | |
1065 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) | |
1066 | return; | |
1067 | ||
1068 | i8xx_disable_fbc(dev); | |
1069 | ||
80824003 JB |
1070 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1071 | ||
1072 | if (fb->pitch < dev_priv->cfb_pitch) | |
1073 | dev_priv->cfb_pitch = fb->pitch; | |
1074 | ||
1075 | /* FBC_CTL wants 64B units */ | |
1076 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
1077 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1078 | dev_priv->cfb_plane = intel_crtc->plane; | |
1079 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1080 | ||
1081 | /* Clear old tags */ | |
1082 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1083 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1084 | ||
1085 | /* Set it up... */ | |
1086 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
1087 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1088 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; | |
1089 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1090 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1091 | ||
1092 | /* enable it... */ | |
1093 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1094 | if (IS_I945GM(dev)) |
49677901 | 1095 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1096 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1097 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
1098 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1099 | fbc_ctl |= dev_priv->cfb_fence; | |
1100 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1101 | ||
28c97730 | 1102 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
5eddb70b | 1103 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
80824003 JB |
1104 | } |
1105 | ||
1106 | void i8xx_disable_fbc(struct drm_device *dev) | |
1107 | { | |
1108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1109 | u32 fbc_ctl; | |
1110 | ||
1111 | /* Disable compression */ | |
1112 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1113 | fbc_ctl &= ~FBC_CTL_EN; | |
1114 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1115 | ||
1116 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1117 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1118 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1119 | return; | |
9517a92f | 1120 | } |
80824003 | 1121 | |
28c97730 | 1122 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1123 | } |
1124 | ||
ee5382ae | 1125 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1126 | { |
80824003 JB |
1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
1128 | ||
1129 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1130 | } | |
1131 | ||
74dff282 JB |
1132 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1133 | { | |
1134 | struct drm_device *dev = crtc->dev; | |
1135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1136 | struct drm_framebuffer *fb = crtc->fb; | |
1137 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
23010e43 | 1138 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); |
74dff282 | 1139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1140 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1141 | unsigned long stall_watermark = 200; |
1142 | u32 dpfc_ctl; | |
1143 | ||
bed4a673 CW |
1144 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1145 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1146 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
1147 | dev_priv->cfb_fence == obj_priv->fence_reg && | |
1148 | dev_priv->cfb_plane == intel_crtc->plane && | |
1149 | dev_priv->cfb_y == crtc->y) | |
1150 | return; | |
1151 | ||
1152 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1153 | POSTING_READ(DPFC_CONTROL); | |
1154 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1155 | } | |
1156 | ||
74dff282 JB |
1157 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
1158 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1159 | dev_priv->cfb_plane = intel_crtc->plane; | |
bed4a673 | 1160 | dev_priv->cfb_y = crtc->y; |
74dff282 JB |
1161 | |
1162 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
1163 | if (obj_priv->tiling_mode != I915_TILING_NONE) { | |
1164 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; | |
1165 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1166 | } else { | |
1167 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1168 | } | |
1169 | ||
74dff282 JB |
1170 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1171 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1172 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1173 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1174 | ||
1175 | /* enable it... */ | |
1176 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1177 | ||
28c97730 | 1178 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1179 | } |
1180 | ||
1181 | void g4x_disable_fbc(struct drm_device *dev) | |
1182 | { | |
1183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1184 | u32 dpfc_ctl; | |
1185 | ||
1186 | /* Disable compression */ | |
1187 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1188 | if (dpfc_ctl & DPFC_CTL_EN) { |
1189 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1190 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1191 | |
bed4a673 CW |
1192 | DRM_DEBUG_KMS("disabled FBC\n"); |
1193 | } | |
74dff282 JB |
1194 | } |
1195 | ||
ee5382ae | 1196 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1197 | { |
74dff282 JB |
1198 | struct drm_i915_private *dev_priv = dev->dev_private; |
1199 | ||
1200 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1201 | } | |
1202 | ||
b52eb4dc ZY |
1203 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1204 | { | |
1205 | struct drm_device *dev = crtc->dev; | |
1206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1207 | struct drm_framebuffer *fb = crtc->fb; | |
1208 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1209 | struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj); | |
1210 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5eddb70b | 1211 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1212 | unsigned long stall_watermark = 200; |
1213 | u32 dpfc_ctl; | |
1214 | ||
bed4a673 CW |
1215 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1216 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1217 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
1218 | dev_priv->cfb_fence == obj_priv->fence_reg && | |
1219 | dev_priv->cfb_plane == intel_crtc->plane && | |
1220 | dev_priv->cfb_offset == obj_priv->gtt_offset && | |
1221 | dev_priv->cfb_y == crtc->y) | |
1222 | return; | |
1223 | ||
1224 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1225 | POSTING_READ(ILK_DPFC_CONTROL); | |
1226 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1227 | } | |
1228 | ||
b52eb4dc ZY |
1229 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
1230 | dev_priv->cfb_fence = obj_priv->fence_reg; | |
1231 | dev_priv->cfb_plane = intel_crtc->plane; | |
bed4a673 CW |
1232 | dev_priv->cfb_offset = obj_priv->gtt_offset; |
1233 | dev_priv->cfb_y = crtc->y; | |
b52eb4dc | 1234 | |
b52eb4dc ZY |
1235 | dpfc_ctl &= DPFC_RESERVED; |
1236 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
1237 | if (obj_priv->tiling_mode != I915_TILING_NONE) { | |
1238 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); | |
1239 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1240 | } else { | |
1241 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1242 | } | |
1243 | ||
b52eb4dc ZY |
1244 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1245 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1246 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1247 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
1248 | I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID); | |
1249 | /* enable it... */ | |
bed4a673 | 1250 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc ZY |
1251 | |
1252 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | |
1253 | } | |
1254 | ||
1255 | void ironlake_disable_fbc(struct drm_device *dev) | |
1256 | { | |
1257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1258 | u32 dpfc_ctl; | |
1259 | ||
1260 | /* Disable compression */ | |
1261 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1262 | if (dpfc_ctl & DPFC_CTL_EN) { |
1263 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1264 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1265 | |
bed4a673 CW |
1266 | DRM_DEBUG_KMS("disabled FBC\n"); |
1267 | } | |
b52eb4dc ZY |
1268 | } |
1269 | ||
1270 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1271 | { | |
1272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1273 | ||
1274 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1275 | } | |
1276 | ||
ee5382ae AJ |
1277 | bool intel_fbc_enabled(struct drm_device *dev) |
1278 | { | |
1279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1280 | ||
1281 | if (!dev_priv->display.fbc_enabled) | |
1282 | return false; | |
1283 | ||
1284 | return dev_priv->display.fbc_enabled(dev); | |
1285 | } | |
1286 | ||
1287 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1288 | { | |
1289 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1290 | ||
1291 | if (!dev_priv->display.enable_fbc) | |
1292 | return; | |
1293 | ||
1294 | dev_priv->display.enable_fbc(crtc, interval); | |
1295 | } | |
1296 | ||
1297 | void intel_disable_fbc(struct drm_device *dev) | |
1298 | { | |
1299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1300 | ||
1301 | if (!dev_priv->display.disable_fbc) | |
1302 | return; | |
1303 | ||
1304 | dev_priv->display.disable_fbc(dev); | |
1305 | } | |
1306 | ||
80824003 JB |
1307 | /** |
1308 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1309 | * @dev: the drm_device |
80824003 JB |
1310 | * |
1311 | * Set up the framebuffer compression hardware at mode set time. We | |
1312 | * enable it if possible: | |
1313 | * - plane A only (on pre-965) | |
1314 | * - no pixel mulitply/line duplication | |
1315 | * - no alpha buffer discard | |
1316 | * - no dual wide | |
1317 | * - framebuffer <= 2048 in width, 1536 in height | |
1318 | * | |
1319 | * We can't assume that any compression will take place (worst case), | |
1320 | * so the compressed buffer has to be the same size as the uncompressed | |
1321 | * one. It also must reside (along with the line length buffer) in | |
1322 | * stolen memory. | |
1323 | * | |
1324 | * We need to enable/disable FBC on a global basis. | |
1325 | */ | |
bed4a673 | 1326 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1327 | { |
80824003 | 1328 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1329 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1330 | struct intel_crtc *intel_crtc; | |
1331 | struct drm_framebuffer *fb; | |
80824003 JB |
1332 | struct intel_framebuffer *intel_fb; |
1333 | struct drm_i915_gem_object *obj_priv; | |
9c928d16 JB |
1334 | |
1335 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1336 | |
1337 | if (!i915_powersave) | |
1338 | return; | |
1339 | ||
ee5382ae | 1340 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1341 | return; |
1342 | ||
80824003 JB |
1343 | /* |
1344 | * If FBC is already on, we just have to verify that we can | |
1345 | * keep it that way... | |
1346 | * Need to disable if: | |
9c928d16 | 1347 | * - more than one pipe is active |
80824003 JB |
1348 | * - changing FBC params (stride, fence, mode) |
1349 | * - new fb is too large to fit in compressed buffer | |
1350 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1351 | */ | |
9c928d16 | 1352 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
bed4a673 CW |
1353 | if (tmp_crtc->enabled) { |
1354 | if (crtc) { | |
1355 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1356 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1357 | goto out_disable; | |
1358 | } | |
1359 | crtc = tmp_crtc; | |
1360 | } | |
9c928d16 | 1361 | } |
bed4a673 CW |
1362 | |
1363 | if (!crtc || crtc->fb == NULL) { | |
1364 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1365 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1366 | goto out_disable; |
1367 | } | |
bed4a673 CW |
1368 | |
1369 | intel_crtc = to_intel_crtc(crtc); | |
1370 | fb = crtc->fb; | |
1371 | intel_fb = to_intel_framebuffer(fb); | |
1372 | obj_priv = to_intel_bo(intel_fb->obj); | |
1373 | ||
80824003 | 1374 | if (intel_fb->obj->size > dev_priv->cfb_size) { |
28c97730 | 1375 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1376 | "compression\n"); |
b5e50c3f | 1377 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1378 | goto out_disable; |
1379 | } | |
bed4a673 CW |
1380 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1381 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1382 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1383 | "disabling\n"); |
b5e50c3f | 1384 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1385 | goto out_disable; |
1386 | } | |
bed4a673 CW |
1387 | if ((crtc->mode.hdisplay > 2048) || |
1388 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1389 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1390 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1391 | goto out_disable; |
1392 | } | |
bed4a673 | 1393 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1394 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1395 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1396 | goto out_disable; |
1397 | } | |
1398 | if (obj_priv->tiling_mode != I915_TILING_X) { | |
28c97730 | 1399 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 1400 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1401 | goto out_disable; |
1402 | } | |
1403 | ||
c924b934 JW |
1404 | /* If the kernel debugger is active, always disable compression */ |
1405 | if (in_dbg_master()) | |
1406 | goto out_disable; | |
1407 | ||
bed4a673 | 1408 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1409 | return; |
1410 | ||
1411 | out_disable: | |
80824003 | 1412 | /* Multiple disables should be harmless */ |
a939406f CW |
1413 | if (intel_fbc_enabled(dev)) { |
1414 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1415 | intel_disable_fbc(dev); |
a939406f | 1416 | } |
80824003 JB |
1417 | } |
1418 | ||
127bd2ac | 1419 | int |
48b956c5 CW |
1420 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
1421 | struct drm_gem_object *obj, | |
1422 | bool pipelined) | |
6b95a207 | 1423 | { |
23010e43 | 1424 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
6b95a207 KH |
1425 | u32 alignment; |
1426 | int ret; | |
1427 | ||
1428 | switch (obj_priv->tiling_mode) { | |
1429 | case I915_TILING_NONE: | |
534843da CW |
1430 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1431 | alignment = 128 * 1024; | |
a6c45cf0 | 1432 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1433 | alignment = 4 * 1024; |
1434 | else | |
1435 | alignment = 64 * 1024; | |
6b95a207 KH |
1436 | break; |
1437 | case I915_TILING_X: | |
1438 | /* pin() will align the object as required by fence */ | |
1439 | alignment = 0; | |
1440 | break; | |
1441 | case I915_TILING_Y: | |
1442 | /* FIXME: Is this true? */ | |
1443 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1444 | return -EINVAL; | |
1445 | default: | |
1446 | BUG(); | |
1447 | } | |
1448 | ||
6b95a207 | 1449 | ret = i915_gem_object_pin(obj, alignment); |
48b956c5 | 1450 | if (ret) |
6b95a207 KH |
1451 | return ret; |
1452 | ||
48b956c5 CW |
1453 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
1454 | if (ret) | |
1455 | goto err_unpin; | |
7213342d | 1456 | |
6b95a207 KH |
1457 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1458 | * fence, whereas 965+ only requires a fence if using | |
1459 | * framebuffer compression. For simplicity, we always install | |
1460 | * a fence as the cost is not that onerous. | |
1461 | */ | |
1462 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE && | |
1463 | obj_priv->tiling_mode != I915_TILING_NONE) { | |
2cf34d7b | 1464 | ret = i915_gem_object_get_fence_reg(obj, false); |
48b956c5 CW |
1465 | if (ret) |
1466 | goto err_unpin; | |
6b95a207 KH |
1467 | } |
1468 | ||
1469 | return 0; | |
48b956c5 CW |
1470 | |
1471 | err_unpin: | |
1472 | i915_gem_object_unpin(obj); | |
1473 | return ret; | |
6b95a207 KH |
1474 | } |
1475 | ||
81255565 JB |
1476 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
1477 | static int | |
1478 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
1479 | int x, int y) | |
1480 | { | |
1481 | struct drm_device *dev = crtc->dev; | |
1482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1483 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1484 | struct intel_framebuffer *intel_fb; | |
1485 | struct drm_i915_gem_object *obj_priv; | |
1486 | struct drm_gem_object *obj; | |
1487 | int plane = intel_crtc->plane; | |
1488 | unsigned long Start, Offset; | |
81255565 | 1489 | u32 dspcntr; |
5eddb70b | 1490 | u32 reg; |
81255565 JB |
1491 | |
1492 | switch (plane) { | |
1493 | case 0: | |
1494 | case 1: | |
1495 | break; | |
1496 | default: | |
1497 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1498 | return -EINVAL; | |
1499 | } | |
1500 | ||
1501 | intel_fb = to_intel_framebuffer(fb); | |
1502 | obj = intel_fb->obj; | |
1503 | obj_priv = to_intel_bo(obj); | |
1504 | ||
5eddb70b CW |
1505 | reg = DSPCNTR(plane); |
1506 | dspcntr = I915_READ(reg); | |
81255565 JB |
1507 | /* Mask out pixel format bits in case we change it */ |
1508 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1509 | switch (fb->bits_per_pixel) { | |
1510 | case 8: | |
1511 | dspcntr |= DISPPLANE_8BPP; | |
1512 | break; | |
1513 | case 16: | |
1514 | if (fb->depth == 15) | |
1515 | dspcntr |= DISPPLANE_15_16BPP; | |
1516 | else | |
1517 | dspcntr |= DISPPLANE_16BPP; | |
1518 | break; | |
1519 | case 24: | |
1520 | case 32: | |
1521 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1522 | break; | |
1523 | default: | |
1524 | DRM_ERROR("Unknown color depth\n"); | |
1525 | return -EINVAL; | |
1526 | } | |
a6c45cf0 | 1527 | if (INTEL_INFO(dev)->gen >= 4) { |
81255565 JB |
1528 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1529 | dspcntr |= DISPPLANE_TILED; | |
1530 | else | |
1531 | dspcntr &= ~DISPPLANE_TILED; | |
1532 | } | |
1533 | ||
4e6cfefc | 1534 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
1535 | /* must disable */ |
1536 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1537 | ||
5eddb70b | 1538 | I915_WRITE(reg, dspcntr); |
81255565 JB |
1539 | |
1540 | Start = obj_priv->gtt_offset; | |
1541 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); | |
1542 | ||
4e6cfefc CW |
1543 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
1544 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 1545 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 1546 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
1547 | I915_WRITE(DSPSURF(plane), Start); |
1548 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
1549 | I915_WRITE(DSPADDR(plane), Offset); | |
1550 | } else | |
1551 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
1552 | POSTING_READ(reg); | |
81255565 | 1553 | |
bed4a673 | 1554 | intel_update_fbc(dev); |
3dec0095 | 1555 | intel_increase_pllclock(crtc); |
81255565 JB |
1556 | |
1557 | return 0; | |
1558 | } | |
1559 | ||
5c3b82e2 | 1560 | static int |
3c4fdcfb KH |
1561 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1562 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1563 | { |
1564 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1565 | struct drm_i915_master_private *master_priv; |
1566 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 1567 | int ret; |
79e53945 JB |
1568 | |
1569 | /* no fb bound */ | |
1570 | if (!crtc->fb) { | |
28c97730 | 1571 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
1572 | return 0; |
1573 | } | |
1574 | ||
265db958 | 1575 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
1576 | case 0: |
1577 | case 1: | |
1578 | break; | |
1579 | default: | |
5c3b82e2 | 1580 | return -EINVAL; |
79e53945 JB |
1581 | } |
1582 | ||
5c3b82e2 | 1583 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
1584 | ret = intel_pin_and_fence_fb_obj(dev, |
1585 | to_intel_framebuffer(crtc->fb)->obj, | |
1586 | false); | |
5c3b82e2 CW |
1587 | if (ret != 0) { |
1588 | mutex_unlock(&dev->struct_mutex); | |
1589 | return ret; | |
1590 | } | |
79e53945 | 1591 | |
265db958 CW |
1592 | if (old_fb) { |
1593 | struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
1594 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1595 | ||
1596 | if (atomic_read(&obj_priv->pending_flip)) { | |
1597 | ret = i915_gem_wait_for_pending_flip(dev, &obj, 1); | |
1598 | if (ret) { | |
1599 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
1600 | mutex_unlock(&dev->struct_mutex); | |
1601 | return ret; | |
1602 | } | |
1603 | } | |
1604 | } | |
1605 | ||
4e6cfefc CW |
1606 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y); |
1607 | if (ret) { | |
265db958 | 1608 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 1609 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 1610 | return ret; |
79e53945 | 1611 | } |
3c4fdcfb | 1612 | |
265db958 CW |
1613 | if (old_fb) |
1614 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); | |
652c393a | 1615 | |
5c3b82e2 | 1616 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1617 | |
1618 | if (!dev->primary->master) | |
5c3b82e2 | 1619 | return 0; |
79e53945 JB |
1620 | |
1621 | master_priv = dev->primary->master->driver_priv; | |
1622 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1623 | return 0; |
79e53945 | 1624 | |
265db958 | 1625 | if (intel_crtc->pipe) { |
79e53945 JB |
1626 | master_priv->sarea_priv->pipeB_x = x; |
1627 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1628 | } else { |
1629 | master_priv->sarea_priv->pipeA_x = x; | |
1630 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1631 | } |
5c3b82e2 CW |
1632 | |
1633 | return 0; | |
79e53945 JB |
1634 | } |
1635 | ||
5eddb70b | 1636 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1637 | { |
1638 | struct drm_device *dev = crtc->dev; | |
1639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1640 | u32 dpa_ctl; | |
1641 | ||
28c97730 | 1642 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1643 | dpa_ctl = I915_READ(DP_A); |
1644 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1645 | ||
1646 | if (clock < 200000) { | |
1647 | u32 temp; | |
1648 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1649 | /* workaround for 160Mhz: | |
1650 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1651 | 2) program 0x46010 bit 0 = 1 | |
1652 | 3) program 0x46034 bit 24 = 1 | |
1653 | 4) program 0x64000 bit 14 = 1 | |
1654 | */ | |
1655 | temp = I915_READ(0x4600c); | |
1656 | temp &= 0xffff0000; | |
1657 | I915_WRITE(0x4600c, temp | 0x8124); | |
1658 | ||
1659 | temp = I915_READ(0x46010); | |
1660 | I915_WRITE(0x46010, temp | 1); | |
1661 | ||
1662 | temp = I915_READ(0x46034); | |
1663 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1664 | } else { | |
1665 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1666 | } | |
1667 | I915_WRITE(DP_A, dpa_ctl); | |
1668 | ||
5eddb70b | 1669 | POSTING_READ(DP_A); |
32f9d658 ZW |
1670 | udelay(500); |
1671 | } | |
1672 | ||
8db9d77b ZW |
1673 | /* The FDI link training functions for ILK/Ibexpeak. */ |
1674 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
1675 | { | |
1676 | struct drm_device *dev = crtc->dev; | |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1679 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1680 | u32 reg, temp, tries; |
8db9d77b | 1681 | |
e1a44743 AJ |
1682 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1683 | for train result */ | |
5eddb70b CW |
1684 | reg = FDI_RX_IMR(pipe); |
1685 | temp = I915_READ(reg); | |
e1a44743 AJ |
1686 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1687 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1688 | I915_WRITE(reg, temp); |
1689 | I915_READ(reg); | |
e1a44743 AJ |
1690 | udelay(150); |
1691 | ||
8db9d77b | 1692 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1693 | reg = FDI_TX_CTL(pipe); |
1694 | temp = I915_READ(reg); | |
77ffb597 AJ |
1695 | temp &= ~(7 << 19); |
1696 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1697 | temp &= ~FDI_LINK_TRAIN_NONE; |
1698 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 1699 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1700 | |
5eddb70b CW |
1701 | reg = FDI_RX_CTL(pipe); |
1702 | temp = I915_READ(reg); | |
8db9d77b ZW |
1703 | temp &= ~FDI_LINK_TRAIN_NONE; |
1704 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
1705 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1706 | ||
1707 | POSTING_READ(reg); | |
8db9d77b ZW |
1708 | udelay(150); |
1709 | ||
5eddb70b | 1710 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1711 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1712 | temp = I915_READ(reg); |
8db9d77b ZW |
1713 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1714 | ||
1715 | if ((temp & FDI_RX_BIT_LOCK)) { | |
1716 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 1717 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1718 | break; |
1719 | } | |
8db9d77b | 1720 | } |
e1a44743 | 1721 | if (tries == 5) |
5eddb70b | 1722 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1723 | |
1724 | /* Train 2 */ | |
5eddb70b CW |
1725 | reg = FDI_TX_CTL(pipe); |
1726 | temp = I915_READ(reg); | |
8db9d77b ZW |
1727 | temp &= ~FDI_LINK_TRAIN_NONE; |
1728 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1729 | I915_WRITE(reg, temp); |
8db9d77b | 1730 | |
5eddb70b CW |
1731 | reg = FDI_RX_CTL(pipe); |
1732 | temp = I915_READ(reg); | |
8db9d77b ZW |
1733 | temp &= ~FDI_LINK_TRAIN_NONE; |
1734 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1735 | I915_WRITE(reg, temp); |
8db9d77b | 1736 | |
5eddb70b CW |
1737 | POSTING_READ(reg); |
1738 | udelay(150); | |
8db9d77b | 1739 | |
5eddb70b | 1740 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1741 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1742 | temp = I915_READ(reg); |
8db9d77b ZW |
1743 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1744 | ||
1745 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1746 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1747 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1748 | break; | |
1749 | } | |
8db9d77b | 1750 | } |
e1a44743 | 1751 | if (tries == 5) |
5eddb70b | 1752 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1753 | |
1754 | DRM_DEBUG_KMS("FDI train done\n"); | |
1755 | } | |
1756 | ||
5eddb70b | 1757 | static const int const snb_b_fdi_train_param [] = { |
8db9d77b ZW |
1758 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
1759 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
1760 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
1761 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
1762 | }; | |
1763 | ||
1764 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
1765 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
1766 | { | |
1767 | struct drm_device *dev = crtc->dev; | |
1768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1769 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1770 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1771 | u32 reg, temp, i; |
8db9d77b | 1772 | |
e1a44743 AJ |
1773 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1774 | for train result */ | |
5eddb70b CW |
1775 | reg = FDI_RX_IMR(pipe); |
1776 | temp = I915_READ(reg); | |
e1a44743 AJ |
1777 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1778 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1779 | I915_WRITE(reg, temp); |
1780 | ||
1781 | POSTING_READ(reg); | |
e1a44743 AJ |
1782 | udelay(150); |
1783 | ||
8db9d77b | 1784 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1785 | reg = FDI_TX_CTL(pipe); |
1786 | temp = I915_READ(reg); | |
77ffb597 AJ |
1787 | temp &= ~(7 << 19); |
1788 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1789 | temp &= ~FDI_LINK_TRAIN_NONE; |
1790 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1791 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1792 | /* SNB-B */ | |
1793 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 1794 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1795 | |
5eddb70b CW |
1796 | reg = FDI_RX_CTL(pipe); |
1797 | temp = I915_READ(reg); | |
8db9d77b ZW |
1798 | if (HAS_PCH_CPT(dev)) { |
1799 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1800 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
1801 | } else { | |
1802 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1803 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1804 | } | |
5eddb70b CW |
1805 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1806 | ||
1807 | POSTING_READ(reg); | |
8db9d77b ZW |
1808 | udelay(150); |
1809 | ||
8db9d77b | 1810 | for (i = 0; i < 4; i++ ) { |
5eddb70b CW |
1811 | reg = FDI_TX_CTL(pipe); |
1812 | temp = I915_READ(reg); | |
8db9d77b ZW |
1813 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1814 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1815 | I915_WRITE(reg, temp); |
1816 | ||
1817 | POSTING_READ(reg); | |
8db9d77b ZW |
1818 | udelay(500); |
1819 | ||
5eddb70b CW |
1820 | reg = FDI_RX_IIR(pipe); |
1821 | temp = I915_READ(reg); | |
8db9d77b ZW |
1822 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1823 | ||
1824 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 1825 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1826 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
1827 | break; | |
1828 | } | |
1829 | } | |
1830 | if (i == 4) | |
5eddb70b | 1831 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1832 | |
1833 | /* Train 2 */ | |
5eddb70b CW |
1834 | reg = FDI_TX_CTL(pipe); |
1835 | temp = I915_READ(reg); | |
8db9d77b ZW |
1836 | temp &= ~FDI_LINK_TRAIN_NONE; |
1837 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1838 | if (IS_GEN6(dev)) { | |
1839 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1840 | /* SNB-B */ | |
1841 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
1842 | } | |
5eddb70b | 1843 | I915_WRITE(reg, temp); |
8db9d77b | 1844 | |
5eddb70b CW |
1845 | reg = FDI_RX_CTL(pipe); |
1846 | temp = I915_READ(reg); | |
8db9d77b ZW |
1847 | if (HAS_PCH_CPT(dev)) { |
1848 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1849 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
1850 | } else { | |
1851 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1852 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1853 | } | |
5eddb70b CW |
1854 | I915_WRITE(reg, temp); |
1855 | ||
1856 | POSTING_READ(reg); | |
8db9d77b ZW |
1857 | udelay(150); |
1858 | ||
1859 | for (i = 0; i < 4; i++ ) { | |
5eddb70b CW |
1860 | reg = FDI_TX_CTL(pipe); |
1861 | temp = I915_READ(reg); | |
8db9d77b ZW |
1862 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1863 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1864 | I915_WRITE(reg, temp); |
1865 | ||
1866 | POSTING_READ(reg); | |
8db9d77b ZW |
1867 | udelay(500); |
1868 | ||
5eddb70b CW |
1869 | reg = FDI_RX_IIR(pipe); |
1870 | temp = I915_READ(reg); | |
8db9d77b ZW |
1871 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1872 | ||
1873 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1874 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1875 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1876 | break; | |
1877 | } | |
1878 | } | |
1879 | if (i == 4) | |
5eddb70b | 1880 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1881 | |
1882 | DRM_DEBUG_KMS("FDI train done.\n"); | |
1883 | } | |
1884 | ||
0e23b99d | 1885 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
2c07245f ZW |
1886 | { |
1887 | struct drm_device *dev = crtc->dev; | |
1888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1890 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1891 | u32 reg, temp; |
79e53945 | 1892 | |
c64e311e | 1893 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
1894 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
1895 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 1896 | |
c98e9dcf | 1897 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
1898 | reg = FDI_RX_CTL(pipe); |
1899 | temp = I915_READ(reg); | |
1900 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 1901 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
1902 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
1903 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
1904 | ||
1905 | POSTING_READ(reg); | |
c98e9dcf JB |
1906 | udelay(200); |
1907 | ||
1908 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
1909 | temp = I915_READ(reg); |
1910 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
1911 | ||
1912 | POSTING_READ(reg); | |
c98e9dcf JB |
1913 | udelay(200); |
1914 | ||
1915 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
1916 | reg = FDI_TX_CTL(pipe); |
1917 | temp = I915_READ(reg); | |
c98e9dcf | 1918 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
1919 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
1920 | ||
1921 | POSTING_READ(reg); | |
c98e9dcf | 1922 | udelay(100); |
6be4a607 | 1923 | } |
0e23b99d JB |
1924 | } |
1925 | ||
5eddb70b CW |
1926 | static void intel_flush_display_plane(struct drm_device *dev, |
1927 | int plane) | |
1928 | { | |
1929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1930 | u32 reg = DSPADDR(plane); | |
1931 | I915_WRITE(reg, I915_READ(reg)); | |
1932 | } | |
1933 | ||
6b383a7f CW |
1934 | /* |
1935 | * When we disable a pipe, we need to clear any pending scanline wait events | |
1936 | * to avoid hanging the ring, which we assume we are waiting on. | |
1937 | */ | |
1938 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
1939 | { | |
1940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1941 | u32 tmp; | |
1942 | ||
1943 | if (IS_GEN2(dev)) | |
1944 | /* Can't break the hang on i8xx */ | |
1945 | return; | |
1946 | ||
1947 | tmp = I915_READ(PRB0_CTL); | |
1948 | if (tmp & RING_WAIT) { | |
1949 | I915_WRITE(PRB0_CTL, tmp); | |
1950 | POSTING_READ(PRB0_CTL); | |
1951 | } | |
1952 | } | |
1953 | ||
0e23b99d JB |
1954 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
1955 | { | |
1956 | struct drm_device *dev = crtc->dev; | |
1957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1959 | int pipe = intel_crtc->pipe; | |
1960 | int plane = intel_crtc->plane; | |
5eddb70b | 1961 | u32 reg, temp; |
0e23b99d | 1962 | |
f7abfe8b CW |
1963 | if (intel_crtc->active) |
1964 | return; | |
1965 | ||
1966 | intel_crtc->active = true; | |
6b383a7f CW |
1967 | intel_update_watermarks(dev); |
1968 | ||
0e23b99d JB |
1969 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
1970 | temp = I915_READ(PCH_LVDS); | |
5eddb70b | 1971 | if ((temp & LVDS_PORT_EN) == 0) |
0e23b99d | 1972 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
0e23b99d JB |
1973 | } |
1974 | ||
1975 | ironlake_fdi_enable(crtc); | |
2c07245f | 1976 | |
6be4a607 JB |
1977 | /* Enable panel fitting for LVDS */ |
1978 | if (dev_priv->pch_pf_size && | |
1979 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) | |
1980 | || HAS_eDP || intel_pch_has_edp(crtc))) { | |
1981 | /* Force use of hard-coded filter coefficients | |
1982 | * as some pre-programmed values are broken, | |
1983 | * e.g. x201. | |
1984 | */ | |
1985 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, | |
1986 | PF_ENABLE | PF_FILTER_MED_3x3); | |
1987 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, | |
1988 | dev_priv->pch_pf_pos); | |
1989 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, | |
1990 | dev_priv->pch_pf_size); | |
1991 | } | |
2c07245f | 1992 | |
6be4a607 | 1993 | /* Enable CPU pipe */ |
5eddb70b CW |
1994 | reg = PIPECONF(pipe); |
1995 | temp = I915_READ(reg); | |
1996 | if ((temp & PIPECONF_ENABLE) == 0) { | |
1997 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
1998 | POSTING_READ(reg); | |
6be4a607 JB |
1999 | udelay(100); |
2000 | } | |
2c07245f | 2001 | |
6be4a607 | 2002 | /* configure and enable CPU plane */ |
5eddb70b CW |
2003 | reg = DSPCNTR(plane); |
2004 | temp = I915_READ(reg); | |
6be4a607 | 2005 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2006 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2007 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2008 | } |
2c07245f | 2009 | |
c98e9dcf JB |
2010 | /* For PCH output, training FDI link */ |
2011 | if (IS_GEN6(dev)) | |
2012 | gen6_fdi_link_train(crtc); | |
2013 | else | |
2014 | ironlake_fdi_link_train(crtc); | |
2c07245f | 2015 | |
c98e9dcf | 2016 | /* enable PCH DPLL */ |
5eddb70b CW |
2017 | reg = PCH_DPLL(pipe); |
2018 | temp = I915_READ(reg); | |
c98e9dcf | 2019 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2020 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
2021 | POSTING_READ(reg); | |
8c4223be | 2022 | udelay(200); |
c98e9dcf | 2023 | } |
8db9d77b | 2024 | |
c98e9dcf JB |
2025 | if (HAS_PCH_CPT(dev)) { |
2026 | /* Be sure PCH DPLL SEL is set */ | |
2027 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2028 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2029 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2030 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2031 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2032 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2033 | } |
5eddb70b | 2034 | |
c98e9dcf | 2035 | /* set transcoder timing */ |
5eddb70b CW |
2036 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2037 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2038 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2039 | |
5eddb70b CW |
2040 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2041 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2042 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2043 | |
c98e9dcf | 2044 | /* enable normal train */ |
5eddb70b CW |
2045 | reg = FDI_TX_CTL(pipe); |
2046 | temp = I915_READ(reg); | |
c98e9dcf | 2047 | temp &= ~FDI_LINK_TRAIN_NONE; |
5eddb70b CW |
2048 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; |
2049 | I915_WRITE(reg, temp); | |
e3421a18 | 2050 | |
5eddb70b CW |
2051 | reg = FDI_RX_CTL(pipe); |
2052 | temp = I915_READ(reg); | |
c98e9dcf JB |
2053 | if (HAS_PCH_CPT(dev)) { |
2054 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2055 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2056 | } else { | |
2057 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2058 | temp |= FDI_LINK_TRAIN_NONE; | |
2059 | } | |
5eddb70b | 2060 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); |
e3421a18 | 2061 | |
c98e9dcf | 2062 | /* wait one idle pattern time */ |
5eddb70b | 2063 | POSTING_READ(reg); |
c98e9dcf JB |
2064 | udelay(100); |
2065 | ||
2066 | /* For PCH DP, enable TRANS_DP_CTL */ | |
2067 | if (HAS_PCH_CPT(dev) && | |
2068 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5eddb70b CW |
2069 | reg = TRANS_DP_CTL(pipe); |
2070 | temp = I915_READ(reg); | |
2071 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
2072 | TRANS_DP_SYNC_MASK); | |
2073 | temp |= (TRANS_DP_OUTPUT_ENABLE | | |
2074 | TRANS_DP_ENH_FRAMING); | |
c98e9dcf JB |
2075 | |
2076 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2077 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2078 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2079 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2080 | |
2081 | switch (intel_trans_dp_port_sel(crtc)) { | |
2082 | case PCH_DP_B: | |
5eddb70b | 2083 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2084 | break; |
2085 | case PCH_DP_C: | |
5eddb70b | 2086 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2087 | break; |
2088 | case PCH_DP_D: | |
5eddb70b | 2089 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2090 | break; |
2091 | default: | |
2092 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2093 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2094 | break; |
32f9d658 | 2095 | } |
2c07245f | 2096 | |
5eddb70b | 2097 | I915_WRITE(reg, temp); |
6be4a607 | 2098 | } |
b52eb4dc | 2099 | |
c98e9dcf | 2100 | /* enable PCH transcoder */ |
5eddb70b CW |
2101 | reg = TRANSCONF(pipe); |
2102 | temp = I915_READ(reg); | |
c98e9dcf JB |
2103 | /* |
2104 | * make the BPC in transcoder be consistent with | |
2105 | * that in pipeconf reg. | |
2106 | */ | |
2107 | temp &= ~PIPE_BPC_MASK; | |
5eddb70b CW |
2108 | temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; |
2109 | I915_WRITE(reg, temp | TRANS_ENABLE); | |
2110 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
c98e9dcf JB |
2111 | DRM_ERROR("failed to enable transcoder\n"); |
2112 | ||
6be4a607 | 2113 | intel_crtc_load_lut(crtc); |
bed4a673 | 2114 | intel_update_fbc(dev); |
6b383a7f | 2115 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2116 | } |
2117 | ||
2118 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2119 | { | |
2120 | struct drm_device *dev = crtc->dev; | |
2121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2123 | int pipe = intel_crtc->pipe; | |
2124 | int plane = intel_crtc->plane; | |
5eddb70b | 2125 | u32 reg, temp; |
b52eb4dc | 2126 | |
f7abfe8b CW |
2127 | if (!intel_crtc->active) |
2128 | return; | |
2129 | ||
6be4a607 | 2130 | drm_vblank_off(dev, pipe); |
6b383a7f | 2131 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2132 | |
6be4a607 | 2133 | /* Disable display plane */ |
5eddb70b CW |
2134 | reg = DSPCNTR(plane); |
2135 | temp = I915_READ(reg); | |
2136 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2137 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
2138 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2139 | } |
913d8d11 | 2140 | |
6be4a607 JB |
2141 | if (dev_priv->cfb_plane == plane && |
2142 | dev_priv->display.disable_fbc) | |
2143 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2144 | |
6be4a607 | 2145 | /* disable cpu pipe, disable after all planes disabled */ |
5eddb70b CW |
2146 | reg = PIPECONF(pipe); |
2147 | temp = I915_READ(reg); | |
2148 | if (temp & PIPECONF_ENABLE) { | |
2149 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
6be4a607 | 2150 | /* wait for cpu pipe off, pipe state */ |
5eddb70b | 2151 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50)) |
6be4a607 | 2152 | DRM_ERROR("failed to turn off cpu pipe\n"); |
5eddb70b | 2153 | } |
32f9d658 | 2154 | |
6be4a607 JB |
2155 | /* Disable PF */ |
2156 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); | |
2157 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); | |
2c07245f | 2158 | |
6be4a607 | 2159 | /* disable CPU FDI tx and PCH FDI rx */ |
5eddb70b CW |
2160 | reg = FDI_TX_CTL(pipe); |
2161 | temp = I915_READ(reg); | |
2162 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2163 | POSTING_READ(reg); | |
249c0e64 | 2164 | |
5eddb70b CW |
2165 | reg = FDI_RX_CTL(pipe); |
2166 | temp = I915_READ(reg); | |
2167 | temp &= ~(0x7 << 16); | |
2168 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2169 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
6be4a607 | 2170 | |
5eddb70b | 2171 | POSTING_READ(reg); |
6be4a607 JB |
2172 | udelay(100); |
2173 | ||
2174 | /* still set train pattern 1 */ | |
5eddb70b CW |
2175 | reg = FDI_TX_CTL(pipe); |
2176 | temp = I915_READ(reg); | |
6be4a607 JB |
2177 | temp &= ~FDI_LINK_TRAIN_NONE; |
2178 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2179 | I915_WRITE(reg, temp); |
6be4a607 | 2180 | |
5eddb70b CW |
2181 | reg = FDI_RX_CTL(pipe); |
2182 | temp = I915_READ(reg); | |
6be4a607 JB |
2183 | if (HAS_PCH_CPT(dev)) { |
2184 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2185 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2186 | } else { | |
2c07245f ZW |
2187 | temp &= ~FDI_LINK_TRAIN_NONE; |
2188 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
6be4a607 | 2189 | } |
5eddb70b CW |
2190 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2191 | temp &= ~(0x07 << 16); | |
2192 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2193 | I915_WRITE(reg, temp); | |
2c07245f | 2194 | |
5eddb70b | 2195 | POSTING_READ(reg); |
6be4a607 | 2196 | udelay(100); |
2c07245f | 2197 | |
6be4a607 JB |
2198 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2199 | temp = I915_READ(PCH_LVDS); | |
5eddb70b CW |
2200 | if (temp & LVDS_PORT_EN) { |
2201 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); | |
2202 | POSTING_READ(PCH_LVDS); | |
2203 | udelay(100); | |
2204 | } | |
6be4a607 | 2205 | } |
249c0e64 | 2206 | |
6be4a607 | 2207 | /* disable PCH transcoder */ |
5eddb70b CW |
2208 | reg = TRANSCONF(plane); |
2209 | temp = I915_READ(reg); | |
2210 | if (temp & TRANS_ENABLE) { | |
2211 | I915_WRITE(reg, temp & ~TRANS_ENABLE); | |
6be4a607 | 2212 | /* wait for PCH transcoder off, transcoder state */ |
5eddb70b | 2213 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
6be4a607 JB |
2214 | DRM_ERROR("failed to disable transcoder\n"); |
2215 | } | |
913d8d11 | 2216 | |
6be4a607 JB |
2217 | if (HAS_PCH_CPT(dev)) { |
2218 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2219 | reg = TRANS_DP_CTL(pipe); |
2220 | temp = I915_READ(reg); | |
2221 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
2222 | I915_WRITE(reg, temp); | |
6be4a607 JB |
2223 | |
2224 | /* disable DPLL_SEL */ | |
2225 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2226 | if (pipe == 0) |
6be4a607 JB |
2227 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
2228 | else | |
2229 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
2230 | I915_WRITE(PCH_DPLL_SEL, temp); | |
6be4a607 | 2231 | } |
e3421a18 | 2232 | |
6be4a607 | 2233 | /* disable PCH DPLL */ |
5eddb70b CW |
2234 | reg = PCH_DPLL(pipe); |
2235 | temp = I915_READ(reg); | |
2236 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
8db9d77b | 2237 | |
6be4a607 | 2238 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2239 | reg = FDI_RX_CTL(pipe); |
2240 | temp = I915_READ(reg); | |
2241 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2242 | |
6be4a607 | 2243 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2244 | reg = FDI_TX_CTL(pipe); |
2245 | temp = I915_READ(reg); | |
2246 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2247 | ||
2248 | POSTING_READ(reg); | |
6be4a607 | 2249 | udelay(100); |
8db9d77b | 2250 | |
5eddb70b CW |
2251 | reg = FDI_RX_CTL(pipe); |
2252 | temp = I915_READ(reg); | |
2253 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2254 | |
6be4a607 | 2255 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2256 | POSTING_READ(reg); |
6be4a607 | 2257 | udelay(100); |
6b383a7f | 2258 | |
f7abfe8b | 2259 | intel_crtc->active = false; |
6b383a7f CW |
2260 | intel_update_watermarks(dev); |
2261 | intel_update_fbc(dev); | |
2262 | intel_clear_scanline_wait(dev); | |
6be4a607 | 2263 | } |
1b3c7a47 | 2264 | |
6be4a607 JB |
2265 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2266 | { | |
2267 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2268 | int pipe = intel_crtc->pipe; | |
2269 | int plane = intel_crtc->plane; | |
8db9d77b | 2270 | |
6be4a607 JB |
2271 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2272 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2273 | */ | |
2274 | switch (mode) { | |
2275 | case DRM_MODE_DPMS_ON: | |
2276 | case DRM_MODE_DPMS_STANDBY: | |
2277 | case DRM_MODE_DPMS_SUSPEND: | |
2278 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2279 | ironlake_crtc_enable(crtc); | |
2280 | break; | |
1b3c7a47 | 2281 | |
6be4a607 JB |
2282 | case DRM_MODE_DPMS_OFF: |
2283 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2284 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2285 | break; |
2286 | } | |
2287 | } | |
2288 | ||
02e792fb DV |
2289 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2290 | { | |
02e792fb | 2291 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2292 | struct drm_device *dev = intel_crtc->base.dev; |
03f77ea5 | 2293 | |
23f09ce3 CW |
2294 | mutex_lock(&dev->struct_mutex); |
2295 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); | |
2296 | mutex_unlock(&dev->struct_mutex); | |
02e792fb | 2297 | } |
02e792fb | 2298 | |
5dcdbcb0 CW |
2299 | /* Let userspace switch the overlay on again. In most cases userspace |
2300 | * has to recompute where to put it anyway. | |
2301 | */ | |
02e792fb DV |
2302 | } |
2303 | ||
0b8765c6 | 2304 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2305 | { |
2306 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2307 | struct drm_i915_private *dev_priv = dev->dev_private; |
2308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2309 | int pipe = intel_crtc->pipe; | |
80824003 | 2310 | int plane = intel_crtc->plane; |
5eddb70b | 2311 | u32 reg, temp; |
79e53945 | 2312 | |
f7abfe8b CW |
2313 | if (intel_crtc->active) |
2314 | return; | |
2315 | ||
2316 | intel_crtc->active = true; | |
6b383a7f CW |
2317 | intel_update_watermarks(dev); |
2318 | ||
0b8765c6 | 2319 | /* Enable the DPLL */ |
5eddb70b CW |
2320 | reg = DPLL(pipe); |
2321 | temp = I915_READ(reg); | |
0b8765c6 | 2322 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2323 | I915_WRITE(reg, temp); |
2324 | ||
0b8765c6 | 2325 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2326 | POSTING_READ(reg); |
0b8765c6 | 2327 | udelay(150); |
5eddb70b CW |
2328 | |
2329 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2330 | ||
0b8765c6 | 2331 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2332 | POSTING_READ(reg); |
0b8765c6 | 2333 | udelay(150); |
5eddb70b CW |
2334 | |
2335 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2336 | ||
0b8765c6 | 2337 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2338 | POSTING_READ(reg); |
0b8765c6 JB |
2339 | udelay(150); |
2340 | } | |
79e53945 | 2341 | |
0b8765c6 | 2342 | /* Enable the pipe */ |
5eddb70b CW |
2343 | reg = PIPECONF(pipe); |
2344 | temp = I915_READ(reg); | |
2345 | if ((temp & PIPECONF_ENABLE) == 0) | |
2346 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
79e53945 | 2347 | |
0b8765c6 | 2348 | /* Enable the plane */ |
5eddb70b CW |
2349 | reg = DSPCNTR(plane); |
2350 | temp = I915_READ(reg); | |
0b8765c6 | 2351 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2352 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2353 | intel_flush_display_plane(dev, plane); | |
0b8765c6 | 2354 | } |
79e53945 | 2355 | |
0b8765c6 | 2356 | intel_crtc_load_lut(crtc); |
bed4a673 | 2357 | intel_update_fbc(dev); |
79e53945 | 2358 | |
0b8765c6 JB |
2359 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2360 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 2361 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 2362 | } |
79e53945 | 2363 | |
0b8765c6 JB |
2364 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2365 | { | |
2366 | struct drm_device *dev = crtc->dev; | |
2367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2369 | int pipe = intel_crtc->pipe; | |
2370 | int plane = intel_crtc->plane; | |
5eddb70b | 2371 | u32 reg, temp; |
b690e96c | 2372 | |
f7abfe8b CW |
2373 | if (!intel_crtc->active) |
2374 | return; | |
2375 | ||
0b8765c6 JB |
2376 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
2377 | intel_crtc_dpms_overlay(intel_crtc, false); | |
6b383a7f | 2378 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 JB |
2379 | drm_vblank_off(dev, pipe); |
2380 | ||
2381 | if (dev_priv->cfb_plane == plane && | |
2382 | dev_priv->display.disable_fbc) | |
2383 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 2384 | |
0b8765c6 | 2385 | /* Disable display plane */ |
5eddb70b CW |
2386 | reg = DSPCNTR(plane); |
2387 | temp = I915_READ(reg); | |
2388 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2389 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
0b8765c6 | 2390 | /* Flush the plane changes */ |
5eddb70b | 2391 | intel_flush_display_plane(dev, plane); |
0b8765c6 | 2392 | |
0b8765c6 | 2393 | /* Wait for vblank for the disable to take effect */ |
a6c45cf0 | 2394 | if (IS_GEN2(dev)) |
5eddb70b | 2395 | intel_wait_for_vblank_off(dev, pipe); |
0b8765c6 | 2396 | } |
79e53945 | 2397 | |
0b8765c6 | 2398 | /* Don't disable pipe A or pipe A PLLs if needed */ |
5eddb70b | 2399 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
6b383a7f | 2400 | goto done; |
0b8765c6 JB |
2401 | |
2402 | /* Next, disable display pipes */ | |
5eddb70b CW |
2403 | reg = PIPECONF(pipe); |
2404 | temp = I915_READ(reg); | |
2405 | if (temp & PIPECONF_ENABLE) { | |
2406 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
2407 | ||
2408 | /* Wait for vblank for the disable to take effect. */ | |
2409 | POSTING_READ(reg); | |
2410 | intel_wait_for_vblank_off(dev, pipe); | |
0b8765c6 JB |
2411 | } |
2412 | ||
5eddb70b CW |
2413 | reg = DPLL(pipe); |
2414 | temp = I915_READ(reg); | |
2415 | if (temp & DPLL_VCO_ENABLE) { | |
2416 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
0b8765c6 | 2417 | |
5eddb70b CW |
2418 | /* Wait for the clocks to turn off. */ |
2419 | POSTING_READ(reg); | |
2420 | udelay(150); | |
0b8765c6 | 2421 | } |
6b383a7f CW |
2422 | |
2423 | done: | |
f7abfe8b | 2424 | intel_crtc->active = false; |
6b383a7f CW |
2425 | intel_update_fbc(dev); |
2426 | intel_update_watermarks(dev); | |
2427 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
2428 | } |
2429 | ||
2430 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2431 | { | |
2432 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2433 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2434 | */ | |
2435 | switch (mode) { | |
2436 | case DRM_MODE_DPMS_ON: | |
2437 | case DRM_MODE_DPMS_STANDBY: | |
2438 | case DRM_MODE_DPMS_SUSPEND: | |
2439 | i9xx_crtc_enable(crtc); | |
2440 | break; | |
2441 | case DRM_MODE_DPMS_OFF: | |
2442 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2443 | break; |
2444 | } | |
2c07245f ZW |
2445 | } |
2446 | ||
2447 | /** | |
2448 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2449 | */ |
2450 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2451 | { | |
2452 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2453 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2454 | struct drm_i915_master_private *master_priv; |
2455 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2456 | int pipe = intel_crtc->pipe; | |
2457 | bool enabled; | |
2458 | ||
032d2a0d CW |
2459 | if (intel_crtc->dpms_mode == mode) |
2460 | return; | |
2461 | ||
65655d4a | 2462 | intel_crtc->dpms_mode = mode; |
debcaddc | 2463 | |
e70236a8 | 2464 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
2465 | |
2466 | if (!dev->primary->master) | |
2467 | return; | |
2468 | ||
2469 | master_priv = dev->primary->master->driver_priv; | |
2470 | if (!master_priv->sarea_priv) | |
2471 | return; | |
2472 | ||
2473 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2474 | ||
2475 | switch (pipe) { | |
2476 | case 0: | |
2477 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2478 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2479 | break; | |
2480 | case 1: | |
2481 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2482 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2483 | break; | |
2484 | default: | |
2485 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
2486 | break; | |
2487 | } | |
79e53945 JB |
2488 | } |
2489 | ||
7e7d76c3 JB |
2490 | /* Prepare for a mode set. |
2491 | * | |
2492 | * Note we could be a lot smarter here. We need to figure out which outputs | |
2493 | * will be enabled, which disabled (in short, how the config will changes) | |
2494 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
2495 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
2496 | * panel fitting is in the proper state, etc. | |
2497 | */ | |
2498 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 2499 | { |
7e7d76c3 | 2500 | i9xx_crtc_disable(crtc); |
79e53945 JB |
2501 | } |
2502 | ||
7e7d76c3 | 2503 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 2504 | { |
7e7d76c3 | 2505 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
2506 | } |
2507 | ||
2508 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
2509 | { | |
7e7d76c3 | 2510 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
2511 | } |
2512 | ||
2513 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
2514 | { | |
7e7d76c3 | 2515 | ironlake_crtc_enable(crtc); |
79e53945 JB |
2516 | } |
2517 | ||
2518 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
2519 | { | |
2520 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2521 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
2522 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
2523 | } | |
2524 | ||
2525 | void intel_encoder_commit (struct drm_encoder *encoder) | |
2526 | { | |
2527 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2528 | /* lvds has its own version of commit see intel_lvds_commit */ | |
2529 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2530 | } | |
2531 | ||
ea5b213a CW |
2532 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2533 | { | |
4ef69c7a | 2534 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 2535 | |
ea5b213a CW |
2536 | drm_encoder_cleanup(encoder); |
2537 | kfree(intel_encoder); | |
2538 | } | |
2539 | ||
79e53945 JB |
2540 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
2541 | struct drm_display_mode *mode, | |
2542 | struct drm_display_mode *adjusted_mode) | |
2543 | { | |
2c07245f | 2544 | struct drm_device *dev = crtc->dev; |
89749350 | 2545 | |
bad720ff | 2546 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 2547 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
2548 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
2549 | return false; | |
2c07245f | 2550 | } |
89749350 CW |
2551 | |
2552 | /* XXX some encoders set the crtcinfo, others don't. | |
2553 | * Obviously we need some form of conflict resolution here... | |
2554 | */ | |
2555 | if (adjusted_mode->crtc_htotal == 0) | |
2556 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
2557 | ||
79e53945 JB |
2558 | return true; |
2559 | } | |
2560 | ||
e70236a8 JB |
2561 | static int i945_get_display_clock_speed(struct drm_device *dev) |
2562 | { | |
2563 | return 400000; | |
2564 | } | |
79e53945 | 2565 | |
e70236a8 | 2566 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 2567 | { |
e70236a8 JB |
2568 | return 333000; |
2569 | } | |
79e53945 | 2570 | |
e70236a8 JB |
2571 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
2572 | { | |
2573 | return 200000; | |
2574 | } | |
79e53945 | 2575 | |
e70236a8 JB |
2576 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
2577 | { | |
2578 | u16 gcfgc = 0; | |
79e53945 | 2579 | |
e70236a8 JB |
2580 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
2581 | ||
2582 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
2583 | return 133000; | |
2584 | else { | |
2585 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
2586 | case GC_DISPLAY_CLOCK_333_MHZ: | |
2587 | return 333000; | |
2588 | default: | |
2589 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
2590 | return 190000; | |
79e53945 | 2591 | } |
e70236a8 JB |
2592 | } |
2593 | } | |
2594 | ||
2595 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
2596 | { | |
2597 | return 266000; | |
2598 | } | |
2599 | ||
2600 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
2601 | { | |
2602 | u16 hpllcc = 0; | |
2603 | /* Assume that the hardware is in the high speed state. This | |
2604 | * should be the default. | |
2605 | */ | |
2606 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
2607 | case GC_CLOCK_133_200: | |
2608 | case GC_CLOCK_100_200: | |
2609 | return 200000; | |
2610 | case GC_CLOCK_166_250: | |
2611 | return 250000; | |
2612 | case GC_CLOCK_100_133: | |
79e53945 | 2613 | return 133000; |
e70236a8 | 2614 | } |
79e53945 | 2615 | |
e70236a8 JB |
2616 | /* Shouldn't happen */ |
2617 | return 0; | |
2618 | } | |
79e53945 | 2619 | |
e70236a8 JB |
2620 | static int i830_get_display_clock_speed(struct drm_device *dev) |
2621 | { | |
2622 | return 133000; | |
79e53945 JB |
2623 | } |
2624 | ||
2c07245f ZW |
2625 | struct fdi_m_n { |
2626 | u32 tu; | |
2627 | u32 gmch_m; | |
2628 | u32 gmch_n; | |
2629 | u32 link_m; | |
2630 | u32 link_n; | |
2631 | }; | |
2632 | ||
2633 | static void | |
2634 | fdi_reduce_ratio(u32 *num, u32 *den) | |
2635 | { | |
2636 | while (*num > 0xffffff || *den > 0xffffff) { | |
2637 | *num >>= 1; | |
2638 | *den >>= 1; | |
2639 | } | |
2640 | } | |
2641 | ||
2642 | #define DATA_N 0x800000 | |
2643 | #define LINK_N 0x80000 | |
2644 | ||
2645 | static void | |
f2b115e6 AJ |
2646 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
2647 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f ZW |
2648 | { |
2649 | u64 temp; | |
2650 | ||
2651 | m_n->tu = 64; /* default size */ | |
2652 | ||
2653 | temp = (u64) DATA_N * pixel_clock; | |
2654 | temp = div_u64(temp, link_clock); | |
58a27471 ZW |
2655 | m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes); |
2656 | m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */ | |
2c07245f ZW |
2657 | m_n->gmch_n = DATA_N; |
2658 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
2659 | ||
2660 | temp = (u64) LINK_N * pixel_clock; | |
2661 | m_n->link_m = div_u64(temp, link_clock); | |
2662 | m_n->link_n = LINK_N; | |
2663 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
2664 | } | |
2665 | ||
2666 | ||
7662c8bd SL |
2667 | struct intel_watermark_params { |
2668 | unsigned long fifo_size; | |
2669 | unsigned long max_wm; | |
2670 | unsigned long default_wm; | |
2671 | unsigned long guard_size; | |
2672 | unsigned long cacheline_size; | |
2673 | }; | |
2674 | ||
f2b115e6 AJ |
2675 | /* Pineview has different values for various configs */ |
2676 | static struct intel_watermark_params pineview_display_wm = { | |
2677 | PINEVIEW_DISPLAY_FIFO, | |
2678 | PINEVIEW_MAX_WM, | |
2679 | PINEVIEW_DFT_WM, | |
2680 | PINEVIEW_GUARD_WM, | |
2681 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2682 | }; |
f2b115e6 AJ |
2683 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
2684 | PINEVIEW_DISPLAY_FIFO, | |
2685 | PINEVIEW_MAX_WM, | |
2686 | PINEVIEW_DFT_HPLLOFF_WM, | |
2687 | PINEVIEW_GUARD_WM, | |
2688 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2689 | }; |
f2b115e6 AJ |
2690 | static struct intel_watermark_params pineview_cursor_wm = { |
2691 | PINEVIEW_CURSOR_FIFO, | |
2692 | PINEVIEW_CURSOR_MAX_WM, | |
2693 | PINEVIEW_CURSOR_DFT_WM, | |
2694 | PINEVIEW_CURSOR_GUARD_WM, | |
2695 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 2696 | }; |
f2b115e6 AJ |
2697 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
2698 | PINEVIEW_CURSOR_FIFO, | |
2699 | PINEVIEW_CURSOR_MAX_WM, | |
2700 | PINEVIEW_CURSOR_DFT_WM, | |
2701 | PINEVIEW_CURSOR_GUARD_WM, | |
2702 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2703 | }; |
0e442c60 JB |
2704 | static struct intel_watermark_params g4x_wm_info = { |
2705 | G4X_FIFO_SIZE, | |
2706 | G4X_MAX_WM, | |
2707 | G4X_MAX_WM, | |
2708 | 2, | |
2709 | G4X_FIFO_LINE_SIZE, | |
2710 | }; | |
4fe5e611 ZY |
2711 | static struct intel_watermark_params g4x_cursor_wm_info = { |
2712 | I965_CURSOR_FIFO, | |
2713 | I965_CURSOR_MAX_WM, | |
2714 | I965_CURSOR_DFT_WM, | |
2715 | 2, | |
2716 | G4X_FIFO_LINE_SIZE, | |
2717 | }; | |
2718 | static struct intel_watermark_params i965_cursor_wm_info = { | |
2719 | I965_CURSOR_FIFO, | |
2720 | I965_CURSOR_MAX_WM, | |
2721 | I965_CURSOR_DFT_WM, | |
2722 | 2, | |
2723 | I915_FIFO_LINE_SIZE, | |
2724 | }; | |
7662c8bd | 2725 | static struct intel_watermark_params i945_wm_info = { |
dff33cfc | 2726 | I945_FIFO_SIZE, |
7662c8bd SL |
2727 | I915_MAX_WM, |
2728 | 1, | |
dff33cfc JB |
2729 | 2, |
2730 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
2731 | }; |
2732 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 2733 | I915_FIFO_SIZE, |
7662c8bd SL |
2734 | I915_MAX_WM, |
2735 | 1, | |
dff33cfc | 2736 | 2, |
7662c8bd SL |
2737 | I915_FIFO_LINE_SIZE |
2738 | }; | |
2739 | static struct intel_watermark_params i855_wm_info = { | |
2740 | I855GM_FIFO_SIZE, | |
2741 | I915_MAX_WM, | |
2742 | 1, | |
dff33cfc | 2743 | 2, |
7662c8bd SL |
2744 | I830_FIFO_LINE_SIZE |
2745 | }; | |
2746 | static struct intel_watermark_params i830_wm_info = { | |
2747 | I830_FIFO_SIZE, | |
2748 | I915_MAX_WM, | |
2749 | 1, | |
dff33cfc | 2750 | 2, |
7662c8bd SL |
2751 | I830_FIFO_LINE_SIZE |
2752 | }; | |
2753 | ||
7f8a8569 ZW |
2754 | static struct intel_watermark_params ironlake_display_wm_info = { |
2755 | ILK_DISPLAY_FIFO, | |
2756 | ILK_DISPLAY_MAXWM, | |
2757 | ILK_DISPLAY_DFTWM, | |
2758 | 2, | |
2759 | ILK_FIFO_LINE_SIZE | |
2760 | }; | |
2761 | ||
c936f44d ZY |
2762 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
2763 | ILK_CURSOR_FIFO, | |
2764 | ILK_CURSOR_MAXWM, | |
2765 | ILK_CURSOR_DFTWM, | |
2766 | 2, | |
2767 | ILK_FIFO_LINE_SIZE | |
2768 | }; | |
2769 | ||
7f8a8569 ZW |
2770 | static struct intel_watermark_params ironlake_display_srwm_info = { |
2771 | ILK_DISPLAY_SR_FIFO, | |
2772 | ILK_DISPLAY_MAX_SRWM, | |
2773 | ILK_DISPLAY_DFT_SRWM, | |
2774 | 2, | |
2775 | ILK_FIFO_LINE_SIZE | |
2776 | }; | |
2777 | ||
2778 | static struct intel_watermark_params ironlake_cursor_srwm_info = { | |
2779 | ILK_CURSOR_SR_FIFO, | |
2780 | ILK_CURSOR_MAX_SRWM, | |
2781 | ILK_CURSOR_DFT_SRWM, | |
2782 | 2, | |
2783 | ILK_FIFO_LINE_SIZE | |
2784 | }; | |
2785 | ||
dff33cfc JB |
2786 | /** |
2787 | * intel_calculate_wm - calculate watermark level | |
2788 | * @clock_in_khz: pixel clock | |
2789 | * @wm: chip FIFO params | |
2790 | * @pixel_size: display pixel size | |
2791 | * @latency_ns: memory latency for the platform | |
2792 | * | |
2793 | * Calculate the watermark level (the level at which the display plane will | |
2794 | * start fetching from memory again). Each chip has a different display | |
2795 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
2796 | * in the correct intel_watermark_params structure. | |
2797 | * | |
2798 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
2799 | * on the pixel size. When it reaches the watermark level, it'll start | |
2800 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
2801 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
2802 | * will occur, and a display engine hang could result. | |
2803 | */ | |
7662c8bd SL |
2804 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
2805 | struct intel_watermark_params *wm, | |
2806 | int pixel_size, | |
2807 | unsigned long latency_ns) | |
2808 | { | |
390c4dd4 | 2809 | long entries_required, wm_size; |
dff33cfc | 2810 | |
d660467c JB |
2811 | /* |
2812 | * Note: we need to make sure we don't overflow for various clock & | |
2813 | * latency values. | |
2814 | * clocks go from a few thousand to several hundred thousand. | |
2815 | * latency is usually a few thousand | |
2816 | */ | |
2817 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
2818 | 1000; | |
8de9b311 | 2819 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 2820 | |
28c97730 | 2821 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc JB |
2822 | |
2823 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
2824 | ||
28c97730 | 2825 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 2826 | |
390c4dd4 JB |
2827 | /* Don't promote wm_size to unsigned... */ |
2828 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 2829 | wm_size = wm->max_wm; |
c3add4b6 | 2830 | if (wm_size <= 0) |
7662c8bd SL |
2831 | wm_size = wm->default_wm; |
2832 | return wm_size; | |
2833 | } | |
2834 | ||
2835 | struct cxsr_latency { | |
2836 | int is_desktop; | |
95534263 | 2837 | int is_ddr3; |
7662c8bd SL |
2838 | unsigned long fsb_freq; |
2839 | unsigned long mem_freq; | |
2840 | unsigned long display_sr; | |
2841 | unsigned long display_hpll_disable; | |
2842 | unsigned long cursor_sr; | |
2843 | unsigned long cursor_hpll_disable; | |
2844 | }; | |
2845 | ||
403c89ff | 2846 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
2847 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
2848 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
2849 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
2850 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
2851 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
2852 | ||
2853 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
2854 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
2855 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
2856 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
2857 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
2858 | ||
2859 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
2860 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
2861 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
2862 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
2863 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
2864 | ||
2865 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
2866 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
2867 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
2868 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
2869 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
2870 | ||
2871 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
2872 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
2873 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
2874 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
2875 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
2876 | ||
2877 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
2878 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
2879 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
2880 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
2881 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
2882 | }; |
2883 | ||
403c89ff CW |
2884 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
2885 | int is_ddr3, | |
2886 | int fsb, | |
2887 | int mem) | |
7662c8bd | 2888 | { |
403c89ff | 2889 | const struct cxsr_latency *latency; |
7662c8bd | 2890 | int i; |
7662c8bd SL |
2891 | |
2892 | if (fsb == 0 || mem == 0) | |
2893 | return NULL; | |
2894 | ||
2895 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
2896 | latency = &cxsr_latency_table[i]; | |
2897 | if (is_desktop == latency->is_desktop && | |
95534263 | 2898 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
2899 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
2900 | return latency; | |
7662c8bd | 2901 | } |
decbbcda | 2902 | |
28c97730 | 2903 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
2904 | |
2905 | return NULL; | |
7662c8bd SL |
2906 | } |
2907 | ||
f2b115e6 | 2908 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
2909 | { |
2910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
2911 | |
2912 | /* deactivate cxsr */ | |
3e33d94d | 2913 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
2914 | } |
2915 | ||
bcc24fb4 JB |
2916 | /* |
2917 | * Latency for FIFO fetches is dependent on several factors: | |
2918 | * - memory configuration (speed, channels) | |
2919 | * - chipset | |
2920 | * - current MCH state | |
2921 | * It can be fairly high in some situations, so here we assume a fairly | |
2922 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
2923 | * set this value too high, the FIFO will fetch frequently to stay full) | |
2924 | * and power consumption (set it too low to save power and we might see | |
2925 | * FIFO underruns and display "flicker"). | |
2926 | * | |
2927 | * A value of 5us seems to be a good balance; safe for very low end | |
2928 | * platforms but not overly aggressive on lower latency configs. | |
2929 | */ | |
69e302a9 | 2930 | static const int latency_ns = 5000; |
7662c8bd | 2931 | |
e70236a8 | 2932 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
2933 | { |
2934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2935 | uint32_t dsparb = I915_READ(DSPARB); | |
2936 | int size; | |
2937 | ||
8de9b311 CW |
2938 | size = dsparb & 0x7f; |
2939 | if (plane) | |
2940 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 2941 | |
28c97730 | 2942 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 2943 | plane ? "B" : "A", size); |
dff33cfc JB |
2944 | |
2945 | return size; | |
2946 | } | |
7662c8bd | 2947 | |
e70236a8 JB |
2948 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
2949 | { | |
2950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2951 | uint32_t dsparb = I915_READ(DSPARB); | |
2952 | int size; | |
2953 | ||
8de9b311 CW |
2954 | size = dsparb & 0x1ff; |
2955 | if (plane) | |
2956 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 2957 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 2958 | |
28c97730 | 2959 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 2960 | plane ? "B" : "A", size); |
dff33cfc JB |
2961 | |
2962 | return size; | |
2963 | } | |
7662c8bd | 2964 | |
e70236a8 JB |
2965 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
2966 | { | |
2967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2968 | uint32_t dsparb = I915_READ(DSPARB); | |
2969 | int size; | |
2970 | ||
2971 | size = dsparb & 0x7f; | |
2972 | size >>= 2; /* Convert to cachelines */ | |
2973 | ||
28c97730 | 2974 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
2975 | plane ? "B" : "A", |
2976 | size); | |
e70236a8 JB |
2977 | |
2978 | return size; | |
2979 | } | |
2980 | ||
2981 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
2982 | { | |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2984 | uint32_t dsparb = I915_READ(DSPARB); | |
2985 | int size; | |
2986 | ||
2987 | size = dsparb & 0x7f; | |
2988 | size >>= 1; /* Convert to cachelines */ | |
2989 | ||
28c97730 | 2990 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 2991 | plane ? "B" : "A", size); |
e70236a8 JB |
2992 | |
2993 | return size; | |
2994 | } | |
2995 | ||
d4294342 | 2996 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
5eddb70b CW |
2997 | int planeb_clock, int sr_hdisplay, int unused, |
2998 | int pixel_size) | |
d4294342 ZY |
2999 | { |
3000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403c89ff | 3001 | const struct cxsr_latency *latency; |
d4294342 ZY |
3002 | u32 reg; |
3003 | unsigned long wm; | |
d4294342 ZY |
3004 | int sr_clock; |
3005 | ||
403c89ff | 3006 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3007 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3008 | if (!latency) { |
3009 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3010 | pineview_disable_cxsr(dev); | |
3011 | return; | |
3012 | } | |
3013 | ||
3014 | if (!planea_clock || !planeb_clock) { | |
3015 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
3016 | ||
3017 | /* Display SR */ | |
3018 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, | |
3019 | pixel_size, latency->display_sr); | |
3020 | reg = I915_READ(DSPFW1); | |
3021 | reg &= ~DSPFW_SR_MASK; | |
3022 | reg |= wm << DSPFW_SR_SHIFT; | |
3023 | I915_WRITE(DSPFW1, reg); | |
3024 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3025 | ||
3026 | /* cursor SR */ | |
3027 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, | |
3028 | pixel_size, latency->cursor_sr); | |
3029 | reg = I915_READ(DSPFW3); | |
3030 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3031 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3032 | I915_WRITE(DSPFW3, reg); | |
3033 | ||
3034 | /* Display HPLL off SR */ | |
3035 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, | |
3036 | pixel_size, latency->display_hpll_disable); | |
3037 | reg = I915_READ(DSPFW3); | |
3038 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3039 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3040 | I915_WRITE(DSPFW3, reg); | |
3041 | ||
3042 | /* cursor HPLL off SR */ | |
3043 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, | |
3044 | pixel_size, latency->cursor_hpll_disable); | |
3045 | reg = I915_READ(DSPFW3); | |
3046 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3047 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3048 | I915_WRITE(DSPFW3, reg); | |
3049 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3050 | ||
3051 | /* activate cxsr */ | |
3e33d94d CW |
3052 | I915_WRITE(DSPFW3, |
3053 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3054 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3055 | } else { | |
3056 | pineview_disable_cxsr(dev); | |
3057 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3058 | } | |
3059 | } | |
3060 | ||
0e442c60 | 3061 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3062 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3063 | int pixel_size) | |
652c393a JB |
3064 | { |
3065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e442c60 JB |
3066 | int total_size, cacheline_size; |
3067 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | |
3068 | struct intel_watermark_params planea_params, planeb_params; | |
3069 | unsigned long line_time_us; | |
3070 | int sr_clock, sr_entries = 0, entries_required; | |
652c393a | 3071 | |
0e442c60 JB |
3072 | /* Create copies of the base settings for each pipe */ |
3073 | planea_params = planeb_params = g4x_wm_info; | |
3074 | ||
3075 | /* Grab a couple of global values before we overwrite them */ | |
3076 | total_size = planea_params.fifo_size; | |
3077 | cacheline_size = planea_params.cacheline_size; | |
3078 | ||
3079 | /* | |
3080 | * Note: we need to make sure we don't overflow for various clock & | |
3081 | * latency values. | |
3082 | * clocks go from a few thousand to several hundred thousand. | |
3083 | * latency is usually a few thousand | |
3084 | */ | |
3085 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | |
3086 | 1000; | |
8de9b311 | 3087 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3088 | planea_wm = entries_required + planea_params.guard_size; |
3089 | ||
3090 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | |
3091 | 1000; | |
8de9b311 | 3092 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3093 | planeb_wm = entries_required + planeb_params.guard_size; |
3094 | ||
3095 | cursora_wm = cursorb_wm = 16; | |
3096 | cursor_sr = 32; | |
3097 | ||
3098 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
3099 | ||
3100 | /* Calc sr entries for one plane configs */ | |
3101 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3102 | /* self-refresh has much higher latency */ | |
69e302a9 | 3103 | static const int sr_latency_ns = 12000; |
0e442c60 JB |
3104 | |
3105 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3106 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
0e442c60 JB |
3107 | |
3108 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3109 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3110 | pixel_size * sr_hdisplay; |
8de9b311 | 3111 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
4fe5e611 ZY |
3112 | |
3113 | entries_required = (((sr_latency_ns / line_time_us) + | |
3114 | 1000) / 1000) * pixel_size * 64; | |
8de9b311 | 3115 | entries_required = DIV_ROUND_UP(entries_required, |
5eddb70b | 3116 | g4x_cursor_wm_info.cacheline_size); |
4fe5e611 ZY |
3117 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
3118 | ||
3119 | if (cursor_sr > g4x_cursor_wm_info.max_wm) | |
3120 | cursor_sr = g4x_cursor_wm_info.max_wm; | |
3121 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3122 | "cursor %d\n", sr_entries, cursor_sr); | |
3123 | ||
0e442c60 | 3124 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3125 | } else { |
3126 | /* Turn off self refresh if both pipes are enabled */ | |
3127 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
5eddb70b | 3128 | & ~FW_BLC_SELF_EN); |
0e442c60 JB |
3129 | } |
3130 | ||
3131 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | |
3132 | planea_wm, planeb_wm, sr_entries); | |
3133 | ||
3134 | planea_wm &= 0x3f; | |
3135 | planeb_wm &= 0x3f; | |
3136 | ||
3137 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | |
3138 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
3139 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | |
3140 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
3141 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
3142 | /* HPLL off in SR has some issues on G4x... disable it */ | |
3143 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
3144 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
652c393a JB |
3145 | } |
3146 | ||
1dc7546d | 3147 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3148 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3149 | int pixel_size) | |
7662c8bd SL |
3150 | { |
3151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dc7546d JB |
3152 | unsigned long line_time_us; |
3153 | int sr_clock, sr_entries, srwm = 1; | |
4fe5e611 | 3154 | int cursor_sr = 16; |
1dc7546d JB |
3155 | |
3156 | /* Calc sr entries for one plane configs */ | |
3157 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3158 | /* self-refresh has much higher latency */ | |
69e302a9 | 3159 | static const int sr_latency_ns = 12000; |
1dc7546d JB |
3160 | |
3161 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3162 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
1dc7546d JB |
3163 | |
3164 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3165 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3166 | pixel_size * sr_hdisplay; |
8de9b311 | 3167 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
1dc7546d | 3168 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
1b07e04e | 3169 | srwm = I965_FIFO_SIZE - sr_entries; |
1dc7546d JB |
3170 | if (srwm < 0) |
3171 | srwm = 1; | |
1b07e04e | 3172 | srwm &= 0x1ff; |
4fe5e611 ZY |
3173 | |
3174 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
5eddb70b | 3175 | pixel_size * 64; |
8de9b311 CW |
3176 | sr_entries = DIV_ROUND_UP(sr_entries, |
3177 | i965_cursor_wm_info.cacheline_size); | |
4fe5e611 | 3178 | cursor_sr = i965_cursor_wm_info.fifo_size - |
5eddb70b | 3179 | (sr_entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
3180 | |
3181 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3182 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3183 | ||
3184 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3185 | "cursor %d\n", srwm, cursor_sr); | |
3186 | ||
a6c45cf0 | 3187 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 3188 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3189 | } else { |
3190 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 3191 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
3192 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
3193 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3194 | } |
7662c8bd | 3195 | |
1dc7546d JB |
3196 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3197 | srwm); | |
7662c8bd SL |
3198 | |
3199 | /* 965 has limitations... */ | |
1dc7546d JB |
3200 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
3201 | (8 << 0)); | |
7662c8bd | 3202 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
3203 | /* update cursor SR watermark */ |
3204 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
3205 | } |
3206 | ||
3207 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3208 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3209 | int pixel_size) | |
7662c8bd SL |
3210 | { |
3211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
3212 | uint32_t fwater_lo; |
3213 | uint32_t fwater_hi; | |
3214 | int total_size, cacheline_size, cwm, srwm = 1; | |
3215 | int planea_wm, planeb_wm; | |
3216 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
3217 | unsigned long line_time_us; |
3218 | int sr_clock, sr_entries = 0; | |
3219 | ||
dff33cfc | 3220 | /* Create copies of the base settings for each pipe */ |
a6c45cf0 | 3221 | if (IS_CRESTLINE(dev) || IS_I945GM(dev)) |
dff33cfc | 3222 | planea_params = planeb_params = i945_wm_info; |
a6c45cf0 | 3223 | else if (!IS_GEN2(dev)) |
dff33cfc | 3224 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 3225 | else |
dff33cfc | 3226 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 3227 | |
dff33cfc JB |
3228 | /* Grab a couple of global values before we overwrite them */ |
3229 | total_size = planea_params.fifo_size; | |
3230 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 3231 | |
dff33cfc | 3232 | /* Update per-plane FIFO sizes */ |
e70236a8 JB |
3233 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
3234 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
7662c8bd | 3235 | |
dff33cfc JB |
3236 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
3237 | pixel_size, latency_ns); | |
3238 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
3239 | pixel_size, latency_ns); | |
28c97730 | 3240 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
3241 | |
3242 | /* | |
3243 | * Overlay gets an aggressive default since video jitter is bad. | |
3244 | */ | |
3245 | cwm = 2; | |
3246 | ||
dff33cfc | 3247 | /* Calc sr entries for one plane configs */ |
652c393a JB |
3248 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
3249 | (!planea_clock || !planeb_clock)) { | |
dff33cfc | 3250 | /* self-refresh has much higher latency */ |
69e302a9 | 3251 | static const int sr_latency_ns = 6000; |
dff33cfc | 3252 | |
7662c8bd | 3253 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
fa143215 | 3254 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
dff33cfc JB |
3255 | |
3256 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3257 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3258 | pixel_size * sr_hdisplay; |
8de9b311 | 3259 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
28c97730 | 3260 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
dff33cfc JB |
3261 | srwm = total_size - sr_entries; |
3262 | if (srwm < 0) | |
3263 | srwm = 1; | |
ee980b80 LP |
3264 | |
3265 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
3266 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
3267 | else if (IS_I915GM(dev)) { | |
3268 | /* 915M has a smaller SRWM field */ | |
3269 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
3270 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
3271 | } | |
33c5fd12 DJ |
3272 | } else { |
3273 | /* Turn off self refresh if both pipes are enabled */ | |
ee980b80 LP |
3274 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
3275 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3276 | & ~FW_BLC_SELF_EN); | |
3277 | } else if (IS_I915GM(dev)) { | |
3278 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
3279 | } | |
7662c8bd SL |
3280 | } |
3281 | ||
28c97730 | 3282 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 3283 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 3284 | |
dff33cfc JB |
3285 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
3286 | fwater_hi = (cwm & 0x1f); | |
3287 | ||
3288 | /* Set request length to 8 cachelines per fetch */ | |
3289 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
3290 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
3291 | |
3292 | I915_WRITE(FW_BLC, fwater_lo); | |
3293 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
3294 | } |
3295 | ||
e70236a8 | 3296 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
fa143215 | 3297 | int unused2, int unused3, int pixel_size) |
7662c8bd SL |
3298 | { |
3299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f3601326 | 3300 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
dff33cfc | 3301 | int planea_wm; |
7662c8bd | 3302 | |
e70236a8 | 3303 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
7662c8bd | 3304 | |
dff33cfc JB |
3305 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
3306 | pixel_size, latency_ns); | |
f3601326 JB |
3307 | fwater_lo |= (3<<8) | planea_wm; |
3308 | ||
28c97730 | 3309 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
3310 | |
3311 | I915_WRITE(FW_BLC, fwater_lo); | |
3312 | } | |
3313 | ||
7f8a8569 | 3314 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 3315 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 3316 | |
4ed765f9 CW |
3317 | static bool ironlake_compute_wm0(struct drm_device *dev, |
3318 | int pipe, | |
3319 | int *plane_wm, | |
3320 | int *cursor_wm) | |
7f8a8569 | 3321 | { |
c936f44d | 3322 | struct drm_crtc *crtc; |
4ed765f9 CW |
3323 | int htotal, hdisplay, clock, pixel_size = 0; |
3324 | int line_time_us, line_count, entries; | |
c936f44d | 3325 | |
4ed765f9 CW |
3326 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
3327 | if (crtc->fb == NULL || !crtc->enabled) | |
3328 | return false; | |
7f8a8569 | 3329 | |
4ed765f9 CW |
3330 | htotal = crtc->mode.htotal; |
3331 | hdisplay = crtc->mode.hdisplay; | |
3332 | clock = crtc->mode.clock; | |
3333 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3334 | ||
3335 | /* Use the small buffer method to calculate plane watermark */ | |
3336 | entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000; | |
3337 | entries = DIV_ROUND_UP(entries, | |
3338 | ironlake_display_wm_info.cacheline_size); | |
3339 | *plane_wm = entries + ironlake_display_wm_info.guard_size; | |
3340 | if (*plane_wm > (int)ironlake_display_wm_info.max_wm) | |
3341 | *plane_wm = ironlake_display_wm_info.max_wm; | |
3342 | ||
3343 | /* Use the large buffer method to calculate cursor watermark */ | |
3344 | line_time_us = ((htotal * 1000) / clock); | |
3345 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; | |
3346 | entries = line_count * 64 * pixel_size; | |
3347 | entries = DIV_ROUND_UP(entries, | |
3348 | ironlake_cursor_wm_info.cacheline_size); | |
3349 | *cursor_wm = entries + ironlake_cursor_wm_info.guard_size; | |
3350 | if (*cursor_wm > ironlake_cursor_wm_info.max_wm) | |
3351 | *cursor_wm = ironlake_cursor_wm_info.max_wm; | |
7f8a8569 | 3352 | |
4ed765f9 CW |
3353 | return true; |
3354 | } | |
c936f44d | 3355 | |
4ed765f9 CW |
3356 | static void ironlake_update_wm(struct drm_device *dev, |
3357 | int planea_clock, int planeb_clock, | |
3358 | int sr_hdisplay, int sr_htotal, | |
3359 | int pixel_size) | |
3360 | { | |
3361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3362 | int plane_wm, cursor_wm, enabled; | |
3363 | int tmp; | |
c936f44d | 3364 | |
4ed765f9 CW |
3365 | enabled = 0; |
3366 | if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) { | |
3367 | I915_WRITE(WM0_PIPEA_ILK, | |
3368 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3369 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3370 | " plane %d, " "cursor: %d\n", | |
3371 | plane_wm, cursor_wm); | |
3372 | enabled++; | |
3373 | } | |
c936f44d | 3374 | |
4ed765f9 CW |
3375 | if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) { |
3376 | I915_WRITE(WM0_PIPEB_ILK, | |
3377 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3378 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3379 | " plane %d, cursor: %d\n", | |
3380 | plane_wm, cursor_wm); | |
3381 | enabled++; | |
7f8a8569 ZW |
3382 | } |
3383 | ||
3384 | /* | |
3385 | * Calculate and update the self-refresh watermark only when one | |
3386 | * display plane is used. | |
3387 | */ | |
4ed765f9 CW |
3388 | tmp = 0; |
3389 | if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) { | |
3390 | unsigned long line_time_us; | |
3391 | int small, large, plane_fbc; | |
3392 | int sr_clock, entries; | |
3393 | int line_count, line_size; | |
7f8a8569 ZW |
3394 | /* Read the self-refresh latency. The unit is 0.5us */ |
3395 | int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK; | |
3396 | ||
3397 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
4ed765f9 | 3398 | line_time_us = (sr_htotal * 1000) / sr_clock; |
7f8a8569 ZW |
3399 | |
3400 | /* Use ns/us then divide to preserve precision */ | |
3401 | line_count = ((ilk_sr_latency * 500) / line_time_us + 1000) | |
5eddb70b | 3402 | / 1000; |
4ed765f9 | 3403 | line_size = sr_hdisplay * pixel_size; |
7f8a8569 | 3404 | |
4ed765f9 CW |
3405 | /* Use the minimum of the small and large buffer method for primary */ |
3406 | small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000; | |
3407 | large = line_count * line_size; | |
7f8a8569 | 3408 | |
4ed765f9 CW |
3409 | entries = DIV_ROUND_UP(min(small, large), |
3410 | ironlake_display_srwm_info.cacheline_size); | |
7f8a8569 | 3411 | |
4ed765f9 CW |
3412 | plane_fbc = entries * 64; |
3413 | plane_fbc = DIV_ROUND_UP(plane_fbc, line_size); | |
7f8a8569 | 3414 | |
4ed765f9 CW |
3415 | plane_wm = entries + ironlake_display_srwm_info.guard_size; |
3416 | if (plane_wm > (int)ironlake_display_srwm_info.max_wm) | |
3417 | plane_wm = ironlake_display_srwm_info.max_wm; | |
7f8a8569 | 3418 | |
4ed765f9 CW |
3419 | /* calculate the self-refresh watermark for display cursor */ |
3420 | entries = line_count * pixel_size * 64; | |
3421 | entries = DIV_ROUND_UP(entries, | |
3422 | ironlake_cursor_srwm_info.cacheline_size); | |
3423 | ||
3424 | cursor_wm = entries + ironlake_cursor_srwm_info.guard_size; | |
3425 | if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm) | |
3426 | cursor_wm = ironlake_cursor_srwm_info.max_wm; | |
3427 | ||
3428 | /* configure watermark and enable self-refresh */ | |
3429 | tmp = (WM1_LP_SR_EN | | |
3430 | (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | | |
3431 | (plane_fbc << WM1_LP_FBC_SHIFT) | | |
3432 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3433 | cursor_wm); | |
3434 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d," | |
3435 | " cursor %d\n", plane_wm, plane_fbc, cursor_wm); | |
7f8a8569 | 3436 | } |
4ed765f9 CW |
3437 | I915_WRITE(WM1_LP_ILK, tmp); |
3438 | /* XXX setup WM2 and WM3 */ | |
7f8a8569 | 3439 | } |
4ed765f9 | 3440 | |
7662c8bd SL |
3441 | /** |
3442 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3443 | * | |
3444 | * Calculate watermark values for the various WM regs based on current mode | |
3445 | * and plane configuration. | |
3446 | * | |
3447 | * There are several cases to deal with here: | |
3448 | * - normal (i.e. non-self-refresh) | |
3449 | * - self-refresh (SR) mode | |
3450 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3451 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3452 | * lines), so need to account for TLB latency | |
3453 | * | |
3454 | * The normal calculation is: | |
3455 | * watermark = dotclock * bytes per pixel * latency | |
3456 | * where latency is platform & configuration dependent (we assume pessimal | |
3457 | * values here). | |
3458 | * | |
3459 | * The SR calculation is: | |
3460 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3461 | * bytes per pixel | |
3462 | * where | |
3463 | * line time = htotal / dotclock | |
fa143215 | 3464 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
3465 | * and latency is assumed to be high, as above. |
3466 | * | |
3467 | * The final value programmed to the register should always be rounded up, | |
3468 | * and include an extra 2 entries to account for clock crossings. | |
3469 | * | |
3470 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3471 | * to set the non-SR watermarks to 8. | |
5eddb70b | 3472 | */ |
7662c8bd SL |
3473 | static void intel_update_watermarks(struct drm_device *dev) |
3474 | { | |
e70236a8 | 3475 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 3476 | struct drm_crtc *crtc; |
7662c8bd SL |
3477 | int sr_hdisplay = 0; |
3478 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
3479 | int enabled = 0, pixel_size = 0; | |
fa143215 | 3480 | int sr_htotal = 0; |
7662c8bd | 3481 | |
c03342fa ZW |
3482 | if (!dev_priv->display.update_wm) |
3483 | return; | |
3484 | ||
7662c8bd SL |
3485 | /* Get the clock config from both planes */ |
3486 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc | 3487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f7abfe8b | 3488 | if (intel_crtc->active) { |
7662c8bd SL |
3489 | enabled++; |
3490 | if (intel_crtc->plane == 0) { | |
28c97730 | 3491 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
5eddb70b | 3492 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3493 | planea_clock = crtc->mode.clock; |
3494 | } else { | |
28c97730 | 3495 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
5eddb70b | 3496 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3497 | planeb_clock = crtc->mode.clock; |
3498 | } | |
3499 | sr_hdisplay = crtc->mode.hdisplay; | |
3500 | sr_clock = crtc->mode.clock; | |
fa143215 | 3501 | sr_htotal = crtc->mode.htotal; |
7662c8bd SL |
3502 | if (crtc->fb) |
3503 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3504 | else | |
3505 | pixel_size = 4; /* by default */ | |
3506 | } | |
3507 | } | |
3508 | ||
3509 | if (enabled <= 0) | |
3510 | return; | |
3511 | ||
e70236a8 | 3512 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
fa143215 | 3513 | sr_hdisplay, sr_htotal, pixel_size); |
7662c8bd SL |
3514 | } |
3515 | ||
5c3b82e2 CW |
3516 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
3517 | struct drm_display_mode *mode, | |
3518 | struct drm_display_mode *adjusted_mode, | |
3519 | int x, int y, | |
3520 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3521 | { |
3522 | struct drm_device *dev = crtc->dev; | |
3523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3524 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3525 | int pipe = intel_crtc->pipe; | |
80824003 | 3526 | int plane = intel_crtc->plane; |
5eddb70b | 3527 | u32 fp_reg, dpll_reg; |
c751ce4f | 3528 | int refclk, num_connectors = 0; |
652c393a | 3529 | intel_clock_t clock, reduced_clock; |
5eddb70b | 3530 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 3531 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 3532 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 3533 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 3534 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 3535 | struct intel_encoder *encoder; |
d4906093 | 3536 | const intel_limit_t *limit; |
5c3b82e2 | 3537 | int ret; |
2c07245f | 3538 | struct fdi_m_n m_n = {0}; |
5eddb70b | 3539 | u32 reg, temp; |
5eb08b69 | 3540 | int target_clock; |
79e53945 JB |
3541 | |
3542 | drm_vblank_pre_modeset(dev, pipe); | |
3543 | ||
5eddb70b CW |
3544 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
3545 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
3546 | continue; |
3547 | ||
5eddb70b | 3548 | switch (encoder->type) { |
79e53945 JB |
3549 | case INTEL_OUTPUT_LVDS: |
3550 | is_lvds = true; | |
3551 | break; | |
3552 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3553 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3554 | is_sdvo = true; |
5eddb70b | 3555 | if (encoder->needs_tv_clock) |
e2f0ba97 | 3556 | is_tv = true; |
79e53945 JB |
3557 | break; |
3558 | case INTEL_OUTPUT_DVO: | |
3559 | is_dvo = true; | |
3560 | break; | |
3561 | case INTEL_OUTPUT_TVOUT: | |
3562 | is_tv = true; | |
3563 | break; | |
3564 | case INTEL_OUTPUT_ANALOG: | |
3565 | is_crt = true; | |
3566 | break; | |
a4fc5ed6 KP |
3567 | case INTEL_OUTPUT_DISPLAYPORT: |
3568 | is_dp = true; | |
3569 | break; | |
32f9d658 | 3570 | case INTEL_OUTPUT_EDP: |
5eddb70b | 3571 | has_edp_encoder = encoder; |
32f9d658 | 3572 | break; |
79e53945 | 3573 | } |
43565a06 | 3574 | |
c751ce4f | 3575 | num_connectors++; |
79e53945 JB |
3576 | } |
3577 | ||
c751ce4f | 3578 | if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { |
43565a06 | 3579 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 3580 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 3581 | refclk / 1000); |
a6c45cf0 | 3582 | } else if (!IS_GEN2(dev)) { |
79e53945 | 3583 | refclk = 96000; |
bad720ff | 3584 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3585 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
3586 | } else { |
3587 | refclk = 48000; | |
3588 | } | |
3589 | ||
d4906093 ML |
3590 | /* |
3591 | * Returns a set of divisors for the desired target clock with the given | |
3592 | * refclk, or FALSE. The returned values represent the clock equation: | |
3593 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
3594 | */ | |
3595 | limit = intel_limit(crtc); | |
3596 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
3597 | if (!ok) { |
3598 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 3599 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 3600 | return -EINVAL; |
79e53945 JB |
3601 | } |
3602 | ||
cda4b7d3 | 3603 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 3604 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 3605 | |
ddc9003c ZY |
3606 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
3607 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
3608 | dev_priv->lvds_downclock, |
3609 | refclk, | |
3610 | &reduced_clock); | |
18f9ed12 ZY |
3611 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
3612 | /* | |
3613 | * If the different P is found, it means that we can't | |
3614 | * switch the display clock by using the FP0/FP1. | |
3615 | * In such case we will disable the LVDS downclock | |
3616 | * feature. | |
3617 | */ | |
3618 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 3619 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
3620 | has_reduced_clock = 0; |
3621 | } | |
652c393a | 3622 | } |
7026d4ac ZW |
3623 | /* SDVO TV has fixed PLL values depend on its clock range, |
3624 | this mirrors vbios setting. */ | |
3625 | if (is_sdvo && is_tv) { | |
3626 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 3627 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
3628 | clock.p1 = 2; |
3629 | clock.p2 = 10; | |
3630 | clock.n = 3; | |
3631 | clock.m1 = 16; | |
3632 | clock.m2 = 8; | |
3633 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 3634 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
3635 | clock.p1 = 1; |
3636 | clock.p2 = 10; | |
3637 | clock.n = 6; | |
3638 | clock.m1 = 12; | |
3639 | clock.m2 = 8; | |
3640 | } | |
3641 | } | |
3642 | ||
2c07245f | 3643 | /* FDI link */ |
bad720ff | 3644 | if (HAS_PCH_SPLIT(dev)) { |
77ffb597 | 3645 | int lane = 0, link_bw, bpp; |
32f9d658 ZW |
3646 | /* eDP doesn't require FDI link, so just set DP M/N |
3647 | according to current link config */ | |
8e647a27 | 3648 | if (has_edp_encoder) { |
5eb08b69 | 3649 | target_clock = mode->clock; |
8e647a27 CW |
3650 | intel_edp_link_config(has_edp_encoder, |
3651 | &lane, &link_bw); | |
32f9d658 ZW |
3652 | } else { |
3653 | /* DP over FDI requires target mode clock | |
3654 | instead of link clock */ | |
3655 | if (is_dp) | |
3656 | target_clock = mode->clock; | |
3657 | else | |
3658 | target_clock = adjusted_mode->clock; | |
021357ac CW |
3659 | |
3660 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
3661 | * each output octet as 10 bits. The actual frequency | |
3662 | * is stored as a divider into a 100MHz clock, and the | |
3663 | * mode pixel clock is stored in units of 1KHz. | |
3664 | * Hence the bw of each lane in terms of the mode signal | |
3665 | * is: | |
3666 | */ | |
3667 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
32f9d658 | 3668 | } |
58a27471 ZW |
3669 | |
3670 | /* determine panel color depth */ | |
5eddb70b | 3671 | temp = I915_READ(PIPECONF(pipe)); |
e5a95eb7 ZY |
3672 | temp &= ~PIPE_BPC_MASK; |
3673 | if (is_lvds) { | |
e5a95eb7 | 3674 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
5eddb70b | 3675 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
e5a95eb7 ZY |
3676 | temp |= PIPE_8BPC; |
3677 | else | |
3678 | temp |= PIPE_6BPC; | |
8e647a27 | 3679 | } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) { |
885a5fb5 ZW |
3680 | switch (dev_priv->edp_bpp/3) { |
3681 | case 8: | |
3682 | temp |= PIPE_8BPC; | |
3683 | break; | |
3684 | case 10: | |
3685 | temp |= PIPE_10BPC; | |
3686 | break; | |
3687 | case 6: | |
3688 | temp |= PIPE_6BPC; | |
3689 | break; | |
3690 | case 12: | |
3691 | temp |= PIPE_12BPC; | |
3692 | break; | |
3693 | } | |
e5a95eb7 ZY |
3694 | } else |
3695 | temp |= PIPE_8BPC; | |
5eddb70b | 3696 | I915_WRITE(PIPECONF(pipe), temp); |
58a27471 ZW |
3697 | |
3698 | switch (temp & PIPE_BPC_MASK) { | |
3699 | case PIPE_8BPC: | |
3700 | bpp = 24; | |
3701 | break; | |
3702 | case PIPE_10BPC: | |
3703 | bpp = 30; | |
3704 | break; | |
3705 | case PIPE_6BPC: | |
3706 | bpp = 18; | |
3707 | break; | |
3708 | case PIPE_12BPC: | |
3709 | bpp = 36; | |
3710 | break; | |
3711 | default: | |
3712 | DRM_ERROR("unknown pipe bpc value\n"); | |
3713 | bpp = 24; | |
3714 | } | |
3715 | ||
77ffb597 AJ |
3716 | if (!lane) { |
3717 | /* | |
3718 | * Account for spread spectrum to avoid | |
3719 | * oversubscribing the link. Max center spread | |
3720 | * is 2.5%; use 5% for safety's sake. | |
3721 | */ | |
3722 | u32 bps = target_clock * bpp * 21 / 20; | |
3723 | lane = bps / (link_bw * 8) + 1; | |
3724 | } | |
3725 | ||
3726 | intel_crtc->fdi_lanes = lane; | |
3727 | ||
f2b115e6 | 3728 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 3729 | } |
2c07245f | 3730 | |
c038e51e ZW |
3731 | /* Ironlake: try to setup display ref clock before DPLL |
3732 | * enabling. This is only under driver's control after | |
3733 | * PCH B stepping, previous chipset stepping should be | |
3734 | * ignoring this setting. | |
3735 | */ | |
bad720ff | 3736 | if (HAS_PCH_SPLIT(dev)) { |
c038e51e ZW |
3737 | temp = I915_READ(PCH_DREF_CONTROL); |
3738 | /* Always enable nonspread source */ | |
3739 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
3740 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
c038e51e ZW |
3741 | temp &= ~DREF_SSC_SOURCE_MASK; |
3742 | temp |= DREF_SSC_SOURCE_ENABLE; | |
3743 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 3744 | |
5eddb70b | 3745 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
3746 | udelay(200); |
3747 | ||
8e647a27 | 3748 | if (has_edp_encoder) { |
c038e51e ZW |
3749 | if (dev_priv->lvds_use_ssc) { |
3750 | temp |= DREF_SSC1_ENABLE; | |
3751 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 3752 | |
5eddb70b | 3753 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
3754 | udelay(200); |
3755 | ||
3756 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
3757 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
c038e51e ZW |
3758 | } else { |
3759 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
c038e51e | 3760 | } |
5eddb70b | 3761 | I915_WRITE(PCH_DREF_CONTROL, temp); |
c038e51e ZW |
3762 | } |
3763 | } | |
3764 | ||
f2b115e6 | 3765 | if (IS_PINEVIEW(dev)) { |
2177832f | 3766 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3767 | if (has_reduced_clock) |
3768 | fp2 = (1 << reduced_clock.n) << 16 | | |
3769 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
3770 | } else { | |
2177832f | 3771 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3772 | if (has_reduced_clock) |
3773 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
3774 | reduced_clock.m2; | |
3775 | } | |
79e53945 | 3776 | |
5eddb70b | 3777 | dpll = 0; |
bad720ff | 3778 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
3779 | dpll = DPLL_VGA_MODE_DIS; |
3780 | ||
a6c45cf0 | 3781 | if (!IS_GEN2(dev)) { |
79e53945 JB |
3782 | if (is_lvds) |
3783 | dpll |= DPLLB_MODE_LVDS; | |
3784 | else | |
3785 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
3786 | if (is_sdvo) { | |
6c9547ff CW |
3787 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
3788 | if (pixel_multiplier > 1) { | |
3789 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
3790 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
3791 | else if (HAS_PCH_SPLIT(dev)) | |
3792 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
3793 | } | |
79e53945 | 3794 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 3795 | } |
a4fc5ed6 KP |
3796 | if (is_dp) |
3797 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 JB |
3798 | |
3799 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
3800 | if (IS_PINEVIEW(dev)) |
3801 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 3802 | else { |
2177832f | 3803 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 3804 | /* also FPA1 */ |
bad720ff | 3805 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3806 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
3807 | if (IS_G4X(dev) && has_reduced_clock) |
3808 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 3809 | } |
79e53945 JB |
3810 | switch (clock.p2) { |
3811 | case 5: | |
3812 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
3813 | break; | |
3814 | case 7: | |
3815 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
3816 | break; | |
3817 | case 10: | |
3818 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
3819 | break; | |
3820 | case 14: | |
3821 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
3822 | break; | |
3823 | } | |
a6c45cf0 | 3824 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
3825 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
3826 | } else { | |
3827 | if (is_lvds) { | |
3828 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3829 | } else { | |
3830 | if (clock.p1 == 2) | |
3831 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
3832 | else | |
3833 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3834 | if (clock.p2 == 4) | |
3835 | dpll |= PLL_P2_DIVIDE_BY_4; | |
3836 | } | |
3837 | } | |
3838 | ||
43565a06 KH |
3839 | if (is_sdvo && is_tv) |
3840 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
3841 | else if (is_tv) | |
79e53945 | 3842 | /* XXX: just matching BIOS for now */ |
43565a06 | 3843 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 3844 | dpll |= 3; |
c751ce4f | 3845 | else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) |
43565a06 | 3846 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
3847 | else |
3848 | dpll |= PLL_REF_INPUT_DREFCLK; | |
3849 | ||
3850 | /* setup pipeconf */ | |
5eddb70b | 3851 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
3852 | |
3853 | /* Set up the display plane register */ | |
3854 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
3855 | ||
f2b115e6 | 3856 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 3857 | enable color space conversion */ |
bad720ff | 3858 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 3859 | if (pipe == 0) |
80824003 | 3860 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
3861 | else |
3862 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3863 | } | |
79e53945 | 3864 | |
a6c45cf0 | 3865 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
3866 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
3867 | * core speed. | |
3868 | * | |
3869 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
3870 | * pipe == 0 check? | |
3871 | */ | |
e70236a8 JB |
3872 | if (mode->clock > |
3873 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 3874 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 3875 | else |
5eddb70b | 3876 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
3877 | } |
3878 | ||
8d86dc6a | 3879 | dspcntr |= DISPLAY_PLANE_ENABLE; |
5eddb70b | 3880 | pipeconf |= PIPECONF_ENABLE; |
8d86dc6a LT |
3881 | dpll |= DPLL_VCO_ENABLE; |
3882 | ||
28c97730 | 3883 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
3884 | drm_mode_debug_printmodeline(mode); |
3885 | ||
f2b115e6 | 3886 | /* assign to Ironlake registers */ |
bad720ff | 3887 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
3888 | fp_reg = PCH_FP0(pipe); |
3889 | dpll_reg = PCH_DPLL(pipe); | |
3890 | } else { | |
3891 | fp_reg = FP0(pipe); | |
3892 | dpll_reg = DPLL(pipe); | |
2c07245f | 3893 | } |
79e53945 | 3894 | |
8e647a27 | 3895 | if (!has_edp_encoder) { |
79e53945 JB |
3896 | I915_WRITE(fp_reg, fp); |
3897 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b CW |
3898 | |
3899 | POSTING_READ(dpll_reg); | |
79e53945 JB |
3900 | udelay(150); |
3901 | } | |
3902 | ||
8db9d77b ZW |
3903 | /* enable transcoder DPLL */ |
3904 | if (HAS_PCH_CPT(dev)) { | |
3905 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b CW |
3906 | if (pipe == 0) |
3907 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; | |
8db9d77b | 3908 | else |
5eddb70b | 3909 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
8db9d77b | 3910 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
3911 | |
3912 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
3913 | udelay(150); |
3914 | } | |
3915 | ||
79e53945 JB |
3916 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
3917 | * This is an exception to the general rule that mode_set doesn't turn | |
3918 | * things on. | |
3919 | */ | |
3920 | if (is_lvds) { | |
5eddb70b | 3921 | reg = LVDS; |
bad720ff | 3922 | if (HAS_PCH_SPLIT(dev)) |
5eddb70b | 3923 | reg = PCH_LVDS; |
541998a1 | 3924 | |
5eddb70b CW |
3925 | temp = I915_READ(reg); |
3926 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
b3b095b3 ZW |
3927 | if (pipe == 1) { |
3928 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 3929 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 3930 | else |
5eddb70b | 3931 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
3932 | } else { |
3933 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 3934 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 3935 | else |
5eddb70b | 3936 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 3937 | } |
a3e17eb8 | 3938 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 3939 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
3940 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
3941 | * set the DPLLs for dual-channel mode or not. | |
3942 | */ | |
3943 | if (clock.p2 == 7) | |
5eddb70b | 3944 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 3945 | else |
5eddb70b | 3946 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
3947 | |
3948 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
3949 | * appropriately here, but we need to look more thoroughly into how | |
3950 | * panels behave in the two modes. | |
3951 | */ | |
434ed097 | 3952 | /* set the dithering flag on non-PCH LVDS as needed */ |
a6c45cf0 | 3953 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
434ed097 | 3954 | if (dev_priv->lvds_dither) |
5eddb70b | 3955 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 3956 | else |
5eddb70b | 3957 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 3958 | } |
5eddb70b | 3959 | I915_WRITE(reg, temp); |
79e53945 | 3960 | } |
434ed097 JB |
3961 | |
3962 | /* set the dithering flag and clear for anything other than a panel. */ | |
3963 | if (HAS_PCH_SPLIT(dev)) { | |
3964 | pipeconf &= ~PIPECONF_DITHER_EN; | |
3965 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
3966 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
3967 | pipeconf |= PIPECONF_DITHER_EN; | |
3968 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
3969 | } | |
3970 | } | |
3971 | ||
a4fc5ed6 KP |
3972 | if (is_dp) |
3973 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
8db9d77b ZW |
3974 | else if (HAS_PCH_SPLIT(dev)) { |
3975 | /* For non-DP output, clear any trans DP clock recovery setting.*/ | |
3976 | if (pipe == 0) { | |
3977 | I915_WRITE(TRANSA_DATA_M1, 0); | |
3978 | I915_WRITE(TRANSA_DATA_N1, 0); | |
3979 | I915_WRITE(TRANSA_DP_LINK_M1, 0); | |
3980 | I915_WRITE(TRANSA_DP_LINK_N1, 0); | |
3981 | } else { | |
3982 | I915_WRITE(TRANSB_DATA_M1, 0); | |
3983 | I915_WRITE(TRANSB_DATA_N1, 0); | |
3984 | I915_WRITE(TRANSB_DP_LINK_M1, 0); | |
3985 | I915_WRITE(TRANSB_DP_LINK_N1, 0); | |
3986 | } | |
3987 | } | |
79e53945 | 3988 | |
8e647a27 | 3989 | if (!has_edp_encoder) { |
32f9d658 | 3990 | I915_WRITE(fp_reg, fp); |
79e53945 | 3991 | I915_WRITE(dpll_reg, dpll); |
5eddb70b | 3992 | |
32f9d658 | 3993 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 3994 | POSTING_READ(dpll_reg); |
32f9d658 ZW |
3995 | udelay(150); |
3996 | ||
a6c45cf0 | 3997 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
5eddb70b | 3998 | temp = 0; |
bb66c512 | 3999 | if (is_sdvo) { |
5eddb70b CW |
4000 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4001 | if (temp > 1) | |
4002 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6c9547ff | 4003 | else |
5eddb70b CW |
4004 | temp = 0; |
4005 | } | |
4006 | I915_WRITE(DPLL_MD(pipe), temp); | |
32f9d658 ZW |
4007 | } else { |
4008 | /* write it again -- the BIOS does, after all */ | |
4009 | I915_WRITE(dpll_reg, dpll); | |
4010 | } | |
5eddb70b | 4011 | |
32f9d658 | 4012 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 4013 | POSTING_READ(dpll_reg); |
32f9d658 | 4014 | udelay(150); |
79e53945 | 4015 | } |
79e53945 | 4016 | |
5eddb70b | 4017 | intel_crtc->lowfreq_avail = false; |
652c393a JB |
4018 | if (is_lvds && has_reduced_clock && i915_powersave) { |
4019 | I915_WRITE(fp_reg + 4, fp2); | |
4020 | intel_crtc->lowfreq_avail = true; | |
4021 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4022 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
4023 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4024 | } | |
4025 | } else { | |
4026 | I915_WRITE(fp_reg + 4, fp); | |
652c393a | 4027 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 4028 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4029 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4030 | } | |
4031 | } | |
4032 | ||
734b4157 KH |
4033 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4034 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4035 | /* the chip adds 2 halflines automatically */ | |
4036 | adjusted_mode->crtc_vdisplay -= 1; | |
4037 | adjusted_mode->crtc_vtotal -= 1; | |
4038 | adjusted_mode->crtc_vblank_start -= 1; | |
4039 | adjusted_mode->crtc_vblank_end -= 1; | |
4040 | adjusted_mode->crtc_vsync_end -= 1; | |
4041 | adjusted_mode->crtc_vsync_start -= 1; | |
4042 | } else | |
4043 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
4044 | ||
5eddb70b CW |
4045 | I915_WRITE(HTOTAL(pipe), |
4046 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4047 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4048 | I915_WRITE(HBLANK(pipe), |
4049 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4050 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4051 | I915_WRITE(HSYNC(pipe), |
4052 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4053 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4054 | |
4055 | I915_WRITE(VTOTAL(pipe), | |
4056 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4057 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4058 | I915_WRITE(VBLANK(pipe), |
4059 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4060 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4061 | I915_WRITE(VSYNC(pipe), |
4062 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4063 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4064 | |
4065 | /* pipesrc and dspsize control the size that is scaled from, | |
4066 | * which should always be the user's requested size. | |
79e53945 | 4067 | */ |
bad720ff | 4068 | if (!HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4069 | I915_WRITE(DSPSIZE(plane), |
4070 | ((mode->vdisplay - 1) << 16) | | |
4071 | (mode->hdisplay - 1)); | |
4072 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4073 | } |
5eddb70b CW |
4074 | I915_WRITE(PIPESRC(pipe), |
4075 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4076 | |
bad720ff | 4077 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4078 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4079 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4080 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4081 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4082 | |
8e647a27 | 4083 | if (has_edp_encoder) { |
f2b115e6 | 4084 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 ZW |
4085 | } else { |
4086 | /* enable FDI RX PLL too */ | |
5eddb70b CW |
4087 | reg = FDI_RX_CTL(pipe); |
4088 | temp = I915_READ(reg); | |
4089 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
4090 | ||
4091 | POSTING_READ(reg); | |
8db9d77b ZW |
4092 | udelay(200); |
4093 | ||
4094 | /* enable FDI TX PLL too */ | |
5eddb70b CW |
4095 | reg = FDI_TX_CTL(pipe); |
4096 | temp = I915_READ(reg); | |
4097 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
8db9d77b ZW |
4098 | |
4099 | /* enable FDI RX PCDCLK */ | |
5eddb70b CW |
4100 | reg = FDI_RX_CTL(pipe); |
4101 | temp = I915_READ(reg); | |
4102 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4103 | ||
4104 | POSTING_READ(reg); | |
32f9d658 ZW |
4105 | udelay(200); |
4106 | } | |
2c07245f ZW |
4107 | } |
4108 | ||
5eddb70b CW |
4109 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4110 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 4111 | |
9d0498a2 | 4112 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4113 | |
c2416fc6 | 4114 | if (IS_IRONLAKE(dev)) { |
553bd149 ZW |
4115 | /* enable address swizzle for tiling buffer */ |
4116 | temp = I915_READ(DISP_ARB_CTL); | |
4117 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
4118 | } | |
4119 | ||
5eddb70b | 4120 | I915_WRITE(DSPCNTR(plane), dspcntr); |
79e53945 | 4121 | |
5c3b82e2 | 4122 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4123 | |
4124 | intel_update_watermarks(dev); | |
4125 | ||
79e53945 | 4126 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4127 | |
1f803ee5 | 4128 | return ret; |
79e53945 JB |
4129 | } |
4130 | ||
4131 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4132 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4133 | { | |
4134 | struct drm_device *dev = crtc->dev; | |
4135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4137 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
4138 | int i; | |
4139 | ||
4140 | /* The clocks have to be on to load the palette. */ | |
4141 | if (!crtc->enabled) | |
4142 | return; | |
4143 | ||
f2b115e6 | 4144 | /* use legacy palette for Ironlake */ |
bad720ff | 4145 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4146 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
4147 | LGC_PALETTE_B; | |
4148 | ||
79e53945 JB |
4149 | for (i = 0; i < 256; i++) { |
4150 | I915_WRITE(palreg + 4 * i, | |
4151 | (intel_crtc->lut_r[i] << 16) | | |
4152 | (intel_crtc->lut_g[i] << 8) | | |
4153 | intel_crtc->lut_b[i]); | |
4154 | } | |
4155 | } | |
4156 | ||
560b85bb CW |
4157 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4158 | { | |
4159 | struct drm_device *dev = crtc->dev; | |
4160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4161 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4162 | bool visible = base != 0; | |
4163 | u32 cntl; | |
4164 | ||
4165 | if (intel_crtc->cursor_visible == visible) | |
4166 | return; | |
4167 | ||
4168 | cntl = I915_READ(CURACNTR); | |
4169 | if (visible) { | |
4170 | /* On these chipsets we can only modify the base whilst | |
4171 | * the cursor is disabled. | |
4172 | */ | |
4173 | I915_WRITE(CURABASE, base); | |
4174 | ||
4175 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4176 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4177 | cntl |= CURSOR_ENABLE | | |
4178 | CURSOR_GAMMA_ENABLE | | |
4179 | CURSOR_FORMAT_ARGB; | |
4180 | } else | |
4181 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
4182 | I915_WRITE(CURACNTR, cntl); | |
4183 | ||
4184 | intel_crtc->cursor_visible = visible; | |
4185 | } | |
4186 | ||
4187 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4188 | { | |
4189 | struct drm_device *dev = crtc->dev; | |
4190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4192 | int pipe = intel_crtc->pipe; | |
4193 | bool visible = base != 0; | |
4194 | ||
4195 | if (intel_crtc->cursor_visible != visible) { | |
4196 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); | |
4197 | if (base) { | |
4198 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4199 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4200 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4201 | } else { | |
4202 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4203 | cntl |= CURSOR_MODE_DISABLE; | |
4204 | } | |
4205 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); | |
4206 | ||
4207 | intel_crtc->cursor_visible = visible; | |
4208 | } | |
4209 | /* and commit changes on next vblank */ | |
4210 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); | |
4211 | } | |
4212 | ||
cda4b7d3 | 4213 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
4214 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
4215 | bool on) | |
cda4b7d3 CW |
4216 | { |
4217 | struct drm_device *dev = crtc->dev; | |
4218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4220 | int pipe = intel_crtc->pipe; | |
4221 | int x = intel_crtc->cursor_x; | |
4222 | int y = intel_crtc->cursor_y; | |
560b85bb | 4223 | u32 base, pos; |
cda4b7d3 CW |
4224 | bool visible; |
4225 | ||
4226 | pos = 0; | |
4227 | ||
6b383a7f | 4228 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
4229 | base = intel_crtc->cursor_addr; |
4230 | if (x > (int) crtc->fb->width) | |
4231 | base = 0; | |
4232 | ||
4233 | if (y > (int) crtc->fb->height) | |
4234 | base = 0; | |
4235 | } else | |
4236 | base = 0; | |
4237 | ||
4238 | if (x < 0) { | |
4239 | if (x + intel_crtc->cursor_width < 0) | |
4240 | base = 0; | |
4241 | ||
4242 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4243 | x = -x; | |
4244 | } | |
4245 | pos |= x << CURSOR_X_SHIFT; | |
4246 | ||
4247 | if (y < 0) { | |
4248 | if (y + intel_crtc->cursor_height < 0) | |
4249 | base = 0; | |
4250 | ||
4251 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4252 | y = -y; | |
4253 | } | |
4254 | pos |= y << CURSOR_Y_SHIFT; | |
4255 | ||
4256 | visible = base != 0; | |
560b85bb | 4257 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4258 | return; |
4259 | ||
4260 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); | |
560b85bb CW |
4261 | if (IS_845G(dev) || IS_I865G(dev)) |
4262 | i845_update_cursor(crtc, base); | |
4263 | else | |
4264 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
4265 | |
4266 | if (visible) | |
4267 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4268 | } | |
4269 | ||
79e53945 JB |
4270 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
4271 | struct drm_file *file_priv, | |
4272 | uint32_t handle, | |
4273 | uint32_t width, uint32_t height) | |
4274 | { | |
4275 | struct drm_device *dev = crtc->dev; | |
4276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4278 | struct drm_gem_object *bo; | |
4279 | struct drm_i915_gem_object *obj_priv; | |
cda4b7d3 | 4280 | uint32_t addr; |
3f8bc370 | 4281 | int ret; |
79e53945 | 4282 | |
28c97730 | 4283 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4284 | |
4285 | /* if we want to turn off the cursor ignore width and height */ | |
4286 | if (!handle) { | |
28c97730 | 4287 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 KH |
4288 | addr = 0; |
4289 | bo = NULL; | |
5004417d | 4290 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4291 | goto finish; |
79e53945 JB |
4292 | } |
4293 | ||
4294 | /* Currently we only support 64x64 cursors */ | |
4295 | if (width != 64 || height != 64) { | |
4296 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4297 | return -EINVAL; | |
4298 | } | |
4299 | ||
4300 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
4301 | if (!bo) | |
4302 | return -ENOENT; | |
4303 | ||
23010e43 | 4304 | obj_priv = to_intel_bo(bo); |
79e53945 JB |
4305 | |
4306 | if (bo->size < width * height * 4) { | |
4307 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
4308 | ret = -ENOMEM; |
4309 | goto fail; | |
79e53945 JB |
4310 | } |
4311 | ||
71acb5eb | 4312 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4313 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4314 | if (!dev_priv->info->cursor_needs_physical) { |
71acb5eb DA |
4315 | ret = i915_gem_object_pin(bo, PAGE_SIZE); |
4316 | if (ret) { | |
4317 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 4318 | goto fail_locked; |
71acb5eb | 4319 | } |
e7b526bb CW |
4320 | |
4321 | ret = i915_gem_object_set_to_gtt_domain(bo, 0); | |
4322 | if (ret) { | |
4323 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4324 | goto fail_unpin; | |
4325 | } | |
4326 | ||
79e53945 | 4327 | addr = obj_priv->gtt_offset; |
71acb5eb | 4328 | } else { |
6eeefaf3 | 4329 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
cda4b7d3 | 4330 | ret = i915_gem_attach_phys_object(dev, bo, |
6eeefaf3 CW |
4331 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4332 | align); | |
71acb5eb DA |
4333 | if (ret) { |
4334 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4335 | goto fail_locked; |
71acb5eb DA |
4336 | } |
4337 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
4338 | } |
4339 | ||
a6c45cf0 | 4340 | if (IS_GEN2(dev)) |
14b60391 JB |
4341 | I915_WRITE(CURSIZE, (height << 12) | width); |
4342 | ||
3f8bc370 | 4343 | finish: |
3f8bc370 | 4344 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4345 | if (dev_priv->info->cursor_needs_physical) { |
71acb5eb DA |
4346 | if (intel_crtc->cursor_bo != bo) |
4347 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
4348 | } else | |
4349 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
4350 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
4351 | } | |
80824003 | 4352 | |
7f9872e0 | 4353 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4354 | |
4355 | intel_crtc->cursor_addr = addr; | |
4356 | intel_crtc->cursor_bo = bo; | |
cda4b7d3 CW |
4357 | intel_crtc->cursor_width = width; |
4358 | intel_crtc->cursor_height = height; | |
4359 | ||
6b383a7f | 4360 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 4361 | |
79e53945 | 4362 | return 0; |
e7b526bb CW |
4363 | fail_unpin: |
4364 | i915_gem_object_unpin(bo); | |
7f9872e0 | 4365 | fail_locked: |
34b8686e | 4366 | mutex_unlock(&dev->struct_mutex); |
bc9025bd LB |
4367 | fail: |
4368 | drm_gem_object_unreference_unlocked(bo); | |
34b8686e | 4369 | return ret; |
79e53945 JB |
4370 | } |
4371 | ||
4372 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4373 | { | |
79e53945 | 4374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4375 | |
cda4b7d3 CW |
4376 | intel_crtc->cursor_x = x; |
4377 | intel_crtc->cursor_y = y; | |
652c393a | 4378 | |
6b383a7f | 4379 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
4380 | |
4381 | return 0; | |
4382 | } | |
4383 | ||
4384 | /** Sets the color ramps on behalf of RandR */ | |
4385 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4386 | u16 blue, int regno) | |
4387 | { | |
4388 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4389 | ||
4390 | intel_crtc->lut_r[regno] = red >> 8; | |
4391 | intel_crtc->lut_g[regno] = green >> 8; | |
4392 | intel_crtc->lut_b[regno] = blue >> 8; | |
4393 | } | |
4394 | ||
b8c00ac5 DA |
4395 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4396 | u16 *blue, int regno) | |
4397 | { | |
4398 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4399 | ||
4400 | *red = intel_crtc->lut_r[regno] << 8; | |
4401 | *green = intel_crtc->lut_g[regno] << 8; | |
4402 | *blue = intel_crtc->lut_b[regno] << 8; | |
4403 | } | |
4404 | ||
79e53945 | 4405 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4406 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4407 | { |
7203425a | 4408 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4409 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4410 | |
7203425a | 4411 | for (i = start; i < end; i++) { |
79e53945 JB |
4412 | intel_crtc->lut_r[i] = red[i] >> 8; |
4413 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4414 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4415 | } | |
4416 | ||
4417 | intel_crtc_load_lut(crtc); | |
4418 | } | |
4419 | ||
4420 | /** | |
4421 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4422 | * detection. | |
4423 | * | |
4424 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4425 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4426 | * |
c751ce4f | 4427 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4428 | * configured for it. In the future, it could choose to temporarily disable |
4429 | * some outputs to free up a pipe for its use. | |
4430 | * | |
4431 | * \return crtc, or NULL if no pipes are available. | |
4432 | */ | |
4433 | ||
4434 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4435 | static struct drm_display_mode load_detect_mode = { | |
4436 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4437 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4438 | }; | |
4439 | ||
21d40d37 | 4440 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 4441 | struct drm_connector *connector, |
79e53945 JB |
4442 | struct drm_display_mode *mode, |
4443 | int *dpms_mode) | |
4444 | { | |
4445 | struct intel_crtc *intel_crtc; | |
4446 | struct drm_crtc *possible_crtc; | |
4447 | struct drm_crtc *supported_crtc =NULL; | |
4ef69c7a | 4448 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4449 | struct drm_crtc *crtc = NULL; |
4450 | struct drm_device *dev = encoder->dev; | |
4451 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4452 | struct drm_crtc_helper_funcs *crtc_funcs; | |
4453 | int i = -1; | |
4454 | ||
4455 | /* | |
4456 | * Algorithm gets a little messy: | |
4457 | * - if the connector already has an assigned crtc, use it (but make | |
4458 | * sure it's on first) | |
4459 | * - try to find the first unused crtc that can drive this connector, | |
4460 | * and use that if we find one | |
4461 | * - if there are no unused crtcs available, try to use the first | |
4462 | * one we found that supports the connector | |
4463 | */ | |
4464 | ||
4465 | /* See if we already have a CRTC for this connector */ | |
4466 | if (encoder->crtc) { | |
4467 | crtc = encoder->crtc; | |
4468 | /* Make sure the crtc and connector are running */ | |
4469 | intel_crtc = to_intel_crtc(crtc); | |
4470 | *dpms_mode = intel_crtc->dpms_mode; | |
4471 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4472 | crtc_funcs = crtc->helper_private; | |
4473 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4474 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
4475 | } | |
4476 | return crtc; | |
4477 | } | |
4478 | ||
4479 | /* Find an unused one (if possible) */ | |
4480 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
4481 | i++; | |
4482 | if (!(encoder->possible_crtcs & (1 << i))) | |
4483 | continue; | |
4484 | if (!possible_crtc->enabled) { | |
4485 | crtc = possible_crtc; | |
4486 | break; | |
4487 | } | |
4488 | if (!supported_crtc) | |
4489 | supported_crtc = possible_crtc; | |
4490 | } | |
4491 | ||
4492 | /* | |
4493 | * If we didn't find an unused CRTC, don't use any. | |
4494 | */ | |
4495 | if (!crtc) { | |
4496 | return NULL; | |
4497 | } | |
4498 | ||
4499 | encoder->crtc = crtc; | |
c1c43977 | 4500 | connector->encoder = encoder; |
21d40d37 | 4501 | intel_encoder->load_detect_temp = true; |
79e53945 JB |
4502 | |
4503 | intel_crtc = to_intel_crtc(crtc); | |
4504 | *dpms_mode = intel_crtc->dpms_mode; | |
4505 | ||
4506 | if (!crtc->enabled) { | |
4507 | if (!mode) | |
4508 | mode = &load_detect_mode; | |
3c4fdcfb | 4509 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
4510 | } else { |
4511 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4512 | crtc_funcs = crtc->helper_private; | |
4513 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4514 | } | |
4515 | ||
4516 | /* Add this connector to the crtc */ | |
4517 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
4518 | encoder_funcs->commit(encoder); | |
4519 | } | |
4520 | /* let the connector get through one full cycle before testing */ | |
9d0498a2 | 4521 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 JB |
4522 | |
4523 | return crtc; | |
4524 | } | |
4525 | ||
c1c43977 ZW |
4526 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
4527 | struct drm_connector *connector, int dpms_mode) | |
79e53945 | 4528 | { |
4ef69c7a | 4529 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4530 | struct drm_device *dev = encoder->dev; |
4531 | struct drm_crtc *crtc = encoder->crtc; | |
4532 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4533 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
4534 | ||
21d40d37 | 4535 | if (intel_encoder->load_detect_temp) { |
79e53945 | 4536 | encoder->crtc = NULL; |
c1c43977 | 4537 | connector->encoder = NULL; |
21d40d37 | 4538 | intel_encoder->load_detect_temp = false; |
79e53945 JB |
4539 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
4540 | drm_helper_disable_unused_functions(dev); | |
4541 | } | |
4542 | ||
c751ce4f | 4543 | /* Switch crtc and encoder back off if necessary */ |
79e53945 JB |
4544 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
4545 | if (encoder->crtc == crtc) | |
4546 | encoder_funcs->dpms(encoder, dpms_mode); | |
4547 | crtc_funcs->dpms(crtc, dpms_mode); | |
4548 | } | |
4549 | } | |
4550 | ||
4551 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
4552 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
4553 | { | |
4554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4556 | int pipe = intel_crtc->pipe; | |
4557 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
4558 | u32 fp; | |
4559 | intel_clock_t clock; | |
4560 | ||
4561 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
4562 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
4563 | else | |
4564 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
4565 | ||
4566 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
4567 | if (IS_PINEVIEW(dev)) { |
4568 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
4569 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
4570 | } else { |
4571 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
4572 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
4573 | } | |
4574 | ||
a6c45cf0 | 4575 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
4576 | if (IS_PINEVIEW(dev)) |
4577 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
4578 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
4579 | else |
4580 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
4581 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
4582 | ||
4583 | switch (dpll & DPLL_MODE_MASK) { | |
4584 | case DPLLB_MODE_DAC_SERIAL: | |
4585 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
4586 | 5 : 10; | |
4587 | break; | |
4588 | case DPLLB_MODE_LVDS: | |
4589 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
4590 | 7 : 14; | |
4591 | break; | |
4592 | default: | |
28c97730 | 4593 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
4594 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
4595 | return 0; | |
4596 | } | |
4597 | ||
4598 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 4599 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
4600 | } else { |
4601 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
4602 | ||
4603 | if (is_lvds) { | |
4604 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
4605 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
4606 | clock.p2 = 14; | |
4607 | ||
4608 | if ((dpll & PLL_REF_INPUT_MASK) == | |
4609 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
4610 | /* XXX: might not be 66MHz */ | |
2177832f | 4611 | intel_clock(dev, 66000, &clock); |
79e53945 | 4612 | } else |
2177832f | 4613 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4614 | } else { |
4615 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
4616 | clock.p1 = 2; | |
4617 | else { | |
4618 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
4619 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
4620 | } | |
4621 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
4622 | clock.p2 = 4; | |
4623 | else | |
4624 | clock.p2 = 2; | |
4625 | ||
2177832f | 4626 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4627 | } |
4628 | } | |
4629 | ||
4630 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
4631 | * i830PllIsValid() because it relies on the xf86_config connector | |
4632 | * configuration being accurate, which it isn't necessarily. | |
4633 | */ | |
4634 | ||
4635 | return clock.dot; | |
4636 | } | |
4637 | ||
4638 | /** Returns the currently programmed mode of the given pipe. */ | |
4639 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
4640 | struct drm_crtc *crtc) | |
4641 | { | |
4642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4644 | int pipe = intel_crtc->pipe; | |
4645 | struct drm_display_mode *mode; | |
4646 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
4647 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
4648 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
4649 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
4650 | ||
4651 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
4652 | if (!mode) | |
4653 | return NULL; | |
4654 | ||
4655 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
4656 | mode->hdisplay = (htot & 0xffff) + 1; | |
4657 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
4658 | mode->hsync_start = (hsync & 0xffff) + 1; | |
4659 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
4660 | mode->vdisplay = (vtot & 0xffff) + 1; | |
4661 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
4662 | mode->vsync_start = (vsync & 0xffff) + 1; | |
4663 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
4664 | ||
4665 | drm_mode_set_name(mode); | |
4666 | drm_mode_set_crtcinfo(mode, 0); | |
4667 | ||
4668 | return mode; | |
4669 | } | |
4670 | ||
652c393a JB |
4671 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
4672 | ||
4673 | /* When this timer fires, we've been idle for awhile */ | |
4674 | static void intel_gpu_idle_timer(unsigned long arg) | |
4675 | { | |
4676 | struct drm_device *dev = (struct drm_device *)arg; | |
4677 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4678 | ||
44d98a61 | 4679 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
652c393a JB |
4680 | |
4681 | dev_priv->busy = false; | |
4682 | ||
01dfba93 | 4683 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4684 | } |
4685 | ||
652c393a JB |
4686 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
4687 | ||
4688 | static void intel_crtc_idle_timer(unsigned long arg) | |
4689 | { | |
4690 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
4691 | struct drm_crtc *crtc = &intel_crtc->base; | |
4692 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
4693 | ||
44d98a61 | 4694 | DRM_DEBUG_DRIVER("idle timer fired, downclocking\n"); |
652c393a JB |
4695 | |
4696 | intel_crtc->busy = false; | |
4697 | ||
01dfba93 | 4698 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4699 | } |
4700 | ||
3dec0095 | 4701 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
4702 | { |
4703 | struct drm_device *dev = crtc->dev; | |
4704 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4706 | int pipe = intel_crtc->pipe; | |
4707 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4708 | int dpll = I915_READ(dpll_reg); | |
4709 | ||
bad720ff | 4710 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4711 | return; |
4712 | ||
4713 | if (!dev_priv->lvds_downclock_avail) | |
4714 | return; | |
4715 | ||
4716 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { | |
44d98a61 | 4717 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
4718 | |
4719 | /* Unlock panel regs */ | |
4a655f04 JB |
4720 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4721 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4722 | |
4723 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
4724 | I915_WRITE(dpll_reg, dpll); | |
4725 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4726 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4727 | dpll = I915_READ(dpll_reg); |
4728 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 4729 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
4730 | |
4731 | /* ...and lock them again */ | |
4732 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4733 | } | |
4734 | ||
4735 | /* Schedule downclock */ | |
3dec0095 DV |
4736 | mod_timer(&intel_crtc->idle_timer, jiffies + |
4737 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
4738 | } |
4739 | ||
4740 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
4741 | { | |
4742 | struct drm_device *dev = crtc->dev; | |
4743 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4745 | int pipe = intel_crtc->pipe; | |
4746 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4747 | int dpll = I915_READ(dpll_reg); | |
4748 | ||
bad720ff | 4749 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4750 | return; |
4751 | ||
4752 | if (!dev_priv->lvds_downclock_avail) | |
4753 | return; | |
4754 | ||
4755 | /* | |
4756 | * Since this is called by a timer, we should never get here in | |
4757 | * the manual case. | |
4758 | */ | |
4759 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 4760 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
4761 | |
4762 | /* Unlock panel regs */ | |
4a655f04 JB |
4763 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4764 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4765 | |
4766 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
4767 | I915_WRITE(dpll_reg, dpll); | |
4768 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4769 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4770 | dpll = I915_READ(dpll_reg); |
4771 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 4772 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
4773 | |
4774 | /* ...and lock them again */ | |
4775 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4776 | } | |
4777 | ||
4778 | } | |
4779 | ||
4780 | /** | |
4781 | * intel_idle_update - adjust clocks for idleness | |
4782 | * @work: work struct | |
4783 | * | |
4784 | * Either the GPU or display (or both) went idle. Check the busy status | |
4785 | * here and adjust the CRTC and GPU clocks as necessary. | |
4786 | */ | |
4787 | static void intel_idle_update(struct work_struct *work) | |
4788 | { | |
4789 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
4790 | idle_work); | |
4791 | struct drm_device *dev = dev_priv->dev; | |
4792 | struct drm_crtc *crtc; | |
4793 | struct intel_crtc *intel_crtc; | |
45ac22c8 | 4794 | int enabled = 0; |
652c393a JB |
4795 | |
4796 | if (!i915_powersave) | |
4797 | return; | |
4798 | ||
4799 | mutex_lock(&dev->struct_mutex); | |
4800 | ||
7648fa99 JB |
4801 | i915_update_gfx_val(dev_priv); |
4802 | ||
652c393a JB |
4803 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
4804 | /* Skip inactive CRTCs */ | |
4805 | if (!crtc->fb) | |
4806 | continue; | |
4807 | ||
45ac22c8 | 4808 | enabled++; |
652c393a JB |
4809 | intel_crtc = to_intel_crtc(crtc); |
4810 | if (!intel_crtc->busy) | |
4811 | intel_decrease_pllclock(crtc); | |
4812 | } | |
4813 | ||
45ac22c8 LP |
4814 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
4815 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); | |
4816 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4817 | } | |
4818 | ||
652c393a JB |
4819 | mutex_unlock(&dev->struct_mutex); |
4820 | } | |
4821 | ||
4822 | /** | |
4823 | * intel_mark_busy - mark the GPU and possibly the display busy | |
4824 | * @dev: drm device | |
4825 | * @obj: object we're operating on | |
4826 | * | |
4827 | * Callers can use this function to indicate that the GPU is busy processing | |
4828 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
4829 | * buffer), we'll also mark the display as busy, so we know to increase its | |
4830 | * clock frequency. | |
4831 | */ | |
4832 | void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) | |
4833 | { | |
4834 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4835 | struct drm_crtc *crtc = NULL; | |
4836 | struct intel_framebuffer *intel_fb; | |
4837 | struct intel_crtc *intel_crtc; | |
4838 | ||
5e17ee74 ZW |
4839 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4840 | return; | |
4841 | ||
060e645a LP |
4842 | if (!dev_priv->busy) { |
4843 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
4844 | u32 fw_blc_self; | |
ee980b80 | 4845 | |
060e645a LP |
4846 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
4847 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4848 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4849 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4850 | } | |
28cf798f | 4851 | dev_priv->busy = true; |
060e645a | 4852 | } else |
28cf798f CW |
4853 | mod_timer(&dev_priv->idle_timer, jiffies + |
4854 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
4855 | |
4856 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
4857 | if (!crtc->fb) | |
4858 | continue; | |
4859 | ||
4860 | intel_crtc = to_intel_crtc(crtc); | |
4861 | intel_fb = to_intel_framebuffer(crtc->fb); | |
4862 | if (intel_fb->obj == obj) { | |
4863 | if (!intel_crtc->busy) { | |
060e645a LP |
4864 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
4865 | u32 fw_blc_self; | |
4866 | ||
4867 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | |
4868 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4869 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4870 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4871 | } | |
652c393a | 4872 | /* Non-busy -> busy, upclock */ |
3dec0095 | 4873 | intel_increase_pllclock(crtc); |
652c393a JB |
4874 | intel_crtc->busy = true; |
4875 | } else { | |
4876 | /* Busy -> busy, put off timer */ | |
4877 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
4878 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
4879 | } | |
4880 | } | |
4881 | } | |
4882 | } | |
4883 | ||
79e53945 JB |
4884 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
4885 | { | |
4886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
4887 | struct drm_device *dev = crtc->dev; |
4888 | struct intel_unpin_work *work; | |
4889 | unsigned long flags; | |
4890 | ||
4891 | spin_lock_irqsave(&dev->event_lock, flags); | |
4892 | work = intel_crtc->unpin_work; | |
4893 | intel_crtc->unpin_work = NULL; | |
4894 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4895 | ||
4896 | if (work) { | |
4897 | cancel_work_sync(&work->work); | |
4898 | kfree(work); | |
4899 | } | |
79e53945 JB |
4900 | |
4901 | drm_crtc_cleanup(crtc); | |
67e77c5a | 4902 | |
79e53945 JB |
4903 | kfree(intel_crtc); |
4904 | } | |
4905 | ||
6b95a207 KH |
4906 | static void intel_unpin_work_fn(struct work_struct *__work) |
4907 | { | |
4908 | struct intel_unpin_work *work = | |
4909 | container_of(__work, struct intel_unpin_work, work); | |
4910 | ||
4911 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 4912 | i915_gem_object_unpin(work->old_fb_obj); |
75dfca80 | 4913 | drm_gem_object_unreference(work->pending_flip_obj); |
b1b87f6b | 4914 | drm_gem_object_unreference(work->old_fb_obj); |
6b95a207 KH |
4915 | mutex_unlock(&work->dev->struct_mutex); |
4916 | kfree(work); | |
4917 | } | |
4918 | ||
1afe3e9d JB |
4919 | static void do_intel_finish_page_flip(struct drm_device *dev, |
4920 | struct drm_crtc *crtc) | |
6b95a207 KH |
4921 | { |
4922 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
4923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4924 | struct intel_unpin_work *work; | |
4925 | struct drm_i915_gem_object *obj_priv; | |
4926 | struct drm_pending_vblank_event *e; | |
4927 | struct timeval now; | |
4928 | unsigned long flags; | |
4929 | ||
4930 | /* Ignore early vblank irqs */ | |
4931 | if (intel_crtc == NULL) | |
4932 | return; | |
4933 | ||
4934 | spin_lock_irqsave(&dev->event_lock, flags); | |
4935 | work = intel_crtc->unpin_work; | |
4936 | if (work == NULL || !work->pending) { | |
4937 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4938 | return; | |
4939 | } | |
4940 | ||
4941 | intel_crtc->unpin_work = NULL; | |
4942 | drm_vblank_put(dev, intel_crtc->pipe); | |
4943 | ||
4944 | if (work->event) { | |
4945 | e = work->event; | |
4946 | do_gettimeofday(&now); | |
4947 | e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe); | |
4948 | e->event.tv_sec = now.tv_sec; | |
4949 | e->event.tv_usec = now.tv_usec; | |
4950 | list_add_tail(&e->base.link, | |
4951 | &e->base.file_priv->event_list); | |
4952 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
4953 | } | |
4954 | ||
4955 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4956 | ||
23010e43 | 4957 | obj_priv = to_intel_bo(work->pending_flip_obj); |
de3f440f JB |
4958 | |
4959 | /* Initial scanout buffer will have a 0 pending flip count */ | |
4960 | if ((atomic_read(&obj_priv->pending_flip) == 0) || | |
4961 | atomic_dec_and_test(&obj_priv->pending_flip)) | |
6b95a207 KH |
4962 | DRM_WAKEUP(&dev_priv->pending_flip_queue); |
4963 | schedule_work(&work->work); | |
e5510fac JB |
4964 | |
4965 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
4966 | } |
4967 | ||
1afe3e9d JB |
4968 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
4969 | { | |
4970 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4971 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
4972 | ||
4973 | do_intel_finish_page_flip(dev, crtc); | |
4974 | } | |
4975 | ||
4976 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
4977 | { | |
4978 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4979 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
4980 | ||
4981 | do_intel_finish_page_flip(dev, crtc); | |
4982 | } | |
4983 | ||
6b95a207 KH |
4984 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
4985 | { | |
4986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4987 | struct intel_crtc *intel_crtc = | |
4988 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
4989 | unsigned long flags; | |
4990 | ||
4991 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 4992 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
4993 | if ((++intel_crtc->unpin_work->pending) > 1) |
4994 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
4995 | } else { |
4996 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
4997 | } | |
6b95a207 KH |
4998 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4999 | } | |
5000 | ||
5001 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
5002 | struct drm_framebuffer *fb, | |
5003 | struct drm_pending_vblank_event *event) | |
5004 | { | |
5005 | struct drm_device *dev = crtc->dev; | |
5006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5007 | struct intel_framebuffer *intel_fb; | |
5008 | struct drm_i915_gem_object *obj_priv; | |
5009 | struct drm_gem_object *obj; | |
5010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5011 | struct intel_unpin_work *work; | |
be9a3dbf | 5012 | unsigned long flags, offset; |
52e68630 | 5013 | int pipe = intel_crtc->pipe; |
48b956c5 | 5014 | u32 was_dirty, pf, pipesrc; |
52e68630 | 5015 | int ret; |
6b95a207 KH |
5016 | |
5017 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5018 | if (work == NULL) | |
5019 | return -ENOMEM; | |
5020 | ||
6b95a207 KH |
5021 | work->event = event; |
5022 | work->dev = crtc->dev; | |
5023 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5024 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5025 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5026 | ||
5027 | /* We borrow the event spin lock for protecting unpin_work */ | |
5028 | spin_lock_irqsave(&dev->event_lock, flags); | |
5029 | if (intel_crtc->unpin_work) { | |
5030 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5031 | kfree(work); | |
468f0b44 CW |
5032 | |
5033 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5034 | return -EBUSY; |
5035 | } | |
5036 | intel_crtc->unpin_work = work; | |
5037 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5038 | ||
5039 | intel_fb = to_intel_framebuffer(fb); | |
5040 | obj = intel_fb->obj; | |
5041 | ||
468f0b44 | 5042 | mutex_lock(&dev->struct_mutex); |
48b956c5 CW |
5043 | was_dirty = obj->write_domain & I915_GEM_GPU_DOMAINS; |
5044 | ret = intel_pin_and_fence_fb_obj(dev, obj, true); | |
96b099fd CW |
5045 | if (ret) |
5046 | goto cleanup_work; | |
6b95a207 | 5047 | |
75dfca80 | 5048 | /* Reference the objects for the scheduled work. */ |
b1b87f6b | 5049 | drm_gem_object_reference(work->old_fb_obj); |
75dfca80 | 5050 | drm_gem_object_reference(obj); |
6b95a207 KH |
5051 | |
5052 | crtc->fb = fb; | |
96b099fd CW |
5053 | |
5054 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
5055 | if (ret) | |
5056 | goto cleanup_objs; | |
5057 | ||
23010e43 | 5058 | obj_priv = to_intel_bo(obj); |
6b95a207 | 5059 | atomic_inc(&obj_priv->pending_flip); |
b1b87f6b | 5060 | work->pending_flip_obj = obj; |
6b95a207 | 5061 | |
c7f9f9a8 CW |
5062 | /* Schedule the pipelined flush */ |
5063 | if (was_dirty) | |
c78ec30b | 5064 | i915_gem_flush_ring(dev, NULL, obj_priv->ring, 0, was_dirty); |
52e68630 | 5065 | |
c7f9f9a8 CW |
5066 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
5067 | u32 flip_mask; | |
48b956c5 | 5068 | |
c7f9f9a8 CW |
5069 | /* Can't queue multiple flips, so wait for the previous |
5070 | * one to finish before executing the next. | |
5071 | */ | |
5072 | BEGIN_LP_RING(2); | |
5073 | if (intel_crtc->plane) | |
5074 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5075 | else | |
5076 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5077 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5078 | OUT_RING(MI_NOOP); | |
6146b3d6 DV |
5079 | ADVANCE_LP_RING(); |
5080 | } | |
83f7fd05 | 5081 | |
4e5359cd SF |
5082 | work->enable_stall_check = true; |
5083 | ||
be9a3dbf | 5084 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 5085 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 5086 | |
6b95a207 | 5087 | BEGIN_LP_RING(4); |
52e68630 CW |
5088 | switch(INTEL_INFO(dev)->gen) { |
5089 | case 2: | |
1afe3e9d JB |
5090 | OUT_RING(MI_DISPLAY_FLIP | |
5091 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5092 | OUT_RING(fb->pitch); | |
52e68630 CW |
5093 | OUT_RING(obj_priv->gtt_offset + offset); |
5094 | OUT_RING(MI_NOOP); | |
5095 | break; | |
5096 | ||
5097 | case 3: | |
1afe3e9d JB |
5098 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
5099 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5100 | OUT_RING(fb->pitch); | |
52e68630 | 5101 | OUT_RING(obj_priv->gtt_offset + offset); |
22fd0fab | 5102 | OUT_RING(MI_NOOP); |
52e68630 CW |
5103 | break; |
5104 | ||
5105 | case 4: | |
5106 | case 5: | |
5107 | /* i965+ uses the linear or tiled offsets from the | |
5108 | * Display Registers (which do not change across a page-flip) | |
5109 | * so we need only reprogram the base address. | |
5110 | */ | |
69d0b96c DV |
5111 | OUT_RING(MI_DISPLAY_FLIP | |
5112 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5113 | OUT_RING(fb->pitch); | |
52e68630 CW |
5114 | OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); |
5115 | ||
5116 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5117 | * untested on non-native modes, so ignore it for now. | |
5118 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5119 | */ | |
5120 | pf = 0; | |
5121 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5122 | OUT_RING(pf | pipesrc); | |
5123 | break; | |
5124 | ||
5125 | case 6: | |
5126 | OUT_RING(MI_DISPLAY_FLIP | | |
5127 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5128 | OUT_RING(fb->pitch | obj_priv->tiling_mode); | |
5129 | OUT_RING(obj_priv->gtt_offset); | |
5130 | ||
5131 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5132 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5133 | OUT_RING(pf | pipesrc); | |
5134 | break; | |
22fd0fab | 5135 | } |
6b95a207 KH |
5136 | ADVANCE_LP_RING(); |
5137 | ||
5138 | mutex_unlock(&dev->struct_mutex); | |
5139 | ||
e5510fac JB |
5140 | trace_i915_flip_request(intel_crtc->plane, obj); |
5141 | ||
6b95a207 | 5142 | return 0; |
96b099fd CW |
5143 | |
5144 | cleanup_objs: | |
5145 | drm_gem_object_unreference(work->old_fb_obj); | |
5146 | drm_gem_object_unreference(obj); | |
5147 | cleanup_work: | |
5148 | mutex_unlock(&dev->struct_mutex); | |
5149 | ||
5150 | spin_lock_irqsave(&dev->event_lock, flags); | |
5151 | intel_crtc->unpin_work = NULL; | |
5152 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5153 | ||
5154 | kfree(work); | |
5155 | ||
5156 | return ret; | |
6b95a207 KH |
5157 | } |
5158 | ||
7e7d76c3 | 5159 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
79e53945 JB |
5160 | .dpms = intel_crtc_dpms, |
5161 | .mode_fixup = intel_crtc_mode_fixup, | |
5162 | .mode_set = intel_crtc_mode_set, | |
5163 | .mode_set_base = intel_pipe_set_base, | |
81255565 | 5164 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
068143d3 | 5165 | .load_lut = intel_crtc_load_lut, |
79e53945 JB |
5166 | }; |
5167 | ||
5168 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
5169 | .cursor_set = intel_crtc_cursor_set, | |
5170 | .cursor_move = intel_crtc_cursor_move, | |
5171 | .gamma_set = intel_crtc_gamma_set, | |
5172 | .set_config = drm_crtc_helper_set_config, | |
5173 | .destroy = intel_crtc_destroy, | |
6b95a207 | 5174 | .page_flip = intel_crtc_page_flip, |
79e53945 JB |
5175 | }; |
5176 | ||
5177 | ||
b358d0a6 | 5178 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 5179 | { |
22fd0fab | 5180 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
5181 | struct intel_crtc *intel_crtc; |
5182 | int i; | |
5183 | ||
5184 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
5185 | if (intel_crtc == NULL) | |
5186 | return; | |
5187 | ||
5188 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
5189 | ||
5190 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
5191 | for (i = 0; i < 256; i++) { |
5192 | intel_crtc->lut_r[i] = i; | |
5193 | intel_crtc->lut_g[i] = i; | |
5194 | intel_crtc->lut_b[i] = i; | |
5195 | } | |
5196 | ||
80824003 JB |
5197 | /* Swap pipes & planes for FBC on pre-965 */ |
5198 | intel_crtc->pipe = pipe; | |
5199 | intel_crtc->plane = pipe; | |
e2e767ab | 5200 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 5201 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 5202 | intel_crtc->plane = !pipe; |
80824003 JB |
5203 | } |
5204 | ||
22fd0fab JB |
5205 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
5206 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
5207 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
5208 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
5209 | ||
79e53945 | 5210 | intel_crtc->cursor_addr = 0; |
032d2a0d | 5211 | intel_crtc->dpms_mode = -1; |
e65d9305 | 5212 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
7e7d76c3 JB |
5213 | |
5214 | if (HAS_PCH_SPLIT(dev)) { | |
5215 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
5216 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
5217 | } else { | |
5218 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
5219 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
5220 | } | |
5221 | ||
79e53945 JB |
5222 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
5223 | ||
652c393a JB |
5224 | intel_crtc->busy = false; |
5225 | ||
5226 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
5227 | (unsigned long)intel_crtc); | |
79e53945 JB |
5228 | } |
5229 | ||
08d7b3d1 CW |
5230 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
5231 | struct drm_file *file_priv) | |
5232 | { | |
5233 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5234 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
5235 | struct drm_mode_object *drmmode_obj; |
5236 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
5237 | |
5238 | if (!dev_priv) { | |
5239 | DRM_ERROR("called with no initialization\n"); | |
5240 | return -EINVAL; | |
5241 | } | |
5242 | ||
c05422d5 DV |
5243 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
5244 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 5245 | |
c05422d5 | 5246 | if (!drmmode_obj) { |
08d7b3d1 CW |
5247 | DRM_ERROR("no such CRTC id\n"); |
5248 | return -EINVAL; | |
5249 | } | |
5250 | ||
c05422d5 DV |
5251 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
5252 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 5253 | |
c05422d5 | 5254 | return 0; |
08d7b3d1 CW |
5255 | } |
5256 | ||
c5e4df33 | 5257 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 5258 | { |
4ef69c7a | 5259 | struct intel_encoder *encoder; |
79e53945 | 5260 | int index_mask = 0; |
79e53945 JB |
5261 | int entry = 0; |
5262 | ||
4ef69c7a CW |
5263 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5264 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
5265 | index_mask |= (1 << entry); |
5266 | entry++; | |
5267 | } | |
4ef69c7a | 5268 | |
79e53945 JB |
5269 | return index_mask; |
5270 | } | |
5271 | ||
79e53945 JB |
5272 | static void intel_setup_outputs(struct drm_device *dev) |
5273 | { | |
725e30ad | 5274 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 5275 | struct intel_encoder *encoder; |
cb0953d7 | 5276 | bool dpd_is_edp = false; |
79e53945 | 5277 | |
541998a1 | 5278 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
79e53945 JB |
5279 | intel_lvds_init(dev); |
5280 | ||
bad720ff | 5281 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 5282 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 5283 | |
32f9d658 ZW |
5284 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
5285 | intel_dp_init(dev, DP_A); | |
5286 | ||
cb0953d7 AJ |
5287 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5288 | intel_dp_init(dev, PCH_DP_D); | |
5289 | } | |
5290 | ||
5291 | intel_crt_init(dev); | |
5292 | ||
5293 | if (HAS_PCH_SPLIT(dev)) { | |
5294 | int found; | |
5295 | ||
30ad48b7 | 5296 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
5297 | /* PCH SDVOB multiplex with HDMIB */ |
5298 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
5299 | if (!found) |
5300 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
5301 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
5302 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
5303 | } |
5304 | ||
5305 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
5306 | intel_hdmi_init(dev, HDMIC); | |
5307 | ||
5308 | if (I915_READ(HDMID) & PORT_DETECTED) | |
5309 | intel_hdmi_init(dev, HDMID); | |
5310 | ||
5eb08b69 ZW |
5311 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
5312 | intel_dp_init(dev, PCH_DP_C); | |
5313 | ||
cb0953d7 | 5314 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
5315 | intel_dp_init(dev, PCH_DP_D); |
5316 | ||
103a196f | 5317 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 5318 | bool found = false; |
7d57382e | 5319 | |
725e30ad | 5320 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 5321 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 5322 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
5323 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
5324 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 5325 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 5326 | } |
27185ae1 | 5327 | |
b01f2c3a JB |
5328 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
5329 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 5330 | intel_dp_init(dev, DP_B); |
b01f2c3a | 5331 | } |
725e30ad | 5332 | } |
13520b05 KH |
5333 | |
5334 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 5335 | |
b01f2c3a JB |
5336 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
5337 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 5338 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 5339 | } |
27185ae1 ML |
5340 | |
5341 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
5342 | ||
b01f2c3a JB |
5343 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
5344 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 5345 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
5346 | } |
5347 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
5348 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 5349 | intel_dp_init(dev, DP_C); |
b01f2c3a | 5350 | } |
725e30ad | 5351 | } |
27185ae1 | 5352 | |
b01f2c3a JB |
5353 | if (SUPPORTS_INTEGRATED_DP(dev) && |
5354 | (I915_READ(DP_D) & DP_DETECTED)) { | |
5355 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 5356 | intel_dp_init(dev, DP_D); |
b01f2c3a | 5357 | } |
bad720ff | 5358 | } else if (IS_GEN2(dev)) |
79e53945 JB |
5359 | intel_dvo_init(dev); |
5360 | ||
103a196f | 5361 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
5362 | intel_tv_init(dev); |
5363 | ||
4ef69c7a CW |
5364 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5365 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
5366 | encoder->base.possible_clones = | |
5367 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 JB |
5368 | } |
5369 | } | |
5370 | ||
5371 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
5372 | { | |
5373 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
5374 | |
5375 | drm_framebuffer_cleanup(fb); | |
bc9025bd | 5376 | drm_gem_object_unreference_unlocked(intel_fb->obj); |
79e53945 JB |
5377 | |
5378 | kfree(intel_fb); | |
5379 | } | |
5380 | ||
5381 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
5382 | struct drm_file *file_priv, | |
5383 | unsigned int *handle) | |
5384 | { | |
5385 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
5386 | struct drm_gem_object *object = intel_fb->obj; | |
5387 | ||
5388 | return drm_gem_handle_create(file_priv, object, handle); | |
5389 | } | |
5390 | ||
5391 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
5392 | .destroy = intel_user_framebuffer_destroy, | |
5393 | .create_handle = intel_user_framebuffer_create_handle, | |
5394 | }; | |
5395 | ||
38651674 DA |
5396 | int intel_framebuffer_init(struct drm_device *dev, |
5397 | struct intel_framebuffer *intel_fb, | |
5398 | struct drm_mode_fb_cmd *mode_cmd, | |
5399 | struct drm_gem_object *obj) | |
79e53945 | 5400 | { |
57cd6508 | 5401 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
79e53945 JB |
5402 | int ret; |
5403 | ||
57cd6508 CW |
5404 | if (obj_priv->tiling_mode == I915_TILING_Y) |
5405 | return -EINVAL; | |
5406 | ||
5407 | if (mode_cmd->pitch & 63) | |
5408 | return -EINVAL; | |
5409 | ||
5410 | switch (mode_cmd->bpp) { | |
5411 | case 8: | |
5412 | case 16: | |
5413 | case 24: | |
5414 | case 32: | |
5415 | break; | |
5416 | default: | |
5417 | return -EINVAL; | |
5418 | } | |
5419 | ||
79e53945 JB |
5420 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
5421 | if (ret) { | |
5422 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
5423 | return ret; | |
5424 | } | |
5425 | ||
5426 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 5427 | intel_fb->obj = obj; |
79e53945 JB |
5428 | return 0; |
5429 | } | |
5430 | ||
79e53945 JB |
5431 | static struct drm_framebuffer * |
5432 | intel_user_framebuffer_create(struct drm_device *dev, | |
5433 | struct drm_file *filp, | |
5434 | struct drm_mode_fb_cmd *mode_cmd) | |
5435 | { | |
5436 | struct drm_gem_object *obj; | |
38651674 | 5437 | struct intel_framebuffer *intel_fb; |
79e53945 JB |
5438 | int ret; |
5439 | ||
5440 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
5441 | if (!obj) | |
cce13ff7 | 5442 | return ERR_PTR(-ENOENT); |
79e53945 | 5443 | |
38651674 DA |
5444 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5445 | if (!intel_fb) | |
cce13ff7 | 5446 | return ERR_PTR(-ENOMEM); |
38651674 DA |
5447 | |
5448 | ret = intel_framebuffer_init(dev, intel_fb, | |
5449 | mode_cmd, obj); | |
79e53945 | 5450 | if (ret) { |
bc9025bd | 5451 | drm_gem_object_unreference_unlocked(obj); |
38651674 | 5452 | kfree(intel_fb); |
cce13ff7 | 5453 | return ERR_PTR(ret); |
79e53945 JB |
5454 | } |
5455 | ||
38651674 | 5456 | return &intel_fb->base; |
79e53945 JB |
5457 | } |
5458 | ||
79e53945 | 5459 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 5460 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 5461 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
5462 | }; |
5463 | ||
9ea8d059 | 5464 | static struct drm_gem_object * |
aa40d6bb | 5465 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 5466 | { |
aa40d6bb | 5467 | struct drm_gem_object *ctx; |
9ea8d059 CW |
5468 | int ret; |
5469 | ||
aa40d6bb ZN |
5470 | ctx = i915_gem_alloc_object(dev, 4096); |
5471 | if (!ctx) { | |
9ea8d059 CW |
5472 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
5473 | return NULL; | |
5474 | } | |
5475 | ||
5476 | mutex_lock(&dev->struct_mutex); | |
aa40d6bb | 5477 | ret = i915_gem_object_pin(ctx, 4096); |
9ea8d059 CW |
5478 | if (ret) { |
5479 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
5480 | goto err_unref; | |
5481 | } | |
5482 | ||
aa40d6bb | 5483 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
5484 | if (ret) { |
5485 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
5486 | goto err_unpin; | |
5487 | } | |
5488 | mutex_unlock(&dev->struct_mutex); | |
5489 | ||
aa40d6bb | 5490 | return ctx; |
9ea8d059 CW |
5491 | |
5492 | err_unpin: | |
aa40d6bb | 5493 | i915_gem_object_unpin(ctx); |
9ea8d059 | 5494 | err_unref: |
aa40d6bb | 5495 | drm_gem_object_unreference(ctx); |
9ea8d059 CW |
5496 | mutex_unlock(&dev->struct_mutex); |
5497 | return NULL; | |
5498 | } | |
5499 | ||
7648fa99 JB |
5500 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
5501 | { | |
5502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5503 | u16 rgvswctl; | |
5504 | ||
5505 | rgvswctl = I915_READ16(MEMSWCTL); | |
5506 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5507 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5508 | return false; /* still busy with another command */ | |
5509 | } | |
5510 | ||
5511 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5512 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5513 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5514 | POSTING_READ16(MEMSWCTL); | |
5515 | ||
5516 | rgvswctl |= MEMCTL_CMD_STS; | |
5517 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5518 | ||
5519 | return true; | |
5520 | } | |
5521 | ||
f97108d1 JB |
5522 | void ironlake_enable_drps(struct drm_device *dev) |
5523 | { | |
5524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5525 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 5526 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 5527 | |
ea056c14 JB |
5528 | /* Enable temp reporting */ |
5529 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
5530 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
5531 | ||
f97108d1 JB |
5532 | /* 100ms RC evaluation intervals */ |
5533 | I915_WRITE(RCUPEI, 100000); | |
5534 | I915_WRITE(RCDNEI, 100000); | |
5535 | ||
5536 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5537 | I915_WRITE(RCBMAXAVG, 90000); | |
5538 | I915_WRITE(RCBMINAVG, 80000); | |
5539 | ||
5540 | I915_WRITE(MEMIHYST, 1); | |
5541 | ||
5542 | /* Set up min, max, and cur for interrupt handling */ | |
5543 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5544 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5545 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5546 | MEMMODE_FSTART_SHIFT; | |
7648fa99 JB |
5547 | fstart = fmax; |
5548 | ||
f97108d1 JB |
5549 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
5550 | PXVFREQ_PX_SHIFT; | |
5551 | ||
7648fa99 JB |
5552 | dev_priv->fmax = fstart; /* IPS callback will increase this */ |
5553 | dev_priv->fstart = fstart; | |
5554 | ||
5555 | dev_priv->max_delay = fmax; | |
f97108d1 JB |
5556 | dev_priv->min_delay = fmin; |
5557 | dev_priv->cur_delay = fstart; | |
5558 | ||
7648fa99 JB |
5559 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin, |
5560 | fstart); | |
5561 | ||
f97108d1 JB |
5562 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
5563 | ||
5564 | /* | |
5565 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5566 | */ | |
5567 | ||
5568 | I915_WRITE(VIDSTART, vstart); | |
5569 | POSTING_READ(VIDSTART); | |
5570 | ||
5571 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5572 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5573 | ||
481b6af3 | 5574 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 5575 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
5576 | msleep(1); |
5577 | ||
7648fa99 | 5578 | ironlake_set_drps(dev, fstart); |
f97108d1 | 5579 | |
7648fa99 JB |
5580 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
5581 | I915_READ(0x112e0); | |
5582 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
5583 | dev_priv->last_count2 = I915_READ(0x112f4); | |
5584 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
5585 | } |
5586 | ||
5587 | void ironlake_disable_drps(struct drm_device *dev) | |
5588 | { | |
5589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5590 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
5591 | |
5592 | /* Ack interrupts, disable EFC interrupt */ | |
5593 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5594 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5595 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5596 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5597 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5598 | ||
5599 | /* Go back to the starting frequency */ | |
7648fa99 | 5600 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
5601 | msleep(1); |
5602 | rgvswctl |= MEMCTL_CMD_STS; | |
5603 | I915_WRITE(MEMSWCTL, rgvswctl); | |
5604 | msleep(1); | |
5605 | ||
5606 | } | |
5607 | ||
7648fa99 JB |
5608 | static unsigned long intel_pxfreq(u32 vidfreq) |
5609 | { | |
5610 | unsigned long freq; | |
5611 | int div = (vidfreq & 0x3f0000) >> 16; | |
5612 | int post = (vidfreq & 0x3000) >> 12; | |
5613 | int pre = (vidfreq & 0x7); | |
5614 | ||
5615 | if (!pre) | |
5616 | return 0; | |
5617 | ||
5618 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5619 | ||
5620 | return freq; | |
5621 | } | |
5622 | ||
5623 | void intel_init_emon(struct drm_device *dev) | |
5624 | { | |
5625 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5626 | u32 lcfuse; | |
5627 | u8 pxw[16]; | |
5628 | int i; | |
5629 | ||
5630 | /* Disable to program */ | |
5631 | I915_WRITE(ECR, 0); | |
5632 | POSTING_READ(ECR); | |
5633 | ||
5634 | /* Program energy weights for various events */ | |
5635 | I915_WRITE(SDEW, 0x15040d00); | |
5636 | I915_WRITE(CSIEW0, 0x007f0000); | |
5637 | I915_WRITE(CSIEW1, 0x1e220004); | |
5638 | I915_WRITE(CSIEW2, 0x04000004); | |
5639 | ||
5640 | for (i = 0; i < 5; i++) | |
5641 | I915_WRITE(PEW + (i * 4), 0); | |
5642 | for (i = 0; i < 3; i++) | |
5643 | I915_WRITE(DEW + (i * 4), 0); | |
5644 | ||
5645 | /* Program P-state weights to account for frequency power adjustment */ | |
5646 | for (i = 0; i < 16; i++) { | |
5647 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5648 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5649 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5650 | PXVFREQ_PX_SHIFT; | |
5651 | unsigned long val; | |
5652 | ||
5653 | val = vid * vid; | |
5654 | val *= (freq / 1000); | |
5655 | val *= 255; | |
5656 | val /= (127*127*900); | |
5657 | if (val > 0xff) | |
5658 | DRM_ERROR("bad pxval: %ld\n", val); | |
5659 | pxw[i] = val; | |
5660 | } | |
5661 | /* Render standby states get 0 weight */ | |
5662 | pxw[14] = 0; | |
5663 | pxw[15] = 0; | |
5664 | ||
5665 | for (i = 0; i < 4; i++) { | |
5666 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5667 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5668 | I915_WRITE(PXW + (i * 4), val); | |
5669 | } | |
5670 | ||
5671 | /* Adjust magic regs to magic values (more experimental results) */ | |
5672 | I915_WRITE(OGW0, 0); | |
5673 | I915_WRITE(OGW1, 0); | |
5674 | I915_WRITE(EG0, 0x00007f00); | |
5675 | I915_WRITE(EG1, 0x0000000e); | |
5676 | I915_WRITE(EG2, 0x000e0000); | |
5677 | I915_WRITE(EG3, 0x68000300); | |
5678 | I915_WRITE(EG4, 0x42000000); | |
5679 | I915_WRITE(EG5, 0x00140031); | |
5680 | I915_WRITE(EG6, 0); | |
5681 | I915_WRITE(EG7, 0); | |
5682 | ||
5683 | for (i = 0; i < 8; i++) | |
5684 | I915_WRITE(PXWL + (i * 4), 0); | |
5685 | ||
5686 | /* Enable PMON + select events */ | |
5687 | I915_WRITE(ECR, 0x80000019); | |
5688 | ||
5689 | lcfuse = I915_READ(LCFUSE02); | |
5690 | ||
5691 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
5692 | } | |
5693 | ||
652c393a JB |
5694 | void intel_init_clock_gating(struct drm_device *dev) |
5695 | { | |
5696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5697 | ||
5698 | /* | |
5699 | * Disable clock gating reported to work incorrectly according to the | |
5700 | * specs, but enable as much else as we can. | |
5701 | */ | |
bad720ff | 5702 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
5703 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
5704 | ||
5705 | if (IS_IRONLAKE(dev)) { | |
5706 | /* Required for FBC */ | |
5707 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | |
5708 | /* Required for CxSR */ | |
5709 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
5710 | ||
5711 | I915_WRITE(PCH_3DCGDIS0, | |
5712 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5713 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5714 | } | |
5715 | ||
5716 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 ZW |
5717 | |
5718 | /* | |
5719 | * According to the spec the following bits should be set in | |
5720 | * order to enable memory self-refresh | |
5721 | * The bit 22/21 of 0x42004 | |
5722 | * The bit 5 of 0x42020 | |
5723 | * The bit 15 of 0x45000 | |
5724 | */ | |
5725 | if (IS_IRONLAKE(dev)) { | |
5726 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5727 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5728 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
5729 | I915_WRITE(ILK_DSPCLK_GATE, | |
5730 | (I915_READ(ILK_DSPCLK_GATE) | | |
5731 | ILK_DPARB_CLK_GATE)); | |
5732 | I915_WRITE(DISP_ARB_CTL, | |
5733 | (I915_READ(DISP_ARB_CTL) | | |
5734 | DISP_FBC_WM_DIS)); | |
dd8849c8 JB |
5735 | I915_WRITE(WM3_LP_ILK, 0); |
5736 | I915_WRITE(WM2_LP_ILK, 0); | |
5737 | I915_WRITE(WM1_LP_ILK, 0); | |
7f8a8569 | 5738 | } |
b52eb4dc ZY |
5739 | /* |
5740 | * Based on the document from hardware guys the following bits | |
5741 | * should be set unconditionally in order to enable FBC. | |
5742 | * The bit 22 of 0x42000 | |
5743 | * The bit 22 of 0x42004 | |
5744 | * The bit 7,8,9 of 0x42020. | |
5745 | */ | |
5746 | if (IS_IRONLAKE_M(dev)) { | |
5747 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5748 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5749 | ILK_FBCQ_DIS); | |
5750 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5751 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5752 | ILK_DPARB_GATE); | |
5753 | I915_WRITE(ILK_DSPCLK_GATE, | |
5754 | I915_READ(ILK_DSPCLK_GATE) | | |
5755 | ILK_DPFC_DIS1 | | |
5756 | ILK_DPFC_DIS2 | | |
5757 | ILK_CLK_FBC); | |
5758 | } | |
bc41606a | 5759 | return; |
c03342fa | 5760 | } else if (IS_G4X(dev)) { |
652c393a JB |
5761 | uint32_t dspclk_gate; |
5762 | I915_WRITE(RENCLK_GATE_D1, 0); | |
5763 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
5764 | GS_UNIT_CLOCK_GATE_DISABLE | | |
5765 | CL_UNIT_CLOCK_GATE_DISABLE); | |
5766 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5767 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
5768 | OVRUNIT_CLOCK_GATE_DISABLE | | |
5769 | OVCUNIT_CLOCK_GATE_DISABLE; | |
5770 | if (IS_GM45(dev)) | |
5771 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
5772 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
a6c45cf0 | 5773 | } else if (IS_CRESTLINE(dev)) { |
652c393a JB |
5774 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
5775 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5776 | I915_WRITE(DSPCLK_GATE_D, 0); | |
5777 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5778 | I915_WRITE16(DEUC, 0); | |
a6c45cf0 | 5779 | } else if (IS_BROADWATER(dev)) { |
652c393a JB |
5780 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
5781 | I965_RCC_CLOCK_GATE_DISABLE | | |
5782 | I965_RCPB_CLOCK_GATE_DISABLE | | |
5783 | I965_ISC_CLOCK_GATE_DISABLE | | |
5784 | I965_FBC_CLOCK_GATE_DISABLE); | |
5785 | I915_WRITE(RENCLK_GATE_D2, 0); | |
a6c45cf0 | 5786 | } else if (IS_GEN3(dev)) { |
652c393a JB |
5787 | u32 dstate = I915_READ(D_STATE); |
5788 | ||
5789 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
5790 | DSTATE_DOT_CLOCK_GATING; | |
5791 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 5792 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
5793 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
5794 | } else if (IS_I830(dev)) { | |
5795 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
5796 | } | |
97f5ab66 JB |
5797 | |
5798 | /* | |
5799 | * GPU can automatically power down the render unit if given a page | |
5800 | * to save state. | |
5801 | */ | |
aa40d6bb ZN |
5802 | if (IS_IRONLAKE_M(dev)) { |
5803 | if (dev_priv->renderctx == NULL) | |
5804 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
5805 | if (dev_priv->renderctx) { | |
5806 | struct drm_i915_gem_object *obj_priv; | |
5807 | obj_priv = to_intel_bo(dev_priv->renderctx); | |
5808 | if (obj_priv) { | |
5809 | BEGIN_LP_RING(4); | |
5810 | OUT_RING(MI_SET_CONTEXT); | |
5811 | OUT_RING(obj_priv->gtt_offset | | |
5812 | MI_MM_SPACE_GTT | | |
5813 | MI_SAVE_EXT_STATE_EN | | |
5814 | MI_RESTORE_EXT_STATE_EN | | |
5815 | MI_RESTORE_INHIBIT); | |
5816 | OUT_RING(MI_NOOP); | |
5817 | OUT_RING(MI_FLUSH); | |
5818 | ADVANCE_LP_RING(); | |
5819 | } | |
bc41606a | 5820 | } else |
aa40d6bb | 5821 | DRM_DEBUG_KMS("Failed to allocate render context." |
bc41606a | 5822 | "Disable RC6\n"); |
aa40d6bb ZN |
5823 | } |
5824 | ||
1d3c36ad | 5825 | if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { |
9ea8d059 | 5826 | struct drm_i915_gem_object *obj_priv = NULL; |
97f5ab66 | 5827 | |
7e8b60fa | 5828 | if (dev_priv->pwrctx) { |
23010e43 | 5829 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
7e8b60fa | 5830 | } else { |
9ea8d059 | 5831 | struct drm_gem_object *pwrctx; |
97f5ab66 | 5832 | |
aa40d6bb | 5833 | pwrctx = intel_alloc_context_page(dev); |
9ea8d059 CW |
5834 | if (pwrctx) { |
5835 | dev_priv->pwrctx = pwrctx; | |
23010e43 | 5836 | obj_priv = to_intel_bo(pwrctx); |
7e8b60fa | 5837 | } |
7e8b60fa | 5838 | } |
97f5ab66 | 5839 | |
9ea8d059 CW |
5840 | if (obj_priv) { |
5841 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN); | |
5842 | I915_WRITE(MCHBAR_RENDER_STANDBY, | |
5843 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); | |
5844 | } | |
97f5ab66 | 5845 | } |
652c393a JB |
5846 | } |
5847 | ||
e70236a8 JB |
5848 | /* Set up chip specific display functions */ |
5849 | static void intel_init_display(struct drm_device *dev) | |
5850 | { | |
5851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5852 | ||
5853 | /* We always want a DPMS function */ | |
bad720ff | 5854 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 5855 | dev_priv->display.dpms = ironlake_crtc_dpms; |
e70236a8 JB |
5856 | else |
5857 | dev_priv->display.dpms = i9xx_crtc_dpms; | |
5858 | ||
ee5382ae | 5859 | if (I915_HAS_FBC(dev)) { |
b52eb4dc ZY |
5860 | if (IS_IRONLAKE_M(dev)) { |
5861 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
5862 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
5863 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
5864 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
5865 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
5866 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
5867 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 5868 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
5869 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
5870 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
5871 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
5872 | } | |
74dff282 | 5873 | /* 855GM needs testing */ |
e70236a8 JB |
5874 | } |
5875 | ||
5876 | /* Returns the core display clock speed */ | |
f2b115e6 | 5877 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
5878 | dev_priv->display.get_display_clock_speed = |
5879 | i945_get_display_clock_speed; | |
5880 | else if (IS_I915G(dev)) | |
5881 | dev_priv->display.get_display_clock_speed = | |
5882 | i915_get_display_clock_speed; | |
f2b115e6 | 5883 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
5884 | dev_priv->display.get_display_clock_speed = |
5885 | i9xx_misc_get_display_clock_speed; | |
5886 | else if (IS_I915GM(dev)) | |
5887 | dev_priv->display.get_display_clock_speed = | |
5888 | i915gm_get_display_clock_speed; | |
5889 | else if (IS_I865G(dev)) | |
5890 | dev_priv->display.get_display_clock_speed = | |
5891 | i865_get_display_clock_speed; | |
f0f8a9ce | 5892 | else if (IS_I85X(dev)) |
e70236a8 JB |
5893 | dev_priv->display.get_display_clock_speed = |
5894 | i855_get_display_clock_speed; | |
5895 | else /* 852, 830 */ | |
5896 | dev_priv->display.get_display_clock_speed = | |
5897 | i830_get_display_clock_speed; | |
5898 | ||
5899 | /* For FIFO watermark updates */ | |
7f8a8569 ZW |
5900 | if (HAS_PCH_SPLIT(dev)) { |
5901 | if (IS_IRONLAKE(dev)) { | |
5902 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) | |
5903 | dev_priv->display.update_wm = ironlake_update_wm; | |
5904 | else { | |
5905 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
5906 | "Disable CxSR\n"); | |
5907 | dev_priv->display.update_wm = NULL; | |
5908 | } | |
5909 | } else | |
5910 | dev_priv->display.update_wm = NULL; | |
5911 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 5912 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 5913 | dev_priv->is_ddr3, |
d4294342 ZY |
5914 | dev_priv->fsb_freq, |
5915 | dev_priv->mem_freq)) { | |
5916 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 5917 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 5918 | "disabling CxSR\n", |
95534263 | 5919 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
5920 | dev_priv->fsb_freq, dev_priv->mem_freq); |
5921 | /* Disable CxSR and never update its watermark again */ | |
5922 | pineview_disable_cxsr(dev); | |
5923 | dev_priv->display.update_wm = NULL; | |
5924 | } else | |
5925 | dev_priv->display.update_wm = pineview_update_wm; | |
5926 | } else if (IS_G4X(dev)) | |
e70236a8 | 5927 | dev_priv->display.update_wm = g4x_update_wm; |
a6c45cf0 | 5928 | else if (IS_GEN4(dev)) |
e70236a8 | 5929 | dev_priv->display.update_wm = i965_update_wm; |
a6c45cf0 | 5930 | else if (IS_GEN3(dev)) { |
e70236a8 JB |
5931 | dev_priv->display.update_wm = i9xx_update_wm; |
5932 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
5933 | } else if (IS_I85X(dev)) { |
5934 | dev_priv->display.update_wm = i9xx_update_wm; | |
5935 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 5936 | } else { |
8f4695ed AJ |
5937 | dev_priv->display.update_wm = i830_update_wm; |
5938 | if (IS_845G(dev)) | |
e70236a8 JB |
5939 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
5940 | else | |
5941 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
5942 | } |
5943 | } | |
5944 | ||
b690e96c JB |
5945 | /* |
5946 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
5947 | * resume, or other times. This quirk makes sure that's the case for | |
5948 | * affected systems. | |
5949 | */ | |
5950 | static void quirk_pipea_force (struct drm_device *dev) | |
5951 | { | |
5952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5953 | ||
5954 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
5955 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
5956 | } | |
5957 | ||
5958 | struct intel_quirk { | |
5959 | int device; | |
5960 | int subsystem_vendor; | |
5961 | int subsystem_device; | |
5962 | void (*hook)(struct drm_device *dev); | |
5963 | }; | |
5964 | ||
5965 | struct intel_quirk intel_quirks[] = { | |
5966 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
5967 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
5968 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
5969 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
5970 | ||
5971 | /* Thinkpad R31 needs pipe A force quirk */ | |
5972 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
5973 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
5974 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
5975 | ||
5976 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
5977 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
5978 | /* ThinkPad X40 needs pipe A force quirk */ | |
5979 | ||
5980 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
5981 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
5982 | ||
5983 | /* 855 & before need to leave pipe A & dpll A up */ | |
5984 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
5985 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
5986 | }; | |
5987 | ||
5988 | static void intel_init_quirks(struct drm_device *dev) | |
5989 | { | |
5990 | struct pci_dev *d = dev->pdev; | |
5991 | int i; | |
5992 | ||
5993 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
5994 | struct intel_quirk *q = &intel_quirks[i]; | |
5995 | ||
5996 | if (d->device == q->device && | |
5997 | (d->subsystem_vendor == q->subsystem_vendor || | |
5998 | q->subsystem_vendor == PCI_ANY_ID) && | |
5999 | (d->subsystem_device == q->subsystem_device || | |
6000 | q->subsystem_device == PCI_ANY_ID)) | |
6001 | q->hook(dev); | |
6002 | } | |
6003 | } | |
6004 | ||
9cce37f4 JB |
6005 | /* Disable the VGA plane that we never use */ |
6006 | static void i915_disable_vga(struct drm_device *dev) | |
6007 | { | |
6008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6009 | u8 sr1; | |
6010 | u32 vga_reg; | |
6011 | ||
6012 | if (HAS_PCH_SPLIT(dev)) | |
6013 | vga_reg = CPU_VGACNTRL; | |
6014 | else | |
6015 | vga_reg = VGACNTRL; | |
6016 | ||
6017 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6018 | outb(1, VGA_SR_INDEX); | |
6019 | sr1 = inb(VGA_SR_DATA); | |
6020 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6021 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6022 | udelay(300); | |
6023 | ||
6024 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6025 | POSTING_READ(vga_reg); | |
6026 | } | |
6027 | ||
79e53945 JB |
6028 | void intel_modeset_init(struct drm_device *dev) |
6029 | { | |
652c393a | 6030 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6031 | int i; |
6032 | ||
6033 | drm_mode_config_init(dev); | |
6034 | ||
6035 | dev->mode_config.min_width = 0; | |
6036 | dev->mode_config.min_height = 0; | |
6037 | ||
6038 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
6039 | ||
b690e96c JB |
6040 | intel_init_quirks(dev); |
6041 | ||
e70236a8 JB |
6042 | intel_init_display(dev); |
6043 | ||
a6c45cf0 CW |
6044 | if (IS_GEN2(dev)) { |
6045 | dev->mode_config.max_width = 2048; | |
6046 | dev->mode_config.max_height = 2048; | |
6047 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
6048 | dev->mode_config.max_width = 4096; |
6049 | dev->mode_config.max_height = 4096; | |
79e53945 | 6050 | } else { |
a6c45cf0 CW |
6051 | dev->mode_config.max_width = 8192; |
6052 | dev->mode_config.max_height = 8192; | |
79e53945 JB |
6053 | } |
6054 | ||
6055 | /* set memory base */ | |
a6c45cf0 | 6056 | if (IS_GEN2(dev)) |
79e53945 | 6057 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); |
a6c45cf0 CW |
6058 | else |
6059 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
79e53945 | 6060 | |
a6c45cf0 | 6061 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
a3524f1b | 6062 | dev_priv->num_pipe = 2; |
79e53945 | 6063 | else |
a3524f1b | 6064 | dev_priv->num_pipe = 1; |
28c97730 | 6065 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6066 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6067 | |
a3524f1b | 6068 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
6069 | intel_crtc_init(dev, i); |
6070 | } | |
6071 | ||
6072 | intel_setup_outputs(dev); | |
652c393a JB |
6073 | |
6074 | intel_init_clock_gating(dev); | |
6075 | ||
9cce37f4 JB |
6076 | /* Just disable it once at startup */ |
6077 | i915_disable_vga(dev); | |
6078 | ||
7648fa99 | 6079 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 6080 | ironlake_enable_drps(dev); |
7648fa99 JB |
6081 | intel_init_emon(dev); |
6082 | } | |
f97108d1 | 6083 | |
652c393a JB |
6084 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6085 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6086 | (unsigned long)dev); | |
02e792fb DV |
6087 | |
6088 | intel_setup_overlay(dev); | |
79e53945 JB |
6089 | } |
6090 | ||
6091 | void intel_modeset_cleanup(struct drm_device *dev) | |
6092 | { | |
652c393a JB |
6093 | struct drm_i915_private *dev_priv = dev->dev_private; |
6094 | struct drm_crtc *crtc; | |
6095 | struct intel_crtc *intel_crtc; | |
6096 | ||
6097 | mutex_lock(&dev->struct_mutex); | |
6098 | ||
eb1f8e4f | 6099 | drm_kms_helper_poll_fini(dev); |
38651674 DA |
6100 | intel_fbdev_fini(dev); |
6101 | ||
652c393a JB |
6102 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6103 | /* Skip inactive CRTCs */ | |
6104 | if (!crtc->fb) | |
6105 | continue; | |
6106 | ||
6107 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6108 | intel_increase_pllclock(crtc); |
652c393a JB |
6109 | } |
6110 | ||
e70236a8 JB |
6111 | if (dev_priv->display.disable_fbc) |
6112 | dev_priv->display.disable_fbc(dev); | |
6113 | ||
aa40d6bb ZN |
6114 | if (dev_priv->renderctx) { |
6115 | struct drm_i915_gem_object *obj_priv; | |
6116 | ||
6117 | obj_priv = to_intel_bo(dev_priv->renderctx); | |
6118 | I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN); | |
6119 | I915_READ(CCID); | |
6120 | i915_gem_object_unpin(dev_priv->renderctx); | |
6121 | drm_gem_object_unreference(dev_priv->renderctx); | |
6122 | } | |
6123 | ||
97f5ab66 | 6124 | if (dev_priv->pwrctx) { |
c1b5dea0 KH |
6125 | struct drm_i915_gem_object *obj_priv; |
6126 | ||
23010e43 | 6127 | obj_priv = to_intel_bo(dev_priv->pwrctx); |
c1b5dea0 KH |
6128 | I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN); |
6129 | I915_READ(PWRCTXA); | |
97f5ab66 JB |
6130 | i915_gem_object_unpin(dev_priv->pwrctx); |
6131 | drm_gem_object_unreference(dev_priv->pwrctx); | |
6132 | } | |
6133 | ||
f97108d1 JB |
6134 | if (IS_IRONLAKE_M(dev)) |
6135 | ironlake_disable_drps(dev); | |
6136 | ||
69341a5e KH |
6137 | mutex_unlock(&dev->struct_mutex); |
6138 | ||
6c0d9350 DV |
6139 | /* Disable the irq before mode object teardown, for the irq might |
6140 | * enqueue unpin/hotplug work. */ | |
6141 | drm_irq_uninstall(dev); | |
6142 | cancel_work_sync(&dev_priv->hotplug_work); | |
6143 | ||
3dec0095 DV |
6144 | /* Shut off idle work before the crtcs get freed. */ |
6145 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6146 | intel_crtc = to_intel_crtc(crtc); | |
6147 | del_timer_sync(&intel_crtc->idle_timer); | |
6148 | } | |
6149 | del_timer_sync(&dev_priv->idle_timer); | |
6150 | cancel_work_sync(&dev_priv->idle_work); | |
6151 | ||
79e53945 JB |
6152 | drm_mode_config_cleanup(dev); |
6153 | } | |
6154 | ||
f1c79df3 ZW |
6155 | /* |
6156 | * Return which encoder is currently attached for connector. | |
6157 | */ | |
df0e9248 | 6158 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6159 | { |
df0e9248 CW |
6160 | return &intel_attached_encoder(connector)->base; |
6161 | } | |
f1c79df3 | 6162 | |
df0e9248 CW |
6163 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6164 | struct intel_encoder *encoder) | |
6165 | { | |
6166 | connector->encoder = encoder; | |
6167 | drm_mode_connector_attach_encoder(&connector->base, | |
6168 | &encoder->base); | |
79e53945 | 6169 | } |
28d52043 DA |
6170 | |
6171 | /* | |
6172 | * set vga decode state - true == enable VGA decode | |
6173 | */ | |
6174 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6175 | { | |
6176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6177 | u16 gmch_ctrl; | |
6178 | ||
6179 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6180 | if (state) | |
6181 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6182 | else | |
6183 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6184 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6185 | return 0; | |
6186 | } |