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drm/i915: rip out an unused lvds_reg variable
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 654 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666 max_n = limit->n.max;
f77f13e2 667 /* based on hardware requirement, prefer smaller n to precision */
d4906093 668 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 669 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 670 for (clock.m1 = limit->m1.max;
671 clock.m1 >= limit->m1.min; clock.m1--) {
672 for (clock.m2 = limit->m2.max;
673 clock.m2 >= limit->m2.min; clock.m2--) {
674 for (clock.p1 = limit->p1.max;
675 clock.p1 >= limit->p1.min; clock.p1--) {
676 int this_err;
677
2177832f 678 intel_clock(dev, refclk, &clock);
1b894b59
CW		 679 if (!intel_PLL_is_valid(dev, limit,
680 &clock))
d4906093 681 continue;
1b894b59
CW		 682
683 this_err = abs(clock.dot - target);
d4906093
ML		 684 if (this_err < err_most) {
685 *best_clock = clock;
686 err_most = this_err;
687 max_n = clock.n;
688 found = true;
689 }
690 }
691 }
692 }
693 }
2c07245f
ZW		 694 return found;
695}
696
a0c4da24
JB		 697static bool
698intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
701{
702 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
703 u32 m, n, fastclk;
704 u32 updrate, minupdate, fracbits, p;
705 unsigned long bestppm, ppm, absppm;
706 int dotclk, flag;
707
af447bd3 708 flag = 0;
a0c4da24
JB		 709 dotclk = target * 1000;
710 bestppm = 1000000;
711 ppm = absppm = 0;
712 fastclk = dotclk / (2*100);
713 updrate = 0;
714 minupdate = 19200;
715 fracbits = 1;
716 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
717 bestm1 = bestm2 = bestp1 = bestp2 = 0;
718
719 /* based on hardware requirement, prefer smaller n to precision */
720 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
721 updrate = refclk / n;
722 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
723 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
724 if (p2 > 10)
725 p2 = p2 - 1;
726 p = p1 * p2;
727 /* based on hardware requirement, prefer bigger m1,m2 values */
728 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
729 m2 = (((2*(fastclk * p * n / m1 )) +
730 refclk) / (2*refclk));
731 m = m1 * m2;
732 vco = updrate * m;
733 if (vco >= limit->vco.min && vco < limit->vco.max) {
734 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
735 absppm = (ppm > 0) ? ppm : (-ppm);
736 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
737 bestppm = 0;
738 flag = 1;
739 }
740 if (absppm < bestppm - 10) {
741 bestppm = absppm;
742 flag = 1;
743 }
744 if (flag) {
745 bestn = n;
746 bestm1 = m1;
747 bestm2 = m2;
748 bestp1 = p1;
749 bestp2 = p2;
750 flag = 0;
751 }
752 }
753 }
754 }
755 }
756 }
757 best_clock->n = bestn;
758 best_clock->m1 = bestm1;
759 best_clock->m2 = bestm2;
760 best_clock->p1 = bestp1;
761 best_clock->p2 = bestp2;
762
763 return true;
764}
a4fc5ed6 765
a5c961d1
PZ		 766enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
767 enum pipe pipe)
768{
769 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
771
3b117c8f 772 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 773}
774
a928d536
PZ		 775static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
776{
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 u32 frame, frame_reg = PIPEFRAME(pipe);
779
780 frame = I915_READ(frame_reg);
781
782 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
783 DRM_DEBUG_KMS("vblank wait timed out\n");
784}
785
9d0498a2
JB		 786/**
787 * intel_wait_for_vblank - wait for vblank on a given pipe
788 * @dev: drm device
789 * @pipe: pipe to wait for
790 *
791 * Wait for vblank to occur on a given pipe. Needed for various bits of
792 * mode setting code.
793 */
794void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 795{
9d0498a2 796 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 797 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 798
a928d536
PZ		 799 if (INTEL_INFO(dev)->gen >= 5) {
800 ironlake_wait_for_vblank(dev, pipe);
801 return;
802 }
803
300387c0
CW		 804 /* Clear existing vblank status. Note this will clear any other
805 * sticky status fields as well.
806 *
807 * This races with i915_driver_irq_handler() with the result
808 * that either function could miss a vblank event. Here it is not
809 * fatal, as we will either wait upon the next vblank interrupt or
810 * timeout. Generally speaking intel_wait_for_vblank() is only
811 * called during modeset at which time the GPU should be idle and
812 * should *not* be performing page flips and thus not waiting on
813 * vblanks...
814 * Currently, the result of us stealing a vblank from the irq
815 * handler is that a single frame will be skipped during swapbuffers.
816 */
817 I915_WRITE(pipestat_reg,
818 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
819
9d0498a2 820 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 821 if (wait_for(I915_READ(pipestat_reg) &
822 PIPE_VBLANK_INTERRUPT_STATUS,
823 50))
9d0498a2
JB		 824 DRM_DEBUG_KMS("vblank wait timed out\n");
825}
826
ab7ad7f6
KP		 827/*
828 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 829 * @dev: drm device
830 * @pipe: pipe to wait for
831 *
832 * After disabling a pipe, we can't wait for vblank in the usual way,
833 * spinning on the vblank interrupt status bit, since we won't actually
834 * see an interrupt when the pipe is disabled.
835 *
ab7ad7f6
KP		 836 * On Gen4 and above:
837 * wait for the pipe register state bit to turn off
838 *
839 * Otherwise:
840 * wait for the display line value to settle (it usually
841 * ends up stopping at the start of the next frame).
58e10eb9 842 *
9d0498a2 843 */
58e10eb9 844void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 847 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
848 pipe);
ab7ad7f6
KP		 849
850 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 851 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 852
853 /* Wait for the Pipe State to go off */
58e10eb9
CW		 854 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
855 100))
284637d9 856 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 857 } else {
837ba00f 858 u32 last_line, line_mask;
58e10eb9 859 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 860 unsigned long timeout = jiffies + msecs_to_jiffies(100);
861
837ba00f
PZ		 862 if (IS_GEN2(dev))
863 line_mask = DSL_LINEMASK_GEN2;
864 else
865 line_mask = DSL_LINEMASK_GEN3;
866
ab7ad7f6
KP		 867 /* Wait for the display line to settle */
868 do {
837ba00f 869 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 870 mdelay(5);
837ba00f 871 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 872 time_after(timeout, jiffies));
873 if (time_after(jiffies, timeout))
284637d9 874 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 875 }
79e53945
JB		 876}
877
b0ea7d37
DL		 878/*
879 * ibx_digital_port_connected - is the specified port connected?
880 * @dev_priv: i915 private structure
881 * @port: the port to test
882 *
883 * Returns true if @port is connected, false otherwise.
884 */
885bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
886 struct intel_digital_port *port)
887{
888 u32 bit;
889
c36346e3
DL		 890 if (HAS_PCH_IBX(dev_priv->dev)) {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG;
900 break;
901 default:
902 return true;
903 }
904 } else {
905 switch(port->port) {
906 case PORT_B:
907 bit = SDE_PORTB_HOTPLUG_CPT;
908 break;
909 case PORT_C:
910 bit = SDE_PORTC_HOTPLUG_CPT;
911 break;
912 case PORT_D:
913 bit = SDE_PORTD_HOTPLUG_CPT;
914 break;
915 default:
916 return true;
917 }
b0ea7d37
DL		 918 }
919
920 return I915_READ(SDEISR) & bit;
921}
922
b24e7179
JB		 923static const char *state_string(bool enabled)
924{
925 return enabled ? "on" : "off";
926}
927
928/* Only for pre-ILK configs */
929static void assert_pll(struct drm_i915_private *dev_priv,
930 enum pipe pipe, bool state)
931{
932 int reg;
933 u32 val;
934 bool cur_state;
935
936 reg = DPLL(pipe);
937 val = I915_READ(reg);
938 cur_state = !!(val & DPLL_VCO_ENABLE);
939 WARN(cur_state != state,
940 "PLL state assertion failure (expected %s, current %s)\n",
941 state_string(state), state_string(cur_state));
942}
943#define assert_pll_enabled(d, p) assert_pll(d, p, true)
944#define assert_pll_disabled(d, p) assert_pll(d, p, false)
945
040484af
JB		 946/* For ILK+ */
947static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 948 struct intel_pch_pll *pll,
949 struct intel_crtc *crtc,
950 bool state)
040484af 951{
040484af
JB		 952 u32 val;
953 bool cur_state;
954
9d82aa17
ED		 955 if (HAS_PCH_LPT(dev_priv->dev)) {
956 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 return;
958 }
959
92b27b08
CW		 960 if (WARN (!pll,
961 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 962 return;
ee7b9f93 963
92b27b08
CW		 964 val = I915_READ(pll->pll_reg);
965 cur_state = !!(val & DPLL_VCO_ENABLE);
966 WARN(cur_state != state,
967 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
968 pll->pll_reg, state_string(state), state_string(cur_state), val);
969
970 /* Make sure the selected PLL is correctly attached to the transcoder */
971 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 972 u32 pch_dpll;
973
974 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 975 cur_state = pll->pll_reg == _PCH_DPLL_B;
976 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 977 "PLL[%d] not attached to this transcoder %c: %08x\n",
978 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 979 cur_state = !!(val >> (4*crtc->pipe + 3));
980 WARN(cur_state != state,
4bb6f1f3 981 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 982 pll->pll_reg == _PCH_DPLL_B,
983 state_string(state),
4bb6f1f3 984 pipe_name(crtc->pipe),
92b27b08
CW		 985 val);
986 }
d3ccbe86 987 }
040484af 988}
92b27b08
CW		 989#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
990#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 991
992static void assert_fdi_tx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
ad80a810
PZ		 998 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
999 pipe);
040484af 1000
affa9354
PZ		 1001 if (HAS_DDI(dev_priv->dev)) {
1002 /* DDI does not have a specific FDI_TX register */
ad80a810 1003 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1004 val = I915_READ(reg);
ad80a810 1005 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1006 } else {
1007 reg = FDI_TX_CTL(pipe);
1008 val = I915_READ(reg);
1009 cur_state = !!(val & FDI_TX_ENABLE);
1010 }
040484af
JB		 1011 WARN(cur_state != state,
1012 "FDI TX state assertion failure (expected %s, current %s)\n",
1013 state_string(state), state_string(cur_state));
1014}
1015#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1016#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1017
1018static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool state)
1020{
1021 int reg;
1022 u32 val;
1023 bool cur_state;
1024
d63fa0dc
PZ		 1025 reg = FDI_RX_CTL(pipe);
1026 val = I915_READ(reg);
1027 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1028 WARN(cur_state != state,
1029 "FDI RX state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1031}
1032#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1033#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1034
1035static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1036 enum pipe pipe)
1037{
1038 int reg;
1039 u32 val;
1040
1041 /* ILK FDI PLL is always enabled */
1042 if (dev_priv->info->gen == 5)
1043 return;
1044
bf507ef7 1045 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1046 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1047 return;
1048
040484af
JB		 1049 reg = FDI_TX_CTL(pipe);
1050 val = I915_READ(reg);
1051 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1052}
1053
1054static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int reg;
1058 u32 val;
1059
1060 reg = FDI_RX_CTL(pipe);
1061 val = I915_READ(reg);
1062 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1063}
1064
ea0760cf
JB		 1065static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066 enum pipe pipe)
1067{
1068 int pp_reg, lvds_reg;
1069 u32 val;
1070 enum pipe panel_pipe = PIPE_A;
0de3b485 1071 bool locked = true;
ea0760cf
JB		 1072
1073 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1074 pp_reg = PCH_PP_CONTROL;
1075 lvds_reg = PCH_LVDS;
1076 } else {
1077 pp_reg = PP_CONTROL;
1078 lvds_reg = LVDS;
1079 }
1080
1081 val = I915_READ(pp_reg);
1082 if (!(val & PANEL_POWER_ON) ||
1083 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084 locked = false;
1085
1086 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1087 panel_pipe = PIPE_B;
1088
1089 WARN(panel_pipe == pipe && locked,
1090 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1091 pipe_name(pipe));
ea0760cf
JB		 1092}
1093
b840d907
JB		 1094void assert_pipe(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
b24e7179
JB		 1096{
1097 int reg;
1098 u32 val;
63d7bbe9 1099 bool cur_state;
702e7a56
PZ		 1100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1101 pipe);
b24e7179 1102
8e636784
DV		 1103 /* if we need the pipe A quirk it must be always on */
1104 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1105 state = true;
1106
b97186f0
PZ		 1107 if (!intel_display_power_enabled(dev_priv->dev,
1108 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1109 cur_state = false;
1110 } else {
1111 reg = PIPECONF(cpu_transcoder);
1112 val = I915_READ(reg);
1113 cur_state = !!(val & PIPECONF_ENABLE);
1114 }
1115
63d7bbe9
JB		 1116 WARN(cur_state != state,
1117 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1118 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1119}
1120
931872fc
CW		 1121static void assert_plane(struct drm_i915_private *dev_priv,
1122 enum plane plane, bool state)
b24e7179
JB		 1123{
1124 int reg;
1125 u32 val;
931872fc 1126 bool cur_state;
b24e7179
JB		 1127
1128 reg = DSPCNTR(plane);
1129 val = I915_READ(reg);
931872fc
CW		 1130 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1131 WARN(cur_state != state,
1132 "plane %c assertion failure (expected %s, current %s)\n",
1133 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1137#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1138
b24e7179
JB		 1139static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141{
1142 int reg, i;
1143 u32 val;
1144 int cur_pipe;
1145
19ec1358 1146 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1147 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1148 reg = DSPCNTR(pipe);
1149 val = I915_READ(reg);
1150 WARN((val & DISPLAY_PLANE_ENABLE),
1151 "plane %c assertion failure, should be disabled but not\n",
1152 plane_name(pipe));
19ec1358 1153 return;
28c05794 1154 }
19ec1358 1155
b24e7179
JB		 1156 /* Need to check both planes against the pipe */
1157 for (i = 0; i < 2; i++) {
1158 reg = DSPCNTR(i);
1159 val = I915_READ(reg);
1160 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1161 DISPPLANE_SEL_PIPE_SHIFT;
1162 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1163 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1164 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1165 }
1166}
1167
19332d7a
JB		 1168static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170{
1171 int reg, i;
1172 u32 val;
1173
1174 if (!IS_VALLEYVIEW(dev_priv->dev))
1175 return;
1176
1177 /* Need to check both planes against the pipe */
1178 for (i = 0; i < dev_priv->num_plane; i++) {
1179 reg = SPCNTR(pipe, i);
1180 val = I915_READ(reg);
1181 WARN((val & SP_ENABLE),
06da8da2
VS		 1182 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1183 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1184 }
1185}
1186
92f2584a
JB		 1187static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1188{
1189 u32 val;
1190 bool enabled;
1191
9d82aa17
ED		 1192 if (HAS_PCH_LPT(dev_priv->dev)) {
1193 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1194 return;
1195 }
1196
92f2584a
JB		 1197 val = I915_READ(PCH_DREF_CONTROL);
1198 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1199 DREF_SUPERSPREAD_SOURCE_MASK));
1200 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1201}
1202
ab9412ba
DV		 1203static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
92f2584a
JB		 1205{
1206 int reg;
1207 u32 val;
1208 bool enabled;
1209
ab9412ba 1210 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1211 val = I915_READ(reg);
1212 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1213 WARN(enabled,
1214 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1215 pipe_name(pipe));
92f2584a
JB		 1216}
1217
4e634389
KP		 1218static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1220{
1221 if ((val & DP_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1226 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1227 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1228 return false;
1229 } else {
1230 if ((val & DP_PIPE_MASK) != (pipe << 30))
1231 return false;
1232 }
1233 return true;
1234}
1235
1519b995
KP		 1236static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
dc0fa718 1239 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1240 return false;
1241
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1243 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1244 return false;
1245 } else {
dc0fa718 1246 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1247 return false;
1248 }
1249 return true;
1250}
1251
1252static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1254{
1255 if ((val & LVDS_PORT_EN) == 0)
1256 return false;
1257
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
1259 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1260 return false;
1261 } else {
1262 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1263 return false;
1264 }
1265 return true;
1266}
1267
1268static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1270{
1271 if ((val & ADPA_DAC_ENABLE) == 0)
1272 return false;
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1275 return false;
1276 } else {
1277 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1278 return false;
1279 }
1280 return true;
1281}
1282
291906f1 1283static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1284 enum pipe pipe, int reg, u32 port_sel)
291906f1 1285{
47a05eca 1286 u32 val = I915_READ(reg);
4e634389 1287 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1288 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1289 reg, pipe_name(pipe));
de9a35ab 1290
75c5da27
DV		 1291 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1292 && (val & DP_PIPEB_SELECT),
de9a35ab 1293 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1294}
1295
1296static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, int reg)
1298{
47a05eca 1299 u32 val = I915_READ(reg);
b70ad586 1300 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1301 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1302 reg, pipe_name(pipe));
de9a35ab 1303
dc0fa718 1304 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1305 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1306 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1307}
1308
1309static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311{
1312 int reg;
1313 u32 val;
291906f1 1314
f0575e92
KP		 1315 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1316 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1317 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1318
1319 reg = PCH_ADPA;
1320 val = I915_READ(reg);
b70ad586 1321 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1322 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1323 pipe_name(pipe));
291906f1
JB		 1324
1325 reg = PCH_LVDS;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1 1330
e2debe91
PZ		 1331 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1332 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1333 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1334}
1335
63d7bbe9
JB		 1336/**
1337 * intel_enable_pll - enable a PLL
1338 * @dev_priv: i915 private structure
1339 * @pipe: pipe PLL to enable
1340 *
1341 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1342 * make sure the PLL reg is writable first though, since the panel write
1343 * protect mechanism may be enabled.
1344 *
1345 * Note! This is for pre-ILK only.
7434a255
TR		 1346 *
1347 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1348 */
1349static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1350{
1351 int reg;
1352 u32 val;
1353
58c6eaa2
DV		 1354 assert_pipe_disabled(dev_priv, pipe);
1355
63d7bbe9 1356 /* No really, not for ILK+ */
a0c4da24 1357 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1358
1359 /* PLL is protected by panel, make sure we can write it */
1360 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1361 assert_panel_unlocked(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val |= DPLL_VCO_ENABLE;
1366
1367 /* We do this three times for luck */
1368 I915_WRITE(reg, val);
1369 POSTING_READ(reg);
1370 udelay(150); /* wait for warmup */
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377}
1378
1379/**
1380 * intel_disable_pll - disable a PLL
1381 * @dev_priv: i915 private structure
1382 * @pipe: pipe PLL to disable
1383 *
1384 * Disable the PLL for @pipe, making sure the pipe is off first.
1385 *
1386 * Note! This is for pre-ILK only.
1387 */
1388static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1389{
1390 int reg;
1391 u32 val;
1392
1393 /* Don't disable pipe A or pipe A PLLs if needed */
1394 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1395 return;
1396
1397 /* Make sure the pipe isn't still relying on us */
1398 assert_pipe_disabled(dev_priv, pipe);
1399
1400 reg = DPLL(pipe);
1401 val = I915_READ(reg);
1402 val &= ~DPLL_VCO_ENABLE;
1403 I915_WRITE(reg, val);
1404 POSTING_READ(reg);
1405}
1406
a416edef
ED		 1407/* SBI access */
1408static void
988d6ee8
PZ		 1409intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1410 enum intel_sbi_destination destination)
a416edef 1411{
988d6ee8 1412 u32 tmp;
a416edef 1413
09153000 1414 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1415
39fb50f6 1416 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1417 100)) {
1418 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1419 return;
a416edef
ED		 1420 }
1421
988d6ee8
PZ		 1422 I915_WRITE(SBI_ADDR, (reg << 16));
1423 I915_WRITE(SBI_DATA, value);
1424
1425 if (destination == SBI_ICLK)
1426 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1427 else
1428 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1429 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1430
39fb50f6 1431 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1432 100)) {
1433 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1434 return;
a416edef 1435 }
a416edef
ED		 1436}
1437
1438static u32
988d6ee8
PZ		 1439intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1440 enum intel_sbi_destination destination)
a416edef 1441{
39fb50f6 1442 u32 value = 0;
09153000 1443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1444
39fb50f6 1445 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1446 100)) {
1447 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1448 return 0;
a416edef
ED		 1449 }
1450
988d6ee8
PZ		 1451 I915_WRITE(SBI_ADDR, (reg << 16));
1452
1453 if (destination == SBI_ICLK)
1454 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1455 else
1456 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1457 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1458
39fb50f6 1459 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1460 100)) {
1461 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1462 return 0;
a416edef
ED		 1463 }
1464
09153000 1465 return I915_READ(SBI_DATA);
a416edef
ED		 1466}
1467
89b667f8
JB		 1468void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1469{
1470 u32 port_mask;
1471
1472 if (!port)
1473 port_mask = DPLL_PORTB_READY_MASK;
1474 else
1475 port_mask = DPLL_PORTC_READY_MASK;
1476
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port, I915_READ(DPLL(0)));
1480}
1481
92f2584a 1482/**
b6b4e185 1483 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1486 *
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1489 */
b6b4e185 1490static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1491{
ee7b9f93 1492 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1493 struct intel_pch_pll *pll;
92f2584a
JB		 1494 int reg;
1495 u32 val;
1496
48da64a8 1497 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1498 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1499 pll = intel_crtc->pch_pll;
1500 if (pll == NULL)
1501 return;
1502
1503 if (WARN_ON(pll->refcount == 0))
1504 return;
ee7b9f93
JB		 1505
1506 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1507 pll->pll_reg, pll->active, pll->on,
1508 intel_crtc->base.base.id);
92f2584a
JB		 1509
1510 /* PCH refclock must be enabled first */
1511 assert_pch_refclk_enabled(dev_priv);
1512
ee7b9f93 1513 if (pll->active++ && pll->on) {
92b27b08 1514 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1515 return;
1516 }
1517
1518 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1519
1520 reg = pll->pll_reg;
92f2584a
JB		 1521 val = I915_READ(reg);
1522 val |= DPLL_VCO_ENABLE;
1523 I915_WRITE(reg, val);
1524 POSTING_READ(reg);
1525 udelay(200);
ee7b9f93
JB		 1526
1527 pll->on = true;
92f2584a
JB		 1528}
1529
ee7b9f93 1530static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1531{
ee7b9f93
JB		 1532 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1533 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1534 int reg;
ee7b9f93 1535 u32 val;
4c609cb8 1536
92f2584a
JB		 1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1539 if (pll == NULL)
1540 return;
92f2584a 1541
48da64a8
CW		 1542 if (WARN_ON(pll->refcount == 0))
1543 return;
7a419866 1544
ee7b9f93
JB		 1545 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1546 pll->pll_reg, pll->active, pll->on,
1547 intel_crtc->base.base.id);
7a419866 1548
48da64a8 1549 if (WARN_ON(pll->active == 0)) {
92b27b08 1550 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1551 return;
1552 }
1553
ee7b9f93 1554 if (--pll->active) {
92b27b08 1555 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1556 return;
ee7b9f93
JB		 1557 }
1558
1559 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1560
1561 /* Make sure transcoder isn't still depending on us */
ab9412ba 1562 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1563
ee7b9f93 1564 reg = pll->pll_reg;
92f2584a
JB		 1565 val = I915_READ(reg);
1566 val &= ~DPLL_VCO_ENABLE;
1567 I915_WRITE(reg, val);
1568 POSTING_READ(reg);
1569 udelay(200);
ee7b9f93
JB		 1570
1571 pll->on = false;
92f2584a
JB		 1572}
1573
b8a4f404
PZ		 1574static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1575 enum pipe pipe)
040484af 1576{
23670b32 1577 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1579 uint32_t reg, val, pipeconf_val;
040484af
JB		 1580
1581 /* PCH only available on ILK+ */
1582 BUG_ON(dev_priv->info->gen < 5);
1583
1584 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1585 assert_pch_pll_enabled(dev_priv,
1586 to_intel_crtc(crtc)->pch_pll,
1587 to_intel_crtc(crtc));
040484af
JB		 1588
1589 /* FDI must be feeding us bits for PCH ports */
1590 assert_fdi_tx_enabled(dev_priv, pipe);
1591 assert_fdi_rx_enabled(dev_priv, pipe);
1592
23670b32
DV		 1593 if (HAS_PCH_CPT(dev)) {
1594 /* Workaround: Set the timing override bit before enabling the
1595 * pch transcoder. */
1596 reg = TRANS_CHICKEN2(pipe);
1597 val = I915_READ(reg);
1598 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599 I915_WRITE(reg, val);
59c859d6 1600 }
23670b32 1601
ab9412ba 1602 reg = PCH_TRANSCONF(pipe);
040484af 1603 val = I915_READ(reg);
5f7f726d 1604 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1605
1606 if (HAS_PCH_IBX(dev_priv->dev)) {
1607 /*
1608 * make the BPC in transcoder be consistent with
1609 * that in pipeconf reg.
1610 */
dfd07d72
DV		 1611 val &= ~PIPECONF_BPC_MASK;
1612 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1613 }
5f7f726d
PZ		 1614
1615 val &= ~TRANS_INTERLACE_MASK;
1616 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1617 if (HAS_PCH_IBX(dev_priv->dev) &&
1618 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619 val |= TRANS_LEGACY_INTERLACED_ILK;
1620 else
1621 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1622 else
1623 val |= TRANS_PROGRESSIVE;
1624
040484af
JB		 1625 I915_WRITE(reg, val | TRANS_ENABLE);
1626 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1627 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1628}
1629
8fb033d7 1630static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1631 enum transcoder cpu_transcoder)
040484af 1632{
8fb033d7 1633 u32 val, pipeconf_val;
8fb033d7
PZ		 1634
1635 /* PCH only available on ILK+ */
1636 BUG_ON(dev_priv->info->gen < 5);
1637
8fb033d7 1638 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1639 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1640 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1641
223a6fdf
PZ		 1642 /* Workaround: set timing override bit. */
1643 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1644 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1645 I915_WRITE(_TRANSA_CHICKEN2, val);
1646
25f3ef11 1647 val = TRANS_ENABLE;
937bb610 1648 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1649
9a76b1c6
PZ		 1650 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651 PIPECONF_INTERLACED_ILK)
a35f2679 1652 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1653 else
1654 val |= TRANS_PROGRESSIVE;
1655
ab9412ba
DV		 1656 I915_WRITE(LPT_TRANSCONF, val);
1657 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1658 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1659}
1660
b8a4f404
PZ		 1661static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
040484af 1663{
23670b32
DV		 1664 struct drm_device *dev = dev_priv->dev;
1665 uint32_t reg, val;
040484af
JB		 1666
1667 /* FDI relies on the transcoder */
1668 assert_fdi_tx_disabled(dev_priv, pipe);
1669 assert_fdi_rx_disabled(dev_priv, pipe);
1670
291906f1
JB		 1671 /* Ports must be off as well */
1672 assert_pch_ports_disabled(dev_priv, pipe);
1673
ab9412ba 1674 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1675 val = I915_READ(reg);
1676 val &= ~TRANS_ENABLE;
1677 I915_WRITE(reg, val);
1678 /* wait for PCH transcoder off, transcoder state */
1679 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1680 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1681
1682 if (!HAS_PCH_IBX(dev)) {
1683 /* Workaround: Clear the timing override chicken bit again. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
040484af
JB		 1689}
1690
ab4d966c 1691static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1692{
8fb033d7
PZ		 1693 u32 val;
1694
ab9412ba 1695 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1696 val &= ~TRANS_ENABLE;
ab9412ba 1697 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1698 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1699 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1700 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1701
1702 /* Workaround: clear timing override bit. */
1703 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1704 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1705 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1706}
1707
b24e7179 1708/**
309cfea8 1709 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe to enable
040484af 1712 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1713 *
1714 * Enable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe is actually running (i.e. first vblank) before
1720 * returning.
1721 */
040484af
JB		 1722static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1723 bool pch_port)
b24e7179 1724{
702e7a56
PZ		 1725 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1726 pipe);
1a240d4d 1727 enum pipe pch_transcoder;
b24e7179
JB		 1728 int reg;
1729 u32 val;
1730
58c6eaa2
DV		 1731 assert_planes_disabled(dev_priv, pipe);
1732 assert_sprites_disabled(dev_priv, pipe);
1733
681e5811 1734 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1735 pch_transcoder = TRANSCODER_A;
1736 else
1737 pch_transcoder = pipe;
1738
b24e7179
JB		 1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
cc391bbb 1749 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1750 assert_fdi_tx_pll_enabled(dev_priv,
1751 (enum pipe) cpu_transcoder);
040484af
JB		 1752 }
1753 /* FIXME: assert CPU port conditions for SNB+ */
1754 }
b24e7179 1755
702e7a56 1756 reg = PIPECONF(cpu_transcoder);
b24e7179 1757 val = I915_READ(reg);
00d70b15
CW		 1758 if (val & PIPECONF_ENABLE)
1759 return;
1760
1761 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1762 intel_wait_for_vblank(dev_priv->dev, pipe);
1763}
1764
1765/**
309cfea8 1766 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe to disable
1769 *
1770 * Disable @pipe, making sure that various hardware specific requirements
1771 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 *
1773 * @pipe should be %PIPE_A or %PIPE_B.
1774 *
1775 * Will wait until the pipe has shut down before returning.
1776 */
1777static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1778 enum pipe pipe)
1779{
702e7a56
PZ		 1780 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1781 pipe);
b24e7179
JB		 1782 int reg;
1783 u32 val;
1784
1785 /*
1786 * Make sure planes won't keep trying to pump pixels to us,
1787 * or we might hang the display.
1788 */
1789 assert_planes_disabled(dev_priv, pipe);
19332d7a 1790 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1791
1792 /* Don't disable pipe A or pipe A PLLs if needed */
1793 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794 return;
1795
702e7a56 1796 reg = PIPECONF(cpu_transcoder);
b24e7179 1797 val = I915_READ(reg);
00d70b15
CW		 1798 if ((val & PIPECONF_ENABLE) == 0)
1799 return;
1800
1801 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1802 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1803}
1804
d74362c9
KP		 1805/*
1806 * Plane regs are double buffered, going from enabled->disabled needs a
1807 * trigger in order to latch. The display address reg provides this.
1808 */
6f1d69b0 1809void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1810 enum plane plane)
1811{
14f86147
DL		 1812 if (dev_priv->info->gen >= 4)
1813 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1814 else
1815 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1816}
1817
b24e7179
JB		 1818/**
1819 * intel_enable_plane - enable a display plane on a given pipe
1820 * @dev_priv: i915 private structure
1821 * @plane: plane to enable
1822 * @pipe: pipe being fed
1823 *
1824 * Enable @plane on @pipe, making sure that @pipe is running first.
1825 */
1826static void intel_enable_plane(struct drm_i915_private *dev_priv,
1827 enum plane plane, enum pipe pipe)
1828{
1829 int reg;
1830 u32 val;
1831
1832 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1833 assert_pipe_enabled(dev_priv, pipe);
1834
1835 reg = DSPCNTR(plane);
1836 val = I915_READ(reg);
00d70b15
CW		 1837 if (val & DISPLAY_PLANE_ENABLE)
1838 return;
1839
1840 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1841 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1842 intel_wait_for_vblank(dev_priv->dev, pipe);
1843}
1844
b24e7179
JB		 1845/**
1846 * intel_disable_plane - disable a display plane
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to disable
1849 * @pipe: pipe consuming the data
1850 *
1851 * Disable @plane; should be an independent operation.
1852 */
1853static void intel_disable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 reg = DSPCNTR(plane);
1860 val = I915_READ(reg);
00d70b15
CW		 1861 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1862 return;
1863
1864 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1865 intel_flush_display_plane(dev_priv, plane);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
693db184
CW		 1869static bool need_vtd_wa(struct drm_device *dev)
1870{
1871#ifdef CONFIG_INTEL_IOMMU
1872 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1873 return true;
1874#endif
1875 return false;
1876}
1877
127bd2ac 1878int
48b956c5 1879intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1880 struct drm_i915_gem_object *obj,
919926ae 1881 struct intel_ring_buffer *pipelined)
6b95a207 1882{
ce453d81 1883 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1884 u32 alignment;
1885 int ret;
1886
05394f39 1887 switch (obj->tiling_mode) {
6b95a207 1888 case I915_TILING_NONE:
534843da
CW		 1889 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1890 alignment = 128 * 1024;
a6c45cf0 1891 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1892 alignment = 4 * 1024;
1893 else
1894 alignment = 64 * 1024;
6b95a207
KH		 1895 break;
1896 case I915_TILING_X:
1897 /* pin() will align the object as required by fence */
1898 alignment = 0;
1899 break;
1900 case I915_TILING_Y:
8bb6e959
DV		 1901 /* Despite that we check this in framebuffer_init userspace can
1902 * screw us over and change the tiling after the fact. Only
1903 * pinned buffers can't change their tiling. */
1904 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1905 return -EINVAL;
1906 default:
1907 BUG();
1908 }
1909
693db184
CW		 1910 /* Note that the w/a also requires 64 PTE of padding following the
1911 * bo. We currently fill all unused PTE with the shadow page and so
1912 * we should always have valid PTE following the scanout preventing
1913 * the VT-d warning.
1914 */
1915 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1916 alignment = 256 * 1024;
1917
ce453d81 1918 dev_priv->mm.interruptible = false;
2da3b9b9 1919 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1920 if (ret)
ce453d81 1921 goto err_interruptible;
6b95a207
KH		 1922
1923 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1924 * fence, whereas 965+ only requires a fence if using
1925 * framebuffer compression. For simplicity, we always install
1926 * a fence as the cost is not that onerous.
1927 */
06d98131 1928 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1929 if (ret)
1930 goto err_unpin;
1690e1eb 1931
9a5a53b3 1932 i915_gem_object_pin_fence(obj);
6b95a207 1933
ce453d81 1934 dev_priv->mm.interruptible = true;
6b95a207 1935 return 0;
48b956c5
CW		 1936
1937err_unpin:
1938 i915_gem_object_unpin(obj);
ce453d81
CW		 1939err_interruptible:
1940 dev_priv->mm.interruptible = true;
48b956c5 1941 return ret;
6b95a207
KH		 1942}
1943
1690e1eb
CW		 1944void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1945{
1946 i915_gem_object_unpin_fence(obj);
1947 i915_gem_object_unpin(obj);
1948}
1949
c2c75131
DV		 1950/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1951 * is assumed to be a power-of-two. */
bc752862
CW		 1952unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1953 unsigned int tiling_mode,
1954 unsigned int cpp,
1955 unsigned int pitch)
c2c75131 1956{
bc752862
CW		 1957 if (tiling_mode != I915_TILING_NONE) {
1958 unsigned int tile_rows, tiles;
c2c75131 1959
bc752862
CW		 1960 tile_rows = *y / 8;
1961 *y %= 8;
c2c75131 1962
bc752862
CW		 1963 tiles = *x / (512/cpp);
1964 *x %= 512/cpp;
1965
1966 return tile_rows * pitch * 8 + tiles * 4096;
1967 } else {
1968 unsigned int offset;
1969
1970 offset = *y * pitch + *x * cpp;
1971 *y = 0;
1972 *x = (offset & 4095) / cpp;
1973 return offset & -4096;
1974 }
c2c75131
DV		 1975}
1976
17638cd6
JB		 1977static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978 int x, int y)
81255565
JB		 1979{
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
05394f39 1984 struct drm_i915_gem_object *obj;
81255565 1985 int plane = intel_crtc->plane;
e506a0c6 1986 unsigned long linear_offset;
81255565 1987 u32 dspcntr;
5eddb70b 1988 u32 reg;
81255565
JB		 1989
1990 switch (plane) {
1991 case 0:
1992 case 1:
1993 break;
1994 default:
84f44ce7 1995 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1996 return -EINVAL;
1997 }
1998
1999 intel_fb = to_intel_framebuffer(fb);
2000 obj = intel_fb->obj;
81255565 2001
5eddb70b
CW		 2002 reg = DSPCNTR(plane);
2003 dspcntr = I915_READ(reg);
81255565
JB		 2004 /* Mask out pixel format bits in case we change it */
2005 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2006 switch (fb->pixel_format) {
2007 case DRM_FORMAT_C8:
81255565
JB		 2008 dspcntr |= DISPPLANE_8BPP;
2009 break;
57779d06
VS		 2010 case DRM_FORMAT_XRGB1555:
2011 case DRM_FORMAT_ARGB1555:
2012 dspcntr |= DISPPLANE_BGRX555;
81255565 2013 break;
57779d06
VS		 2014 case DRM_FORMAT_RGB565:
2015 dspcntr |= DISPPLANE_BGRX565;
2016 break;
2017 case DRM_FORMAT_XRGB8888:
2018 case DRM_FORMAT_ARGB8888:
2019 dspcntr |= DISPPLANE_BGRX888;
2020 break;
2021 case DRM_FORMAT_XBGR8888:
2022 case DRM_FORMAT_ABGR8888:
2023 dspcntr |= DISPPLANE_RGBX888;
2024 break;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 dspcntr |= DISPPLANE_BGRX101010;
2028 break;
2029 case DRM_FORMAT_XBGR2101010:
2030 case DRM_FORMAT_ABGR2101010:
2031 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2032 break;
2033 default:
baba133a 2034 BUG();
81255565 2035 }
57779d06 2036
a6c45cf0 2037 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2038 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2039 dspcntr |= DISPPLANE_TILED;
2040 else
2041 dspcntr &= ~DISPPLANE_TILED;
2042 }
2043
5eddb70b 2044 I915_WRITE(reg, dspcntr);
81255565 2045
e506a0c6 2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2047
c2c75131
DV		 2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
bc752862
CW		 2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
c2c75131
DV		 2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
e506a0c6 2055 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2056 }
e506a0c6
DV		 2057
2058 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2059 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2060 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2061 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2062 I915_MODIFY_DISPBASE(DSPSURF(plane),
2063 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2064 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2065 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2066 } else
e506a0c6 2067 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2068 POSTING_READ(reg);
81255565 2069
17638cd6
JB		 2070 return 0;
2071}
2072
2073static int ironlake_update_plane(struct drm_crtc *crtc,
2074 struct drm_framebuffer *fb, int x, int y)
2075{
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 struct intel_framebuffer *intel_fb;
2080 struct drm_i915_gem_object *obj;
2081 int plane = intel_crtc->plane;
e506a0c6 2082 unsigned long linear_offset;
17638cd6
JB		 2083 u32 dspcntr;
2084 u32 reg;
2085
2086 switch (plane) {
2087 case 0:
2088 case 1:
27f8227b 2089 case 2:
17638cd6
JB		 2090 break;
2091 default:
84f44ce7 2092 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2093 return -EINVAL;
2094 }
2095
2096 intel_fb = to_intel_framebuffer(fb);
2097 obj = intel_fb->obj;
2098
2099 reg = DSPCNTR(plane);
2100 dspcntr = I915_READ(reg);
2101 /* Mask out pixel format bits in case we change it */
2102 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2103 switch (fb->pixel_format) {
2104 case DRM_FORMAT_C8:
17638cd6
JB		 2105 dspcntr |= DISPPLANE_8BPP;
2106 break;
57779d06
VS		 2107 case DRM_FORMAT_RGB565:
2108 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2109 break;
57779d06
VS		 2110 case DRM_FORMAT_XRGB8888:
2111 case DRM_FORMAT_ARGB8888:
2112 dspcntr |= DISPPLANE_BGRX888;
2113 break;
2114 case DRM_FORMAT_XBGR8888:
2115 case DRM_FORMAT_ABGR8888:
2116 dspcntr |= DISPPLANE_RGBX888;
2117 break;
2118 case DRM_FORMAT_XRGB2101010:
2119 case DRM_FORMAT_ARGB2101010:
2120 dspcntr |= DISPPLANE_BGRX101010;
2121 break;
2122 case DRM_FORMAT_XBGR2101010:
2123 case DRM_FORMAT_ABGR2101010:
2124 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2125 break;
2126 default:
baba133a 2127 BUG();
17638cd6
JB		 2128 }
2129
2130 if (obj->tiling_mode != I915_TILING_NONE)
2131 dspcntr |= DISPPLANE_TILED;
2132 else
2133 dspcntr &= ~DISPPLANE_TILED;
2134
2135 /* must disable */
2136 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2137
2138 I915_WRITE(reg, dspcntr);
2139
e506a0c6 2140 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2141 intel_crtc->dspaddr_offset =
bc752862
CW		 2142 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2143 fb->bits_per_pixel / 8,
2144 fb->pitches[0]);
c2c75131 2145 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2146
e506a0c6
DV		 2147 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2149 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2150 I915_MODIFY_DISPBASE(DSPSURF(plane),
2151 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2152 if (IS_HASWELL(dev)) {
2153 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2154 } else {
2155 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2156 I915_WRITE(DSPLINOFF(plane), linear_offset);
2157 }
17638cd6
JB		 2158 POSTING_READ(reg);
2159
2160 return 0;
2161}
2162
2163/* Assume fb object is pinned & idle & fenced and just update base pointers */
2164static int
2165intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2166 int x, int y, enum mode_set_atomic state)
2167{
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2170
6b8e6ed0
CW		 2171 if (dev_priv->display.disable_fbc)
2172 dev_priv->display.disable_fbc(dev);
3dec0095 2173 intel_increase_pllclock(crtc);
81255565 2174
6b8e6ed0 2175 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2176}
2177
96a02917
VS		 2178void intel_display_handle_reset(struct drm_device *dev)
2179{
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct drm_crtc *crtc;
2182
2183 /*
2184 * Flips in the rings have been nuked by the reset,
2185 * so complete all pending flips so that user space
2186 * will get its events and not get stuck.
2187 *
2188 * Also update the base address of all primary
2189 * planes to the the last fb to make sure we're
2190 * showing the correct fb after a reset.
2191 *
2192 * Need to make two loops over the crtcs so that we
2193 * don't try to grab a crtc mutex before the
2194 * pending_flip_queue really got woken up.
2195 */
2196
2197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 enum plane plane = intel_crtc->plane;
2200
2201 intel_prepare_page_flip(dev, plane);
2202 intel_finish_page_flip_plane(dev, plane);
2203 }
2204
2205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207
2208 mutex_lock(&crtc->mutex);
2209 if (intel_crtc->active)
2210 dev_priv->display.update_plane(crtc, crtc->fb,
2211 crtc->x, crtc->y);
2212 mutex_unlock(&crtc->mutex);
2213 }
2214}
2215
14667a4b
CW		 2216static int
2217intel_finish_fb(struct drm_framebuffer *old_fb)
2218{
2219 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2221 bool was_interruptible = dev_priv->mm.interruptible;
2222 int ret;
2223
14667a4b
CW		 2224 /* Big Hammer, we also need to ensure that any pending
2225 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2226 * current scanout is retired before unpinning the old
2227 * framebuffer.
2228 *
2229 * This should only fail upon a hung GPU, in which case we
2230 * can safely continue.
2231 */
2232 dev_priv->mm.interruptible = false;
2233 ret = i915_gem_object_finish_gpu(obj);
2234 dev_priv->mm.interruptible = was_interruptible;
2235
2236 return ret;
2237}
2238
198598d0
VS		 2239static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2240{
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_master_private *master_priv;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244
2245 if (!dev->primary->master)
2246 return;
2247
2248 master_priv = dev->primary->master->driver_priv;
2249 if (!master_priv->sarea_priv)
2250 return;
2251
2252 switch (intel_crtc->pipe) {
2253 case 0:
2254 master_priv->sarea_priv->pipeA_x = x;
2255 master_priv->sarea_priv->pipeA_y = y;
2256 break;
2257 case 1:
2258 master_priv->sarea_priv->pipeB_x = x;
2259 master_priv->sarea_priv->pipeB_y = y;
2260 break;
2261 default:
2262 break;
2263 }
2264}
2265
5c3b82e2 2266static int
3c4fdcfb 2267intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2268 struct drm_framebuffer *fb)
79e53945
JB		 2269{
2270 struct drm_device *dev = crtc->dev;
6b8e6ed0 2271 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2273 struct drm_framebuffer *old_fb;
5c3b82e2 2274 int ret;
79e53945
JB		 2275
2276 /* no fb bound */
94352cf9 2277 if (!fb) {
a5071c2f 2278 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2279 return 0;
2280 }
2281
7eb552ae 2282 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2283 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2284 plane_name(intel_crtc->plane),
2285 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2286 return -EINVAL;
79e53945
JB		 2287 }
2288
5c3b82e2 2289 mutex_lock(&dev->struct_mutex);
265db958 2290 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2291 to_intel_framebuffer(fb)->obj,
919926ae 2292 NULL);
5c3b82e2
CW		 2293 if (ret != 0) {
2294 mutex_unlock(&dev->struct_mutex);
a5071c2f 2295 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2296 return ret;
2297 }
79e53945 2298
94352cf9 2299 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2300 if (ret) {
94352cf9 2301 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2302 mutex_unlock(&dev->struct_mutex);
a5071c2f 2303 DRM_ERROR("failed to update base address\n");
4e6cfefc 2304 return ret;
79e53945 2305 }
3c4fdcfb 2306
94352cf9
DV		 2307 old_fb = crtc->fb;
2308 crtc->fb = fb;
6c4c86f5
DV		 2309 crtc->x = x;
2310 crtc->y = y;
94352cf9 2311
b7f1de28
CW		 2312 if (old_fb) {
2313 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2314 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2315 }
652c393a 2316
6b8e6ed0 2317 intel_update_fbc(dev);
5c3b82e2 2318 mutex_unlock(&dev->struct_mutex);
79e53945 2319
198598d0 2320 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2321
2322 return 0;
79e53945
JB		 2323}
2324
5e84e1a4
ZW		 2325static void intel_fdi_normal_train(struct drm_crtc *crtc)
2326{
2327 struct drm_device *dev = crtc->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2330 int pipe = intel_crtc->pipe;
2331 u32 reg, temp;
2332
2333 /* enable normal train */
2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
61e499bf 2336 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2337 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2338 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2342 }
5e84e1a4
ZW		 2343 I915_WRITE(reg, temp);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 if (HAS_PCH_CPT(dev)) {
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2350 } else {
2351 temp &= ~FDI_LINK_TRAIN_NONE;
2352 temp |= FDI_LINK_TRAIN_NONE;
2353 }
2354 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2355
2356 /* wait one idle pattern time */
2357 POSTING_READ(reg);
2358 udelay(1000);
357555c0
JB		 2359
2360 /* IVB wants error correction enabled */
2361 if (IS_IVYBRIDGE(dev))
2362 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2363 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2364}
2365
1e833f40
DV		 2366static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2367{
2368 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2369}
2370
01a415fd
DV		 2371static void ivb_modeset_global_resources(struct drm_device *dev)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *pipe_B_crtc =
2375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376 struct intel_crtc *pipe_C_crtc =
2377 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2378 uint32_t temp;
2379
1e833f40
DV		 2380 /*
2381 * When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. Note that we don't care about enabled pipes without
2383 * an enabled pch encoder.
2384 */
2385 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2386 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395}
2396
8db9d77b
ZW		 2397/* The FDI link training functions for ILK/Ibexpeak. */
2398static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
0fc932b8 2404 int plane = intel_crtc->plane;
5eddb70b 2405 u32 reg, temp, tries;
8db9d77b 2406
0fc932b8
JB		 2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
e1a44743
AJ		 2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
5eddb70b
CW		 2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
e1a44743
AJ		 2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
e1a44743
AJ		 2419 udelay(150);
2420
8db9d77b 2421 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
627eb5a3
DV		 2424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
8db9d77b
ZW		 2437 udelay(150);
2438
5b2adf89 2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2443
5eddb70b 2444 reg = FDI_RX_IIR(pipe);
e1a44743 2445 for (tries = 0; tries < 5; tries++) {
5eddb70b 2446 temp = I915_READ(reg);
8db9d77b
ZW		 2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2452 break;
2453 }
8db9d77b 2454 }
e1a44743 2455 if (tries == 5)
5eddb70b 2456 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2457
2458 /* Train 2 */
5eddb70b
CW		 2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
8db9d77b
ZW		 2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2463 I915_WRITE(reg, temp);
8db9d77b 2464
5eddb70b
CW		 2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 POSTING_READ(reg);
2472 udelay(150);
8db9d77b 2473
5eddb70b 2474 reg = FDI_RX_IIR(pipe);
e1a44743 2475 for (tries = 0; tries < 5; tries++) {
5eddb70b 2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
8db9d77b 2484 }
e1a44743 2485 if (tries == 5)
5eddb70b 2486 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2487
2488 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2489
8db9d77b
ZW		 2490}
2491
0206e353 2492static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497};
2498
2499/* The FDI link training functions for SNB/Cougarpoint. */
2500static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501{
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
fa37d39e 2506 u32 reg, temp, i, retry;
8db9d77b 2507
e1a44743
AJ		 2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
5eddb70b
CW		 2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
e1a44743
AJ		 2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
e1a44743
AJ		 2517 udelay(150);
2518
8db9d77b 2519 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
627eb5a3
DV		 2522 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2523 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2530
d74cf324
DV		 2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
5eddb70b
CW		 2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
5eddb70b
CW		 2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
8db9d77b
ZW		 2546 udelay(150);
2547
0206e353 2548 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
8db9d77b
ZW		 2556 udelay(500);
2557
fa37d39e
SP		 2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
8db9d77b 2568 }
fa37d39e
SP		 2569 if (retry < 5)
2570 break;
8db9d77b
ZW		 2571 }
2572 if (i == 4)
5eddb70b 2573 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2574
2575 /* Train 2 */
5eddb70b
CW		 2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
5eddb70b 2585 I915_WRITE(reg, temp);
8db9d77b 2586
5eddb70b
CW		 2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
5eddb70b
CW		 2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
8db9d77b
ZW		 2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
8db9d77b
ZW		 2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
8db9d77b
ZW		 2609 udelay(500);
2610
fa37d39e
SP		 2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
8db9d77b 2621 }
fa37d39e
SP		 2622 if (retry < 5)
2623 break;
8db9d77b
ZW		 2624 }
2625 if (i == 4)
5eddb70b 2626 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629}
2630
357555c0
JB		 2631/* Manual link training for Ivy Bridge A0 parts */
2632static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
01a415fd
DV		 2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
357555c0
JB		 2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
627eb5a3
DV		 2657 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2663 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
d74cf324
DV		 2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
357555c0
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2674 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
0206e353 2680 for (i = 0; i < 4; i++) {
357555c0
JB		 2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
0206e353 2722 for (i = 0; i < 4; i++) {
357555c0
JB		 2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746}
2747
88cefb6c 2748static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2749{
88cefb6c 2750 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2751 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2752 int pipe = intel_crtc->pipe;
5eddb70b 2753 u32 reg, temp;
79e53945 2754
c64e311e 2755
c98e9dcf 2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
627eb5a3
DV		 2759 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2760 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
c98e9dcf
JB		 2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
c98e9dcf
JB		 2772 udelay(200);
2773
20749730
PZ		 2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2779
20749730
PZ		 2780 POSTING_READ(reg);
2781 udelay(100);
6be4a607 2782 }
0e23b99d
JB		 2783}
2784
88cefb6c
DV		 2785static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786{
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812}
2813
0fc932b8
JB		 2814static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
dfd07d72 2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2840 }
0fc932b8
JB		 2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
dfd07d72 2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865}
2866
5bb61643
CW		 2867static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2872 unsigned long flags;
2873 bool pending;
2874
10d83730
VS		 2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2877 return false;
2878
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883 return pending;
2884}
2885
e6c3a2a6
CW		 2886static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887{
0f91128d 2888 struct drm_device *dev = crtc->dev;
5bb61643 2889 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2890
2891 if (crtc->fb == NULL)
2892 return;
2893
2c10d571
DV		 2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
5bb61643
CW		 2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2898
0f91128d
CW		 2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2902}
2903
e615efe4
ED		 2904/* Program iCLKIP clock to the desired frequency */
2905static void lpt_program_iclkip(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
09153000
DV		 2912 mutex_lock(&dev_priv->dpio_lock);
2913
e615efe4
ED		 2914 /* It is necessary to ungate the pixclk gate prior to programming
2915 * the divisors, and gate it back when it is done.
2916 */
2917 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2918
2919 /* Disable SSCCTL */
2920 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2921 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2922 SBI_SSCCTL_DISABLE,
2923 SBI_ICLK);
e615efe4
ED		 2924
2925 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2926 if (crtc->mode.clock == 20000) {
2927 auxdiv = 1;
2928 divsel = 0x41;
2929 phaseinc = 0x20;
2930 } else {
2931 /* The iCLK virtual clock root frequency is in MHz,
2932 * but the crtc->mode.clock in in KHz. To get the divisors,
2933 * it is necessary to divide one by another, so we
2934 * convert the virtual clock precision to KHz here for higher
2935 * precision.
2936 */
2937 u32 iclk_virtual_root_freq = 172800 * 1000;
2938 u32 iclk_pi_range = 64;
2939 u32 desired_divisor, msb_divisor_value, pi_value;
2940
2941 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2942 msb_divisor_value = desired_divisor / iclk_pi_range;
2943 pi_value = desired_divisor % iclk_pi_range;
2944
2945 auxdiv = 0;
2946 divsel = msb_divisor_value - 2;
2947 phaseinc = pi_value;
2948 }
2949
2950 /* This should not happen with any sane values */
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2952 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2953 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2954 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2955
2956 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2957 crtc->mode.clock,
2958 auxdiv,
2959 divsel,
2960 phasedir,
2961 phaseinc);
2962
2963 /* Program SSCDIVINTPHASE6 */
988d6ee8 2964 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2965 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2967 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2968 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2969 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2970 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2971 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2972
2973 /* Program SSCAUXDIV */
988d6ee8 2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2977 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2978
2979 /* Enable modulator and associated divider */
988d6ee8 2980 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2981 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2982 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2983
2984 /* Wait for initialization time */
2985 udelay(24);
2986
2987 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2988
2989 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2990}
2991
275f01b2
DV		 2992static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2993 enum pipe pch_transcoder)
2994{
2995 struct drm_device *dev = crtc->base.dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2998
2999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3000 I915_READ(HTOTAL(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3002 I915_READ(HBLANK(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3004 I915_READ(HSYNC(cpu_transcoder)));
3005
3006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3007 I915_READ(VTOTAL(cpu_transcoder)));
3008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3009 I915_READ(VBLANK(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3011 I915_READ(VSYNC(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3014}
3015
f67a559d
JB		 3016/*
3017 * Enable PCH resources required for PCH ports:
3018 * - PCH PLLs
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3022 * - transcoder
3023 */
3024static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
ee7b9f93 3030 u32 reg, temp;
2c07245f 3031
ab9412ba 3032 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3033
cd986abb
DV		 3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
c98e9dcf 3039 /* For PCH output, training FDI link */
674cf967 3040 dev_priv->display.fdi_link_train(crtc);
2c07245f 3041
572deb37
DV		 3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3045 *
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
b6b4e185 3049 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3050
303b81e0 3051 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3052 u32 sel;
4b645f14 3053
c98e9dcf 3054 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3055 switch (pipe) {
3056 default:
3057 case 0:
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3060 break;
3061 case 1:
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3064 break;
3065 case 2:
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3068 break;
d64311ab 3069 }
ee7b9f93
JB		 3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071 temp |= sel;
3072 else
3073 temp &= ~sel;
c98e9dcf 3074 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3075 }
5eddb70b 3076
d9b6cb56
JB		 3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3079 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3080
303b81e0 3081 intel_fdi_normal_train(crtc);
5e84e1a4 3082
c98e9dcf
JB		 3083 /* For PCH DP, enable TRANS_DP_CTL */
3084 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3085 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3086 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3087 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3088 reg = TRANS_DP_CTL(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3091 TRANS_DP_SYNC_MASK |
3092 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3093 temp |= (TRANS_DP_OUTPUT_ENABLE |
3094 TRANS_DP_ENH_FRAMING);
9325c9f0 3095 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3096
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3098 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3099 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3100 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3101
3102 switch (intel_trans_dp_port_sel(crtc)) {
3103 case PCH_DP_B:
5eddb70b 3104 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3105 break;
3106 case PCH_DP_C:
5eddb70b 3107 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3108 break;
3109 case PCH_DP_D:
5eddb70b 3110 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3111 break;
3112 default:
e95d41e1 3113 BUG();
32f9d658 3114 }
2c07245f 3115
5eddb70b 3116 I915_WRITE(reg, temp);
6be4a607 3117 }
b52eb4dc 3118
b8a4f404 3119 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3120}
3121
1507e5bd
PZ		 3122static void lpt_pch_enable(struct drm_crtc *crtc)
3123{
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3128
ab9412ba 3129 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3130
8c52b5e8 3131 lpt_program_iclkip(crtc);
1507e5bd 3132
0540e488 3133 /* Set transcoder timing. */
275f01b2 3134 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3135
937bb610 3136 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3137}
3138
ee7b9f93
JB		 3139static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3140{
3141 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3142
3143 if (pll == NULL)
3144 return;
3145
3146 if (pll->refcount == 0) {
3147 WARN(1, "bad PCH PLL refcount\n");
3148 return;
3149 }
3150
3151 --pll->refcount;
3152 intel_crtc->pch_pll = NULL;
3153}
3154
3155static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3156{
3157 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3158 struct intel_pch_pll *pll;
3159 int i;
3160
3161 pll = intel_crtc->pch_pll;
3162 if (pll) {
3163 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto prepare;
3166 }
3167
98b6bd99
DV		 3168 if (HAS_PCH_IBX(dev_priv->dev)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170 i = intel_crtc->pipe;
3171 pll = &dev_priv->pch_plls[i];
3172
3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3174 intel_crtc->base.base.id, pll->pll_reg);
3175
3176 goto found;
3177 }
3178
ee7b9f93
JB		 3179 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3180 pll = &dev_priv->pch_plls[i];
3181
3182 /* Only want to check enabled timings first */
3183 if (pll->refcount == 0)
3184 continue;
3185
3186 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3187 fp == I915_READ(pll->fp0_reg)) {
3188 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3189 intel_crtc->base.base.id,
3190 pll->pll_reg, pll->refcount, pll->active);
3191
3192 goto found;
3193 }
3194 }
3195
3196 /* Ok no matching timings, maybe there's a free one? */
3197 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3198 pll = &dev_priv->pch_plls[i];
3199 if (pll->refcount == 0) {
3200 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3201 intel_crtc->base.base.id, pll->pll_reg);
3202 goto found;
3203 }
3204 }
3205
3206 return NULL;
3207
3208found:
3209 intel_crtc->pch_pll = pll;
3210 pll->refcount++;
84f44ce7 3211 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3212prepare: /* separate function? */
3213 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3214
e04c7350
CW		 3215 /* Wait for the clocks to stabilize before rewriting the regs */
3216 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3217 POSTING_READ(pll->pll_reg);
3218 udelay(150);
e04c7350
CW		 3219
3220 I915_WRITE(pll->fp0_reg, fp);
3221 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3222 pll->on = false;
3223 return pll;
3224}
3225
a1520318 3226static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3227{
3228 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3229 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3230 u32 temp;
3231
3232 temp = I915_READ(dslreg);
3233 udelay(500);
3234 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3235 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3236 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3237 }
3238}
3239
b074cec8
JB		 3240static void ironlake_pfit_enable(struct intel_crtc *crtc)
3241{
3242 struct drm_device *dev = crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 int pipe = crtc->pipe;
3245
0ef37f3f 3246 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3247 /* Force use of hard-coded filter coefficients
3248 * as some pre-programmed values are broken,
3249 * e.g. x201.
3250 */
3251 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3253 PF_PIPE_SEL_IVB(pipe));
3254 else
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3256 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3257 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3258 }
3259}
3260
f67a559d
JB		 3261static void ironlake_crtc_enable(struct drm_crtc *crtc)
3262{
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3266 struct intel_encoder *encoder;
f67a559d
JB		 3267 int pipe = intel_crtc->pipe;
3268 int plane = intel_crtc->plane;
3269 u32 temp;
f67a559d 3270
08a48469
DV		 3271 WARN_ON(!crtc->enabled);
3272
f67a559d
JB		 3273 if (intel_crtc->active)
3274 return;
3275
3276 intel_crtc->active = true;
8664281b
PZ		 3277
3278 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3279 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3280
f67a559d
JB		 3281 intel_update_watermarks(dev);
3282
3283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3284 temp = I915_READ(PCH_LVDS);
3285 if ((temp & LVDS_PORT_EN) == 0)
3286 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3287 }
3288
f67a559d 3289
5bfe2ac0 3290 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3291 /* Note: FDI PLL enabling _must_ be done before we enable the
3292 * cpu pipes, hence this is separate from all the other fdi/pch
3293 * enabling. */
88cefb6c 3294 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3295 } else {
3296 assert_fdi_tx_disabled(dev_priv, pipe);
3297 assert_fdi_rx_disabled(dev_priv, pipe);
3298 }
f67a559d 3299
bf49ec8c
DV		 3300 for_each_encoder_on_crtc(dev, crtc, encoder)
3301 if (encoder->pre_enable)
3302 encoder->pre_enable(encoder);
f67a559d
JB		 3303
3304 /* Enable panel fitting for LVDS */
b074cec8 3305 ironlake_pfit_enable(intel_crtc);
f67a559d 3306
9c54c0dd
JB		 3307 /*
3308 * On ILK+ LUT must be loaded before the pipe is running but with
3309 * clocks enabled
3310 */
3311 intel_crtc_load_lut(crtc);
3312
5bfe2ac0
DV		 3313 intel_enable_pipe(dev_priv, pipe,
3314 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3315 intel_enable_plane(dev_priv, plane, pipe);
3316
5bfe2ac0 3317 if (intel_crtc->config.has_pch_encoder)
f67a559d 3318 ironlake_pch_enable(crtc);
c98e9dcf 3319
d1ebd816 3320 mutex_lock(&dev->struct_mutex);
bed4a673 3321 intel_update_fbc(dev);
d1ebd816
BW		 3322 mutex_unlock(&dev->struct_mutex);
3323
6b383a7f 3324 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3325
fa5c73b1
DV		 3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 encoder->enable(encoder);
61b77ddd
DV		 3328
3329 if (HAS_PCH_CPT(dev))
a1520318 3330 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3331
3332 /*
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3338 * happening.
3339 */
3340 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3341}
3342
4f771f10
PZ		 3343static void haswell_crtc_enable(struct drm_crtc *crtc)
3344{
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 struct intel_encoder *encoder;
3349 int pipe = intel_crtc->pipe;
3350 int plane = intel_crtc->plane;
4f771f10
PZ		 3351
3352 WARN_ON(!crtc->enabled);
3353
3354 if (intel_crtc->active)
3355 return;
3356
3357 intel_crtc->active = true;
8664281b
PZ		 3358
3359 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3360 if (intel_crtc->config.has_pch_encoder)
3361 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3362
4f771f10
PZ		 3363 intel_update_watermarks(dev);
3364
5bfe2ac0 3365 if (intel_crtc->config.has_pch_encoder)
04945641 3366 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3367
3368 for_each_encoder_on_crtc(dev, crtc, encoder)
3369 if (encoder->pre_enable)
3370 encoder->pre_enable(encoder);
3371
1f544388 3372 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3373
1f544388 3374 /* Enable panel fitting for eDP */
b074cec8 3375 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3376
3377 /*
3378 * On ILK+ LUT must be loaded before the pipe is running but with
3379 * clocks enabled
3380 */
3381 intel_crtc_load_lut(crtc);
3382
1f544388 3383 intel_ddi_set_pipe_settings(crtc);
8228c251 3384 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3385
5bfe2ac0
DV		 3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3388 intel_enable_plane(dev_priv, plane, pipe);
3389
5bfe2ac0 3390 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3391 lpt_pch_enable(crtc);
4f771f10
PZ		 3392
3393 mutex_lock(&dev->struct_mutex);
3394 intel_update_fbc(dev);
3395 mutex_unlock(&dev->struct_mutex);
3396
3397 intel_crtc_update_cursor(crtc, true);
3398
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
3401
4f771f10
PZ		 3402 /*
3403 * There seems to be a race in PCH platform hw (at least on some
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3406 * as the first vblank happend, everything works as expected. Hence just
3407 * wait for one vblank before returning to avoid strange things
3408 * happening.
3409 */
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3411}
3412
6be4a607
JB		 3413static void ironlake_crtc_disable(struct drm_crtc *crtc)
3414{
3415 struct drm_device *dev = crtc->dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3418 struct intel_encoder *encoder;
6be4a607
JB		 3419 int pipe = intel_crtc->pipe;
3420 int plane = intel_crtc->plane;
5eddb70b 3421 u32 reg, temp;
b52eb4dc 3422
ef9c3aee 3423
f7abfe8b
CW		 3424 if (!intel_crtc->active)
3425 return;
3426
ea9d758d
DV		 3427 for_each_encoder_on_crtc(dev, crtc, encoder)
3428 encoder->disable(encoder);
3429
e6c3a2a6 3430 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3431 drm_vblank_off(dev, pipe);
6b383a7f 3432 intel_crtc_update_cursor(crtc, false);
5eddb70b 3433
b24e7179 3434 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3435
973d04f9
CW		 3436 if (dev_priv->cfb_plane == plane)
3437 intel_disable_fbc(dev);
2c07245f 3438
8664281b 3439 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3440 intel_disable_pipe(dev_priv, pipe);
32f9d658 3441
6be4a607 3442 /* Disable PF */
9db4a9c7
JB		 3443 I915_WRITE(PF_CTL(pipe), 0);
3444 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3445
bf49ec8c
DV		 3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 if (encoder->post_disable)
3448 encoder->post_disable(encoder);
2c07245f 3449
0fc932b8 3450 ironlake_fdi_disable(crtc);
249c0e64 3451
b8a4f404 3452 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3453 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3454
6be4a607
JB		 3455 if (HAS_PCH_CPT(dev)) {
3456 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3457 reg = TRANS_DP_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3460 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3461 I915_WRITE(reg, temp);
6be4a607
JB		 3462
3463 /* disable DPLL_SEL */
3464 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3465 switch (pipe) {
3466 case 0:
d64311ab 3467 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3468 break;
3469 case 1:
6be4a607 3470 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3471 break;
3472 case 2:
4b645f14 3473 /* C shares PLL A or B */
d64311ab 3474 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3475 break;
3476 default:
3477 BUG(); /* wtf */
3478 }
6be4a607 3479 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3480 }
e3421a18 3481
6be4a607 3482 /* disable PCH DPLL */
ee7b9f93 3483 intel_disable_pch_pll(intel_crtc);
8db9d77b 3484
88cefb6c 3485 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3486
f7abfe8b 3487 intel_crtc->active = false;
6b383a7f 3488 intel_update_watermarks(dev);
d1ebd816
BW		 3489
3490 mutex_lock(&dev->struct_mutex);
6b383a7f 3491 intel_update_fbc(dev);
d1ebd816 3492 mutex_unlock(&dev->struct_mutex);
6be4a607 3493}
1b3c7a47 3494
4f771f10 3495static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3496{
4f771f10
PZ		 3497 struct drm_device *dev = crtc->dev;
3498 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3500 struct intel_encoder *encoder;
3501 int pipe = intel_crtc->pipe;
3502 int plane = intel_crtc->plane;
3b117c8f 3503 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3504
4f771f10
PZ		 3505 if (!intel_crtc->active)
3506 return;
3507
3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 encoder->disable(encoder);
3510
3511 intel_crtc_wait_for_pending_flips(crtc);
3512 drm_vblank_off(dev, pipe);
3513 intel_crtc_update_cursor(crtc, false);
3514
891348b2 3515 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3516 if (dev_priv->cfb_plane == plane)
3517 intel_disable_fbc(dev);
3518
891348b2
RV		 3519 intel_disable_plane(dev_priv, plane, pipe);
3520
8664281b
PZ		 3521 if (intel_crtc->config.has_pch_encoder)
3522 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3523 intel_disable_pipe(dev_priv, pipe);
3524
ad80a810 3525 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3526
f7708f78
PZ		 3527 /* XXX: Once we have proper panel fitter state tracking implemented with
3528 * hardware state read/check support we should switch to only disable
3529 * the panel fitter when we know it's used. */
b97186f0
PZ		 3530 if (intel_display_power_enabled(dev,
3531 POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
f7708f78
PZ		 3532 I915_WRITE(PF_CTL(pipe), 0);
3533 I915_WRITE(PF_WIN_SZ(pipe), 0);
3534 }
4f771f10 3535
1f544388 3536 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3537
3538 for_each_encoder_on_crtc(dev, crtc, encoder)
3539 if (encoder->post_disable)
3540 encoder->post_disable(encoder);
3541
88adfff1 3542 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3543 lpt_disable_pch_transcoder(dev_priv);
8664281b 3544 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3545 intel_ddi_fdi_disable(crtc);
83616634 3546 }
4f771f10
PZ		 3547
3548 intel_crtc->active = false;
3549 intel_update_watermarks(dev);
3550
3551 mutex_lock(&dev->struct_mutex);
3552 intel_update_fbc(dev);
3553 mutex_unlock(&dev->struct_mutex);
3554}
3555
ee7b9f93
JB		 3556static void ironlake_crtc_off(struct drm_crtc *crtc)
3557{
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559 intel_put_pch_pll(intel_crtc);
3560}
3561
6441ab5f
PZ		 3562static void haswell_crtc_off(struct drm_crtc *crtc)
3563{
a5c961d1
PZ		 3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565
3566 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3567 * start using it. */
3b117c8f 3568 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3569
6441ab5f
PZ		 3570 intel_ddi_put_crtc_pll(crtc);
3571}
3572
02e792fb
DV		 3573static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3574{
02e792fb 3575 if (!enable && intel_crtc->overlay) {
23f09ce3 3576 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3577 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3578
23f09ce3 3579 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3580 dev_priv->mm.interruptible = false;
3581 (void) intel_overlay_switch_off(intel_crtc->overlay);
3582 dev_priv->mm.interruptible = true;
23f09ce3 3583 mutex_unlock(&dev->struct_mutex);
02e792fb 3584 }
02e792fb 3585
5dcdbcb0
CW		 3586 /* Let userspace switch the overlay on again. In most cases userspace
3587 * has to recompute where to put it anyway.
3588 */
02e792fb
DV		 3589}
3590
61bc95c1
EE		 3591/**
3592 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3593 * cursor plane briefly if not already running after enabling the display
3594 * plane.
3595 * This workaround avoids occasional blank screens when self refresh is
3596 * enabled.
3597 */
3598static void
3599g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3600{
3601 u32 cntl = I915_READ(CURCNTR(pipe));
3602
3603 if ((cntl & CURSOR_MODE) == 0) {
3604 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3605
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3607 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3608 intel_wait_for_vblank(dev_priv->dev, pipe);
3609 I915_WRITE(CURCNTR(pipe), cntl);
3610 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3611 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3612 }
3613}
3614
2dd24552
JB		 3615static void i9xx_pfit_enable(struct intel_crtc *crtc)
3616{
3617 struct drm_device *dev = crtc->base.dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 struct intel_crtc_config *pipe_config = &crtc->config;
3620
3621 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3622 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3623 return;
3624
3625 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3626 assert_pipe_disabled(dev_priv, crtc->pipe);
3627
3628 /*
3629 * Enable automatic panel scaling so that non-native modes
3630 * fill the screen. The panel fitter should only be
3631 * adjusted whilst the pipe is disabled, according to
3632 * register description and PRM.
3633 */
3634 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3635 pipe_config->gmch_pfit.control,
3636 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3637
b074cec8
JB		 3638 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3639 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3640
3641 /* Border color in case we don't scale up to the full screen. Black by
3642 * default, change to something else for debugging. */
3643 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3644}
3645
89b667f8
JB		 3646static void valleyview_crtc_enable(struct drm_crtc *crtc)
3647{
3648 struct drm_device *dev = crtc->dev;
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3651 struct intel_encoder *encoder;
3652 int pipe = intel_crtc->pipe;
3653 int plane = intel_crtc->plane;
3654
3655 WARN_ON(!crtc->enabled);
3656
3657 if (intel_crtc->active)
3658 return;
3659
3660 intel_crtc->active = true;
3661 intel_update_watermarks(dev);
3662
3663 mutex_lock(&dev_priv->dpio_lock);
3664
3665 for_each_encoder_on_crtc(dev, crtc, encoder)
3666 if (encoder->pre_pll_enable)
3667 encoder->pre_pll_enable(encoder);
3668
3669 intel_enable_pll(dev_priv, pipe);
3670
3671 for_each_encoder_on_crtc(dev, crtc, encoder)
3672 if (encoder->pre_enable)
3673 encoder->pre_enable(encoder);
3674
3675 /* VLV wants encoder enabling _before_ the pipe is up. */
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 encoder->enable(encoder);
3678
2dd24552
JB		 3679 /* Enable panel fitting for eDP */
3680 i9xx_pfit_enable(intel_crtc);
3681
89b667f8
JB		 3682 intel_enable_pipe(dev_priv, pipe, false);
3683 intel_enable_plane(dev_priv, plane, pipe);
3684
3685 intel_crtc_load_lut(crtc);
3686 intel_update_fbc(dev);
3687
3688 /* Give the overlay scaler a chance to enable if it's on this pipe */
3689 intel_crtc_dpms_overlay(intel_crtc, true);
3690 intel_crtc_update_cursor(crtc, true);
3691
3692 mutex_unlock(&dev_priv->dpio_lock);
3693}
3694
0b8765c6 3695static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3696{
3697 struct drm_device *dev = crtc->dev;
79e53945
JB		 3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3700 struct intel_encoder *encoder;
79e53945 3701 int pipe = intel_crtc->pipe;
80824003 3702 int plane = intel_crtc->plane;
79e53945 3703
08a48469
DV		 3704 WARN_ON(!crtc->enabled);
3705
f7abfe8b
CW		 3706 if (intel_crtc->active)
3707 return;
3708
3709 intel_crtc->active = true;
6b383a7f
CW		 3710 intel_update_watermarks(dev);
3711
63d7bbe9 3712 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3713
3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 if (encoder->pre_enable)
3716 encoder->pre_enable(encoder);
3717
2dd24552
JB		 3718 /* Enable panel fitting for LVDS */
3719 i9xx_pfit_enable(intel_crtc);
3720
040484af 3721 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3722 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3723 if (IS_G4X(dev))
3724 g4x_fixup_plane(dev_priv, pipe);
79e53945 3725
0b8765c6 3726 intel_crtc_load_lut(crtc);
bed4a673 3727 intel_update_fbc(dev);
79e53945 3728
0b8765c6
JB		 3729 /* Give the overlay scaler a chance to enable if it's on this pipe */
3730 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3731 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3732
fa5c73b1
DV		 3733 for_each_encoder_on_crtc(dev, crtc, encoder)
3734 encoder->enable(encoder);
0b8765c6 3735}
79e53945 3736
87476d63
DV		 3737static void i9xx_pfit_disable(struct intel_crtc *crtc)
3738{
3739 struct drm_device *dev = crtc->base.dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 enum pipe pipe;
3742 uint32_t pctl = I915_READ(PFIT_CONTROL);
3743
3744 assert_pipe_disabled(dev_priv, crtc->pipe);
3745
3746 if (INTEL_INFO(dev)->gen >= 4)
3747 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3748 else
3749 pipe = PIPE_B;
3750
3751 if (pipe == crtc->pipe) {
3752 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3753 I915_WRITE(PFIT_CONTROL, 0);
3754 }
3755}
3756
0b8765c6
JB		 3757static void i9xx_crtc_disable(struct drm_crtc *crtc)
3758{
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3762 struct intel_encoder *encoder;
0b8765c6
JB		 3763 int pipe = intel_crtc->pipe;
3764 int plane = intel_crtc->plane;
ef9c3aee 3765
f7abfe8b
CW		 3766 if (!intel_crtc->active)
3767 return;
3768
ea9d758d
DV		 3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 encoder->disable(encoder);
3771
0b8765c6 3772 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3773 intel_crtc_wait_for_pending_flips(crtc);
3774 drm_vblank_off(dev, pipe);
0b8765c6 3775 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3776 intel_crtc_update_cursor(crtc, false);
0b8765c6 3777
973d04f9
CW		 3778 if (dev_priv->cfb_plane == plane)
3779 intel_disable_fbc(dev);
79e53945 3780
b24e7179 3781 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3782 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3783
87476d63 3784 i9xx_pfit_disable(intel_crtc);
24a1f16d 3785
89b667f8
JB		 3786 for_each_encoder_on_crtc(dev, crtc, encoder)
3787 if (encoder->post_disable)
3788 encoder->post_disable(encoder);
3789
63d7bbe9 3790 intel_disable_pll(dev_priv, pipe);
0b8765c6 3791
f7abfe8b 3792 intel_crtc->active = false;
6b383a7f
CW		 3793 intel_update_fbc(dev);
3794 intel_update_watermarks(dev);
0b8765c6
JB		 3795}
3796
ee7b9f93
JB		 3797static void i9xx_crtc_off(struct drm_crtc *crtc)
3798{
3799}
3800
976f8a20
DV		 3801static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3802 bool enabled)
2c07245f
ZW		 3803{
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_master_private *master_priv;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807 int pipe = intel_crtc->pipe;
79e53945
JB		 3808
3809 if (!dev->primary->master)
3810 return;
3811
3812 master_priv = dev->primary->master->driver_priv;
3813 if (!master_priv->sarea_priv)
3814 return;
3815
79e53945
JB		 3816 switch (pipe) {
3817 case 0:
3818 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3819 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3820 break;
3821 case 1:
3822 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3823 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3824 break;
3825 default:
9db4a9c7 3826 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3827 break;
3828 }
79e53945
JB		 3829}
3830
976f8a20
DV		 3831/**
3832 * Sets the power management mode of the pipe and plane.
3833 */
3834void intel_crtc_update_dpms(struct drm_crtc *crtc)
3835{
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_encoder *intel_encoder;
3839 bool enable = false;
3840
3841 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3842 enable |= intel_encoder->connectors_active;
3843
3844 if (enable)
3845 dev_priv->display.crtc_enable(crtc);
3846 else
3847 dev_priv->display.crtc_disable(crtc);
3848
3849 intel_crtc_update_sarea(crtc, enable);
3850}
3851
cdd59983
CW		 3852static void intel_crtc_disable(struct drm_crtc *crtc)
3853{
cdd59983 3854 struct drm_device *dev = crtc->dev;
976f8a20 3855 struct drm_connector *connector;
ee7b9f93 3856 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3858
976f8a20
DV		 3859 /* crtc should still be enabled when we disable it. */
3860 WARN_ON(!crtc->enabled);
3861
3862 dev_priv->display.crtc_disable(crtc);
c77bf565 3863 intel_crtc->eld_vld = false;
976f8a20 3864 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3865 dev_priv->display.off(crtc);
3866
931872fc
CW		 3867 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3868 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3869
3870 if (crtc->fb) {
3871 mutex_lock(&dev->struct_mutex);
1690e1eb 3872 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3873 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3874 crtc->fb = NULL;
3875 }
3876
3877 /* Update computed state. */
3878 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3879 if (!connector->encoder || !connector->encoder->crtc)
3880 continue;
3881
3882 if (connector->encoder->crtc != crtc)
3883 continue;
3884
3885 connector->dpms = DRM_MODE_DPMS_OFF;
3886 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3887 }
3888}
3889
a261b246 3890void intel_modeset_disable(struct drm_device *dev)
79e53945 3891{
a261b246
DV		 3892 struct drm_crtc *crtc;
3893
3894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3895 if (crtc->enabled)
3896 intel_crtc_disable(crtc);
3897 }
79e53945
JB		 3898}
3899
ea5b213a 3900void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3901{
4ef69c7a 3902 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3903
ea5b213a
CW		 3904 drm_encoder_cleanup(encoder);
3905 kfree(intel_encoder);
7e7d76c3
JB		 3906}
3907
5ab432ef
DV		 3908/* Simple dpms helper for encodres with just one connector, no cloning and only
3909 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3910 * state of the entire output pipe. */
3911void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3912{
5ab432ef
DV		 3913 if (mode == DRM_MODE_DPMS_ON) {
3914 encoder->connectors_active = true;
3915
b2cabb0e 3916 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3917 } else {
3918 encoder->connectors_active = false;
3919
b2cabb0e 3920 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3921 }
79e53945
JB		 3922}
3923
0a91ca29
DV		 3924/* Cross check the actual hw state with our own modeset state tracking (and it's
3925 * internal consistency). */
b980514c 3926static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3927{
0a91ca29
DV		 3928 if (connector->get_hw_state(connector)) {
3929 struct intel_encoder *encoder = connector->encoder;
3930 struct drm_crtc *crtc;
3931 bool encoder_enabled;
3932 enum pipe pipe;
3933
3934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3935 connector->base.base.id,
3936 drm_get_connector_name(&connector->base));
3937
3938 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3939 "wrong connector dpms state\n");
3940 WARN(connector->base.encoder != &encoder->base,
3941 "active connector not linked to encoder\n");
3942 WARN(!encoder->connectors_active,
3943 "encoder->connectors_active not set\n");
3944
3945 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3946 WARN(!encoder_enabled, "encoder not enabled\n");
3947 if (WARN_ON(!encoder->base.crtc))
3948 return;
3949
3950 crtc = encoder->base.crtc;
3951
3952 WARN(!crtc->enabled, "crtc not enabled\n");
3953 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3954 WARN(pipe != to_intel_crtc(crtc)->pipe,
3955 "encoder active on the wrong pipe\n");
3956 }
79e53945
JB		 3957}
3958
5ab432ef
DV		 3959/* Even simpler default implementation, if there's really no special case to
3960 * consider. */
3961void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3962{
5ab432ef 3963 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3964
5ab432ef
DV		 3965 /* All the simple cases only support two dpms states. */
3966 if (mode != DRM_MODE_DPMS_ON)
3967 mode = DRM_MODE_DPMS_OFF;
d4270e57 3968
5ab432ef
DV		 3969 if (mode == connector->dpms)
3970 return;
3971
3972 connector->dpms = mode;
3973
3974 /* Only need to change hw state when actually enabled */
3975 if (encoder->base.crtc)
3976 intel_encoder_dpms(encoder, mode);
3977 else
8af6cf88 3978 WARN_ON(encoder->connectors_active != false);
0a91ca29 3979
b980514c 3980 intel_modeset_check_state(connector->dev);
79e53945
JB		 3981}
3982
f0947c37
DV		 3983/* Simple connector->get_hw_state implementation for encoders that support only
3984 * one connector and no cloning and hence the encoder state determines the state
3985 * of the connector. */
3986bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3987{
24929352 3988 enum pipe pipe = 0;
f0947c37 3989 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3990
f0947c37 3991 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3992}
3993
1857e1da
DV		 3994static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3995 struct intel_crtc_config *pipe_config)
3996{
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 struct intel_crtc *pipe_B_crtc =
3999 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4000
4001 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4002 pipe_name(pipe), pipe_config->fdi_lanes);
4003 if (pipe_config->fdi_lanes > 4) {
4004 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4005 pipe_name(pipe), pipe_config->fdi_lanes);
4006 return false;
4007 }
4008
4009 if (IS_HASWELL(dev)) {
4010 if (pipe_config->fdi_lanes > 2) {
4011 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4012 pipe_config->fdi_lanes);
4013 return false;
4014 } else {
4015 return true;
4016 }
4017 }
4018
4019 if (INTEL_INFO(dev)->num_pipes == 2)
4020 return true;
4021
4022 /* Ivybridge 3 pipe is really complicated */
4023 switch (pipe) {
4024 case PIPE_A:
4025 return true;
4026 case PIPE_B:
4027 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4028 pipe_config->fdi_lanes > 2) {
4029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030 pipe_name(pipe), pipe_config->fdi_lanes);
4031 return false;
4032 }
4033 return true;
4034 case PIPE_C:
1e833f40 4035 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4036 pipe_B_crtc->config.fdi_lanes <= 2) {
4037 if (pipe_config->fdi_lanes > 2) {
4038 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4039 pipe_name(pipe), pipe_config->fdi_lanes);
4040 return false;
4041 }
4042 } else {
4043 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4044 return false;
4045 }
4046 return true;
4047 default:
4048 BUG();
4049 }
4050}
4051
e29c22c0
DV		 4052#define RETRY 1
4053static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4054 struct intel_crtc_config *pipe_config)
877d48d5 4055{
1857e1da 4056 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4057 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4058 int target_clock, lane, link_bw;
e29c22c0 4059 bool setup_ok, needs_recompute = false;
877d48d5 4060
e29c22c0 4061retry:
877d48d5
DV		 4062 /* FDI is a binary signal running at ~2.7GHz, encoding
4063 * each output octet as 10 bits. The actual frequency
4064 * is stored as a divider into a 100MHz clock, and the
4065 * mode pixel clock is stored in units of 1KHz.
4066 * Hence the bw of each lane in terms of the mode signal
4067 * is:
4068 */
4069 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4070
4071 if (pipe_config->pixel_target_clock)
4072 target_clock = pipe_config->pixel_target_clock;
4073 else
4074 target_clock = adjusted_mode->clock;
4075
4076 lane = ironlake_get_lanes_required(target_clock, link_bw,
4077 pipe_config->pipe_bpp);
4078
4079 pipe_config->fdi_lanes = lane;
4080
4081 if (pipe_config->pixel_multiplier > 1)
4082 link_bw *= pipe_config->pixel_multiplier;
4083 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4084 link_bw, &pipe_config->fdi_m_n);
1857e1da 4085
e29c22c0
DV		 4086 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4087 intel_crtc->pipe, pipe_config);
4088 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4089 pipe_config->pipe_bpp -= 2*3;
4090 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4091 pipe_config->pipe_bpp);
4092 needs_recompute = true;
4093 pipe_config->bw_constrained = true;
4094
4095 goto retry;
4096 }
4097
4098 if (needs_recompute)
4099 return RETRY;
4100
4101 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4102}
4103
e29c22c0
DV		 4104static int intel_crtc_compute_config(struct drm_crtc *crtc,
4105 struct intel_crtc_config *pipe_config)
79e53945 4106{
2c07245f 4107 struct drm_device *dev = crtc->dev;
b8cecdf5 4108 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4109
bad720ff 4110 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4111 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4112 if (pipe_config->requested_mode.clock * 3
4113 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4114 return -EINVAL;
2c07245f 4115 }
89749350 4116
f9bef081
DV		 4117 /* All interlaced capable intel hw wants timings in frames. Note though
4118 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4119 * timings, so we need to be careful not to clobber these.*/
7ae89233 4120 if (!pipe_config->timings_set)
f9bef081 4121 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4122
8693a824
DL		 4123 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4124 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4125 */
4126 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4127 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4128 return -EINVAL;
44f46b42 4129
bd080ee5 4130 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4131 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4132 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4133 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4134 * for lvds. */
4135 pipe_config->pipe_bpp = 8*3;
4136 }
4137
877d48d5 4138 if (pipe_config->has_pch_encoder)
1857e1da 4139 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4140
e29c22c0 4141 return 0;
79e53945
JB		 4142}
4143
25eb05fc
JB		 4144static int valleyview_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 400000; /* FIXME */
4147}
4148
e70236a8
JB		 4149static int i945_get_display_clock_speed(struct drm_device *dev)
4150{
4151 return 400000;
4152}
79e53945 4153
e70236a8 4154static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4155{
e70236a8
JB		 4156 return 333000;
4157}
79e53945 4158
e70236a8
JB		 4159static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4160{
4161 return 200000;
4162}
79e53945 4163
e70236a8
JB		 4164static int i915gm_get_display_clock_speed(struct drm_device *dev)
4165{
4166 u16 gcfgc = 0;
79e53945 4167
e70236a8
JB		 4168 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4169
4170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4171 return 133000;
4172 else {
4173 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4174 case GC_DISPLAY_CLOCK_333_MHZ:
4175 return 333000;
4176 default:
4177 case GC_DISPLAY_CLOCK_190_200_MHZ:
4178 return 190000;
79e53945 4179 }
e70236a8
JB		 4180 }
4181}
4182
4183static int i865_get_display_clock_speed(struct drm_device *dev)
4184{
4185 return 266000;
4186}
4187
4188static int i855_get_display_clock_speed(struct drm_device *dev)
4189{
4190 u16 hpllcc = 0;
4191 /* Assume that the hardware is in the high speed state. This
4192 * should be the default.
4193 */
4194 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4195 case GC_CLOCK_133_200:
4196 case GC_CLOCK_100_200:
4197 return 200000;
4198 case GC_CLOCK_166_250:
4199 return 250000;
4200 case GC_CLOCK_100_133:
79e53945 4201 return 133000;
e70236a8 4202 }
79e53945 4203
e70236a8
JB		 4204 /* Shouldn't happen */
4205 return 0;
4206}
79e53945 4207
e70236a8
JB		 4208static int i830_get_display_clock_speed(struct drm_device *dev)
4209{
4210 return 133000;
79e53945
JB		 4211}
4212
2c07245f 4213static void
e69d0bc1 4214intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4215{
4216 while (*num > 0xffffff || *den > 0xffffff) {
4217 *num >>= 1;
4218 *den >>= 1;
4219 }
4220}
4221
e69d0bc1
DV		 4222void
4223intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4224 int pixel_clock, int link_clock,
4225 struct intel_link_m_n *m_n)
2c07245f 4226{
e69d0bc1 4227 m_n->tu = 64;
22ed1113
CW		 4228 m_n->gmch_m = bits_per_pixel * pixel_clock;
4229 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4230 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4231 m_n->link_m = pixel_clock;
4232 m_n->link_n = link_clock;
e69d0bc1 4233 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4234}
4235
a7615030
CW		 4236static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4237{
72bbe58c
KP		 4238 if (i915_panel_use_ssc >= 0)
4239 return i915_panel_use_ssc != 0;
41aa3448 4240 return dev_priv->vbt.lvds_use_ssc
435793df 4241 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4242}
4243
a0c4da24
JB		 4244static int vlv_get_refclk(struct drm_crtc *crtc)
4245{
4246 struct drm_device *dev = crtc->dev;
4247 struct drm_i915_private *dev_priv = dev->dev_private;
4248 int refclk = 27000; /* for DP & HDMI */
4249
4250 return 100000; /* only one validated so far */
4251
4252 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4253 refclk = 96000;
4254 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4255 if (intel_panel_use_ssc(dev_priv))
4256 refclk = 100000;
4257 else
4258 refclk = 96000;
4259 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4260 refclk = 100000;
4261 }
4262
4263 return refclk;
4264}
4265
c65d77d8
JB		 4266static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4267{
4268 struct drm_device *dev = crtc->dev;
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270 int refclk;
4271
a0c4da24
JB		 4272 if (IS_VALLEYVIEW(dev)) {
4273 refclk = vlv_get_refclk(crtc);
4274 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4275 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4276 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4277 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4278 refclk / 1000);
4279 } else if (!IS_GEN2(dev)) {
4280 refclk = 96000;
4281 } else {
4282 refclk = 48000;
4283 }
4284
4285 return refclk;
4286}
4287
7429e9d4
DV		 4288static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4289{
4290 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4291}
4292
4293static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4294{
4295 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4296}
4297
f47709a9 4298static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4299 intel_clock_t *reduced_clock)
4300{
f47709a9 4301 struct drm_device *dev = crtc->base.dev;
a7516a05 4302 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4303 int pipe = crtc->pipe;
a7516a05
JB		 4304 u32 fp, fp2 = 0;
4305
4306 if (IS_PINEVIEW(dev)) {
7429e9d4 4307 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4308 if (reduced_clock)
7429e9d4 4309 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4310 } else {
7429e9d4 4311 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4312 if (reduced_clock)
7429e9d4 4313 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4314 }
4315
4316 I915_WRITE(FP0(pipe), fp);
4317
f47709a9
DV		 4318 crtc->lowfreq_avail = false;
4319 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4320 reduced_clock && i915_powersave) {
4321 I915_WRITE(FP1(pipe), fp2);
f47709a9 4322 crtc->lowfreq_avail = true;
a7516a05
JB		 4323 } else {
4324 I915_WRITE(FP1(pipe), fp);
4325 }
4326}
4327
89b667f8
JB		 4328static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4329{
4330 u32 reg_val;
4331
4332 /*
4333 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4334 * and set it to a reasonable value instead.
4335 */
4336 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4337 reg_val &= 0xffffff00;
4338 reg_val |= 0x00000030;
4339 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4340
4341 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4342 reg_val &= 0x8cffffff;
4343 reg_val = 0x8c000000;
4344 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4345
4346 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4347 reg_val &= 0xffffff00;
4348 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4349
4350 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4351 reg_val &= 0x00ffffff;
4352 reg_val |= 0xb0000000;
4353 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4354}
4355
b551842d
DV		 4356static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4357 struct intel_link_m_n *m_n)
4358{
4359 struct drm_device *dev = crtc->base.dev;
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 int pipe = crtc->pipe;
4362
e3b95f1e
DV		 4363 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4364 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4365 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4366 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4367}
4368
4369static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4370 struct intel_link_m_n *m_n)
4371{
4372 struct drm_device *dev = crtc->base.dev;
4373 struct drm_i915_private *dev_priv = dev->dev_private;
4374 int pipe = crtc->pipe;
4375 enum transcoder transcoder = crtc->config.cpu_transcoder;
4376
4377 if (INTEL_INFO(dev)->gen >= 5) {
4378 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4379 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4380 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4381 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4382 } else {
e3b95f1e
DV		 4383 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4385 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4386 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4387 }
4388}
4389
03afc4a2
DV		 4390static void intel_dp_set_m_n(struct intel_crtc *crtc)
4391{
4392 if (crtc->config.has_pch_encoder)
4393 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4394 else
4395 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4396}
4397
f47709a9 4398static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4399{
f47709a9 4400 struct drm_device *dev = crtc->base.dev;
a0c4da24 4401 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4402 struct drm_display_mode *adjusted_mode =
4403 &crtc->config.adjusted_mode;
4404 struct intel_encoder *encoder;
f47709a9 4405 int pipe = crtc->pipe;
89b667f8 4406 u32 dpll, mdiv;
a0c4da24 4407 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4408 bool is_hdmi;
198a037f 4409 u32 coreclk, reg_val, dpll_md;
a0c4da24 4410
09153000
DV		 4411 mutex_lock(&dev_priv->dpio_lock);
4412
89b667f8 4413 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4414
f47709a9
DV		 4415 bestn = crtc->config.dpll.n;
4416 bestm1 = crtc->config.dpll.m1;
4417 bestm2 = crtc->config.dpll.m2;
4418 bestp1 = crtc->config.dpll.p1;
4419 bestp2 = crtc->config.dpll.p2;
a0c4da24 4420
89b667f8
JB		 4421 /* See eDP HDMI DPIO driver vbios notes doc */
4422
4423 /* PLL B needs special handling */
4424 if (pipe)
4425 vlv_pllb_recal_opamp(dev_priv);
4426
4427 /* Set up Tx target for periodic Rcomp update */
4428 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4429
4430 /* Disable target IRef on PLL */
4431 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4432 reg_val &= 0x00ffffff;
4433 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4434
4435 /* Disable fast lock */
4436 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4437
4438 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4439 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4440 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4441 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4442 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4443
4444 /*
4445 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4446 * but we don't support that).
4447 * Note: don't use the DAC post divider as it seems unstable.
4448 */
4449 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4450 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4451
89b667f8
JB		 4452 mdiv |= DPIO_ENABLE_CALIBRATION;
4453 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4454
89b667f8
JB		 4455 /* Set HBR and RBR LPF coefficients */
4456 if (adjusted_mode->clock == 162000 ||
4457 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4458 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4459 0x005f0021);
4460 else
4461 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4462 0x00d0000f);
4463
4464 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4465 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4466 /* Use SSC source */
4467 if (!pipe)
4468 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4469 0x0df40000);
4470 else
4471 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4472 0x0df70000);
4473 } else { /* HDMI or VGA */
4474 /* Use bend source */
4475 if (!pipe)
4476 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4477 0x0df70000);
4478 else
4479 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4480 0x0df40000);
4481 }
a0c4da24 4482
89b667f8
JB		 4483 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4484 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4485 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4486 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4487 coreclk |= 0x01000000;
4488 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4489
89b667f8 4490 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4491
89b667f8
JB		 4492 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4493 if (encoder->pre_pll_enable)
4494 encoder->pre_pll_enable(encoder);
2a8f64ca 4495
89b667f8
JB		 4496 /* Enable DPIO clock input */
4497 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4498 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4499 if (pipe)
4500 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4501
89b667f8 4502 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4503 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4504 POSTING_READ(DPLL(pipe));
4505 udelay(150);
a0c4da24 4506
89b667f8
JB		 4507 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4509
198a037f
DV		 4510 dpll_md = 0;
4511 if (crtc->config.pixel_multiplier > 1) {
4512 dpll_md = (crtc->config.pixel_multiplier - 1)
4513 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4514 }
198a037f
DV		 4515 I915_WRITE(DPLL_MD(pipe), dpll_md);
4516 POSTING_READ(DPLL_MD(pipe));
f47709a9 4517
89b667f8
JB		 4518 if (crtc->config.has_dp_encoder)
4519 intel_dp_set_m_n(crtc);
09153000
DV		 4520
4521 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4522}
4523
f47709a9
DV		 4524static void i9xx_update_pll(struct intel_crtc *crtc,
4525 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4526 int num_connectors)
4527{
f47709a9 4528 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4529 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4530 struct intel_encoder *encoder;
f47709a9 4531 int pipe = crtc->pipe;
eb1cbe48
DV		 4532 u32 dpll;
4533 bool is_sdvo;
f47709a9 4534 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4535
f47709a9 4536 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4537
f47709a9
DV		 4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4540
4541 dpll = DPLL_VGA_MODE_DIS;
4542
f47709a9 4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4544 dpll |= DPLLB_MODE_LVDS;
4545 else
4546 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4547
198a037f
DV		 4548 if ((crtc->config.pixel_multiplier > 1) &&
4549 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4550 dpll |= (crtc->config.pixel_multiplier - 1)
4551 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4552 }
198a037f
DV		 4553
4554 if (is_sdvo)
4555 dpll |= DPLL_DVO_HIGH_SPEED;
4556
f47709a9 4557 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4558 dpll |= DPLL_DVO_HIGH_SPEED;
4559
4560 /* compute bitmask from p1 value */
4561 if (IS_PINEVIEW(dev))
4562 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4563 else {
4564 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4565 if (IS_G4X(dev) && reduced_clock)
4566 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4567 }
4568 switch (clock->p2) {
4569 case 5:
4570 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4571 break;
4572 case 7:
4573 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4574 break;
4575 case 10:
4576 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4577 break;
4578 case 14:
4579 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4580 break;
4581 }
4582 if (INTEL_INFO(dev)->gen >= 4)
4583 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4584
09ede541 4585 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4586 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4587 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4588 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4589 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4590 else
4591 dpll |= PLL_REF_INPUT_DREFCLK;
4592
4593 dpll |= DPLL_VCO_ENABLE;
4594 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4595 POSTING_READ(DPLL(pipe));
4596 udelay(150);
4597
f47709a9 4598 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4599 if (encoder->pre_pll_enable)
4600 encoder->pre_pll_enable(encoder);
eb1cbe48 4601
f47709a9
DV		 4602 if (crtc->config.has_dp_encoder)
4603 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4604
4605 I915_WRITE(DPLL(pipe), dpll);
4606
4607 /* Wait for the clocks to stabilize. */
4608 POSTING_READ(DPLL(pipe));
4609 udelay(150);
4610
4611 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4612 u32 dpll_md = 0;
4613 if (crtc->config.pixel_multiplier > 1) {
4614 dpll_md = (crtc->config.pixel_multiplier - 1)
4615 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4616 }
198a037f 4617 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4618 } else {
4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4621 *
4622 * So write it again.
4623 */
4624 I915_WRITE(DPLL(pipe), dpll);
4625 }
4626}
4627
f47709a9 4628static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4629 struct drm_display_mode *adjusted_mode,
f47709a9 4630 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4631 int num_connectors)
4632{
f47709a9 4633 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4634 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4635 struct intel_encoder *encoder;
f47709a9 4636 int pipe = crtc->pipe;
eb1cbe48 4637 u32 dpll;
f47709a9 4638 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4639
f47709a9 4640 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4641
eb1cbe48
DV		 4642 dpll = DPLL_VGA_MODE_DIS;
4643
f47709a9 4644 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4645 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4646 } else {
4647 if (clock->p1 == 2)
4648 dpll |= PLL_P1_DIVIDE_BY_TWO;
4649 else
4650 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4651 if (clock->p2 == 4)
4652 dpll |= PLL_P2_DIVIDE_BY_4;
4653 }
4654
f47709a9 4655 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4656 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4657 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4658 else
4659 dpll |= PLL_REF_INPUT_DREFCLK;
4660
4661 dpll |= DPLL_VCO_ENABLE;
4662 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4663 POSTING_READ(DPLL(pipe));
4664 udelay(150);
4665
f47709a9 4666 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4667 if (encoder->pre_pll_enable)
4668 encoder->pre_pll_enable(encoder);
eb1cbe48 4669
5b5896e4
DV		 4670 I915_WRITE(DPLL(pipe), dpll);
4671
4672 /* Wait for the clocks to stabilize. */
4673 POSTING_READ(DPLL(pipe));
4674 udelay(150);
4675
eb1cbe48
DV		 4676 /* The pixel multiplier can only be updated once the
4677 * DPLL is enabled and the clocks are stable.
4678 *
4679 * So write it again.
4680 */
4681 I915_WRITE(DPLL(pipe), dpll);
4682}
4683
b0e77b9c
PZ		 4684static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4685 struct drm_display_mode *mode,
4686 struct drm_display_mode *adjusted_mode)
4687{
4688 struct drm_device *dev = intel_crtc->base.dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4691 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4692 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4693
4694 /* We need to be careful not to changed the adjusted mode, for otherwise
4695 * the hw state checker will get angry at the mismatch. */
4696 crtc_vtotal = adjusted_mode->crtc_vtotal;
4697 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4698
4699 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4700 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4701 crtc_vtotal -= 1;
4702 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4703 vsyncshift = adjusted_mode->crtc_hsync_start
4704 - adjusted_mode->crtc_htotal / 2;
4705 } else {
4706 vsyncshift = 0;
4707 }
4708
4709 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4710 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4711
fe2b8f9d 4712 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4713 (adjusted_mode->crtc_hdisplay - 1) |
4714 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4715 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4716 (adjusted_mode->crtc_hblank_start - 1) |
4717 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4718 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4719 (adjusted_mode->crtc_hsync_start - 1) |
4720 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4721
fe2b8f9d 4722 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4723 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4724 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4725 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4726 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4727 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4728 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4729 (adjusted_mode->crtc_vsync_start - 1) |
4730 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4731
b5e508d4
PZ		 4732 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4733 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4734 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4735 * bits. */
4736 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4737 (pipe == PIPE_B || pipe == PIPE_C))
4738 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4739
b0e77b9c
PZ		 4740 /* pipesrc controls the size that is scaled from, which should
4741 * always be the user's requested size.
4742 */
4743 I915_WRITE(PIPESRC(pipe),
4744 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4745}
4746
1bd1bd80
DV		 4747static void intel_get_pipe_timings(struct intel_crtc *crtc,
4748 struct intel_crtc_config *pipe_config)
4749{
4750 struct drm_device *dev = crtc->base.dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4753 uint32_t tmp;
4754
4755 tmp = I915_READ(HTOTAL(cpu_transcoder));
4756 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4757 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4758 tmp = I915_READ(HBLANK(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(HSYNC(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4764
4765 tmp = I915_READ(VTOTAL(cpu_transcoder));
4766 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4767 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4768 tmp = I915_READ(VBLANK(cpu_transcoder));
4769 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4770 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4771 tmp = I915_READ(VSYNC(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4774
4775 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4776 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4777 pipe_config->adjusted_mode.crtc_vtotal += 1;
4778 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4779 }
4780
4781 tmp = I915_READ(PIPESRC(crtc->pipe));
4782 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4783 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4784}
4785
84b046f3
DV		 4786static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4787{
4788 struct drm_device *dev = intel_crtc->base.dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 uint32_t pipeconf;
4791
4792 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4793
4794 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4795 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4796 * core speed.
4797 *
4798 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4799 * pipe == 0 check?
4800 */
4801 if (intel_crtc->config.requested_mode.clock >
4802 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4803 pipeconf |= PIPECONF_DOUBLE_WIDE;
4804 else
4805 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4806 }
4807
ff9ce46e
DV		 4808 /* only g4x and later have fancy bpc/dither controls */
4809 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4810 pipeconf &= ~(PIPECONF_BPC_MASK |
4811 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4812
4813 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4814 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4815 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4816 PIPECONF_DITHER_TYPE_SP;
84b046f3 4817
ff9ce46e
DV		 4818 switch (intel_crtc->config.pipe_bpp) {
4819 case 18:
4820 pipeconf |= PIPECONF_6BPC;
4821 break;
4822 case 24:
4823 pipeconf |= PIPECONF_8BPC;
4824 break;
4825 case 30:
4826 pipeconf |= PIPECONF_10BPC;
4827 break;
4828 default:
4829 /* Case prevented by intel_choose_pipe_bpp_dither. */
4830 BUG();
84b046f3
DV		 4831 }
4832 }
4833
4834 if (HAS_PIPE_CXSR(dev)) {
4835 if (intel_crtc->lowfreq_avail) {
4836 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4837 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4838 } else {
4839 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4840 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4841 }
4842 }
4843
4844 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4845 if (!IS_GEN2(dev) &&
4846 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4847 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4848 else
4849 pipeconf |= PIPECONF_PROGRESSIVE;
4850
9c8e09b7
VS		 4851 if (IS_VALLEYVIEW(dev)) {
4852 if (intel_crtc->config.limited_color_range)
4853 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4854 else
4855 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4856 }
4857
84b046f3
DV		 4858 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4859 POSTING_READ(PIPECONF(intel_crtc->pipe));
4860}
4861
f564048e 4862static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4863 int x, int y,
94352cf9 4864 struct drm_framebuffer *fb)
79e53945
JB		 4865{
4866 struct drm_device *dev = crtc->dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4869 struct drm_display_mode *adjusted_mode =
4870 &intel_crtc->config.adjusted_mode;
4871 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4872 int pipe = intel_crtc->pipe;
80824003 4873 int plane = intel_crtc->plane;
c751ce4f 4874 int refclk, num_connectors = 0;
652c393a 4875 intel_clock_t clock, reduced_clock;
84b046f3 4876 u32 dspcntr;
a16af721
DV		 4877 bool ok, has_reduced_clock = false;
4878 bool is_lvds = false;
5eddb70b 4879 struct intel_encoder *encoder;
d4906093 4880 const intel_limit_t *limit;
5c3b82e2 4881 int ret;
79e53945 4882
6c2b7c12 4883 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4884 switch (encoder->type) {
79e53945
JB		 4885 case INTEL_OUTPUT_LVDS:
4886 is_lvds = true;
4887 break;
79e53945 4888 }
43565a06 4889
c751ce4f 4890 num_connectors++;
79e53945
JB		 4891 }
4892
c65d77d8 4893 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4894
d4906093
ML		 4895 /*
4896 * Returns a set of divisors for the desired target clock with the given
4897 * refclk, or FALSE. The returned values represent the clock equation:
4898 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4899 */
1b894b59 4900 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4901 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4902 &clock);
79e53945
JB		 4903 if (!ok) {
4904 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4905 return -EINVAL;
79e53945
JB		 4906 }
4907
cda4b7d3 4908 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4909 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4910
ddc9003c 4911 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4912 /*
4913 * Ensure we match the reduced clock's P to the target clock.
4914 * If the clocks don't match, we can't switch the display clock
4915 * by using the FP0/FP1. In such case we will disable the LVDS
4916 * downclock feature.
4917 */
ddc9003c 4918 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4919 dev_priv->lvds_downclock,
4920 refclk,
cec2f356 4921 &clock,
5eddb70b 4922 &reduced_clock);
7026d4ac 4923 }
f47709a9
DV		 4924 /* Compat-code for transition, will disappear. */
4925 if (!intel_crtc->config.clock_set) {
4926 intel_crtc->config.dpll.n = clock.n;
4927 intel_crtc->config.dpll.m1 = clock.m1;
4928 intel_crtc->config.dpll.m2 = clock.m2;
4929 intel_crtc->config.dpll.p1 = clock.p1;
4930 intel_crtc->config.dpll.p2 = clock.p2;
4931 }
7026d4ac 4932
eb1cbe48 4933 if (IS_GEN2(dev))
f47709a9 4934 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4935 has_reduced_clock ? &reduced_clock : NULL,
4936 num_connectors);
a0c4da24 4937 else if (IS_VALLEYVIEW(dev))
f47709a9 4938 vlv_update_pll(intel_crtc);
79e53945 4939 else
f47709a9 4940 i9xx_update_pll(intel_crtc,
eb1cbe48 4941 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4942 num_connectors);
79e53945 4943
79e53945
JB		 4944 /* Set up the display plane register */
4945 dspcntr = DISPPLANE_GAMMA_ENABLE;
4946
da6ecc5d
JB		 4947 if (!IS_VALLEYVIEW(dev)) {
4948 if (pipe == 0)
4949 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4950 else
4951 dspcntr |= DISPPLANE_SEL_PIPE_B;
4952 }
79e53945 4953
2582a850 4954 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4955 drm_mode_debug_printmodeline(mode);
4956
b0e77b9c 4957 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4958
4959 /* pipesrc and dspsize control the size that is scaled from,
4960 * which should always be the user's requested size.
79e53945 4961 */
929c77fb
EA		 4962 I915_WRITE(DSPSIZE(plane),
4963 ((mode->vdisplay - 1) << 16) |
4964 (mode->hdisplay - 1));
4965 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4966
84b046f3
DV		 4967 i9xx_set_pipeconf(intel_crtc);
4968
f564048e
EA		 4969 I915_WRITE(DSPCNTR(plane), dspcntr);
4970 POSTING_READ(DSPCNTR(plane));
4971
94352cf9 4972 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4973
4974 intel_update_watermarks(dev);
4975
f564048e
EA		 4976 return ret;
4977}
4978
0e8ffe1b
DV		 4979static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4980 struct intel_crtc_config *pipe_config)
4981{
4982 struct drm_device *dev = crtc->base.dev;
4983 struct drm_i915_private *dev_priv = dev->dev_private;
4984 uint32_t tmp;
4985
4986 tmp = I915_READ(PIPECONF(crtc->pipe));
4987 if (!(tmp & PIPECONF_ENABLE))
4988 return false;
4989
1bd1bd80
DV		 4990 intel_get_pipe_timings(crtc, pipe_config);
4991
0e8ffe1b
DV		 4992 return true;
4993}
4994
dde86e2d 4995static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4996{
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4999 struct intel_encoder *encoder;
74cfd7ac 5000 u32 val, final;
13d83a67 5001 bool has_lvds = false;
199e5d79 5002 bool has_cpu_edp = false;
199e5d79 5003 bool has_panel = false;
99eb6a01
KP		 5004 bool has_ck505 = false;
5005 bool can_ssc = false;
13d83a67
JB		 5006
5007 /* We need to take the global config into account */
199e5d79
KP		 5008 list_for_each_entry(encoder, &mode_config->encoder_list,
5009 base.head) {
5010 switch (encoder->type) {
5011 case INTEL_OUTPUT_LVDS:
5012 has_panel = true;
5013 has_lvds = true;
5014 break;
5015 case INTEL_OUTPUT_EDP:
5016 has_panel = true;
2de6905f 5017 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5018 has_cpu_edp = true;
5019 break;
13d83a67
JB		 5020 }
5021 }
5022
99eb6a01 5023 if (HAS_PCH_IBX(dev)) {
41aa3448 5024 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5025 can_ssc = has_ck505;
5026 } else {
5027 has_ck505 = false;
5028 can_ssc = true;
5029 }
5030
2de6905f
ID		 5031 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5032 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5033
5034 /* Ironlake: try to setup display ref clock before DPLL
5035 * enabling. This is only under driver's control after
5036 * PCH B stepping, previous chipset stepping should be
5037 * ignoring this setting.
5038 */
74cfd7ac
CW		 5039 val = I915_READ(PCH_DREF_CONTROL);
5040
5041 /* As we must carefully and slowly disable/enable each source in turn,
5042 * compute the final state we want first and check if we need to
5043 * make any changes at all.
5044 */
5045 final = val;
5046 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5047 if (has_ck505)
5048 final |= DREF_NONSPREAD_CK505_ENABLE;
5049 else
5050 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5051
5052 final &= ~DREF_SSC_SOURCE_MASK;
5053 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5054 final &= ~DREF_SSC1_ENABLE;
5055
5056 if (has_panel) {
5057 final |= DREF_SSC_SOURCE_ENABLE;
5058
5059 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5060 final |= DREF_SSC1_ENABLE;
5061
5062 if (has_cpu_edp) {
5063 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5064 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5065 else
5066 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5067 } else
5068 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5069 } else {
5070 final |= DREF_SSC_SOURCE_DISABLE;
5071 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5072 }
5073
5074 if (final == val)
5075 return;
5076
13d83a67 5077 /* Always enable nonspread source */
74cfd7ac 5078 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5079
99eb6a01 5080 if (has_ck505)
74cfd7ac 5081 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5082 else
74cfd7ac 5083 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5084
199e5d79 5085 if (has_panel) {
74cfd7ac
CW		 5086 val &= ~DREF_SSC_SOURCE_MASK;
5087 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5088
199e5d79 5089 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5090 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5091 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5092 val |= DREF_SSC1_ENABLE;
e77166b5 5093 } else
74cfd7ac 5094 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5095
5096 /* Get SSC going before enabling the outputs */
74cfd7ac 5097 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5098 POSTING_READ(PCH_DREF_CONTROL);
5099 udelay(200);
5100
74cfd7ac 5101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5102
5103 /* Enable CPU source on CPU attached eDP */
199e5d79 5104 if (has_cpu_edp) {
99eb6a01 5105 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5106 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5107 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5108 }
13d83a67 5109 else
74cfd7ac 5110 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5111 } else
74cfd7ac 5112 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5113
74cfd7ac 5114 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5115 POSTING_READ(PCH_DREF_CONTROL);
5116 udelay(200);
5117 } else {
5118 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5119
74cfd7ac 5120 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5121
5122 /* Turn off CPU output */
74cfd7ac 5123 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5124
74cfd7ac 5125 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5126 POSTING_READ(PCH_DREF_CONTROL);
5127 udelay(200);
5128
5129 /* Turn off the SSC source */
74cfd7ac
CW		 5130 val &= ~DREF_SSC_SOURCE_MASK;
5131 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5132
5133 /* Turn off SSC1 */
74cfd7ac 5134 val &= ~DREF_SSC1_ENABLE;
199e5d79 5135
74cfd7ac 5136 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5137 POSTING_READ(PCH_DREF_CONTROL);
5138 udelay(200);
5139 }
74cfd7ac
CW		 5140
5141 BUG_ON(val != final);
13d83a67
JB		 5142}
5143
dde86e2d
PZ		 5144/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5145static void lpt_init_pch_refclk(struct drm_device *dev)
5146{
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 struct drm_mode_config *mode_config = &dev->mode_config;
5149 struct intel_encoder *encoder;
5150 bool has_vga = false;
5151 bool is_sdv = false;
5152 u32 tmp;
5153
5154 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5155 switch (encoder->type) {
5156 case INTEL_OUTPUT_ANALOG:
5157 has_vga = true;
5158 break;
5159 }
5160 }
5161
5162 if (!has_vga)
5163 return;
5164
c00db246
DV		 5165 mutex_lock(&dev_priv->dpio_lock);
5166
dde86e2d
PZ		 5167 /* XXX: Rip out SDV support once Haswell ships for real. */
5168 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5169 is_sdv = true;
5170
5171 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5172 tmp &= ~SBI_SSCCTL_DISABLE;
5173 tmp |= SBI_SSCCTL_PATHALT;
5174 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5175
5176 udelay(24);
5177
5178 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5179 tmp &= ~SBI_SSCCTL_PATHALT;
5180 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5181
5182 if (!is_sdv) {
5183 tmp = I915_READ(SOUTH_CHICKEN2);
5184 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5185 I915_WRITE(SOUTH_CHICKEN2, tmp);
5186
5187 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5188 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5189 DRM_ERROR("FDI mPHY reset assert timeout\n");
5190
5191 tmp = I915_READ(SOUTH_CHICKEN2);
5192 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5193 I915_WRITE(SOUTH_CHICKEN2, tmp);
5194
5195 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5196 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5197 100))
5198 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5199 }
5200
5201 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5202 tmp &= ~(0xFF << 24);
5203 tmp |= (0x12 << 24);
5204 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5205
dde86e2d
PZ		 5206 if (is_sdv) {
5207 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5208 tmp |= 0x7FFF;
5209 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5210 }
5211
5212 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5213 tmp |= (1 << 11);
5214 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5215
5216 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5217 tmp |= (1 << 11);
5218 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5219
5220 if (is_sdv) {
5221 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5222 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5223 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5224
5225 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5226 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5227 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5228
5229 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5230 tmp |= (0x3F << 8);
5231 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5234 tmp |= (0x3F << 8);
5235 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5236 }
5237
5238 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5239 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5240 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5241
5242 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5243 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5244 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5245
5246 if (!is_sdv) {
5247 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5248 tmp &= ~(7 << 13);
5249 tmp |= (5 << 13);
5250 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5253 tmp &= ~(7 << 13);
5254 tmp |= (5 << 13);
5255 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5256 }
5257
5258 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5259 tmp &= ~0xFF;
5260 tmp |= 0x1C;
5261 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5264 tmp &= ~0xFF;
5265 tmp |= 0x1C;
5266 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5269 tmp &= ~(0xFF << 16);
5270 tmp |= (0x1C << 16);
5271 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5274 tmp &= ~(0xFF << 16);
5275 tmp |= (0x1C << 16);
5276 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5277
5278 if (!is_sdv) {
5279 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5280 tmp |= (1 << 27);
5281 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5282
5283 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5284 tmp |= (1 << 27);
5285 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5286
5287 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5288 tmp &= ~(0xF << 28);
5289 tmp |= (4 << 28);
5290 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5291
5292 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5293 tmp &= ~(0xF << 28);
5294 tmp |= (4 << 28);
5295 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5296 }
5297
5298 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5299 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5300 tmp |= SBI_DBUFF0_ENABLE;
5301 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5302
5303 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5304}
5305
5306/*
5307 * Initialize reference clocks when the driver loads
5308 */
5309void intel_init_pch_refclk(struct drm_device *dev)
5310{
5311 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5312 ironlake_init_pch_refclk(dev);
5313 else if (HAS_PCH_LPT(dev))
5314 lpt_init_pch_refclk(dev);
5315}
5316
d9d444cb
JB		 5317static int ironlake_get_refclk(struct drm_crtc *crtc)
5318{
5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 struct intel_encoder *encoder;
d9d444cb
JB		 5322 int num_connectors = 0;
5323 bool is_lvds = false;
5324
6c2b7c12 5325 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5326 switch (encoder->type) {
5327 case INTEL_OUTPUT_LVDS:
5328 is_lvds = true;
5329 break;
d9d444cb
JB		 5330 }
5331 num_connectors++;
5332 }
5333
5334 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5335 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5336 dev_priv->vbt.lvds_ssc_freq);
5337 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5338 }
5339
5340 return 120000;
5341}
5342
6ff93609 5343static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5344{
c8203565 5345 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347 int pipe = intel_crtc->pipe;
c8203565
PZ		 5348 uint32_t val;
5349
5350 val = I915_READ(PIPECONF(pipe));
5351
dfd07d72 5352 val &= ~PIPECONF_BPC_MASK;
965e0c48 5353 switch (intel_crtc->config.pipe_bpp) {
c8203565 5354 case 18:
dfd07d72 5355 val |= PIPECONF_6BPC;
c8203565
PZ		 5356 break;
5357 case 24:
dfd07d72 5358 val |= PIPECONF_8BPC;
c8203565
PZ		 5359 break;
5360 case 30:
dfd07d72 5361 val |= PIPECONF_10BPC;
c8203565
PZ		 5362 break;
5363 case 36:
dfd07d72 5364 val |= PIPECONF_12BPC;
c8203565
PZ		 5365 break;
5366 default:
cc769b62
PZ		 5367 /* Case prevented by intel_choose_pipe_bpp_dither. */
5368 BUG();
c8203565
PZ		 5369 }
5370
5371 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5372 if (intel_crtc->config.dither)
c8203565
PZ		 5373 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5374
5375 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5376 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5377 val |= PIPECONF_INTERLACED_ILK;
5378 else
5379 val |= PIPECONF_PROGRESSIVE;
5380
50f3b016 5381 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5382 val |= PIPECONF_COLOR_RANGE_SELECT;
5383 else
5384 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5385
c8203565
PZ		 5386 I915_WRITE(PIPECONF(pipe), val);
5387 POSTING_READ(PIPECONF(pipe));
5388}
5389
86d3efce
VS		 5390/*
5391 * Set up the pipe CSC unit.
5392 *
5393 * Currently only full range RGB to limited range RGB conversion
5394 * is supported, but eventually this should handle various
5395 * RGB<->YCbCr scenarios as well.
5396 */
50f3b016 5397static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5398{
5399 struct drm_device *dev = crtc->dev;
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402 int pipe = intel_crtc->pipe;
5403 uint16_t coeff = 0x7800; /* 1.0 */
5404
5405 /*
5406 * TODO: Check what kind of values actually come out of the pipe
5407 * with these coeff/postoff values and adjust to get the best
5408 * accuracy. Perhaps we even need to take the bpc value into
5409 * consideration.
5410 */
5411
50f3b016 5412 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5413 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5414
5415 /*
5416 * GY/GU and RY/RU should be the other way around according
5417 * to BSpec, but reality doesn't agree. Just set them up in
5418 * a way that results in the correct picture.
5419 */
5420 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5421 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5422
5423 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5424 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5425
5426 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5427 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5428
5429 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5430 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5431 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5432
5433 if (INTEL_INFO(dev)->gen > 6) {
5434 uint16_t postoff = 0;
5435
50f3b016 5436 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5437 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5438
5439 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5440 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5441 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5442
5443 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5444 } else {
5445 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5446
50f3b016 5447 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5448 mode |= CSC_BLACK_SCREEN_OFFSET;
5449
5450 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5451 }
5452}
5453
6ff93609 5454static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5455{
5456 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5458 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5459 uint32_t val;
5460
702e7a56 5461 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5462
5463 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5464 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5465 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5466
5467 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5468 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5469 val |= PIPECONF_INTERLACED_ILK;
5470 else
5471 val |= PIPECONF_PROGRESSIVE;
5472
702e7a56
PZ		 5473 I915_WRITE(PIPECONF(cpu_transcoder), val);
5474 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5475}
5476
6591c6e4
PZ		 5477static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5478 struct drm_display_mode *adjusted_mode,
5479 intel_clock_t *clock,
5480 bool *has_reduced_clock,
5481 intel_clock_t *reduced_clock)
5482{
5483 struct drm_device *dev = crtc->dev;
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485 struct intel_encoder *intel_encoder;
5486 int refclk;
d4906093 5487 const intel_limit_t *limit;
a16af721 5488 bool ret, is_lvds = false;
79e53945 5489
6591c6e4
PZ		 5490 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5491 switch (intel_encoder->type) {
79e53945
JB		 5492 case INTEL_OUTPUT_LVDS:
5493 is_lvds = true;
5494 break;
79e53945
JB		 5495 }
5496 }
5497
d9d444cb 5498 refclk = ironlake_get_refclk(crtc);
79e53945 5499
d4906093
ML		 5500 /*
5501 * Returns a set of divisors for the desired target clock with the given
5502 * refclk, or FALSE. The returned values represent the clock equation:
5503 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5504 */
1b894b59 5505 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5506 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5507 clock);
5508 if (!ret)
5509 return false;
cda4b7d3 5510
ddc9003c 5511 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5512 /*
5513 * Ensure we match the reduced clock's P to the target clock.
5514 * If the clocks don't match, we can't switch the display clock
5515 * by using the FP0/FP1. In such case we will disable the LVDS
5516 * downclock feature.
5517 */
6591c6e4
PZ		 5518 *has_reduced_clock = limit->find_pll(limit, crtc,
5519 dev_priv->lvds_downclock,
5520 refclk,
5521 clock,
5522 reduced_clock);
652c393a 5523 }
61e9653f 5524
6591c6e4
PZ		 5525 return true;
5526}
5527
01a415fd
DV		 5528static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5529{
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531 uint32_t temp;
5532
5533 temp = I915_READ(SOUTH_CHICKEN1);
5534 if (temp & FDI_BC_BIFURCATION_SELECT)
5535 return;
5536
5537 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5538 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5539
5540 temp |= FDI_BC_BIFURCATION_SELECT;
5541 DRM_DEBUG_KMS("enabling fdi C rx\n");
5542 I915_WRITE(SOUTH_CHICKEN1, temp);
5543 POSTING_READ(SOUTH_CHICKEN1);
5544}
5545
ebfd86fd
DV		 5546static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5547{
5548 struct drm_device *dev = intel_crtc->base.dev;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551 switch (intel_crtc->pipe) {
5552 case PIPE_A:
5553 break;
5554 case PIPE_B:
5555 if (intel_crtc->config.fdi_lanes > 2)
5556 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5557 else
5558 cpt_enable_fdi_bc_bifurcation(dev);
5559
5560 break;
5561 case PIPE_C:
01a415fd
DV		 5562 cpt_enable_fdi_bc_bifurcation(dev);
5563
ebfd86fd 5564 break;
01a415fd
DV		 5565 default:
5566 BUG();
5567 }
5568}
5569
d4b1931c
PZ		 5570int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5571{
5572 /*
5573 * Account for spread spectrum to avoid
5574 * oversubscribing the link. Max center spread
5575 * is 2.5%; use 5% for safety's sake.
5576 */
5577 u32 bps = target_clock * bpp * 21 / 20;
5578 return bps / (link_bw * 8) + 1;
5579}
5580
7429e9d4
DV		 5581static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5582{
5583 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5584}
5585
de13a2e3 5586static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5587 u32 *fp,
9a7c7890 5588 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5589{
de13a2e3 5590 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5591 struct drm_device *dev = crtc->dev;
5592 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5593 struct intel_encoder *intel_encoder;
5594 uint32_t dpll;
6cc5f341 5595 int factor, num_connectors = 0;
09ede541 5596 bool is_lvds = false, is_sdvo = false;
79e53945 5597
de13a2e3
PZ		 5598 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5599 switch (intel_encoder->type) {
79e53945
JB		 5600 case INTEL_OUTPUT_LVDS:
5601 is_lvds = true;
5602 break;
5603 case INTEL_OUTPUT_SDVO:
7d57382e 5604 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5605 is_sdvo = true;
5606 break;
79e53945 5607 }
43565a06 5608
c751ce4f 5609 num_connectors++;
79e53945 5610 }
79e53945 5611
c1858123 5612 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5613 factor = 21;
5614 if (is_lvds) {
5615 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5616 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5617 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5618 factor = 25;
09ede541 5619 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5620 factor = 20;
c1858123 5621
7429e9d4 5622 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5623 *fp |= FP_CB_TUNE;
2c07245f 5624
9a7c7890
DV		 5625 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5626 *fp2 |= FP_CB_TUNE;
5627
5eddb70b 5628 dpll = 0;
2c07245f 5629
a07d6787
EA		 5630 if (is_lvds)
5631 dpll |= DPLLB_MODE_LVDS;
5632 else
5633 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5634
5635 if (intel_crtc->config.pixel_multiplier > 1) {
5636 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5637 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5638 }
198a037f
DV		 5639
5640 if (is_sdvo)
5641 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5642 if (intel_crtc->config.has_dp_encoder)
a07d6787 5643 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5644
a07d6787 5645 /* compute bitmask from p1 value */
7429e9d4 5646 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5647 /* also FPA1 */
7429e9d4 5648 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5649
7429e9d4 5650 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5651 case 5:
5652 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5653 break;
5654 case 7:
5655 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5656 break;
5657 case 10:
5658 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5659 break;
5660 case 14:
5661 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5662 break;
79e53945
JB		 5663 }
5664
b4c09f3b 5665 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5666 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5667 else
5668 dpll |= PLL_REF_INPUT_DREFCLK;
5669
de13a2e3
PZ		 5670 return dpll;
5671}
5672
5673static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5674 int x, int y,
5675 struct drm_framebuffer *fb)
5676{
5677 struct drm_device *dev = crtc->dev;
5678 struct drm_i915_private *dev_priv = dev->dev_private;
5679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5680 struct drm_display_mode *adjusted_mode =
5681 &intel_crtc->config.adjusted_mode;
5682 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5683 int pipe = intel_crtc->pipe;
5684 int plane = intel_crtc->plane;
5685 int num_connectors = 0;
5686 intel_clock_t clock, reduced_clock;
cbbab5bd 5687 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5688 bool ok, has_reduced_clock = false;
8b47047b 5689 bool is_lvds = false;
de13a2e3 5690 struct intel_encoder *encoder;
de13a2e3 5691 int ret;
de13a2e3
PZ		 5692
5693 for_each_encoder_on_crtc(dev, crtc, encoder) {
5694 switch (encoder->type) {
5695 case INTEL_OUTPUT_LVDS:
5696 is_lvds = true;
5697 break;
de13a2e3
PZ		 5698 }
5699
5700 num_connectors++;
a07d6787 5701 }
79e53945 5702
5dc5298b
PZ		 5703 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5704 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5705
3b117c8f 5706 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5707
de13a2e3
PZ		 5708 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5709 &has_reduced_clock, &reduced_clock);
5710 if (!ok) {
5711 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5712 return -EINVAL;
79e53945 5713 }
f47709a9
DV		 5714 /* Compat-code for transition, will disappear. */
5715 if (!intel_crtc->config.clock_set) {
5716 intel_crtc->config.dpll.n = clock.n;
5717 intel_crtc->config.dpll.m1 = clock.m1;
5718 intel_crtc->config.dpll.m2 = clock.m2;
5719 intel_crtc->config.dpll.p1 = clock.p1;
5720 intel_crtc->config.dpll.p2 = clock.p2;
5721 }
79e53945 5722
de13a2e3
PZ		 5723 /* Ensure that the cursor is valid for the new mode before changing... */
5724 intel_crtc_update_cursor(crtc, true);
5725
84f44ce7 5726 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5727 drm_mode_debug_printmodeline(mode);
5728
5dc5298b 5729 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5730 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5731 struct intel_pch_pll *pll;
4b645f14 5732
7429e9d4 5733 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5734 if (has_reduced_clock)
7429e9d4 5735 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5736
7429e9d4 5737 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5738 &fp, &reduced_clock,
5739 has_reduced_clock ? &fp2 : NULL);
5740
ee7b9f93
JB		 5741 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5742 if (pll == NULL) {
84f44ce7
VS		 5743 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5744 pipe_name(pipe));
4b645f14
JB		 5745 return -EINVAL;
5746 }
ee7b9f93
JB		 5747 } else
5748 intel_put_pch_pll(intel_crtc);
79e53945 5749
03afc4a2
DV		 5750 if (intel_crtc->config.has_dp_encoder)
5751 intel_dp_set_m_n(intel_crtc);
79e53945 5752
dafd226c
DV		 5753 for_each_encoder_on_crtc(dev, crtc, encoder)
5754 if (encoder->pre_pll_enable)
5755 encoder->pre_pll_enable(encoder);
79e53945 5756
ee7b9f93
JB		 5757 if (intel_crtc->pch_pll) {
5758 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5759
32f9d658 5760 /* Wait for the clocks to stabilize. */
ee7b9f93 5761 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5762 udelay(150);
5763
8febb297
EA		 5764 /* The pixel multiplier can only be updated once the
5765 * DPLL is enabled and the clocks are stable.
5766 *
5767 * So write it again.
5768 */
ee7b9f93 5769 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5770 }
79e53945 5771
5eddb70b 5772 intel_crtc->lowfreq_avail = false;
ee7b9f93 5773 if (intel_crtc->pch_pll) {
4b645f14 5774 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5775 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5776 intel_crtc->lowfreq_avail = true;
4b645f14 5777 } else {
ee7b9f93 5778 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5779 }
5780 }
5781
b0e77b9c 5782 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5783
ca3a0ff8 5784 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5785 intel_cpu_transcoder_set_m_n(intel_crtc,
5786 &intel_crtc->config.fdi_m_n);
5787 }
2c07245f 5788
ebfd86fd
DV		 5789 if (IS_IVYBRIDGE(dev))
5790 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5791
6ff93609 5792 ironlake_set_pipeconf(crtc);
79e53945 5793
a1f9e77e
PZ		 5794 /* Set up the display plane register */
5795 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5796 POSTING_READ(DSPCNTR(plane));
79e53945 5797
94352cf9 5798 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5799
5800 intel_update_watermarks(dev);
5801
1f8eeabf
ED		 5802 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5803
1857e1da 5804 return ret;
79e53945
JB		 5805}
5806
72419203
DV		 5807static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5808 struct intel_crtc_config *pipe_config)
5809{
5810 struct drm_device *dev = crtc->base.dev;
5811 struct drm_i915_private *dev_priv = dev->dev_private;
5812 enum transcoder transcoder = pipe_config->cpu_transcoder;
5813
5814 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5815 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5816 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5817 & ~TU_SIZE_MASK;
5818 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5819 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5820 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5821}
5822
0e8ffe1b
DV		 5823static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5824 struct intel_crtc_config *pipe_config)
5825{
5826 struct drm_device *dev = crtc->base.dev;
5827 struct drm_i915_private *dev_priv = dev->dev_private;
5828 uint32_t tmp;
5829
5830 tmp = I915_READ(PIPECONF(crtc->pipe));
5831 if (!(tmp & PIPECONF_ENABLE))
5832 return false;
5833
ab9412ba 5834 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5835 pipe_config->has_pch_encoder = true;
5836
627eb5a3
DV		 5837 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5838 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5839 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5840
5841 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5842 }
5843
1bd1bd80
DV		 5844 intel_get_pipe_timings(crtc, pipe_config);
5845
0e8ffe1b
DV		 5846 return true;
5847}
5848
d6dd9eb1
DV		 5849static void haswell_modeset_global_resources(struct drm_device *dev)
5850{
d6dd9eb1
DV		 5851 bool enable = false;
5852 struct intel_crtc *crtc;
5853 struct intel_encoder *encoder;
5854
5855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5856 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5857 enable = true;
5858 /* XXX: Should check for edp transcoder here, but thanks to init
5859 * sequence that's not yet available. Just in case desktop eDP
5860 * on PORT D is possible on haswell, too. */
b074cec8 5861 /* Even the eDP panel fitter is outside the always-on well. */
2b87f3b1 5862 if (crtc->config.pch_pfit.size && crtc->base.enabled)
b074cec8 5863 enable = true;
d6dd9eb1
DV		 5864 }
5865
5866 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5867 base.head) {
5868 if (encoder->type != INTEL_OUTPUT_EDP &&
5869 encoder->connectors_active)
5870 enable = true;
5871 }
5872
d6dd9eb1
DV		 5873 intel_set_power_well(dev, enable);
5874}
5875
09b4ddf9 5876static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5877 int x, int y,
5878 struct drm_framebuffer *fb)
5879{
5880 struct drm_device *dev = crtc->dev;
5881 struct drm_i915_private *dev_priv = dev->dev_private;
5882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5883 struct drm_display_mode *adjusted_mode =
5884 &intel_crtc->config.adjusted_mode;
5885 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5886 int pipe = intel_crtc->pipe;
5887 int plane = intel_crtc->plane;
5888 int num_connectors = 0;
8b47047b 5889 bool is_cpu_edp = false;
09b4ddf9 5890 struct intel_encoder *encoder;
09b4ddf9 5891 int ret;
09b4ddf9
PZ		 5892
5893 for_each_encoder_on_crtc(dev, crtc, encoder) {
5894 switch (encoder->type) {
09b4ddf9 5895 case INTEL_OUTPUT_EDP:
d8e8b582 5896 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5897 is_cpu_edp = true;
5898 break;
5899 }
5900
5901 num_connectors++;
5902 }
5903
bba2181c 5904 if (is_cpu_edp)
3b117c8f 5905 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5906 else
3b117c8f 5907 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5908
5dc5298b
PZ		 5909 /* We are not sure yet this won't happen. */
5910 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5911 INTEL_PCH_TYPE(dev));
5912
5913 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5914 num_connectors, pipe_name(pipe));
5915
3b117c8f 5916 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5917 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5918
5919 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5920
6441ab5f
PZ		 5921 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5922 return -EINVAL;
5923
09b4ddf9
PZ		 5924 /* Ensure that the cursor is valid for the new mode before changing... */
5925 intel_crtc_update_cursor(crtc, true);
5926
84f44ce7 5927 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5928 drm_mode_debug_printmodeline(mode);
5929
03afc4a2
DV		 5930 if (intel_crtc->config.has_dp_encoder)
5931 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5932
5933 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5934
5935 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5936
ca3a0ff8 5937 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5938 intel_cpu_transcoder_set_m_n(intel_crtc,
5939 &intel_crtc->config.fdi_m_n);
5940 }
09b4ddf9 5941
6ff93609 5942 haswell_set_pipeconf(crtc);
09b4ddf9 5943
50f3b016 5944 intel_set_pipe_csc(crtc);
86d3efce 5945
09b4ddf9 5946 /* Set up the display plane register */
86d3efce 5947 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5948 POSTING_READ(DSPCNTR(plane));
5949
5950 ret = intel_pipe_set_base(crtc, x, y, fb);
5951
5952 intel_update_watermarks(dev);
5953
5954 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5955
1f803ee5 5956 return ret;
79e53945
JB		 5957}
5958
0e8ffe1b
DV		 5959static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5960 struct intel_crtc_config *pipe_config)
5961{
5962 struct drm_device *dev = crtc->base.dev;
5963 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5964 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5965 uint32_t tmp;
5966
b97186f0
PZ		 5967 if (!intel_display_power_enabled(dev,
5968 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
2bfce950
PZ		 5969 return false;
5970
5971 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5972 if (!(tmp & PIPECONF_ENABLE))
5973 return false;
5974
88adfff1 5975 /*
f196e6be 5976 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5977 * DDI E. So just check whether this pipe is wired to DDI E and whether
5978 * the PCH transcoder is on.
5979 */
f196e6be 5980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1 5981 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5982 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5983 pipe_config->has_pch_encoder = true;
5984
627eb5a3
DV		 5985 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5986 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5987 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5988
5989 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5990 }
5991
1bd1bd80
DV		 5992 intel_get_pipe_timings(crtc, pipe_config);
5993
0e8ffe1b
DV		 5994 return true;
5995}
5996
f564048e 5997static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5998 int x, int y,
94352cf9 5999 struct drm_framebuffer *fb)
f564048e
EA		 6000{
6001 struct drm_device *dev = crtc->dev;
6002 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6003 struct drm_encoder_helper_funcs *encoder_funcs;
6004 struct intel_encoder *encoder;
0b701d27 6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6006 struct drm_display_mode *adjusted_mode =
6007 &intel_crtc->config.adjusted_mode;
6008 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6009 int pipe = intel_crtc->pipe;
f564048e
EA		 6010 int ret;
6011
0b701d27 6012 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6013
b8cecdf5
DV		 6014 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6015
79e53945 6016 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6017
9256aa19
DV		 6018 if (ret != 0)
6019 return ret;
6020
6021 for_each_encoder_on_crtc(dev, crtc, encoder) {
6022 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6023 encoder->base.base.id,
6024 drm_get_encoder_name(&encoder->base),
6025 mode->base.id, mode->name);
6cc5f341
DV		 6026 if (encoder->mode_set) {
6027 encoder->mode_set(encoder);
6028 } else {
6029 encoder_funcs = encoder->base.helper_private;
6030 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6031 }
9256aa19
DV		 6032 }
6033
6034 return 0;
79e53945
JB		 6035}
6036
3a9627f4
WF		 6037static bool intel_eld_uptodate(struct drm_connector *connector,
6038 int reg_eldv, uint32_t bits_eldv,
6039 int reg_elda, uint32_t bits_elda,
6040 int reg_edid)
6041{
6042 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6043 uint8_t *eld = connector->eld;
6044 uint32_t i;
6045
6046 i = I915_READ(reg_eldv);
6047 i &= bits_eldv;
6048
6049 if (!eld[0])
6050 return !i;
6051
6052 if (!i)
6053 return false;
6054
6055 i = I915_READ(reg_elda);
6056 i &= ~bits_elda;
6057 I915_WRITE(reg_elda, i);
6058
6059 for (i = 0; i < eld[2]; i++)
6060 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6061 return false;
6062
6063 return true;
6064}
6065
e0dac65e
WF		 6066static void g4x_write_eld(struct drm_connector *connector,
6067 struct drm_crtc *crtc)
6068{
6069 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6070 uint8_t *eld = connector->eld;
6071 uint32_t eldv;
6072 uint32_t len;
6073 uint32_t i;
6074
6075 i = I915_READ(G4X_AUD_VID_DID);
6076
6077 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6078 eldv = G4X_ELDV_DEVCL_DEVBLC;
6079 else
6080 eldv = G4X_ELDV_DEVCTG;
6081
3a9627f4
WF		 6082 if (intel_eld_uptodate(connector,
6083 G4X_AUD_CNTL_ST, eldv,
6084 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6085 G4X_HDMIW_HDMIEDID))
6086 return;
6087
e0dac65e
WF		 6088 i = I915_READ(G4X_AUD_CNTL_ST);
6089 i &= ~(eldv | G4X_ELD_ADDR);
6090 len = (i >> 9) & 0x1f; /* ELD buffer size */
6091 I915_WRITE(G4X_AUD_CNTL_ST, i);
6092
6093 if (!eld[0])
6094 return;
6095
6096 len = min_t(uint8_t, eld[2], len);
6097 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6098 for (i = 0; i < len; i++)
6099 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6100
6101 i = I915_READ(G4X_AUD_CNTL_ST);
6102 i |= eldv;
6103 I915_WRITE(G4X_AUD_CNTL_ST, i);
6104}
6105
83358c85
WX		 6106static void haswell_write_eld(struct drm_connector *connector,
6107 struct drm_crtc *crtc)
6108{
6109 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6110 uint8_t *eld = connector->eld;
6111 struct drm_device *dev = crtc->dev;
7b9f35a6 6112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6113 uint32_t eldv;
6114 uint32_t i;
6115 int len;
6116 int pipe = to_intel_crtc(crtc)->pipe;
6117 int tmp;
6118
6119 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6120 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6121 int aud_config = HSW_AUD_CFG(pipe);
6122 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6123
6124
6125 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6126
6127 /* Audio output enable */
6128 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6129 tmp = I915_READ(aud_cntrl_st2);
6130 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6131 I915_WRITE(aud_cntrl_st2, tmp);
6132
6133 /* Wait for 1 vertical blank */
6134 intel_wait_for_vblank(dev, pipe);
6135
6136 /* Set ELD valid state */
6137 tmp = I915_READ(aud_cntrl_st2);
6138 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6139 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6140 I915_WRITE(aud_cntrl_st2, tmp);
6141 tmp = I915_READ(aud_cntrl_st2);
6142 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6143
6144 /* Enable HDMI mode */
6145 tmp = I915_READ(aud_config);
6146 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6147 /* clear N_programing_enable and N_value_index */
6148 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6149 I915_WRITE(aud_config, tmp);
6150
6151 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6152
6153 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6154 intel_crtc->eld_vld = true;
83358c85
WX		 6155
6156 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6157 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6158 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6159 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6160 } else
6161 I915_WRITE(aud_config, 0);
6162
6163 if (intel_eld_uptodate(connector,
6164 aud_cntrl_st2, eldv,
6165 aud_cntl_st, IBX_ELD_ADDRESS,
6166 hdmiw_hdmiedid))
6167 return;
6168
6169 i = I915_READ(aud_cntrl_st2);
6170 i &= ~eldv;
6171 I915_WRITE(aud_cntrl_st2, i);
6172
6173 if (!eld[0])
6174 return;
6175
6176 i = I915_READ(aud_cntl_st);
6177 i &= ~IBX_ELD_ADDRESS;
6178 I915_WRITE(aud_cntl_st, i);
6179 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6180 DRM_DEBUG_DRIVER("port num:%d\n", i);
6181
6182 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6183 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6184 for (i = 0; i < len; i++)
6185 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6186
6187 i = I915_READ(aud_cntrl_st2);
6188 i |= eldv;
6189 I915_WRITE(aud_cntrl_st2, i);
6190
6191}
6192
e0dac65e
WF		 6193static void ironlake_write_eld(struct drm_connector *connector,
6194 struct drm_crtc *crtc)
6195{
6196 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6197 uint8_t *eld = connector->eld;
6198 uint32_t eldv;
6199 uint32_t i;
6200 int len;
6201 int hdmiw_hdmiedid;
b6daa025 6202 int aud_config;
e0dac65e
WF		 6203 int aud_cntl_st;
6204 int aud_cntrl_st2;
9b138a83 6205 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6206
b3f33cbf 6207 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6208 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6209 aud_config = IBX_AUD_CFG(pipe);
6210 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6211 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6212 } else {
9b138a83
WX		 6213 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6214 aud_config = CPT_AUD_CFG(pipe);
6215 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6216 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6217 }
6218
9b138a83 6219 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6220
6221 i = I915_READ(aud_cntl_st);
9b138a83 6222 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6223 if (!i) {
6224 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6225 /* operate blindly on all ports */
1202b4c6
WF		 6226 eldv = IBX_ELD_VALIDB;
6227 eldv |= IBX_ELD_VALIDB << 4;
6228 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6229 } else {
2582a850 6230 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6231 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6232 }
6233
3a9627f4
WF		 6234 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6235 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6236 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6237 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6238 } else
6239 I915_WRITE(aud_config, 0);
e0dac65e 6240
3a9627f4
WF		 6241 if (intel_eld_uptodate(connector,
6242 aud_cntrl_st2, eldv,
6243 aud_cntl_st, IBX_ELD_ADDRESS,
6244 hdmiw_hdmiedid))
6245 return;
6246
e0dac65e
WF		 6247 i = I915_READ(aud_cntrl_st2);
6248 i &= ~eldv;
6249 I915_WRITE(aud_cntrl_st2, i);
6250
6251 if (!eld[0])
6252 return;
6253
e0dac65e 6254 i = I915_READ(aud_cntl_st);
1202b4c6 6255 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6256 I915_WRITE(aud_cntl_st, i);
6257
6258 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6259 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6260 for (i = 0; i < len; i++)
6261 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6262
6263 i = I915_READ(aud_cntrl_st2);
6264 i |= eldv;
6265 I915_WRITE(aud_cntrl_st2, i);
6266}
6267
6268void intel_write_eld(struct drm_encoder *encoder,
6269 struct drm_display_mode *mode)
6270{
6271 struct drm_crtc *crtc = encoder->crtc;
6272 struct drm_connector *connector;
6273 struct drm_device *dev = encoder->dev;
6274 struct drm_i915_private *dev_priv = dev->dev_private;
6275
6276 connector = drm_select_eld(encoder, mode);
6277 if (!connector)
6278 return;
6279
6280 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6281 connector->base.id,
6282 drm_get_connector_name(connector),
6283 connector->encoder->base.id,
6284 drm_get_encoder_name(connector->encoder));
6285
6286 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6287
6288 if (dev_priv->display.write_eld)
6289 dev_priv->display.write_eld(connector, crtc);
6290}
6291
79e53945
JB		 6292/** Loads the palette/gamma unit for the CRTC with the prepared values */
6293void intel_crtc_load_lut(struct drm_crtc *crtc)
6294{
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6298 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6299 int i;
6300
6301 /* The clocks have to be on to load the palette. */
aed3f09d 6302 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6303 return;
6304
f2b115e6 6305 /* use legacy palette for Ironlake */
bad720ff 6306 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6307 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6308
79e53945
JB		 6309 for (i = 0; i < 256; i++) {
6310 I915_WRITE(palreg + 4 * i,
6311 (intel_crtc->lut_r[i] << 16) |
6312 (intel_crtc->lut_g[i] << 8) |
6313 intel_crtc->lut_b[i]);
6314 }
6315}
6316
560b85bb
CW		 6317static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6318{
6319 struct drm_device *dev = crtc->dev;
6320 struct drm_i915_private *dev_priv = dev->dev_private;
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6322 bool visible = base != 0;
6323 u32 cntl;
6324
6325 if (intel_crtc->cursor_visible == visible)
6326 return;
6327
9db4a9c7 6328 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6329 if (visible) {
6330 /* On these chipsets we can only modify the base whilst
6331 * the cursor is disabled.
6332 */
9db4a9c7 6333 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6334
6335 cntl &= ~(CURSOR_FORMAT_MASK);
6336 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6337 cntl |= CURSOR_ENABLE |
6338 CURSOR_GAMMA_ENABLE |
6339 CURSOR_FORMAT_ARGB;
6340 } else
6341 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6342 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6343
6344 intel_crtc->cursor_visible = visible;
6345}
6346
6347static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6348{
6349 struct drm_device *dev = crtc->dev;
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352 int pipe = intel_crtc->pipe;
6353 bool visible = base != 0;
6354
6355 if (intel_crtc->cursor_visible != visible) {
548f245b 6356 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6357 if (base) {
6358 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6359 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6360 cntl |= pipe << 28; /* Connect to correct pipe */
6361 } else {
6362 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6363 cntl |= CURSOR_MODE_DISABLE;
6364 }
9db4a9c7 6365 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6366
6367 intel_crtc->cursor_visible = visible;
6368 }
6369 /* and commit changes on next vblank */
9db4a9c7 6370 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6371}
6372
65a21cd6
JB		 6373static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6374{
6375 struct drm_device *dev = crtc->dev;
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378 int pipe = intel_crtc->pipe;
6379 bool visible = base != 0;
6380
6381 if (intel_crtc->cursor_visible != visible) {
6382 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6383 if (base) {
6384 cntl &= ~CURSOR_MODE;
6385 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6386 } else {
6387 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6388 cntl |= CURSOR_MODE_DISABLE;
6389 }
86d3efce
VS		 6390 if (IS_HASWELL(dev))
6391 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6392 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6393
6394 intel_crtc->cursor_visible = visible;
6395 }
6396 /* and commit changes on next vblank */
6397 I915_WRITE(CURBASE_IVB(pipe), base);
6398}
6399
cda4b7d3 6400/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6401static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6402 bool on)
cda4b7d3
CW		 6403{
6404 struct drm_device *dev = crtc->dev;
6405 struct drm_i915_private *dev_priv = dev->dev_private;
6406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6407 int pipe = intel_crtc->pipe;
6408 int x = intel_crtc->cursor_x;
6409 int y = intel_crtc->cursor_y;
560b85bb 6410 u32 base, pos;
cda4b7d3
CW		 6411 bool visible;
6412
6413 pos = 0;
6414
6b383a7f 6415 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6416 base = intel_crtc->cursor_addr;
6417 if (x > (int) crtc->fb->width)
6418 base = 0;
6419
6420 if (y > (int) crtc->fb->height)
6421 base = 0;
6422 } else
6423 base = 0;
6424
6425 if (x < 0) {
6426 if (x + intel_crtc->cursor_width < 0)
6427 base = 0;
6428
6429 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6430 x = -x;
6431 }
6432 pos |= x << CURSOR_X_SHIFT;
6433
6434 if (y < 0) {
6435 if (y + intel_crtc->cursor_height < 0)
6436 base = 0;
6437
6438 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6439 y = -y;
6440 }
6441 pos |= y << CURSOR_Y_SHIFT;
6442
6443 visible = base != 0;
560b85bb 6444 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6445 return;
6446
0cd83aa9 6447 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6448 I915_WRITE(CURPOS_IVB(pipe), pos);
6449 ivb_update_cursor(crtc, base);
6450 } else {
6451 I915_WRITE(CURPOS(pipe), pos);
6452 if (IS_845G(dev) || IS_I865G(dev))
6453 i845_update_cursor(crtc, base);
6454 else
6455 i9xx_update_cursor(crtc, base);
6456 }
cda4b7d3
CW		 6457}
6458
79e53945 6459static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6460 struct drm_file *file,
79e53945
JB		 6461 uint32_t handle,
6462 uint32_t width, uint32_t height)
6463{
6464 struct drm_device *dev = crtc->dev;
6465 struct drm_i915_private *dev_priv = dev->dev_private;
6466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6467 struct drm_i915_gem_object *obj;
cda4b7d3 6468 uint32_t addr;
3f8bc370 6469 int ret;
79e53945 6470
79e53945
JB		 6471 /* if we want to turn off the cursor ignore width and height */
6472 if (!handle) {
28c97730 6473 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6474 addr = 0;
05394f39 6475 obj = NULL;
5004417d 6476 mutex_lock(&dev->struct_mutex);
3f8bc370 6477 goto finish;
79e53945
JB		 6478 }
6479
6480 /* Currently we only support 64x64 cursors */
6481 if (width != 64 || height != 64) {
6482 DRM_ERROR("we currently only support 64x64 cursors\n");
6483 return -EINVAL;
6484 }
6485
05394f39 6486 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6487 if (&obj->base == NULL)
79e53945
JB		 6488 return -ENOENT;
6489
05394f39 6490 if (obj->base.size < width * height * 4) {
79e53945 6491 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6492 ret = -ENOMEM;
6493 goto fail;
79e53945
JB		 6494 }
6495
71acb5eb 6496 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6497 mutex_lock(&dev->struct_mutex);
b295d1b6 6498 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6499 unsigned alignment;
6500
d9e86c0e
CW		 6501 if (obj->tiling_mode) {
6502 DRM_ERROR("cursor cannot be tiled\n");
6503 ret = -EINVAL;
6504 goto fail_locked;
6505 }
6506
693db184
CW		 6507 /* Note that the w/a also requires 2 PTE of padding following
6508 * the bo. We currently fill all unused PTE with the shadow
6509 * page and so we should always have valid PTE following the
6510 * cursor preventing the VT-d warning.
6511 */
6512 alignment = 0;
6513 if (need_vtd_wa(dev))
6514 alignment = 64*1024;
6515
6516 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6517 if (ret) {
6518 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6519 goto fail_locked;
e7b526bb
CW		 6520 }
6521
d9e86c0e
CW		 6522 ret = i915_gem_object_put_fence(obj);
6523 if (ret) {
2da3b9b9 6524 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6525 goto fail_unpin;
6526 }
6527
05394f39 6528 addr = obj->gtt_offset;
71acb5eb 6529 } else {
6eeefaf3 6530 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6531 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6532 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6533 align);
71acb5eb
DA		 6534 if (ret) {
6535 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6536 goto fail_locked;
71acb5eb 6537 }
05394f39 6538 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6539 }
6540
a6c45cf0 6541 if (IS_GEN2(dev))
14b60391
JB		 6542 I915_WRITE(CURSIZE, (height << 12) | width);
6543
3f8bc370 6544 finish:
3f8bc370 6545 if (intel_crtc->cursor_bo) {
b295d1b6 6546 if (dev_priv->info->cursor_needs_physical) {
05394f39 6547 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6548 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6549 } else
6550 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6551 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6552 }
80824003 6553
7f9872e0 6554 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6555
6556 intel_crtc->cursor_addr = addr;
05394f39 6557 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6558 intel_crtc->cursor_width = width;
6559 intel_crtc->cursor_height = height;
6560
6b383a7f 6561 intel_crtc_update_cursor(crtc, true);
3f8bc370 6562
79e53945 6563 return 0;
e7b526bb 6564fail_unpin:
05394f39 6565 i915_gem_object_unpin(obj);
7f9872e0 6566fail_locked:
34b8686e 6567 mutex_unlock(&dev->struct_mutex);
bc9025bd 6568fail:
05394f39 6569 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6570 return ret;
79e53945
JB		 6571}
6572
6573static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6574{
79e53945 6575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6576
cda4b7d3
CW		 6577 intel_crtc->cursor_x = x;
6578 intel_crtc->cursor_y = y;
652c393a 6579
6b383a7f 6580 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6581
6582 return 0;
6583}
6584
6585/** Sets the color ramps on behalf of RandR */
6586void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6587 u16 blue, int regno)
6588{
6589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6590
6591 intel_crtc->lut_r[regno] = red >> 8;
6592 intel_crtc->lut_g[regno] = green >> 8;
6593 intel_crtc->lut_b[regno] = blue >> 8;
6594}
6595
b8c00ac5
DA		 6596void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6597 u16 *blue, int regno)
6598{
6599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600
6601 *red = intel_crtc->lut_r[regno] << 8;
6602 *green = intel_crtc->lut_g[regno] << 8;
6603 *blue = intel_crtc->lut_b[regno] << 8;
6604}
6605
79e53945 6606static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6607 u16 *blue, uint32_t start, uint32_t size)
79e53945 6608{
7203425a 6609 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6611
7203425a 6612 for (i = start; i < end; i++) {
79e53945
JB		 6613 intel_crtc->lut_r[i] = red[i] >> 8;
6614 intel_crtc->lut_g[i] = green[i] >> 8;
6615 intel_crtc->lut_b[i] = blue[i] >> 8;
6616 }
6617
6618 intel_crtc_load_lut(crtc);
6619}
6620
79e53945
JB		 6621/* VESA 640x480x72Hz mode to set on the pipe */
6622static struct drm_display_mode load_detect_mode = {
6623 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6624 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6625};
6626
d2dff872
CW		 6627static struct drm_framebuffer *
6628intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6629 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6630 struct drm_i915_gem_object *obj)
6631{
6632 struct intel_framebuffer *intel_fb;
6633 int ret;
6634
6635 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6636 if (!intel_fb) {
6637 drm_gem_object_unreference_unlocked(&obj->base);
6638 return ERR_PTR(-ENOMEM);
6639 }
6640
6641 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6642 if (ret) {
6643 drm_gem_object_unreference_unlocked(&obj->base);
6644 kfree(intel_fb);
6645 return ERR_PTR(ret);
6646 }
6647
6648 return &intel_fb->base;
6649}
6650
6651static u32
6652intel_framebuffer_pitch_for_width(int width, int bpp)
6653{
6654 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6655 return ALIGN(pitch, 64);
6656}
6657
6658static u32
6659intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6660{
6661 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6662 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6663}
6664
6665static struct drm_framebuffer *
6666intel_framebuffer_create_for_mode(struct drm_device *dev,
6667 struct drm_display_mode *mode,
6668 int depth, int bpp)
6669{
6670 struct drm_i915_gem_object *obj;
0fed39bd 6671 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6672
6673 obj = i915_gem_alloc_object(dev,
6674 intel_framebuffer_size_for_mode(mode, bpp));
6675 if (obj == NULL)
6676 return ERR_PTR(-ENOMEM);
6677
6678 mode_cmd.width = mode->hdisplay;
6679 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6680 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6681 bpp);
5ca0c34a 6682 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6683
6684 return intel_framebuffer_create(dev, &mode_cmd, obj);
6685}
6686
6687static struct drm_framebuffer *
6688mode_fits_in_fbdev(struct drm_device *dev,
6689 struct drm_display_mode *mode)
6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 struct drm_i915_gem_object *obj;
6693 struct drm_framebuffer *fb;
6694
6695 if (dev_priv->fbdev == NULL)
6696 return NULL;
6697
6698 obj = dev_priv->fbdev->ifb.obj;
6699 if (obj == NULL)
6700 return NULL;
6701
6702 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6703 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6704 fb->bits_per_pixel))
d2dff872
CW		 6705 return NULL;
6706
01f2c773 6707 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6708 return NULL;
6709
6710 return fb;
6711}
6712
d2434ab7 6713bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6714 struct drm_display_mode *mode,
8261b191 6715 struct intel_load_detect_pipe *old)
79e53945
JB		 6716{
6717 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6718 struct intel_encoder *intel_encoder =
6719 intel_attached_encoder(connector);
79e53945 6720 struct drm_crtc *possible_crtc;
4ef69c7a 6721 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6722 struct drm_crtc *crtc = NULL;
6723 struct drm_device *dev = encoder->dev;
94352cf9 6724 struct drm_framebuffer *fb;
79e53945
JB		 6725 int i = -1;
6726
d2dff872
CW		 6727 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6728 connector->base.id, drm_get_connector_name(connector),
6729 encoder->base.id, drm_get_encoder_name(encoder));
6730
79e53945
JB		 6731 /*
6732 * Algorithm gets a little messy:
7a5e4805 6733 *
79e53945
JB		 6734 * - if the connector already has an assigned crtc, use it (but make
6735 * sure it's on first)
7a5e4805 6736 *
79e53945
JB		 6737 * - try to find the first unused crtc that can drive this connector,
6738 * and use that if we find one
79e53945
JB		 6739 */
6740
6741 /* See if we already have a CRTC for this connector */
6742 if (encoder->crtc) {
6743 crtc = encoder->crtc;
8261b191 6744
7b24056b
DV		 6745 mutex_lock(&crtc->mutex);
6746
24218aac 6747 old->dpms_mode = connector->dpms;
8261b191
CW		 6748 old->load_detect_temp = false;
6749
6750 /* Make sure the crtc and connector are running */
24218aac
DV		 6751 if (connector->dpms != DRM_MODE_DPMS_ON)
6752 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6753
7173188d 6754 return true;
79e53945
JB		 6755 }
6756
6757 /* Find an unused one (if possible) */
6758 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6759 i++;
6760 if (!(encoder->possible_crtcs & (1 << i)))
6761 continue;
6762 if (!possible_crtc->enabled) {
6763 crtc = possible_crtc;
6764 break;
6765 }
79e53945
JB		 6766 }
6767
6768 /*
6769 * If we didn't find an unused CRTC, don't use any.
6770 */
6771 if (!crtc) {
7173188d
CW		 6772 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6773 return false;
79e53945
JB		 6774 }
6775
7b24056b 6776 mutex_lock(&crtc->mutex);
fc303101
DV		 6777 intel_encoder->new_crtc = to_intel_crtc(crtc);
6778 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6779
6780 intel_crtc = to_intel_crtc(crtc);
24218aac 6781 old->dpms_mode = connector->dpms;
8261b191 6782 old->load_detect_temp = true;
d2dff872 6783 old->release_fb = NULL;
79e53945 6784
6492711d
CW		 6785 if (!mode)
6786 mode = &load_detect_mode;
79e53945 6787
d2dff872
CW		 6788 /* We need a framebuffer large enough to accommodate all accesses
6789 * that the plane may generate whilst we perform load detection.
6790 * We can not rely on the fbcon either being present (we get called
6791 * during its initialisation to detect all boot displays, or it may
6792 * not even exist) or that it is large enough to satisfy the
6793 * requested mode.
6794 */
94352cf9
DV		 6795 fb = mode_fits_in_fbdev(dev, mode);
6796 if (fb == NULL) {
d2dff872 6797 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6798 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6799 old->release_fb = fb;
d2dff872
CW		 6800 } else
6801 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6802 if (IS_ERR(fb)) {
d2dff872 6803 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6804 mutex_unlock(&crtc->mutex);
0e8b3d3e 6805 return false;
79e53945 6806 }
79e53945 6807
c0c36b94 6808 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6809 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6810 if (old->release_fb)
6811 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6812 mutex_unlock(&crtc->mutex);
0e8b3d3e 6813 return false;
79e53945 6814 }
7173188d 6815
79e53945 6816 /* let the connector get through one full cycle before testing */
9d0498a2 6817 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6818 return true;
79e53945
JB		 6819}
6820
d2434ab7 6821void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6822 struct intel_load_detect_pipe *old)
79e53945 6823{
d2434ab7
DV		 6824 struct intel_encoder *intel_encoder =
6825 intel_attached_encoder(connector);
4ef69c7a 6826 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6827 struct drm_crtc *crtc = encoder->crtc;
79e53945 6828
d2dff872
CW		 6829 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6830 connector->base.id, drm_get_connector_name(connector),
6831 encoder->base.id, drm_get_encoder_name(encoder));
6832
8261b191 6833 if (old->load_detect_temp) {
fc303101
DV		 6834 to_intel_connector(connector)->new_encoder = NULL;
6835 intel_encoder->new_crtc = NULL;
6836 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6837
36206361
DV		 6838 if (old->release_fb) {
6839 drm_framebuffer_unregister_private(old->release_fb);
6840 drm_framebuffer_unreference(old->release_fb);
6841 }
d2dff872 6842
67c96400 6843 mutex_unlock(&crtc->mutex);
0622a53c 6844 return;
79e53945
JB		 6845 }
6846
c751ce4f 6847 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6848 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6849 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6850
6851 mutex_unlock(&crtc->mutex);
79e53945
JB		 6852}
6853
6854/* Returns the clock of the currently programmed mode of the given pipe. */
6855static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6856{
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 int pipe = intel_crtc->pipe;
548f245b 6860 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6861 u32 fp;
6862 intel_clock_t clock;
6863
6864 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6865 fp = I915_READ(FP0(pipe));
79e53945 6866 else
39adb7a5 6867 fp = I915_READ(FP1(pipe));
79e53945
JB		 6868
6869 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6870 if (IS_PINEVIEW(dev)) {
6871 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6872 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6873 } else {
6874 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6875 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6876 }
6877
a6c45cf0 6878 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6879 if (IS_PINEVIEW(dev))
6880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6881 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6882 else
6883 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6884 DPLL_FPA01_P1_POST_DIV_SHIFT);
6885
6886 switch (dpll & DPLL_MODE_MASK) {
6887 case DPLLB_MODE_DAC_SERIAL:
6888 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6889 5 : 10;
6890 break;
6891 case DPLLB_MODE_LVDS:
6892 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6893 7 : 14;
6894 break;
6895 default:
28c97730 6896 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6897 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6898 return 0;
6899 }
6900
6901 /* XXX: Handle the 100Mhz refclk */
2177832f 6902 intel_clock(dev, 96000, &clock);
79e53945
JB		 6903 } else {
6904 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6905
6906 if (is_lvds) {
6907 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6908 DPLL_FPA01_P1_POST_DIV_SHIFT);
6909 clock.p2 = 14;
6910
6911 if ((dpll & PLL_REF_INPUT_MASK) ==
6912 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6913 /* XXX: might not be 66MHz */
2177832f 6914 intel_clock(dev, 66000, &clock);
79e53945 6915 } else
2177832f 6916 intel_clock(dev, 48000, &clock);
79e53945
JB		 6917 } else {
6918 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6919 clock.p1 = 2;
6920 else {
6921 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6922 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6923 }
6924 if (dpll & PLL_P2_DIVIDE_BY_4)
6925 clock.p2 = 4;
6926 else
6927 clock.p2 = 2;
6928
2177832f 6929 intel_clock(dev, 48000, &clock);
79e53945
JB		 6930 }
6931 }
6932
6933 /* XXX: It would be nice to validate the clocks, but we can't reuse
6934 * i830PllIsValid() because it relies on the xf86_config connector
6935 * configuration being accurate, which it isn't necessarily.
6936 */
6937
6938 return clock.dot;
6939}
6940
6941/** Returns the currently programmed mode of the given pipe. */
6942struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6943 struct drm_crtc *crtc)
6944{
548f245b 6945 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6947 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6948 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6949 int htot = I915_READ(HTOTAL(cpu_transcoder));
6950 int hsync = I915_READ(HSYNC(cpu_transcoder));
6951 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6952 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6953
6954 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6955 if (!mode)
6956 return NULL;
6957
6958 mode->clock = intel_crtc_clock_get(dev, crtc);
6959 mode->hdisplay = (htot & 0xffff) + 1;
6960 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6961 mode->hsync_start = (hsync & 0xffff) + 1;
6962 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6963 mode->vdisplay = (vtot & 0xffff) + 1;
6964 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6965 mode->vsync_start = (vsync & 0xffff) + 1;
6966 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6967
6968 drm_mode_set_name(mode);
79e53945
JB		 6969
6970 return mode;
6971}
6972
3dec0095 6973static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6974{
6975 struct drm_device *dev = crtc->dev;
6976 drm_i915_private_t *dev_priv = dev->dev_private;
6977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6978 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6979 int dpll_reg = DPLL(pipe);
6980 int dpll;
652c393a 6981
bad720ff 6982 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6983 return;
6984
6985 if (!dev_priv->lvds_downclock_avail)
6986 return;
6987
dbdc6479 6988 dpll = I915_READ(dpll_reg);
652c393a 6989 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6990 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6991
8ac5a6d5 6992 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6993
6994 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6995 I915_WRITE(dpll_reg, dpll);
9d0498a2 6996 intel_wait_for_vblank(dev, pipe);
dbdc6479 6997
652c393a
JB		 6998 dpll = I915_READ(dpll_reg);
6999 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7000 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7001 }
652c393a
JB		 7002}
7003
7004static void intel_decrease_pllclock(struct drm_crtc *crtc)
7005{
7006 struct drm_device *dev = crtc->dev;
7007 drm_i915_private_t *dev_priv = dev->dev_private;
7008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7009
bad720ff 7010 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7011 return;
7012
7013 if (!dev_priv->lvds_downclock_avail)
7014 return;
7015
7016 /*
7017 * Since this is called by a timer, we should never get here in
7018 * the manual case.
7019 */
7020 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7021 int pipe = intel_crtc->pipe;
7022 int dpll_reg = DPLL(pipe);
7023 int dpll;
f6e5b160 7024
44d98a61 7025 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7026
8ac5a6d5 7027 assert_panel_unlocked(dev_priv, pipe);
652c393a 7028
dc257cf1 7029 dpll = I915_READ(dpll_reg);
652c393a
JB		 7030 dpll |= DISPLAY_RATE_SELECT_FPA1;
7031 I915_WRITE(dpll_reg, dpll);
9d0498a2 7032 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7033 dpll = I915_READ(dpll_reg);
7034 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7035 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7036 }
7037
7038}
7039
f047e395
CW		 7040void intel_mark_busy(struct drm_device *dev)
7041{
f047e395
CW		 7042 i915_update_gfx_val(dev->dev_private);
7043}
7044
7045void intel_mark_idle(struct drm_device *dev)
652c393a 7046{
652c393a 7047 struct drm_crtc *crtc;
652c393a
JB		 7048
7049 if (!i915_powersave)
7050 return;
7051
652c393a 7052 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7053 if (!crtc->fb)
7054 continue;
7055
725a5b54 7056 intel_decrease_pllclock(crtc);
652c393a 7057 }
652c393a
JB		 7058}
7059
725a5b54 7060void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7061{
f047e395
CW		 7062 struct drm_device *dev = obj->base.dev;
7063 struct drm_crtc *crtc;
652c393a 7064
f047e395 7065 if (!i915_powersave)
acb87dfb
CW		 7066 return;
7067
652c393a
JB		 7068 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7069 if (!crtc->fb)
7070 continue;
7071
f047e395 7072 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7073 intel_increase_pllclock(crtc);
652c393a
JB		 7074 }
7075}
7076
79e53945
JB		 7077static void intel_crtc_destroy(struct drm_crtc *crtc)
7078{
7079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7080 struct drm_device *dev = crtc->dev;
7081 struct intel_unpin_work *work;
7082 unsigned long flags;
7083
7084 spin_lock_irqsave(&dev->event_lock, flags);
7085 work = intel_crtc->unpin_work;
7086 intel_crtc->unpin_work = NULL;
7087 spin_unlock_irqrestore(&dev->event_lock, flags);
7088
7089 if (work) {
7090 cancel_work_sync(&work->work);
7091 kfree(work);
7092 }
79e53945
JB		 7093
7094 drm_crtc_cleanup(crtc);
67e77c5a 7095
79e53945
JB		 7096 kfree(intel_crtc);
7097}
7098
6b95a207
KH		 7099static void intel_unpin_work_fn(struct work_struct *__work)
7100{
7101 struct intel_unpin_work *work =
7102 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7103 struct drm_device *dev = work->crtc->dev;
6b95a207 7104
b4a98e57 7105 mutex_lock(&dev->struct_mutex);
1690e1eb 7106 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7107 drm_gem_object_unreference(&work->pending_flip_obj->base);
7108 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7109
b4a98e57
CW		 7110 intel_update_fbc(dev);
7111 mutex_unlock(&dev->struct_mutex);
7112
7113 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7114 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7115
6b95a207
KH		 7116 kfree(work);
7117}
7118
1afe3e9d 7119static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7120 struct drm_crtc *crtc)
6b95a207
KH		 7121{
7122 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7124 struct intel_unpin_work *work;
6b95a207
KH		 7125 unsigned long flags;
7126
7127 /* Ignore early vblank irqs */
7128 if (intel_crtc == NULL)
7129 return;
7130
7131 spin_lock_irqsave(&dev->event_lock, flags);
7132 work = intel_crtc->unpin_work;
e7d841ca
CW		 7133
7134 /* Ensure we don't miss a work->pending update ... */
7135 smp_rmb();
7136
7137 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7138 spin_unlock_irqrestore(&dev->event_lock, flags);
7139 return;
7140 }
7141
e7d841ca
CW		 7142 /* and that the unpin work is consistent wrt ->pending. */
7143 smp_rmb();
7144
6b95a207 7145 intel_crtc->unpin_work = NULL;
6b95a207 7146
45a066eb
RC		 7147 if (work->event)
7148 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7149
0af7e4df
MK		 7150 drm_vblank_put(dev, intel_crtc->pipe);
7151
6b95a207
KH		 7152 spin_unlock_irqrestore(&dev->event_lock, flags);
7153
2c10d571 7154 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7155
7156 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7157
7158 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7159}
7160
1afe3e9d
JB		 7161void intel_finish_page_flip(struct drm_device *dev, int pipe)
7162{
7163 drm_i915_private_t *dev_priv = dev->dev_private;
7164 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7165
49b14a5c 7166 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7167}
7168
7169void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7170{
7171 drm_i915_private_t *dev_priv = dev->dev_private;
7172 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7173
49b14a5c 7174 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7175}
7176
6b95a207
KH		 7177void intel_prepare_page_flip(struct drm_device *dev, int plane)
7178{
7179 drm_i915_private_t *dev_priv = dev->dev_private;
7180 struct intel_crtc *intel_crtc =
7181 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7182 unsigned long flags;
7183
e7d841ca
CW		 7184 /* NB: An MMIO update of the plane base pointer will also
7185 * generate a page-flip completion irq, i.e. every modeset
7186 * is also accompanied by a spurious intel_prepare_page_flip().
7187 */
6b95a207 7188 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7189 if (intel_crtc->unpin_work)
7190 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7191 spin_unlock_irqrestore(&dev->event_lock, flags);
7192}
7193
e7d841ca
CW		 7194inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7195{
7196 /* Ensure that the work item is consistent when activating it ... */
7197 smp_wmb();
7198 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7199 /* and that it is marked active as soon as the irq could fire. */
7200 smp_wmb();
7201}
7202
8c9f3aaf
JB		 7203static int intel_gen2_queue_flip(struct drm_device *dev,
7204 struct drm_crtc *crtc,
7205 struct drm_framebuffer *fb,
7206 struct drm_i915_gem_object *obj)
7207{
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7210 u32 flip_mask;
6d90c952 7211 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7212 int ret;
7213
6d90c952 7214 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7215 if (ret)
83d4092b 7216 goto err;
8c9f3aaf 7217
6d90c952 7218 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7219 if (ret)
83d4092b 7220 goto err_unpin;
8c9f3aaf
JB		 7221
7222 /* Can't queue multiple flips, so wait for the previous
7223 * one to finish before executing the next.
7224 */
7225 if (intel_crtc->plane)
7226 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7227 else
7228 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7229 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7230 intel_ring_emit(ring, MI_NOOP);
7231 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7232 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7233 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7234 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7235 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7236
7237 intel_mark_page_flip_active(intel_crtc);
6d90c952 7238 intel_ring_advance(ring);
83d4092b
CW		 7239 return 0;
7240
7241err_unpin:
7242 intel_unpin_fb_obj(obj);
7243err:
8c9f3aaf
JB		 7244 return ret;
7245}
7246
7247static int intel_gen3_queue_flip(struct drm_device *dev,
7248 struct drm_crtc *crtc,
7249 struct drm_framebuffer *fb,
7250 struct drm_i915_gem_object *obj)
7251{
7252 struct drm_i915_private *dev_priv = dev->dev_private;
7253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7254 u32 flip_mask;
6d90c952 7255 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7256 int ret;
7257
6d90c952 7258 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7259 if (ret)
83d4092b 7260 goto err;
8c9f3aaf 7261
6d90c952 7262 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7263 if (ret)
83d4092b 7264 goto err_unpin;
8c9f3aaf
JB		 7265
7266 if (intel_crtc->plane)
7267 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7268 else
7269 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7270 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7271 intel_ring_emit(ring, MI_NOOP);
7272 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7273 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7274 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7275 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7276 intel_ring_emit(ring, MI_NOOP);
7277
e7d841ca 7278 intel_mark_page_flip_active(intel_crtc);
6d90c952 7279 intel_ring_advance(ring);
83d4092b
CW		 7280 return 0;
7281
7282err_unpin:
7283 intel_unpin_fb_obj(obj);
7284err:
8c9f3aaf
JB		 7285 return ret;
7286}
7287
7288static int intel_gen4_queue_flip(struct drm_device *dev,
7289 struct drm_crtc *crtc,
7290 struct drm_framebuffer *fb,
7291 struct drm_i915_gem_object *obj)
7292{
7293 struct drm_i915_private *dev_priv = dev->dev_private;
7294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7295 uint32_t pf, pipesrc;
6d90c952 7296 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7297 int ret;
7298
6d90c952 7299 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7300 if (ret)
83d4092b 7301 goto err;
8c9f3aaf 7302
6d90c952 7303 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7304 if (ret)
83d4092b 7305 goto err_unpin;
8c9f3aaf
JB		 7306
7307 /* i965+ uses the linear or tiled offsets from the
7308 * Display Registers (which do not change across a page-flip)
7309 * so we need only reprogram the base address.
7310 */
6d90c952
DV		 7311 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7312 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7313 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7314 intel_ring_emit(ring,
7315 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7316 obj->tiling_mode);
8c9f3aaf
JB		 7317
7318 /* XXX Enabling the panel-fitter across page-flip is so far
7319 * untested on non-native modes, so ignore it for now.
7320 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7321 */
7322 pf = 0;
7323 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7324 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7325
7326 intel_mark_page_flip_active(intel_crtc);
6d90c952 7327 intel_ring_advance(ring);
83d4092b
CW		 7328 return 0;
7329
7330err_unpin:
7331 intel_unpin_fb_obj(obj);
7332err:
8c9f3aaf
JB		 7333 return ret;
7334}
7335
7336static int intel_gen6_queue_flip(struct drm_device *dev,
7337 struct drm_crtc *crtc,
7338 struct drm_framebuffer *fb,
7339 struct drm_i915_gem_object *obj)
7340{
7341 struct drm_i915_private *dev_priv = dev->dev_private;
7342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7343 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7344 uint32_t pf, pipesrc;
7345 int ret;
7346
6d90c952 7347 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7348 if (ret)
83d4092b 7349 goto err;
8c9f3aaf 7350
6d90c952 7351 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7352 if (ret)
83d4092b 7353 goto err_unpin;
8c9f3aaf 7354
6d90c952
DV		 7355 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7356 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7357 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7358 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7359
dc257cf1
DV		 7360 /* Contrary to the suggestions in the documentation,
7361 * "Enable Panel Fitter" does not seem to be required when page
7362 * flipping with a non-native mode, and worse causes a normal
7363 * modeset to fail.
7364 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7365 */
7366 pf = 0;
8c9f3aaf 7367 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7368 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7369
7370 intel_mark_page_flip_active(intel_crtc);
6d90c952 7371 intel_ring_advance(ring);
83d4092b
CW		 7372 return 0;
7373
7374err_unpin:
7375 intel_unpin_fb_obj(obj);
7376err:
8c9f3aaf
JB		 7377 return ret;
7378}
7379
7c9017e5
JB		 7380/*
7381 * On gen7 we currently use the blit ring because (in early silicon at least)
7382 * the render ring doesn't give us interrpts for page flip completion, which
7383 * means clients will hang after the first flip is queued. Fortunately the
7384 * blit ring generates interrupts properly, so use it instead.
7385 */
7386static int intel_gen7_queue_flip(struct drm_device *dev,
7387 struct drm_crtc *crtc,
7388 struct drm_framebuffer *fb,
7389 struct drm_i915_gem_object *obj)
7390{
7391 struct drm_i915_private *dev_priv = dev->dev_private;
7392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7393 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7394 uint32_t plane_bit = 0;
7c9017e5
JB		 7395 int ret;
7396
7397 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7398 if (ret)
83d4092b 7399 goto err;
7c9017e5 7400
cb05d8de
DV		 7401 switch(intel_crtc->plane) {
7402 case PLANE_A:
7403 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7404 break;
7405 case PLANE_B:
7406 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7407 break;
7408 case PLANE_C:
7409 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7410 break;
7411 default:
7412 WARN_ONCE(1, "unknown plane in flip command\n");
7413 ret = -ENODEV;
ab3951eb 7414 goto err_unpin;
cb05d8de
DV		 7415 }
7416
7c9017e5
JB		 7417 ret = intel_ring_begin(ring, 4);
7418 if (ret)
83d4092b 7419 goto err_unpin;
7c9017e5 7420
cb05d8de 7421 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7422 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7423 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7424 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7425
7426 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7427 intel_ring_advance(ring);
83d4092b
CW		 7428 return 0;
7429
7430err_unpin:
7431 intel_unpin_fb_obj(obj);
7432err:
7c9017e5
JB		 7433 return ret;
7434}
7435
8c9f3aaf
JB		 7436static int intel_default_queue_flip(struct drm_device *dev,
7437 struct drm_crtc *crtc,
7438 struct drm_framebuffer *fb,
7439 struct drm_i915_gem_object *obj)
7440{
7441 return -ENODEV;
7442}
7443
6b95a207
KH		 7444static int intel_crtc_page_flip(struct drm_crtc *crtc,
7445 struct drm_framebuffer *fb,
7446 struct drm_pending_vblank_event *event)
7447{
7448 struct drm_device *dev = crtc->dev;
7449 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7450 struct drm_framebuffer *old_fb = crtc->fb;
7451 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453 struct intel_unpin_work *work;
8c9f3aaf 7454 unsigned long flags;
52e68630 7455 int ret;
6b95a207 7456
e6a595d2
VS		 7457 /* Can't change pixel format via MI display flips. */
7458 if (fb->pixel_format != crtc->fb->pixel_format)
7459 return -EINVAL;
7460
7461 /*
7462 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7463 * Note that pitch changes could also affect these register.
7464 */
7465 if (INTEL_INFO(dev)->gen > 3 &&
7466 (fb->offsets[0] != crtc->fb->offsets[0] ||
7467 fb->pitches[0] != crtc->fb->pitches[0]))
7468 return -EINVAL;
7469
6b95a207
KH		 7470 work = kzalloc(sizeof *work, GFP_KERNEL);
7471 if (work == NULL)
7472 return -ENOMEM;
7473
6b95a207 7474 work->event = event;
b4a98e57 7475 work->crtc = crtc;
4a35f83b 7476 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7477 INIT_WORK(&work->work, intel_unpin_work_fn);
7478
7317c75e
JB		 7479 ret = drm_vblank_get(dev, intel_crtc->pipe);
7480 if (ret)
7481 goto free_work;
7482
6b95a207
KH		 7483 /* We borrow the event spin lock for protecting unpin_work */
7484 spin_lock_irqsave(&dev->event_lock, flags);
7485 if (intel_crtc->unpin_work) {
7486 spin_unlock_irqrestore(&dev->event_lock, flags);
7487 kfree(work);
7317c75e 7488 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7489
7490 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7491 return -EBUSY;
7492 }
7493 intel_crtc->unpin_work = work;
7494 spin_unlock_irqrestore(&dev->event_lock, flags);
7495
b4a98e57
CW		 7496 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7497 flush_workqueue(dev_priv->wq);
7498
79158103
CW		 7499 ret = i915_mutex_lock_interruptible(dev);
7500 if (ret)
7501 goto cleanup;
6b95a207 7502
75dfca80 7503 /* Reference the objects for the scheduled work. */
05394f39
CW		 7504 drm_gem_object_reference(&work->old_fb_obj->base);
7505 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7506
7507 crtc->fb = fb;
96b099fd 7508
e1f99ce6 7509 work->pending_flip_obj = obj;
e1f99ce6 7510
4e5359cd
SF		 7511 work->enable_stall_check = true;
7512
b4a98e57 7513 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7514 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7515
8c9f3aaf
JB		 7516 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7517 if (ret)
7518 goto cleanup_pending;
6b95a207 7519
7782de3b 7520 intel_disable_fbc(dev);
f047e395 7521 intel_mark_fb_busy(obj);
6b95a207
KH		 7522 mutex_unlock(&dev->struct_mutex);
7523
e5510fac
JB		 7524 trace_i915_flip_request(intel_crtc->plane, obj);
7525
6b95a207 7526 return 0;
96b099fd 7527
8c9f3aaf 7528cleanup_pending:
b4a98e57 7529 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7530 crtc->fb = old_fb;
05394f39
CW		 7531 drm_gem_object_unreference(&work->old_fb_obj->base);
7532 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7533 mutex_unlock(&dev->struct_mutex);
7534
79158103 7535cleanup:
96b099fd
CW		 7536 spin_lock_irqsave(&dev->event_lock, flags);
7537 intel_crtc->unpin_work = NULL;
7538 spin_unlock_irqrestore(&dev->event_lock, flags);
7539
7317c75e
JB		 7540 drm_vblank_put(dev, intel_crtc->pipe);
7541free_work:
96b099fd
CW		 7542 kfree(work);
7543
7544 return ret;
6b95a207
KH		 7545}
7546
f6e5b160 7547static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7548 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7549 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7550};
7551
6ed0f796 7552bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7553{
6ed0f796
DV		 7554 struct intel_encoder *other_encoder;
7555 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7556
6ed0f796
DV		 7557 if (WARN_ON(!crtc))
7558 return false;
7559
7560 list_for_each_entry(other_encoder,
7561 &crtc->dev->mode_config.encoder_list,
7562 base.head) {
7563
7564 if (&other_encoder->new_crtc->base != crtc ||
7565 encoder == other_encoder)
7566 continue;
7567 else
7568 return true;
f47166d2
CW		 7569 }
7570
6ed0f796
DV		 7571 return false;
7572}
47f1c6c9 7573
50f56119
DV		 7574static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7575 struct drm_crtc *crtc)
7576{
7577 struct drm_device *dev;
7578 struct drm_crtc *tmp;
7579 int crtc_mask = 1;
47f1c6c9 7580
50f56119 7581 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7582
50f56119 7583 dev = crtc->dev;
47f1c6c9 7584
50f56119
DV		 7585 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7586 if (tmp == crtc)
7587 break;
7588 crtc_mask <<= 1;
7589 }
47f1c6c9 7590
50f56119
DV		 7591 if (encoder->possible_crtcs & crtc_mask)
7592 return true;
7593 return false;
47f1c6c9 7594}
79e53945 7595
9a935856
DV		 7596/**
7597 * intel_modeset_update_staged_output_state
7598 *
7599 * Updates the staged output configuration state, e.g. after we've read out the
7600 * current hw state.
7601 */
7602static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7603{
9a935856
DV		 7604 struct intel_encoder *encoder;
7605 struct intel_connector *connector;
f6e5b160 7606
9a935856
DV		 7607 list_for_each_entry(connector, &dev->mode_config.connector_list,
7608 base.head) {
7609 connector->new_encoder =
7610 to_intel_encoder(connector->base.encoder);
7611 }
f6e5b160 7612
9a935856
DV		 7613 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7614 base.head) {
7615 encoder->new_crtc =
7616 to_intel_crtc(encoder->base.crtc);
7617 }
f6e5b160
CW		 7618}
7619
9a935856
DV		 7620/**
7621 * intel_modeset_commit_output_state
7622 *
7623 * This function copies the stage display pipe configuration to the real one.
7624 */
7625static void intel_modeset_commit_output_state(struct drm_device *dev)
7626{
7627 struct intel_encoder *encoder;
7628 struct intel_connector *connector;
f6e5b160 7629
9a935856
DV		 7630 list_for_each_entry(connector, &dev->mode_config.connector_list,
7631 base.head) {
7632 connector->base.encoder = &connector->new_encoder->base;
7633 }
f6e5b160 7634
9a935856
DV		 7635 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7636 base.head) {
7637 encoder->base.crtc = &encoder->new_crtc->base;
7638 }
7639}
7640
4e53c2e0
DV		 7641static int
7642pipe_config_set_bpp(struct drm_crtc *crtc,
7643 struct drm_framebuffer *fb,
7644 struct intel_crtc_config *pipe_config)
7645{
7646 struct drm_device *dev = crtc->dev;
7647 struct drm_connector *connector;
7648 int bpp;
7649
d42264b1
DV		 7650 switch (fb->pixel_format) {
7651 case DRM_FORMAT_C8:
4e53c2e0
DV		 7652 bpp = 8*3; /* since we go through a colormap */
7653 break;
d42264b1
DV		 7654 case DRM_FORMAT_XRGB1555:
7655 case DRM_FORMAT_ARGB1555:
7656 /* checked in intel_framebuffer_init already */
7657 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7658 return -EINVAL;
7659 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7660 bpp = 6*3; /* min is 18bpp */
7661 break;
d42264b1
DV		 7662 case DRM_FORMAT_XBGR8888:
7663 case DRM_FORMAT_ABGR8888:
7664 /* checked in intel_framebuffer_init already */
7665 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7666 return -EINVAL;
7667 case DRM_FORMAT_XRGB8888:
7668 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7669 bpp = 8*3;
7670 break;
d42264b1
DV		 7671 case DRM_FORMAT_XRGB2101010:
7672 case DRM_FORMAT_ARGB2101010:
7673 case DRM_FORMAT_XBGR2101010:
7674 case DRM_FORMAT_ABGR2101010:
7675 /* checked in intel_framebuffer_init already */
7676 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7677 return -EINVAL;
4e53c2e0
DV		 7678 bpp = 10*3;
7679 break;
baba133a 7680 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7681 default:
7682 DRM_DEBUG_KMS("unsupported depth\n");
7683 return -EINVAL;
7684 }
7685
4e53c2e0
DV		 7686 pipe_config->pipe_bpp = bpp;
7687
7688 /* Clamp display bpp to EDID value */
7689 list_for_each_entry(connector, &dev->mode_config.connector_list,
7690 head) {
7691 if (connector->encoder && connector->encoder->crtc != crtc)
7692 continue;
7693
7694 /* Don't use an invalid EDID bpc value */
7695 if (connector->display_info.bpc &&
7696 connector->display_info.bpc * 3 < bpp) {
7697 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7698 bpp, connector->display_info.bpc*3);
7699 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7700 }
996a2239
DV		 7701
7702 /* Clamp bpp to 8 on screens without EDID 1.4 */
7703 if (connector->display_info.bpc == 0 && bpp > 24) {
7704 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7705 bpp);
7706 pipe_config->pipe_bpp = 24;
7707 }
4e53c2e0
DV		 7708 }
7709
7710 return bpp;
7711}
7712
b8cecdf5
DV		 7713static struct intel_crtc_config *
7714intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7715 struct drm_framebuffer *fb,
b8cecdf5 7716 struct drm_display_mode *mode)
ee7b9f93 7717{
7758a113 7718 struct drm_device *dev = crtc->dev;
7758a113
DV		 7719 struct drm_encoder_helper_funcs *encoder_funcs;
7720 struct intel_encoder *encoder;
b8cecdf5 7721 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7722 int plane_bpp, ret = -EINVAL;
7723 bool retry = true;
ee7b9f93 7724
b8cecdf5
DV		 7725 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7726 if (!pipe_config)
7758a113
DV		 7727 return ERR_PTR(-ENOMEM);
7728
b8cecdf5
DV		 7729 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7730 drm_mode_copy(&pipe_config->requested_mode, mode);
7731
4e53c2e0
DV		 7732 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7733 if (plane_bpp < 0)
7734 goto fail;
7735
e29c22c0 7736encoder_retry:
7758a113
DV		 7737 /* Pass our mode to the connectors and the CRTC to give them a chance to
7738 * adjust it according to limitations or connector properties, and also
7739 * a chance to reject the mode entirely.
47f1c6c9 7740 */
7758a113
DV		 7741 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7742 base.head) {
47f1c6c9 7743
7758a113
DV		 7744 if (&encoder->new_crtc->base != crtc)
7745 continue;
7ae89233
DV		 7746
7747 if (encoder->compute_config) {
7748 if (!(encoder->compute_config(encoder, pipe_config))) {
7749 DRM_DEBUG_KMS("Encoder config failure\n");
7750 goto fail;
7751 }
7752
7753 continue;
7754 }
7755
7758a113 7756 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7757 if (!(encoder_funcs->mode_fixup(&encoder->base,
7758 &pipe_config->requested_mode,
7759 &pipe_config->adjusted_mode))) {
7758a113
DV		 7760 DRM_DEBUG_KMS("Encoder fixup failed\n");
7761 goto fail;
7762 }
ee7b9f93 7763 }
47f1c6c9 7764
e29c22c0
DV		 7765 ret = intel_crtc_compute_config(crtc, pipe_config);
7766 if (ret < 0) {
7758a113
DV		 7767 DRM_DEBUG_KMS("CRTC fixup failed\n");
7768 goto fail;
ee7b9f93 7769 }
e29c22c0
DV		 7770
7771 if (ret == RETRY) {
7772 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7773 ret = -EINVAL;
7774 goto fail;
7775 }
7776
7777 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7778 retry = false;
7779 goto encoder_retry;
7780 }
7781
7758a113 7782 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7783
4e53c2e0
DV		 7784 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7785 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7786 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7787
b8cecdf5 7788 return pipe_config;
7758a113 7789fail:
b8cecdf5 7790 kfree(pipe_config);
e29c22c0 7791 return ERR_PTR(ret);
ee7b9f93 7792}
47f1c6c9 7793
e2e1ed41
DV		 7794/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7795 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7796static void
7797intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7798 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7799{
7800 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7801 struct drm_device *dev = crtc->dev;
7802 struct intel_encoder *encoder;
7803 struct intel_connector *connector;
7804 struct drm_crtc *tmp_crtc;
79e53945 7805
e2e1ed41 7806 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7807
e2e1ed41
DV		 7808 /* Check which crtcs have changed outputs connected to them, these need
7809 * to be part of the prepare_pipes mask. We don't (yet) support global
7810 * modeset across multiple crtcs, so modeset_pipes will only have one
7811 * bit set at most. */
7812 list_for_each_entry(connector, &dev->mode_config.connector_list,
7813 base.head) {
7814 if (connector->base.encoder == &connector->new_encoder->base)
7815 continue;
79e53945 7816
e2e1ed41
DV		 7817 if (connector->base.encoder) {
7818 tmp_crtc = connector->base.encoder->crtc;
7819
7820 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7821 }
7822
7823 if (connector->new_encoder)
7824 *prepare_pipes |=
7825 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7826 }
7827
e2e1ed41
DV		 7828 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7829 base.head) {
7830 if (encoder->base.crtc == &encoder->new_crtc->base)
7831 continue;
7832
7833 if (encoder->base.crtc) {
7834 tmp_crtc = encoder->base.crtc;
7835
7836 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7837 }
7838
7839 if (encoder->new_crtc)
7840 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7841 }
7842
e2e1ed41
DV		 7843 /* Check for any pipes that will be fully disabled ... */
7844 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7845 base.head) {
7846 bool used = false;
22fd0fab 7847
e2e1ed41
DV		 7848 /* Don't try to disable disabled crtcs. */
7849 if (!intel_crtc->base.enabled)
7850 continue;
7e7d76c3 7851
e2e1ed41
DV		 7852 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7853 base.head) {
7854 if (encoder->new_crtc == intel_crtc)
7855 used = true;
7856 }
7857
7858 if (!used)
7859 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7860 }
7861
e2e1ed41
DV		 7862
7863 /* set_mode is also used to update properties on life display pipes. */
7864 intel_crtc = to_intel_crtc(crtc);
7865 if (crtc->enabled)
7866 *prepare_pipes |= 1 << intel_crtc->pipe;
7867
b6c5164d
DV		 7868 /*
7869 * For simplicity do a full modeset on any pipe where the output routing
7870 * changed. We could be more clever, but that would require us to be
7871 * more careful with calling the relevant encoder->mode_set functions.
7872 */
e2e1ed41
DV		 7873 if (*prepare_pipes)
7874 *modeset_pipes = *prepare_pipes;
7875
7876 /* ... and mask these out. */
7877 *modeset_pipes &= ~(*disable_pipes);
7878 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7879
7880 /*
7881 * HACK: We don't (yet) fully support global modesets. intel_set_config
7882 * obies this rule, but the modeset restore mode of
7883 * intel_modeset_setup_hw_state does not.
7884 */
7885 *modeset_pipes &= 1 << intel_crtc->pipe;
7886 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7887
7888 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7889 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7890}
79e53945 7891
ea9d758d 7892static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7893{
ea9d758d 7894 struct drm_encoder *encoder;
f6e5b160 7895 struct drm_device *dev = crtc->dev;
f6e5b160 7896
ea9d758d
DV		 7897 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7898 if (encoder->crtc == crtc)
7899 return true;
7900
7901 return false;
7902}
7903
7904static void
7905intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7906{
7907 struct intel_encoder *intel_encoder;
7908 struct intel_crtc *intel_crtc;
7909 struct drm_connector *connector;
7910
7911 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7912 base.head) {
7913 if (!intel_encoder->base.crtc)
7914 continue;
7915
7916 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7917
7918 if (prepare_pipes & (1 << intel_crtc->pipe))
7919 intel_encoder->connectors_active = false;
7920 }
7921
7922 intel_modeset_commit_output_state(dev);
7923
7924 /* Update computed state. */
7925 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7926 base.head) {
7927 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7928 }
7929
7930 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7931 if (!connector->encoder || !connector->encoder->crtc)
7932 continue;
7933
7934 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7935
7936 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7937 struct drm_property *dpms_property =
7938 dev->mode_config.dpms_property;
7939
ea9d758d 7940 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7941 drm_object_property_set_value(&connector->base,
68d34720
DV		 7942 dpms_property,
7943 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7944
7945 intel_encoder = to_intel_encoder(connector->encoder);
7946 intel_encoder->connectors_active = true;
7947 }
7948 }
7949
7950}
7951
25c5b266
DV		 7952#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7953 list_for_each_entry((intel_crtc), \
7954 &(dev)->mode_config.crtc_list, \
7955 base.head) \
0973f18f 7956 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 7957
0e8ffe1b
DV		 7958static bool
7959intel_pipe_config_compare(struct intel_crtc_config *current_config,
7960 struct intel_crtc_config *pipe_config)
7961{
08a24034
DV		 7962#define PIPE_CONF_CHECK_I(name) \
7963 if (current_config->name != pipe_config->name) { \
7964 DRM_ERROR("mismatch in " #name " " \
7965 "(expected %i, found %i)\n", \
7966 current_config->name, \
7967 pipe_config->name); \
7968 return false; \
88adfff1
DV		 7969 }
7970
1bd1bd80
DV		 7971#define PIPE_CONF_CHECK_FLAGS(name, mask) \
7972 if ((current_config->name ^ pipe_config->name) & (mask)) { \
7973 DRM_ERROR("mismatch in " #name " " \
7974 "(expected %i, found %i)\n", \
7975 current_config->name & (mask), \
7976 pipe_config->name & (mask)); \
7977 return false; \
7978 }
7979
08a24034
DV		 7980 PIPE_CONF_CHECK_I(has_pch_encoder);
7981 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 7982 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
7983 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
7984 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
7985 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
7986 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 7987
1bd1bd80
DV		 7988 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
7989 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
7990 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
7991 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
7992 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
7993 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
7994
7995 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
7996 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
7997 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
7998 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
7999 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8000 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8001
8002 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8003 DRM_MODE_FLAG_INTERLACE);
8004
8005 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8006 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8007
08a24034 8008#undef PIPE_CONF_CHECK_I
1bd1bd80 8009#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8010
0e8ffe1b
DV		 8011 return true;
8012}
8013
b980514c 8014void
8af6cf88
DV		 8015intel_modeset_check_state(struct drm_device *dev)
8016{
0e8ffe1b 8017 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8018 struct intel_crtc *crtc;
8019 struct intel_encoder *encoder;
8020 struct intel_connector *connector;
0e8ffe1b 8021 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8022
8023 list_for_each_entry(connector, &dev->mode_config.connector_list,
8024 base.head) {
8025 /* This also checks the encoder/connector hw state with the
8026 * ->get_hw_state callbacks. */
8027 intel_connector_check_state(connector);
8028
8029 WARN(&connector->new_encoder->base != connector->base.encoder,
8030 "connector's staged encoder doesn't match current encoder\n");
8031 }
8032
8033 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8034 base.head) {
8035 bool enabled = false;
8036 bool active = false;
8037 enum pipe pipe, tracked_pipe;
8038
8039 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8040 encoder->base.base.id,
8041 drm_get_encoder_name(&encoder->base));
8042
8043 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8044 "encoder's stage crtc doesn't match current crtc\n");
8045 WARN(encoder->connectors_active && !encoder->base.crtc,
8046 "encoder's active_connectors set, but no crtc\n");
8047
8048 list_for_each_entry(connector, &dev->mode_config.connector_list,
8049 base.head) {
8050 if (connector->base.encoder != &encoder->base)
8051 continue;
8052 enabled = true;
8053 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8054 active = true;
8055 }
8056 WARN(!!encoder->base.crtc != enabled,
8057 "encoder's enabled state mismatch "
8058 "(expected %i, found %i)\n",
8059 !!encoder->base.crtc, enabled);
8060 WARN(active && !encoder->base.crtc,
8061 "active encoder with no crtc\n");
8062
8063 WARN(encoder->connectors_active != active,
8064 "encoder's computed active state doesn't match tracked active state "
8065 "(expected %i, found %i)\n", active, encoder->connectors_active);
8066
8067 active = encoder->get_hw_state(encoder, &pipe);
8068 WARN(active != encoder->connectors_active,
8069 "encoder's hw state doesn't match sw tracking "
8070 "(expected %i, found %i)\n",
8071 encoder->connectors_active, active);
8072
8073 if (!encoder->base.crtc)
8074 continue;
8075
8076 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8077 WARN(active && pipe != tracked_pipe,
8078 "active encoder's pipe doesn't match"
8079 "(expected %i, found %i)\n",
8080 tracked_pipe, pipe);
8081
8082 }
8083
8084 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8085 base.head) {
8086 bool enabled = false;
8087 bool active = false;
8088
8089 DRM_DEBUG_KMS("[CRTC:%d]\n",
8090 crtc->base.base.id);
8091
8092 WARN(crtc->active && !crtc->base.enabled,
8093 "active crtc, but not enabled in sw tracking\n");
8094
8095 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8096 base.head) {
8097 if (encoder->base.crtc != &crtc->base)
8098 continue;
8099 enabled = true;
8100 if (encoder->connectors_active)
8101 active = true;
8102 }
8103 WARN(active != crtc->active,
8104 "crtc's computed active state doesn't match tracked active state "
8105 "(expected %i, found %i)\n", active, crtc->active);
8106 WARN(enabled != crtc->base.enabled,
8107 "crtc's computed enabled state doesn't match tracked enabled state "
8108 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8109
88adfff1 8110 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 8111 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 8112 active = dev_priv->display.get_pipe_config(crtc,
8113 &pipe_config);
8114 WARN(crtc->active != active,
8115 "crtc active state doesn't match with hw state "
8116 "(expected %i, found %i)\n", crtc->active, active);
8117
8118 WARN(active &&
8119 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8120 "pipe state doesn't match!\n");
8af6cf88
DV		 8121 }
8122}
8123
f30da187
DV		 8124static int __intel_set_mode(struct drm_crtc *crtc,
8125 struct drm_display_mode *mode,
8126 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8127{
8128 struct drm_device *dev = crtc->dev;
dbf2b54e 8129 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8130 struct drm_display_mode *saved_mode, *saved_hwmode;
8131 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8132 struct intel_crtc *intel_crtc;
8133 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8134 int ret = 0;
a6778b3c 8135
3ac18232 8136 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8137 if (!saved_mode)
8138 return -ENOMEM;
3ac18232 8139 saved_hwmode = saved_mode + 1;
a6778b3c 8140
e2e1ed41 8141 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8142 &prepare_pipes, &disable_pipes);
8143
3ac18232
TG		 8144 *saved_hwmode = crtc->hwmode;
8145 *saved_mode = crtc->mode;
a6778b3c 8146
25c5b266
DV		 8147 /* Hack: Because we don't (yet) support global modeset on multiple
8148 * crtcs, we don't keep track of the new mode for more than one crtc.
8149 * Hence simply check whether any bit is set in modeset_pipes in all the
8150 * pieces of code that are not yet converted to deal with mutliple crtcs
8151 * changing their mode at the same time. */
25c5b266 8152 if (modeset_pipes) {
4e53c2e0 8153 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8154 if (IS_ERR(pipe_config)) {
8155 ret = PTR_ERR(pipe_config);
8156 pipe_config = NULL;
8157
3ac18232 8158 goto out;
25c5b266 8159 }
25c5b266 8160 }
a6778b3c 8161
460da916
DV		 8162 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8163 intel_crtc_disable(&intel_crtc->base);
8164
ea9d758d
DV		 8165 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8166 if (intel_crtc->base.enabled)
8167 dev_priv->display.crtc_disable(&intel_crtc->base);
8168 }
a6778b3c 8169
6c4c86f5
DV		 8170 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8171 * to set it here already despite that we pass it down the callchain.
f6e5b160 8172 */
b8cecdf5 8173 if (modeset_pipes) {
3b117c8f 8174 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8175 crtc->mode = *mode;
b8cecdf5
DV		 8176 /* mode_set/enable/disable functions rely on a correct pipe
8177 * config. */
8178 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8179 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8180 }
7758a113 8181
ea9d758d
DV		 8182 /* Only after disabling all output pipelines that will be changed can we
8183 * update the the output configuration. */
8184 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8185
47fab737
DV		 8186 if (dev_priv->display.modeset_global_resources)
8187 dev_priv->display.modeset_global_resources(dev);
8188
a6778b3c
DV		 8189 /* Set up the DPLL and any encoders state that needs to adjust or depend
8190 * on the DPLL.
f6e5b160 8191 */
25c5b266 8192 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8193 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8194 x, y, fb);
8195 if (ret)
8196 goto done;
a6778b3c
DV		 8197 }
8198
8199 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8200 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8201 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8202
25c5b266
DV		 8203 if (modeset_pipes) {
8204 /* Store real post-adjustment hardware mode. */
b8cecdf5 8205 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8206
25c5b266
DV		 8207 /* Calculate and store various constants which
8208 * are later needed by vblank and swap-completion
8209 * timestamping. They are derived from true hwmode.
8210 */
8211 drm_calc_timestamping_constants(crtc);
8212 }
a6778b3c
DV		 8213
8214 /* FIXME: add subpixel order */
8215done:
c0c36b94 8216 if (ret && crtc->enabled) {
3ac18232
TG		 8217 crtc->hwmode = *saved_hwmode;
8218 crtc->mode = *saved_mode;
a6778b3c
DV		 8219 }
8220
3ac18232 8221out:
b8cecdf5 8222 kfree(pipe_config);
3ac18232 8223 kfree(saved_mode);
a6778b3c 8224 return ret;
f6e5b160
CW		 8225}
8226
f30da187
DV		 8227int intel_set_mode(struct drm_crtc *crtc,
8228 struct drm_display_mode *mode,
8229 int x, int y, struct drm_framebuffer *fb)
8230{
8231 int ret;
8232
8233 ret = __intel_set_mode(crtc, mode, x, y, fb);
8234
8235 if (ret == 0)
8236 intel_modeset_check_state(crtc->dev);
8237
8238 return ret;
8239}
8240
c0c36b94
CW		 8241void intel_crtc_restore_mode(struct drm_crtc *crtc)
8242{
8243 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8244}
8245
25c5b266
DV		 8246#undef for_each_intel_crtc_masked
8247
d9e55608
DV		 8248static void intel_set_config_free(struct intel_set_config *config)
8249{
8250 if (!config)
8251 return;
8252
1aa4b628
DV		 8253 kfree(config->save_connector_encoders);
8254 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8255 kfree(config);
8256}
8257
85f9eb71
DV		 8258static int intel_set_config_save_state(struct drm_device *dev,
8259 struct intel_set_config *config)
8260{
85f9eb71
DV		 8261 struct drm_encoder *encoder;
8262 struct drm_connector *connector;
8263 int count;
8264
1aa4b628
DV		 8265 config->save_encoder_crtcs =
8266 kcalloc(dev->mode_config.num_encoder,
8267 sizeof(struct drm_crtc *), GFP_KERNEL);
8268 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8269 return -ENOMEM;
8270
1aa4b628
DV		 8271 config->save_connector_encoders =
8272 kcalloc(dev->mode_config.num_connector,
8273 sizeof(struct drm_encoder *), GFP_KERNEL);
8274 if (!config->save_connector_encoders)
85f9eb71
DV		 8275 return -ENOMEM;
8276
8277 /* Copy data. Note that driver private data is not affected.
8278 * Should anything bad happen only the expected state is
8279 * restored, not the drivers personal bookkeeping.
8280 */
85f9eb71
DV		 8281 count = 0;
8282 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8283 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8284 }
8285
8286 count = 0;
8287 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8288 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8289 }
8290
8291 return 0;
8292}
8293
8294static void intel_set_config_restore_state(struct drm_device *dev,
8295 struct intel_set_config *config)
8296{
9a935856
DV		 8297 struct intel_encoder *encoder;
8298 struct intel_connector *connector;
85f9eb71
DV		 8299 int count;
8300
85f9eb71 8301 count = 0;
9a935856
DV		 8302 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8303 encoder->new_crtc =
8304 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8305 }
8306
8307 count = 0;
9a935856
DV		 8308 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8309 connector->new_encoder =
8310 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8311 }
8312}
8313
5e2b584e
DV		 8314static void
8315intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8316 struct intel_set_config *config)
8317{
8318
8319 /* We should be able to check here if the fb has the same properties
8320 * and then just flip_or_move it */
8321 if (set->crtc->fb != set->fb) {
8322 /* If we have no fb then treat it as a full mode set */
8323 if (set->crtc->fb == NULL) {
8324 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8325 config->mode_changed = true;
8326 } else if (set->fb == NULL) {
8327 config->mode_changed = true;
72f4901e
DV		 8328 } else if (set->fb->pixel_format !=
8329 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8330 config->mode_changed = true;
8331 } else
8332 config->fb_changed = true;
8333 }
8334
835c5873 8335 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8336 config->fb_changed = true;
8337
8338 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8339 DRM_DEBUG_KMS("modes are different, full mode set\n");
8340 drm_mode_debug_printmodeline(&set->crtc->mode);
8341 drm_mode_debug_printmodeline(set->mode);
8342 config->mode_changed = true;
8343 }
8344}
8345
2e431051 8346static int
9a935856
DV		 8347intel_modeset_stage_output_state(struct drm_device *dev,
8348 struct drm_mode_set *set,
8349 struct intel_set_config *config)
50f56119 8350{
85f9eb71 8351 struct drm_crtc *new_crtc;
9a935856
DV		 8352 struct intel_connector *connector;
8353 struct intel_encoder *encoder;
2e431051 8354 int count, ro;
50f56119 8355
9abdda74 8356 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8357 * of connectors. For paranoia, double-check this. */
8358 WARN_ON(!set->fb && (set->num_connectors != 0));
8359 WARN_ON(set->fb && (set->num_connectors == 0));
8360
50f56119 8361 count = 0;
9a935856
DV		 8362 list_for_each_entry(connector, &dev->mode_config.connector_list,
8363 base.head) {
8364 /* Otherwise traverse passed in connector list and get encoders
8365 * for them. */
50f56119 8366 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8367 if (set->connectors[ro] == &connector->base) {
8368 connector->new_encoder = connector->encoder;
50f56119
DV		 8369 break;
8370 }
8371 }
8372
9a935856
DV		 8373 /* If we disable the crtc, disable all its connectors. Also, if
8374 * the connector is on the changing crtc but not on the new
8375 * connector list, disable it. */
8376 if ((!set->fb || ro == set->num_connectors) &&
8377 connector->base.encoder &&
8378 connector->base.encoder->crtc == set->crtc) {
8379 connector->new_encoder = NULL;
8380
8381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8382 connector->base.base.id,
8383 drm_get_connector_name(&connector->base));
8384 }
8385
8386
8387 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8388 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8389 config->mode_changed = true;
50f56119
DV		 8390 }
8391 }
9a935856 8392 /* connector->new_encoder is now updated for all connectors. */
50f56119 8393
9a935856 8394 /* Update crtc of enabled connectors. */
50f56119 8395 count = 0;
9a935856
DV		 8396 list_for_each_entry(connector, &dev->mode_config.connector_list,
8397 base.head) {
8398 if (!connector->new_encoder)
50f56119
DV		 8399 continue;
8400
9a935856 8401 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8402
8403 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8404 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8405 new_crtc = set->crtc;
8406 }
8407
8408 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8409 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8410 new_crtc)) {
5e2b584e 8411 return -EINVAL;
50f56119 8412 }
9a935856
DV		 8413 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8414
8415 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8416 connector->base.base.id,
8417 drm_get_connector_name(&connector->base),
8418 new_crtc->base.id);
8419 }
8420
8421 /* Check for any encoders that needs to be disabled. */
8422 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8423 base.head) {
8424 list_for_each_entry(connector,
8425 &dev->mode_config.connector_list,
8426 base.head) {
8427 if (connector->new_encoder == encoder) {
8428 WARN_ON(!connector->new_encoder->new_crtc);
8429
8430 goto next_encoder;
8431 }
8432 }
8433 encoder->new_crtc = NULL;
8434next_encoder:
8435 /* Only now check for crtc changes so we don't miss encoders
8436 * that will be disabled. */
8437 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8438 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8439 config->mode_changed = true;
50f56119
DV		 8440 }
8441 }
9a935856 8442 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8443
2e431051
DV		 8444 return 0;
8445}
8446
8447static int intel_crtc_set_config(struct drm_mode_set *set)
8448{
8449 struct drm_device *dev;
2e431051
DV		 8450 struct drm_mode_set save_set;
8451 struct intel_set_config *config;
8452 int ret;
2e431051 8453
8d3e375e
DV		 8454 BUG_ON(!set);
8455 BUG_ON(!set->crtc);
8456 BUG_ON(!set->crtc->helper_private);
2e431051 8457
7e53f3a4
DV		 8458 /* Enforce sane interface api - has been abused by the fb helper. */
8459 BUG_ON(!set->mode && set->fb);
8460 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8461
2e431051
DV		 8462 if (set->fb) {
8463 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8464 set->crtc->base.id, set->fb->base.id,
8465 (int)set->num_connectors, set->x, set->y);
8466 } else {
8467 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8468 }
8469
8470 dev = set->crtc->dev;
8471
8472 ret = -ENOMEM;
8473 config = kzalloc(sizeof(*config), GFP_KERNEL);
8474 if (!config)
8475 goto out_config;
8476
8477 ret = intel_set_config_save_state(dev, config);
8478 if (ret)
8479 goto out_config;
8480
8481 save_set.crtc = set->crtc;
8482 save_set.mode = &set->crtc->mode;
8483 save_set.x = set->crtc->x;
8484 save_set.y = set->crtc->y;
8485 save_set.fb = set->crtc->fb;
8486
8487 /* Compute whether we need a full modeset, only an fb base update or no
8488 * change at all. In the future we might also check whether only the
8489 * mode changed, e.g. for LVDS where we only change the panel fitter in
8490 * such cases. */
8491 intel_set_config_compute_mode_changes(set, config);
8492
9a935856 8493 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8494 if (ret)
8495 goto fail;
8496
5e2b584e 8497 if (config->mode_changed) {
87f1faa6 8498 if (set->mode) {
50f56119
DV		 8499 DRM_DEBUG_KMS("attempting to set mode from"
8500 " userspace\n");
8501 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8502 }
8503
c0c36b94
CW		 8504 ret = intel_set_mode(set->crtc, set->mode,
8505 set->x, set->y, set->fb);
8506 if (ret) {
8507 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8508 set->crtc->base.id, ret);
87f1faa6
DV		 8509 goto fail;
8510 }
5e2b584e 8511 } else if (config->fb_changed) {
4878cae2
VS		 8512 intel_crtc_wait_for_pending_flips(set->crtc);
8513
4f660f49 8514 ret = intel_pipe_set_base(set->crtc,
94352cf9 8515 set->x, set->y, set->fb);
50f56119
DV		 8516 }
8517
d9e55608
DV		 8518 intel_set_config_free(config);
8519
50f56119
DV		 8520 return 0;
8521
8522fail:
85f9eb71 8523 intel_set_config_restore_state(dev, config);
50f56119
DV		 8524
8525 /* Try to restore the config */
5e2b584e 8526 if (config->mode_changed &&
c0c36b94
CW		 8527 intel_set_mode(save_set.crtc, save_set.mode,
8528 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8529 DRM_ERROR("failed to restore config after modeset failure\n");
8530
d9e55608
DV		 8531out_config:
8532 intel_set_config_free(config);
50f56119
DV		 8533 return ret;
8534}
f6e5b160
CW		 8535
8536static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8537 .cursor_set = intel_crtc_cursor_set,
8538 .cursor_move = intel_crtc_cursor_move,
8539 .gamma_set = intel_crtc_gamma_set,
50f56119 8540 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8541 .destroy = intel_crtc_destroy,
8542 .page_flip = intel_crtc_page_flip,
8543};
8544
79f689aa
PZ		 8545static void intel_cpu_pll_init(struct drm_device *dev)
8546{
affa9354 8547 if (HAS_DDI(dev))
79f689aa
PZ		 8548 intel_ddi_pll_init(dev);
8549}
8550
ee7b9f93
JB		 8551static void intel_pch_pll_init(struct drm_device *dev)
8552{
8553 drm_i915_private_t *dev_priv = dev->dev_private;
8554 int i;
8555
8556 if (dev_priv->num_pch_pll == 0) {
8557 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8558 return;
8559 }
8560
8561 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8562 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8563 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8564 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8565 }
8566}
8567
b358d0a6 8568static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8569{
22fd0fab 8570 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8571 struct intel_crtc *intel_crtc;
8572 int i;
8573
8574 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8575 if (intel_crtc == NULL)
8576 return;
8577
8578 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8579
8580 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8581 for (i = 0; i < 256; i++) {
8582 intel_crtc->lut_r[i] = i;
8583 intel_crtc->lut_g[i] = i;
8584 intel_crtc->lut_b[i] = i;
8585 }
8586
80824003
JB		 8587 /* Swap pipes & planes for FBC on pre-965 */
8588 intel_crtc->pipe = pipe;
8589 intel_crtc->plane = pipe;
3b117c8f 8590 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8591 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8592 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8593 intel_crtc->plane = !pipe;
80824003
JB		 8594 }
8595
22fd0fab
JB		 8596 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8597 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8598 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8599 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8600
79e53945 8601 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8602}
8603
08d7b3d1 8604int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8605 struct drm_file *file)
08d7b3d1 8606{
08d7b3d1 8607 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8608 struct drm_mode_object *drmmode_obj;
8609 struct intel_crtc *crtc;
08d7b3d1 8610
1cff8f6b
DV		 8611 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8612 return -ENODEV;
08d7b3d1 8613
c05422d5
DV		 8614 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8615 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8616
c05422d5 8617 if (!drmmode_obj) {
08d7b3d1
CW		 8618 DRM_ERROR("no such CRTC id\n");
8619 return -EINVAL;
8620 }
8621
c05422d5
DV		 8622 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8623 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8624
c05422d5 8625 return 0;
08d7b3d1
CW		 8626}
8627
66a9278e 8628static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8629{
66a9278e
DV		 8630 struct drm_device *dev = encoder->base.dev;
8631 struct intel_encoder *source_encoder;
79e53945 8632 int index_mask = 0;
79e53945
JB		 8633 int entry = 0;
8634
66a9278e
DV		 8635 list_for_each_entry(source_encoder,
8636 &dev->mode_config.encoder_list, base.head) {
8637
8638 if (encoder == source_encoder)
79e53945 8639 index_mask |= (1 << entry);
66a9278e
DV		 8640
8641 /* Intel hw has only one MUX where enocoders could be cloned. */
8642 if (encoder->cloneable && source_encoder->cloneable)
8643 index_mask |= (1 << entry);
8644
79e53945
JB		 8645 entry++;
8646 }
4ef69c7a 8647
79e53945
JB		 8648 return index_mask;
8649}
8650
4d302442
CW		 8651static bool has_edp_a(struct drm_device *dev)
8652{
8653 struct drm_i915_private *dev_priv = dev->dev_private;
8654
8655 if (!IS_MOBILE(dev))
8656 return false;
8657
8658 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8659 return false;
8660
8661 if (IS_GEN5(dev) &&
8662 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8663 return false;
8664
8665 return true;
8666}
8667
79e53945
JB		 8668static void intel_setup_outputs(struct drm_device *dev)
8669{
725e30ad 8670 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8671 struct intel_encoder *encoder;
cb0953d7 8672 bool dpd_is_edp = false;
f3cfcba6 8673 bool has_lvds;
79e53945 8674
f3cfcba6 8675 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8676 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8677 /* disable the panel fitter on everything but LVDS */
8678 I915_WRITE(PFIT_CONTROL, 0);
8679 }
79e53945 8680
c40c0f5b 8681 if (!IS_ULT(dev))
79935fca 8682 intel_crt_init(dev);
cb0953d7 8683
affa9354 8684 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8685 int found;
8686
8687 /* Haswell uses DDI functions to detect digital outputs */
8688 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8689 /* DDI A only supports eDP */
8690 if (found)
8691 intel_ddi_init(dev, PORT_A);
8692
8693 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8694 * register */
8695 found = I915_READ(SFUSE_STRAP);
8696
8697 if (found & SFUSE_STRAP_DDIB_DETECTED)
8698 intel_ddi_init(dev, PORT_B);
8699 if (found & SFUSE_STRAP_DDIC_DETECTED)
8700 intel_ddi_init(dev, PORT_C);
8701 if (found & SFUSE_STRAP_DDID_DETECTED)
8702 intel_ddi_init(dev, PORT_D);
8703 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8704 int found;
270b3042
DV		 8705 dpd_is_edp = intel_dpd_is_edp(dev);
8706
8707 if (has_edp_a(dev))
8708 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8709
dc0fa718 8710 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8711 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8712 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8713 if (!found)
e2debe91 8714 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8715 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8716 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8717 }
8718
dc0fa718 8719 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8720 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8721
dc0fa718 8722 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8723 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8724
5eb08b69 8725 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8726 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8727
270b3042 8728 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8729 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8730 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8731 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8732 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8733 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8734
dc0fa718 8735 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8736 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8737 PORT_B);
67cfc203
VS		 8738 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8739 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8740 }
103a196f 8741 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8742 bool found = false;
7d57382e 8743
e2debe91 8744 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8745 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8746 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8747 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8748 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8749 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8750 }
27185ae1 8751
e7281eab 8752 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8753 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8754 }
13520b05
KH		 8755
8756 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8757
e2debe91 8758 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8759 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8760 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8761 }
27185ae1 8762
e2debe91 8763 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8764
b01f2c3a
JB		 8765 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8766 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8767 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8768 }
e7281eab 8769 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8770 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8771 }
27185ae1 8772
b01f2c3a 8773 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8774 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8775 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8776 } else if (IS_GEN2(dev))
79e53945
JB		 8777 intel_dvo_init(dev);
8778
103a196f 8779 if (SUPPORTS_TV(dev))
79e53945
JB		 8780 intel_tv_init(dev);
8781
4ef69c7a
CW		 8782 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8783 encoder->base.possible_crtcs = encoder->crtc_mask;
8784 encoder->base.possible_clones =
66a9278e 8785 intel_encoder_clones(encoder);
79e53945 8786 }
47356eb6 8787
dde86e2d 8788 intel_init_pch_refclk(dev);
270b3042
DV		 8789
8790 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8791}
8792
8793static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8794{
8795 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8796
8797 drm_framebuffer_cleanup(fb);
05394f39 8798 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8799
8800 kfree(intel_fb);
8801}
8802
8803static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8804 struct drm_file *file,
79e53945
JB		 8805 unsigned int *handle)
8806{
8807 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8808 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8809
05394f39 8810 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8811}
8812
8813static const struct drm_framebuffer_funcs intel_fb_funcs = {
8814 .destroy = intel_user_framebuffer_destroy,
8815 .create_handle = intel_user_framebuffer_create_handle,
8816};
8817
38651674
DA		 8818int intel_framebuffer_init(struct drm_device *dev,
8819 struct intel_framebuffer *intel_fb,
308e5bcb 8820 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8821 struct drm_i915_gem_object *obj)
79e53945 8822{
79e53945
JB		 8823 int ret;
8824
c16ed4be
CW		 8825 if (obj->tiling_mode == I915_TILING_Y) {
8826 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8827 return -EINVAL;
c16ed4be 8828 }
57cd6508 8829
c16ed4be
CW		 8830 if (mode_cmd->pitches[0] & 63) {
8831 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8832 mode_cmd->pitches[0]);
57cd6508 8833 return -EINVAL;
c16ed4be 8834 }
57cd6508 8835
5d7bd705 8836 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8837 if (mode_cmd->pitches[0] > 32768) {
8838 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8839 mode_cmd->pitches[0]);
5d7bd705 8840 return -EINVAL;
c16ed4be 8841 }
5d7bd705
VS		 8842
8843 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8844 mode_cmd->pitches[0] != obj->stride) {
8845 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8846 mode_cmd->pitches[0], obj->stride);
5d7bd705 8847 return -EINVAL;
c16ed4be 8848 }
5d7bd705 8849
57779d06 8850 /* Reject formats not supported by any plane early. */
308e5bcb 8851 switch (mode_cmd->pixel_format) {
57779d06 8852 case DRM_FORMAT_C8:
04b3924d
VS		 8853 case DRM_FORMAT_RGB565:
8854 case DRM_FORMAT_XRGB8888:
8855 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8856 break;
8857 case DRM_FORMAT_XRGB1555:
8858 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8859 if (INTEL_INFO(dev)->gen > 3) {
8860 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8861 return -EINVAL;
c16ed4be 8862 }
57779d06
VS		 8863 break;
8864 case DRM_FORMAT_XBGR8888:
8865 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8866 case DRM_FORMAT_XRGB2101010:
8867 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8868 case DRM_FORMAT_XBGR2101010:
8869 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8870 if (INTEL_INFO(dev)->gen < 4) {
8871 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8872 return -EINVAL;
c16ed4be 8873 }
b5626747 8874 break;
04b3924d
VS		 8875 case DRM_FORMAT_YUYV:
8876 case DRM_FORMAT_UYVY:
8877 case DRM_FORMAT_YVYU:
8878 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8879 if (INTEL_INFO(dev)->gen < 5) {
8880 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8881 return -EINVAL;
c16ed4be 8882 }
57cd6508
CW		 8883 break;
8884 default:
c16ed4be 8885 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8886 return -EINVAL;
8887 }
8888
90f9a336
VS		 8889 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8890 if (mode_cmd->offsets[0] != 0)
8891 return -EINVAL;
8892
c7d73f6a
DV		 8893 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8894 intel_fb->obj = obj;
8895
79e53945
JB		 8896 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8897 if (ret) {
8898 DRM_ERROR("framebuffer init failed %d\n", ret);
8899 return ret;
8900 }
8901
79e53945
JB		 8902 return 0;
8903}
8904
79e53945
JB		 8905static struct drm_framebuffer *
8906intel_user_framebuffer_create(struct drm_device *dev,
8907 struct drm_file *filp,
308e5bcb 8908 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8909{
05394f39 8910 struct drm_i915_gem_object *obj;
79e53945 8911
308e5bcb
JB		 8912 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8913 mode_cmd->handles[0]));
c8725226 8914 if (&obj->base == NULL)
cce13ff7 8915 return ERR_PTR(-ENOENT);
79e53945 8916
d2dff872 8917 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8918}
8919
79e53945 8920static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8921 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8922 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8923};
8924
e70236a8
JB		 8925/* Set up chip specific display functions */
8926static void intel_init_display(struct drm_device *dev)
8927{
8928 struct drm_i915_private *dev_priv = dev->dev_private;
8929
affa9354 8930 if (HAS_DDI(dev)) {
0e8ffe1b 8931 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8932 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8933 dev_priv->display.crtc_enable = haswell_crtc_enable;
8934 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8935 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8936 dev_priv->display.update_plane = ironlake_update_plane;
8937 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8938 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8939 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8940 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8941 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8942 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8943 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8944 } else if (IS_VALLEYVIEW(dev)) {
8945 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8946 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8947 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8948 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8949 dev_priv->display.off = i9xx_crtc_off;
8950 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8951 } else {
0e8ffe1b 8952 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8953 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8954 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8955 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8956 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8957 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8958 }
e70236a8 8959
e70236a8 8960 /* Returns the core display clock speed */
25eb05fc
JB		 8961 if (IS_VALLEYVIEW(dev))
8962 dev_priv->display.get_display_clock_speed =
8963 valleyview_get_display_clock_speed;
8964 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8965 dev_priv->display.get_display_clock_speed =
8966 i945_get_display_clock_speed;
8967 else if (IS_I915G(dev))
8968 dev_priv->display.get_display_clock_speed =
8969 i915_get_display_clock_speed;
f2b115e6 8970 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8971 dev_priv->display.get_display_clock_speed =
8972 i9xx_misc_get_display_clock_speed;
8973 else if (IS_I915GM(dev))
8974 dev_priv->display.get_display_clock_speed =
8975 i915gm_get_display_clock_speed;
8976 else if (IS_I865G(dev))
8977 dev_priv->display.get_display_clock_speed =
8978 i865_get_display_clock_speed;
f0f8a9ce 8979 else if (IS_I85X(dev))
e70236a8
JB		 8980 dev_priv->display.get_display_clock_speed =
8981 i855_get_display_clock_speed;
8982 else /* 852, 830 */
8983 dev_priv->display.get_display_clock_speed =
8984 i830_get_display_clock_speed;
8985
7f8a8569 8986 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8987 if (IS_GEN5(dev)) {
674cf967 8988 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8989 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8990 } else if (IS_GEN6(dev)) {
674cf967 8991 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8992 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8993 } else if (IS_IVYBRIDGE(dev)) {
8994 /* FIXME: detect B0+ stepping and use auto training */
8995 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8996 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8997 dev_priv->display.modeset_global_resources =
8998 ivb_modeset_global_resources;
c82e4d26
ED		 8999 } else if (IS_HASWELL(dev)) {
9000 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9001 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9002 dev_priv->display.modeset_global_resources =
9003 haswell_modeset_global_resources;
a0e63c22 9004 }
6067aaea 9005 } else if (IS_G4X(dev)) {
e0dac65e 9006 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9007 }
8c9f3aaf
JB		 9008
9009 /* Default just returns -ENODEV to indicate unsupported */
9010 dev_priv->display.queue_flip = intel_default_queue_flip;
9011
9012 switch (INTEL_INFO(dev)->gen) {
9013 case 2:
9014 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9015 break;
9016
9017 case 3:
9018 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9019 break;
9020
9021 case 4:
9022 case 5:
9023 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9024 break;
9025
9026 case 6:
9027 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9028 break;
7c9017e5
JB		 9029 case 7:
9030 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9031 break;
8c9f3aaf 9032 }
e70236a8
JB		 9033}
9034
b690e96c
JB		 9035/*
9036 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9037 * resume, or other times. This quirk makes sure that's the case for
9038 * affected systems.
9039 */
0206e353 9040static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9041{
9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043
9044 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9045 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9046}
9047
435793df
KP		 9048/*
9049 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9050 */
9051static void quirk_ssc_force_disable(struct drm_device *dev)
9052{
9053 struct drm_i915_private *dev_priv = dev->dev_private;
9054 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9055 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9056}
9057
4dca20ef 9058/*
5a15ab5b
CE		 9059 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9060 * brightness value
4dca20ef
CE		 9061 */
9062static void quirk_invert_brightness(struct drm_device *dev)
9063{
9064 struct drm_i915_private *dev_priv = dev->dev_private;
9065 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9066 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9067}
9068
b690e96c
JB		 9069struct intel_quirk {
9070 int device;
9071 int subsystem_vendor;
9072 int subsystem_device;
9073 void (*hook)(struct drm_device *dev);
9074};
9075
5f85f176
EE		 9076/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9077struct intel_dmi_quirk {
9078 void (*hook)(struct drm_device *dev);
9079 const struct dmi_system_id (*dmi_id_list)[];
9080};
9081
9082static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9083{
9084 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9085 return 1;
9086}
9087
9088static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9089 {
9090 .dmi_id_list = &(const struct dmi_system_id[]) {
9091 {
9092 .callback = intel_dmi_reverse_brightness,
9093 .ident = "NCR Corporation",
9094 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9095 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9096 },
9097 },
9098 { } /* terminating entry */
9099 },
9100 .hook = quirk_invert_brightness,
9101 },
9102};
9103
c43b5634 9104static struct intel_quirk intel_quirks[] = {
b690e96c 9105 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9106 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9107
b690e96c
JB		 9108 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9109 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9110
b690e96c
JB		 9111 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9112 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9113
ccd0d36e 9114 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9115 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9116 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9117
9118 /* Lenovo U160 cannot use SSC on LVDS */
9119 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9120
9121 /* Sony Vaio Y cannot use SSC on LVDS */
9122 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9123
9124 /* Acer Aspire 5734Z must invert backlight brightness */
9125 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9126
9127 /* Acer/eMachines G725 */
9128 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9129
9130 /* Acer/eMachines e725 */
9131 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9132
9133 /* Acer/Packard Bell NCL20 */
9134 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9135
9136 /* Acer Aspire 4736Z */
9137 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9138};
9139
9140static void intel_init_quirks(struct drm_device *dev)
9141{
9142 struct pci_dev *d = dev->pdev;
9143 int i;
9144
9145 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9146 struct intel_quirk *q = &intel_quirks[i];
9147
9148 if (d->device == q->device &&
9149 (d->subsystem_vendor == q->subsystem_vendor ||
9150 q->subsystem_vendor == PCI_ANY_ID) &&
9151 (d->subsystem_device == q->subsystem_device ||
9152 q->subsystem_device == PCI_ANY_ID))
9153 q->hook(dev);
9154 }
5f85f176
EE		 9155 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9156 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9157 intel_dmi_quirks[i].hook(dev);
9158 }
b690e96c
JB		 9159}
9160
9cce37f4
JB		 9161/* Disable the VGA plane that we never use */
9162static void i915_disable_vga(struct drm_device *dev)
9163{
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 u8 sr1;
766aa1c4 9166 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9167
9168 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9169 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9170 sr1 = inb(VGA_SR_DATA);
9171 outb(sr1 | 1<<5, VGA_SR_DATA);
9172 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9173 udelay(300);
9174
9175 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9176 POSTING_READ(vga_reg);
9177}
9178
f817586c
DV		 9179void intel_modeset_init_hw(struct drm_device *dev)
9180{
fa42e23c 9181 intel_init_power_well(dev);
0232e927 9182
a8f78b58
ED		 9183 intel_prepare_ddi(dev);
9184
f817586c
DV		 9185 intel_init_clock_gating(dev);
9186
79f5b2c7 9187 mutex_lock(&dev->struct_mutex);
8090c6b9 9188 intel_enable_gt_powersave(dev);
79f5b2c7 9189 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9190}
9191
7d708ee4
ID		 9192void intel_modeset_suspend_hw(struct drm_device *dev)
9193{
9194 intel_suspend_hw(dev);
9195}
9196
79e53945
JB		 9197void intel_modeset_init(struct drm_device *dev)
9198{
652c393a 9199 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9200 int i, j, ret;
79e53945
JB		 9201
9202 drm_mode_config_init(dev);
9203
9204 dev->mode_config.min_width = 0;
9205 dev->mode_config.min_height = 0;
9206
019d96cb
DA		 9207 dev->mode_config.preferred_depth = 24;
9208 dev->mode_config.prefer_shadow = 1;
9209
e6ecefaa 9210 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9211
b690e96c
JB		 9212 intel_init_quirks(dev);
9213
1fa61106
ED		 9214 intel_init_pm(dev);
9215
e3c74757
BW		 9216 if (INTEL_INFO(dev)->num_pipes == 0)
9217 return;
9218
e70236a8
JB		 9219 intel_init_display(dev);
9220
a6c45cf0
CW		 9221 if (IS_GEN2(dev)) {
9222 dev->mode_config.max_width = 2048;
9223 dev->mode_config.max_height = 2048;
9224 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9225 dev->mode_config.max_width = 4096;
9226 dev->mode_config.max_height = 4096;
79e53945 9227 } else {
a6c45cf0
CW		 9228 dev->mode_config.max_width = 8192;
9229 dev->mode_config.max_height = 8192;
79e53945 9230 }
5d4545ae 9231 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9232
28c97730 9233 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9234 INTEL_INFO(dev)->num_pipes,
9235 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9236
7eb552ae 9237 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9238 intel_crtc_init(dev, i);
7f1f3851
JB		 9239 for (j = 0; j < dev_priv->num_plane; j++) {
9240 ret = intel_plane_init(dev, i, j);
9241 if (ret)
06da8da2
VS		 9242 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9243 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9244 }
79e53945
JB		 9245 }
9246
79f689aa 9247 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9248 intel_pch_pll_init(dev);
9249
9cce37f4
JB		 9250 /* Just disable it once at startup */
9251 i915_disable_vga(dev);
79e53945 9252 intel_setup_outputs(dev);
11be49eb
CW		 9253
9254 /* Just in case the BIOS is doing something questionable. */
9255 intel_disable_fbc(dev);
2c7111db
CW		 9256}
9257
24929352
DV		 9258static void
9259intel_connector_break_all_links(struct intel_connector *connector)
9260{
9261 connector->base.dpms = DRM_MODE_DPMS_OFF;
9262 connector->base.encoder = NULL;
9263 connector->encoder->connectors_active = false;
9264 connector->encoder->base.crtc = NULL;
9265}
9266
7fad798e
DV		 9267static void intel_enable_pipe_a(struct drm_device *dev)
9268{
9269 struct intel_connector *connector;
9270 struct drm_connector *crt = NULL;
9271 struct intel_load_detect_pipe load_detect_temp;
9272
9273 /* We can't just switch on the pipe A, we need to set things up with a
9274 * proper mode and output configuration. As a gross hack, enable pipe A
9275 * by enabling the load detect pipe once. */
9276 list_for_each_entry(connector,
9277 &dev->mode_config.connector_list,
9278 base.head) {
9279 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9280 crt = &connector->base;
9281 break;
9282 }
9283 }
9284
9285 if (!crt)
9286 return;
9287
9288 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9289 intel_release_load_detect_pipe(crt, &load_detect_temp);
9290
652c393a 9291
7fad798e
DV		 9292}
9293
fa555837
DV		 9294static bool
9295intel_check_plane_mapping(struct intel_crtc *crtc)
9296{
7eb552ae
BW		 9297 struct drm_device *dev = crtc->base.dev;
9298 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9299 u32 reg, val;
9300
7eb552ae 9301 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9302 return true;
9303
9304 reg = DSPCNTR(!crtc->plane);
9305 val = I915_READ(reg);
9306
9307 if ((val & DISPLAY_PLANE_ENABLE) &&
9308 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9309 return false;
9310
9311 return true;
9312}
9313
24929352
DV		 9314static void intel_sanitize_crtc(struct intel_crtc *crtc)
9315{
9316 struct drm_device *dev = crtc->base.dev;
9317 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9318 u32 reg;
24929352 9319
24929352 9320 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9321 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9322 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9323
9324 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9325 * disable the crtc (and hence change the state) if it is wrong. Note
9326 * that gen4+ has a fixed plane -> pipe mapping. */
9327 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9328 struct intel_connector *connector;
9329 bool plane;
9330
24929352
DV		 9331 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9332 crtc->base.base.id);
9333
9334 /* Pipe has the wrong plane attached and the plane is active.
9335 * Temporarily change the plane mapping and disable everything
9336 * ... */
9337 plane = crtc->plane;
9338 crtc->plane = !plane;
9339 dev_priv->display.crtc_disable(&crtc->base);
9340 crtc->plane = plane;
9341
9342 /* ... and break all links. */
9343 list_for_each_entry(connector, &dev->mode_config.connector_list,
9344 base.head) {
9345 if (connector->encoder->base.crtc != &crtc->base)
9346 continue;
9347
9348 intel_connector_break_all_links(connector);
9349 }
9350
9351 WARN_ON(crtc->active);
9352 crtc->base.enabled = false;
9353 }
24929352 9354
7fad798e
DV		 9355 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9356 crtc->pipe == PIPE_A && !crtc->active) {
9357 /* BIOS forgot to enable pipe A, this mostly happens after
9358 * resume. Force-enable the pipe to fix this, the update_dpms
9359 * call below we restore the pipe to the right state, but leave
9360 * the required bits on. */
9361 intel_enable_pipe_a(dev);
9362 }
9363
24929352
DV		 9364 /* Adjust the state of the output pipe according to whether we
9365 * have active connectors/encoders. */
9366 intel_crtc_update_dpms(&crtc->base);
9367
9368 if (crtc->active != crtc->base.enabled) {
9369 struct intel_encoder *encoder;
9370
9371 /* This can happen either due to bugs in the get_hw_state
9372 * functions or because the pipe is force-enabled due to the
9373 * pipe A quirk. */
9374 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9375 crtc->base.base.id,
9376 crtc->base.enabled ? "enabled" : "disabled",
9377 crtc->active ? "enabled" : "disabled");
9378
9379 crtc->base.enabled = crtc->active;
9380
9381 /* Because we only establish the connector -> encoder ->
9382 * crtc links if something is active, this means the
9383 * crtc is now deactivated. Break the links. connector
9384 * -> encoder links are only establish when things are
9385 * actually up, hence no need to break them. */
9386 WARN_ON(crtc->active);
9387
9388 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9389 WARN_ON(encoder->connectors_active);
9390 encoder->base.crtc = NULL;
9391 }
9392 }
9393}
9394
9395static void intel_sanitize_encoder(struct intel_encoder *encoder)
9396{
9397 struct intel_connector *connector;
9398 struct drm_device *dev = encoder->base.dev;
9399
9400 /* We need to check both for a crtc link (meaning that the
9401 * encoder is active and trying to read from a pipe) and the
9402 * pipe itself being active. */
9403 bool has_active_crtc = encoder->base.crtc &&
9404 to_intel_crtc(encoder->base.crtc)->active;
9405
9406 if (encoder->connectors_active && !has_active_crtc) {
9407 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9408 encoder->base.base.id,
9409 drm_get_encoder_name(&encoder->base));
9410
9411 /* Connector is active, but has no active pipe. This is
9412 * fallout from our resume register restoring. Disable
9413 * the encoder manually again. */
9414 if (encoder->base.crtc) {
9415 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9416 encoder->base.base.id,
9417 drm_get_encoder_name(&encoder->base));
9418 encoder->disable(encoder);
9419 }
9420
9421 /* Inconsistent output/port/pipe state happens presumably due to
9422 * a bug in one of the get_hw_state functions. Or someplace else
9423 * in our code, like the register restore mess on resume. Clamp
9424 * things to off as a safer default. */
9425 list_for_each_entry(connector,
9426 &dev->mode_config.connector_list,
9427 base.head) {
9428 if (connector->encoder != encoder)
9429 continue;
9430
9431 intel_connector_break_all_links(connector);
9432 }
9433 }
9434 /* Enabled encoders without active connectors will be fixed in
9435 * the crtc fixup. */
9436}
9437
44cec740 9438void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9439{
9440 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9441 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9442
9443 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9444 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9445 i915_disable_vga(dev);
0fde901f
KM		 9446 }
9447}
9448
24929352
DV		 9449/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9450 * and i915 state tracking structures. */
45e2b5f6
DV		 9451void intel_modeset_setup_hw_state(struct drm_device *dev,
9452 bool force_restore)
24929352
DV		 9453{
9454 struct drm_i915_private *dev_priv = dev->dev_private;
9455 enum pipe pipe;
9456 u32 tmp;
b5644d05 9457 struct drm_plane *plane;
24929352
DV		 9458 struct intel_crtc *crtc;
9459 struct intel_encoder *encoder;
9460 struct intel_connector *connector;
9461
affa9354 9462 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9463 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9464
9465 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9466 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9467 case TRANS_DDI_EDP_INPUT_A_ON:
9468 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9469 pipe = PIPE_A;
9470 break;
9471 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9472 pipe = PIPE_B;
9473 break;
9474 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9475 pipe = PIPE_C;
9476 break;
aaa148ec
DL		 9477 default:
9478 /* A bogus value has been programmed, disable
9479 * the transcoder */
9480 WARN(1, "Bogus eDP source %08x\n", tmp);
9481 intel_ddi_disable_transcoder_func(dev_priv,
9482 TRANSCODER_EDP);
9483 goto setup_pipes;
e28d54cb
PZ		 9484 }
9485
9486 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9487 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9488
9489 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9490 pipe_name(pipe));
9491 }
9492 }
9493
aaa148ec 9494setup_pipes:
0e8ffe1b
DV		 9495 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9496 base.head) {
3b117c8f 9497 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9498 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9499 crtc->config.cpu_transcoder = tmp;
9500
0e8ffe1b
DV		 9501 crtc->active = dev_priv->display.get_pipe_config(crtc,
9502 &crtc->config);
24929352
DV		 9503
9504 crtc->base.enabled = crtc->active;
9505
9506 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9507 crtc->base.base.id,
9508 crtc->active ? "enabled" : "disabled");
9509 }
9510
affa9354 9511 if (HAS_DDI(dev))
6441ab5f
PZ		 9512 intel_ddi_setup_hw_pll_state(dev);
9513
24929352
DV		 9514 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9515 base.head) {
9516 pipe = 0;
9517
9518 if (encoder->get_hw_state(encoder, &pipe)) {
9519 encoder->base.crtc =
9520 dev_priv->pipe_to_crtc_mapping[pipe];
9521 } else {
9522 encoder->base.crtc = NULL;
9523 }
9524
9525 encoder->connectors_active = false;
9526 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9527 encoder->base.base.id,
9528 drm_get_encoder_name(&encoder->base),
9529 encoder->base.crtc ? "enabled" : "disabled",
9530 pipe);
9531 }
9532
9533 list_for_each_entry(connector, &dev->mode_config.connector_list,
9534 base.head) {
9535 if (connector->get_hw_state(connector)) {
9536 connector->base.dpms = DRM_MODE_DPMS_ON;
9537 connector->encoder->connectors_active = true;
9538 connector->base.encoder = &connector->encoder->base;
9539 } else {
9540 connector->base.dpms = DRM_MODE_DPMS_OFF;
9541 connector->base.encoder = NULL;
9542 }
9543 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9544 connector->base.base.id,
9545 drm_get_connector_name(&connector->base),
9546 connector->base.encoder ? "enabled" : "disabled");
9547 }
9548
9549 /* HW state is read out, now we need to sanitize this mess. */
9550 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9551 base.head) {
9552 intel_sanitize_encoder(encoder);
9553 }
9554
9555 for_each_pipe(pipe) {
9556 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9557 intel_sanitize_crtc(crtc);
9558 }
9a935856 9559
45e2b5f6 9560 if (force_restore) {
f30da187
DV		 9561 /*
9562 * We need to use raw interfaces for restoring state to avoid
9563 * checking (bogus) intermediate states.
9564 */
45e2b5f6 9565 for_each_pipe(pipe) {
b5644d05
JB		 9566 struct drm_crtc *crtc =
9567 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9568
9569 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9570 crtc->fb);
45e2b5f6 9571 }
b5644d05
JB		 9572 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9573 intel_plane_restore(plane);
0fde901f
KM		 9574
9575 i915_redisable_vga(dev);
45e2b5f6
DV		 9576 } else {
9577 intel_modeset_update_staged_output_state(dev);
9578 }
8af6cf88
DV		 9579
9580 intel_modeset_check_state(dev);
2e938892
DV		 9581
9582 drm_mode_config_reset(dev);
2c7111db
CW		 9583}
9584
9585void intel_modeset_gem_init(struct drm_device *dev)
9586{
1833b134 9587 intel_modeset_init_hw(dev);
02e792fb
DV		 9588
9589 intel_setup_overlay(dev);
24929352 9590
45e2b5f6 9591 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9592}
9593
9594void intel_modeset_cleanup(struct drm_device *dev)
9595{
652c393a
JB		 9596 struct drm_i915_private *dev_priv = dev->dev_private;
9597 struct drm_crtc *crtc;
9598 struct intel_crtc *intel_crtc;
9599
fd0c0642
DV		 9600 /*
9601 * Interrupts and polling as the first thing to avoid creating havoc.
9602 * Too much stuff here (turning of rps, connectors, ...) would
9603 * experience fancy races otherwise.
9604 */
9605 drm_irq_uninstall(dev);
9606 cancel_work_sync(&dev_priv->hotplug_work);
9607 /*
9608 * Due to the hpd irq storm handling the hotplug work can re-arm the
9609 * poll handlers. Hence disable polling after hpd handling is shut down.
9610 */
f87ea761 9611 drm_kms_helper_poll_fini(dev);
fd0c0642 9612
652c393a
JB		 9613 mutex_lock(&dev->struct_mutex);
9614
723bfd70
JB		 9615 intel_unregister_dsm_handler();
9616
652c393a
JB		 9617 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9618 /* Skip inactive CRTCs */
9619 if (!crtc->fb)
9620 continue;
9621
9622 intel_crtc = to_intel_crtc(crtc);
3dec0095 9623 intel_increase_pllclock(crtc);
652c393a
JB		 9624 }
9625
973d04f9 9626 intel_disable_fbc(dev);
e70236a8 9627
8090c6b9 9628 intel_disable_gt_powersave(dev);
0cdab21f 9629
930ebb46
DV		 9630 ironlake_teardown_rc6(dev);
9631
69341a5e
KH		 9632 mutex_unlock(&dev->struct_mutex);
9633
1630fe75
CW		 9634 /* flush any delayed tasks or pending work */
9635 flush_scheduled_work();
9636
dc652f90
JN		 9637 /* destroy backlight, if any, before the connectors */
9638 intel_panel_destroy_backlight(dev);
9639
79e53945 9640 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9641
9642 intel_cleanup_overlay(dev);
79e53945
JB		 9643}
9644
f1c79df3
ZW		 9645/*
9646 * Return which encoder is currently attached for connector.
9647 */
df0e9248 9648struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9649{
df0e9248
CW		 9650 return &intel_attached_encoder(connector)->base;
9651}
f1c79df3 9652
df0e9248
CW		 9653void intel_connector_attach_encoder(struct intel_connector *connector,
9654 struct intel_encoder *encoder)
9655{
9656 connector->encoder = encoder;
9657 drm_mode_connector_attach_encoder(&connector->base,
9658 &encoder->base);
79e53945 9659}
28d52043
DA		 9660
9661/*
9662 * set vga decode state - true == enable VGA decode
9663 */
9664int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9665{
9666 struct drm_i915_private *dev_priv = dev->dev_private;
9667 u16 gmch_ctrl;
9668
9669 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9670 if (state)
9671 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9672 else
9673 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9674 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9675 return 0;
9676}
c4a1d9e4
CW		 9677
9678#ifdef CONFIG_DEBUG_FS
9679#include <linux/seq_file.h>
9680
9681struct intel_display_error_state {
ff57f1b0
PZ		 9682
9683 u32 power_well_driver;
9684
c4a1d9e4
CW		 9685 struct intel_cursor_error_state {
9686 u32 control;
9687 u32 position;
9688 u32 base;
9689 u32 size;
52331309 9690 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9691
9692 struct intel_pipe_error_state {
ff57f1b0 9693 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9694 u32 conf;
9695 u32 source;
9696
9697 u32 htotal;
9698 u32 hblank;
9699 u32 hsync;
9700 u32 vtotal;
9701 u32 vblank;
9702 u32 vsync;
52331309 9703 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9704
9705 struct intel_plane_error_state {
9706 u32 control;
9707 u32 stride;
9708 u32 size;
9709 u32 pos;
9710 u32 addr;
9711 u32 surface;
9712 u32 tile_offset;
52331309 9713 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9714};
9715
9716struct intel_display_error_state *
9717intel_display_capture_error_state(struct drm_device *dev)
9718{
0206e353 9719 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9720 struct intel_display_error_state *error;
702e7a56 9721 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9722 int i;
9723
9724 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9725 if (error == NULL)
9726 return NULL;
9727
ff57f1b0
PZ		 9728 if (HAS_POWER_WELL(dev))
9729 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9730
52331309 9731 for_each_pipe(i) {
702e7a56 9732 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9733 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9734
a18c4c3d
PZ		 9735 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9736 error->cursor[i].control = I915_READ(CURCNTR(i));
9737 error->cursor[i].position = I915_READ(CURPOS(i));
9738 error->cursor[i].base = I915_READ(CURBASE(i));
9739 } else {
9740 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9741 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9742 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9743 }
c4a1d9e4
CW		 9744
9745 error->plane[i].control = I915_READ(DSPCNTR(i));
9746 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9747 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9748 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9749 error->plane[i].pos = I915_READ(DSPPOS(i));
9750 }
ca291363
PZ		 9751 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9752 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9753 if (INTEL_INFO(dev)->gen >= 4) {
9754 error->plane[i].surface = I915_READ(DSPSURF(i));
9755 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9756 }
9757
702e7a56 9758 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9759 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9760 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9761 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9762 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9763 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9764 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9765 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9766 }
9767
12d217c7
PZ		 9768 /* In the code above we read the registers without checking if the power
9769 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9770 * prevent the next I915_WRITE from detecting it and printing an error
9771 * message. */
9772 if (HAS_POWER_WELL(dev))
9773 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9774
c4a1d9e4
CW		 9775 return error;
9776}
9777
9778void
9779intel_display_print_error_state(struct seq_file *m,
9780 struct drm_device *dev,
9781 struct intel_display_error_state *error)
9782{
9783 int i;
9784
7eb552ae 9785 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0
PZ		 9786 if (HAS_POWER_WELL(dev))
9787 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9788 error->power_well_driver);
52331309 9789 for_each_pipe(i) {
c4a1d9e4 9790 seq_printf(m, "Pipe [%d]:\n", i);
ff57f1b0
PZ		 9791 seq_printf(m, " CPU transcoder: %c\n",
9792 transcoder_name(error->pipe[i].cpu_transcoder));
c4a1d9e4
CW		 9793 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9794 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9795 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9796 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9797 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9798 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9799 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9800 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9801
9802 seq_printf(m, "Plane [%d]:\n", i);
9803 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9804 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9805 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9806 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9807 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9808 }
4b71a570 9809 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9810 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9811 if (INTEL_INFO(dev)->gen >= 4) {
9812 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9813 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9814 }
9815
9816 seq_printf(m, "Cursor [%d]:\n", i);
9817 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9818 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9819 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9820 }
9821}
9822#endif
Linux kernel - Deliverables
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