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Revert "drm/i915: Disable 12bpc hdmi for now"
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
cdba954e
ACO		 421static bool
422needs_modeset(struct drm_crtc_state *state)
423{
424 return state->mode_changed || state->active_changed;
425}
426
e0638cdf
PZ		 427/**
428 * Returns whether any output on the specified pipe is of the specified type
429 */
4093561b 430bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 431{
409ee761 432 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 433 struct intel_encoder *encoder;
434
409ee761 435 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 436 if (encoder->type == type)
437 return true;
438
439 return false;
440}
441
d0737e1d
ACO		 442/**
443 * Returns whether any output on the specified pipe will have the specified
444 * type after a staged modeset is complete, i.e., the same as
445 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
446 * encoder->crtc.
447 */
a93e255f
ACO		 448static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
449 int type)
d0737e1d 450{
a93e255f 451 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 452 struct drm_connector *connector;
a93e255f 453 struct drm_connector_state *connector_state;
d0737e1d 454 struct intel_encoder *encoder;
a93e255f
ACO		 455 int i, num_connectors = 0;
456
da3ced29 457 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 458 if (connector_state->crtc != crtc_state->base.crtc)
459 continue;
460
461 num_connectors++;
d0737e1d 462
a93e255f
ACO		 463 encoder = to_intel_encoder(connector_state->best_encoder);
464 if (encoder->type == type)
d0737e1d 465 return true;
a93e255f
ACO		 466 }
467
468 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 469
470 return false;
471}
472
a93e255f
ACO		 473static const intel_limit_t *
474intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 475{
a93e255f 476 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 477 const intel_limit_t *limit;
b91ad0ec 478
a93e255f 479 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 480 if (intel_is_dual_link_lvds(dev)) {
1b894b59 481 if (refclk == 100000)
b91ad0ec
ZW		 482 limit = &intel_limits_ironlake_dual_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_dual_lvds;
485 } else {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_single_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_single_lvds;
490 }
c6bb3538 491 } else
b91ad0ec 492 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 493
494 return limit;
495}
496
a93e255f
ACO		 497static const intel_limit_t *
498intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 499{
a93e255f 500 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 501 const intel_limit_t *limit;
502
a93e255f 503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 504 if (intel_is_dual_link_lvds(dev))
e4b36699 505 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 506 else
e4b36699 507 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 508 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 510 limit = &intel_limits_g4x_hdmi;
a93e255f 511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 512 limit = &intel_limits_g4x_sdvo;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
a93e255f
ACO		 519static const intel_limit_t *
520intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 521{
a93e255f 522 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 523 const intel_limit_t *limit;
524
5ab7b0b7
ID		 525 if (IS_BROXTON(dev))
526 limit = &intel_limits_bxt;
527 else if (HAS_PCH_SPLIT(dev))
a93e255f 528 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 529 else if (IS_G4X(dev)) {
a93e255f 530 limit = intel_g4x_limit(crtc_state);
f2b115e6 531 } else if (IS_PINEVIEW(dev)) {
a93e255f 532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 533 limit = &intel_limits_pineview_lvds;
2177832f 534 else
f2b115e6 535 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 536 } else if (IS_CHERRYVIEW(dev)) {
537 limit = &intel_limits_chv;
a0c4da24 538 } else if (IS_VALLEYVIEW(dev)) {
dc730512 539 limit = &intel_limits_vlv;
a6c45cf0 540 } else if (!IS_GEN2(dev)) {
a93e255f 541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945 545 } else {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
a93e255f 548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 549 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 550 else
551 limit = &intel_limits_i8xx_dac;
79e53945
JB		 552 }
553 return limit;
554}
555
dccbea3b
ID		 556/*
557 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
558 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
559 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
560 * The helpers' return value is the rate of the clock that is fed to the
561 * display engine's pipe which can be the above fast dot clock rate or a
562 * divided-down version of it.
563 */
f2b115e6 564/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 565static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 566{
2177832f
SL		 567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
ed5ca77e 569 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 570 return 0;
fb03ac01
VS		 571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 573
574 return clock->dot;
2177832f
SL		 575}
576
7429e9d4
DV		 577static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578{
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580}
581
dccbea3b 582static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 583{
7429e9d4 584 clock->m = i9xx_dpll_compute_m(clock);
79e53945 585 clock->p = clock->p1 * clock->p2;
ed5ca77e 586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 587 return 0;
fb03ac01
VS		 588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 590
591 return clock->dot;
79e53945
JB		 592}
593
dccbea3b 594static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 599 return 0;
589eca67
ID		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot / 5;
589eca67
ID		 604}
605
dccbea3b 606int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 607{
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 611 return 0;
ef9348c8
CML		 612 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
613 clock->n << 22);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 615
616 return clock->dot / 5;
ef9348c8
CML		 617}
618
7c04d1d9 619#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 620/**
621 * Returns whether the given set of divisors are valid for a given refclk with
622 * the given connectors.
623 */
624
1b894b59
CW		 625static bool intel_PLL_is_valid(struct drm_device *dev,
626 const intel_limit_t *limit,
627 const intel_clock_t *clock)
79e53945 628{
f01b7962
VS		 629 if (clock->n < limit->n.min || limit->n.max < clock->n)
630 INTELPllInvalid("n out of range\n");
79e53945 631 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 632 INTELPllInvalid("p1 out of range\n");
79e53945 633 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 634 INTELPllInvalid("m2 out of range\n");
79e53945 635 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 636 INTELPllInvalid("m1 out of range\n");
f01b7962 637
5ab7b0b7 638 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 639 if (clock->m1 <= clock->m2)
640 INTELPllInvalid("m1 <= m2\n");
641
5ab7b0b7 642 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 643 if (clock->p < limit->p.min || limit->p.max < clock->p)
644 INTELPllInvalid("p out of range\n");
645 if (clock->m < limit->m.min || limit->m.max < clock->m)
646 INTELPllInvalid("m out of range\n");
647 }
648
79e53945 649 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 650 INTELPllInvalid("vco out of range\n");
79e53945
JB		 651 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
652 * connector, etc., rather than just a single range.
653 */
654 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 655 INTELPllInvalid("dot out of range\n");
79e53945
JB		 656
657 return true;
658}
659
3b1429d9
VS		 660static int
661i9xx_select_p2_div(const intel_limit_t *limit,
662 const struct intel_crtc_state *crtc_state,
663 int target)
79e53945 664{
3b1429d9 665 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 666
a93e255f 667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 668 /*
a210b028
DV		 669 * For LVDS just rely on its current settings for dual-channel.
670 * We haven't figured out how to reliably set up different
671 * single/dual channel state, if we even can.
79e53945 672 */
1974cad0 673 if (intel_is_dual_link_lvds(dev))
3b1429d9 674 return limit->p2.p2_fast;
79e53945 675 else
3b1429d9 676 return limit->p2.p2_slow;
79e53945
JB		 677 } else {
678 if (target < limit->p2.dot_limit)
3b1429d9 679 return limit->p2.p2_slow;
79e53945 680 else
3b1429d9 681 return limit->p2.p2_fast;
79e53945 682 }
3b1429d9
VS		 683}
684
685static bool
686i9xx_find_best_dpll(const intel_limit_t *limit,
687 struct intel_crtc_state *crtc_state,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
690{
691 struct drm_device *dev = crtc_state->base.crtc->dev;
692 intel_clock_t clock;
693 int err = target;
79e53945 694
0206e353 695 memset(best_clock, 0, sizeof(*best_clock));
79e53945 696
3b1429d9
VS		 697 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
698
42158660
ZY		 699 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
700 clock.m1++) {
701 for (clock.m2 = limit->m2.min;
702 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 703 if (clock.m2 >= clock.m1)
42158660
ZY		 704 break;
705 for (clock.n = limit->n.min;
706 clock.n <= limit->n.max; clock.n++) {
707 for (clock.p1 = limit->p1.min;
708 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 709 int this_err;
710
dccbea3b 711 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err) {
721 *best_clock = clock;
722 err = this_err;
723 }
724 }
725 }
726 }
727 }
728
729 return (err != target);
730}
731
732static bool
a93e255f
ACO		 733pnv_find_best_dpll(const intel_limit_t *limit,
734 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
79e53945 737{
3b1429d9 738 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 739 intel_clock_t clock;
79e53945
JB		 740 int err = target;
741
0206e353 742 memset(best_clock, 0, sizeof(*best_clock));
79e53945 743
3b1429d9
VS		 744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
42158660
ZY		 746 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 clock.m1++) {
748 for (clock.m2 = limit->m2.min;
749 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 750 for (clock.n = limit->n.min;
751 clock.n <= limit->n.max; clock.n++) {
752 for (clock.p1 = limit->p1.min;
753 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 754 int this_err;
755
dccbea3b 756 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
79e53945 759 continue;
cec2f356
SP		 760 if (match_clock &&
761 clock.p != match_clock->p)
762 continue;
79e53945
JB		 763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 }
769 }
770 }
771 }
772 }
773
774 return (err != target);
775}
776
d4906093 777static bool
a93e255f
ACO		 778g4x_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
d4906093 782{
3b1429d9 783 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 784 intel_clock_t clock;
785 int max_n;
3b1429d9 786 bool found = false;
6ba770dc
AJ		 787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 789
790 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 791
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
793
d4906093 794 max_n = limit->n.max;
f77f13e2 795 /* based on hardware requirement, prefer smaller n to precision */
d4906093 796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 797 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
804 int this_err;
805
dccbea3b 806 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 807 if (!intel_PLL_is_valid(dev, limit,
808 &clock))
d4906093 809 continue;
1b894b59
CW		 810
811 this_err = abs(clock.dot - target);
d4906093
ML		 812 if (this_err < err_most) {
813 *best_clock = clock;
814 err_most = this_err;
815 max_n = clock.n;
816 found = true;
817 }
818 }
819 }
820 }
821 }
2c07245f
ZW		 822 return found;
823}
824
d5dd62bd
ID		 825/*
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
828 */
829static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
834{
9ca3ba01
ID		 835 /*
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
838 */
839 if (IS_CHERRYVIEW(dev)) {
840 *error_ppm = 0;
841
842 return calculated_clock->p > best_clock->p;
843 }
844
24be4e46
ID		 845 if (WARN_ON_ONCE(!target_freq))
846 return false;
847
d5dd62bd
ID		 848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
850 target_freq);
851 /*
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
855 */
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
857 *error_ppm = 0;
858
859 return true;
860 }
861
862 return *error_ppm + 10 < best_error_ppm;
863}
864
a0c4da24 865static bool
a93e255f
ACO		 866vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
a0c4da24 870{
a93e255f 871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 872 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 873 intel_clock_t clock;
69e4f900 874 unsigned int bestppm = 1000000;
27e639bf
VS		 875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 877 bool found = false;
a0c4da24 878
6b4bf1c4
VS		 879 target *= 5; /* fast clock */
880
881 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 882
883 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 888 clock.p = clock.p1 * clock.p2;
a0c4da24 889 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 891 unsigned int ppm;
69e4f900 892
6b4bf1c4
VS		 893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
894 refclk * clock.m1);
895
dccbea3b 896 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 897
f01b7962
VS		 898 if (!intel_PLL_is_valid(dev, limit,
899 &clock))
43b0ac53
VS		 900 continue;
901
d5dd62bd
ID		 902 if (!vlv_PLL_is_optimal(dev, target,
903 &clock,
904 best_clock,
905 bestppm, &ppm))
906 continue;
6b4bf1c4 907
d5dd62bd
ID		 908 *best_clock = clock;
909 bestppm = ppm;
910 found = true;
a0c4da24
JB		 911 }
912 }
913 }
914 }
a0c4da24 915
49e497ef 916 return found;
a0c4da24 917}
a4fc5ed6 918
ef9348c8 919static bool
a93e255f
ACO		 920chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
924{
a93e255f 925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 926 struct drm_device *dev = crtc->base.dev;
9ca3ba01 927 unsigned int best_error_ppm;
ef9348c8
CML		 928 intel_clock_t clock;
929 uint64_t m2;
930 int found = false;
931
932 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 933 best_error_ppm = 1000000;
ef9348c8
CML		 934
935 /*
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
939 */
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
942
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 947 unsigned int error_ppm;
ef9348c8
CML		 948
949 clock.p = clock.p1 * clock.p2;
950
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
953
954 if (m2 > INT_MAX/clock.m1)
955 continue;
956
957 clock.m2 = m2;
958
dccbea3b 959 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 960
961 if (!intel_PLL_is_valid(dev, limit, &clock))
962 continue;
963
9ca3ba01
ID		 964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
966 continue;
967
968 *best_clock = clock;
969 best_error_ppm = error_ppm;
970 found = true;
ef9348c8
CML		 971 }
972 }
973
974 return found;
975}
976
5ab7b0b7
ID		 977bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
979{
980 int refclk = i9xx_get_refclk(crtc_state, 0);
981
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
984}
985
20ddf665
VS		 986bool intel_crtc_active(struct drm_crtc *crtc)
987{
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
989
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
992 *
241bfc38 993 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 994 * as Haswell has gained clock readout/fastboot support.
995 *
66e514c1 996 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 997 * properly reconstruct framebuffers.
c3d1f436
MR		 998 *
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1001 * for atomic.
20ddf665 1002 */
c3d1f436 1003 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1005}
1006
a5c961d1
PZ		 1007enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
6e3c9717 1013 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1014}
1015
fbf49ea2
VS		 1016static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1020 u32 line1, line2;
1021 u32 line_mask;
1022
1023 if (IS_GEN2(dev))
1024 line_mask = DSL_LINEMASK_GEN2;
1025 else
1026 line_mask = DSL_LINEMASK_GEN3;
1027
1028 line1 = I915_READ(reg) & line_mask;
1029 mdelay(5);
1030 line2 = I915_READ(reg) & line_mask;
1031
1032 return line1 == line2;
1033}
1034
ab7ad7f6
KP		 1035/*
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1037 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1038 *
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1042 *
ab7ad7f6
KP		 1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1045 *
1046 * Otherwise:
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
58e10eb9 1049 *
9d0498a2 1050 */
575f7ab7 1051static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1052{
575f7ab7 1053 struct drm_device *dev = crtc->base.dev;
9d0498a2 1054 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1056 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1057
1058 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1059 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1060
1061 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063 100))
284637d9 1064 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1065 } else {
ab7ad7f6 1066 /* Wait for the display line to settle */
fbf49ea2 1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1068 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1069 }
79e53945
JB		 1070}
1071
b0ea7d37
DL		 1072/*
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1076 *
1077 * Returns true if @port is connected, false otherwise.
1078 */
1079bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1081{
1082 u32 bit;
1083
c36346e3 1084 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1085 switch (port->port) {
c36346e3
DL		 1086 case PORT_B:
1087 bit = SDE_PORTB_HOTPLUG;
1088 break;
1089 case PORT_C:
1090 bit = SDE_PORTC_HOTPLUG;
1091 break;
1092 case PORT_D:
1093 bit = SDE_PORTD_HOTPLUG;
1094 break;
1095 default:
1096 return true;
1097 }
1098 } else {
eba905b2 1099 switch (port->port) {
c36346e3
DL		 1100 case PORT_B:
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1102 break;
1103 case PORT_C:
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1105 break;
1106 case PORT_D:
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1108 break;
1109 default:
1110 return true;
1111 }
b0ea7d37
DL		 1112 }
1113
1114 return I915_READ(SDEISR) & bit;
1115}
1116
b24e7179
JB		 1117static const char *state_string(bool enabled)
1118{
1119 return enabled ? "on" : "off";
1120}
1121
1122/* Only for pre-ILK configs */
55607e8a
DV		 1123void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
b24e7179
JB		 1125{
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
b24e7179 1137
23538ef1
JN		 1138/* XXX: the dsi pll is shared between MIPI DSI ports */
1139static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140{
1141 u32 val;
1142 bool cur_state;
1143
a580516d 1144 mutex_lock(&dev_priv->sb_lock);
23538ef1 1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1146 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1147
1148 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1149 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1152}
1153#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
55607e8a 1156struct intel_shared_dpll *
e2b78267
DV		 1157intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158{
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
6e3c9717 1161 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1162 return NULL;
1163
6e3c9717 1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1165}
1166
040484af 1167/* For ILK+ */
55607e8a
DV		 1168void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1170 bool state)
040484af 1171{
040484af 1172 bool cur_state;
5358901f 1173 struct intel_dpll_hw_state hw_state;
040484af 1174
92b27b08 1175 if (WARN (!pll,
46edb027 1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1177 return;
ee7b9f93 1178
5358901f 1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1180 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
040484af 1183}
040484af
JB		 1184
1185static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 int reg;
1189 u32 val;
1190 bool cur_state;
ad80a810
PZ		 1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
040484af 1193
affa9354
PZ		 1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
ad80a810 1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1197 val = I915_READ(reg);
ad80a810 1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1199 } else {
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1203 }
e2c719b7 1204 I915_STATE_WARN(cur_state != state,
040484af
JB		 1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1207}
1208#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1213{
1214 int reg;
1215 u32 val;
1216 bool cur_state;
1217
d63fa0dc
PZ		 1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1221 I915_STATE_WARN(cur_state != state,
040484af
JB		 1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1224}
1225#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* ILK FDI PLL is always enabled */
3d13ef2e 1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1236 return;
1237
bf507ef7 1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1239 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1240 return;
1241
040484af
JB		 1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
e2c719b7 1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1245}
1246
55607e8a
DV		 1247void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
040484af
JB		 1249{
1250 int reg;
1251 u32 val;
55607e8a 1252 bool cur_state;
040484af
JB		 1253
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
55607e8a 1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1257 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
040484af
JB		 1260}
1261
b680c37a
DV		 1262void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
ea0760cf 1264{
bedd4dba
JN		 1265 struct drm_device *dev = dev_priv->dev;
1266 int pp_reg;
ea0760cf
JB		 1267 u32 val;
1268 enum pipe panel_pipe = PIPE_A;
0de3b485 1269 bool locked = true;
ea0760cf 1270
bedd4dba
JN		 1271 if (WARN_ON(HAS_DDI(dev)))
1272 return;
1273
1274 if (HAS_PCH_SPLIT(dev)) {
1275 u32 port_sel;
1276
ea0760cf 1277 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287 panel_pipe = pipe;
ea0760cf
JB		 1288 } else {
1289 pp_reg = PP_CONTROL;
bedd4dba
JN		 1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
ea0760cf
JB		 1292 }
1293
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1297 locked = false;
1298
e2c719b7 1299 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1300 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1301 pipe_name(pipe));
ea0760cf
JB		 1302}
1303
93ce0ba6
JN		 1304static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1306{
1307 struct drm_device *dev = dev_priv->dev;
1308 bool cur_state;
1309
d9d82081 1310 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1312 else
5efb3e28 1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318}
1319#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
b840d907
JB		 1322void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
63d7bbe9 1327 bool cur_state;
702e7a56
PZ		 1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329 pipe);
b24e7179 1330
b6b5d049
VS		 1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1334 state = true;
1335
f458ebbc 1336 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1338 cur_state = false;
1339 } else {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1343 }
1344
e2c719b7 1345 I915_STATE_WARN(cur_state != state,
63d7bbe9 1346 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1347 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1348}
1349
931872fc
CW		 1350static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
b24e7179
JB		 1352{
1353 int reg;
1354 u32 val;
931872fc 1355 bool cur_state;
b24e7179
JB		 1356
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
931872fc 1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1360 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1363}
1364
931872fc
CW		 1365#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
b24e7179
JB		 1368static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
653e1026 1371 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1372 int reg, i;
1373 u32 val;
1374 int cur_pipe;
1375
653e1026
VS		 1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
e2c719b7 1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1381 "plane %c assertion failure, should be disabled but not\n",
1382 plane_name(pipe));
19ec1358 1383 return;
28c05794 1384 }
19ec1358 1385
b24e7179 1386 /* Need to check both planes against the pipe */
055e393f 1387 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1388 reg = DSPCNTR(i);
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1395 }
1396}
1397
19332d7a
JB		 1398static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400{
20674eef 1401 struct drm_device *dev = dev_priv->dev;
1fe47785 1402 int reg, sprite;
19332d7a
JB		 1403 u32 val;
1404
7feb8b88 1405 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1406 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1407 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1411 }
1412 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1413 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1414 reg = SPCNTR(pipe, sprite);
20674eef 1415 val = I915_READ(reg);
e2c719b7 1416 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1418 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1419 }
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1421 reg = SPRCTL(pipe);
19332d7a 1422 val = I915_READ(reg);
e2c719b7 1423 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
19332d7a 1428 val = I915_READ(reg);
e2c719b7 1429 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1431 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1432 }
1433}
1434
08c71e5e
VS		 1435static void assert_vblank_disabled(struct drm_crtc *crtc)
1436{
e2c719b7 1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1438 drm_crtc_vblank_put(crtc);
1439}
1440
89eff4be 1441static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1442{
1443 u32 val;
1444 bool enabled;
1445
e2c719b7 1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1447
92f2584a
JB		 1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1452}
1453
ab9412ba
DV		 1454static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe)
92f2584a
JB		 1456{
1457 int reg;
1458 u32 val;
1459 bool enabled;
1460
ab9412ba 1461 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1464 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 pipe_name(pipe));
92f2584a
JB		 1467}
1468
4e634389
KP		 1469static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1471{
1472 if ((val & DP_PORT_EN) == 0)
1473 return false;
1474
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479 return false;
44f37d1f
CML		 1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482 return false;
f0575e92
KP		 1483 } else {
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 return false;
1486 }
1487 return true;
1488}
1489
1519b995
KP		 1490static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1492{
dc0fa718 1493 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1494 return false;
1495
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1498 return false;
44f37d1f
CML		 1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501 return false;
1519b995 1502 } else {
dc0fa718 1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & LVDS_PORT_EN) == 0)
1513 return false;
1514
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517 return false;
1518 } else {
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 return false;
1521 }
1522 return true;
1523}
1524
1525static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1527{
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1529 return false;
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532 return false;
1533 } else {
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 return false;
1536 }
1537 return true;
1538}
1539
291906f1 1540static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1541 enum pipe pipe, int reg, u32 port_sel)
291906f1 1542{
47a05eca 1543 u32 val = I915_READ(reg);
e2c719b7 1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1546 reg, pipe_name(pipe));
de9a35ab 1547
e2c719b7 1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1549 && (val & DP_PIPEB_SELECT),
de9a35ab 1550 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1551}
1552
1553static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1555{
47a05eca 1556 u32 val = I915_READ(reg);
e2c719b7 1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1559 reg, pipe_name(pipe));
de9a35ab 1560
e2c719b7 1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1562 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1563 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1564}
1565
1566static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568{
1569 int reg;
1570 u32 val;
291906f1 1571
f0575e92
KP		 1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1575
1576 reg = PCH_ADPA;
1577 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 pipe_name(pipe));
291906f1
JB		 1581
1582 reg = PCH_LVDS;
1583 val = I915_READ(reg);
e2c719b7 1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1586 pipe_name(pipe));
291906f1 1587
e2debe91
PZ		 1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1591}
1592
40e9cf64
JB		 1593static void intel_init_dpio(struct drm_device *dev)
1594{
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 if (!IS_VALLEYVIEW(dev))
1598 return;
1599
a09caddd
CML		 1600 /*
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 */
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608 } else {
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610 }
5382f5f3
JB		 1611}
1612
d288f65f 1613static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1614 const struct intel_crtc_state *pipe_config)
87442f73 1615{
426115cf
DV		 1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
d288f65f 1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1620
426115cf 1621 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1622
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1627 if (IS_MOBILE(dev_priv->dev))
426115cf 1628 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1629
426115cf
DV		 1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
d288f65f 1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1638 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1639
1640 /* We do this three times for luck */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
426115cf 1647 I915_WRITE(reg, dpll);
87442f73
DV		 1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650}
1651
d288f65f 1652static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1653 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1654{
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1659 u32 tmp;
1660
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
a580516d 1665 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1666
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
54433e91
VS		 1672 mutex_unlock(&dev_priv->sb_lock);
1673
9d556c99
CML		 1674 /*
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676 */
1677 udelay(1);
1678
1679 /* Enable PLL */
d288f65f 1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1681
1682 /* Check PLL is locked */
a11b0703 1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
a11b0703 1686 /* not sure when this should be written */
d288f65f 1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1688 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1689}
1690
1c4e0274
VS		 1691static int intel_num_dvo_pipes(struct drm_device *dev)
1692{
1693 struct intel_crtc *crtc;
1694 int count = 0;
1695
1696 for_each_intel_crtc(dev, crtc)
3538b9df 1697 count += crtc->base.state->active &&
409ee761 1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1699
1700 return count;
1701}
1702
66e3d5c0 1703static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1704{
66e3d5c0
DV		 1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
6e3c9717 1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1709
66e3d5c0 1710 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1711
63d7bbe9 1712 /* No really, not for ILK+ */
3d13ef2e 1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1714
1715 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1718
1c4e0274
VS		 1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721 /*
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1726 */
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730 }
66e3d5c0
DV		 1731
1732 /* Wait for the clocks to stabilize. */
1733 POSTING_READ(reg);
1734 udelay(150);
1735
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1738 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1739 } else {
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1742 *
1743 * So write it again.
1744 */
1745 I915_WRITE(reg, dpll);
1746 }
63d7bbe9
JB		 1747
1748 /* We do this three times for luck */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
66e3d5c0 1755 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758}
1759
1760/**
50b44a44 1761 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1764 *
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 *
1767 * Note! This is for pre-ILK only.
1768 */
1c4e0274 1769static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1770{
1c4e0274
VS		 1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1774
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1776 if (IS_I830(dev) &&
409ee761 1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1778 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783 }
1784
b6b5d049
VS		 1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1788 return;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
50b44a44
DV		 1793 I915_WRITE(DPLL(pipe), 0);
1794 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1795}
1796
f6071166
JB		 1797static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798{
1799 u32 val = 0;
1800
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1803
e5cbfbfb
ID		 1804 /*
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1807 */
f6071166 1808 if (pipe == PIPE_B)
e5cbfbfb 1809 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1810 I915_WRITE(DPLL(pipe), val);
1811 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1812
1813}
1814
1815static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1816{
d752048d 1817 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1818 u32 val;
1819
a11b0703
VS		 1820 /* Make sure the pipe isn't still relying on us */
1821 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1822
a11b0703 1823 /* Set PLL en = 0 */
d17ec4ce 1824 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1825 if (pipe != PIPE_A)
1826 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827 I915_WRITE(DPLL(pipe), val);
1828 POSTING_READ(DPLL(pipe));
d752048d 1829
a580516d 1830 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1831
1832 /* Disable 10bit clock to display controller */
1833 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834 val &= ~DPIO_DCLKP_EN;
1835 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1836
61407f6d
VS		 1837 /* disable left/right clock distribution */
1838 if (pipe != PIPE_B) {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1842 } else {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1846 }
1847
a580516d 1848 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1849}
1850
e4607fcf 1851void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1852 struct intel_digital_port *dport,
1853 unsigned int expected_mask)
89b667f8
JB		 1854{
1855 u32 port_mask;
00fc31b7 1856 int dpll_reg;
89b667f8 1857
e4607fcf
CML		 1858 switch (dport->port) {
1859 case PORT_B:
89b667f8 1860 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1861 dpll_reg = DPLL(0);
e4607fcf
CML		 1862 break;
1863 case PORT_C:
89b667f8 1864 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1865 dpll_reg = DPLL(0);
9b6de0a1 1866 expected_mask <<= 4;
00fc31b7
CML		 1867 break;
1868 case PORT_D:
1869 port_mask = DPLL_PORTD_READY_MASK;
1870 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1871 break;
1872 default:
1873 BUG();
1874 }
89b667f8 1875
9b6de0a1
VS		 1876 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1879}
1880
b14b1055
DV		 1881static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1882{
1883 struct drm_device *dev = crtc->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1886
be19f0ff
CW		 1887 if (WARN_ON(pll == NULL))
1888 return;
1889
3e369b76 1890 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1891 if (pll->active == 0) {
1892 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1893 WARN_ON(pll->on);
1894 assert_shared_dpll_disabled(dev_priv, pll);
1895
1896 pll->mode_set(dev_priv, pll);
1897 }
1898}
1899
92f2584a 1900/**
85b3894f 1901 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1902 * @dev_priv: i915 private structure
1903 * @pipe: pipe PLL to enable
1904 *
1905 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906 * drives the transcoder clock.
1907 */
85b3894f 1908static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1909{
3d13ef2e
DL		 1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1913
87a875bb 1914 if (WARN_ON(pll == NULL))
48da64a8
CW		 1915 return;
1916
3e369b76 1917 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1918 return;
ee7b9f93 1919
74dd6928 1920 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1921 pll->name, pll->active, pll->on,
e2b78267 1922 crtc->base.base.id);
92f2584a 1923
cdbd2316
DV		 1924 if (pll->active++) {
1925 WARN_ON(!pll->on);
e9d6944e 1926 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1927 return;
1928 }
f4a091c7 1929 WARN_ON(pll->on);
ee7b9f93 1930
bd2bb1b9
PZ		 1931 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1932
46edb027 1933 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1934 pll->enable(dev_priv, pll);
ee7b9f93 1935 pll->on = true;
92f2584a
JB		 1936}
1937
f6daaec2 1938static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1939{
3d13ef2e
DL		 1940 struct drm_device *dev = crtc->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1942 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1943
92f2584a 1944 /* PCH only available on ILK+ */
3d13ef2e 1945 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1946 if (pll == NULL)
1947 return;
92f2584a 1948
eddfcbcd 1949 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1950 return;
7a419866 1951
46edb027
DV		 1952 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953 pll->name, pll->active, pll->on,
e2b78267 1954 crtc->base.base.id);
7a419866 1955
48da64a8 1956 if (WARN_ON(pll->active == 0)) {
e9d6944e 1957 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1958 return;
1959 }
1960
e9d6944e 1961 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1962 WARN_ON(!pll->on);
cdbd2316 1963 if (--pll->active)
7a419866 1964 return;
ee7b9f93 1965
46edb027 1966 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1967 pll->disable(dev_priv, pll);
ee7b9f93 1968 pll->on = false;
bd2bb1b9
PZ		 1969
1970 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1971}
1972
b8a4f404
PZ		 1973static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1974 enum pipe pipe)
040484af 1975{
23670b32 1976 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1977 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1979 uint32_t reg, val, pipeconf_val;
040484af
JB		 1980
1981 /* PCH only available on ILK+ */
55522f37 1982 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1983
1984 /* Make sure PCH DPLL is enabled */
e72f9fbf 1985 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1986 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1987
1988 /* FDI must be feeding us bits for PCH ports */
1989 assert_fdi_tx_enabled(dev_priv, pipe);
1990 assert_fdi_rx_enabled(dev_priv, pipe);
1991
23670b32
DV		 1992 if (HAS_PCH_CPT(dev)) {
1993 /* Workaround: Set the timing override bit before enabling the
1994 * pch transcoder. */
1995 reg = TRANS_CHICKEN2(pipe);
1996 val = I915_READ(reg);
1997 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(reg, val);
59c859d6 1999 }
23670b32 2000
ab9412ba 2001 reg = PCH_TRANSCONF(pipe);
040484af 2002 val = I915_READ(reg);
5f7f726d 2003 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2004
2005 if (HAS_PCH_IBX(dev_priv->dev)) {
2006 /*
c5de7c6f
VS		 2007 * Make the BPC in transcoder be consistent with
2008 * that in pipeconf reg. For HDMI we must use 8bpc
2009 * here for both 8bpc and 12bpc.
e9bcff5c 2010 */
dfd07d72 2011 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2012 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2013 val |= PIPECONF_8BPC;
2014 else
2015 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2016 }
5f7f726d
PZ		 2017
2018 val &= ~TRANS_INTERLACE_MASK;
2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2020 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2021 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2022 val |= TRANS_LEGACY_INTERLACED_ILK;
2023 else
2024 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2025 else
2026 val |= TRANS_PROGRESSIVE;
2027
040484af
JB		 2028 I915_WRITE(reg, val | TRANS_ENABLE);
2029 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2030 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2031}
2032
8fb033d7 2033static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2034 enum transcoder cpu_transcoder)
040484af 2035{
8fb033d7 2036 u32 val, pipeconf_val;
8fb033d7
PZ		 2037
2038 /* PCH only available on ILK+ */
55522f37 2039 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2040
8fb033d7 2041 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2042 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2043 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2044
223a6fdf
PZ		 2045 /* Workaround: set timing override bit. */
2046 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2047 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2048 I915_WRITE(_TRANSA_CHICKEN2, val);
2049
25f3ef11 2050 val = TRANS_ENABLE;
937bb610 2051 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2052
9a76b1c6
PZ		 2053 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054 PIPECONF_INTERLACED_ILK)
a35f2679 2055 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2056 else
2057 val |= TRANS_PROGRESSIVE;
2058
ab9412ba
DV		 2059 I915_WRITE(LPT_TRANSCONF, val);
2060 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2061 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2062}
2063
b8a4f404
PZ		 2064static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2065 enum pipe pipe)
040484af 2066{
23670b32
DV		 2067 struct drm_device *dev = dev_priv->dev;
2068 uint32_t reg, val;
040484af
JB		 2069
2070 /* FDI relies on the transcoder */
2071 assert_fdi_tx_disabled(dev_priv, pipe);
2072 assert_fdi_rx_disabled(dev_priv, pipe);
2073
291906f1
JB		 2074 /* Ports must be off as well */
2075 assert_pch_ports_disabled(dev_priv, pipe);
2076
ab9412ba 2077 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2078 val = I915_READ(reg);
2079 val &= ~TRANS_ENABLE;
2080 I915_WRITE(reg, val);
2081 /* wait for PCH transcoder off, transcoder state */
2082 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2083 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2084
2085 if (!HAS_PCH_IBX(dev)) {
2086 /* Workaround: Clear the timing override chicken bit again. */
2087 reg = TRANS_CHICKEN2(pipe);
2088 val = I915_READ(reg);
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(reg, val);
2091 }
040484af
JB		 2092}
2093
ab4d966c 2094static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2095{
8fb033d7
PZ		 2096 u32 val;
2097
ab9412ba 2098 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2099 val &= ~TRANS_ENABLE;
ab9412ba 2100 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2101 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2102 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2103 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2104
2105 /* Workaround: clear timing override bit. */
2106 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2107 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2108 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2109}
2110
b24e7179 2111/**
309cfea8 2112 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2113 * @crtc: crtc responsible for the pipe
b24e7179 2114 *
0372264a 2115 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2116 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2117 */
e1fdc473 2118static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2119{
0372264a
PZ		 2120 struct drm_device *dev = crtc->base.dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124 pipe);
1a240d4d 2125 enum pipe pch_transcoder;
b24e7179
JB		 2126 int reg;
2127 u32 val;
2128
9e2ee2dd
VS		 2129 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2130
58c6eaa2 2131 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2132 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2133 assert_sprites_disabled(dev_priv, pipe);
2134
681e5811 2135 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2136 pch_transcoder = TRANSCODER_A;
2137 else
2138 pch_transcoder = pipe;
2139
b24e7179
JB		 2140 /*
2141 * A pipe without a PLL won't actually be able to drive bits from
2142 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2143 * need the check.
2144 */
50360403 2145 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2146 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2147 assert_dsi_pll_enabled(dev_priv);
2148 else
2149 assert_pll_enabled(dev_priv, pipe);
040484af 2150 else {
6e3c9717 2151 if (crtc->config->has_pch_encoder) {
040484af 2152 /* if driving the PCH, we need FDI enabled */
cc391bbb 2153 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2154 assert_fdi_tx_pll_enabled(dev_priv,
2155 (enum pipe) cpu_transcoder);
040484af
JB		 2156 }
2157 /* FIXME: assert CPU port conditions for SNB+ */
2158 }
b24e7179 2159
702e7a56 2160 reg = PIPECONF(cpu_transcoder);
b24e7179 2161 val = I915_READ(reg);
7ad25d48 2162 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2163 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2164 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2165 return;
7ad25d48 2166 }
00d70b15
CW		 2167
2168 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2169 POSTING_READ(reg);
b24e7179
JB		 2170}
2171
2172/**
309cfea8 2173 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2174 * @crtc: crtc whose pipes is to be disabled
b24e7179 2175 *
575f7ab7
VS		 2176 * Disable the pipe of @crtc, making sure that various hardware
2177 * specific requirements are met, if applicable, e.g. plane
2178 * disabled, panel fitter off, etc.
b24e7179
JB		 2179 *
2180 * Will wait until the pipe has shut down before returning.
2181 */
575f7ab7 2182static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2183{
575f7ab7 2184 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2185 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2186 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2187 int reg;
2188 u32 val;
2189
9e2ee2dd
VS		 2190 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2191
b24e7179
JB		 2192 /*
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2195 */
2196 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2197 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2198 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2199
702e7a56 2200 reg = PIPECONF(cpu_transcoder);
b24e7179 2201 val = I915_READ(reg);
00d70b15
CW		 2202 if ((val & PIPECONF_ENABLE) == 0)
2203 return;
2204
67adc644
VS		 2205 /*
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2208 */
6e3c9717 2209 if (crtc->config->double_wide)
67adc644
VS		 2210 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2215 val &= ~PIPECONF_ENABLE;
2216
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2220}
2221
693db184
CW		 2222static bool need_vtd_wa(struct drm_device *dev)
2223{
2224#ifdef CONFIG_INTEL_IOMMU
2225 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2226 return true;
2227#endif
2228 return false;
2229}
2230
50470bb0 2231unsigned int
6761dd31
TU		 2232intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2233 uint64_t fb_format_modifier)
a57ce0b2 2234{
6761dd31
TU		 2235 unsigned int tile_height;
2236 uint32_t pixel_bytes;
a57ce0b2 2237
b5d0e9bf
DL		 2238 switch (fb_format_modifier) {
2239 case DRM_FORMAT_MOD_NONE:
2240 tile_height = 1;
2241 break;
2242 case I915_FORMAT_MOD_X_TILED:
2243 tile_height = IS_GEN2(dev) ? 16 : 8;
2244 break;
2245 case I915_FORMAT_MOD_Y_TILED:
2246 tile_height = 32;
2247 break;
2248 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2249 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2250 switch (pixel_bytes) {
b5d0e9bf 2251 default:
6761dd31 2252 case 1:
b5d0e9bf
DL		 2253 tile_height = 64;
2254 break;
6761dd31
TU		 2255 case 2:
2256 case 4:
b5d0e9bf
DL		 2257 tile_height = 32;
2258 break;
6761dd31 2259 case 8:
b5d0e9bf
DL		 2260 tile_height = 16;
2261 break;
6761dd31 2262 case 16:
b5d0e9bf
DL		 2263 WARN_ONCE(1,
2264 "128-bit pixels are not supported for display!");
2265 tile_height = 16;
2266 break;
2267 }
2268 break;
2269 default:
2270 MISSING_CASE(fb_format_modifier);
2271 tile_height = 1;
2272 break;
2273 }
091df6cb 2274
6761dd31
TU		 2275 return tile_height;
2276}
2277
2278unsigned int
2279intel_fb_align_height(struct drm_device *dev, unsigned int height,
2280 uint32_t pixel_format, uint64_t fb_format_modifier)
2281{
2282 return ALIGN(height, intel_tile_height(dev, pixel_format,
2283 fb_format_modifier));
a57ce0b2
JB		 2284}
2285
f64b98cd
TU		 2286static int
2287intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2288 const struct drm_plane_state *plane_state)
2289{
50470bb0 2290 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2291 unsigned int tile_height, tile_pitch;
50470bb0 2292
f64b98cd
TU		 2293 *view = i915_ggtt_view_normal;
2294
50470bb0
TU		 2295 if (!plane_state)
2296 return 0;
2297
121920fa 2298 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2299 return 0;
2300
9abc4648 2301 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2302
2303 info->height = fb->height;
2304 info->pixel_format = fb->pixel_format;
2305 info->pitch = fb->pitches[0];
2306 info->fb_modifier = fb->modifier[0];
2307
84fe03f7
TU		 2308 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2309 fb->modifier[0]);
2310 tile_pitch = PAGE_SIZE / tile_height;
2311 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2312 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2313 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2314
f64b98cd
TU		 2315 return 0;
2316}
2317
4e9a86b6
VS		 2318static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2319{
2320 if (INTEL_INFO(dev_priv)->gen >= 9)
2321 return 256 * 1024;
985b8bb4
VS		 2322 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2323 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2324 return 128 * 1024;
2325 else if (INTEL_INFO(dev_priv)->gen >= 4)
2326 return 4 * 1024;
2327 else
44c5905e 2328 return 0;
4e9a86b6
VS		 2329}
2330
127bd2ac 2331int
850c4cdc
TU		 2332intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2333 struct drm_framebuffer *fb,
82bc3b2d 2334 const struct drm_plane_state *plane_state,
91af127f
JH		 2335 struct intel_engine_cs *pipelined,
2336 struct drm_i915_gem_request **pipelined_request)
6b95a207 2337{
850c4cdc 2338 struct drm_device *dev = fb->dev;
ce453d81 2339 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2340 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2341 struct i915_ggtt_view view;
6b95a207
KH		 2342 u32 alignment;
2343 int ret;
2344
ebcdd39e
MR		 2345 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346
7b911adc
TU		 2347 switch (fb->modifier[0]) {
2348 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2349 alignment = intel_linear_alignment(dev_priv);
6b95a207 2350 break;
7b911adc 2351 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2352 if (INTEL_INFO(dev)->gen >= 9)
2353 alignment = 256 * 1024;
2354 else {
2355 /* pin() will align the object as required by fence */
2356 alignment = 0;
2357 }
6b95a207 2358 break;
7b911adc 2359 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2360 case I915_FORMAT_MOD_Yf_TILED:
2361 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362 "Y tiling bo slipped through, driver bug!\n"))
2363 return -EINVAL;
2364 alignment = 1 * 1024 * 1024;
2365 break;
6b95a207 2366 default:
7b911adc
TU		 2367 MISSING_CASE(fb->modifier[0]);
2368 return -EINVAL;
6b95a207
KH		 2369 }
2370
f64b98cd
TU		 2371 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2372 if (ret)
2373 return ret;
2374
693db184
CW		 2375 /* Note that the w/a also requires 64 PTE of padding following the
2376 * bo. We currently fill all unused PTE with the shadow page and so
2377 * we should always have valid PTE following the scanout preventing
2378 * the VT-d warning.
2379 */
2380 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381 alignment = 256 * 1024;
2382
d6dd6843
PZ		 2383 /*
2384 * Global gtt pte registers are special registers which actually forward
2385 * writes to a chunk of system memory. Which means that there is no risk
2386 * that the register values disappear as soon as we call
2387 * intel_runtime_pm_put(), so it is correct to wrap only the
2388 * pin/unpin/fence and not more.
2389 */
2390 intel_runtime_pm_get(dev_priv);
2391
ce453d81 2392 dev_priv->mm.interruptible = false;
e6617330 2393 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2394 pipelined_request, &view);
48b956c5 2395 if (ret)
ce453d81 2396 goto err_interruptible;
6b95a207
KH		 2397
2398 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399 * fence, whereas 965+ only requires a fence if using
2400 * framebuffer compression. For simplicity, we always install
2401 * a fence as the cost is not that onerous.
2402 */
06d98131 2403 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2404 if (ret)
2405 goto err_unpin;
1690e1eb 2406
9a5a53b3 2407 i915_gem_object_pin_fence(obj);
6b95a207 2408
ce453d81 2409 dev_priv->mm.interruptible = true;
d6dd6843 2410 intel_runtime_pm_put(dev_priv);
6b95a207 2411 return 0;
48b956c5
CW		 2412
2413err_unpin:
f64b98cd 2414 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2415err_interruptible:
2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
48b956c5 2418 return ret;
6b95a207
KH		 2419}
2420
82bc3b2d
TU		 2421static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
1690e1eb 2423{
82bc3b2d 2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2425 struct i915_ggtt_view view;
2426 int ret;
82bc3b2d 2427
ebcdd39e
MR		 2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
f64b98cd
TU		 2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
1690e1eb 2433 i915_gem_object_unpin_fence(obj);
f64b98cd 2434 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2435}
2436
c2c75131
DV		 2437/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2439unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2440 int *x, int *y,
bc752862
CW		 2441 unsigned int tiling_mode,
2442 unsigned int cpp,
2443 unsigned int pitch)
c2c75131 2444{
bc752862
CW		 2445 if (tiling_mode != I915_TILING_NONE) {
2446 unsigned int tile_rows, tiles;
c2c75131 2447
bc752862
CW		 2448 tile_rows = *y / 8;
2449 *y %= 8;
c2c75131 2450
bc752862
CW		 2451 tiles = *x / (512/cpp);
2452 *x %= 512/cpp;
2453
2454 return tile_rows * pitch * 8 + tiles * 4096;
2455 } else {
4e9a86b6 2456 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2457 unsigned int offset;
2458
2459 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2460 *y = (offset & alignment) / pitch;
2461 *x = ((offset & alignment) - *y * pitch) / cpp;
2462 return offset & ~alignment;
bc752862 2463 }
c2c75131
DV		 2464}
2465
b35d63fa 2466static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2467{
2468 switch (format) {
2469 case DISPPLANE_8BPP:
2470 return DRM_FORMAT_C8;
2471 case DISPPLANE_BGRX555:
2472 return DRM_FORMAT_XRGB1555;
2473 case DISPPLANE_BGRX565:
2474 return DRM_FORMAT_RGB565;
2475 default:
2476 case DISPPLANE_BGRX888:
2477 return DRM_FORMAT_XRGB8888;
2478 case DISPPLANE_RGBX888:
2479 return DRM_FORMAT_XBGR8888;
2480 case DISPPLANE_BGRX101010:
2481 return DRM_FORMAT_XRGB2101010;
2482 case DISPPLANE_RGBX101010:
2483 return DRM_FORMAT_XBGR2101010;
2484 }
2485}
2486
bc8d7dff
DL		 2487static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2488{
2489 switch (format) {
2490 case PLANE_CTL_FORMAT_RGB_565:
2491 return DRM_FORMAT_RGB565;
2492 default:
2493 case PLANE_CTL_FORMAT_XRGB_8888:
2494 if (rgb_order) {
2495 if (alpha)
2496 return DRM_FORMAT_ABGR8888;
2497 else
2498 return DRM_FORMAT_XBGR8888;
2499 } else {
2500 if (alpha)
2501 return DRM_FORMAT_ARGB8888;
2502 else
2503 return DRM_FORMAT_XRGB8888;
2504 }
2505 case PLANE_CTL_FORMAT_XRGB_2101010:
2506 if (rgb_order)
2507 return DRM_FORMAT_XBGR2101010;
2508 else
2509 return DRM_FORMAT_XRGB2101010;
2510 }
2511}
2512
5724dbd1 2513static bool
f6936e29
DV		 2514intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2516{
2517 struct drm_device *dev = crtc->base.dev;
2518 struct drm_i915_gem_object *obj = NULL;
2519 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2520 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2521 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2522 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2523 PAGE_SIZE);
2524
2525 size_aligned -= base_aligned;
46f297fb 2526
ff2652ea
CW		 2527 if (plane_config->size == 0)
2528 return false;
2529
f37b5c2b
DV		 2530 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2531 base_aligned,
2532 base_aligned,
2533 size_aligned);
46f297fb 2534 if (!obj)
484b41dd 2535 return false;
46f297fb 2536
49af449b
DL		 2537 obj->tiling_mode = plane_config->tiling;
2538 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2539 obj->stride = fb->pitches[0];
46f297fb 2540
6bf129df
DL		 2541 mode_cmd.pixel_format = fb->pixel_format;
2542 mode_cmd.width = fb->width;
2543 mode_cmd.height = fb->height;
2544 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2545 mode_cmd.modifier[0] = fb->modifier[0];
2546 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2547
2548 mutex_lock(&dev->struct_mutex);
6bf129df 2549 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2550 &mode_cmd, obj)) {
46f297fb
JB		 2551 DRM_DEBUG_KMS("intel fb init failed\n");
2552 goto out_unref_obj;
2553 }
46f297fb 2554 mutex_unlock(&dev->struct_mutex);
484b41dd 2555
f6936e29 2556 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2557 return true;
46f297fb
JB		 2558
2559out_unref_obj:
2560 drm_gem_object_unreference(&obj->base);
2561 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2562 return false;
2563}
2564
afd65eb4
MR		 2565/* Update plane->state->fb to match plane->fb after driver-internal updates */
2566static void
2567update_state_fb(struct drm_plane *plane)
2568{
2569 if (plane->fb == plane->state->fb)
2570 return;
2571
2572 if (plane->state->fb)
2573 drm_framebuffer_unreference(plane->state->fb);
2574 plane->state->fb = plane->fb;
2575 if (plane->state->fb)
2576 drm_framebuffer_reference(plane->state->fb);
2577}
2578
5724dbd1 2579static void
f6936e29
DV		 2580intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2581 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2582{
2583 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2584 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2585 struct drm_crtc *c;
2586 struct intel_crtc *i;
2ff8fde1 2587 struct drm_i915_gem_object *obj;
88595ac9
DV		 2588 struct drm_plane *primary = intel_crtc->base.primary;
2589 struct drm_framebuffer *fb;
484b41dd 2590
2d14030b 2591 if (!plane_config->fb)
484b41dd
JB		 2592 return;
2593
f6936e29 2594 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2595 fb = &plane_config->fb->base;
2596 goto valid_fb;
f55548b5 2597 }
484b41dd 2598
2d14030b 2599 kfree(plane_config->fb);
484b41dd
JB		 2600
2601 /*
2602 * Failed to alloc the obj, check to see if we should share
2603 * an fb with another CRTC instead
2604 */
70e1e0ec 2605 for_each_crtc(dev, c) {
484b41dd
JB		 2606 i = to_intel_crtc(c);
2607
2608 if (c == &intel_crtc->base)
2609 continue;
2610
2ff8fde1
MR		 2611 if (!i->active)
2612 continue;
2613
88595ac9
DV		 2614 fb = c->primary->fb;
2615 if (!fb)
484b41dd
JB		 2616 continue;
2617
88595ac9 2618 obj = intel_fb_obj(fb);
2ff8fde1 2619 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2620 drm_framebuffer_reference(fb);
2621 goto valid_fb;
484b41dd
JB		 2622 }
2623 }
88595ac9
DV		 2624
2625 return;
2626
2627valid_fb:
2628 obj = intel_fb_obj(fb);
2629 if (obj->tiling_mode != I915_TILING_NONE)
2630 dev_priv->preserve_bios_swizzle = true;
2631
2632 primary->fb = fb;
36750f28 2633 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2634 update_state_fb(primary);
36750f28 2635 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2636 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2637}
2638
29b9bde6
DV		 2639static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2640 struct drm_framebuffer *fb,
2641 int x, int y)
81255565
JB		 2642{
2643 struct drm_device *dev = crtc->dev;
2644 struct drm_i915_private *dev_priv = dev->dev_private;
2645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2646 struct drm_plane *primary = crtc->primary;
2647 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2648 struct drm_i915_gem_object *obj;
81255565 2649 int plane = intel_crtc->plane;
e506a0c6 2650 unsigned long linear_offset;
81255565 2651 u32 dspcntr;
f45651ba 2652 u32 reg = DSPCNTR(plane);
48404c1e 2653 int pixel_size;
f45651ba 2654
b70709a6 2655 if (!visible || !fb) {
fdd508a6
VS		 2656 I915_WRITE(reg, 0);
2657 if (INTEL_INFO(dev)->gen >= 4)
2658 I915_WRITE(DSPSURF(plane), 0);
2659 else
2660 I915_WRITE(DSPADDR(plane), 0);
2661 POSTING_READ(reg);
2662 return;
2663 }
2664
c9ba6fad
VS		 2665 obj = intel_fb_obj(fb);
2666 if (WARN_ON(obj == NULL))
2667 return;
2668
2669 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2670
f45651ba
VS		 2671 dspcntr = DISPPLANE_GAMMA_ENABLE;
2672
fdd508a6 2673 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2674
2675 if (INTEL_INFO(dev)->gen < 4) {
2676 if (intel_crtc->pipe == PIPE_B)
2677 dspcntr |= DISPPLANE_SEL_PIPE_B;
2678
2679 /* pipesrc and dspsize control the size that is scaled from,
2680 * which should always be the user's requested size.
2681 */
2682 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2683 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2684 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2685 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2686 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2687 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2690 I915_WRITE(PRIMPOS(plane), 0);
2691 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2692 }
81255565 2693
57779d06
VS		 2694 switch (fb->pixel_format) {
2695 case DRM_FORMAT_C8:
81255565
JB		 2696 dspcntr |= DISPPLANE_8BPP;
2697 break;
57779d06 2698 case DRM_FORMAT_XRGB1555:
57779d06 2699 dspcntr |= DISPPLANE_BGRX555;
81255565 2700 break;
57779d06
VS		 2701 case DRM_FORMAT_RGB565:
2702 dspcntr |= DISPPLANE_BGRX565;
2703 break;
2704 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2705 dspcntr |= DISPPLANE_BGRX888;
2706 break;
2707 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2708 dspcntr |= DISPPLANE_RGBX888;
2709 break;
2710 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2711 dspcntr |= DISPPLANE_BGRX101010;
2712 break;
2713 case DRM_FORMAT_XBGR2101010:
57779d06 2714 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2715 break;
2716 default:
baba133a 2717 BUG();
81255565 2718 }
57779d06 2719
f45651ba
VS		 2720 if (INTEL_INFO(dev)->gen >= 4 &&
2721 obj->tiling_mode != I915_TILING_NONE)
2722 dspcntr |= DISPPLANE_TILED;
81255565 2723
de1aa629
VS		 2724 if (IS_G4X(dev))
2725 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2726
b9897127 2727 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2728
c2c75131
DV		 2729 if (INTEL_INFO(dev)->gen >= 4) {
2730 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2731 intel_gen4_compute_page_offset(dev_priv,
2732 &x, &y, obj->tiling_mode,
b9897127 2733 pixel_size,
bc752862 2734 fb->pitches[0]);
c2c75131
DV		 2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
e506a0c6 2737 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2738 }
e506a0c6 2739
8e7d688b 2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
6e3c9717
ACO		 2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
6e3c9717
ACO		 2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
01f2c773 2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2756 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2761 } else
f343c5f6 2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2763 POSTING_READ(reg);
17638cd6
JB		 2764}
2765
29b9bde6
DV		 2766static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
17638cd6
JB		 2769{
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2773 struct drm_plane *primary = crtc->primary;
2774 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2775 struct drm_i915_gem_object *obj;
17638cd6 2776 int plane = intel_crtc->plane;
e506a0c6 2777 unsigned long linear_offset;
17638cd6 2778 u32 dspcntr;
f45651ba 2779 u32 reg = DSPCNTR(plane);
48404c1e 2780 int pixel_size;
f45651ba 2781
b70709a6 2782 if (!visible || !fb) {
fdd508a6
VS		 2783 I915_WRITE(reg, 0);
2784 I915_WRITE(DSPSURF(plane), 0);
2785 POSTING_READ(reg);
2786 return;
2787 }
2788
c9ba6fad
VS		 2789 obj = intel_fb_obj(fb);
2790 if (WARN_ON(obj == NULL))
2791 return;
2792
2793 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
f45651ba
VS		 2795 dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
fdd508a6 2797 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2798
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2801
57779d06
VS		 2802 switch (fb->pixel_format) {
2803 case DRM_FORMAT_C8:
17638cd6
JB		 2804 dspcntr |= DISPPLANE_8BPP;
2805 break;
57779d06
VS		 2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2808 break;
57779d06 2809 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2816 dspcntr |= DISPPLANE_BGRX101010;
2817 break;
2818 case DRM_FORMAT_XBGR2101010:
57779d06 2819 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2820 break;
2821 default:
baba133a 2822 BUG();
17638cd6
JB		 2823 }
2824
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
17638cd6 2827
f45651ba 2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2830
b9897127 2831 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2832 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2833 intel_gen4_compute_page_offset(dev_priv,
2834 &x, &y, obj->tiling_mode,
b9897127 2835 pixel_size,
bc752862 2836 fb->pitches[0]);
c2c75131 2837 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2838 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2839 dspcntr |= DISPPLANE_ROTATE_180;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2842 x += (intel_crtc->config->pipe_src_w - 1);
2843 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2844
2845 /* Finding the last pixel of the last line of the display
2846 data and adding to linear_offset*/
2847 linear_offset +=
6e3c9717
ACO		 2848 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2850 }
2851 }
2852
2853 I915_WRITE(reg, dspcntr);
17638cd6 2854
01f2c773 2855 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2856 I915_WRITE(DSPSURF(plane),
2857 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2858 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2859 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2860 } else {
2861 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862 I915_WRITE(DSPLINOFF(plane), linear_offset);
2863 }
17638cd6 2864 POSTING_READ(reg);
17638cd6
JB		 2865}
2866
b321803d
DL		 2867u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868 uint32_t pixel_format)
2869{
2870 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871
2872 /*
2873 * The stride is either expressed as a multiple of 64 bytes
2874 * chunks for linear buffers or in number of tiles for tiled
2875 * buffers.
2876 */
2877 switch (fb_modifier) {
2878 case DRM_FORMAT_MOD_NONE:
2879 return 64;
2880 case I915_FORMAT_MOD_X_TILED:
2881 if (INTEL_INFO(dev)->gen == 2)
2882 return 128;
2883 return 512;
2884 case I915_FORMAT_MOD_Y_TILED:
2885 /* No need to check for old gens and Y tiling since this is
2886 * about the display engine and those will be blocked before
2887 * we get here.
2888 */
2889 return 128;
2890 case I915_FORMAT_MOD_Yf_TILED:
2891 if (bits_per_pixel == 8)
2892 return 64;
2893 else
2894 return 128;
2895 default:
2896 MISSING_CASE(fb_modifier);
2897 return 64;
2898 }
2899}
2900
121920fa
TU		 2901unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902 struct drm_i915_gem_object *obj)
2903{
9abc4648 2904 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2905
2906 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2907 view = &i915_ggtt_view_rotated;
121920fa
TU		 2908
2909 return i915_gem_obj_ggtt_offset_view(obj, view);
2910}
2911
a1b2278e
CK		 2912/*
2913 * This function detaches (aka. unbinds) unused scalers in hardware
2914 */
0583236e 2915static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e
CK		 2916{
2917 struct drm_device *dev;
2918 struct drm_i915_private *dev_priv;
2919 struct intel_crtc_scaler_state *scaler_state;
2920 int i;
2921
a1b2278e
CK		 2922 dev = intel_crtc->base.dev;
2923 dev_priv = dev->dev_private;
2924 scaler_state = &intel_crtc->config->scaler_state;
2925
2926 /* loop through and disable scalers that aren't in use */
2927 for (i = 0; i < intel_crtc->num_scalers; i++) {
2928 if (!scaler_state->scalers[i].in_use) {
2929 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2930 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2931 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2932 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2933 intel_crtc->base.base.id, intel_crtc->pipe, i);
2934 }
2935 }
2936}
2937
6156a456 2938u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2939{
6156a456 2940 switch (pixel_format) {
d161cf7a 2941 case DRM_FORMAT_C8:
c34ce3d1 2942 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2943 case DRM_FORMAT_RGB565:
c34ce3d1 2944 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2945 case DRM_FORMAT_XBGR8888:
c34ce3d1 2946 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2947 case DRM_FORMAT_XRGB8888:
c34ce3d1 2948 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2949 /*
2950 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2951 * to be already pre-multiplied. We need to add a knob (or a different
2952 * DRM_FORMAT) for user-space to configure that.
2953 */
f75fb42a 2954 case DRM_FORMAT_ABGR8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2957 case DRM_FORMAT_ARGB8888:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2959 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2960 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2962 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2963 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2964 case DRM_FORMAT_YUYV:
c34ce3d1 2965 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2966 case DRM_FORMAT_YVYU:
c34ce3d1 2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2968 case DRM_FORMAT_UYVY:
c34ce3d1 2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2970 case DRM_FORMAT_VYUY:
c34ce3d1 2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2972 default:
4249eeef 2973 MISSING_CASE(pixel_format);
70d21f0e 2974 }
8cfcba41 2975
c34ce3d1 2976 return 0;
6156a456 2977}
70d21f0e 2978
6156a456
CK		 2979u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2980{
6156a456 2981 switch (fb_modifier) {
30af77c4 2982 case DRM_FORMAT_MOD_NONE:
70d21f0e 2983 break;
30af77c4 2984 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2985 return PLANE_CTL_TILED_X;
b321803d 2986 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2987 return PLANE_CTL_TILED_Y;
b321803d 2988 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2989 return PLANE_CTL_TILED_YF;
70d21f0e 2990 default:
6156a456 2991 MISSING_CASE(fb_modifier);
70d21f0e 2992 }
8cfcba41 2993
c34ce3d1 2994 return 0;
6156a456 2995}
70d21f0e 2996
6156a456
CK		 2997u32 skl_plane_ctl_rotation(unsigned int rotation)
2998{
3b7a5119 2999 switch (rotation) {
6156a456
CK		 3000 case BIT(DRM_ROTATE_0):
3001 break;
1e8df167
SJ		 3002 /*
3003 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3004 * while i915 HW rotation is clockwise, thats why this swapping.
3005 */
3b7a5119 3006 case BIT(DRM_ROTATE_90):
1e8df167 3007 return PLANE_CTL_ROTATE_270;
3b7a5119 3008 case BIT(DRM_ROTATE_180):
c34ce3d1 3009 return PLANE_CTL_ROTATE_180;
3b7a5119 3010 case BIT(DRM_ROTATE_270):
1e8df167 3011 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3012 default:
3013 MISSING_CASE(rotation);
3014 }
3015
c34ce3d1 3016 return 0;
6156a456
CK		 3017}
3018
3019static void skylake_update_primary_plane(struct drm_crtc *crtc,
3020 struct drm_framebuffer *fb,
3021 int x, int y)
3022{
3023 struct drm_device *dev = crtc->dev;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3026 struct drm_plane *plane = crtc->primary;
3027 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3028 struct drm_i915_gem_object *obj;
3029 int pipe = intel_crtc->pipe;
3030 u32 plane_ctl, stride_div, stride;
3031 u32 tile_height, plane_offset, plane_size;
3032 unsigned int rotation;
3033 int x_offset, y_offset;
3034 unsigned long surf_addr;
6156a456
CK		 3035 struct intel_crtc_state *crtc_state = intel_crtc->config;
3036 struct intel_plane_state *plane_state;
3037 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3038 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3039 int scaler_id = -1;
3040
6156a456
CK		 3041 plane_state = to_intel_plane_state(plane->state);
3042
b70709a6 3043 if (!visible || !fb) {
6156a456
CK		 3044 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3045 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3046 POSTING_READ(PLANE_CTL(pipe, 0));
3047 return;
3b7a5119 3048 }
70d21f0e 3049
6156a456
CK		 3050 plane_ctl = PLANE_CTL_ENABLE |
3051 PLANE_CTL_PIPE_GAMMA_ENABLE |
3052 PLANE_CTL_PIPE_CSC_ENABLE;
3053
3054 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3055 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3056 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3057
3058 rotation = plane->state->rotation;
3059 plane_ctl |= skl_plane_ctl_rotation(rotation);
3060
b321803d
DL		 3061 obj = intel_fb_obj(fb);
3062 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3063 fb->pixel_format);
3b7a5119
SJ		 3064 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3065
6156a456
CK		 3066 /*
3067 * FIXME: intel_plane_state->src, dst aren't set when transitional
3068 * update_plane helpers are called from legacy paths.
3069 * Once full atomic crtc is available, below check can be avoided.
3070 */
3071 if (drm_rect_width(&plane_state->src)) {
3072 scaler_id = plane_state->scaler_id;
3073 src_x = plane_state->src.x1 >> 16;
3074 src_y = plane_state->src.y1 >> 16;
3075 src_w = drm_rect_width(&plane_state->src) >> 16;
3076 src_h = drm_rect_height(&plane_state->src) >> 16;
3077 dst_x = plane_state->dst.x1;
3078 dst_y = plane_state->dst.y1;
3079 dst_w = drm_rect_width(&plane_state->dst);
3080 dst_h = drm_rect_height(&plane_state->dst);
3081
3082 WARN_ON(x != src_x || y != src_y);
3083 } else {
3084 src_w = intel_crtc->config->pipe_src_w;
3085 src_h = intel_crtc->config->pipe_src_h;
3086 }
3087
3b7a5119
SJ		 3088 if (intel_rotation_90_or_270(rotation)) {
3089 /* stride = Surface height in tiles */
2614f17d 3090 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3091 fb->modifier[0]);
3092 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3093 x_offset = stride * tile_height - y - src_h;
3b7a5119 3094 y_offset = x;
6156a456 3095 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3096 } else {
3097 stride = fb->pitches[0] / stride_div;
3098 x_offset = x;
3099 y_offset = y;
6156a456 3100 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3101 }
3102 plane_offset = y_offset << 16 | x_offset;
b321803d 3103
70d21f0e 3104 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3105 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3106 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3107 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3108
3109 if (scaler_id >= 0) {
3110 uint32_t ps_ctrl = 0;
3111
3112 WARN_ON(!dst_w || !dst_h);
3113 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3114 crtc_state->scaler_state.scalers[scaler_id].mode;
3115 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3116 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3117 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3118 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3119 I915_WRITE(PLANE_POS(pipe, 0), 0);
3120 } else {
3121 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3122 }
3123
121920fa 3124 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3125
3126 POSTING_READ(PLANE_SURF(pipe, 0));
3127}
3128
17638cd6
JB		 3129/* Assume fb object is pinned & idle & fenced and just update base pointers */
3130static int
3131intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3132 int x, int y, enum mode_set_atomic state)
3133{
3134 struct drm_device *dev = crtc->dev;
3135 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3136
6b8e6ed0
CW		 3137 if (dev_priv->display.disable_fbc)
3138 dev_priv->display.disable_fbc(dev);
81255565 3139
29b9bde6
DV		 3140 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3141
3142 return 0;
81255565
JB		 3143}
3144
7514747d 3145static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3146{
96a02917
VS		 3147 struct drm_crtc *crtc;
3148
70e1e0ec 3149 for_each_crtc(dev, crtc) {
96a02917
VS		 3150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151 enum plane plane = intel_crtc->plane;
3152
3153 intel_prepare_page_flip(dev, plane);
3154 intel_finish_page_flip_plane(dev, plane);
3155 }
7514747d
VS		 3156}
3157
3158static void intel_update_primary_planes(struct drm_device *dev)
3159{
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 struct drm_crtc *crtc;
96a02917 3162
70e1e0ec 3163 for_each_crtc(dev, crtc) {
96a02917
VS		 3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165
51fd371b 3166 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3167 /*
3168 * FIXME: Once we have proper support for primary planes (and
3169 * disabling them without disabling the entire crtc) allow again
66e514c1 3170 * a NULL crtc->primary->fb.
947fdaad 3171 */
f4510a27 3172 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3173 dev_priv->display.update_primary_plane(crtc,
66e514c1 3174 crtc->primary->fb,
262ca2b0
MR		 3175 crtc->x,
3176 crtc->y);
51fd371b 3177 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3178 }
3179}
3180
7514747d
VS		 3181void intel_prepare_reset(struct drm_device *dev)
3182{
3183 /* no reset support for gen2 */
3184 if (IS_GEN2(dev))
3185 return;
3186
3187 /* reset doesn't touch the display */
3188 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3189 return;
3190
3191 drm_modeset_lock_all(dev);
f98ce92f
VS		 3192 /*
3193 * Disabling the crtcs gracefully seems nicer. Also the
3194 * g33 docs say we should at least disable all the planes.
3195 */
6b72d486 3196 intel_display_suspend(dev);
7514747d
VS		 3197}
3198
3199void intel_finish_reset(struct drm_device *dev)
3200{
3201 struct drm_i915_private *dev_priv = to_i915(dev);
3202
3203 /*
3204 * Flips in the rings will be nuked by the reset,
3205 * so complete all pending flips so that user space
3206 * will get its events and not get stuck.
3207 */
3208 intel_complete_page_flips(dev);
3209
3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3216 /*
3217 * Flips in the rings have been nuked by the reset,
3218 * so update the base address of all primary
3219 * planes to the the last fb to make sure we're
3220 * showing the correct fb after a reset.
3221 */
3222 intel_update_primary_planes(dev);
3223 return;
3224 }
3225
3226 /*
3227 * The display has been reset as well,
3228 * so need a full re-initialization.
3229 */
3230 intel_runtime_pm_disable_interrupts(dev_priv);
3231 intel_runtime_pm_enable_interrupts(dev_priv);
3232
3233 intel_modeset_init_hw(dev);
3234
3235 spin_lock_irq(&dev_priv->irq_lock);
3236 if (dev_priv->display.hpd_irq_setup)
3237 dev_priv->display.hpd_irq_setup(dev);
3238 spin_unlock_irq(&dev_priv->irq_lock);
3239
3240 intel_modeset_setup_hw_state(dev, true);
3241
3242 intel_hpd_init(dev_priv);
3243
3244 drm_modeset_unlock_all(dev);
3245}
3246
2e2f351d 3247static void
14667a4b
CW		 3248intel_finish_fb(struct drm_framebuffer *old_fb)
3249{
2ff8fde1 3250 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3251 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3252 bool was_interruptible = dev_priv->mm.interruptible;
3253 int ret;
3254
14667a4b
CW		 3255 /* Big Hammer, we also need to ensure that any pending
3256 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3257 * current scanout is retired before unpinning the old
2e2f351d
CW		 3258 * framebuffer. Note that we rely on userspace rendering
3259 * into the buffer attached to the pipe they are waiting
3260 * on. If not, userspace generates a GPU hang with IPEHR
3261 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3262 *
3263 * This should only fail upon a hung GPU, in which case we
3264 * can safely continue.
3265 */
3266 dev_priv->mm.interruptible = false;
2e2f351d 3267 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3268 dev_priv->mm.interruptible = was_interruptible;
3269
2e2f351d 3270 WARN_ON(ret);
14667a4b
CW		 3271}
3272
7d5e3799
CW		 3273static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3274{
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3278 bool pending;
3279
3280 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3281 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3282 return false;
3283
5e2d7afc 3284 spin_lock_irq(&dev->event_lock);
7d5e3799 3285 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3286 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3287
3288 return pending;
3289}
3290
e30e8f75
GP		 3291static void intel_update_pipe_size(struct intel_crtc *crtc)
3292{
3293 struct drm_device *dev = crtc->base.dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 const struct drm_display_mode *adjusted_mode;
3296
3297 if (!i915.fastboot)
3298 return;
3299
3300 /*
3301 * Update pipe size and adjust fitter if needed: the reason for this is
3302 * that in compute_mode_changes we check the native mode (not the pfit
3303 * mode) to see if we can flip rather than do a full mode set. In the
3304 * fastboot case, we'll flip, but if we don't update the pipesrc and
3305 * pfit state, we'll end up with a big fb scanned out into the wrong
3306 * sized surface.
3307 *
3308 * To fix this properly, we need to hoist the checks up into
3309 * compute_mode_changes (or above), check the actual pfit state and
3310 * whether the platform allows pfit disable with pipe active, and only
3311 * then update the pipesrc and pfit state, even on the flip path.
3312 */
3313
6e3c9717 3314 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3315
3316 I915_WRITE(PIPESRC(crtc->pipe),
3317 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3318 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3319 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3320 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3321 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3322 I915_WRITE(PF_CTL(crtc->pipe), 0);
3323 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3324 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3325 }
6e3c9717
ACO		 3326 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3327 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3328}
3329
5e84e1a4
ZW		 3330static void intel_fdi_normal_train(struct drm_crtc *crtc)
3331{
3332 struct drm_device *dev = crtc->dev;
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335 int pipe = intel_crtc->pipe;
3336 u32 reg, temp;
3337
3338 /* enable normal train */
3339 reg = FDI_TX_CTL(pipe);
3340 temp = I915_READ(reg);
61e499bf 3341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3344 } else {
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3347 }
5e84e1a4
ZW		 3348 I915_WRITE(reg, temp);
3349
3350 reg = FDI_RX_CTL(pipe);
3351 temp = I915_READ(reg);
3352 if (HAS_PCH_CPT(dev)) {
3353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3355 } else {
3356 temp &= ~FDI_LINK_TRAIN_NONE;
3357 temp |= FDI_LINK_TRAIN_NONE;
3358 }
3359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3360
3361 /* wait one idle pattern time */
3362 POSTING_READ(reg);
3363 udelay(1000);
357555c0
JB		 3364
3365 /* IVB wants error correction enabled */
3366 if (IS_IVYBRIDGE(dev))
3367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3369}
3370
8db9d77b
ZW		 3371/* The FDI link training functions for ILK/Ibexpeak. */
3372static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377 int pipe = intel_crtc->pipe;
5eddb70b 3378 u32 reg, temp, tries;
8db9d77b 3379
1c8562f6 3380 /* FDI needs bits from pipe first */
0fc932b8 3381 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3382
e1a44743
AJ		 3383 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3384 for train result */
5eddb70b
CW		 3385 reg = FDI_RX_IMR(pipe);
3386 temp = I915_READ(reg);
e1a44743
AJ		 3387 temp &= ~FDI_RX_SYMBOL_LOCK;
3388 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3389 I915_WRITE(reg, temp);
3390 I915_READ(reg);
e1a44743
AJ		 3391 udelay(150);
3392
8db9d77b 3393 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
627eb5a3 3396 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3397 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3398 temp &= ~FDI_LINK_TRAIN_NONE;
3399 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3400 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3401
5eddb70b
CW		 3402 reg = FDI_RX_CTL(pipe);
3403 temp = I915_READ(reg);
8db9d77b
ZW		 3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3406 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3407
3408 POSTING_READ(reg);
8db9d77b
ZW		 3409 udelay(150);
3410
5b2adf89 3411 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3412 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3413 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3414 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3415
5eddb70b 3416 reg = FDI_RX_IIR(pipe);
e1a44743 3417 for (tries = 0; tries < 5; tries++) {
5eddb70b 3418 temp = I915_READ(reg);
8db9d77b
ZW		 3419 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3420
3421 if ((temp & FDI_RX_BIT_LOCK)) {
3422 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3423 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3424 break;
3425 }
8db9d77b 3426 }
e1a44743 3427 if (tries == 5)
5eddb70b 3428 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3429
3430 /* Train 2 */
5eddb70b
CW		 3431 reg = FDI_TX_CTL(pipe);
3432 temp = I915_READ(reg);
8db9d77b
ZW		 3433 temp &= ~FDI_LINK_TRAIN_NONE;
3434 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3435 I915_WRITE(reg, temp);
8db9d77b 3436
5eddb70b
CW		 3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3441 I915_WRITE(reg, temp);
8db9d77b 3442
5eddb70b
CW		 3443 POSTING_READ(reg);
3444 udelay(150);
8db9d77b 3445
5eddb70b 3446 reg = FDI_RX_IIR(pipe);
e1a44743 3447 for (tries = 0; tries < 5; tries++) {
5eddb70b 3448 temp = I915_READ(reg);
8db9d77b
ZW		 3449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3450
3451 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3452 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3453 DRM_DEBUG_KMS("FDI train 2 done.\n");
3454 break;
3455 }
8db9d77b 3456 }
e1a44743 3457 if (tries == 5)
5eddb70b 3458 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3459
3460 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3461
8db9d77b
ZW		 3462}
3463
0206e353 3464static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3465 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3466 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3467 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3468 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3469};
3470
3471/* The FDI link training functions for SNB/Cougarpoint. */
3472static void gen6_fdi_link_train(struct drm_crtc *crtc)
3473{
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 int pipe = intel_crtc->pipe;
fa37d39e 3478 u32 reg, temp, i, retry;
8db9d77b 3479
e1a44743
AJ		 3480 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3481 for train result */
5eddb70b
CW		 3482 reg = FDI_RX_IMR(pipe);
3483 temp = I915_READ(reg);
e1a44743
AJ		 3484 temp &= ~FDI_RX_SYMBOL_LOCK;
3485 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3486 I915_WRITE(reg, temp);
3487
3488 POSTING_READ(reg);
e1a44743
AJ		 3489 udelay(150);
3490
8db9d77b 3491 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3492 reg = FDI_TX_CTL(pipe);
3493 temp = I915_READ(reg);
627eb5a3 3494 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3495 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_1;
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499 /* SNB-B */
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3501 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3502
d74cf324
DV		 3503 I915_WRITE(FDI_RX_MISC(pipe),
3504 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3505
5eddb70b
CW		 3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
8db9d77b
ZW		 3508 if (HAS_PCH_CPT(dev)) {
3509 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3511 } else {
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514 }
5eddb70b
CW		 3515 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3516
3517 POSTING_READ(reg);
8db9d77b
ZW		 3518 udelay(150);
3519
0206e353 3520 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
8db9d77b
ZW		 3523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3524 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3525 I915_WRITE(reg, temp);
3526
3527 POSTING_READ(reg);
8db9d77b
ZW		 3528 udelay(500);
3529
fa37d39e
SP		 3530 for (retry = 0; retry < 5; retry++) {
3531 reg = FDI_RX_IIR(pipe);
3532 temp = I915_READ(reg);
3533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3534 if (temp & FDI_RX_BIT_LOCK) {
3535 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3536 DRM_DEBUG_KMS("FDI train 1 done.\n");
3537 break;
3538 }
3539 udelay(50);
8db9d77b 3540 }
fa37d39e
SP		 3541 if (retry < 5)
3542 break;
8db9d77b
ZW		 3543 }
3544 if (i == 4)
5eddb70b 3545 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3546
3547 /* Train 2 */
5eddb70b
CW		 3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
8db9d77b
ZW		 3550 temp &= ~FDI_LINK_TRAIN_NONE;
3551 temp |= FDI_LINK_TRAIN_PATTERN_2;
3552 if (IS_GEN6(dev)) {
3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554 /* SNB-B */
3555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3556 }
5eddb70b 3557 I915_WRITE(reg, temp);
8db9d77b 3558
5eddb70b
CW		 3559 reg = FDI_RX_CTL(pipe);
3560 temp = I915_READ(reg);
8db9d77b
ZW		 3561 if (HAS_PCH_CPT(dev)) {
3562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3564 } else {
3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_2;
3567 }
5eddb70b
CW		 3568 I915_WRITE(reg, temp);
3569
3570 POSTING_READ(reg);
8db9d77b
ZW		 3571 udelay(150);
3572
0206e353 3573 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
8db9d77b
ZW		 3576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3578 I915_WRITE(reg, temp);
3579
3580 POSTING_READ(reg);
8db9d77b
ZW		 3581 udelay(500);
3582
fa37d39e
SP		 3583 for (retry = 0; retry < 5; retry++) {
3584 reg = FDI_RX_IIR(pipe);
3585 temp = I915_READ(reg);
3586 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587 if (temp & FDI_RX_SYMBOL_LOCK) {
3588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3589 DRM_DEBUG_KMS("FDI train 2 done.\n");
3590 break;
3591 }
3592 udelay(50);
8db9d77b 3593 }
fa37d39e
SP		 3594 if (retry < 5)
3595 break;
8db9d77b
ZW		 3596 }
3597 if (i == 4)
5eddb70b 3598 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3599
3600 DRM_DEBUG_KMS("FDI train done.\n");
3601}
3602
357555c0
JB		 3603/* Manual link training for Ivy Bridge A0 parts */
3604static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3605{
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 int pipe = intel_crtc->pipe;
139ccd3f 3610 u32 reg, temp, i, j;
357555c0
JB		 3611
3612 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3613 for train result */
3614 reg = FDI_RX_IMR(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~FDI_RX_SYMBOL_LOCK;
3617 temp &= ~FDI_RX_BIT_LOCK;
3618 I915_WRITE(reg, temp);
3619
3620 POSTING_READ(reg);
3621 udelay(150);
3622
01a415fd
DV		 3623 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3624 I915_READ(FDI_RX_IIR(pipe)));
3625
139ccd3f
JB		 3626 /* Try each vswing and preemphasis setting twice before moving on */
3627 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3628 /* disable first in case we need to retry */
3629 reg = FDI_TX_CTL(pipe);
3630 temp = I915_READ(reg);
3631 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3632 temp &= ~FDI_TX_ENABLE;
3633 I915_WRITE(reg, temp);
357555c0 3634
139ccd3f
JB		 3635 reg = FDI_RX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_LINK_TRAIN_AUTO;
3638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639 temp &= ~FDI_RX_ENABLE;
3640 I915_WRITE(reg, temp);
357555c0 3641
139ccd3f 3642 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
139ccd3f 3645 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3646 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3647 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3649 temp |= snb_b_fdi_train_param[j/2];
3650 temp |= FDI_COMPOSITE_SYNC;
3651 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3652
139ccd3f
JB		 3653 I915_WRITE(FDI_RX_MISC(pipe),
3654 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3655
139ccd3f 3656 reg = FDI_RX_CTL(pipe);
357555c0 3657 temp = I915_READ(reg);
139ccd3f
JB		 3658 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3659 temp |= FDI_COMPOSITE_SYNC;
3660 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3661
139ccd3f
JB		 3662 POSTING_READ(reg);
3663 udelay(1); /* should be 0.5us */
357555c0 3664
139ccd3f
JB		 3665 for (i = 0; i < 4; i++) {
3666 reg = FDI_RX_IIR(pipe);
3667 temp = I915_READ(reg);
3668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3669
139ccd3f
JB		 3670 if (temp & FDI_RX_BIT_LOCK ||
3671 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3672 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3673 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3674 i);
3675 break;
3676 }
3677 udelay(1); /* should be 0.5us */
3678 }
3679 if (i == 4) {
3680 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3681 continue;
3682 }
357555c0 3683
139ccd3f 3684 /* Train 2 */
357555c0
JB		 3685 reg = FDI_TX_CTL(pipe);
3686 temp = I915_READ(reg);
139ccd3f
JB		 3687 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3688 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3689 I915_WRITE(reg, temp);
3690
3691 reg = FDI_RX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3695 I915_WRITE(reg, temp);
3696
3697 POSTING_READ(reg);
139ccd3f 3698 udelay(2); /* should be 1.5us */
357555c0 3699
139ccd3f
JB		 3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3704
139ccd3f
JB		 3705 if (temp & FDI_RX_SYMBOL_LOCK ||
3706 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3708 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3709 i);
3710 goto train_done;
3711 }
3712 udelay(2); /* should be 1.5us */
357555c0 3713 }
139ccd3f
JB		 3714 if (i == 4)
3715 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3716 }
357555c0 3717
139ccd3f 3718train_done:
357555c0
JB		 3719 DRM_DEBUG_KMS("FDI train done.\n");
3720}
3721
88cefb6c 3722static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3723{
88cefb6c 3724 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3725 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3726 int pipe = intel_crtc->pipe;
5eddb70b 3727 u32 reg, temp;
79e53945 3728
c64e311e 3729
c98e9dcf 3730 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3731 reg = FDI_RX_CTL(pipe);
3732 temp = I915_READ(reg);
627eb5a3 3733 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3734 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3735 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3736 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3737
3738 POSTING_READ(reg);
c98e9dcf
JB		 3739 udelay(200);
3740
3741 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3742 temp = I915_READ(reg);
3743 I915_WRITE(reg, temp | FDI_PCDCLK);
3744
3745 POSTING_READ(reg);
c98e9dcf
JB		 3746 udelay(200);
3747
20749730
PZ		 3748 /* Enable CPU FDI TX PLL, always on for Ironlake */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3752 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3753
20749730
PZ		 3754 POSTING_READ(reg);
3755 udelay(100);
6be4a607 3756 }
0e23b99d
JB		 3757}
3758
88cefb6c
DV		 3759static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3760{
3761 struct drm_device *dev = intel_crtc->base.dev;
3762 struct drm_i915_private *dev_priv = dev->dev_private;
3763 int pipe = intel_crtc->pipe;
3764 u32 reg, temp;
3765
3766 /* Switch from PCDclk to Rawclk */
3767 reg = FDI_RX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3770
3771 /* Disable CPU FDI TX PLL */
3772 reg = FDI_TX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3775
3776 POSTING_READ(reg);
3777 udelay(100);
3778
3779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3782
3783 /* Wait for the clocks to turn off. */
3784 POSTING_READ(reg);
3785 udelay(100);
3786}
3787
0fc932b8
JB		 3788static void ironlake_fdi_disable(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793 int pipe = intel_crtc->pipe;
3794 u32 reg, temp;
3795
3796 /* disable CPU FDI tx and PCH FDI rx */
3797 reg = FDI_TX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3800 POSTING_READ(reg);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 temp &= ~(0x7 << 16);
dfd07d72 3805 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3806 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3807
3808 POSTING_READ(reg);
3809 udelay(100);
3810
3811 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3812 if (HAS_PCH_IBX(dev))
6f06ce18 3813 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3814
3815 /* still set train pattern 1 */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 temp &= ~FDI_LINK_TRAIN_NONE;
3819 temp |= FDI_LINK_TRAIN_PATTERN_1;
3820 I915_WRITE(reg, temp);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 if (HAS_PCH_CPT(dev)) {
3825 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3826 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3827 } else {
3828 temp &= ~FDI_LINK_TRAIN_NONE;
3829 temp |= FDI_LINK_TRAIN_PATTERN_1;
3830 }
3831 /* BPC in FDI rx is consistent with that in PIPECONF */
3832 temp &= ~(0x07 << 16);
dfd07d72 3833 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3834 I915_WRITE(reg, temp);
3835
3836 POSTING_READ(reg);
3837 udelay(100);
3838}
3839
5dce5b93
CW		 3840bool intel_has_pending_fb_unpin(struct drm_device *dev)
3841{
3842 struct intel_crtc *crtc;
3843
3844 /* Note that we don't need to be called with mode_config.lock here
3845 * as our list of CRTC objects is static for the lifetime of the
3846 * device and so cannot disappear as we iterate. Similarly, we can
3847 * happily treat the predicates as racy, atomic checks as userspace
3848 * cannot claim and pin a new fb without at least acquring the
3849 * struct_mutex and so serialising with us.
3850 */
d3fcc808 3851 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3852 if (atomic_read(&crtc->unpin_work_count) == 0)
3853 continue;
3854
3855 if (crtc->unpin_work)
3856 intel_wait_for_vblank(dev, crtc->pipe);
3857
3858 return true;
3859 }
3860
3861 return false;
3862}
3863
d6bbafa1
CW		 3864static void page_flip_completed(struct intel_crtc *intel_crtc)
3865{
3866 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3867 struct intel_unpin_work *work = intel_crtc->unpin_work;
3868
3869 /* ensure that the unpin work is consistent wrt ->pending. */
3870 smp_rmb();
3871 intel_crtc->unpin_work = NULL;
3872
3873 if (work->event)
3874 drm_send_vblank_event(intel_crtc->base.dev,
3875 intel_crtc->pipe,
3876 work->event);
3877
3878 drm_crtc_vblank_put(&intel_crtc->base);
3879
3880 wake_up_all(&dev_priv->pending_flip_queue);
3881 queue_work(dev_priv->wq, &work->work);
3882
3883 trace_i915_flip_complete(intel_crtc->plane,
3884 work->pending_flip_obj);
3885}
3886
46a55d30 3887void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3888{
0f91128d 3889 struct drm_device *dev = crtc->dev;
5bb61643 3890 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3891
2c10d571 3892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3893 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3894 !intel_crtc_has_pending_flip(crtc),
3895 60*HZ) == 0)) {
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3897
5e2d7afc 3898 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3899 if (intel_crtc->unpin_work) {
3900 WARN_ONCE(1, "Removing stuck page flip\n");
3901 page_flip_completed(intel_crtc);
3902 }
5e2d7afc 3903 spin_unlock_irq(&dev->event_lock);
9c787942 3904 }
5bb61643 3905
975d568a
CW		 3906 if (crtc->primary->fb) {
3907 mutex_lock(&dev->struct_mutex);
3908 intel_finish_fb(crtc->primary->fb);
3909 mutex_unlock(&dev->struct_mutex);
3910 }
e6c3a2a6
CW		 3911}
3912
e615efe4
ED		 3913/* Program iCLKIP clock to the desired frequency */
3914static void lpt_program_iclkip(struct drm_crtc *crtc)
3915{
3916 struct drm_device *dev = crtc->dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3918 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3919 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3920 u32 temp;
3921
a580516d 3922 mutex_lock(&dev_priv->sb_lock);
09153000 3923
e615efe4
ED		 3924 /* It is necessary to ungate the pixclk gate prior to programming
3925 * the divisors, and gate it back when it is done.
3926 */
3927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3928
3929 /* Disable SSCCTL */
3930 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3931 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3932 SBI_SSCCTL_DISABLE,
3933 SBI_ICLK);
e615efe4
ED		 3934
3935 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3936 if (clock == 20000) {
e615efe4
ED		 3937 auxdiv = 1;
3938 divsel = 0x41;
3939 phaseinc = 0x20;
3940 } else {
3941 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3942 * but the adjusted_mode->crtc_clock in in KHz. To get the
3943 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3944 * convert the virtual clock precision to KHz here for higher
3945 * precision.
3946 */
3947 u32 iclk_virtual_root_freq = 172800 * 1000;
3948 u32 iclk_pi_range = 64;
3949 u32 desired_divisor, msb_divisor_value, pi_value;
3950
12d7ceed 3951 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3952 msb_divisor_value = desired_divisor / iclk_pi_range;
3953 pi_value = desired_divisor % iclk_pi_range;
3954
3955 auxdiv = 0;
3956 divsel = msb_divisor_value - 2;
3957 phaseinc = pi_value;
3958 }
3959
3960 /* This should not happen with any sane values */
3961 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3962 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3964 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3965
3966 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3967 clock,
e615efe4
ED		 3968 auxdiv,
3969 divsel,
3970 phasedir,
3971 phaseinc);
3972
3973 /* Program SSCDIVINTPHASE6 */
988d6ee8 3974 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3975 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3976 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3977 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3979 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3980 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3981 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3982
3983 /* Program SSCAUXDIV */
988d6ee8 3984 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3985 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3986 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3987 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3988
3989 /* Enable modulator and associated divider */
988d6ee8 3990 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3991 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3992 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3993
3994 /* Wait for initialization time */
3995 udelay(24);
3996
3997 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3998
a580516d 3999 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4000}
4001
275f01b2
DV		 4002static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4003 enum pipe pch_transcoder)
4004{
4005 struct drm_device *dev = crtc->base.dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4007 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4008
4009 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4010 I915_READ(HTOTAL(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4012 I915_READ(HBLANK(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4014 I915_READ(HSYNC(cpu_transcoder)));
4015
4016 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4017 I915_READ(VTOTAL(cpu_transcoder)));
4018 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4019 I915_READ(VBLANK(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4021 I915_READ(VSYNC(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4023 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4024}
4025
003632d9 4026static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4027{
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 uint32_t temp;
4030
4031 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4032 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4033 return;
4034
4035 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4036 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4037
003632d9
ACO		 4038 temp &= ~FDI_BC_BIFURCATION_SELECT;
4039 if (enable)
4040 temp |= FDI_BC_BIFURCATION_SELECT;
4041
4042 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4043 I915_WRITE(SOUTH_CHICKEN1, temp);
4044 POSTING_READ(SOUTH_CHICKEN1);
4045}
4046
4047static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4048{
4049 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4050
4051 switch (intel_crtc->pipe) {
4052 case PIPE_A:
4053 break;
4054 case PIPE_B:
6e3c9717 4055 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4056 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4057 else
003632d9 4058 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4059
4060 break;
4061 case PIPE_C:
003632d9 4062 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4063
4064 break;
4065 default:
4066 BUG();
4067 }
4068}
4069
f67a559d
JB		 4070/*
4071 * Enable PCH resources required for PCH ports:
4072 * - PCH PLLs
4073 * - FDI training & RX/TX
4074 * - update transcoder timings
4075 * - DP transcoding bits
4076 * - transcoder
4077 */
4078static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4079{
4080 struct drm_device *dev = crtc->dev;
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4083 int pipe = intel_crtc->pipe;
ee7b9f93 4084 u32 reg, temp;
2c07245f 4085
ab9412ba 4086 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4087
1fbc0d78
DV		 4088 if (IS_IVYBRIDGE(dev))
4089 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4090
cd986abb
DV		 4091 /* Write the TU size bits before fdi link training, so that error
4092 * detection works. */
4093 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4094 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4095
c98e9dcf 4096 /* For PCH output, training FDI link */
674cf967 4097 dev_priv->display.fdi_link_train(crtc);
2c07245f 4098
3ad8a208
DV		 4099 /* We need to program the right clock selection before writing the pixel
4100 * mutliplier into the DPLL. */
303b81e0 4101 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4102 u32 sel;
4b645f14 4103
c98e9dcf 4104 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4105 temp |= TRANS_DPLL_ENABLE(pipe);
4106 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4107 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4108 temp |= sel;
4109 else
4110 temp &= ~sel;
c98e9dcf 4111 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4112 }
5eddb70b 4113
3ad8a208
DV		 4114 /* XXX: pch pll's can be enabled any time before we enable the PCH
4115 * transcoder, and we actually should do this to not upset any PCH
4116 * transcoder that already use the clock when we share it.
4117 *
4118 * Note that enable_shared_dpll tries to do the right thing, but
4119 * get_shared_dpll unconditionally resets the pll - we need that to have
4120 * the right LVDS enable sequence. */
85b3894f 4121 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4122
d9b6cb56
JB		 4123 /* set transcoder timing, panel must allow it */
4124 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4125 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4126
303b81e0 4127 intel_fdi_normal_train(crtc);
5e84e1a4 4128
c98e9dcf 4129 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4130 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4131 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4132 reg = TRANS_DP_CTL(pipe);
4133 temp = I915_READ(reg);
4134 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4135 TRANS_DP_SYNC_MASK |
4136 TRANS_DP_BPC_MASK);
e3ef4479 4137 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4138 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4139
4140 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4141 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4142 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4143 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4144
4145 switch (intel_trans_dp_port_sel(crtc)) {
4146 case PCH_DP_B:
5eddb70b 4147 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4148 break;
4149 case PCH_DP_C:
5eddb70b 4150 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4151 break;
4152 case PCH_DP_D:
5eddb70b 4153 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4154 break;
4155 default:
e95d41e1 4156 BUG();
32f9d658 4157 }
2c07245f 4158
5eddb70b 4159 I915_WRITE(reg, temp);
6be4a607 4160 }
b52eb4dc 4161
b8a4f404 4162 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4163}
4164
1507e5bd
PZ		 4165static void lpt_pch_enable(struct drm_crtc *crtc)
4166{
4167 struct drm_device *dev = crtc->dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4170 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4171
ab9412ba 4172 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4173
8c52b5e8 4174 lpt_program_iclkip(crtc);
1507e5bd 4175
0540e488 4176 /* Set transcoder timing. */
275f01b2 4177 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4178
937bb610 4179 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4180}
4181
190f68c5
ACO		 4182struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4183 struct intel_crtc_state *crtc_state)
ee7b9f93 4184{
e2b78267 4185 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4186 struct intel_shared_dpll *pll;
de419ab6 4187 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4188 enum intel_dpll_id i;
ee7b9f93 4189
de419ab6
ML		 4190 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4191
98b6bd99
DV		 4192 if (HAS_PCH_IBX(dev_priv->dev)) {
4193 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4194 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4195 pll = &dev_priv->shared_dplls[i];
98b6bd99 4196
46edb027
DV		 4197 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4198 crtc->base.base.id, pll->name);
98b6bd99 4199
de419ab6 4200 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4201
98b6bd99
DV		 4202 goto found;
4203 }
4204
bcddf610
S		 4205 if (IS_BROXTON(dev_priv->dev)) {
4206 /* PLL is attached to port in bxt */
4207 struct intel_encoder *encoder;
4208 struct intel_digital_port *intel_dig_port;
4209
4210 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4211 if (WARN_ON(!encoder))
4212 return NULL;
4213
4214 intel_dig_port = enc_to_dig_port(&encoder->base);
4215 /* 1:1 mapping between ports and PLLs */
4216 i = (enum intel_dpll_id)intel_dig_port->port;
4217 pll = &dev_priv->shared_dplls[i];
4218 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4219 crtc->base.base.id, pll->name);
de419ab6 4220 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4221
4222 goto found;
4223 }
4224
e72f9fbf
DV		 4225 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4226 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4227
4228 /* Only want to check enabled timings first */
de419ab6 4229 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4230 continue;
4231
190f68c5 4232 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4233 &shared_dpll[i].hw_state,
4234 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4235 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4236 crtc->base.base.id, pll->name,
de419ab6 4237 shared_dpll[i].crtc_mask,
8bd31e67 4238 pll->active);
ee7b9f93
JB		 4239 goto found;
4240 }
4241 }
4242
4243 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
de419ab6 4246 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4247 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4248 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4249 goto found;
4250 }
4251 }
4252
4253 return NULL;
4254
4255found:
de419ab6
ML		 4256 if (shared_dpll[i].crtc_mask == 0)
4257 shared_dpll[i].hw_state =
4258 crtc_state->dpll_hw_state;
f2a69f44 4259
190f68c5 4260 crtc_state->shared_dpll = i;
46edb027
DV		 4261 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4262 pipe_name(crtc->pipe));
ee7b9f93 4263
de419ab6 4264 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4265
ee7b9f93
JB		 4266 return pll;
4267}
4268
de419ab6 4269static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4270{
de419ab6
ML		 4271 struct drm_i915_private *dev_priv = to_i915(state->dev);
4272 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4273 struct intel_shared_dpll *pll;
4274 enum intel_dpll_id i;
4275
de419ab6
ML		 4276 if (!to_intel_atomic_state(state)->dpll_set)
4277 return;
8bd31e67 4278
de419ab6 4279 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4280 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4281 pll = &dev_priv->shared_dplls[i];
de419ab6 4282 pll->config = shared_dpll[i];
8bd31e67
ACO		 4283 }
4284}
4285
a1520318 4286static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4287{
4288 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4289 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4290 u32 temp;
4291
4292 temp = I915_READ(dslreg);
4293 udelay(500);
4294 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4295 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4296 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4297 }
4298}
4299
86adf9d7
ML		 4300static int
4301skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4302 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4303 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4304{
86adf9d7
ML		 4305 struct intel_crtc_scaler_state *scaler_state =
4306 &crtc_state->scaler_state;
4307 struct intel_crtc *intel_crtc =
4308 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4309 int need_scaling;
6156a456
CK		 4310
4311 need_scaling = intel_rotation_90_or_270(rotation) ?
4312 (src_h != dst_w || src_w != dst_h):
4313 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4314
4315 /*
4316 * if plane is being disabled or scaler is no more required or force detach
4317 * - free scaler binded to this plane/crtc
4318 * - in order to do this, update crtc->scaler_usage
4319 *
4320 * Here scaler state in crtc_state is set free so that
4321 * scaler can be assigned to other user. Actual register
4322 * update to free the scaler is done in plane/panel-fit programming.
4323 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4324 */
86adf9d7 4325 if (force_detach || !need_scaling) {
a1b2278e 4326 if (*scaler_id >= 0) {
86adf9d7 4327 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4328 scaler_state->scalers[*scaler_id].in_use = 0;
4329
86adf9d7
ML		 4330 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4331 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4332 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4333 scaler_state->scaler_users);
4334 *scaler_id = -1;
4335 }
4336 return 0;
4337 }
4338
4339 /* range checks */
4340 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4341 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4342
4343 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4344 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4345 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4346 "size is out of scaler range\n",
86adf9d7 4347 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4348 return -EINVAL;
4349 }
4350
86adf9d7
ML		 4351 /* mark this plane as a scaler user in crtc_state */
4352 scaler_state->scaler_users |= (1 << scaler_user);
4353 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4354 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4355 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4356 scaler_state->scaler_users);
4357
4358 return 0;
4359}
4360
4361/**
4362 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4363 *
4364 * @state: crtc's scaler state
4365 * @force_detach: whether to forcibly disable scaler
4366 *
4367 * Return
4368 * 0 - scaler_usage updated successfully
4369 * error - requested scaling cannot be supported or other error condition
4370 */
4371int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4372{
4373 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4374 struct drm_display_mode *adjusted_mode =
4375 &state->base.adjusted_mode;
4376
4377 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4378 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4379
4380 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4381 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4382 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4383 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4384}
4385
4386/**
4387 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4388 *
4389 * @state: crtc's scaler state
86adf9d7
ML		 4390 * @plane_state: atomic plane state to update
4391 *
4392 * Return
4393 * 0 - scaler_usage updated successfully
4394 * error - requested scaling cannot be supported or other error condition
4395 */
da20eabd
ML		 4396static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4397 struct intel_plane_state *plane_state)
86adf9d7
ML		 4398{
4399
4400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4401 struct intel_plane *intel_plane =
4402 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4403 struct drm_framebuffer *fb = plane_state->base.fb;
4404 int ret;
4405
4406 bool force_detach = !fb || !plane_state->visible;
4407
4408 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4409 intel_plane->base.base.id, intel_crtc->pipe,
4410 drm_plane_index(&intel_plane->base));
4411
4412 ret = skl_update_scaler(crtc_state, force_detach,
4413 drm_plane_index(&intel_plane->base),
4414 &plane_state->scaler_id,
4415 plane_state->base.rotation,
4416 drm_rect_width(&plane_state->src) >> 16,
4417 drm_rect_height(&plane_state->src) >> 16,
4418 drm_rect_width(&plane_state->dst),
4419 drm_rect_height(&plane_state->dst));
4420
4421 if (ret || plane_state->scaler_id < 0)
4422 return ret;
4423
a1b2278e 4424 /* check colorkey */
818ed961 4425 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4426 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4427 intel_plane->base.base.id);
a1b2278e
CK		 4428 return -EINVAL;
4429 }
4430
4431 /* Check src format */
86adf9d7
ML		 4432 switch (fb->pixel_format) {
4433 case DRM_FORMAT_RGB565:
4434 case DRM_FORMAT_XBGR8888:
4435 case DRM_FORMAT_XRGB8888:
4436 case DRM_FORMAT_ABGR8888:
4437 case DRM_FORMAT_ARGB8888:
4438 case DRM_FORMAT_XRGB2101010:
4439 case DRM_FORMAT_XBGR2101010:
4440 case DRM_FORMAT_YUYV:
4441 case DRM_FORMAT_YVYU:
4442 case DRM_FORMAT_UYVY:
4443 case DRM_FORMAT_VYUY:
4444 break;
4445 default:
4446 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4447 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4448 return -EINVAL;
a1b2278e
CK		 4449 }
4450
a1b2278e
CK		 4451 return 0;
4452}
4453
4454static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4455{
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 int pipe = crtc->pipe;
a1b2278e
CK		 4459 struct intel_crtc_scaler_state *scaler_state =
4460 &crtc->config->scaler_state;
4461
4462 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4463
4464 /* To update pfit, first update scaler state */
86adf9d7 4465 skl_update_scaler_crtc(crtc->config, !enable);
a1b2278e
CK		 4466 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4467 skl_detach_scalers(crtc);
4468 if (!enable)
4469 return;
bd2e244f 4470
6e3c9717 4471 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4472 int id;
4473
4474 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4475 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4476 return;
4477 }
4478
4479 id = scaler_state->scaler_id;
4480 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4481 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4482 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4483 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4484
4485 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4486 }
4487}
4488
b074cec8
JB		 4489static void ironlake_pfit_enable(struct intel_crtc *crtc)
4490{
4491 struct drm_device *dev = crtc->base.dev;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493 int pipe = crtc->pipe;
4494
6e3c9717 4495 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4496 /* Force use of hard-coded filter coefficients
4497 * as some pre-programmed values are broken,
4498 * e.g. x201.
4499 */
4500 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4501 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4502 PF_PIPE_SEL_IVB(pipe));
4503 else
4504 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4505 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4506 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4507 }
4508}
4509
20bc8673 4510void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4511{
cea165c3
VS		 4512 struct drm_device *dev = crtc->base.dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4514
6e3c9717 4515 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4516 return;
4517
cea165c3
VS		 4518 /* We can only enable IPS after we enable a plane and wait for a vblank */
4519 intel_wait_for_vblank(dev, crtc->pipe);
4520
d77e4531 4521 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4522 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4523 mutex_lock(&dev_priv->rps.hw_lock);
4524 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4525 mutex_unlock(&dev_priv->rps.hw_lock);
4526 /* Quoting Art Runyan: "its not safe to expect any particular
4527 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4528 * mailbox." Moreover, the mailbox may return a bogus state,
4529 * so we need to just enable it and continue on.
2a114cc1
BW		 4530 */
4531 } else {
4532 I915_WRITE(IPS_CTL, IPS_ENABLE);
4533 /* The bit only becomes 1 in the next vblank, so this wait here
4534 * is essentially intel_wait_for_vblank. If we don't have this
4535 * and don't wait for vblanks until the end of crtc_enable, then
4536 * the HW state readout code will complain that the expected
4537 * IPS_CTL value is not the one we read. */
4538 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4539 DRM_ERROR("Timed out waiting for IPS enable\n");
4540 }
d77e4531
PZ		 4541}
4542
20bc8673 4543void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4544{
4545 struct drm_device *dev = crtc->base.dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547
6e3c9717 4548 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4549 return;
4550
4551 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4552 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4553 mutex_lock(&dev_priv->rps.hw_lock);
4554 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4555 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4556 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4557 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4558 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4559 } else {
2a114cc1 4560 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4561 POSTING_READ(IPS_CTL);
4562 }
d77e4531
PZ		 4563
4564 /* We need to wait for a vblank before we can disable the plane. */
4565 intel_wait_for_vblank(dev, crtc->pipe);
4566}
4567
4568/** Loads the palette/gamma unit for the CRTC with the prepared values */
4569static void intel_crtc_load_lut(struct drm_crtc *crtc)
4570{
4571 struct drm_device *dev = crtc->dev;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4574 enum pipe pipe = intel_crtc->pipe;
4575 int palreg = PALETTE(pipe);
4576 int i;
4577 bool reenable_ips = false;
4578
4579 /* The clocks have to be on to load the palette. */
53d9f4e9 4580 if (!crtc->state->active)
d77e4531
PZ		 4581 return;
4582
50360403 4583 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4584 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4585 assert_dsi_pll_enabled(dev_priv);
4586 else
4587 assert_pll_enabled(dev_priv, pipe);
4588 }
4589
4590 /* use legacy palette for Ironlake */
7a1db49a 4591 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4592 palreg = LGC_PALETTE(pipe);
4593
4594 /* Workaround : Do not read or write the pipe palette/gamma data while
4595 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4596 */
6e3c9717 4597 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4598 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4599 GAMMA_MODE_MODE_SPLIT)) {
4600 hsw_disable_ips(intel_crtc);
4601 reenable_ips = true;
4602 }
4603
4604 for (i = 0; i < 256; i++) {
4605 I915_WRITE(palreg + 4 * i,
4606 (intel_crtc->lut_r[i] << 16) |
4607 (intel_crtc->lut_g[i] << 8) |
4608 intel_crtc->lut_b[i]);
4609 }
4610
4611 if (reenable_ips)
4612 hsw_enable_ips(intel_crtc);
4613}
4614
7cac945f 4615static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4616{
7cac945f 4617 if (intel_crtc->overlay) {
d3eedb1a
VS		 4618 struct drm_device *dev = intel_crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621 mutex_lock(&dev->struct_mutex);
4622 dev_priv->mm.interruptible = false;
4623 (void) intel_overlay_switch_off(intel_crtc->overlay);
4624 dev_priv->mm.interruptible = true;
4625 mutex_unlock(&dev->struct_mutex);
4626 }
4627
4628 /* Let userspace switch the overlay on again. In most cases userspace
4629 * has to recompute where to put it anyway.
4630 */
4631}
4632
87d4300a
ML		 4633/**
4634 * intel_post_enable_primary - Perform operations after enabling primary plane
4635 * @crtc: the CRTC whose primary plane was just enabled
4636 *
4637 * Performs potentially sleeping operations that must be done after the primary
4638 * plane is enabled, such as updating FBC and IPS. Note that this may be
4639 * called due to an explicit primary plane update, or due to an implicit
4640 * re-enable that is caused when a sprite plane is updated to no longer
4641 * completely hide the primary plane.
4642 */
4643static void
4644intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4645{
4646 struct drm_device *dev = crtc->dev;
87d4300a 4647 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 int pipe = intel_crtc->pipe;
a5c4d7bc 4650
87d4300a
ML		 4651 /*
4652 * BDW signals flip done immediately if the plane
4653 * is disabled, even if the plane enable is already
4654 * armed to occur at the next vblank :(
4655 */
4656 if (IS_BROADWELL(dev))
4657 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4658
87d4300a
ML		 4659 /*
4660 * FIXME IPS should be fine as long as one plane is
4661 * enabled, but in practice it seems to have problems
4662 * when going from primary only to sprite only and vice
4663 * versa.
4664 */
a5c4d7bc
VS		 4665 hsw_enable_ips(intel_crtc);
4666
f99d7069 4667 /*
87d4300a
ML		 4668 * Gen2 reports pipe underruns whenever all planes are disabled.
4669 * So don't enable underrun reporting before at least some planes
4670 * are enabled.
4671 * FIXME: Need to fix the logic to work when we turn off all planes
4672 * but leave the pipe running.
f99d7069 4673 */
87d4300a
ML		 4674 if (IS_GEN2(dev))
4675 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4676
4677 /* Underruns don't raise interrupts, so check manually. */
4678 if (HAS_GMCH_DISPLAY(dev))
4679 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4680}
4681
87d4300a
ML		 4682/**
4683 * intel_pre_disable_primary - Perform operations before disabling primary plane
4684 * @crtc: the CRTC whose primary plane is to be disabled
4685 *
4686 * Performs potentially sleeping operations that must be done before the
4687 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4688 * be called due to an explicit primary plane update, or due to an implicit
4689 * disable that is caused when a sprite plane completely hides the primary
4690 * plane.
4691 */
4692static void
4693intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4694{
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
a5c4d7bc 4699
87d4300a
ML		 4700 /*
4701 * Gen2 reports pipe underruns whenever all planes are disabled.
4702 * So diasble underrun reporting before all the planes get disabled.
4703 * FIXME: Need to fix the logic to work when we turn off all planes
4704 * but leave the pipe running.
4705 */
4706 if (IS_GEN2(dev))
4707 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4708
87d4300a
ML		 4709 /*
4710 * Vblank time updates from the shadow to live plane control register
4711 * are blocked if the memory self-refresh mode is active at that
4712 * moment. So to make sure the plane gets truly disabled, disable
4713 * first the self-refresh mode. The self-refresh enable bit in turn
4714 * will be checked/applied by the HW only at the next frame start
4715 * event which is after the vblank start event, so we need to have a
4716 * wait-for-vblank between disabling the plane and the pipe.
4717 */
262cd2e1 4718 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4719 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4720 dev_priv->wm.vlv.cxsr = false;
4721 intel_wait_for_vblank(dev, pipe);
4722 }
87d4300a 4723
87d4300a
ML		 4724 /*
4725 * FIXME IPS should be fine as long as one plane is
4726 * enabled, but in practice it seems to have problems
4727 * when going from primary only to sprite only and vice
4728 * versa.
4729 */
a5c4d7bc 4730 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4731}
4732
ac21b225
ML		 4733static void intel_post_plane_update(struct intel_crtc *crtc)
4734{
4735 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4736 struct drm_device *dev = crtc->base.dev;
4737 struct drm_plane *plane;
4738
4739 if (atomic->wait_vblank)
4740 intel_wait_for_vblank(dev, crtc->pipe);
4741
4742 intel_frontbuffer_flip(dev, atomic->fb_bits);
4743
852eb00d
VS		 4744 if (atomic->disable_cxsr)
4745 crtc->wm.cxsr_allowed = true;
4746
f015c551
VS		 4747 if (crtc->atomic.update_wm_post)
4748 intel_update_watermarks(&crtc->base);
4749
ac21b225
ML		 4750 if (atomic->update_fbc) {
4751 mutex_lock(&dev->struct_mutex);
4752 intel_fbc_update(dev);
4753 mutex_unlock(&dev->struct_mutex);
4754 }
4755
4756 if (atomic->post_enable_primary)
4757 intel_post_enable_primary(&crtc->base);
4758
4759 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4760 intel_update_sprite_watermarks(plane, &crtc->base,
4761 0, 0, 0, false, false);
4762
4763 memset(atomic, 0, sizeof(*atomic));
4764}
4765
4766static void intel_pre_plane_update(struct intel_crtc *crtc)
4767{
4768 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4769 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4770 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771 struct drm_plane *p;
4772
4773 /* Track fb's for any planes being disabled */
ac21b225
ML		 4774 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4775 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4776
4777 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4778 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4779 plane->frontbuffer_bit);
ac21b225
ML		 4780 mutex_unlock(&dev->struct_mutex);
4781 }
4782
4783 if (atomic->wait_for_flips)
4784 intel_crtc_wait_for_pending_flips(&crtc->base);
4785
eddfcbcd
ML		 4786 if (atomic->disable_fbc &&
4787 dev_priv->fbc.crtc == crtc) {
4788 mutex_lock(&dev->struct_mutex);
4789 if (dev_priv->fbc.crtc == crtc)
4790 intel_fbc_disable(dev);
4791 mutex_unlock(&dev->struct_mutex);
4792 }
ac21b225 4793
066cf55b
RV		 4794 if (crtc->atomic.disable_ips)
4795 hsw_disable_ips(crtc);
4796
ac21b225
ML		 4797 if (atomic->pre_disable_primary)
4798 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4799
4800 if (atomic->disable_cxsr) {
4801 crtc->wm.cxsr_allowed = false;
4802 intel_set_memory_cxsr(dev_priv, false);
4803 }
ac21b225
ML		 4804}
4805
d032ffa0 4806static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4807{
4808 struct drm_device *dev = crtc->dev;
4809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4810 struct drm_plane *p;
87d4300a
ML		 4811 int pipe = intel_crtc->pipe;
4812
7cac945f 4813 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4814
d032ffa0
ML		 4815 drm_for_each_plane_mask(p, dev, plane_mask)
4816 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4817
f99d7069
DV		 4818 /*
4819 * FIXME: Once we grow proper nuclear flip support out of this we need
4820 * to compute the mask of flip planes precisely. For the time being
4821 * consider this a flip to a NULL plane.
4822 */
4823 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4824}
4825
f67a559d
JB		 4826static void ironlake_crtc_enable(struct drm_crtc *crtc)
4827{
4828 struct drm_device *dev = crtc->dev;
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4831 struct intel_encoder *encoder;
f67a559d 4832 int pipe = intel_crtc->pipe;
f67a559d 4833
53d9f4e9 4834 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4835 return;
4836
6e3c9717 4837 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4838 intel_prepare_shared_dpll(intel_crtc);
4839
6e3c9717 4840 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4841 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4842
4843 intel_set_pipe_timings(intel_crtc);
4844
6e3c9717 4845 if (intel_crtc->config->has_pch_encoder) {
29407aab 4846 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4847 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4848 }
4849
4850 ironlake_set_pipeconf(crtc);
4851
f67a559d 4852 intel_crtc->active = true;
8664281b 4853
a72e4c9f
DV		 4854 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4855 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4856
f6736a1a 4857 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4858 if (encoder->pre_enable)
4859 encoder->pre_enable(encoder);
f67a559d 4860
6e3c9717 4861 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4862 /* Note: FDI PLL enabling _must_ be done before we enable the
4863 * cpu pipes, hence this is separate from all the other fdi/pch
4864 * enabling. */
88cefb6c 4865 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4866 } else {
4867 assert_fdi_tx_disabled(dev_priv, pipe);
4868 assert_fdi_rx_disabled(dev_priv, pipe);
4869 }
f67a559d 4870
b074cec8 4871 ironlake_pfit_enable(intel_crtc);
f67a559d 4872
9c54c0dd
JB		 4873 /*
4874 * On ILK+ LUT must be loaded before the pipe is running but with
4875 * clocks enabled
4876 */
4877 intel_crtc_load_lut(crtc);
4878
f37fcc2a 4879 intel_update_watermarks(crtc);
e1fdc473 4880 intel_enable_pipe(intel_crtc);
f67a559d 4881
6e3c9717 4882 if (intel_crtc->config->has_pch_encoder)
f67a559d 4883 ironlake_pch_enable(crtc);
c98e9dcf 4884
f9b61ff6
DV		 4885 assert_vblank_disabled(crtc);
4886 drm_crtc_vblank_on(crtc);
4887
fa5c73b1
DV		 4888 for_each_encoder_on_crtc(dev, crtc, encoder)
4889 encoder->enable(encoder);
61b77ddd
DV		 4890
4891 if (HAS_PCH_CPT(dev))
a1520318 4892 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4893}
4894
42db64ef
PZ		 4895/* IPS only exists on ULT machines and is tied to pipe A. */
4896static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4897{
f5adf94e 4898 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4899}
4900
4f771f10
PZ		 4901static void haswell_crtc_enable(struct drm_crtc *crtc)
4902{
4903 struct drm_device *dev = crtc->dev;
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4906 struct intel_encoder *encoder;
99d736a2
ML		 4907 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4908 struct intel_crtc_state *pipe_config =
4909 to_intel_crtc_state(crtc->state);
4f771f10 4910
53d9f4e9 4911 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4912 return;
4913
df8ad70c
DV		 4914 if (intel_crtc_to_shared_dpll(intel_crtc))
4915 intel_enable_shared_dpll(intel_crtc);
4916
6e3c9717 4917 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4918 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4919
4920 intel_set_pipe_timings(intel_crtc);
4921
6e3c9717
ACO		 4922 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4923 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4924 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4925 }
4926
6e3c9717 4927 if (intel_crtc->config->has_pch_encoder) {
229fca97 4928 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4929 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4930 }
4931
4932 haswell_set_pipeconf(crtc);
4933
4934 intel_set_pipe_csc(crtc);
4935
4f771f10 4936 intel_crtc->active = true;
8664281b 4937
a72e4c9f 4938 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4939 for_each_encoder_on_crtc(dev, crtc, encoder)
4940 if (encoder->pre_enable)
4941 encoder->pre_enable(encoder);
4942
6e3c9717 4943 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4944 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4945 true);
4fe9467d
ID		 4946 dev_priv->display.fdi_link_train(crtc);
4947 }
4948
1f544388 4949 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4950
ff6d9f55 4951 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4952 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4953 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4954 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4955 else
4956 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4957
4958 /*
4959 * On ILK+ LUT must be loaded before the pipe is running but with
4960 * clocks enabled
4961 */
4962 intel_crtc_load_lut(crtc);
4963
1f544388 4964 intel_ddi_set_pipe_settings(crtc);
8228c251 4965 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4966
f37fcc2a 4967 intel_update_watermarks(crtc);
e1fdc473 4968 intel_enable_pipe(intel_crtc);
42db64ef 4969
6e3c9717 4970 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4971 lpt_pch_enable(crtc);
4f771f10 4972
6e3c9717 4973 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4974 intel_ddi_set_vc_payload_alloc(crtc, true);
4975
f9b61ff6
DV		 4976 assert_vblank_disabled(crtc);
4977 drm_crtc_vblank_on(crtc);
4978
8807e55b 4979 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4980 encoder->enable(encoder);
8807e55b
JN		 4981 intel_opregion_notify_encoder(encoder, true);
4982 }
4f771f10 4983
e4916946
PZ		 4984 /* If we change the relative order between pipe/planes enabling, we need
4985 * to change the workaround. */
99d736a2
ML		 4986 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4987 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4988 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4989 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4990 }
4f771f10
PZ		 4991}
4992
3f8dce3a
DV		 4993static void ironlake_pfit_disable(struct intel_crtc *crtc)
4994{
4995 struct drm_device *dev = crtc->base.dev;
4996 struct drm_i915_private *dev_priv = dev->dev_private;
4997 int pipe = crtc->pipe;
4998
4999 /* To avoid upsetting the power well on haswell only disable the pfit if
5000 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5001 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5002 I915_WRITE(PF_CTL(pipe), 0);
5003 I915_WRITE(PF_WIN_POS(pipe), 0);
5004 I915_WRITE(PF_WIN_SZ(pipe), 0);
5005 }
5006}
5007
6be4a607
JB		 5008static void ironlake_crtc_disable(struct drm_crtc *crtc)
5009{
5010 struct drm_device *dev = crtc->dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5013 struct intel_encoder *encoder;
6be4a607 5014 int pipe = intel_crtc->pipe;
5eddb70b 5015 u32 reg, temp;
b52eb4dc 5016
ea9d758d
DV		 5017 for_each_encoder_on_crtc(dev, crtc, encoder)
5018 encoder->disable(encoder);
5019
f9b61ff6
DV		 5020 drm_crtc_vblank_off(crtc);
5021 assert_vblank_disabled(crtc);
5022
6e3c9717 5023 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5024 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5025
575f7ab7 5026 intel_disable_pipe(intel_crtc);
32f9d658 5027
3f8dce3a 5028 ironlake_pfit_disable(intel_crtc);
2c07245f 5029
5a74f70a
VS		 5030 if (intel_crtc->config->has_pch_encoder)
5031 ironlake_fdi_disable(crtc);
5032
bf49ec8c
DV		 5033 for_each_encoder_on_crtc(dev, crtc, encoder)
5034 if (encoder->post_disable)
5035 encoder->post_disable(encoder);
2c07245f 5036
6e3c9717 5037 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5038 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5039
d925c59a
DV		 5040 if (HAS_PCH_CPT(dev)) {
5041 /* disable TRANS_DP_CTL */
5042 reg = TRANS_DP_CTL(pipe);
5043 temp = I915_READ(reg);
5044 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5045 TRANS_DP_PORT_SEL_MASK);
5046 temp |= TRANS_DP_PORT_SEL_NONE;
5047 I915_WRITE(reg, temp);
5048
5049 /* disable DPLL_SEL */
5050 temp = I915_READ(PCH_DPLL_SEL);
11887397 5051 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5052 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5053 }
e3421a18 5054
d925c59a
DV		 5055 ironlake_fdi_pll_disable(intel_crtc);
5056 }
6be4a607 5057}
1b3c7a47 5058
4f771f10 5059static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5060{
4f771f10
PZ		 5061 struct drm_device *dev = crtc->dev;
5062 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5064 struct intel_encoder *encoder;
6e3c9717 5065 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5066
8807e55b
JN		 5067 for_each_encoder_on_crtc(dev, crtc, encoder) {
5068 intel_opregion_notify_encoder(encoder, false);
4f771f10 5069 encoder->disable(encoder);
8807e55b 5070 }
4f771f10 5071
f9b61ff6
DV		 5072 drm_crtc_vblank_off(crtc);
5073 assert_vblank_disabled(crtc);
5074
6e3c9717 5075 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5076 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5077 false);
575f7ab7 5078 intel_disable_pipe(intel_crtc);
4f771f10 5079
6e3c9717 5080 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5081 intel_ddi_set_vc_payload_alloc(crtc, false);
5082
ad80a810 5083 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5084
ff6d9f55 5085 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5086 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5087 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5088 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5089 else
5090 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5091
1f544388 5092 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5093
6e3c9717 5094 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5095 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5096 intel_ddi_fdi_disable(crtc);
83616634 5097 }
4f771f10 5098
97b040aa
ID		 5099 for_each_encoder_on_crtc(dev, crtc, encoder)
5100 if (encoder->post_disable)
5101 encoder->post_disable(encoder);
4f771f10
PZ		 5102}
5103
2dd24552
JB		 5104static void i9xx_pfit_enable(struct intel_crtc *crtc)
5105{
5106 struct drm_device *dev = crtc->base.dev;
5107 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5108 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5109
681a8504 5110 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5111 return;
5112
2dd24552 5113 /*
c0b03411
DV		 5114 * The panel fitter should only be adjusted whilst the pipe is disabled,
5115 * according to register description and PRM.
2dd24552 5116 */
c0b03411
DV		 5117 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5118 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5119
b074cec8
JB		 5120 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5121 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5122
5123 /* Border color in case we don't scale up to the full screen. Black by
5124 * default, change to something else for debugging. */
5125 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5126}
5127
d05410f9
DA		 5128static enum intel_display_power_domain port_to_power_domain(enum port port)
5129{
5130 switch (port) {
5131 case PORT_A:
5132 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5133 case PORT_B:
5134 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5135 case PORT_C:
5136 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5137 case PORT_D:
5138 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5139 default:
5140 WARN_ON_ONCE(1);
5141 return POWER_DOMAIN_PORT_OTHER;
5142 }
5143}
5144
77d22dca
ID		 5145#define for_each_power_domain(domain, mask) \
5146 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5147 if ((1 << (domain)) & (mask))
5148
319be8ae
ID		 5149enum intel_display_power_domain
5150intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5151{
5152 struct drm_device *dev = intel_encoder->base.dev;
5153 struct intel_digital_port *intel_dig_port;
5154
5155 switch (intel_encoder->type) {
5156 case INTEL_OUTPUT_UNKNOWN:
5157 /* Only DDI platforms should ever use this output type */
5158 WARN_ON_ONCE(!HAS_DDI(dev));
5159 case INTEL_OUTPUT_DISPLAYPORT:
5160 case INTEL_OUTPUT_HDMI:
5161 case INTEL_OUTPUT_EDP:
5162 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5163 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5164 case INTEL_OUTPUT_DP_MST:
5165 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5166 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5167 case INTEL_OUTPUT_ANALOG:
5168 return POWER_DOMAIN_PORT_CRT;
5169 case INTEL_OUTPUT_DSI:
5170 return POWER_DOMAIN_PORT_DSI;
5171 default:
5172 return POWER_DOMAIN_PORT_OTHER;
5173 }
5174}
5175
5176static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5177{
319be8ae
ID		 5178 struct drm_device *dev = crtc->dev;
5179 struct intel_encoder *intel_encoder;
5180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5181 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5182 unsigned long mask;
5183 enum transcoder transcoder;
5184
5185 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5186
5187 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5188 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5189 if (intel_crtc->config->pch_pfit.enabled ||
5190 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5191 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5192
319be8ae
ID		 5193 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5194 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5195
77d22dca
ID		 5196 return mask;
5197}
5198
679dacd4 5199static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5200{
679dacd4 5201 struct drm_device *dev = state->dev;
77d22dca
ID		 5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5204 struct intel_crtc *crtc;
5205
5206 /*
5207 * First get all needed power domains, then put all unneeded, to avoid
5208 * any unnecessary toggling of the power wells.
5209 */
d3fcc808 5210 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5211 enum intel_display_power_domain domain;
5212
83d65738 5213 if (!crtc->base.state->enable)
77d22dca
ID		 5214 continue;
5215
319be8ae 5216 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5217
5218 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5219 intel_display_power_get(dev_priv, domain);
5220 }
5221
27c329ed
ML		 5222 if (dev_priv->display.modeset_commit_cdclk) {
5223 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5224
5225 if (cdclk != dev_priv->cdclk_freq &&
5226 !WARN_ON(!state->allow_modeset))
5227 dev_priv->display.modeset_commit_cdclk(state);
5228 }
50f6e502 5229
d3fcc808 5230 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5231 enum intel_display_power_domain domain;
5232
5233 for_each_power_domain(domain, crtc->enabled_power_domains)
5234 intel_display_power_put(dev_priv, domain);
5235
5236 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5237 }
5238
5239 intel_display_set_init_power(dev_priv, false);
5240}
5241
560a7ae4
DL		 5242static void intel_update_max_cdclk(struct drm_device *dev)
5243{
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5245
5246 if (IS_SKYLAKE(dev)) {
5247 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5248
5249 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5250 dev_priv->max_cdclk_freq = 675000;
5251 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5252 dev_priv->max_cdclk_freq = 540000;
5253 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5254 dev_priv->max_cdclk_freq = 450000;
5255 else
5256 dev_priv->max_cdclk_freq = 337500;
5257 } else if (IS_BROADWELL(dev)) {
5258 /*
5259 * FIXME with extra cooling we can allow
5260 * 540 MHz for ULX and 675 Mhz for ULT.
5261 * How can we know if extra cooling is
5262 * available? PCI ID, VTB, something else?
5263 */
5264 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5265 dev_priv->max_cdclk_freq = 450000;
5266 else if (IS_BDW_ULX(dev))
5267 dev_priv->max_cdclk_freq = 450000;
5268 else if (IS_BDW_ULT(dev))
5269 dev_priv->max_cdclk_freq = 540000;
5270 else
5271 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5272 } else if (IS_CHERRYVIEW(dev)) {
5273 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5274 } else if (IS_VALLEYVIEW(dev)) {
5275 dev_priv->max_cdclk_freq = 400000;
5276 } else {
5277 /* otherwise assume cdclk is fixed */
5278 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5279 }
5280
5281 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5282 dev_priv->max_cdclk_freq);
5283}
5284
5285static void intel_update_cdclk(struct drm_device *dev)
5286{
5287 struct drm_i915_private *dev_priv = dev->dev_private;
5288
5289 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5290 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5291 dev_priv->cdclk_freq);
5292
5293 /*
5294 * Program the gmbus_freq based on the cdclk frequency.
5295 * BSpec erroneously claims we should aim for 4MHz, but
5296 * in fact 1MHz is the correct frequency.
5297 */
5298 if (IS_VALLEYVIEW(dev)) {
5299 /*
5300 * Program the gmbus_freq based on the cdclk frequency.
5301 * BSpec erroneously claims we should aim for 4MHz, but
5302 * in fact 1MHz is the correct frequency.
5303 */
5304 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5305 }
5306
5307 if (dev_priv->max_cdclk_freq == 0)
5308 intel_update_max_cdclk(dev);
5309}
5310
70d0c574 5311static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5312{
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 uint32_t divider;
5315 uint32_t ratio;
5316 uint32_t current_freq;
5317 int ret;
5318
5319 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5320 switch (frequency) {
5321 case 144000:
5322 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5323 ratio = BXT_DE_PLL_RATIO(60);
5324 break;
5325 case 288000:
5326 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5327 ratio = BXT_DE_PLL_RATIO(60);
5328 break;
5329 case 384000:
5330 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5331 ratio = BXT_DE_PLL_RATIO(60);
5332 break;
5333 case 576000:
5334 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5335 ratio = BXT_DE_PLL_RATIO(60);
5336 break;
5337 case 624000:
5338 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5339 ratio = BXT_DE_PLL_RATIO(65);
5340 break;
5341 case 19200:
5342 /*
5343 * Bypass frequency with DE PLL disabled. Init ratio, divider
5344 * to suppress GCC warning.
5345 */
5346 ratio = 0;
5347 divider = 0;
5348 break;
5349 default:
5350 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5351
5352 return;
5353 }
5354
5355 mutex_lock(&dev_priv->rps.hw_lock);
5356 /* Inform power controller of upcoming frequency change */
5357 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5358 0x80000000);
5359 mutex_unlock(&dev_priv->rps.hw_lock);
5360
5361 if (ret) {
5362 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5363 ret, frequency);
5364 return;
5365 }
5366
5367 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5368 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5369 current_freq = current_freq * 500 + 1000;
5370
5371 /*
5372 * DE PLL has to be disabled when
5373 * - setting to 19.2MHz (bypass, PLL isn't used)
5374 * - before setting to 624MHz (PLL needs toggling)
5375 * - before setting to any frequency from 624MHz (PLL needs toggling)
5376 */
5377 if (frequency == 19200 || frequency == 624000 ||
5378 current_freq == 624000) {
5379 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5380 /* Timeout 200us */
5381 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5382 1))
5383 DRM_ERROR("timout waiting for DE PLL unlock\n");
5384 }
5385
5386 if (frequency != 19200) {
5387 uint32_t val;
5388
5389 val = I915_READ(BXT_DE_PLL_CTL);
5390 val &= ~BXT_DE_PLL_RATIO_MASK;
5391 val |= ratio;
5392 I915_WRITE(BXT_DE_PLL_CTL, val);
5393
5394 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5395 /* Timeout 200us */
5396 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5397 DRM_ERROR("timeout waiting for DE PLL lock\n");
5398
5399 val = I915_READ(CDCLK_CTL);
5400 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5401 val |= divider;
5402 /*
5403 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5404 * enable otherwise.
5405 */
5406 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5407 if (frequency >= 500000)
5408 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5409
5410 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5411 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5412 val |= (frequency - 1000) / 500;
5413 I915_WRITE(CDCLK_CTL, val);
5414 }
5415
5416 mutex_lock(&dev_priv->rps.hw_lock);
5417 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5418 DIV_ROUND_UP(frequency, 25000));
5419 mutex_unlock(&dev_priv->rps.hw_lock);
5420
5421 if (ret) {
5422 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5423 ret, frequency);
5424 return;
5425 }
5426
a47871bd 5427 intel_update_cdclk(dev);
f8437dd1
VK		 5428}
5429
5430void broxton_init_cdclk(struct drm_device *dev)
5431{
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 uint32_t val;
5434
5435 /*
5436 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5437 * or else the reset will hang because there is no PCH to respond.
5438 * Move the handshake programming to initialization sequence.
5439 * Previously was left up to BIOS.
5440 */
5441 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5442 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5443 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5444
5445 /* Enable PG1 for cdclk */
5446 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5447
5448 /* check if cd clock is enabled */
5449 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5450 DRM_DEBUG_KMS("Display already initialized\n");
5451 return;
5452 }
5453
5454 /*
5455 * FIXME:
5456 * - The initial CDCLK needs to be read from VBT.
5457 * Need to make this change after VBT has changes for BXT.
5458 * - check if setting the max (or any) cdclk freq is really necessary
5459 * here, it belongs to modeset time
5460 */
5461 broxton_set_cdclk(dev, 624000);
5462
5463 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5464 POSTING_READ(DBUF_CTL);
5465
f8437dd1
VK		 5466 udelay(10);
5467
5468 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5469 DRM_ERROR("DBuf power enable timeout!\n");
5470}
5471
5472void broxton_uninit_cdclk(struct drm_device *dev)
5473{
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475
5476 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5477 POSTING_READ(DBUF_CTL);
5478
f8437dd1
VK		 5479 udelay(10);
5480
5481 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5482 DRM_ERROR("DBuf power disable timeout!\n");
5483
5484 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5485 broxton_set_cdclk(dev, 19200);
5486
5487 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5488}
5489
5d96d8af
DL		 5490static const struct skl_cdclk_entry {
5491 unsigned int freq;
5492 unsigned int vco;
5493} skl_cdclk_frequencies[] = {
5494 { .freq = 308570, .vco = 8640 },
5495 { .freq = 337500, .vco = 8100 },
5496 { .freq = 432000, .vco = 8640 },
5497 { .freq = 450000, .vco = 8100 },
5498 { .freq = 540000, .vco = 8100 },
5499 { .freq = 617140, .vco = 8640 },
5500 { .freq = 675000, .vco = 8100 },
5501};
5502
5503static unsigned int skl_cdclk_decimal(unsigned int freq)
5504{
5505 return (freq - 1000) / 500;
5506}
5507
5508static unsigned int skl_cdclk_get_vco(unsigned int freq)
5509{
5510 unsigned int i;
5511
5512 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5513 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5514
5515 if (e->freq == freq)
5516 return e->vco;
5517 }
5518
5519 return 8100;
5520}
5521
5522static void
5523skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5524{
5525 unsigned int min_freq;
5526 u32 val;
5527
5528 /* select the minimum CDCLK before enabling DPLL 0 */
5529 val = I915_READ(CDCLK_CTL);
5530 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5531 val |= CDCLK_FREQ_337_308;
5532
5533 if (required_vco == 8640)
5534 min_freq = 308570;
5535 else
5536 min_freq = 337500;
5537
5538 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5539
5540 I915_WRITE(CDCLK_CTL, val);
5541 POSTING_READ(CDCLK_CTL);
5542
5543 /*
5544 * We always enable DPLL0 with the lowest link rate possible, but still
5545 * taking into account the VCO required to operate the eDP panel at the
5546 * desired frequency. The usual DP link rates operate with a VCO of
5547 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5548 * The modeset code is responsible for the selection of the exact link
5549 * rate later on, with the constraint of choosing a frequency that
5550 * works with required_vco.
5551 */
5552 val = I915_READ(DPLL_CTRL1);
5553
5554 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5555 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5556 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5557 if (required_vco == 8640)
5558 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5559 SKL_DPLL0);
5560 else
5561 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5562 SKL_DPLL0);
5563
5564 I915_WRITE(DPLL_CTRL1, val);
5565 POSTING_READ(DPLL_CTRL1);
5566
5567 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5568
5569 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5570 DRM_ERROR("DPLL0 not locked\n");
5571}
5572
5573static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5574{
5575 int ret;
5576 u32 val;
5577
5578 /* inform PCU we want to change CDCLK */
5579 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5580 mutex_lock(&dev_priv->rps.hw_lock);
5581 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5582 mutex_unlock(&dev_priv->rps.hw_lock);
5583
5584 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5585}
5586
5587static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5588{
5589 unsigned int i;
5590
5591 for (i = 0; i < 15; i++) {
5592 if (skl_cdclk_pcu_ready(dev_priv))
5593 return true;
5594 udelay(10);
5595 }
5596
5597 return false;
5598}
5599
5600static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5601{
560a7ae4 5602 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5603 u32 freq_select, pcu_ack;
5604
5605 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5606
5607 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5608 DRM_ERROR("failed to inform PCU about cdclk change\n");
5609 return;
5610 }
5611
5612 /* set CDCLK_CTL */
5613 switch(freq) {
5614 case 450000:
5615 case 432000:
5616 freq_select = CDCLK_FREQ_450_432;
5617 pcu_ack = 1;
5618 break;
5619 case 540000:
5620 freq_select = CDCLK_FREQ_540;
5621 pcu_ack = 2;
5622 break;
5623 case 308570:
5624 case 337500:
5625 default:
5626 freq_select = CDCLK_FREQ_337_308;
5627 pcu_ack = 0;
5628 break;
5629 case 617140:
5630 case 675000:
5631 freq_select = CDCLK_FREQ_675_617;
5632 pcu_ack = 3;
5633 break;
5634 }
5635
5636 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5637 POSTING_READ(CDCLK_CTL);
5638
5639 /* inform PCU of the change */
5640 mutex_lock(&dev_priv->rps.hw_lock);
5641 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5642 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5643
5644 intel_update_cdclk(dev);
5d96d8af
DL		 5645}
5646
5647void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5648{
5649 /* disable DBUF power */
5650 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5651 POSTING_READ(DBUF_CTL);
5652
5653 udelay(10);
5654
5655 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5656 DRM_ERROR("DBuf power disable timeout\n");
5657
5658 /* disable DPLL0 */
5659 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5660 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5661 DRM_ERROR("Couldn't disable DPLL0\n");
5662
5663 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5664}
5665
5666void skl_init_cdclk(struct drm_i915_private *dev_priv)
5667{
5668 u32 val;
5669 unsigned int required_vco;
5670
5671 /* enable PCH reset handshake */
5672 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5673 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5674
5675 /* enable PG1 and Misc I/O */
5676 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5677
5678 /* DPLL0 already enabed !? */
5679 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5680 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5681 return;
5682 }
5683
5684 /* enable DPLL0 */
5685 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5686 skl_dpll0_enable(dev_priv, required_vco);
5687
5688 /* set CDCLK to the frequency the BIOS chose */
5689 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5690
5691 /* enable DBUF power */
5692 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5693 POSTING_READ(DBUF_CTL);
5694
5695 udelay(10);
5696
5697 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5698 DRM_ERROR("DBuf power enable timeout\n");
5699}
5700
dfcab17e 5701/* returns HPLL frequency in kHz */
f8bf63fd 5702static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5703{
586f49dc 5704 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5705
586f49dc 5706 /* Obtain SKU information */
a580516d 5707 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5708 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5709 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5710 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5711
dfcab17e 5712 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5713}
5714
5715/* Adjust CDclk dividers to allow high res or save power if possible */
5716static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5717{
5718 struct drm_i915_private *dev_priv = dev->dev_private;
5719 u32 val, cmd;
5720
164dfd28
VK		 5721 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5722 != dev_priv->cdclk_freq);
d60c4473 5723
dfcab17e 5724 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5725 cmd = 2;
dfcab17e 5726 else if (cdclk == 266667)
30a970c6
JB		 5727 cmd = 1;
5728 else
5729 cmd = 0;
5730
5731 mutex_lock(&dev_priv->rps.hw_lock);
5732 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5733 val &= ~DSPFREQGUAR_MASK;
5734 val |= (cmd << DSPFREQGUAR_SHIFT);
5735 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5736 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5737 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5738 50)) {
5739 DRM_ERROR("timed out waiting for CDclk change\n");
5740 }
5741 mutex_unlock(&dev_priv->rps.hw_lock);
5742
54433e91
VS		 5743 mutex_lock(&dev_priv->sb_lock);
5744
dfcab17e 5745 if (cdclk == 400000) {
6bcda4f0 5746 u32 divider;
30a970c6 5747
6bcda4f0 5748 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5749
30a970c6
JB		 5750 /* adjust cdclk divider */
5751 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5752 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5753 val |= divider;
5754 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5755
5756 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5757 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5758 50))
5759 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5760 }
5761
30a970c6
JB		 5762 /* adjust self-refresh exit latency value */
5763 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5764 val &= ~0x7f;
5765
5766 /*
5767 * For high bandwidth configs, we set a higher latency in the bunit
5768 * so that the core display fetch happens in time to avoid underruns.
5769 */
dfcab17e 5770 if (cdclk == 400000)
30a970c6
JB		 5771 val |= 4500 / 250; /* 4.5 usec */
5772 else
5773 val |= 3000 / 250; /* 3.0 usec */
5774 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5775
a580516d 5776 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5777
b6283055 5778 intel_update_cdclk(dev);
30a970c6
JB		 5779}
5780
383c5a6a
VS		 5781static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5782{
5783 struct drm_i915_private *dev_priv = dev->dev_private;
5784 u32 val, cmd;
5785
164dfd28
VK		 5786 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5787 != dev_priv->cdclk_freq);
383c5a6a
VS		 5788
5789 switch (cdclk) {
383c5a6a
VS		 5790 case 333333:
5791 case 320000:
383c5a6a 5792 case 266667:
383c5a6a 5793 case 200000:
383c5a6a
VS		 5794 break;
5795 default:
5f77eeb0 5796 MISSING_CASE(cdclk);
383c5a6a
VS		 5797 return;
5798 }
5799
9d0d3fda
VS		 5800 /*
5801 * Specs are full of misinformation, but testing on actual
5802 * hardware has shown that we just need to write the desired
5803 * CCK divider into the Punit register.
5804 */
5805 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5806
383c5a6a
VS		 5807 mutex_lock(&dev_priv->rps.hw_lock);
5808 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809 val &= ~DSPFREQGUAR_MASK_CHV;
5810 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5811 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5814 50)) {
5815 DRM_ERROR("timed out waiting for CDclk change\n");
5816 }
5817 mutex_unlock(&dev_priv->rps.hw_lock);
5818
b6283055 5819 intel_update_cdclk(dev);
383c5a6a
VS		 5820}
5821
30a970c6
JB		 5822static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5823 int max_pixclk)
5824{
6bcda4f0 5825 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5826 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5827
30a970c6
JB		 5828 /*
5829 * Really only a few cases to deal with, as only 4 CDclks are supported:
5830 * 200MHz
5831 * 267MHz
29dc7ef3 5832 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5833 * 400MHz (VLV only)
5834 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5835 * of the lower bin and adjust if needed.
e37c67a1
VS		 5836 *
5837 * We seem to get an unstable or solid color picture at 200MHz.
5838 * Not sure what's wrong. For now use 200MHz only when all pipes
5839 * are off.
30a970c6 5840 */
6cca3195
VS		 5841 if (!IS_CHERRYVIEW(dev_priv) &&
5842 max_pixclk > freq_320*limit/100)
dfcab17e 5843 return 400000;
6cca3195 5844 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5845 return freq_320;
e37c67a1 5846 else if (max_pixclk > 0)
dfcab17e 5847 return 266667;
e37c67a1
VS		 5848 else
5849 return 200000;
30a970c6
JB		 5850}
5851
f8437dd1
VK		 5852static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5853 int max_pixclk)
5854{
5855 /*
5856 * FIXME:
5857 * - remove the guardband, it's not needed on BXT
5858 * - set 19.2MHz bypass frequency if there are no active pipes
5859 */
5860 if (max_pixclk > 576000*9/10)
5861 return 624000;
5862 else if (max_pixclk > 384000*9/10)
5863 return 576000;
5864 else if (max_pixclk > 288000*9/10)
5865 return 384000;
5866 else if (max_pixclk > 144000*9/10)
5867 return 288000;
5868 else
5869 return 144000;
5870}
5871
a821fc46
ACO		 5872/* Compute the max pixel clock for new configuration. Uses atomic state if
5873 * that's non-NULL, look at current state otherwise. */
5874static int intel_mode_max_pixclk(struct drm_device *dev,
5875 struct drm_atomic_state *state)
30a970c6 5876{
30a970c6 5877 struct intel_crtc *intel_crtc;
304603f4 5878 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5879 int max_pixclk = 0;
5880
d3fcc808 5881 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5882 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5883 if (IS_ERR(crtc_state))
5884 return PTR_ERR(crtc_state);
5885
5886 if (!crtc_state->base.enable)
5887 continue;
5888
5889 max_pixclk = max(max_pixclk,
5890 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5891 }
5892
5893 return max_pixclk;
5894}
5895
27c329ed 5896static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5897{
27c329ed
ML		 5898 struct drm_device *dev = state->dev;
5899 struct drm_i915_private *dev_priv = dev->dev_private;
5900 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5901
304603f4
ACO		 5902 if (max_pixclk < 0)
5903 return max_pixclk;
30a970c6 5904
27c329ed
ML		 5905 to_intel_atomic_state(state)->cdclk =
5906 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5907
27c329ed
ML		 5908 return 0;
5909}
304603f4 5910
27c329ed
ML		 5911static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5912{
5913 struct drm_device *dev = state->dev;
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5916
27c329ed
ML		 5917 if (max_pixclk < 0)
5918 return max_pixclk;
85a96e7a 5919
27c329ed
ML		 5920 to_intel_atomic_state(state)->cdclk =
5921 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5922
27c329ed 5923 return 0;
30a970c6
JB		 5924}
5925
1e69cd74
VS		 5926static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5927{
5928 unsigned int credits, default_credits;
5929
5930 if (IS_CHERRYVIEW(dev_priv))
5931 default_credits = PFI_CREDIT(12);
5932 else
5933 default_credits = PFI_CREDIT(8);
5934
164dfd28 5935 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5936 /* CHV suggested value is 31 or 63 */
5937 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5938 credits = PFI_CREDIT_63;
1e69cd74
VS		 5939 else
5940 credits = PFI_CREDIT(15);
5941 } else {
5942 credits = default_credits;
5943 }
5944
5945 /*
5946 * WA - write default credits before re-programming
5947 * FIXME: should we also set the resend bit here?
5948 */
5949 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5950 default_credits);
5951
5952 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5953 credits | PFI_CREDIT_RESEND);
5954
5955 /*
5956 * FIXME is this guaranteed to clear
5957 * immediately or should we poll for it?
5958 */
5959 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5960}
5961
27c329ed 5962static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5963{
a821fc46 5964 struct drm_device *dev = old_state->dev;
27c329ed 5965 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5966 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5967
27c329ed
ML		 5968 /*
5969 * FIXME: We can end up here with all power domains off, yet
5970 * with a CDCLK frequency other than the minimum. To account
5971 * for this take the PIPE-A power domain, which covers the HW
5972 * blocks needed for the following programming. This can be
5973 * removed once it's guaranteed that we get here either with
5974 * the minimum CDCLK set, or the required power domains
5975 * enabled.
5976 */
5977 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5978
27c329ed
ML		 5979 if (IS_CHERRYVIEW(dev))
5980 cherryview_set_cdclk(dev, req_cdclk);
5981 else
5982 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5983
27c329ed 5984 vlv_program_pfi_credits(dev_priv);
1e69cd74 5985
27c329ed 5986 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5987}
5988
89b667f8
JB		 5989static void valleyview_crtc_enable(struct drm_crtc *crtc)
5990{
5991 struct drm_device *dev = crtc->dev;
a72e4c9f 5992 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994 struct intel_encoder *encoder;
5995 int pipe = intel_crtc->pipe;
23538ef1 5996 bool is_dsi;
89b667f8 5997
53d9f4e9 5998 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 5999 return;
6000
409ee761 6001 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6002
1ae0d137
VS		 6003 if (!is_dsi) {
6004 if (IS_CHERRYVIEW(dev))
6e3c9717 6005 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6006 else
6e3c9717 6007 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6008 }
5b18e57c 6009
6e3c9717 6010 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6011 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6012
6013 intel_set_pipe_timings(intel_crtc);
6014
c14b0485
VS		 6015 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017
6018 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6019 I915_WRITE(CHV_CANVAS(pipe), 0);
6020 }
6021
5b18e57c
DV		 6022 i9xx_set_pipeconf(intel_crtc);
6023
89b667f8 6024 intel_crtc->active = true;
89b667f8 6025
a72e4c9f 6026 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6027
89b667f8
JB		 6028 for_each_encoder_on_crtc(dev, crtc, encoder)
6029 if (encoder->pre_pll_enable)
6030 encoder->pre_pll_enable(encoder);
6031
9d556c99
CML		 6032 if (!is_dsi) {
6033 if (IS_CHERRYVIEW(dev))
6e3c9717 6034 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6035 else
6e3c9717 6036 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6037 }
89b667f8
JB		 6038
6039 for_each_encoder_on_crtc(dev, crtc, encoder)
6040 if (encoder->pre_enable)
6041 encoder->pre_enable(encoder);
6042
2dd24552
JB		 6043 i9xx_pfit_enable(intel_crtc);
6044
63cbb074
VS		 6045 intel_crtc_load_lut(crtc);
6046
e1fdc473 6047 intel_enable_pipe(intel_crtc);
be6a6f8e 6048
4b3a9526
VS		 6049 assert_vblank_disabled(crtc);
6050 drm_crtc_vblank_on(crtc);
6051
f9b61ff6
DV		 6052 for_each_encoder_on_crtc(dev, crtc, encoder)
6053 encoder->enable(encoder);
89b667f8
JB		 6054}
6055
f13c2ef3
DV		 6056static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6057{
6058 struct drm_device *dev = crtc->base.dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060
6e3c9717
ACO		 6061 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6062 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6063}
6064
0b8765c6 6065static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6066{
6067 struct drm_device *dev = crtc->dev;
a72e4c9f 6068 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6070 struct intel_encoder *encoder;
79e53945 6071 int pipe = intel_crtc->pipe;
79e53945 6072
53d9f4e9 6073 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6074 return;
6075
f13c2ef3
DV		 6076 i9xx_set_pll_dividers(intel_crtc);
6077
6e3c9717 6078 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6079 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6080
6081 intel_set_pipe_timings(intel_crtc);
6082
5b18e57c
DV		 6083 i9xx_set_pipeconf(intel_crtc);
6084
f7abfe8b 6085 intel_crtc->active = true;
6b383a7f 6086
4a3436e8 6087 if (!IS_GEN2(dev))
a72e4c9f 6088 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6089
9d6d9f19
MK		 6090 for_each_encoder_on_crtc(dev, crtc, encoder)
6091 if (encoder->pre_enable)
6092 encoder->pre_enable(encoder);
6093
f6736a1a
DV		 6094 i9xx_enable_pll(intel_crtc);
6095
2dd24552
JB		 6096 i9xx_pfit_enable(intel_crtc);
6097
63cbb074
VS		 6098 intel_crtc_load_lut(crtc);
6099
f37fcc2a 6100 intel_update_watermarks(crtc);
e1fdc473 6101 intel_enable_pipe(intel_crtc);
be6a6f8e 6102
4b3a9526
VS		 6103 assert_vblank_disabled(crtc);
6104 drm_crtc_vblank_on(crtc);
6105
f9b61ff6
DV		 6106 for_each_encoder_on_crtc(dev, crtc, encoder)
6107 encoder->enable(encoder);
0b8765c6 6108}
79e53945 6109
87476d63
DV		 6110static void i9xx_pfit_disable(struct intel_crtc *crtc)
6111{
6112 struct drm_device *dev = crtc->base.dev;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6114
6e3c9717 6115 if (!crtc->config->gmch_pfit.control)
328d8e82 6116 return;
87476d63 6117
328d8e82 6118 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6119
328d8e82
DV		 6120 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6121 I915_READ(PFIT_CONTROL));
6122 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6123}
6124
0b8765c6
JB		 6125static void i9xx_crtc_disable(struct drm_crtc *crtc)
6126{
6127 struct drm_device *dev = crtc->dev;
6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6130 struct intel_encoder *encoder;
0b8765c6 6131 int pipe = intel_crtc->pipe;
ef9c3aee 6132
6304cd91
VS		 6133 /*
6134 * On gen2 planes are double buffered but the pipe isn't, so we must
6135 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6136 * We also need to wait on all gmch platforms because of the
6137 * self-refresh mode constraint explained above.
6304cd91 6138 */
564ed191 6139 intel_wait_for_vblank(dev, pipe);
6304cd91 6140
4b3a9526
VS		 6141 for_each_encoder_on_crtc(dev, crtc, encoder)
6142 encoder->disable(encoder);
6143
f9b61ff6
DV		 6144 drm_crtc_vblank_off(crtc);
6145 assert_vblank_disabled(crtc);
6146
575f7ab7 6147 intel_disable_pipe(intel_crtc);
24a1f16d 6148
87476d63 6149 i9xx_pfit_disable(intel_crtc);
24a1f16d 6150
89b667f8
JB		 6151 for_each_encoder_on_crtc(dev, crtc, encoder)
6152 if (encoder->post_disable)
6153 encoder->post_disable(encoder);
6154
409ee761 6155 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6156 if (IS_CHERRYVIEW(dev))
6157 chv_disable_pll(dev_priv, pipe);
6158 else if (IS_VALLEYVIEW(dev))
6159 vlv_disable_pll(dev_priv, pipe);
6160 else
1c4e0274 6161 i9xx_disable_pll(intel_crtc);
076ed3b2 6162 }
0b8765c6 6163
4a3436e8 6164 if (!IS_GEN2(dev))
a72e4c9f 6165 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6166}
6167
b17d48e2
ML		 6168static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6169{
6170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6171 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6172 enum intel_display_power_domain domain;
6173 unsigned long domains;
6174
6175 if (!intel_crtc->active)
6176 return;
6177
a539205a
ML		 6178 if (to_intel_plane_state(crtc->primary->state)->visible) {
6179 intel_crtc_wait_for_pending_flips(crtc);
6180 intel_pre_disable_primary(crtc);
6181 }
6182
d032ffa0 6183 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6184 dev_priv->display.crtc_disable(crtc);
6185
6186 domains = intel_crtc->enabled_power_domains;
6187 for_each_power_domain(domain, domains)
6188 intel_display_power_put(dev_priv, domain);
6189 intel_crtc->enabled_power_domains = 0;
6190}
6191
6b72d486
ML		 6192/*
6193 * turn all crtc's off, but do not adjust state
6194 * This has to be paired with a call to intel_modeset_setup_hw_state.
6195 */
9716c691 6196void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6197{
6b72d486
ML		 6198 struct drm_crtc *crtc;
6199
b17d48e2
ML		 6200 for_each_crtc(dev, crtc)
6201 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6202}
6203
b04c5bd6 6204/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6205int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6206{
6207 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6208 struct drm_mode_config *config = &dev->mode_config;
6209 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6211 struct intel_crtc_state *pipe_config;
6212 struct drm_atomic_state *state;
6213 int ret;
976f8a20 6214
1b509259 6215 if (enable == intel_crtc->active)
5da76e94 6216 return 0;
0e572fe7 6217
1b509259 6218 if (enable && !crtc->state->enable)
5da76e94 6219 return 0;
1b509259 6220
5da76e94
ML		 6221 /* this function should be called with drm_modeset_lock_all for now */
6222 if (WARN_ON(!ctx))
6223 return -EIO;
6224 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6225
5da76e94
ML		 6226 state = drm_atomic_state_alloc(dev);
6227 if (WARN_ON(!state))
6228 return -ENOMEM;
1b509259 6229
5da76e94
ML		 6230 state->acquire_ctx = ctx;
6231 state->allow_modeset = true;
6232
6233 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6234 if (IS_ERR(pipe_config)) {
6235 ret = PTR_ERR(pipe_config);
6236 goto err;
0e572fe7 6237 }
5da76e94
ML		 6238 pipe_config->base.active = enable;
6239
6240 ret = intel_set_mode(state);
6241 if (!ret)
6242 return ret;
6243
6244err:
6245 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6246 drm_atomic_state_free(state);
6247 return ret;
b04c5bd6
BF		 6248}
6249
6250/**
6251 * Sets the power management mode of the pipe and plane.
6252 */
6253void intel_crtc_update_dpms(struct drm_crtc *crtc)
6254{
6255 struct drm_device *dev = crtc->dev;
6256 struct intel_encoder *intel_encoder;
6257 bool enable = false;
6258
6259 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6260 enable |= intel_encoder->connectors_active;
6261
6262 intel_crtc_control(crtc, enable);
cdd59983
CW		 6263}
6264
ea5b213a 6265void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6266{
4ef69c7a 6267 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6268
ea5b213a
CW		 6269 drm_encoder_cleanup(encoder);
6270 kfree(intel_encoder);
7e7d76c3
JB		 6271}
6272
9237329d 6273/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6274 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6275 * state of the entire output pipe. */
9237329d 6276static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6277{
5ab432ef
DV		 6278 if (mode == DRM_MODE_DPMS_ON) {
6279 encoder->connectors_active = true;
6280
b2cabb0e 6281 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6282 } else {
6283 encoder->connectors_active = false;
6284
b2cabb0e 6285 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6286 }
79e53945
JB		 6287}
6288
0a91ca29
DV		 6289/* Cross check the actual hw state with our own modeset state tracking (and it's
6290 * internal consistency). */
b980514c 6291static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6292{
0a91ca29
DV		 6293 if (connector->get_hw_state(connector)) {
6294 struct intel_encoder *encoder = connector->encoder;
6295 struct drm_crtc *crtc;
6296 bool encoder_enabled;
6297 enum pipe pipe;
6298
6299 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6300 connector->base.base.id,
c23cc417 6301 connector->base.name);
0a91ca29 6302
0e32b39c
DA		 6303 /* there is no real hw state for MST connectors */
6304 if (connector->mst_port)
6305 return;
6306
e2c719b7 6307 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6308 "wrong connector dpms state\n");
e2c719b7 6309 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6310 "active connector not linked to encoder\n");
0a91ca29 6311
36cd7444 6312 if (encoder) {
e2c719b7 6313 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6314 "encoder->connectors_active not set\n");
6315
6316 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6317 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6318 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6319 return;
0a91ca29 6320
36cd7444 6321 crtc = encoder->base.crtc;
0a91ca29 6322
83d65738
MR		 6323 I915_STATE_WARN(!crtc->state->enable,
6324 "crtc not enabled\n");
e2c719b7
RC		 6325 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6326 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6327 "encoder active on the wrong pipe\n");
6328 }
0a91ca29 6329 }
79e53945
JB		 6330}
6331
08d9bc92
ACO		 6332int intel_connector_init(struct intel_connector *connector)
6333{
6334 struct drm_connector_state *connector_state;
6335
6336 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6337 if (!connector_state)
6338 return -ENOMEM;
6339
6340 connector->base.state = connector_state;
6341 return 0;
6342}
6343
6344struct intel_connector *intel_connector_alloc(void)
6345{
6346 struct intel_connector *connector;
6347
6348 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6349 if (!connector)
6350 return NULL;
6351
6352 if (intel_connector_init(connector) < 0) {
6353 kfree(connector);
6354 return NULL;
6355 }
6356
6357 return connector;
6358}
6359
5ab432ef
DV		 6360/* Even simpler default implementation, if there's really no special case to
6361 * consider. */
6362void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6363{
5ab432ef
DV		 6364 /* All the simple cases only support two dpms states. */
6365 if (mode != DRM_MODE_DPMS_ON)
6366 mode = DRM_MODE_DPMS_OFF;
d4270e57 6367
5ab432ef
DV		 6368 if (mode == connector->dpms)
6369 return;
6370
6371 connector->dpms = mode;
6372
6373 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6374 if (connector->encoder)
6375 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6376
b980514c 6377 intel_modeset_check_state(connector->dev);
79e53945
JB		 6378}
6379
f0947c37
DV		 6380/* Simple connector->get_hw_state implementation for encoders that support only
6381 * one connector and no cloning and hence the encoder state determines the state
6382 * of the connector. */
6383bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6384{
24929352 6385 enum pipe pipe = 0;
f0947c37 6386 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6387
f0947c37 6388 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6389}
6390
6d293983 6391static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6392{
6d293983
ACO		 6393 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6394 return crtc_state->fdi_lanes;
d272ddfa
VS		 6395
6396 return 0;
6397}
6398
6d293983 6399static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6400 struct intel_crtc_state *pipe_config)
1857e1da 6401{
6d293983
ACO		 6402 struct drm_atomic_state *state = pipe_config->base.state;
6403 struct intel_crtc *other_crtc;
6404 struct intel_crtc_state *other_crtc_state;
6405
1857e1da
DV		 6406 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6407 pipe_name(pipe), pipe_config->fdi_lanes);
6408 if (pipe_config->fdi_lanes > 4) {
6409 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6410 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6411 return -EINVAL;
1857e1da
DV		 6412 }
6413
bafb6553 6414 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6415 if (pipe_config->fdi_lanes > 2) {
6416 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6417 pipe_config->fdi_lanes);
6d293983 6418 return -EINVAL;
1857e1da 6419 } else {
6d293983 6420 return 0;
1857e1da
DV		 6421 }
6422 }
6423
6424 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6425 return 0;
1857e1da
DV		 6426
6427 /* Ivybridge 3 pipe is really complicated */
6428 switch (pipe) {
6429 case PIPE_A:
6d293983 6430 return 0;
1857e1da 6431 case PIPE_B:
6d293983
ACO		 6432 if (pipe_config->fdi_lanes <= 2)
6433 return 0;
6434
6435 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6436 other_crtc_state =
6437 intel_atomic_get_crtc_state(state, other_crtc);
6438 if (IS_ERR(other_crtc_state))
6439 return PTR_ERR(other_crtc_state);
6440
6441 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6442 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6443 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6444 return -EINVAL;
1857e1da 6445 }
6d293983 6446 return 0;
1857e1da 6447 case PIPE_C:
251cc67c
VS		 6448 if (pipe_config->fdi_lanes > 2) {
6449 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6451 return -EINVAL;
251cc67c 6452 }
6d293983
ACO		 6453
6454 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6455 other_crtc_state =
6456 intel_atomic_get_crtc_state(state, other_crtc);
6457 if (IS_ERR(other_crtc_state))
6458 return PTR_ERR(other_crtc_state);
6459
6460 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6461 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6462 return -EINVAL;
1857e1da 6463 }
6d293983 6464 return 0;
1857e1da
DV		 6465 default:
6466 BUG();
6467 }
6468}
6469
e29c22c0
DV		 6470#define RETRY 1
6471static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6472 struct intel_crtc_state *pipe_config)
877d48d5 6473{
1857e1da 6474 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6475 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6476 int lane, link_bw, fdi_dotclock, ret;
6477 bool needs_recompute = false;
877d48d5 6478
e29c22c0 6479retry:
877d48d5
DV		 6480 /* FDI is a binary signal running at ~2.7GHz, encoding
6481 * each output octet as 10 bits. The actual frequency
6482 * is stored as a divider into a 100MHz clock, and the
6483 * mode pixel clock is stored in units of 1KHz.
6484 * Hence the bw of each lane in terms of the mode signal
6485 * is:
6486 */
6487 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6488
241bfc38 6489 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6490
2bd89a07 6491 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6492 pipe_config->pipe_bpp);
6493
6494 pipe_config->fdi_lanes = lane;
6495
2bd89a07 6496 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6497 link_bw, &pipe_config->fdi_m_n);
1857e1da 6498
6d293983
ACO		 6499 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6500 intel_crtc->pipe, pipe_config);
6501 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6502 pipe_config->pipe_bpp -= 2*3;
6503 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6504 pipe_config->pipe_bpp);
6505 needs_recompute = true;
6506 pipe_config->bw_constrained = true;
6507
6508 goto retry;
6509 }
6510
6511 if (needs_recompute)
6512 return RETRY;
6513
6d293983 6514 return ret;
877d48d5
DV		 6515}
6516
8cfb3407
VS		 6517static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6518 struct intel_crtc_state *pipe_config)
6519{
6520 if (pipe_config->pipe_bpp > 24)
6521 return false;
6522
6523 /* HSW can handle pixel rate up to cdclk? */
6524 if (IS_HASWELL(dev_priv->dev))
6525 return true;
6526
6527 /*
b432e5cf
VS		 6528 * We compare against max which means we must take
6529 * the increased cdclk requirement into account when
6530 * calculating the new cdclk.
6531 *
6532 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6533 */
6534 return ilk_pipe_pixel_rate(pipe_config) <=
6535 dev_priv->max_cdclk_freq * 95 / 100;
6536}
6537
42db64ef 6538static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6539 struct intel_crtc_state *pipe_config)
42db64ef 6540{
8cfb3407
VS		 6541 struct drm_device *dev = crtc->base.dev;
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543
d330a953 6544 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6545 hsw_crtc_supports_ips(crtc) &&
6546 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6547}
6548
a43f6e0f 6549static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6550 struct intel_crtc_state *pipe_config)
79e53945 6551{
a43f6e0f 6552 struct drm_device *dev = crtc->base.dev;
8bd31e67 6553 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6554 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6555
ad3a4479 6556 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6557 if (INTEL_INFO(dev)->gen < 4) {
44913155 6558 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6559
6560 /*
6561 * Enable pixel doubling when the dot clock
6562 * is > 90% of the (display) core speed.
6563 *
b397c96b
VS		 6564 * GDG double wide on either pipe,
6565 * otherwise pipe A only.
cf532bb2 6566 */
b397c96b 6567 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6568 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6569 clock_limit *= 2;
cf532bb2 6570 pipe_config->double_wide = true;
ad3a4479
VS		 6571 }
6572
241bfc38 6573 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6574 return -EINVAL;
2c07245f 6575 }
89749350 6576
1d1d0e27
VS		 6577 /*
6578 * Pipe horizontal size must be even in:
6579 * - DVO ganged mode
6580 * - LVDS dual channel mode
6581 * - Double wide pipe
6582 */
a93e255f 6583 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6584 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6585 pipe_config->pipe_src_w &= ~1;
6586
8693a824
DL		 6587 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6588 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6589 */
6590 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6591 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6592 return -EINVAL;
44f46b42 6593
f5adf94e 6594 if (HAS_IPS(dev))
a43f6e0f
DV		 6595 hsw_compute_ips_config(crtc, pipe_config);
6596
877d48d5 6597 if (pipe_config->has_pch_encoder)
a43f6e0f 6598 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6599
cf5a15be 6600 return 0;
79e53945
JB		 6601}
6602
1652d19e
VS		 6603static int skylake_get_display_clock_speed(struct drm_device *dev)
6604{
6605 struct drm_i915_private *dev_priv = to_i915(dev);
6606 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6607 uint32_t cdctl = I915_READ(CDCLK_CTL);
6608 uint32_t linkrate;
6609
414355a7 6610 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6611 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6612
6613 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6614 return 540000;
6615
6616 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6617 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6618
71cd8423
DL		 6619 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6620 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6621 /* vco 8640 */
6622 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6623 case CDCLK_FREQ_450_432:
6624 return 432000;
6625 case CDCLK_FREQ_337_308:
6626 return 308570;
6627 case CDCLK_FREQ_675_617:
6628 return 617140;
6629 default:
6630 WARN(1, "Unknown cd freq selection\n");
6631 }
6632 } else {
6633 /* vco 8100 */
6634 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6635 case CDCLK_FREQ_450_432:
6636 return 450000;
6637 case CDCLK_FREQ_337_308:
6638 return 337500;
6639 case CDCLK_FREQ_675_617:
6640 return 675000;
6641 default:
6642 WARN(1, "Unknown cd freq selection\n");
6643 }
6644 }
6645
6646 /* error case, do as if DPLL0 isn't enabled */
6647 return 24000;
6648}
6649
acd3f3d3
BP		 6650static int broxton_get_display_clock_speed(struct drm_device *dev)
6651{
6652 struct drm_i915_private *dev_priv = to_i915(dev);
6653 uint32_t cdctl = I915_READ(CDCLK_CTL);
6654 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6655 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6656 int cdclk;
6657
6658 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6659 return 19200;
6660
6661 cdclk = 19200 * pll_ratio / 2;
6662
6663 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6664 case BXT_CDCLK_CD2X_DIV_SEL_1:
6665 return cdclk; /* 576MHz or 624MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6667 return cdclk * 2 / 3; /* 384MHz */
6668 case BXT_CDCLK_CD2X_DIV_SEL_2:
6669 return cdclk / 2; /* 288MHz */
6670 case BXT_CDCLK_CD2X_DIV_SEL_4:
6671 return cdclk / 4; /* 144MHz */
6672 }
6673
6674 /* error case, do as if DE PLL isn't enabled */
6675 return 19200;
6676}
6677
1652d19e
VS		 6678static int broadwell_get_display_clock_speed(struct drm_device *dev)
6679{
6680 struct drm_i915_private *dev_priv = dev->dev_private;
6681 uint32_t lcpll = I915_READ(LCPLL_CTL);
6682 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6683
6684 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6685 return 800000;
6686 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6687 return 450000;
6688 else if (freq == LCPLL_CLK_FREQ_450)
6689 return 450000;
6690 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6691 return 540000;
6692 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6693 return 337500;
6694 else
6695 return 675000;
6696}
6697
6698static int haswell_get_display_clock_speed(struct drm_device *dev)
6699{
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 uint32_t lcpll = I915_READ(LCPLL_CTL);
6702 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6703
6704 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6705 return 800000;
6706 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6707 return 450000;
6708 else if (freq == LCPLL_CLK_FREQ_450)
6709 return 450000;
6710 else if (IS_HSW_ULT(dev))
6711 return 337500;
6712 else
6713 return 540000;
79e53945
JB		 6714}
6715
25eb05fc
JB		 6716static int valleyview_get_display_clock_speed(struct drm_device *dev)
6717{
d197b7d3 6718 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6719 u32 val;
6720 int divider;
6721
6bcda4f0
VS		 6722 if (dev_priv->hpll_freq == 0)
6723 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6724
a580516d 6725 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6726 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6727 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6728
6729 divider = val & DISPLAY_FREQUENCY_VALUES;
6730
7d007f40
VS		 6731 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6732 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6733 "cdclk change in progress\n");
6734
6bcda4f0 6735 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6736}
6737
b37a6434
VS		 6738static int ilk_get_display_clock_speed(struct drm_device *dev)
6739{
6740 return 450000;
6741}
6742
e70236a8
JB		 6743static int i945_get_display_clock_speed(struct drm_device *dev)
6744{
6745 return 400000;
6746}
79e53945 6747
e70236a8 6748static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6749{
e907f170 6750 return 333333;
e70236a8 6751}
79e53945 6752
e70236a8
JB		 6753static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6754{
6755 return 200000;
6756}
79e53945 6757
257a7ffc
DV		 6758static int pnv_get_display_clock_speed(struct drm_device *dev)
6759{
6760 u16 gcfgc = 0;
6761
6762 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6763
6764 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6765 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6766 return 266667;
257a7ffc 6767 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6768 return 333333;
257a7ffc 6769 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6770 return 444444;
257a7ffc
DV		 6771 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6772 return 200000;
6773 default:
6774 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6775 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6776 return 133333;
257a7ffc 6777 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6778 return 166667;
257a7ffc
DV		 6779 }
6780}
6781
e70236a8
JB		 6782static int i915gm_get_display_clock_speed(struct drm_device *dev)
6783{
6784 u16 gcfgc = 0;
79e53945 6785
e70236a8
JB		 6786 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6787
6788 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6789 return 133333;
e70236a8
JB		 6790 else {
6791 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6792 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6793 return 333333;
e70236a8
JB		 6794 default:
6795 case GC_DISPLAY_CLOCK_190_200_MHZ:
6796 return 190000;
79e53945 6797 }
e70236a8
JB		 6798 }
6799}
6800
6801static int i865_get_display_clock_speed(struct drm_device *dev)
6802{
e907f170 6803 return 266667;
e70236a8
JB		 6804}
6805
1b1d2716 6806static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6807{
6808 u16 hpllcc = 0;
1b1d2716 6809
65cd2b3f
VS		 6810 /*
6811 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6812 * encoding is different :(
6813 * FIXME is this the right way to detect 852GM/852GMV?
6814 */
6815 if (dev->pdev->revision == 0x1)
6816 return 133333;
6817
1b1d2716
VS		 6818 pci_bus_read_config_word(dev->pdev->bus,
6819 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6820
e70236a8
JB		 6821 /* Assume that the hardware is in the high speed state. This
6822 * should be the default.
6823 */
6824 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6825 case GC_CLOCK_133_200:
1b1d2716 6826 case GC_CLOCK_133_200_2:
e70236a8
JB		 6827 case GC_CLOCK_100_200:
6828 return 200000;
6829 case GC_CLOCK_166_250:
6830 return 250000;
6831 case GC_CLOCK_100_133:
e907f170 6832 return 133333;
1b1d2716
VS		 6833 case GC_CLOCK_133_266:
6834 case GC_CLOCK_133_266_2:
6835 case GC_CLOCK_166_266:
6836 return 266667;
e70236a8 6837 }
79e53945 6838
e70236a8
JB		 6839 /* Shouldn't happen */
6840 return 0;
6841}
79e53945 6842
e70236a8
JB		 6843static int i830_get_display_clock_speed(struct drm_device *dev)
6844{
e907f170 6845 return 133333;
79e53945
JB		 6846}
6847
34edce2f
VS		 6848static unsigned int intel_hpll_vco(struct drm_device *dev)
6849{
6850 struct drm_i915_private *dev_priv = dev->dev_private;
6851 static const unsigned int blb_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 4800000,
6856 [4] = 6400000,
6857 };
6858 static const unsigned int pnv_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 4800000,
6863 [4] = 2666667,
6864 };
6865 static const unsigned int cl_vco[8] = {
6866 [0] = 3200000,
6867 [1] = 4000000,
6868 [2] = 5333333,
6869 [3] = 6400000,
6870 [4] = 3333333,
6871 [5] = 3566667,
6872 [6] = 4266667,
6873 };
6874 static const unsigned int elk_vco[8] = {
6875 [0] = 3200000,
6876 [1] = 4000000,
6877 [2] = 5333333,
6878 [3] = 4800000,
6879 };
6880 static const unsigned int ctg_vco[8] = {
6881 [0] = 3200000,
6882 [1] = 4000000,
6883 [2] = 5333333,
6884 [3] = 6400000,
6885 [4] = 2666667,
6886 [5] = 4266667,
6887 };
6888 const unsigned int *vco_table;
6889 unsigned int vco;
6890 uint8_t tmp = 0;
6891
6892 /* FIXME other chipsets? */
6893 if (IS_GM45(dev))
6894 vco_table = ctg_vco;
6895 else if (IS_G4X(dev))
6896 vco_table = elk_vco;
6897 else if (IS_CRESTLINE(dev))
6898 vco_table = cl_vco;
6899 else if (IS_PINEVIEW(dev))
6900 vco_table = pnv_vco;
6901 else if (IS_G33(dev))
6902 vco_table = blb_vco;
6903 else
6904 return 0;
6905
6906 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6907
6908 vco = vco_table[tmp & 0x7];
6909 if (vco == 0)
6910 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6911 else
6912 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6913
6914 return vco;
6915}
6916
6917static int gm45_get_display_clock_speed(struct drm_device *dev)
6918{
6919 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6920 uint16_t tmp = 0;
6921
6922 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6923
6924 cdclk_sel = (tmp >> 12) & 0x1;
6925
6926 switch (vco) {
6927 case 2666667:
6928 case 4000000:
6929 case 5333333:
6930 return cdclk_sel ? 333333 : 222222;
6931 case 3200000:
6932 return cdclk_sel ? 320000 : 228571;
6933 default:
6934 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6935 return 222222;
6936 }
6937}
6938
6939static int i965gm_get_display_clock_speed(struct drm_device *dev)
6940{
6941 static const uint8_t div_3200[] = { 16, 10, 8 };
6942 static const uint8_t div_4000[] = { 20, 12, 10 };
6943 static const uint8_t div_5333[] = { 24, 16, 14 };
6944 const uint8_t *div_table;
6945 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6946 uint16_t tmp = 0;
6947
6948 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6949
6950 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6951
6952 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6953 goto fail;
6954
6955 switch (vco) {
6956 case 3200000:
6957 div_table = div_3200;
6958 break;
6959 case 4000000:
6960 div_table = div_4000;
6961 break;
6962 case 5333333:
6963 div_table = div_5333;
6964 break;
6965 default:
6966 goto fail;
6967 }
6968
6969 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6970
caf4e252 6971fail:
34edce2f
VS		 6972 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6973 return 200000;
6974}
6975
6976static int g33_get_display_clock_speed(struct drm_device *dev)
6977{
6978 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6979 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6980 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6981 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6982 const uint8_t *div_table;
6983 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6984 uint16_t tmp = 0;
6985
6986 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6987
6988 cdclk_sel = (tmp >> 4) & 0x7;
6989
6990 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6991 goto fail;
6992
6993 switch (vco) {
6994 case 3200000:
6995 div_table = div_3200;
6996 break;
6997 case 4000000:
6998 div_table = div_4000;
6999 break;
7000 case 4800000:
7001 div_table = div_4800;
7002 break;
7003 case 5333333:
7004 div_table = div_5333;
7005 break;
7006 default:
7007 goto fail;
7008 }
7009
7010 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7011
caf4e252 7012fail:
34edce2f
VS		 7013 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7014 return 190476;
7015}
7016
2c07245f 7017static void
a65851af 7018intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7019{
a65851af
VS		 7020 while (*num > DATA_LINK_M_N_MASK ||
7021 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7022 *num >>= 1;
7023 *den >>= 1;
7024 }
7025}
7026
a65851af
VS		 7027static void compute_m_n(unsigned int m, unsigned int n,
7028 uint32_t *ret_m, uint32_t *ret_n)
7029{
7030 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7031 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7032 intel_reduce_m_n_ratio(ret_m, ret_n);
7033}
7034
e69d0bc1
DV		 7035void
7036intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7037 int pixel_clock, int link_clock,
7038 struct intel_link_m_n *m_n)
2c07245f 7039{
e69d0bc1 7040 m_n->tu = 64;
a65851af
VS		 7041
7042 compute_m_n(bits_per_pixel * pixel_clock,
7043 link_clock * nlanes * 8,
7044 &m_n->gmch_m, &m_n->gmch_n);
7045
7046 compute_m_n(pixel_clock, link_clock,
7047 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7048}
7049
a7615030
CW		 7050static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7051{
d330a953
JN		 7052 if (i915.panel_use_ssc >= 0)
7053 return i915.panel_use_ssc != 0;
41aa3448 7054 return dev_priv->vbt.lvds_use_ssc
435793df 7055 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7056}
7057
a93e255f
ACO		 7058static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7059 int num_connectors)
c65d77d8 7060{
a93e255f 7061 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7062 struct drm_i915_private *dev_priv = dev->dev_private;
7063 int refclk;
7064
a93e255f
ACO		 7065 WARN_ON(!crtc_state->base.state);
7066
5ab7b0b7 7067 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7068 refclk = 100000;
a93e255f 7069 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7070 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7071 refclk = dev_priv->vbt.lvds_ssc_freq;
7072 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7073 } else if (!IS_GEN2(dev)) {
7074 refclk = 96000;
7075 } else {
7076 refclk = 48000;
7077 }
7078
7079 return refclk;
7080}
7081
7429e9d4 7082static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7083{
7df00d7a 7084 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7085}
f47709a9 7086
7429e9d4
DV		 7087static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7088{
7089 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7090}
7091
f47709a9 7092static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7093 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7094 intel_clock_t *reduced_clock)
7095{
f47709a9 7096 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7097 u32 fp, fp2 = 0;
7098
7099 if (IS_PINEVIEW(dev)) {
190f68c5 7100 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7101 if (reduced_clock)
7429e9d4 7102 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7103 } else {
190f68c5 7104 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7105 if (reduced_clock)
7429e9d4 7106 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7107 }
7108
190f68c5 7109 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7110
f47709a9 7111 crtc->lowfreq_avail = false;
a93e255f 7112 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7113 reduced_clock) {
190f68c5 7114 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7115 crtc->lowfreq_avail = true;
a7516a05 7116 } else {
190f68c5 7117 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7118 }
7119}
7120
5e69f97f
CML		 7121static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7122 pipe)
89b667f8
JB		 7123{
7124 u32 reg_val;
7125
7126 /*
7127 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7128 * and set it to a reasonable value instead.
7129 */
ab3c759a 7130 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7131 reg_val &= 0xffffff00;
7132 reg_val |= 0x00000030;
ab3c759a 7133 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7134
ab3c759a 7135 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7136 reg_val &= 0x8cffffff;
7137 reg_val = 0x8c000000;
ab3c759a 7138 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7139
ab3c759a 7140 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7141 reg_val &= 0xffffff00;
ab3c759a 7142 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7143
ab3c759a 7144 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7145 reg_val &= 0x00ffffff;
7146 reg_val |= 0xb0000000;
ab3c759a 7147 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7148}
7149
b551842d
DV		 7150static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7151 struct intel_link_m_n *m_n)
7152{
7153 struct drm_device *dev = crtc->base.dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 int pipe = crtc->pipe;
7156
e3b95f1e
DV		 7157 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7159 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7160 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7161}
7162
7163static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7164 struct intel_link_m_n *m_n,
7165 struct intel_link_m_n *m2_n2)
b551842d
DV		 7166{
7167 struct drm_device *dev = crtc->base.dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 int pipe = crtc->pipe;
6e3c9717 7170 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7171
7172 if (INTEL_INFO(dev)->gen >= 5) {
7173 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7175 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7176 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7177 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7178 * for gen < 8) and if DRRS is supported (to make sure the
7179 * registers are not unnecessarily accessed).
7180 */
44395bfe 7181 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7182 crtc->config->has_drrs) {
f769cd24
VK		 7183 I915_WRITE(PIPE_DATA_M2(transcoder),
7184 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7185 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7186 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7187 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7188 }
b551842d 7189 } else {
e3b95f1e
DV		 7190 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7191 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7192 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7193 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7194 }
7195}
7196
fe3cd48d 7197void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7198{
fe3cd48d
R		 7199 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7200
7201 if (m_n == M1_N1) {
7202 dp_m_n = &crtc->config->dp_m_n;
7203 dp_m2_n2 = &crtc->config->dp_m2_n2;
7204 } else if (m_n == M2_N2) {
7205
7206 /*
7207 * M2_N2 registers are not supported. Hence m2_n2 divider value
7208 * needs to be programmed into M1_N1.
7209 */
7210 dp_m_n = &crtc->config->dp_m2_n2;
7211 } else {
7212 DRM_ERROR("Unsupported divider value\n");
7213 return;
7214 }
7215
6e3c9717
ACO		 7216 if (crtc->config->has_pch_encoder)
7217 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7218 else
fe3cd48d 7219 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7220}
7221
251ac862
DV		 7222static void vlv_compute_dpll(struct intel_crtc *crtc,
7223 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7224{
7225 u32 dpll, dpll_md;
7226
7227 /*
7228 * Enable DPIO clock input. We should never disable the reference
7229 * clock for pipe B, since VGA hotplug / manual detection depends
7230 * on it.
7231 */
7232 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7233 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7234 /* We should never disable this, set it here for state tracking */
7235 if (crtc->pipe == PIPE_B)
7236 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7237 dpll |= DPLL_VCO_ENABLE;
d288f65f 7238 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7239
d288f65f 7240 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7241 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7242 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7243}
7244
d288f65f 7245static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7246 const struct intel_crtc_state *pipe_config)
a0c4da24 7247{
f47709a9 7248 struct drm_device *dev = crtc->base.dev;
a0c4da24 7249 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7250 int pipe = crtc->pipe;
bdd4b6a6 7251 u32 mdiv;
a0c4da24 7252 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7253 u32 coreclk, reg_val;
a0c4da24 7254
a580516d 7255 mutex_lock(&dev_priv->sb_lock);
09153000 7256
d288f65f
VS		 7257 bestn = pipe_config->dpll.n;
7258 bestm1 = pipe_config->dpll.m1;
7259 bestm2 = pipe_config->dpll.m2;
7260 bestp1 = pipe_config->dpll.p1;
7261 bestp2 = pipe_config->dpll.p2;
a0c4da24 7262
89b667f8
JB		 7263 /* See eDP HDMI DPIO driver vbios notes doc */
7264
7265 /* PLL B needs special handling */
bdd4b6a6 7266 if (pipe == PIPE_B)
5e69f97f 7267 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7268
7269 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7270 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7271
7272 /* Disable target IRef on PLL */
ab3c759a 7273 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7274 reg_val &= 0x00ffffff;
ab3c759a 7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7276
7277 /* Disable fast lock */
ab3c759a 7278 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7279
7280 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7281 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7282 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7283 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7284 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7285
7286 /*
7287 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7288 * but we don't support that).
7289 * Note: don't use the DAC post divider as it seems unstable.
7290 */
7291 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7293
a0c4da24 7294 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7296
89b667f8 7297 /* Set HBR and RBR LPF coefficients */
d288f65f 7298 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7299 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7300 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7302 0x009f0003);
89b667f8 7303 else
ab3c759a 7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7305 0x00d0000f);
7306
681a8504 7307 if (pipe_config->has_dp_encoder) {
89b667f8 7308 /* Use SSC source */
bdd4b6a6 7309 if (pipe == PIPE_A)
ab3c759a 7310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7311 0x0df40000);
7312 else
ab3c759a 7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7314 0x0df70000);
7315 } else { /* HDMI or VGA */
7316 /* Use bend source */
bdd4b6a6 7317 if (pipe == PIPE_A)
ab3c759a 7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7319 0x0df70000);
7320 else
ab3c759a 7321 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7322 0x0df40000);
7323 }
a0c4da24 7324
ab3c759a 7325 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7326 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7327 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7328 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7329 coreclk |= 0x01000000;
ab3c759a 7330 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7331
ab3c759a 7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7333 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7334}
7335
251ac862
DV		 7336static void chv_compute_dpll(struct intel_crtc *crtc,
7337 struct intel_crtc_state *pipe_config)
1ae0d137 7338{
d288f65f 7339 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7340 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7341 DPLL_VCO_ENABLE;
7342 if (crtc->pipe != PIPE_A)
d288f65f 7343 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7344
d288f65f
VS		 7345 pipe_config->dpll_hw_state.dpll_md =
7346 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7347}
7348
d288f65f 7349static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7350 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7351{
7352 struct drm_device *dev = crtc->base.dev;
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354 int pipe = crtc->pipe;
7355 int dpll_reg = DPLL(crtc->pipe);
7356 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7357 u32 loopfilter, tribuf_calcntr;
9d556c99 7358 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7359 u32 dpio_val;
9cbe40c1 7360 int vco;
9d556c99 7361
d288f65f
VS		 7362 bestn = pipe_config->dpll.n;
7363 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7364 bestm1 = pipe_config->dpll.m1;
7365 bestm2 = pipe_config->dpll.m2 >> 22;
7366 bestp1 = pipe_config->dpll.p1;
7367 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7368 vco = pipe_config->dpll.vco;
a945ce7e 7369 dpio_val = 0;
9cbe40c1 7370 loopfilter = 0;
9d556c99
CML		 7371
7372 /*
7373 * Enable Refclk and SSC
7374 */
a11b0703 7375 I915_WRITE(dpll_reg,
d288f65f 7376 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7377
a580516d 7378 mutex_lock(&dev_priv->sb_lock);
9d556c99 7379
9d556c99
CML		 7380 /* p1 and p2 divider */
7381 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7382 5 << DPIO_CHV_S1_DIV_SHIFT |
7383 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7384 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7385 1 << DPIO_CHV_K_DIV_SHIFT);
7386
7387 /* Feedback post-divider - m2 */
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7389
7390 /* Feedback refclk divider - n and m1 */
7391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7392 DPIO_CHV_M1_DIV_BY_2 |
7393 1 << DPIO_CHV_N_DIV_SHIFT);
7394
7395 /* M2 fraction division */
a945ce7e
VP		 7396 if (bestm2_frac)
7397 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7398
7399 /* M2 fraction division enable */
a945ce7e
VP		 7400 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7401 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7402 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7403 if (bestm2_frac)
7404 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7405 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7406
de3a0fde
VP		 7407 /* Program digital lock detect threshold */
7408 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7409 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7410 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7411 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7412 if (!bestm2_frac)
7413 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7414 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7415
9d556c99 7416 /* Loop filter */
9cbe40c1
VP		 7417 if (vco == 5400000) {
7418 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7419 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7420 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7421 tribuf_calcntr = 0x9;
7422 } else if (vco <= 6200000) {
7423 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7424 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7425 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7426 tribuf_calcntr = 0x9;
7427 } else if (vco <= 6480000) {
7428 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7429 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7430 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7431 tribuf_calcntr = 0x8;
7432 } else {
7433 /* Not supported. Apply the same limits as in the max case */
7434 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7435 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7436 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437 tribuf_calcntr = 0;
7438 }
9d556c99
CML		 7439 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7440
968040b2 7441 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7442 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7443 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7444 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7445
9d556c99
CML		 7446 /* AFC Recal */
7447 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7448 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7449 DPIO_AFC_RECAL);
7450
a580516d 7451 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7452}
7453
d288f65f
VS		 7454/**
7455 * vlv_force_pll_on - forcibly enable just the PLL
7456 * @dev_priv: i915 private structure
7457 * @pipe: pipe PLL to enable
7458 * @dpll: PLL configuration
7459 *
7460 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7461 * in cases where we need the PLL enabled even when @pipe is not going to
7462 * be enabled.
7463 */
7464void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7465 const struct dpll *dpll)
7466{
7467 struct intel_crtc *crtc =
7468 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7469 struct intel_crtc_state pipe_config = {
a93e255f 7470 .base.crtc = &crtc->base,
d288f65f
VS		 7471 .pixel_multiplier = 1,
7472 .dpll = *dpll,
7473 };
7474
7475 if (IS_CHERRYVIEW(dev)) {
251ac862 7476 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7477 chv_prepare_pll(crtc, &pipe_config);
7478 chv_enable_pll(crtc, &pipe_config);
7479 } else {
251ac862 7480 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7481 vlv_prepare_pll(crtc, &pipe_config);
7482 vlv_enable_pll(crtc, &pipe_config);
7483 }
7484}
7485
7486/**
7487 * vlv_force_pll_off - forcibly disable just the PLL
7488 * @dev_priv: i915 private structure
7489 * @pipe: pipe PLL to disable
7490 *
7491 * Disable the PLL for @pipe. To be used in cases where we need
7492 * the PLL enabled even when @pipe is not going to be enabled.
7493 */
7494void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7495{
7496 if (IS_CHERRYVIEW(dev))
7497 chv_disable_pll(to_i915(dev), pipe);
7498 else
7499 vlv_disable_pll(to_i915(dev), pipe);
7500}
7501
251ac862
DV		 7502static void i9xx_compute_dpll(struct intel_crtc *crtc,
7503 struct intel_crtc_state *crtc_state,
7504 intel_clock_t *reduced_clock,
7505 int num_connectors)
eb1cbe48 7506{
f47709a9 7507 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7508 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7509 u32 dpll;
7510 bool is_sdvo;
190f68c5 7511 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7512
190f68c5 7513 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7514
a93e255f
ACO		 7515 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7517
7518 dpll = DPLL_VGA_MODE_DIS;
7519
a93e255f 7520 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7521 dpll |= DPLLB_MODE_LVDS;
7522 else
7523 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7524
ef1b460d 7525 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7526 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7527 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7528 }
198a037f
DV		 7529
7530 if (is_sdvo)
4a33e48d 7531 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7532
190f68c5 7533 if (crtc_state->has_dp_encoder)
4a33e48d 7534 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7535
7536 /* compute bitmask from p1 value */
7537 if (IS_PINEVIEW(dev))
7538 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7539 else {
7540 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7541 if (IS_G4X(dev) && reduced_clock)
7542 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7543 }
7544 switch (clock->p2) {
7545 case 5:
7546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7547 break;
7548 case 7:
7549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7550 break;
7551 case 10:
7552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7553 break;
7554 case 14:
7555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7556 break;
7557 }
7558 if (INTEL_INFO(dev)->gen >= 4)
7559 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7560
190f68c5 7561 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7562 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7563 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7564 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7565 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7566 else
7567 dpll |= PLL_REF_INPUT_DREFCLK;
7568
7569 dpll |= DPLL_VCO_ENABLE;
190f68c5 7570 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7571
eb1cbe48 7572 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7573 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7574 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7575 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7576 }
7577}
7578
251ac862
DV		 7579static void i8xx_compute_dpll(struct intel_crtc *crtc,
7580 struct intel_crtc_state *crtc_state,
7581 intel_clock_t *reduced_clock,
7582 int num_connectors)
eb1cbe48 7583{
f47709a9 7584 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7585 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7586 u32 dpll;
190f68c5 7587 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7588
190f68c5 7589 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7590
eb1cbe48
DV		 7591 dpll = DPLL_VGA_MODE_DIS;
7592
a93e255f 7593 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7595 } else {
7596 if (clock->p1 == 2)
7597 dpll |= PLL_P1_DIVIDE_BY_TWO;
7598 else
7599 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7600 if (clock->p2 == 4)
7601 dpll |= PLL_P2_DIVIDE_BY_4;
7602 }
7603
a93e255f 7604 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7605 dpll |= DPLL_DVO_2X_MODE;
7606
a93e255f 7607 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7608 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7609 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7610 else
7611 dpll |= PLL_REF_INPUT_DREFCLK;
7612
7613 dpll |= DPLL_VCO_ENABLE;
190f68c5 7614 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7615}
7616
8a654f3b 7617static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7618{
7619 struct drm_device *dev = intel_crtc->base.dev;
7620 struct drm_i915_private *dev_priv = dev->dev_private;
7621 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7622 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7623 struct drm_display_mode *adjusted_mode =
6e3c9717 7624 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7625 uint32_t crtc_vtotal, crtc_vblank_end;
7626 int vsyncshift = 0;
4d8a62ea
DV		 7627
7628 /* We need to be careful not to changed the adjusted mode, for otherwise
7629 * the hw state checker will get angry at the mismatch. */
7630 crtc_vtotal = adjusted_mode->crtc_vtotal;
7631 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7632
609aeaca 7633 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7634 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7635 crtc_vtotal -= 1;
7636 crtc_vblank_end -= 1;
609aeaca 7637
409ee761 7638 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7639 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7640 else
7641 vsyncshift = adjusted_mode->crtc_hsync_start -
7642 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7643 if (vsyncshift < 0)
7644 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7645 }
7646
7647 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7648 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7649
fe2b8f9d 7650 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7651 (adjusted_mode->crtc_hdisplay - 1) |
7652 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7653 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7654 (adjusted_mode->crtc_hblank_start - 1) |
7655 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7656 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7657 (adjusted_mode->crtc_hsync_start - 1) |
7658 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7659
fe2b8f9d 7660 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7661 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7662 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7663 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7664 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7665 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7666 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7667 (adjusted_mode->crtc_vsync_start - 1) |
7668 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7669
b5e508d4
PZ		 7670 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7671 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7672 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7673 * bits. */
7674 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7675 (pipe == PIPE_B || pipe == PIPE_C))
7676 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7677
b0e77b9c
PZ		 7678 /* pipesrc controls the size that is scaled from, which should
7679 * always be the user's requested size.
7680 */
7681 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7682 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7683 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7684}
7685
1bd1bd80 7686static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7687 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7688{
7689 struct drm_device *dev = crtc->base.dev;
7690 struct drm_i915_private *dev_priv = dev->dev_private;
7691 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7692 uint32_t tmp;
7693
7694 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7695 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7696 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7697 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7698 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7699 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7700 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7701 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7702 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7703
7704 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7705 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7706 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7707 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7708 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7709 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7710 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7711 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7712 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7713
7714 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7715 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7716 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7717 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7718 }
7719
7720 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7721 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7722 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7723
2d112de7
ACO		 7724 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7725 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7726}
7727
f6a83288 7728void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7729 struct intel_crtc_state *pipe_config)
babea61d 7730{
2d112de7
ACO		 7731 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7732 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7733 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7734 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7735
2d112de7
ACO		 7736 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7737 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7738 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7739 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7740
2d112de7 7741 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7742
2d112de7
ACO		 7743 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7744 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7745}
7746
84b046f3
DV		 7747static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7748{
7749 struct drm_device *dev = intel_crtc->base.dev;
7750 struct drm_i915_private *dev_priv = dev->dev_private;
7751 uint32_t pipeconf;
7752
9f11a9e4 7753 pipeconf = 0;
84b046f3 7754
b6b5d049
VS		 7755 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7756 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7757 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7758
6e3c9717 7759 if (intel_crtc->config->double_wide)
cf532bb2 7760 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7761
ff9ce46e
DV		 7762 /* only g4x and later have fancy bpc/dither controls */
7763 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7764 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7765 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7766 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7767 PIPECONF_DITHER_TYPE_SP;
84b046f3 7768
6e3c9717 7769 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7770 case 18:
7771 pipeconf |= PIPECONF_6BPC;
7772 break;
7773 case 24:
7774 pipeconf |= PIPECONF_8BPC;
7775 break;
7776 case 30:
7777 pipeconf |= PIPECONF_10BPC;
7778 break;
7779 default:
7780 /* Case prevented by intel_choose_pipe_bpp_dither. */
7781 BUG();
84b046f3
DV		 7782 }
7783 }
7784
7785 if (HAS_PIPE_CXSR(dev)) {
7786 if (intel_crtc->lowfreq_avail) {
7787 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7788 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7789 } else {
7790 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7791 }
7792 }
7793
6e3c9717 7794 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7795 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7796 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7797 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7798 else
7799 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7800 } else
84b046f3
DV		 7801 pipeconf |= PIPECONF_PROGRESSIVE;
7802
6e3c9717 7803 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7804 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7805
84b046f3
DV		 7806 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7807 POSTING_READ(PIPECONF(intel_crtc->pipe));
7808}
7809
190f68c5
ACO		 7810static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7811 struct intel_crtc_state *crtc_state)
79e53945 7812{
c7653199 7813 struct drm_device *dev = crtc->base.dev;
79e53945 7814 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7815 int refclk, num_connectors = 0;
c329a4ec
DV		 7816 intel_clock_t clock;
7817 bool ok;
7818 bool is_dsi = false;
5eddb70b 7819 struct intel_encoder *encoder;
d4906093 7820 const intel_limit_t *limit;
55bb9992 7821 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7822 struct drm_connector *connector;
55bb9992
ACO		 7823 struct drm_connector_state *connector_state;
7824 int i;
79e53945 7825
dd3cd74a
ACO		 7826 memset(&crtc_state->dpll_hw_state, 0,
7827 sizeof(crtc_state->dpll_hw_state));
7828
da3ced29 7829 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7830 if (connector_state->crtc != &crtc->base)
7831 continue;
7832
7833 encoder = to_intel_encoder(connector_state->best_encoder);
7834
5eddb70b 7835 switch (encoder->type) {
e9fd1c02
JN		 7836 case INTEL_OUTPUT_DSI:
7837 is_dsi = true;
7838 break;
6847d71b
PZ		 7839 default:
7840 break;
79e53945 7841 }
43565a06 7842
c751ce4f 7843 num_connectors++;
79e53945
JB		 7844 }
7845
f2335330 7846 if (is_dsi)
5b18e57c 7847 return 0;
f2335330 7848
190f68c5 7849 if (!crtc_state->clock_set) {
a93e255f 7850 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7851
e9fd1c02
JN		 7852 /*
7853 * Returns a set of divisors for the desired target clock with
7854 * the given refclk, or FALSE. The returned values represent
7855 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7856 * 2) / p1 / p2.
7857 */
a93e255f
ACO		 7858 limit = intel_limit(crtc_state, refclk);
7859 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7860 crtc_state->port_clock,
e9fd1c02 7861 refclk, NULL, &clock);
f2335330 7862 if (!ok) {
e9fd1c02
JN		 7863 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7864 return -EINVAL;
7865 }
79e53945 7866
f2335330 7867 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7868 crtc_state->dpll.n = clock.n;
7869 crtc_state->dpll.m1 = clock.m1;
7870 crtc_state->dpll.m2 = clock.m2;
7871 crtc_state->dpll.p1 = clock.p1;
7872 crtc_state->dpll.p2 = clock.p2;
f47709a9 7873 }
7026d4ac 7874
e9fd1c02 7875 if (IS_GEN2(dev)) {
c329a4ec 7876 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7877 num_connectors);
9d556c99 7878 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7879 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7880 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7881 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7882 } else {
c329a4ec 7883 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7884 num_connectors);
e9fd1c02 7885 }
79e53945 7886
c8f7a0db 7887 return 0;
f564048e
EA		 7888}
7889
2fa2fe9a 7890static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7891 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7892{
7893 struct drm_device *dev = crtc->base.dev;
7894 struct drm_i915_private *dev_priv = dev->dev_private;
7895 uint32_t tmp;
7896
dc9e7dec
VS		 7897 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7898 return;
7899
2fa2fe9a 7900 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7901 if (!(tmp & PFIT_ENABLE))
7902 return;
2fa2fe9a 7903
06922821 7904 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7905 if (INTEL_INFO(dev)->gen < 4) {
7906 if (crtc->pipe != PIPE_B)
7907 return;
2fa2fe9a
DV		 7908 } else {
7909 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7910 return;
7911 }
7912
06922821 7913 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7914 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7915 if (INTEL_INFO(dev)->gen < 5)
7916 pipe_config->gmch_pfit.lvds_border_bits =
7917 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7918}
7919
acbec814 7920static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7921 struct intel_crtc_state *pipe_config)
acbec814
JB		 7922{
7923 struct drm_device *dev = crtc->base.dev;
7924 struct drm_i915_private *dev_priv = dev->dev_private;
7925 int pipe = pipe_config->cpu_transcoder;
7926 intel_clock_t clock;
7927 u32 mdiv;
662c6ecb 7928 int refclk = 100000;
acbec814 7929
f573de5a
SK		 7930 /* In case of MIPI DPLL will not even be used */
7931 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7932 return;
7933
a580516d 7934 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7935 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7936 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7937
7938 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7939 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7940 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7941 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7942 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7943
dccbea3b 7944 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7945}
7946
5724dbd1
DL		 7947static void
7948i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7949 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7950{
7951 struct drm_device *dev = crtc->base.dev;
7952 struct drm_i915_private *dev_priv = dev->dev_private;
7953 u32 val, base, offset;
7954 int pipe = crtc->pipe, plane = crtc->plane;
7955 int fourcc, pixel_format;
6761dd31 7956 unsigned int aligned_height;
b113d5ee 7957 struct drm_framebuffer *fb;
1b842c89 7958 struct intel_framebuffer *intel_fb;
1ad292b5 7959
42a7b088
DL		 7960 val = I915_READ(DSPCNTR(plane));
7961 if (!(val & DISPLAY_PLANE_ENABLE))
7962 return;
7963
d9806c9f 7964 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7965 if (!intel_fb) {
1ad292b5
JB		 7966 DRM_DEBUG_KMS("failed to alloc fb\n");
7967 return;
7968 }
7969
1b842c89
DL		 7970 fb = &intel_fb->base;
7971
18c5247e
DV		 7972 if (INTEL_INFO(dev)->gen >= 4) {
7973 if (val & DISPPLANE_TILED) {
49af449b 7974 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7975 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7976 }
7977 }
1ad292b5
JB		 7978
7979 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7980 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7981 fb->pixel_format = fourcc;
7982 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7983
7984 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7985 if (plane_config->tiling)
1ad292b5
JB		 7986 offset = I915_READ(DSPTILEOFF(plane));
7987 else
7988 offset = I915_READ(DSPLINOFF(plane));
7989 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7990 } else {
7991 base = I915_READ(DSPADDR(plane));
7992 }
7993 plane_config->base = base;
7994
7995 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7996 fb->width = ((val >> 16) & 0xfff) + 1;
7997 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7998
7999 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8000 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8001
b113d5ee 8002 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8003 fb->pixel_format,
8004 fb->modifier[0]);
1ad292b5 8005
f37b5c2b 8006 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8007
2844a921
DL		 8008 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8009 pipe_name(pipe), plane, fb->width, fb->height,
8010 fb->bits_per_pixel, base, fb->pitches[0],
8011 plane_config->size);
1ad292b5 8012
2d14030b 8013 plane_config->fb = intel_fb;
1ad292b5
JB		 8014}
8015
70b23a98 8016static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8017 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8018{
8019 struct drm_device *dev = crtc->base.dev;
8020 struct drm_i915_private *dev_priv = dev->dev_private;
8021 int pipe = pipe_config->cpu_transcoder;
8022 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8023 intel_clock_t clock;
8024 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8025 int refclk = 100000;
8026
a580516d 8027 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8028 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8029 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8030 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8031 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8032 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8033
8034 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8035 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8036 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8037 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8038 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8039
dccbea3b 8040 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8041}
8042
0e8ffe1b 8043static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8044 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8045{
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 uint32_t tmp;
8049
f458ebbc
DV		 8050 if (!intel_display_power_is_enabled(dev_priv,
8051 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8052 return false;
8053
e143a21c 8054 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8055 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8056
0e8ffe1b
DV		 8057 tmp = I915_READ(PIPECONF(crtc->pipe));
8058 if (!(tmp & PIPECONF_ENABLE))
8059 return false;
8060
42571aef
VS		 8061 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8062 switch (tmp & PIPECONF_BPC_MASK) {
8063 case PIPECONF_6BPC:
8064 pipe_config->pipe_bpp = 18;
8065 break;
8066 case PIPECONF_8BPC:
8067 pipe_config->pipe_bpp = 24;
8068 break;
8069 case PIPECONF_10BPC:
8070 pipe_config->pipe_bpp = 30;
8071 break;
8072 default:
8073 break;
8074 }
8075 }
8076
b5a9fa09
DV		 8077 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8078 pipe_config->limited_color_range = true;
8079
282740f7
VS		 8080 if (INTEL_INFO(dev)->gen < 4)
8081 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8082
1bd1bd80
DV		 8083 intel_get_pipe_timings(crtc, pipe_config);
8084
2fa2fe9a
DV		 8085 i9xx_get_pfit_config(crtc, pipe_config);
8086
6c49f241
DV		 8087 if (INTEL_INFO(dev)->gen >= 4) {
8088 tmp = I915_READ(DPLL_MD(crtc->pipe));
8089 pipe_config->pixel_multiplier =
8090 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8091 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8092 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8093 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8094 tmp = I915_READ(DPLL(crtc->pipe));
8095 pipe_config->pixel_multiplier =
8096 ((tmp & SDVO_MULTIPLIER_MASK)
8097 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8098 } else {
8099 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8100 * port and will be fixed up in the encoder->get_config
8101 * function. */
8102 pipe_config->pixel_multiplier = 1;
8103 }
8bcc2795
DV		 8104 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8105 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8106 /*
8107 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8108 * on 830. Filter it out here so that we don't
8109 * report errors due to that.
8110 */
8111 if (IS_I830(dev))
8112 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8113
8bcc2795
DV		 8114 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8115 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8116 } else {
8117 /* Mask out read-only status bits. */
8118 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8119 DPLL_PORTC_READY_MASK |
8120 DPLL_PORTB_READY_MASK);
8bcc2795 8121 }
6c49f241 8122
70b23a98
VS		 8123 if (IS_CHERRYVIEW(dev))
8124 chv_crtc_clock_get(crtc, pipe_config);
8125 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8126 vlv_crtc_clock_get(crtc, pipe_config);
8127 else
8128 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8129
0e8ffe1b
DV		 8130 return true;
8131}
8132
dde86e2d 8133static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8134{
8135 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8136 struct intel_encoder *encoder;
74cfd7ac 8137 u32 val, final;
13d83a67 8138 bool has_lvds = false;
199e5d79 8139 bool has_cpu_edp = false;
199e5d79 8140 bool has_panel = false;
99eb6a01
KP		 8141 bool has_ck505 = false;
8142 bool can_ssc = false;
13d83a67
JB		 8143
8144 /* We need to take the global config into account */
b2784e15 8145 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8146 switch (encoder->type) {
8147 case INTEL_OUTPUT_LVDS:
8148 has_panel = true;
8149 has_lvds = true;
8150 break;
8151 case INTEL_OUTPUT_EDP:
8152 has_panel = true;
2de6905f 8153 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8154 has_cpu_edp = true;
8155 break;
6847d71b
PZ		 8156 default:
8157 break;
13d83a67
JB		 8158 }
8159 }
8160
99eb6a01 8161 if (HAS_PCH_IBX(dev)) {
41aa3448 8162 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8163 can_ssc = has_ck505;
8164 } else {
8165 has_ck505 = false;
8166 can_ssc = true;
8167 }
8168
2de6905f
ID		 8169 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8170 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8171
8172 /* Ironlake: try to setup display ref clock before DPLL
8173 * enabling. This is only under driver's control after
8174 * PCH B stepping, previous chipset stepping should be
8175 * ignoring this setting.
8176 */
74cfd7ac
CW		 8177 val = I915_READ(PCH_DREF_CONTROL);
8178
8179 /* As we must carefully and slowly disable/enable each source in turn,
8180 * compute the final state we want first and check if we need to
8181 * make any changes at all.
8182 */
8183 final = val;
8184 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8185 if (has_ck505)
8186 final |= DREF_NONSPREAD_CK505_ENABLE;
8187 else
8188 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8189
8190 final &= ~DREF_SSC_SOURCE_MASK;
8191 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8192 final &= ~DREF_SSC1_ENABLE;
8193
8194 if (has_panel) {
8195 final |= DREF_SSC_SOURCE_ENABLE;
8196
8197 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8198 final |= DREF_SSC1_ENABLE;
8199
8200 if (has_cpu_edp) {
8201 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8202 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8203 else
8204 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8205 } else
8206 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8207 } else {
8208 final |= DREF_SSC_SOURCE_DISABLE;
8209 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8210 }
8211
8212 if (final == val)
8213 return;
8214
13d83a67 8215 /* Always enable nonspread source */
74cfd7ac 8216 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8217
99eb6a01 8218 if (has_ck505)
74cfd7ac 8219 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8220 else
74cfd7ac 8221 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8222
199e5d79 8223 if (has_panel) {
74cfd7ac
CW		 8224 val &= ~DREF_SSC_SOURCE_MASK;
8225 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8226
199e5d79 8227 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8228 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8229 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8230 val |= DREF_SSC1_ENABLE;
e77166b5 8231 } else
74cfd7ac 8232 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8233
8234 /* Get SSC going before enabling the outputs */
74cfd7ac 8235 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8236 POSTING_READ(PCH_DREF_CONTROL);
8237 udelay(200);
8238
74cfd7ac 8239 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8240
8241 /* Enable CPU source on CPU attached eDP */
199e5d79 8242 if (has_cpu_edp) {
99eb6a01 8243 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8244 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8245 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8246 } else
74cfd7ac 8247 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8248 } else
74cfd7ac 8249 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8250
74cfd7ac 8251 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8252 POSTING_READ(PCH_DREF_CONTROL);
8253 udelay(200);
8254 } else {
8255 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8256
74cfd7ac 8257 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8258
8259 /* Turn off CPU output */
74cfd7ac 8260 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8261
74cfd7ac 8262 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8263 POSTING_READ(PCH_DREF_CONTROL);
8264 udelay(200);
8265
8266 /* Turn off the SSC source */
74cfd7ac
CW		 8267 val &= ~DREF_SSC_SOURCE_MASK;
8268 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8269
8270 /* Turn off SSC1 */
74cfd7ac 8271 val &= ~DREF_SSC1_ENABLE;
199e5d79 8272
74cfd7ac 8273 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8274 POSTING_READ(PCH_DREF_CONTROL);
8275 udelay(200);
8276 }
74cfd7ac
CW		 8277
8278 BUG_ON(val != final);
13d83a67
JB		 8279}
8280
f31f2d55 8281static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8282{
f31f2d55 8283 uint32_t tmp;
dde86e2d 8284
0ff066a9
PZ		 8285 tmp = I915_READ(SOUTH_CHICKEN2);
8286 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8287 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8288
0ff066a9
PZ		 8289 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8290 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8291 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8292
0ff066a9
PZ		 8293 tmp = I915_READ(SOUTH_CHICKEN2);
8294 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8295 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8296
0ff066a9
PZ		 8297 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8298 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8299 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8300}
8301
8302/* WaMPhyProgramming:hsw */
8303static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8304{
8305 uint32_t tmp;
dde86e2d
PZ		 8306
8307 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8308 tmp &= ~(0xFF << 24);
8309 tmp |= (0x12 << 24);
8310 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8311
dde86e2d
PZ		 8312 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8313 tmp |= (1 << 11);
8314 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8315
8316 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8317 tmp |= (1 << 11);
8318 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8319
dde86e2d
PZ		 8320 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8321 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8322 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8323
8324 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8325 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8326 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8327
0ff066a9
PZ		 8328 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8329 tmp &= ~(7 << 13);
8330 tmp |= (5 << 13);
8331 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8332
0ff066a9
PZ		 8333 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8334 tmp &= ~(7 << 13);
8335 tmp |= (5 << 13);
8336 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8337
8338 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8339 tmp &= ~0xFF;
8340 tmp |= 0x1C;
8341 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8342
8343 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8344 tmp &= ~0xFF;
8345 tmp |= 0x1C;
8346 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8347
8348 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8349 tmp &= ~(0xFF << 16);
8350 tmp |= (0x1C << 16);
8351 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8352
8353 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8354 tmp &= ~(0xFF << 16);
8355 tmp |= (0x1C << 16);
8356 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8357
0ff066a9
PZ		 8358 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8359 tmp |= (1 << 27);
8360 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8361
0ff066a9
PZ		 8362 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8363 tmp |= (1 << 27);
8364 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8365
0ff066a9
PZ		 8366 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8367 tmp &= ~(0xF << 28);
8368 tmp |= (4 << 28);
8369 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8370
0ff066a9
PZ		 8371 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8372 tmp &= ~(0xF << 28);
8373 tmp |= (4 << 28);
8374 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8375}
8376
2fa86a1f
PZ		 8377/* Implements 3 different sequences from BSpec chapter "Display iCLK
8378 * Programming" based on the parameters passed:
8379 * - Sequence to enable CLKOUT_DP
8380 * - Sequence to enable CLKOUT_DP without spread
8381 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8382 */
8383static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8384 bool with_fdi)
f31f2d55
PZ		 8385{
8386 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8387 uint32_t reg, tmp;
8388
8389 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8390 with_spread = true;
8391 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8392 with_fdi, "LP PCH doesn't have FDI\n"))
8393 with_fdi = false;
f31f2d55 8394
a580516d 8395 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8396
8397 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8398 tmp &= ~SBI_SSCCTL_DISABLE;
8399 tmp |= SBI_SSCCTL_PATHALT;
8400 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8401
8402 udelay(24);
8403
2fa86a1f
PZ		 8404 if (with_spread) {
8405 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8406 tmp &= ~SBI_SSCCTL_PATHALT;
8407 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8408
2fa86a1f
PZ		 8409 if (with_fdi) {
8410 lpt_reset_fdi_mphy(dev_priv);
8411 lpt_program_fdi_mphy(dev_priv);
8412 }
8413 }
dde86e2d 8414
2fa86a1f
PZ		 8415 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8416 SBI_GEN0 : SBI_DBUFF0;
8417 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8418 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8419 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8420
a580516d 8421 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8422}
8423
47701c3b
PZ		 8424/* Sequence to disable CLKOUT_DP */
8425static void lpt_disable_clkout_dp(struct drm_device *dev)
8426{
8427 struct drm_i915_private *dev_priv = dev->dev_private;
8428 uint32_t reg, tmp;
8429
a580516d 8430 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8431
8432 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8433 SBI_GEN0 : SBI_DBUFF0;
8434 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8435 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8436 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8437
8438 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8439 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8440 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8441 tmp |= SBI_SSCCTL_PATHALT;
8442 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8443 udelay(32);
8444 }
8445 tmp |= SBI_SSCCTL_DISABLE;
8446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8447 }
8448
a580516d 8449 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8450}
8451
bf8fa3d3
PZ		 8452static void lpt_init_pch_refclk(struct drm_device *dev)
8453{
bf8fa3d3
PZ		 8454 struct intel_encoder *encoder;
8455 bool has_vga = false;
8456
b2784e15 8457 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8458 switch (encoder->type) {
8459 case INTEL_OUTPUT_ANALOG:
8460 has_vga = true;
8461 break;
6847d71b
PZ		 8462 default:
8463 break;
bf8fa3d3
PZ		 8464 }
8465 }
8466
47701c3b
PZ		 8467 if (has_vga)
8468 lpt_enable_clkout_dp(dev, true, true);
8469 else
8470 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8471}
8472
dde86e2d
PZ		 8473/*
8474 * Initialize reference clocks when the driver loads
8475 */
8476void intel_init_pch_refclk(struct drm_device *dev)
8477{
8478 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8479 ironlake_init_pch_refclk(dev);
8480 else if (HAS_PCH_LPT(dev))
8481 lpt_init_pch_refclk(dev);
8482}
8483
55bb9992 8484static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8485{
55bb9992 8486 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8487 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8488 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8489 struct drm_connector *connector;
55bb9992 8490 struct drm_connector_state *connector_state;
d9d444cb 8491 struct intel_encoder *encoder;
55bb9992 8492 int num_connectors = 0, i;
d9d444cb
JB		 8493 bool is_lvds = false;
8494
da3ced29 8495 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8496 if (connector_state->crtc != crtc_state->base.crtc)
8497 continue;
8498
8499 encoder = to_intel_encoder(connector_state->best_encoder);
8500
d9d444cb
JB		 8501 switch (encoder->type) {
8502 case INTEL_OUTPUT_LVDS:
8503 is_lvds = true;
8504 break;
6847d71b
PZ		 8505 default:
8506 break;
d9d444cb
JB		 8507 }
8508 num_connectors++;
8509 }
8510
8511 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8512 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8513 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8514 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8515 }
8516
8517 return 120000;
8518}
8519
6ff93609 8520static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8521{
c8203565 8522 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8524 int pipe = intel_crtc->pipe;
c8203565
PZ		 8525 uint32_t val;
8526
78114071 8527 val = 0;
c8203565 8528
6e3c9717 8529 switch (intel_crtc->config->pipe_bpp) {
c8203565 8530 case 18:
dfd07d72 8531 val |= PIPECONF_6BPC;
c8203565
PZ		 8532 break;
8533 case 24:
dfd07d72 8534 val |= PIPECONF_8BPC;
c8203565
PZ		 8535 break;
8536 case 30:
dfd07d72 8537 val |= PIPECONF_10BPC;
c8203565
PZ		 8538 break;
8539 case 36:
dfd07d72 8540 val |= PIPECONF_12BPC;
c8203565
PZ		 8541 break;
8542 default:
cc769b62
PZ		 8543 /* Case prevented by intel_choose_pipe_bpp_dither. */
8544 BUG();
c8203565
PZ		 8545 }
8546
6e3c9717 8547 if (intel_crtc->config->dither)
c8203565
PZ		 8548 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8549
6e3c9717 8550 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8551 val |= PIPECONF_INTERLACED_ILK;
8552 else
8553 val |= PIPECONF_PROGRESSIVE;
8554
6e3c9717 8555 if (intel_crtc->config->limited_color_range)
3685a8f3 8556 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8557
c8203565
PZ		 8558 I915_WRITE(PIPECONF(pipe), val);
8559 POSTING_READ(PIPECONF(pipe));
8560}
8561
86d3efce
VS		 8562/*
8563 * Set up the pipe CSC unit.
8564 *
8565 * Currently only full range RGB to limited range RGB conversion
8566 * is supported, but eventually this should handle various
8567 * RGB<->YCbCr scenarios as well.
8568 */
50f3b016 8569static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8570{
8571 struct drm_device *dev = crtc->dev;
8572 struct drm_i915_private *dev_priv = dev->dev_private;
8573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8574 int pipe = intel_crtc->pipe;
8575 uint16_t coeff = 0x7800; /* 1.0 */
8576
8577 /*
8578 * TODO: Check what kind of values actually come out of the pipe
8579 * with these coeff/postoff values and adjust to get the best
8580 * accuracy. Perhaps we even need to take the bpc value into
8581 * consideration.
8582 */
8583
6e3c9717 8584 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8585 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8586
8587 /*
8588 * GY/GU and RY/RU should be the other way around according
8589 * to BSpec, but reality doesn't agree. Just set them up in
8590 * a way that results in the correct picture.
8591 */
8592 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8593 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8594
8595 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8596 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8597
8598 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8599 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8600
8601 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8602 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8603 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8604
8605 if (INTEL_INFO(dev)->gen > 6) {
8606 uint16_t postoff = 0;
8607
6e3c9717 8608 if (intel_crtc->config->limited_color_range)
32cf0cb0 8609 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8610
8611 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8612 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8613 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8614
8615 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8616 } else {
8617 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8618
6e3c9717 8619 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8620 mode |= CSC_BLACK_SCREEN_OFFSET;
8621
8622 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8623 }
8624}
8625
6ff93609 8626static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8627{
756f85cf
PZ		 8628 struct drm_device *dev = crtc->dev;
8629 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8631 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8632 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8633 uint32_t val;
8634
3eff4faa 8635 val = 0;
ee2b0b38 8636
6e3c9717 8637 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8638 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8639
6e3c9717 8640 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8641 val |= PIPECONF_INTERLACED_ILK;
8642 else
8643 val |= PIPECONF_PROGRESSIVE;
8644
702e7a56
PZ		 8645 I915_WRITE(PIPECONF(cpu_transcoder), val);
8646 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8647
8648 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8649 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8650
3cdf122c 8651 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8652 val = 0;
8653
6e3c9717 8654 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8655 case 18:
8656 val |= PIPEMISC_DITHER_6_BPC;
8657 break;
8658 case 24:
8659 val |= PIPEMISC_DITHER_8_BPC;
8660 break;
8661 case 30:
8662 val |= PIPEMISC_DITHER_10_BPC;
8663 break;
8664 case 36:
8665 val |= PIPEMISC_DITHER_12_BPC;
8666 break;
8667 default:
8668 /* Case prevented by pipe_config_set_bpp. */
8669 BUG();
8670 }
8671
6e3c9717 8672 if (intel_crtc->config->dither)
756f85cf
PZ		 8673 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8674
8675 I915_WRITE(PIPEMISC(pipe), val);
8676 }
ee2b0b38
PZ		 8677}
8678
6591c6e4 8679static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8680 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8681 intel_clock_t *clock,
8682 bool *has_reduced_clock,
8683 intel_clock_t *reduced_clock)
8684{
8685 struct drm_device *dev = crtc->dev;
8686 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8687 int refclk;
d4906093 8688 const intel_limit_t *limit;
c329a4ec 8689 bool ret;
79e53945 8690
55bb9992 8691 refclk = ironlake_get_refclk(crtc_state);
79e53945 8692
d4906093
ML		 8693 /*
8694 * Returns a set of divisors for the desired target clock with the given
8695 * refclk, or FALSE. The returned values represent the clock equation:
8696 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8697 */
a93e255f
ACO		 8698 limit = intel_limit(crtc_state, refclk);
8699 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8700 crtc_state->port_clock,
ee9300bb 8701 refclk, NULL, clock);
6591c6e4
PZ		 8702 if (!ret)
8703 return false;
cda4b7d3 8704
6591c6e4
PZ		 8705 return true;
8706}
8707
d4b1931c
PZ		 8708int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8709{
8710 /*
8711 * Account for spread spectrum to avoid
8712 * oversubscribing the link. Max center spread
8713 * is 2.5%; use 5% for safety's sake.
8714 */
8715 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8716 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8717}
8718
7429e9d4 8719static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8720{
7429e9d4 8721 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8722}
8723
de13a2e3 8724static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8725 struct intel_crtc_state *crtc_state,
7429e9d4 8726 u32 *fp,
9a7c7890 8727 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8728{
de13a2e3 8729 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8730 struct drm_device *dev = crtc->dev;
8731 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8732 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8733 struct drm_connector *connector;
55bb9992
ACO		 8734 struct drm_connector_state *connector_state;
8735 struct intel_encoder *encoder;
de13a2e3 8736 uint32_t dpll;
55bb9992 8737 int factor, num_connectors = 0, i;
09ede541 8738 bool is_lvds = false, is_sdvo = false;
79e53945 8739
da3ced29 8740 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8741 if (connector_state->crtc != crtc_state->base.crtc)
8742 continue;
8743
8744 encoder = to_intel_encoder(connector_state->best_encoder);
8745
8746 switch (encoder->type) {
79e53945
JB		 8747 case INTEL_OUTPUT_LVDS:
8748 is_lvds = true;
8749 break;
8750 case INTEL_OUTPUT_SDVO:
7d57382e 8751 case INTEL_OUTPUT_HDMI:
79e53945 8752 is_sdvo = true;
79e53945 8753 break;
6847d71b
PZ		 8754 default:
8755 break;
79e53945 8756 }
43565a06 8757
c751ce4f 8758 num_connectors++;
79e53945 8759 }
79e53945 8760
c1858123 8761 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8762 factor = 21;
8763 if (is_lvds) {
8764 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8765 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8766 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8767 factor = 25;
190f68c5 8768 } else if (crtc_state->sdvo_tv_clock)
8febb297 8769 factor = 20;
c1858123 8770
190f68c5 8771 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8772 *fp |= FP_CB_TUNE;
2c07245f 8773
9a7c7890
DV		 8774 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8775 *fp2 |= FP_CB_TUNE;
8776
5eddb70b 8777 dpll = 0;
2c07245f 8778
a07d6787
EA		 8779 if (is_lvds)
8780 dpll |= DPLLB_MODE_LVDS;
8781 else
8782 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8783
190f68c5 8784 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8785 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8786
8787 if (is_sdvo)
4a33e48d 8788 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8789 if (crtc_state->has_dp_encoder)
4a33e48d 8790 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8791
a07d6787 8792 /* compute bitmask from p1 value */
190f68c5 8793 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8794 /* also FPA1 */
190f68c5 8795 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8796
190f68c5 8797 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8798 case 5:
8799 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8800 break;
8801 case 7:
8802 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8803 break;
8804 case 10:
8805 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8806 break;
8807 case 14:
8808 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8809 break;
79e53945
JB		 8810 }
8811
b4c09f3b 8812 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8813 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8814 else
8815 dpll |= PLL_REF_INPUT_DREFCLK;
8816
959e16d6 8817 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8818}
8819
190f68c5
ACO		 8820static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8821 struct intel_crtc_state *crtc_state)
de13a2e3 8822{
c7653199 8823 struct drm_device *dev = crtc->base.dev;
de13a2e3 8824 intel_clock_t clock, reduced_clock;
cbbab5bd 8825 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8826 bool ok, has_reduced_clock = false;
8b47047b 8827 bool is_lvds = false;
e2b78267 8828 struct intel_shared_dpll *pll;
de13a2e3 8829
dd3cd74a
ACO		 8830 memset(&crtc_state->dpll_hw_state, 0,
8831 sizeof(crtc_state->dpll_hw_state));
8832
409ee761 8833 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8834
5dc5298b
PZ		 8835 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8836 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8837
190f68c5 8838 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8839 &has_reduced_clock, &reduced_clock);
190f68c5 8840 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8841 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8842 return -EINVAL;
79e53945 8843 }
f47709a9 8844 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8845 if (!crtc_state->clock_set) {
8846 crtc_state->dpll.n = clock.n;
8847 crtc_state->dpll.m1 = clock.m1;
8848 crtc_state->dpll.m2 = clock.m2;
8849 crtc_state->dpll.p1 = clock.p1;
8850 crtc_state->dpll.p2 = clock.p2;
f47709a9 8851 }
79e53945 8852
5dc5298b 8853 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8854 if (crtc_state->has_pch_encoder) {
8855 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8856 if (has_reduced_clock)
7429e9d4 8857 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8858
190f68c5 8859 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8860 &fp, &reduced_clock,
8861 has_reduced_clock ? &fp2 : NULL);
8862
190f68c5
ACO		 8863 crtc_state->dpll_hw_state.dpll = dpll;
8864 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8865 if (has_reduced_clock)
190f68c5 8866 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8867 else
190f68c5 8868 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8869
190f68c5 8870 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8871 if (pll == NULL) {
84f44ce7 8872 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8873 pipe_name(crtc->pipe));
4b645f14
JB		 8874 return -EINVAL;
8875 }
3fb37703 8876 }
79e53945 8877
ab585dea 8878 if (is_lvds && has_reduced_clock)
c7653199 8879 crtc->lowfreq_avail = true;
bcd644e0 8880 else
c7653199 8881 crtc->lowfreq_avail = false;
e2b78267 8882
c8f7a0db 8883 return 0;
79e53945
JB		 8884}
8885
eb14cb74
VS		 8886static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8887 struct intel_link_m_n *m_n)
8888{
8889 struct drm_device *dev = crtc->base.dev;
8890 struct drm_i915_private *dev_priv = dev->dev_private;
8891 enum pipe pipe = crtc->pipe;
8892
8893 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8894 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8895 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8896 & ~TU_SIZE_MASK;
8897 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8898 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8899 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8900}
8901
8902static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8903 enum transcoder transcoder,
b95af8be
VK		 8904 struct intel_link_m_n *m_n,
8905 struct intel_link_m_n *m2_n2)
72419203
DV		 8906{
8907 struct drm_device *dev = crtc->base.dev;
8908 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8909 enum pipe pipe = crtc->pipe;
72419203 8910
eb14cb74
VS		 8911 if (INTEL_INFO(dev)->gen >= 5) {
8912 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8913 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8914 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8915 & ~TU_SIZE_MASK;
8916 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8917 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8918 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8919 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8920 * gen < 8) and if DRRS is supported (to make sure the
8921 * registers are not unnecessarily read).
8922 */
8923 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8924 crtc->config->has_drrs) {
b95af8be
VK		 8925 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8926 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8927 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8928 & ~TU_SIZE_MASK;
8929 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8930 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8931 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8932 }
eb14cb74
VS		 8933 } else {
8934 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8935 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8936 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8937 & ~TU_SIZE_MASK;
8938 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8939 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8940 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8941 }
8942}
8943
8944void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8945 struct intel_crtc_state *pipe_config)
eb14cb74 8946{
681a8504 8947 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8948 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8949 else
8950 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8951 &pipe_config->dp_m_n,
8952 &pipe_config->dp_m2_n2);
eb14cb74 8953}
72419203 8954
eb14cb74 8955static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8956 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8957{
8958 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8959 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8960}
8961
bd2e244f 8962static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8963 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8964{
8965 struct drm_device *dev = crtc->base.dev;
8966 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8967 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8968 uint32_t ps_ctrl = 0;
8969 int id = -1;
8970 int i;
bd2e244f 8971
a1b2278e
CK		 8972 /* find scaler attached to this pipe */
8973 for (i = 0; i < crtc->num_scalers; i++) {
8974 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8975 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8976 id = i;
8977 pipe_config->pch_pfit.enabled = true;
8978 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8979 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8980 break;
8981 }
8982 }
bd2e244f 8983
a1b2278e
CK		 8984 scaler_state->scaler_id = id;
8985 if (id >= 0) {
8986 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8987 } else {
8988 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8989 }
8990}
8991
5724dbd1
DL		 8992static void
8993skylake_get_initial_plane_config(struct intel_crtc *crtc,
8994 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8995{
8996 struct drm_device *dev = crtc->base.dev;
8997 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8998 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8999 int pipe = crtc->pipe;
9000 int fourcc, pixel_format;
6761dd31 9001 unsigned int aligned_height;
bc8d7dff 9002 struct drm_framebuffer *fb;
1b842c89 9003 struct intel_framebuffer *intel_fb;
bc8d7dff 9004
d9806c9f 9005 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9006 if (!intel_fb) {
bc8d7dff
DL		 9007 DRM_DEBUG_KMS("failed to alloc fb\n");
9008 return;
9009 }
9010
1b842c89
DL		 9011 fb = &intel_fb->base;
9012
bc8d7dff 9013 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9014 if (!(val & PLANE_CTL_ENABLE))
9015 goto error;
9016
bc8d7dff
DL		 9017 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9018 fourcc = skl_format_to_fourcc(pixel_format,
9019 val & PLANE_CTL_ORDER_RGBX,
9020 val & PLANE_CTL_ALPHA_MASK);
9021 fb->pixel_format = fourcc;
9022 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9023
40f46283
DL		 9024 tiling = val & PLANE_CTL_TILED_MASK;
9025 switch (tiling) {
9026 case PLANE_CTL_TILED_LINEAR:
9027 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9028 break;
9029 case PLANE_CTL_TILED_X:
9030 plane_config->tiling = I915_TILING_X;
9031 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9032 break;
9033 case PLANE_CTL_TILED_Y:
9034 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9035 break;
9036 case PLANE_CTL_TILED_YF:
9037 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9038 break;
9039 default:
9040 MISSING_CASE(tiling);
9041 goto error;
9042 }
9043
bc8d7dff
DL		 9044 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9045 plane_config->base = base;
9046
9047 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9048
9049 val = I915_READ(PLANE_SIZE(pipe, 0));
9050 fb->height = ((val >> 16) & 0xfff) + 1;
9051 fb->width = ((val >> 0) & 0x1fff) + 1;
9052
9053 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9054 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9055 fb->pixel_format);
bc8d7dff
DL		 9056 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9057
9058 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9059 fb->pixel_format,
9060 fb->modifier[0]);
bc8d7dff 9061
f37b5c2b 9062 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9063
9064 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9065 pipe_name(pipe), fb->width, fb->height,
9066 fb->bits_per_pixel, base, fb->pitches[0],
9067 plane_config->size);
9068
2d14030b 9069 plane_config->fb = intel_fb;
bc8d7dff
DL		 9070 return;
9071
9072error:
9073 kfree(fb);
9074}
9075
2fa2fe9a 9076static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9077 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9078{
9079 struct drm_device *dev = crtc->base.dev;
9080 struct drm_i915_private *dev_priv = dev->dev_private;
9081 uint32_t tmp;
9082
9083 tmp = I915_READ(PF_CTL(crtc->pipe));
9084
9085 if (tmp & PF_ENABLE) {
fd4daa9c 9086 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9087 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9088 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9089
9090 /* We currently do not free assignements of panel fitters on
9091 * ivb/hsw (since we don't use the higher upscaling modes which
9092 * differentiates them) so just WARN about this case for now. */
9093 if (IS_GEN7(dev)) {
9094 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9095 PF_PIPE_SEL_IVB(crtc->pipe));
9096 }
2fa2fe9a 9097 }
79e53945
JB		 9098}
9099
5724dbd1
DL		 9100static void
9101ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9102 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9103{
9104 struct drm_device *dev = crtc->base.dev;
9105 struct drm_i915_private *dev_priv = dev->dev_private;
9106 u32 val, base, offset;
aeee5a49 9107 int pipe = crtc->pipe;
4c6baa59 9108 int fourcc, pixel_format;
6761dd31 9109 unsigned int aligned_height;
b113d5ee 9110 struct drm_framebuffer *fb;
1b842c89 9111 struct intel_framebuffer *intel_fb;
4c6baa59 9112
42a7b088
DL		 9113 val = I915_READ(DSPCNTR(pipe));
9114 if (!(val & DISPLAY_PLANE_ENABLE))
9115 return;
9116
d9806c9f 9117 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9118 if (!intel_fb) {
4c6baa59
JB		 9119 DRM_DEBUG_KMS("failed to alloc fb\n");
9120 return;
9121 }
9122
1b842c89
DL		 9123 fb = &intel_fb->base;
9124
18c5247e
DV		 9125 if (INTEL_INFO(dev)->gen >= 4) {
9126 if (val & DISPPLANE_TILED) {
49af449b 9127 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9128 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9129 }
9130 }
4c6baa59
JB		 9131
9132 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9133 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9134 fb->pixel_format = fourcc;
9135 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9136
aeee5a49 9137 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9138 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9139 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9140 } else {
49af449b 9141 if (plane_config->tiling)
aeee5a49 9142 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9143 else
aeee5a49 9144 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9145 }
9146 plane_config->base = base;
9147
9148 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9149 fb->width = ((val >> 16) & 0xfff) + 1;
9150 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9151
9152 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9153 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9154
b113d5ee 9155 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9156 fb->pixel_format,
9157 fb->modifier[0]);
4c6baa59 9158
f37b5c2b 9159 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9160
2844a921
DL		 9161 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9162 pipe_name(pipe), fb->width, fb->height,
9163 fb->bits_per_pixel, base, fb->pitches[0],
9164 plane_config->size);
b113d5ee 9165
2d14030b 9166 plane_config->fb = intel_fb;
4c6baa59
JB		 9167}
9168
0e8ffe1b 9169static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9170 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9171{
9172 struct drm_device *dev = crtc->base.dev;
9173 struct drm_i915_private *dev_priv = dev->dev_private;
9174 uint32_t tmp;
9175
f458ebbc
DV		 9176 if (!intel_display_power_is_enabled(dev_priv,
9177 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9178 return false;
9179
e143a21c 9180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9181 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9182
0e8ffe1b
DV		 9183 tmp = I915_READ(PIPECONF(crtc->pipe));
9184 if (!(tmp & PIPECONF_ENABLE))
9185 return false;
9186
42571aef
VS		 9187 switch (tmp & PIPECONF_BPC_MASK) {
9188 case PIPECONF_6BPC:
9189 pipe_config->pipe_bpp = 18;
9190 break;
9191 case PIPECONF_8BPC:
9192 pipe_config->pipe_bpp = 24;
9193 break;
9194 case PIPECONF_10BPC:
9195 pipe_config->pipe_bpp = 30;
9196 break;
9197 case PIPECONF_12BPC:
9198 pipe_config->pipe_bpp = 36;
9199 break;
9200 default:
9201 break;
9202 }
9203
b5a9fa09
DV		 9204 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9205 pipe_config->limited_color_range = true;
9206
ab9412ba 9207 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9208 struct intel_shared_dpll *pll;
9209
88adfff1
DV		 9210 pipe_config->has_pch_encoder = true;
9211
627eb5a3
DV		 9212 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9213 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9214 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9215
9216 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9217
c0d43d62 9218 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9219 pipe_config->shared_dpll =
9220 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9221 } else {
9222 tmp = I915_READ(PCH_DPLL_SEL);
9223 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9224 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9225 else
9226 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9227 }
66e985c0
DV		 9228
9229 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9230
9231 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9232 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9233
9234 tmp = pipe_config->dpll_hw_state.dpll;
9235 pipe_config->pixel_multiplier =
9236 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9237 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9238
9239 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9240 } else {
9241 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9242 }
9243
1bd1bd80
DV		 9244 intel_get_pipe_timings(crtc, pipe_config);
9245
2fa2fe9a
DV		 9246 ironlake_get_pfit_config(crtc, pipe_config);
9247
0e8ffe1b
DV		 9248 return true;
9249}
9250
be256dc7
PZ		 9251static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9252{
9253 struct drm_device *dev = dev_priv->dev;
be256dc7 9254 struct intel_crtc *crtc;
be256dc7 9255
d3fcc808 9256 for_each_intel_crtc(dev, crtc)
e2c719b7 9257 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9258 pipe_name(crtc->pipe));
9259
e2c719b7
RC		 9260 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9261 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9262 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9263 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9264 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9265 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9266 "CPU PWM1 enabled\n");
c5107b87 9267 if (IS_HASWELL(dev))
e2c719b7 9268 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9269 "CPU PWM2 enabled\n");
e2c719b7 9270 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9271 "PCH PWM1 enabled\n");
e2c719b7 9272 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9273 "Utility pin enabled\n");
e2c719b7 9274 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9275
9926ada1
PZ		 9276 /*
9277 * In theory we can still leave IRQs enabled, as long as only the HPD
9278 * interrupts remain enabled. We used to check for that, but since it's
9279 * gen-specific and since we only disable LCPLL after we fully disable
9280 * the interrupts, the check below should be enough.
9281 */
e2c719b7 9282 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9283}
9284
9ccd5aeb
PZ		 9285static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9286{
9287 struct drm_device *dev = dev_priv->dev;
9288
9289 if (IS_HASWELL(dev))
9290 return I915_READ(D_COMP_HSW);
9291 else
9292 return I915_READ(D_COMP_BDW);
9293}
9294
3c4c9b81
PZ		 9295static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9296{
9297 struct drm_device *dev = dev_priv->dev;
9298
9299 if (IS_HASWELL(dev)) {
9300 mutex_lock(&dev_priv->rps.hw_lock);
9301 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9302 val))
f475dadf 9303 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9304 mutex_unlock(&dev_priv->rps.hw_lock);
9305 } else {
9ccd5aeb
PZ		 9306 I915_WRITE(D_COMP_BDW, val);
9307 POSTING_READ(D_COMP_BDW);
3c4c9b81 9308 }
be256dc7
PZ		 9309}
9310
9311/*
9312 * This function implements pieces of two sequences from BSpec:
9313 * - Sequence for display software to disable LCPLL
9314 * - Sequence for display software to allow package C8+
9315 * The steps implemented here are just the steps that actually touch the LCPLL
9316 * register. Callers should take care of disabling all the display engine
9317 * functions, doing the mode unset, fixing interrupts, etc.
9318 */
6ff58d53
PZ		 9319static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9320 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9321{
9322 uint32_t val;
9323
9324 assert_can_disable_lcpll(dev_priv);
9325
9326 val = I915_READ(LCPLL_CTL);
9327
9328 if (switch_to_fclk) {
9329 val |= LCPLL_CD_SOURCE_FCLK;
9330 I915_WRITE(LCPLL_CTL, val);
9331
9332 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9333 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9334 DRM_ERROR("Switching to FCLK failed\n");
9335
9336 val = I915_READ(LCPLL_CTL);
9337 }
9338
9339 val |= LCPLL_PLL_DISABLE;
9340 I915_WRITE(LCPLL_CTL, val);
9341 POSTING_READ(LCPLL_CTL);
9342
9343 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9344 DRM_ERROR("LCPLL still locked\n");
9345
9ccd5aeb 9346 val = hsw_read_dcomp(dev_priv);
be256dc7 9347 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9348 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9349 ndelay(100);
9350
9ccd5aeb
PZ		 9351 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9352 1))
be256dc7
PZ		 9353 DRM_ERROR("D_COMP RCOMP still in progress\n");
9354
9355 if (allow_power_down) {
9356 val = I915_READ(LCPLL_CTL);
9357 val |= LCPLL_POWER_DOWN_ALLOW;
9358 I915_WRITE(LCPLL_CTL, val);
9359 POSTING_READ(LCPLL_CTL);
9360 }
9361}
9362
9363/*
9364 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9365 * source.
9366 */
6ff58d53 9367static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9368{
9369 uint32_t val;
9370
9371 val = I915_READ(LCPLL_CTL);
9372
9373 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9374 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9375 return;
9376
a8a8bd54
PZ		 9377 /*
9378 * Make sure we're not on PC8 state before disabling PC8, otherwise
9379 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9380 */
59bad947 9381 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9382
be256dc7
PZ		 9383 if (val & LCPLL_POWER_DOWN_ALLOW) {
9384 val &= ~LCPLL_POWER_DOWN_ALLOW;
9385 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9386 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9387 }
9388
9ccd5aeb 9389 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9390 val |= D_COMP_COMP_FORCE;
9391 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9392 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9393
9394 val = I915_READ(LCPLL_CTL);
9395 val &= ~LCPLL_PLL_DISABLE;
9396 I915_WRITE(LCPLL_CTL, val);
9397
9398 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9399 DRM_ERROR("LCPLL not locked yet\n");
9400
9401 if (val & LCPLL_CD_SOURCE_FCLK) {
9402 val = I915_READ(LCPLL_CTL);
9403 val &= ~LCPLL_CD_SOURCE_FCLK;
9404 I915_WRITE(LCPLL_CTL, val);
9405
9406 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9407 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9408 DRM_ERROR("Switching back to LCPLL failed\n");
9409 }
215733fa 9410
59bad947 9411 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9412 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9413}
9414
765dab67
PZ		 9415/*
9416 * Package states C8 and deeper are really deep PC states that can only be
9417 * reached when all the devices on the system allow it, so even if the graphics
9418 * device allows PC8+, it doesn't mean the system will actually get to these
9419 * states. Our driver only allows PC8+ when going into runtime PM.
9420 *
9421 * The requirements for PC8+ are that all the outputs are disabled, the power
9422 * well is disabled and most interrupts are disabled, and these are also
9423 * requirements for runtime PM. When these conditions are met, we manually do
9424 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9425 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9426 * hang the machine.
9427 *
9428 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9429 * the state of some registers, so when we come back from PC8+ we need to
9430 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9431 * need to take care of the registers kept by RC6. Notice that this happens even
9432 * if we don't put the device in PCI D3 state (which is what currently happens
9433 * because of the runtime PM support).
9434 *
9435 * For more, read "Display Sequences for Package C8" on the hardware
9436 * documentation.
9437 */
a14cb6fc 9438void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9439{
c67a470b
PZ		 9440 struct drm_device *dev = dev_priv->dev;
9441 uint32_t val;
9442
c67a470b
PZ		 9443 DRM_DEBUG_KMS("Enabling package C8+\n");
9444
c67a470b
PZ		 9445 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9446 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9447 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9448 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9449 }
9450
9451 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9452 hsw_disable_lcpll(dev_priv, true, true);
9453}
9454
a14cb6fc 9455void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9456{
9457 struct drm_device *dev = dev_priv->dev;
9458 uint32_t val;
9459
c67a470b
PZ		 9460 DRM_DEBUG_KMS("Disabling package C8+\n");
9461
9462 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9463 lpt_init_pch_refclk(dev);
9464
9465 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9466 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9467 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9468 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9469 }
9470
9471 intel_prepare_ddi(dev);
c67a470b
PZ		 9472}
9473
27c329ed 9474static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9475{
a821fc46 9476 struct drm_device *dev = old_state->dev;
27c329ed 9477 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9478
27c329ed 9479 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9480}
9481
b432e5cf 9482/* compute the max rate for new configuration */
27c329ed 9483static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9484{
b432e5cf 9485 struct intel_crtc *intel_crtc;
27c329ed 9486 struct intel_crtc_state *crtc_state;
b432e5cf 9487 int max_pixel_rate = 0;
b432e5cf 9488
27c329ed
ML		 9489 for_each_intel_crtc(state->dev, intel_crtc) {
9490 int pixel_rate;
9491
9492 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9493 if (IS_ERR(crtc_state))
9494 return PTR_ERR(crtc_state);
9495
9496 if (!crtc_state->base.enable)
b432e5cf
VS		 9497 continue;
9498
27c329ed 9499 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9500
9501 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9502 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9503 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9504
9505 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9506 }
9507
9508 return max_pixel_rate;
9509}
9510
9511static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9512{
9513 struct drm_i915_private *dev_priv = dev->dev_private;
9514 uint32_t val, data;
9515 int ret;
9516
9517 if (WARN((I915_READ(LCPLL_CTL) &
9518 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9519 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9520 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9521 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9522 "trying to change cdclk frequency with cdclk not enabled\n"))
9523 return;
9524
9525 mutex_lock(&dev_priv->rps.hw_lock);
9526 ret = sandybridge_pcode_write(dev_priv,
9527 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9528 mutex_unlock(&dev_priv->rps.hw_lock);
9529 if (ret) {
9530 DRM_ERROR("failed to inform pcode about cdclk change\n");
9531 return;
9532 }
9533
9534 val = I915_READ(LCPLL_CTL);
9535 val |= LCPLL_CD_SOURCE_FCLK;
9536 I915_WRITE(LCPLL_CTL, val);
9537
9538 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9539 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9540 DRM_ERROR("Switching to FCLK failed\n");
9541
9542 val = I915_READ(LCPLL_CTL);
9543 val &= ~LCPLL_CLK_FREQ_MASK;
9544
9545 switch (cdclk) {
9546 case 450000:
9547 val |= LCPLL_CLK_FREQ_450;
9548 data = 0;
9549 break;
9550 case 540000:
9551 val |= LCPLL_CLK_FREQ_54O_BDW;
9552 data = 1;
9553 break;
9554 case 337500:
9555 val |= LCPLL_CLK_FREQ_337_5_BDW;
9556 data = 2;
9557 break;
9558 case 675000:
9559 val |= LCPLL_CLK_FREQ_675_BDW;
9560 data = 3;
9561 break;
9562 default:
9563 WARN(1, "invalid cdclk frequency\n");
9564 return;
9565 }
9566
9567 I915_WRITE(LCPLL_CTL, val);
9568
9569 val = I915_READ(LCPLL_CTL);
9570 val &= ~LCPLL_CD_SOURCE_FCLK;
9571 I915_WRITE(LCPLL_CTL, val);
9572
9573 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9574 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9575 DRM_ERROR("Switching back to LCPLL failed\n");
9576
9577 mutex_lock(&dev_priv->rps.hw_lock);
9578 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9579 mutex_unlock(&dev_priv->rps.hw_lock);
9580
9581 intel_update_cdclk(dev);
9582
9583 WARN(cdclk != dev_priv->cdclk_freq,
9584 "cdclk requested %d kHz but got %d kHz\n",
9585 cdclk, dev_priv->cdclk_freq);
9586}
9587
27c329ed 9588static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9589{
27c329ed
ML		 9590 struct drm_i915_private *dev_priv = to_i915(state->dev);
9591 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9592 int cdclk;
9593
9594 /*
9595 * FIXME should also account for plane ratio
9596 * once 64bpp pixel formats are supported.
9597 */
27c329ed 9598 if (max_pixclk > 540000)
b432e5cf 9599 cdclk = 675000;
27c329ed 9600 else if (max_pixclk > 450000)
b432e5cf 9601 cdclk = 540000;
27c329ed 9602 else if (max_pixclk > 337500)
b432e5cf
VS		 9603 cdclk = 450000;
9604 else
9605 cdclk = 337500;
9606
9607 /*
9608 * FIXME move the cdclk caclulation to
9609 * compute_config() so we can fail gracegully.
9610 */
9611 if (cdclk > dev_priv->max_cdclk_freq) {
9612 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9613 cdclk, dev_priv->max_cdclk_freq);
9614 cdclk = dev_priv->max_cdclk_freq;
9615 }
9616
27c329ed 9617 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9618
9619 return 0;
9620}
9621
27c329ed 9622static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9623{
27c329ed
ML		 9624 struct drm_device *dev = old_state->dev;
9625 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9626
27c329ed 9627 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9628}
9629
190f68c5
ACO		 9630static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9631 struct intel_crtc_state *crtc_state)
09b4ddf9 9632{
190f68c5 9633 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9634 return -EINVAL;
716c2e55 9635
c7653199 9636 crtc->lowfreq_avail = false;
644cef34 9637
c8f7a0db 9638 return 0;
79e53945
JB		 9639}
9640
3760b59c
S		 9641static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9642 enum port port,
9643 struct intel_crtc_state *pipe_config)
9644{
9645 switch (port) {
9646 case PORT_A:
9647 pipe_config->ddi_pll_sel = SKL_DPLL0;
9648 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9649 break;
9650 case PORT_B:
9651 pipe_config->ddi_pll_sel = SKL_DPLL1;
9652 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9653 break;
9654 case PORT_C:
9655 pipe_config->ddi_pll_sel = SKL_DPLL2;
9656 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9657 break;
9658 default:
9659 DRM_ERROR("Incorrect port type\n");
9660 }
9661}
9662
96b7dfb7
S		 9663static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9664 enum port port,
5cec258b 9665 struct intel_crtc_state *pipe_config)
96b7dfb7 9666{
3148ade7 9667 u32 temp, dpll_ctl1;
96b7dfb7
S		 9668
9669 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9670 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9671
9672 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9673 case SKL_DPLL0:
9674 /*
9675 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9676 * of the shared DPLL framework and thus needs to be read out
9677 * separately
9678 */
9679 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9680 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9681 break;
96b7dfb7
S		 9682 case SKL_DPLL1:
9683 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9684 break;
9685 case SKL_DPLL2:
9686 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9687 break;
9688 case SKL_DPLL3:
9689 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9690 break;
96b7dfb7
S		 9691 }
9692}
9693
7d2c8175
DL		 9694static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9695 enum port port,
5cec258b 9696 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9697{
9698 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9699
9700 switch (pipe_config->ddi_pll_sel) {
9701 case PORT_CLK_SEL_WRPLL1:
9702 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9703 break;
9704 case PORT_CLK_SEL_WRPLL2:
9705 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9706 break;
9707 }
9708}
9709
26804afd 9710static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9711 struct intel_crtc_state *pipe_config)
26804afd
DV		 9712{
9713 struct drm_device *dev = crtc->base.dev;
9714 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9715 struct intel_shared_dpll *pll;
26804afd
DV		 9716 enum port port;
9717 uint32_t tmp;
9718
9719 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9720
9721 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9722
96b7dfb7
S		 9723 if (IS_SKYLAKE(dev))
9724 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9725 else if (IS_BROXTON(dev))
9726 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9727 else
9728 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9729
d452c5b6
DV		 9730 if (pipe_config->shared_dpll >= 0) {
9731 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9732
9733 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9734 &pipe_config->dpll_hw_state));
9735 }
9736
26804afd
DV		 9737 /*
9738 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9739 * DDI E. So just check whether this pipe is wired to DDI E and whether
9740 * the PCH transcoder is on.
9741 */
ca370455
DL		 9742 if (INTEL_INFO(dev)->gen < 9 &&
9743 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9744 pipe_config->has_pch_encoder = true;
9745
9746 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9747 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9748 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9749
9750 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9751 }
9752}
9753
0e8ffe1b 9754static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9755 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9756{
9757 struct drm_device *dev = crtc->base.dev;
9758 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9759 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9760 uint32_t tmp;
9761
f458ebbc 9762 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9763 POWER_DOMAIN_PIPE(crtc->pipe)))
9764 return false;
9765
e143a21c 9766 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9767 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9768
eccb140b
DV		 9769 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9770 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9771 enum pipe trans_edp_pipe;
9772 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9773 default:
9774 WARN(1, "unknown pipe linked to edp transcoder\n");
9775 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9776 case TRANS_DDI_EDP_INPUT_A_ON:
9777 trans_edp_pipe = PIPE_A;
9778 break;
9779 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9780 trans_edp_pipe = PIPE_B;
9781 break;
9782 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9783 trans_edp_pipe = PIPE_C;
9784 break;
9785 }
9786
9787 if (trans_edp_pipe == crtc->pipe)
9788 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9789 }
9790
f458ebbc 9791 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9792 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9793 return false;
9794
eccb140b 9795 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9796 if (!(tmp & PIPECONF_ENABLE))
9797 return false;
9798
26804afd 9799 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9800
1bd1bd80
DV		 9801 intel_get_pipe_timings(crtc, pipe_config);
9802
a1b2278e
CK		 9803 if (INTEL_INFO(dev)->gen >= 9) {
9804 skl_init_scalers(dev, crtc, pipe_config);
9805 }
9806
2fa2fe9a 9807 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9808
9809 if (INTEL_INFO(dev)->gen >= 9) {
9810 pipe_config->scaler_state.scaler_id = -1;
9811 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9812 }
9813
bd2e244f 9814 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9815 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9816 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9817 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9818 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9819 else
9820 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9821 }
88adfff1 9822
e59150dc
JB		 9823 if (IS_HASWELL(dev))
9824 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9825 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9826
ebb69c95
CT		 9827 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9828 pipe_config->pixel_multiplier =
9829 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9830 } else {
9831 pipe_config->pixel_multiplier = 1;
9832 }
6c49f241 9833
0e8ffe1b
DV		 9834 return true;
9835}
9836
560b85bb
CW		 9837static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9838{
9839 struct drm_device *dev = crtc->dev;
9840 struct drm_i915_private *dev_priv = dev->dev_private;
9841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9842 uint32_t cntl = 0, size = 0;
560b85bb 9843
dc41c154 9844 if (base) {
3dd512fb
MR		 9845 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9846 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9847 unsigned int stride = roundup_pow_of_two(width) * 4;
9848
9849 switch (stride) {
9850 default:
9851 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9852 width, stride);
9853 stride = 256;
9854 /* fallthrough */
9855 case 256:
9856 case 512:
9857 case 1024:
9858 case 2048:
9859 break;
4b0e333e
CW		 9860 }
9861
dc41c154
VS		 9862 cntl |= CURSOR_ENABLE |
9863 CURSOR_GAMMA_ENABLE |
9864 CURSOR_FORMAT_ARGB |
9865 CURSOR_STRIDE(stride);
9866
9867 size = (height << 12) | width;
4b0e333e 9868 }
560b85bb 9869
dc41c154
VS		 9870 if (intel_crtc->cursor_cntl != 0 &&
9871 (intel_crtc->cursor_base != base ||
9872 intel_crtc->cursor_size != size ||
9873 intel_crtc->cursor_cntl != cntl)) {
9874 /* On these chipsets we can only modify the base/size/stride
9875 * whilst the cursor is disabled.
9876 */
9877 I915_WRITE(_CURACNTR, 0);
4b0e333e 9878 POSTING_READ(_CURACNTR);
dc41c154 9879 intel_crtc->cursor_cntl = 0;
4b0e333e 9880 }
560b85bb 9881
99d1f387 9882 if (intel_crtc->cursor_base != base) {
9db4a9c7 9883 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9884 intel_crtc->cursor_base = base;
9885 }
4726e0b0 9886
dc41c154
VS		 9887 if (intel_crtc->cursor_size != size) {
9888 I915_WRITE(CURSIZE, size);
9889 intel_crtc->cursor_size = size;
4b0e333e 9890 }
560b85bb 9891
4b0e333e 9892 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9893 I915_WRITE(_CURACNTR, cntl);
9894 POSTING_READ(_CURACNTR);
4b0e333e 9895 intel_crtc->cursor_cntl = cntl;
560b85bb 9896 }
560b85bb
CW		 9897}
9898
560b85bb 9899static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9900{
9901 struct drm_device *dev = crtc->dev;
9902 struct drm_i915_private *dev_priv = dev->dev_private;
9903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9904 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9905 uint32_t cntl;
9906
9907 cntl = 0;
9908 if (base) {
9909 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9910 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9911 case 64:
9912 cntl |= CURSOR_MODE_64_ARGB_AX;
9913 break;
9914 case 128:
9915 cntl |= CURSOR_MODE_128_ARGB_AX;
9916 break;
9917 case 256:
9918 cntl |= CURSOR_MODE_256_ARGB_AX;
9919 break;
9920 default:
3dd512fb 9921 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9922 return;
65a21cd6 9923 }
4b0e333e 9924 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9925
9926 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9927 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9928 }
65a21cd6 9929
8e7d688b 9930 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9931 cntl |= CURSOR_ROTATE_180;
9932
4b0e333e
CW		 9933 if (intel_crtc->cursor_cntl != cntl) {
9934 I915_WRITE(CURCNTR(pipe), cntl);
9935 POSTING_READ(CURCNTR(pipe));
9936 intel_crtc->cursor_cntl = cntl;
65a21cd6 9937 }
4b0e333e 9938
65a21cd6 9939 /* and commit changes on next vblank */
5efb3e28
VS		 9940 I915_WRITE(CURBASE(pipe), base);
9941 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9942
9943 intel_crtc->cursor_base = base;
65a21cd6
JB		 9944}
9945
cda4b7d3 9946/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9947static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9948 bool on)
cda4b7d3
CW		 9949{
9950 struct drm_device *dev = crtc->dev;
9951 struct drm_i915_private *dev_priv = dev->dev_private;
9952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9953 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9954 int x = crtc->cursor_x;
9955 int y = crtc->cursor_y;
d6e4db15 9956 u32 base = 0, pos = 0;
cda4b7d3 9957
d6e4db15 9958 if (on)
cda4b7d3 9959 base = intel_crtc->cursor_addr;
cda4b7d3 9960
6e3c9717 9961 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9962 base = 0;
9963
6e3c9717 9964 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9965 base = 0;
9966
9967 if (x < 0) {
3dd512fb 9968 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9969 base = 0;
9970
9971 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9972 x = -x;
9973 }
9974 pos |= x << CURSOR_X_SHIFT;
9975
9976 if (y < 0) {
3dd512fb 9977 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9978 base = 0;
9979
9980 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9981 y = -y;
9982 }
9983 pos |= y << CURSOR_Y_SHIFT;
9984
4b0e333e 9985 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9986 return;
9987
5efb3e28
VS		 9988 I915_WRITE(CURPOS(pipe), pos);
9989
4398ad45
VS		 9990 /* ILK+ do this automagically */
9991 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9992 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9993 base += (intel_crtc->base.cursor->state->crtc_h *
9994 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9995 }
9996
8ac54669 9997 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9998 i845_update_cursor(crtc, base);
9999 else
10000 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10001}
10002
dc41c154
VS		 10003static bool cursor_size_ok(struct drm_device *dev,
10004 uint32_t width, uint32_t height)
10005{
10006 if (width == 0 || height == 0)
10007 return false;
10008
10009 /*
10010 * 845g/865g are special in that they are only limited by
10011 * the width of their cursors, the height is arbitrary up to
10012 * the precision of the register. Everything else requires
10013 * square cursors, limited to a few power-of-two sizes.
10014 */
10015 if (IS_845G(dev) || IS_I865G(dev)) {
10016 if ((width & 63) != 0)
10017 return false;
10018
10019 if (width > (IS_845G(dev) ? 64 : 512))
10020 return false;
10021
10022 if (height > 1023)
10023 return false;
10024 } else {
10025 switch (width | height) {
10026 case 256:
10027 case 128:
10028 if (IS_GEN2(dev))
10029 return false;
10030 case 64:
10031 break;
10032 default:
10033 return false;
10034 }
10035 }
10036
10037 return true;
10038}
10039
79e53945 10040static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10041 u16 *blue, uint32_t start, uint32_t size)
79e53945 10042{
7203425a 10043 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10045
7203425a 10046 for (i = start; i < end; i++) {
79e53945
JB		 10047 intel_crtc->lut_r[i] = red[i] >> 8;
10048 intel_crtc->lut_g[i] = green[i] >> 8;
10049 intel_crtc->lut_b[i] = blue[i] >> 8;
10050 }
10051
10052 intel_crtc_load_lut(crtc);
10053}
10054
79e53945
JB		 10055/* VESA 640x480x72Hz mode to set on the pipe */
10056static struct drm_display_mode load_detect_mode = {
10057 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10058 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10059};
10060
a8bb6818
DV		 10061struct drm_framebuffer *
10062__intel_framebuffer_create(struct drm_device *dev,
10063 struct drm_mode_fb_cmd2 *mode_cmd,
10064 struct drm_i915_gem_object *obj)
d2dff872
CW		 10065{
10066 struct intel_framebuffer *intel_fb;
10067 int ret;
10068
10069 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10070 if (!intel_fb) {
6ccb81f2 10071 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10072 return ERR_PTR(-ENOMEM);
10073 }
10074
10075 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10076 if (ret)
10077 goto err;
d2dff872
CW		 10078
10079 return &intel_fb->base;
dd4916c5 10080err:
6ccb81f2 10081 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10082 kfree(intel_fb);
10083
10084 return ERR_PTR(ret);
d2dff872
CW		 10085}
10086
b5ea642a 10087static struct drm_framebuffer *
a8bb6818
DV		 10088intel_framebuffer_create(struct drm_device *dev,
10089 struct drm_mode_fb_cmd2 *mode_cmd,
10090 struct drm_i915_gem_object *obj)
10091{
10092 struct drm_framebuffer *fb;
10093 int ret;
10094
10095 ret = i915_mutex_lock_interruptible(dev);
10096 if (ret)
10097 return ERR_PTR(ret);
10098 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10099 mutex_unlock(&dev->struct_mutex);
10100
10101 return fb;
10102}
10103
d2dff872
CW		 10104static u32
10105intel_framebuffer_pitch_for_width(int width, int bpp)
10106{
10107 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10108 return ALIGN(pitch, 64);
10109}
10110
10111static u32
10112intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10113{
10114 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10115 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10116}
10117
10118static struct drm_framebuffer *
10119intel_framebuffer_create_for_mode(struct drm_device *dev,
10120 struct drm_display_mode *mode,
10121 int depth, int bpp)
10122{
10123 struct drm_i915_gem_object *obj;
0fed39bd 10124 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10125
10126 obj = i915_gem_alloc_object(dev,
10127 intel_framebuffer_size_for_mode(mode, bpp));
10128 if (obj == NULL)
10129 return ERR_PTR(-ENOMEM);
10130
10131 mode_cmd.width = mode->hdisplay;
10132 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10133 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10134 bpp);
5ca0c34a 10135 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10136
10137 return intel_framebuffer_create(dev, &mode_cmd, obj);
10138}
10139
10140static struct drm_framebuffer *
10141mode_fits_in_fbdev(struct drm_device *dev,
10142 struct drm_display_mode *mode)
10143{
4520f53a 10144#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10145 struct drm_i915_private *dev_priv = dev->dev_private;
10146 struct drm_i915_gem_object *obj;
10147 struct drm_framebuffer *fb;
10148
4c0e5528 10149 if (!dev_priv->fbdev)
d2dff872
CW		 10150 return NULL;
10151
4c0e5528 10152 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10153 return NULL;
10154
4c0e5528
DV		 10155 obj = dev_priv->fbdev->fb->obj;
10156 BUG_ON(!obj);
10157
8bcd4553 10158 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10159 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10160 fb->bits_per_pixel))
d2dff872
CW		 10161 return NULL;
10162
01f2c773 10163 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10164 return NULL;
10165
10166 return fb;
4520f53a
DV		 10167#else
10168 return NULL;
10169#endif
d2dff872
CW		 10170}
10171
d3a40d1b
ACO		 10172static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10173 struct drm_crtc *crtc,
10174 struct drm_display_mode *mode,
10175 struct drm_framebuffer *fb,
10176 int x, int y)
10177{
10178 struct drm_plane_state *plane_state;
10179 int hdisplay, vdisplay;
10180 int ret;
10181
10182 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10183 if (IS_ERR(plane_state))
10184 return PTR_ERR(plane_state);
10185
10186 if (mode)
10187 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10188 else
10189 hdisplay = vdisplay = 0;
10190
10191 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10192 if (ret)
10193 return ret;
10194 drm_atomic_set_fb_for_plane(plane_state, fb);
10195 plane_state->crtc_x = 0;
10196 plane_state->crtc_y = 0;
10197 plane_state->crtc_w = hdisplay;
10198 plane_state->crtc_h = vdisplay;
10199 plane_state->src_x = x << 16;
10200 plane_state->src_y = y << 16;
10201 plane_state->src_w = hdisplay << 16;
10202 plane_state->src_h = vdisplay << 16;
10203
10204 return 0;
10205}
10206
d2434ab7 10207bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10208 struct drm_display_mode *mode,
51fd371b
RC		 10209 struct intel_load_detect_pipe *old,
10210 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10211{
10212 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10213 struct intel_encoder *intel_encoder =
10214 intel_attached_encoder(connector);
79e53945 10215 struct drm_crtc *possible_crtc;
4ef69c7a 10216 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10217 struct drm_crtc *crtc = NULL;
10218 struct drm_device *dev = encoder->dev;
94352cf9 10219 struct drm_framebuffer *fb;
51fd371b 10220 struct drm_mode_config *config = &dev->mode_config;
83a57153 10221 struct drm_atomic_state *state = NULL;
944b0c76 10222 struct drm_connector_state *connector_state;
4be07317 10223 struct intel_crtc_state *crtc_state;
51fd371b 10224 int ret, i = -1;
79e53945 10225
d2dff872 10226 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10227 connector->base.id, connector->name,
8e329a03 10228 encoder->base.id, encoder->name);
d2dff872 10229
51fd371b
RC		 10230retry:
10231 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10232 if (ret)
10233 goto fail_unlock;
6e9f798d 10234
79e53945
JB		 10235 /*
10236 * Algorithm gets a little messy:
7a5e4805 10237 *
79e53945
JB		 10238 * - if the connector already has an assigned crtc, use it (but make
10239 * sure it's on first)
7a5e4805 10240 *
79e53945
JB		 10241 * - try to find the first unused crtc that can drive this connector,
10242 * and use that if we find one
79e53945
JB		 10243 */
10244
10245 /* See if we already have a CRTC for this connector */
10246 if (encoder->crtc) {
10247 crtc = encoder->crtc;
8261b191 10248
51fd371b 10249 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10250 if (ret)
10251 goto fail_unlock;
10252 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10253 if (ret)
10254 goto fail_unlock;
7b24056b 10255
24218aac 10256 old->dpms_mode = connector->dpms;
8261b191
CW		 10257 old->load_detect_temp = false;
10258
10259 /* Make sure the crtc and connector are running */
24218aac
DV		 10260 if (connector->dpms != DRM_MODE_DPMS_ON)
10261 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10262
7173188d 10263 return true;
79e53945
JB		 10264 }
10265
10266 /* Find an unused one (if possible) */
70e1e0ec 10267 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10268 i++;
10269 if (!(encoder->possible_crtcs & (1 << i)))
10270 continue;
83d65738 10271 if (possible_crtc->state->enable)
a459249c
VS		 10272 continue;
10273 /* This can occur when applying the pipe A quirk on resume. */
10274 if (to_intel_crtc(possible_crtc)->new_enabled)
10275 continue;
10276
10277 crtc = possible_crtc;
10278 break;
79e53945
JB		 10279 }
10280
10281 /*
10282 * If we didn't find an unused CRTC, don't use any.
10283 */
10284 if (!crtc) {
7173188d 10285 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10286 goto fail_unlock;
79e53945
JB		 10287 }
10288
51fd371b
RC		 10289 ret = drm_modeset_lock(&crtc->mutex, ctx);
10290 if (ret)
4d02e2de
DV		 10291 goto fail_unlock;
10292 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10293 if (ret)
51fd371b 10294 goto fail_unlock;
fc303101
DV		 10295 intel_encoder->new_crtc = to_intel_crtc(crtc);
10296 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10297
10298 intel_crtc = to_intel_crtc(crtc);
412b61d8 10299 intel_crtc->new_enabled = true;
24218aac 10300 old->dpms_mode = connector->dpms;
8261b191 10301 old->load_detect_temp = true;
d2dff872 10302 old->release_fb = NULL;
79e53945 10303
83a57153
ACO		 10304 state = drm_atomic_state_alloc(dev);
10305 if (!state)
10306 return false;
10307
10308 state->acquire_ctx = ctx;
10309
944b0c76
ACO		 10310 connector_state = drm_atomic_get_connector_state(state, connector);
10311 if (IS_ERR(connector_state)) {
10312 ret = PTR_ERR(connector_state);
10313 goto fail;
10314 }
10315
10316 connector_state->crtc = crtc;
10317 connector_state->best_encoder = &intel_encoder->base;
10318
4be07317
ACO		 10319 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10320 if (IS_ERR(crtc_state)) {
10321 ret = PTR_ERR(crtc_state);
10322 goto fail;
10323 }
10324
49d6fa21 10325 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10326
6492711d
CW		 10327 if (!mode)
10328 mode = &load_detect_mode;
79e53945 10329
d2dff872
CW		 10330 /* We need a framebuffer large enough to accommodate all accesses
10331 * that the plane may generate whilst we perform load detection.
10332 * We can not rely on the fbcon either being present (we get called
10333 * during its initialisation to detect all boot displays, or it may
10334 * not even exist) or that it is large enough to satisfy the
10335 * requested mode.
10336 */
94352cf9
DV		 10337 fb = mode_fits_in_fbdev(dev, mode);
10338 if (fb == NULL) {
d2dff872 10339 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10340 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10341 old->release_fb = fb;
d2dff872
CW		 10342 } else
10343 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10344 if (IS_ERR(fb)) {
d2dff872 10345 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10346 goto fail;
79e53945 10347 }
79e53945 10348
d3a40d1b
ACO		 10349 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10350 if (ret)
10351 goto fail;
10352
8c7b5ccb
ACO		 10353 drm_mode_copy(&crtc_state->base.mode, mode);
10354
568c634a 10355 if (intel_set_mode(state)) {
6492711d 10356 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10357 if (old->release_fb)
10358 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10359 goto fail;
79e53945 10360 }
9128b040 10361 crtc->primary->crtc = crtc;
7173188d 10362
79e53945 10363 /* let the connector get through one full cycle before testing */
9d0498a2 10364 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10365 return true;
412b61d8
VS		 10366
10367 fail:
83d65738 10368 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10369fail_unlock:
e5d958ef
ACO		 10370 drm_atomic_state_free(state);
10371 state = NULL;
83a57153 10372
51fd371b
RC		 10373 if (ret == -EDEADLK) {
10374 drm_modeset_backoff(ctx);
10375 goto retry;
10376 }
10377
412b61d8 10378 return false;
79e53945
JB		 10379}
10380
d2434ab7 10381void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10382 struct intel_load_detect_pipe *old,
10383 struct drm_modeset_acquire_ctx *ctx)
79e53945 10384{
83a57153 10385 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10386 struct intel_encoder *intel_encoder =
10387 intel_attached_encoder(connector);
4ef69c7a 10388 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10389 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10391 struct drm_atomic_state *state;
944b0c76 10392 struct drm_connector_state *connector_state;
4be07317 10393 struct intel_crtc_state *crtc_state;
d3a40d1b 10394 int ret;
79e53945 10395
d2dff872 10396 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10397 connector->base.id, connector->name,
8e329a03 10398 encoder->base.id, encoder->name);
d2dff872 10399
8261b191 10400 if (old->load_detect_temp) {
83a57153 10401 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10402 if (!state)
10403 goto fail;
83a57153
ACO		 10404
10405 state->acquire_ctx = ctx;
10406
944b0c76
ACO		 10407 connector_state = drm_atomic_get_connector_state(state, connector);
10408 if (IS_ERR(connector_state))
10409 goto fail;
10410
4be07317
ACO		 10411 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10412 if (IS_ERR(crtc_state))
10413 goto fail;
10414
fc303101
DV		 10415 to_intel_connector(connector)->new_encoder = NULL;
10416 intel_encoder->new_crtc = NULL;
412b61d8 10417 intel_crtc->new_enabled = false;
944b0c76
ACO		 10418
10419 connector_state->best_encoder = NULL;
10420 connector_state->crtc = NULL;
10421
49d6fa21 10422 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10423
d3a40d1b
ACO		 10424 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10425 0, 0);
10426 if (ret)
10427 goto fail;
10428
568c634a 10429 ret = intel_set_mode(state);
2bfb4627
ACO		 10430 if (ret)
10431 goto fail;
d2dff872 10432
36206361
DV		 10433 if (old->release_fb) {
10434 drm_framebuffer_unregister_private(old->release_fb);
10435 drm_framebuffer_unreference(old->release_fb);
10436 }
d2dff872 10437
0622a53c 10438 return;
79e53945
JB		 10439 }
10440
c751ce4f 10441 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10442 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10443 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10444
10445 return;
10446fail:
10447 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10448 drm_atomic_state_free(state);
79e53945
JB		 10449}
10450
da4a1efa 10451static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10452 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10453{
10454 struct drm_i915_private *dev_priv = dev->dev_private;
10455 u32 dpll = pipe_config->dpll_hw_state.dpll;
10456
10457 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10458 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10459 else if (HAS_PCH_SPLIT(dev))
10460 return 120000;
10461 else if (!IS_GEN2(dev))
10462 return 96000;
10463 else
10464 return 48000;
10465}
10466
79e53945 10467/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10468static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10469 struct intel_crtc_state *pipe_config)
79e53945 10470{
f1f644dc 10471 struct drm_device *dev = crtc->base.dev;
79e53945 10472 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10473 int pipe = pipe_config->cpu_transcoder;
293623f7 10474 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10475 u32 fp;
10476 intel_clock_t clock;
dccbea3b 10477 int port_clock;
da4a1efa 10478 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10479
10480 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10481 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10482 else
293623f7 10483 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10484
10485 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10486 if (IS_PINEVIEW(dev)) {
10487 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10488 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10489 } else {
10490 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10491 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10492 }
10493
a6c45cf0 10494 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10495 if (IS_PINEVIEW(dev))
10496 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10497 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10498 else
10499 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10500 DPLL_FPA01_P1_POST_DIV_SHIFT);
10501
10502 switch (dpll & DPLL_MODE_MASK) {
10503 case DPLLB_MODE_DAC_SERIAL:
10504 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10505 5 : 10;
10506 break;
10507 case DPLLB_MODE_LVDS:
10508 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10509 7 : 14;
10510 break;
10511 default:
28c97730 10512 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10513 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10514 return;
79e53945
JB		 10515 }
10516
ac58c3f0 10517 if (IS_PINEVIEW(dev))
dccbea3b 10518 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10519 else
dccbea3b 10520 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10521 } else {
0fb58223 10522 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10523 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10524
10525 if (is_lvds) {
10526 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10527 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10528
10529 if (lvds & LVDS_CLKB_POWER_UP)
10530 clock.p2 = 7;
10531 else
10532 clock.p2 = 14;
79e53945
JB		 10533 } else {
10534 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10535 clock.p1 = 2;
10536 else {
10537 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10538 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10539 }
10540 if (dpll & PLL_P2_DIVIDE_BY_4)
10541 clock.p2 = 4;
10542 else
10543 clock.p2 = 2;
79e53945 10544 }
da4a1efa 10545
dccbea3b 10546 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10547 }
10548
18442d08
VS		 10549 /*
10550 * This value includes pixel_multiplier. We will use
241bfc38 10551 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10552 * encoder's get_config() function.
10553 */
dccbea3b 10554 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10555}
10556
6878da05
VS		 10557int intel_dotclock_calculate(int link_freq,
10558 const struct intel_link_m_n *m_n)
f1f644dc 10559{
f1f644dc
JB		 10560 /*
10561 * The calculation for the data clock is:
1041a02f 10562 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10563 * But we want to avoid losing precison if possible, so:
1041a02f 10564 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10565 *
10566 * and the link clock is simpler:
1041a02f 10567 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10568 */
10569
6878da05
VS		 10570 if (!m_n->link_n)
10571 return 0;
f1f644dc 10572
6878da05
VS		 10573 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10574}
f1f644dc 10575
18442d08 10576static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10577 struct intel_crtc_state *pipe_config)
6878da05
VS		 10578{
10579 struct drm_device *dev = crtc->base.dev;
79e53945 10580
18442d08
VS		 10581 /* read out port_clock from the DPLL */
10582 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10583
f1f644dc 10584 /*
18442d08 10585 * This value does not include pixel_multiplier.
241bfc38 10586 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10587 * agree once we know their relationship in the encoder's
10588 * get_config() function.
79e53945 10589 */
2d112de7 10590 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10591 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10592 &pipe_config->fdi_m_n);
79e53945
JB		 10593}
10594
10595/** Returns the currently programmed mode of the given pipe. */
10596struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10597 struct drm_crtc *crtc)
10598{
548f245b 10599 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10601 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10602 struct drm_display_mode *mode;
5cec258b 10603 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10604 int htot = I915_READ(HTOTAL(cpu_transcoder));
10605 int hsync = I915_READ(HSYNC(cpu_transcoder));
10606 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10607 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10608 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10609
10610 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10611 if (!mode)
10612 return NULL;
10613
f1f644dc
JB		 10614 /*
10615 * Construct a pipe_config sufficient for getting the clock info
10616 * back out of crtc_clock_get.
10617 *
10618 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10619 * to use a real value here instead.
10620 */
293623f7 10621 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10622 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10623 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10624 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10625 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10626 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10627
773ae034 10628 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10629 mode->hdisplay = (htot & 0xffff) + 1;
10630 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10631 mode->hsync_start = (hsync & 0xffff) + 1;
10632 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10633 mode->vdisplay = (vtot & 0xffff) + 1;
10634 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10635 mode->vsync_start = (vsync & 0xffff) + 1;
10636 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10637
10638 drm_mode_set_name(mode);
79e53945
JB		 10639
10640 return mode;
10641}
10642
f047e395
CW		 10643void intel_mark_busy(struct drm_device *dev)
10644{
c67a470b
PZ		 10645 struct drm_i915_private *dev_priv = dev->dev_private;
10646
f62a0076
CW		 10647 if (dev_priv->mm.busy)
10648 return;
10649
43694d69 10650 intel_runtime_pm_get(dev_priv);
c67a470b 10651 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10652 if (INTEL_INFO(dev)->gen >= 6)
10653 gen6_rps_busy(dev_priv);
f62a0076 10654 dev_priv->mm.busy = true;
f047e395
CW		 10655}
10656
10657void intel_mark_idle(struct drm_device *dev)
652c393a 10658{
c67a470b 10659 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10660
f62a0076
CW		 10661 if (!dev_priv->mm.busy)
10662 return;
10663
10664 dev_priv->mm.busy = false;
10665
3d13ef2e 10666 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10667 gen6_rps_idle(dev->dev_private);
bb4cdd53 10668
43694d69 10669 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10670}
10671
79e53945
JB		 10672static void intel_crtc_destroy(struct drm_crtc *crtc)
10673{
10674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10675 struct drm_device *dev = crtc->dev;
10676 struct intel_unpin_work *work;
67e77c5a 10677
5e2d7afc 10678 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10679 work = intel_crtc->unpin_work;
10680 intel_crtc->unpin_work = NULL;
5e2d7afc 10681 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10682
10683 if (work) {
10684 cancel_work_sync(&work->work);
10685 kfree(work);
10686 }
79e53945
JB		 10687
10688 drm_crtc_cleanup(crtc);
67e77c5a 10689
79e53945
JB		 10690 kfree(intel_crtc);
10691}
10692
6b95a207
KH		 10693static void intel_unpin_work_fn(struct work_struct *__work)
10694{
10695 struct intel_unpin_work *work =
10696 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10697 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10698 struct drm_device *dev = crtc->base.dev;
10699 struct drm_plane *primary = crtc->base.primary;
6b95a207 10700
b4a98e57 10701 mutex_lock(&dev->struct_mutex);
a9ff8714 10702 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10703 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10704
7ff0ebcc 10705 intel_fbc_update(dev);
f06cc1b9
JH		 10706
10707 if (work->flip_queued_req)
146d84f0 10708 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10709 mutex_unlock(&dev->struct_mutex);
10710
a9ff8714 10711 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10712 drm_framebuffer_unreference(work->old_fb);
f99d7069 10713
a9ff8714
VS		 10714 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10715 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10716
6b95a207
KH		 10717 kfree(work);
10718}
10719
1afe3e9d 10720static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10721 struct drm_crtc *crtc)
6b95a207 10722{
6b95a207
KH		 10723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10724 struct intel_unpin_work *work;
6b95a207
KH		 10725 unsigned long flags;
10726
10727 /* Ignore early vblank irqs */
10728 if (intel_crtc == NULL)
10729 return;
10730
f326038a
DV		 10731 /*
10732 * This is called both by irq handlers and the reset code (to complete
10733 * lost pageflips) so needs the full irqsave spinlocks.
10734 */
6b95a207
KH		 10735 spin_lock_irqsave(&dev->event_lock, flags);
10736 work = intel_crtc->unpin_work;
e7d841ca
CW		 10737
10738 /* Ensure we don't miss a work->pending update ... */
10739 smp_rmb();
10740
10741 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10742 spin_unlock_irqrestore(&dev->event_lock, flags);
10743 return;
10744 }
10745
d6bbafa1 10746 page_flip_completed(intel_crtc);
0af7e4df 10747
6b95a207 10748 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10749}
10750
1afe3e9d
JB		 10751void intel_finish_page_flip(struct drm_device *dev, int pipe)
10752{
fbee40df 10753 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10755
49b14a5c 10756 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10757}
10758
10759void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10760{
fbee40df 10761 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10762 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10763
49b14a5c 10764 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10765}
10766
75f7f3ec
VS		 10767/* Is 'a' after or equal to 'b'? */
10768static bool g4x_flip_count_after_eq(u32 a, u32 b)
10769{
10770 return !((a - b) & 0x80000000);
10771}
10772
10773static bool page_flip_finished(struct intel_crtc *crtc)
10774{
10775 struct drm_device *dev = crtc->base.dev;
10776 struct drm_i915_private *dev_priv = dev->dev_private;
10777
bdfa7542
VS		 10778 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10779 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10780 return true;
10781
75f7f3ec
VS		 10782 /*
10783 * The relevant registers doen't exist on pre-ctg.
10784 * As the flip done interrupt doesn't trigger for mmio
10785 * flips on gmch platforms, a flip count check isn't
10786 * really needed there. But since ctg has the registers,
10787 * include it in the check anyway.
10788 */
10789 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10790 return true;
10791
10792 /*
10793 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10794 * used the same base address. In that case the mmio flip might
10795 * have completed, but the CS hasn't even executed the flip yet.
10796 *
10797 * A flip count check isn't enough as the CS might have updated
10798 * the base address just after start of vblank, but before we
10799 * managed to process the interrupt. This means we'd complete the
10800 * CS flip too soon.
10801 *
10802 * Combining both checks should get us a good enough result. It may
10803 * still happen that the CS flip has been executed, but has not
10804 * yet actually completed. But in case the base address is the same
10805 * anyway, we don't really care.
10806 */
10807 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10808 crtc->unpin_work->gtt_offset &&
10809 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10810 crtc->unpin_work->flip_count);
10811}
10812
6b95a207
KH		 10813void intel_prepare_page_flip(struct drm_device *dev, int plane)
10814{
fbee40df 10815 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10816 struct intel_crtc *intel_crtc =
10817 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10818 unsigned long flags;
10819
f326038a
DV		 10820
10821 /*
10822 * This is called both by irq handlers and the reset code (to complete
10823 * lost pageflips) so needs the full irqsave spinlocks.
10824 *
10825 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10826 * generate a page-flip completion irq, i.e. every modeset
10827 * is also accompanied by a spurious intel_prepare_page_flip().
10828 */
6b95a207 10829 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10830 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10831 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10832 spin_unlock_irqrestore(&dev->event_lock, flags);
10833}
10834
eba905b2 10835static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10836{
10837 /* Ensure that the work item is consistent when activating it ... */
10838 smp_wmb();
10839 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10840 /* and that it is marked active as soon as the irq could fire. */
10841 smp_wmb();
10842}
10843
8c9f3aaf
JB		 10844static int intel_gen2_queue_flip(struct drm_device *dev,
10845 struct drm_crtc *crtc,
10846 struct drm_framebuffer *fb,
ed8d1975 10847 struct drm_i915_gem_object *obj,
6258fbe2 10848 struct drm_i915_gem_request *req,
ed8d1975 10849 uint32_t flags)
8c9f3aaf 10850{
6258fbe2 10851 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10853 u32 flip_mask;
10854 int ret;
10855
5fb9de1a 10856 ret = intel_ring_begin(req, 6);
8c9f3aaf 10857 if (ret)
4fa62c89 10858 return ret;
8c9f3aaf
JB		 10859
10860 /* Can't queue multiple flips, so wait for the previous
10861 * one to finish before executing the next.
10862 */
10863 if (intel_crtc->plane)
10864 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10865 else
10866 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10867 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10868 intel_ring_emit(ring, MI_NOOP);
10869 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10870 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10871 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10872 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10873 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10874
10875 intel_mark_page_flip_active(intel_crtc);
83d4092b 10876 return 0;
8c9f3aaf
JB		 10877}
10878
10879static int intel_gen3_queue_flip(struct drm_device *dev,
10880 struct drm_crtc *crtc,
10881 struct drm_framebuffer *fb,
ed8d1975 10882 struct drm_i915_gem_object *obj,
6258fbe2 10883 struct drm_i915_gem_request *req,
ed8d1975 10884 uint32_t flags)
8c9f3aaf 10885{
6258fbe2 10886 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10888 u32 flip_mask;
10889 int ret;
10890
5fb9de1a 10891 ret = intel_ring_begin(req, 6);
8c9f3aaf 10892 if (ret)
4fa62c89 10893 return ret;
8c9f3aaf
JB		 10894
10895 if (intel_crtc->plane)
10896 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10897 else
10898 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10899 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10900 intel_ring_emit(ring, MI_NOOP);
10901 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10902 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10903 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10904 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10905 intel_ring_emit(ring, MI_NOOP);
10906
e7d841ca 10907 intel_mark_page_flip_active(intel_crtc);
83d4092b 10908 return 0;
8c9f3aaf
JB		 10909}
10910
10911static int intel_gen4_queue_flip(struct drm_device *dev,
10912 struct drm_crtc *crtc,
10913 struct drm_framebuffer *fb,
ed8d1975 10914 struct drm_i915_gem_object *obj,
6258fbe2 10915 struct drm_i915_gem_request *req,
ed8d1975 10916 uint32_t flags)
8c9f3aaf 10917{
6258fbe2 10918 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10919 struct drm_i915_private *dev_priv = dev->dev_private;
10920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10921 uint32_t pf, pipesrc;
10922 int ret;
10923
5fb9de1a 10924 ret = intel_ring_begin(req, 4);
8c9f3aaf 10925 if (ret)
4fa62c89 10926 return ret;
8c9f3aaf
JB		 10927
10928 /* i965+ uses the linear or tiled offsets from the
10929 * Display Registers (which do not change across a page-flip)
10930 * so we need only reprogram the base address.
10931 */
6d90c952
DV		 10932 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10933 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10934 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10935 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10936 obj->tiling_mode);
8c9f3aaf
JB		 10937
10938 /* XXX Enabling the panel-fitter across page-flip is so far
10939 * untested on non-native modes, so ignore it for now.
10940 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10941 */
10942 pf = 0;
10943 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10944 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10945
10946 intel_mark_page_flip_active(intel_crtc);
83d4092b 10947 return 0;
8c9f3aaf
JB		 10948}
10949
10950static int intel_gen6_queue_flip(struct drm_device *dev,
10951 struct drm_crtc *crtc,
10952 struct drm_framebuffer *fb,
ed8d1975 10953 struct drm_i915_gem_object *obj,
6258fbe2 10954 struct drm_i915_gem_request *req,
ed8d1975 10955 uint32_t flags)
8c9f3aaf 10956{
6258fbe2 10957 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10958 struct drm_i915_private *dev_priv = dev->dev_private;
10959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10960 uint32_t pf, pipesrc;
10961 int ret;
10962
5fb9de1a 10963 ret = intel_ring_begin(req, 4);
8c9f3aaf 10964 if (ret)
4fa62c89 10965 return ret;
8c9f3aaf 10966
6d90c952
DV		 10967 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10968 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10969 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10970 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10971
dc257cf1
DV		 10972 /* Contrary to the suggestions in the documentation,
10973 * "Enable Panel Fitter" does not seem to be required when page
10974 * flipping with a non-native mode, and worse causes a normal
10975 * modeset to fail.
10976 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10977 */
10978 pf = 0;
8c9f3aaf 10979 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10980 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10981
10982 intel_mark_page_flip_active(intel_crtc);
83d4092b 10983 return 0;
8c9f3aaf
JB		 10984}
10985
7c9017e5
JB		 10986static int intel_gen7_queue_flip(struct drm_device *dev,
10987 struct drm_crtc *crtc,
10988 struct drm_framebuffer *fb,
ed8d1975 10989 struct drm_i915_gem_object *obj,
6258fbe2 10990 struct drm_i915_gem_request *req,
ed8d1975 10991 uint32_t flags)
7c9017e5 10992{
6258fbe2 10993 struct intel_engine_cs *ring = req->ring;
7c9017e5 10994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10995 uint32_t plane_bit = 0;
ffe74d75
CW		 10996 int len, ret;
10997
eba905b2 10998 switch (intel_crtc->plane) {
cb05d8de
DV		 10999 case PLANE_A:
11000 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11001 break;
11002 case PLANE_B:
11003 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11004 break;
11005 case PLANE_C:
11006 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11007 break;
11008 default:
11009 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11010 return -ENODEV;
cb05d8de
DV		 11011 }
11012
ffe74d75 11013 len = 4;
f476828a 11014 if (ring->id == RCS) {
ffe74d75 11015 len += 6;
f476828a
DL		 11016 /*
11017 * On Gen 8, SRM is now taking an extra dword to accommodate
11018 * 48bits addresses, and we need a NOOP for the batch size to
11019 * stay even.
11020 */
11021 if (IS_GEN8(dev))
11022 len += 2;
11023 }
ffe74d75 11024
f66fab8e
VS		 11025 /*
11026 * BSpec MI_DISPLAY_FLIP for IVB:
11027 * "The full packet must be contained within the same cache line."
11028 *
11029 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11030 * cacheline, if we ever start emitting more commands before
11031 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11032 * then do the cacheline alignment, and finally emit the
11033 * MI_DISPLAY_FLIP.
11034 */
bba09b12 11035 ret = intel_ring_cacheline_align(req);
f66fab8e 11036 if (ret)
4fa62c89 11037 return ret;
f66fab8e 11038
5fb9de1a 11039 ret = intel_ring_begin(req, len);
7c9017e5 11040 if (ret)
4fa62c89 11041 return ret;
7c9017e5 11042
ffe74d75
CW		 11043 /* Unmask the flip-done completion message. Note that the bspec says that
11044 * we should do this for both the BCS and RCS, and that we must not unmask
11045 * more than one flip event at any time (or ensure that one flip message
11046 * can be sent by waiting for flip-done prior to queueing new flips).
11047 * Experimentation says that BCS works despite DERRMR masking all
11048 * flip-done completion events and that unmasking all planes at once
11049 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11050 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11051 */
11052 if (ring->id == RCS) {
11053 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11054 intel_ring_emit(ring, DERRMR);
11055 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11056 DERRMR_PIPEB_PRI_FLIP_DONE |
11057 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11058 if (IS_GEN8(dev))
11059 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11060 MI_SRM_LRM_GLOBAL_GTT);
11061 else
11062 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11063 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11064 intel_ring_emit(ring, DERRMR);
11065 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11066 if (IS_GEN8(dev)) {
11067 intel_ring_emit(ring, 0);
11068 intel_ring_emit(ring, MI_NOOP);
11069 }
ffe74d75
CW		 11070 }
11071
cb05d8de 11072 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11073 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11074 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11075 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11076
11077 intel_mark_page_flip_active(intel_crtc);
83d4092b 11078 return 0;
7c9017e5
JB		 11079}
11080
84c33a64
SG		 11081static bool use_mmio_flip(struct intel_engine_cs *ring,
11082 struct drm_i915_gem_object *obj)
11083{
11084 /*
11085 * This is not being used for older platforms, because
11086 * non-availability of flip done interrupt forces us to use
11087 * CS flips. Older platforms derive flip done using some clever
11088 * tricks involving the flip_pending status bits and vblank irqs.
11089 * So using MMIO flips there would disrupt this mechanism.
11090 */
11091
8e09bf83
CW		 11092 if (ring == NULL)
11093 return true;
11094
84c33a64
SG		 11095 if (INTEL_INFO(ring->dev)->gen < 5)
11096 return false;
11097
11098 if (i915.use_mmio_flip < 0)
11099 return false;
11100 else if (i915.use_mmio_flip > 0)
11101 return true;
14bf993e
OM		 11102 else if (i915.enable_execlists)
11103 return true;
84c33a64 11104 else
b4716185 11105 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11106}
11107
ff944564
DL		 11108static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11109{
11110 struct drm_device *dev = intel_crtc->base.dev;
11111 struct drm_i915_private *dev_priv = dev->dev_private;
11112 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11113 const enum pipe pipe = intel_crtc->pipe;
11114 u32 ctl, stride;
11115
11116 ctl = I915_READ(PLANE_CTL(pipe, 0));
11117 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11118 switch (fb->modifier[0]) {
11119 case DRM_FORMAT_MOD_NONE:
11120 break;
11121 case I915_FORMAT_MOD_X_TILED:
ff944564 11122 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11123 break;
11124 case I915_FORMAT_MOD_Y_TILED:
11125 ctl |= PLANE_CTL_TILED_Y;
11126 break;
11127 case I915_FORMAT_MOD_Yf_TILED:
11128 ctl |= PLANE_CTL_TILED_YF;
11129 break;
11130 default:
11131 MISSING_CASE(fb->modifier[0]);
11132 }
ff944564
DL		 11133
11134 /*
11135 * The stride is either expressed as a multiple of 64 bytes chunks for
11136 * linear buffers or in number of tiles for tiled buffers.
11137 */
2ebef630
TU		 11138 stride = fb->pitches[0] /
11139 intel_fb_stride_alignment(dev, fb->modifier[0],
11140 fb->pixel_format);
ff944564
DL		 11141
11142 /*
11143 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11144 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11145 */
11146 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11147 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11148
11149 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11150 POSTING_READ(PLANE_SURF(pipe, 0));
11151}
11152
11153static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11154{
11155 struct drm_device *dev = intel_crtc->base.dev;
11156 struct drm_i915_private *dev_priv = dev->dev_private;
11157 struct intel_framebuffer *intel_fb =
11158 to_intel_framebuffer(intel_crtc->base.primary->fb);
11159 struct drm_i915_gem_object *obj = intel_fb->obj;
11160 u32 dspcntr;
11161 u32 reg;
11162
84c33a64
SG		 11163 reg = DSPCNTR(intel_crtc->plane);
11164 dspcntr = I915_READ(reg);
11165
c5d97472
DL		 11166 if (obj->tiling_mode != I915_TILING_NONE)
11167 dspcntr |= DISPPLANE_TILED;
11168 else
11169 dspcntr &= ~DISPPLANE_TILED;
11170
84c33a64
SG		 11171 I915_WRITE(reg, dspcntr);
11172
11173 I915_WRITE(DSPSURF(intel_crtc->plane),
11174 intel_crtc->unpin_work->gtt_offset);
11175 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11176
ff944564
DL		 11177}
11178
11179/*
11180 * XXX: This is the temporary way to update the plane registers until we get
11181 * around to using the usual plane update functions for MMIO flips
11182 */
11183static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11184{
11185 struct drm_device *dev = intel_crtc->base.dev;
11186 bool atomic_update;
11187 u32 start_vbl_count;
11188
11189 intel_mark_page_flip_active(intel_crtc);
11190
11191 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11192
11193 if (INTEL_INFO(dev)->gen >= 9)
11194 skl_do_mmio_flip(intel_crtc);
11195 else
11196 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11197 ilk_do_mmio_flip(intel_crtc);
11198
9362c7c5
ACO		 11199 if (atomic_update)
11200 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11201}
11202
9362c7c5 11203static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11204{
b2cfe0ab
CW		 11205 struct intel_mmio_flip *mmio_flip =
11206 container_of(work, struct intel_mmio_flip, work);
84c33a64 11207
eed29a5b
DV		 11208 if (mmio_flip->req)
11209 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11210 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11211 false, NULL,
11212 &mmio_flip->i915->rps.mmioflips));
84c33a64 11213
b2cfe0ab
CW		 11214 intel_do_mmio_flip(mmio_flip->crtc);
11215
eed29a5b 11216 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11217 kfree(mmio_flip);
84c33a64
SG		 11218}
11219
11220static int intel_queue_mmio_flip(struct drm_device *dev,
11221 struct drm_crtc *crtc,
11222 struct drm_framebuffer *fb,
11223 struct drm_i915_gem_object *obj,
11224 struct intel_engine_cs *ring,
11225 uint32_t flags)
11226{
b2cfe0ab
CW		 11227 struct intel_mmio_flip *mmio_flip;
11228
11229 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11230 if (mmio_flip == NULL)
11231 return -ENOMEM;
84c33a64 11232
bcafc4e3 11233 mmio_flip->i915 = to_i915(dev);
eed29a5b 11234 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11235 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11236
b2cfe0ab
CW		 11237 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11238 schedule_work(&mmio_flip->work);
84c33a64 11239
84c33a64
SG		 11240 return 0;
11241}
11242
8c9f3aaf
JB		 11243static int intel_default_queue_flip(struct drm_device *dev,
11244 struct drm_crtc *crtc,
11245 struct drm_framebuffer *fb,
ed8d1975 11246 struct drm_i915_gem_object *obj,
6258fbe2 11247 struct drm_i915_gem_request *req,
ed8d1975 11248 uint32_t flags)
8c9f3aaf
JB		 11249{
11250 return -ENODEV;
11251}
11252
d6bbafa1
CW		 11253static bool __intel_pageflip_stall_check(struct drm_device *dev,
11254 struct drm_crtc *crtc)
11255{
11256 struct drm_i915_private *dev_priv = dev->dev_private;
11257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11258 struct intel_unpin_work *work = intel_crtc->unpin_work;
11259 u32 addr;
11260
11261 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11262 return true;
11263
11264 if (!work->enable_stall_check)
11265 return false;
11266
11267 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11268 if (work->flip_queued_req &&
11269 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11270 return false;
11271
1e3feefd 11272 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11273 }
11274
1e3feefd 11275 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11276 return false;
11277
11278 /* Potential stall - if we see that the flip has happened,
11279 * assume a missed interrupt. */
11280 if (INTEL_INFO(dev)->gen >= 4)
11281 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11282 else
11283 addr = I915_READ(DSPADDR(intel_crtc->plane));
11284
11285 /* There is a potential issue here with a false positive after a flip
11286 * to the same address. We could address this by checking for a
11287 * non-incrementing frame counter.
11288 */
11289 return addr == work->gtt_offset;
11290}
11291
11292void intel_check_page_flip(struct drm_device *dev, int pipe)
11293{
11294 struct drm_i915_private *dev_priv = dev->dev_private;
11295 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11297 struct intel_unpin_work *work;
f326038a 11298
6c51d46f 11299 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11300
11301 if (crtc == NULL)
11302 return;
11303
f326038a 11304 spin_lock(&dev->event_lock);
6ad790c0
CW		 11305 work = intel_crtc->unpin_work;
11306 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11307 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11308 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11309 page_flip_completed(intel_crtc);
6ad790c0 11310 work = NULL;
d6bbafa1 11311 }
6ad790c0
CW		 11312 if (work != NULL &&
11313 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11314 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11315 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11316}
11317
6b95a207
KH		 11318static int intel_crtc_page_flip(struct drm_crtc *crtc,
11319 struct drm_framebuffer *fb,
ed8d1975
KP		 11320 struct drm_pending_vblank_event *event,
11321 uint32_t page_flip_flags)
6b95a207
KH		 11322{
11323 struct drm_device *dev = crtc->dev;
11324 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11325 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11326 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11328 struct drm_plane *primary = crtc->primary;
a071fa00 11329 enum pipe pipe = intel_crtc->pipe;
6b95a207 11330 struct intel_unpin_work *work;
a4872ba6 11331 struct intel_engine_cs *ring;
cf5d8a46 11332 bool mmio_flip;
91af127f 11333 struct drm_i915_gem_request *request = NULL;
52e68630 11334 int ret;
6b95a207 11335
2ff8fde1
MR		 11336 /*
11337 * drm_mode_page_flip_ioctl() should already catch this, but double
11338 * check to be safe. In the future we may enable pageflipping from
11339 * a disabled primary plane.
11340 */
11341 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11342 return -EBUSY;
11343
e6a595d2 11344 /* Can't change pixel format via MI display flips. */
f4510a27 11345 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11346 return -EINVAL;
11347
11348 /*
11349 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11350 * Note that pitch changes could also affect these register.
11351 */
11352 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11353 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11354 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11355 return -EINVAL;
11356
f900db47
CW		 11357 if (i915_terminally_wedged(&dev_priv->gpu_error))
11358 goto out_hang;
11359
b14c5679 11360 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11361 if (work == NULL)
11362 return -ENOMEM;
11363
6b95a207 11364 work->event = event;
b4a98e57 11365 work->crtc = crtc;
ab8d6675 11366 work->old_fb = old_fb;
6b95a207
KH		 11367 INIT_WORK(&work->work, intel_unpin_work_fn);
11368
87b6b101 11369 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11370 if (ret)
11371 goto free_work;
11372
6b95a207 11373 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11374 spin_lock_irq(&dev->event_lock);
6b95a207 11375 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11376 /* Before declaring the flip queue wedged, check if
11377 * the hardware completed the operation behind our backs.
11378 */
11379 if (__intel_pageflip_stall_check(dev, crtc)) {
11380 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11381 page_flip_completed(intel_crtc);
11382 } else {
11383 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11384 spin_unlock_irq(&dev->event_lock);
468f0b44 11385
d6bbafa1
CW		 11386 drm_crtc_vblank_put(crtc);
11387 kfree(work);
11388 return -EBUSY;
11389 }
6b95a207
KH		 11390 }
11391 intel_crtc->unpin_work = work;
5e2d7afc 11392 spin_unlock_irq(&dev->event_lock);
6b95a207 11393
b4a98e57
CW		 11394 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11395 flush_workqueue(dev_priv->wq);
11396
75dfca80 11397 /* Reference the objects for the scheduled work. */
ab8d6675 11398 drm_framebuffer_reference(work->old_fb);
05394f39 11399 drm_gem_object_reference(&obj->base);
6b95a207 11400
f4510a27 11401 crtc->primary->fb = fb;
afd65eb4 11402 update_state_fb(crtc->primary);
1ed1f968 11403
e1f99ce6 11404 work->pending_flip_obj = obj;
e1f99ce6 11405
89ed88ba
CW		 11406 ret = i915_mutex_lock_interruptible(dev);
11407 if (ret)
11408 goto cleanup;
11409
b4a98e57 11410 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11411 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11412
75f7f3ec 11413 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11414 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11415
4fa62c89
VS		 11416 if (IS_VALLEYVIEW(dev)) {
11417 ring = &dev_priv->ring[BCS];
ab8d6675 11418 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11419 /* vlv: DISPLAY_FLIP fails to change tiling */
11420 ring = NULL;
48bf5b2d 11421 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11422 ring = &dev_priv->ring[BCS];
4fa62c89 11423 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11424 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11425 if (ring == NULL || ring->id != RCS)
11426 ring = &dev_priv->ring[BCS];
11427 } else {
11428 ring = &dev_priv->ring[RCS];
11429 }
11430
cf5d8a46
CW		 11431 mmio_flip = use_mmio_flip(ring, obj);
11432
11433 /* When using CS flips, we want to emit semaphores between rings.
11434 * However, when using mmio flips we will create a task to do the
11435 * synchronisation, so all we want here is to pin the framebuffer
11436 * into the display plane and skip any waits.
11437 */
82bc3b2d 11438 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11439 crtc->primary->state,
91af127f 11440 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11441 if (ret)
11442 goto cleanup_pending;
6b95a207 11443
121920fa
TU		 11444 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11445 + intel_crtc->dspaddr_offset;
4fa62c89 11446
cf5d8a46 11447 if (mmio_flip) {
84c33a64
SG		 11448 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11449 page_flip_flags);
d6bbafa1
CW		 11450 if (ret)
11451 goto cleanup_unpin;
11452
f06cc1b9
JH		 11453 i915_gem_request_assign(&work->flip_queued_req,
11454 obj->last_write_req);
d6bbafa1 11455 } else {
6258fbe2
JH		 11456 if (!request) {
11457 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11458 if (ret)
11459 goto cleanup_unpin;
11460 }
11461
11462 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11463 page_flip_flags);
11464 if (ret)
11465 goto cleanup_unpin;
11466
6258fbe2 11467 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11468 }
11469
91af127f 11470 if (request)
75289874 11471 i915_add_request_no_flush(request);
91af127f 11472
1e3feefd 11473 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11474 work->enable_stall_check = true;
4fa62c89 11475
ab8d6675 11476 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11477 to_intel_plane(primary)->frontbuffer_bit);
a071fa00 11478
7ff0ebcc 11479 intel_fbc_disable(dev);
a9ff8714
VS		 11480 intel_frontbuffer_flip_prepare(dev,
11481 to_intel_plane(primary)->frontbuffer_bit);
6b95a207
KH		 11482 mutex_unlock(&dev->struct_mutex);
11483
e5510fac
JB		 11484 trace_i915_flip_request(intel_crtc->plane, obj);
11485
6b95a207 11486 return 0;
96b099fd 11487
4fa62c89 11488cleanup_unpin:
82bc3b2d 11489 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11490cleanup_pending:
91af127f
JH		 11491 if (request)
11492 i915_gem_request_cancel(request);
b4a98e57 11493 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11494 mutex_unlock(&dev->struct_mutex);
11495cleanup:
f4510a27 11496 crtc->primary->fb = old_fb;
afd65eb4 11497 update_state_fb(crtc->primary);
89ed88ba
CW		 11498
11499 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11500 drm_framebuffer_unreference(work->old_fb);
96b099fd 11501
5e2d7afc 11502 spin_lock_irq(&dev->event_lock);
96b099fd 11503 intel_crtc->unpin_work = NULL;
5e2d7afc 11504 spin_unlock_irq(&dev->event_lock);
96b099fd 11505
87b6b101 11506 drm_crtc_vblank_put(crtc);
7317c75e 11507free_work:
96b099fd
CW		 11508 kfree(work);
11509
f900db47 11510 if (ret == -EIO) {
02e0efb5
ML		 11511 struct drm_atomic_state *state;
11512 struct drm_plane_state *plane_state;
11513
f900db47 11514out_hang:
02e0efb5
ML		 11515 state = drm_atomic_state_alloc(dev);
11516 if (!state)
11517 return -ENOMEM;
11518 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11519
11520retry:
11521 plane_state = drm_atomic_get_plane_state(state, primary);
11522 ret = PTR_ERR_OR_ZERO(plane_state);
11523 if (!ret) {
11524 drm_atomic_set_fb_for_plane(plane_state, fb);
11525
11526 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11527 if (!ret)
11528 ret = drm_atomic_commit(state);
11529 }
11530
11531 if (ret == -EDEADLK) {
11532 drm_modeset_backoff(state->acquire_ctx);
11533 drm_atomic_state_clear(state);
11534 goto retry;
11535 }
11536
11537 if (ret)
11538 drm_atomic_state_free(state);
11539
f0d3dad3 11540 if (ret == 0 && event) {
5e2d7afc 11541 spin_lock_irq(&dev->event_lock);
a071fa00 11542 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11543 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11544 }
f900db47 11545 }
96b099fd 11546 return ret;
6b95a207
KH		 11547}
11548
da20eabd
ML		 11549
11550/**
11551 * intel_wm_need_update - Check whether watermarks need updating
11552 * @plane: drm plane
11553 * @state: new plane state
11554 *
11555 * Check current plane state versus the new one to determine whether
11556 * watermarks need to be recalculated.
11557 *
11558 * Returns true or false.
11559 */
11560static bool intel_wm_need_update(struct drm_plane *plane,
11561 struct drm_plane_state *state)
11562{
11563 /* Update watermarks on tiling changes. */
11564 if (!plane->state->fb || !state->fb ||
11565 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11566 plane->state->rotation != state->rotation)
11567 return true;
11568
11569 if (plane->state->crtc_w != state->crtc_w)
11570 return true;
11571
11572 return false;
11573}
11574
11575int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11576 struct drm_plane_state *plane_state)
11577{
11578 struct drm_crtc *crtc = crtc_state->crtc;
11579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11580 struct drm_plane *plane = plane_state->plane;
11581 struct drm_device *dev = crtc->dev;
11582 struct drm_i915_private *dev_priv = dev->dev_private;
11583 struct intel_plane_state *old_plane_state =
11584 to_intel_plane_state(plane->state);
11585 int idx = intel_crtc->base.base.id, ret;
11586 int i = drm_plane_index(plane);
11587 bool mode_changed = needs_modeset(crtc_state);
11588 bool was_crtc_enabled = crtc->state->active;
11589 bool is_crtc_enabled = crtc_state->active;
11590
11591 bool turn_off, turn_on, visible, was_visible;
11592 struct drm_framebuffer *fb = plane_state->fb;
11593
11594 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11595 plane->type != DRM_PLANE_TYPE_CURSOR) {
11596 ret = skl_update_scaler_plane(
11597 to_intel_crtc_state(crtc_state),
11598 to_intel_plane_state(plane_state));
11599 if (ret)
11600 return ret;
11601 }
11602
11603 /*
11604 * Disabling a plane is always okay; we just need to update
11605 * fb tracking in a special way since cleanup_fb() won't
11606 * get called by the plane helpers.
11607 */
11608 if (old_plane_state->base.fb && !fb)
11609 intel_crtc->atomic.disabled_planes |= 1 << i;
11610
da20eabd
ML		 11611 was_visible = old_plane_state->visible;
11612 visible = to_intel_plane_state(plane_state)->visible;
11613
11614 if (!was_crtc_enabled && WARN_ON(was_visible))
11615 was_visible = false;
11616
11617 if (!is_crtc_enabled && WARN_ON(visible))
11618 visible = false;
11619
11620 if (!was_visible && !visible)
11621 return 0;
11622
11623 turn_off = was_visible && (!visible || mode_changed);
11624 turn_on = visible && (!was_visible || mode_changed);
11625
11626 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11627 plane->base.id, fb ? fb->base.id : -1);
11628
11629 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11630 plane->base.id, was_visible, visible,
11631 turn_off, turn_on, mode_changed);
11632
852eb00d 11633 if (turn_on) {
f015c551 11634 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11635 /* must disable cxsr around plane enable/disable */
11636 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11637 intel_crtc->atomic.disable_cxsr = true;
11638 /* to potentially re-enable cxsr */
11639 intel_crtc->atomic.wait_vblank = true;
11640 intel_crtc->atomic.update_wm_post = true;
11641 }
11642 } else if (turn_off) {
f015c551 11643 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11644 /* must disable cxsr around plane enable/disable */
11645 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11646 if (is_crtc_enabled)
11647 intel_crtc->atomic.wait_vblank = true;
11648 intel_crtc->atomic.disable_cxsr = true;
11649 }
11650 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11651 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11652 }
da20eabd 11653
a9ff8714
VS		 11654 if (visible)
11655 intel_crtc->atomic.fb_bits |=
11656 to_intel_plane(plane)->frontbuffer_bit;
11657
da20eabd
ML		 11658 switch (plane->type) {
11659 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11660 intel_crtc->atomic.wait_for_flips = true;
11661 intel_crtc->atomic.pre_disable_primary = turn_off;
11662 intel_crtc->atomic.post_enable_primary = turn_on;
11663
066cf55b
RV		 11664 if (turn_off) {
11665 /*
11666 * FIXME: Actually if we will still have any other
11667 * plane enabled on the pipe we could let IPS enabled
11668 * still, but for now lets consider that when we make
11669 * primary invisible by setting DSPCNTR to 0 on
11670 * update_primary_plane function IPS needs to be
11671 * disable.
11672 */
11673 intel_crtc->atomic.disable_ips = true;
11674
da20eabd 11675 intel_crtc->atomic.disable_fbc = true;
066cf55b 11676 }
da20eabd
ML		 11677
11678 /*
11679 * FBC does not work on some platforms for rotated
11680 * planes, so disable it when rotation is not 0 and
11681 * update it when rotation is set back to 0.
11682 *
11683 * FIXME: This is redundant with the fbc update done in
11684 * the primary plane enable function except that that
11685 * one is done too late. We eventually need to unify
11686 * this.
11687 */
11688
11689 if (visible &&
11690 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11691 dev_priv->fbc.crtc == intel_crtc &&
11692 plane_state->rotation != BIT(DRM_ROTATE_0))
11693 intel_crtc->atomic.disable_fbc = true;
11694
11695 /*
11696 * BDW signals flip done immediately if the plane
11697 * is disabled, even if the plane enable is already
11698 * armed to occur at the next vblank :(
11699 */
11700 if (turn_on && IS_BROADWELL(dev))
11701 intel_crtc->atomic.wait_vblank = true;
11702
11703 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11704 break;
11705 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11706 break;
11707 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11708 if (turn_off && !mode_changed) {
da20eabd
ML		 11709 intel_crtc->atomic.wait_vblank = true;
11710 intel_crtc->atomic.update_sprite_watermarks |=
11711 1 << i;
11712 }
da20eabd
ML		 11713 }
11714 return 0;
11715}
11716
6d3a1ce7
ML		 11717static bool encoders_cloneable(const struct intel_encoder *a,
11718 const struct intel_encoder *b)
11719{
11720 /* masks could be asymmetric, so check both ways */
11721 return a == b || (a->cloneable & (1 << b->type) &&
11722 b->cloneable & (1 << a->type));
11723}
11724
11725static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11726 struct intel_crtc *crtc,
11727 struct intel_encoder *encoder)
11728{
11729 struct intel_encoder *source_encoder;
11730 struct drm_connector *connector;
11731 struct drm_connector_state *connector_state;
11732 int i;
11733
11734 for_each_connector_in_state(state, connector, connector_state, i) {
11735 if (connector_state->crtc != &crtc->base)
11736 continue;
11737
11738 source_encoder =
11739 to_intel_encoder(connector_state->best_encoder);
11740 if (!encoders_cloneable(encoder, source_encoder))
11741 return false;
11742 }
11743
11744 return true;
11745}
11746
11747static bool check_encoder_cloning(struct drm_atomic_state *state,
11748 struct intel_crtc *crtc)
11749{
11750 struct intel_encoder *encoder;
11751 struct drm_connector *connector;
11752 struct drm_connector_state *connector_state;
11753 int i;
11754
11755 for_each_connector_in_state(state, connector, connector_state, i) {
11756 if (connector_state->crtc != &crtc->base)
11757 continue;
11758
11759 encoder = to_intel_encoder(connector_state->best_encoder);
11760 if (!check_single_encoder_cloning(state, crtc, encoder))
11761 return false;
11762 }
11763
11764 return true;
11765}
11766
d032ffa0
ML		 11767static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11768 struct drm_crtc_state *crtc_state)
11769{
11770 struct intel_crtc_state *pipe_config =
11771 to_intel_crtc_state(crtc_state);
11772 struct drm_plane *p;
11773 unsigned visible_mask = 0;
11774
11775 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11776 struct drm_plane_state *plane_state =
11777 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11778
11779 if (WARN_ON(!plane_state))
11780 continue;
11781
11782 if (!plane_state->fb)
11783 crtc_state->plane_mask &=
11784 ~(1 << drm_plane_index(p));
11785 else if (to_intel_plane_state(plane_state)->visible)
11786 visible_mask |= 1 << drm_plane_index(p);
11787 }
11788
11789 if (!visible_mask)
11790 return;
11791
11792 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11793}
11794
6d3a1ce7
ML		 11795static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11796 struct drm_crtc_state *crtc_state)
11797{
cf5a15be 11798 struct drm_device *dev = crtc->dev;
ad421372 11799 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11801 struct intel_crtc_state *pipe_config =
11802 to_intel_crtc_state(crtc_state);
6d3a1ce7 11803 struct drm_atomic_state *state = crtc_state->state;
ad421372 11804 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11805 bool mode_changed = needs_modeset(crtc_state);
11806
11807 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11808 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11809 return -EINVAL;
11810 }
11811
11812 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11813 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11814 idx, crtc->state->active, intel_crtc->active);
11815
d032ffa0
ML		 11816 /* plane mask is fixed up after all initial planes are calculated */
11817 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11818 intel_crtc_check_initial_planes(crtc, crtc_state);
11819
852eb00d
VS		 11820 if (mode_changed && !crtc_state->active)
11821 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11822
ad421372
ML		 11823 if (mode_changed && crtc_state->enable &&
11824 dev_priv->display.crtc_compute_clock &&
11825 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11826 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11827 pipe_config);
11828 if (ret)
11829 return ret;
11830 }
11831
cf5a15be 11832 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
6d3a1ce7
ML		 11833}
11834
65b38e0d 11835static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11836 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11837 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11838 .atomic_begin = intel_begin_crtc_commit,
11839 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11840 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11841};
11842
9a935856
DV		 11843/**
11844 * intel_modeset_update_staged_output_state
11845 *
11846 * Updates the staged output configuration state, e.g. after we've read out the
11847 * current hw state.
11848 */
11849static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11850{
7668851f 11851 struct intel_crtc *crtc;
9a935856
DV		 11852 struct intel_encoder *encoder;
11853 struct intel_connector *connector;
f6e5b160 11854
3a3371ff 11855 for_each_intel_connector(dev, connector) {
9a935856
DV		 11856 connector->new_encoder =
11857 to_intel_encoder(connector->base.encoder);
11858 }
f6e5b160 11859
b2784e15 11860 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11861 encoder->new_crtc =
11862 to_intel_crtc(encoder->base.crtc);
11863 }
7668851f 11864
d3fcc808 11865 for_each_intel_crtc(dev, crtc) {
83d65738 11866 crtc->new_enabled = crtc->base.state->enable;
7668851f 11867 }
f6e5b160
CW		 11868}
11869
d29b2f9d
ACO		 11870/* Transitional helper to copy current connector/encoder state to
11871 * connector->state. This is needed so that code that is partially
11872 * converted to atomic does the right thing.
11873 */
11874static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11875{
11876 struct intel_connector *connector;
11877
11878 for_each_intel_connector(dev, connector) {
11879 if (connector->base.encoder) {
11880 connector->base.state->best_encoder =
11881 connector->base.encoder;
11882 connector->base.state->crtc =
11883 connector->base.encoder->crtc;
11884 } else {
11885 connector->base.state->best_encoder = NULL;
11886 connector->base.state->crtc = NULL;
11887 }
11888 }
11889}
11890
050f7aeb 11891static void
eba905b2 11892connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11893 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11894{
11895 int bpp = pipe_config->pipe_bpp;
11896
11897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11898 connector->base.base.id,
c23cc417 11899 connector->base.name);
050f7aeb
DV		 11900
11901 /* Don't use an invalid EDID bpc value */
11902 if (connector->base.display_info.bpc &&
11903 connector->base.display_info.bpc * 3 < bpp) {
11904 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11905 bpp, connector->base.display_info.bpc*3);
11906 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11907 }
11908
11909 /* Clamp bpp to 8 on screens without EDID 1.4 */
11910 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11911 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11912 bpp);
11913 pipe_config->pipe_bpp = 24;
11914 }
11915}
11916
4e53c2e0 11917static int
050f7aeb 11918compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11919 struct intel_crtc_state *pipe_config)
4e53c2e0 11920{
050f7aeb 11921 struct drm_device *dev = crtc->base.dev;
1486017f 11922 struct drm_atomic_state *state;
da3ced29
ACO		 11923 struct drm_connector *connector;
11924 struct drm_connector_state *connector_state;
1486017f 11925 int bpp, i;
4e53c2e0 11926
d328c9d7 11927 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11928 bpp = 10*3;
d328c9d7
DV		 11929 else if (INTEL_INFO(dev)->gen >= 5)
11930 bpp = 12*3;
11931 else
11932 bpp = 8*3;
11933
4e53c2e0 11934
4e53c2e0
DV		 11935 pipe_config->pipe_bpp = bpp;
11936
1486017f
ACO		 11937 state = pipe_config->base.state;
11938
4e53c2e0 11939 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11940 for_each_connector_in_state(state, connector, connector_state, i) {
11941 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11942 continue;
11943
da3ced29
ACO		 11944 connected_sink_compute_bpp(to_intel_connector(connector),
11945 pipe_config);
4e53c2e0
DV		 11946 }
11947
11948 return bpp;
11949}
11950
644db711
DV		 11951static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11952{
11953 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11954 "type: 0x%x flags: 0x%x\n",
1342830c 11955 mode->crtc_clock,
644db711
DV		 11956 mode->crtc_hdisplay, mode->crtc_hsync_start,
11957 mode->crtc_hsync_end, mode->crtc_htotal,
11958 mode->crtc_vdisplay, mode->crtc_vsync_start,
11959 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11960}
11961
c0b03411 11962static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11963 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11964 const char *context)
11965{
6a60cd87
CK		 11966 struct drm_device *dev = crtc->base.dev;
11967 struct drm_plane *plane;
11968 struct intel_plane *intel_plane;
11969 struct intel_plane_state *state;
11970 struct drm_framebuffer *fb;
11971
11972 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11973 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11974
11975 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11976 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11977 pipe_config->pipe_bpp, pipe_config->dither);
11978 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11979 pipe_config->has_pch_encoder,
11980 pipe_config->fdi_lanes,
11981 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11982 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11983 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11984 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11985 pipe_config->has_dp_encoder,
11986 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11987 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11988 pipe_config->dp_m_n.tu);
b95af8be
VK		 11989
11990 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11991 pipe_config->has_dp_encoder,
11992 pipe_config->dp_m2_n2.gmch_m,
11993 pipe_config->dp_m2_n2.gmch_n,
11994 pipe_config->dp_m2_n2.link_m,
11995 pipe_config->dp_m2_n2.link_n,
11996 pipe_config->dp_m2_n2.tu);
11997
55072d19
DV		 11998 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11999 pipe_config->has_audio,
12000 pipe_config->has_infoframe);
12001
c0b03411 12002 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12003 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12004 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12005 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12006 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12007 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12008 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12009 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12010 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12011 crtc->num_scalers,
12012 pipe_config->scaler_state.scaler_users,
12013 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12014 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12015 pipe_config->gmch_pfit.control,
12016 pipe_config->gmch_pfit.pgm_ratios,
12017 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12018 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12019 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12020 pipe_config->pch_pfit.size,
12021 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12022 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12023 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12024
415ff0f6 12025 if (IS_BROXTON(dev)) {
05712c15 12026 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12027 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12028 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12029 pipe_config->ddi_pll_sel,
12030 pipe_config->dpll_hw_state.ebb0,
05712c15 12031 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12032 pipe_config->dpll_hw_state.pll0,
12033 pipe_config->dpll_hw_state.pll1,
12034 pipe_config->dpll_hw_state.pll2,
12035 pipe_config->dpll_hw_state.pll3,
12036 pipe_config->dpll_hw_state.pll6,
12037 pipe_config->dpll_hw_state.pll8,
05712c15 12038 pipe_config->dpll_hw_state.pll9,
c8453338 12039 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12040 pipe_config->dpll_hw_state.pcsdw12);
12041 } else if (IS_SKYLAKE(dev)) {
12042 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12043 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12044 pipe_config->ddi_pll_sel,
12045 pipe_config->dpll_hw_state.ctrl1,
12046 pipe_config->dpll_hw_state.cfgcr1,
12047 pipe_config->dpll_hw_state.cfgcr2);
12048 } else if (HAS_DDI(dev)) {
12049 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12050 pipe_config->ddi_pll_sel,
12051 pipe_config->dpll_hw_state.wrpll);
12052 } else {
12053 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12054 "fp0: 0x%x, fp1: 0x%x\n",
12055 pipe_config->dpll_hw_state.dpll,
12056 pipe_config->dpll_hw_state.dpll_md,
12057 pipe_config->dpll_hw_state.fp0,
12058 pipe_config->dpll_hw_state.fp1);
12059 }
12060
6a60cd87
CK		 12061 DRM_DEBUG_KMS("planes on this crtc\n");
12062 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12063 intel_plane = to_intel_plane(plane);
12064 if (intel_plane->pipe != crtc->pipe)
12065 continue;
12066
12067 state = to_intel_plane_state(plane->state);
12068 fb = state->base.fb;
12069 if (!fb) {
12070 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12071 "disabled, scaler_id = %d\n",
12072 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12073 plane->base.id, intel_plane->pipe,
12074 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12075 drm_plane_index(plane), state->scaler_id);
12076 continue;
12077 }
12078
12079 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12080 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12081 plane->base.id, intel_plane->pipe,
12082 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12083 drm_plane_index(plane));
12084 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12085 fb->base.id, fb->width, fb->height, fb->pixel_format);
12086 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12087 state->scaler_id,
12088 state->src.x1 >> 16, state->src.y1 >> 16,
12089 drm_rect_width(&state->src) >> 16,
12090 drm_rect_height(&state->src) >> 16,
12091 state->dst.x1, state->dst.y1,
12092 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12093 }
c0b03411
DV		 12094}
12095
5448a00d 12096static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12097{
5448a00d
ACO		 12098 struct drm_device *dev = state->dev;
12099 struct intel_encoder *encoder;
da3ced29 12100 struct drm_connector *connector;
5448a00d 12101 struct drm_connector_state *connector_state;
00f0b378 12102 unsigned int used_ports = 0;
5448a00d 12103 int i;
00f0b378
VS		 12104
12105 /*
12106 * Walk the connector list instead of the encoder
12107 * list to detect the problem on ddi platforms
12108 * where there's just one encoder per digital port.
12109 */
da3ced29 12110 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12111 if (!connector_state->best_encoder)
00f0b378
VS		 12112 continue;
12113
5448a00d
ACO		 12114 encoder = to_intel_encoder(connector_state->best_encoder);
12115
12116 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12117
12118 switch (encoder->type) {
12119 unsigned int port_mask;
12120 case INTEL_OUTPUT_UNKNOWN:
12121 if (WARN_ON(!HAS_DDI(dev)))
12122 break;
12123 case INTEL_OUTPUT_DISPLAYPORT:
12124 case INTEL_OUTPUT_HDMI:
12125 case INTEL_OUTPUT_EDP:
12126 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12127
12128 /* the same port mustn't appear more than once */
12129 if (used_ports & port_mask)
12130 return false;
12131
12132 used_ports |= port_mask;
12133 default:
12134 break;
12135 }
12136 }
12137
12138 return true;
12139}
12140
83a57153
ACO		 12141static void
12142clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12143{
12144 struct drm_crtc_state tmp_state;
663a3640 12145 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12146 struct intel_dpll_hw_state dpll_hw_state;
12147 enum intel_dpll_id shared_dpll;
8504c74c 12148 uint32_t ddi_pll_sel;
83a57153 12149
7546a384
ACO		 12150 /* FIXME: before the switch to atomic started, a new pipe_config was
12151 * kzalloc'd. Code that depends on any field being zero should be
12152 * fixed, so that the crtc_state can be safely duplicated. For now,
12153 * only fields that are know to not cause problems are preserved. */
12154
83a57153 12155 tmp_state = crtc_state->base;
663a3640 12156 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12157 shared_dpll = crtc_state->shared_dpll;
12158 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12159 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12160
83a57153 12161 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12162
83a57153 12163 crtc_state->base = tmp_state;
663a3640 12164 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12165 crtc_state->shared_dpll = shared_dpll;
12166 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12167 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12168}
12169
548ee15b 12170static int
b8cecdf5 12171intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12172 struct intel_crtc_state *pipe_config)
ee7b9f93 12173{
b359283a 12174 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12175 struct intel_encoder *encoder;
da3ced29 12176 struct drm_connector *connector;
0b901879 12177 struct drm_connector_state *connector_state;
d328c9d7 12178 int base_bpp, ret = -EINVAL;
0b901879 12179 int i;
e29c22c0 12180 bool retry = true;
ee7b9f93 12181
83a57153 12182 clear_intel_crtc_state(pipe_config);
7758a113 12183
e143a21c
DV		 12184 pipe_config->cpu_transcoder =
12185 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12186
2960bc9c
ID		 12187 /*
12188 * Sanitize sync polarity flags based on requested ones. If neither
12189 * positive or negative polarity is requested, treat this as meaning
12190 * negative polarity.
12191 */
2d112de7 12192 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12193 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12194 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12195
2d112de7 12196 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12197 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12198 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12199
050f7aeb
DV		 12200 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12201 * plane pixel format and any sink constraints into account. Returns the
12202 * source plane bpp so that dithering can be selected on mismatches
12203 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12204 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12205 pipe_config);
12206 if (base_bpp < 0)
4e53c2e0
DV		 12207 goto fail;
12208
e41a56be
VS		 12209 /*
12210 * Determine the real pipe dimensions. Note that stereo modes can
12211 * increase the actual pipe size due to the frame doubling and
12212 * insertion of additional space for blanks between the frame. This
12213 * is stored in the crtc timings. We use the requested mode to do this
12214 * computation to clearly distinguish it from the adjusted mode, which
12215 * can be changed by the connectors in the below retry loop.
12216 */
2d112de7 12217 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12218 &pipe_config->pipe_src_w,
12219 &pipe_config->pipe_src_h);
e41a56be 12220
e29c22c0 12221encoder_retry:
ef1b460d 12222 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12223 pipe_config->port_clock = 0;
ef1b460d 12224 pipe_config->pixel_multiplier = 1;
ff9a6750 12225
135c81b8 12226 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12227 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12228 CRTC_STEREO_DOUBLE);
135c81b8 12229
7758a113
DV		 12230 /* Pass our mode to the connectors and the CRTC to give them a chance to
12231 * adjust it according to limitations or connector properties, and also
12232 * a chance to reject the mode entirely.
47f1c6c9 12233 */
da3ced29 12234 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12235 if (connector_state->crtc != crtc)
7758a113 12236 continue;
7ae89233 12237
0b901879
ACO		 12238 encoder = to_intel_encoder(connector_state->best_encoder);
12239
efea6e8e
DV		 12240 if (!(encoder->compute_config(encoder, pipe_config))) {
12241 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12242 goto fail;
12243 }
ee7b9f93 12244 }
47f1c6c9 12245
ff9a6750
DV		 12246 /* Set default port clock if not overwritten by the encoder. Needs to be
12247 * done afterwards in case the encoder adjusts the mode. */
12248 if (!pipe_config->port_clock)
2d112de7 12249 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12250 * pipe_config->pixel_multiplier;
ff9a6750 12251
a43f6e0f 12252 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12253 if (ret < 0) {
7758a113
DV		 12254 DRM_DEBUG_KMS("CRTC fixup failed\n");
12255 goto fail;
ee7b9f93 12256 }
e29c22c0
DV		 12257
12258 if (ret == RETRY) {
12259 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12260 ret = -EINVAL;
12261 goto fail;
12262 }
12263
12264 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12265 retry = false;
12266 goto encoder_retry;
12267 }
12268
d328c9d7 12269 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12270 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12271 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12272
cdba954e
ACO		 12273 /* Check if we need to force a modeset */
12274 if (pipe_config->has_audio !=
85a96e7a 12275 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12276 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12277 ret = drm_atomic_add_affected_planes(state, crtc);
12278 }
cdba954e
ACO		 12279
12280 /*
12281 * Note we have an issue here with infoframes: current code
12282 * only updates them on the full mode set path per hw
12283 * requirements. So here we should be checking for any
12284 * required changes and forcing a mode set.
12285 */
7758a113 12286fail:
548ee15b 12287 return ret;
ee7b9f93 12288}
47f1c6c9 12289
ea9d758d 12290static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12291{
ea9d758d 12292 struct drm_encoder *encoder;
f6e5b160 12293 struct drm_device *dev = crtc->dev;
f6e5b160 12294
ea9d758d
DV		 12295 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12296 if (encoder->crtc == crtc)
12297 return true;
12298
12299 return false;
12300}
12301
12302static void
0a9ab303 12303intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12304{
0a9ab303 12305 struct drm_device *dev = state->dev;
ea9d758d 12306 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12307 struct drm_crtc *crtc;
12308 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12309 struct drm_connector *connector;
12310
de419ab6 12311 intel_shared_dpll_commit(state);
ba41c0de 12312
b2784e15 12313 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12314 if (!intel_encoder->base.crtc)
12315 continue;
12316
69024de8
ML		 12317 crtc = intel_encoder->base.crtc;
12318 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12319 if (!crtc_state || !needs_modeset(crtc->state))
12320 continue;
ea9d758d 12321
69024de8 12322 intel_encoder->connectors_active = false;
ea9d758d
DV		 12323 }
12324
3cb480bc 12325 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12326 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12327
7668851f 12328 /* Double check state. */
0a9ab303
ACO		 12329 for_each_crtc(dev, crtc) {
12330 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12331
12332 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12333
12334 /* Update hwmode for vblank functions */
12335 if (crtc->state->active)
12336 crtc->hwmode = crtc->state->adjusted_mode;
12337 else
12338 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12339 }
12340
12341 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12342 if (!connector->encoder || !connector->encoder->crtc)
12343 continue;
12344
69024de8
ML		 12345 crtc = connector->encoder->crtc;
12346 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12347 if (!crtc_state || !needs_modeset(crtc->state))
12348 continue;
ea9d758d 12349
53d9f4e9 12350 if (crtc->state->active) {
69024de8
ML		 12351 struct drm_property *dpms_property =
12352 dev->mode_config.dpms_property;
68d34720 12353
69024de8
ML		 12354 connector->dpms = DRM_MODE_DPMS_ON;
12355 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12356
69024de8
ML		 12357 intel_encoder = to_intel_encoder(connector->encoder);
12358 intel_encoder->connectors_active = true;
12359 } else
12360 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12361 }
ea9d758d
DV		 12362}
12363
3bd26263 12364static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12365{
3bd26263 12366 int diff;
f1f644dc
JB		 12367
12368 if (clock1 == clock2)
12369 return true;
12370
12371 if (!clock1 || !clock2)
12372 return false;
12373
12374 diff = abs(clock1 - clock2);
12375
12376 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12377 return true;
12378
12379 return false;
12380}
12381
25c5b266
DV		 12382#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12383 list_for_each_entry((intel_crtc), \
12384 &(dev)->mode_config.crtc_list, \
12385 base.head) \
0973f18f 12386 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12387
0e8ffe1b 12388static bool
2fa2fe9a 12389intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12390 struct intel_crtc_state *current_config,
12391 struct intel_crtc_state *pipe_config)
0e8ffe1b 12392{
66e985c0
DV		 12393#define PIPE_CONF_CHECK_X(name) \
12394 if (current_config->name != pipe_config->name) { \
12395 DRM_ERROR("mismatch in " #name " " \
12396 "(expected 0x%08x, found 0x%08x)\n", \
12397 current_config->name, \
12398 pipe_config->name); \
12399 return false; \
12400 }
12401
08a24034
DV		 12402#define PIPE_CONF_CHECK_I(name) \
12403 if (current_config->name != pipe_config->name) { \
12404 DRM_ERROR("mismatch in " #name " " \
12405 "(expected %i, found %i)\n", \
12406 current_config->name, \
12407 pipe_config->name); \
12408 return false; \
88adfff1
DV		 12409 }
12410
b95af8be
VK		 12411/* This is required for BDW+ where there is only one set of registers for
12412 * switching between high and low RR.
12413 * This macro can be used whenever a comparison has to be made between one
12414 * hw state and multiple sw state variables.
12415 */
12416#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12417 if ((current_config->name != pipe_config->name) && \
12418 (current_config->alt_name != pipe_config->name)) { \
12419 DRM_ERROR("mismatch in " #name " " \
12420 "(expected %i or %i, found %i)\n", \
12421 current_config->name, \
12422 current_config->alt_name, \
12423 pipe_config->name); \
12424 return false; \
12425 }
12426
1bd1bd80
DV		 12427#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12428 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12429 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12430 "(expected %i, found %i)\n", \
12431 current_config->name & (mask), \
12432 pipe_config->name & (mask)); \
12433 return false; \
12434 }
12435
5e550656
VS		 12436#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12437 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12438 DRM_ERROR("mismatch in " #name " " \
12439 "(expected %i, found %i)\n", \
12440 current_config->name, \
12441 pipe_config->name); \
12442 return false; \
12443 }
12444
bb760063
DV		 12445#define PIPE_CONF_QUIRK(quirk) \
12446 ((current_config->quirks | pipe_config->quirks) & (quirk))
12447
eccb140b
DV		 12448 PIPE_CONF_CHECK_I(cpu_transcoder);
12449
08a24034
DV		 12450 PIPE_CONF_CHECK_I(has_pch_encoder);
12451 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12452 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12453 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12454 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12455 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12456 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12457
eb14cb74 12458 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12459
12460 if (INTEL_INFO(dev)->gen < 8) {
12461 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12462 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12463 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12464 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12465 PIPE_CONF_CHECK_I(dp_m_n.tu);
12466
12467 if (current_config->has_drrs) {
12468 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12469 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12470 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12471 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12472 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12473 }
12474 } else {
12475 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12476 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12477 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12478 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12479 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12480 }
eb14cb74 12481
2d112de7
ACO		 12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12488
2d112de7
ACO		 12489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12495
c93f54cf 12496 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12497 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12498 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12499 IS_VALLEYVIEW(dev))
12500 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12501 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12502
9ed109a7
DV		 12503 PIPE_CONF_CHECK_I(has_audio);
12504
2d112de7 12505 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12506 DRM_MODE_FLAG_INTERLACE);
12507
bb760063 12508 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12509 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12510 DRM_MODE_FLAG_PHSYNC);
2d112de7 12511 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12512 DRM_MODE_FLAG_NHSYNC);
2d112de7 12513 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12514 DRM_MODE_FLAG_PVSYNC);
2d112de7 12515 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12516 DRM_MODE_FLAG_NVSYNC);
12517 }
045ac3b5 12518
37327abd
VS		 12519 PIPE_CONF_CHECK_I(pipe_src_w);
12520 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12521
9953599b
DV		 12522 /*
12523 * FIXME: BIOS likes to set up a cloned config with lvds+external
12524 * screen. Since we don't yet re-compute the pipe config when moving
12525 * just the lvds port away to another pipe the sw tracking won't match.
12526 *
12527 * Proper atomic modesets with recomputed global state will fix this.
12528 * Until then just don't check gmch state for inherited modes.
12529 */
12530 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12531 PIPE_CONF_CHECK_I(gmch_pfit.control);
12532 /* pfit ratios are autocomputed by the hw on gen4+ */
12533 if (INTEL_INFO(dev)->gen < 4)
12534 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12535 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12536 }
12537
fd4daa9c
CW		 12538 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12539 if (current_config->pch_pfit.enabled) {
12540 PIPE_CONF_CHECK_I(pch_pfit.pos);
12541 PIPE_CONF_CHECK_I(pch_pfit.size);
12542 }
2fa2fe9a 12543
a1b2278e
CK		 12544 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12545
e59150dc
JB		 12546 /* BDW+ don't expose a synchronous way to read the state */
12547 if (IS_HASWELL(dev))
12548 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12549
282740f7
VS		 12550 PIPE_CONF_CHECK_I(double_wide);
12551
26804afd
DV		 12552 PIPE_CONF_CHECK_X(ddi_pll_sel);
12553
c0d43d62 12554 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12555 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12556 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12557 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12558 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12559 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12560 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12561 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12562 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12563
42571aef
VS		 12564 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12565 PIPE_CONF_CHECK_I(pipe_bpp);
12566
2d112de7 12567 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12568 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12569
66e985c0 12570#undef PIPE_CONF_CHECK_X
08a24034 12571#undef PIPE_CONF_CHECK_I
b95af8be 12572#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12573#undef PIPE_CONF_CHECK_FLAGS
5e550656 12574#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12575#undef PIPE_CONF_QUIRK
88adfff1 12576
0e8ffe1b
DV		 12577 return true;
12578}
12579
08db6652
DL		 12580static void check_wm_state(struct drm_device *dev)
12581{
12582 struct drm_i915_private *dev_priv = dev->dev_private;
12583 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12584 struct intel_crtc *intel_crtc;
12585 int plane;
12586
12587 if (INTEL_INFO(dev)->gen < 9)
12588 return;
12589
12590 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12591 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12592
12593 for_each_intel_crtc(dev, intel_crtc) {
12594 struct skl_ddb_entry *hw_entry, *sw_entry;
12595 const enum pipe pipe = intel_crtc->pipe;
12596
12597 if (!intel_crtc->active)
12598 continue;
12599
12600 /* planes */
dd740780 12601 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12602 hw_entry = &hw_ddb.plane[pipe][plane];
12603 sw_entry = &sw_ddb->plane[pipe][plane];
12604
12605 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12606 continue;
12607
12608 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12609 "(expected (%u,%u), found (%u,%u))\n",
12610 pipe_name(pipe), plane + 1,
12611 sw_entry->start, sw_entry->end,
12612 hw_entry->start, hw_entry->end);
12613 }
12614
12615 /* cursor */
12616 hw_entry = &hw_ddb.cursor[pipe];
12617 sw_entry = &sw_ddb->cursor[pipe];
12618
12619 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12620 continue;
12621
12622 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12623 "(expected (%u,%u), found (%u,%u))\n",
12624 pipe_name(pipe),
12625 sw_entry->start, sw_entry->end,
12626 hw_entry->start, hw_entry->end);
12627 }
12628}
12629
91d1b4bd
DV		 12630static void
12631check_connector_state(struct drm_device *dev)
8af6cf88 12632{
8af6cf88
DV		 12633 struct intel_connector *connector;
12634
3a3371ff 12635 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12636 /* This also checks the encoder/connector hw state with the
12637 * ->get_hw_state callbacks. */
12638 intel_connector_check_state(connector);
12639
e2c719b7 12640 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12641 "connector's staged encoder doesn't match current encoder\n");
12642 }
91d1b4bd
DV		 12643}
12644
12645static void
12646check_encoder_state(struct drm_device *dev)
12647{
12648 struct intel_encoder *encoder;
12649 struct intel_connector *connector;
8af6cf88 12650
b2784e15 12651 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12652 bool enabled = false;
12653 bool active = false;
12654 enum pipe pipe, tracked_pipe;
12655
12656 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12657 encoder->base.base.id,
8e329a03 12658 encoder->base.name);
8af6cf88 12659
e2c719b7 12660 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12661 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12662 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12663 "encoder's active_connectors set, but no crtc\n");
12664
3a3371ff 12665 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12666 if (connector->base.encoder != &encoder->base)
12667 continue;
12668 enabled = true;
12669 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12670 active = true;
12671 }
0e32b39c
DA		 12672 /*
12673 * for MST connectors if we unplug the connector is gone
12674 * away but the encoder is still connected to a crtc
12675 * until a modeset happens in response to the hotplug.
12676 */
12677 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12678 continue;
12679
e2c719b7 12680 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12681 "encoder's enabled state mismatch "
12682 "(expected %i, found %i)\n",
12683 !!encoder->base.crtc, enabled);
e2c719b7 12684 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12685 "active encoder with no crtc\n");
12686
e2c719b7 12687 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12688 "encoder's computed active state doesn't match tracked active state "
12689 "(expected %i, found %i)\n", active, encoder->connectors_active);
12690
12691 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12692 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12693 "encoder's hw state doesn't match sw tracking "
12694 "(expected %i, found %i)\n",
12695 encoder->connectors_active, active);
12696
12697 if (!encoder->base.crtc)
12698 continue;
12699
12700 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12701 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12702 "active encoder's pipe doesn't match"
12703 "(expected %i, found %i)\n",
12704 tracked_pipe, pipe);
12705
12706 }
91d1b4bd
DV		 12707}
12708
12709static void
12710check_crtc_state(struct drm_device *dev)
12711{
fbee40df 12712 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12713 struct intel_crtc *crtc;
12714 struct intel_encoder *encoder;
5cec258b 12715 struct intel_crtc_state pipe_config;
8af6cf88 12716
d3fcc808 12717 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12718 bool enabled = false;
12719 bool active = false;
12720
045ac3b5
JB		 12721 memset(&pipe_config, 0, sizeof(pipe_config));
12722
8af6cf88
DV		 12723 DRM_DEBUG_KMS("[CRTC:%d]\n",
12724 crtc->base.base.id);
12725
83d65738 12726 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12727 "active crtc, but not enabled in sw tracking\n");
12728
b2784e15 12729 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12730 if (encoder->base.crtc != &crtc->base)
12731 continue;
12732 enabled = true;
12733 if (encoder->connectors_active)
12734 active = true;
12735 }
6c49f241 12736
e2c719b7 12737 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12738 "crtc's computed active state doesn't match tracked active state "
12739 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12740 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12741 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12742 "(expected %i, found %i)\n", enabled,
12743 crtc->base.state->enable);
8af6cf88 12744
0e8ffe1b
DV		 12745 active = dev_priv->display.get_pipe_config(crtc,
12746 &pipe_config);
d62cf62a 12747
b6b5d049
VS		 12748 /* hw state is inconsistent with the pipe quirk */
12749 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12750 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12751 active = crtc->active;
12752
b2784e15 12753 for_each_intel_encoder(dev, encoder) {
3eaba51c 12754 enum pipe pipe;
6c49f241
DV		 12755 if (encoder->base.crtc != &crtc->base)
12756 continue;
1d37b689 12757 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12758 encoder->get_config(encoder, &pipe_config);
12759 }
12760
e2c719b7 12761 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12762 "crtc active state doesn't match with hw state "
12763 "(expected %i, found %i)\n", crtc->active, active);
12764
53d9f4e9
ML		 12765 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12766 "transitional active state does not match atomic hw state "
12767 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12768
c0b03411 12769 if (active &&
6e3c9717 12770 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12771 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12772 intel_dump_pipe_config(crtc, &pipe_config,
12773 "[hw state]");
6e3c9717 12774 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12775 "[sw state]");
12776 }
8af6cf88
DV		 12777 }
12778}
12779
91d1b4bd
DV		 12780static void
12781check_shared_dpll_state(struct drm_device *dev)
12782{
fbee40df 12783 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12784 struct intel_crtc *crtc;
12785 struct intel_dpll_hw_state dpll_hw_state;
12786 int i;
5358901f
DV		 12787
12788 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12789 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12790 int enabled_crtcs = 0, active_crtcs = 0;
12791 bool active;
12792
12793 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12794
12795 DRM_DEBUG_KMS("%s\n", pll->name);
12796
12797 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12798
e2c719b7 12799 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12800 "more active pll users than references: %i vs %i\n",
3e369b76 12801 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12802 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12803 "pll in active use but not on in sw tracking\n");
e2c719b7 12804 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12805 "pll in on but not on in use in sw tracking\n");
e2c719b7 12806 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12807 "pll on state mismatch (expected %i, found %i)\n",
12808 pll->on, active);
12809
d3fcc808 12810 for_each_intel_crtc(dev, crtc) {
83d65738 12811 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12812 enabled_crtcs++;
12813 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12814 active_crtcs++;
12815 }
e2c719b7 12816 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12817 "pll active crtcs mismatch (expected %i, found %i)\n",
12818 pll->active, active_crtcs);
e2c719b7 12819 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12820 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12821 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12822
e2c719b7 12823 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12824 sizeof(dpll_hw_state)),
12825 "pll hw state mismatch\n");
5358901f 12826 }
8af6cf88
DV		 12827}
12828
91d1b4bd
DV		 12829void
12830intel_modeset_check_state(struct drm_device *dev)
12831{
08db6652 12832 check_wm_state(dev);
91d1b4bd
DV		 12833 check_connector_state(dev);
12834 check_encoder_state(dev);
12835 check_crtc_state(dev);
12836 check_shared_dpll_state(dev);
12837}
12838
5cec258b 12839void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12840 int dotclock)
12841{
12842 /*
12843 * FDI already provided one idea for the dotclock.
12844 * Yell if the encoder disagrees.
12845 */
2d112de7 12846 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12847 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12848 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12849}
12850
80715b2f
VS		 12851static void update_scanline_offset(struct intel_crtc *crtc)
12852{
12853 struct drm_device *dev = crtc->base.dev;
12854
12855 /*
12856 * The scanline counter increments at the leading edge of hsync.
12857 *
12858 * On most platforms it starts counting from vtotal-1 on the
12859 * first active line. That means the scanline counter value is
12860 * always one less than what we would expect. Ie. just after
12861 * start of vblank, which also occurs at start of hsync (on the
12862 * last active line), the scanline counter will read vblank_start-1.
12863 *
12864 * On gen2 the scanline counter starts counting from 1 instead
12865 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12866 * to keep the value positive), instead of adding one.
12867 *
12868 * On HSW+ the behaviour of the scanline counter depends on the output
12869 * type. For DP ports it behaves like most other platforms, but on HDMI
12870 * there's an extra 1 line difference. So we need to add two instead of
12871 * one to the value.
12872 */
12873 if (IS_GEN2(dev)) {
6e3c9717 12874 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12875 int vtotal;
12876
12877 vtotal = mode->crtc_vtotal;
12878 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12879 vtotal /= 2;
12880
12881 crtc->scanline_offset = vtotal - 1;
12882 } else if (HAS_DDI(dev) &&
409ee761 12883 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12884 crtc->scanline_offset = 2;
12885 } else
12886 crtc->scanline_offset = 1;
12887}
12888
ad421372 12889static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12890{
225da59b 12891 struct drm_device *dev = state->dev;
ed6739ef 12892 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12893 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12894 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12895 struct intel_crtc_state *intel_crtc_state;
12896 struct drm_crtc *crtc;
12897 struct drm_crtc_state *crtc_state;
0a9ab303 12898 int i;
ed6739ef
ACO		 12899
12900 if (!dev_priv->display.crtc_compute_clock)
ad421372 12901 return;
ed6739ef 12902
0a9ab303 12903 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12904 int dpll;
12905
0a9ab303 12906 intel_crtc = to_intel_crtc(crtc);
4978cc93 12907 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12908 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12909
ad421372 12910 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12911 continue;
12912
ad421372 12913 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12914
ad421372
ML		 12915 if (!shared_dpll)
12916 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12917
ad421372
ML		 12918 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12919 }
ed6739ef
ACO		 12920}
12921
99d736a2
ML		 12922/*
12923 * This implements the workaround described in the "notes" section of the mode
12924 * set sequence documentation. When going from no pipes or single pipe to
12925 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12926 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12927 */
12928static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12929{
12930 struct drm_crtc_state *crtc_state;
12931 struct intel_crtc *intel_crtc;
12932 struct drm_crtc *crtc;
12933 struct intel_crtc_state *first_crtc_state = NULL;
12934 struct intel_crtc_state *other_crtc_state = NULL;
12935 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12936 int i;
12937
12938 /* look at all crtc's that are going to be enabled in during modeset */
12939 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12940 intel_crtc = to_intel_crtc(crtc);
12941
12942 if (!crtc_state->active || !needs_modeset(crtc_state))
12943 continue;
12944
12945 if (first_crtc_state) {
12946 other_crtc_state = to_intel_crtc_state(crtc_state);
12947 break;
12948 } else {
12949 first_crtc_state = to_intel_crtc_state(crtc_state);
12950 first_pipe = intel_crtc->pipe;
12951 }
12952 }
12953
12954 /* No workaround needed? */
12955 if (!first_crtc_state)
12956 return 0;
12957
12958 /* w/a possibly needed, check how many crtc's are already enabled. */
12959 for_each_intel_crtc(state->dev, intel_crtc) {
12960 struct intel_crtc_state *pipe_config;
12961
12962 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12963 if (IS_ERR(pipe_config))
12964 return PTR_ERR(pipe_config);
12965
12966 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12967
12968 if (!pipe_config->base.active ||
12969 needs_modeset(&pipe_config->base))
12970 continue;
12971
12972 /* 2 or more enabled crtcs means no need for w/a */
12973 if (enabled_pipe != INVALID_PIPE)
12974 return 0;
12975
12976 enabled_pipe = intel_crtc->pipe;
12977 }
12978
12979 if (enabled_pipe != INVALID_PIPE)
12980 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12981 else if (other_crtc_state)
12982 other_crtc_state->hsw_workaround_pipe = first_pipe;
12983
12984 return 0;
12985}
12986
27c329ed
ML		 12987static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12988{
12989 struct drm_crtc *crtc;
12990 struct drm_crtc_state *crtc_state;
12991 int ret = 0;
12992
12993 /* add all active pipes to the state */
12994 for_each_crtc(state->dev, crtc) {
12995 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12996 if (IS_ERR(crtc_state))
12997 return PTR_ERR(crtc_state);
12998
12999 if (!crtc_state->active || needs_modeset(crtc_state))
13000 continue;
13001
13002 crtc_state->mode_changed = true;
13003
13004 ret = drm_atomic_add_affected_connectors(state, crtc);
13005 if (ret)
13006 break;
13007
13008 ret = drm_atomic_add_affected_planes(state, crtc);
13009 if (ret)
13010 break;
13011 }
13012
13013 return ret;
13014}
13015
13016
054518dd 13017/* Code that should eventually be part of atomic_check() */
c347a676 13018static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13019{
13020 struct drm_device *dev = state->dev;
27c329ed 13021 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13022 int ret;
13023
b359283a
ML		 13024 if (!check_digital_port_conflicts(state)) {
13025 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13026 return -EINVAL;
13027 }
13028
054518dd
ACO		 13029 /*
13030 * See if the config requires any additional preparation, e.g.
13031 * to adjust global state with pipes off. We need to do this
13032 * here so we can get the modeset_pipe updated config for the new
13033 * mode set on this crtc. For other crtcs we need to use the
13034 * adjusted_mode bits in the crtc directly.
13035 */
27c329ed
ML		 13036 if (dev_priv->display.modeset_calc_cdclk) {
13037 unsigned int cdclk;
b432e5cf 13038
27c329ed
ML		 13039 ret = dev_priv->display.modeset_calc_cdclk(state);
13040
13041 cdclk = to_intel_atomic_state(state)->cdclk;
13042 if (!ret && cdclk != dev_priv->cdclk_freq)
13043 ret = intel_modeset_all_pipes(state);
13044
13045 if (ret < 0)
054518dd 13046 return ret;
27c329ed
ML		 13047 } else
13048 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13049
ad421372 13050 intel_modeset_clear_plls(state);
054518dd 13051
99d736a2 13052 if (IS_HASWELL(dev))
ad421372 13053 return haswell_mode_set_planes_workaround(state);
99d736a2 13054
ad421372 13055 return 0;
c347a676
ACO		 13056}
13057
13058static int
13059intel_modeset_compute_config(struct drm_atomic_state *state)
13060{
13061 struct drm_crtc *crtc;
13062 struct drm_crtc_state *crtc_state;
13063 int ret, i;
61333b60 13064 bool any_ms = false;
c347a676
ACO		 13065
13066 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13067 if (ret)
13068 return ret;
13069
c347a676 13070 for_each_crtc_in_state(state, crtc, crtc_state, i) {
61333b60
ML		 13071 if (!crtc_state->enable) {
13072 if (needs_modeset(crtc_state))
13073 any_ms = true;
c347a676 13074 continue;
61333b60 13075 }
c347a676 13076
d032ffa0
ML		 13077 if (to_intel_crtc_state(crtc_state)->quirks &
13078 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13079 ret = drm_atomic_add_affected_planes(state, crtc);
13080 if (ret)
13081 return ret;
13082
13083 /*
13084 * We ought to handle i915.fastboot here.
13085 * If no modeset is required and the primary plane has
13086 * a fb, update the members of crtc_state as needed,
13087 * and run the necessary updates during vblank evasion.
13088 */
13089 }
13090
b359283a
ML		 13091 if (!needs_modeset(crtc_state)) {
13092 ret = drm_atomic_add_affected_connectors(state, crtc);
13093 if (ret)
13094 return ret;
13095 }
13096
13097 ret = intel_modeset_pipe_config(crtc,
13098 to_intel_crtc_state(crtc_state));
c347a676
ACO		 13099 if (ret)
13100 return ret;
13101
61333b60
ML		 13102 if (needs_modeset(crtc_state))
13103 any_ms = true;
13104
c347a676
ACO		 13105 intel_dump_pipe_config(to_intel_crtc(crtc),
13106 to_intel_crtc_state(crtc_state),
13107 "[modeset]");
13108 }
13109
61333b60
ML		 13110 if (any_ms) {
13111 ret = intel_modeset_checks(state);
13112
13113 if (ret)
13114 return ret;
27c329ed
ML		 13115 } else
13116 to_intel_atomic_state(state)->cdclk =
13117 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13118
13119 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13120}
13121
c72d969b 13122static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13123{
c72d969b 13124 struct drm_device *dev = state->dev;
fbee40df 13125 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13126 struct drm_crtc *crtc;
13127 struct drm_crtc_state *crtc_state;
c0c36b94 13128 int ret = 0;
0a9ab303 13129 int i;
61333b60 13130 bool any_ms = false;
a6778b3c 13131
d4afb8cc
ACO		 13132 ret = drm_atomic_helper_prepare_planes(dev, state);
13133 if (ret)
13134 return ret;
13135
1c5e19f8
ML		 13136 drm_atomic_helper_swap_state(dev, state);
13137
0a9ab303 13138 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13140
61333b60
ML		 13141 if (!needs_modeset(crtc->state))
13142 continue;
13143
852eb00d
VS		 13144 intel_pre_plane_update(intel_crtc);
13145
61333b60 13146 any_ms = true;
a539205a 13147 intel_pre_plane_update(intel_crtc);
460da916 13148
a539205a
ML		 13149 if (crtc_state->active) {
13150 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13151 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13152 intel_crtc->active = false;
13153 intel_disable_shared_dpll(intel_crtc);
a539205a 13154 }
b8cecdf5 13155 }
7758a113 13156
ea9d758d
DV		 13157 /* Only after disabling all output pipelines that will be changed can we
13158 * update the the output configuration. */
0a9ab303 13159 intel_modeset_update_state(state);
f6e5b160 13160
a821fc46
ACO		 13161 /* The state has been swaped above, so state actually contains the
13162 * old state now. */
61333b60
ML		 13163 if (any_ms)
13164 modeset_update_crtc_power_domains(state);
47fab737 13165
a6778b3c 13166 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13167 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13168 if (needs_modeset(crtc->state) && crtc->state->active) {
13169 update_scanline_offset(to_intel_crtc(crtc));
13170 dev_priv->display.crtc_enable(crtc);
13171 }
80715b2f 13172
a539205a 13173 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13174 }
a6778b3c 13175
a6778b3c 13176 /* FIXME: add subpixel order */
83a57153 13177
d4afb8cc
ACO		 13178 drm_atomic_helper_cleanup_planes(dev, state);
13179
2bfb4627
ACO		 13180 drm_atomic_state_free(state);
13181
9eb45f22 13182 return 0;
f6e5b160
CW		 13183}
13184
568c634a 13185static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13186{
568c634a 13187 struct drm_device *dev = state->dev;
f30da187
DV		 13188 int ret;
13189
568c634a 13190 ret = __intel_set_mode(state);
f30da187 13191 if (ret == 0)
568c634a 13192 intel_modeset_check_state(dev);
f30da187
DV		 13193
13194 return ret;
13195}
13196
568c634a 13197static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13198{
568c634a 13199 int ret;
83a57153 13200
568c634a 13201 ret = intel_modeset_compute_config(state);
83a57153 13202 if (ret)
568c634a 13203 return ret;
7f27126e 13204
568c634a 13205 return intel_set_mode_checked(state);
7f27126e
JB		 13206}
13207
c0c36b94
CW		 13208void intel_crtc_restore_mode(struct drm_crtc *crtc)
13209{
83a57153
ACO		 13210 struct drm_device *dev = crtc->dev;
13211 struct drm_atomic_state *state;
13212 struct intel_encoder *encoder;
13213 struct intel_connector *connector;
13214 struct drm_connector_state *connector_state;
4be07317 13215 struct intel_crtc_state *crtc_state;
2bfb4627 13216 int ret;
83a57153
ACO		 13217
13218 state = drm_atomic_state_alloc(dev);
13219 if (!state) {
13220 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13221 crtc->base.id);
13222 return;
13223 }
13224
13225 state->acquire_ctx = dev->mode_config.acquire_ctx;
13226
13227 /* The force restore path in the HW readout code relies on the staged
13228 * config still keeping the user requested config while the actual
13229 * state has been overwritten by the configuration read from HW. We
13230 * need to copy the staged config to the atomic state, otherwise the
13231 * mode set will just reapply the state the HW is already in. */
13232 for_each_intel_encoder(dev, encoder) {
13233 if (&encoder->new_crtc->base != crtc)
13234 continue;
13235
13236 for_each_intel_connector(dev, connector) {
13237 if (connector->new_encoder != encoder)
13238 continue;
13239
13240 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13241 if (IS_ERR(connector_state)) {
13242 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13243 connector->base.base.id,
13244 connector->base.name,
13245 PTR_ERR(connector_state));
13246 continue;
13247 }
13248
13249 connector_state->crtc = crtc;
13250 connector_state->best_encoder = &encoder->base;
13251 }
13252 }
13253
4ed9fb37
ACO		 13254 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13255 if (IS_ERR(crtc_state)) {
13256 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13257 crtc->base.id, PTR_ERR(crtc_state));
13258 drm_atomic_state_free(state);
13259 return;
13260 }
4be07317 13261
4ed9fb37
ACO		 13262 crtc_state->base.active = crtc_state->base.enable =
13263 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13264
4ed9fb37 13265 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13266
d3a40d1b
ACO		 13267 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13268 crtc->primary->fb, crtc->x, crtc->y);
13269
568c634a 13270 ret = intel_set_mode(state);
2bfb4627
ACO		 13271 if (ret)
13272 drm_atomic_state_free(state);
c0c36b94
CW		 13273}
13274
25c5b266
DV		 13275#undef for_each_intel_crtc_masked
13276
b7885264
ACO		 13277static bool intel_connector_in_mode_set(struct intel_connector *connector,
13278 struct drm_mode_set *set)
13279{
13280 int ro;
13281
13282 for (ro = 0; ro < set->num_connectors; ro++)
13283 if (set->connectors[ro] == &connector->base)
13284 return true;
13285
13286 return false;
13287}
13288
2e431051 13289static int
9a935856
DV		 13290intel_modeset_stage_output_state(struct drm_device *dev,
13291 struct drm_mode_set *set,
944b0c76 13292 struct drm_atomic_state *state)
50f56119 13293{
9a935856 13294 struct intel_connector *connector;
d5432a9d 13295 struct drm_connector *drm_connector;
944b0c76 13296 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13297 struct drm_crtc *crtc;
13298 struct drm_crtc_state *crtc_state;
13299 int i, ret;
50f56119 13300
9abdda74 13301 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13302 * of connectors. For paranoia, double-check this. */
13303 WARN_ON(!set->fb && (set->num_connectors != 0));
13304 WARN_ON(set->fb && (set->num_connectors == 0));
13305
3a3371ff 13306 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13307 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13308
d5432a9d
ACO		 13309 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13310 continue;
13311
13312 connector_state =
13313 drm_atomic_get_connector_state(state, &connector->base);
13314 if (IS_ERR(connector_state))
13315 return PTR_ERR(connector_state);
13316
b7885264
ACO		 13317 if (in_mode_set) {
13318 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13319 connector_state->best_encoder =
13320 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13321 }
13322
d5432a9d 13323 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13324 continue;
13325
9a935856
DV		 13326 /* If we disable the crtc, disable all its connectors. Also, if
13327 * the connector is on the changing crtc but not on the new
13328 * connector list, disable it. */
b7885264 13329 if (!set->fb || !in_mode_set) {
d5432a9d 13330 connector_state->best_encoder = NULL;
9a935856
DV		 13331
13332 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13333 connector->base.base.id,
c23cc417 13334 connector->base.name);
9a935856 13335 }
50f56119 13336 }
9a935856 13337 /* connector->new_encoder is now updated for all connectors. */
50f56119 13338
d5432a9d
ACO		 13339 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13340 connector = to_intel_connector(drm_connector);
13341
13342 if (!connector_state->best_encoder) {
13343 ret = drm_atomic_set_crtc_for_connector(connector_state,
13344 NULL);
13345 if (ret)
13346 return ret;
7668851f 13347
50f56119 13348 continue;
d5432a9d 13349 }
50f56119 13350
d5432a9d
ACO		 13351 if (intel_connector_in_mode_set(connector, set)) {
13352 struct drm_crtc *crtc = connector->base.state->crtc;
13353
13354 /* If this connector was in a previous crtc, add it
13355 * to the state. We might need to disable it. */
13356 if (crtc) {
13357 crtc_state =
13358 drm_atomic_get_crtc_state(state, crtc);
13359 if (IS_ERR(crtc_state))
13360 return PTR_ERR(crtc_state);
13361 }
13362
13363 ret = drm_atomic_set_crtc_for_connector(connector_state,
13364 set->crtc);
13365 if (ret)
13366 return ret;
13367 }
50f56119
DV		 13368
13369 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13370 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13371 connector_state->crtc)) {
5e2b584e 13372 return -EINVAL;
50f56119 13373 }
944b0c76 13374
9a935856
DV		 13375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13376 connector->base.base.id,
c23cc417 13377 connector->base.name,
d5432a9d 13378 connector_state->crtc->base.id);
944b0c76 13379
d5432a9d
ACO		 13380 if (connector_state->best_encoder != &connector->encoder->base)
13381 connector->encoder =
13382 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13383 }
7668851f 13384
d5432a9d 13385 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13386 bool has_connectors;
13387
d5432a9d
ACO		 13388 ret = drm_atomic_add_affected_connectors(state, crtc);
13389 if (ret)
13390 return ret;
4be07317 13391
49d6fa21
ML		 13392 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13393 if (has_connectors != crtc_state->enable)
13394 crtc_state->enable =
13395 crtc_state->active = has_connectors;
7668851f
VS		 13396 }
13397
8c7b5ccb
ACO		 13398 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13399 set->fb, set->x, set->y);
13400 if (ret)
13401 return ret;
13402
13403 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13404 if (IS_ERR(crtc_state))
13405 return PTR_ERR(crtc_state);
13406
ce52299c
MR		 13407 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13408 if (ret)
13409 return ret;
8c7b5ccb
ACO		 13410
13411 if (set->num_connectors)
13412 crtc_state->active = true;
13413
2e431051
DV		 13414 return 0;
13415}
13416
13417static int intel_crtc_set_config(struct drm_mode_set *set)
13418{
13419 struct drm_device *dev;
83a57153 13420 struct drm_atomic_state *state = NULL;
2e431051 13421 int ret;
2e431051 13422
8d3e375e
DV		 13423 BUG_ON(!set);
13424 BUG_ON(!set->crtc);
13425 BUG_ON(!set->crtc->helper_private);
2e431051 13426
7e53f3a4
DV		 13427 /* Enforce sane interface api - has been abused by the fb helper. */
13428 BUG_ON(!set->mode && set->fb);
13429 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13430
2e431051
DV		 13431 if (set->fb) {
13432 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13433 set->crtc->base.id, set->fb->base.id,
13434 (int)set->num_connectors, set->x, set->y);
13435 } else {
13436 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13437 }
13438
13439 dev = set->crtc->dev;
13440
83a57153 13441 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13442 if (!state)
13443 return -ENOMEM;
83a57153
ACO		 13444
13445 state->acquire_ctx = dev->mode_config.acquire_ctx;
13446
462a425a 13447 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13448 if (ret)
7cbf41d6 13449 goto out;
2e431051 13450
568c634a
ACO		 13451 ret = intel_modeset_compute_config(state);
13452 if (ret)
7cbf41d6 13453 goto out;
50f52756 13454
1f9954d0
JB		 13455 intel_update_pipe_size(to_intel_crtc(set->crtc));
13456
568c634a 13457 ret = intel_set_mode_checked(state);
2d05eae1 13458 if (ret) {
bf67dfeb
DV		 13459 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13460 set->crtc->base.id, ret);
2d05eae1 13461 }
50f56119 13462
7cbf41d6 13463out:
2bfb4627
ACO		 13464 if (ret)
13465 drm_atomic_state_free(state);
50f56119
DV		 13466 return ret;
13467}
f6e5b160
CW		 13468
13469static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13470 .gamma_set = intel_crtc_gamma_set,
50f56119 13471 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13472 .destroy = intel_crtc_destroy,
13473 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13474 .atomic_duplicate_state = intel_crtc_duplicate_state,
13475 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13476};
13477
5358901f
DV		 13478static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13479 struct intel_shared_dpll *pll,
13480 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13481{
5358901f 13482 uint32_t val;
ee7b9f93 13483
f458ebbc 13484 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13485 return false;
13486
5358901f 13487 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13488 hw_state->dpll = val;
13489 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13490 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13491
13492 return val & DPLL_VCO_ENABLE;
13493}
13494
15bdd4cf
DV		 13495static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13496 struct intel_shared_dpll *pll)
13497{
3e369b76
ACO		 13498 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13499 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13500}
13501
e7b903d2
DV		 13502static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13503 struct intel_shared_dpll *pll)
13504{
e7b903d2 13505 /* PCH refclock must be enabled first */
89eff4be 13506 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13507
3e369b76 13508 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13509
13510 /* Wait for the clocks to stabilize. */
13511 POSTING_READ(PCH_DPLL(pll->id));
13512 udelay(150);
13513
13514 /* The pixel multiplier can only be updated once the
13515 * DPLL is enabled and the clocks are stable.
13516 *
13517 * So write it again.
13518 */
3e369b76 13519 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13520 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13521 udelay(200);
13522}
13523
13524static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13525 struct intel_shared_dpll *pll)
13526{
13527 struct drm_device *dev = dev_priv->dev;
13528 struct intel_crtc *crtc;
e7b903d2
DV		 13529
13530 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13531 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13532 if (intel_crtc_to_shared_dpll(crtc) == pll)
13533 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13534 }
13535
15bdd4cf
DV		 13536 I915_WRITE(PCH_DPLL(pll->id), 0);
13537 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13538 udelay(200);
13539}
13540
46edb027
DV		 13541static char *ibx_pch_dpll_names[] = {
13542 "PCH DPLL A",
13543 "PCH DPLL B",
13544};
13545
7c74ade1 13546static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13547{
e7b903d2 13548 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13549 int i;
13550
7c74ade1 13551 dev_priv->num_shared_dpll = 2;
ee7b9f93 13552
e72f9fbf 13553 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13554 dev_priv->shared_dplls[i].id = i;
13555 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13556 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13557 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13558 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13559 dev_priv->shared_dplls[i].get_hw_state =
13560 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13561 }
13562}
13563
7c74ade1
DV		 13564static void intel_shared_dpll_init(struct drm_device *dev)
13565{
e7b903d2 13566 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13567
b6283055
VS		 13568 intel_update_cdclk(dev);
13569
9cd86933
DV		 13570 if (HAS_DDI(dev))
13571 intel_ddi_pll_init(dev);
13572 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13573 ibx_pch_dpll_init(dev);
13574 else
13575 dev_priv->num_shared_dpll = 0;
13576
13577 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13578}
13579
6beb8c23
MR		 13580/**
13581 * intel_prepare_plane_fb - Prepare fb for usage on plane
13582 * @plane: drm plane to prepare for
13583 * @fb: framebuffer to prepare for presentation
13584 *
13585 * Prepares a framebuffer for usage on a display plane. Generally this
13586 * involves pinning the underlying object and updating the frontbuffer tracking
13587 * bits. Some older platforms need special physical address handling for
13588 * cursor planes.
13589 *
13590 * Returns 0 on success, negative error code on failure.
13591 */
13592int
13593intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13594 struct drm_framebuffer *fb,
13595 const struct drm_plane_state *new_state)
465c120c
MR		 13596{
13597 struct drm_device *dev = plane->dev;
6beb8c23 13598 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13599 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13600 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13601 int ret = 0;
465c120c 13602
ea2c67bb 13603 if (!obj)
465c120c
MR		 13604 return 0;
13605
6beb8c23 13606 mutex_lock(&dev->struct_mutex);
465c120c 13607
6beb8c23
MR		 13608 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13609 INTEL_INFO(dev)->cursor_needs_physical) {
13610 int align = IS_I830(dev) ? 16 * 1024 : 256;
13611 ret = i915_gem_object_attach_phys(obj, align);
13612 if (ret)
13613 DRM_DEBUG_KMS("failed to attach phys object\n");
13614 } else {
91af127f 13615 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13616 }
465c120c 13617
6beb8c23 13618 if (ret == 0)
a9ff8714 13619 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13620
4c34574f 13621 mutex_unlock(&dev->struct_mutex);
465c120c 13622
6beb8c23
MR		 13623 return ret;
13624}
13625
38f3ce3a
MR		 13626/**
13627 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13628 * @plane: drm plane to clean up for
13629 * @fb: old framebuffer that was on plane
13630 *
13631 * Cleans up a framebuffer that has just been removed from a plane.
13632 */
13633void
13634intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13635 struct drm_framebuffer *fb,
13636 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13637{
13638 struct drm_device *dev = plane->dev;
13639 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13640
13641 if (WARN_ON(!obj))
13642 return;
13643
13644 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13645 !INTEL_INFO(dev)->cursor_needs_physical) {
13646 mutex_lock(&dev->struct_mutex);
82bc3b2d 13647 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13648 mutex_unlock(&dev->struct_mutex);
13649 }
465c120c
MR		 13650}
13651
6156a456
CK		 13652int
13653skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13654{
13655 int max_scale;
13656 struct drm_device *dev;
13657 struct drm_i915_private *dev_priv;
13658 int crtc_clock, cdclk;
13659
13660 if (!intel_crtc || !crtc_state)
13661 return DRM_PLANE_HELPER_NO_SCALING;
13662
13663 dev = intel_crtc->base.dev;
13664 dev_priv = dev->dev_private;
13665 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13666 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13667
13668 if (!crtc_clock || !cdclk)
13669 return DRM_PLANE_HELPER_NO_SCALING;
13670
13671 /*
13672 * skl max scale is lower of:
13673 * close to 3 but not 3, -1 is for that purpose
13674 * or
13675 * cdclk/crtc_clock
13676 */
13677 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13678
13679 return max_scale;
13680}
13681
465c120c 13682static int
3c692a41 13683intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13684 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13685 struct intel_plane_state *state)
13686{
2b875c22
MR		 13687 struct drm_crtc *crtc = state->base.crtc;
13688 struct drm_framebuffer *fb = state->base.fb;
6156a456 13689 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13690 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13691 bool can_position = false;
465c120c 13692
061e4b8d
ML		 13693 /* use scaler when colorkey is not required */
13694 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13695 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13696 min_scale = 1;
13697 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13698 can_position = true;
6156a456 13699 }
d8106366 13700
061e4b8d
ML		 13701 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13702 &state->dst, &state->clip,
da20eabd
ML		 13703 min_scale, max_scale,
13704 can_position, true,
13705 &state->visible);
14af293f
GP		 13706}
13707
13708static void
13709intel_commit_primary_plane(struct drm_plane *plane,
13710 struct intel_plane_state *state)
13711{
2b875c22
MR		 13712 struct drm_crtc *crtc = state->base.crtc;
13713 struct drm_framebuffer *fb = state->base.fb;
13714 struct drm_device *dev = plane->dev;
14af293f 13715 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13716 struct intel_crtc *intel_crtc;
14af293f
GP		 13717 struct drm_rect *src = &state->src;
13718
ea2c67bb
MR		 13719 crtc = crtc ? crtc : plane->crtc;
13720 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13721
13722 plane->fb = fb;
9dc806fc
MR		 13723 crtc->x = src->x1 >> 16;
13724 crtc->y = src->y1 >> 16;
ccc759dc 13725
a539205a 13726 if (!crtc->state->active)
302d19ac 13727 return;
465c120c 13728
302d19ac
ML		 13729 if (state->visible)
13730 /* FIXME: kill this fastboot hack */
13731 intel_update_pipe_size(intel_crtc);
13732
13733 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13734}
13735
a8ad0d8e
ML		 13736static void
13737intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13738 struct drm_crtc *crtc)
a8ad0d8e
ML		 13739{
13740 struct drm_device *dev = plane->dev;
13741 struct drm_i915_private *dev_priv = dev->dev_private;
13742
a8ad0d8e
ML		 13743 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13744}
13745
32b7eeec 13746static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13747{
32b7eeec 13748 struct drm_device *dev = crtc->dev;
140fd38d 13749 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13751
a539205a
ML		 13752 if (!needs_modeset(crtc->state))
13753 intel_pre_plane_update(intel_crtc);
3c692a41 13754
f015c551 13755 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13756 intel_update_watermarks(crtc);
3c692a41 13757
32b7eeec 13758 intel_runtime_pm_get(dev_priv);
3c692a41 13759
c34c9ee4 13760 /* Perform vblank evasion around commit operation */
a539205a 13761 if (crtc->state->active)
c34c9ee4
MR		 13762 intel_crtc->atomic.evade =
13763 intel_pipe_update_start(intel_crtc,
13764 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13765
13766 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13767 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13768}
13769
13770static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13771{
13772 struct drm_device *dev = crtc->dev;
13773 struct drm_i915_private *dev_priv = dev->dev_private;
13774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13775
c34c9ee4
MR		 13776 if (intel_crtc->atomic.evade)
13777 intel_pipe_update_end(intel_crtc,
13778 intel_crtc->atomic.start_vbl_count);
3c692a41 13779
140fd38d 13780 intel_runtime_pm_put(dev_priv);
3c692a41 13781
ac21b225 13782 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13783}
13784
cf4c7c12 13785/**
4a3b8769
MR		 13786 * intel_plane_destroy - destroy a plane
13787 * @plane: plane to destroy
cf4c7c12 13788 *
4a3b8769
MR		 13789 * Common destruction function for all types of planes (primary, cursor,
13790 * sprite).
cf4c7c12 13791 */
4a3b8769 13792void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13793{
13794 struct intel_plane *intel_plane = to_intel_plane(plane);
13795 drm_plane_cleanup(plane);
13796 kfree(intel_plane);
13797}
13798
65a3fea0 13799const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13800 .update_plane = drm_atomic_helper_update_plane,
13801 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13802 .destroy = intel_plane_destroy,
c196e1d6 13803 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13804 .atomic_get_property = intel_plane_atomic_get_property,
13805 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13806 .atomic_duplicate_state = intel_plane_duplicate_state,
13807 .atomic_destroy_state = intel_plane_destroy_state,
13808
465c120c
MR		 13809};
13810
13811static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13812 int pipe)
13813{
13814 struct intel_plane *primary;
8e7d688b 13815 struct intel_plane_state *state;
465c120c
MR		 13816 const uint32_t *intel_primary_formats;
13817 int num_formats;
13818
13819 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13820 if (primary == NULL)
13821 return NULL;
13822
8e7d688b
MR		 13823 state = intel_create_plane_state(&primary->base);
13824 if (!state) {
ea2c67bb
MR		 13825 kfree(primary);
13826 return NULL;
13827 }
8e7d688b 13828 primary->base.state = &state->base;
ea2c67bb 13829
465c120c
MR		 13830 primary->can_scale = false;
13831 primary->max_downscale = 1;
6156a456
CK		 13832 if (INTEL_INFO(dev)->gen >= 9) {
13833 primary->can_scale = true;
af99ceda 13834 state->scaler_id = -1;
6156a456 13835 }
465c120c
MR		 13836 primary->pipe = pipe;
13837 primary->plane = pipe;
a9ff8714 13838 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13839 primary->check_plane = intel_check_primary_plane;
13840 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13841 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13842 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13843 primary->plane = !pipe;
13844
6c0fd451
DL		 13845 if (INTEL_INFO(dev)->gen >= 9) {
13846 intel_primary_formats = skl_primary_formats;
13847 num_formats = ARRAY_SIZE(skl_primary_formats);
13848 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13849 intel_primary_formats = i965_primary_formats;
13850 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13851 } else {
13852 intel_primary_formats = i8xx_primary_formats;
13853 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13854 }
13855
13856 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13857 &intel_plane_funcs,
465c120c
MR		 13858 intel_primary_formats, num_formats,
13859 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13860
3b7a5119
SJ		 13861 if (INTEL_INFO(dev)->gen >= 4)
13862 intel_create_rotation_property(dev, primary);
48404c1e 13863
ea2c67bb
MR		 13864 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13865
465c120c
MR		 13866 return &primary->base;
13867}
13868
3b7a5119
SJ		 13869void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13870{
13871 if (!dev->mode_config.rotation_property) {
13872 unsigned long flags = BIT(DRM_ROTATE_0) |
13873 BIT(DRM_ROTATE_180);
13874
13875 if (INTEL_INFO(dev)->gen >= 9)
13876 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13877
13878 dev->mode_config.rotation_property =
13879 drm_mode_create_rotation_property(dev, flags);
13880 }
13881 if (dev->mode_config.rotation_property)
13882 drm_object_attach_property(&plane->base.base,
13883 dev->mode_config.rotation_property,
13884 plane->base.state->rotation);
13885}
13886
3d7d6510 13887static int
852e787c 13888intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13889 struct intel_crtc_state *crtc_state,
852e787c 13890 struct intel_plane_state *state)
3d7d6510 13891{
061e4b8d 13892 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13893 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13894 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13895 unsigned stride;
13896 int ret;
3d7d6510 13897
061e4b8d
ML		 13898 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13899 &state->dst, &state->clip,
3d7d6510
MR		 13900 DRM_PLANE_HELPER_NO_SCALING,
13901 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13902 true, true, &state->visible);
757f9a3e
GP		 13903 if (ret)
13904 return ret;
13905
757f9a3e
GP		 13906 /* if we want to turn off the cursor ignore width and height */
13907 if (!obj)
da20eabd 13908 return 0;
757f9a3e 13909
757f9a3e 13910 /* Check for which cursor types we support */
061e4b8d 13911 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13912 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13913 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13914 return -EINVAL;
13915 }
13916
ea2c67bb
MR		 13917 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13918 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13919 DRM_DEBUG_KMS("buffer is too small\n");
13920 return -ENOMEM;
13921 }
13922
3a656b54 13923 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13924 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13925 return -EINVAL;
32b7eeec
MR		 13926 }
13927
da20eabd 13928 return 0;
852e787c 13929}
3d7d6510 13930
a8ad0d8e
ML		 13931static void
13932intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13933 struct drm_crtc *crtc)
a8ad0d8e 13934{
a8ad0d8e
ML		 13935 intel_crtc_update_cursor(crtc, false);
13936}
13937
f4a2cf29 13938static void
852e787c
GP		 13939intel_commit_cursor_plane(struct drm_plane *plane,
13940 struct intel_plane_state *state)
13941{
2b875c22 13942 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13943 struct drm_device *dev = plane->dev;
13944 struct intel_crtc *intel_crtc;
2b875c22 13945 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13946 uint32_t addr;
852e787c 13947
ea2c67bb
MR		 13948 crtc = crtc ? crtc : plane->crtc;
13949 intel_crtc = to_intel_crtc(crtc);
13950
2b875c22 13951 plane->fb = state->base.fb;
ea2c67bb
MR		 13952 crtc->cursor_x = state->base.crtc_x;
13953 crtc->cursor_y = state->base.crtc_y;
13954
a912f12f
GP		 13955 if (intel_crtc->cursor_bo == obj)
13956 goto update;
4ed91096 13957
f4a2cf29 13958 if (!obj)
a912f12f 13959 addr = 0;
f4a2cf29 13960 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13961 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13962 else
a912f12f 13963 addr = obj->phys_handle->busaddr;
852e787c 13964
a912f12f
GP		 13965 intel_crtc->cursor_addr = addr;
13966 intel_crtc->cursor_bo = obj;
852e787c 13967
302d19ac 13968update:
a539205a 13969 if (crtc->state->active)
a912f12f 13970 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13971}
13972
3d7d6510
MR		 13973static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13974 int pipe)
13975{
13976 struct intel_plane *cursor;
8e7d688b 13977 struct intel_plane_state *state;
3d7d6510
MR		 13978
13979 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13980 if (cursor == NULL)
13981 return NULL;
13982
8e7d688b
MR		 13983 state = intel_create_plane_state(&cursor->base);
13984 if (!state) {
ea2c67bb
MR		 13985 kfree(cursor);
13986 return NULL;
13987 }
8e7d688b 13988 cursor->base.state = &state->base;
ea2c67bb 13989
3d7d6510
MR		 13990 cursor->can_scale = false;
13991 cursor->max_downscale = 1;
13992 cursor->pipe = pipe;
13993 cursor->plane = pipe;
a9ff8714 13994 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13995 cursor->check_plane = intel_check_cursor_plane;
13996 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13997 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13998
13999 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14000 &intel_plane_funcs,
3d7d6510
MR		 14001 intel_cursor_formats,
14002 ARRAY_SIZE(intel_cursor_formats),
14003 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14004
14005 if (INTEL_INFO(dev)->gen >= 4) {
14006 if (!dev->mode_config.rotation_property)
14007 dev->mode_config.rotation_property =
14008 drm_mode_create_rotation_property(dev,
14009 BIT(DRM_ROTATE_0) |
14010 BIT(DRM_ROTATE_180));
14011 if (dev->mode_config.rotation_property)
14012 drm_object_attach_property(&cursor->base.base,
14013 dev->mode_config.rotation_property,
8e7d688b 14014 state->base.rotation);
4398ad45
VS		 14015 }
14016
af99ceda
CK		 14017 if (INTEL_INFO(dev)->gen >=9)
14018 state->scaler_id = -1;
14019
ea2c67bb
MR		 14020 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14021
3d7d6510
MR		 14022 return &cursor->base;
14023}
14024
549e2bfb
CK		 14025static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14026 struct intel_crtc_state *crtc_state)
14027{
14028 int i;
14029 struct intel_scaler *intel_scaler;
14030 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14031
14032 for (i = 0; i < intel_crtc->num_scalers; i++) {
14033 intel_scaler = &scaler_state->scalers[i];
14034 intel_scaler->in_use = 0;
549e2bfb
CK		 14035 intel_scaler->mode = PS_SCALER_MODE_DYN;
14036 }
14037
14038 scaler_state->scaler_id = -1;
14039}
14040
b358d0a6 14041static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14042{
fbee40df 14043 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14044 struct intel_crtc *intel_crtc;
f5de6e07 14045 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14046 struct drm_plane *primary = NULL;
14047 struct drm_plane *cursor = NULL;
465c120c 14048 int i, ret;
79e53945 14049
955382f3 14050 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14051 if (intel_crtc == NULL)
14052 return;
14053
f5de6e07
ACO		 14054 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14055 if (!crtc_state)
14056 goto fail;
550acefd
ACO		 14057 intel_crtc->config = crtc_state;
14058 intel_crtc->base.state = &crtc_state->base;
07878248 14059 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14060
549e2bfb
CK		 14061 /* initialize shared scalers */
14062 if (INTEL_INFO(dev)->gen >= 9) {
14063 if (pipe == PIPE_C)
14064 intel_crtc->num_scalers = 1;
14065 else
14066 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14067
14068 skl_init_scalers(dev, intel_crtc, crtc_state);
14069 }
14070
465c120c 14071 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14072 if (!primary)
14073 goto fail;
14074
14075 cursor = intel_cursor_plane_create(dev, pipe);
14076 if (!cursor)
14077 goto fail;
14078
465c120c 14079 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14080 cursor, &intel_crtc_funcs);
14081 if (ret)
14082 goto fail;
79e53945
JB		 14083
14084 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14085 for (i = 0; i < 256; i++) {
14086 intel_crtc->lut_r[i] = i;
14087 intel_crtc->lut_g[i] = i;
14088 intel_crtc->lut_b[i] = i;
14089 }
14090
1f1c2e24
VS		 14091 /*
14092 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14093 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14094 */
80824003
JB		 14095 intel_crtc->pipe = pipe;
14096 intel_crtc->plane = pipe;
3a77c4c4 14097 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14098 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14099 intel_crtc->plane = !pipe;
80824003
JB		 14100 }
14101
4b0e333e
CW		 14102 intel_crtc->cursor_base = ~0;
14103 intel_crtc->cursor_cntl = ~0;
dc41c154 14104 intel_crtc->cursor_size = ~0;
8d7849db 14105
852eb00d
VS		 14106 intel_crtc->wm.cxsr_allowed = true;
14107
22fd0fab
JB		 14108 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14109 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14110 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14111 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14112
79e53945 14113 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14114
14115 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14116 return;
14117
14118fail:
14119 if (primary)
14120 drm_plane_cleanup(primary);
14121 if (cursor)
14122 drm_plane_cleanup(cursor);
f5de6e07 14123 kfree(crtc_state);
3d7d6510 14124 kfree(intel_crtc);
79e53945
JB		 14125}
14126
752aa88a
JB		 14127enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14128{
14129 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14130 struct drm_device *dev = connector->base.dev;
752aa88a 14131
51fd371b 14132 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14133
d3babd3f 14134 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14135 return INVALID_PIPE;
14136
14137 return to_intel_crtc(encoder->crtc)->pipe;
14138}
14139
08d7b3d1 14140int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14141 struct drm_file *file)
08d7b3d1 14142{
08d7b3d1 14143 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14144 struct drm_crtc *drmmode_crtc;
c05422d5 14145 struct intel_crtc *crtc;
08d7b3d1 14146
7707e653 14147 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14148
7707e653 14149 if (!drmmode_crtc) {
08d7b3d1 14150 DRM_ERROR("no such CRTC id\n");
3f2c2057 14151 return -ENOENT;
08d7b3d1
CW		 14152 }
14153
7707e653 14154 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14155 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14156
c05422d5 14157 return 0;
08d7b3d1
CW		 14158}
14159
66a9278e 14160static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14161{
66a9278e
DV		 14162 struct drm_device *dev = encoder->base.dev;
14163 struct intel_encoder *source_encoder;
79e53945 14164 int index_mask = 0;
79e53945
JB		 14165 int entry = 0;
14166
b2784e15 14167 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14168 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14169 index_mask |= (1 << entry);
14170
79e53945
JB		 14171 entry++;
14172 }
4ef69c7a 14173
79e53945
JB		 14174 return index_mask;
14175}
14176
4d302442
CW		 14177static bool has_edp_a(struct drm_device *dev)
14178{
14179 struct drm_i915_private *dev_priv = dev->dev_private;
14180
14181 if (!IS_MOBILE(dev))
14182 return false;
14183
14184 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14185 return false;
14186
e3589908 14187 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14188 return false;
14189
14190 return true;
14191}
14192
84b4e042
JB		 14193static bool intel_crt_present(struct drm_device *dev)
14194{
14195 struct drm_i915_private *dev_priv = dev->dev_private;
14196
884497ed
DL		 14197 if (INTEL_INFO(dev)->gen >= 9)
14198 return false;
14199
cf404ce4 14200 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14201 return false;
14202
14203 if (IS_CHERRYVIEW(dev))
14204 return false;
14205
14206 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14207 return false;
14208
14209 return true;
14210}
14211
79e53945
JB		 14212static void intel_setup_outputs(struct drm_device *dev)
14213{
725e30ad 14214 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14215 struct intel_encoder *encoder;
cb0953d7 14216 bool dpd_is_edp = false;
79e53945 14217
c9093354 14218 intel_lvds_init(dev);
79e53945 14219
84b4e042 14220 if (intel_crt_present(dev))
79935fca 14221 intel_crt_init(dev);
cb0953d7 14222
c776eb2e
VK		 14223 if (IS_BROXTON(dev)) {
14224 /*
14225 * FIXME: Broxton doesn't support port detection via the
14226 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14227 * detect the ports.
14228 */
14229 intel_ddi_init(dev, PORT_A);
14230 intel_ddi_init(dev, PORT_B);
14231 intel_ddi_init(dev, PORT_C);
14232 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14233 int found;
14234
de31facd
JB		 14235 /*
14236 * Haswell uses DDI functions to detect digital outputs.
14237 * On SKL pre-D0 the strap isn't connected, so we assume
14238 * it's there.
14239 */
0e72a5b5 14240 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14241 /* WaIgnoreDDIAStrap: skl */
14242 if (found ||
14243 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14244 intel_ddi_init(dev, PORT_A);
14245
14246 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14247 * register */
14248 found = I915_READ(SFUSE_STRAP);
14249
14250 if (found & SFUSE_STRAP_DDIB_DETECTED)
14251 intel_ddi_init(dev, PORT_B);
14252 if (found & SFUSE_STRAP_DDIC_DETECTED)
14253 intel_ddi_init(dev, PORT_C);
14254 if (found & SFUSE_STRAP_DDID_DETECTED)
14255 intel_ddi_init(dev, PORT_D);
14256 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14257 int found;
5d8a7752 14258 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14259
14260 if (has_edp_a(dev))
14261 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14262
dc0fa718 14263 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14264 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14265 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14266 if (!found)
e2debe91 14267 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14268 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14269 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14270 }
14271
dc0fa718 14272 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14273 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14274
dc0fa718 14275 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14276 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14277
5eb08b69 14278 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14279 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14280
270b3042 14281 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14282 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14283 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14284 /*
14285 * The DP_DETECTED bit is the latched state of the DDC
14286 * SDA pin at boot. However since eDP doesn't require DDC
14287 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14288 * eDP ports may have been muxed to an alternate function.
14289 * Thus we can't rely on the DP_DETECTED bit alone to detect
14290 * eDP ports. Consult the VBT as well as DP_DETECTED to
14291 * detect eDP ports.
14292 */
d2182a66
VS		 14293 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14294 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14295 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14296 PORT_B);
e17ac6db
VS		 14297 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14298 intel_dp_is_edp(dev, PORT_B))
14299 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14300
d2182a66
VS		 14301 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14302 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14303 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14304 PORT_C);
e17ac6db
VS		 14305 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14306 intel_dp_is_edp(dev, PORT_C))
14307 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14308
9418c1f1 14309 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14310 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14311 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14312 PORT_D);
e17ac6db
VS		 14313 /* eDP not supported on port D, so don't check VBT */
14314 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14315 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14316 }
14317
3cfca973 14318 intel_dsi_init(dev);
103a196f 14319 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14320 bool found = false;
7d57382e 14321
e2debe91 14322 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14323 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14324 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14325 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14326 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14327 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14328 }
27185ae1 14329
e7281eab 14330 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14331 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14332 }
13520b05
KH		 14333
14334 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14335
e2debe91 14336 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14337 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14338 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14339 }
27185ae1 14340
e2debe91 14341 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14342
b01f2c3a
JB		 14343 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14344 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14345 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14346 }
e7281eab 14347 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14348 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14349 }
27185ae1 14350
b01f2c3a 14351 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14352 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14353 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14354 } else if (IS_GEN2(dev))
79e53945
JB		 14355 intel_dvo_init(dev);
14356
103a196f 14357 if (SUPPORTS_TV(dev))
79e53945
JB		 14358 intel_tv_init(dev);
14359
0bc12bcb 14360 intel_psr_init(dev);
7c8f8a70 14361
b2784e15 14362 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14363 encoder->base.possible_crtcs = encoder->crtc_mask;
14364 encoder->base.possible_clones =
66a9278e 14365 intel_encoder_clones(encoder);
79e53945 14366 }
47356eb6 14367
dde86e2d 14368 intel_init_pch_refclk(dev);
270b3042
DV		 14369
14370 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14371}
14372
14373static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14374{
60a5ca01 14375 struct drm_device *dev = fb->dev;
79e53945 14376 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14377
ef2d633e 14378 drm_framebuffer_cleanup(fb);
60a5ca01 14379 mutex_lock(&dev->struct_mutex);
ef2d633e 14380 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14381 drm_gem_object_unreference(&intel_fb->obj->base);
14382 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14383 kfree(intel_fb);
14384}
14385
14386static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14387 struct drm_file *file,
79e53945
JB		 14388 unsigned int *handle)
14389{
14390 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14391 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14392
05394f39 14393 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14394}
14395
14396static const struct drm_framebuffer_funcs intel_fb_funcs = {
14397 .destroy = intel_user_framebuffer_destroy,
14398 .create_handle = intel_user_framebuffer_create_handle,
14399};
14400
b321803d
DL		 14401static
14402u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14403 uint32_t pixel_format)
14404{
14405 u32 gen = INTEL_INFO(dev)->gen;
14406
14407 if (gen >= 9) {
14408 /* "The stride in bytes must not exceed the of the size of 8K
14409 * pixels and 32K bytes."
14410 */
14411 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14412 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14413 return 32*1024;
14414 } else if (gen >= 4) {
14415 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14416 return 16*1024;
14417 else
14418 return 32*1024;
14419 } else if (gen >= 3) {
14420 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14421 return 8*1024;
14422 else
14423 return 16*1024;
14424 } else {
14425 /* XXX DSPC is limited to 4k tiled */
14426 return 8*1024;
14427 }
14428}
14429
b5ea642a
DV		 14430static int intel_framebuffer_init(struct drm_device *dev,
14431 struct intel_framebuffer *intel_fb,
14432 struct drm_mode_fb_cmd2 *mode_cmd,
14433 struct drm_i915_gem_object *obj)
79e53945 14434{
6761dd31 14435 unsigned int aligned_height;
79e53945 14436 int ret;
b321803d 14437 u32 pitch_limit, stride_alignment;
79e53945 14438
dd4916c5
DV		 14439 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14440
2a80eada
DV		 14441 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14442 /* Enforce that fb modifier and tiling mode match, but only for
14443 * X-tiled. This is needed for FBC. */
14444 if (!!(obj->tiling_mode == I915_TILING_X) !=
14445 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14446 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14447 return -EINVAL;
14448 }
14449 } else {
14450 if (obj->tiling_mode == I915_TILING_X)
14451 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14452 else if (obj->tiling_mode == I915_TILING_Y) {
14453 DRM_DEBUG("No Y tiling for legacy addfb\n");
14454 return -EINVAL;
14455 }
14456 }
14457
9a8f0a12
TU		 14458 /* Passed in modifier sanity checking. */
14459 switch (mode_cmd->modifier[0]) {
14460 case I915_FORMAT_MOD_Y_TILED:
14461 case I915_FORMAT_MOD_Yf_TILED:
14462 if (INTEL_INFO(dev)->gen < 9) {
14463 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14464 mode_cmd->modifier[0]);
14465 return -EINVAL;
14466 }
14467 case DRM_FORMAT_MOD_NONE:
14468 case I915_FORMAT_MOD_X_TILED:
14469 break;
14470 default:
c0f40428
JB		 14471 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14472 mode_cmd->modifier[0]);
57cd6508 14473 return -EINVAL;
c16ed4be 14474 }
57cd6508 14475
b321803d
DL		 14476 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14477 mode_cmd->pixel_format);
14478 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14479 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14480 mode_cmd->pitches[0], stride_alignment);
57cd6508 14481 return -EINVAL;
c16ed4be 14482 }
57cd6508 14483
b321803d
DL		 14484 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14485 mode_cmd->pixel_format);
a35cdaa0 14486 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14487 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14488 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14489 "tiled" : "linear",
a35cdaa0 14490 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14491 return -EINVAL;
c16ed4be 14492 }
5d7bd705 14493
2a80eada 14494 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14495 mode_cmd->pitches[0] != obj->stride) {
14496 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14497 mode_cmd->pitches[0], obj->stride);
5d7bd705 14498 return -EINVAL;
c16ed4be 14499 }
5d7bd705 14500
57779d06 14501 /* Reject formats not supported by any plane early. */
308e5bcb 14502 switch (mode_cmd->pixel_format) {
57779d06 14503 case DRM_FORMAT_C8:
04b3924d
VS		 14504 case DRM_FORMAT_RGB565:
14505 case DRM_FORMAT_XRGB8888:
14506 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14507 break;
14508 case DRM_FORMAT_XRGB1555:
c16ed4be 14509 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14510 DRM_DEBUG("unsupported pixel format: %s\n",
14511 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14512 return -EINVAL;
c16ed4be 14513 }
57779d06 14514 break;
57779d06 14515 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14516 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14517 DRM_DEBUG("unsupported pixel format: %s\n",
14518 drm_get_format_name(mode_cmd->pixel_format));
14519 return -EINVAL;
14520 }
14521 break;
14522 case DRM_FORMAT_XBGR8888:
04b3924d 14523 case DRM_FORMAT_XRGB2101010:
57779d06 14524 case DRM_FORMAT_XBGR2101010:
c16ed4be 14525 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14526 DRM_DEBUG("unsupported pixel format: %s\n",
14527 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14528 return -EINVAL;
c16ed4be 14529 }
b5626747 14530 break;
7531208b
DL		 14531 case DRM_FORMAT_ABGR2101010:
14532 if (!IS_VALLEYVIEW(dev)) {
14533 DRM_DEBUG("unsupported pixel format: %s\n",
14534 drm_get_format_name(mode_cmd->pixel_format));
14535 return -EINVAL;
14536 }
14537 break;
04b3924d
VS		 14538 case DRM_FORMAT_YUYV:
14539 case DRM_FORMAT_UYVY:
14540 case DRM_FORMAT_YVYU:
14541 case DRM_FORMAT_VYUY:
c16ed4be 14542 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14543 DRM_DEBUG("unsupported pixel format: %s\n",
14544 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14545 return -EINVAL;
c16ed4be 14546 }
57cd6508
CW		 14547 break;
14548 default:
4ee62c76
VS		 14549 DRM_DEBUG("unsupported pixel format: %s\n",
14550 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14551 return -EINVAL;
14552 }
14553
90f9a336
VS		 14554 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14555 if (mode_cmd->offsets[0] != 0)
14556 return -EINVAL;
14557
ec2c981e 14558 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14559 mode_cmd->pixel_format,
14560 mode_cmd->modifier[0]);
53155c0a
DV		 14561 /* FIXME drm helper for size checks (especially planar formats)? */
14562 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14563 return -EINVAL;
14564
c7d73f6a
DV		 14565 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14566 intel_fb->obj = obj;
80075d49 14567 intel_fb->obj->framebuffer_references++;
c7d73f6a 14568
79e53945
JB		 14569 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14570 if (ret) {
14571 DRM_ERROR("framebuffer init failed %d\n", ret);
14572 return ret;
14573 }
14574
79e53945
JB		 14575 return 0;
14576}
14577
79e53945
JB		 14578static struct drm_framebuffer *
14579intel_user_framebuffer_create(struct drm_device *dev,
14580 struct drm_file *filp,
308e5bcb 14581 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14582{
05394f39 14583 struct drm_i915_gem_object *obj;
79e53945 14584
308e5bcb
JB		 14585 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14586 mode_cmd->handles[0]));
c8725226 14587 if (&obj->base == NULL)
cce13ff7 14588 return ERR_PTR(-ENOENT);
79e53945 14589
d2dff872 14590 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14591}
14592
4520f53a 14593#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14594static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14595{
14596}
14597#endif
14598
79e53945 14599static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14600 .fb_create = intel_user_framebuffer_create,
0632fef6 14601 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14602 .atomic_check = intel_atomic_check,
14603 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14604 .atomic_state_alloc = intel_atomic_state_alloc,
14605 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14606};
14607
e70236a8
JB		 14608/* Set up chip specific display functions */
14609static void intel_init_display(struct drm_device *dev)
14610{
14611 struct drm_i915_private *dev_priv = dev->dev_private;
14612
ee9300bb
DV		 14613 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14614 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14615 else if (IS_CHERRYVIEW(dev))
14616 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14617 else if (IS_VALLEYVIEW(dev))
14618 dev_priv->display.find_dpll = vlv_find_best_dpll;
14619 else if (IS_PINEVIEW(dev))
14620 dev_priv->display.find_dpll = pnv_find_best_dpll;
14621 else
14622 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14623
bc8d7dff
DL		 14624 if (INTEL_INFO(dev)->gen >= 9) {
14625 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14626 dev_priv->display.get_initial_plane_config =
14627 skylake_get_initial_plane_config;
bc8d7dff
DL		 14628 dev_priv->display.crtc_compute_clock =
14629 haswell_crtc_compute_clock;
14630 dev_priv->display.crtc_enable = haswell_crtc_enable;
14631 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14632 dev_priv->display.update_primary_plane =
14633 skylake_update_primary_plane;
14634 } else if (HAS_DDI(dev)) {
0e8ffe1b 14635 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14636 dev_priv->display.get_initial_plane_config =
14637 ironlake_get_initial_plane_config;
797d0259
ACO		 14638 dev_priv->display.crtc_compute_clock =
14639 haswell_crtc_compute_clock;
4f771f10
PZ		 14640 dev_priv->display.crtc_enable = haswell_crtc_enable;
14641 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14642 dev_priv->display.update_primary_plane =
14643 ironlake_update_primary_plane;
09b4ddf9 14644 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14645 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14646 dev_priv->display.get_initial_plane_config =
14647 ironlake_get_initial_plane_config;
3fb37703
ACO		 14648 dev_priv->display.crtc_compute_clock =
14649 ironlake_crtc_compute_clock;
76e5a89c
DV		 14650 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14651 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14652 dev_priv->display.update_primary_plane =
14653 ironlake_update_primary_plane;
89b667f8
JB		 14654 } else if (IS_VALLEYVIEW(dev)) {
14655 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14656 dev_priv->display.get_initial_plane_config =
14657 i9xx_get_initial_plane_config;
d6dfee7a 14658 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14659 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14660 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14661 dev_priv->display.update_primary_plane =
14662 i9xx_update_primary_plane;
f564048e 14663 } else {
0e8ffe1b 14664 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14665 dev_priv->display.get_initial_plane_config =
14666 i9xx_get_initial_plane_config;
d6dfee7a 14667 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14668 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14669 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14670 dev_priv->display.update_primary_plane =
14671 i9xx_update_primary_plane;
f564048e 14672 }
e70236a8 14673
e70236a8 14674 /* Returns the core display clock speed */
1652d19e
VS		 14675 if (IS_SKYLAKE(dev))
14676 dev_priv->display.get_display_clock_speed =
14677 skylake_get_display_clock_speed;
acd3f3d3
BP		 14678 else if (IS_BROXTON(dev))
14679 dev_priv->display.get_display_clock_speed =
14680 broxton_get_display_clock_speed;
1652d19e
VS		 14681 else if (IS_BROADWELL(dev))
14682 dev_priv->display.get_display_clock_speed =
14683 broadwell_get_display_clock_speed;
14684 else if (IS_HASWELL(dev))
14685 dev_priv->display.get_display_clock_speed =
14686 haswell_get_display_clock_speed;
14687 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14688 dev_priv->display.get_display_clock_speed =
14689 valleyview_get_display_clock_speed;
b37a6434
VS		 14690 else if (IS_GEN5(dev))
14691 dev_priv->display.get_display_clock_speed =
14692 ilk_get_display_clock_speed;
a7c66cd8 14693 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14694 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14695 dev_priv->display.get_display_clock_speed =
14696 i945_get_display_clock_speed;
34edce2f
VS		 14697 else if (IS_GM45(dev))
14698 dev_priv->display.get_display_clock_speed =
14699 gm45_get_display_clock_speed;
14700 else if (IS_CRESTLINE(dev))
14701 dev_priv->display.get_display_clock_speed =
14702 i965gm_get_display_clock_speed;
14703 else if (IS_PINEVIEW(dev))
14704 dev_priv->display.get_display_clock_speed =
14705 pnv_get_display_clock_speed;
14706 else if (IS_G33(dev) || IS_G4X(dev))
14707 dev_priv->display.get_display_clock_speed =
14708 g33_get_display_clock_speed;
e70236a8
JB		 14709 else if (IS_I915G(dev))
14710 dev_priv->display.get_display_clock_speed =
14711 i915_get_display_clock_speed;
257a7ffc 14712 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14713 dev_priv->display.get_display_clock_speed =
14714 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14715 else if (IS_PINEVIEW(dev))
14716 dev_priv->display.get_display_clock_speed =
14717 pnv_get_display_clock_speed;
e70236a8
JB		 14718 else if (IS_I915GM(dev))
14719 dev_priv->display.get_display_clock_speed =
14720 i915gm_get_display_clock_speed;
14721 else if (IS_I865G(dev))
14722 dev_priv->display.get_display_clock_speed =
14723 i865_get_display_clock_speed;
f0f8a9ce 14724 else if (IS_I85X(dev))
e70236a8 14725 dev_priv->display.get_display_clock_speed =
1b1d2716 14726 i85x_get_display_clock_speed;
623e01e5
VS		 14727 else { /* 830 */
14728 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14729 dev_priv->display.get_display_clock_speed =
14730 i830_get_display_clock_speed;
623e01e5 14731 }
e70236a8 14732
7c10a2b5 14733 if (IS_GEN5(dev)) {
3bb11b53 14734 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14735 } else if (IS_GEN6(dev)) {
14736 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14737 } else if (IS_IVYBRIDGE(dev)) {
14738 /* FIXME: detect B0+ stepping and use auto training */
14739 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14740 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14741 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14742 if (IS_BROADWELL(dev)) {
14743 dev_priv->display.modeset_commit_cdclk =
14744 broadwell_modeset_commit_cdclk;
14745 dev_priv->display.modeset_calc_cdclk =
14746 broadwell_modeset_calc_cdclk;
14747 }
30a970c6 14748 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14749 dev_priv->display.modeset_commit_cdclk =
14750 valleyview_modeset_commit_cdclk;
14751 dev_priv->display.modeset_calc_cdclk =
14752 valleyview_modeset_calc_cdclk;
f8437dd1 14753 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14754 dev_priv->display.modeset_commit_cdclk =
14755 broxton_modeset_commit_cdclk;
14756 dev_priv->display.modeset_calc_cdclk =
14757 broxton_modeset_calc_cdclk;
e70236a8 14758 }
8c9f3aaf 14759
8c9f3aaf
JB		 14760 switch (INTEL_INFO(dev)->gen) {
14761 case 2:
14762 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14763 break;
14764
14765 case 3:
14766 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14767 break;
14768
14769 case 4:
14770 case 5:
14771 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14772 break;
14773
14774 case 6:
14775 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14776 break;
7c9017e5 14777 case 7:
4e0bbc31 14778 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14779 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14780 break;
830c81db 14781 case 9:
ba343e02
TU		 14782 /* Drop through - unsupported since execlist only. */
14783 default:
14784 /* Default just returns -ENODEV to indicate unsupported */
14785 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14786 }
7bd688cd
JN		 14787
14788 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14789
14790 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14791}
14792
b690e96c
JB		 14793/*
14794 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14795 * resume, or other times. This quirk makes sure that's the case for
14796 * affected systems.
14797 */
0206e353 14798static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14799{
14800 struct drm_i915_private *dev_priv = dev->dev_private;
14801
14802 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14803 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14804}
14805
b6b5d049
VS		 14806static void quirk_pipeb_force(struct drm_device *dev)
14807{
14808 struct drm_i915_private *dev_priv = dev->dev_private;
14809
14810 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14811 DRM_INFO("applying pipe b force quirk\n");
14812}
14813
435793df
KP		 14814/*
14815 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14816 */
14817static void quirk_ssc_force_disable(struct drm_device *dev)
14818{
14819 struct drm_i915_private *dev_priv = dev->dev_private;
14820 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14821 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14822}
14823
4dca20ef 14824/*
5a15ab5b
CE		 14825 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14826 * brightness value
4dca20ef
CE		 14827 */
14828static void quirk_invert_brightness(struct drm_device *dev)
14829{
14830 struct drm_i915_private *dev_priv = dev->dev_private;
14831 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14832 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14833}
14834
9c72cc6f
SD		 14835/* Some VBT's incorrectly indicate no backlight is present */
14836static void quirk_backlight_present(struct drm_device *dev)
14837{
14838 struct drm_i915_private *dev_priv = dev->dev_private;
14839 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14840 DRM_INFO("applying backlight present quirk\n");
14841}
14842
b690e96c
JB		 14843struct intel_quirk {
14844 int device;
14845 int subsystem_vendor;
14846 int subsystem_device;
14847 void (*hook)(struct drm_device *dev);
14848};
14849
5f85f176
EE		 14850/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14851struct intel_dmi_quirk {
14852 void (*hook)(struct drm_device *dev);
14853 const struct dmi_system_id (*dmi_id_list)[];
14854};
14855
14856static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14857{
14858 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14859 return 1;
14860}
14861
14862static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14863 {
14864 .dmi_id_list = &(const struct dmi_system_id[]) {
14865 {
14866 .callback = intel_dmi_reverse_brightness,
14867 .ident = "NCR Corporation",
14868 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14869 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14870 },
14871 },
14872 { } /* terminating entry */
14873 },
14874 .hook = quirk_invert_brightness,
14875 },
14876};
14877
c43b5634 14878static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14879 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14880 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14881
b690e96c
JB		 14882 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14883 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14884
5f080c0f
VS		 14885 /* 830 needs to leave pipe A & dpll A up */
14886 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14887
b6b5d049
VS		 14888 /* 830 needs to leave pipe B & dpll B up */
14889 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14890
435793df
KP		 14891 /* Lenovo U160 cannot use SSC on LVDS */
14892 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14893
14894 /* Sony Vaio Y cannot use SSC on LVDS */
14895 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14896
be505f64
AH		 14897 /* Acer Aspire 5734Z must invert backlight brightness */
14898 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14899
14900 /* Acer/eMachines G725 */
14901 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14902
14903 /* Acer/eMachines e725 */
14904 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14905
14906 /* Acer/Packard Bell NCL20 */
14907 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14908
14909 /* Acer Aspire 4736Z */
14910 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14911
14912 /* Acer Aspire 5336 */
14913 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14914
14915 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14916 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14917
dfb3d47b
SD		 14918 /* Acer C720 Chromebook (Core i3 4005U) */
14919 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14920
b2a9601c 14921 /* Apple Macbook 2,1 (Core 2 T7400) */
14922 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14923
d4967d8c
SD		 14924 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14925 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14926
14927 /* HP Chromebook 14 (Celeron 2955U) */
14928 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14929
14930 /* Dell Chromebook 11 */
14931 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14932};
14933
14934static void intel_init_quirks(struct drm_device *dev)
14935{
14936 struct pci_dev *d = dev->pdev;
14937 int i;
14938
14939 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14940 struct intel_quirk *q = &intel_quirks[i];
14941
14942 if (d->device == q->device &&
14943 (d->subsystem_vendor == q->subsystem_vendor ||
14944 q->subsystem_vendor == PCI_ANY_ID) &&
14945 (d->subsystem_device == q->subsystem_device ||
14946 q->subsystem_device == PCI_ANY_ID))
14947 q->hook(dev);
14948 }
5f85f176
EE		 14949 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14950 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14951 intel_dmi_quirks[i].hook(dev);
14952 }
b690e96c
JB		 14953}
14954
9cce37f4
JB		 14955/* Disable the VGA plane that we never use */
14956static void i915_disable_vga(struct drm_device *dev)
14957{
14958 struct drm_i915_private *dev_priv = dev->dev_private;
14959 u8 sr1;
766aa1c4 14960 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14961
2b37c616 14962 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14963 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14964 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14965 sr1 = inb(VGA_SR_DATA);
14966 outb(sr1 | 1<<5, VGA_SR_DATA);
14967 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14968 udelay(300);
14969
01f5a626 14970 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14971 POSTING_READ(vga_reg);
14972}
14973
f817586c
DV		 14974void intel_modeset_init_hw(struct drm_device *dev)
14975{
b6283055 14976 intel_update_cdclk(dev);
a8f78b58 14977 intel_prepare_ddi(dev);
f817586c 14978 intel_init_clock_gating(dev);
8090c6b9 14979 intel_enable_gt_powersave(dev);
f817586c
DV		 14980}
14981
79e53945
JB		 14982void intel_modeset_init(struct drm_device *dev)
14983{
652c393a 14984 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14985 int sprite, ret;
8cc87b75 14986 enum pipe pipe;
46f297fb 14987 struct intel_crtc *crtc;
79e53945
JB		 14988
14989 drm_mode_config_init(dev);
14990
14991 dev->mode_config.min_width = 0;
14992 dev->mode_config.min_height = 0;
14993
019d96cb
DA		 14994 dev->mode_config.preferred_depth = 24;
14995 dev->mode_config.prefer_shadow = 1;
14996
25bab385
TU		 14997 dev->mode_config.allow_fb_modifiers = true;
14998
e6ecefaa 14999 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15000
b690e96c
JB		 15001 intel_init_quirks(dev);
15002
1fa61106
ED		 15003 intel_init_pm(dev);
15004
e3c74757
BW		 15005 if (INTEL_INFO(dev)->num_pipes == 0)
15006 return;
15007
e70236a8 15008 intel_init_display(dev);
7c10a2b5 15009 intel_init_audio(dev);
e70236a8 15010
a6c45cf0
CW		 15011 if (IS_GEN2(dev)) {
15012 dev->mode_config.max_width = 2048;
15013 dev->mode_config.max_height = 2048;
15014 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15015 dev->mode_config.max_width = 4096;
15016 dev->mode_config.max_height = 4096;
79e53945 15017 } else {
a6c45cf0
CW		 15018 dev->mode_config.max_width = 8192;
15019 dev->mode_config.max_height = 8192;
79e53945 15020 }
068be561 15021
dc41c154
VS		 15022 if (IS_845G(dev) || IS_I865G(dev)) {
15023 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15024 dev->mode_config.cursor_height = 1023;
15025 } else if (IS_GEN2(dev)) {
068be561
DL		 15026 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15027 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15028 } else {
15029 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15030 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15031 }
15032
5d4545ae 15033 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15034
28c97730 15035 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15036 INTEL_INFO(dev)->num_pipes,
15037 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15038
055e393f 15039 for_each_pipe(dev_priv, pipe) {
8cc87b75 15040 intel_crtc_init(dev, pipe);
3bdcfc0c 15041 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15042 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15043 if (ret)
06da8da2 15044 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15045 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15046 }
79e53945
JB		 15047 }
15048
f42bb70d
JB		 15049 intel_init_dpio(dev);
15050
e72f9fbf 15051 intel_shared_dpll_init(dev);
ee7b9f93 15052
9cce37f4
JB		 15053 /* Just disable it once at startup */
15054 i915_disable_vga(dev);
79e53945 15055 intel_setup_outputs(dev);
11be49eb
CW		 15056
15057 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15058 intel_fbc_disable(dev);
fa9fa083 15059
6e9f798d 15060 drm_modeset_lock_all(dev);
fa9fa083 15061 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15062 drm_modeset_unlock_all(dev);
46f297fb 15063
d3fcc808 15064 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15065 if (!crtc->active)
15066 continue;
15067
46f297fb 15068 /*
46f297fb
JB		 15069 * Note that reserving the BIOS fb up front prevents us
15070 * from stuffing other stolen allocations like the ring
15071 * on top. This prevents some ugliness at boot time, and
15072 * can even allow for smooth boot transitions if the BIOS
15073 * fb is large enough for the active pipe configuration.
15074 */
5724dbd1
DL		 15075 if (dev_priv->display.get_initial_plane_config) {
15076 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15077 &crtc->plane_config);
15078 /*
15079 * If the fb is shared between multiple heads, we'll
15080 * just get the first one.
15081 */
f6936e29 15082 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15083 }
46f297fb 15084 }
2c7111db
CW		 15085}
15086
7fad798e
DV		 15087static void intel_enable_pipe_a(struct drm_device *dev)
15088{
15089 struct intel_connector *connector;
15090 struct drm_connector *crt = NULL;
15091 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15092 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15093
15094 /* We can't just switch on the pipe A, we need to set things up with a
15095 * proper mode and output configuration. As a gross hack, enable pipe A
15096 * by enabling the load detect pipe once. */
3a3371ff 15097 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15098 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15099 crt = &connector->base;
15100 break;
15101 }
15102 }
15103
15104 if (!crt)
15105 return;
15106
208bf9fd 15107 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15108 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15109}
15110
fa555837
DV		 15111static bool
15112intel_check_plane_mapping(struct intel_crtc *crtc)
15113{
7eb552ae
BW		 15114 struct drm_device *dev = crtc->base.dev;
15115 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15116 u32 reg, val;
15117
7eb552ae 15118 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15119 return true;
15120
15121 reg = DSPCNTR(!crtc->plane);
15122 val = I915_READ(reg);
15123
15124 if ((val & DISPLAY_PLANE_ENABLE) &&
15125 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15126 return false;
15127
15128 return true;
15129}
15130
24929352
DV		 15131static void intel_sanitize_crtc(struct intel_crtc *crtc)
15132{
15133 struct drm_device *dev = crtc->base.dev;
15134 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15135 struct intel_encoder *encoder;
fa555837 15136 u32 reg;
b17d48e2 15137 bool enable;
24929352 15138
24929352 15139 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15140 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15141 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15142
d3eaf884 15143 /* restore vblank interrupts to correct state */
9625604c 15144 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15145 if (crtc->active) {
15146 update_scanline_offset(crtc);
9625604c
DV		 15147 drm_crtc_vblank_on(&crtc->base);
15148 }
d3eaf884 15149
24929352 15150 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15151 * disable the crtc (and hence change the state) if it is wrong. Note
15152 * that gen4+ has a fixed plane -> pipe mapping. */
15153 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15154 bool plane;
15155
24929352
DV		 15156 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15157 crtc->base.base.id);
15158
15159 /* Pipe has the wrong plane attached and the plane is active.
15160 * Temporarily change the plane mapping and disable everything
15161 * ... */
15162 plane = crtc->plane;
b70709a6 15163 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15164 crtc->plane = !plane;
b17d48e2 15165 intel_crtc_disable_noatomic(&crtc->base);
24929352 15166 crtc->plane = plane;
24929352 15167 }
24929352 15168
7fad798e
DV		 15169 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15170 crtc->pipe == PIPE_A && !crtc->active) {
15171 /* BIOS forgot to enable pipe A, this mostly happens after
15172 * resume. Force-enable the pipe to fix this, the update_dpms
15173 * call below we restore the pipe to the right state, but leave
15174 * the required bits on. */
15175 intel_enable_pipe_a(dev);
15176 }
15177
24929352
DV		 15178 /* Adjust the state of the output pipe according to whether we
15179 * have active connectors/encoders. */
b17d48e2
ML		 15180 enable = false;
15181 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15182 enable |= encoder->connectors_active;
24929352 15183
b17d48e2
ML		 15184 if (!enable)
15185 intel_crtc_disable_noatomic(&crtc->base);
24929352 15186
53d9f4e9 15187 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15188
15189 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15190 * functions or because of calls to intel_crtc_disable_noatomic,
15191 * or because the pipe is force-enabled due to the
24929352
DV		 15192 * pipe A quirk. */
15193 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15194 crtc->base.base.id,
83d65738 15195 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15196 crtc->active ? "enabled" : "disabled");
15197
83d65738 15198 crtc->base.state->enable = crtc->active;
49d6fa21 15199 crtc->base.state->active = crtc->active;
24929352
DV		 15200 crtc->base.enabled = crtc->active;
15201
15202 /* Because we only establish the connector -> encoder ->
15203 * crtc links if something is active, this means the
15204 * crtc is now deactivated. Break the links. connector
15205 * -> encoder links are only establish when things are
15206 * actually up, hence no need to break them. */
15207 WARN_ON(crtc->active);
15208
15209 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15210 WARN_ON(encoder->connectors_active);
15211 encoder->base.crtc = NULL;
15212 }
15213 }
c5ab3bc0 15214
a3ed6aad 15215 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15216 /*
15217 * We start out with underrun reporting disabled to avoid races.
15218 * For correct bookkeeping mark this on active crtcs.
15219 *
c5ab3bc0
DV		 15220 * Also on gmch platforms we dont have any hardware bits to
15221 * disable the underrun reporting. Which means we need to start
15222 * out with underrun reporting disabled also on inactive pipes,
15223 * since otherwise we'll complain about the garbage we read when
15224 * e.g. coming up after runtime pm.
15225 *
4cc31489
DV		 15226 * No protection against concurrent access is required - at
15227 * worst a fifo underrun happens which also sets this to false.
15228 */
15229 crtc->cpu_fifo_underrun_disabled = true;
15230 crtc->pch_fifo_underrun_disabled = true;
15231 }
24929352
DV		 15232}
15233
15234static void intel_sanitize_encoder(struct intel_encoder *encoder)
15235{
15236 struct intel_connector *connector;
15237 struct drm_device *dev = encoder->base.dev;
15238
15239 /* We need to check both for a crtc link (meaning that the
15240 * encoder is active and trying to read from a pipe) and the
15241 * pipe itself being active. */
15242 bool has_active_crtc = encoder->base.crtc &&
15243 to_intel_crtc(encoder->base.crtc)->active;
15244
15245 if (encoder->connectors_active && !has_active_crtc) {
15246 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15247 encoder->base.base.id,
8e329a03 15248 encoder->base.name);
24929352
DV		 15249
15250 /* Connector is active, but has no active pipe. This is
15251 * fallout from our resume register restoring. Disable
15252 * the encoder manually again. */
15253 if (encoder->base.crtc) {
15254 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15255 encoder->base.base.id,
8e329a03 15256 encoder->base.name);
24929352 15257 encoder->disable(encoder);
a62d1497
VS		 15258 if (encoder->post_disable)
15259 encoder->post_disable(encoder);
24929352 15260 }
7f1950fb
EE		 15261 encoder->base.crtc = NULL;
15262 encoder->connectors_active = false;
24929352
DV		 15263
15264 /* Inconsistent output/port/pipe state happens presumably due to
15265 * a bug in one of the get_hw_state functions. Or someplace else
15266 * in our code, like the register restore mess on resume. Clamp
15267 * things to off as a safer default. */
3a3371ff 15268 for_each_intel_connector(dev, connector) {
24929352
DV		 15269 if (connector->encoder != encoder)
15270 continue;
7f1950fb
EE		 15271 connector->base.dpms = DRM_MODE_DPMS_OFF;
15272 connector->base.encoder = NULL;
24929352
DV		 15273 }
15274 }
15275 /* Enabled encoders without active connectors will be fixed in
15276 * the crtc fixup. */
15277}
15278
04098753 15279void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15280{
15281 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15282 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15283
04098753
ID		 15284 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15285 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15286 i915_disable_vga(dev);
15287 }
15288}
15289
15290void i915_redisable_vga(struct drm_device *dev)
15291{
15292 struct drm_i915_private *dev_priv = dev->dev_private;
15293
8dc8a27c
PZ		 15294 /* This function can be called both from intel_modeset_setup_hw_state or
15295 * at a very early point in our resume sequence, where the power well
15296 * structures are not yet restored. Since this function is at a very
15297 * paranoid "someone might have enabled VGA while we were not looking"
15298 * level, just check if the power well is enabled instead of trying to
15299 * follow the "don't touch the power well if we don't need it" policy
15300 * the rest of the driver uses. */
f458ebbc 15301 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15302 return;
15303
04098753 15304 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15305}
15306
98ec7739
VS		 15307static bool primary_get_hw_state(struct intel_crtc *crtc)
15308{
15309 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15310
d032ffa0
ML		 15311 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15312}
15313
15314static void readout_plane_state(struct intel_crtc *crtc,
15315 struct intel_crtc_state *crtc_state)
15316{
15317 struct intel_plane *p;
15318 struct drm_plane_state *drm_plane_state;
15319 bool active = crtc_state->base.active;
15320
15321 if (active) {
15322 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15323
15324 /* apply to previous sw state too */
15325 to_intel_crtc_state(crtc->base.state)->quirks |=
15326 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15327 }
98ec7739 15328
d032ffa0
ML		 15329 for_each_intel_plane(crtc->base.dev, p) {
15330 bool visible = active;
15331
15332 if (crtc->pipe != p->pipe)
15333 continue;
15334
15335 drm_plane_state = p->base.state;
15336 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15337 visible = primary_get_hw_state(crtc);
15338 to_intel_plane_state(drm_plane_state)->visible = visible;
15339 } else {
15340 /*
15341 * unknown state, assume it's off to force a transition
15342 * to on when calculating state changes.
15343 */
15344 to_intel_plane_state(drm_plane_state)->visible = false;
15345 }
15346
15347 if (visible) {
15348 crtc_state->base.plane_mask |=
15349 1 << drm_plane_index(&p->base);
15350 } else if (crtc_state->base.state) {
15351 /* Make this unconditional for atomic hw readout. */
15352 crtc_state->base.plane_mask &=
15353 ~(1 << drm_plane_index(&p->base));
15354 }
15355 }
98ec7739
VS		 15356}
15357
30e984df 15358static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15359{
15360 struct drm_i915_private *dev_priv = dev->dev_private;
15361 enum pipe pipe;
24929352
DV		 15362 struct intel_crtc *crtc;
15363 struct intel_encoder *encoder;
15364 struct intel_connector *connector;
5358901f 15365 int i;
24929352 15366
d3fcc808 15367 for_each_intel_crtc(dev, crtc) {
6e3c9717 15368 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15369 crtc->config->base.crtc = &crtc->base;
3b117c8f 15370
6e3c9717 15371 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15372
0e8ffe1b 15373 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15374 crtc->config);
24929352 15375
83d65738 15376 crtc->base.state->enable = crtc->active;
49d6fa21 15377 crtc->base.state->active = crtc->active;
24929352 15378 crtc->base.enabled = crtc->active;
b8b7fade 15379 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6 15380
d032ffa0 15381 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15382
15383 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15384 crtc->base.base.id,
15385 crtc->active ? "enabled" : "disabled");
15386 }
15387
5358901f
DV		 15388 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15389 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15390
3e369b76
ACO		 15391 pll->on = pll->get_hw_state(dev_priv, pll,
15392 &pll->config.hw_state);
5358901f 15393 pll->active = 0;
3e369b76 15394 pll->config.crtc_mask = 0;
d3fcc808 15395 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15396 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15397 pll->active++;
3e369b76 15398 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15399 }
5358901f 15400 }
5358901f 15401
1e6f2ddc 15402 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15403 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15404
3e369b76 15405 if (pll->config.crtc_mask)
bd2bb1b9 15406 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15407 }
15408
b2784e15 15409 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15410 pipe = 0;
15411
15412 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15413 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15414 encoder->base.crtc = &crtc->base;
6e3c9717 15415 encoder->get_config(encoder, crtc->config);
24929352
DV		 15416 } else {
15417 encoder->base.crtc = NULL;
15418 }
15419
15420 encoder->connectors_active = false;
6f2bcceb 15421 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15422 encoder->base.base.id,
8e329a03 15423 encoder->base.name,
24929352 15424 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15425 pipe_name(pipe));
24929352
DV		 15426 }
15427
3a3371ff 15428 for_each_intel_connector(dev, connector) {
24929352
DV		 15429 if (connector->get_hw_state(connector)) {
15430 connector->base.dpms = DRM_MODE_DPMS_ON;
15431 connector->encoder->connectors_active = true;
15432 connector->base.encoder = &connector->encoder->base;
15433 } else {
15434 connector->base.dpms = DRM_MODE_DPMS_OFF;
15435 connector->base.encoder = NULL;
15436 }
15437 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15438 connector->base.base.id,
c23cc417 15439 connector->base.name,
24929352
DV		 15440 connector->base.encoder ? "enabled" : "disabled");
15441 }
30e984df
DV		 15442}
15443
15444/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15445 * and i915 state tracking structures. */
15446void intel_modeset_setup_hw_state(struct drm_device *dev,
15447 bool force_restore)
15448{
15449 struct drm_i915_private *dev_priv = dev->dev_private;
15450 enum pipe pipe;
30e984df
DV		 15451 struct intel_crtc *crtc;
15452 struct intel_encoder *encoder;
35c95375 15453 int i;
30e984df
DV		 15454
15455 intel_modeset_readout_hw_state(dev);
24929352 15456
babea61d
JB		 15457 /*
15458 * Now that we have the config, copy it to each CRTC struct
15459 * Note that this could go away if we move to using crtc_config
15460 * checking everywhere.
15461 */
d3fcc808 15462 for_each_intel_crtc(dev, crtc) {
d330a953 15463 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15464 intel_mode_from_pipe_config(&crtc->base.mode,
15465 crtc->config);
babea61d
JB		 15466 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15467 crtc->base.base.id);
15468 drm_mode_debug_printmodeline(&crtc->base.mode);
15469 }
15470 }
15471
24929352 15472 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15473 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15474 intel_sanitize_encoder(encoder);
15475 }
15476
055e393f 15477 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15478 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15479 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15480 intel_dump_pipe_config(crtc, crtc->config,
15481 "[setup_hw_state]");
24929352 15482 }
9a935856 15483
d29b2f9d
ACO		 15484 intel_modeset_update_connector_atomic_state(dev);
15485
35c95375
DV		 15486 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15487 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15488
15489 if (!pll->on || pll->active)
15490 continue;
15491
15492 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15493
15494 pll->disable(dev_priv, pll);
15495 pll->on = false;
15496 }
15497
26e1fe4f 15498 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15499 vlv_wm_get_hw_state(dev);
15500 else if (IS_GEN9(dev))
3078999f
PB		 15501 skl_wm_get_hw_state(dev);
15502 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15503 ilk_wm_get_hw_state(dev);
15504
45e2b5f6 15505 if (force_restore) {
7d0bc1ea
VS		 15506 i915_redisable_vga(dev);
15507
f30da187
DV		 15508 /*
15509 * We need to use raw interfaces for restoring state to avoid
15510 * checking (bogus) intermediate states.
15511 */
055e393f 15512 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15513 struct drm_crtc *crtc =
15514 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15515
83a57153 15516 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15517 }
15518 } else {
15519 intel_modeset_update_staged_output_state(dev);
15520 }
8af6cf88
DV		 15521
15522 intel_modeset_check_state(dev);
2c7111db
CW		 15523}
15524
15525void intel_modeset_gem_init(struct drm_device *dev)
15526{
92122789 15527 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15528 struct drm_crtc *c;
2ff8fde1 15529 struct drm_i915_gem_object *obj;
e0d6149b 15530 int ret;
484b41dd 15531
ae48434c
ID		 15532 mutex_lock(&dev->struct_mutex);
15533 intel_init_gt_powersave(dev);
15534 mutex_unlock(&dev->struct_mutex);
15535
92122789
JB		 15536 /*
15537 * There may be no VBT; and if the BIOS enabled SSC we can
15538 * just keep using it to avoid unnecessary flicker. Whereas if the
15539 * BIOS isn't using it, don't assume it will work even if the VBT
15540 * indicates as much.
15541 */
15542 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15543 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15544 DREF_SSC1_ENABLE);
15545
1833b134 15546 intel_modeset_init_hw(dev);
02e792fb
DV		 15547
15548 intel_setup_overlay(dev);
484b41dd
JB		 15549
15550 /*
15551 * Make sure any fbs we allocated at startup are properly
15552 * pinned & fenced. When we do the allocation it's too early
15553 * for this.
15554 */
70e1e0ec 15555 for_each_crtc(dev, c) {
2ff8fde1
MR		 15556 obj = intel_fb_obj(c->primary->fb);
15557 if (obj == NULL)
484b41dd
JB		 15558 continue;
15559
e0d6149b
TU		 15560 mutex_lock(&dev->struct_mutex);
15561 ret = intel_pin_and_fence_fb_obj(c->primary,
15562 c->primary->fb,
15563 c->primary->state,
91af127f 15564 NULL, NULL);
e0d6149b
TU		 15565 mutex_unlock(&dev->struct_mutex);
15566 if (ret) {
484b41dd
JB		 15567 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15568 to_intel_crtc(c)->pipe);
66e514c1
DA		 15569 drm_framebuffer_unreference(c->primary->fb);
15570 c->primary->fb = NULL;
36750f28 15571 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15572 update_state_fb(c->primary);
36750f28 15573 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15574 }
15575 }
0962c3c9
VS		 15576
15577 intel_backlight_register(dev);
79e53945
JB		 15578}
15579
4932e2c3
ID		 15580void intel_connector_unregister(struct intel_connector *intel_connector)
15581{
15582 struct drm_connector *connector = &intel_connector->base;
15583
15584 intel_panel_destroy_backlight(connector);
34ea3d38 15585 drm_connector_unregister(connector);
4932e2c3
ID		 15586}
15587
79e53945
JB		 15588void intel_modeset_cleanup(struct drm_device *dev)
15589{
652c393a 15590 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15591 struct drm_connector *connector;
652c393a 15592
2eb5252e
ID		 15593 intel_disable_gt_powersave(dev);
15594
0962c3c9
VS		 15595 intel_backlight_unregister(dev);
15596
fd0c0642
DV		 15597 /*
15598 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15599 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15600 * experience fancy races otherwise.
15601 */
2aeb7d3a 15602 intel_irq_uninstall(dev_priv);
eb21b92b 15603
fd0c0642
DV		 15604 /*
15605 * Due to the hpd irq storm handling the hotplug work can re-arm the
15606 * poll handlers. Hence disable polling after hpd handling is shut down.
15607 */
f87ea761 15608 drm_kms_helper_poll_fini(dev);
fd0c0642 15609
652c393a
JB		 15610 mutex_lock(&dev->struct_mutex);
15611
723bfd70
JB		 15612 intel_unregister_dsm_handler();
15613
7ff0ebcc 15614 intel_fbc_disable(dev);
e70236a8 15615
69341a5e
KH		 15616 mutex_unlock(&dev->struct_mutex);
15617
1630fe75
CW		 15618 /* flush any delayed tasks or pending work */
15619 flush_scheduled_work();
15620
db31af1d
JN		 15621 /* destroy the backlight and sysfs files before encoders/connectors */
15622 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15623 struct intel_connector *intel_connector;
15624
15625 intel_connector = to_intel_connector(connector);
15626 intel_connector->unregister(intel_connector);
db31af1d 15627 }
d9255d57 15628
79e53945 15629 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15630
15631 intel_cleanup_overlay(dev);
ae48434c
ID		 15632
15633 mutex_lock(&dev->struct_mutex);
15634 intel_cleanup_gt_powersave(dev);
15635 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15636}
15637
f1c79df3
ZW		 15638/*
15639 * Return which encoder is currently attached for connector.
15640 */
df0e9248 15641struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15642{
df0e9248
CW		 15643 return &intel_attached_encoder(connector)->base;
15644}
f1c79df3 15645
df0e9248
CW		 15646void intel_connector_attach_encoder(struct intel_connector *connector,
15647 struct intel_encoder *encoder)
15648{
15649 connector->encoder = encoder;
15650 drm_mode_connector_attach_encoder(&connector->base,
15651 &encoder->base);
79e53945 15652}
28d52043
DA		 15653
15654/*
15655 * set vga decode state - true == enable VGA decode
15656 */
15657int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15658{
15659 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15660 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15661 u16 gmch_ctrl;
15662
75fa041d
CW		 15663 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15664 DRM_ERROR("failed to read control word\n");
15665 return -EIO;
15666 }
15667
c0cc8a55
CW		 15668 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15669 return 0;
15670
28d52043
DA		 15671 if (state)
15672 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15673 else
15674 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15675
15676 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15677 DRM_ERROR("failed to write control word\n");
15678 return -EIO;
15679 }
15680
28d52043
DA		 15681 return 0;
15682}
c4a1d9e4 15683
c4a1d9e4 15684struct intel_display_error_state {
ff57f1b0
PZ		 15685
15686 u32 power_well_driver;
15687
63b66e5b
CW		 15688 int num_transcoders;
15689
c4a1d9e4
CW		 15690 struct intel_cursor_error_state {
15691 u32 control;
15692 u32 position;
15693 u32 base;
15694 u32 size;
52331309 15695 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15696
15697 struct intel_pipe_error_state {
ddf9c536 15698 bool power_domain_on;
c4a1d9e4 15699 u32 source;
f301b1e1 15700 u32 stat;
52331309 15701 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15702
15703 struct intel_plane_error_state {
15704 u32 control;
15705 u32 stride;
15706 u32 size;
15707 u32 pos;
15708 u32 addr;
15709 u32 surface;
15710 u32 tile_offset;
52331309 15711 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15712
15713 struct intel_transcoder_error_state {
ddf9c536 15714 bool power_domain_on;
63b66e5b
CW		 15715 enum transcoder cpu_transcoder;
15716
15717 u32 conf;
15718
15719 u32 htotal;
15720 u32 hblank;
15721 u32 hsync;
15722 u32 vtotal;
15723 u32 vblank;
15724 u32 vsync;
15725 } transcoder[4];
c4a1d9e4
CW		 15726};
15727
15728struct intel_display_error_state *
15729intel_display_capture_error_state(struct drm_device *dev)
15730{
fbee40df 15731 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15732 struct intel_display_error_state *error;
63b66e5b
CW		 15733 int transcoders[] = {
15734 TRANSCODER_A,
15735 TRANSCODER_B,
15736 TRANSCODER_C,
15737 TRANSCODER_EDP,
15738 };
c4a1d9e4
CW		 15739 int i;
15740
63b66e5b
CW		 15741 if (INTEL_INFO(dev)->num_pipes == 0)
15742 return NULL;
15743
9d1cb914 15744 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15745 if (error == NULL)
15746 return NULL;
15747
190be112 15748 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15749 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15750
055e393f 15751 for_each_pipe(dev_priv, i) {
ddf9c536 15752 error->pipe[i].power_domain_on =
f458ebbc
DV		 15753 __intel_display_power_is_enabled(dev_priv,
15754 POWER_DOMAIN_PIPE(i));
ddf9c536 15755 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15756 continue;
15757
5efb3e28
VS		 15758 error->cursor[i].control = I915_READ(CURCNTR(i));
15759 error->cursor[i].position = I915_READ(CURPOS(i));
15760 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15761
15762 error->plane[i].control = I915_READ(DSPCNTR(i));
15763 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15764 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15765 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15766 error->plane[i].pos = I915_READ(DSPPOS(i));
15767 }
ca291363
PZ		 15768 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15769 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15770 if (INTEL_INFO(dev)->gen >= 4) {
15771 error->plane[i].surface = I915_READ(DSPSURF(i));
15772 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15773 }
15774
c4a1d9e4 15775 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15776
3abfce77 15777 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15778 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15779 }
15780
15781 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15782 if (HAS_DDI(dev_priv->dev))
15783 error->num_transcoders++; /* Account for eDP. */
15784
15785 for (i = 0; i < error->num_transcoders; i++) {
15786 enum transcoder cpu_transcoder = transcoders[i];
15787
ddf9c536 15788 error->transcoder[i].power_domain_on =
f458ebbc 15789 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15790 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15791 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15792 continue;
15793
63b66e5b
CW		 15794 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15795
15796 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15797 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15798 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15799 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15800 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15801 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15802 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15803 }
15804
15805 return error;
15806}
15807
edc3d884
MK		 15808#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15809
c4a1d9e4 15810void
edc3d884 15811intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15812 struct drm_device *dev,
15813 struct intel_display_error_state *error)
15814{
055e393f 15815 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15816 int i;
15817
63b66e5b
CW		 15818 if (!error)
15819 return;
15820
edc3d884 15821 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15822 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15823 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15824 error->power_well_driver);
055e393f 15825 for_each_pipe(dev_priv, i) {
edc3d884 15826 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15827 err_printf(m, " Power: %s\n",
15828 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15829 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15830 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15831
15832 err_printf(m, "Plane [%d]:\n", i);
15833 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15834 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15835 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15836 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15837 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15838 }
4b71a570 15839 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15840 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15841 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15842 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15843 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15844 }
15845
edc3d884
MK		 15846 err_printf(m, "Cursor [%d]:\n", i);
15847 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15848 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15849 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15850 }
63b66e5b
CW		 15851
15852 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15853 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15854 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15855 err_printf(m, " Power: %s\n",
15856 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15857 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15858 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15859 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15860 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15861 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15862 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15863 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15864 }
c4a1d9e4 15865}
e2fcdaa9
VS		 15866
15867void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15868{
15869 struct intel_crtc *crtc;
15870
15871 for_each_intel_crtc(dev, crtc) {
15872 struct intel_unpin_work *work;
e2fcdaa9 15873
5e2d7afc 15874 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15875
15876 work = crtc->unpin_work;
15877
15878 if (work && work->event &&
15879 work->event->base.file_priv == file) {
15880 kfree(work->event);
15881 work->event = NULL;
15882 }
15883
5e2d7afc 15884 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15885 }
15886}
Linux kernel - Deliverables
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