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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
021357ac CW |
345 | static inline u32 /* units of 100MHz */ |
346 | intel_fdi_link_freq(struct drm_device *dev) | |
347 | { | |
8b99e68c CW |
348 | if (IS_GEN5(dev)) { |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
351 | } else | |
352 | return 27; | |
021357ac CW |
353 | } |
354 | ||
e4b36699 | 355 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
356 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
357 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
358 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
359 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
360 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
361 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
362 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
363 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
364 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
365 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 366 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
367 | }; |
368 | ||
369 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
370 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
371 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
372 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
373 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
374 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
375 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
376 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
377 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
378 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
379 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 380 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
381 | }; |
382 | ||
383 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
384 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
385 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
386 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
387 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
388 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
389 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
390 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
391 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
392 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
393 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 394 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
395 | }; |
396 | ||
397 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
398 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
399 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
400 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
401 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
402 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
403 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
404 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
405 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
406 | /* The single-channel range is 25-112Mhz, and dual-channel | |
407 | * is 80-224Mhz. Prefer single channel as much as possible. | |
408 | */ | |
409 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
410 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 411 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
412 | }; |
413 | ||
044c7c41 | 414 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 415 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
416 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
417 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
418 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
419 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
420 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
421 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
422 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
423 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
424 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
425 | .p2_slow = G4X_P2_SDVO_SLOW, | |
426 | .p2_fast = G4X_P2_SDVO_FAST | |
427 | }, | |
d4906093 | 428 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
429 | }; |
430 | ||
431 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
432 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
433 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
434 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
435 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
436 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
437 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
438 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
439 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
440 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
441 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
442 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
443 | }, | |
d4906093 | 444 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
445 | }; |
446 | ||
447 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
448 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
449 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
450 | .vco = { .min = G4X_VCO_MIN, | |
451 | .max = G4X_VCO_MAX }, | |
452 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
453 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
454 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
455 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
456 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
457 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
458 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
459 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
460 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
461 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
462 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
463 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
464 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
465 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
466 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
467 | }, | |
d4906093 | 468 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
469 | }; |
470 | ||
471 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
472 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
473 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
474 | .vco = { .min = G4X_VCO_MIN, | |
475 | .max = G4X_VCO_MAX }, | |
476 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
477 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
478 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
479 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
480 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
481 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
482 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
483 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
484 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
485 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
486 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
487 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
488 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
489 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
490 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
491 | }, | |
d4906093 | 492 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
493 | }; |
494 | ||
495 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
496 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
497 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
498 | .vco = { .min = G4X_VCO_MIN, | |
499 | .max = G4X_VCO_MAX}, | |
500 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
501 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
502 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
503 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
504 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
505 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
506 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
507 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
508 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
509 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
510 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
511 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
512 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
513 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
514 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
515 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
516 | }; |
517 | ||
f2b115e6 | 518 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 519 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
520 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
521 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
522 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
523 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
524 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
525 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
526 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
527 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
528 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 529 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
530 | }; |
531 | ||
f2b115e6 | 532 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 533 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
534 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
535 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
536 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
537 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
538 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
539 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 540 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 541 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
542 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
543 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 544 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
545 | }; |
546 | ||
b91ad0ec | 547 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
548 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
549 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
550 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
551 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
552 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
553 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
554 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
555 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 556 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
557 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
558 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 559 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
560 | }; |
561 | ||
b91ad0ec | 562 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
563 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
564 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
565 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
566 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
567 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
568 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
569 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
570 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 571 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
572 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
573 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
574 | .find_pll = intel_g4x_find_best_PLL, | |
575 | }; | |
576 | ||
577 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
578 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
579 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
580 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
581 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
582 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
583 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
584 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
585 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
586 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
587 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
588 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
589 | .find_pll = intel_g4x_find_best_PLL, | |
590 | }; | |
591 | ||
592 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
593 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
594 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
595 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
596 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
597 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
598 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
599 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
600 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
601 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
602 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
603 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
604 | .find_pll = intel_g4x_find_best_PLL, | |
605 | }; | |
606 | ||
607 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
608 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
609 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
610 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
611 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
612 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
613 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
614 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
615 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
616 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
617 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
618 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
619 | .find_pll = intel_g4x_find_best_PLL, |
620 | }; | |
621 | ||
622 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
623 | .dot = { .min = IRONLAKE_DOT_MIN, | |
624 | .max = IRONLAKE_DOT_MAX }, | |
625 | .vco = { .min = IRONLAKE_VCO_MIN, | |
626 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
627 | .n = { .min = IRONLAKE_DP_N_MIN, |
628 | .max = IRONLAKE_DP_N_MAX }, | |
629 | .m = { .min = IRONLAKE_DP_M_MIN, | |
630 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
631 | .m1 = { .min = IRONLAKE_M1_MIN, |
632 | .max = IRONLAKE_M1_MAX }, | |
633 | .m2 = { .min = IRONLAKE_M2_MIN, | |
634 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
635 | .p = { .min = IRONLAKE_DP_P_MIN, |
636 | .max = IRONLAKE_DP_P_MAX }, | |
637 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
638 | .max = IRONLAKE_DP_P1_MAX}, | |
639 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
640 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
641 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 642 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
643 | }; |
644 | ||
1b894b59 CW |
645 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
646 | int refclk) | |
2c07245f | 647 | { |
b91ad0ec ZW |
648 | struct drm_device *dev = crtc->dev; |
649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 650 | const intel_limit_t *limit; |
b91ad0ec ZW |
651 | |
652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
654 | LVDS_CLKB_POWER_UP) { | |
655 | /* LVDS dual channel */ | |
1b894b59 | 656 | if (refclk == 100000) |
b91ad0ec ZW |
657 | limit = &intel_limits_ironlake_dual_lvds_100m; |
658 | else | |
659 | limit = &intel_limits_ironlake_dual_lvds; | |
660 | } else { | |
1b894b59 | 661 | if (refclk == 100000) |
b91ad0ec ZW |
662 | limit = &intel_limits_ironlake_single_lvds_100m; |
663 | else | |
664 | limit = &intel_limits_ironlake_single_lvds; | |
665 | } | |
666 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
667 | HAS_eDP) |
668 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 669 | else |
b91ad0ec | 670 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
671 | |
672 | return limit; | |
673 | } | |
674 | ||
044c7c41 ML |
675 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
676 | { | |
677 | struct drm_device *dev = crtc->dev; | |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | const intel_limit_t *limit; | |
680 | ||
681 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
682 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
683 | LVDS_CLKB_POWER_UP) | |
684 | /* LVDS with dual channel */ | |
e4b36699 | 685 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
686 | else |
687 | /* LVDS with dual channel */ | |
e4b36699 | 688 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
689 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 691 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 693 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 694 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 695 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 696 | } else /* The option is for other outputs */ |
e4b36699 | 697 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
698 | |
699 | return limit; | |
700 | } | |
701 | ||
1b894b59 | 702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
703 | { |
704 | struct drm_device *dev = crtc->dev; | |
705 | const intel_limit_t *limit; | |
706 | ||
bad720ff | 707 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 708 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 709 | else if (IS_G4X(dev)) { |
044c7c41 | 710 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 711 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 713 | limit = &intel_limits_pineview_lvds; |
2177832f | 714 | else |
f2b115e6 | 715 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
716 | } else if (!IS_GEN2(dev)) { |
717 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
718 | limit = &intel_limits_i9xx_lvds; | |
719 | else | |
720 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
721 | } else { |
722 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 723 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 724 | else |
e4b36699 | 725 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
726 | } |
727 | return limit; | |
728 | } | |
729 | ||
f2b115e6 AJ |
730 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
731 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 732 | { |
2177832f SL |
733 | clock->m = clock->m2 + 2; |
734 | clock->p = clock->p1 * clock->p2; | |
735 | clock->vco = refclk * clock->m / clock->n; | |
736 | clock->dot = clock->vco / clock->p; | |
737 | } | |
738 | ||
739 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
740 | { | |
f2b115e6 AJ |
741 | if (IS_PINEVIEW(dev)) { |
742 | pineview_clock(refclk, clock); | |
2177832f SL |
743 | return; |
744 | } | |
79e53945 JB |
745 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
746 | clock->p = clock->p1 * clock->p2; | |
747 | clock->vco = refclk * clock->m / (clock->n + 2); | |
748 | clock->dot = clock->vco / clock->p; | |
749 | } | |
750 | ||
79e53945 JB |
751 | /** |
752 | * Returns whether any output on the specified pipe is of the specified type | |
753 | */ | |
4ef69c7a | 754 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 755 | { |
4ef69c7a CW |
756 | struct drm_device *dev = crtc->dev; |
757 | struct drm_mode_config *mode_config = &dev->mode_config; | |
758 | struct intel_encoder *encoder; | |
759 | ||
760 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
761 | if (encoder->base.crtc == crtc && encoder->type == type) | |
762 | return true; | |
763 | ||
764 | return false; | |
79e53945 JB |
765 | } |
766 | ||
7c04d1d9 | 767 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
768 | /** |
769 | * Returns whether the given set of divisors are valid for a given refclk with | |
770 | * the given connectors. | |
771 | */ | |
772 | ||
1b894b59 CW |
773 | static bool intel_PLL_is_valid(struct drm_device *dev, |
774 | const intel_limit_t *limit, | |
775 | const intel_clock_t *clock) | |
79e53945 | 776 | { |
79e53945 JB |
777 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
778 | INTELPllInvalid ("p1 out of range\n"); | |
779 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
780 | INTELPllInvalid ("p out of range\n"); | |
781 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
782 | INTELPllInvalid ("m2 out of range\n"); | |
783 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
784 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 785 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
786 | INTELPllInvalid ("m1 <= m2\n"); |
787 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
788 | INTELPllInvalid ("m out of range\n"); | |
789 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
790 | INTELPllInvalid ("n out of range\n"); | |
791 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
792 | INTELPllInvalid ("vco out of range\n"); | |
793 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
794 | * connector, etc., rather than just a single range. | |
795 | */ | |
796 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
797 | INTELPllInvalid ("dot out of range\n"); | |
798 | ||
799 | return true; | |
800 | } | |
801 | ||
d4906093 ML |
802 | static bool |
803 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
804 | int target, int refclk, intel_clock_t *best_clock) | |
805 | ||
79e53945 JB |
806 | { |
807 | struct drm_device *dev = crtc->dev; | |
808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
809 | intel_clock_t clock; | |
79e53945 JB |
810 | int err = target; |
811 | ||
bc5e5718 | 812 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 813 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
814 | /* |
815 | * For LVDS, if the panel is on, just rely on its current | |
816 | * settings for dual-channel. We haven't figured out how to | |
817 | * reliably set up different single/dual channel state, if we | |
818 | * even can. | |
819 | */ | |
820 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
821 | LVDS_CLKB_POWER_UP) | |
822 | clock.p2 = limit->p2.p2_fast; | |
823 | else | |
824 | clock.p2 = limit->p2.p2_slow; | |
825 | } else { | |
826 | if (target < limit->p2.dot_limit) | |
827 | clock.p2 = limit->p2.p2_slow; | |
828 | else | |
829 | clock.p2 = limit->p2.p2_fast; | |
830 | } | |
831 | ||
832 | memset (best_clock, 0, sizeof (*best_clock)); | |
833 | ||
42158660 ZY |
834 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
835 | clock.m1++) { | |
836 | for (clock.m2 = limit->m2.min; | |
837 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
838 | /* m1 is always 0 in Pineview */ |
839 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
840 | break; |
841 | for (clock.n = limit->n.min; | |
842 | clock.n <= limit->n.max; clock.n++) { | |
843 | for (clock.p1 = limit->p1.min; | |
844 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
845 | int this_err; |
846 | ||
2177832f | 847 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
848 | if (!intel_PLL_is_valid(dev, limit, |
849 | &clock)) | |
79e53945 JB |
850 | continue; |
851 | ||
852 | this_err = abs(clock.dot - target); | |
853 | if (this_err < err) { | |
854 | *best_clock = clock; | |
855 | err = this_err; | |
856 | } | |
857 | } | |
858 | } | |
859 | } | |
860 | } | |
861 | ||
862 | return (err != target); | |
863 | } | |
864 | ||
d4906093 ML |
865 | static bool |
866 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
867 | int target, int refclk, intel_clock_t *best_clock) | |
868 | { | |
869 | struct drm_device *dev = crtc->dev; | |
870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
871 | intel_clock_t clock; | |
872 | int max_n; | |
873 | bool found; | |
6ba770dc AJ |
874 | /* approximately equals target * 0.00585 */ |
875 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
876 | found = false; |
877 | ||
878 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
879 | int lvds_reg; |
880 | ||
c619eed4 | 881 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
882 | lvds_reg = PCH_LVDS; |
883 | else | |
884 | lvds_reg = LVDS; | |
885 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
886 | LVDS_CLKB_POWER_UP) |
887 | clock.p2 = limit->p2.p2_fast; | |
888 | else | |
889 | clock.p2 = limit->p2.p2_slow; | |
890 | } else { | |
891 | if (target < limit->p2.dot_limit) | |
892 | clock.p2 = limit->p2.p2_slow; | |
893 | else | |
894 | clock.p2 = limit->p2.p2_fast; | |
895 | } | |
896 | ||
897 | memset(best_clock, 0, sizeof(*best_clock)); | |
898 | max_n = limit->n.max; | |
f77f13e2 | 899 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 900 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 901 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
902 | for (clock.m1 = limit->m1.max; |
903 | clock.m1 >= limit->m1.min; clock.m1--) { | |
904 | for (clock.m2 = limit->m2.max; | |
905 | clock.m2 >= limit->m2.min; clock.m2--) { | |
906 | for (clock.p1 = limit->p1.max; | |
907 | clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | int this_err; | |
909 | ||
2177832f | 910 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
911 | if (!intel_PLL_is_valid(dev, limit, |
912 | &clock)) | |
d4906093 | 913 | continue; |
1b894b59 CW |
914 | |
915 | this_err = abs(clock.dot - target); | |
d4906093 ML |
916 | if (this_err < err_most) { |
917 | *best_clock = clock; | |
918 | err_most = this_err; | |
919 | max_n = clock.n; | |
920 | found = true; | |
921 | } | |
922 | } | |
923 | } | |
924 | } | |
925 | } | |
2c07245f ZW |
926 | return found; |
927 | } | |
928 | ||
5eb08b69 | 929 | static bool |
f2b115e6 AJ |
930 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
931 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
932 | { |
933 | struct drm_device *dev = crtc->dev; | |
934 | intel_clock_t clock; | |
4547668a | 935 | |
5eb08b69 ZW |
936 | if (target < 200000) { |
937 | clock.n = 1; | |
938 | clock.p1 = 2; | |
939 | clock.p2 = 10; | |
940 | clock.m1 = 12; | |
941 | clock.m2 = 9; | |
942 | } else { | |
943 | clock.n = 2; | |
944 | clock.p1 = 1; | |
945 | clock.p2 = 10; | |
946 | clock.m1 = 14; | |
947 | clock.m2 = 8; | |
948 | } | |
949 | intel_clock(dev, refclk, &clock); | |
950 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
951 | return true; | |
952 | } | |
953 | ||
a4fc5ed6 KP |
954 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
955 | static bool | |
956 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
957 | int target, int refclk, intel_clock_t *best_clock) | |
958 | { | |
5eddb70b CW |
959 | intel_clock_t clock; |
960 | if (target < 200000) { | |
961 | clock.p1 = 2; | |
962 | clock.p2 = 10; | |
963 | clock.n = 2; | |
964 | clock.m1 = 23; | |
965 | clock.m2 = 8; | |
966 | } else { | |
967 | clock.p1 = 1; | |
968 | clock.p2 = 10; | |
969 | clock.n = 1; | |
970 | clock.m1 = 14; | |
971 | clock.m2 = 2; | |
972 | } | |
973 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
974 | clock.p = (clock.p1 * clock.p2); | |
975 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
976 | clock.vco = 0; | |
977 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
978 | return true; | |
a4fc5ed6 KP |
979 | } |
980 | ||
9d0498a2 JB |
981 | /** |
982 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
983 | * @dev: drm device | |
984 | * @pipe: pipe to wait for | |
985 | * | |
986 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
987 | * mode setting code. | |
988 | */ | |
989 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 990 | { |
9d0498a2 JB |
991 | struct drm_i915_private *dev_priv = dev->dev_private; |
992 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); | |
993 | ||
300387c0 CW |
994 | /* Clear existing vblank status. Note this will clear any other |
995 | * sticky status fields as well. | |
996 | * | |
997 | * This races with i915_driver_irq_handler() with the result | |
998 | * that either function could miss a vblank event. Here it is not | |
999 | * fatal, as we will either wait upon the next vblank interrupt or | |
1000 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
1001 | * called during modeset at which time the GPU should be idle and | |
1002 | * should *not* be performing page flips and thus not waiting on | |
1003 | * vblanks... | |
1004 | * Currently, the result of us stealing a vblank from the irq | |
1005 | * handler is that a single frame will be skipped during swapbuffers. | |
1006 | */ | |
1007 | I915_WRITE(pipestat_reg, | |
1008 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1009 | ||
9d0498a2 | 1010 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1011 | if (wait_for(I915_READ(pipestat_reg) & |
1012 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1013 | 50)) | |
9d0498a2 JB |
1014 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1015 | } | |
1016 | ||
ab7ad7f6 KP |
1017 | /* |
1018 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
1019 | * @dev: drm device |
1020 | * @pipe: pipe to wait for | |
1021 | * | |
1022 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1023 | * spinning on the vblank interrupt status bit, since we won't actually | |
1024 | * see an interrupt when the pipe is disabled. | |
1025 | * | |
ab7ad7f6 KP |
1026 | * On Gen4 and above: |
1027 | * wait for the pipe register state bit to turn off | |
1028 | * | |
1029 | * Otherwise: | |
1030 | * wait for the display line value to settle (it usually | |
1031 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1032 | * |
9d0498a2 | 1033 | */ |
58e10eb9 | 1034 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
1035 | { |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1037 | |
1038 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1039 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1040 | |
1041 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1042 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1043 | 100)) | |
ab7ad7f6 KP |
1044 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
1045 | } else { | |
1046 | u32 last_line; | |
58e10eb9 | 1047 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1048 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1049 | ||
1050 | /* Wait for the display line to settle */ | |
1051 | do { | |
58e10eb9 | 1052 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 1053 | mdelay(5); |
58e10eb9 | 1054 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
1055 | time_after(timeout, jiffies)); |
1056 | if (time_after(jiffies, timeout)) | |
1057 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
1058 | } | |
79e53945 JB |
1059 | } |
1060 | ||
80824003 JB |
1061 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1062 | { | |
1063 | struct drm_device *dev = crtc->dev; | |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1065 | struct drm_framebuffer *fb = crtc->fb; | |
1066 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1067 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 JB |
1068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1069 | int plane, i; | |
1070 | u32 fbc_ctl, fbc_ctl2; | |
1071 | ||
bed4a673 | 1072 | if (fb->pitch == dev_priv->cfb_pitch && |
05394f39 | 1073 | obj->fence_reg == dev_priv->cfb_fence && |
bed4a673 CW |
1074 | intel_crtc->plane == dev_priv->cfb_plane && |
1075 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) | |
1076 | return; | |
1077 | ||
1078 | i8xx_disable_fbc(dev); | |
1079 | ||
80824003 JB |
1080 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1081 | ||
1082 | if (fb->pitch < dev_priv->cfb_pitch) | |
1083 | dev_priv->cfb_pitch = fb->pitch; | |
1084 | ||
1085 | /* FBC_CTL wants 64B units */ | |
1086 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
05394f39 | 1087 | dev_priv->cfb_fence = obj->fence_reg; |
80824003 JB |
1088 | dev_priv->cfb_plane = intel_crtc->plane; |
1089 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1090 | ||
1091 | /* Clear old tags */ | |
1092 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1093 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1094 | ||
1095 | /* Set it up... */ | |
1096 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
05394f39 | 1097 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1098 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
1099 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1100 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1101 | ||
1102 | /* enable it... */ | |
1103 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1104 | if (IS_I945GM(dev)) |
49677901 | 1105 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1106 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1107 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
05394f39 | 1108 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1109 | fbc_ctl |= dev_priv->cfb_fence; |
1110 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1111 | ||
28c97730 | 1112 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
5eddb70b | 1113 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
80824003 JB |
1114 | } |
1115 | ||
1116 | void i8xx_disable_fbc(struct drm_device *dev) | |
1117 | { | |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1119 | u32 fbc_ctl; | |
1120 | ||
1121 | /* Disable compression */ | |
1122 | fbc_ctl = I915_READ(FBC_CONTROL); | |
a5cad620 CW |
1123 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
1124 | return; | |
1125 | ||
80824003 JB |
1126 | fbc_ctl &= ~FBC_CTL_EN; |
1127 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1128 | ||
1129 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1130 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1131 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1132 | return; | |
9517a92f | 1133 | } |
80824003 | 1134 | |
28c97730 | 1135 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1136 | } |
1137 | ||
ee5382ae | 1138 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1139 | { |
80824003 JB |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
1141 | ||
1142 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1143 | } | |
1144 | ||
74dff282 JB |
1145 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1146 | { | |
1147 | struct drm_device *dev = crtc->dev; | |
1148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1149 | struct drm_framebuffer *fb = crtc->fb; | |
1150 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1151 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1153 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1154 | unsigned long stall_watermark = 200; |
1155 | u32 dpfc_ctl; | |
1156 | ||
bed4a673 CW |
1157 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1158 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1159 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1160 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 CW |
1161 | dev_priv->cfb_plane == intel_crtc->plane && |
1162 | dev_priv->cfb_y == crtc->y) | |
1163 | return; | |
1164 | ||
1165 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1166 | POSTING_READ(DPFC_CONTROL); | |
1167 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1168 | } | |
1169 | ||
74dff282 | 1170 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1171 | dev_priv->cfb_fence = obj->fence_reg; |
74dff282 | 1172 | dev_priv->cfb_plane = intel_crtc->plane; |
bed4a673 | 1173 | dev_priv->cfb_y = crtc->y; |
74dff282 JB |
1174 | |
1175 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
05394f39 | 1176 | if (obj->tiling_mode != I915_TILING_NONE) { |
74dff282 JB |
1177 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
1178 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1179 | } else { | |
1180 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1181 | } | |
1182 | ||
74dff282 JB |
1183 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1184 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1185 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1186 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1187 | ||
1188 | /* enable it... */ | |
1189 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1190 | ||
28c97730 | 1191 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1192 | } |
1193 | ||
1194 | void g4x_disable_fbc(struct drm_device *dev) | |
1195 | { | |
1196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1197 | u32 dpfc_ctl; | |
1198 | ||
1199 | /* Disable compression */ | |
1200 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1201 | if (dpfc_ctl & DPFC_CTL_EN) { |
1202 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1203 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1204 | |
bed4a673 CW |
1205 | DRM_DEBUG_KMS("disabled FBC\n"); |
1206 | } | |
74dff282 JB |
1207 | } |
1208 | ||
ee5382ae | 1209 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1210 | { |
74dff282 JB |
1211 | struct drm_i915_private *dev_priv = dev->dev_private; |
1212 | ||
1213 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1214 | } | |
1215 | ||
4efe0708 JB |
1216 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1217 | { | |
1218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1219 | u32 blt_ecoskpd; | |
1220 | ||
1221 | /* Make sure blitter notifies FBC of writes */ | |
1222 | __gen6_force_wake_get(dev_priv); | |
1223 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | |
1224 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1225 | GEN6_BLITTER_LOCK_SHIFT; | |
1226 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1227 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1228 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1229 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1230 | GEN6_BLITTER_LOCK_SHIFT); | |
1231 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1232 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
1233 | __gen6_force_wake_put(dev_priv); | |
1234 | } | |
1235 | ||
b52eb4dc ZY |
1236 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1237 | { | |
1238 | struct drm_device *dev = crtc->dev; | |
1239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1240 | struct drm_framebuffer *fb = crtc->fb; | |
1241 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1242 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1243 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1244 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1245 | unsigned long stall_watermark = 200; |
1246 | u32 dpfc_ctl; | |
1247 | ||
bed4a673 CW |
1248 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1249 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1250 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1251 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 | 1252 | dev_priv->cfb_plane == intel_crtc->plane && |
05394f39 | 1253 | dev_priv->cfb_offset == obj->gtt_offset && |
bed4a673 CW |
1254 | dev_priv->cfb_y == crtc->y) |
1255 | return; | |
1256 | ||
1257 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1258 | POSTING_READ(ILK_DPFC_CONTROL); | |
1259 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1260 | } | |
1261 | ||
b52eb4dc | 1262 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1263 | dev_priv->cfb_fence = obj->fence_reg; |
b52eb4dc | 1264 | dev_priv->cfb_plane = intel_crtc->plane; |
05394f39 | 1265 | dev_priv->cfb_offset = obj->gtt_offset; |
bed4a673 | 1266 | dev_priv->cfb_y = crtc->y; |
b52eb4dc | 1267 | |
b52eb4dc ZY |
1268 | dpfc_ctl &= DPFC_RESERVED; |
1269 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
05394f39 | 1270 | if (obj->tiling_mode != I915_TILING_NONE) { |
b52eb4dc ZY |
1271 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); |
1272 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1273 | } else { | |
1274 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1275 | } | |
1276 | ||
b52eb4dc ZY |
1277 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1278 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1279 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1280 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1281 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1282 | /* enable it... */ |
bed4a673 | 1283 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1284 | |
9c04f015 YL |
1285 | if (IS_GEN6(dev)) { |
1286 | I915_WRITE(SNB_DPFC_CTL_SA, | |
1287 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); | |
1288 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
4efe0708 | 1289 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1290 | } |
1291 | ||
b52eb4dc ZY |
1292 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1293 | } | |
1294 | ||
1295 | void ironlake_disable_fbc(struct drm_device *dev) | |
1296 | { | |
1297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1298 | u32 dpfc_ctl; | |
1299 | ||
1300 | /* Disable compression */ | |
1301 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1302 | if (dpfc_ctl & DPFC_CTL_EN) { |
1303 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1304 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1305 | |
bed4a673 CW |
1306 | DRM_DEBUG_KMS("disabled FBC\n"); |
1307 | } | |
b52eb4dc ZY |
1308 | } |
1309 | ||
1310 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1311 | { | |
1312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1313 | ||
1314 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1315 | } | |
1316 | ||
ee5382ae AJ |
1317 | bool intel_fbc_enabled(struct drm_device *dev) |
1318 | { | |
1319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1320 | ||
1321 | if (!dev_priv->display.fbc_enabled) | |
1322 | return false; | |
1323 | ||
1324 | return dev_priv->display.fbc_enabled(dev); | |
1325 | } | |
1326 | ||
1327 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1328 | { | |
1329 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1330 | ||
1331 | if (!dev_priv->display.enable_fbc) | |
1332 | return; | |
1333 | ||
1334 | dev_priv->display.enable_fbc(crtc, interval); | |
1335 | } | |
1336 | ||
1337 | void intel_disable_fbc(struct drm_device *dev) | |
1338 | { | |
1339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1340 | ||
1341 | if (!dev_priv->display.disable_fbc) | |
1342 | return; | |
1343 | ||
1344 | dev_priv->display.disable_fbc(dev); | |
1345 | } | |
1346 | ||
80824003 JB |
1347 | /** |
1348 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1349 | * @dev: the drm_device |
80824003 JB |
1350 | * |
1351 | * Set up the framebuffer compression hardware at mode set time. We | |
1352 | * enable it if possible: | |
1353 | * - plane A only (on pre-965) | |
1354 | * - no pixel mulitply/line duplication | |
1355 | * - no alpha buffer discard | |
1356 | * - no dual wide | |
1357 | * - framebuffer <= 2048 in width, 1536 in height | |
1358 | * | |
1359 | * We can't assume that any compression will take place (worst case), | |
1360 | * so the compressed buffer has to be the same size as the uncompressed | |
1361 | * one. It also must reside (along with the line length buffer) in | |
1362 | * stolen memory. | |
1363 | * | |
1364 | * We need to enable/disable FBC on a global basis. | |
1365 | */ | |
bed4a673 | 1366 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1367 | { |
80824003 | 1368 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1369 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1370 | struct intel_crtc *intel_crtc; | |
1371 | struct drm_framebuffer *fb; | |
80824003 | 1372 | struct intel_framebuffer *intel_fb; |
05394f39 | 1373 | struct drm_i915_gem_object *obj; |
9c928d16 JB |
1374 | |
1375 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1376 | |
1377 | if (!i915_powersave) | |
1378 | return; | |
1379 | ||
ee5382ae | 1380 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1381 | return; |
1382 | ||
80824003 JB |
1383 | /* |
1384 | * If FBC is already on, we just have to verify that we can | |
1385 | * keep it that way... | |
1386 | * Need to disable if: | |
9c928d16 | 1387 | * - more than one pipe is active |
80824003 JB |
1388 | * - changing FBC params (stride, fence, mode) |
1389 | * - new fb is too large to fit in compressed buffer | |
1390 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1391 | */ | |
9c928d16 | 1392 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
bed4a673 CW |
1393 | if (tmp_crtc->enabled) { |
1394 | if (crtc) { | |
1395 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1396 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1397 | goto out_disable; | |
1398 | } | |
1399 | crtc = tmp_crtc; | |
1400 | } | |
9c928d16 | 1401 | } |
bed4a673 CW |
1402 | |
1403 | if (!crtc || crtc->fb == NULL) { | |
1404 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1405 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1406 | goto out_disable; |
1407 | } | |
bed4a673 CW |
1408 | |
1409 | intel_crtc = to_intel_crtc(crtc); | |
1410 | fb = crtc->fb; | |
1411 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1412 | obj = intel_fb->obj; |
bed4a673 | 1413 | |
05394f39 | 1414 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1415 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1416 | "compression\n"); |
b5e50c3f | 1417 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1418 | goto out_disable; |
1419 | } | |
bed4a673 CW |
1420 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1421 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1422 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1423 | "disabling\n"); |
b5e50c3f | 1424 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1425 | goto out_disable; |
1426 | } | |
bed4a673 CW |
1427 | if ((crtc->mode.hdisplay > 2048) || |
1428 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1429 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1430 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1431 | goto out_disable; |
1432 | } | |
bed4a673 | 1433 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1434 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1435 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1436 | goto out_disable; |
1437 | } | |
05394f39 | 1438 | if (obj->tiling_mode != I915_TILING_X) { |
28c97730 | 1439 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 1440 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1441 | goto out_disable; |
1442 | } | |
1443 | ||
c924b934 JW |
1444 | /* If the kernel debugger is active, always disable compression */ |
1445 | if (in_dbg_master()) | |
1446 | goto out_disable; | |
1447 | ||
bed4a673 | 1448 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1449 | return; |
1450 | ||
1451 | out_disable: | |
80824003 | 1452 | /* Multiple disables should be harmless */ |
a939406f CW |
1453 | if (intel_fbc_enabled(dev)) { |
1454 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1455 | intel_disable_fbc(dev); |
a939406f | 1456 | } |
80824003 JB |
1457 | } |
1458 | ||
127bd2ac | 1459 | int |
48b956c5 | 1460 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1461 | struct drm_i915_gem_object *obj, |
919926ae | 1462 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1463 | { |
6b95a207 KH |
1464 | u32 alignment; |
1465 | int ret; | |
1466 | ||
05394f39 | 1467 | switch (obj->tiling_mode) { |
6b95a207 | 1468 | case I915_TILING_NONE: |
534843da CW |
1469 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1470 | alignment = 128 * 1024; | |
a6c45cf0 | 1471 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1472 | alignment = 4 * 1024; |
1473 | else | |
1474 | alignment = 64 * 1024; | |
6b95a207 KH |
1475 | break; |
1476 | case I915_TILING_X: | |
1477 | /* pin() will align the object as required by fence */ | |
1478 | alignment = 0; | |
1479 | break; | |
1480 | case I915_TILING_Y: | |
1481 | /* FIXME: Is this true? */ | |
1482 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1483 | return -EINVAL; | |
1484 | default: | |
1485 | BUG(); | |
1486 | } | |
1487 | ||
75e9e915 | 1488 | ret = i915_gem_object_pin(obj, alignment, true); |
48b956c5 | 1489 | if (ret) |
6b95a207 KH |
1490 | return ret; |
1491 | ||
48b956c5 CW |
1492 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
1493 | if (ret) | |
1494 | goto err_unpin; | |
7213342d | 1495 | |
6b95a207 KH |
1496 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1497 | * fence, whereas 965+ only requires a fence if using | |
1498 | * framebuffer compression. For simplicity, we always install | |
1499 | * a fence as the cost is not that onerous. | |
1500 | */ | |
05394f39 | 1501 | if (obj->tiling_mode != I915_TILING_NONE) { |
d9e86c0e | 1502 | ret = i915_gem_object_get_fence(obj, pipelined, false); |
48b956c5 CW |
1503 | if (ret) |
1504 | goto err_unpin; | |
6b95a207 KH |
1505 | } |
1506 | ||
1507 | return 0; | |
48b956c5 CW |
1508 | |
1509 | err_unpin: | |
1510 | i915_gem_object_unpin(obj); | |
1511 | return ret; | |
6b95a207 KH |
1512 | } |
1513 | ||
81255565 JB |
1514 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
1515 | static int | |
1516 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
21c74a8e | 1517 | int x, int y, enum mode_set_atomic state) |
81255565 JB |
1518 | { |
1519 | struct drm_device *dev = crtc->dev; | |
1520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1522 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1523 | struct drm_i915_gem_object *obj; |
81255565 JB |
1524 | int plane = intel_crtc->plane; |
1525 | unsigned long Start, Offset; | |
81255565 | 1526 | u32 dspcntr; |
5eddb70b | 1527 | u32 reg; |
81255565 JB |
1528 | |
1529 | switch (plane) { | |
1530 | case 0: | |
1531 | case 1: | |
1532 | break; | |
1533 | default: | |
1534 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1535 | return -EINVAL; | |
1536 | } | |
1537 | ||
1538 | intel_fb = to_intel_framebuffer(fb); | |
1539 | obj = intel_fb->obj; | |
81255565 | 1540 | |
5eddb70b CW |
1541 | reg = DSPCNTR(plane); |
1542 | dspcntr = I915_READ(reg); | |
81255565 JB |
1543 | /* Mask out pixel format bits in case we change it */ |
1544 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1545 | switch (fb->bits_per_pixel) { | |
1546 | case 8: | |
1547 | dspcntr |= DISPPLANE_8BPP; | |
1548 | break; | |
1549 | case 16: | |
1550 | if (fb->depth == 15) | |
1551 | dspcntr |= DISPPLANE_15_16BPP; | |
1552 | else | |
1553 | dspcntr |= DISPPLANE_16BPP; | |
1554 | break; | |
1555 | case 24: | |
1556 | case 32: | |
1557 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1558 | break; | |
1559 | default: | |
1560 | DRM_ERROR("Unknown color depth\n"); | |
1561 | return -EINVAL; | |
1562 | } | |
a6c45cf0 | 1563 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 1564 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
1565 | dspcntr |= DISPPLANE_TILED; |
1566 | else | |
1567 | dspcntr &= ~DISPPLANE_TILED; | |
1568 | } | |
1569 | ||
4e6cfefc | 1570 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
1571 | /* must disable */ |
1572 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1573 | ||
5eddb70b | 1574 | I915_WRITE(reg, dspcntr); |
81255565 | 1575 | |
05394f39 | 1576 | Start = obj->gtt_offset; |
81255565 JB |
1577 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
1578 | ||
4e6cfefc CW |
1579 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
1580 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 1581 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 1582 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
1583 | I915_WRITE(DSPSURF(plane), Start); |
1584 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
1585 | I915_WRITE(DSPADDR(plane), Offset); | |
1586 | } else | |
1587 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
1588 | POSTING_READ(reg); | |
81255565 | 1589 | |
bed4a673 | 1590 | intel_update_fbc(dev); |
3dec0095 | 1591 | intel_increase_pllclock(crtc); |
81255565 JB |
1592 | |
1593 | return 0; | |
1594 | } | |
1595 | ||
5c3b82e2 | 1596 | static int |
3c4fdcfb KH |
1597 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1598 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1599 | { |
1600 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1601 | struct drm_i915_master_private *master_priv; |
1602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 1603 | int ret; |
79e53945 JB |
1604 | |
1605 | /* no fb bound */ | |
1606 | if (!crtc->fb) { | |
28c97730 | 1607 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
1608 | return 0; |
1609 | } | |
1610 | ||
265db958 | 1611 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
1612 | case 0: |
1613 | case 1: | |
1614 | break; | |
1615 | default: | |
5c3b82e2 | 1616 | return -EINVAL; |
79e53945 JB |
1617 | } |
1618 | ||
5c3b82e2 | 1619 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
1620 | ret = intel_pin_and_fence_fb_obj(dev, |
1621 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 1622 | NULL); |
5c3b82e2 CW |
1623 | if (ret != 0) { |
1624 | mutex_unlock(&dev->struct_mutex); | |
1625 | return ret; | |
1626 | } | |
79e53945 | 1627 | |
265db958 | 1628 | if (old_fb) { |
e6c3a2a6 | 1629 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1630 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 1631 | |
e6c3a2a6 | 1632 | wait_event(dev_priv->pending_flip_queue, |
05394f39 | 1633 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
1634 | |
1635 | /* Big Hammer, we also need to ensure that any pending | |
1636 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
1637 | * current scanout is retired before unpinning the old | |
1638 | * framebuffer. | |
1639 | */ | |
05394f39 | 1640 | ret = i915_gem_object_flush_gpu(obj, false); |
85345517 CW |
1641 | if (ret) { |
1642 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
1643 | mutex_unlock(&dev->struct_mutex); | |
1644 | return ret; | |
1645 | } | |
265db958 CW |
1646 | } |
1647 | ||
21c74a8e JW |
1648 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
1649 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 1650 | if (ret) { |
265db958 | 1651 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 1652 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 1653 | return ret; |
79e53945 | 1654 | } |
3c4fdcfb | 1655 | |
b7f1de28 CW |
1656 | if (old_fb) { |
1657 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
265db958 | 1658 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 1659 | } |
652c393a | 1660 | |
5c3b82e2 | 1661 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1662 | |
1663 | if (!dev->primary->master) | |
5c3b82e2 | 1664 | return 0; |
79e53945 JB |
1665 | |
1666 | master_priv = dev->primary->master->driver_priv; | |
1667 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1668 | return 0; |
79e53945 | 1669 | |
265db958 | 1670 | if (intel_crtc->pipe) { |
79e53945 JB |
1671 | master_priv->sarea_priv->pipeB_x = x; |
1672 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1673 | } else { |
1674 | master_priv->sarea_priv->pipeA_x = x; | |
1675 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1676 | } |
5c3b82e2 CW |
1677 | |
1678 | return 0; | |
79e53945 JB |
1679 | } |
1680 | ||
5eddb70b | 1681 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1682 | { |
1683 | struct drm_device *dev = crtc->dev; | |
1684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1685 | u32 dpa_ctl; | |
1686 | ||
28c97730 | 1687 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1688 | dpa_ctl = I915_READ(DP_A); |
1689 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1690 | ||
1691 | if (clock < 200000) { | |
1692 | u32 temp; | |
1693 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1694 | /* workaround for 160Mhz: | |
1695 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1696 | 2) program 0x46010 bit 0 = 1 | |
1697 | 3) program 0x46034 bit 24 = 1 | |
1698 | 4) program 0x64000 bit 14 = 1 | |
1699 | */ | |
1700 | temp = I915_READ(0x4600c); | |
1701 | temp &= 0xffff0000; | |
1702 | I915_WRITE(0x4600c, temp | 0x8124); | |
1703 | ||
1704 | temp = I915_READ(0x46010); | |
1705 | I915_WRITE(0x46010, temp | 1); | |
1706 | ||
1707 | temp = I915_READ(0x46034); | |
1708 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1709 | } else { | |
1710 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1711 | } | |
1712 | I915_WRITE(DP_A, dpa_ctl); | |
1713 | ||
5eddb70b | 1714 | POSTING_READ(DP_A); |
32f9d658 ZW |
1715 | udelay(500); |
1716 | } | |
1717 | ||
5e84e1a4 ZW |
1718 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
1719 | { | |
1720 | struct drm_device *dev = crtc->dev; | |
1721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1723 | int pipe = intel_crtc->pipe; | |
1724 | u32 reg, temp; | |
1725 | ||
1726 | /* enable normal train */ | |
1727 | reg = FDI_TX_CTL(pipe); | |
1728 | temp = I915_READ(reg); | |
1729 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1730 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
1731 | I915_WRITE(reg, temp); | |
1732 | ||
1733 | reg = FDI_RX_CTL(pipe); | |
1734 | temp = I915_READ(reg); | |
1735 | if (HAS_PCH_CPT(dev)) { | |
1736 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1737 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
1738 | } else { | |
1739 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1740 | temp |= FDI_LINK_TRAIN_NONE; | |
1741 | } | |
1742 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1743 | ||
1744 | /* wait one idle pattern time */ | |
1745 | POSTING_READ(reg); | |
1746 | udelay(1000); | |
1747 | } | |
1748 | ||
8db9d77b ZW |
1749 | /* The FDI link training functions for ILK/Ibexpeak. */ |
1750 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
1751 | { | |
1752 | struct drm_device *dev = crtc->dev; | |
1753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1754 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1755 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1756 | u32 reg, temp, tries; |
8db9d77b | 1757 | |
e1a44743 AJ |
1758 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1759 | for train result */ | |
5eddb70b CW |
1760 | reg = FDI_RX_IMR(pipe); |
1761 | temp = I915_READ(reg); | |
e1a44743 AJ |
1762 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1763 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1764 | I915_WRITE(reg, temp); |
1765 | I915_READ(reg); | |
e1a44743 AJ |
1766 | udelay(150); |
1767 | ||
8db9d77b | 1768 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1769 | reg = FDI_TX_CTL(pipe); |
1770 | temp = I915_READ(reg); | |
77ffb597 AJ |
1771 | temp &= ~(7 << 19); |
1772 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1773 | temp &= ~FDI_LINK_TRAIN_NONE; |
1774 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 1775 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1776 | |
5eddb70b CW |
1777 | reg = FDI_RX_CTL(pipe); |
1778 | temp = I915_READ(reg); | |
8db9d77b ZW |
1779 | temp &= ~FDI_LINK_TRAIN_NONE; |
1780 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
1781 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1782 | ||
1783 | POSTING_READ(reg); | |
8db9d77b ZW |
1784 | udelay(150); |
1785 | ||
5b2adf89 JB |
1786 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
1787 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE); | |
1788 | ||
5eddb70b | 1789 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1790 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1791 | temp = I915_READ(reg); |
8db9d77b ZW |
1792 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1793 | ||
1794 | if ((temp & FDI_RX_BIT_LOCK)) { | |
1795 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 1796 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1797 | break; |
1798 | } | |
8db9d77b | 1799 | } |
e1a44743 | 1800 | if (tries == 5) |
5eddb70b | 1801 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1802 | |
1803 | /* Train 2 */ | |
5eddb70b CW |
1804 | reg = FDI_TX_CTL(pipe); |
1805 | temp = I915_READ(reg); | |
8db9d77b ZW |
1806 | temp &= ~FDI_LINK_TRAIN_NONE; |
1807 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1808 | I915_WRITE(reg, temp); |
8db9d77b | 1809 | |
5eddb70b CW |
1810 | reg = FDI_RX_CTL(pipe); |
1811 | temp = I915_READ(reg); | |
8db9d77b ZW |
1812 | temp &= ~FDI_LINK_TRAIN_NONE; |
1813 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1814 | I915_WRITE(reg, temp); |
8db9d77b | 1815 | |
5eddb70b CW |
1816 | POSTING_READ(reg); |
1817 | udelay(150); | |
8db9d77b | 1818 | |
5eddb70b | 1819 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1820 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1821 | temp = I915_READ(reg); |
8db9d77b ZW |
1822 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1823 | ||
1824 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1825 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1826 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1827 | break; | |
1828 | } | |
8db9d77b | 1829 | } |
e1a44743 | 1830 | if (tries == 5) |
5eddb70b | 1831 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1832 | |
1833 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 1834 | |
8db9d77b ZW |
1835 | } |
1836 | ||
5eddb70b | 1837 | static const int const snb_b_fdi_train_param [] = { |
8db9d77b ZW |
1838 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
1839 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
1840 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
1841 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
1842 | }; | |
1843 | ||
1844 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
1845 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
1846 | { | |
1847 | struct drm_device *dev = crtc->dev; | |
1848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1850 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1851 | u32 reg, temp, i; |
8db9d77b | 1852 | |
e1a44743 AJ |
1853 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1854 | for train result */ | |
5eddb70b CW |
1855 | reg = FDI_RX_IMR(pipe); |
1856 | temp = I915_READ(reg); | |
e1a44743 AJ |
1857 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1858 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1859 | I915_WRITE(reg, temp); |
1860 | ||
1861 | POSTING_READ(reg); | |
e1a44743 AJ |
1862 | udelay(150); |
1863 | ||
8db9d77b | 1864 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1865 | reg = FDI_TX_CTL(pipe); |
1866 | temp = I915_READ(reg); | |
77ffb597 AJ |
1867 | temp &= ~(7 << 19); |
1868 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1869 | temp &= ~FDI_LINK_TRAIN_NONE; |
1870 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1871 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1872 | /* SNB-B */ | |
1873 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 1874 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1875 | |
5eddb70b CW |
1876 | reg = FDI_RX_CTL(pipe); |
1877 | temp = I915_READ(reg); | |
8db9d77b ZW |
1878 | if (HAS_PCH_CPT(dev)) { |
1879 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1880 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
1881 | } else { | |
1882 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1883 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1884 | } | |
5eddb70b CW |
1885 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1886 | ||
1887 | POSTING_READ(reg); | |
8db9d77b ZW |
1888 | udelay(150); |
1889 | ||
8db9d77b | 1890 | for (i = 0; i < 4; i++ ) { |
5eddb70b CW |
1891 | reg = FDI_TX_CTL(pipe); |
1892 | temp = I915_READ(reg); | |
8db9d77b ZW |
1893 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1894 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1895 | I915_WRITE(reg, temp); |
1896 | ||
1897 | POSTING_READ(reg); | |
8db9d77b ZW |
1898 | udelay(500); |
1899 | ||
5eddb70b CW |
1900 | reg = FDI_RX_IIR(pipe); |
1901 | temp = I915_READ(reg); | |
8db9d77b ZW |
1902 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1903 | ||
1904 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 1905 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1906 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
1907 | break; | |
1908 | } | |
1909 | } | |
1910 | if (i == 4) | |
5eddb70b | 1911 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1912 | |
1913 | /* Train 2 */ | |
5eddb70b CW |
1914 | reg = FDI_TX_CTL(pipe); |
1915 | temp = I915_READ(reg); | |
8db9d77b ZW |
1916 | temp &= ~FDI_LINK_TRAIN_NONE; |
1917 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1918 | if (IS_GEN6(dev)) { | |
1919 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1920 | /* SNB-B */ | |
1921 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
1922 | } | |
5eddb70b | 1923 | I915_WRITE(reg, temp); |
8db9d77b | 1924 | |
5eddb70b CW |
1925 | reg = FDI_RX_CTL(pipe); |
1926 | temp = I915_READ(reg); | |
8db9d77b ZW |
1927 | if (HAS_PCH_CPT(dev)) { |
1928 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1929 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
1930 | } else { | |
1931 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1932 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1933 | } | |
5eddb70b CW |
1934 | I915_WRITE(reg, temp); |
1935 | ||
1936 | POSTING_READ(reg); | |
8db9d77b ZW |
1937 | udelay(150); |
1938 | ||
1939 | for (i = 0; i < 4; i++ ) { | |
5eddb70b CW |
1940 | reg = FDI_TX_CTL(pipe); |
1941 | temp = I915_READ(reg); | |
8db9d77b ZW |
1942 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1943 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1944 | I915_WRITE(reg, temp); |
1945 | ||
1946 | POSTING_READ(reg); | |
8db9d77b ZW |
1947 | udelay(500); |
1948 | ||
5eddb70b CW |
1949 | reg = FDI_RX_IIR(pipe); |
1950 | temp = I915_READ(reg); | |
8db9d77b ZW |
1951 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1952 | ||
1953 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1954 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1955 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1956 | break; | |
1957 | } | |
1958 | } | |
1959 | if (i == 4) | |
5eddb70b | 1960 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1961 | |
1962 | DRM_DEBUG_KMS("FDI train done.\n"); | |
1963 | } | |
1964 | ||
0e23b99d | 1965 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
2c07245f ZW |
1966 | { |
1967 | struct drm_device *dev = crtc->dev; | |
1968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1969 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1970 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1971 | u32 reg, temp; |
79e53945 | 1972 | |
c64e311e | 1973 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
1974 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
1975 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 1976 | |
c98e9dcf | 1977 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
1978 | reg = FDI_RX_CTL(pipe); |
1979 | temp = I915_READ(reg); | |
1980 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 1981 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
1982 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
1983 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
1984 | ||
1985 | POSTING_READ(reg); | |
c98e9dcf JB |
1986 | udelay(200); |
1987 | ||
1988 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
1989 | temp = I915_READ(reg); |
1990 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
1991 | ||
1992 | POSTING_READ(reg); | |
c98e9dcf JB |
1993 | udelay(200); |
1994 | ||
1995 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
1996 | reg = FDI_TX_CTL(pipe); |
1997 | temp = I915_READ(reg); | |
c98e9dcf | 1998 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
1999 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2000 | ||
2001 | POSTING_READ(reg); | |
c98e9dcf | 2002 | udelay(100); |
6be4a607 | 2003 | } |
0e23b99d JB |
2004 | } |
2005 | ||
5eddb70b CW |
2006 | static void intel_flush_display_plane(struct drm_device *dev, |
2007 | int plane) | |
2008 | { | |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2010 | u32 reg = DSPADDR(plane); | |
2011 | I915_WRITE(reg, I915_READ(reg)); | |
2012 | } | |
2013 | ||
6b383a7f CW |
2014 | /* |
2015 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2016 | * to avoid hanging the ring, which we assume we are waiting on. | |
2017 | */ | |
2018 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2019 | { | |
2020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2021 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2022 | u32 tmp; |
2023 | ||
2024 | if (IS_GEN2(dev)) | |
2025 | /* Can't break the hang on i8xx */ | |
2026 | return; | |
2027 | ||
1ec14ad3 | 2028 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2029 | tmp = I915_READ_CTL(ring); |
2030 | if (tmp & RING_WAIT) | |
2031 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2032 | } |
2033 | ||
e6c3a2a6 CW |
2034 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2035 | { | |
05394f39 | 2036 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2037 | struct drm_i915_private *dev_priv; |
2038 | ||
2039 | if (crtc->fb == NULL) | |
2040 | return; | |
2041 | ||
05394f39 | 2042 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2043 | dev_priv = crtc->dev->dev_private; |
2044 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2045 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2046 | } |
2047 | ||
0e23b99d JB |
2048 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
2049 | { | |
2050 | struct drm_device *dev = crtc->dev; | |
2051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2053 | int pipe = intel_crtc->pipe; | |
2054 | int plane = intel_crtc->plane; | |
5eddb70b | 2055 | u32 reg, temp; |
0e23b99d | 2056 | |
f7abfe8b CW |
2057 | if (intel_crtc->active) |
2058 | return; | |
2059 | ||
2060 | intel_crtc->active = true; | |
6b383a7f CW |
2061 | intel_update_watermarks(dev); |
2062 | ||
0e23b99d JB |
2063 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2064 | temp = I915_READ(PCH_LVDS); | |
5eddb70b | 2065 | if ((temp & LVDS_PORT_EN) == 0) |
0e23b99d | 2066 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
0e23b99d JB |
2067 | } |
2068 | ||
2069 | ironlake_fdi_enable(crtc); | |
2c07245f | 2070 | |
6be4a607 JB |
2071 | /* Enable panel fitting for LVDS */ |
2072 | if (dev_priv->pch_pf_size && | |
1d850362 | 2073 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
6be4a607 JB |
2074 | /* Force use of hard-coded filter coefficients |
2075 | * as some pre-programmed values are broken, | |
2076 | * e.g. x201. | |
2077 | */ | |
2078 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, | |
2079 | PF_ENABLE | PF_FILTER_MED_3x3); | |
2080 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, | |
2081 | dev_priv->pch_pf_pos); | |
2082 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, | |
2083 | dev_priv->pch_pf_size); | |
2084 | } | |
2c07245f | 2085 | |
6be4a607 | 2086 | /* Enable CPU pipe */ |
5eddb70b CW |
2087 | reg = PIPECONF(pipe); |
2088 | temp = I915_READ(reg); | |
2089 | if ((temp & PIPECONF_ENABLE) == 0) { | |
2090 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
2091 | POSTING_READ(reg); | |
17f6766c | 2092 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
6be4a607 | 2093 | } |
2c07245f | 2094 | |
6be4a607 | 2095 | /* configure and enable CPU plane */ |
5eddb70b CW |
2096 | reg = DSPCNTR(plane); |
2097 | temp = I915_READ(reg); | |
6be4a607 | 2098 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2099 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2100 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2101 | } |
2c07245f | 2102 | |
c98e9dcf JB |
2103 | /* For PCH output, training FDI link */ |
2104 | if (IS_GEN6(dev)) | |
2105 | gen6_fdi_link_train(crtc); | |
2106 | else | |
2107 | ironlake_fdi_link_train(crtc); | |
2c07245f | 2108 | |
c98e9dcf | 2109 | /* enable PCH DPLL */ |
5eddb70b CW |
2110 | reg = PCH_DPLL(pipe); |
2111 | temp = I915_READ(reg); | |
c98e9dcf | 2112 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2113 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
2114 | POSTING_READ(reg); | |
8c4223be | 2115 | udelay(200); |
c98e9dcf | 2116 | } |
8db9d77b | 2117 | |
c98e9dcf JB |
2118 | if (HAS_PCH_CPT(dev)) { |
2119 | /* Be sure PCH DPLL SEL is set */ | |
2120 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2121 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2122 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2123 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2124 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2125 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2126 | } |
5eddb70b | 2127 | |
c98e9dcf | 2128 | /* set transcoder timing */ |
5eddb70b CW |
2129 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2130 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2131 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2132 | |
5eddb70b CW |
2133 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2134 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2135 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2136 | |
5e84e1a4 ZW |
2137 | intel_fdi_normal_train(crtc); |
2138 | ||
c98e9dcf JB |
2139 | /* For PCH DP, enable TRANS_DP_CTL */ |
2140 | if (HAS_PCH_CPT(dev) && | |
2141 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5eddb70b CW |
2142 | reg = TRANS_DP_CTL(pipe); |
2143 | temp = I915_READ(reg); | |
2144 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2145 | TRANS_DP_SYNC_MASK | |
2146 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2147 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2148 | TRANS_DP_ENH_FRAMING); | |
220cad3c | 2149 | temp |= TRANS_DP_8BPC; |
c98e9dcf JB |
2150 | |
2151 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2152 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2153 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2154 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2155 | |
2156 | switch (intel_trans_dp_port_sel(crtc)) { | |
2157 | case PCH_DP_B: | |
5eddb70b | 2158 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2159 | break; |
2160 | case PCH_DP_C: | |
5eddb70b | 2161 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2162 | break; |
2163 | case PCH_DP_D: | |
5eddb70b | 2164 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2165 | break; |
2166 | default: | |
2167 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2168 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2169 | break; |
32f9d658 | 2170 | } |
2c07245f | 2171 | |
5eddb70b | 2172 | I915_WRITE(reg, temp); |
6be4a607 | 2173 | } |
b52eb4dc | 2174 | |
c98e9dcf | 2175 | /* enable PCH transcoder */ |
5eddb70b CW |
2176 | reg = TRANSCONF(pipe); |
2177 | temp = I915_READ(reg); | |
c98e9dcf JB |
2178 | /* |
2179 | * make the BPC in transcoder be consistent with | |
2180 | * that in pipeconf reg. | |
2181 | */ | |
2182 | temp &= ~PIPE_BPC_MASK; | |
5eddb70b CW |
2183 | temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; |
2184 | I915_WRITE(reg, temp | TRANS_ENABLE); | |
2185 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
17f6766c | 2186 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
c98e9dcf | 2187 | |
6be4a607 | 2188 | intel_crtc_load_lut(crtc); |
bed4a673 | 2189 | intel_update_fbc(dev); |
6b383a7f | 2190 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2191 | } |
2192 | ||
2193 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2194 | { | |
2195 | struct drm_device *dev = crtc->dev; | |
2196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2198 | int pipe = intel_crtc->pipe; | |
2199 | int plane = intel_crtc->plane; | |
5eddb70b | 2200 | u32 reg, temp; |
b52eb4dc | 2201 | |
f7abfe8b CW |
2202 | if (!intel_crtc->active) |
2203 | return; | |
2204 | ||
e6c3a2a6 | 2205 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 2206 | drm_vblank_off(dev, pipe); |
6b383a7f | 2207 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2208 | |
6be4a607 | 2209 | /* Disable display plane */ |
5eddb70b CW |
2210 | reg = DSPCNTR(plane); |
2211 | temp = I915_READ(reg); | |
2212 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2213 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
2214 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2215 | } |
913d8d11 | 2216 | |
6be4a607 JB |
2217 | if (dev_priv->cfb_plane == plane && |
2218 | dev_priv->display.disable_fbc) | |
2219 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2220 | |
6be4a607 | 2221 | /* disable cpu pipe, disable after all planes disabled */ |
5eddb70b CW |
2222 | reg = PIPECONF(pipe); |
2223 | temp = I915_READ(reg); | |
2224 | if (temp & PIPECONF_ENABLE) { | |
2225 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
17f6766c | 2226 | POSTING_READ(reg); |
6be4a607 | 2227 | /* wait for cpu pipe off, pipe state */ |
17f6766c | 2228 | intel_wait_for_pipe_off(dev, intel_crtc->pipe); |
5eddb70b | 2229 | } |
32f9d658 | 2230 | |
6be4a607 JB |
2231 | /* Disable PF */ |
2232 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); | |
2233 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); | |
2c07245f | 2234 | |
6be4a607 | 2235 | /* disable CPU FDI tx and PCH FDI rx */ |
5eddb70b CW |
2236 | reg = FDI_TX_CTL(pipe); |
2237 | temp = I915_READ(reg); | |
2238 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2239 | POSTING_READ(reg); | |
249c0e64 | 2240 | |
5eddb70b CW |
2241 | reg = FDI_RX_CTL(pipe); |
2242 | temp = I915_READ(reg); | |
2243 | temp &= ~(0x7 << 16); | |
2244 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2245 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
6be4a607 | 2246 | |
5eddb70b | 2247 | POSTING_READ(reg); |
6be4a607 JB |
2248 | udelay(100); |
2249 | ||
5b2adf89 | 2250 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
e07ac3a0 ZW |
2251 | if (HAS_PCH_IBX(dev)) |
2252 | I915_WRITE(FDI_RX_CHICKEN(pipe), | |
2253 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
2254 | ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); | |
5b2adf89 | 2255 | |
6be4a607 | 2256 | /* still set train pattern 1 */ |
5eddb70b CW |
2257 | reg = FDI_TX_CTL(pipe); |
2258 | temp = I915_READ(reg); | |
6be4a607 JB |
2259 | temp &= ~FDI_LINK_TRAIN_NONE; |
2260 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2261 | I915_WRITE(reg, temp); |
6be4a607 | 2262 | |
5eddb70b CW |
2263 | reg = FDI_RX_CTL(pipe); |
2264 | temp = I915_READ(reg); | |
6be4a607 JB |
2265 | if (HAS_PCH_CPT(dev)) { |
2266 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2267 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2268 | } else { | |
2c07245f ZW |
2269 | temp &= ~FDI_LINK_TRAIN_NONE; |
2270 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
6be4a607 | 2271 | } |
5eddb70b CW |
2272 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2273 | temp &= ~(0x07 << 16); | |
2274 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2275 | I915_WRITE(reg, temp); | |
2c07245f | 2276 | |
5eddb70b | 2277 | POSTING_READ(reg); |
6be4a607 | 2278 | udelay(100); |
2c07245f | 2279 | |
6be4a607 JB |
2280 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2281 | temp = I915_READ(PCH_LVDS); | |
5eddb70b CW |
2282 | if (temp & LVDS_PORT_EN) { |
2283 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); | |
2284 | POSTING_READ(PCH_LVDS); | |
2285 | udelay(100); | |
2286 | } | |
6be4a607 | 2287 | } |
249c0e64 | 2288 | |
6be4a607 | 2289 | /* disable PCH transcoder */ |
5eddb70b CW |
2290 | reg = TRANSCONF(plane); |
2291 | temp = I915_READ(reg); | |
2292 | if (temp & TRANS_ENABLE) { | |
2293 | I915_WRITE(reg, temp & ~TRANS_ENABLE); | |
6be4a607 | 2294 | /* wait for PCH transcoder off, transcoder state */ |
5eddb70b | 2295 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
6be4a607 JB |
2296 | DRM_ERROR("failed to disable transcoder\n"); |
2297 | } | |
913d8d11 | 2298 | |
6be4a607 JB |
2299 | if (HAS_PCH_CPT(dev)) { |
2300 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2301 | reg = TRANS_DP_CTL(pipe); |
2302 | temp = I915_READ(reg); | |
2303 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
2304 | I915_WRITE(reg, temp); | |
6be4a607 JB |
2305 | |
2306 | /* disable DPLL_SEL */ | |
2307 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2308 | if (pipe == 0) |
6be4a607 JB |
2309 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
2310 | else | |
2311 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
2312 | I915_WRITE(PCH_DPLL_SEL, temp); | |
6be4a607 | 2313 | } |
e3421a18 | 2314 | |
6be4a607 | 2315 | /* disable PCH DPLL */ |
5eddb70b CW |
2316 | reg = PCH_DPLL(pipe); |
2317 | temp = I915_READ(reg); | |
2318 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
8db9d77b | 2319 | |
6be4a607 | 2320 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2321 | reg = FDI_RX_CTL(pipe); |
2322 | temp = I915_READ(reg); | |
2323 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2324 | |
6be4a607 | 2325 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2326 | reg = FDI_TX_CTL(pipe); |
2327 | temp = I915_READ(reg); | |
2328 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2329 | ||
2330 | POSTING_READ(reg); | |
6be4a607 | 2331 | udelay(100); |
8db9d77b | 2332 | |
5eddb70b CW |
2333 | reg = FDI_RX_CTL(pipe); |
2334 | temp = I915_READ(reg); | |
2335 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2336 | |
6be4a607 | 2337 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2338 | POSTING_READ(reg); |
6be4a607 | 2339 | udelay(100); |
6b383a7f | 2340 | |
f7abfe8b | 2341 | intel_crtc->active = false; |
6b383a7f CW |
2342 | intel_update_watermarks(dev); |
2343 | intel_update_fbc(dev); | |
2344 | intel_clear_scanline_wait(dev); | |
6be4a607 | 2345 | } |
1b3c7a47 | 2346 | |
6be4a607 JB |
2347 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2348 | { | |
2349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2350 | int pipe = intel_crtc->pipe; | |
2351 | int plane = intel_crtc->plane; | |
8db9d77b | 2352 | |
6be4a607 JB |
2353 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2354 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2355 | */ | |
2356 | switch (mode) { | |
2357 | case DRM_MODE_DPMS_ON: | |
2358 | case DRM_MODE_DPMS_STANDBY: | |
2359 | case DRM_MODE_DPMS_SUSPEND: | |
2360 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2361 | ironlake_crtc_enable(crtc); | |
2362 | break; | |
1b3c7a47 | 2363 | |
6be4a607 JB |
2364 | case DRM_MODE_DPMS_OFF: |
2365 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2366 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2367 | break; |
2368 | } | |
2369 | } | |
2370 | ||
02e792fb DV |
2371 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2372 | { | |
02e792fb | 2373 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2374 | struct drm_device *dev = intel_crtc->base.dev; |
03f77ea5 | 2375 | |
23f09ce3 CW |
2376 | mutex_lock(&dev->struct_mutex); |
2377 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); | |
2378 | mutex_unlock(&dev->struct_mutex); | |
02e792fb | 2379 | } |
02e792fb | 2380 | |
5dcdbcb0 CW |
2381 | /* Let userspace switch the overlay on again. In most cases userspace |
2382 | * has to recompute where to put it anyway. | |
2383 | */ | |
02e792fb DV |
2384 | } |
2385 | ||
0b8765c6 | 2386 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2387 | { |
2388 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2389 | struct drm_i915_private *dev_priv = dev->dev_private; |
2390 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2391 | int pipe = intel_crtc->pipe; | |
80824003 | 2392 | int plane = intel_crtc->plane; |
5eddb70b | 2393 | u32 reg, temp; |
79e53945 | 2394 | |
f7abfe8b CW |
2395 | if (intel_crtc->active) |
2396 | return; | |
2397 | ||
2398 | intel_crtc->active = true; | |
6b383a7f CW |
2399 | intel_update_watermarks(dev); |
2400 | ||
0b8765c6 | 2401 | /* Enable the DPLL */ |
5eddb70b CW |
2402 | reg = DPLL(pipe); |
2403 | temp = I915_READ(reg); | |
0b8765c6 | 2404 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2405 | I915_WRITE(reg, temp); |
2406 | ||
0b8765c6 | 2407 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2408 | POSTING_READ(reg); |
0b8765c6 | 2409 | udelay(150); |
5eddb70b CW |
2410 | |
2411 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2412 | ||
0b8765c6 | 2413 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2414 | POSTING_READ(reg); |
0b8765c6 | 2415 | udelay(150); |
5eddb70b CW |
2416 | |
2417 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2418 | ||
0b8765c6 | 2419 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2420 | POSTING_READ(reg); |
0b8765c6 JB |
2421 | udelay(150); |
2422 | } | |
79e53945 | 2423 | |
0b8765c6 | 2424 | /* Enable the pipe */ |
5eddb70b CW |
2425 | reg = PIPECONF(pipe); |
2426 | temp = I915_READ(reg); | |
2427 | if ((temp & PIPECONF_ENABLE) == 0) | |
2428 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
79e53945 | 2429 | |
0b8765c6 | 2430 | /* Enable the plane */ |
5eddb70b CW |
2431 | reg = DSPCNTR(plane); |
2432 | temp = I915_READ(reg); | |
0b8765c6 | 2433 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2434 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2435 | intel_flush_display_plane(dev, plane); | |
0b8765c6 | 2436 | } |
79e53945 | 2437 | |
0b8765c6 | 2438 | intel_crtc_load_lut(crtc); |
bed4a673 | 2439 | intel_update_fbc(dev); |
79e53945 | 2440 | |
0b8765c6 JB |
2441 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2442 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 2443 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 2444 | } |
79e53945 | 2445 | |
0b8765c6 JB |
2446 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2447 | { | |
2448 | struct drm_device *dev = crtc->dev; | |
2449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2450 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2451 | int pipe = intel_crtc->pipe; | |
2452 | int plane = intel_crtc->plane; | |
5eddb70b | 2453 | u32 reg, temp; |
b690e96c | 2454 | |
f7abfe8b CW |
2455 | if (!intel_crtc->active) |
2456 | return; | |
2457 | ||
0b8765c6 | 2458 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
2459 | intel_crtc_wait_for_pending_flips(crtc); |
2460 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 2461 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 2462 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 JB |
2463 | |
2464 | if (dev_priv->cfb_plane == plane && | |
2465 | dev_priv->display.disable_fbc) | |
2466 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 2467 | |
0b8765c6 | 2468 | /* Disable display plane */ |
5eddb70b CW |
2469 | reg = DSPCNTR(plane); |
2470 | temp = I915_READ(reg); | |
2471 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2472 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
0b8765c6 | 2473 | /* Flush the plane changes */ |
5eddb70b | 2474 | intel_flush_display_plane(dev, plane); |
0b8765c6 | 2475 | |
0b8765c6 | 2476 | /* Wait for vblank for the disable to take effect */ |
a6c45cf0 | 2477 | if (IS_GEN2(dev)) |
ab7ad7f6 | 2478 | intel_wait_for_vblank(dev, pipe); |
0b8765c6 | 2479 | } |
79e53945 | 2480 | |
0b8765c6 | 2481 | /* Don't disable pipe A or pipe A PLLs if needed */ |
5eddb70b | 2482 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
6b383a7f | 2483 | goto done; |
0b8765c6 JB |
2484 | |
2485 | /* Next, disable display pipes */ | |
5eddb70b CW |
2486 | reg = PIPECONF(pipe); |
2487 | temp = I915_READ(reg); | |
2488 | if (temp & PIPECONF_ENABLE) { | |
2489 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
2490 | ||
ab7ad7f6 | 2491 | /* Wait for the pipe to turn off */ |
5eddb70b | 2492 | POSTING_READ(reg); |
ab7ad7f6 | 2493 | intel_wait_for_pipe_off(dev, pipe); |
0b8765c6 JB |
2494 | } |
2495 | ||
5eddb70b CW |
2496 | reg = DPLL(pipe); |
2497 | temp = I915_READ(reg); | |
2498 | if (temp & DPLL_VCO_ENABLE) { | |
2499 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
0b8765c6 | 2500 | |
5eddb70b CW |
2501 | /* Wait for the clocks to turn off. */ |
2502 | POSTING_READ(reg); | |
2503 | udelay(150); | |
0b8765c6 | 2504 | } |
6b383a7f CW |
2505 | |
2506 | done: | |
f7abfe8b | 2507 | intel_crtc->active = false; |
6b383a7f CW |
2508 | intel_update_fbc(dev); |
2509 | intel_update_watermarks(dev); | |
2510 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
2511 | } |
2512 | ||
2513 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2514 | { | |
2515 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2516 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2517 | */ | |
2518 | switch (mode) { | |
2519 | case DRM_MODE_DPMS_ON: | |
2520 | case DRM_MODE_DPMS_STANDBY: | |
2521 | case DRM_MODE_DPMS_SUSPEND: | |
2522 | i9xx_crtc_enable(crtc); | |
2523 | break; | |
2524 | case DRM_MODE_DPMS_OFF: | |
2525 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2526 | break; |
2527 | } | |
2c07245f ZW |
2528 | } |
2529 | ||
2530 | /** | |
2531 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2532 | */ |
2533 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2534 | { | |
2535 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2536 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2537 | struct drm_i915_master_private *master_priv; |
2538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2539 | int pipe = intel_crtc->pipe; | |
2540 | bool enabled; | |
2541 | ||
032d2a0d CW |
2542 | if (intel_crtc->dpms_mode == mode) |
2543 | return; | |
2544 | ||
65655d4a | 2545 | intel_crtc->dpms_mode = mode; |
debcaddc | 2546 | |
e70236a8 | 2547 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
2548 | |
2549 | if (!dev->primary->master) | |
2550 | return; | |
2551 | ||
2552 | master_priv = dev->primary->master->driver_priv; | |
2553 | if (!master_priv->sarea_priv) | |
2554 | return; | |
2555 | ||
2556 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2557 | ||
2558 | switch (pipe) { | |
2559 | case 0: | |
2560 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2561 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2562 | break; | |
2563 | case 1: | |
2564 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2565 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2566 | break; | |
2567 | default: | |
2568 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
2569 | break; | |
2570 | } | |
79e53945 JB |
2571 | } |
2572 | ||
cdd59983 CW |
2573 | static void intel_crtc_disable(struct drm_crtc *crtc) |
2574 | { | |
2575 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2576 | struct drm_device *dev = crtc->dev; | |
2577 | ||
2578 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
2579 | ||
2580 | if (crtc->fb) { | |
2581 | mutex_lock(&dev->struct_mutex); | |
2582 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
2583 | mutex_unlock(&dev->struct_mutex); | |
2584 | } | |
2585 | } | |
2586 | ||
7e7d76c3 JB |
2587 | /* Prepare for a mode set. |
2588 | * | |
2589 | * Note we could be a lot smarter here. We need to figure out which outputs | |
2590 | * will be enabled, which disabled (in short, how the config will changes) | |
2591 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
2592 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
2593 | * panel fitting is in the proper state, etc. | |
2594 | */ | |
2595 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 2596 | { |
7e7d76c3 | 2597 | i9xx_crtc_disable(crtc); |
79e53945 JB |
2598 | } |
2599 | ||
7e7d76c3 | 2600 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 2601 | { |
7e7d76c3 | 2602 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
2603 | } |
2604 | ||
2605 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
2606 | { | |
7e7d76c3 | 2607 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
2608 | } |
2609 | ||
2610 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
2611 | { | |
7e7d76c3 | 2612 | ironlake_crtc_enable(crtc); |
79e53945 JB |
2613 | } |
2614 | ||
2615 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
2616 | { | |
2617 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2618 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
2619 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
2620 | } | |
2621 | ||
2622 | void intel_encoder_commit (struct drm_encoder *encoder) | |
2623 | { | |
2624 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2625 | /* lvds has its own version of commit see intel_lvds_commit */ | |
2626 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2627 | } | |
2628 | ||
ea5b213a CW |
2629 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2630 | { | |
4ef69c7a | 2631 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 2632 | |
ea5b213a CW |
2633 | drm_encoder_cleanup(encoder); |
2634 | kfree(intel_encoder); | |
2635 | } | |
2636 | ||
79e53945 JB |
2637 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
2638 | struct drm_display_mode *mode, | |
2639 | struct drm_display_mode *adjusted_mode) | |
2640 | { | |
2c07245f | 2641 | struct drm_device *dev = crtc->dev; |
89749350 | 2642 | |
bad720ff | 2643 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 2644 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
2645 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
2646 | return false; | |
2c07245f | 2647 | } |
89749350 CW |
2648 | |
2649 | /* XXX some encoders set the crtcinfo, others don't. | |
2650 | * Obviously we need some form of conflict resolution here... | |
2651 | */ | |
2652 | if (adjusted_mode->crtc_htotal == 0) | |
2653 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
2654 | ||
79e53945 JB |
2655 | return true; |
2656 | } | |
2657 | ||
e70236a8 JB |
2658 | static int i945_get_display_clock_speed(struct drm_device *dev) |
2659 | { | |
2660 | return 400000; | |
2661 | } | |
79e53945 | 2662 | |
e70236a8 | 2663 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 2664 | { |
e70236a8 JB |
2665 | return 333000; |
2666 | } | |
79e53945 | 2667 | |
e70236a8 JB |
2668 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
2669 | { | |
2670 | return 200000; | |
2671 | } | |
79e53945 | 2672 | |
e70236a8 JB |
2673 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
2674 | { | |
2675 | u16 gcfgc = 0; | |
79e53945 | 2676 | |
e70236a8 JB |
2677 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
2678 | ||
2679 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
2680 | return 133000; | |
2681 | else { | |
2682 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
2683 | case GC_DISPLAY_CLOCK_333_MHZ: | |
2684 | return 333000; | |
2685 | default: | |
2686 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
2687 | return 190000; | |
79e53945 | 2688 | } |
e70236a8 JB |
2689 | } |
2690 | } | |
2691 | ||
2692 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
2693 | { | |
2694 | return 266000; | |
2695 | } | |
2696 | ||
2697 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
2698 | { | |
2699 | u16 hpllcc = 0; | |
2700 | /* Assume that the hardware is in the high speed state. This | |
2701 | * should be the default. | |
2702 | */ | |
2703 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
2704 | case GC_CLOCK_133_200: | |
2705 | case GC_CLOCK_100_200: | |
2706 | return 200000; | |
2707 | case GC_CLOCK_166_250: | |
2708 | return 250000; | |
2709 | case GC_CLOCK_100_133: | |
79e53945 | 2710 | return 133000; |
e70236a8 | 2711 | } |
79e53945 | 2712 | |
e70236a8 JB |
2713 | /* Shouldn't happen */ |
2714 | return 0; | |
2715 | } | |
79e53945 | 2716 | |
e70236a8 JB |
2717 | static int i830_get_display_clock_speed(struct drm_device *dev) |
2718 | { | |
2719 | return 133000; | |
79e53945 JB |
2720 | } |
2721 | ||
2c07245f ZW |
2722 | struct fdi_m_n { |
2723 | u32 tu; | |
2724 | u32 gmch_m; | |
2725 | u32 gmch_n; | |
2726 | u32 link_m; | |
2727 | u32 link_n; | |
2728 | }; | |
2729 | ||
2730 | static void | |
2731 | fdi_reduce_ratio(u32 *num, u32 *den) | |
2732 | { | |
2733 | while (*num > 0xffffff || *den > 0xffffff) { | |
2734 | *num >>= 1; | |
2735 | *den >>= 1; | |
2736 | } | |
2737 | } | |
2738 | ||
2c07245f | 2739 | static void |
f2b115e6 AJ |
2740 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
2741 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 2742 | { |
2c07245f ZW |
2743 | m_n->tu = 64; /* default size */ |
2744 | ||
22ed1113 CW |
2745 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
2746 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
2747 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
2748 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
2749 | ||
22ed1113 CW |
2750 | m_n->link_m = pixel_clock; |
2751 | m_n->link_n = link_clock; | |
2c07245f ZW |
2752 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2753 | } | |
2754 | ||
2755 | ||
7662c8bd SL |
2756 | struct intel_watermark_params { |
2757 | unsigned long fifo_size; | |
2758 | unsigned long max_wm; | |
2759 | unsigned long default_wm; | |
2760 | unsigned long guard_size; | |
2761 | unsigned long cacheline_size; | |
2762 | }; | |
2763 | ||
f2b115e6 AJ |
2764 | /* Pineview has different values for various configs */ |
2765 | static struct intel_watermark_params pineview_display_wm = { | |
2766 | PINEVIEW_DISPLAY_FIFO, | |
2767 | PINEVIEW_MAX_WM, | |
2768 | PINEVIEW_DFT_WM, | |
2769 | PINEVIEW_GUARD_WM, | |
2770 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2771 | }; |
f2b115e6 AJ |
2772 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
2773 | PINEVIEW_DISPLAY_FIFO, | |
2774 | PINEVIEW_MAX_WM, | |
2775 | PINEVIEW_DFT_HPLLOFF_WM, | |
2776 | PINEVIEW_GUARD_WM, | |
2777 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2778 | }; |
f2b115e6 AJ |
2779 | static struct intel_watermark_params pineview_cursor_wm = { |
2780 | PINEVIEW_CURSOR_FIFO, | |
2781 | PINEVIEW_CURSOR_MAX_WM, | |
2782 | PINEVIEW_CURSOR_DFT_WM, | |
2783 | PINEVIEW_CURSOR_GUARD_WM, | |
2784 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 2785 | }; |
f2b115e6 AJ |
2786 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
2787 | PINEVIEW_CURSOR_FIFO, | |
2788 | PINEVIEW_CURSOR_MAX_WM, | |
2789 | PINEVIEW_CURSOR_DFT_WM, | |
2790 | PINEVIEW_CURSOR_GUARD_WM, | |
2791 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2792 | }; |
0e442c60 JB |
2793 | static struct intel_watermark_params g4x_wm_info = { |
2794 | G4X_FIFO_SIZE, | |
2795 | G4X_MAX_WM, | |
2796 | G4X_MAX_WM, | |
2797 | 2, | |
2798 | G4X_FIFO_LINE_SIZE, | |
2799 | }; | |
4fe5e611 ZY |
2800 | static struct intel_watermark_params g4x_cursor_wm_info = { |
2801 | I965_CURSOR_FIFO, | |
2802 | I965_CURSOR_MAX_WM, | |
2803 | I965_CURSOR_DFT_WM, | |
2804 | 2, | |
2805 | G4X_FIFO_LINE_SIZE, | |
2806 | }; | |
2807 | static struct intel_watermark_params i965_cursor_wm_info = { | |
2808 | I965_CURSOR_FIFO, | |
2809 | I965_CURSOR_MAX_WM, | |
2810 | I965_CURSOR_DFT_WM, | |
2811 | 2, | |
2812 | I915_FIFO_LINE_SIZE, | |
2813 | }; | |
7662c8bd | 2814 | static struct intel_watermark_params i945_wm_info = { |
dff33cfc | 2815 | I945_FIFO_SIZE, |
7662c8bd SL |
2816 | I915_MAX_WM, |
2817 | 1, | |
dff33cfc JB |
2818 | 2, |
2819 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
2820 | }; |
2821 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 2822 | I915_FIFO_SIZE, |
7662c8bd SL |
2823 | I915_MAX_WM, |
2824 | 1, | |
dff33cfc | 2825 | 2, |
7662c8bd SL |
2826 | I915_FIFO_LINE_SIZE |
2827 | }; | |
2828 | static struct intel_watermark_params i855_wm_info = { | |
2829 | I855GM_FIFO_SIZE, | |
2830 | I915_MAX_WM, | |
2831 | 1, | |
dff33cfc | 2832 | 2, |
7662c8bd SL |
2833 | I830_FIFO_LINE_SIZE |
2834 | }; | |
2835 | static struct intel_watermark_params i830_wm_info = { | |
2836 | I830_FIFO_SIZE, | |
2837 | I915_MAX_WM, | |
2838 | 1, | |
dff33cfc | 2839 | 2, |
7662c8bd SL |
2840 | I830_FIFO_LINE_SIZE |
2841 | }; | |
2842 | ||
7f8a8569 ZW |
2843 | static struct intel_watermark_params ironlake_display_wm_info = { |
2844 | ILK_DISPLAY_FIFO, | |
2845 | ILK_DISPLAY_MAXWM, | |
2846 | ILK_DISPLAY_DFTWM, | |
2847 | 2, | |
2848 | ILK_FIFO_LINE_SIZE | |
2849 | }; | |
2850 | ||
c936f44d ZY |
2851 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
2852 | ILK_CURSOR_FIFO, | |
2853 | ILK_CURSOR_MAXWM, | |
2854 | ILK_CURSOR_DFTWM, | |
2855 | 2, | |
2856 | ILK_FIFO_LINE_SIZE | |
2857 | }; | |
2858 | ||
7f8a8569 ZW |
2859 | static struct intel_watermark_params ironlake_display_srwm_info = { |
2860 | ILK_DISPLAY_SR_FIFO, | |
2861 | ILK_DISPLAY_MAX_SRWM, | |
2862 | ILK_DISPLAY_DFT_SRWM, | |
2863 | 2, | |
2864 | ILK_FIFO_LINE_SIZE | |
2865 | }; | |
2866 | ||
2867 | static struct intel_watermark_params ironlake_cursor_srwm_info = { | |
2868 | ILK_CURSOR_SR_FIFO, | |
2869 | ILK_CURSOR_MAX_SRWM, | |
2870 | ILK_CURSOR_DFT_SRWM, | |
2871 | 2, | |
2872 | ILK_FIFO_LINE_SIZE | |
2873 | }; | |
2874 | ||
1398261a YL |
2875 | static struct intel_watermark_params sandybridge_display_wm_info = { |
2876 | SNB_DISPLAY_FIFO, | |
2877 | SNB_DISPLAY_MAXWM, | |
2878 | SNB_DISPLAY_DFTWM, | |
2879 | 2, | |
2880 | SNB_FIFO_LINE_SIZE | |
2881 | }; | |
2882 | ||
2883 | static struct intel_watermark_params sandybridge_cursor_wm_info = { | |
2884 | SNB_CURSOR_FIFO, | |
2885 | SNB_CURSOR_MAXWM, | |
2886 | SNB_CURSOR_DFTWM, | |
2887 | 2, | |
2888 | SNB_FIFO_LINE_SIZE | |
2889 | }; | |
2890 | ||
2891 | static struct intel_watermark_params sandybridge_display_srwm_info = { | |
2892 | SNB_DISPLAY_SR_FIFO, | |
2893 | SNB_DISPLAY_MAX_SRWM, | |
2894 | SNB_DISPLAY_DFT_SRWM, | |
2895 | 2, | |
2896 | SNB_FIFO_LINE_SIZE | |
2897 | }; | |
2898 | ||
2899 | static struct intel_watermark_params sandybridge_cursor_srwm_info = { | |
2900 | SNB_CURSOR_SR_FIFO, | |
2901 | SNB_CURSOR_MAX_SRWM, | |
2902 | SNB_CURSOR_DFT_SRWM, | |
2903 | 2, | |
2904 | SNB_FIFO_LINE_SIZE | |
2905 | }; | |
2906 | ||
2907 | ||
dff33cfc JB |
2908 | /** |
2909 | * intel_calculate_wm - calculate watermark level | |
2910 | * @clock_in_khz: pixel clock | |
2911 | * @wm: chip FIFO params | |
2912 | * @pixel_size: display pixel size | |
2913 | * @latency_ns: memory latency for the platform | |
2914 | * | |
2915 | * Calculate the watermark level (the level at which the display plane will | |
2916 | * start fetching from memory again). Each chip has a different display | |
2917 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
2918 | * in the correct intel_watermark_params structure. | |
2919 | * | |
2920 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
2921 | * on the pixel size. When it reaches the watermark level, it'll start | |
2922 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
2923 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
2924 | * will occur, and a display engine hang could result. | |
2925 | */ | |
7662c8bd SL |
2926 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
2927 | struct intel_watermark_params *wm, | |
2928 | int pixel_size, | |
2929 | unsigned long latency_ns) | |
2930 | { | |
390c4dd4 | 2931 | long entries_required, wm_size; |
dff33cfc | 2932 | |
d660467c JB |
2933 | /* |
2934 | * Note: we need to make sure we don't overflow for various clock & | |
2935 | * latency values. | |
2936 | * clocks go from a few thousand to several hundred thousand. | |
2937 | * latency is usually a few thousand | |
2938 | */ | |
2939 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
2940 | 1000; | |
8de9b311 | 2941 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 2942 | |
28c97730 | 2943 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc JB |
2944 | |
2945 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
2946 | ||
28c97730 | 2947 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 2948 | |
390c4dd4 JB |
2949 | /* Don't promote wm_size to unsigned... */ |
2950 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 2951 | wm_size = wm->max_wm; |
c3add4b6 | 2952 | if (wm_size <= 0) |
7662c8bd SL |
2953 | wm_size = wm->default_wm; |
2954 | return wm_size; | |
2955 | } | |
2956 | ||
2957 | struct cxsr_latency { | |
2958 | int is_desktop; | |
95534263 | 2959 | int is_ddr3; |
7662c8bd SL |
2960 | unsigned long fsb_freq; |
2961 | unsigned long mem_freq; | |
2962 | unsigned long display_sr; | |
2963 | unsigned long display_hpll_disable; | |
2964 | unsigned long cursor_sr; | |
2965 | unsigned long cursor_hpll_disable; | |
2966 | }; | |
2967 | ||
403c89ff | 2968 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
2969 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
2970 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
2971 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
2972 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
2973 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
2974 | ||
2975 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
2976 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
2977 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
2978 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
2979 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
2980 | ||
2981 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
2982 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
2983 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
2984 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
2985 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
2986 | ||
2987 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
2988 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
2989 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
2990 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
2991 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
2992 | ||
2993 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
2994 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
2995 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
2996 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
2997 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
2998 | ||
2999 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3000 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3001 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3002 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3003 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3004 | }; |
3005 | ||
403c89ff CW |
3006 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3007 | int is_ddr3, | |
3008 | int fsb, | |
3009 | int mem) | |
7662c8bd | 3010 | { |
403c89ff | 3011 | const struct cxsr_latency *latency; |
7662c8bd | 3012 | int i; |
7662c8bd SL |
3013 | |
3014 | if (fsb == 0 || mem == 0) | |
3015 | return NULL; | |
3016 | ||
3017 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3018 | latency = &cxsr_latency_table[i]; | |
3019 | if (is_desktop == latency->is_desktop && | |
95534263 | 3020 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3021 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3022 | return latency; | |
7662c8bd | 3023 | } |
decbbcda | 3024 | |
28c97730 | 3025 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3026 | |
3027 | return NULL; | |
7662c8bd SL |
3028 | } |
3029 | ||
f2b115e6 | 3030 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3031 | { |
3032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3033 | |
3034 | /* deactivate cxsr */ | |
3e33d94d | 3035 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3036 | } |
3037 | ||
bcc24fb4 JB |
3038 | /* |
3039 | * Latency for FIFO fetches is dependent on several factors: | |
3040 | * - memory configuration (speed, channels) | |
3041 | * - chipset | |
3042 | * - current MCH state | |
3043 | * It can be fairly high in some situations, so here we assume a fairly | |
3044 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3045 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3046 | * and power consumption (set it too low to save power and we might see | |
3047 | * FIFO underruns and display "flicker"). | |
3048 | * | |
3049 | * A value of 5us seems to be a good balance; safe for very low end | |
3050 | * platforms but not overly aggressive on lower latency configs. | |
3051 | */ | |
69e302a9 | 3052 | static const int latency_ns = 5000; |
7662c8bd | 3053 | |
e70236a8 | 3054 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3055 | { |
3056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3057 | uint32_t dsparb = I915_READ(DSPARB); | |
3058 | int size; | |
3059 | ||
8de9b311 CW |
3060 | size = dsparb & 0x7f; |
3061 | if (plane) | |
3062 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3063 | |
28c97730 | 3064 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3065 | plane ? "B" : "A", size); |
dff33cfc JB |
3066 | |
3067 | return size; | |
3068 | } | |
7662c8bd | 3069 | |
e70236a8 JB |
3070 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3071 | { | |
3072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3073 | uint32_t dsparb = I915_READ(DSPARB); | |
3074 | int size; | |
3075 | ||
8de9b311 CW |
3076 | size = dsparb & 0x1ff; |
3077 | if (plane) | |
3078 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3079 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3080 | |
28c97730 | 3081 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3082 | plane ? "B" : "A", size); |
dff33cfc JB |
3083 | |
3084 | return size; | |
3085 | } | |
7662c8bd | 3086 | |
e70236a8 JB |
3087 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3088 | { | |
3089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3090 | uint32_t dsparb = I915_READ(DSPARB); | |
3091 | int size; | |
3092 | ||
3093 | size = dsparb & 0x7f; | |
3094 | size >>= 2; /* Convert to cachelines */ | |
3095 | ||
28c97730 | 3096 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3097 | plane ? "B" : "A", |
3098 | size); | |
e70236a8 JB |
3099 | |
3100 | return size; | |
3101 | } | |
3102 | ||
3103 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3104 | { | |
3105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3106 | uint32_t dsparb = I915_READ(DSPARB); | |
3107 | int size; | |
3108 | ||
3109 | size = dsparb & 0x7f; | |
3110 | size >>= 1; /* Convert to cachelines */ | |
3111 | ||
28c97730 | 3112 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3113 | plane ? "B" : "A", size); |
e70236a8 JB |
3114 | |
3115 | return size; | |
3116 | } | |
3117 | ||
d4294342 | 3118 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
5eddb70b CW |
3119 | int planeb_clock, int sr_hdisplay, int unused, |
3120 | int pixel_size) | |
d4294342 ZY |
3121 | { |
3122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403c89ff | 3123 | const struct cxsr_latency *latency; |
d4294342 ZY |
3124 | u32 reg; |
3125 | unsigned long wm; | |
d4294342 ZY |
3126 | int sr_clock; |
3127 | ||
403c89ff | 3128 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3129 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3130 | if (!latency) { |
3131 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3132 | pineview_disable_cxsr(dev); | |
3133 | return; | |
3134 | } | |
3135 | ||
3136 | if (!planea_clock || !planeb_clock) { | |
3137 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
3138 | ||
3139 | /* Display SR */ | |
3140 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, | |
3141 | pixel_size, latency->display_sr); | |
3142 | reg = I915_READ(DSPFW1); | |
3143 | reg &= ~DSPFW_SR_MASK; | |
3144 | reg |= wm << DSPFW_SR_SHIFT; | |
3145 | I915_WRITE(DSPFW1, reg); | |
3146 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3147 | ||
3148 | /* cursor SR */ | |
3149 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, | |
3150 | pixel_size, latency->cursor_sr); | |
3151 | reg = I915_READ(DSPFW3); | |
3152 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3153 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3154 | I915_WRITE(DSPFW3, reg); | |
3155 | ||
3156 | /* Display HPLL off SR */ | |
3157 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, | |
3158 | pixel_size, latency->display_hpll_disable); | |
3159 | reg = I915_READ(DSPFW3); | |
3160 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3161 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3162 | I915_WRITE(DSPFW3, reg); | |
3163 | ||
3164 | /* cursor HPLL off SR */ | |
3165 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, | |
3166 | pixel_size, latency->cursor_hpll_disable); | |
3167 | reg = I915_READ(DSPFW3); | |
3168 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3169 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3170 | I915_WRITE(DSPFW3, reg); | |
3171 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3172 | ||
3173 | /* activate cxsr */ | |
3e33d94d CW |
3174 | I915_WRITE(DSPFW3, |
3175 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3176 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3177 | } else { | |
3178 | pineview_disable_cxsr(dev); | |
3179 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3180 | } | |
3181 | } | |
3182 | ||
0e442c60 | 3183 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3184 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3185 | int pixel_size) | |
652c393a JB |
3186 | { |
3187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e442c60 JB |
3188 | int total_size, cacheline_size; |
3189 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | |
3190 | struct intel_watermark_params planea_params, planeb_params; | |
3191 | unsigned long line_time_us; | |
3192 | int sr_clock, sr_entries = 0, entries_required; | |
652c393a | 3193 | |
0e442c60 JB |
3194 | /* Create copies of the base settings for each pipe */ |
3195 | planea_params = planeb_params = g4x_wm_info; | |
3196 | ||
3197 | /* Grab a couple of global values before we overwrite them */ | |
3198 | total_size = planea_params.fifo_size; | |
3199 | cacheline_size = planea_params.cacheline_size; | |
3200 | ||
3201 | /* | |
3202 | * Note: we need to make sure we don't overflow for various clock & | |
3203 | * latency values. | |
3204 | * clocks go from a few thousand to several hundred thousand. | |
3205 | * latency is usually a few thousand | |
3206 | */ | |
3207 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | |
3208 | 1000; | |
8de9b311 | 3209 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3210 | planea_wm = entries_required + planea_params.guard_size; |
3211 | ||
3212 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | |
3213 | 1000; | |
8de9b311 | 3214 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3215 | planeb_wm = entries_required + planeb_params.guard_size; |
3216 | ||
3217 | cursora_wm = cursorb_wm = 16; | |
3218 | cursor_sr = 32; | |
3219 | ||
3220 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
3221 | ||
3222 | /* Calc sr entries for one plane configs */ | |
3223 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3224 | /* self-refresh has much higher latency */ | |
69e302a9 | 3225 | static const int sr_latency_ns = 12000; |
0e442c60 JB |
3226 | |
3227 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3228 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
0e442c60 JB |
3229 | |
3230 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3231 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3232 | pixel_size * sr_hdisplay; |
8de9b311 | 3233 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
4fe5e611 ZY |
3234 | |
3235 | entries_required = (((sr_latency_ns / line_time_us) + | |
3236 | 1000) / 1000) * pixel_size * 64; | |
8de9b311 | 3237 | entries_required = DIV_ROUND_UP(entries_required, |
5eddb70b | 3238 | g4x_cursor_wm_info.cacheline_size); |
4fe5e611 ZY |
3239 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
3240 | ||
3241 | if (cursor_sr > g4x_cursor_wm_info.max_wm) | |
3242 | cursor_sr = g4x_cursor_wm_info.max_wm; | |
3243 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3244 | "cursor %d\n", sr_entries, cursor_sr); | |
3245 | ||
0e442c60 | 3246 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3247 | } else { |
3248 | /* Turn off self refresh if both pipes are enabled */ | |
3249 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
5eddb70b | 3250 | & ~FW_BLC_SELF_EN); |
0e442c60 JB |
3251 | } |
3252 | ||
3253 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | |
3254 | planea_wm, planeb_wm, sr_entries); | |
3255 | ||
3256 | planea_wm &= 0x3f; | |
3257 | planeb_wm &= 0x3f; | |
3258 | ||
3259 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | |
3260 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
3261 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | |
3262 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
3263 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
3264 | /* HPLL off in SR has some issues on G4x... disable it */ | |
3265 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
3266 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
652c393a JB |
3267 | } |
3268 | ||
1dc7546d | 3269 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3270 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3271 | int pixel_size) | |
7662c8bd SL |
3272 | { |
3273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dc7546d JB |
3274 | unsigned long line_time_us; |
3275 | int sr_clock, sr_entries, srwm = 1; | |
4fe5e611 | 3276 | int cursor_sr = 16; |
1dc7546d JB |
3277 | |
3278 | /* Calc sr entries for one plane configs */ | |
3279 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3280 | /* self-refresh has much higher latency */ | |
69e302a9 | 3281 | static const int sr_latency_ns = 12000; |
1dc7546d JB |
3282 | |
3283 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3284 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
1dc7546d JB |
3285 | |
3286 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3287 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3288 | pixel_size * sr_hdisplay; |
8de9b311 | 3289 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
1dc7546d | 3290 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
1b07e04e | 3291 | srwm = I965_FIFO_SIZE - sr_entries; |
1dc7546d JB |
3292 | if (srwm < 0) |
3293 | srwm = 1; | |
1b07e04e | 3294 | srwm &= 0x1ff; |
4fe5e611 ZY |
3295 | |
3296 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
5eddb70b | 3297 | pixel_size * 64; |
8de9b311 CW |
3298 | sr_entries = DIV_ROUND_UP(sr_entries, |
3299 | i965_cursor_wm_info.cacheline_size); | |
4fe5e611 | 3300 | cursor_sr = i965_cursor_wm_info.fifo_size - |
5eddb70b | 3301 | (sr_entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
3302 | |
3303 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3304 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3305 | ||
3306 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3307 | "cursor %d\n", srwm, cursor_sr); | |
3308 | ||
a6c45cf0 | 3309 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 3310 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3311 | } else { |
3312 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 3313 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
3314 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
3315 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3316 | } |
7662c8bd | 3317 | |
1dc7546d JB |
3318 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3319 | srwm); | |
7662c8bd SL |
3320 | |
3321 | /* 965 has limitations... */ | |
1dc7546d JB |
3322 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
3323 | (8 << 0)); | |
7662c8bd | 3324 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
3325 | /* update cursor SR watermark */ |
3326 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
3327 | } |
3328 | ||
3329 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3330 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3331 | int pixel_size) | |
7662c8bd SL |
3332 | { |
3333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
3334 | uint32_t fwater_lo; |
3335 | uint32_t fwater_hi; | |
3336 | int total_size, cacheline_size, cwm, srwm = 1; | |
3337 | int planea_wm, planeb_wm; | |
3338 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
3339 | unsigned long line_time_us; |
3340 | int sr_clock, sr_entries = 0; | |
3341 | ||
dff33cfc | 3342 | /* Create copies of the base settings for each pipe */ |
a6c45cf0 | 3343 | if (IS_CRESTLINE(dev) || IS_I945GM(dev)) |
dff33cfc | 3344 | planea_params = planeb_params = i945_wm_info; |
a6c45cf0 | 3345 | else if (!IS_GEN2(dev)) |
dff33cfc | 3346 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 3347 | else |
dff33cfc | 3348 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 3349 | |
dff33cfc JB |
3350 | /* Grab a couple of global values before we overwrite them */ |
3351 | total_size = planea_params.fifo_size; | |
3352 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 3353 | |
dff33cfc | 3354 | /* Update per-plane FIFO sizes */ |
e70236a8 JB |
3355 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
3356 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
7662c8bd | 3357 | |
dff33cfc JB |
3358 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
3359 | pixel_size, latency_ns); | |
3360 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
3361 | pixel_size, latency_ns); | |
28c97730 | 3362 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
3363 | |
3364 | /* | |
3365 | * Overlay gets an aggressive default since video jitter is bad. | |
3366 | */ | |
3367 | cwm = 2; | |
3368 | ||
dff33cfc | 3369 | /* Calc sr entries for one plane configs */ |
652c393a JB |
3370 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
3371 | (!planea_clock || !planeb_clock)) { | |
dff33cfc | 3372 | /* self-refresh has much higher latency */ |
69e302a9 | 3373 | static const int sr_latency_ns = 6000; |
dff33cfc | 3374 | |
7662c8bd | 3375 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
fa143215 | 3376 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
dff33cfc JB |
3377 | |
3378 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3379 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3380 | pixel_size * sr_hdisplay; |
8de9b311 | 3381 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
28c97730 | 3382 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
dff33cfc JB |
3383 | srwm = total_size - sr_entries; |
3384 | if (srwm < 0) | |
3385 | srwm = 1; | |
ee980b80 LP |
3386 | |
3387 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
3388 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
3389 | else if (IS_I915GM(dev)) { | |
3390 | /* 915M has a smaller SRWM field */ | |
3391 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
3392 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
3393 | } | |
33c5fd12 DJ |
3394 | } else { |
3395 | /* Turn off self refresh if both pipes are enabled */ | |
ee980b80 LP |
3396 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
3397 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3398 | & ~FW_BLC_SELF_EN); | |
3399 | } else if (IS_I915GM(dev)) { | |
3400 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
3401 | } | |
7662c8bd SL |
3402 | } |
3403 | ||
28c97730 | 3404 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 3405 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 3406 | |
dff33cfc JB |
3407 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
3408 | fwater_hi = (cwm & 0x1f); | |
3409 | ||
3410 | /* Set request length to 8 cachelines per fetch */ | |
3411 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
3412 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
3413 | |
3414 | I915_WRITE(FW_BLC, fwater_lo); | |
3415 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
3416 | } |
3417 | ||
e70236a8 | 3418 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
fa143215 | 3419 | int unused2, int unused3, int pixel_size) |
7662c8bd SL |
3420 | { |
3421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f3601326 | 3422 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
dff33cfc | 3423 | int planea_wm; |
7662c8bd | 3424 | |
e70236a8 | 3425 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
7662c8bd | 3426 | |
dff33cfc JB |
3427 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
3428 | pixel_size, latency_ns); | |
f3601326 JB |
3429 | fwater_lo |= (3<<8) | planea_wm; |
3430 | ||
28c97730 | 3431 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
3432 | |
3433 | I915_WRITE(FW_BLC, fwater_lo); | |
3434 | } | |
3435 | ||
7f8a8569 | 3436 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 3437 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 3438 | |
4ed765f9 CW |
3439 | static bool ironlake_compute_wm0(struct drm_device *dev, |
3440 | int pipe, | |
1398261a | 3441 | const struct intel_watermark_params *display, |
a0fa62d3 | 3442 | int display_latency_ns, |
1398261a | 3443 | const struct intel_watermark_params *cursor, |
a0fa62d3 | 3444 | int cursor_latency_ns, |
4ed765f9 CW |
3445 | int *plane_wm, |
3446 | int *cursor_wm) | |
7f8a8569 | 3447 | { |
c936f44d | 3448 | struct drm_crtc *crtc; |
db66e37d CW |
3449 | int htotal, hdisplay, clock, pixel_size; |
3450 | int line_time_us, line_count; | |
3451 | int entries, tlb_miss; | |
c936f44d | 3452 | |
4ed765f9 CW |
3453 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
3454 | if (crtc->fb == NULL || !crtc->enabled) | |
3455 | return false; | |
7f8a8569 | 3456 | |
4ed765f9 CW |
3457 | htotal = crtc->mode.htotal; |
3458 | hdisplay = crtc->mode.hdisplay; | |
3459 | clock = crtc->mode.clock; | |
3460 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3461 | ||
3462 | /* Use the small buffer method to calculate plane watermark */ | |
a0fa62d3 | 3463 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
db66e37d CW |
3464 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
3465 | if (tlb_miss > 0) | |
3466 | entries += tlb_miss; | |
1398261a YL |
3467 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
3468 | *plane_wm = entries + display->guard_size; | |
3469 | if (*plane_wm > (int)display->max_wm) | |
3470 | *plane_wm = display->max_wm; | |
4ed765f9 CW |
3471 | |
3472 | /* Use the large buffer method to calculate cursor watermark */ | |
3473 | line_time_us = ((htotal * 1000) / clock); | |
a0fa62d3 | 3474 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
4ed765f9 | 3475 | entries = line_count * 64 * pixel_size; |
db66e37d CW |
3476 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
3477 | if (tlb_miss > 0) | |
3478 | entries += tlb_miss; | |
1398261a YL |
3479 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
3480 | *cursor_wm = entries + cursor->guard_size; | |
3481 | if (*cursor_wm > (int)cursor->max_wm) | |
3482 | *cursor_wm = (int)cursor->max_wm; | |
7f8a8569 | 3483 | |
4ed765f9 CW |
3484 | return true; |
3485 | } | |
c936f44d | 3486 | |
1398261a YL |
3487 | /* |
3488 | * Check the wm result. | |
3489 | * | |
3490 | * If any calculated watermark values is larger than the maximum value that | |
3491 | * can be programmed into the associated watermark register, that watermark | |
3492 | * must be disabled. | |
1398261a | 3493 | */ |
b79d4990 JB |
3494 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
3495 | int fbc_wm, int display_wm, int cursor_wm, | |
3496 | const struct intel_watermark_params *display, | |
3497 | const struct intel_watermark_params *cursor) | |
1398261a YL |
3498 | { |
3499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3500 | ||
3501 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
3502 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
3503 | ||
3504 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
3505 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 3506 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
3507 | |
3508 | /* fbc has it's own way to disable FBC WM */ | |
3509 | I915_WRITE(DISP_ARB_CTL, | |
3510 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
3511 | return false; | |
3512 | } | |
3513 | ||
b79d4990 | 3514 | if (display_wm > display->max_wm) { |
1398261a | 3515 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 3516 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
3517 | return false; |
3518 | } | |
3519 | ||
b79d4990 | 3520 | if (cursor_wm > cursor->max_wm) { |
1398261a | 3521 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 3522 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
3523 | return false; |
3524 | } | |
3525 | ||
3526 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
3527 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
3528 | return false; | |
3529 | } | |
3530 | ||
3531 | return true; | |
3532 | } | |
3533 | ||
3534 | /* | |
3535 | * Compute watermark values of WM[1-3], | |
3536 | */ | |
b79d4990 JB |
3537 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, |
3538 | int hdisplay, int htotal, | |
3539 | int pixel_size, int clock, int latency_ns, | |
3540 | const struct intel_watermark_params *display, | |
3541 | const struct intel_watermark_params *cursor, | |
3542 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a YL |
3543 | { |
3544 | ||
3545 | unsigned long line_time_us; | |
b79d4990 | 3546 | int line_count, line_size; |
1398261a YL |
3547 | int small, large; |
3548 | int entries; | |
1398261a YL |
3549 | |
3550 | if (!latency_ns) { | |
3551 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
3552 | return false; | |
3553 | } | |
3554 | ||
3555 | line_time_us = (htotal * 1000) / clock; | |
3556 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
3557 | line_size = hdisplay * pixel_size; | |
3558 | ||
3559 | /* Use the minimum of the small and large buffer method for primary */ | |
3560 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
3561 | large = line_count * line_size; | |
3562 | ||
b79d4990 JB |
3563 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
3564 | *display_wm = entries + display->guard_size; | |
1398261a YL |
3565 | |
3566 | /* | |
b79d4990 | 3567 | * Spec says: |
1398261a YL |
3568 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
3569 | */ | |
3570 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
3571 | ||
3572 | /* calculate the self-refresh watermark for display cursor */ | |
3573 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
3574 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
3575 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 3576 | |
b79d4990 JB |
3577 | return ironlake_check_srwm(dev, level, |
3578 | *fbc_wm, *display_wm, *cursor_wm, | |
3579 | display, cursor); | |
3580 | } | |
3581 | ||
3582 | static void ironlake_update_wm(struct drm_device *dev, | |
3583 | int planea_clock, int planeb_clock, | |
3584 | int hdisplay, int htotal, | |
3585 | int pixel_size) | |
3586 | { | |
3587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3588 | int fbc_wm, plane_wm, cursor_wm, enabled; | |
3589 | int clock; | |
3590 | ||
3591 | enabled = 0; | |
3592 | if (ironlake_compute_wm0(dev, 0, | |
3593 | &ironlake_display_wm_info, | |
3594 | ILK_LP0_PLANE_LATENCY, | |
3595 | &ironlake_cursor_wm_info, | |
3596 | ILK_LP0_CURSOR_LATENCY, | |
3597 | &plane_wm, &cursor_wm)) { | |
3598 | I915_WRITE(WM0_PIPEA_ILK, | |
3599 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3600 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3601 | " plane %d, " "cursor: %d\n", | |
3602 | plane_wm, cursor_wm); | |
3603 | enabled++; | |
3604 | } | |
3605 | ||
3606 | if (ironlake_compute_wm0(dev, 1, | |
3607 | &ironlake_display_wm_info, | |
3608 | ILK_LP0_PLANE_LATENCY, | |
3609 | &ironlake_cursor_wm_info, | |
3610 | ILK_LP0_CURSOR_LATENCY, | |
3611 | &plane_wm, &cursor_wm)) { | |
3612 | I915_WRITE(WM0_PIPEB_ILK, | |
3613 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3614 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3615 | " plane %d, cursor: %d\n", | |
3616 | plane_wm, cursor_wm); | |
3617 | enabled++; | |
3618 | } | |
3619 | ||
3620 | /* | |
3621 | * Calculate and update the self-refresh watermark only when one | |
3622 | * display plane is used. | |
3623 | */ | |
3624 | I915_WRITE(WM3_LP_ILK, 0); | |
3625 | I915_WRITE(WM2_LP_ILK, 0); | |
3626 | I915_WRITE(WM1_LP_ILK, 0); | |
3627 | ||
3628 | if (enabled != 1) | |
3629 | return; | |
3630 | ||
3631 | clock = planea_clock ? planea_clock : planeb_clock; | |
3632 | ||
3633 | /* WM1 */ | |
3634 | if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size, | |
3635 | clock, ILK_READ_WM1_LATENCY() * 500, | |
3636 | &ironlake_display_srwm_info, | |
3637 | &ironlake_cursor_srwm_info, | |
3638 | &fbc_wm, &plane_wm, &cursor_wm)) | |
3639 | return; | |
3640 | ||
3641 | I915_WRITE(WM1_LP_ILK, | |
3642 | WM1_LP_SR_EN | | |
3643 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3644 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3645 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3646 | cursor_wm); | |
3647 | ||
3648 | /* WM2 */ | |
3649 | if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size, | |
3650 | clock, ILK_READ_WM2_LATENCY() * 500, | |
3651 | &ironlake_display_srwm_info, | |
3652 | &ironlake_cursor_srwm_info, | |
3653 | &fbc_wm, &plane_wm, &cursor_wm)) | |
3654 | return; | |
3655 | ||
3656 | I915_WRITE(WM2_LP_ILK, | |
3657 | WM2_LP_EN | | |
3658 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3659 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3660 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3661 | cursor_wm); | |
3662 | ||
3663 | /* | |
3664 | * WM3 is unsupported on ILK, probably because we don't have latency | |
3665 | * data for that power state | |
3666 | */ | |
1398261a YL |
3667 | } |
3668 | ||
3669 | static void sandybridge_update_wm(struct drm_device *dev, | |
3670 | int planea_clock, int planeb_clock, | |
3671 | int hdisplay, int htotal, | |
3672 | int pixel_size) | |
3673 | { | |
3674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 3675 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1398261a YL |
3676 | int fbc_wm, plane_wm, cursor_wm, enabled; |
3677 | int clock; | |
3678 | ||
3679 | enabled = 0; | |
3680 | if (ironlake_compute_wm0(dev, 0, | |
3681 | &sandybridge_display_wm_info, latency, | |
3682 | &sandybridge_cursor_wm_info, latency, | |
3683 | &plane_wm, &cursor_wm)) { | |
3684 | I915_WRITE(WM0_PIPEA_ILK, | |
3685 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3686 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3687 | " plane %d, " "cursor: %d\n", | |
3688 | plane_wm, cursor_wm); | |
3689 | enabled++; | |
3690 | } | |
3691 | ||
3692 | if (ironlake_compute_wm0(dev, 1, | |
3693 | &sandybridge_display_wm_info, latency, | |
3694 | &sandybridge_cursor_wm_info, latency, | |
3695 | &plane_wm, &cursor_wm)) { | |
3696 | I915_WRITE(WM0_PIPEB_ILK, | |
3697 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3698 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3699 | " plane %d, cursor: %d\n", | |
3700 | plane_wm, cursor_wm); | |
3701 | enabled++; | |
3702 | } | |
3703 | ||
3704 | /* | |
3705 | * Calculate and update the self-refresh watermark only when one | |
3706 | * display plane is used. | |
3707 | * | |
3708 | * SNB support 3 levels of watermark. | |
3709 | * | |
3710 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
3711 | * and disabled in the descending order | |
3712 | * | |
3713 | */ | |
3714 | I915_WRITE(WM3_LP_ILK, 0); | |
3715 | I915_WRITE(WM2_LP_ILK, 0); | |
3716 | I915_WRITE(WM1_LP_ILK, 0); | |
3717 | ||
3718 | if (enabled != 1) | |
3719 | return; | |
3720 | ||
3721 | clock = planea_clock ? planea_clock : planeb_clock; | |
3722 | ||
3723 | /* WM1 */ | |
b79d4990 JB |
3724 | if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size, |
3725 | clock, SNB_READ_WM1_LATENCY() * 500, | |
3726 | &sandybridge_display_srwm_info, | |
3727 | &sandybridge_cursor_srwm_info, | |
3728 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
3729 | return; |
3730 | ||
3731 | I915_WRITE(WM1_LP_ILK, | |
3732 | WM1_LP_SR_EN | | |
3733 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3734 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3735 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3736 | cursor_wm); | |
3737 | ||
3738 | /* WM2 */ | |
b79d4990 JB |
3739 | if (!ironlake_compute_srwm(dev, 2, |
3740 | hdisplay, htotal, pixel_size, | |
3741 | clock, SNB_READ_WM2_LATENCY() * 500, | |
3742 | &sandybridge_display_srwm_info, | |
3743 | &sandybridge_cursor_srwm_info, | |
3744 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
3745 | return; |
3746 | ||
3747 | I915_WRITE(WM2_LP_ILK, | |
3748 | WM2_LP_EN | | |
3749 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3750 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3751 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3752 | cursor_wm); | |
3753 | ||
3754 | /* WM3 */ | |
b79d4990 JB |
3755 | if (!ironlake_compute_srwm(dev, 3, |
3756 | hdisplay, htotal, pixel_size, | |
3757 | clock, SNB_READ_WM3_LATENCY() * 500, | |
3758 | &sandybridge_display_srwm_info, | |
3759 | &sandybridge_cursor_srwm_info, | |
3760 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
3761 | return; |
3762 | ||
3763 | I915_WRITE(WM3_LP_ILK, | |
3764 | WM3_LP_EN | | |
3765 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3766 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3767 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3768 | cursor_wm); | |
3769 | } | |
3770 | ||
7662c8bd SL |
3771 | /** |
3772 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3773 | * | |
3774 | * Calculate watermark values for the various WM regs based on current mode | |
3775 | * and plane configuration. | |
3776 | * | |
3777 | * There are several cases to deal with here: | |
3778 | * - normal (i.e. non-self-refresh) | |
3779 | * - self-refresh (SR) mode | |
3780 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3781 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3782 | * lines), so need to account for TLB latency | |
3783 | * | |
3784 | * The normal calculation is: | |
3785 | * watermark = dotclock * bytes per pixel * latency | |
3786 | * where latency is platform & configuration dependent (we assume pessimal | |
3787 | * values here). | |
3788 | * | |
3789 | * The SR calculation is: | |
3790 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3791 | * bytes per pixel | |
3792 | * where | |
3793 | * line time = htotal / dotclock | |
fa143215 | 3794 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
3795 | * and latency is assumed to be high, as above. |
3796 | * | |
3797 | * The final value programmed to the register should always be rounded up, | |
3798 | * and include an extra 2 entries to account for clock crossings. | |
3799 | * | |
3800 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3801 | * to set the non-SR watermarks to 8. | |
5eddb70b | 3802 | */ |
7662c8bd SL |
3803 | static void intel_update_watermarks(struct drm_device *dev) |
3804 | { | |
e70236a8 | 3805 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 3806 | struct drm_crtc *crtc; |
7662c8bd SL |
3807 | int sr_hdisplay = 0; |
3808 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
3809 | int enabled = 0, pixel_size = 0; | |
fa143215 | 3810 | int sr_htotal = 0; |
7662c8bd | 3811 | |
c03342fa ZW |
3812 | if (!dev_priv->display.update_wm) |
3813 | return; | |
3814 | ||
7662c8bd SL |
3815 | /* Get the clock config from both planes */ |
3816 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc | 3817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f7abfe8b | 3818 | if (intel_crtc->active) { |
7662c8bd SL |
3819 | enabled++; |
3820 | if (intel_crtc->plane == 0) { | |
28c97730 | 3821 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
5eddb70b | 3822 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3823 | planea_clock = crtc->mode.clock; |
3824 | } else { | |
28c97730 | 3825 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
5eddb70b | 3826 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3827 | planeb_clock = crtc->mode.clock; |
3828 | } | |
3829 | sr_hdisplay = crtc->mode.hdisplay; | |
3830 | sr_clock = crtc->mode.clock; | |
fa143215 | 3831 | sr_htotal = crtc->mode.htotal; |
7662c8bd SL |
3832 | if (crtc->fb) |
3833 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3834 | else | |
3835 | pixel_size = 4; /* by default */ | |
3836 | } | |
3837 | } | |
3838 | ||
3839 | if (enabled <= 0) | |
3840 | return; | |
3841 | ||
e70236a8 | 3842 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
fa143215 | 3843 | sr_hdisplay, sr_htotal, pixel_size); |
7662c8bd SL |
3844 | } |
3845 | ||
a7615030 CW |
3846 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3847 | { | |
3848 | return dev_priv->lvds_use_ssc && i915_panel_use_ssc; | |
3849 | } | |
3850 | ||
5c3b82e2 CW |
3851 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
3852 | struct drm_display_mode *mode, | |
3853 | struct drm_display_mode *adjusted_mode, | |
3854 | int x, int y, | |
3855 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3856 | { |
3857 | struct drm_device *dev = crtc->dev; | |
3858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3860 | int pipe = intel_crtc->pipe; | |
80824003 | 3861 | int plane = intel_crtc->plane; |
5eddb70b | 3862 | u32 fp_reg, dpll_reg; |
c751ce4f | 3863 | int refclk, num_connectors = 0; |
652c393a | 3864 | intel_clock_t clock, reduced_clock; |
5eddb70b | 3865 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 3866 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 3867 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 3868 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 3869 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 3870 | struct intel_encoder *encoder; |
d4906093 | 3871 | const intel_limit_t *limit; |
5c3b82e2 | 3872 | int ret; |
2c07245f | 3873 | struct fdi_m_n m_n = {0}; |
5eddb70b | 3874 | u32 reg, temp; |
5eb08b69 | 3875 | int target_clock; |
79e53945 JB |
3876 | |
3877 | drm_vblank_pre_modeset(dev, pipe); | |
3878 | ||
5eddb70b CW |
3879 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
3880 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
3881 | continue; |
3882 | ||
5eddb70b | 3883 | switch (encoder->type) { |
79e53945 JB |
3884 | case INTEL_OUTPUT_LVDS: |
3885 | is_lvds = true; | |
3886 | break; | |
3887 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3888 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3889 | is_sdvo = true; |
5eddb70b | 3890 | if (encoder->needs_tv_clock) |
e2f0ba97 | 3891 | is_tv = true; |
79e53945 JB |
3892 | break; |
3893 | case INTEL_OUTPUT_DVO: | |
3894 | is_dvo = true; | |
3895 | break; | |
3896 | case INTEL_OUTPUT_TVOUT: | |
3897 | is_tv = true; | |
3898 | break; | |
3899 | case INTEL_OUTPUT_ANALOG: | |
3900 | is_crt = true; | |
3901 | break; | |
a4fc5ed6 KP |
3902 | case INTEL_OUTPUT_DISPLAYPORT: |
3903 | is_dp = true; | |
3904 | break; | |
32f9d658 | 3905 | case INTEL_OUTPUT_EDP: |
5eddb70b | 3906 | has_edp_encoder = encoder; |
32f9d658 | 3907 | break; |
79e53945 | 3908 | } |
43565a06 | 3909 | |
c751ce4f | 3910 | num_connectors++; |
79e53945 JB |
3911 | } |
3912 | ||
a7615030 | 3913 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
43565a06 | 3914 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 3915 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 3916 | refclk / 1000); |
a6c45cf0 | 3917 | } else if (!IS_GEN2(dev)) { |
79e53945 | 3918 | refclk = 96000; |
1cb1b75e JB |
3919 | if (HAS_PCH_SPLIT(dev) && |
3920 | (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base))) | |
2c07245f | 3921 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
3922 | } else { |
3923 | refclk = 48000; | |
3924 | } | |
3925 | ||
d4906093 ML |
3926 | /* |
3927 | * Returns a set of divisors for the desired target clock with the given | |
3928 | * refclk, or FALSE. The returned values represent the clock equation: | |
3929 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
3930 | */ | |
1b894b59 | 3931 | limit = intel_limit(crtc, refclk); |
d4906093 | 3932 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
3933 | if (!ok) { |
3934 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 3935 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 3936 | return -EINVAL; |
79e53945 JB |
3937 | } |
3938 | ||
cda4b7d3 | 3939 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 3940 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 3941 | |
ddc9003c ZY |
3942 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
3943 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
3944 | dev_priv->lvds_downclock, |
3945 | refclk, | |
3946 | &reduced_clock); | |
18f9ed12 ZY |
3947 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
3948 | /* | |
3949 | * If the different P is found, it means that we can't | |
3950 | * switch the display clock by using the FP0/FP1. | |
3951 | * In such case we will disable the LVDS downclock | |
3952 | * feature. | |
3953 | */ | |
3954 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 3955 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
3956 | has_reduced_clock = 0; |
3957 | } | |
652c393a | 3958 | } |
7026d4ac ZW |
3959 | /* SDVO TV has fixed PLL values depend on its clock range, |
3960 | this mirrors vbios setting. */ | |
3961 | if (is_sdvo && is_tv) { | |
3962 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 3963 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
3964 | clock.p1 = 2; |
3965 | clock.p2 = 10; | |
3966 | clock.n = 3; | |
3967 | clock.m1 = 16; | |
3968 | clock.m2 = 8; | |
3969 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 3970 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
3971 | clock.p1 = 1; |
3972 | clock.p2 = 10; | |
3973 | clock.n = 6; | |
3974 | clock.m1 = 12; | |
3975 | clock.m2 = 8; | |
3976 | } | |
3977 | } | |
3978 | ||
2c07245f | 3979 | /* FDI link */ |
bad720ff | 3980 | if (HAS_PCH_SPLIT(dev)) { |
49078f7d | 3981 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
77ffb597 | 3982 | int lane = 0, link_bw, bpp; |
5c5313c8 | 3983 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
32f9d658 | 3984 | according to current link config */ |
858bc21f | 3985 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
5eb08b69 | 3986 | target_clock = mode->clock; |
8e647a27 CW |
3987 | intel_edp_link_config(has_edp_encoder, |
3988 | &lane, &link_bw); | |
32f9d658 | 3989 | } else { |
5c5313c8 | 3990 | /* [e]DP over FDI requires target mode clock |
32f9d658 | 3991 | instead of link clock */ |
5c5313c8 | 3992 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
32f9d658 ZW |
3993 | target_clock = mode->clock; |
3994 | else | |
3995 | target_clock = adjusted_mode->clock; | |
021357ac CW |
3996 | |
3997 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
3998 | * each output octet as 10 bits. The actual frequency | |
3999 | * is stored as a divider into a 100MHz clock, and the | |
4000 | * mode pixel clock is stored in units of 1KHz. | |
4001 | * Hence the bw of each lane in terms of the mode signal | |
4002 | * is: | |
4003 | */ | |
4004 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
32f9d658 | 4005 | } |
58a27471 ZW |
4006 | |
4007 | /* determine panel color depth */ | |
5eddb70b | 4008 | temp = I915_READ(PIPECONF(pipe)); |
e5a95eb7 ZY |
4009 | temp &= ~PIPE_BPC_MASK; |
4010 | if (is_lvds) { | |
e5a95eb7 | 4011 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
5eddb70b | 4012 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
e5a95eb7 ZY |
4013 | temp |= PIPE_8BPC; |
4014 | else | |
4015 | temp |= PIPE_6BPC; | |
1d850362 | 4016 | } else if (has_edp_encoder) { |
5ceb0f9b | 4017 | switch (dev_priv->edp.bpp/3) { |
885a5fb5 ZW |
4018 | case 8: |
4019 | temp |= PIPE_8BPC; | |
4020 | break; | |
4021 | case 10: | |
4022 | temp |= PIPE_10BPC; | |
4023 | break; | |
4024 | case 6: | |
4025 | temp |= PIPE_6BPC; | |
4026 | break; | |
4027 | case 12: | |
4028 | temp |= PIPE_12BPC; | |
4029 | break; | |
4030 | } | |
e5a95eb7 ZY |
4031 | } else |
4032 | temp |= PIPE_8BPC; | |
5eddb70b | 4033 | I915_WRITE(PIPECONF(pipe), temp); |
58a27471 ZW |
4034 | |
4035 | switch (temp & PIPE_BPC_MASK) { | |
4036 | case PIPE_8BPC: | |
4037 | bpp = 24; | |
4038 | break; | |
4039 | case PIPE_10BPC: | |
4040 | bpp = 30; | |
4041 | break; | |
4042 | case PIPE_6BPC: | |
4043 | bpp = 18; | |
4044 | break; | |
4045 | case PIPE_12BPC: | |
4046 | bpp = 36; | |
4047 | break; | |
4048 | default: | |
4049 | DRM_ERROR("unknown pipe bpc value\n"); | |
4050 | bpp = 24; | |
4051 | } | |
4052 | ||
77ffb597 AJ |
4053 | if (!lane) { |
4054 | /* | |
4055 | * Account for spread spectrum to avoid | |
4056 | * oversubscribing the link. Max center spread | |
4057 | * is 2.5%; use 5% for safety's sake. | |
4058 | */ | |
4059 | u32 bps = target_clock * bpp * 21 / 20; | |
4060 | lane = bps / (link_bw * 8) + 1; | |
4061 | } | |
4062 | ||
4063 | intel_crtc->fdi_lanes = lane; | |
4064 | ||
49078f7d CW |
4065 | if (pixel_multiplier > 1) |
4066 | link_bw *= pixel_multiplier; | |
f2b115e6 | 4067 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 4068 | } |
2c07245f | 4069 | |
c038e51e ZW |
4070 | /* Ironlake: try to setup display ref clock before DPLL |
4071 | * enabling. This is only under driver's control after | |
4072 | * PCH B stepping, previous chipset stepping should be | |
4073 | * ignoring this setting. | |
4074 | */ | |
bad720ff | 4075 | if (HAS_PCH_SPLIT(dev)) { |
c038e51e ZW |
4076 | temp = I915_READ(PCH_DREF_CONTROL); |
4077 | /* Always enable nonspread source */ | |
4078 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
4079 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
c038e51e ZW |
4080 | temp &= ~DREF_SSC_SOURCE_MASK; |
4081 | temp |= DREF_SSC_SOURCE_ENABLE; | |
4082 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 4083 | |
5eddb70b | 4084 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
4085 | udelay(200); |
4086 | ||
8e647a27 | 4087 | if (has_edp_encoder) { |
a7615030 | 4088 | if (intel_panel_use_ssc(dev_priv)) { |
c038e51e ZW |
4089 | temp |= DREF_SSC1_ENABLE; |
4090 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 4091 | |
5eddb70b | 4092 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e | 4093 | udelay(200); |
7f823282 JB |
4094 | } |
4095 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4096 | ||
4097 | /* Enable CPU source on CPU attached eDP */ | |
4098 | if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
a7615030 | 4099 | if (intel_panel_use_ssc(dev_priv)) |
7f823282 JB |
4100 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
4101 | else | |
4102 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
c038e51e | 4103 | } else { |
7f823282 | 4104 | /* Enable SSC on PCH eDP if needed */ |
a7615030 | 4105 | if (intel_panel_use_ssc(dev_priv)) { |
7f823282 JB |
4106 | DRM_ERROR("enabling SSC on PCH\n"); |
4107 | temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; | |
4108 | } | |
c038e51e | 4109 | } |
5eddb70b | 4110 | I915_WRITE(PCH_DREF_CONTROL, temp); |
7f823282 JB |
4111 | POSTING_READ(PCH_DREF_CONTROL); |
4112 | udelay(200); | |
c038e51e ZW |
4113 | } |
4114 | } | |
4115 | ||
f2b115e6 | 4116 | if (IS_PINEVIEW(dev)) { |
2177832f | 4117 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4118 | if (has_reduced_clock) |
4119 | fp2 = (1 << reduced_clock.n) << 16 | | |
4120 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
4121 | } else { | |
2177832f | 4122 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4123 | if (has_reduced_clock) |
4124 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4125 | reduced_clock.m2; | |
4126 | } | |
79e53945 | 4127 | |
c1858123 CW |
4128 | /* Enable autotuning of the PLL clock (if permissible) */ |
4129 | if (HAS_PCH_SPLIT(dev)) { | |
4130 | int factor = 21; | |
4131 | ||
4132 | if (is_lvds) { | |
a7615030 | 4133 | if ((intel_panel_use_ssc(dev_priv) && |
c1858123 CW |
4134 | dev_priv->lvds_ssc_freq == 100) || |
4135 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
4136 | factor = 25; | |
4137 | } else if (is_sdvo && is_tv) | |
4138 | factor = 20; | |
4139 | ||
4140 | if (clock.m1 < factor * clock.n) | |
4141 | fp |= FP_CB_TUNE; | |
4142 | } | |
4143 | ||
5eddb70b | 4144 | dpll = 0; |
bad720ff | 4145 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4146 | dpll = DPLL_VGA_MODE_DIS; |
4147 | ||
a6c45cf0 | 4148 | if (!IS_GEN2(dev)) { |
79e53945 JB |
4149 | if (is_lvds) |
4150 | dpll |= DPLLB_MODE_LVDS; | |
4151 | else | |
4152 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4153 | if (is_sdvo) { | |
6c9547ff CW |
4154 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4155 | if (pixel_multiplier > 1) { | |
4156 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4157 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4158 | else if (HAS_PCH_SPLIT(dev)) | |
4159 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
4160 | } | |
79e53945 | 4161 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4162 | } |
83240120 | 4163 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
a4fc5ed6 | 4164 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
4165 | |
4166 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
4167 | if (IS_PINEVIEW(dev)) |
4168 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 4169 | else { |
2177832f | 4170 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 4171 | /* also FPA1 */ |
bad720ff | 4172 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 4173 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
4174 | if (IS_G4X(dev) && has_reduced_clock) |
4175 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 4176 | } |
79e53945 JB |
4177 | switch (clock.p2) { |
4178 | case 5: | |
4179 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4180 | break; | |
4181 | case 7: | |
4182 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4183 | break; | |
4184 | case 10: | |
4185 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4186 | break; | |
4187 | case 14: | |
4188 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4189 | break; | |
4190 | } | |
a6c45cf0 | 4191 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
4192 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4193 | } else { | |
4194 | if (is_lvds) { | |
4195 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4196 | } else { | |
4197 | if (clock.p1 == 2) | |
4198 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4199 | else | |
4200 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4201 | if (clock.p2 == 4) | |
4202 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4203 | } | |
4204 | } | |
4205 | ||
43565a06 KH |
4206 | if (is_sdvo && is_tv) |
4207 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4208 | else if (is_tv) | |
79e53945 | 4209 | /* XXX: just matching BIOS for now */ |
43565a06 | 4210 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4211 | dpll |= 3; |
a7615030 | 4212 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4213 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4214 | else |
4215 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4216 | ||
4217 | /* setup pipeconf */ | |
5eddb70b | 4218 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4219 | |
4220 | /* Set up the display plane register */ | |
4221 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4222 | ||
f2b115e6 | 4223 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 4224 | enable color space conversion */ |
bad720ff | 4225 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 4226 | if (pipe == 0) |
80824003 | 4227 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
4228 | else |
4229 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4230 | } | |
79e53945 | 4231 | |
a6c45cf0 | 4232 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4233 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4234 | * core speed. | |
4235 | * | |
4236 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4237 | * pipe == 0 check? | |
4238 | */ | |
e70236a8 JB |
4239 | if (mode->clock > |
4240 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4241 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4242 | else |
5eddb70b | 4243 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4244 | } |
4245 | ||
8d86dc6a | 4246 | dspcntr |= DISPLAY_PLANE_ENABLE; |
5eddb70b | 4247 | pipeconf |= PIPECONF_ENABLE; |
8d86dc6a LT |
4248 | dpll |= DPLL_VCO_ENABLE; |
4249 | ||
28c97730 | 4250 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4251 | drm_mode_debug_printmodeline(mode); |
4252 | ||
f2b115e6 | 4253 | /* assign to Ironlake registers */ |
bad720ff | 4254 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4255 | fp_reg = PCH_FP0(pipe); |
4256 | dpll_reg = PCH_DPLL(pipe); | |
4257 | } else { | |
4258 | fp_reg = FP0(pipe); | |
4259 | dpll_reg = DPLL(pipe); | |
2c07245f | 4260 | } |
79e53945 | 4261 | |
5c5313c8 JB |
4262 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4263 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
79e53945 JB |
4264 | I915_WRITE(fp_reg, fp); |
4265 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b CW |
4266 | |
4267 | POSTING_READ(dpll_reg); | |
79e53945 JB |
4268 | udelay(150); |
4269 | } | |
4270 | ||
8db9d77b ZW |
4271 | /* enable transcoder DPLL */ |
4272 | if (HAS_PCH_CPT(dev)) { | |
4273 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b CW |
4274 | if (pipe == 0) |
4275 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; | |
8db9d77b | 4276 | else |
5eddb70b | 4277 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
8db9d77b | 4278 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
4279 | |
4280 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
4281 | udelay(150); |
4282 | } | |
4283 | ||
79e53945 JB |
4284 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4285 | * This is an exception to the general rule that mode_set doesn't turn | |
4286 | * things on. | |
4287 | */ | |
4288 | if (is_lvds) { | |
5eddb70b | 4289 | reg = LVDS; |
bad720ff | 4290 | if (HAS_PCH_SPLIT(dev)) |
5eddb70b | 4291 | reg = PCH_LVDS; |
541998a1 | 4292 | |
5eddb70b CW |
4293 | temp = I915_READ(reg); |
4294 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
b3b095b3 ZW |
4295 | if (pipe == 1) { |
4296 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 4297 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 4298 | else |
5eddb70b | 4299 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
4300 | } else { |
4301 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 4302 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 4303 | else |
5eddb70b | 4304 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 4305 | } |
a3e17eb8 | 4306 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4307 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4308 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4309 | * set the DPLLs for dual-channel mode or not. | |
4310 | */ | |
4311 | if (clock.p2 == 7) | |
5eddb70b | 4312 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4313 | else |
5eddb70b | 4314 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4315 | |
4316 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4317 | * appropriately here, but we need to look more thoroughly into how | |
4318 | * panels behave in the two modes. | |
4319 | */ | |
434ed097 | 4320 | /* set the dithering flag on non-PCH LVDS as needed */ |
a6c45cf0 | 4321 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
434ed097 | 4322 | if (dev_priv->lvds_dither) |
5eddb70b | 4323 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 4324 | else |
5eddb70b | 4325 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 4326 | } |
5eddb70b | 4327 | I915_WRITE(reg, temp); |
79e53945 | 4328 | } |
434ed097 JB |
4329 | |
4330 | /* set the dithering flag and clear for anything other than a panel. */ | |
4331 | if (HAS_PCH_SPLIT(dev)) { | |
4332 | pipeconf &= ~PIPECONF_DITHER_EN; | |
4333 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
4334 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
4335 | pipeconf |= PIPECONF_DITHER_EN; | |
4336 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
4337 | } | |
4338 | } | |
4339 | ||
5c5313c8 | 4340 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 4341 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5c5313c8 | 4342 | } else if (HAS_PCH_SPLIT(dev)) { |
8db9d77b ZW |
4343 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
4344 | if (pipe == 0) { | |
4345 | I915_WRITE(TRANSA_DATA_M1, 0); | |
4346 | I915_WRITE(TRANSA_DATA_N1, 0); | |
4347 | I915_WRITE(TRANSA_DP_LINK_M1, 0); | |
4348 | I915_WRITE(TRANSA_DP_LINK_N1, 0); | |
4349 | } else { | |
4350 | I915_WRITE(TRANSB_DATA_M1, 0); | |
4351 | I915_WRITE(TRANSB_DATA_N1, 0); | |
4352 | I915_WRITE(TRANSB_DP_LINK_M1, 0); | |
4353 | I915_WRITE(TRANSB_DP_LINK_N1, 0); | |
4354 | } | |
4355 | } | |
79e53945 | 4356 | |
5c5313c8 | 4357 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
79e53945 | 4358 | I915_WRITE(dpll_reg, dpll); |
5eddb70b | 4359 | |
32f9d658 | 4360 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 4361 | POSTING_READ(dpll_reg); |
32f9d658 ZW |
4362 | udelay(150); |
4363 | ||
a6c45cf0 | 4364 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
5eddb70b | 4365 | temp = 0; |
bb66c512 | 4366 | if (is_sdvo) { |
5eddb70b CW |
4367 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4368 | if (temp > 1) | |
4369 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6c9547ff | 4370 | else |
5eddb70b CW |
4371 | temp = 0; |
4372 | } | |
4373 | I915_WRITE(DPLL_MD(pipe), temp); | |
32f9d658 | 4374 | } else { |
a589b9f4 CW |
4375 | /* The pixel multiplier can only be updated once the |
4376 | * DPLL is enabled and the clocks are stable. | |
4377 | * | |
4378 | * So write it again. | |
4379 | */ | |
32f9d658 ZW |
4380 | I915_WRITE(dpll_reg, dpll); |
4381 | } | |
79e53945 | 4382 | } |
79e53945 | 4383 | |
5eddb70b | 4384 | intel_crtc->lowfreq_avail = false; |
652c393a JB |
4385 | if (is_lvds && has_reduced_clock && i915_powersave) { |
4386 | I915_WRITE(fp_reg + 4, fp2); | |
4387 | intel_crtc->lowfreq_avail = true; | |
4388 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4389 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
4390 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4391 | } | |
4392 | } else { | |
4393 | I915_WRITE(fp_reg + 4, fp); | |
652c393a | 4394 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 4395 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4396 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4397 | } | |
4398 | } | |
4399 | ||
734b4157 KH |
4400 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4401 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4402 | /* the chip adds 2 halflines automatically */ | |
4403 | adjusted_mode->crtc_vdisplay -= 1; | |
4404 | adjusted_mode->crtc_vtotal -= 1; | |
4405 | adjusted_mode->crtc_vblank_start -= 1; | |
4406 | adjusted_mode->crtc_vblank_end -= 1; | |
4407 | adjusted_mode->crtc_vsync_end -= 1; | |
4408 | adjusted_mode->crtc_vsync_start -= 1; | |
4409 | } else | |
4410 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
4411 | ||
5eddb70b CW |
4412 | I915_WRITE(HTOTAL(pipe), |
4413 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4414 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4415 | I915_WRITE(HBLANK(pipe), |
4416 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4417 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4418 | I915_WRITE(HSYNC(pipe), |
4419 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4420 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4421 | |
4422 | I915_WRITE(VTOTAL(pipe), | |
4423 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4424 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4425 | I915_WRITE(VBLANK(pipe), |
4426 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4427 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4428 | I915_WRITE(VSYNC(pipe), |
4429 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4430 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4431 | |
4432 | /* pipesrc and dspsize control the size that is scaled from, | |
4433 | * which should always be the user's requested size. | |
79e53945 | 4434 | */ |
bad720ff | 4435 | if (!HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4436 | I915_WRITE(DSPSIZE(plane), |
4437 | ((mode->vdisplay - 1) << 16) | | |
4438 | (mode->hdisplay - 1)); | |
4439 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4440 | } |
5eddb70b CW |
4441 | I915_WRITE(PIPESRC(pipe), |
4442 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4443 | |
bad720ff | 4444 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4445 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4446 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4447 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4448 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4449 | |
5c5313c8 | 4450 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
f2b115e6 | 4451 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 | 4452 | } |
2c07245f ZW |
4453 | } |
4454 | ||
5eddb70b CW |
4455 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4456 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 4457 | |
9d0498a2 | 4458 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4459 | |
f00a3ddf | 4460 | if (IS_GEN5(dev)) { |
553bd149 ZW |
4461 | /* enable address swizzle for tiling buffer */ |
4462 | temp = I915_READ(DISP_ARB_CTL); | |
4463 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
4464 | } | |
4465 | ||
5eddb70b | 4466 | I915_WRITE(DSPCNTR(plane), dspcntr); |
79e53945 | 4467 | |
5c3b82e2 | 4468 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4469 | |
4470 | intel_update_watermarks(dev); | |
4471 | ||
79e53945 | 4472 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4473 | |
1f803ee5 | 4474 | return ret; |
79e53945 JB |
4475 | } |
4476 | ||
4477 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4478 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4479 | { | |
4480 | struct drm_device *dev = crtc->dev; | |
4481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4483 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
4484 | int i; | |
4485 | ||
4486 | /* The clocks have to be on to load the palette. */ | |
4487 | if (!crtc->enabled) | |
4488 | return; | |
4489 | ||
f2b115e6 | 4490 | /* use legacy palette for Ironlake */ |
bad720ff | 4491 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4492 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
4493 | LGC_PALETTE_B; | |
4494 | ||
79e53945 JB |
4495 | for (i = 0; i < 256; i++) { |
4496 | I915_WRITE(palreg + 4 * i, | |
4497 | (intel_crtc->lut_r[i] << 16) | | |
4498 | (intel_crtc->lut_g[i] << 8) | | |
4499 | intel_crtc->lut_b[i]); | |
4500 | } | |
4501 | } | |
4502 | ||
560b85bb CW |
4503 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4504 | { | |
4505 | struct drm_device *dev = crtc->dev; | |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4507 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4508 | bool visible = base != 0; | |
4509 | u32 cntl; | |
4510 | ||
4511 | if (intel_crtc->cursor_visible == visible) | |
4512 | return; | |
4513 | ||
4514 | cntl = I915_READ(CURACNTR); | |
4515 | if (visible) { | |
4516 | /* On these chipsets we can only modify the base whilst | |
4517 | * the cursor is disabled. | |
4518 | */ | |
4519 | I915_WRITE(CURABASE, base); | |
4520 | ||
4521 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4522 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4523 | cntl |= CURSOR_ENABLE | | |
4524 | CURSOR_GAMMA_ENABLE | | |
4525 | CURSOR_FORMAT_ARGB; | |
4526 | } else | |
4527 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
4528 | I915_WRITE(CURACNTR, cntl); | |
4529 | ||
4530 | intel_crtc->cursor_visible = visible; | |
4531 | } | |
4532 | ||
4533 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4534 | { | |
4535 | struct drm_device *dev = crtc->dev; | |
4536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4537 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4538 | int pipe = intel_crtc->pipe; | |
4539 | bool visible = base != 0; | |
4540 | ||
4541 | if (intel_crtc->cursor_visible != visible) { | |
4542 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); | |
4543 | if (base) { | |
4544 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4545 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4546 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4547 | } else { | |
4548 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4549 | cntl |= CURSOR_MODE_DISABLE; | |
4550 | } | |
4551 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); | |
4552 | ||
4553 | intel_crtc->cursor_visible = visible; | |
4554 | } | |
4555 | /* and commit changes on next vblank */ | |
4556 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); | |
4557 | } | |
4558 | ||
cda4b7d3 | 4559 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
4560 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
4561 | bool on) | |
cda4b7d3 CW |
4562 | { |
4563 | struct drm_device *dev = crtc->dev; | |
4564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4565 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4566 | int pipe = intel_crtc->pipe; | |
4567 | int x = intel_crtc->cursor_x; | |
4568 | int y = intel_crtc->cursor_y; | |
560b85bb | 4569 | u32 base, pos; |
cda4b7d3 CW |
4570 | bool visible; |
4571 | ||
4572 | pos = 0; | |
4573 | ||
6b383a7f | 4574 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
4575 | base = intel_crtc->cursor_addr; |
4576 | if (x > (int) crtc->fb->width) | |
4577 | base = 0; | |
4578 | ||
4579 | if (y > (int) crtc->fb->height) | |
4580 | base = 0; | |
4581 | } else | |
4582 | base = 0; | |
4583 | ||
4584 | if (x < 0) { | |
4585 | if (x + intel_crtc->cursor_width < 0) | |
4586 | base = 0; | |
4587 | ||
4588 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4589 | x = -x; | |
4590 | } | |
4591 | pos |= x << CURSOR_X_SHIFT; | |
4592 | ||
4593 | if (y < 0) { | |
4594 | if (y + intel_crtc->cursor_height < 0) | |
4595 | base = 0; | |
4596 | ||
4597 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4598 | y = -y; | |
4599 | } | |
4600 | pos |= y << CURSOR_Y_SHIFT; | |
4601 | ||
4602 | visible = base != 0; | |
560b85bb | 4603 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4604 | return; |
4605 | ||
4606 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); | |
560b85bb CW |
4607 | if (IS_845G(dev) || IS_I865G(dev)) |
4608 | i845_update_cursor(crtc, base); | |
4609 | else | |
4610 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
4611 | |
4612 | if (visible) | |
4613 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4614 | } | |
4615 | ||
79e53945 | 4616 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 4617 | struct drm_file *file, |
79e53945 JB |
4618 | uint32_t handle, |
4619 | uint32_t width, uint32_t height) | |
4620 | { | |
4621 | struct drm_device *dev = crtc->dev; | |
4622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 4624 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 4625 | uint32_t addr; |
3f8bc370 | 4626 | int ret; |
79e53945 | 4627 | |
28c97730 | 4628 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4629 | |
4630 | /* if we want to turn off the cursor ignore width and height */ | |
4631 | if (!handle) { | |
28c97730 | 4632 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 4633 | addr = 0; |
05394f39 | 4634 | obj = NULL; |
5004417d | 4635 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4636 | goto finish; |
79e53945 JB |
4637 | } |
4638 | ||
4639 | /* Currently we only support 64x64 cursors */ | |
4640 | if (width != 64 || height != 64) { | |
4641 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4642 | return -EINVAL; | |
4643 | } | |
4644 | ||
05394f39 CW |
4645 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
4646 | if (!obj) | |
79e53945 JB |
4647 | return -ENOENT; |
4648 | ||
05394f39 | 4649 | if (obj->base.size < width * height * 4) { |
79e53945 | 4650 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
4651 | ret = -ENOMEM; |
4652 | goto fail; | |
79e53945 JB |
4653 | } |
4654 | ||
71acb5eb | 4655 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4656 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4657 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
4658 | if (obj->tiling_mode) { |
4659 | DRM_ERROR("cursor cannot be tiled\n"); | |
4660 | ret = -EINVAL; | |
4661 | goto fail_locked; | |
4662 | } | |
4663 | ||
05394f39 | 4664 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
71acb5eb DA |
4665 | if (ret) { |
4666 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 4667 | goto fail_locked; |
71acb5eb | 4668 | } |
e7b526bb | 4669 | |
05394f39 | 4670 | ret = i915_gem_object_set_to_gtt_domain(obj, 0); |
e7b526bb CW |
4671 | if (ret) { |
4672 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4673 | goto fail_unpin; | |
4674 | } | |
4675 | ||
d9e86c0e CW |
4676 | ret = i915_gem_object_put_fence(obj); |
4677 | if (ret) { | |
4678 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4679 | goto fail_unpin; | |
4680 | } | |
4681 | ||
05394f39 | 4682 | addr = obj->gtt_offset; |
71acb5eb | 4683 | } else { |
6eeefaf3 | 4684 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 4685 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
4686 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4687 | align); | |
71acb5eb DA |
4688 | if (ret) { |
4689 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4690 | goto fail_locked; |
71acb5eb | 4691 | } |
05394f39 | 4692 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
4693 | } |
4694 | ||
a6c45cf0 | 4695 | if (IS_GEN2(dev)) |
14b60391 JB |
4696 | I915_WRITE(CURSIZE, (height << 12) | width); |
4697 | ||
3f8bc370 | 4698 | finish: |
3f8bc370 | 4699 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4700 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 4701 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
4702 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
4703 | } else | |
4704 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 4705 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 4706 | } |
80824003 | 4707 | |
7f9872e0 | 4708 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4709 | |
4710 | intel_crtc->cursor_addr = addr; | |
05394f39 | 4711 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
4712 | intel_crtc->cursor_width = width; |
4713 | intel_crtc->cursor_height = height; | |
4714 | ||
6b383a7f | 4715 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 4716 | |
79e53945 | 4717 | return 0; |
e7b526bb | 4718 | fail_unpin: |
05394f39 | 4719 | i915_gem_object_unpin(obj); |
7f9872e0 | 4720 | fail_locked: |
34b8686e | 4721 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 4722 | fail: |
05394f39 | 4723 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 4724 | return ret; |
79e53945 JB |
4725 | } |
4726 | ||
4727 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4728 | { | |
79e53945 | 4729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4730 | |
cda4b7d3 CW |
4731 | intel_crtc->cursor_x = x; |
4732 | intel_crtc->cursor_y = y; | |
652c393a | 4733 | |
6b383a7f | 4734 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
4735 | |
4736 | return 0; | |
4737 | } | |
4738 | ||
4739 | /** Sets the color ramps on behalf of RandR */ | |
4740 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4741 | u16 blue, int regno) | |
4742 | { | |
4743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4744 | ||
4745 | intel_crtc->lut_r[regno] = red >> 8; | |
4746 | intel_crtc->lut_g[regno] = green >> 8; | |
4747 | intel_crtc->lut_b[regno] = blue >> 8; | |
4748 | } | |
4749 | ||
b8c00ac5 DA |
4750 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4751 | u16 *blue, int regno) | |
4752 | { | |
4753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4754 | ||
4755 | *red = intel_crtc->lut_r[regno] << 8; | |
4756 | *green = intel_crtc->lut_g[regno] << 8; | |
4757 | *blue = intel_crtc->lut_b[regno] << 8; | |
4758 | } | |
4759 | ||
79e53945 | 4760 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4761 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4762 | { |
7203425a | 4763 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4764 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4765 | |
7203425a | 4766 | for (i = start; i < end; i++) { |
79e53945 JB |
4767 | intel_crtc->lut_r[i] = red[i] >> 8; |
4768 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4769 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4770 | } | |
4771 | ||
4772 | intel_crtc_load_lut(crtc); | |
4773 | } | |
4774 | ||
4775 | /** | |
4776 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4777 | * detection. | |
4778 | * | |
4779 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4780 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4781 | * |
c751ce4f | 4782 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4783 | * configured for it. In the future, it could choose to temporarily disable |
4784 | * some outputs to free up a pipe for its use. | |
4785 | * | |
4786 | * \return crtc, or NULL if no pipes are available. | |
4787 | */ | |
4788 | ||
4789 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4790 | static struct drm_display_mode load_detect_mode = { | |
4791 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4792 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4793 | }; | |
4794 | ||
21d40d37 | 4795 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 4796 | struct drm_connector *connector, |
79e53945 JB |
4797 | struct drm_display_mode *mode, |
4798 | int *dpms_mode) | |
4799 | { | |
4800 | struct intel_crtc *intel_crtc; | |
4801 | struct drm_crtc *possible_crtc; | |
4802 | struct drm_crtc *supported_crtc =NULL; | |
4ef69c7a | 4803 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4804 | struct drm_crtc *crtc = NULL; |
4805 | struct drm_device *dev = encoder->dev; | |
4806 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4807 | struct drm_crtc_helper_funcs *crtc_funcs; | |
4808 | int i = -1; | |
4809 | ||
4810 | /* | |
4811 | * Algorithm gets a little messy: | |
4812 | * - if the connector already has an assigned crtc, use it (but make | |
4813 | * sure it's on first) | |
4814 | * - try to find the first unused crtc that can drive this connector, | |
4815 | * and use that if we find one | |
4816 | * - if there are no unused crtcs available, try to use the first | |
4817 | * one we found that supports the connector | |
4818 | */ | |
4819 | ||
4820 | /* See if we already have a CRTC for this connector */ | |
4821 | if (encoder->crtc) { | |
4822 | crtc = encoder->crtc; | |
4823 | /* Make sure the crtc and connector are running */ | |
4824 | intel_crtc = to_intel_crtc(crtc); | |
4825 | *dpms_mode = intel_crtc->dpms_mode; | |
4826 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4827 | crtc_funcs = crtc->helper_private; | |
4828 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4829 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
4830 | } | |
4831 | return crtc; | |
4832 | } | |
4833 | ||
4834 | /* Find an unused one (if possible) */ | |
4835 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
4836 | i++; | |
4837 | if (!(encoder->possible_crtcs & (1 << i))) | |
4838 | continue; | |
4839 | if (!possible_crtc->enabled) { | |
4840 | crtc = possible_crtc; | |
4841 | break; | |
4842 | } | |
4843 | if (!supported_crtc) | |
4844 | supported_crtc = possible_crtc; | |
4845 | } | |
4846 | ||
4847 | /* | |
4848 | * If we didn't find an unused CRTC, don't use any. | |
4849 | */ | |
4850 | if (!crtc) { | |
4851 | return NULL; | |
4852 | } | |
4853 | ||
4854 | encoder->crtc = crtc; | |
c1c43977 | 4855 | connector->encoder = encoder; |
21d40d37 | 4856 | intel_encoder->load_detect_temp = true; |
79e53945 JB |
4857 | |
4858 | intel_crtc = to_intel_crtc(crtc); | |
4859 | *dpms_mode = intel_crtc->dpms_mode; | |
4860 | ||
4861 | if (!crtc->enabled) { | |
4862 | if (!mode) | |
4863 | mode = &load_detect_mode; | |
3c4fdcfb | 4864 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
4865 | } else { |
4866 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4867 | crtc_funcs = crtc->helper_private; | |
4868 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4869 | } | |
4870 | ||
4871 | /* Add this connector to the crtc */ | |
4872 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
4873 | encoder_funcs->commit(encoder); | |
4874 | } | |
4875 | /* let the connector get through one full cycle before testing */ | |
9d0498a2 | 4876 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 JB |
4877 | |
4878 | return crtc; | |
4879 | } | |
4880 | ||
c1c43977 ZW |
4881 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
4882 | struct drm_connector *connector, int dpms_mode) | |
79e53945 | 4883 | { |
4ef69c7a | 4884 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4885 | struct drm_device *dev = encoder->dev; |
4886 | struct drm_crtc *crtc = encoder->crtc; | |
4887 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4888 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
4889 | ||
21d40d37 | 4890 | if (intel_encoder->load_detect_temp) { |
79e53945 | 4891 | encoder->crtc = NULL; |
c1c43977 | 4892 | connector->encoder = NULL; |
21d40d37 | 4893 | intel_encoder->load_detect_temp = false; |
79e53945 JB |
4894 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
4895 | drm_helper_disable_unused_functions(dev); | |
4896 | } | |
4897 | ||
c751ce4f | 4898 | /* Switch crtc and encoder back off if necessary */ |
79e53945 JB |
4899 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
4900 | if (encoder->crtc == crtc) | |
4901 | encoder_funcs->dpms(encoder, dpms_mode); | |
4902 | crtc_funcs->dpms(crtc, dpms_mode); | |
4903 | } | |
4904 | } | |
4905 | ||
4906 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
4907 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
4908 | { | |
4909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4910 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4911 | int pipe = intel_crtc->pipe; | |
4912 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
4913 | u32 fp; | |
4914 | intel_clock_t clock; | |
4915 | ||
4916 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
4917 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
4918 | else | |
4919 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
4920 | ||
4921 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
4922 | if (IS_PINEVIEW(dev)) { |
4923 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
4924 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
4925 | } else { |
4926 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
4927 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
4928 | } | |
4929 | ||
a6c45cf0 | 4930 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
4931 | if (IS_PINEVIEW(dev)) |
4932 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
4933 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
4934 | else |
4935 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
4936 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
4937 | ||
4938 | switch (dpll & DPLL_MODE_MASK) { | |
4939 | case DPLLB_MODE_DAC_SERIAL: | |
4940 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
4941 | 5 : 10; | |
4942 | break; | |
4943 | case DPLLB_MODE_LVDS: | |
4944 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
4945 | 7 : 14; | |
4946 | break; | |
4947 | default: | |
28c97730 | 4948 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
4949 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
4950 | return 0; | |
4951 | } | |
4952 | ||
4953 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 4954 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
4955 | } else { |
4956 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
4957 | ||
4958 | if (is_lvds) { | |
4959 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
4960 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
4961 | clock.p2 = 14; | |
4962 | ||
4963 | if ((dpll & PLL_REF_INPUT_MASK) == | |
4964 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
4965 | /* XXX: might not be 66MHz */ | |
2177832f | 4966 | intel_clock(dev, 66000, &clock); |
79e53945 | 4967 | } else |
2177832f | 4968 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4969 | } else { |
4970 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
4971 | clock.p1 = 2; | |
4972 | else { | |
4973 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
4974 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
4975 | } | |
4976 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
4977 | clock.p2 = 4; | |
4978 | else | |
4979 | clock.p2 = 2; | |
4980 | ||
2177832f | 4981 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4982 | } |
4983 | } | |
4984 | ||
4985 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
4986 | * i830PllIsValid() because it relies on the xf86_config connector | |
4987 | * configuration being accurate, which it isn't necessarily. | |
4988 | */ | |
4989 | ||
4990 | return clock.dot; | |
4991 | } | |
4992 | ||
4993 | /** Returns the currently programmed mode of the given pipe. */ | |
4994 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
4995 | struct drm_crtc *crtc) | |
4996 | { | |
4997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4999 | int pipe = intel_crtc->pipe; | |
5000 | struct drm_display_mode *mode; | |
5001 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
5002 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
5003 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
5004 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
5005 | ||
5006 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
5007 | if (!mode) | |
5008 | return NULL; | |
5009 | ||
5010 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
5011 | mode->hdisplay = (htot & 0xffff) + 1; | |
5012 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
5013 | mode->hsync_start = (hsync & 0xffff) + 1; | |
5014 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
5015 | mode->vdisplay = (vtot & 0xffff) + 1; | |
5016 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
5017 | mode->vsync_start = (vsync & 0xffff) + 1; | |
5018 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
5019 | ||
5020 | drm_mode_set_name(mode); | |
5021 | drm_mode_set_crtcinfo(mode, 0); | |
5022 | ||
5023 | return mode; | |
5024 | } | |
5025 | ||
652c393a JB |
5026 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
5027 | ||
5028 | /* When this timer fires, we've been idle for awhile */ | |
5029 | static void intel_gpu_idle_timer(unsigned long arg) | |
5030 | { | |
5031 | struct drm_device *dev = (struct drm_device *)arg; | |
5032 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5033 | ||
ff7ea4c0 CW |
5034 | if (!list_empty(&dev_priv->mm.active_list)) { |
5035 | /* Still processing requests, so just re-arm the timer. */ | |
5036 | mod_timer(&dev_priv->idle_timer, jiffies + | |
5037 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
5038 | return; | |
5039 | } | |
652c393a | 5040 | |
ff7ea4c0 | 5041 | dev_priv->busy = false; |
01dfba93 | 5042 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5043 | } |
5044 | ||
652c393a JB |
5045 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
5046 | ||
5047 | static void intel_crtc_idle_timer(unsigned long arg) | |
5048 | { | |
5049 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
5050 | struct drm_crtc *crtc = &intel_crtc->base; | |
5051 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 5052 | struct intel_framebuffer *intel_fb; |
652c393a | 5053 | |
ff7ea4c0 CW |
5054 | intel_fb = to_intel_framebuffer(crtc->fb); |
5055 | if (intel_fb && intel_fb->obj->active) { | |
5056 | /* The framebuffer is still being accessed by the GPU. */ | |
5057 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5058 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5059 | return; | |
5060 | } | |
652c393a | 5061 | |
ff7ea4c0 | 5062 | intel_crtc->busy = false; |
01dfba93 | 5063 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5064 | } |
5065 | ||
3dec0095 | 5066 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
5067 | { |
5068 | struct drm_device *dev = crtc->dev; | |
5069 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5071 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
5072 | int dpll_reg = DPLL(pipe); |
5073 | int dpll; | |
652c393a | 5074 | |
bad720ff | 5075 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5076 | return; |
5077 | ||
5078 | if (!dev_priv->lvds_downclock_avail) | |
5079 | return; | |
5080 | ||
dbdc6479 | 5081 | dpll = I915_READ(dpll_reg); |
652c393a | 5082 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 5083 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
5084 | |
5085 | /* Unlock panel regs */ | |
dbdc6479 JB |
5086 | I915_WRITE(PP_CONTROL, |
5087 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
652c393a JB |
5088 | |
5089 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
5090 | I915_WRITE(dpll_reg, dpll); | |
dbdc6479 | 5091 | POSTING_READ(dpll_reg); |
9d0498a2 | 5092 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 5093 | |
652c393a JB |
5094 | dpll = I915_READ(dpll_reg); |
5095 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 5096 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
5097 | |
5098 | /* ...and lock them again */ | |
5099 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
5100 | } | |
5101 | ||
5102 | /* Schedule downclock */ | |
3dec0095 DV |
5103 | mod_timer(&intel_crtc->idle_timer, jiffies + |
5104 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
5105 | } |
5106 | ||
5107 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
5108 | { | |
5109 | struct drm_device *dev = crtc->dev; | |
5110 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5112 | int pipe = intel_crtc->pipe; | |
5113 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
5114 | int dpll = I915_READ(dpll_reg); | |
5115 | ||
bad720ff | 5116 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5117 | return; |
5118 | ||
5119 | if (!dev_priv->lvds_downclock_avail) | |
5120 | return; | |
5121 | ||
5122 | /* | |
5123 | * Since this is called by a timer, we should never get here in | |
5124 | * the manual case. | |
5125 | */ | |
5126 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 5127 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
5128 | |
5129 | /* Unlock panel regs */ | |
4a655f04 JB |
5130 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
5131 | PANEL_UNLOCK_REGS); | |
652c393a JB |
5132 | |
5133 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
5134 | I915_WRITE(dpll_reg, dpll); | |
5135 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 5136 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
5137 | dpll = I915_READ(dpll_reg); |
5138 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 5139 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
5140 | |
5141 | /* ...and lock them again */ | |
5142 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
5143 | } | |
5144 | ||
5145 | } | |
5146 | ||
5147 | /** | |
5148 | * intel_idle_update - adjust clocks for idleness | |
5149 | * @work: work struct | |
5150 | * | |
5151 | * Either the GPU or display (or both) went idle. Check the busy status | |
5152 | * here and adjust the CRTC and GPU clocks as necessary. | |
5153 | */ | |
5154 | static void intel_idle_update(struct work_struct *work) | |
5155 | { | |
5156 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
5157 | idle_work); | |
5158 | struct drm_device *dev = dev_priv->dev; | |
5159 | struct drm_crtc *crtc; | |
5160 | struct intel_crtc *intel_crtc; | |
45ac22c8 | 5161 | int enabled = 0; |
652c393a JB |
5162 | |
5163 | if (!i915_powersave) | |
5164 | return; | |
5165 | ||
5166 | mutex_lock(&dev->struct_mutex); | |
5167 | ||
7648fa99 JB |
5168 | i915_update_gfx_val(dev_priv); |
5169 | ||
652c393a JB |
5170 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
5171 | /* Skip inactive CRTCs */ | |
5172 | if (!crtc->fb) | |
5173 | continue; | |
5174 | ||
45ac22c8 | 5175 | enabled++; |
652c393a JB |
5176 | intel_crtc = to_intel_crtc(crtc); |
5177 | if (!intel_crtc->busy) | |
5178 | intel_decrease_pllclock(crtc); | |
5179 | } | |
5180 | ||
45ac22c8 LP |
5181 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
5182 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); | |
5183 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
5184 | } | |
5185 | ||
652c393a JB |
5186 | mutex_unlock(&dev->struct_mutex); |
5187 | } | |
5188 | ||
5189 | /** | |
5190 | * intel_mark_busy - mark the GPU and possibly the display busy | |
5191 | * @dev: drm device | |
5192 | * @obj: object we're operating on | |
5193 | * | |
5194 | * Callers can use this function to indicate that the GPU is busy processing | |
5195 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
5196 | * buffer), we'll also mark the display as busy, so we know to increase its | |
5197 | * clock frequency. | |
5198 | */ | |
05394f39 | 5199 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
5200 | { |
5201 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5202 | struct drm_crtc *crtc = NULL; | |
5203 | struct intel_framebuffer *intel_fb; | |
5204 | struct intel_crtc *intel_crtc; | |
5205 | ||
5e17ee74 ZW |
5206 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
5207 | return; | |
5208 | ||
060e645a LP |
5209 | if (!dev_priv->busy) { |
5210 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
5211 | u32 fw_blc_self; | |
ee980b80 | 5212 | |
060e645a LP |
5213 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
5214 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
5215 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
5216 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
5217 | } | |
28cf798f | 5218 | dev_priv->busy = true; |
060e645a | 5219 | } else |
28cf798f CW |
5220 | mod_timer(&dev_priv->idle_timer, jiffies + |
5221 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
5222 | |
5223 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
5224 | if (!crtc->fb) | |
5225 | continue; | |
5226 | ||
5227 | intel_crtc = to_intel_crtc(crtc); | |
5228 | intel_fb = to_intel_framebuffer(crtc->fb); | |
5229 | if (intel_fb->obj == obj) { | |
5230 | if (!intel_crtc->busy) { | |
060e645a LP |
5231 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
5232 | u32 fw_blc_self; | |
5233 | ||
5234 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | |
5235 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
5236 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
5237 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
5238 | } | |
652c393a | 5239 | /* Non-busy -> busy, upclock */ |
3dec0095 | 5240 | intel_increase_pllclock(crtc); |
652c393a JB |
5241 | intel_crtc->busy = true; |
5242 | } else { | |
5243 | /* Busy -> busy, put off timer */ | |
5244 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5245 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5246 | } | |
5247 | } | |
5248 | } | |
5249 | } | |
5250 | ||
79e53945 JB |
5251 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
5252 | { | |
5253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
5254 | struct drm_device *dev = crtc->dev; |
5255 | struct intel_unpin_work *work; | |
5256 | unsigned long flags; | |
5257 | ||
5258 | spin_lock_irqsave(&dev->event_lock, flags); | |
5259 | work = intel_crtc->unpin_work; | |
5260 | intel_crtc->unpin_work = NULL; | |
5261 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5262 | ||
5263 | if (work) { | |
5264 | cancel_work_sync(&work->work); | |
5265 | kfree(work); | |
5266 | } | |
79e53945 JB |
5267 | |
5268 | drm_crtc_cleanup(crtc); | |
67e77c5a | 5269 | |
79e53945 JB |
5270 | kfree(intel_crtc); |
5271 | } | |
5272 | ||
6b95a207 KH |
5273 | static void intel_unpin_work_fn(struct work_struct *__work) |
5274 | { | |
5275 | struct intel_unpin_work *work = | |
5276 | container_of(__work, struct intel_unpin_work, work); | |
5277 | ||
5278 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 5279 | i915_gem_object_unpin(work->old_fb_obj); |
05394f39 CW |
5280 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
5281 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 5282 | |
6b95a207 KH |
5283 | mutex_unlock(&work->dev->struct_mutex); |
5284 | kfree(work); | |
5285 | } | |
5286 | ||
1afe3e9d | 5287 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 5288 | struct drm_crtc *crtc) |
6b95a207 KH |
5289 | { |
5290 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
5291 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5292 | struct intel_unpin_work *work; | |
05394f39 | 5293 | struct drm_i915_gem_object *obj; |
6b95a207 | 5294 | struct drm_pending_vblank_event *e; |
49b14a5c | 5295 | struct timeval tnow, tvbl; |
6b95a207 KH |
5296 | unsigned long flags; |
5297 | ||
5298 | /* Ignore early vblank irqs */ | |
5299 | if (intel_crtc == NULL) | |
5300 | return; | |
5301 | ||
49b14a5c MK |
5302 | do_gettimeofday(&tnow); |
5303 | ||
6b95a207 KH |
5304 | spin_lock_irqsave(&dev->event_lock, flags); |
5305 | work = intel_crtc->unpin_work; | |
5306 | if (work == NULL || !work->pending) { | |
5307 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5308 | return; | |
5309 | } | |
5310 | ||
5311 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
5312 | |
5313 | if (work->event) { | |
5314 | e = work->event; | |
49b14a5c | 5315 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
5316 | |
5317 | /* Called before vblank count and timestamps have | |
5318 | * been updated for the vblank interval of flip | |
5319 | * completion? Need to increment vblank count and | |
5320 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
5321 | * to account for this. We assume this happened if we |
5322 | * get called over 0.9 frame durations after the last | |
5323 | * timestamped vblank. | |
5324 | * | |
5325 | * This calculation can not be used with vrefresh rates | |
5326 | * below 5Hz (10Hz to be on the safe side) without | |
5327 | * promoting to 64 integers. | |
0af7e4df | 5328 | */ |
49b14a5c MK |
5329 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
5330 | 9 * crtc->framedur_ns) { | |
0af7e4df | 5331 | e->event.sequence++; |
49b14a5c MK |
5332 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
5333 | crtc->framedur_ns); | |
0af7e4df MK |
5334 | } |
5335 | ||
49b14a5c MK |
5336 | e->event.tv_sec = tvbl.tv_sec; |
5337 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 5338 | |
6b95a207 KH |
5339 | list_add_tail(&e->base.link, |
5340 | &e->base.file_priv->event_list); | |
5341 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
5342 | } | |
5343 | ||
0af7e4df MK |
5344 | drm_vblank_put(dev, intel_crtc->pipe); |
5345 | ||
6b95a207 KH |
5346 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5347 | ||
05394f39 | 5348 | obj = work->old_fb_obj; |
d9e86c0e | 5349 | |
e59f2bac | 5350 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
5351 | &obj->pending_flip.counter); |
5352 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 5353 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 5354 | |
6b95a207 | 5355 | schedule_work(&work->work); |
e5510fac JB |
5356 | |
5357 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
5358 | } |
5359 | ||
1afe3e9d JB |
5360 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
5361 | { | |
5362 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5363 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
5364 | ||
49b14a5c | 5365 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
5366 | } |
5367 | ||
5368 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
5369 | { | |
5370 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5371 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
5372 | ||
49b14a5c | 5373 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
5374 | } |
5375 | ||
6b95a207 KH |
5376 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
5377 | { | |
5378 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5379 | struct intel_crtc *intel_crtc = | |
5380 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
5381 | unsigned long flags; | |
5382 | ||
5383 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 5384 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
5385 | if ((++intel_crtc->unpin_work->pending) > 1) |
5386 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
5387 | } else { |
5388 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
5389 | } | |
6b95a207 KH |
5390 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5391 | } | |
5392 | ||
5393 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
5394 | struct drm_framebuffer *fb, | |
5395 | struct drm_pending_vblank_event *event) | |
5396 | { | |
5397 | struct drm_device *dev = crtc->dev; | |
5398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5399 | struct intel_framebuffer *intel_fb; | |
05394f39 | 5400 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
5401 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5402 | struct intel_unpin_work *work; | |
be9a3dbf | 5403 | unsigned long flags, offset; |
52e68630 | 5404 | int pipe = intel_crtc->pipe; |
20f0cd55 | 5405 | u32 pf, pipesrc; |
52e68630 | 5406 | int ret; |
6b95a207 KH |
5407 | |
5408 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5409 | if (work == NULL) | |
5410 | return -ENOMEM; | |
5411 | ||
6b95a207 KH |
5412 | work->event = event; |
5413 | work->dev = crtc->dev; | |
5414 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5415 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5416 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5417 | ||
5418 | /* We borrow the event spin lock for protecting unpin_work */ | |
5419 | spin_lock_irqsave(&dev->event_lock, flags); | |
5420 | if (intel_crtc->unpin_work) { | |
5421 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5422 | kfree(work); | |
468f0b44 CW |
5423 | |
5424 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5425 | return -EBUSY; |
5426 | } | |
5427 | intel_crtc->unpin_work = work; | |
5428 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5429 | ||
5430 | intel_fb = to_intel_framebuffer(fb); | |
5431 | obj = intel_fb->obj; | |
5432 | ||
468f0b44 | 5433 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 | 5434 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
96b099fd CW |
5435 | if (ret) |
5436 | goto cleanup_work; | |
6b95a207 | 5437 | |
75dfca80 | 5438 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
5439 | drm_gem_object_reference(&work->old_fb_obj->base); |
5440 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
5441 | |
5442 | crtc->fb = fb; | |
96b099fd CW |
5443 | |
5444 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
5445 | if (ret) | |
5446 | goto cleanup_objs; | |
5447 | ||
c7f9f9a8 CW |
5448 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
5449 | u32 flip_mask; | |
48b956c5 | 5450 | |
c7f9f9a8 CW |
5451 | /* Can't queue multiple flips, so wait for the previous |
5452 | * one to finish before executing the next. | |
5453 | */ | |
e1f99ce6 CW |
5454 | ret = BEGIN_LP_RING(2); |
5455 | if (ret) | |
5456 | goto cleanup_objs; | |
5457 | ||
c7f9f9a8 CW |
5458 | if (intel_crtc->plane) |
5459 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5460 | else | |
5461 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5462 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5463 | OUT_RING(MI_NOOP); | |
6146b3d6 DV |
5464 | ADVANCE_LP_RING(); |
5465 | } | |
83f7fd05 | 5466 | |
e1f99ce6 | 5467 | work->pending_flip_obj = obj; |
e1f99ce6 | 5468 | |
4e5359cd SF |
5469 | work->enable_stall_check = true; |
5470 | ||
be9a3dbf | 5471 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 5472 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 5473 | |
e1f99ce6 CW |
5474 | ret = BEGIN_LP_RING(4); |
5475 | if (ret) | |
5476 | goto cleanup_objs; | |
5477 | ||
5478 | /* Block clients from rendering to the new back buffer until | |
5479 | * the flip occurs and the object is no longer visible. | |
5480 | */ | |
05394f39 | 5481 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 CW |
5482 | |
5483 | switch (INTEL_INFO(dev)->gen) { | |
52e68630 | 5484 | case 2: |
1afe3e9d JB |
5485 | OUT_RING(MI_DISPLAY_FLIP | |
5486 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5487 | OUT_RING(fb->pitch); | |
05394f39 | 5488 | OUT_RING(obj->gtt_offset + offset); |
52e68630 CW |
5489 | OUT_RING(MI_NOOP); |
5490 | break; | |
5491 | ||
5492 | case 3: | |
1afe3e9d JB |
5493 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
5494 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5495 | OUT_RING(fb->pitch); | |
05394f39 | 5496 | OUT_RING(obj->gtt_offset + offset); |
22fd0fab | 5497 | OUT_RING(MI_NOOP); |
52e68630 CW |
5498 | break; |
5499 | ||
5500 | case 4: | |
5501 | case 5: | |
5502 | /* i965+ uses the linear or tiled offsets from the | |
5503 | * Display Registers (which do not change across a page-flip) | |
5504 | * so we need only reprogram the base address. | |
5505 | */ | |
69d0b96c DV |
5506 | OUT_RING(MI_DISPLAY_FLIP | |
5507 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5508 | OUT_RING(fb->pitch); | |
05394f39 | 5509 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
52e68630 CW |
5510 | |
5511 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5512 | * untested on non-native modes, so ignore it for now. | |
5513 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5514 | */ | |
5515 | pf = 0; | |
5516 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5517 | OUT_RING(pf | pipesrc); | |
5518 | break; | |
5519 | ||
5520 | case 6: | |
5521 | OUT_RING(MI_DISPLAY_FLIP | | |
5522 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
05394f39 CW |
5523 | OUT_RING(fb->pitch | obj->tiling_mode); |
5524 | OUT_RING(obj->gtt_offset); | |
52e68630 CW |
5525 | |
5526 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5527 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5528 | OUT_RING(pf | pipesrc); | |
5529 | break; | |
22fd0fab | 5530 | } |
6b95a207 KH |
5531 | ADVANCE_LP_RING(); |
5532 | ||
5533 | mutex_unlock(&dev->struct_mutex); | |
5534 | ||
e5510fac JB |
5535 | trace_i915_flip_request(intel_crtc->plane, obj); |
5536 | ||
6b95a207 | 5537 | return 0; |
96b099fd CW |
5538 | |
5539 | cleanup_objs: | |
05394f39 CW |
5540 | drm_gem_object_unreference(&work->old_fb_obj->base); |
5541 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
5542 | cleanup_work: |
5543 | mutex_unlock(&dev->struct_mutex); | |
5544 | ||
5545 | spin_lock_irqsave(&dev->event_lock, flags); | |
5546 | intel_crtc->unpin_work = NULL; | |
5547 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5548 | ||
5549 | kfree(work); | |
5550 | ||
5551 | return ret; | |
6b95a207 KH |
5552 | } |
5553 | ||
5d1d0cc8 CW |
5554 | static void intel_crtc_reset(struct drm_crtc *crtc) |
5555 | { | |
5556 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5557 | ||
5558 | /* Reset flags back to the 'unknown' status so that they | |
5559 | * will be correctly set on the initial modeset. | |
5560 | */ | |
5d1d0cc8 | 5561 | intel_crtc->dpms_mode = -1; |
5d1d0cc8 CW |
5562 | } |
5563 | ||
7e7d76c3 | 5564 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
79e53945 JB |
5565 | .dpms = intel_crtc_dpms, |
5566 | .mode_fixup = intel_crtc_mode_fixup, | |
5567 | .mode_set = intel_crtc_mode_set, | |
5568 | .mode_set_base = intel_pipe_set_base, | |
81255565 | 5569 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
068143d3 | 5570 | .load_lut = intel_crtc_load_lut, |
cdd59983 | 5571 | .disable = intel_crtc_disable, |
79e53945 JB |
5572 | }; |
5573 | ||
5574 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
5d1d0cc8 | 5575 | .reset = intel_crtc_reset, |
79e53945 JB |
5576 | .cursor_set = intel_crtc_cursor_set, |
5577 | .cursor_move = intel_crtc_cursor_move, | |
5578 | .gamma_set = intel_crtc_gamma_set, | |
5579 | .set_config = drm_crtc_helper_set_config, | |
5580 | .destroy = intel_crtc_destroy, | |
6b95a207 | 5581 | .page_flip = intel_crtc_page_flip, |
79e53945 JB |
5582 | }; |
5583 | ||
47f1c6c9 CW |
5584 | static void intel_sanitize_modesetting(struct drm_device *dev, |
5585 | int pipe, int plane) | |
5586 | { | |
5587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5588 | u32 reg, val; | |
5589 | ||
5590 | if (HAS_PCH_SPLIT(dev)) | |
5591 | return; | |
5592 | ||
5593 | /* Who knows what state these registers were left in by the BIOS or | |
5594 | * grub? | |
5595 | * | |
5596 | * If we leave the registers in a conflicting state (e.g. with the | |
5597 | * display plane reading from the other pipe than the one we intend | |
5598 | * to use) then when we attempt to teardown the active mode, we will | |
5599 | * not disable the pipes and planes in the correct order -- leaving | |
5600 | * a plane reading from a disabled pipe and possibly leading to | |
5601 | * undefined behaviour. | |
5602 | */ | |
5603 | ||
5604 | reg = DSPCNTR(plane); | |
5605 | val = I915_READ(reg); | |
5606 | ||
5607 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
5608 | return; | |
5609 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
5610 | return; | |
5611 | ||
5612 | /* This display plane is active and attached to the other CPU pipe. */ | |
5613 | pipe = !pipe; | |
5614 | ||
5615 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
5616 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
5617 | intel_flush_display_plane(dev, plane); | |
5618 | ||
5619 | if (IS_GEN2(dev)) | |
5620 | intel_wait_for_vblank(dev, pipe); | |
5621 | ||
5622 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
5623 | return; | |
5624 | ||
5625 | /* Switch off the pipe. */ | |
5626 | reg = PIPECONF(pipe); | |
5627 | val = I915_READ(reg); | |
5628 | if (val & PIPECONF_ENABLE) { | |
5629 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
5630 | intel_wait_for_pipe_off(dev, pipe); | |
5631 | } | |
5632 | } | |
79e53945 | 5633 | |
b358d0a6 | 5634 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 5635 | { |
22fd0fab | 5636 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
5637 | struct intel_crtc *intel_crtc; |
5638 | int i; | |
5639 | ||
5640 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
5641 | if (intel_crtc == NULL) | |
5642 | return; | |
5643 | ||
5644 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
5645 | ||
5646 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
5647 | for (i = 0; i < 256; i++) { |
5648 | intel_crtc->lut_r[i] = i; | |
5649 | intel_crtc->lut_g[i] = i; | |
5650 | intel_crtc->lut_b[i] = i; | |
5651 | } | |
5652 | ||
80824003 JB |
5653 | /* Swap pipes & planes for FBC on pre-965 */ |
5654 | intel_crtc->pipe = pipe; | |
5655 | intel_crtc->plane = pipe; | |
e2e767ab | 5656 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 5657 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 5658 | intel_crtc->plane = !pipe; |
80824003 JB |
5659 | } |
5660 | ||
22fd0fab JB |
5661 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
5662 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
5663 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
5664 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
5665 | ||
5d1d0cc8 | 5666 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 5667 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
7e7d76c3 JB |
5668 | |
5669 | if (HAS_PCH_SPLIT(dev)) { | |
5670 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
5671 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
5672 | } else { | |
5673 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
5674 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
5675 | } | |
5676 | ||
79e53945 JB |
5677 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
5678 | ||
652c393a JB |
5679 | intel_crtc->busy = false; |
5680 | ||
5681 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
5682 | (unsigned long)intel_crtc); | |
47f1c6c9 CW |
5683 | |
5684 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
79e53945 JB |
5685 | } |
5686 | ||
08d7b3d1 | 5687 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 5688 | struct drm_file *file) |
08d7b3d1 CW |
5689 | { |
5690 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5691 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
5692 | struct drm_mode_object *drmmode_obj; |
5693 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
5694 | |
5695 | if (!dev_priv) { | |
5696 | DRM_ERROR("called with no initialization\n"); | |
5697 | return -EINVAL; | |
5698 | } | |
5699 | ||
c05422d5 DV |
5700 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
5701 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 5702 | |
c05422d5 | 5703 | if (!drmmode_obj) { |
08d7b3d1 CW |
5704 | DRM_ERROR("no such CRTC id\n"); |
5705 | return -EINVAL; | |
5706 | } | |
5707 | ||
c05422d5 DV |
5708 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
5709 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 5710 | |
c05422d5 | 5711 | return 0; |
08d7b3d1 CW |
5712 | } |
5713 | ||
c5e4df33 | 5714 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 5715 | { |
4ef69c7a | 5716 | struct intel_encoder *encoder; |
79e53945 | 5717 | int index_mask = 0; |
79e53945 JB |
5718 | int entry = 0; |
5719 | ||
4ef69c7a CW |
5720 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5721 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
5722 | index_mask |= (1 << entry); |
5723 | entry++; | |
5724 | } | |
4ef69c7a | 5725 | |
79e53945 JB |
5726 | return index_mask; |
5727 | } | |
5728 | ||
4d302442 CW |
5729 | static bool has_edp_a(struct drm_device *dev) |
5730 | { | |
5731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5732 | ||
5733 | if (!IS_MOBILE(dev)) | |
5734 | return false; | |
5735 | ||
5736 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
5737 | return false; | |
5738 | ||
5739 | if (IS_GEN5(dev) && | |
5740 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
5741 | return false; | |
5742 | ||
5743 | return true; | |
5744 | } | |
5745 | ||
79e53945 JB |
5746 | static void intel_setup_outputs(struct drm_device *dev) |
5747 | { | |
725e30ad | 5748 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 5749 | struct intel_encoder *encoder; |
cb0953d7 | 5750 | bool dpd_is_edp = false; |
c5d1b51d | 5751 | bool has_lvds = false; |
79e53945 | 5752 | |
541998a1 | 5753 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
5754 | has_lvds = intel_lvds_init(dev); |
5755 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
5756 | /* disable the panel fitter on everything but LVDS */ | |
5757 | I915_WRITE(PFIT_CONTROL, 0); | |
5758 | } | |
79e53945 | 5759 | |
bad720ff | 5760 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 5761 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 5762 | |
4d302442 | 5763 | if (has_edp_a(dev)) |
32f9d658 ZW |
5764 | intel_dp_init(dev, DP_A); |
5765 | ||
cb0953d7 AJ |
5766 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5767 | intel_dp_init(dev, PCH_DP_D); | |
5768 | } | |
5769 | ||
5770 | intel_crt_init(dev); | |
5771 | ||
5772 | if (HAS_PCH_SPLIT(dev)) { | |
5773 | int found; | |
5774 | ||
30ad48b7 | 5775 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
5776 | /* PCH SDVOB multiplex with HDMIB */ |
5777 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
5778 | if (!found) |
5779 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
5780 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
5781 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
5782 | } |
5783 | ||
5784 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
5785 | intel_hdmi_init(dev, HDMIC); | |
5786 | ||
5787 | if (I915_READ(HDMID) & PORT_DETECTED) | |
5788 | intel_hdmi_init(dev, HDMID); | |
5789 | ||
5eb08b69 ZW |
5790 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
5791 | intel_dp_init(dev, PCH_DP_C); | |
5792 | ||
cb0953d7 | 5793 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
5794 | intel_dp_init(dev, PCH_DP_D); |
5795 | ||
103a196f | 5796 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 5797 | bool found = false; |
7d57382e | 5798 | |
725e30ad | 5799 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 5800 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 5801 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
5802 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
5803 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 5804 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 5805 | } |
27185ae1 | 5806 | |
b01f2c3a JB |
5807 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
5808 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 5809 | intel_dp_init(dev, DP_B); |
b01f2c3a | 5810 | } |
725e30ad | 5811 | } |
13520b05 KH |
5812 | |
5813 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 5814 | |
b01f2c3a JB |
5815 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
5816 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 5817 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 5818 | } |
27185ae1 ML |
5819 | |
5820 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
5821 | ||
b01f2c3a JB |
5822 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
5823 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 5824 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
5825 | } |
5826 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
5827 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 5828 | intel_dp_init(dev, DP_C); |
b01f2c3a | 5829 | } |
725e30ad | 5830 | } |
27185ae1 | 5831 | |
b01f2c3a JB |
5832 | if (SUPPORTS_INTEGRATED_DP(dev) && |
5833 | (I915_READ(DP_D) & DP_DETECTED)) { | |
5834 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 5835 | intel_dp_init(dev, DP_D); |
b01f2c3a | 5836 | } |
bad720ff | 5837 | } else if (IS_GEN2(dev)) |
79e53945 JB |
5838 | intel_dvo_init(dev); |
5839 | ||
103a196f | 5840 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
5841 | intel_tv_init(dev); |
5842 | ||
4ef69c7a CW |
5843 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5844 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
5845 | encoder->base.possible_clones = | |
5846 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 5847 | } |
47356eb6 CW |
5848 | |
5849 | intel_panel_setup_backlight(dev); | |
79e53945 JB |
5850 | } |
5851 | ||
5852 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
5853 | { | |
5854 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
5855 | |
5856 | drm_framebuffer_cleanup(fb); | |
05394f39 | 5857 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
5858 | |
5859 | kfree(intel_fb); | |
5860 | } | |
5861 | ||
5862 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 5863 | struct drm_file *file, |
79e53945 JB |
5864 | unsigned int *handle) |
5865 | { | |
5866 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 5867 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 5868 | |
05394f39 | 5869 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
5870 | } |
5871 | ||
5872 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
5873 | .destroy = intel_user_framebuffer_destroy, | |
5874 | .create_handle = intel_user_framebuffer_create_handle, | |
5875 | }; | |
5876 | ||
38651674 DA |
5877 | int intel_framebuffer_init(struct drm_device *dev, |
5878 | struct intel_framebuffer *intel_fb, | |
5879 | struct drm_mode_fb_cmd *mode_cmd, | |
05394f39 | 5880 | struct drm_i915_gem_object *obj) |
79e53945 | 5881 | { |
79e53945 JB |
5882 | int ret; |
5883 | ||
05394f39 | 5884 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
5885 | return -EINVAL; |
5886 | ||
5887 | if (mode_cmd->pitch & 63) | |
5888 | return -EINVAL; | |
5889 | ||
5890 | switch (mode_cmd->bpp) { | |
5891 | case 8: | |
5892 | case 16: | |
5893 | case 24: | |
5894 | case 32: | |
5895 | break; | |
5896 | default: | |
5897 | return -EINVAL; | |
5898 | } | |
5899 | ||
79e53945 JB |
5900 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
5901 | if (ret) { | |
5902 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
5903 | return ret; | |
5904 | } | |
5905 | ||
5906 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 5907 | intel_fb->obj = obj; |
79e53945 JB |
5908 | return 0; |
5909 | } | |
5910 | ||
79e53945 JB |
5911 | static struct drm_framebuffer * |
5912 | intel_user_framebuffer_create(struct drm_device *dev, | |
5913 | struct drm_file *filp, | |
5914 | struct drm_mode_fb_cmd *mode_cmd) | |
5915 | { | |
05394f39 | 5916 | struct drm_i915_gem_object *obj; |
38651674 | 5917 | struct intel_framebuffer *intel_fb; |
79e53945 JB |
5918 | int ret; |
5919 | ||
05394f39 | 5920 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); |
79e53945 | 5921 | if (!obj) |
cce13ff7 | 5922 | return ERR_PTR(-ENOENT); |
79e53945 | 5923 | |
38651674 DA |
5924 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5925 | if (!intel_fb) | |
cce13ff7 | 5926 | return ERR_PTR(-ENOMEM); |
38651674 | 5927 | |
05394f39 | 5928 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
79e53945 | 5929 | if (ret) { |
05394f39 | 5930 | drm_gem_object_unreference_unlocked(&obj->base); |
38651674 | 5931 | kfree(intel_fb); |
cce13ff7 | 5932 | return ERR_PTR(ret); |
79e53945 JB |
5933 | } |
5934 | ||
38651674 | 5935 | return &intel_fb->base; |
79e53945 JB |
5936 | } |
5937 | ||
79e53945 | 5938 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 5939 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 5940 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
5941 | }; |
5942 | ||
05394f39 | 5943 | static struct drm_i915_gem_object * |
aa40d6bb | 5944 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 5945 | { |
05394f39 | 5946 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
5947 | int ret; |
5948 | ||
aa40d6bb ZN |
5949 | ctx = i915_gem_alloc_object(dev, 4096); |
5950 | if (!ctx) { | |
9ea8d059 CW |
5951 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
5952 | return NULL; | |
5953 | } | |
5954 | ||
5955 | mutex_lock(&dev->struct_mutex); | |
75e9e915 | 5956 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
5957 | if (ret) { |
5958 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
5959 | goto err_unref; | |
5960 | } | |
5961 | ||
aa40d6bb | 5962 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
5963 | if (ret) { |
5964 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
5965 | goto err_unpin; | |
5966 | } | |
5967 | mutex_unlock(&dev->struct_mutex); | |
5968 | ||
aa40d6bb | 5969 | return ctx; |
9ea8d059 CW |
5970 | |
5971 | err_unpin: | |
aa40d6bb | 5972 | i915_gem_object_unpin(ctx); |
9ea8d059 | 5973 | err_unref: |
05394f39 | 5974 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
5975 | mutex_unlock(&dev->struct_mutex); |
5976 | return NULL; | |
5977 | } | |
5978 | ||
7648fa99 JB |
5979 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
5980 | { | |
5981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5982 | u16 rgvswctl; | |
5983 | ||
5984 | rgvswctl = I915_READ16(MEMSWCTL); | |
5985 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5986 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5987 | return false; /* still busy with another command */ | |
5988 | } | |
5989 | ||
5990 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5991 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5992 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5993 | POSTING_READ16(MEMSWCTL); | |
5994 | ||
5995 | rgvswctl |= MEMCTL_CMD_STS; | |
5996 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5997 | ||
5998 | return true; | |
5999 | } | |
6000 | ||
f97108d1 JB |
6001 | void ironlake_enable_drps(struct drm_device *dev) |
6002 | { | |
6003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 6004 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 6005 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 6006 | |
ea056c14 JB |
6007 | /* Enable temp reporting */ |
6008 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
6009 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
6010 | ||
f97108d1 JB |
6011 | /* 100ms RC evaluation intervals */ |
6012 | I915_WRITE(RCUPEI, 100000); | |
6013 | I915_WRITE(RCDNEI, 100000); | |
6014 | ||
6015 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
6016 | I915_WRITE(RCBMAXAVG, 90000); | |
6017 | I915_WRITE(RCBMINAVG, 80000); | |
6018 | ||
6019 | I915_WRITE(MEMIHYST, 1); | |
6020 | ||
6021 | /* Set up min, max, and cur for interrupt handling */ | |
6022 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
6023 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
6024 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
6025 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 6026 | |
f97108d1 JB |
6027 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
6028 | PXVFREQ_PX_SHIFT; | |
6029 | ||
80dbf4b7 | 6030 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
6031 | dev_priv->fstart = fstart; |
6032 | ||
80dbf4b7 | 6033 | dev_priv->max_delay = fstart; |
f97108d1 JB |
6034 | dev_priv->min_delay = fmin; |
6035 | dev_priv->cur_delay = fstart; | |
6036 | ||
80dbf4b7 JB |
6037 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
6038 | fmax, fmin, fstart); | |
7648fa99 | 6039 | |
f97108d1 JB |
6040 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
6041 | ||
6042 | /* | |
6043 | * Interrupts will be enabled in ironlake_irq_postinstall | |
6044 | */ | |
6045 | ||
6046 | I915_WRITE(VIDSTART, vstart); | |
6047 | POSTING_READ(VIDSTART); | |
6048 | ||
6049 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
6050 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
6051 | ||
481b6af3 | 6052 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 6053 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
6054 | msleep(1); |
6055 | ||
7648fa99 | 6056 | ironlake_set_drps(dev, fstart); |
f97108d1 | 6057 | |
7648fa99 JB |
6058 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
6059 | I915_READ(0x112e0); | |
6060 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
6061 | dev_priv->last_count2 = I915_READ(0x112f4); | |
6062 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
6063 | } |
6064 | ||
6065 | void ironlake_disable_drps(struct drm_device *dev) | |
6066 | { | |
6067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 6068 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
6069 | |
6070 | /* Ack interrupts, disable EFC interrupt */ | |
6071 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
6072 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
6073 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
6074 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
6075 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
6076 | ||
6077 | /* Go back to the starting frequency */ | |
7648fa99 | 6078 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
6079 | msleep(1); |
6080 | rgvswctl |= MEMCTL_CMD_STS; | |
6081 | I915_WRITE(MEMSWCTL, rgvswctl); | |
6082 | msleep(1); | |
6083 | ||
6084 | } | |
6085 | ||
3b8d8d91 JB |
6086 | void gen6_set_rps(struct drm_device *dev, u8 val) |
6087 | { | |
6088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6089 | u32 swreq; | |
6090 | ||
6091 | swreq = (val & 0x3ff) << 25; | |
6092 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
6093 | } | |
6094 | ||
6095 | void gen6_disable_rps(struct drm_device *dev) | |
6096 | { | |
6097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6098 | ||
6099 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
6100 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
6101 | I915_WRITE(GEN6_PMIER, 0); | |
6102 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); | |
6103 | } | |
6104 | ||
7648fa99 JB |
6105 | static unsigned long intel_pxfreq(u32 vidfreq) |
6106 | { | |
6107 | unsigned long freq; | |
6108 | int div = (vidfreq & 0x3f0000) >> 16; | |
6109 | int post = (vidfreq & 0x3000) >> 12; | |
6110 | int pre = (vidfreq & 0x7); | |
6111 | ||
6112 | if (!pre) | |
6113 | return 0; | |
6114 | ||
6115 | freq = ((div * 133333) / ((1<<post) * pre)); | |
6116 | ||
6117 | return freq; | |
6118 | } | |
6119 | ||
6120 | void intel_init_emon(struct drm_device *dev) | |
6121 | { | |
6122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6123 | u32 lcfuse; | |
6124 | u8 pxw[16]; | |
6125 | int i; | |
6126 | ||
6127 | /* Disable to program */ | |
6128 | I915_WRITE(ECR, 0); | |
6129 | POSTING_READ(ECR); | |
6130 | ||
6131 | /* Program energy weights for various events */ | |
6132 | I915_WRITE(SDEW, 0x15040d00); | |
6133 | I915_WRITE(CSIEW0, 0x007f0000); | |
6134 | I915_WRITE(CSIEW1, 0x1e220004); | |
6135 | I915_WRITE(CSIEW2, 0x04000004); | |
6136 | ||
6137 | for (i = 0; i < 5; i++) | |
6138 | I915_WRITE(PEW + (i * 4), 0); | |
6139 | for (i = 0; i < 3; i++) | |
6140 | I915_WRITE(DEW + (i * 4), 0); | |
6141 | ||
6142 | /* Program P-state weights to account for frequency power adjustment */ | |
6143 | for (i = 0; i < 16; i++) { | |
6144 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
6145 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
6146 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
6147 | PXVFREQ_PX_SHIFT; | |
6148 | unsigned long val; | |
6149 | ||
6150 | val = vid * vid; | |
6151 | val *= (freq / 1000); | |
6152 | val *= 255; | |
6153 | val /= (127*127*900); | |
6154 | if (val > 0xff) | |
6155 | DRM_ERROR("bad pxval: %ld\n", val); | |
6156 | pxw[i] = val; | |
6157 | } | |
6158 | /* Render standby states get 0 weight */ | |
6159 | pxw[14] = 0; | |
6160 | pxw[15] = 0; | |
6161 | ||
6162 | for (i = 0; i < 4; i++) { | |
6163 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
6164 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
6165 | I915_WRITE(PXW + (i * 4), val); | |
6166 | } | |
6167 | ||
6168 | /* Adjust magic regs to magic values (more experimental results) */ | |
6169 | I915_WRITE(OGW0, 0); | |
6170 | I915_WRITE(OGW1, 0); | |
6171 | I915_WRITE(EG0, 0x00007f00); | |
6172 | I915_WRITE(EG1, 0x0000000e); | |
6173 | I915_WRITE(EG2, 0x000e0000); | |
6174 | I915_WRITE(EG3, 0x68000300); | |
6175 | I915_WRITE(EG4, 0x42000000); | |
6176 | I915_WRITE(EG5, 0x00140031); | |
6177 | I915_WRITE(EG6, 0); | |
6178 | I915_WRITE(EG7, 0); | |
6179 | ||
6180 | for (i = 0; i < 8; i++) | |
6181 | I915_WRITE(PXWL + (i * 4), 0); | |
6182 | ||
6183 | /* Enable PMON + select events */ | |
6184 | I915_WRITE(ECR, 0x80000019); | |
6185 | ||
6186 | lcfuse = I915_READ(LCFUSE02); | |
6187 | ||
6188 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
6189 | } | |
6190 | ||
3b8d8d91 | 6191 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 6192 | { |
a6044e23 JB |
6193 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
6194 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
6195 | u32 pcu_mbox; | |
6196 | int cur_freq, min_freq, max_freq; | |
8fd26859 CW |
6197 | int i; |
6198 | ||
6199 | /* Here begins a magic sequence of register writes to enable | |
6200 | * auto-downclocking. | |
6201 | * | |
6202 | * Perhaps there might be some value in exposing these to | |
6203 | * userspace... | |
6204 | */ | |
6205 | I915_WRITE(GEN6_RC_STATE, 0); | |
6206 | __gen6_force_wake_get(dev_priv); | |
6207 | ||
3b8d8d91 | 6208 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
6209 | I915_WRITE(GEN6_RC_CONTROL, 0); |
6210 | ||
6211 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
6212 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
6213 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
6214 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
6215 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
6216 | ||
6217 | for (i = 0; i < I915_NUM_RINGS; i++) | |
6218 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
6219 | ||
6220 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
6221 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
6222 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
6223 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
6224 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
6225 | ||
6226 | I915_WRITE(GEN6_RC_CONTROL, | |
6227 | GEN6_RC_CTL_RC6p_ENABLE | | |
6228 | GEN6_RC_CTL_RC6_ENABLE | | |
9c3d2f7f | 6229 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
6230 | GEN6_RC_CTL_HW_ENABLE); |
6231 | ||
3b8d8d91 | 6232 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
6233 | GEN6_FREQUENCY(10) | |
6234 | GEN6_OFFSET(0) | | |
6235 | GEN6_AGGRESSIVE_TURBO); | |
6236 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
6237 | GEN6_FREQUENCY(12)); | |
6238 | ||
6239 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
6240 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
6241 | 18 << 24 | | |
6242 | 6 << 16); | |
6243 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000); | |
6244 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000); | |
6245 | I915_WRITE(GEN6_RP_UP_EI, 100000); | |
6246 | I915_WRITE(GEN6_RP_DOWN_EI, 300000); | |
6247 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6248 | I915_WRITE(GEN6_RP_CONTROL, | |
6249 | GEN6_RP_MEDIA_TURBO | | |
6250 | GEN6_RP_USE_NORMAL_FREQ | | |
6251 | GEN6_RP_MEDIA_IS_GFX | | |
6252 | GEN6_RP_ENABLE | | |
6253 | GEN6_RP_UP_BUSY_MAX | | |
6254 | GEN6_RP_DOWN_BUSY_MIN); | |
6255 | ||
6256 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6257 | 500)) | |
6258 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
6259 | ||
6260 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6261 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
6262 | GEN6_PCODE_READY | | |
6263 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
6264 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6265 | 500)) | |
6266 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
6267 | ||
a6044e23 JB |
6268 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
6269 | max_freq = rp_state_cap & 0xff; | |
6270 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
6271 | ||
6272 | /* Check for overclock support */ | |
6273 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6274 | 500)) | |
6275 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
6276 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
6277 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
6278 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6279 | 500)) | |
6280 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
6281 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
6282 | max_freq = pcu_mbox & 0xff; | |
6283 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100); | |
6284 | } | |
6285 | ||
6286 | /* In units of 100MHz */ | |
6287 | dev_priv->max_delay = max_freq; | |
6288 | dev_priv->min_delay = min_freq; | |
6289 | dev_priv->cur_delay = cur_freq; | |
6290 | ||
8fd26859 CW |
6291 | /* requires MSI enabled */ |
6292 | I915_WRITE(GEN6_PMIER, | |
6293 | GEN6_PM_MBOX_EVENT | | |
6294 | GEN6_PM_THERMAL_EVENT | | |
6295 | GEN6_PM_RP_DOWN_TIMEOUT | | |
6296 | GEN6_PM_RP_UP_THRESHOLD | | |
6297 | GEN6_PM_RP_DOWN_THRESHOLD | | |
6298 | GEN6_PM_RP_UP_EI_EXPIRED | | |
6299 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
3b8d8d91 JB |
6300 | I915_WRITE(GEN6_PMIMR, 0); |
6301 | /* enable all PM interrupts */ | |
6302 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 CW |
6303 | |
6304 | __gen6_force_wake_put(dev_priv); | |
6305 | } | |
6306 | ||
0cdab21f | 6307 | void intel_enable_clock_gating(struct drm_device *dev) |
652c393a JB |
6308 | { |
6309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6310 | ||
6311 | /* | |
6312 | * Disable clock gating reported to work incorrectly according to the | |
6313 | * specs, but enable as much else as we can. | |
6314 | */ | |
bad720ff | 6315 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
6316 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
6317 | ||
f00a3ddf | 6318 | if (IS_GEN5(dev)) { |
8956c8bb | 6319 | /* Required for FBC */ |
1ffa325b JB |
6320 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
6321 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
6322 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8956c8bb EA |
6323 | /* Required for CxSR */ |
6324 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
6325 | ||
6326 | I915_WRITE(PCH_3DCGDIS0, | |
6327 | MARIUNIT_CLOCK_GATE_DISABLE | | |
6328 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
06f37751 EA |
6329 | I915_WRITE(PCH_3DCGDIS1, |
6330 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8956c8bb EA |
6331 | } |
6332 | ||
6333 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 | 6334 | |
382b0936 JB |
6335 | /* |
6336 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6337 | * gating for the panel power sequencer or it will fail to | |
6338 | * start up when no ports are active. | |
6339 | */ | |
6340 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
6341 | ||
7f8a8569 ZW |
6342 | /* |
6343 | * According to the spec the following bits should be set in | |
6344 | * order to enable memory self-refresh | |
6345 | * The bit 22/21 of 0x42004 | |
6346 | * The bit 5 of 0x42020 | |
6347 | * The bit 15 of 0x45000 | |
6348 | */ | |
f00a3ddf | 6349 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
6350 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6351 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6352 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
6353 | I915_WRITE(ILK_DSPCLK_GATE, | |
6354 | (I915_READ(ILK_DSPCLK_GATE) | | |
6355 | ILK_DPARB_CLK_GATE)); | |
6356 | I915_WRITE(DISP_ARB_CTL, | |
6357 | (I915_READ(DISP_ARB_CTL) | | |
6358 | DISP_FBC_WM_DIS)); | |
1398261a YL |
6359 | I915_WRITE(WM3_LP_ILK, 0); |
6360 | I915_WRITE(WM2_LP_ILK, 0); | |
6361 | I915_WRITE(WM1_LP_ILK, 0); | |
7f8a8569 | 6362 | } |
b52eb4dc ZY |
6363 | /* |
6364 | * Based on the document from hardware guys the following bits | |
6365 | * should be set unconditionally in order to enable FBC. | |
6366 | * The bit 22 of 0x42000 | |
6367 | * The bit 22 of 0x42004 | |
6368 | * The bit 7,8,9 of 0x42020. | |
6369 | */ | |
6370 | if (IS_IRONLAKE_M(dev)) { | |
6371 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6372 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6373 | ILK_FBCQ_DIS); | |
6374 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6375 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6376 | ILK_DPARB_GATE); | |
6377 | I915_WRITE(ILK_DSPCLK_GATE, | |
6378 | I915_READ(ILK_DSPCLK_GATE) | | |
6379 | ILK_DPFC_DIS1 | | |
6380 | ILK_DPFC_DIS2 | | |
6381 | ILK_CLK_FBC); | |
6382 | } | |
de6e2eaf | 6383 | |
67e92af0 EA |
6384 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6385 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6386 | ILK_ELPIN_409_SELECT); | |
6387 | ||
de6e2eaf EA |
6388 | if (IS_GEN5(dev)) { |
6389 | I915_WRITE(_3D_CHICKEN2, | |
6390 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
6391 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
6392 | } | |
8fd26859 | 6393 | |
1398261a YL |
6394 | if (IS_GEN6(dev)) { |
6395 | I915_WRITE(WM3_LP_ILK, 0); | |
6396 | I915_WRITE(WM2_LP_ILK, 0); | |
6397 | I915_WRITE(WM1_LP_ILK, 0); | |
6398 | ||
6399 | /* | |
6400 | * According to the spec the following bits should be | |
6401 | * set in order to enable memory self-refresh and fbc: | |
6402 | * The bit21 and bit22 of 0x42000 | |
6403 | * The bit21 and bit22 of 0x42004 | |
6404 | * The bit5 and bit7 of 0x42020 | |
6405 | * The bit14 of 0x70180 | |
6406 | * The bit14 of 0x71180 | |
6407 | */ | |
6408 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6409 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6410 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
6411 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6412 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6413 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
6414 | I915_WRITE(ILK_DSPCLK_GATE, | |
6415 | I915_READ(ILK_DSPCLK_GATE) | | |
6416 | ILK_DPARB_CLK_GATE | | |
6417 | ILK_DPFD_CLK_GATE); | |
6418 | ||
6419 | I915_WRITE(DSPACNTR, | |
6420 | I915_READ(DSPACNTR) | | |
6421 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
6422 | I915_WRITE(DSPBCNTR, | |
6423 | I915_READ(DSPBCNTR) | | |
6424 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
6425 | } | |
c03342fa | 6426 | } else if (IS_G4X(dev)) { |
652c393a JB |
6427 | uint32_t dspclk_gate; |
6428 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6429 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6430 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6431 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6432 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6433 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6434 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6435 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6436 | if (IS_GM45(dev)) | |
6437 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6438 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
a6c45cf0 | 6439 | } else if (IS_CRESTLINE(dev)) { |
652c393a JB |
6440 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
6441 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6442 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6443 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6444 | I915_WRITE16(DEUC, 0); | |
a6c45cf0 | 6445 | } else if (IS_BROADWATER(dev)) { |
652c393a JB |
6446 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
6447 | I965_RCC_CLOCK_GATE_DISABLE | | |
6448 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6449 | I965_ISC_CLOCK_GATE_DISABLE | | |
6450 | I965_FBC_CLOCK_GATE_DISABLE); | |
6451 | I915_WRITE(RENCLK_GATE_D2, 0); | |
a6c45cf0 | 6452 | } else if (IS_GEN3(dev)) { |
652c393a JB |
6453 | u32 dstate = I915_READ(D_STATE); |
6454 | ||
6455 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6456 | DSTATE_DOT_CLOCK_GATING; | |
6457 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 6458 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
6459 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
6460 | } else if (IS_I830(dev)) { | |
6461 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
6462 | } | |
6463 | } | |
6464 | ||
ac668088 | 6465 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
6466 | { |
6467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6468 | ||
6469 | if (dev_priv->renderctx) { | |
ac668088 CW |
6470 | i915_gem_object_unpin(dev_priv->renderctx); |
6471 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
6472 | dev_priv->renderctx = NULL; |
6473 | } | |
6474 | ||
6475 | if (dev_priv->pwrctx) { | |
ac668088 CW |
6476 | i915_gem_object_unpin(dev_priv->pwrctx); |
6477 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
6478 | dev_priv->pwrctx = NULL; | |
6479 | } | |
6480 | } | |
6481 | ||
6482 | static void ironlake_disable_rc6(struct drm_device *dev) | |
6483 | { | |
6484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6485 | ||
6486 | if (I915_READ(PWRCTXA)) { | |
6487 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
6488 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
6489 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
6490 | 50); | |
0cdab21f CW |
6491 | |
6492 | I915_WRITE(PWRCTXA, 0); | |
6493 | POSTING_READ(PWRCTXA); | |
6494 | ||
ac668088 CW |
6495 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
6496 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 6497 | } |
ac668088 CW |
6498 | |
6499 | ironlake_disable_rc6(dev); | |
0cdab21f CW |
6500 | } |
6501 | ||
ac668088 | 6502 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
6503 | { |
6504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6505 | ||
ac668088 CW |
6506 | if (dev_priv->renderctx == NULL) |
6507 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
6508 | if (!dev_priv->renderctx) | |
6509 | return -ENOMEM; | |
6510 | ||
6511 | if (dev_priv->pwrctx == NULL) | |
6512 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
6513 | if (!dev_priv->pwrctx) { | |
6514 | ironlake_teardown_rc6(dev); | |
6515 | return -ENOMEM; | |
6516 | } | |
6517 | ||
6518 | return 0; | |
d5bb081b JB |
6519 | } |
6520 | ||
6521 | void ironlake_enable_rc6(struct drm_device *dev) | |
6522 | { | |
6523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6524 | int ret; | |
6525 | ||
ac668088 CW |
6526 | /* rc6 disabled by default due to repeated reports of hanging during |
6527 | * boot and resume. | |
6528 | */ | |
6529 | if (!i915_enable_rc6) | |
6530 | return; | |
6531 | ||
6532 | ret = ironlake_setup_rc6(dev); | |
6533 | if (ret) | |
6534 | return; | |
6535 | ||
d5bb081b JB |
6536 | /* |
6537 | * GPU can automatically power down the render unit if given a page | |
6538 | * to save state. | |
6539 | */ | |
6540 | ret = BEGIN_LP_RING(6); | |
6541 | if (ret) { | |
ac668088 | 6542 | ironlake_teardown_rc6(dev); |
d5bb081b JB |
6543 | return; |
6544 | } | |
ac668088 | 6545 | |
d5bb081b JB |
6546 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
6547 | OUT_RING(MI_SET_CONTEXT); | |
6548 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
6549 | MI_MM_SPACE_GTT | | |
6550 | MI_SAVE_EXT_STATE_EN | | |
6551 | MI_RESTORE_EXT_STATE_EN | | |
6552 | MI_RESTORE_INHIBIT); | |
6553 | OUT_RING(MI_SUSPEND_FLUSH); | |
6554 | OUT_RING(MI_NOOP); | |
6555 | OUT_RING(MI_FLUSH); | |
6556 | ADVANCE_LP_RING(); | |
6557 | ||
6558 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); | |
6559 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
6560 | } | |
6561 | ||
ac668088 | 6562 | |
e70236a8 JB |
6563 | /* Set up chip specific display functions */ |
6564 | static void intel_init_display(struct drm_device *dev) | |
6565 | { | |
6566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6567 | ||
6568 | /* We always want a DPMS function */ | |
bad720ff | 6569 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 6570 | dev_priv->display.dpms = ironlake_crtc_dpms; |
e70236a8 JB |
6571 | else |
6572 | dev_priv->display.dpms = i9xx_crtc_dpms; | |
6573 | ||
ee5382ae | 6574 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 6575 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
6576 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
6577 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
6578 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
6579 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
6580 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
6581 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
6582 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 6583 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
6584 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
6585 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
6586 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
6587 | } | |
74dff282 | 6588 | /* 855GM needs testing */ |
e70236a8 JB |
6589 | } |
6590 | ||
6591 | /* Returns the core display clock speed */ | |
f2b115e6 | 6592 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
6593 | dev_priv->display.get_display_clock_speed = |
6594 | i945_get_display_clock_speed; | |
6595 | else if (IS_I915G(dev)) | |
6596 | dev_priv->display.get_display_clock_speed = | |
6597 | i915_get_display_clock_speed; | |
f2b115e6 | 6598 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
6599 | dev_priv->display.get_display_clock_speed = |
6600 | i9xx_misc_get_display_clock_speed; | |
6601 | else if (IS_I915GM(dev)) | |
6602 | dev_priv->display.get_display_clock_speed = | |
6603 | i915gm_get_display_clock_speed; | |
6604 | else if (IS_I865G(dev)) | |
6605 | dev_priv->display.get_display_clock_speed = | |
6606 | i865_get_display_clock_speed; | |
f0f8a9ce | 6607 | else if (IS_I85X(dev)) |
e70236a8 JB |
6608 | dev_priv->display.get_display_clock_speed = |
6609 | i855_get_display_clock_speed; | |
6610 | else /* 852, 830 */ | |
6611 | dev_priv->display.get_display_clock_speed = | |
6612 | i830_get_display_clock_speed; | |
6613 | ||
6614 | /* For FIFO watermark updates */ | |
7f8a8569 | 6615 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 6616 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
6617 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
6618 | dev_priv->display.update_wm = ironlake_update_wm; | |
6619 | else { | |
6620 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
6621 | "Disable CxSR\n"); | |
6622 | dev_priv->display.update_wm = NULL; | |
1398261a YL |
6623 | } |
6624 | } else if (IS_GEN6(dev)) { | |
6625 | if (SNB_READ_WM0_LATENCY()) { | |
6626 | dev_priv->display.update_wm = sandybridge_update_wm; | |
6627 | } else { | |
6628 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6629 | "Disable CxSR\n"); | |
6630 | dev_priv->display.update_wm = NULL; | |
7f8a8569 ZW |
6631 | } |
6632 | } else | |
6633 | dev_priv->display.update_wm = NULL; | |
6634 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 6635 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 6636 | dev_priv->is_ddr3, |
d4294342 ZY |
6637 | dev_priv->fsb_freq, |
6638 | dev_priv->mem_freq)) { | |
6639 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 6640 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 6641 | "disabling CxSR\n", |
95534263 | 6642 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
6643 | dev_priv->fsb_freq, dev_priv->mem_freq); |
6644 | /* Disable CxSR and never update its watermark again */ | |
6645 | pineview_disable_cxsr(dev); | |
6646 | dev_priv->display.update_wm = NULL; | |
6647 | } else | |
6648 | dev_priv->display.update_wm = pineview_update_wm; | |
6649 | } else if (IS_G4X(dev)) | |
e70236a8 | 6650 | dev_priv->display.update_wm = g4x_update_wm; |
a6c45cf0 | 6651 | else if (IS_GEN4(dev)) |
e70236a8 | 6652 | dev_priv->display.update_wm = i965_update_wm; |
a6c45cf0 | 6653 | else if (IS_GEN3(dev)) { |
e70236a8 JB |
6654 | dev_priv->display.update_wm = i9xx_update_wm; |
6655 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
6656 | } else if (IS_I85X(dev)) { |
6657 | dev_priv->display.update_wm = i9xx_update_wm; | |
6658 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 6659 | } else { |
8f4695ed AJ |
6660 | dev_priv->display.update_wm = i830_update_wm; |
6661 | if (IS_845G(dev)) | |
e70236a8 JB |
6662 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
6663 | else | |
6664 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
6665 | } |
6666 | } | |
6667 | ||
b690e96c JB |
6668 | /* |
6669 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
6670 | * resume, or other times. This quirk makes sure that's the case for | |
6671 | * affected systems. | |
6672 | */ | |
6673 | static void quirk_pipea_force (struct drm_device *dev) | |
6674 | { | |
6675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6676 | ||
6677 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
6678 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
6679 | } | |
6680 | ||
6681 | struct intel_quirk { | |
6682 | int device; | |
6683 | int subsystem_vendor; | |
6684 | int subsystem_device; | |
6685 | void (*hook)(struct drm_device *dev); | |
6686 | }; | |
6687 | ||
6688 | struct intel_quirk intel_quirks[] = { | |
6689 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
6690 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
6691 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
6692 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
6693 | ||
6694 | /* Thinkpad R31 needs pipe A force quirk */ | |
6695 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
6696 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
6697 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
6698 | ||
6699 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
6700 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
6701 | /* ThinkPad X40 needs pipe A force quirk */ | |
6702 | ||
6703 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
6704 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
6705 | ||
6706 | /* 855 & before need to leave pipe A & dpll A up */ | |
6707 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6708 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6709 | }; | |
6710 | ||
6711 | static void intel_init_quirks(struct drm_device *dev) | |
6712 | { | |
6713 | struct pci_dev *d = dev->pdev; | |
6714 | int i; | |
6715 | ||
6716 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
6717 | struct intel_quirk *q = &intel_quirks[i]; | |
6718 | ||
6719 | if (d->device == q->device && | |
6720 | (d->subsystem_vendor == q->subsystem_vendor || | |
6721 | q->subsystem_vendor == PCI_ANY_ID) && | |
6722 | (d->subsystem_device == q->subsystem_device || | |
6723 | q->subsystem_device == PCI_ANY_ID)) | |
6724 | q->hook(dev); | |
6725 | } | |
6726 | } | |
6727 | ||
9cce37f4 JB |
6728 | /* Disable the VGA plane that we never use */ |
6729 | static void i915_disable_vga(struct drm_device *dev) | |
6730 | { | |
6731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6732 | u8 sr1; | |
6733 | u32 vga_reg; | |
6734 | ||
6735 | if (HAS_PCH_SPLIT(dev)) | |
6736 | vga_reg = CPU_VGACNTRL; | |
6737 | else | |
6738 | vga_reg = VGACNTRL; | |
6739 | ||
6740 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6741 | outb(1, VGA_SR_INDEX); | |
6742 | sr1 = inb(VGA_SR_DATA); | |
6743 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6744 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6745 | udelay(300); | |
6746 | ||
6747 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6748 | POSTING_READ(vga_reg); | |
6749 | } | |
6750 | ||
79e53945 JB |
6751 | void intel_modeset_init(struct drm_device *dev) |
6752 | { | |
652c393a | 6753 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6754 | int i; |
6755 | ||
6756 | drm_mode_config_init(dev); | |
6757 | ||
6758 | dev->mode_config.min_width = 0; | |
6759 | dev->mode_config.min_height = 0; | |
6760 | ||
6761 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
6762 | ||
b690e96c JB |
6763 | intel_init_quirks(dev); |
6764 | ||
e70236a8 JB |
6765 | intel_init_display(dev); |
6766 | ||
a6c45cf0 CW |
6767 | if (IS_GEN2(dev)) { |
6768 | dev->mode_config.max_width = 2048; | |
6769 | dev->mode_config.max_height = 2048; | |
6770 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
6771 | dev->mode_config.max_width = 4096; |
6772 | dev->mode_config.max_height = 4096; | |
79e53945 | 6773 | } else { |
a6c45cf0 CW |
6774 | dev->mode_config.max_width = 8192; |
6775 | dev->mode_config.max_height = 8192; | |
79e53945 | 6776 | } |
35c3047a | 6777 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 6778 | |
a6c45cf0 | 6779 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
a3524f1b | 6780 | dev_priv->num_pipe = 2; |
79e53945 | 6781 | else |
a3524f1b | 6782 | dev_priv->num_pipe = 1; |
28c97730 | 6783 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6784 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6785 | |
a3524f1b | 6786 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
6787 | intel_crtc_init(dev, i); |
6788 | } | |
6789 | ||
6790 | intel_setup_outputs(dev); | |
652c393a | 6791 | |
0cdab21f | 6792 | intel_enable_clock_gating(dev); |
652c393a | 6793 | |
9cce37f4 JB |
6794 | /* Just disable it once at startup */ |
6795 | i915_disable_vga(dev); | |
6796 | ||
7648fa99 | 6797 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 6798 | ironlake_enable_drps(dev); |
7648fa99 JB |
6799 | intel_init_emon(dev); |
6800 | } | |
f97108d1 | 6801 | |
3b8d8d91 JB |
6802 | if (IS_GEN6(dev)) |
6803 | gen6_enable_rps(dev_priv); | |
6804 | ||
ac668088 | 6805 | if (IS_IRONLAKE_M(dev)) |
d5bb081b | 6806 | ironlake_enable_rc6(dev); |
d5bb081b | 6807 | |
652c393a JB |
6808 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6809 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6810 | (unsigned long)dev); | |
02e792fb DV |
6811 | |
6812 | intel_setup_overlay(dev); | |
79e53945 JB |
6813 | } |
6814 | ||
6815 | void intel_modeset_cleanup(struct drm_device *dev) | |
6816 | { | |
652c393a JB |
6817 | struct drm_i915_private *dev_priv = dev->dev_private; |
6818 | struct drm_crtc *crtc; | |
6819 | struct intel_crtc *intel_crtc; | |
6820 | ||
f87ea761 | 6821 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
6822 | mutex_lock(&dev->struct_mutex); |
6823 | ||
723bfd70 JB |
6824 | intel_unregister_dsm_handler(); |
6825 | ||
6826 | ||
652c393a JB |
6827 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6828 | /* Skip inactive CRTCs */ | |
6829 | if (!crtc->fb) | |
6830 | continue; | |
6831 | ||
6832 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6833 | intel_increase_pllclock(crtc); |
652c393a JB |
6834 | } |
6835 | ||
e70236a8 JB |
6836 | if (dev_priv->display.disable_fbc) |
6837 | dev_priv->display.disable_fbc(dev); | |
6838 | ||
f97108d1 JB |
6839 | if (IS_IRONLAKE_M(dev)) |
6840 | ironlake_disable_drps(dev); | |
3b8d8d91 JB |
6841 | if (IS_GEN6(dev)) |
6842 | gen6_disable_rps(dev); | |
f97108d1 | 6843 | |
d5bb081b JB |
6844 | if (IS_IRONLAKE_M(dev)) |
6845 | ironlake_disable_rc6(dev); | |
0cdab21f | 6846 | |
69341a5e KH |
6847 | mutex_unlock(&dev->struct_mutex); |
6848 | ||
6c0d9350 DV |
6849 | /* Disable the irq before mode object teardown, for the irq might |
6850 | * enqueue unpin/hotplug work. */ | |
6851 | drm_irq_uninstall(dev); | |
6852 | cancel_work_sync(&dev_priv->hotplug_work); | |
6853 | ||
3dec0095 DV |
6854 | /* Shut off idle work before the crtcs get freed. */ |
6855 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6856 | intel_crtc = to_intel_crtc(crtc); | |
6857 | del_timer_sync(&intel_crtc->idle_timer); | |
6858 | } | |
6859 | del_timer_sync(&dev_priv->idle_timer); | |
6860 | cancel_work_sync(&dev_priv->idle_work); | |
6861 | ||
79e53945 JB |
6862 | drm_mode_config_cleanup(dev); |
6863 | } | |
6864 | ||
f1c79df3 ZW |
6865 | /* |
6866 | * Return which encoder is currently attached for connector. | |
6867 | */ | |
df0e9248 | 6868 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6869 | { |
df0e9248 CW |
6870 | return &intel_attached_encoder(connector)->base; |
6871 | } | |
f1c79df3 | 6872 | |
df0e9248 CW |
6873 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6874 | struct intel_encoder *encoder) | |
6875 | { | |
6876 | connector->encoder = encoder; | |
6877 | drm_mode_connector_attach_encoder(&connector->base, | |
6878 | &encoder->base); | |
79e53945 | 6879 | } |
28d52043 DA |
6880 | |
6881 | /* | |
6882 | * set vga decode state - true == enable VGA decode | |
6883 | */ | |
6884 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6885 | { | |
6886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6887 | u16 gmch_ctrl; | |
6888 | ||
6889 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6890 | if (state) | |
6891 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6892 | else | |
6893 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6894 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6895 | return 0; | |
6896 | } | |
c4a1d9e4 CW |
6897 | |
6898 | #ifdef CONFIG_DEBUG_FS | |
6899 | #include <linux/seq_file.h> | |
6900 | ||
6901 | struct intel_display_error_state { | |
6902 | struct intel_cursor_error_state { | |
6903 | u32 control; | |
6904 | u32 position; | |
6905 | u32 base; | |
6906 | u32 size; | |
6907 | } cursor[2]; | |
6908 | ||
6909 | struct intel_pipe_error_state { | |
6910 | u32 conf; | |
6911 | u32 source; | |
6912 | ||
6913 | u32 htotal; | |
6914 | u32 hblank; | |
6915 | u32 hsync; | |
6916 | u32 vtotal; | |
6917 | u32 vblank; | |
6918 | u32 vsync; | |
6919 | } pipe[2]; | |
6920 | ||
6921 | struct intel_plane_error_state { | |
6922 | u32 control; | |
6923 | u32 stride; | |
6924 | u32 size; | |
6925 | u32 pos; | |
6926 | u32 addr; | |
6927 | u32 surface; | |
6928 | u32 tile_offset; | |
6929 | } plane[2]; | |
6930 | }; | |
6931 | ||
6932 | struct intel_display_error_state * | |
6933 | intel_display_capture_error_state(struct drm_device *dev) | |
6934 | { | |
6935 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6936 | struct intel_display_error_state *error; | |
6937 | int i; | |
6938 | ||
6939 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
6940 | if (error == NULL) | |
6941 | return NULL; | |
6942 | ||
6943 | for (i = 0; i < 2; i++) { | |
6944 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
6945 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
6946 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
6947 | ||
6948 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
6949 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
6950 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
6951 | error->plane[i].pos= I915_READ(DSPPOS(i)); | |
6952 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
6953 | if (INTEL_INFO(dev)->gen >= 4) { | |
6954 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
6955 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
6956 | } | |
6957 | ||
6958 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
6959 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
6960 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
6961 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
6962 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
6963 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
6964 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
6965 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
6966 | } | |
6967 | ||
6968 | return error; | |
6969 | } | |
6970 | ||
6971 | void | |
6972 | intel_display_print_error_state(struct seq_file *m, | |
6973 | struct drm_device *dev, | |
6974 | struct intel_display_error_state *error) | |
6975 | { | |
6976 | int i; | |
6977 | ||
6978 | for (i = 0; i < 2; i++) { | |
6979 | seq_printf(m, "Pipe [%d]:\n", i); | |
6980 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
6981 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
6982 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
6983 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
6984 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
6985 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
6986 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
6987 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
6988 | ||
6989 | seq_printf(m, "Plane [%d]:\n", i); | |
6990 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
6991 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
6992 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
6993 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
6994 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
6995 | if (INTEL_INFO(dev)->gen >= 4) { | |
6996 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
6997 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
6998 | } | |
6999 | ||
7000 | seq_printf(m, "Cursor [%d]:\n", i); | |
7001 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
7002 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
7003 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
7004 | } | |
7005 | } | |
7006 | #endif |