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drm/i915: Make sure all planes and connectors are added on modeset.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
cdba954e
ACO		 434static bool
435needs_modeset(struct drm_crtc_state *state)
436{
437 return state->mode_changed || state->active_changed;
438}
439
e0638cdf
PZ		 440/**
441 * Returns whether any output on the specified pipe is of the specified type
442 */
4093561b 443bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 444{
409ee761 445 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 446 struct intel_encoder *encoder;
447
409ee761 448 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 449 if (encoder->type == type)
450 return true;
451
452 return false;
453}
454
d0737e1d
ACO		 455/**
456 * Returns whether any output on the specified pipe will have the specified
457 * type after a staged modeset is complete, i.e., the same as
458 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
459 * encoder->crtc.
460 */
a93e255f
ACO		 461static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
462 int type)
d0737e1d 463{
a93e255f 464 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 465 struct drm_connector *connector;
a93e255f 466 struct drm_connector_state *connector_state;
d0737e1d 467 struct intel_encoder *encoder;
a93e255f
ACO		 468 int i, num_connectors = 0;
469
da3ced29 470 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 471 if (connector_state->crtc != crtc_state->base.crtc)
472 continue;
473
474 num_connectors++;
d0737e1d 475
a93e255f
ACO		 476 encoder = to_intel_encoder(connector_state->best_encoder);
477 if (encoder->type == type)
d0737e1d 478 return true;
a93e255f
ACO		 479 }
480
481 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 482
483 return false;
484}
485
a93e255f
ACO		 486static const intel_limit_t *
487intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 488{
a93e255f 489 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 490 const intel_limit_t *limit;
b91ad0ec 491
a93e255f 492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 493 if (intel_is_dual_link_lvds(dev)) {
1b894b59 494 if (refclk == 100000)
b91ad0ec
ZW		 495 limit = &intel_limits_ironlake_dual_lvds_100m;
496 else
497 limit = &intel_limits_ironlake_dual_lvds;
498 } else {
1b894b59 499 if (refclk == 100000)
b91ad0ec
ZW		 500 limit = &intel_limits_ironlake_single_lvds_100m;
501 else
502 limit = &intel_limits_ironlake_single_lvds;
503 }
c6bb3538 504 } else
b91ad0ec 505 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 506
507 return limit;
508}
509
a93e255f
ACO		 510static const intel_limit_t *
511intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 512{
a93e255f 513 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 514 const intel_limit_t *limit;
515
a93e255f 516 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 517 if (intel_is_dual_link_lvds(dev))
e4b36699 518 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 519 else
e4b36699 520 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
522 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 523 limit = &intel_limits_g4x_hdmi;
a93e255f 524 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 525 limit = &intel_limits_g4x_sdvo;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
a93e255f
ACO		 532static const intel_limit_t *
533intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 534{
a93e255f 535 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 536 const intel_limit_t *limit;
537
5ab7b0b7
ID		 538 if (IS_BROXTON(dev))
539 limit = &intel_limits_bxt;
540 else if (HAS_PCH_SPLIT(dev))
a93e255f 541 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 542 else if (IS_G4X(dev)) {
a93e255f 543 limit = intel_g4x_limit(crtc_state);
f2b115e6 544 } else if (IS_PINEVIEW(dev)) {
a93e255f 545 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 546 limit = &intel_limits_pineview_lvds;
2177832f 547 else
f2b115e6 548 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 549 } else if (IS_CHERRYVIEW(dev)) {
550 limit = &intel_limits_chv;
a0c4da24 551 } else if (IS_VALLEYVIEW(dev)) {
dc730512 552 limit = &intel_limits_vlv;
a6c45cf0 553 } else if (!IS_GEN2(dev)) {
a93e255f 554 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945 558 } else {
a93e255f 559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
a93e255f 561 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 562 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 563 else
564 limit = &intel_limits_i8xx_dac;
79e53945
JB		 565 }
566 return limit;
567}
568
f2b115e6
AJ		 569/* m1 is reserved as 0 in Pineview, n is a ring counter */
570static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 571{
2177832f
SL		 572 clock->m = clock->m2 + 2;
573 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 574 if (WARN_ON(clock->n == 0 || clock->p == 0))
575 return;
fb03ac01
VS		 576 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 578}
579
7429e9d4
DV		 580static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
581{
582 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
583}
584
ac58c3f0 585static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 586{
7429e9d4 587 clock->m = i9xx_dpll_compute_m(clock);
79e53945 588 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 589 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
590 return;
fb03ac01
VS		 591 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 593}
594
ef9348c8
CML		 595static void chv_clock(int refclk, intel_clock_t *clock)
596{
597 clock->m = clock->m1 * clock->m2;
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n == 0 || clock->p == 0))
600 return;
601 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
602 clock->n << 22);
603 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
604}
605
7c04d1d9 606#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 607/**
608 * Returns whether the given set of divisors are valid for a given refclk with
609 * the given connectors.
610 */
611
1b894b59
CW		 612static bool intel_PLL_is_valid(struct drm_device *dev,
613 const intel_limit_t *limit,
614 const intel_clock_t *clock)
79e53945 615{
f01b7962
VS		 616 if (clock->n < limit->n.min || limit->n.max < clock->n)
617 INTELPllInvalid("n out of range\n");
79e53945 618 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 619 INTELPllInvalid("p1 out of range\n");
79e53945 620 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 621 INTELPllInvalid("m2 out of range\n");
79e53945 622 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 623 INTELPllInvalid("m1 out of range\n");
f01b7962 624
5ab7b0b7 625 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 626 if (clock->m1 <= clock->m2)
627 INTELPllInvalid("m1 <= m2\n");
628
5ab7b0b7 629 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 630 if (clock->p < limit->p.min || limit->p.max < clock->p)
631 INTELPllInvalid("p out of range\n");
632 if (clock->m < limit->m.min || limit->m.max < clock->m)
633 INTELPllInvalid("m out of range\n");
634 }
635
79e53945 636 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 637 INTELPllInvalid("vco out of range\n");
79e53945
JB		 638 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
639 * connector, etc., rather than just a single range.
640 */
641 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 642 INTELPllInvalid("dot out of range\n");
79e53945
JB		 643
644 return true;
645}
646
d4906093 647static bool
a93e255f
ACO		 648i9xx_find_best_dpll(const intel_limit_t *limit,
649 struct intel_crtc_state *crtc_state,
cec2f356
SP		 650 int target, int refclk, intel_clock_t *match_clock,
651 intel_clock_t *best_clock)
79e53945 652{
a93e255f 653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 654 struct drm_device *dev = crtc->base.dev;
79e53945 655 intel_clock_t clock;
79e53945
JB		 656 int err = target;
657
a93e255f 658 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 659 /*
a210b028
DV		 660 * For LVDS just rely on its current settings for dual-channel.
661 * We haven't figured out how to reliably set up different
662 * single/dual channel state, if we even can.
79e53945 663 */
1974cad0 664 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 665 clock.p2 = limit->p2.p2_fast;
666 else
667 clock.p2 = limit->p2.p2_slow;
668 } else {
669 if (target < limit->p2.dot_limit)
670 clock.p2 = limit->p2.p2_slow;
671 else
672 clock.p2 = limit->p2.p2_fast;
673 }
674
0206e353 675 memset(best_clock, 0, sizeof(*best_clock));
79e53945 676
42158660
ZY		 677 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
678 clock.m1++) {
679 for (clock.m2 = limit->m2.min;
680 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 681 if (clock.m2 >= clock.m1)
42158660
ZY		 682 break;
683 for (clock.n = limit->n.min;
684 clock.n <= limit->n.max; clock.n++) {
685 for (clock.p1 = limit->p1.min;
686 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 687 int this_err;
688
ac58c3f0
DV		 689 i9xx_clock(refclk, &clock);
690 if (!intel_PLL_is_valid(dev, limit,
691 &clock))
692 continue;
693 if (match_clock &&
694 clock.p != match_clock->p)
695 continue;
696
697 this_err = abs(clock.dot - target);
698 if (this_err < err) {
699 *best_clock = clock;
700 err = this_err;
701 }
702 }
703 }
704 }
705 }
706
707 return (err != target);
708}
709
710static bool
a93e255f
ACO		 711pnv_find_best_dpll(const intel_limit_t *limit,
712 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 713 int target, int refclk, intel_clock_t *match_clock,
714 intel_clock_t *best_clock)
79e53945 715{
a93e255f 716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 717 struct drm_device *dev = crtc->base.dev;
79e53945 718 intel_clock_t clock;
79e53945
JB		 719 int err = target;
720
a93e255f 721 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 722 /*
a210b028
DV		 723 * For LVDS just rely on its current settings for dual-channel.
724 * We haven't figured out how to reliably set up different
725 * single/dual channel state, if we even can.
79e53945 726 */
1974cad0 727 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 728 clock.p2 = limit->p2.p2_fast;
729 else
730 clock.p2 = limit->p2.p2_slow;
731 } else {
732 if (target < limit->p2.dot_limit)
733 clock.p2 = limit->p2.p2_slow;
734 else
735 clock.p2 = limit->p2.p2_fast;
736 }
737
0206e353 738 memset(best_clock, 0, sizeof(*best_clock));
79e53945 739
42158660
ZY		 740 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
741 clock.m1++) {
742 for (clock.m2 = limit->m2.min;
743 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 744 for (clock.n = limit->n.min;
745 clock.n <= limit->n.max; clock.n++) {
746 for (clock.p1 = limit->p1.min;
747 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 748 int this_err;
749
ac58c3f0 750 pineview_clock(refclk, &clock);
1b894b59
CW		 751 if (!intel_PLL_is_valid(dev, limit,
752 &clock))
79e53945 753 continue;
cec2f356
SP		 754 if (match_clock &&
755 clock.p != match_clock->p)
756 continue;
79e53945
JB		 757
758 this_err = abs(clock.dot - target);
759 if (this_err < err) {
760 *best_clock = clock;
761 err = this_err;
762 }
763 }
764 }
765 }
766 }
767
768 return (err != target);
769}
770
d4906093 771static bool
a93e255f
ACO		 772g4x_find_best_dpll(const intel_limit_t *limit,
773 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 774 int target, int refclk, intel_clock_t *match_clock,
775 intel_clock_t *best_clock)
d4906093 776{
a93e255f 777 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 778 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 779 intel_clock_t clock;
780 int max_n;
781 bool found;
6ba770dc
AJ		 782 /* approximately equals target * 0.00585 */
783 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 784 found = false;
785
a93e255f 786 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 787 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 788 clock.p2 = limit->p2.p2_fast;
789 else
790 clock.p2 = limit->p2.p2_slow;
791 } else {
792 if (target < limit->p2.dot_limit)
793 clock.p2 = limit->p2.p2_slow;
794 else
795 clock.p2 = limit->p2.p2_fast;
796 }
797
798 memset(best_clock, 0, sizeof(*best_clock));
799 max_n = limit->n.max;
f77f13e2 800 /* based on hardware requirement, prefer smaller n to precision */
d4906093 801 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 802 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 803 for (clock.m1 = limit->m1.max;
804 clock.m1 >= limit->m1.min; clock.m1--) {
805 for (clock.m2 = limit->m2.max;
806 clock.m2 >= limit->m2.min; clock.m2--) {
807 for (clock.p1 = limit->p1.max;
808 clock.p1 >= limit->p1.min; clock.p1--) {
809 int this_err;
810
ac58c3f0 811 i9xx_clock(refclk, &clock);
1b894b59
CW		 812 if (!intel_PLL_is_valid(dev, limit,
813 &clock))
d4906093 814 continue;
1b894b59
CW		 815
816 this_err = abs(clock.dot - target);
d4906093
ML		 817 if (this_err < err_most) {
818 *best_clock = clock;
819 err_most = this_err;
820 max_n = clock.n;
821 found = true;
822 }
823 }
824 }
825 }
826 }
2c07245f
ZW		 827 return found;
828}
829
d5dd62bd
ID		 830/*
831 * Check if the calculated PLL configuration is more optimal compared to the
832 * best configuration and error found so far. Return the calculated error.
833 */
834static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
835 const intel_clock_t *calculated_clock,
836 const intel_clock_t *best_clock,
837 unsigned int best_error_ppm,
838 unsigned int *error_ppm)
839{
9ca3ba01
ID		 840 /*
841 * For CHV ignore the error and consider only the P value.
842 * Prefer a bigger P value based on HW requirements.
843 */
844 if (IS_CHERRYVIEW(dev)) {
845 *error_ppm = 0;
846
847 return calculated_clock->p > best_clock->p;
848 }
849
24be4e46
ID		 850 if (WARN_ON_ONCE(!target_freq))
851 return false;
852
d5dd62bd
ID		 853 *error_ppm = div_u64(1000000ULL *
854 abs(target_freq - calculated_clock->dot),
855 target_freq);
856 /*
857 * Prefer a better P value over a better (smaller) error if the error
858 * is small. Ensure this preference for future configurations too by
859 * setting the error to 0.
860 */
861 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
862 *error_ppm = 0;
863
864 return true;
865 }
866
867 return *error_ppm + 10 < best_error_ppm;
868}
869
a0c4da24 870static bool
a93e255f
ACO		 871vlv_find_best_dpll(const intel_limit_t *limit,
872 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
a0c4da24 875{
a93e255f 876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 877 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 878 intel_clock_t clock;
69e4f900 879 unsigned int bestppm = 1000000;
27e639bf
VS		 880 /* min update 19.2 MHz */
881 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 882 bool found = false;
a0c4da24 883
6b4bf1c4
VS		 884 target *= 5; /* fast clock */
885
886 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 887
888 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 889 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 890 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 891 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 892 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 893 clock.p = clock.p1 * clock.p2;
a0c4da24 894 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 895 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 896 unsigned int ppm;
69e4f900 897
6b4bf1c4
VS		 898 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
899 refclk * clock.m1);
900
901 vlv_clock(refclk, &clock);
43b0ac53 902
f01b7962
VS		 903 if (!intel_PLL_is_valid(dev, limit,
904 &clock))
43b0ac53
VS		 905 continue;
906
d5dd62bd
ID		 907 if (!vlv_PLL_is_optimal(dev, target,
908 &clock,
909 best_clock,
910 bestppm, &ppm))
911 continue;
6b4bf1c4 912
d5dd62bd
ID		 913 *best_clock = clock;
914 bestppm = ppm;
915 found = true;
a0c4da24
JB		 916 }
917 }
918 }
919 }
a0c4da24 920
49e497ef 921 return found;
a0c4da24 922}
a4fc5ed6 923
ef9348c8 924static bool
a93e255f
ACO		 925chv_find_best_dpll(const intel_limit_t *limit,
926 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 927 int target, int refclk, intel_clock_t *match_clock,
928 intel_clock_t *best_clock)
929{
a93e255f 930 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 931 struct drm_device *dev = crtc->base.dev;
9ca3ba01 932 unsigned int best_error_ppm;
ef9348c8
CML		 933 intel_clock_t clock;
934 uint64_t m2;
935 int found = false;
936
937 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 938 best_error_ppm = 1000000;
ef9348c8
CML		 939
940 /*
941 * Based on hardware doc, the n always set to 1, and m1 always
942 * set to 2. If requires to support 200Mhz refclk, we need to
943 * revisit this because n may not 1 anymore.
944 */
945 clock.n = 1, clock.m1 = 2;
946 target *= 5; /* fast clock */
947
948 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
949 for (clock.p2 = limit->p2.p2_fast;
950 clock.p2 >= limit->p2.p2_slow;
951 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 952 unsigned int error_ppm;
ef9348c8
CML		 953
954 clock.p = clock.p1 * clock.p2;
955
956 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
957 clock.n) << 22, refclk * clock.m1);
958
959 if (m2 > INT_MAX/clock.m1)
960 continue;
961
962 clock.m2 = m2;
963
964 chv_clock(refclk, &clock);
965
966 if (!intel_PLL_is_valid(dev, limit, &clock))
967 continue;
968
9ca3ba01
ID		 969 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
970 best_error_ppm, &error_ppm))
971 continue;
972
973 *best_clock = clock;
974 best_error_ppm = error_ppm;
975 found = true;
ef9348c8
CML		 976 }
977 }
978
979 return found;
980}
981
5ab7b0b7
ID		 982bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
983 intel_clock_t *best_clock)
984{
985 int refclk = i9xx_get_refclk(crtc_state, 0);
986
987 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
988 target_clock, refclk, NULL, best_clock);
989}
990
20ddf665
VS		 991bool intel_crtc_active(struct drm_crtc *crtc)
992{
993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
994
995 /* Be paranoid as we can arrive here with only partial
996 * state retrieved from the hardware during setup.
997 *
241bfc38 998 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 999 * as Haswell has gained clock readout/fastboot support.
1000 *
66e514c1 1001 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1002 * properly reconstruct framebuffers.
c3d1f436
MR		 1003 *
1004 * FIXME: The intel_crtc->active here should be switched to
1005 * crtc->state->active once we have proper CRTC states wired up
1006 * for atomic.
20ddf665 1007 */
c3d1f436 1008 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1009 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1010}
1011
a5c961d1
PZ		 1012enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1013 enum pipe pipe)
1014{
1015 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1017
6e3c9717 1018 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1019}
1020
fbf49ea2
VS		 1021static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1022{
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 u32 reg = PIPEDSL(pipe);
1025 u32 line1, line2;
1026 u32 line_mask;
1027
1028 if (IS_GEN2(dev))
1029 line_mask = DSL_LINEMASK_GEN2;
1030 else
1031 line_mask = DSL_LINEMASK_GEN3;
1032
1033 line1 = I915_READ(reg) & line_mask;
1034 mdelay(5);
1035 line2 = I915_READ(reg) & line_mask;
1036
1037 return line1 == line2;
1038}
1039
ab7ad7f6
KP		 1040/*
1041 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1042 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1043 *
1044 * After disabling a pipe, we can't wait for vblank in the usual way,
1045 * spinning on the vblank interrupt status bit, since we won't actually
1046 * see an interrupt when the pipe is disabled.
1047 *
ab7ad7f6
KP		 1048 * On Gen4 and above:
1049 * wait for the pipe register state bit to turn off
1050 *
1051 * Otherwise:
1052 * wait for the display line value to settle (it usually
1053 * ends up stopping at the start of the next frame).
58e10eb9 1054 *
9d0498a2 1055 */
575f7ab7 1056static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1057{
575f7ab7 1058 struct drm_device *dev = crtc->base.dev;
9d0498a2 1059 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1060 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1061 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1062
1063 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1064 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1065
1066 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1067 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1068 100))
284637d9 1069 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1070 } else {
ab7ad7f6 1071 /* Wait for the display line to settle */
fbf49ea2 1072 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1073 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1074 }
79e53945
JB		 1075}
1076
b0ea7d37
DL		 1077/*
1078 * ibx_digital_port_connected - is the specified port connected?
1079 * @dev_priv: i915 private structure
1080 * @port: the port to test
1081 *
1082 * Returns true if @port is connected, false otherwise.
1083 */
1084bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1085 struct intel_digital_port *port)
1086{
1087 u32 bit;
1088
c36346e3 1089 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1090 switch (port->port) {
c36346e3
DL		 1091 case PORT_B:
1092 bit = SDE_PORTB_HOTPLUG;
1093 break;
1094 case PORT_C:
1095 bit = SDE_PORTC_HOTPLUG;
1096 break;
1097 case PORT_D:
1098 bit = SDE_PORTD_HOTPLUG;
1099 break;
1100 default:
1101 return true;
1102 }
1103 } else {
eba905b2 1104 switch (port->port) {
c36346e3
DL		 1105 case PORT_B:
1106 bit = SDE_PORTB_HOTPLUG_CPT;
1107 break;
1108 case PORT_C:
1109 bit = SDE_PORTC_HOTPLUG_CPT;
1110 break;
1111 case PORT_D:
1112 bit = SDE_PORTD_HOTPLUG_CPT;
1113 break;
1114 default:
1115 return true;
1116 }
b0ea7d37
DL		 1117 }
1118
1119 return I915_READ(SDEISR) & bit;
1120}
1121
b24e7179
JB		 1122static const char *state_string(bool enabled)
1123{
1124 return enabled ? "on" : "off";
1125}
1126
1127/* Only for pre-ILK configs */
55607e8a
DV		 1128void assert_pll(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
b24e7179
JB		 1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
1135 reg = DPLL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1138 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1139 "PLL state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
b24e7179 1142
23538ef1
JN		 1143/* XXX: the dsi pll is shared between MIPI DSI ports */
1144static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1145{
1146 u32 val;
1147 bool cur_state;
1148
a580516d 1149 mutex_lock(&dev_priv->sb_lock);
23538ef1 1150 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1151 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1152
1153 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1154 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1155 "DSI PLL state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157}
1158#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1159#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1160
55607e8a 1161struct intel_shared_dpll *
e2b78267
DV		 1162intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1163{
1164 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1165
6e3c9717 1166 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1167 return NULL;
1168
6e3c9717 1169 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1170}
1171
040484af 1172/* For ILK+ */
55607e8a
DV		 1173void assert_shared_dpll(struct drm_i915_private *dev_priv,
1174 struct intel_shared_dpll *pll,
1175 bool state)
040484af 1176{
040484af 1177 bool cur_state;
5358901f 1178 struct intel_dpll_hw_state hw_state;
040484af 1179
92b27b08 1180 if (WARN (!pll,
46edb027 1181 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1182 return;
ee7b9f93 1183
5358901f 1184 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1185 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1186 "%s assertion failure (expected %s, current %s)\n",
1187 pll->name, state_string(state), state_string(cur_state));
040484af 1188}
040484af
JB		 1189
1190static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1191 enum pipe pipe, bool state)
1192{
1193 int reg;
1194 u32 val;
1195 bool cur_state;
ad80a810
PZ		 1196 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1197 pipe);
040484af 1198
affa9354
PZ		 1199 if (HAS_DDI(dev_priv->dev)) {
1200 /* DDI does not have a specific FDI_TX register */
ad80a810 1201 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1202 val = I915_READ(reg);
ad80a810 1203 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1204 } else {
1205 reg = FDI_TX_CTL(pipe);
1206 val = I915_READ(reg);
1207 cur_state = !!(val & FDI_TX_ENABLE);
1208 }
e2c719b7 1209 I915_STATE_WARN(cur_state != state,
040484af
JB		 1210 "FDI TX state assertion failure (expected %s, current %s)\n",
1211 state_string(state), state_string(cur_state));
1212}
1213#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1214#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1215
1216static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218{
1219 int reg;
1220 u32 val;
1221 bool cur_state;
1222
d63fa0dc
PZ		 1223 reg = FDI_RX_CTL(pipe);
1224 val = I915_READ(reg);
1225 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1226 I915_STATE_WARN(cur_state != state,
040484af
JB		 1227 "FDI RX state assertion failure (expected %s, current %s)\n",
1228 state_string(state), state_string(cur_state));
1229}
1230#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1231#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1232
1233static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1234 enum pipe pipe)
1235{
1236 int reg;
1237 u32 val;
1238
1239 /* ILK FDI PLL is always enabled */
3d13ef2e 1240 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1241 return;
1242
bf507ef7 1243 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1244 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1245 return;
1246
040484af
JB		 1247 reg = FDI_TX_CTL(pipe);
1248 val = I915_READ(reg);
e2c719b7 1249 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1250}
1251
55607e8a
DV		 1252void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, bool state)
040484af
JB		 1254{
1255 int reg;
1256 u32 val;
55607e8a 1257 bool cur_state;
040484af
JB		 1258
1259 reg = FDI_RX_CTL(pipe);
1260 val = I915_READ(reg);
55607e8a 1261 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1262 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1263 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1264 state_string(state), state_string(cur_state));
040484af
JB		 1265}
1266
b680c37a
DV		 1267void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1268 enum pipe pipe)
ea0760cf 1269{
bedd4dba
JN		 1270 struct drm_device *dev = dev_priv->dev;
1271 int pp_reg;
ea0760cf
JB		 1272 u32 val;
1273 enum pipe panel_pipe = PIPE_A;
0de3b485 1274 bool locked = true;
ea0760cf 1275
bedd4dba
JN		 1276 if (WARN_ON(HAS_DDI(dev)))
1277 return;
1278
1279 if (HAS_PCH_SPLIT(dev)) {
1280 u32 port_sel;
1281
ea0760cf 1282 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1283 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284
1285 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1286 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1287 panel_pipe = PIPE_B;
1288 /* XXX: else fix for eDP */
1289 } else if (IS_VALLEYVIEW(dev)) {
1290 /* presumably write lock depends on pipe, not port select */
1291 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1292 panel_pipe = pipe;
ea0760cf
JB		 1293 } else {
1294 pp_reg = PP_CONTROL;
bedd4dba
JN		 1295 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1296 panel_pipe = PIPE_B;
ea0760cf
JB		 1297 }
1298
1299 val = I915_READ(pp_reg);
1300 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1301 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1302 locked = false;
1303
e2c719b7 1304 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1305 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1306 pipe_name(pipe));
ea0760cf
JB		 1307}
1308
93ce0ba6
JN		 1309static void assert_cursor(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, bool state)
1311{
1312 struct drm_device *dev = dev_priv->dev;
1313 bool cur_state;
1314
d9d82081 1315 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1316 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1317 else
5efb3e28 1318 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1319
e2c719b7 1320 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1321 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1322 pipe_name(pipe), state_string(state), state_string(cur_state));
1323}
1324#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1325#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326
b840d907
JB		 1327void assert_pipe(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, bool state)
b24e7179
JB		 1329{
1330 int reg;
1331 u32 val;
63d7bbe9 1332 bool cur_state;
702e7a56
PZ		 1333 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1334 pipe);
b24e7179 1335
b6b5d049
VS		 1336 /* if we need the pipe quirk it must be always on */
1337 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1338 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1339 state = true;
1340
f458ebbc 1341 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1342 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1343 cur_state = false;
1344 } else {
1345 reg = PIPECONF(cpu_transcoder);
1346 val = I915_READ(reg);
1347 cur_state = !!(val & PIPECONF_ENABLE);
1348 }
1349
e2c719b7 1350 I915_STATE_WARN(cur_state != state,
63d7bbe9 1351 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1352 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1353}
1354
931872fc
CW		 1355static void assert_plane(struct drm_i915_private *dev_priv,
1356 enum plane plane, bool state)
b24e7179
JB		 1357{
1358 int reg;
1359 u32 val;
931872fc 1360 bool cur_state;
b24e7179
JB		 1361
1362 reg = DSPCNTR(plane);
1363 val = I915_READ(reg);
931872fc 1364 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1365 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1366 "plane %c assertion failure (expected %s, current %s)\n",
1367 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1368}
1369
931872fc
CW		 1370#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1371#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1372
b24e7179
JB		 1373static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe)
1375{
653e1026 1376 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1377 int reg, i;
1378 u32 val;
1379 int cur_pipe;
1380
653e1026
VS		 1381 /* Primary planes are fixed to pipes on gen4+ */
1382 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1383 reg = DSPCNTR(pipe);
1384 val = I915_READ(reg);
e2c719b7 1385 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1386 "plane %c assertion failure, should be disabled but not\n",
1387 plane_name(pipe));
19ec1358 1388 return;
28c05794 1389 }
19ec1358 1390
b24e7179 1391 /* Need to check both planes against the pipe */
055e393f 1392 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1393 reg = DSPCNTR(i);
1394 val = I915_READ(reg);
1395 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1396 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1397 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1398 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1399 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1400 }
1401}
1402
19332d7a
JB		 1403static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405{
20674eef 1406 struct drm_device *dev = dev_priv->dev;
1fe47785 1407 int reg, sprite;
19332d7a
JB		 1408 u32 val;
1409
7feb8b88 1410 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1411 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1412 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1413 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1414 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1415 sprite, pipe_name(pipe));
1416 }
1417 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1419 reg = SPCNTR(pipe, sprite);
20674eef 1420 val = I915_READ(reg);
e2c719b7 1421 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1423 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1424 }
1425 } else if (INTEL_INFO(dev)->gen >= 7) {
1426 reg = SPRCTL(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1430 plane_name(pipe), pipe_name(pipe));
1431 } else if (INTEL_INFO(dev)->gen >= 5) {
1432 reg = DVSCNTR(pipe);
19332d7a 1433 val = I915_READ(reg);
e2c719b7 1434 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1435 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1436 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1437 }
1438}
1439
08c71e5e
VS		 1440static void assert_vblank_disabled(struct drm_crtc *crtc)
1441{
e2c719b7 1442 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1443 drm_crtc_vblank_put(crtc);
1444}
1445
89eff4be 1446static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1447{
1448 u32 val;
1449 bool enabled;
1450
e2c719b7 1451 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1452
92f2584a
JB		 1453 val = I915_READ(PCH_DREF_CONTROL);
1454 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1455 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1456 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1457}
1458
ab9412ba
DV		 1459static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
92f2584a
JB		 1461{
1462 int reg;
1463 u32 val;
1464 bool enabled;
1465
ab9412ba 1466 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1467 val = I915_READ(reg);
1468 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1469 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1470 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1471 pipe_name(pipe));
92f2584a
JB		 1472}
1473
4e634389
KP		 1474static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1476{
1477 if ((val & DP_PORT_EN) == 0)
1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
1481 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1482 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1483 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1484 return false;
44f37d1f
CML		 1485 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1486 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1487 return false;
f0575e92
KP		 1488 } else {
1489 if ((val & DP_PIPE_MASK) != (pipe << 30))
1490 return false;
1491 }
1492 return true;
1493}
1494
1519b995
KP		 1495static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497{
dc0fa718 1498 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1499 return false;
1500
1501 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1503 return false;
44f37d1f
CML		 1504 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1505 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1506 return false;
1519b995 1507 } else {
dc0fa718 1508 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1509 return false;
1510 }
1511 return true;
1512}
1513
1514static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1515 enum pipe pipe, u32 val)
1516{
1517 if ((val & LVDS_PORT_EN) == 0)
1518 return false;
1519
1520 if (HAS_PCH_CPT(dev_priv->dev)) {
1521 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1522 return false;
1523 } else {
1524 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1525 return false;
1526 }
1527 return true;
1528}
1529
1530static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1531 enum pipe pipe, u32 val)
1532{
1533 if ((val & ADPA_DAC_ENABLE) == 0)
1534 return false;
1535 if (HAS_PCH_CPT(dev_priv->dev)) {
1536 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1537 return false;
1538 } else {
1539 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1540 return false;
1541 }
1542 return true;
1543}
1544
291906f1 1545static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1546 enum pipe pipe, int reg, u32 port_sel)
291906f1 1547{
47a05eca 1548 u32 val = I915_READ(reg);
e2c719b7 1549 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1550 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1551 reg, pipe_name(pipe));
de9a35ab 1552
e2c719b7 1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1554 && (val & DP_PIPEB_SELECT),
de9a35ab 1555 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1556}
1557
1558static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe, int reg)
1560{
47a05eca 1561 u32 val = I915_READ(reg);
e2c719b7 1562 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1563 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1564 reg, pipe_name(pipe));
de9a35ab 1565
e2c719b7 1566 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1567 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1568 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1569}
1570
1571static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1572 enum pipe pipe)
1573{
1574 int reg;
1575 u32 val;
291906f1 1576
f0575e92
KP		 1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1580
1581 reg = PCH_ADPA;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1
JB		 1586
1587 reg = PCH_LVDS;
1588 val = I915_READ(reg);
e2c719b7 1589 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1590 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1591 pipe_name(pipe));
291906f1 1592
e2debe91
PZ		 1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1595 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1596}
1597
40e9cf64
JB		 1598static void intel_init_dpio(struct drm_device *dev)
1599{
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601
1602 if (!IS_VALLEYVIEW(dev))
1603 return;
1604
a09caddd
CML		 1605 /*
1606 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1607 * CHV x1 PHY (DP/HDMI D)
1608 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1609 */
1610 if (IS_CHERRYVIEW(dev)) {
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1612 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1613 } else {
1614 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1615 }
5382f5f3
JB		 1616}
1617
d288f65f 1618static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1619 const struct intel_crtc_state *pipe_config)
87442f73 1620{
426115cf
DV		 1621 struct drm_device *dev = crtc->base.dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623 int reg = DPLL(crtc->pipe);
d288f65f 1624 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1625
426115cf 1626 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1627
1628 /* No really, not for ILK+ */
1629 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1630
1631 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1632 if (IS_MOBILE(dev_priv->dev))
426115cf 1633 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1634
426115cf
DV		 1635 I915_WRITE(reg, dpll);
1636 POSTING_READ(reg);
1637 udelay(150);
1638
1639 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1640 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1641
d288f65f 1642 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1643 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1644
1645 /* We do this three times for luck */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
426115cf 1649 I915_WRITE(reg, dpll);
87442f73
DV		 1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
426115cf 1652 I915_WRITE(reg, dpll);
87442f73
DV		 1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655}
1656
d288f65f 1657static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1658 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1659{
1660 struct drm_device *dev = crtc->base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 int pipe = crtc->pipe;
1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1664 u32 tmp;
1665
1666 assert_pipe_disabled(dev_priv, crtc->pipe);
1667
1668 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1669
a580516d 1670 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1671
1672 /* Enable back the 10bit clock to display controller */
1673 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1674 tmp |= DPIO_DCLKP_EN;
1675 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1676
54433e91
VS		 1677 mutex_unlock(&dev_priv->sb_lock);
1678
9d556c99
CML		 1679 /*
1680 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1681 */
1682 udelay(1);
1683
1684 /* Enable PLL */
d288f65f 1685 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1686
1687 /* Check PLL is locked */
a11b0703 1688 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1689 DRM_ERROR("PLL %d failed to lock\n", pipe);
1690
a11b0703 1691 /* not sure when this should be written */
d288f65f 1692 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1693 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1694}
1695
1c4e0274
VS		 1696static int intel_num_dvo_pipes(struct drm_device *dev)
1697{
1698 struct intel_crtc *crtc;
1699 int count = 0;
1700
1701 for_each_intel_crtc(dev, crtc)
1702 count += crtc->active &&
409ee761 1703 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1704
1705 return count;
1706}
1707
66e3d5c0 1708static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1709{
66e3d5c0
DV		 1710 struct drm_device *dev = crtc->base.dev;
1711 struct drm_i915_private *dev_priv = dev->dev_private;
1712 int reg = DPLL(crtc->pipe);
6e3c9717 1713 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1714
66e3d5c0 1715 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1716
63d7bbe9 1717 /* No really, not for ILK+ */
3d13ef2e 1718 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1719
1720 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1721 if (IS_MOBILE(dev) && !IS_I830(dev))
1722 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1723
1c4e0274
VS		 1724 /* Enable DVO 2x clock on both PLLs if necessary */
1725 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1726 /*
1727 * It appears to be important that we don't enable this
1728 * for the current pipe before otherwise configuring the
1729 * PLL. No idea how this should be handled if multiple
1730 * DVO outputs are enabled simultaneosly.
1731 */
1732 dpll |= DPLL_DVO_2X_MODE;
1733 I915_WRITE(DPLL(!crtc->pipe),
1734 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1735 }
66e3d5c0
DV		 1736
1737 /* Wait for the clocks to stabilize. */
1738 POSTING_READ(reg);
1739 udelay(150);
1740
1741 if (INTEL_INFO(dev)->gen >= 4) {
1742 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1743 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1744 } else {
1745 /* The pixel multiplier can only be updated once the
1746 * DPLL is enabled and the clocks are stable.
1747 *
1748 * So write it again.
1749 */
1750 I915_WRITE(reg, dpll);
1751 }
63d7bbe9
JB		 1752
1753 /* We do this three times for luck */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
66e3d5c0 1757 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1758 POSTING_READ(reg);
1759 udelay(150); /* wait for warmup */
66e3d5c0 1760 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1761 POSTING_READ(reg);
1762 udelay(150); /* wait for warmup */
1763}
1764
1765/**
50b44a44 1766 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe PLL to disable
1769 *
1770 * Disable the PLL for @pipe, making sure the pipe is off first.
1771 *
1772 * Note! This is for pre-ILK only.
1773 */
1c4e0274 1774static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1775{
1c4e0274
VS		 1776 struct drm_device *dev = crtc->base.dev;
1777 struct drm_i915_private *dev_priv = dev->dev_private;
1778 enum pipe pipe = crtc->pipe;
1779
1780 /* Disable DVO 2x clock on both PLLs if necessary */
1781 if (IS_I830(dev) &&
409ee761 1782 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1783 intel_num_dvo_pipes(dev) == 1) {
1784 I915_WRITE(DPLL(PIPE_B),
1785 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1786 I915_WRITE(DPLL(PIPE_A),
1787 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1788 }
1789
b6b5d049
VS		 1790 /* Don't disable pipe or pipe PLLs if needed */
1791 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1792 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1793 return;
1794
1795 /* Make sure the pipe isn't still relying on us */
1796 assert_pipe_disabled(dev_priv, pipe);
1797
50b44a44
DV		 1798 I915_WRITE(DPLL(pipe), 0);
1799 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1800}
1801
f6071166
JB		 1802static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1803{
1804 u32 val = 0;
1805
1806 /* Make sure the pipe isn't still relying on us */
1807 assert_pipe_disabled(dev_priv, pipe);
1808
e5cbfbfb
ID		 1809 /*
1810 * Leave integrated clock source and reference clock enabled for pipe B.
1811 * The latter is needed for VGA hotplug / manual detection.
1812 */
f6071166 1813 if (pipe == PIPE_B)
e5cbfbfb 1814 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1815 I915_WRITE(DPLL(pipe), val);
1816 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1817
1818}
1819
1820static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1821{
d752048d 1822 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1823 u32 val;
1824
a11b0703
VS		 1825 /* Make sure the pipe isn't still relying on us */
1826 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1827
a11b0703 1828 /* Set PLL en = 0 */
d17ec4ce 1829 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1830 if (pipe != PIPE_A)
1831 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1832 I915_WRITE(DPLL(pipe), val);
1833 POSTING_READ(DPLL(pipe));
d752048d 1834
a580516d 1835 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1836
1837 /* Disable 10bit clock to display controller */
1838 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1839 val &= ~DPIO_DCLKP_EN;
1840 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1841
61407f6d
VS		 1842 /* disable left/right clock distribution */
1843 if (pipe != PIPE_B) {
1844 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1845 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1846 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1847 } else {
1848 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1849 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1850 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1851 }
1852
a580516d 1853 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1854}
1855
e4607fcf 1856void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1857 struct intel_digital_port *dport,
1858 unsigned int expected_mask)
89b667f8
JB		 1859{
1860 u32 port_mask;
00fc31b7 1861 int dpll_reg;
89b667f8 1862
e4607fcf
CML		 1863 switch (dport->port) {
1864 case PORT_B:
89b667f8 1865 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1866 dpll_reg = DPLL(0);
e4607fcf
CML		 1867 break;
1868 case PORT_C:
89b667f8 1869 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1870 dpll_reg = DPLL(0);
9b6de0a1 1871 expected_mask <<= 4;
00fc31b7
CML		 1872 break;
1873 case PORT_D:
1874 port_mask = DPLL_PORTD_READY_MASK;
1875 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1876 break;
1877 default:
1878 BUG();
1879 }
89b667f8 1880
9b6de0a1
VS		 1881 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1884}
1885
b14b1055
DV		 1886static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887{
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
be19f0ff
CW		 1892 if (WARN_ON(pll == NULL))
1893 return;
1894
3e369b76 1895 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1896 if (pll->active == 0) {
1897 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898 WARN_ON(pll->on);
1899 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901 pll->mode_set(dev_priv, pll);
1902 }
1903}
1904
92f2584a 1905/**
85b3894f 1906 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1907 * @dev_priv: i915 private structure
1908 * @pipe: pipe PLL to enable
1909 *
1910 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911 * drives the transcoder clock.
1912 */
85b3894f 1913static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1918
87a875bb 1919 if (WARN_ON(pll == NULL))
48da64a8
CW		 1920 return;
1921
3e369b76 1922 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1923 return;
ee7b9f93 1924
74dd6928 1925 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1926 pll->name, pll->active, pll->on,
e2b78267 1927 crtc->base.base.id);
92f2584a 1928
cdbd2316
DV		 1929 if (pll->active++) {
1930 WARN_ON(!pll->on);
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1932 return;
1933 }
f4a091c7 1934 WARN_ON(pll->on);
ee7b9f93 1935
bd2bb1b9
PZ		 1936 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
46edb027 1938 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1939 pll->enable(dev_priv, pll);
ee7b9f93 1940 pll->on = true;
92f2584a
JB		 1941}
1942
f6daaec2 1943static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1944{
3d13ef2e
DL		 1945 struct drm_device *dev = crtc->base.dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1947 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1948
92f2584a 1949 /* PCH only available on ILK+ */
3d13ef2e 1950 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1951 if (WARN_ON(pll == NULL))
ee7b9f93 1952 return;
92f2584a 1953
3e369b76 1954 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1955 return;
7a419866 1956
46edb027
DV		 1957 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1958 pll->name, pll->active, pll->on,
e2b78267 1959 crtc->base.base.id);
7a419866 1960
48da64a8 1961 if (WARN_ON(pll->active == 0)) {
e9d6944e 1962 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1963 return;
1964 }
1965
e9d6944e 1966 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1967 WARN_ON(!pll->on);
cdbd2316 1968 if (--pll->active)
7a419866 1969 return;
ee7b9f93 1970
46edb027 1971 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1972 pll->disable(dev_priv, pll);
ee7b9f93 1973 pll->on = false;
bd2bb1b9
PZ		 1974
1975 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1976}
1977
b8a4f404
PZ		 1978static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1979 enum pipe pipe)
040484af 1980{
23670b32 1981 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1982 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1984 uint32_t reg, val, pipeconf_val;
040484af
JB		 1985
1986 /* PCH only available on ILK+ */
55522f37 1987 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1988
1989 /* Make sure PCH DPLL is enabled */
e72f9fbf 1990 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1991 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1992
1993 /* FDI must be feeding us bits for PCH ports */
1994 assert_fdi_tx_enabled(dev_priv, pipe);
1995 assert_fdi_rx_enabled(dev_priv, pipe);
1996
23670b32
DV		 1997 if (HAS_PCH_CPT(dev)) {
1998 /* Workaround: Set the timing override bit before enabling the
1999 * pch transcoder. */
2000 reg = TRANS_CHICKEN2(pipe);
2001 val = I915_READ(reg);
2002 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2003 I915_WRITE(reg, val);
59c859d6 2004 }
23670b32 2005
ab9412ba 2006 reg = PCH_TRANSCONF(pipe);
040484af 2007 val = I915_READ(reg);
5f7f726d 2008 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2009
2010 if (HAS_PCH_IBX(dev_priv->dev)) {
2011 /*
2012 * make the BPC in transcoder be consistent with
2013 * that in pipeconf reg.
2014 */
dfd07d72
DV		 2015 val &= ~PIPECONF_BPC_MASK;
2016 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2017 }
5f7f726d
PZ		 2018
2019 val &= ~TRANS_INTERLACE_MASK;
2020 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2021 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2022 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2023 val |= TRANS_LEGACY_INTERLACED_ILK;
2024 else
2025 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2026 else
2027 val |= TRANS_PROGRESSIVE;
2028
040484af
JB		 2029 I915_WRITE(reg, val | TRANS_ENABLE);
2030 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2031 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2032}
2033
8fb033d7 2034static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2035 enum transcoder cpu_transcoder)
040484af 2036{
8fb033d7 2037 u32 val, pipeconf_val;
8fb033d7
PZ		 2038
2039 /* PCH only available on ILK+ */
55522f37 2040 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2041
8fb033d7 2042 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2043 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2044 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2045
223a6fdf
PZ		 2046 /* Workaround: set timing override bit. */
2047 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2048 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2049 I915_WRITE(_TRANSA_CHICKEN2, val);
2050
25f3ef11 2051 val = TRANS_ENABLE;
937bb610 2052 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2053
9a76b1c6
PZ		 2054 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2055 PIPECONF_INTERLACED_ILK)
a35f2679 2056 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2057 else
2058 val |= TRANS_PROGRESSIVE;
2059
ab9412ba
DV		 2060 I915_WRITE(LPT_TRANSCONF, val);
2061 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2062 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2063}
2064
b8a4f404
PZ		 2065static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2066 enum pipe pipe)
040484af 2067{
23670b32
DV		 2068 struct drm_device *dev = dev_priv->dev;
2069 uint32_t reg, val;
040484af
JB		 2070
2071 /* FDI relies on the transcoder */
2072 assert_fdi_tx_disabled(dev_priv, pipe);
2073 assert_fdi_rx_disabled(dev_priv, pipe);
2074
291906f1
JB		 2075 /* Ports must be off as well */
2076 assert_pch_ports_disabled(dev_priv, pipe);
2077
ab9412ba 2078 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2079 val = I915_READ(reg);
2080 val &= ~TRANS_ENABLE;
2081 I915_WRITE(reg, val);
2082 /* wait for PCH transcoder off, transcoder state */
2083 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2084 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2085
2086 if (!HAS_PCH_IBX(dev)) {
2087 /* Workaround: Clear the timing override chicken bit again. */
2088 reg = TRANS_CHICKEN2(pipe);
2089 val = I915_READ(reg);
2090 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2091 I915_WRITE(reg, val);
2092 }
040484af
JB		 2093}
2094
ab4d966c 2095static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2096{
8fb033d7
PZ		 2097 u32 val;
2098
ab9412ba 2099 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2100 val &= ~TRANS_ENABLE;
ab9412ba 2101 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2102 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2103 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2104 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2105
2106 /* Workaround: clear timing override bit. */
2107 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2108 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2109 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2110}
2111
b24e7179 2112/**
309cfea8 2113 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2114 * @crtc: crtc responsible for the pipe
b24e7179 2115 *
0372264a 2116 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2117 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2118 */
e1fdc473 2119static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2120{
0372264a
PZ		 2121 struct drm_device *dev = crtc->base.dev;
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2125 pipe);
1a240d4d 2126 enum pipe pch_transcoder;
b24e7179
JB		 2127 int reg;
2128 u32 val;
2129
58c6eaa2 2130 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2131 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2132 assert_sprites_disabled(dev_priv, pipe);
2133
681e5811 2134 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2135 pch_transcoder = TRANSCODER_A;
2136 else
2137 pch_transcoder = pipe;
2138
b24e7179
JB		 2139 /*
2140 * A pipe without a PLL won't actually be able to drive bits from
2141 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2142 * need the check.
2143 */
50360403 2144 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2145 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2146 assert_dsi_pll_enabled(dev_priv);
2147 else
2148 assert_pll_enabled(dev_priv, pipe);
040484af 2149 else {
6e3c9717 2150 if (crtc->config->has_pch_encoder) {
040484af 2151 /* if driving the PCH, we need FDI enabled */
cc391bbb 2152 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2153 assert_fdi_tx_pll_enabled(dev_priv,
2154 (enum pipe) cpu_transcoder);
040484af
JB		 2155 }
2156 /* FIXME: assert CPU port conditions for SNB+ */
2157 }
b24e7179 2158
702e7a56 2159 reg = PIPECONF(cpu_transcoder);
b24e7179 2160 val = I915_READ(reg);
7ad25d48 2161 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2162 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2163 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2164 return;
7ad25d48 2165 }
00d70b15
CW		 2166
2167 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2168 POSTING_READ(reg);
b24e7179
JB		 2169}
2170
2171/**
309cfea8 2172 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2173 * @crtc: crtc whose pipes is to be disabled
b24e7179 2174 *
575f7ab7
VS		 2175 * Disable the pipe of @crtc, making sure that various hardware
2176 * specific requirements are met, if applicable, e.g. plane
2177 * disabled, panel fitter off, etc.
b24e7179
JB		 2178 *
2179 * Will wait until the pipe has shut down before returning.
2180 */
575f7ab7 2181static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2182{
575f7ab7 2183 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2184 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2185 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2186 int reg;
2187 u32 val;
2188
2189 /*
2190 * Make sure planes won't keep trying to pump pixels to us,
2191 * or we might hang the display.
2192 */
2193 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2194 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2195 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2196
702e7a56 2197 reg = PIPECONF(cpu_transcoder);
b24e7179 2198 val = I915_READ(reg);
00d70b15
CW		 2199 if ((val & PIPECONF_ENABLE) == 0)
2200 return;
2201
67adc644
VS		 2202 /*
2203 * Double wide has implications for planes
2204 * so best keep it disabled when not needed.
2205 */
6e3c9717 2206 if (crtc->config->double_wide)
67adc644
VS		 2207 val &= ~PIPECONF_DOUBLE_WIDE;
2208
2209 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2210 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2211 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2212 val &= ~PIPECONF_ENABLE;
2213
2214 I915_WRITE(reg, val);
2215 if ((val & PIPECONF_ENABLE) == 0)
2216 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2217}
2218
2219/**
262ca2b0 2220 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2221 * @plane: plane to be enabled
2222 * @crtc: crtc for the plane
b24e7179 2223 *
fdd508a6 2224 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2225 */
fdd508a6
VS		 2226static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2227 struct drm_crtc *crtc)
b24e7179 2228{
fdd508a6
VS		 2229 struct drm_device *dev = plane->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2232
2233 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2234 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2235 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2236
fdd508a6
VS		 2237 dev_priv->display.update_primary_plane(crtc, plane->fb,
2238 crtc->x, crtc->y);
b24e7179
JB		 2239}
2240
693db184
CW		 2241static bool need_vtd_wa(struct drm_device *dev)
2242{
2243#ifdef CONFIG_INTEL_IOMMU
2244 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2245 return true;
2246#endif
2247 return false;
2248}
2249
50470bb0 2250unsigned int
6761dd31
TU		 2251intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2252 uint64_t fb_format_modifier)
a57ce0b2 2253{
6761dd31
TU		 2254 unsigned int tile_height;
2255 uint32_t pixel_bytes;
a57ce0b2 2256
b5d0e9bf
DL		 2257 switch (fb_format_modifier) {
2258 case DRM_FORMAT_MOD_NONE:
2259 tile_height = 1;
2260 break;
2261 case I915_FORMAT_MOD_X_TILED:
2262 tile_height = IS_GEN2(dev) ? 16 : 8;
2263 break;
2264 case I915_FORMAT_MOD_Y_TILED:
2265 tile_height = 32;
2266 break;
2267 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2268 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2269 switch (pixel_bytes) {
b5d0e9bf 2270 default:
6761dd31 2271 case 1:
b5d0e9bf
DL		 2272 tile_height = 64;
2273 break;
6761dd31
TU		 2274 case 2:
2275 case 4:
b5d0e9bf
DL		 2276 tile_height = 32;
2277 break;
6761dd31 2278 case 8:
b5d0e9bf
DL		 2279 tile_height = 16;
2280 break;
6761dd31 2281 case 16:
b5d0e9bf
DL		 2282 WARN_ONCE(1,
2283 "128-bit pixels are not supported for display!");
2284 tile_height = 16;
2285 break;
2286 }
2287 break;
2288 default:
2289 MISSING_CASE(fb_format_modifier);
2290 tile_height = 1;
2291 break;
2292 }
091df6cb 2293
6761dd31
TU		 2294 return tile_height;
2295}
2296
2297unsigned int
2298intel_fb_align_height(struct drm_device *dev, unsigned int height,
2299 uint32_t pixel_format, uint64_t fb_format_modifier)
2300{
2301 return ALIGN(height, intel_tile_height(dev, pixel_format,
2302 fb_format_modifier));
a57ce0b2
JB		 2303}
2304
f64b98cd
TU		 2305static int
2306intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2307 const struct drm_plane_state *plane_state)
2308{
50470bb0 2309 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2310
f64b98cd
TU		 2311 *view = i915_ggtt_view_normal;
2312
50470bb0
TU		 2313 if (!plane_state)
2314 return 0;
2315
121920fa 2316 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2317 return 0;
2318
9abc4648 2319 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2320
2321 info->height = fb->height;
2322 info->pixel_format = fb->pixel_format;
2323 info->pitch = fb->pitches[0];
2324 info->fb_modifier = fb->modifier[0];
2325
f64b98cd
TU		 2326 return 0;
2327}
2328
127bd2ac 2329int
850c4cdc
TU		 2330intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331 struct drm_framebuffer *fb,
82bc3b2d 2332 const struct drm_plane_state *plane_state,
a4872ba6 2333 struct intel_engine_cs *pipelined)
6b95a207 2334{
850c4cdc 2335 struct drm_device *dev = fb->dev;
ce453d81 2336 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2337 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2338 struct i915_ggtt_view view;
6b95a207
KH		 2339 u32 alignment;
2340 int ret;
2341
ebcdd39e
MR		 2342 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343
7b911adc
TU		 2344 switch (fb->modifier[0]) {
2345 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2348 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2349 alignment = 128 * 1024;
a6c45cf0 2350 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2351 alignment = 4 * 1024;
2352 else
2353 alignment = 64 * 1024;
6b95a207 2354 break;
7b911adc 2355 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2356 if (INTEL_INFO(dev)->gen >= 9)
2357 alignment = 256 * 1024;
2358 else {
2359 /* pin() will align the object as required by fence */
2360 alignment = 0;
2361 }
6b95a207 2362 break;
7b911adc 2363 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2364 case I915_FORMAT_MOD_Yf_TILED:
2365 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2366 "Y tiling bo slipped through, driver bug!\n"))
2367 return -EINVAL;
2368 alignment = 1 * 1024 * 1024;
2369 break;
6b95a207 2370 default:
7b911adc
TU		 2371 MISSING_CASE(fb->modifier[0]);
2372 return -EINVAL;
6b95a207
KH		 2373 }
2374
f64b98cd
TU		 2375 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376 if (ret)
2377 return ret;
2378
693db184
CW		 2379 /* Note that the w/a also requires 64 PTE of padding following the
2380 * bo. We currently fill all unused PTE with the shadow page and so
2381 * we should always have valid PTE following the scanout preventing
2382 * the VT-d warning.
2383 */
2384 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2385 alignment = 256 * 1024;
2386
d6dd6843
PZ		 2387 /*
2388 * Global gtt pte registers are special registers which actually forward
2389 * writes to a chunk of system memory. Which means that there is no risk
2390 * that the register values disappear as soon as we call
2391 * intel_runtime_pm_put(), so it is correct to wrap only the
2392 * pin/unpin/fence and not more.
2393 */
2394 intel_runtime_pm_get(dev_priv);
2395
ce453d81 2396 dev_priv->mm.interruptible = false;
e6617330 2397 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2398 &view);
48b956c5 2399 if (ret)
ce453d81 2400 goto err_interruptible;
6b95a207
KH		 2401
2402 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2403 * fence, whereas 965+ only requires a fence if using
2404 * framebuffer compression. For simplicity, we always install
2405 * a fence as the cost is not that onerous.
2406 */
06d98131 2407 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2408 if (ret)
2409 goto err_unpin;
1690e1eb 2410
9a5a53b3 2411 i915_gem_object_pin_fence(obj);
6b95a207 2412
ce453d81 2413 dev_priv->mm.interruptible = true;
d6dd6843 2414 intel_runtime_pm_put(dev_priv);
6b95a207 2415 return 0;
48b956c5
CW		 2416
2417err_unpin:
f64b98cd 2418 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2419err_interruptible:
2420 dev_priv->mm.interruptible = true;
d6dd6843 2421 intel_runtime_pm_put(dev_priv);
48b956c5 2422 return ret;
6b95a207
KH		 2423}
2424
82bc3b2d
TU		 2425static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2426 const struct drm_plane_state *plane_state)
1690e1eb 2427{
82bc3b2d 2428 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2429 struct i915_ggtt_view view;
2430 int ret;
82bc3b2d 2431
ebcdd39e
MR		 2432 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433
f64b98cd
TU		 2434 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435 WARN_ONCE(ret, "Couldn't get view from plane state!");
2436
1690e1eb 2437 i915_gem_object_unpin_fence(obj);
f64b98cd 2438 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2439}
2440
c2c75131
DV		 2441/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2442 * is assumed to be a power-of-two. */
bc752862
CW		 2443unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2444 unsigned int tiling_mode,
2445 unsigned int cpp,
2446 unsigned int pitch)
c2c75131 2447{
bc752862
CW		 2448 if (tiling_mode != I915_TILING_NONE) {
2449 unsigned int tile_rows, tiles;
c2c75131 2450
bc752862
CW		 2451 tile_rows = *y / 8;
2452 *y %= 8;
c2c75131 2453
bc752862
CW		 2454 tiles = *x / (512/cpp);
2455 *x %= 512/cpp;
2456
2457 return tile_rows * pitch * 8 + tiles * 4096;
2458 } else {
2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
2462 *y = 0;
2463 *x = (offset & 4095) / cpp;
2464 return offset & -4096;
2465 }
c2c75131
DV		 2466}
2467
b35d63fa 2468static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2469{
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487}
2488
bc8d7dff
DL		 2489static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490{
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513}
2514
5724dbd1 2515static bool
f6936e29
DV		 2516intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2518{
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2522 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
46f297fb 2528
ff2652ea
CW		 2529 if (plane_config->size == 0)
2530 return false;
2531
f37b5c2b
DV		 2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
46f297fb 2536 if (!obj)
484b41dd 2537 return false;
46f297fb 2538
49af449b
DL		 2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2541 obj->stride = fb->pitches[0];
46f297fb 2542
6bf129df
DL		 2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2549
2550 mutex_lock(&dev->struct_mutex);
6bf129df 2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2552 &mode_cmd, obj)) {
46f297fb
JB		 2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
46f297fb 2556 mutex_unlock(&dev->struct_mutex);
484b41dd 2557
f6936e29 2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2559 return true;
46f297fb
JB		 2560
2561out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2564 return false;
2565}
2566
afd65eb4
MR		 2567/* Update plane->state->fb to match plane->fb after driver-internal updates */
2568static void
2569update_state_fb(struct drm_plane *plane)
2570{
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579}
2580
5724dbd1 2581static void
f6936e29
DV		 2582intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2584{
2585 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2586 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2ff8fde1 2589 struct drm_i915_gem_object *obj;
88595ac9
DV		 2590 struct drm_plane *primary = intel_crtc->base.primary;
2591 struct drm_framebuffer *fb;
484b41dd 2592
2d14030b 2593 if (!plane_config->fb)
484b41dd
JB		 2594 return;
2595
f6936e29 2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
f55548b5 2599 }
484b41dd 2600
2d14030b 2601 kfree(plane_config->fb);
484b41dd
JB		 2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
70e1e0ec 2607 for_each_crtc(dev, c) {
484b41dd
JB		 2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2ff8fde1
MR		 2613 if (!i->active)
2614 continue;
2615
88595ac9
DV		 2616 fb = c->primary->fb;
2617 if (!fb)
484b41dd
JB		 2618 continue;
2619
88595ac9 2620 obj = intel_fb_obj(fb);
2ff8fde1 2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
484b41dd
JB		 2624 }
2625 }
88595ac9
DV		 2626
2627 return;
2628
2629valid_fb:
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 primary->fb = fb;
2635 primary->state->crtc = &intel_crtc->base;
2636 primary->crtc = &intel_crtc->base;
2637 update_state_fb(primary);
2638 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2639}
2640
29b9bde6
DV		 2641static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2642 struct drm_framebuffer *fb,
2643 int x, int y)
81255565
JB		 2644{
2645 struct drm_device *dev = crtc->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2648 struct drm_plane *primary = crtc->primary;
2649 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2650 struct drm_i915_gem_object *obj;
81255565 2651 int plane = intel_crtc->plane;
e506a0c6 2652 unsigned long linear_offset;
81255565 2653 u32 dspcntr;
f45651ba 2654 u32 reg = DSPCNTR(plane);
48404c1e 2655 int pixel_size;
f45651ba 2656
b70709a6 2657 if (!visible || !fb) {
fdd508a6
VS		 2658 I915_WRITE(reg, 0);
2659 if (INTEL_INFO(dev)->gen >= 4)
2660 I915_WRITE(DSPSURF(plane), 0);
2661 else
2662 I915_WRITE(DSPADDR(plane), 0);
2663 POSTING_READ(reg);
2664 return;
2665 }
2666
c9ba6fad
VS		 2667 obj = intel_fb_obj(fb);
2668 if (WARN_ON(obj == NULL))
2669 return;
2670
2671 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2672
f45651ba
VS		 2673 dspcntr = DISPPLANE_GAMMA_ENABLE;
2674
fdd508a6 2675 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2676
2677 if (INTEL_INFO(dev)->gen < 4) {
2678 if (intel_crtc->pipe == PIPE_B)
2679 dspcntr |= DISPPLANE_SEL_PIPE_B;
2680
2681 /* pipesrc and dspsize control the size that is scaled from,
2682 * which should always be the user's requested size.
2683 */
2684 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2687 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2688 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2689 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2690 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2691 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2692 I915_WRITE(PRIMPOS(plane), 0);
2693 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2694 }
81255565 2695
57779d06
VS		 2696 switch (fb->pixel_format) {
2697 case DRM_FORMAT_C8:
81255565
JB		 2698 dspcntr |= DISPPLANE_8BPP;
2699 break;
57779d06 2700 case DRM_FORMAT_XRGB1555:
57779d06 2701 dspcntr |= DISPPLANE_BGRX555;
81255565 2702 break;
57779d06
VS		 2703 case DRM_FORMAT_RGB565:
2704 dspcntr |= DISPPLANE_BGRX565;
2705 break;
2706 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX888;
2708 break;
2709 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2710 dspcntr |= DISPPLANE_RGBX888;
2711 break;
2712 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2713 dspcntr |= DISPPLANE_BGRX101010;
2714 break;
2715 case DRM_FORMAT_XBGR2101010:
57779d06 2716 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2717 break;
2718 default:
baba133a 2719 BUG();
81255565 2720 }
57779d06 2721
f45651ba
VS		 2722 if (INTEL_INFO(dev)->gen >= 4 &&
2723 obj->tiling_mode != I915_TILING_NONE)
2724 dspcntr |= DISPPLANE_TILED;
81255565 2725
de1aa629
VS		 2726 if (IS_G4X(dev))
2727 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728
b9897127 2729 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2730
c2c75131
DV		 2731 if (INTEL_INFO(dev)->gen >= 4) {
2732 intel_crtc->dspaddr_offset =
bc752862 2733 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2734 pixel_size,
bc752862 2735 fb->pitches[0]);
c2c75131
DV		 2736 linear_offset -= intel_crtc->dspaddr_offset;
2737 } else {
e506a0c6 2738 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2739 }
e506a0c6 2740
8e7d688b 2741 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2742 dspcntr |= DISPPLANE_ROTATE_180;
2743
6e3c9717
ACO		 2744 x += (intel_crtc->config->pipe_src_w - 1);
2745 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2746
2747 /* Finding the last pixel of the last line of the display
2748 data and adding to linear_offset*/
2749 linear_offset +=
6e3c9717
ACO		 2750 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2751 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2752 }
2753
2754 I915_WRITE(reg, dspcntr);
2755
01f2c773 2756 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2757 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2758 I915_WRITE(DSPSURF(plane),
2759 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2760 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2761 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2762 } else
f343c5f6 2763 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2764 POSTING_READ(reg);
17638cd6
JB		 2765}
2766
29b9bde6
DV		 2767static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2768 struct drm_framebuffer *fb,
2769 int x, int y)
17638cd6
JB		 2770{
2771 struct drm_device *dev = crtc->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2774 struct drm_plane *primary = crtc->primary;
2775 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2776 struct drm_i915_gem_object *obj;
17638cd6 2777 int plane = intel_crtc->plane;
e506a0c6 2778 unsigned long linear_offset;
17638cd6 2779 u32 dspcntr;
f45651ba 2780 u32 reg = DSPCNTR(plane);
48404c1e 2781 int pixel_size;
f45651ba 2782
b70709a6 2783 if (!visible || !fb) {
fdd508a6
VS		 2784 I915_WRITE(reg, 0);
2785 I915_WRITE(DSPSURF(plane), 0);
2786 POSTING_READ(reg);
2787 return;
2788 }
2789
c9ba6fad
VS		 2790 obj = intel_fb_obj(fb);
2791 if (WARN_ON(obj == NULL))
2792 return;
2793
2794 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2795
f45651ba
VS		 2796 dspcntr = DISPPLANE_GAMMA_ENABLE;
2797
fdd508a6 2798 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2799
2800 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2801 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2802
57779d06
VS		 2803 switch (fb->pixel_format) {
2804 case DRM_FORMAT_C8:
17638cd6
JB		 2805 dspcntr |= DISPPLANE_8BPP;
2806 break;
57779d06
VS		 2807 case DRM_FORMAT_RGB565:
2808 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2809 break;
57779d06 2810 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX888;
2812 break;
2813 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2814 dspcntr |= DISPPLANE_RGBX888;
2815 break;
2816 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2817 dspcntr |= DISPPLANE_BGRX101010;
2818 break;
2819 case DRM_FORMAT_XBGR2101010:
57779d06 2820 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2821 break;
2822 default:
baba133a 2823 BUG();
17638cd6
JB		 2824 }
2825
2826 if (obj->tiling_mode != I915_TILING_NONE)
2827 dspcntr |= DISPPLANE_TILED;
17638cd6 2828
f45651ba 2829 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2830 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2831
b9897127 2832 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2833 intel_crtc->dspaddr_offset =
bc752862 2834 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2835 pixel_size,
bc752862 2836 fb->pitches[0]);
c2c75131 2837 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2838 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2839 dspcntr |= DISPPLANE_ROTATE_180;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2842 x += (intel_crtc->config->pipe_src_w - 1);
2843 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2844
2845 /* Finding the last pixel of the last line of the display
2846 data and adding to linear_offset*/
2847 linear_offset +=
6e3c9717
ACO		 2848 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2850 }
2851 }
2852
2853 I915_WRITE(reg, dspcntr);
17638cd6 2854
01f2c773 2855 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2856 I915_WRITE(DSPSURF(plane),
2857 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2858 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2859 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2860 } else {
2861 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862 I915_WRITE(DSPLINOFF(plane), linear_offset);
2863 }
17638cd6 2864 POSTING_READ(reg);
17638cd6
JB		 2865}
2866
b321803d
DL		 2867u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868 uint32_t pixel_format)
2869{
2870 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871
2872 /*
2873 * The stride is either expressed as a multiple of 64 bytes
2874 * chunks for linear buffers or in number of tiles for tiled
2875 * buffers.
2876 */
2877 switch (fb_modifier) {
2878 case DRM_FORMAT_MOD_NONE:
2879 return 64;
2880 case I915_FORMAT_MOD_X_TILED:
2881 if (INTEL_INFO(dev)->gen == 2)
2882 return 128;
2883 return 512;
2884 case I915_FORMAT_MOD_Y_TILED:
2885 /* No need to check for old gens and Y tiling since this is
2886 * about the display engine and those will be blocked before
2887 * we get here.
2888 */
2889 return 128;
2890 case I915_FORMAT_MOD_Yf_TILED:
2891 if (bits_per_pixel == 8)
2892 return 64;
2893 else
2894 return 128;
2895 default:
2896 MISSING_CASE(fb_modifier);
2897 return 64;
2898 }
2899}
2900
121920fa
TU		 2901unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902 struct drm_i915_gem_object *obj)
2903{
9abc4648 2904 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2905
2906 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2907 view = &i915_ggtt_view_rotated;
121920fa
TU		 2908
2909 return i915_gem_obj_ggtt_offset_view(obj, view);
2910}
2911
a1b2278e
CK		 2912/*
2913 * This function detaches (aka. unbinds) unused scalers in hardware
2914 */
2915void skl_detach_scalers(struct intel_crtc *intel_crtc)
2916{
2917 struct drm_device *dev;
2918 struct drm_i915_private *dev_priv;
2919 struct intel_crtc_scaler_state *scaler_state;
2920 int i;
2921
2922 if (!intel_crtc || !intel_crtc->config)
2923 return;
2924
2925 dev = intel_crtc->base.dev;
2926 dev_priv = dev->dev_private;
2927 scaler_state = &intel_crtc->config->scaler_state;
2928
2929 /* loop through and disable scalers that aren't in use */
2930 for (i = 0; i < intel_crtc->num_scalers; i++) {
2931 if (!scaler_state->scalers[i].in_use) {
2932 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2933 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2934 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2935 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2936 intel_crtc->base.base.id, intel_crtc->pipe, i);
2937 }
2938 }
2939}
2940
6156a456 2941u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2942{
6156a456 2943 switch (pixel_format) {
d161cf7a 2944 case DRM_FORMAT_C8:
c34ce3d1 2945 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2946 case DRM_FORMAT_RGB565:
c34ce3d1 2947 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2948 case DRM_FORMAT_XBGR8888:
c34ce3d1 2949 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2950 case DRM_FORMAT_XRGB8888:
c34ce3d1 2951 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2952 /*
2953 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2954 * to be already pre-multiplied. We need to add a knob (or a different
2955 * DRM_FORMAT) for user-space to configure that.
2956 */
f75fb42a 2957 case DRM_FORMAT_ABGR8888:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2959 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2960 case DRM_FORMAT_ARGB8888:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2962 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2963 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2964 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2965 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2966 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2967 case DRM_FORMAT_YUYV:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2969 case DRM_FORMAT_YVYU:
c34ce3d1 2970 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2971 case DRM_FORMAT_UYVY:
c34ce3d1 2972 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2973 case DRM_FORMAT_VYUY:
c34ce3d1 2974 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2975 default:
4249eeef 2976 MISSING_CASE(pixel_format);
70d21f0e 2977 }
8cfcba41 2978
c34ce3d1 2979 return 0;
6156a456 2980}
70d21f0e 2981
6156a456
CK		 2982u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2983{
6156a456 2984 switch (fb_modifier) {
30af77c4 2985 case DRM_FORMAT_MOD_NONE:
70d21f0e 2986 break;
30af77c4 2987 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2988 return PLANE_CTL_TILED_X;
b321803d 2989 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2990 return PLANE_CTL_TILED_Y;
b321803d 2991 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2992 return PLANE_CTL_TILED_YF;
70d21f0e 2993 default:
6156a456 2994 MISSING_CASE(fb_modifier);
70d21f0e 2995 }
8cfcba41 2996
c34ce3d1 2997 return 0;
6156a456 2998}
70d21f0e 2999
6156a456
CK		 3000u32 skl_plane_ctl_rotation(unsigned int rotation)
3001{
3b7a5119 3002 switch (rotation) {
6156a456
CK		 3003 case BIT(DRM_ROTATE_0):
3004 break;
1e8df167
SJ		 3005 /*
3006 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3007 * while i915 HW rotation is clockwise, thats why this swapping.
3008 */
3b7a5119 3009 case BIT(DRM_ROTATE_90):
1e8df167 3010 return PLANE_CTL_ROTATE_270;
3b7a5119 3011 case BIT(DRM_ROTATE_180):
c34ce3d1 3012 return PLANE_CTL_ROTATE_180;
3b7a5119 3013 case BIT(DRM_ROTATE_270):
1e8df167 3014 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3015 default:
3016 MISSING_CASE(rotation);
3017 }
3018
c34ce3d1 3019 return 0;
6156a456
CK		 3020}
3021
3022static void skylake_update_primary_plane(struct drm_crtc *crtc,
3023 struct drm_framebuffer *fb,
3024 int x, int y)
3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3029 struct drm_plane *plane = crtc->primary;
3030 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3031 struct drm_i915_gem_object *obj;
3032 int pipe = intel_crtc->pipe;
3033 u32 plane_ctl, stride_div, stride;
3034 u32 tile_height, plane_offset, plane_size;
3035 unsigned int rotation;
3036 int x_offset, y_offset;
3037 unsigned long surf_addr;
6156a456
CK		 3038 struct intel_crtc_state *crtc_state = intel_crtc->config;
3039 struct intel_plane_state *plane_state;
3040 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3041 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3042 int scaler_id = -1;
3043
6156a456
CK		 3044 plane_state = to_intel_plane_state(plane->state);
3045
b70709a6 3046 if (!visible || !fb) {
6156a456
CK		 3047 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3048 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3049 POSTING_READ(PLANE_CTL(pipe, 0));
3050 return;
3b7a5119 3051 }
70d21f0e 3052
6156a456
CK		 3053 plane_ctl = PLANE_CTL_ENABLE |
3054 PLANE_CTL_PIPE_GAMMA_ENABLE |
3055 PLANE_CTL_PIPE_CSC_ENABLE;
3056
3057 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3058 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3059 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3060
3061 rotation = plane->state->rotation;
3062 plane_ctl |= skl_plane_ctl_rotation(rotation);
3063
b321803d
DL		 3064 obj = intel_fb_obj(fb);
3065 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3066 fb->pixel_format);
3b7a5119
SJ		 3067 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3068
6156a456
CK		 3069 /*
3070 * FIXME: intel_plane_state->src, dst aren't set when transitional
3071 * update_plane helpers are called from legacy paths.
3072 * Once full atomic crtc is available, below check can be avoided.
3073 */
3074 if (drm_rect_width(&plane_state->src)) {
3075 scaler_id = plane_state->scaler_id;
3076 src_x = plane_state->src.x1 >> 16;
3077 src_y = plane_state->src.y1 >> 16;
3078 src_w = drm_rect_width(&plane_state->src) >> 16;
3079 src_h = drm_rect_height(&plane_state->src) >> 16;
3080 dst_x = plane_state->dst.x1;
3081 dst_y = plane_state->dst.y1;
3082 dst_w = drm_rect_width(&plane_state->dst);
3083 dst_h = drm_rect_height(&plane_state->dst);
3084
3085 WARN_ON(x != src_x || y != src_y);
3086 } else {
3087 src_w = intel_crtc->config->pipe_src_w;
3088 src_h = intel_crtc->config->pipe_src_h;
3089 }
3090
3b7a5119
SJ		 3091 if (intel_rotation_90_or_270(rotation)) {
3092 /* stride = Surface height in tiles */
2614f17d 3093 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3094 fb->modifier[0]);
3095 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3096 x_offset = stride * tile_height - y - src_h;
3b7a5119 3097 y_offset = x;
6156a456 3098 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3099 } else {
3100 stride = fb->pitches[0] / stride_div;
3101 x_offset = x;
3102 y_offset = y;
6156a456 3103 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3104 }
3105 plane_offset = y_offset << 16 | x_offset;
b321803d 3106
70d21f0e 3107 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3108 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3109 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3110 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3111
3112 if (scaler_id >= 0) {
3113 uint32_t ps_ctrl = 0;
3114
3115 WARN_ON(!dst_w || !dst_h);
3116 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3117 crtc_state->scaler_state.scalers[scaler_id].mode;
3118 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3119 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3120 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3121 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3122 I915_WRITE(PLANE_POS(pipe, 0), 0);
3123 } else {
3124 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3125 }
3126
121920fa 3127 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3128
3129 POSTING_READ(PLANE_SURF(pipe, 0));
3130}
3131
17638cd6
JB		 3132/* Assume fb object is pinned & idle & fenced and just update base pointers */
3133static int
3134intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3135 int x, int y, enum mode_set_atomic state)
3136{
3137 struct drm_device *dev = crtc->dev;
3138 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3139
6b8e6ed0
CW		 3140 if (dev_priv->display.disable_fbc)
3141 dev_priv->display.disable_fbc(dev);
81255565 3142
29b9bde6
DV		 3143 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3144
3145 return 0;
81255565
JB		 3146}
3147
7514747d 3148static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3149{
96a02917
VS		 3150 struct drm_crtc *crtc;
3151
70e1e0ec 3152 for_each_crtc(dev, crtc) {
96a02917
VS		 3153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154 enum plane plane = intel_crtc->plane;
3155
3156 intel_prepare_page_flip(dev, plane);
3157 intel_finish_page_flip_plane(dev, plane);
3158 }
7514747d
VS		 3159}
3160
3161static void intel_update_primary_planes(struct drm_device *dev)
3162{
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct drm_crtc *crtc;
96a02917 3165
70e1e0ec 3166 for_each_crtc(dev, crtc) {
96a02917
VS		 3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168
51fd371b 3169 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3170 /*
3171 * FIXME: Once we have proper support for primary planes (and
3172 * disabling them without disabling the entire crtc) allow again
66e514c1 3173 * a NULL crtc->primary->fb.
947fdaad 3174 */
f4510a27 3175 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3176 dev_priv->display.update_primary_plane(crtc,
66e514c1 3177 crtc->primary->fb,
262ca2b0
MR		 3178 crtc->x,
3179 crtc->y);
51fd371b 3180 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3181 }
3182}
3183
7514747d
VS		 3184void intel_prepare_reset(struct drm_device *dev)
3185{
3186 /* no reset support for gen2 */
3187 if (IS_GEN2(dev))
3188 return;
3189
3190 /* reset doesn't touch the display */
3191 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3192 return;
3193
3194 drm_modeset_lock_all(dev);
f98ce92f
VS		 3195 /*
3196 * Disabling the crtcs gracefully seems nicer. Also the
3197 * g33 docs say we should at least disable all the planes.
3198 */
6b72d486 3199 intel_display_suspend(dev);
7514747d
VS		 3200}
3201
3202void intel_finish_reset(struct drm_device *dev)
3203{
3204 struct drm_i915_private *dev_priv = to_i915(dev);
3205
3206 /*
3207 * Flips in the rings will be nuked by the reset,
3208 * so complete all pending flips so that user space
3209 * will get its events and not get stuck.
3210 */
3211 intel_complete_page_flips(dev);
3212
3213 /* no reset support for gen2 */
3214 if (IS_GEN2(dev))
3215 return;
3216
3217 /* reset doesn't touch the display */
3218 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3219 /*
3220 * Flips in the rings have been nuked by the reset,
3221 * so update the base address of all primary
3222 * planes to the the last fb to make sure we're
3223 * showing the correct fb after a reset.
3224 */
3225 intel_update_primary_planes(dev);
3226 return;
3227 }
3228
3229 /*
3230 * The display has been reset as well,
3231 * so need a full re-initialization.
3232 */
3233 intel_runtime_pm_disable_interrupts(dev_priv);
3234 intel_runtime_pm_enable_interrupts(dev_priv);
3235
3236 intel_modeset_init_hw(dev);
3237
3238 spin_lock_irq(&dev_priv->irq_lock);
3239 if (dev_priv->display.hpd_irq_setup)
3240 dev_priv->display.hpd_irq_setup(dev);
3241 spin_unlock_irq(&dev_priv->irq_lock);
3242
3243 intel_modeset_setup_hw_state(dev, true);
3244
3245 intel_hpd_init(dev_priv);
3246
3247 drm_modeset_unlock_all(dev);
3248}
3249
2e2f351d 3250static void
14667a4b
CW		 3251intel_finish_fb(struct drm_framebuffer *old_fb)
3252{
2ff8fde1 3253 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3254 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3255 bool was_interruptible = dev_priv->mm.interruptible;
3256 int ret;
3257
14667a4b
CW		 3258 /* Big Hammer, we also need to ensure that any pending
3259 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3260 * current scanout is retired before unpinning the old
2e2f351d
CW		 3261 * framebuffer. Note that we rely on userspace rendering
3262 * into the buffer attached to the pipe they are waiting
3263 * on. If not, userspace generates a GPU hang with IPEHR
3264 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3265 *
3266 * This should only fail upon a hung GPU, in which case we
3267 * can safely continue.
3268 */
3269 dev_priv->mm.interruptible = false;
2e2f351d 3270 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3271 dev_priv->mm.interruptible = was_interruptible;
3272
2e2f351d 3273 WARN_ON(ret);
14667a4b
CW		 3274}
3275
7d5e3799
CW		 3276static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3277{
3278 struct drm_device *dev = crtc->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3281 bool pending;
3282
3283 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3284 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3285 return false;
3286
5e2d7afc 3287 spin_lock_irq(&dev->event_lock);
7d5e3799 3288 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3289 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3290
3291 return pending;
3292}
3293
e30e8f75
GP		 3294static void intel_update_pipe_size(struct intel_crtc *crtc)
3295{
3296 struct drm_device *dev = crtc->base.dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 const struct drm_display_mode *adjusted_mode;
3299
3300 if (!i915.fastboot)
3301 return;
3302
3303 /*
3304 * Update pipe size and adjust fitter if needed: the reason for this is
3305 * that in compute_mode_changes we check the native mode (not the pfit
3306 * mode) to see if we can flip rather than do a full mode set. In the
3307 * fastboot case, we'll flip, but if we don't update the pipesrc and
3308 * pfit state, we'll end up with a big fb scanned out into the wrong
3309 * sized surface.
3310 *
3311 * To fix this properly, we need to hoist the checks up into
3312 * compute_mode_changes (or above), check the actual pfit state and
3313 * whether the platform allows pfit disable with pipe active, and only
3314 * then update the pipesrc and pfit state, even on the flip path.
3315 */
3316
6e3c9717 3317 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3318
3319 I915_WRITE(PIPESRC(crtc->pipe),
3320 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3321 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3322 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3323 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3324 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3325 I915_WRITE(PF_CTL(crtc->pipe), 0);
3326 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3327 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3328 }
6e3c9717
ACO		 3329 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3330 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3331}
3332
5e84e1a4
ZW		 3333static void intel_fdi_normal_train(struct drm_crtc *crtc)
3334{
3335 struct drm_device *dev = crtc->dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 int pipe = intel_crtc->pipe;
3339 u32 reg, temp;
3340
3341 /* enable normal train */
3342 reg = FDI_TX_CTL(pipe);
3343 temp = I915_READ(reg);
61e499bf 3344 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3347 } else {
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3350 }
5e84e1a4
ZW		 3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 if (HAS_PCH_CPT(dev)) {
3356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3358 } else {
3359 temp &= ~FDI_LINK_TRAIN_NONE;
3360 temp |= FDI_LINK_TRAIN_NONE;
3361 }
3362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3363
3364 /* wait one idle pattern time */
3365 POSTING_READ(reg);
3366 udelay(1000);
357555c0
JB		 3367
3368 /* IVB wants error correction enabled */
3369 if (IS_IVYBRIDGE(dev))
3370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3371 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3372}
3373
8db9d77b
ZW		 3374/* The FDI link training functions for ILK/Ibexpeak. */
3375static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3376{
3377 struct drm_device *dev = crtc->dev;
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3380 int pipe = intel_crtc->pipe;
5eddb70b 3381 u32 reg, temp, tries;
8db9d77b 3382
1c8562f6 3383 /* FDI needs bits from pipe first */
0fc932b8 3384 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3385
e1a44743
AJ		 3386 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3387 for train result */
5eddb70b
CW		 3388 reg = FDI_RX_IMR(pipe);
3389 temp = I915_READ(reg);
e1a44743
AJ		 3390 temp &= ~FDI_RX_SYMBOL_LOCK;
3391 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3392 I915_WRITE(reg, temp);
3393 I915_READ(reg);
e1a44743
AJ		 3394 udelay(150);
3395
8db9d77b 3396 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
627eb5a3 3399 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3400 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3403 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3404
5eddb70b
CW		 3405 reg = FDI_RX_CTL(pipe);
3406 temp = I915_READ(reg);
8db9d77b
ZW		 3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3409 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3410
3411 POSTING_READ(reg);
8db9d77b
ZW		 3412 udelay(150);
3413
5b2adf89 3414 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3417 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3418
5eddb70b 3419 reg = FDI_RX_IIR(pipe);
e1a44743 3420 for (tries = 0; tries < 5; tries++) {
5eddb70b 3421 temp = I915_READ(reg);
8db9d77b
ZW		 3422 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3423
3424 if ((temp & FDI_RX_BIT_LOCK)) {
3425 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3426 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3427 break;
3428 }
8db9d77b 3429 }
e1a44743 3430 if (tries == 5)
5eddb70b 3431 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3432
3433 /* Train 2 */
5eddb70b
CW		 3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
8db9d77b
ZW		 3436 temp &= ~FDI_LINK_TRAIN_NONE;
3437 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3438 I915_WRITE(reg, temp);
8db9d77b 3439
5eddb70b
CW		 3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
8db9d77b
ZW		 3442 temp &= ~FDI_LINK_TRAIN_NONE;
3443 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3444 I915_WRITE(reg, temp);
8db9d77b 3445
5eddb70b
CW		 3446 POSTING_READ(reg);
3447 udelay(150);
8db9d77b 3448
5eddb70b 3449 reg = FDI_RX_IIR(pipe);
e1a44743 3450 for (tries = 0; tries < 5; tries++) {
5eddb70b 3451 temp = I915_READ(reg);
8db9d77b
ZW		 3452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3453
3454 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3455 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3456 DRM_DEBUG_KMS("FDI train 2 done.\n");
3457 break;
3458 }
8db9d77b 3459 }
e1a44743 3460 if (tries == 5)
5eddb70b 3461 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3462
3463 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3464
8db9d77b
ZW		 3465}
3466
0206e353 3467static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3468 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3469 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3470 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3471 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3472};
3473
3474/* The FDI link training functions for SNB/Cougarpoint. */
3475static void gen6_fdi_link_train(struct drm_crtc *crtc)
3476{
3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 int pipe = intel_crtc->pipe;
fa37d39e 3481 u32 reg, temp, i, retry;
8db9d77b 3482
e1a44743
AJ		 3483 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3484 for train result */
5eddb70b
CW		 3485 reg = FDI_RX_IMR(pipe);
3486 temp = I915_READ(reg);
e1a44743
AJ		 3487 temp &= ~FDI_RX_SYMBOL_LOCK;
3488 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3489 I915_WRITE(reg, temp);
3490
3491 POSTING_READ(reg);
e1a44743
AJ		 3492 udelay(150);
3493
8db9d77b 3494 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3495 reg = FDI_TX_CTL(pipe);
3496 temp = I915_READ(reg);
627eb5a3 3497 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3498 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3499 temp &= ~FDI_LINK_TRAIN_NONE;
3500 temp |= FDI_LINK_TRAIN_PATTERN_1;
3501 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3502 /* SNB-B */
3503 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3504 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3505
d74cf324
DV		 3506 I915_WRITE(FDI_RX_MISC(pipe),
3507 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3508
5eddb70b
CW		 3509 reg = FDI_RX_CTL(pipe);
3510 temp = I915_READ(reg);
8db9d77b
ZW		 3511 if (HAS_PCH_CPT(dev)) {
3512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3514 } else {
3515 temp &= ~FDI_LINK_TRAIN_NONE;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1;
3517 }
5eddb70b
CW		 3518 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3519
3520 POSTING_READ(reg);
8db9d77b
ZW		 3521 udelay(150);
3522
0206e353 3523 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3524 reg = FDI_TX_CTL(pipe);
3525 temp = I915_READ(reg);
8db9d77b
ZW		 3526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3527 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3528 I915_WRITE(reg, temp);
3529
3530 POSTING_READ(reg);
8db9d77b
ZW		 3531 udelay(500);
3532
fa37d39e
SP		 3533 for (retry = 0; retry < 5; retry++) {
3534 reg = FDI_RX_IIR(pipe);
3535 temp = I915_READ(reg);
3536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3537 if (temp & FDI_RX_BIT_LOCK) {
3538 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3539 DRM_DEBUG_KMS("FDI train 1 done.\n");
3540 break;
3541 }
3542 udelay(50);
8db9d77b 3543 }
fa37d39e
SP		 3544 if (retry < 5)
3545 break;
8db9d77b
ZW		 3546 }
3547 if (i == 4)
5eddb70b 3548 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3549
3550 /* Train 2 */
5eddb70b
CW		 3551 reg = FDI_TX_CTL(pipe);
3552 temp = I915_READ(reg);
8db9d77b
ZW		 3553 temp &= ~FDI_LINK_TRAIN_NONE;
3554 temp |= FDI_LINK_TRAIN_PATTERN_2;
3555 if (IS_GEN6(dev)) {
3556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3557 /* SNB-B */
3558 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3559 }
5eddb70b 3560 I915_WRITE(reg, temp);
8db9d77b 3561
5eddb70b
CW		 3562 reg = FDI_RX_CTL(pipe);
3563 temp = I915_READ(reg);
8db9d77b
ZW		 3564 if (HAS_PCH_CPT(dev)) {
3565 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3566 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3567 } else {
3568 temp &= ~FDI_LINK_TRAIN_NONE;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2;
3570 }
5eddb70b
CW		 3571 I915_WRITE(reg, temp);
3572
3573 POSTING_READ(reg);
8db9d77b
ZW		 3574 udelay(150);
3575
0206e353 3576 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3577 reg = FDI_TX_CTL(pipe);
3578 temp = I915_READ(reg);
8db9d77b
ZW		 3579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3580 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
8db9d77b
ZW		 3584 udelay(500);
3585
fa37d39e
SP		 3586 for (retry = 0; retry < 5; retry++) {
3587 reg = FDI_RX_IIR(pipe);
3588 temp = I915_READ(reg);
3589 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3590 if (temp & FDI_RX_SYMBOL_LOCK) {
3591 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3592 DRM_DEBUG_KMS("FDI train 2 done.\n");
3593 break;
3594 }
3595 udelay(50);
8db9d77b 3596 }
fa37d39e
SP		 3597 if (retry < 5)
3598 break;
8db9d77b
ZW		 3599 }
3600 if (i == 4)
5eddb70b 3601 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3602
3603 DRM_DEBUG_KMS("FDI train done.\n");
3604}
3605
357555c0
JB		 3606/* Manual link training for Ivy Bridge A0 parts */
3607static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3608{
3609 struct drm_device *dev = crtc->dev;
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612 int pipe = intel_crtc->pipe;
139ccd3f 3613 u32 reg, temp, i, j;
357555c0
JB		 3614
3615 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3616 for train result */
3617 reg = FDI_RX_IMR(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~FDI_RX_SYMBOL_LOCK;
3620 temp &= ~FDI_RX_BIT_LOCK;
3621 I915_WRITE(reg, temp);
3622
3623 POSTING_READ(reg);
3624 udelay(150);
3625
01a415fd
DV		 3626 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3627 I915_READ(FDI_RX_IIR(pipe)));
3628
139ccd3f
JB		 3629 /* Try each vswing and preemphasis setting twice before moving on */
3630 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3631 /* disable first in case we need to retry */
3632 reg = FDI_TX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3635 temp &= ~FDI_TX_ENABLE;
3636 I915_WRITE(reg, temp);
357555c0 3637
139ccd3f
JB		 3638 reg = FDI_RX_CTL(pipe);
3639 temp = I915_READ(reg);
3640 temp &= ~FDI_LINK_TRAIN_AUTO;
3641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3642 temp &= ~FDI_RX_ENABLE;
3643 I915_WRITE(reg, temp);
357555c0 3644
139ccd3f 3645 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3646 reg = FDI_TX_CTL(pipe);
3647 temp = I915_READ(reg);
139ccd3f 3648 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3649 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3650 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3652 temp |= snb_b_fdi_train_param[j/2];
3653 temp |= FDI_COMPOSITE_SYNC;
3654 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3655
139ccd3f
JB		 3656 I915_WRITE(FDI_RX_MISC(pipe),
3657 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3658
139ccd3f 3659 reg = FDI_RX_CTL(pipe);
357555c0 3660 temp = I915_READ(reg);
139ccd3f
JB		 3661 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3662 temp |= FDI_COMPOSITE_SYNC;
3663 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3664
139ccd3f
JB		 3665 POSTING_READ(reg);
3666 udelay(1); /* should be 0.5us */
357555c0 3667
139ccd3f
JB		 3668 for (i = 0; i < 4; i++) {
3669 reg = FDI_RX_IIR(pipe);
3670 temp = I915_READ(reg);
3671 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3672
139ccd3f
JB		 3673 if (temp & FDI_RX_BIT_LOCK ||
3674 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3675 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3676 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3677 i);
3678 break;
3679 }
3680 udelay(1); /* should be 0.5us */
3681 }
3682 if (i == 4) {
3683 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3684 continue;
3685 }
357555c0 3686
139ccd3f 3687 /* Train 2 */
357555c0
JB		 3688 reg = FDI_TX_CTL(pipe);
3689 temp = I915_READ(reg);
139ccd3f
JB		 3690 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3691 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3692 I915_WRITE(reg, temp);
3693
3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3697 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3698 I915_WRITE(reg, temp);
3699
3700 POSTING_READ(reg);
139ccd3f 3701 udelay(2); /* should be 1.5us */
357555c0 3702
139ccd3f
JB		 3703 for (i = 0; i < 4; i++) {
3704 reg = FDI_RX_IIR(pipe);
3705 temp = I915_READ(reg);
3706 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3707
139ccd3f
JB		 3708 if (temp & FDI_RX_SYMBOL_LOCK ||
3709 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3711 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3712 i);
3713 goto train_done;
3714 }
3715 udelay(2); /* should be 1.5us */
357555c0 3716 }
139ccd3f
JB		 3717 if (i == 4)
3718 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3719 }
357555c0 3720
139ccd3f 3721train_done:
357555c0
JB		 3722 DRM_DEBUG_KMS("FDI train done.\n");
3723}
3724
88cefb6c 3725static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3726{
88cefb6c 3727 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3728 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3729 int pipe = intel_crtc->pipe;
5eddb70b 3730 u32 reg, temp;
79e53945 3731
c64e311e 3732
c98e9dcf 3733 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3734 reg = FDI_RX_CTL(pipe);
3735 temp = I915_READ(reg);
627eb5a3 3736 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3737 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3738 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3739 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3740
3741 POSTING_READ(reg);
c98e9dcf
JB		 3742 udelay(200);
3743
3744 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3745 temp = I915_READ(reg);
3746 I915_WRITE(reg, temp | FDI_PCDCLK);
3747
3748 POSTING_READ(reg);
c98e9dcf
JB		 3749 udelay(200);
3750
20749730
PZ		 3751 /* Enable CPU FDI TX PLL, always on for Ironlake */
3752 reg = FDI_TX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3755 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3756
20749730
PZ		 3757 POSTING_READ(reg);
3758 udelay(100);
6be4a607 3759 }
0e23b99d
JB		 3760}
3761
88cefb6c
DV		 3762static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3763{
3764 struct drm_device *dev = intel_crtc->base.dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 int pipe = intel_crtc->pipe;
3767 u32 reg, temp;
3768
3769 /* Switch from PCDclk to Rawclk */
3770 reg = FDI_RX_CTL(pipe);
3771 temp = I915_READ(reg);
3772 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3773
3774 /* Disable CPU FDI TX PLL */
3775 reg = FDI_TX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3778
3779 POSTING_READ(reg);
3780 udelay(100);
3781
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3785
3786 /* Wait for the clocks to turn off. */
3787 POSTING_READ(reg);
3788 udelay(100);
3789}
3790
0fc932b8
JB		 3791static void ironlake_fdi_disable(struct drm_crtc *crtc)
3792{
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796 int pipe = intel_crtc->pipe;
3797 u32 reg, temp;
3798
3799 /* disable CPU FDI tx and PCH FDI rx */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3803 POSTING_READ(reg);
3804
3805 reg = FDI_RX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 temp &= ~(0x7 << 16);
dfd07d72 3808 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3809 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3810
3811 POSTING_READ(reg);
3812 udelay(100);
3813
3814 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3815 if (HAS_PCH_IBX(dev))
6f06ce18 3816 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3817
3818 /* still set train pattern 1 */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 temp &= ~FDI_LINK_TRAIN_NONE;
3822 temp |= FDI_LINK_TRAIN_PATTERN_1;
3823 I915_WRITE(reg, temp);
3824
3825 reg = FDI_RX_CTL(pipe);
3826 temp = I915_READ(reg);
3827 if (HAS_PCH_CPT(dev)) {
3828 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3829 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3830 } else {
3831 temp &= ~FDI_LINK_TRAIN_NONE;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1;
3833 }
3834 /* BPC in FDI rx is consistent with that in PIPECONF */
3835 temp &= ~(0x07 << 16);
dfd07d72 3836 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3837 I915_WRITE(reg, temp);
3838
3839 POSTING_READ(reg);
3840 udelay(100);
3841}
3842
5dce5b93
CW		 3843bool intel_has_pending_fb_unpin(struct drm_device *dev)
3844{
3845 struct intel_crtc *crtc;
3846
3847 /* Note that we don't need to be called with mode_config.lock here
3848 * as our list of CRTC objects is static for the lifetime of the
3849 * device and so cannot disappear as we iterate. Similarly, we can
3850 * happily treat the predicates as racy, atomic checks as userspace
3851 * cannot claim and pin a new fb without at least acquring the
3852 * struct_mutex and so serialising with us.
3853 */
d3fcc808 3854 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3855 if (atomic_read(&crtc->unpin_work_count) == 0)
3856 continue;
3857
3858 if (crtc->unpin_work)
3859 intel_wait_for_vblank(dev, crtc->pipe);
3860
3861 return true;
3862 }
3863
3864 return false;
3865}
3866
d6bbafa1
CW		 3867static void page_flip_completed(struct intel_crtc *intel_crtc)
3868{
3869 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3870 struct intel_unpin_work *work = intel_crtc->unpin_work;
3871
3872 /* ensure that the unpin work is consistent wrt ->pending. */
3873 smp_rmb();
3874 intel_crtc->unpin_work = NULL;
3875
3876 if (work->event)
3877 drm_send_vblank_event(intel_crtc->base.dev,
3878 intel_crtc->pipe,
3879 work->event);
3880
3881 drm_crtc_vblank_put(&intel_crtc->base);
3882
3883 wake_up_all(&dev_priv->pending_flip_queue);
3884 queue_work(dev_priv->wq, &work->work);
3885
3886 trace_i915_flip_complete(intel_crtc->plane,
3887 work->pending_flip_obj);
3888}
3889
46a55d30 3890void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3891{
0f91128d 3892 struct drm_device *dev = crtc->dev;
5bb61643 3893 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3894
2c10d571 3895 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3896 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3897 !intel_crtc_has_pending_flip(crtc),
3898 60*HZ) == 0)) {
3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3900
5e2d7afc 3901 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3902 if (intel_crtc->unpin_work) {
3903 WARN_ONCE(1, "Removing stuck page flip\n");
3904 page_flip_completed(intel_crtc);
3905 }
5e2d7afc 3906 spin_unlock_irq(&dev->event_lock);
9c787942 3907 }
5bb61643 3908
975d568a
CW		 3909 if (crtc->primary->fb) {
3910 mutex_lock(&dev->struct_mutex);
3911 intel_finish_fb(crtc->primary->fb);
3912 mutex_unlock(&dev->struct_mutex);
3913 }
e6c3a2a6
CW		 3914}
3915
e615efe4
ED		 3916/* Program iCLKIP clock to the desired frequency */
3917static void lpt_program_iclkip(struct drm_crtc *crtc)
3918{
3919 struct drm_device *dev = crtc->dev;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3921 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3922 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3923 u32 temp;
3924
a580516d 3925 mutex_lock(&dev_priv->sb_lock);
09153000 3926
e615efe4
ED		 3927 /* It is necessary to ungate the pixclk gate prior to programming
3928 * the divisors, and gate it back when it is done.
3929 */
3930 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3931
3932 /* Disable SSCCTL */
3933 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3934 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3935 SBI_SSCCTL_DISABLE,
3936 SBI_ICLK);
e615efe4
ED		 3937
3938 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3939 if (clock == 20000) {
e615efe4
ED		 3940 auxdiv = 1;
3941 divsel = 0x41;
3942 phaseinc = 0x20;
3943 } else {
3944 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3945 * but the adjusted_mode->crtc_clock in in KHz. To get the
3946 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3947 * convert the virtual clock precision to KHz here for higher
3948 * precision.
3949 */
3950 u32 iclk_virtual_root_freq = 172800 * 1000;
3951 u32 iclk_pi_range = 64;
3952 u32 desired_divisor, msb_divisor_value, pi_value;
3953
12d7ceed 3954 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3955 msb_divisor_value = desired_divisor / iclk_pi_range;
3956 pi_value = desired_divisor % iclk_pi_range;
3957
3958 auxdiv = 0;
3959 divsel = msb_divisor_value - 2;
3960 phaseinc = pi_value;
3961 }
3962
3963 /* This should not happen with any sane values */
3964 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3965 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3966 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3967 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3968
3969 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3970 clock,
e615efe4
ED		 3971 auxdiv,
3972 divsel,
3973 phasedir,
3974 phaseinc);
3975
3976 /* Program SSCDIVINTPHASE6 */
988d6ee8 3977 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3978 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3979 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3980 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3981 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3982 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3983 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3984 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3985
3986 /* Program SSCAUXDIV */
988d6ee8 3987 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3988 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3989 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3990 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3991
3992 /* Enable modulator and associated divider */
988d6ee8 3993 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3994 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3995 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3996
3997 /* Wait for initialization time */
3998 udelay(24);
3999
4000 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4001
a580516d 4002 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4003}
4004
275f01b2
DV		 4005static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4006 enum pipe pch_transcoder)
4007{
4008 struct drm_device *dev = crtc->base.dev;
4009 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4010 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4011
4012 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4013 I915_READ(HTOTAL(cpu_transcoder)));
4014 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4015 I915_READ(HBLANK(cpu_transcoder)));
4016 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4017 I915_READ(HSYNC(cpu_transcoder)));
4018
4019 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4020 I915_READ(VTOTAL(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4022 I915_READ(VBLANK(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4024 I915_READ(VSYNC(cpu_transcoder)));
4025 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4026 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4027}
4028
003632d9 4029static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4030{
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 uint32_t temp;
4033
4034 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4035 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4036 return;
4037
4038 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4039 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4040
003632d9
ACO		 4041 temp &= ~FDI_BC_BIFURCATION_SELECT;
4042 if (enable)
4043 temp |= FDI_BC_BIFURCATION_SELECT;
4044
4045 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4046 I915_WRITE(SOUTH_CHICKEN1, temp);
4047 POSTING_READ(SOUTH_CHICKEN1);
4048}
4049
4050static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4051{
4052 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4053
4054 switch (intel_crtc->pipe) {
4055 case PIPE_A:
4056 break;
4057 case PIPE_B:
6e3c9717 4058 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4059 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4060 else
003632d9 4061 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4062
4063 break;
4064 case PIPE_C:
003632d9 4065 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4066
4067 break;
4068 default:
4069 BUG();
4070 }
4071}
4072
f67a559d
JB		 4073/*
4074 * Enable PCH resources required for PCH ports:
4075 * - PCH PLLs
4076 * - FDI training & RX/TX
4077 * - update transcoder timings
4078 * - DP transcoding bits
4079 * - transcoder
4080 */
4081static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4082{
4083 struct drm_device *dev = crtc->dev;
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4086 int pipe = intel_crtc->pipe;
ee7b9f93 4087 u32 reg, temp;
2c07245f 4088
ab9412ba 4089 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4090
1fbc0d78
DV		 4091 if (IS_IVYBRIDGE(dev))
4092 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4093
cd986abb
DV		 4094 /* Write the TU size bits before fdi link training, so that error
4095 * detection works. */
4096 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4097 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4098
c98e9dcf 4099 /* For PCH output, training FDI link */
674cf967 4100 dev_priv->display.fdi_link_train(crtc);
2c07245f 4101
3ad8a208
DV		 4102 /* We need to program the right clock selection before writing the pixel
4103 * mutliplier into the DPLL. */
303b81e0 4104 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4105 u32 sel;
4b645f14 4106
c98e9dcf 4107 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4108 temp |= TRANS_DPLL_ENABLE(pipe);
4109 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4110 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4111 temp |= sel;
4112 else
4113 temp &= ~sel;
c98e9dcf 4114 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4115 }
5eddb70b 4116
3ad8a208
DV		 4117 /* XXX: pch pll's can be enabled any time before we enable the PCH
4118 * transcoder, and we actually should do this to not upset any PCH
4119 * transcoder that already use the clock when we share it.
4120 *
4121 * Note that enable_shared_dpll tries to do the right thing, but
4122 * get_shared_dpll unconditionally resets the pll - we need that to have
4123 * the right LVDS enable sequence. */
85b3894f 4124 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4125
d9b6cb56
JB		 4126 /* set transcoder timing, panel must allow it */
4127 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4128 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4129
303b81e0 4130 intel_fdi_normal_train(crtc);
5e84e1a4 4131
c98e9dcf 4132 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4133 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4134 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4135 reg = TRANS_DP_CTL(pipe);
4136 temp = I915_READ(reg);
4137 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4138 TRANS_DP_SYNC_MASK |
4139 TRANS_DP_BPC_MASK);
e3ef4479 4140 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4141 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4142
4143 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4144 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4145 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4146 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4147
4148 switch (intel_trans_dp_port_sel(crtc)) {
4149 case PCH_DP_B:
5eddb70b 4150 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4151 break;
4152 case PCH_DP_C:
5eddb70b 4153 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4154 break;
4155 case PCH_DP_D:
5eddb70b 4156 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4157 break;
4158 default:
e95d41e1 4159 BUG();
32f9d658 4160 }
2c07245f 4161
5eddb70b 4162 I915_WRITE(reg, temp);
6be4a607 4163 }
b52eb4dc 4164
b8a4f404 4165 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4166}
4167
1507e5bd
PZ		 4168static void lpt_pch_enable(struct drm_crtc *crtc)
4169{
4170 struct drm_device *dev = crtc->dev;
4171 struct drm_i915_private *dev_priv = dev->dev_private;
4172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4173 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4174
ab9412ba 4175 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4176
8c52b5e8 4177 lpt_program_iclkip(crtc);
1507e5bd 4178
0540e488 4179 /* Set transcoder timing. */
275f01b2 4180 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4181
937bb610 4182 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4183}
4184
190f68c5
ACO		 4185struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4186 struct intel_crtc_state *crtc_state)
ee7b9f93 4187{
e2b78267 4188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4189 struct intel_shared_dpll *pll;
e2b78267 4190 enum intel_dpll_id i;
ee7b9f93 4191
98b6bd99
DV		 4192 if (HAS_PCH_IBX(dev_priv->dev)) {
4193 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4194 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4195 pll = &dev_priv->shared_dplls[i];
98b6bd99 4196
46edb027
DV		 4197 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4198 crtc->base.base.id, pll->name);
98b6bd99 4199
8bd31e67 4200 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4201
98b6bd99
DV		 4202 goto found;
4203 }
4204
bcddf610
S		 4205 if (IS_BROXTON(dev_priv->dev)) {
4206 /* PLL is attached to port in bxt */
4207 struct intel_encoder *encoder;
4208 struct intel_digital_port *intel_dig_port;
4209
4210 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4211 if (WARN_ON(!encoder))
4212 return NULL;
4213
4214 intel_dig_port = enc_to_dig_port(&encoder->base);
4215 /* 1:1 mapping between ports and PLLs */
4216 i = (enum intel_dpll_id)intel_dig_port->port;
4217 pll = &dev_priv->shared_dplls[i];
4218 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4219 crtc->base.base.id, pll->name);
4220 WARN_ON(pll->new_config->crtc_mask);
4221
4222 goto found;
4223 }
4224
e72f9fbf
DV		 4225 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4226 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4227
4228 /* Only want to check enabled timings first */
8bd31e67 4229 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4230 continue;
4231
190f68c5 4232 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4233 &pll->new_config->hw_state,
4234 sizeof(pll->new_config->hw_state)) == 0) {
4235 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4236 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4237 pll->new_config->crtc_mask,
4238 pll->active);
ee7b9f93
JB		 4239 goto found;
4240 }
4241 }
4242
4243 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
8bd31e67 4246 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4247 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4248 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4249 goto found;
4250 }
4251 }
4252
4253 return NULL;
4254
4255found:
8bd31e67 4256 if (pll->new_config->crtc_mask == 0)
190f68c5 4257 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4258
190f68c5 4259 crtc_state->shared_dpll = i;
46edb027
DV		 4260 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4261 pipe_name(crtc->pipe));
ee7b9f93 4262
8bd31e67 4263 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4264
ee7b9f93
JB		 4265 return pll;
4266}
4267
8bd31e67
ACO		 4268/**
4269 * intel_shared_dpll_start_config - start a new PLL staged config
4270 * @dev_priv: DRM device
4271 * @clear_pipes: mask of pipes that will have their PLLs freed
4272 *
4273 * Starts a new PLL staged config, copying the current config but
4274 * releasing the references of pipes specified in clear_pipes.
4275 */
4276static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4277 unsigned clear_pipes)
4278{
4279 struct intel_shared_dpll *pll;
4280 enum intel_dpll_id i;
4281
4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
4284
4285 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4286 GFP_KERNEL);
4287 if (!pll->new_config)
4288 goto cleanup;
4289
4290 pll->new_config->crtc_mask &= ~clear_pipes;
4291 }
4292
4293 return 0;
4294
4295cleanup:
4296 while (--i >= 0) {
4297 pll = &dev_priv->shared_dplls[i];
f354d733 4298 kfree(pll->new_config);
8bd31e67
ACO		 4299 pll->new_config = NULL;
4300 }
4301
4302 return -ENOMEM;
4303}
4304
4305static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4306{
4307 struct intel_shared_dpll *pll;
4308 enum intel_dpll_id i;
4309
4310 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4311 pll = &dev_priv->shared_dplls[i];
4312
4313 WARN_ON(pll->new_config == &pll->config);
4314
4315 pll->config = *pll->new_config;
4316 kfree(pll->new_config);
4317 pll->new_config = NULL;
4318 }
4319}
4320
4321static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4322{
4323 struct intel_shared_dpll *pll;
4324 enum intel_dpll_id i;
4325
4326 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4327 pll = &dev_priv->shared_dplls[i];
4328
4329 WARN_ON(pll->new_config == &pll->config);
4330
4331 kfree(pll->new_config);
4332 pll->new_config = NULL;
4333 }
4334}
4335
a1520318 4336static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4337{
4338 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4339 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4340 u32 temp;
4341
4342 temp = I915_READ(dslreg);
4343 udelay(500);
4344 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4345 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4346 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4347 }
4348}
4349
a1b2278e
CK		 4350/**
4351 * skl_update_scaler_users - Stages update to crtc's scaler state
4352 * @intel_crtc: crtc
4353 * @crtc_state: crtc_state
4354 * @plane: plane (NULL indicates crtc is requesting update)
4355 * @plane_state: plane's state
4356 * @force_detach: request unconditional detachment of scaler
4357 *
4358 * This function updates scaler state for requested plane or crtc.
4359 * To request scaler usage update for a plane, caller shall pass plane pointer.
4360 * To request scaler usage update for crtc, caller shall pass plane pointer
4361 * as NULL.
4362 *
4363 * Return
4364 * 0 - scaler_usage updated successfully
4365 * error - requested scaling cannot be supported or other error condition
4366 */
4367int
4368skl_update_scaler_users(
4369 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4370 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4371 int force_detach)
4372{
4373 int need_scaling;
4374 int idx;
4375 int src_w, src_h, dst_w, dst_h;
4376 int *scaler_id;
4377 struct drm_framebuffer *fb;
4378 struct intel_crtc_scaler_state *scaler_state;
6156a456 4379 unsigned int rotation;
a1b2278e
CK		 4380
4381 if (!intel_crtc || !crtc_state)
4382 return 0;
4383
4384 scaler_state = &crtc_state->scaler_state;
4385
4386 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4387 fb = intel_plane ? plane_state->base.fb : NULL;
4388
4389 if (intel_plane) {
4390 src_w = drm_rect_width(&plane_state->src) >> 16;
4391 src_h = drm_rect_height(&plane_state->src) >> 16;
4392 dst_w = drm_rect_width(&plane_state->dst);
4393 dst_h = drm_rect_height(&plane_state->dst);
4394 scaler_id = &plane_state->scaler_id;
6156a456 4395 rotation = plane_state->base.rotation;
a1b2278e
CK		 4396 } else {
4397 struct drm_display_mode *adjusted_mode =
4398 &crtc_state->base.adjusted_mode;
4399 src_w = crtc_state->pipe_src_w;
4400 src_h = crtc_state->pipe_src_h;
4401 dst_w = adjusted_mode->hdisplay;
4402 dst_h = adjusted_mode->vdisplay;
4403 scaler_id = &scaler_state->scaler_id;
6156a456 4404 rotation = DRM_ROTATE_0;
a1b2278e 4405 }
6156a456
CK		 4406
4407 need_scaling = intel_rotation_90_or_270(rotation) ?
4408 (src_h != dst_w || src_w != dst_h):
4409 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4410
4411 /*
4412 * if plane is being disabled or scaler is no more required or force detach
4413 * - free scaler binded to this plane/crtc
4414 * - in order to do this, update crtc->scaler_usage
4415 *
4416 * Here scaler state in crtc_state is set free so that
4417 * scaler can be assigned to other user. Actual register
4418 * update to free the scaler is done in plane/panel-fit programming.
4419 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4420 */
4421 if (force_detach || !need_scaling || (intel_plane &&
4422 (!fb || !plane_state->visible))) {
4423 if (*scaler_id >= 0) {
4424 scaler_state->scaler_users &= ~(1 << idx);
4425 scaler_state->scalers[*scaler_id].in_use = 0;
4426
4427 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4428 "crtc_state = %p scaler_users = 0x%x\n",
4429 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4430 intel_plane ? intel_plane->base.base.id :
4431 intel_crtc->base.base.id, crtc_state,
4432 scaler_state->scaler_users);
4433 *scaler_id = -1;
4434 }
4435 return 0;
4436 }
4437
4438 /* range checks */
4439 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4440 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4441
4442 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4443 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4444 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4445 "size is out of scaler range\n",
4446 intel_plane ? "PLANE" : "CRTC",
4447 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4448 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4449 return -EINVAL;
4450 }
4451
4452 /* check colorkey */
225c228a
CK		 4453 if (WARN_ON(intel_plane &&
4454 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4455 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4456 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4457 return -EINVAL;
4458 }
4459
4460 /* Check src format */
4461 if (intel_plane) {
4462 switch (fb->pixel_format) {
4463 case DRM_FORMAT_RGB565:
4464 case DRM_FORMAT_XBGR8888:
4465 case DRM_FORMAT_XRGB8888:
4466 case DRM_FORMAT_ABGR8888:
4467 case DRM_FORMAT_ARGB8888:
4468 case DRM_FORMAT_XRGB2101010:
a1b2278e 4469 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4470 case DRM_FORMAT_YUYV:
4471 case DRM_FORMAT_YVYU:
4472 case DRM_FORMAT_UYVY:
4473 case DRM_FORMAT_VYUY:
4474 break;
4475 default:
4476 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4477 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4478 return -EINVAL;
4479 }
4480 }
4481
4482 /* mark this plane as a scaler user in crtc_state */
4483 scaler_state->scaler_users |= (1 << idx);
4484 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4485 "crtc_state = %p scaler_users = 0x%x\n",
4486 intel_plane ? "PLANE" : "CRTC",
4487 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4488 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4489 return 0;
4490}
4491
4492static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4493{
4494 struct drm_device *dev = crtc->base.dev;
4495 struct drm_i915_private *dev_priv = dev->dev_private;
4496 int pipe = crtc->pipe;
a1b2278e
CK		 4497 struct intel_crtc_scaler_state *scaler_state =
4498 &crtc->config->scaler_state;
4499
4500 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4501
4502 /* To update pfit, first update scaler state */
4503 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4504 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4505 skl_detach_scalers(crtc);
4506 if (!enable)
4507 return;
bd2e244f 4508
6e3c9717 4509 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4510 int id;
4511
4512 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4513 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4514 return;
4515 }
4516
4517 id = scaler_state->scaler_id;
4518 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4519 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4520 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4521 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4522
4523 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4524 }
4525}
4526
b074cec8
JB		 4527static void ironlake_pfit_enable(struct intel_crtc *crtc)
4528{
4529 struct drm_device *dev = crtc->base.dev;
4530 struct drm_i915_private *dev_priv = dev->dev_private;
4531 int pipe = crtc->pipe;
4532
6e3c9717 4533 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4534 /* Force use of hard-coded filter coefficients
4535 * as some pre-programmed values are broken,
4536 * e.g. x201.
4537 */
4538 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4539 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4540 PF_PIPE_SEL_IVB(pipe));
4541 else
4542 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4543 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4544 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4545 }
4546}
4547
4a3b8769 4548static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4549{
4550 struct drm_device *dev = crtc->dev;
4551 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4552 struct drm_plane *plane;
bb53d4ae
VS		 4553 struct intel_plane *intel_plane;
4554
af2b653b
MR		 4555 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4556 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4557 if (intel_plane->pipe == pipe)
4558 intel_plane_restore(&intel_plane->base);
af2b653b 4559 }
bb53d4ae
VS		 4560}
4561
20bc8673 4562void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4563{
cea165c3
VS		 4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4566
6e3c9717 4567 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4568 return;
4569
cea165c3
VS		 4570 /* We can only enable IPS after we enable a plane and wait for a vblank */
4571 intel_wait_for_vblank(dev, crtc->pipe);
4572
d77e4531 4573 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4574 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4575 mutex_lock(&dev_priv->rps.hw_lock);
4576 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578 /* Quoting Art Runyan: "its not safe to expect any particular
4579 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4580 * mailbox." Moreover, the mailbox may return a bogus state,
4581 * so we need to just enable it and continue on.
2a114cc1
BW		 4582 */
4583 } else {
4584 I915_WRITE(IPS_CTL, IPS_ENABLE);
4585 /* The bit only becomes 1 in the next vblank, so this wait here
4586 * is essentially intel_wait_for_vblank. If we don't have this
4587 * and don't wait for vblanks until the end of crtc_enable, then
4588 * the HW state readout code will complain that the expected
4589 * IPS_CTL value is not the one we read. */
4590 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4591 DRM_ERROR("Timed out waiting for IPS enable\n");
4592 }
d77e4531
PZ		 4593}
4594
20bc8673 4595void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4596{
4597 struct drm_device *dev = crtc->base.dev;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599
6e3c9717 4600 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4601 return;
4602
4603 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4604 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4605 mutex_lock(&dev_priv->rps.hw_lock);
4606 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4607 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4608 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4609 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4610 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4611 } else {
2a114cc1 4612 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4613 POSTING_READ(IPS_CTL);
4614 }
d77e4531
PZ		 4615
4616 /* We need to wait for a vblank before we can disable the plane. */
4617 intel_wait_for_vblank(dev, crtc->pipe);
4618}
4619
4620/** Loads the palette/gamma unit for the CRTC with the prepared values */
4621static void intel_crtc_load_lut(struct drm_crtc *crtc)
4622{
4623 struct drm_device *dev = crtc->dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 enum pipe pipe = intel_crtc->pipe;
4627 int palreg = PALETTE(pipe);
4628 int i;
4629 bool reenable_ips = false;
4630
4631 /* The clocks have to be on to load the palette. */
53d9f4e9 4632 if (!crtc->state->active)
d77e4531
PZ		 4633 return;
4634
50360403 4635 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4636 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4637 assert_dsi_pll_enabled(dev_priv);
4638 else
4639 assert_pll_enabled(dev_priv, pipe);
4640 }
4641
4642 /* use legacy palette for Ironlake */
7a1db49a 4643 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4644 palreg = LGC_PALETTE(pipe);
4645
4646 /* Workaround : Do not read or write the pipe palette/gamma data while
4647 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4648 */
6e3c9717 4649 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4650 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4651 GAMMA_MODE_MODE_SPLIT)) {
4652 hsw_disable_ips(intel_crtc);
4653 reenable_ips = true;
4654 }
4655
4656 for (i = 0; i < 256; i++) {
4657 I915_WRITE(palreg + 4 * i,
4658 (intel_crtc->lut_r[i] << 16) |
4659 (intel_crtc->lut_g[i] << 8) |
4660 intel_crtc->lut_b[i]);
4661 }
4662
4663 if (reenable_ips)
4664 hsw_enable_ips(intel_crtc);
4665}
4666
7cac945f 4667static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4668{
7cac945f 4669 if (intel_crtc->overlay) {
d3eedb1a
VS		 4670 struct drm_device *dev = intel_crtc->base.dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672
4673 mutex_lock(&dev->struct_mutex);
4674 dev_priv->mm.interruptible = false;
4675 (void) intel_overlay_switch_off(intel_crtc->overlay);
4676 dev_priv->mm.interruptible = true;
4677 mutex_unlock(&dev->struct_mutex);
4678 }
4679
4680 /* Let userspace switch the overlay on again. In most cases userspace
4681 * has to recompute where to put it anyway.
4682 */
4683}
4684
87d4300a
ML		 4685/**
4686 * intel_post_enable_primary - Perform operations after enabling primary plane
4687 * @crtc: the CRTC whose primary plane was just enabled
4688 *
4689 * Performs potentially sleeping operations that must be done after the primary
4690 * plane is enabled, such as updating FBC and IPS. Note that this may be
4691 * called due to an explicit primary plane update, or due to an implicit
4692 * re-enable that is caused when a sprite plane is updated to no longer
4693 * completely hide the primary plane.
4694 */
4695static void
4696intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4697{
4698 struct drm_device *dev = crtc->dev;
87d4300a 4699 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701 int pipe = intel_crtc->pipe;
a5c4d7bc 4702
87d4300a
ML		 4703 /*
4704 * BDW signals flip done immediately if the plane
4705 * is disabled, even if the plane enable is already
4706 * armed to occur at the next vblank :(
4707 */
4708 if (IS_BROADWELL(dev))
4709 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4710
87d4300a
ML		 4711 /*
4712 * FIXME IPS should be fine as long as one plane is
4713 * enabled, but in practice it seems to have problems
4714 * when going from primary only to sprite only and vice
4715 * versa.
4716 */
a5c4d7bc
VS		 4717 hsw_enable_ips(intel_crtc);
4718
4719 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4720 intel_fbc_update(dev);
a5c4d7bc 4721 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4722
4723 /*
87d4300a
ML		 4724 * Gen2 reports pipe underruns whenever all planes are disabled.
4725 * So don't enable underrun reporting before at least some planes
4726 * are enabled.
4727 * FIXME: Need to fix the logic to work when we turn off all planes
4728 * but leave the pipe running.
f99d7069 4729 */
87d4300a
ML		 4730 if (IS_GEN2(dev))
4731 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4732
4733 /* Underruns don't raise interrupts, so check manually. */
4734 if (HAS_GMCH_DISPLAY(dev))
4735 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4736}
4737
87d4300a
ML		 4738/**
4739 * intel_pre_disable_primary - Perform operations before disabling primary plane
4740 * @crtc: the CRTC whose primary plane is to be disabled
4741 *
4742 * Performs potentially sleeping operations that must be done before the
4743 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4744 * be called due to an explicit primary plane update, or due to an implicit
4745 * disable that is caused when a sprite plane completely hides the primary
4746 * plane.
4747 */
4748static void
4749intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4750{
4751 struct drm_device *dev = crtc->dev;
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4754 int pipe = intel_crtc->pipe;
a5c4d7bc 4755
87d4300a
ML		 4756 /*
4757 * Gen2 reports pipe underruns whenever all planes are disabled.
4758 * So diasble underrun reporting before all the planes get disabled.
4759 * FIXME: Need to fix the logic to work when we turn off all planes
4760 * but leave the pipe running.
4761 */
4762 if (IS_GEN2(dev))
4763 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4764
87d4300a
ML		 4765 /*
4766 * Vblank time updates from the shadow to live plane control register
4767 * are blocked if the memory self-refresh mode is active at that
4768 * moment. So to make sure the plane gets truly disabled, disable
4769 * first the self-refresh mode. The self-refresh enable bit in turn
4770 * will be checked/applied by the HW only at the next frame start
4771 * event which is after the vblank start event, so we need to have a
4772 * wait-for-vblank between disabling the plane and the pipe.
4773 */
4774 if (HAS_GMCH_DISPLAY(dev))
4775 intel_set_memory_cxsr(dev_priv, false);
4776
4777 mutex_lock(&dev->struct_mutex);
e35fef21 4778 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4779 intel_fbc_disable(dev);
87d4300a 4780 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4781
87d4300a
ML		 4782 /*
4783 * FIXME IPS should be fine as long as one plane is
4784 * enabled, but in practice it seems to have problems
4785 * when going from primary only to sprite only and vice
4786 * versa.
4787 */
a5c4d7bc 4788 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4789}
4790
4791static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4792{
2d847d45
RV		 4793 struct drm_device *dev = crtc->dev;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4795 int pipe = intel_crtc->pipe;
4796
87d4300a
ML		 4797 intel_enable_primary_hw_plane(crtc->primary, crtc);
4798 intel_enable_sprite_planes(crtc);
4799 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4800
4801 intel_post_enable_primary(crtc);
2d847d45
RV		 4802
4803 /*
4804 * FIXME: Once we grow proper nuclear flip support out of this we need
4805 * to compute the mask of flip planes precisely. For the time being
4806 * consider this a flip to a NULL plane.
4807 */
4808 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4809}
4810
4811static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4812{
4813 struct drm_device *dev = crtc->dev;
4814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815 struct intel_plane *intel_plane;
4816 int pipe = intel_crtc->pipe;
4817
4818 intel_crtc_wait_for_pending_flips(crtc);
4819
4820 intel_pre_disable_primary(crtc);
a5c4d7bc 4821
7cac945f 4822 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4823 for_each_intel_plane(dev, intel_plane) {
4824 if (intel_plane->pipe == pipe) {
4825 struct drm_crtc *from = intel_plane->base.crtc;
4826
4827 intel_plane->disable_plane(&intel_plane->base,
4828 from ?: crtc, true);
4829 }
4830 }
f98551ae 4831
f99d7069
DV		 4832 /*
4833 * FIXME: Once we grow proper nuclear flip support out of this we need
4834 * to compute the mask of flip planes precisely. For the time being
4835 * consider this a flip to a NULL plane.
4836 */
4837 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4838}
4839
f67a559d
JB		 4840static void ironlake_crtc_enable(struct drm_crtc *crtc)
4841{
4842 struct drm_device *dev = crtc->dev;
4843 struct drm_i915_private *dev_priv = dev->dev_private;
4844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4845 struct intel_encoder *encoder;
f67a559d 4846 int pipe = intel_crtc->pipe;
f67a559d 4847
53d9f4e9 4848 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4849 return;
4850
6e3c9717 4851 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4852 intel_prepare_shared_dpll(intel_crtc);
4853
6e3c9717 4854 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4855 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4856
4857 intel_set_pipe_timings(intel_crtc);
4858
6e3c9717 4859 if (intel_crtc->config->has_pch_encoder) {
29407aab 4860 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4861 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4862 }
4863
4864 ironlake_set_pipeconf(crtc);
4865
f67a559d 4866 intel_crtc->active = true;
8664281b 4867
a72e4c9f
DV		 4868 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4869 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4870
f6736a1a 4871 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4872 if (encoder->pre_enable)
4873 encoder->pre_enable(encoder);
f67a559d 4874
6e3c9717 4875 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4876 /* Note: FDI PLL enabling _must_ be done before we enable the
4877 * cpu pipes, hence this is separate from all the other fdi/pch
4878 * enabling. */
88cefb6c 4879 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4880 } else {
4881 assert_fdi_tx_disabled(dev_priv, pipe);
4882 assert_fdi_rx_disabled(dev_priv, pipe);
4883 }
f67a559d 4884
b074cec8 4885 ironlake_pfit_enable(intel_crtc);
f67a559d 4886
9c54c0dd
JB		 4887 /*
4888 * On ILK+ LUT must be loaded before the pipe is running but with
4889 * clocks enabled
4890 */
4891 intel_crtc_load_lut(crtc);
4892
f37fcc2a 4893 intel_update_watermarks(crtc);
e1fdc473 4894 intel_enable_pipe(intel_crtc);
f67a559d 4895
6e3c9717 4896 if (intel_crtc->config->has_pch_encoder)
f67a559d 4897 ironlake_pch_enable(crtc);
c98e9dcf 4898
f9b61ff6
DV		 4899 assert_vblank_disabled(crtc);
4900 drm_crtc_vblank_on(crtc);
4901
fa5c73b1
DV		 4902 for_each_encoder_on_crtc(dev, crtc, encoder)
4903 encoder->enable(encoder);
61b77ddd
DV		 4904
4905 if (HAS_PCH_CPT(dev))
a1520318 4906 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4907}
4908
42db64ef
PZ		 4909/* IPS only exists on ULT machines and is tied to pipe A. */
4910static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4911{
f5adf94e 4912 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4913}
4914
e4916946
PZ		 4915/*
4916 * This implements the workaround described in the "notes" section of the mode
4917 * set sequence documentation. When going from no pipes or single pipe to
4918 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4919 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4920 */
4921static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4922{
4923 struct drm_device *dev = crtc->base.dev;
4924 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4925
4926 /* We want to get the other_active_crtc only if there's only 1 other
4927 * active crtc. */
d3fcc808 4928 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4929 if (!crtc_it->active || crtc_it == crtc)
4930 continue;
4931
4932 if (other_active_crtc)
4933 return;
4934
4935 other_active_crtc = crtc_it;
4936 }
4937 if (!other_active_crtc)
4938 return;
4939
4940 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4941 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4942}
4943
4f771f10
PZ		 4944static void haswell_crtc_enable(struct drm_crtc *crtc)
4945{
4946 struct drm_device *dev = crtc->dev;
4947 struct drm_i915_private *dev_priv = dev->dev_private;
4948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949 struct intel_encoder *encoder;
4950 int pipe = intel_crtc->pipe;
4f771f10 4951
53d9f4e9 4952 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4953 return;
4954
df8ad70c
DV		 4955 if (intel_crtc_to_shared_dpll(intel_crtc))
4956 intel_enable_shared_dpll(intel_crtc);
4957
6e3c9717 4958 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4959 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4960
4961 intel_set_pipe_timings(intel_crtc);
4962
6e3c9717
ACO		 4963 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4964 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4965 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4966 }
4967
6e3c9717 4968 if (intel_crtc->config->has_pch_encoder) {
229fca97 4969 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4970 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4971 }
4972
4973 haswell_set_pipeconf(crtc);
4974
4975 intel_set_pipe_csc(crtc);
4976
4f771f10 4977 intel_crtc->active = true;
8664281b 4978
a72e4c9f 4979 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4980 for_each_encoder_on_crtc(dev, crtc, encoder)
4981 if (encoder->pre_enable)
4982 encoder->pre_enable(encoder);
4983
6e3c9717 4984 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4985 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4986 true);
4fe9467d
ID		 4987 dev_priv->display.fdi_link_train(crtc);
4988 }
4989
1f544388 4990 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4991
ff6d9f55 4992 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4993 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4994 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4995 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4996 else
4997 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4998
4999 /*
5000 * On ILK+ LUT must be loaded before the pipe is running but with
5001 * clocks enabled
5002 */
5003 intel_crtc_load_lut(crtc);
5004
1f544388 5005 intel_ddi_set_pipe_settings(crtc);
8228c251 5006 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5007
f37fcc2a 5008 intel_update_watermarks(crtc);
e1fdc473 5009 intel_enable_pipe(intel_crtc);
42db64ef 5010
6e3c9717 5011 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5012 lpt_pch_enable(crtc);
4f771f10 5013
6e3c9717 5014 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5015 intel_ddi_set_vc_payload_alloc(crtc, true);
5016
f9b61ff6
DV		 5017 assert_vblank_disabled(crtc);
5018 drm_crtc_vblank_on(crtc);
5019
8807e55b 5020 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5021 encoder->enable(encoder);
8807e55b
JN		 5022 intel_opregion_notify_encoder(encoder, true);
5023 }
4f771f10 5024
e4916946
PZ		 5025 /* If we change the relative order between pipe/planes enabling, we need
5026 * to change the workaround. */
5027 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5028}
5029
3f8dce3a
DV		 5030static void ironlake_pfit_disable(struct intel_crtc *crtc)
5031{
5032 struct drm_device *dev = crtc->base.dev;
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 int pipe = crtc->pipe;
5035
5036 /* To avoid upsetting the power well on haswell only disable the pfit if
5037 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5038 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5039 I915_WRITE(PF_CTL(pipe), 0);
5040 I915_WRITE(PF_WIN_POS(pipe), 0);
5041 I915_WRITE(PF_WIN_SZ(pipe), 0);
5042 }
5043}
5044
6be4a607
JB		 5045static void ironlake_crtc_disable(struct drm_crtc *crtc)
5046{
5047 struct drm_device *dev = crtc->dev;
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5050 struct intel_encoder *encoder;
6be4a607 5051 int pipe = intel_crtc->pipe;
5eddb70b 5052 u32 reg, temp;
b52eb4dc 5053
53d9f4e9 5054 if (WARN_ON(!intel_crtc->active))
f7abfe8b
CW		 5055 return;
5056
ea9d758d
DV		 5057 for_each_encoder_on_crtc(dev, crtc, encoder)
5058 encoder->disable(encoder);
5059
f9b61ff6
DV		 5060 drm_crtc_vblank_off(crtc);
5061 assert_vblank_disabled(crtc);
5062
6e3c9717 5063 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5064 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5065
575f7ab7 5066 intel_disable_pipe(intel_crtc);
32f9d658 5067
3f8dce3a 5068 ironlake_pfit_disable(intel_crtc);
2c07245f 5069
5a74f70a
VS		 5070 if (intel_crtc->config->has_pch_encoder)
5071 ironlake_fdi_disable(crtc);
5072
bf49ec8c
DV		 5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 if (encoder->post_disable)
5075 encoder->post_disable(encoder);
2c07245f 5076
6e3c9717 5077 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5078 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5079
d925c59a
DV		 5080 if (HAS_PCH_CPT(dev)) {
5081 /* disable TRANS_DP_CTL */
5082 reg = TRANS_DP_CTL(pipe);
5083 temp = I915_READ(reg);
5084 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5085 TRANS_DP_PORT_SEL_MASK);
5086 temp |= TRANS_DP_PORT_SEL_NONE;
5087 I915_WRITE(reg, temp);
5088
5089 /* disable DPLL_SEL */
5090 temp = I915_READ(PCH_DPLL_SEL);
11887397 5091 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5092 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5093 }
e3421a18 5094
d925c59a 5095 /* disable PCH DPLL */
e72f9fbf 5096 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5097
d925c59a
DV		 5098 ironlake_fdi_pll_disable(intel_crtc);
5099 }
6b383a7f 5100
f7abfe8b 5101 intel_crtc->active = false;
46ba614c 5102 intel_update_watermarks(crtc);
d1ebd816
BW		 5103
5104 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5105 intel_fbc_update(dev);
d1ebd816 5106 mutex_unlock(&dev->struct_mutex);
6be4a607 5107}
1b3c7a47 5108
4f771f10 5109static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5110{
4f771f10
PZ		 5111 struct drm_device *dev = crtc->dev;
5112 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5114 struct intel_encoder *encoder;
6e3c9717 5115 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5116
53d9f4e9 5117 if (WARN_ON(!intel_crtc->active))
4f771f10
PZ		 5118 return;
5119
8807e55b
JN		 5120 for_each_encoder_on_crtc(dev, crtc, encoder) {
5121 intel_opregion_notify_encoder(encoder, false);
4f771f10 5122 encoder->disable(encoder);
8807e55b 5123 }
4f771f10 5124
f9b61ff6
DV		 5125 drm_crtc_vblank_off(crtc);
5126 assert_vblank_disabled(crtc);
5127
6e3c9717 5128 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5129 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5130 false);
575f7ab7 5131 intel_disable_pipe(intel_crtc);
4f771f10 5132
6e3c9717 5133 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5134 intel_ddi_set_vc_payload_alloc(crtc, false);
5135
ad80a810 5136 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5137
ff6d9f55 5138 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5139 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5140 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5141 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5142 else
5143 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5144
1f544388 5145 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5146
6e3c9717 5147 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5148 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5149 intel_ddi_fdi_disable(crtc);
83616634 5150 }
4f771f10 5151
97b040aa
ID		 5152 for_each_encoder_on_crtc(dev, crtc, encoder)
5153 if (encoder->post_disable)
5154 encoder->post_disable(encoder);
5155
4f771f10 5156 intel_crtc->active = false;
46ba614c 5157 intel_update_watermarks(crtc);
4f771f10
PZ		 5158
5159 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5160 intel_fbc_update(dev);
4f771f10 5161 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5162
5163 if (intel_crtc_to_shared_dpll(intel_crtc))
5164 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5165}
5166
2dd24552
JB		 5167static void i9xx_pfit_enable(struct intel_crtc *crtc)
5168{
5169 struct drm_device *dev = crtc->base.dev;
5170 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5171 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5172
681a8504 5173 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5174 return;
5175
2dd24552 5176 /*
c0b03411
DV		 5177 * The panel fitter should only be adjusted whilst the pipe is disabled,
5178 * according to register description and PRM.
2dd24552 5179 */
c0b03411
DV		 5180 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5181 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5182
b074cec8
JB		 5183 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5184 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5185
5186 /* Border color in case we don't scale up to the full screen. Black by
5187 * default, change to something else for debugging. */
5188 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5189}
5190
d05410f9
DA		 5191static enum intel_display_power_domain port_to_power_domain(enum port port)
5192{
5193 switch (port) {
5194 case PORT_A:
5195 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5196 case PORT_B:
5197 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5198 case PORT_C:
5199 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5200 case PORT_D:
5201 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5202 default:
5203 WARN_ON_ONCE(1);
5204 return POWER_DOMAIN_PORT_OTHER;
5205 }
5206}
5207
77d22dca
ID		 5208#define for_each_power_domain(domain, mask) \
5209 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5210 if ((1 << (domain)) & (mask))
5211
319be8ae
ID		 5212enum intel_display_power_domain
5213intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5214{
5215 struct drm_device *dev = intel_encoder->base.dev;
5216 struct intel_digital_port *intel_dig_port;
5217
5218 switch (intel_encoder->type) {
5219 case INTEL_OUTPUT_UNKNOWN:
5220 /* Only DDI platforms should ever use this output type */
5221 WARN_ON_ONCE(!HAS_DDI(dev));
5222 case INTEL_OUTPUT_DISPLAYPORT:
5223 case INTEL_OUTPUT_HDMI:
5224 case INTEL_OUTPUT_EDP:
5225 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5226 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5227 case INTEL_OUTPUT_DP_MST:
5228 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5229 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5230 case INTEL_OUTPUT_ANALOG:
5231 return POWER_DOMAIN_PORT_CRT;
5232 case INTEL_OUTPUT_DSI:
5233 return POWER_DOMAIN_PORT_DSI;
5234 default:
5235 return POWER_DOMAIN_PORT_OTHER;
5236 }
5237}
5238
5239static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5240{
319be8ae
ID		 5241 struct drm_device *dev = crtc->dev;
5242 struct intel_encoder *intel_encoder;
5243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5244 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5245 unsigned long mask;
5246 enum transcoder transcoder;
5247
5248 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5249
5250 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5251 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5252 if (intel_crtc->config->pch_pfit.enabled ||
5253 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5254 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5255
319be8ae
ID		 5256 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5257 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5258
77d22dca
ID		 5259 return mask;
5260}
5261
679dacd4 5262static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5263{
679dacd4 5264 struct drm_device *dev = state->dev;
77d22dca
ID		 5265 struct drm_i915_private *dev_priv = dev->dev_private;
5266 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5267 struct intel_crtc *crtc;
5268
5269 /*
5270 * First get all needed power domains, then put all unneeded, to avoid
5271 * any unnecessary toggling of the power wells.
5272 */
d3fcc808 5273 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5274 enum intel_display_power_domain domain;
5275
83d65738 5276 if (!crtc->base.state->enable)
77d22dca
ID		 5277 continue;
5278
319be8ae 5279 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5280
5281 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5282 intel_display_power_get(dev_priv, domain);
5283 }
5284
50f6e502 5285 if (dev_priv->display.modeset_global_resources)
679dacd4 5286 dev_priv->display.modeset_global_resources(state);
50f6e502 5287
d3fcc808 5288 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5289 enum intel_display_power_domain domain;
5290
5291 for_each_power_domain(domain, crtc->enabled_power_domains)
5292 intel_display_power_put(dev_priv, domain);
5293
5294 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5295 }
5296
5297 intel_display_set_init_power(dev_priv, false);
5298}
5299
560a7ae4
DL		 5300static void intel_update_max_cdclk(struct drm_device *dev)
5301{
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303
5304 if (IS_SKYLAKE(dev)) {
5305 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5306
5307 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5308 dev_priv->max_cdclk_freq = 675000;
5309 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5310 dev_priv->max_cdclk_freq = 540000;
5311 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5312 dev_priv->max_cdclk_freq = 450000;
5313 else
5314 dev_priv->max_cdclk_freq = 337500;
5315 } else if (IS_BROADWELL(dev)) {
5316 /*
5317 * FIXME with extra cooling we can allow
5318 * 540 MHz for ULX and 675 Mhz for ULT.
5319 * How can we know if extra cooling is
5320 * available? PCI ID, VTB, something else?
5321 */
5322 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5323 dev_priv->max_cdclk_freq = 450000;
5324 else if (IS_BDW_ULX(dev))
5325 dev_priv->max_cdclk_freq = 450000;
5326 else if (IS_BDW_ULT(dev))
5327 dev_priv->max_cdclk_freq = 540000;
5328 else
5329 dev_priv->max_cdclk_freq = 675000;
5330 } else if (IS_VALLEYVIEW(dev)) {
5331 dev_priv->max_cdclk_freq = 400000;
5332 } else {
5333 /* otherwise assume cdclk is fixed */
5334 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5335 }
5336
5337 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5338 dev_priv->max_cdclk_freq);
5339}
5340
5341static void intel_update_cdclk(struct drm_device *dev)
5342{
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344
5345 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5346 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5347 dev_priv->cdclk_freq);
5348
5349 /*
5350 * Program the gmbus_freq based on the cdclk frequency.
5351 * BSpec erroneously claims we should aim for 4MHz, but
5352 * in fact 1MHz is the correct frequency.
5353 */
5354 if (IS_VALLEYVIEW(dev)) {
5355 /*
5356 * Program the gmbus_freq based on the cdclk frequency.
5357 * BSpec erroneously claims we should aim for 4MHz, but
5358 * in fact 1MHz is the correct frequency.
5359 */
5360 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5361 }
5362
5363 if (dev_priv->max_cdclk_freq == 0)
5364 intel_update_max_cdclk(dev);
5365}
5366
70d0c574 5367static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t divider;
5371 uint32_t ratio;
5372 uint32_t current_freq;
5373 int ret;
5374
5375 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5376 switch (frequency) {
5377 case 144000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5379 ratio = BXT_DE_PLL_RATIO(60);
5380 break;
5381 case 288000:
5382 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5383 ratio = BXT_DE_PLL_RATIO(60);
5384 break;
5385 case 384000:
5386 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5387 ratio = BXT_DE_PLL_RATIO(60);
5388 break;
5389 case 576000:
5390 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5391 ratio = BXT_DE_PLL_RATIO(60);
5392 break;
5393 case 624000:
5394 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5395 ratio = BXT_DE_PLL_RATIO(65);
5396 break;
5397 case 19200:
5398 /*
5399 * Bypass frequency with DE PLL disabled. Init ratio, divider
5400 * to suppress GCC warning.
5401 */
5402 ratio = 0;
5403 divider = 0;
5404 break;
5405 default:
5406 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5407
5408 return;
5409 }
5410
5411 mutex_lock(&dev_priv->rps.hw_lock);
5412 /* Inform power controller of upcoming frequency change */
5413 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5414 0x80000000);
5415 mutex_unlock(&dev_priv->rps.hw_lock);
5416
5417 if (ret) {
5418 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5419 ret, frequency);
5420 return;
5421 }
5422
5423 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5424 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5425 current_freq = current_freq * 500 + 1000;
5426
5427 /*
5428 * DE PLL has to be disabled when
5429 * - setting to 19.2MHz (bypass, PLL isn't used)
5430 * - before setting to 624MHz (PLL needs toggling)
5431 * - before setting to any frequency from 624MHz (PLL needs toggling)
5432 */
5433 if (frequency == 19200 || frequency == 624000 ||
5434 current_freq == 624000) {
5435 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5436 /* Timeout 200us */
5437 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5438 1))
5439 DRM_ERROR("timout waiting for DE PLL unlock\n");
5440 }
5441
5442 if (frequency != 19200) {
5443 uint32_t val;
5444
5445 val = I915_READ(BXT_DE_PLL_CTL);
5446 val &= ~BXT_DE_PLL_RATIO_MASK;
5447 val |= ratio;
5448 I915_WRITE(BXT_DE_PLL_CTL, val);
5449
5450 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5451 /* Timeout 200us */
5452 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5453 DRM_ERROR("timeout waiting for DE PLL lock\n");
5454
5455 val = I915_READ(CDCLK_CTL);
5456 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5457 val |= divider;
5458 /*
5459 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5460 * enable otherwise.
5461 */
5462 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463 if (frequency >= 500000)
5464 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5465
5466 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5467 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5468 val |= (frequency - 1000) / 500;
5469 I915_WRITE(CDCLK_CTL, val);
5470 }
5471
5472 mutex_lock(&dev_priv->rps.hw_lock);
5473 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5474 DIV_ROUND_UP(frequency, 25000));
5475 mutex_unlock(&dev_priv->rps.hw_lock);
5476
5477 if (ret) {
5478 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5479 ret, frequency);
5480 return;
5481 }
5482
a47871bd 5483 intel_update_cdclk(dev);
f8437dd1
VK		 5484}
5485
5486void broxton_init_cdclk(struct drm_device *dev)
5487{
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 uint32_t val;
5490
5491 /*
5492 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5493 * or else the reset will hang because there is no PCH to respond.
5494 * Move the handshake programming to initialization sequence.
5495 * Previously was left up to BIOS.
5496 */
5497 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5498 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5499 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5500
5501 /* Enable PG1 for cdclk */
5502 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5503
5504 /* check if cd clock is enabled */
5505 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5506 DRM_DEBUG_KMS("Display already initialized\n");
5507 return;
5508 }
5509
5510 /*
5511 * FIXME:
5512 * - The initial CDCLK needs to be read from VBT.
5513 * Need to make this change after VBT has changes for BXT.
5514 * - check if setting the max (or any) cdclk freq is really necessary
5515 * here, it belongs to modeset time
5516 */
5517 broxton_set_cdclk(dev, 624000);
5518
5519 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5520 POSTING_READ(DBUF_CTL);
5521
f8437dd1
VK		 5522 udelay(10);
5523
5524 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5525 DRM_ERROR("DBuf power enable timeout!\n");
5526}
5527
5528void broxton_uninit_cdclk(struct drm_device *dev)
5529{
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5533 POSTING_READ(DBUF_CTL);
5534
f8437dd1
VK		 5535 udelay(10);
5536
5537 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5538 DRM_ERROR("DBuf power disable timeout!\n");
5539
5540 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5541 broxton_set_cdclk(dev, 19200);
5542
5543 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5544}
5545
5d96d8af
DL		 5546static const struct skl_cdclk_entry {
5547 unsigned int freq;
5548 unsigned int vco;
5549} skl_cdclk_frequencies[] = {
5550 { .freq = 308570, .vco = 8640 },
5551 { .freq = 337500, .vco = 8100 },
5552 { .freq = 432000, .vco = 8640 },
5553 { .freq = 450000, .vco = 8100 },
5554 { .freq = 540000, .vco = 8100 },
5555 { .freq = 617140, .vco = 8640 },
5556 { .freq = 675000, .vco = 8100 },
5557};
5558
5559static unsigned int skl_cdclk_decimal(unsigned int freq)
5560{
5561 return (freq - 1000) / 500;
5562}
5563
5564static unsigned int skl_cdclk_get_vco(unsigned int freq)
5565{
5566 unsigned int i;
5567
5568 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5569 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5570
5571 if (e->freq == freq)
5572 return e->vco;
5573 }
5574
5575 return 8100;
5576}
5577
5578static void
5579skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5580{
5581 unsigned int min_freq;
5582 u32 val;
5583
5584 /* select the minimum CDCLK before enabling DPLL 0 */
5585 val = I915_READ(CDCLK_CTL);
5586 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5587 val |= CDCLK_FREQ_337_308;
5588
5589 if (required_vco == 8640)
5590 min_freq = 308570;
5591 else
5592 min_freq = 337500;
5593
5594 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5595
5596 I915_WRITE(CDCLK_CTL, val);
5597 POSTING_READ(CDCLK_CTL);
5598
5599 /*
5600 * We always enable DPLL0 with the lowest link rate possible, but still
5601 * taking into account the VCO required to operate the eDP panel at the
5602 * desired frequency. The usual DP link rates operate with a VCO of
5603 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5604 * The modeset code is responsible for the selection of the exact link
5605 * rate later on, with the constraint of choosing a frequency that
5606 * works with required_vco.
5607 */
5608 val = I915_READ(DPLL_CTRL1);
5609
5610 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5611 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5612 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5613 if (required_vco == 8640)
5614 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5615 SKL_DPLL0);
5616 else
5617 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5618 SKL_DPLL0);
5619
5620 I915_WRITE(DPLL_CTRL1, val);
5621 POSTING_READ(DPLL_CTRL1);
5622
5623 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5624
5625 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5626 DRM_ERROR("DPLL0 not locked\n");
5627}
5628
5629static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5630{
5631 int ret;
5632 u32 val;
5633
5634 /* inform PCU we want to change CDCLK */
5635 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5636 mutex_lock(&dev_priv->rps.hw_lock);
5637 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5638 mutex_unlock(&dev_priv->rps.hw_lock);
5639
5640 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5641}
5642
5643static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5644{
5645 unsigned int i;
5646
5647 for (i = 0; i < 15; i++) {
5648 if (skl_cdclk_pcu_ready(dev_priv))
5649 return true;
5650 udelay(10);
5651 }
5652
5653 return false;
5654}
5655
5656static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5657{
560a7ae4 5658 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5659 u32 freq_select, pcu_ack;
5660
5661 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5662
5663 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5664 DRM_ERROR("failed to inform PCU about cdclk change\n");
5665 return;
5666 }
5667
5668 /* set CDCLK_CTL */
5669 switch(freq) {
5670 case 450000:
5671 case 432000:
5672 freq_select = CDCLK_FREQ_450_432;
5673 pcu_ack = 1;
5674 break;
5675 case 540000:
5676 freq_select = CDCLK_FREQ_540;
5677 pcu_ack = 2;
5678 break;
5679 case 308570:
5680 case 337500:
5681 default:
5682 freq_select = CDCLK_FREQ_337_308;
5683 pcu_ack = 0;
5684 break;
5685 case 617140:
5686 case 675000:
5687 freq_select = CDCLK_FREQ_675_617;
5688 pcu_ack = 3;
5689 break;
5690 }
5691
5692 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5693 POSTING_READ(CDCLK_CTL);
5694
5695 /* inform PCU of the change */
5696 mutex_lock(&dev_priv->rps.hw_lock);
5697 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5698 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5699
5700 intel_update_cdclk(dev);
5d96d8af
DL		 5701}
5702
5703void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5704{
5705 /* disable DBUF power */
5706 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5707 POSTING_READ(DBUF_CTL);
5708
5709 udelay(10);
5710
5711 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5712 DRM_ERROR("DBuf power disable timeout\n");
5713
5714 /* disable DPLL0 */
5715 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5716 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5717 DRM_ERROR("Couldn't disable DPLL0\n");
5718
5719 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5720}
5721
5722void skl_init_cdclk(struct drm_i915_private *dev_priv)
5723{
5724 u32 val;
5725 unsigned int required_vco;
5726
5727 /* enable PCH reset handshake */
5728 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5729 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5730
5731 /* enable PG1 and Misc I/O */
5732 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5733
5734 /* DPLL0 already enabed !? */
5735 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5736 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5737 return;
5738 }
5739
5740 /* enable DPLL0 */
5741 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5742 skl_dpll0_enable(dev_priv, required_vco);
5743
5744 /* set CDCLK to the frequency the BIOS chose */
5745 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5746
5747 /* enable DBUF power */
5748 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5749 POSTING_READ(DBUF_CTL);
5750
5751 udelay(10);
5752
5753 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5754 DRM_ERROR("DBuf power enable timeout\n");
5755}
5756
dfcab17e 5757/* returns HPLL frequency in kHz */
f8bf63fd 5758static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5759{
586f49dc 5760 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5761
586f49dc 5762 /* Obtain SKU information */
a580516d 5763 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5764 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5765 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5766 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5767
dfcab17e 5768 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5769}
5770
5771/* Adjust CDclk dividers to allow high res or save power if possible */
5772static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5773{
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 u32 val, cmd;
5776
164dfd28
VK		 5777 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5778 != dev_priv->cdclk_freq);
d60c4473 5779
dfcab17e 5780 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5781 cmd = 2;
dfcab17e 5782 else if (cdclk == 266667)
30a970c6
JB		 5783 cmd = 1;
5784 else
5785 cmd = 0;
5786
5787 mutex_lock(&dev_priv->rps.hw_lock);
5788 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5789 val &= ~DSPFREQGUAR_MASK;
5790 val |= (cmd << DSPFREQGUAR_SHIFT);
5791 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5792 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5793 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5794 50)) {
5795 DRM_ERROR("timed out waiting for CDclk change\n");
5796 }
5797 mutex_unlock(&dev_priv->rps.hw_lock);
5798
54433e91
VS		 5799 mutex_lock(&dev_priv->sb_lock);
5800
dfcab17e 5801 if (cdclk == 400000) {
6bcda4f0 5802 u32 divider;
30a970c6 5803
6bcda4f0 5804 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5805
30a970c6
JB		 5806 /* adjust cdclk divider */
5807 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5808 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5809 val |= divider;
5810 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5811
5812 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5813 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5814 50))
5815 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5816 }
5817
30a970c6
JB		 5818 /* adjust self-refresh exit latency value */
5819 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5820 val &= ~0x7f;
5821
5822 /*
5823 * For high bandwidth configs, we set a higher latency in the bunit
5824 * so that the core display fetch happens in time to avoid underruns.
5825 */
dfcab17e 5826 if (cdclk == 400000)
30a970c6
JB		 5827 val |= 4500 / 250; /* 4.5 usec */
5828 else
5829 val |= 3000 / 250; /* 3.0 usec */
5830 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5831
a580516d 5832 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5833
b6283055 5834 intel_update_cdclk(dev);
30a970c6
JB		 5835}
5836
383c5a6a
VS		 5837static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5838{
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 u32 val, cmd;
5841
164dfd28
VK		 5842 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5843 != dev_priv->cdclk_freq);
383c5a6a
VS		 5844
5845 switch (cdclk) {
383c5a6a
VS		 5846 case 333333:
5847 case 320000:
383c5a6a 5848 case 266667:
383c5a6a 5849 case 200000:
383c5a6a
VS		 5850 break;
5851 default:
5f77eeb0 5852 MISSING_CASE(cdclk);
383c5a6a
VS		 5853 return;
5854 }
5855
9d0d3fda
VS		 5856 /*
5857 * Specs are full of misinformation, but testing on actual
5858 * hardware has shown that we just need to write the desired
5859 * CCK divider into the Punit register.
5860 */
5861 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5862
383c5a6a
VS		 5863 mutex_lock(&dev_priv->rps.hw_lock);
5864 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5865 val &= ~DSPFREQGUAR_MASK_CHV;
5866 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5867 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5868 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5869 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5870 50)) {
5871 DRM_ERROR("timed out waiting for CDclk change\n");
5872 }
5873 mutex_unlock(&dev_priv->rps.hw_lock);
5874
b6283055 5875 intel_update_cdclk(dev);
383c5a6a
VS		 5876}
5877
30a970c6
JB		 5878static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5879 int max_pixclk)
5880{
6bcda4f0 5881 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5882 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5883
30a970c6
JB		 5884 /*
5885 * Really only a few cases to deal with, as only 4 CDclks are supported:
5886 * 200MHz
5887 * 267MHz
29dc7ef3 5888 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5889 * 400MHz (VLV only)
5890 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5891 * of the lower bin and adjust if needed.
e37c67a1
VS		 5892 *
5893 * We seem to get an unstable or solid color picture at 200MHz.
5894 * Not sure what's wrong. For now use 200MHz only when all pipes
5895 * are off.
30a970c6 5896 */
6cca3195
VS		 5897 if (!IS_CHERRYVIEW(dev_priv) &&
5898 max_pixclk > freq_320*limit/100)
dfcab17e 5899 return 400000;
6cca3195 5900 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5901 return freq_320;
e37c67a1 5902 else if (max_pixclk > 0)
dfcab17e 5903 return 266667;
e37c67a1
VS		 5904 else
5905 return 200000;
30a970c6
JB		 5906}
5907
f8437dd1
VK		 5908static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5909 int max_pixclk)
5910{
5911 /*
5912 * FIXME:
5913 * - remove the guardband, it's not needed on BXT
5914 * - set 19.2MHz bypass frequency if there are no active pipes
5915 */
5916 if (max_pixclk > 576000*9/10)
5917 return 624000;
5918 else if (max_pixclk > 384000*9/10)
5919 return 576000;
5920 else if (max_pixclk > 288000*9/10)
5921 return 384000;
5922 else if (max_pixclk > 144000*9/10)
5923 return 288000;
5924 else
5925 return 144000;
5926}
5927
a821fc46
ACO		 5928/* Compute the max pixel clock for new configuration. Uses atomic state if
5929 * that's non-NULL, look at current state otherwise. */
5930static int intel_mode_max_pixclk(struct drm_device *dev,
5931 struct drm_atomic_state *state)
30a970c6 5932{
30a970c6 5933 struct intel_crtc *intel_crtc;
304603f4 5934 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5935 int max_pixclk = 0;
5936
d3fcc808 5937 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5938 if (state)
5939 crtc_state =
5940 intel_atomic_get_crtc_state(state, intel_crtc);
5941 else
5942 crtc_state = intel_crtc->config;
304603f4
ACO		 5943 if (IS_ERR(crtc_state))
5944 return PTR_ERR(crtc_state);
5945
5946 if (!crtc_state->base.enable)
5947 continue;
5948
5949 max_pixclk = max(max_pixclk,
5950 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5951 }
5952
5953 return max_pixclk;
5954}
5955
0a9ab303 5956static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5957{
304603f4 5958 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5959 struct drm_crtc *crtc;
5960 struct drm_crtc_state *crtc_state;
a821fc46 5961 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
85a96e7a 5962 int cdclk, ret = 0;
30a970c6 5963
304603f4
ACO		 5964 if (max_pixclk < 0)
5965 return max_pixclk;
30a970c6 5966
f8437dd1
VK		 5967 if (IS_VALLEYVIEW(dev_priv))
5968 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5969 else
5970 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5971
5972 if (cdclk == dev_priv->cdclk_freq)
304603f4 5973 return 0;
30a970c6 5974
0a9ab303
ACO		 5975 /* add all active pipes to the state */
5976 for_each_crtc(state->dev, crtc) {
0a9ab303
ACO		 5977 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5978 if (IS_ERR(crtc_state))
5979 return PTR_ERR(crtc_state);
0a9ab303 5980
85a96e7a
ML		 5981 if (!crtc_state->active || needs_modeset(crtc_state))
5982 continue;
304603f4 5983
85a96e7a
ML		 5984 crtc_state->mode_changed = true;
5985
5986 ret = drm_atomic_add_affected_connectors(state, crtc);
5987 if (ret)
5988 break;
5989
5990 ret = drm_atomic_add_affected_planes(state, crtc);
5991 if (ret)
5992 break;
5993 }
5994
5995 return ret;
30a970c6
JB		 5996}
5997
1e69cd74
VS		 5998static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5999{
6000 unsigned int credits, default_credits;
6001
6002 if (IS_CHERRYVIEW(dev_priv))
6003 default_credits = PFI_CREDIT(12);
6004 else
6005 default_credits = PFI_CREDIT(8);
6006
164dfd28 6007 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6008 /* CHV suggested value is 31 or 63 */
6009 if (IS_CHERRYVIEW(dev_priv))
6010 credits = PFI_CREDIT_31;
6011 else
6012 credits = PFI_CREDIT(15);
6013 } else {
6014 credits = default_credits;
6015 }
6016
6017 /*
6018 * WA - write default credits before re-programming
6019 * FIXME: should we also set the resend bit here?
6020 */
6021 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6022 default_credits);
6023
6024 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6025 credits | PFI_CREDIT_RESEND);
6026
6027 /*
6028 * FIXME is this guaranteed to clear
6029 * immediately or should we poll for it?
6030 */
6031 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6032}
6033
a821fc46 6034static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6035{
a821fc46 6036 struct drm_device *dev = old_state->dev;
30a970c6 6037 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6038 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6039 int req_cdclk;
6040
a821fc46
ACO		 6041 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6042 * never fail. */
304603f4
ACO		 6043 if (WARN_ON(max_pixclk < 0))
6044 return;
30a970c6 6045
304603f4 6046 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6047
164dfd28 6048 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6049 /*
6050 * FIXME: We can end up here with all power domains off, yet
6051 * with a CDCLK frequency other than the minimum. To account
6052 * for this take the PIPE-A power domain, which covers the HW
6053 * blocks needed for the following programming. This can be
6054 * removed once it's guaranteed that we get here either with
6055 * the minimum CDCLK set, or the required power domains
6056 * enabled.
6057 */
6058 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6059
383c5a6a
VS		 6060 if (IS_CHERRYVIEW(dev))
6061 cherryview_set_cdclk(dev, req_cdclk);
6062 else
6063 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6064
1e69cd74
VS		 6065 vlv_program_pfi_credits(dev_priv);
6066
738c05c0 6067 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6068 }
30a970c6
JB		 6069}
6070
89b667f8
JB		 6071static void valleyview_crtc_enable(struct drm_crtc *crtc)
6072{
6073 struct drm_device *dev = crtc->dev;
a72e4c9f 6074 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076 struct intel_encoder *encoder;
6077 int pipe = intel_crtc->pipe;
23538ef1 6078 bool is_dsi;
89b667f8 6079
53d9f4e9 6080 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6081 return;
6082
409ee761 6083 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6084
1ae0d137
VS		 6085 if (!is_dsi) {
6086 if (IS_CHERRYVIEW(dev))
6e3c9717 6087 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6088 else
6e3c9717 6089 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6090 }
5b18e57c 6091
6e3c9717 6092 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6093 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6094
6095 intel_set_pipe_timings(intel_crtc);
6096
c14b0485
VS		 6097 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099
6100 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6101 I915_WRITE(CHV_CANVAS(pipe), 0);
6102 }
6103
5b18e57c
DV		 6104 i9xx_set_pipeconf(intel_crtc);
6105
89b667f8 6106 intel_crtc->active = true;
89b667f8 6107
a72e4c9f 6108 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6109
89b667f8
JB		 6110 for_each_encoder_on_crtc(dev, crtc, encoder)
6111 if (encoder->pre_pll_enable)
6112 encoder->pre_pll_enable(encoder);
6113
9d556c99
CML		 6114 if (!is_dsi) {
6115 if (IS_CHERRYVIEW(dev))
6e3c9717 6116 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6117 else
6e3c9717 6118 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6119 }
89b667f8
JB		 6120
6121 for_each_encoder_on_crtc(dev, crtc, encoder)
6122 if (encoder->pre_enable)
6123 encoder->pre_enable(encoder);
6124
2dd24552
JB		 6125 i9xx_pfit_enable(intel_crtc);
6126
63cbb074
VS		 6127 intel_crtc_load_lut(crtc);
6128
f37fcc2a 6129 intel_update_watermarks(crtc);
e1fdc473 6130 intel_enable_pipe(intel_crtc);
be6a6f8e 6131
4b3a9526
VS		 6132 assert_vblank_disabled(crtc);
6133 drm_crtc_vblank_on(crtc);
6134
f9b61ff6
DV		 6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 encoder->enable(encoder);
89b667f8
JB		 6137}
6138
f13c2ef3
DV		 6139static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6140{
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143
6e3c9717
ACO		 6144 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6145 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6146}
6147
0b8765c6 6148static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6149{
6150 struct drm_device *dev = crtc->dev;
a72e4c9f 6151 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6153 struct intel_encoder *encoder;
79e53945 6154 int pipe = intel_crtc->pipe;
79e53945 6155
53d9f4e9 6156 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6157 return;
6158
f13c2ef3
DV		 6159 i9xx_set_pll_dividers(intel_crtc);
6160
6e3c9717 6161 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6162 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6163
6164 intel_set_pipe_timings(intel_crtc);
6165
5b18e57c
DV		 6166 i9xx_set_pipeconf(intel_crtc);
6167
f7abfe8b 6168 intel_crtc->active = true;
6b383a7f 6169
4a3436e8 6170 if (!IS_GEN2(dev))
a72e4c9f 6171 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6172
9d6d9f19
MK		 6173 for_each_encoder_on_crtc(dev, crtc, encoder)
6174 if (encoder->pre_enable)
6175 encoder->pre_enable(encoder);
6176
f6736a1a
DV		 6177 i9xx_enable_pll(intel_crtc);
6178
2dd24552
JB		 6179 i9xx_pfit_enable(intel_crtc);
6180
63cbb074
VS		 6181 intel_crtc_load_lut(crtc);
6182
f37fcc2a 6183 intel_update_watermarks(crtc);
e1fdc473 6184 intel_enable_pipe(intel_crtc);
be6a6f8e 6185
4b3a9526
VS		 6186 assert_vblank_disabled(crtc);
6187 drm_crtc_vblank_on(crtc);
6188
f9b61ff6
DV		 6189 for_each_encoder_on_crtc(dev, crtc, encoder)
6190 encoder->enable(encoder);
0b8765c6 6191}
79e53945 6192
87476d63
DV		 6193static void i9xx_pfit_disable(struct intel_crtc *crtc)
6194{
6195 struct drm_device *dev = crtc->base.dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6197
6e3c9717 6198 if (!crtc->config->gmch_pfit.control)
328d8e82 6199 return;
87476d63 6200
328d8e82 6201 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6202
328d8e82
DV		 6203 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6204 I915_READ(PFIT_CONTROL));
6205 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6206}
6207
0b8765c6
JB		 6208static void i9xx_crtc_disable(struct drm_crtc *crtc)
6209{
6210 struct drm_device *dev = crtc->dev;
6211 struct drm_i915_private *dev_priv = dev->dev_private;
6212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6213 struct intel_encoder *encoder;
0b8765c6 6214 int pipe = intel_crtc->pipe;
ef9c3aee 6215
53d9f4e9 6216 if (WARN_ON(!intel_crtc->active))
f7abfe8b
CW		 6217 return;
6218
6304cd91
VS		 6219 /*
6220 * On gen2 planes are double buffered but the pipe isn't, so we must
6221 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6222 * We also need to wait on all gmch platforms because of the
6223 * self-refresh mode constraint explained above.
6304cd91 6224 */
564ed191 6225 intel_wait_for_vblank(dev, pipe);
6304cd91 6226
4b3a9526
VS		 6227 for_each_encoder_on_crtc(dev, crtc, encoder)
6228 encoder->disable(encoder);
6229
f9b61ff6
DV		 6230 drm_crtc_vblank_off(crtc);
6231 assert_vblank_disabled(crtc);
6232
575f7ab7 6233 intel_disable_pipe(intel_crtc);
24a1f16d 6234
87476d63 6235 i9xx_pfit_disable(intel_crtc);
24a1f16d 6236
89b667f8
JB		 6237 for_each_encoder_on_crtc(dev, crtc, encoder)
6238 if (encoder->post_disable)
6239 encoder->post_disable(encoder);
6240
409ee761 6241 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6242 if (IS_CHERRYVIEW(dev))
6243 chv_disable_pll(dev_priv, pipe);
6244 else if (IS_VALLEYVIEW(dev))
6245 vlv_disable_pll(dev_priv, pipe);
6246 else
1c4e0274 6247 i9xx_disable_pll(intel_crtc);
076ed3b2 6248 }
0b8765c6 6249
4a3436e8 6250 if (!IS_GEN2(dev))
a72e4c9f 6251 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6252
f7abfe8b 6253 intel_crtc->active = false;
46ba614c 6254 intel_update_watermarks(crtc);
f37fcc2a 6255
efa9624e 6256 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6257 intel_fbc_update(dev);
efa9624e 6258 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6259}
6260
6b72d486
ML		 6261/*
6262 * turn all crtc's off, but do not adjust state
6263 * This has to be paired with a call to intel_modeset_setup_hw_state.
6264 */
6265void intel_display_suspend(struct drm_device *dev)
6266{
6267 struct drm_i915_private *dev_priv = to_i915(dev);
6268 struct drm_crtc *crtc;
6269
6270 for_each_crtc(dev, crtc) {
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 enum intel_display_power_domain domain;
6273 unsigned long domains;
6274
6275 if (!intel_crtc->active)
6276 continue;
6277
6278 intel_crtc_disable_planes(crtc);
6279 dev_priv->display.crtc_disable(crtc);
6280
6281 domains = intel_crtc->enabled_power_domains;
6282 for_each_power_domain(domain, domains)
6283 intel_display_power_put(dev_priv, domain);
6284 intel_crtc->enabled_power_domains = 0;
6285 }
6286}
6287
b04c5bd6
BF		 6288/* Master function to enable/disable CRTC and corresponding power wells */
6289void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6290{
6291 struct drm_device *dev = crtc->dev;
6292 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6294 enum intel_display_power_domain domain;
6295 unsigned long domains;
976f8a20 6296
1b509259
ML		 6297 if (enable == intel_crtc->active)
6298 return;
6299
6300 if (enable && !crtc->state->enable)
6301 return;
6302
6303 crtc->state->active = enable;
0e572fe7 6304 if (enable) {
1b509259
ML		 6305 domains = get_crtc_power_domains(crtc);
6306 for_each_power_domain(domain, domains)
6307 intel_display_power_get(dev_priv, domain);
6308 intel_crtc->enabled_power_domains = domains;
6309
6310 dev_priv->display.crtc_enable(crtc);
6311 intel_crtc_enable_planes(crtc);
0e572fe7 6312 } else {
1b509259
ML		 6313 intel_crtc_disable_planes(crtc);
6314 dev_priv->display.crtc_disable(crtc);
6315
6316 domains = intel_crtc->enabled_power_domains;
6317 for_each_power_domain(domain, domains)
6318 intel_display_power_put(dev_priv, domain);
6319 intel_crtc->enabled_power_domains = 0;
0e572fe7 6320 }
b04c5bd6
BF		 6321}
6322
6323/**
6324 * Sets the power management mode of the pipe and plane.
6325 */
6326void intel_crtc_update_dpms(struct drm_crtc *crtc)
6327{
6328 struct drm_device *dev = crtc->dev;
6329 struct intel_encoder *intel_encoder;
6330 bool enable = false;
6331
6332 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6333 enable |= intel_encoder->connectors_active;
6334
6335 intel_crtc_control(crtc, enable);
976f8a20
DV		 6336}
6337
ea5b213a 6338void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6339{
4ef69c7a 6340 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6341
ea5b213a
CW		 6342 drm_encoder_cleanup(encoder);
6343 kfree(intel_encoder);
7e7d76c3
JB		 6344}
6345
9237329d 6346/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6347 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6348 * state of the entire output pipe. */
9237329d 6349static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6350{
5ab432ef
DV		 6351 if (mode == DRM_MODE_DPMS_ON) {
6352 encoder->connectors_active = true;
6353
b2cabb0e 6354 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6355 } else {
6356 encoder->connectors_active = false;
6357
b2cabb0e 6358 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6359 }
79e53945
JB		 6360}
6361
0a91ca29
DV		 6362/* Cross check the actual hw state with our own modeset state tracking (and it's
6363 * internal consistency). */
b980514c 6364static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6365{
0a91ca29
DV		 6366 if (connector->get_hw_state(connector)) {
6367 struct intel_encoder *encoder = connector->encoder;
6368 struct drm_crtc *crtc;
6369 bool encoder_enabled;
6370 enum pipe pipe;
6371
6372 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6373 connector->base.base.id,
c23cc417 6374 connector->base.name);
0a91ca29 6375
0e32b39c
DA		 6376 /* there is no real hw state for MST connectors */
6377 if (connector->mst_port)
6378 return;
6379
e2c719b7 6380 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6381 "wrong connector dpms state\n");
e2c719b7 6382 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6383 "active connector not linked to encoder\n");
0a91ca29 6384
36cd7444 6385 if (encoder) {
e2c719b7 6386 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6387 "encoder->connectors_active not set\n");
6388
6389 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6390 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6391 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6392 return;
0a91ca29 6393
36cd7444 6394 crtc = encoder->base.crtc;
0a91ca29 6395
83d65738
MR		 6396 I915_STATE_WARN(!crtc->state->enable,
6397 "crtc not enabled\n");
e2c719b7
RC		 6398 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6399 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6400 "encoder active on the wrong pipe\n");
6401 }
0a91ca29 6402 }
79e53945
JB		 6403}
6404
08d9bc92
ACO		 6405int intel_connector_init(struct intel_connector *connector)
6406{
6407 struct drm_connector_state *connector_state;
6408
6409 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6410 if (!connector_state)
6411 return -ENOMEM;
6412
6413 connector->base.state = connector_state;
6414 return 0;
6415}
6416
6417struct intel_connector *intel_connector_alloc(void)
6418{
6419 struct intel_connector *connector;
6420
6421 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6422 if (!connector)
6423 return NULL;
6424
6425 if (intel_connector_init(connector) < 0) {
6426 kfree(connector);
6427 return NULL;
6428 }
6429
6430 return connector;
6431}
6432
5ab432ef
DV		 6433/* Even simpler default implementation, if there's really no special case to
6434 * consider. */
6435void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6436{
5ab432ef
DV		 6437 /* All the simple cases only support two dpms states. */
6438 if (mode != DRM_MODE_DPMS_ON)
6439 mode = DRM_MODE_DPMS_OFF;
d4270e57 6440
5ab432ef
DV		 6441 if (mode == connector->dpms)
6442 return;
6443
6444 connector->dpms = mode;
6445
6446 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6447 if (connector->encoder)
6448 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6449
b980514c 6450 intel_modeset_check_state(connector->dev);
79e53945
JB		 6451}
6452
f0947c37
DV		 6453/* Simple connector->get_hw_state implementation for encoders that support only
6454 * one connector and no cloning and hence the encoder state determines the state
6455 * of the connector. */
6456bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6457{
24929352 6458 enum pipe pipe = 0;
f0947c37 6459 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6460
f0947c37 6461 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6462}
6463
6d293983 6464static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6465{
6d293983
ACO		 6466 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6467 return crtc_state->fdi_lanes;
d272ddfa
VS		 6468
6469 return 0;
6470}
6471
6d293983 6472static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6473 struct intel_crtc_state *pipe_config)
1857e1da 6474{
6d293983
ACO		 6475 struct drm_atomic_state *state = pipe_config->base.state;
6476 struct intel_crtc *other_crtc;
6477 struct intel_crtc_state *other_crtc_state;
6478
1857e1da
DV		 6479 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6480 pipe_name(pipe), pipe_config->fdi_lanes);
6481 if (pipe_config->fdi_lanes > 4) {
6482 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6483 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6484 return -EINVAL;
1857e1da
DV		 6485 }
6486
bafb6553 6487 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6488 if (pipe_config->fdi_lanes > 2) {
6489 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6490 pipe_config->fdi_lanes);
6d293983 6491 return -EINVAL;
1857e1da 6492 } else {
6d293983 6493 return 0;
1857e1da
DV		 6494 }
6495 }
6496
6497 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6498 return 0;
1857e1da
DV		 6499
6500 /* Ivybridge 3 pipe is really complicated */
6501 switch (pipe) {
6502 case PIPE_A:
6d293983 6503 return 0;
1857e1da 6504 case PIPE_B:
6d293983
ACO		 6505 if (pipe_config->fdi_lanes <= 2)
6506 return 0;
6507
6508 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6509 other_crtc_state =
6510 intel_atomic_get_crtc_state(state, other_crtc);
6511 if (IS_ERR(other_crtc_state))
6512 return PTR_ERR(other_crtc_state);
6513
6514 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6515 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6516 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6517 return -EINVAL;
1857e1da 6518 }
6d293983 6519 return 0;
1857e1da 6520 case PIPE_C:
251cc67c
VS		 6521 if (pipe_config->fdi_lanes > 2) {
6522 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6523 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6524 return -EINVAL;
251cc67c 6525 }
6d293983
ACO		 6526
6527 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6528 other_crtc_state =
6529 intel_atomic_get_crtc_state(state, other_crtc);
6530 if (IS_ERR(other_crtc_state))
6531 return PTR_ERR(other_crtc_state);
6532
6533 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6534 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6535 return -EINVAL;
1857e1da 6536 }
6d293983 6537 return 0;
1857e1da
DV		 6538 default:
6539 BUG();
6540 }
6541}
6542
e29c22c0
DV		 6543#define RETRY 1
6544static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6545 struct intel_crtc_state *pipe_config)
877d48d5 6546{
1857e1da 6547 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6548 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6549 int lane, link_bw, fdi_dotclock, ret;
6550 bool needs_recompute = false;
877d48d5 6551
e29c22c0 6552retry:
877d48d5
DV		 6553 /* FDI is a binary signal running at ~2.7GHz, encoding
6554 * each output octet as 10 bits. The actual frequency
6555 * is stored as a divider into a 100MHz clock, and the
6556 * mode pixel clock is stored in units of 1KHz.
6557 * Hence the bw of each lane in terms of the mode signal
6558 * is:
6559 */
6560 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6561
241bfc38 6562 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6563
2bd89a07 6564 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6565 pipe_config->pipe_bpp);
6566
6567 pipe_config->fdi_lanes = lane;
6568
2bd89a07 6569 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6570 link_bw, &pipe_config->fdi_m_n);
1857e1da 6571
6d293983
ACO		 6572 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6573 intel_crtc->pipe, pipe_config);
6574 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6575 pipe_config->pipe_bpp -= 2*3;
6576 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6577 pipe_config->pipe_bpp);
6578 needs_recompute = true;
6579 pipe_config->bw_constrained = true;
6580
6581 goto retry;
6582 }
6583
6584 if (needs_recompute)
6585 return RETRY;
6586
6d293983 6587 return ret;
877d48d5
DV		 6588}
6589
8cfb3407
VS		 6590static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6591 struct intel_crtc_state *pipe_config)
6592{
6593 if (pipe_config->pipe_bpp > 24)
6594 return false;
6595
6596 /* HSW can handle pixel rate up to cdclk? */
6597 if (IS_HASWELL(dev_priv->dev))
6598 return true;
6599
6600 /*
b432e5cf
VS		 6601 * We compare against max which means we must take
6602 * the increased cdclk requirement into account when
6603 * calculating the new cdclk.
6604 *
6605 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6606 */
6607 return ilk_pipe_pixel_rate(pipe_config) <=
6608 dev_priv->max_cdclk_freq * 95 / 100;
6609}
6610
42db64ef 6611static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6612 struct intel_crtc_state *pipe_config)
42db64ef 6613{
8cfb3407
VS		 6614 struct drm_device *dev = crtc->base.dev;
6615 struct drm_i915_private *dev_priv = dev->dev_private;
6616
d330a953 6617 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6618 hsw_crtc_supports_ips(crtc) &&
6619 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6620}
6621
a43f6e0f 6622static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6623 struct intel_crtc_state *pipe_config)
79e53945 6624{
a43f6e0f 6625 struct drm_device *dev = crtc->base.dev;
8bd31e67 6626 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6627 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6628 int ret;
89749350 6629
ad3a4479 6630 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6631 if (INTEL_INFO(dev)->gen < 4) {
44913155 6632 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6633
6634 /*
6635 * Enable pixel doubling when the dot clock
6636 * is > 90% of the (display) core speed.
6637 *
b397c96b
VS		 6638 * GDG double wide on either pipe,
6639 * otherwise pipe A only.
cf532bb2 6640 */
b397c96b 6641 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6642 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6643 clock_limit *= 2;
cf532bb2 6644 pipe_config->double_wide = true;
ad3a4479
VS		 6645 }
6646
241bfc38 6647 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6648 return -EINVAL;
2c07245f 6649 }
89749350 6650
1d1d0e27
VS		 6651 /*
6652 * Pipe horizontal size must be even in:
6653 * - DVO ganged mode
6654 * - LVDS dual channel mode
6655 * - Double wide pipe
6656 */
a93e255f 6657 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6658 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6659 pipe_config->pipe_src_w &= ~1;
6660
8693a824
DL		 6661 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6662 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6663 */
6664 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6665 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6666 return -EINVAL;
44f46b42 6667
f5adf94e 6668 if (HAS_IPS(dev))
a43f6e0f
DV		 6669 hsw_compute_ips_config(crtc, pipe_config);
6670
877d48d5 6671 if (pipe_config->has_pch_encoder)
a43f6e0f 6672 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6673
d03c93d4
CK		 6674 /* FIXME: remove below call once atomic mode set is place and all crtc
6675 * related checks called from atomic_crtc_check function */
6676 ret = 0;
6677 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6678 crtc, pipe_config->base.state);
6679 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6680
6681 return ret;
79e53945
JB		 6682}
6683
1652d19e
VS		 6684static int skylake_get_display_clock_speed(struct drm_device *dev)
6685{
6686 struct drm_i915_private *dev_priv = to_i915(dev);
6687 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6688 uint32_t cdctl = I915_READ(CDCLK_CTL);
6689 uint32_t linkrate;
6690
414355a7 6691 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6692 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6693
6694 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6695 return 540000;
6696
6697 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6698 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6699
71cd8423
DL		 6700 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6701 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6702 /* vco 8640 */
6703 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6704 case CDCLK_FREQ_450_432:
6705 return 432000;
6706 case CDCLK_FREQ_337_308:
6707 return 308570;
6708 case CDCLK_FREQ_675_617:
6709 return 617140;
6710 default:
6711 WARN(1, "Unknown cd freq selection\n");
6712 }
6713 } else {
6714 /* vco 8100 */
6715 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6716 case CDCLK_FREQ_450_432:
6717 return 450000;
6718 case CDCLK_FREQ_337_308:
6719 return 337500;
6720 case CDCLK_FREQ_675_617:
6721 return 675000;
6722 default:
6723 WARN(1, "Unknown cd freq selection\n");
6724 }
6725 }
6726
6727 /* error case, do as if DPLL0 isn't enabled */
6728 return 24000;
6729}
6730
6731static int broadwell_get_display_clock_speed(struct drm_device *dev)
6732{
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 uint32_t lcpll = I915_READ(LCPLL_CTL);
6735 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6736
6737 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6738 return 800000;
6739 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6740 return 450000;
6741 else if (freq == LCPLL_CLK_FREQ_450)
6742 return 450000;
6743 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6744 return 540000;
6745 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6746 return 337500;
6747 else
6748 return 675000;
6749}
6750
6751static int haswell_get_display_clock_speed(struct drm_device *dev)
6752{
6753 struct drm_i915_private *dev_priv = dev->dev_private;
6754 uint32_t lcpll = I915_READ(LCPLL_CTL);
6755 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6756
6757 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6758 return 800000;
6759 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6760 return 450000;
6761 else if (freq == LCPLL_CLK_FREQ_450)
6762 return 450000;
6763 else if (IS_HSW_ULT(dev))
6764 return 337500;
6765 else
6766 return 540000;
79e53945
JB		 6767}
6768
25eb05fc
JB		 6769static int valleyview_get_display_clock_speed(struct drm_device *dev)
6770{
d197b7d3 6771 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6772 u32 val;
6773 int divider;
6774
6bcda4f0
VS		 6775 if (dev_priv->hpll_freq == 0)
6776 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6777
a580516d 6778 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6779 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6780 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6781
6782 divider = val & DISPLAY_FREQUENCY_VALUES;
6783
7d007f40
VS		 6784 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6785 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6786 "cdclk change in progress\n");
6787
6bcda4f0 6788 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6789}
6790
b37a6434
VS		 6791static int ilk_get_display_clock_speed(struct drm_device *dev)
6792{
6793 return 450000;
6794}
6795
e70236a8
JB		 6796static int i945_get_display_clock_speed(struct drm_device *dev)
6797{
6798 return 400000;
6799}
79e53945 6800
e70236a8 6801static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6802{
e907f170 6803 return 333333;
e70236a8 6804}
79e53945 6805
e70236a8
JB		 6806static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6807{
6808 return 200000;
6809}
79e53945 6810
257a7ffc
DV		 6811static int pnv_get_display_clock_speed(struct drm_device *dev)
6812{
6813 u16 gcfgc = 0;
6814
6815 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6816
6817 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6818 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6819 return 266667;
257a7ffc 6820 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6821 return 333333;
257a7ffc 6822 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6823 return 444444;
257a7ffc
DV		 6824 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6825 return 200000;
6826 default:
6827 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6828 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6829 return 133333;
257a7ffc 6830 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6831 return 166667;
257a7ffc
DV		 6832 }
6833}
6834
e70236a8
JB		 6835static int i915gm_get_display_clock_speed(struct drm_device *dev)
6836{
6837 u16 gcfgc = 0;
79e53945 6838
e70236a8
JB		 6839 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6840
6841 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6842 return 133333;
e70236a8
JB		 6843 else {
6844 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6845 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6846 return 333333;
e70236a8
JB		 6847 default:
6848 case GC_DISPLAY_CLOCK_190_200_MHZ:
6849 return 190000;
79e53945 6850 }
e70236a8
JB		 6851 }
6852}
6853
6854static int i865_get_display_clock_speed(struct drm_device *dev)
6855{
e907f170 6856 return 266667;
e70236a8
JB		 6857}
6858
1b1d2716 6859static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6860{
6861 u16 hpllcc = 0;
1b1d2716 6862
65cd2b3f
VS		 6863 /*
6864 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6865 * encoding is different :(
6866 * FIXME is this the right way to detect 852GM/852GMV?
6867 */
6868 if (dev->pdev->revision == 0x1)
6869 return 133333;
6870
1b1d2716
VS		 6871 pci_bus_read_config_word(dev->pdev->bus,
6872 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6873
e70236a8
JB		 6874 /* Assume that the hardware is in the high speed state. This
6875 * should be the default.
6876 */
6877 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6878 case GC_CLOCK_133_200:
1b1d2716 6879 case GC_CLOCK_133_200_2:
e70236a8
JB		 6880 case GC_CLOCK_100_200:
6881 return 200000;
6882 case GC_CLOCK_166_250:
6883 return 250000;
6884 case GC_CLOCK_100_133:
e907f170 6885 return 133333;
1b1d2716
VS		 6886 case GC_CLOCK_133_266:
6887 case GC_CLOCK_133_266_2:
6888 case GC_CLOCK_166_266:
6889 return 266667;
e70236a8 6890 }
79e53945 6891
e70236a8
JB		 6892 /* Shouldn't happen */
6893 return 0;
6894}
79e53945 6895
e70236a8
JB		 6896static int i830_get_display_clock_speed(struct drm_device *dev)
6897{
e907f170 6898 return 133333;
79e53945
JB		 6899}
6900
34edce2f
VS		 6901static unsigned int intel_hpll_vco(struct drm_device *dev)
6902{
6903 struct drm_i915_private *dev_priv = dev->dev_private;
6904 static const unsigned int blb_vco[8] = {
6905 [0] = 3200000,
6906 [1] = 4000000,
6907 [2] = 5333333,
6908 [3] = 4800000,
6909 [4] = 6400000,
6910 };
6911 static const unsigned int pnv_vco[8] = {
6912 [0] = 3200000,
6913 [1] = 4000000,
6914 [2] = 5333333,
6915 [3] = 4800000,
6916 [4] = 2666667,
6917 };
6918 static const unsigned int cl_vco[8] = {
6919 [0] = 3200000,
6920 [1] = 4000000,
6921 [2] = 5333333,
6922 [3] = 6400000,
6923 [4] = 3333333,
6924 [5] = 3566667,
6925 [6] = 4266667,
6926 };
6927 static const unsigned int elk_vco[8] = {
6928 [0] = 3200000,
6929 [1] = 4000000,
6930 [2] = 5333333,
6931 [3] = 4800000,
6932 };
6933 static const unsigned int ctg_vco[8] = {
6934 [0] = 3200000,
6935 [1] = 4000000,
6936 [2] = 5333333,
6937 [3] = 6400000,
6938 [4] = 2666667,
6939 [5] = 4266667,
6940 };
6941 const unsigned int *vco_table;
6942 unsigned int vco;
6943 uint8_t tmp = 0;
6944
6945 /* FIXME other chipsets? */
6946 if (IS_GM45(dev))
6947 vco_table = ctg_vco;
6948 else if (IS_G4X(dev))
6949 vco_table = elk_vco;
6950 else if (IS_CRESTLINE(dev))
6951 vco_table = cl_vco;
6952 else if (IS_PINEVIEW(dev))
6953 vco_table = pnv_vco;
6954 else if (IS_G33(dev))
6955 vco_table = blb_vco;
6956 else
6957 return 0;
6958
6959 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6960
6961 vco = vco_table[tmp & 0x7];
6962 if (vco == 0)
6963 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6964 else
6965 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6966
6967 return vco;
6968}
6969
6970static int gm45_get_display_clock_speed(struct drm_device *dev)
6971{
6972 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6973 uint16_t tmp = 0;
6974
6975 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6976
6977 cdclk_sel = (tmp >> 12) & 0x1;
6978
6979 switch (vco) {
6980 case 2666667:
6981 case 4000000:
6982 case 5333333:
6983 return cdclk_sel ? 333333 : 222222;
6984 case 3200000:
6985 return cdclk_sel ? 320000 : 228571;
6986 default:
6987 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6988 return 222222;
6989 }
6990}
6991
6992static int i965gm_get_display_clock_speed(struct drm_device *dev)
6993{
6994 static const uint8_t div_3200[] = { 16, 10, 8 };
6995 static const uint8_t div_4000[] = { 20, 12, 10 };
6996 static const uint8_t div_5333[] = { 24, 16, 14 };
6997 const uint8_t *div_table;
6998 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6999 uint16_t tmp = 0;
7000
7001 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7002
7003 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7004
7005 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7006 goto fail;
7007
7008 switch (vco) {
7009 case 3200000:
7010 div_table = div_3200;
7011 break;
7012 case 4000000:
7013 div_table = div_4000;
7014 break;
7015 case 5333333:
7016 div_table = div_5333;
7017 break;
7018 default:
7019 goto fail;
7020 }
7021
7022 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7023
7024 fail:
7025 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7026 return 200000;
7027}
7028
7029static int g33_get_display_clock_speed(struct drm_device *dev)
7030{
7031 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7032 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7033 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7034 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7035 const uint8_t *div_table;
7036 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7037 uint16_t tmp = 0;
7038
7039 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7040
7041 cdclk_sel = (tmp >> 4) & 0x7;
7042
7043 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7044 goto fail;
7045
7046 switch (vco) {
7047 case 3200000:
7048 div_table = div_3200;
7049 break;
7050 case 4000000:
7051 div_table = div_4000;
7052 break;
7053 case 4800000:
7054 div_table = div_4800;
7055 break;
7056 case 5333333:
7057 div_table = div_5333;
7058 break;
7059 default:
7060 goto fail;
7061 }
7062
7063 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7064
7065 fail:
7066 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7067 return 190476;
7068}
7069
2c07245f 7070static void
a65851af 7071intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7072{
a65851af
VS		 7073 while (*num > DATA_LINK_M_N_MASK ||
7074 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7075 *num >>= 1;
7076 *den >>= 1;
7077 }
7078}
7079
a65851af
VS		 7080static void compute_m_n(unsigned int m, unsigned int n,
7081 uint32_t *ret_m, uint32_t *ret_n)
7082{
7083 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7084 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7085 intel_reduce_m_n_ratio(ret_m, ret_n);
7086}
7087
e69d0bc1
DV		 7088void
7089intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7090 int pixel_clock, int link_clock,
7091 struct intel_link_m_n *m_n)
2c07245f 7092{
e69d0bc1 7093 m_n->tu = 64;
a65851af
VS		 7094
7095 compute_m_n(bits_per_pixel * pixel_clock,
7096 link_clock * nlanes * 8,
7097 &m_n->gmch_m, &m_n->gmch_n);
7098
7099 compute_m_n(pixel_clock, link_clock,
7100 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7101}
7102
a7615030
CW		 7103static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7104{
d330a953
JN		 7105 if (i915.panel_use_ssc >= 0)
7106 return i915.panel_use_ssc != 0;
41aa3448 7107 return dev_priv->vbt.lvds_use_ssc
435793df 7108 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7109}
7110
a93e255f
ACO		 7111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7112 int num_connectors)
c65d77d8 7113{
a93e255f 7114 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7115 struct drm_i915_private *dev_priv = dev->dev_private;
7116 int refclk;
7117
a93e255f
ACO		 7118 WARN_ON(!crtc_state->base.state);
7119
5ab7b0b7 7120 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7121 refclk = 100000;
a93e255f 7122 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7123 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7124 refclk = dev_priv->vbt.lvds_ssc_freq;
7125 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7126 } else if (!IS_GEN2(dev)) {
7127 refclk = 96000;
7128 } else {
7129 refclk = 48000;
7130 }
7131
7132 return refclk;
7133}
7134
7429e9d4 7135static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7136{
7df00d7a 7137 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7138}
f47709a9 7139
7429e9d4
DV		 7140static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7141{
7142 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7143}
7144
f47709a9 7145static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7146 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7147 intel_clock_t *reduced_clock)
7148{
f47709a9 7149 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7150 u32 fp, fp2 = 0;
7151
7152 if (IS_PINEVIEW(dev)) {
190f68c5 7153 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7154 if (reduced_clock)
7429e9d4 7155 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7156 } else {
190f68c5 7157 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7158 if (reduced_clock)
7429e9d4 7159 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7160 }
7161
190f68c5 7162 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7163
f47709a9 7164 crtc->lowfreq_avail = false;
a93e255f 7165 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7166 reduced_clock) {
190f68c5 7167 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7168 crtc->lowfreq_avail = true;
a7516a05 7169 } else {
190f68c5 7170 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7171 }
7172}
7173
5e69f97f
CML		 7174static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7175 pipe)
89b667f8
JB		 7176{
7177 u32 reg_val;
7178
7179 /*
7180 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7181 * and set it to a reasonable value instead.
7182 */
ab3c759a 7183 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7184 reg_val &= 0xffffff00;
7185 reg_val |= 0x00000030;
ab3c759a 7186 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7187
ab3c759a 7188 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7189 reg_val &= 0x8cffffff;
7190 reg_val = 0x8c000000;
ab3c759a 7191 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7192
ab3c759a 7193 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7194 reg_val &= 0xffffff00;
ab3c759a 7195 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7196
ab3c759a 7197 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7198 reg_val &= 0x00ffffff;
7199 reg_val |= 0xb0000000;
ab3c759a 7200 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7201}
7202
b551842d
DV		 7203static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7204 struct intel_link_m_n *m_n)
7205{
7206 struct drm_device *dev = crtc->base.dev;
7207 struct drm_i915_private *dev_priv = dev->dev_private;
7208 int pipe = crtc->pipe;
7209
e3b95f1e
DV		 7210 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7211 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7212 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7213 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7214}
7215
7216static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7217 struct intel_link_m_n *m_n,
7218 struct intel_link_m_n *m2_n2)
b551842d
DV		 7219{
7220 struct drm_device *dev = crtc->base.dev;
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 int pipe = crtc->pipe;
6e3c9717 7223 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7224
7225 if (INTEL_INFO(dev)->gen >= 5) {
7226 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7227 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7228 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7229 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7230 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7231 * for gen < 8) and if DRRS is supported (to make sure the
7232 * registers are not unnecessarily accessed).
7233 */
44395bfe 7234 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7235 crtc->config->has_drrs) {
f769cd24
VK		 7236 I915_WRITE(PIPE_DATA_M2(transcoder),
7237 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7238 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7239 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7240 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7241 }
b551842d 7242 } else {
e3b95f1e
DV		 7243 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7244 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7245 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7246 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7247 }
7248}
7249
fe3cd48d 7250void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7251{
fe3cd48d
R		 7252 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7253
7254 if (m_n == M1_N1) {
7255 dp_m_n = &crtc->config->dp_m_n;
7256 dp_m2_n2 = &crtc->config->dp_m2_n2;
7257 } else if (m_n == M2_N2) {
7258
7259 /*
7260 * M2_N2 registers are not supported. Hence m2_n2 divider value
7261 * needs to be programmed into M1_N1.
7262 */
7263 dp_m_n = &crtc->config->dp_m2_n2;
7264 } else {
7265 DRM_ERROR("Unsupported divider value\n");
7266 return;
7267 }
7268
6e3c9717
ACO		 7269 if (crtc->config->has_pch_encoder)
7270 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7271 else
fe3cd48d 7272 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7273}
7274
d288f65f 7275static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7276 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7277{
7278 u32 dpll, dpll_md;
7279
7280 /*
7281 * Enable DPIO clock input. We should never disable the reference
7282 * clock for pipe B, since VGA hotplug / manual detection depends
7283 * on it.
7284 */
7285 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7286 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7287 /* We should never disable this, set it here for state tracking */
7288 if (crtc->pipe == PIPE_B)
7289 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7290 dpll |= DPLL_VCO_ENABLE;
d288f65f 7291 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7292
d288f65f 7293 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7294 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7295 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7296}
7297
d288f65f 7298static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7299 const struct intel_crtc_state *pipe_config)
a0c4da24 7300{
f47709a9 7301 struct drm_device *dev = crtc->base.dev;
a0c4da24 7302 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7303 int pipe = crtc->pipe;
bdd4b6a6 7304 u32 mdiv;
a0c4da24 7305 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7306 u32 coreclk, reg_val;
a0c4da24 7307
a580516d 7308 mutex_lock(&dev_priv->sb_lock);
09153000 7309
d288f65f
VS		 7310 bestn = pipe_config->dpll.n;
7311 bestm1 = pipe_config->dpll.m1;
7312 bestm2 = pipe_config->dpll.m2;
7313 bestp1 = pipe_config->dpll.p1;
7314 bestp2 = pipe_config->dpll.p2;
a0c4da24 7315
89b667f8
JB		 7316 /* See eDP HDMI DPIO driver vbios notes doc */
7317
7318 /* PLL B needs special handling */
bdd4b6a6 7319 if (pipe == PIPE_B)
5e69f97f 7320 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7321
7322 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7323 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7324
7325 /* Disable target IRef on PLL */
ab3c759a 7326 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7327 reg_val &= 0x00ffffff;
ab3c759a 7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7329
7330 /* Disable fast lock */
ab3c759a 7331 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7332
7333 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7334 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7335 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7336 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7337 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7338
7339 /*
7340 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7341 * but we don't support that).
7342 * Note: don't use the DAC post divider as it seems unstable.
7343 */
7344 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7346
a0c4da24 7347 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7349
89b667f8 7350 /* Set HBR and RBR LPF coefficients */
d288f65f 7351 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7352 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7353 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7354 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7355 0x009f0003);
89b667f8 7356 else
ab3c759a 7357 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7358 0x00d0000f);
7359
681a8504 7360 if (pipe_config->has_dp_encoder) {
89b667f8 7361 /* Use SSC source */
bdd4b6a6 7362 if (pipe == PIPE_A)
ab3c759a 7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7364 0x0df40000);
7365 else
ab3c759a 7366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7367 0x0df70000);
7368 } else { /* HDMI or VGA */
7369 /* Use bend source */
bdd4b6a6 7370 if (pipe == PIPE_A)
ab3c759a 7371 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7372 0x0df70000);
7373 else
ab3c759a 7374 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7375 0x0df40000);
7376 }
a0c4da24 7377
ab3c759a 7378 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7379 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7381 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7382 coreclk |= 0x01000000;
ab3c759a 7383 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7384
ab3c759a 7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7386 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7387}
7388
d288f65f 7389static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7390 struct intel_crtc_state *pipe_config)
1ae0d137 7391{
d288f65f 7392 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7393 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7394 DPLL_VCO_ENABLE;
7395 if (crtc->pipe != PIPE_A)
d288f65f 7396 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7397
d288f65f
VS		 7398 pipe_config->dpll_hw_state.dpll_md =
7399 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7400}
7401
d288f65f 7402static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7403 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7404{
7405 struct drm_device *dev = crtc->base.dev;
7406 struct drm_i915_private *dev_priv = dev->dev_private;
7407 int pipe = crtc->pipe;
7408 int dpll_reg = DPLL(crtc->pipe);
7409 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7410 u32 loopfilter, tribuf_calcntr;
9d556c99 7411 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7412 u32 dpio_val;
9cbe40c1 7413 int vco;
9d556c99 7414
d288f65f
VS		 7415 bestn = pipe_config->dpll.n;
7416 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7417 bestm1 = pipe_config->dpll.m1;
7418 bestm2 = pipe_config->dpll.m2 >> 22;
7419 bestp1 = pipe_config->dpll.p1;
7420 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7421 vco = pipe_config->dpll.vco;
a945ce7e 7422 dpio_val = 0;
9cbe40c1 7423 loopfilter = 0;
9d556c99
CML		 7424
7425 /*
7426 * Enable Refclk and SSC
7427 */
a11b0703 7428 I915_WRITE(dpll_reg,
d288f65f 7429 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7430
a580516d 7431 mutex_lock(&dev_priv->sb_lock);
9d556c99 7432
9d556c99
CML		 7433 /* p1 and p2 divider */
7434 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7435 5 << DPIO_CHV_S1_DIV_SHIFT |
7436 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7437 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7438 1 << DPIO_CHV_K_DIV_SHIFT);
7439
7440 /* Feedback post-divider - m2 */
7441 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7442
7443 /* Feedback refclk divider - n and m1 */
7444 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7445 DPIO_CHV_M1_DIV_BY_2 |
7446 1 << DPIO_CHV_N_DIV_SHIFT);
7447
7448 /* M2 fraction division */
a945ce7e
VP		 7449 if (bestm2_frac)
7450 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7451
7452 /* M2 fraction division enable */
a945ce7e
VP		 7453 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7454 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7455 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7456 if (bestm2_frac)
7457 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7459
de3a0fde
VP		 7460 /* Program digital lock detect threshold */
7461 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7462 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7463 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7464 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7465 if (!bestm2_frac)
7466 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7468
9d556c99 7469 /* Loop filter */
9cbe40c1
VP		 7470 if (vco == 5400000) {
7471 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7472 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7473 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7474 tribuf_calcntr = 0x9;
7475 } else if (vco <= 6200000) {
7476 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7477 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7478 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7479 tribuf_calcntr = 0x9;
7480 } else if (vco <= 6480000) {
7481 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7482 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7483 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7484 tribuf_calcntr = 0x8;
7485 } else {
7486 /* Not supported. Apply the same limits as in the max case */
7487 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7488 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7489 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7490 tribuf_calcntr = 0;
7491 }
9d556c99
CML		 7492 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7493
968040b2 7494 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7495 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7496 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7497 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7498
9d556c99
CML		 7499 /* AFC Recal */
7500 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7501 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7502 DPIO_AFC_RECAL);
7503
a580516d 7504 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7505}
7506
d288f65f
VS		 7507/**
7508 * vlv_force_pll_on - forcibly enable just the PLL
7509 * @dev_priv: i915 private structure
7510 * @pipe: pipe PLL to enable
7511 * @dpll: PLL configuration
7512 *
7513 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7514 * in cases where we need the PLL enabled even when @pipe is not going to
7515 * be enabled.
7516 */
7517void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7518 const struct dpll *dpll)
7519{
7520 struct intel_crtc *crtc =
7521 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7522 struct intel_crtc_state pipe_config = {
a93e255f 7523 .base.crtc = &crtc->base,
d288f65f
VS		 7524 .pixel_multiplier = 1,
7525 .dpll = *dpll,
7526 };
7527
7528 if (IS_CHERRYVIEW(dev)) {
7529 chv_update_pll(crtc, &pipe_config);
7530 chv_prepare_pll(crtc, &pipe_config);
7531 chv_enable_pll(crtc, &pipe_config);
7532 } else {
7533 vlv_update_pll(crtc, &pipe_config);
7534 vlv_prepare_pll(crtc, &pipe_config);
7535 vlv_enable_pll(crtc, &pipe_config);
7536 }
7537}
7538
7539/**
7540 * vlv_force_pll_off - forcibly disable just the PLL
7541 * @dev_priv: i915 private structure
7542 * @pipe: pipe PLL to disable
7543 *
7544 * Disable the PLL for @pipe. To be used in cases where we need
7545 * the PLL enabled even when @pipe is not going to be enabled.
7546 */
7547void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7548{
7549 if (IS_CHERRYVIEW(dev))
7550 chv_disable_pll(to_i915(dev), pipe);
7551 else
7552 vlv_disable_pll(to_i915(dev), pipe);
7553}
7554
f47709a9 7555static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7556 struct intel_crtc_state *crtc_state,
f47709a9 7557 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7558 int num_connectors)
7559{
f47709a9 7560 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7561 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7562 u32 dpll;
7563 bool is_sdvo;
190f68c5 7564 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7565
190f68c5 7566 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7567
a93e255f
ACO		 7568 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7569 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7570
7571 dpll = DPLL_VGA_MODE_DIS;
7572
a93e255f 7573 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7574 dpll |= DPLLB_MODE_LVDS;
7575 else
7576 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7577
ef1b460d 7578 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7579 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7580 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7581 }
198a037f
DV		 7582
7583 if (is_sdvo)
4a33e48d 7584 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7585
190f68c5 7586 if (crtc_state->has_dp_encoder)
4a33e48d 7587 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7588
7589 /* compute bitmask from p1 value */
7590 if (IS_PINEVIEW(dev))
7591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7592 else {
7593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7594 if (IS_G4X(dev) && reduced_clock)
7595 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7596 }
7597 switch (clock->p2) {
7598 case 5:
7599 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7600 break;
7601 case 7:
7602 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7603 break;
7604 case 10:
7605 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7606 break;
7607 case 14:
7608 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7609 break;
7610 }
7611 if (INTEL_INFO(dev)->gen >= 4)
7612 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7613
190f68c5 7614 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7615 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7616 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7617 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7618 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7619 else
7620 dpll |= PLL_REF_INPUT_DREFCLK;
7621
7622 dpll |= DPLL_VCO_ENABLE;
190f68c5 7623 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7624
eb1cbe48 7625 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7626 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7627 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7628 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7629 }
7630}
7631
f47709a9 7632static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7633 struct intel_crtc_state *crtc_state,
f47709a9 7634 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7635 int num_connectors)
7636{
f47709a9 7637 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7638 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7639 u32 dpll;
190f68c5 7640 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7641
190f68c5 7642 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7643
eb1cbe48
DV		 7644 dpll = DPLL_VGA_MODE_DIS;
7645
a93e255f 7646 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7647 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7648 } else {
7649 if (clock->p1 == 2)
7650 dpll |= PLL_P1_DIVIDE_BY_TWO;
7651 else
7652 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7653 if (clock->p2 == 4)
7654 dpll |= PLL_P2_DIVIDE_BY_4;
7655 }
7656
a93e255f 7657 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7658 dpll |= DPLL_DVO_2X_MODE;
7659
a93e255f 7660 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7661 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7662 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7663 else
7664 dpll |= PLL_REF_INPUT_DREFCLK;
7665
7666 dpll |= DPLL_VCO_ENABLE;
190f68c5 7667 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7668}
7669
8a654f3b 7670static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7671{
7672 struct drm_device *dev = intel_crtc->base.dev;
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7675 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7676 struct drm_display_mode *adjusted_mode =
6e3c9717 7677 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7678 uint32_t crtc_vtotal, crtc_vblank_end;
7679 int vsyncshift = 0;
4d8a62ea
DV		 7680
7681 /* We need to be careful not to changed the adjusted mode, for otherwise
7682 * the hw state checker will get angry at the mismatch. */
7683 crtc_vtotal = adjusted_mode->crtc_vtotal;
7684 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7685
609aeaca 7686 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7687 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7688 crtc_vtotal -= 1;
7689 crtc_vblank_end -= 1;
609aeaca 7690
409ee761 7691 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7692 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7693 else
7694 vsyncshift = adjusted_mode->crtc_hsync_start -
7695 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7696 if (vsyncshift < 0)
7697 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7698 }
7699
7700 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7701 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7702
fe2b8f9d 7703 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7704 (adjusted_mode->crtc_hdisplay - 1) |
7705 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7706 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7707 (adjusted_mode->crtc_hblank_start - 1) |
7708 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7709 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7710 (adjusted_mode->crtc_hsync_start - 1) |
7711 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7712
fe2b8f9d 7713 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7714 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7715 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7716 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7717 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7718 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7719 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7720 (adjusted_mode->crtc_vsync_start - 1) |
7721 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7722
b5e508d4
PZ		 7723 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7724 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7725 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7726 * bits. */
7727 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7728 (pipe == PIPE_B || pipe == PIPE_C))
7729 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7730
b0e77b9c
PZ		 7731 /* pipesrc controls the size that is scaled from, which should
7732 * always be the user's requested size.
7733 */
7734 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7735 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7736 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7737}
7738
1bd1bd80 7739static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7740 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7741{
7742 struct drm_device *dev = crtc->base.dev;
7743 struct drm_i915_private *dev_priv = dev->dev_private;
7744 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7745 uint32_t tmp;
7746
7747 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7748 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7749 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7750 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7751 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7752 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7753 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7754 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7755 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7756
7757 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7758 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7759 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7760 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7761 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7762 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7763 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7764 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7765 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7766
7767 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7768 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7769 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7770 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7771 }
7772
7773 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7774 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7775 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7776
2d112de7
ACO		 7777 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7778 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7779}
7780
f6a83288 7781void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7782 struct intel_crtc_state *pipe_config)
babea61d 7783{
2d112de7
ACO		 7784 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7785 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7786 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7787 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7788
2d112de7
ACO		 7789 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7790 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7791 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7792 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7793
2d112de7 7794 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7795
2d112de7
ACO		 7796 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7797 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7798}
7799
84b046f3
DV		 7800static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7801{
7802 struct drm_device *dev = intel_crtc->base.dev;
7803 struct drm_i915_private *dev_priv = dev->dev_private;
7804 uint32_t pipeconf;
7805
9f11a9e4 7806 pipeconf = 0;
84b046f3 7807
b6b5d049
VS		 7808 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7809 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7810 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7811
6e3c9717 7812 if (intel_crtc->config->double_wide)
cf532bb2 7813 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7814
ff9ce46e
DV		 7815 /* only g4x and later have fancy bpc/dither controls */
7816 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7817 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7818 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7819 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7820 PIPECONF_DITHER_TYPE_SP;
84b046f3 7821
6e3c9717 7822 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7823 case 18:
7824 pipeconf |= PIPECONF_6BPC;
7825 break;
7826 case 24:
7827 pipeconf |= PIPECONF_8BPC;
7828 break;
7829 case 30:
7830 pipeconf |= PIPECONF_10BPC;
7831 break;
7832 default:
7833 /* Case prevented by intel_choose_pipe_bpp_dither. */
7834 BUG();
84b046f3
DV		 7835 }
7836 }
7837
7838 if (HAS_PIPE_CXSR(dev)) {
7839 if (intel_crtc->lowfreq_avail) {
7840 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7841 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7842 } else {
7843 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7844 }
7845 }
7846
6e3c9717 7847 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7848 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7849 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7850 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7851 else
7852 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7853 } else
84b046f3
DV		 7854 pipeconf |= PIPECONF_PROGRESSIVE;
7855
6e3c9717 7856 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7857 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7858
84b046f3
DV		 7859 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7860 POSTING_READ(PIPECONF(intel_crtc->pipe));
7861}
7862
190f68c5
ACO		 7863static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7864 struct intel_crtc_state *crtc_state)
79e53945 7865{
c7653199 7866 struct drm_device *dev = crtc->base.dev;
79e53945 7867 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7868 int refclk, num_connectors = 0;
652c393a 7869 intel_clock_t clock, reduced_clock;
a16af721 7870 bool ok, has_reduced_clock = false;
e9fd1c02 7871 bool is_lvds = false, is_dsi = false;
5eddb70b 7872 struct intel_encoder *encoder;
d4906093 7873 const intel_limit_t *limit;
55bb9992 7874 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7875 struct drm_connector *connector;
55bb9992
ACO		 7876 struct drm_connector_state *connector_state;
7877 int i;
79e53945 7878
dd3cd74a
ACO		 7879 memset(&crtc_state->dpll_hw_state, 0,
7880 sizeof(crtc_state->dpll_hw_state));
7881
da3ced29 7882 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7883 if (connector_state->crtc != &crtc->base)
7884 continue;
7885
7886 encoder = to_intel_encoder(connector_state->best_encoder);
7887
5eddb70b 7888 switch (encoder->type) {
79e53945
JB		 7889 case INTEL_OUTPUT_LVDS:
7890 is_lvds = true;
7891 break;
e9fd1c02
JN		 7892 case INTEL_OUTPUT_DSI:
7893 is_dsi = true;
7894 break;
6847d71b
PZ		 7895 default:
7896 break;
79e53945 7897 }
43565a06 7898
c751ce4f 7899 num_connectors++;
79e53945
JB		 7900 }
7901
f2335330 7902 if (is_dsi)
5b18e57c 7903 return 0;
f2335330 7904
190f68c5 7905 if (!crtc_state->clock_set) {
a93e255f 7906 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7907
e9fd1c02
JN		 7908 /*
7909 * Returns a set of divisors for the desired target clock with
7910 * the given refclk, or FALSE. The returned values represent
7911 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7912 * 2) / p1 / p2.
7913 */
a93e255f
ACO		 7914 limit = intel_limit(crtc_state, refclk);
7915 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7916 crtc_state->port_clock,
e9fd1c02 7917 refclk, NULL, &clock);
f2335330 7918 if (!ok) {
e9fd1c02
JN		 7919 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7920 return -EINVAL;
7921 }
79e53945 7922
f2335330
JN		 7923 if (is_lvds && dev_priv->lvds_downclock_avail) {
7924 /*
7925 * Ensure we match the reduced clock's P to the target
7926 * clock. If the clocks don't match, we can't switch
7927 * the display clock by using the FP0/FP1. In such case
7928 * we will disable the LVDS downclock feature.
7929 */
7930 has_reduced_clock =
a93e255f 7931 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7932 dev_priv->lvds_downclock,
7933 refclk, &clock,
7934 &reduced_clock);
7935 }
7936 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7937 crtc_state->dpll.n = clock.n;
7938 crtc_state->dpll.m1 = clock.m1;
7939 crtc_state->dpll.m2 = clock.m2;
7940 crtc_state->dpll.p1 = clock.p1;
7941 crtc_state->dpll.p2 = clock.p2;
f47709a9 7942 }
7026d4ac 7943
e9fd1c02 7944 if (IS_GEN2(dev)) {
190f68c5 7945 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7946 has_reduced_clock ? &reduced_clock : NULL,
7947 num_connectors);
9d556c99 7948 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7949 chv_update_pll(crtc, crtc_state);
e9fd1c02 7950 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7951 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7952 } else {
190f68c5 7953 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7954 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7955 num_connectors);
e9fd1c02 7956 }
79e53945 7957
c8f7a0db 7958 return 0;
f564048e
EA		 7959}
7960
2fa2fe9a 7961static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7962 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7963{
7964 struct drm_device *dev = crtc->base.dev;
7965 struct drm_i915_private *dev_priv = dev->dev_private;
7966 uint32_t tmp;
7967
dc9e7dec
VS		 7968 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7969 return;
7970
2fa2fe9a 7971 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7972 if (!(tmp & PFIT_ENABLE))
7973 return;
2fa2fe9a 7974
06922821 7975 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7976 if (INTEL_INFO(dev)->gen < 4) {
7977 if (crtc->pipe != PIPE_B)
7978 return;
2fa2fe9a
DV		 7979 } else {
7980 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7981 return;
7982 }
7983
06922821 7984 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7985 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7986 if (INTEL_INFO(dev)->gen < 5)
7987 pipe_config->gmch_pfit.lvds_border_bits =
7988 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7989}
7990
acbec814 7991static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7992 struct intel_crtc_state *pipe_config)
acbec814
JB		 7993{
7994 struct drm_device *dev = crtc->base.dev;
7995 struct drm_i915_private *dev_priv = dev->dev_private;
7996 int pipe = pipe_config->cpu_transcoder;
7997 intel_clock_t clock;
7998 u32 mdiv;
662c6ecb 7999 int refclk = 100000;
acbec814 8000
f573de5a
SK		 8001 /* In case of MIPI DPLL will not even be used */
8002 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8003 return;
8004
a580516d 8005 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8006 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8007 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8008
8009 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8010 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8011 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8012 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8013 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8014
f646628b 8015 vlv_clock(refclk, &clock);
acbec814 8016
f646628b
VS		 8017 /* clock.dot is the fast clock */
8018 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8019}
8020
5724dbd1
DL		 8021static void
8022i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8023 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8024{
8025 struct drm_device *dev = crtc->base.dev;
8026 struct drm_i915_private *dev_priv = dev->dev_private;
8027 u32 val, base, offset;
8028 int pipe = crtc->pipe, plane = crtc->plane;
8029 int fourcc, pixel_format;
6761dd31 8030 unsigned int aligned_height;
b113d5ee 8031 struct drm_framebuffer *fb;
1b842c89 8032 struct intel_framebuffer *intel_fb;
1ad292b5 8033
42a7b088
DL		 8034 val = I915_READ(DSPCNTR(plane));
8035 if (!(val & DISPLAY_PLANE_ENABLE))
8036 return;
8037
d9806c9f 8038 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8039 if (!intel_fb) {
1ad292b5
JB		 8040 DRM_DEBUG_KMS("failed to alloc fb\n");
8041 return;
8042 }
8043
1b842c89
DL		 8044 fb = &intel_fb->base;
8045
18c5247e
DV		 8046 if (INTEL_INFO(dev)->gen >= 4) {
8047 if (val & DISPPLANE_TILED) {
49af449b 8048 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8049 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8050 }
8051 }
1ad292b5
JB		 8052
8053 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8054 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8055 fb->pixel_format = fourcc;
8056 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8057
8058 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8059 if (plane_config->tiling)
1ad292b5
JB		 8060 offset = I915_READ(DSPTILEOFF(plane));
8061 else
8062 offset = I915_READ(DSPLINOFF(plane));
8063 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8064 } else {
8065 base = I915_READ(DSPADDR(plane));
8066 }
8067 plane_config->base = base;
8068
8069 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8070 fb->width = ((val >> 16) & 0xfff) + 1;
8071 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8072
8073 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8074 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8075
b113d5ee 8076 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8077 fb->pixel_format,
8078 fb->modifier[0]);
1ad292b5 8079
f37b5c2b 8080 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8081
2844a921
DL		 8082 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8083 pipe_name(pipe), plane, fb->width, fb->height,
8084 fb->bits_per_pixel, base, fb->pitches[0],
8085 plane_config->size);
1ad292b5 8086
2d14030b 8087 plane_config->fb = intel_fb;
1ad292b5
JB		 8088}
8089
70b23a98 8090static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8091 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8092{
8093 struct drm_device *dev = crtc->base.dev;
8094 struct drm_i915_private *dev_priv = dev->dev_private;
8095 int pipe = pipe_config->cpu_transcoder;
8096 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8097 intel_clock_t clock;
8098 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8099 int refclk = 100000;
8100
a580516d 8101 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8102 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8103 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8104 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8105 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8106 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8107
8108 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8109 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8110 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8111 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8112 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8113
8114 chv_clock(refclk, &clock);
8115
8116 /* clock.dot is the fast clock */
8117 pipe_config->port_clock = clock.dot / 5;
8118}
8119
0e8ffe1b 8120static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8121 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8122{
8123 struct drm_device *dev = crtc->base.dev;
8124 struct drm_i915_private *dev_priv = dev->dev_private;
8125 uint32_t tmp;
8126
f458ebbc
DV		 8127 if (!intel_display_power_is_enabled(dev_priv,
8128 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8129 return false;
8130
e143a21c 8131 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8132 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8133
0e8ffe1b
DV		 8134 tmp = I915_READ(PIPECONF(crtc->pipe));
8135 if (!(tmp & PIPECONF_ENABLE))
8136 return false;
8137
42571aef
VS		 8138 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8139 switch (tmp & PIPECONF_BPC_MASK) {
8140 case PIPECONF_6BPC:
8141 pipe_config->pipe_bpp = 18;
8142 break;
8143 case PIPECONF_8BPC:
8144 pipe_config->pipe_bpp = 24;
8145 break;
8146 case PIPECONF_10BPC:
8147 pipe_config->pipe_bpp = 30;
8148 break;
8149 default:
8150 break;
8151 }
8152 }
8153
b5a9fa09
DV		 8154 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8155 pipe_config->limited_color_range = true;
8156
282740f7
VS		 8157 if (INTEL_INFO(dev)->gen < 4)
8158 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8159
1bd1bd80
DV		 8160 intel_get_pipe_timings(crtc, pipe_config);
8161
2fa2fe9a
DV		 8162 i9xx_get_pfit_config(crtc, pipe_config);
8163
6c49f241
DV		 8164 if (INTEL_INFO(dev)->gen >= 4) {
8165 tmp = I915_READ(DPLL_MD(crtc->pipe));
8166 pipe_config->pixel_multiplier =
8167 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8168 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8169 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8170 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8171 tmp = I915_READ(DPLL(crtc->pipe));
8172 pipe_config->pixel_multiplier =
8173 ((tmp & SDVO_MULTIPLIER_MASK)
8174 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8175 } else {
8176 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8177 * port and will be fixed up in the encoder->get_config
8178 * function. */
8179 pipe_config->pixel_multiplier = 1;
8180 }
8bcc2795
DV		 8181 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8182 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8183 /*
8184 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8185 * on 830. Filter it out here so that we don't
8186 * report errors due to that.
8187 */
8188 if (IS_I830(dev))
8189 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8190
8bcc2795
DV		 8191 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8192 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8193 } else {
8194 /* Mask out read-only status bits. */
8195 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8196 DPLL_PORTC_READY_MASK |
8197 DPLL_PORTB_READY_MASK);
8bcc2795 8198 }
6c49f241 8199
70b23a98
VS		 8200 if (IS_CHERRYVIEW(dev))
8201 chv_crtc_clock_get(crtc, pipe_config);
8202 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8203 vlv_crtc_clock_get(crtc, pipe_config);
8204 else
8205 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8206
0e8ffe1b
DV		 8207 return true;
8208}
8209
dde86e2d 8210static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8211{
8212 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8213 struct intel_encoder *encoder;
74cfd7ac 8214 u32 val, final;
13d83a67 8215 bool has_lvds = false;
199e5d79 8216 bool has_cpu_edp = false;
199e5d79 8217 bool has_panel = false;
99eb6a01
KP		 8218 bool has_ck505 = false;
8219 bool can_ssc = false;
13d83a67
JB		 8220
8221 /* We need to take the global config into account */
b2784e15 8222 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8223 switch (encoder->type) {
8224 case INTEL_OUTPUT_LVDS:
8225 has_panel = true;
8226 has_lvds = true;
8227 break;
8228 case INTEL_OUTPUT_EDP:
8229 has_panel = true;
2de6905f 8230 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8231 has_cpu_edp = true;
8232 break;
6847d71b
PZ		 8233 default:
8234 break;
13d83a67
JB		 8235 }
8236 }
8237
99eb6a01 8238 if (HAS_PCH_IBX(dev)) {
41aa3448 8239 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8240 can_ssc = has_ck505;
8241 } else {
8242 has_ck505 = false;
8243 can_ssc = true;
8244 }
8245
2de6905f
ID		 8246 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8247 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8248
8249 /* Ironlake: try to setup display ref clock before DPLL
8250 * enabling. This is only under driver's control after
8251 * PCH B stepping, previous chipset stepping should be
8252 * ignoring this setting.
8253 */
74cfd7ac
CW		 8254 val = I915_READ(PCH_DREF_CONTROL);
8255
8256 /* As we must carefully and slowly disable/enable each source in turn,
8257 * compute the final state we want first and check if we need to
8258 * make any changes at all.
8259 */
8260 final = val;
8261 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8262 if (has_ck505)
8263 final |= DREF_NONSPREAD_CK505_ENABLE;
8264 else
8265 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8266
8267 final &= ~DREF_SSC_SOURCE_MASK;
8268 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8269 final &= ~DREF_SSC1_ENABLE;
8270
8271 if (has_panel) {
8272 final |= DREF_SSC_SOURCE_ENABLE;
8273
8274 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8275 final |= DREF_SSC1_ENABLE;
8276
8277 if (has_cpu_edp) {
8278 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8279 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8280 else
8281 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8282 } else
8283 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8284 } else {
8285 final |= DREF_SSC_SOURCE_DISABLE;
8286 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8287 }
8288
8289 if (final == val)
8290 return;
8291
13d83a67 8292 /* Always enable nonspread source */
74cfd7ac 8293 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8294
99eb6a01 8295 if (has_ck505)
74cfd7ac 8296 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8297 else
74cfd7ac 8298 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8299
199e5d79 8300 if (has_panel) {
74cfd7ac
CW		 8301 val &= ~DREF_SSC_SOURCE_MASK;
8302 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8303
199e5d79 8304 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8305 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8306 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8307 val |= DREF_SSC1_ENABLE;
e77166b5 8308 } else
74cfd7ac 8309 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8310
8311 /* Get SSC going before enabling the outputs */
74cfd7ac 8312 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8313 POSTING_READ(PCH_DREF_CONTROL);
8314 udelay(200);
8315
74cfd7ac 8316 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8317
8318 /* Enable CPU source on CPU attached eDP */
199e5d79 8319 if (has_cpu_edp) {
99eb6a01 8320 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8321 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8322 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8323 } else
74cfd7ac 8324 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8325 } else
74cfd7ac 8326 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8327
74cfd7ac 8328 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8329 POSTING_READ(PCH_DREF_CONTROL);
8330 udelay(200);
8331 } else {
8332 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8333
74cfd7ac 8334 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8335
8336 /* Turn off CPU output */
74cfd7ac 8337 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8338
74cfd7ac 8339 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8340 POSTING_READ(PCH_DREF_CONTROL);
8341 udelay(200);
8342
8343 /* Turn off the SSC source */
74cfd7ac
CW		 8344 val &= ~DREF_SSC_SOURCE_MASK;
8345 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8346
8347 /* Turn off SSC1 */
74cfd7ac 8348 val &= ~DREF_SSC1_ENABLE;
199e5d79 8349
74cfd7ac 8350 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8351 POSTING_READ(PCH_DREF_CONTROL);
8352 udelay(200);
8353 }
74cfd7ac
CW		 8354
8355 BUG_ON(val != final);
13d83a67
JB		 8356}
8357
f31f2d55 8358static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8359{
f31f2d55 8360 uint32_t tmp;
dde86e2d 8361
0ff066a9
PZ		 8362 tmp = I915_READ(SOUTH_CHICKEN2);
8363 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8364 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8365
0ff066a9
PZ		 8366 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8367 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8368 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8369
0ff066a9
PZ		 8370 tmp = I915_READ(SOUTH_CHICKEN2);
8371 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8372 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8373
0ff066a9
PZ		 8374 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8375 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8376 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8377}
8378
8379/* WaMPhyProgramming:hsw */
8380static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8381{
8382 uint32_t tmp;
dde86e2d
PZ		 8383
8384 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8385 tmp &= ~(0xFF << 24);
8386 tmp |= (0x12 << 24);
8387 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8388
dde86e2d
PZ		 8389 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8390 tmp |= (1 << 11);
8391 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8392
8393 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8394 tmp |= (1 << 11);
8395 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8396
dde86e2d
PZ		 8397 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8398 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8399 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8400
8401 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8402 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8403 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8404
0ff066a9
PZ		 8405 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8406 tmp &= ~(7 << 13);
8407 tmp |= (5 << 13);
8408 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8409
0ff066a9
PZ		 8410 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8411 tmp &= ~(7 << 13);
8412 tmp |= (5 << 13);
8413 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8414
8415 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8416 tmp &= ~0xFF;
8417 tmp |= 0x1C;
8418 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8419
8420 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8421 tmp &= ~0xFF;
8422 tmp |= 0x1C;
8423 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8424
8425 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8426 tmp &= ~(0xFF << 16);
8427 tmp |= (0x1C << 16);
8428 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8429
8430 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8431 tmp &= ~(0xFF << 16);
8432 tmp |= (0x1C << 16);
8433 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8434
0ff066a9
PZ		 8435 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8436 tmp |= (1 << 27);
8437 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8438
0ff066a9
PZ		 8439 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8440 tmp |= (1 << 27);
8441 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8442
0ff066a9
PZ		 8443 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8444 tmp &= ~(0xF << 28);
8445 tmp |= (4 << 28);
8446 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8447
0ff066a9
PZ		 8448 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8449 tmp &= ~(0xF << 28);
8450 tmp |= (4 << 28);
8451 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8452}
8453
2fa86a1f
PZ		 8454/* Implements 3 different sequences from BSpec chapter "Display iCLK
8455 * Programming" based on the parameters passed:
8456 * - Sequence to enable CLKOUT_DP
8457 * - Sequence to enable CLKOUT_DP without spread
8458 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8459 */
8460static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8461 bool with_fdi)
f31f2d55
PZ		 8462{
8463 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8464 uint32_t reg, tmp;
8465
8466 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8467 with_spread = true;
8468 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8469 with_fdi, "LP PCH doesn't have FDI\n"))
8470 with_fdi = false;
f31f2d55 8471
a580516d 8472 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8473
8474 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8475 tmp &= ~SBI_SSCCTL_DISABLE;
8476 tmp |= SBI_SSCCTL_PATHALT;
8477 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8478
8479 udelay(24);
8480
2fa86a1f
PZ		 8481 if (with_spread) {
8482 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8483 tmp &= ~SBI_SSCCTL_PATHALT;
8484 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8485
2fa86a1f
PZ		 8486 if (with_fdi) {
8487 lpt_reset_fdi_mphy(dev_priv);
8488 lpt_program_fdi_mphy(dev_priv);
8489 }
8490 }
dde86e2d 8491
2fa86a1f
PZ		 8492 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8493 SBI_GEN0 : SBI_DBUFF0;
8494 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8495 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8496 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8497
a580516d 8498 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8499}
8500
47701c3b
PZ		 8501/* Sequence to disable CLKOUT_DP */
8502static void lpt_disable_clkout_dp(struct drm_device *dev)
8503{
8504 struct drm_i915_private *dev_priv = dev->dev_private;
8505 uint32_t reg, tmp;
8506
a580516d 8507 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8508
8509 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8510 SBI_GEN0 : SBI_DBUFF0;
8511 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8512 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8513 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8514
8515 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8516 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8517 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8518 tmp |= SBI_SSCCTL_PATHALT;
8519 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8520 udelay(32);
8521 }
8522 tmp |= SBI_SSCCTL_DISABLE;
8523 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8524 }
8525
a580516d 8526 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8527}
8528
bf8fa3d3
PZ		 8529static void lpt_init_pch_refclk(struct drm_device *dev)
8530{
bf8fa3d3
PZ		 8531 struct intel_encoder *encoder;
8532 bool has_vga = false;
8533
b2784e15 8534 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8535 switch (encoder->type) {
8536 case INTEL_OUTPUT_ANALOG:
8537 has_vga = true;
8538 break;
6847d71b
PZ		 8539 default:
8540 break;
bf8fa3d3
PZ		 8541 }
8542 }
8543
47701c3b
PZ		 8544 if (has_vga)
8545 lpt_enable_clkout_dp(dev, true, true);
8546 else
8547 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8548}
8549
dde86e2d
PZ		 8550/*
8551 * Initialize reference clocks when the driver loads
8552 */
8553void intel_init_pch_refclk(struct drm_device *dev)
8554{
8555 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8556 ironlake_init_pch_refclk(dev);
8557 else if (HAS_PCH_LPT(dev))
8558 lpt_init_pch_refclk(dev);
8559}
8560
55bb9992 8561static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8562{
55bb9992 8563 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8564 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8565 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8566 struct drm_connector *connector;
55bb9992 8567 struct drm_connector_state *connector_state;
d9d444cb 8568 struct intel_encoder *encoder;
55bb9992 8569 int num_connectors = 0, i;
d9d444cb
JB		 8570 bool is_lvds = false;
8571
da3ced29 8572 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8573 if (connector_state->crtc != crtc_state->base.crtc)
8574 continue;
8575
8576 encoder = to_intel_encoder(connector_state->best_encoder);
8577
d9d444cb
JB		 8578 switch (encoder->type) {
8579 case INTEL_OUTPUT_LVDS:
8580 is_lvds = true;
8581 break;
6847d71b
PZ		 8582 default:
8583 break;
d9d444cb
JB		 8584 }
8585 num_connectors++;
8586 }
8587
8588 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8589 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8590 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8591 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8592 }
8593
8594 return 120000;
8595}
8596
6ff93609 8597static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8598{
c8203565 8599 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8601 int pipe = intel_crtc->pipe;
c8203565
PZ		 8602 uint32_t val;
8603
78114071 8604 val = 0;
c8203565 8605
6e3c9717 8606 switch (intel_crtc->config->pipe_bpp) {
c8203565 8607 case 18:
dfd07d72 8608 val |= PIPECONF_6BPC;
c8203565
PZ		 8609 break;
8610 case 24:
dfd07d72 8611 val |= PIPECONF_8BPC;
c8203565
PZ		 8612 break;
8613 case 30:
dfd07d72 8614 val |= PIPECONF_10BPC;
c8203565
PZ		 8615 break;
8616 case 36:
dfd07d72 8617 val |= PIPECONF_12BPC;
c8203565
PZ		 8618 break;
8619 default:
cc769b62
PZ		 8620 /* Case prevented by intel_choose_pipe_bpp_dither. */
8621 BUG();
c8203565
PZ		 8622 }
8623
6e3c9717 8624 if (intel_crtc->config->dither)
c8203565
PZ		 8625 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8626
6e3c9717 8627 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8628 val |= PIPECONF_INTERLACED_ILK;
8629 else
8630 val |= PIPECONF_PROGRESSIVE;
8631
6e3c9717 8632 if (intel_crtc->config->limited_color_range)
3685a8f3 8633 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8634
c8203565
PZ		 8635 I915_WRITE(PIPECONF(pipe), val);
8636 POSTING_READ(PIPECONF(pipe));
8637}
8638
86d3efce
VS		 8639/*
8640 * Set up the pipe CSC unit.
8641 *
8642 * Currently only full range RGB to limited range RGB conversion
8643 * is supported, but eventually this should handle various
8644 * RGB<->YCbCr scenarios as well.
8645 */
50f3b016 8646static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8647{
8648 struct drm_device *dev = crtc->dev;
8649 struct drm_i915_private *dev_priv = dev->dev_private;
8650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8651 int pipe = intel_crtc->pipe;
8652 uint16_t coeff = 0x7800; /* 1.0 */
8653
8654 /*
8655 * TODO: Check what kind of values actually come out of the pipe
8656 * with these coeff/postoff values and adjust to get the best
8657 * accuracy. Perhaps we even need to take the bpc value into
8658 * consideration.
8659 */
8660
6e3c9717 8661 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8662 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8663
8664 /*
8665 * GY/GU and RY/RU should be the other way around according
8666 * to BSpec, but reality doesn't agree. Just set them up in
8667 * a way that results in the correct picture.
8668 */
8669 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8670 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8671
8672 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8673 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8674
8675 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8676 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8677
8678 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8679 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8680 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8681
8682 if (INTEL_INFO(dev)->gen > 6) {
8683 uint16_t postoff = 0;
8684
6e3c9717 8685 if (intel_crtc->config->limited_color_range)
32cf0cb0 8686 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8687
8688 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8689 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8690 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8691
8692 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8693 } else {
8694 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8695
6e3c9717 8696 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8697 mode |= CSC_BLACK_SCREEN_OFFSET;
8698
8699 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8700 }
8701}
8702
6ff93609 8703static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8704{
756f85cf
PZ		 8705 struct drm_device *dev = crtc->dev;
8706 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8708 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8709 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8710 uint32_t val;
8711
3eff4faa 8712 val = 0;
ee2b0b38 8713
6e3c9717 8714 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8715 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8716
6e3c9717 8717 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8718 val |= PIPECONF_INTERLACED_ILK;
8719 else
8720 val |= PIPECONF_PROGRESSIVE;
8721
702e7a56
PZ		 8722 I915_WRITE(PIPECONF(cpu_transcoder), val);
8723 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8724
8725 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8726 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8727
3cdf122c 8728 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8729 val = 0;
8730
6e3c9717 8731 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8732 case 18:
8733 val |= PIPEMISC_DITHER_6_BPC;
8734 break;
8735 case 24:
8736 val |= PIPEMISC_DITHER_8_BPC;
8737 break;
8738 case 30:
8739 val |= PIPEMISC_DITHER_10_BPC;
8740 break;
8741 case 36:
8742 val |= PIPEMISC_DITHER_12_BPC;
8743 break;
8744 default:
8745 /* Case prevented by pipe_config_set_bpp. */
8746 BUG();
8747 }
8748
6e3c9717 8749 if (intel_crtc->config->dither)
756f85cf
PZ		 8750 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8751
8752 I915_WRITE(PIPEMISC(pipe), val);
8753 }
ee2b0b38
PZ		 8754}
8755
6591c6e4 8756static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8757 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8758 intel_clock_t *clock,
8759 bool *has_reduced_clock,
8760 intel_clock_t *reduced_clock)
8761{
8762 struct drm_device *dev = crtc->dev;
8763 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8764 int refclk;
d4906093 8765 const intel_limit_t *limit;
a16af721 8766 bool ret, is_lvds = false;
79e53945 8767
a93e255f 8768 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8769
55bb9992 8770 refclk = ironlake_get_refclk(crtc_state);
79e53945 8771
d4906093
ML		 8772 /*
8773 * Returns a set of divisors for the desired target clock with the given
8774 * refclk, or FALSE. The returned values represent the clock equation:
8775 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8776 */
a93e255f
ACO		 8777 limit = intel_limit(crtc_state, refclk);
8778 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8779 crtc_state->port_clock,
ee9300bb 8780 refclk, NULL, clock);
6591c6e4
PZ		 8781 if (!ret)
8782 return false;
cda4b7d3 8783
ddc9003c 8784 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8785 /*
8786 * Ensure we match the reduced clock's P to the target clock.
8787 * If the clocks don't match, we can't switch the display clock
8788 * by using the FP0/FP1. In such case we will disable the LVDS
8789 * downclock feature.
8790 */
ee9300bb 8791 *has_reduced_clock =
a93e255f 8792 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8793 dev_priv->lvds_downclock,
8794 refclk, clock,
8795 reduced_clock);
652c393a 8796 }
61e9653f 8797
6591c6e4
PZ		 8798 return true;
8799}
8800
d4b1931c
PZ		 8801int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8802{
8803 /*
8804 * Account for spread spectrum to avoid
8805 * oversubscribing the link. Max center spread
8806 * is 2.5%; use 5% for safety's sake.
8807 */
8808 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8809 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8810}
8811
7429e9d4 8812static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8813{
7429e9d4 8814 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8815}
8816
de13a2e3 8817static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8818 struct intel_crtc_state *crtc_state,
7429e9d4 8819 u32 *fp,
9a7c7890 8820 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8821{
de13a2e3 8822 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8823 struct drm_device *dev = crtc->dev;
8824 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8825 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8826 struct drm_connector *connector;
55bb9992
ACO		 8827 struct drm_connector_state *connector_state;
8828 struct intel_encoder *encoder;
de13a2e3 8829 uint32_t dpll;
55bb9992 8830 int factor, num_connectors = 0, i;
09ede541 8831 bool is_lvds = false, is_sdvo = false;
79e53945 8832
da3ced29 8833 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8834 if (connector_state->crtc != crtc_state->base.crtc)
8835 continue;
8836
8837 encoder = to_intel_encoder(connector_state->best_encoder);
8838
8839 switch (encoder->type) {
79e53945
JB		 8840 case INTEL_OUTPUT_LVDS:
8841 is_lvds = true;
8842 break;
8843 case INTEL_OUTPUT_SDVO:
7d57382e 8844 case INTEL_OUTPUT_HDMI:
79e53945 8845 is_sdvo = true;
79e53945 8846 break;
6847d71b
PZ		 8847 default:
8848 break;
79e53945 8849 }
43565a06 8850
c751ce4f 8851 num_connectors++;
79e53945 8852 }
79e53945 8853
c1858123 8854 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8855 factor = 21;
8856 if (is_lvds) {
8857 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8858 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8859 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8860 factor = 25;
190f68c5 8861 } else if (crtc_state->sdvo_tv_clock)
8febb297 8862 factor = 20;
c1858123 8863
190f68c5 8864 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8865 *fp |= FP_CB_TUNE;
2c07245f 8866
9a7c7890
DV		 8867 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8868 *fp2 |= FP_CB_TUNE;
8869
5eddb70b 8870 dpll = 0;
2c07245f 8871
a07d6787
EA		 8872 if (is_lvds)
8873 dpll |= DPLLB_MODE_LVDS;
8874 else
8875 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8876
190f68c5 8877 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8878 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8879
8880 if (is_sdvo)
4a33e48d 8881 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8882 if (crtc_state->has_dp_encoder)
4a33e48d 8883 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8884
a07d6787 8885 /* compute bitmask from p1 value */
190f68c5 8886 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8887 /* also FPA1 */
190f68c5 8888 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8889
190f68c5 8890 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8891 case 5:
8892 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8893 break;
8894 case 7:
8895 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8896 break;
8897 case 10:
8898 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8899 break;
8900 case 14:
8901 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8902 break;
79e53945
JB		 8903 }
8904
b4c09f3b 8905 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8906 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8907 else
8908 dpll |= PLL_REF_INPUT_DREFCLK;
8909
959e16d6 8910 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8911}
8912
190f68c5
ACO		 8913static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8914 struct intel_crtc_state *crtc_state)
de13a2e3 8915{
c7653199 8916 struct drm_device *dev = crtc->base.dev;
de13a2e3 8917 intel_clock_t clock, reduced_clock;
cbbab5bd 8918 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8919 bool ok, has_reduced_clock = false;
8b47047b 8920 bool is_lvds = false;
e2b78267 8921 struct intel_shared_dpll *pll;
de13a2e3 8922
dd3cd74a
ACO		 8923 memset(&crtc_state->dpll_hw_state, 0,
8924 sizeof(crtc_state->dpll_hw_state));
8925
409ee761 8926 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8927
5dc5298b
PZ		 8928 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8929 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8930
190f68c5 8931 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8932 &has_reduced_clock, &reduced_clock);
190f68c5 8933 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8934 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8935 return -EINVAL;
79e53945 8936 }
f47709a9 8937 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8938 if (!crtc_state->clock_set) {
8939 crtc_state->dpll.n = clock.n;
8940 crtc_state->dpll.m1 = clock.m1;
8941 crtc_state->dpll.m2 = clock.m2;
8942 crtc_state->dpll.p1 = clock.p1;
8943 crtc_state->dpll.p2 = clock.p2;
f47709a9 8944 }
79e53945 8945
5dc5298b 8946 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8947 if (crtc_state->has_pch_encoder) {
8948 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8949 if (has_reduced_clock)
7429e9d4 8950 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8951
190f68c5 8952 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8953 &fp, &reduced_clock,
8954 has_reduced_clock ? &fp2 : NULL);
8955
190f68c5
ACO		 8956 crtc_state->dpll_hw_state.dpll = dpll;
8957 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8958 if (has_reduced_clock)
190f68c5 8959 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8960 else
190f68c5 8961 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8962
190f68c5 8963 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8964 if (pll == NULL) {
84f44ce7 8965 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8966 pipe_name(crtc->pipe));
4b645f14
JB		 8967 return -EINVAL;
8968 }
3fb37703 8969 }
79e53945 8970
ab585dea 8971 if (is_lvds && has_reduced_clock)
c7653199 8972 crtc->lowfreq_avail = true;
bcd644e0 8973 else
c7653199 8974 crtc->lowfreq_avail = false;
e2b78267 8975
c8f7a0db 8976 return 0;
79e53945
JB		 8977}
8978
eb14cb74
VS		 8979static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8980 struct intel_link_m_n *m_n)
8981{
8982 struct drm_device *dev = crtc->base.dev;
8983 struct drm_i915_private *dev_priv = dev->dev_private;
8984 enum pipe pipe = crtc->pipe;
8985
8986 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8987 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8988 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8989 & ~TU_SIZE_MASK;
8990 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8991 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8992 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8993}
8994
8995static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8996 enum transcoder transcoder,
b95af8be
VK		 8997 struct intel_link_m_n *m_n,
8998 struct intel_link_m_n *m2_n2)
72419203
DV		 8999{
9000 struct drm_device *dev = crtc->base.dev;
9001 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 9002 enum pipe pipe = crtc->pipe;
72419203 9003
eb14cb74
VS		 9004 if (INTEL_INFO(dev)->gen >= 5) {
9005 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9006 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9007 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9008 & ~TU_SIZE_MASK;
9009 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9010 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9011 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9012 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9013 * gen < 8) and if DRRS is supported (to make sure the
9014 * registers are not unnecessarily read).
9015 */
9016 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9017 crtc->config->has_drrs) {
b95af8be
VK		 9018 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9019 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9020 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9021 & ~TU_SIZE_MASK;
9022 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9023 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9024 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9025 }
eb14cb74
VS		 9026 } else {
9027 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9028 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9029 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9030 & ~TU_SIZE_MASK;
9031 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9032 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9033 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9034 }
9035}
9036
9037void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9038 struct intel_crtc_state *pipe_config)
eb14cb74 9039{
681a8504 9040 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9041 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9042 else
9043 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9044 &pipe_config->dp_m_n,
9045 &pipe_config->dp_m2_n2);
eb14cb74 9046}
72419203 9047
eb14cb74 9048static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9049 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9050{
9051 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9052 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9053}
9054
bd2e244f 9055static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9056 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9057{
9058 struct drm_device *dev = crtc->base.dev;
9059 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9060 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9061 uint32_t ps_ctrl = 0;
9062 int id = -1;
9063 int i;
bd2e244f 9064
a1b2278e
CK		 9065 /* find scaler attached to this pipe */
9066 for (i = 0; i < crtc->num_scalers; i++) {
9067 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9068 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9069 id = i;
9070 pipe_config->pch_pfit.enabled = true;
9071 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9072 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9073 break;
9074 }
9075 }
bd2e244f 9076
a1b2278e
CK		 9077 scaler_state->scaler_id = id;
9078 if (id >= 0) {
9079 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9080 } else {
9081 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9082 }
9083}
9084
5724dbd1
DL		 9085static void
9086skylake_get_initial_plane_config(struct intel_crtc *crtc,
9087 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9088{
9089 struct drm_device *dev = crtc->base.dev;
9090 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9091 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9092 int pipe = crtc->pipe;
9093 int fourcc, pixel_format;
6761dd31 9094 unsigned int aligned_height;
bc8d7dff 9095 struct drm_framebuffer *fb;
1b842c89 9096 struct intel_framebuffer *intel_fb;
bc8d7dff 9097
d9806c9f 9098 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9099 if (!intel_fb) {
bc8d7dff
DL		 9100 DRM_DEBUG_KMS("failed to alloc fb\n");
9101 return;
9102 }
9103
1b842c89
DL		 9104 fb = &intel_fb->base;
9105
bc8d7dff 9106 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9107 if (!(val & PLANE_CTL_ENABLE))
9108 goto error;
9109
bc8d7dff
DL		 9110 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9111 fourcc = skl_format_to_fourcc(pixel_format,
9112 val & PLANE_CTL_ORDER_RGBX,
9113 val & PLANE_CTL_ALPHA_MASK);
9114 fb->pixel_format = fourcc;
9115 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9116
40f46283
DL		 9117 tiling = val & PLANE_CTL_TILED_MASK;
9118 switch (tiling) {
9119 case PLANE_CTL_TILED_LINEAR:
9120 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9121 break;
9122 case PLANE_CTL_TILED_X:
9123 plane_config->tiling = I915_TILING_X;
9124 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9125 break;
9126 case PLANE_CTL_TILED_Y:
9127 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9128 break;
9129 case PLANE_CTL_TILED_YF:
9130 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9131 break;
9132 default:
9133 MISSING_CASE(tiling);
9134 goto error;
9135 }
9136
bc8d7dff
DL		 9137 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9138 plane_config->base = base;
9139
9140 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9141
9142 val = I915_READ(PLANE_SIZE(pipe, 0));
9143 fb->height = ((val >> 16) & 0xfff) + 1;
9144 fb->width = ((val >> 0) & 0x1fff) + 1;
9145
9146 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9147 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9148 fb->pixel_format);
bc8d7dff
DL		 9149 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9150
9151 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9152 fb->pixel_format,
9153 fb->modifier[0]);
bc8d7dff 9154
f37b5c2b 9155 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9156
9157 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9158 pipe_name(pipe), fb->width, fb->height,
9159 fb->bits_per_pixel, base, fb->pitches[0],
9160 plane_config->size);
9161
2d14030b 9162 plane_config->fb = intel_fb;
bc8d7dff
DL		 9163 return;
9164
9165error:
9166 kfree(fb);
9167}
9168
2fa2fe9a 9169static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9170 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9171{
9172 struct drm_device *dev = crtc->base.dev;
9173 struct drm_i915_private *dev_priv = dev->dev_private;
9174 uint32_t tmp;
9175
9176 tmp = I915_READ(PF_CTL(crtc->pipe));
9177
9178 if (tmp & PF_ENABLE) {
fd4daa9c 9179 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9180 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9181 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9182
9183 /* We currently do not free assignements of panel fitters on
9184 * ivb/hsw (since we don't use the higher upscaling modes which
9185 * differentiates them) so just WARN about this case for now. */
9186 if (IS_GEN7(dev)) {
9187 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9188 PF_PIPE_SEL_IVB(crtc->pipe));
9189 }
2fa2fe9a 9190 }
79e53945
JB		 9191}
9192
5724dbd1
DL		 9193static void
9194ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9195 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9196{
9197 struct drm_device *dev = crtc->base.dev;
9198 struct drm_i915_private *dev_priv = dev->dev_private;
9199 u32 val, base, offset;
aeee5a49 9200 int pipe = crtc->pipe;
4c6baa59 9201 int fourcc, pixel_format;
6761dd31 9202 unsigned int aligned_height;
b113d5ee 9203 struct drm_framebuffer *fb;
1b842c89 9204 struct intel_framebuffer *intel_fb;
4c6baa59 9205
42a7b088
DL		 9206 val = I915_READ(DSPCNTR(pipe));
9207 if (!(val & DISPLAY_PLANE_ENABLE))
9208 return;
9209
d9806c9f 9210 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9211 if (!intel_fb) {
4c6baa59
JB		 9212 DRM_DEBUG_KMS("failed to alloc fb\n");
9213 return;
9214 }
9215
1b842c89
DL		 9216 fb = &intel_fb->base;
9217
18c5247e
DV		 9218 if (INTEL_INFO(dev)->gen >= 4) {
9219 if (val & DISPPLANE_TILED) {
49af449b 9220 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9221 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9222 }
9223 }
4c6baa59
JB		 9224
9225 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9226 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9227 fb->pixel_format = fourcc;
9228 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9229
aeee5a49 9230 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9231 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9232 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9233 } else {
49af449b 9234 if (plane_config->tiling)
aeee5a49 9235 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9236 else
aeee5a49 9237 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9238 }
9239 plane_config->base = base;
9240
9241 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9242 fb->width = ((val >> 16) & 0xfff) + 1;
9243 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9244
9245 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9246 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9247
b113d5ee 9248 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9249 fb->pixel_format,
9250 fb->modifier[0]);
4c6baa59 9251
f37b5c2b 9252 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9253
2844a921
DL		 9254 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9255 pipe_name(pipe), fb->width, fb->height,
9256 fb->bits_per_pixel, base, fb->pitches[0],
9257 plane_config->size);
b113d5ee 9258
2d14030b 9259 plane_config->fb = intel_fb;
4c6baa59
JB		 9260}
9261
0e8ffe1b 9262static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9263 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9264{
9265 struct drm_device *dev = crtc->base.dev;
9266 struct drm_i915_private *dev_priv = dev->dev_private;
9267 uint32_t tmp;
9268
f458ebbc
DV		 9269 if (!intel_display_power_is_enabled(dev_priv,
9270 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9271 return false;
9272
e143a21c 9273 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9274 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9275
0e8ffe1b
DV		 9276 tmp = I915_READ(PIPECONF(crtc->pipe));
9277 if (!(tmp & PIPECONF_ENABLE))
9278 return false;
9279
42571aef
VS		 9280 switch (tmp & PIPECONF_BPC_MASK) {
9281 case PIPECONF_6BPC:
9282 pipe_config->pipe_bpp = 18;
9283 break;
9284 case PIPECONF_8BPC:
9285 pipe_config->pipe_bpp = 24;
9286 break;
9287 case PIPECONF_10BPC:
9288 pipe_config->pipe_bpp = 30;
9289 break;
9290 case PIPECONF_12BPC:
9291 pipe_config->pipe_bpp = 36;
9292 break;
9293 default:
9294 break;
9295 }
9296
b5a9fa09
DV		 9297 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9298 pipe_config->limited_color_range = true;
9299
ab9412ba 9300 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9301 struct intel_shared_dpll *pll;
9302
88adfff1
DV		 9303 pipe_config->has_pch_encoder = true;
9304
627eb5a3
DV		 9305 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9306 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9307 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9308
9309 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9310
c0d43d62 9311 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9312 pipe_config->shared_dpll =
9313 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9314 } else {
9315 tmp = I915_READ(PCH_DPLL_SEL);
9316 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9317 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9318 else
9319 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9320 }
66e985c0
DV		 9321
9322 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9323
9324 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9325 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9326
9327 tmp = pipe_config->dpll_hw_state.dpll;
9328 pipe_config->pixel_multiplier =
9329 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9330 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9331
9332 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9333 } else {
9334 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9335 }
9336
1bd1bd80
DV		 9337 intel_get_pipe_timings(crtc, pipe_config);
9338
2fa2fe9a
DV		 9339 ironlake_get_pfit_config(crtc, pipe_config);
9340
0e8ffe1b
DV		 9341 return true;
9342}
9343
be256dc7
PZ		 9344static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9345{
9346 struct drm_device *dev = dev_priv->dev;
be256dc7 9347 struct intel_crtc *crtc;
be256dc7 9348
d3fcc808 9349 for_each_intel_crtc(dev, crtc)
e2c719b7 9350 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9351 pipe_name(crtc->pipe));
9352
e2c719b7
RC		 9353 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9354 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9355 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9356 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9357 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9358 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9359 "CPU PWM1 enabled\n");
c5107b87 9360 if (IS_HASWELL(dev))
e2c719b7 9361 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9362 "CPU PWM2 enabled\n");
e2c719b7 9363 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9364 "PCH PWM1 enabled\n");
e2c719b7 9365 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9366 "Utility pin enabled\n");
e2c719b7 9367 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9368
9926ada1
PZ		 9369 /*
9370 * In theory we can still leave IRQs enabled, as long as only the HPD
9371 * interrupts remain enabled. We used to check for that, but since it's
9372 * gen-specific and since we only disable LCPLL after we fully disable
9373 * the interrupts, the check below should be enough.
9374 */
e2c719b7 9375 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9376}
9377
9ccd5aeb
PZ		 9378static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9379{
9380 struct drm_device *dev = dev_priv->dev;
9381
9382 if (IS_HASWELL(dev))
9383 return I915_READ(D_COMP_HSW);
9384 else
9385 return I915_READ(D_COMP_BDW);
9386}
9387
3c4c9b81
PZ		 9388static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9389{
9390 struct drm_device *dev = dev_priv->dev;
9391
9392 if (IS_HASWELL(dev)) {
9393 mutex_lock(&dev_priv->rps.hw_lock);
9394 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9395 val))
f475dadf 9396 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9397 mutex_unlock(&dev_priv->rps.hw_lock);
9398 } else {
9ccd5aeb
PZ		 9399 I915_WRITE(D_COMP_BDW, val);
9400 POSTING_READ(D_COMP_BDW);
3c4c9b81 9401 }
be256dc7
PZ		 9402}
9403
9404/*
9405 * This function implements pieces of two sequences from BSpec:
9406 * - Sequence for display software to disable LCPLL
9407 * - Sequence for display software to allow package C8+
9408 * The steps implemented here are just the steps that actually touch the LCPLL
9409 * register. Callers should take care of disabling all the display engine
9410 * functions, doing the mode unset, fixing interrupts, etc.
9411 */
6ff58d53
PZ		 9412static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9413 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9414{
9415 uint32_t val;
9416
9417 assert_can_disable_lcpll(dev_priv);
9418
9419 val = I915_READ(LCPLL_CTL);
9420
9421 if (switch_to_fclk) {
9422 val |= LCPLL_CD_SOURCE_FCLK;
9423 I915_WRITE(LCPLL_CTL, val);
9424
9425 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9426 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9427 DRM_ERROR("Switching to FCLK failed\n");
9428
9429 val = I915_READ(LCPLL_CTL);
9430 }
9431
9432 val |= LCPLL_PLL_DISABLE;
9433 I915_WRITE(LCPLL_CTL, val);
9434 POSTING_READ(LCPLL_CTL);
9435
9436 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9437 DRM_ERROR("LCPLL still locked\n");
9438
9ccd5aeb 9439 val = hsw_read_dcomp(dev_priv);
be256dc7 9440 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9441 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9442 ndelay(100);
9443
9ccd5aeb
PZ		 9444 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9445 1))
be256dc7
PZ		 9446 DRM_ERROR("D_COMP RCOMP still in progress\n");
9447
9448 if (allow_power_down) {
9449 val = I915_READ(LCPLL_CTL);
9450 val |= LCPLL_POWER_DOWN_ALLOW;
9451 I915_WRITE(LCPLL_CTL, val);
9452 POSTING_READ(LCPLL_CTL);
9453 }
9454}
9455
9456/*
9457 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9458 * source.
9459 */
6ff58d53 9460static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9461{
9462 uint32_t val;
9463
9464 val = I915_READ(LCPLL_CTL);
9465
9466 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9467 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9468 return;
9469
a8a8bd54
PZ		 9470 /*
9471 * Make sure we're not on PC8 state before disabling PC8, otherwise
9472 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9473 */
59bad947 9474 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9475
be256dc7
PZ		 9476 if (val & LCPLL_POWER_DOWN_ALLOW) {
9477 val &= ~LCPLL_POWER_DOWN_ALLOW;
9478 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9479 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9480 }
9481
9ccd5aeb 9482 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9483 val |= D_COMP_COMP_FORCE;
9484 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9485 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9486
9487 val = I915_READ(LCPLL_CTL);
9488 val &= ~LCPLL_PLL_DISABLE;
9489 I915_WRITE(LCPLL_CTL, val);
9490
9491 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9492 DRM_ERROR("LCPLL not locked yet\n");
9493
9494 if (val & LCPLL_CD_SOURCE_FCLK) {
9495 val = I915_READ(LCPLL_CTL);
9496 val &= ~LCPLL_CD_SOURCE_FCLK;
9497 I915_WRITE(LCPLL_CTL, val);
9498
9499 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9500 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9501 DRM_ERROR("Switching back to LCPLL failed\n");
9502 }
215733fa 9503
59bad947 9504 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9505 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9506}
9507
765dab67
PZ		 9508/*
9509 * Package states C8 and deeper are really deep PC states that can only be
9510 * reached when all the devices on the system allow it, so even if the graphics
9511 * device allows PC8+, it doesn't mean the system will actually get to these
9512 * states. Our driver only allows PC8+ when going into runtime PM.
9513 *
9514 * The requirements for PC8+ are that all the outputs are disabled, the power
9515 * well is disabled and most interrupts are disabled, and these are also
9516 * requirements for runtime PM. When these conditions are met, we manually do
9517 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9518 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9519 * hang the machine.
9520 *
9521 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9522 * the state of some registers, so when we come back from PC8+ we need to
9523 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9524 * need to take care of the registers kept by RC6. Notice that this happens even
9525 * if we don't put the device in PCI D3 state (which is what currently happens
9526 * because of the runtime PM support).
9527 *
9528 * For more, read "Display Sequences for Package C8" on the hardware
9529 * documentation.
9530 */
a14cb6fc 9531void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9532{
c67a470b
PZ		 9533 struct drm_device *dev = dev_priv->dev;
9534 uint32_t val;
9535
c67a470b
PZ		 9536 DRM_DEBUG_KMS("Enabling package C8+\n");
9537
c67a470b
PZ		 9538 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9539 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9540 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9541 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9542 }
9543
9544 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9545 hsw_disable_lcpll(dev_priv, true, true);
9546}
9547
a14cb6fc 9548void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9549{
9550 struct drm_device *dev = dev_priv->dev;
9551 uint32_t val;
9552
c67a470b
PZ		 9553 DRM_DEBUG_KMS("Disabling package C8+\n");
9554
9555 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9556 lpt_init_pch_refclk(dev);
9557
9558 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9559 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9560 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9561 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9562 }
9563
9564 intel_prepare_ddi(dev);
c67a470b
PZ		 9565}
9566
a821fc46 9567static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9568{
a821fc46 9569 struct drm_device *dev = old_state->dev;
f8437dd1 9570 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9571 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9572 int req_cdclk;
9573
9574 /* see the comment in valleyview_modeset_global_resources */
9575 if (WARN_ON(max_pixclk < 0))
9576 return;
9577
9578 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9579
9580 if (req_cdclk != dev_priv->cdclk_freq)
9581 broxton_set_cdclk(dev, req_cdclk);
9582}
9583
b432e5cf
VS		 9584/* compute the max rate for new configuration */
9585static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9586{
9587 struct drm_device *dev = dev_priv->dev;
9588 struct intel_crtc *intel_crtc;
9589 struct drm_crtc *crtc;
9590 int max_pixel_rate = 0;
9591 int pixel_rate;
9592
9593 for_each_crtc(dev, crtc) {
9594 if (!crtc->state->enable)
9595 continue;
9596
9597 intel_crtc = to_intel_crtc(crtc);
9598 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9599
9600 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9601 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9602 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9603
9604 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9605 }
9606
9607 return max_pixel_rate;
9608}
9609
9610static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9611{
9612 struct drm_i915_private *dev_priv = dev->dev_private;
9613 uint32_t val, data;
9614 int ret;
9615
9616 if (WARN((I915_READ(LCPLL_CTL) &
9617 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9618 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9619 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9620 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9621 "trying to change cdclk frequency with cdclk not enabled\n"))
9622 return;
9623
9624 mutex_lock(&dev_priv->rps.hw_lock);
9625 ret = sandybridge_pcode_write(dev_priv,
9626 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9627 mutex_unlock(&dev_priv->rps.hw_lock);
9628 if (ret) {
9629 DRM_ERROR("failed to inform pcode about cdclk change\n");
9630 return;
9631 }
9632
9633 val = I915_READ(LCPLL_CTL);
9634 val |= LCPLL_CD_SOURCE_FCLK;
9635 I915_WRITE(LCPLL_CTL, val);
9636
9637 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9638 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9639 DRM_ERROR("Switching to FCLK failed\n");
9640
9641 val = I915_READ(LCPLL_CTL);
9642 val &= ~LCPLL_CLK_FREQ_MASK;
9643
9644 switch (cdclk) {
9645 case 450000:
9646 val |= LCPLL_CLK_FREQ_450;
9647 data = 0;
9648 break;
9649 case 540000:
9650 val |= LCPLL_CLK_FREQ_54O_BDW;
9651 data = 1;
9652 break;
9653 case 337500:
9654 val |= LCPLL_CLK_FREQ_337_5_BDW;
9655 data = 2;
9656 break;
9657 case 675000:
9658 val |= LCPLL_CLK_FREQ_675_BDW;
9659 data = 3;
9660 break;
9661 default:
9662 WARN(1, "invalid cdclk frequency\n");
9663 return;
9664 }
9665
9666 I915_WRITE(LCPLL_CTL, val);
9667
9668 val = I915_READ(LCPLL_CTL);
9669 val &= ~LCPLL_CD_SOURCE_FCLK;
9670 I915_WRITE(LCPLL_CTL, val);
9671
9672 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9673 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9674 DRM_ERROR("Switching back to LCPLL failed\n");
9675
9676 mutex_lock(&dev_priv->rps.hw_lock);
9677 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9678 mutex_unlock(&dev_priv->rps.hw_lock);
9679
9680 intel_update_cdclk(dev);
9681
9682 WARN(cdclk != dev_priv->cdclk_freq,
9683 "cdclk requested %d kHz but got %d kHz\n",
9684 cdclk, dev_priv->cdclk_freq);
9685}
9686
9687static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9688 int max_pixel_rate)
9689{
9690 int cdclk;
9691
9692 /*
9693 * FIXME should also account for plane ratio
9694 * once 64bpp pixel formats are supported.
9695 */
9696 if (max_pixel_rate > 540000)
9697 cdclk = 675000;
9698 else if (max_pixel_rate > 450000)
9699 cdclk = 540000;
9700 else if (max_pixel_rate > 337500)
9701 cdclk = 450000;
9702 else
9703 cdclk = 337500;
9704
9705 /*
9706 * FIXME move the cdclk caclulation to
9707 * compute_config() so we can fail gracegully.
9708 */
9709 if (cdclk > dev_priv->max_cdclk_freq) {
9710 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9711 cdclk, dev_priv->max_cdclk_freq);
9712 cdclk = dev_priv->max_cdclk_freq;
9713 }
9714
9715 return cdclk;
9716}
9717
9718static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9719{
9720 struct drm_i915_private *dev_priv = to_i915(state->dev);
9721 struct drm_crtc *crtc;
9722 struct drm_crtc_state *crtc_state;
9723 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9724 int cdclk, i;
9725
9726 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9727
9728 if (cdclk == dev_priv->cdclk_freq)
9729 return 0;
9730
9731 /* add all active pipes to the state */
9732 for_each_crtc(state->dev, crtc) {
9733 if (!crtc->state->enable)
9734 continue;
9735
9736 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9737 if (IS_ERR(crtc_state))
9738 return PTR_ERR(crtc_state);
9739 }
9740
9741 /* disable/enable all currently active pipes while we change cdclk */
9742 for_each_crtc_in_state(state, crtc, crtc_state, i)
9743 if (crtc_state->enable)
9744 crtc_state->mode_changed = true;
9745
9746 return 0;
9747}
9748
9749static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9750{
9751 struct drm_device *dev = state->dev;
9752 struct drm_i915_private *dev_priv = dev->dev_private;
9753 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9754 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9755
9756 if (req_cdclk != dev_priv->cdclk_freq)
9757 broadwell_set_cdclk(dev, req_cdclk);
9758}
9759
190f68c5
ACO		 9760static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9761 struct intel_crtc_state *crtc_state)
09b4ddf9 9762{
190f68c5 9763 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9764 return -EINVAL;
716c2e55 9765
c7653199 9766 crtc->lowfreq_avail = false;
644cef34 9767
c8f7a0db 9768 return 0;
79e53945
JB		 9769}
9770
3760b59c
S		 9771static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9772 enum port port,
9773 struct intel_crtc_state *pipe_config)
9774{
9775 switch (port) {
9776 case PORT_A:
9777 pipe_config->ddi_pll_sel = SKL_DPLL0;
9778 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9779 break;
9780 case PORT_B:
9781 pipe_config->ddi_pll_sel = SKL_DPLL1;
9782 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9783 break;
9784 case PORT_C:
9785 pipe_config->ddi_pll_sel = SKL_DPLL2;
9786 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9787 break;
9788 default:
9789 DRM_ERROR("Incorrect port type\n");
9790 }
9791}
9792
96b7dfb7
S		 9793static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9794 enum port port,
5cec258b 9795 struct intel_crtc_state *pipe_config)
96b7dfb7 9796{
3148ade7 9797 u32 temp, dpll_ctl1;
96b7dfb7
S		 9798
9799 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9800 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9801
9802 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9803 case SKL_DPLL0:
9804 /*
9805 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9806 * of the shared DPLL framework and thus needs to be read out
9807 * separately
9808 */
9809 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9810 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9811 break;
96b7dfb7
S		 9812 case SKL_DPLL1:
9813 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9814 break;
9815 case SKL_DPLL2:
9816 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9817 break;
9818 case SKL_DPLL3:
9819 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9820 break;
96b7dfb7
S		 9821 }
9822}
9823
7d2c8175
DL		 9824static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9825 enum port port,
5cec258b 9826 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9827{
9828 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9829
9830 switch (pipe_config->ddi_pll_sel) {
9831 case PORT_CLK_SEL_WRPLL1:
9832 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9833 break;
9834 case PORT_CLK_SEL_WRPLL2:
9835 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9836 break;
9837 }
9838}
9839
26804afd 9840static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9841 struct intel_crtc_state *pipe_config)
26804afd
DV		 9842{
9843 struct drm_device *dev = crtc->base.dev;
9844 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9845 struct intel_shared_dpll *pll;
26804afd
DV		 9846 enum port port;
9847 uint32_t tmp;
9848
9849 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9850
9851 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9852
96b7dfb7
S		 9853 if (IS_SKYLAKE(dev))
9854 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9855 else if (IS_BROXTON(dev))
9856 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9857 else
9858 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9859
d452c5b6
DV		 9860 if (pipe_config->shared_dpll >= 0) {
9861 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9862
9863 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9864 &pipe_config->dpll_hw_state));
9865 }
9866
26804afd
DV		 9867 /*
9868 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9869 * DDI E. So just check whether this pipe is wired to DDI E and whether
9870 * the PCH transcoder is on.
9871 */
ca370455
DL		 9872 if (INTEL_INFO(dev)->gen < 9 &&
9873 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9874 pipe_config->has_pch_encoder = true;
9875
9876 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9877 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9878 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9879
9880 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9881 }
9882}
9883
0e8ffe1b 9884static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9885 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9886{
9887 struct drm_device *dev = crtc->base.dev;
9888 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9889 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9890 uint32_t tmp;
9891
f458ebbc 9892 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9893 POWER_DOMAIN_PIPE(crtc->pipe)))
9894 return false;
9895
e143a21c 9896 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9897 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9898
eccb140b
DV		 9899 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9900 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9901 enum pipe trans_edp_pipe;
9902 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9903 default:
9904 WARN(1, "unknown pipe linked to edp transcoder\n");
9905 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9906 case TRANS_DDI_EDP_INPUT_A_ON:
9907 trans_edp_pipe = PIPE_A;
9908 break;
9909 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9910 trans_edp_pipe = PIPE_B;
9911 break;
9912 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9913 trans_edp_pipe = PIPE_C;
9914 break;
9915 }
9916
9917 if (trans_edp_pipe == crtc->pipe)
9918 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9919 }
9920
f458ebbc 9921 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9922 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9923 return false;
9924
eccb140b 9925 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9926 if (!(tmp & PIPECONF_ENABLE))
9927 return false;
9928
26804afd 9929 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9930
1bd1bd80
DV		 9931 intel_get_pipe_timings(crtc, pipe_config);
9932
a1b2278e
CK		 9933 if (INTEL_INFO(dev)->gen >= 9) {
9934 skl_init_scalers(dev, crtc, pipe_config);
9935 }
9936
2fa2fe9a 9937 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9938
9939 if (INTEL_INFO(dev)->gen >= 9) {
9940 pipe_config->scaler_state.scaler_id = -1;
9941 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9942 }
9943
bd2e244f 9944 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9945 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9946 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9947 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9948 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9949 else
9950 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9951 }
88adfff1 9952
e59150dc
JB		 9953 if (IS_HASWELL(dev))
9954 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9955 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9956
ebb69c95
CT		 9957 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9958 pipe_config->pixel_multiplier =
9959 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9960 } else {
9961 pipe_config->pixel_multiplier = 1;
9962 }
6c49f241 9963
0e8ffe1b
DV		 9964 return true;
9965}
9966
560b85bb
CW		 9967static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9968{
9969 struct drm_device *dev = crtc->dev;
9970 struct drm_i915_private *dev_priv = dev->dev_private;
9971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9972 uint32_t cntl = 0, size = 0;
560b85bb 9973
dc41c154 9974 if (base) {
3dd512fb
MR		 9975 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9976 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9977 unsigned int stride = roundup_pow_of_two(width) * 4;
9978
9979 switch (stride) {
9980 default:
9981 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9982 width, stride);
9983 stride = 256;
9984 /* fallthrough */
9985 case 256:
9986 case 512:
9987 case 1024:
9988 case 2048:
9989 break;
4b0e333e
CW		 9990 }
9991
dc41c154
VS		 9992 cntl |= CURSOR_ENABLE |
9993 CURSOR_GAMMA_ENABLE |
9994 CURSOR_FORMAT_ARGB |
9995 CURSOR_STRIDE(stride);
9996
9997 size = (height << 12) | width;
4b0e333e 9998 }
560b85bb 9999
dc41c154
VS		 10000 if (intel_crtc->cursor_cntl != 0 &&
10001 (intel_crtc->cursor_base != base ||
10002 intel_crtc->cursor_size != size ||
10003 intel_crtc->cursor_cntl != cntl)) {
10004 /* On these chipsets we can only modify the base/size/stride
10005 * whilst the cursor is disabled.
10006 */
10007 I915_WRITE(_CURACNTR, 0);
4b0e333e 10008 POSTING_READ(_CURACNTR);
dc41c154 10009 intel_crtc->cursor_cntl = 0;
4b0e333e 10010 }
560b85bb 10011
99d1f387 10012 if (intel_crtc->cursor_base != base) {
9db4a9c7 10013 I915_WRITE(_CURABASE, base);
99d1f387
VS		 10014 intel_crtc->cursor_base = base;
10015 }
4726e0b0 10016
dc41c154
VS		 10017 if (intel_crtc->cursor_size != size) {
10018 I915_WRITE(CURSIZE, size);
10019 intel_crtc->cursor_size = size;
4b0e333e 10020 }
560b85bb 10021
4b0e333e 10022 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 10023 I915_WRITE(_CURACNTR, cntl);
10024 POSTING_READ(_CURACNTR);
4b0e333e 10025 intel_crtc->cursor_cntl = cntl;
560b85bb 10026 }
560b85bb
CW		 10027}
10028
560b85bb 10029static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 10030{
10031 struct drm_device *dev = crtc->dev;
10032 struct drm_i915_private *dev_priv = dev->dev_private;
10033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10034 int pipe = intel_crtc->pipe;
4b0e333e
CW		 10035 uint32_t cntl;
10036
10037 cntl = 0;
10038 if (base) {
10039 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10040 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10041 case 64:
10042 cntl |= CURSOR_MODE_64_ARGB_AX;
10043 break;
10044 case 128:
10045 cntl |= CURSOR_MODE_128_ARGB_AX;
10046 break;
10047 case 256:
10048 cntl |= CURSOR_MODE_256_ARGB_AX;
10049 break;
10050 default:
3dd512fb 10051 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10052 return;
65a21cd6 10053 }
4b0e333e 10054 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10055
10056 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10057 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10058 }
65a21cd6 10059
8e7d688b 10060 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10061 cntl |= CURSOR_ROTATE_180;
10062
4b0e333e
CW		 10063 if (intel_crtc->cursor_cntl != cntl) {
10064 I915_WRITE(CURCNTR(pipe), cntl);
10065 POSTING_READ(CURCNTR(pipe));
10066 intel_crtc->cursor_cntl = cntl;
65a21cd6 10067 }
4b0e333e 10068
65a21cd6 10069 /* and commit changes on next vblank */
5efb3e28
VS		 10070 I915_WRITE(CURBASE(pipe), base);
10071 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10072
10073 intel_crtc->cursor_base = base;
65a21cd6
JB		 10074}
10075
cda4b7d3 10076/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10077static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10078 bool on)
cda4b7d3
CW		 10079{
10080 struct drm_device *dev = crtc->dev;
10081 struct drm_i915_private *dev_priv = dev->dev_private;
10082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10083 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10084 int x = crtc->cursor_x;
10085 int y = crtc->cursor_y;
d6e4db15 10086 u32 base = 0, pos = 0;
cda4b7d3 10087
d6e4db15 10088 if (on)
cda4b7d3 10089 base = intel_crtc->cursor_addr;
cda4b7d3 10090
6e3c9717 10091 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10092 base = 0;
10093
6e3c9717 10094 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10095 base = 0;
10096
10097 if (x < 0) {
3dd512fb 10098 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10099 base = 0;
10100
10101 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10102 x = -x;
10103 }
10104 pos |= x << CURSOR_X_SHIFT;
10105
10106 if (y < 0) {
3dd512fb 10107 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10108 base = 0;
10109
10110 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10111 y = -y;
10112 }
10113 pos |= y << CURSOR_Y_SHIFT;
10114
4b0e333e 10115 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10116 return;
10117
5efb3e28
VS		 10118 I915_WRITE(CURPOS(pipe), pos);
10119
4398ad45
VS		 10120 /* ILK+ do this automagically */
10121 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10122 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10123 base += (intel_crtc->base.cursor->state->crtc_h *
10124 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10125 }
10126
8ac54669 10127 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10128 i845_update_cursor(crtc, base);
10129 else
10130 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10131}
10132
dc41c154
VS		 10133static bool cursor_size_ok(struct drm_device *dev,
10134 uint32_t width, uint32_t height)
10135{
10136 if (width == 0 || height == 0)
10137 return false;
10138
10139 /*
10140 * 845g/865g are special in that they are only limited by
10141 * the width of their cursors, the height is arbitrary up to
10142 * the precision of the register. Everything else requires
10143 * square cursors, limited to a few power-of-two sizes.
10144 */
10145 if (IS_845G(dev) || IS_I865G(dev)) {
10146 if ((width & 63) != 0)
10147 return false;
10148
10149 if (width > (IS_845G(dev) ? 64 : 512))
10150 return false;
10151
10152 if (height > 1023)
10153 return false;
10154 } else {
10155 switch (width | height) {
10156 case 256:
10157 case 128:
10158 if (IS_GEN2(dev))
10159 return false;
10160 case 64:
10161 break;
10162 default:
10163 return false;
10164 }
10165 }
10166
10167 return true;
10168}
10169
79e53945 10170static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10171 u16 *blue, uint32_t start, uint32_t size)
79e53945 10172{
7203425a 10173 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10175
7203425a 10176 for (i = start; i < end; i++) {
79e53945
JB		 10177 intel_crtc->lut_r[i] = red[i] >> 8;
10178 intel_crtc->lut_g[i] = green[i] >> 8;
10179 intel_crtc->lut_b[i] = blue[i] >> 8;
10180 }
10181
10182 intel_crtc_load_lut(crtc);
10183}
10184
79e53945
JB		 10185/* VESA 640x480x72Hz mode to set on the pipe */
10186static struct drm_display_mode load_detect_mode = {
10187 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10188 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10189};
10190
a8bb6818
DV		 10191struct drm_framebuffer *
10192__intel_framebuffer_create(struct drm_device *dev,
10193 struct drm_mode_fb_cmd2 *mode_cmd,
10194 struct drm_i915_gem_object *obj)
d2dff872
CW		 10195{
10196 struct intel_framebuffer *intel_fb;
10197 int ret;
10198
10199 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10200 if (!intel_fb) {
6ccb81f2 10201 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10202 return ERR_PTR(-ENOMEM);
10203 }
10204
10205 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10206 if (ret)
10207 goto err;
d2dff872
CW		 10208
10209 return &intel_fb->base;
dd4916c5 10210err:
6ccb81f2 10211 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10212 kfree(intel_fb);
10213
10214 return ERR_PTR(ret);
d2dff872
CW		 10215}
10216
b5ea642a 10217static struct drm_framebuffer *
a8bb6818
DV		 10218intel_framebuffer_create(struct drm_device *dev,
10219 struct drm_mode_fb_cmd2 *mode_cmd,
10220 struct drm_i915_gem_object *obj)
10221{
10222 struct drm_framebuffer *fb;
10223 int ret;
10224
10225 ret = i915_mutex_lock_interruptible(dev);
10226 if (ret)
10227 return ERR_PTR(ret);
10228 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10229 mutex_unlock(&dev->struct_mutex);
10230
10231 return fb;
10232}
10233
d2dff872
CW		 10234static u32
10235intel_framebuffer_pitch_for_width(int width, int bpp)
10236{
10237 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10238 return ALIGN(pitch, 64);
10239}
10240
10241static u32
10242intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10243{
10244 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10245 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10246}
10247
10248static struct drm_framebuffer *
10249intel_framebuffer_create_for_mode(struct drm_device *dev,
10250 struct drm_display_mode *mode,
10251 int depth, int bpp)
10252{
10253 struct drm_i915_gem_object *obj;
0fed39bd 10254 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10255
10256 obj = i915_gem_alloc_object(dev,
10257 intel_framebuffer_size_for_mode(mode, bpp));
10258 if (obj == NULL)
10259 return ERR_PTR(-ENOMEM);
10260
10261 mode_cmd.width = mode->hdisplay;
10262 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10263 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10264 bpp);
5ca0c34a 10265 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10266
10267 return intel_framebuffer_create(dev, &mode_cmd, obj);
10268}
10269
10270static struct drm_framebuffer *
10271mode_fits_in_fbdev(struct drm_device *dev,
10272 struct drm_display_mode *mode)
10273{
4520f53a 10274#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10275 struct drm_i915_private *dev_priv = dev->dev_private;
10276 struct drm_i915_gem_object *obj;
10277 struct drm_framebuffer *fb;
10278
4c0e5528 10279 if (!dev_priv->fbdev)
d2dff872
CW		 10280 return NULL;
10281
4c0e5528 10282 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10283 return NULL;
10284
4c0e5528
DV		 10285 obj = dev_priv->fbdev->fb->obj;
10286 BUG_ON(!obj);
10287
8bcd4553 10288 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10289 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10290 fb->bits_per_pixel))
d2dff872
CW		 10291 return NULL;
10292
01f2c773 10293 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10294 return NULL;
10295
10296 return fb;
4520f53a
DV		 10297#else
10298 return NULL;
10299#endif
d2dff872
CW		 10300}
10301
d3a40d1b
ACO		 10302static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10303 struct drm_crtc *crtc,
10304 struct drm_display_mode *mode,
10305 struct drm_framebuffer *fb,
10306 int x, int y)
10307{
10308 struct drm_plane_state *plane_state;
10309 int hdisplay, vdisplay;
10310 int ret;
10311
10312 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10313 if (IS_ERR(plane_state))
10314 return PTR_ERR(plane_state);
10315
10316 if (mode)
10317 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10318 else
10319 hdisplay = vdisplay = 0;
10320
10321 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10322 if (ret)
10323 return ret;
10324 drm_atomic_set_fb_for_plane(plane_state, fb);
10325 plane_state->crtc_x = 0;
10326 plane_state->crtc_y = 0;
10327 plane_state->crtc_w = hdisplay;
10328 plane_state->crtc_h = vdisplay;
10329 plane_state->src_x = x << 16;
10330 plane_state->src_y = y << 16;
10331 plane_state->src_w = hdisplay << 16;
10332 plane_state->src_h = vdisplay << 16;
10333
10334 return 0;
10335}
10336
d2434ab7 10337bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10338 struct drm_display_mode *mode,
51fd371b
RC		 10339 struct intel_load_detect_pipe *old,
10340 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10341{
10342 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10343 struct intel_encoder *intel_encoder =
10344 intel_attached_encoder(connector);
79e53945 10345 struct drm_crtc *possible_crtc;
4ef69c7a 10346 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10347 struct drm_crtc *crtc = NULL;
10348 struct drm_device *dev = encoder->dev;
94352cf9 10349 struct drm_framebuffer *fb;
51fd371b 10350 struct drm_mode_config *config = &dev->mode_config;
83a57153 10351 struct drm_atomic_state *state = NULL;
944b0c76 10352 struct drm_connector_state *connector_state;
4be07317 10353 struct intel_crtc_state *crtc_state;
51fd371b 10354 int ret, i = -1;
79e53945 10355
d2dff872 10356 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10357 connector->base.id, connector->name,
8e329a03 10358 encoder->base.id, encoder->name);
d2dff872 10359
51fd371b
RC		 10360retry:
10361 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10362 if (ret)
10363 goto fail_unlock;
6e9f798d 10364
79e53945
JB		 10365 /*
10366 * Algorithm gets a little messy:
7a5e4805 10367 *
79e53945
JB		 10368 * - if the connector already has an assigned crtc, use it (but make
10369 * sure it's on first)
7a5e4805 10370 *
79e53945
JB		 10371 * - try to find the first unused crtc that can drive this connector,
10372 * and use that if we find one
79e53945
JB		 10373 */
10374
10375 /* See if we already have a CRTC for this connector */
10376 if (encoder->crtc) {
10377 crtc = encoder->crtc;
8261b191 10378
51fd371b 10379 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10380 if (ret)
10381 goto fail_unlock;
10382 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10383 if (ret)
10384 goto fail_unlock;
7b24056b 10385
24218aac 10386 old->dpms_mode = connector->dpms;
8261b191
CW		 10387 old->load_detect_temp = false;
10388
10389 /* Make sure the crtc and connector are running */
24218aac
DV		 10390 if (connector->dpms != DRM_MODE_DPMS_ON)
10391 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10392
7173188d 10393 return true;
79e53945
JB		 10394 }
10395
10396 /* Find an unused one (if possible) */
70e1e0ec 10397 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10398 i++;
10399 if (!(encoder->possible_crtcs & (1 << i)))
10400 continue;
83d65738 10401 if (possible_crtc->state->enable)
a459249c
VS		 10402 continue;
10403 /* This can occur when applying the pipe A quirk on resume. */
10404 if (to_intel_crtc(possible_crtc)->new_enabled)
10405 continue;
10406
10407 crtc = possible_crtc;
10408 break;
79e53945
JB		 10409 }
10410
10411 /*
10412 * If we didn't find an unused CRTC, don't use any.
10413 */
10414 if (!crtc) {
7173188d 10415 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10416 goto fail_unlock;
79e53945
JB		 10417 }
10418
51fd371b
RC		 10419 ret = drm_modeset_lock(&crtc->mutex, ctx);
10420 if (ret)
4d02e2de
DV		 10421 goto fail_unlock;
10422 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10423 if (ret)
51fd371b 10424 goto fail_unlock;
fc303101
DV		 10425 intel_encoder->new_crtc = to_intel_crtc(crtc);
10426 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10427
10428 intel_crtc = to_intel_crtc(crtc);
412b61d8 10429 intel_crtc->new_enabled = true;
24218aac 10430 old->dpms_mode = connector->dpms;
8261b191 10431 old->load_detect_temp = true;
d2dff872 10432 old->release_fb = NULL;
79e53945 10433
83a57153
ACO		 10434 state = drm_atomic_state_alloc(dev);
10435 if (!state)
10436 return false;
10437
10438 state->acquire_ctx = ctx;
10439
944b0c76
ACO		 10440 connector_state = drm_atomic_get_connector_state(state, connector);
10441 if (IS_ERR(connector_state)) {
10442 ret = PTR_ERR(connector_state);
10443 goto fail;
10444 }
10445
10446 connector_state->crtc = crtc;
10447 connector_state->best_encoder = &intel_encoder->base;
10448
4be07317
ACO		 10449 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10450 if (IS_ERR(crtc_state)) {
10451 ret = PTR_ERR(crtc_state);
10452 goto fail;
10453 }
10454
49d6fa21 10455 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10456
6492711d
CW		 10457 if (!mode)
10458 mode = &load_detect_mode;
79e53945 10459
d2dff872
CW		 10460 /* We need a framebuffer large enough to accommodate all accesses
10461 * that the plane may generate whilst we perform load detection.
10462 * We can not rely on the fbcon either being present (we get called
10463 * during its initialisation to detect all boot displays, or it may
10464 * not even exist) or that it is large enough to satisfy the
10465 * requested mode.
10466 */
94352cf9
DV		 10467 fb = mode_fits_in_fbdev(dev, mode);
10468 if (fb == NULL) {
d2dff872 10469 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10470 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10471 old->release_fb = fb;
d2dff872
CW		 10472 } else
10473 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10474 if (IS_ERR(fb)) {
d2dff872 10475 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10476 goto fail;
79e53945 10477 }
79e53945 10478
d3a40d1b
ACO		 10479 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10480 if (ret)
10481 goto fail;
10482
8c7b5ccb
ACO		 10483 drm_mode_copy(&crtc_state->base.mode, mode);
10484
10485 if (intel_set_mode(crtc, state)) {
6492711d 10486 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10487 if (old->release_fb)
10488 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10489 goto fail;
79e53945 10490 }
9128b040 10491 crtc->primary->crtc = crtc;
7173188d 10492
79e53945 10493 /* let the connector get through one full cycle before testing */
9d0498a2 10494 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10495 return true;
412b61d8
VS		 10496
10497 fail:
83d65738 10498 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10499fail_unlock:
e5d958ef
ACO		 10500 drm_atomic_state_free(state);
10501 state = NULL;
83a57153 10502
51fd371b
RC		 10503 if (ret == -EDEADLK) {
10504 drm_modeset_backoff(ctx);
10505 goto retry;
10506 }
10507
412b61d8 10508 return false;
79e53945
JB		 10509}
10510
d2434ab7 10511void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10512 struct intel_load_detect_pipe *old,
10513 struct drm_modeset_acquire_ctx *ctx)
79e53945 10514{
83a57153 10515 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10516 struct intel_encoder *intel_encoder =
10517 intel_attached_encoder(connector);
4ef69c7a 10518 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10519 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10521 struct drm_atomic_state *state;
944b0c76 10522 struct drm_connector_state *connector_state;
4be07317 10523 struct intel_crtc_state *crtc_state;
d3a40d1b 10524 int ret;
79e53945 10525
d2dff872 10526 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10527 connector->base.id, connector->name,
8e329a03 10528 encoder->base.id, encoder->name);
d2dff872 10529
8261b191 10530 if (old->load_detect_temp) {
83a57153 10531 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10532 if (!state)
10533 goto fail;
83a57153
ACO		 10534
10535 state->acquire_ctx = ctx;
10536
944b0c76
ACO		 10537 connector_state = drm_atomic_get_connector_state(state, connector);
10538 if (IS_ERR(connector_state))
10539 goto fail;
10540
4be07317
ACO		 10541 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10542 if (IS_ERR(crtc_state))
10543 goto fail;
10544
fc303101
DV		 10545 to_intel_connector(connector)->new_encoder = NULL;
10546 intel_encoder->new_crtc = NULL;
412b61d8 10547 intel_crtc->new_enabled = false;
944b0c76
ACO		 10548
10549 connector_state->best_encoder = NULL;
10550 connector_state->crtc = NULL;
10551
49d6fa21 10552 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10553
d3a40d1b
ACO		 10554 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10555 0, 0);
10556 if (ret)
10557 goto fail;
10558
2bfb4627
ACO		 10559 ret = intel_set_mode(crtc, state);
10560 if (ret)
10561 goto fail;
d2dff872 10562
36206361
DV		 10563 if (old->release_fb) {
10564 drm_framebuffer_unregister_private(old->release_fb);
10565 drm_framebuffer_unreference(old->release_fb);
10566 }
d2dff872 10567
0622a53c 10568 return;
79e53945
JB		 10569 }
10570
c751ce4f 10571 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10572 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10573 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10574
10575 return;
10576fail:
10577 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10578 drm_atomic_state_free(state);
79e53945
JB		 10579}
10580
da4a1efa 10581static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10582 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10583{
10584 struct drm_i915_private *dev_priv = dev->dev_private;
10585 u32 dpll = pipe_config->dpll_hw_state.dpll;
10586
10587 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10588 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10589 else if (HAS_PCH_SPLIT(dev))
10590 return 120000;
10591 else if (!IS_GEN2(dev))
10592 return 96000;
10593 else
10594 return 48000;
10595}
10596
79e53945 10597/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10598static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10599 struct intel_crtc_state *pipe_config)
79e53945 10600{
f1f644dc 10601 struct drm_device *dev = crtc->base.dev;
79e53945 10602 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10603 int pipe = pipe_config->cpu_transcoder;
293623f7 10604 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10605 u32 fp;
10606 intel_clock_t clock;
da4a1efa 10607 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10608
10609 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10610 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10611 else
293623f7 10612 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10613
10614 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10615 if (IS_PINEVIEW(dev)) {
10616 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10617 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10618 } else {
10619 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10620 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10621 }
10622
a6c45cf0 10623 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10624 if (IS_PINEVIEW(dev))
10625 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10626 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10627 else
10628 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10629 DPLL_FPA01_P1_POST_DIV_SHIFT);
10630
10631 switch (dpll & DPLL_MODE_MASK) {
10632 case DPLLB_MODE_DAC_SERIAL:
10633 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10634 5 : 10;
10635 break;
10636 case DPLLB_MODE_LVDS:
10637 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10638 7 : 14;
10639 break;
10640 default:
28c97730 10641 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10642 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10643 return;
79e53945
JB		 10644 }
10645
ac58c3f0 10646 if (IS_PINEVIEW(dev))
da4a1efa 10647 pineview_clock(refclk, &clock);
ac58c3f0 10648 else
da4a1efa 10649 i9xx_clock(refclk, &clock);
79e53945 10650 } else {
0fb58223 10651 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10652 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10653
10654 if (is_lvds) {
10655 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10656 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10657
10658 if (lvds & LVDS_CLKB_POWER_UP)
10659 clock.p2 = 7;
10660 else
10661 clock.p2 = 14;
79e53945
JB		 10662 } else {
10663 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10664 clock.p1 = 2;
10665 else {
10666 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10667 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10668 }
10669 if (dpll & PLL_P2_DIVIDE_BY_4)
10670 clock.p2 = 4;
10671 else
10672 clock.p2 = 2;
79e53945 10673 }
da4a1efa
VS		 10674
10675 i9xx_clock(refclk, &clock);
79e53945
JB		 10676 }
10677
18442d08
VS		 10678 /*
10679 * This value includes pixel_multiplier. We will use
241bfc38 10680 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10681 * encoder's get_config() function.
10682 */
10683 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10684}
10685
6878da05
VS		 10686int intel_dotclock_calculate(int link_freq,
10687 const struct intel_link_m_n *m_n)
f1f644dc 10688{
f1f644dc
JB		 10689 /*
10690 * The calculation for the data clock is:
1041a02f 10691 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10692 * But we want to avoid losing precison if possible, so:
1041a02f 10693 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10694 *
10695 * and the link clock is simpler:
1041a02f 10696 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10697 */
10698
6878da05
VS		 10699 if (!m_n->link_n)
10700 return 0;
f1f644dc 10701
6878da05
VS		 10702 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10703}
f1f644dc 10704
18442d08 10705static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10706 struct intel_crtc_state *pipe_config)
6878da05
VS		 10707{
10708 struct drm_device *dev = crtc->base.dev;
79e53945 10709
18442d08
VS		 10710 /* read out port_clock from the DPLL */
10711 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10712
f1f644dc 10713 /*
18442d08 10714 * This value does not include pixel_multiplier.
241bfc38 10715 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10716 * agree once we know their relationship in the encoder's
10717 * get_config() function.
79e53945 10718 */
2d112de7 10719 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10720 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10721 &pipe_config->fdi_m_n);
79e53945
JB		 10722}
10723
10724/** Returns the currently programmed mode of the given pipe. */
10725struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10726 struct drm_crtc *crtc)
10727{
548f245b 10728 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10730 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10731 struct drm_display_mode *mode;
5cec258b 10732 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10733 int htot = I915_READ(HTOTAL(cpu_transcoder));
10734 int hsync = I915_READ(HSYNC(cpu_transcoder));
10735 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10736 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10737 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10738
10739 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10740 if (!mode)
10741 return NULL;
10742
f1f644dc
JB		 10743 /*
10744 * Construct a pipe_config sufficient for getting the clock info
10745 * back out of crtc_clock_get.
10746 *
10747 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10748 * to use a real value here instead.
10749 */
293623f7 10750 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10751 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10752 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10753 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10754 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10755 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10756
773ae034 10757 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10758 mode->hdisplay = (htot & 0xffff) + 1;
10759 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10760 mode->hsync_start = (hsync & 0xffff) + 1;
10761 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10762 mode->vdisplay = (vtot & 0xffff) + 1;
10763 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10764 mode->vsync_start = (vsync & 0xffff) + 1;
10765 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10766
10767 drm_mode_set_name(mode);
79e53945
JB		 10768
10769 return mode;
10770}
10771
652c393a
JB		 10772static void intel_decrease_pllclock(struct drm_crtc *crtc)
10773{
10774 struct drm_device *dev = crtc->dev;
fbee40df 10775 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10777
baff296c 10778 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10779 return;
10780
10781 if (!dev_priv->lvds_downclock_avail)
10782 return;
10783
10784 /*
10785 * Since this is called by a timer, we should never get here in
10786 * the manual case.
10787 */
10788 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10789 int pipe = intel_crtc->pipe;
10790 int dpll_reg = DPLL(pipe);
10791 int dpll;
f6e5b160 10792
44d98a61 10793 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10794
8ac5a6d5 10795 assert_panel_unlocked(dev_priv, pipe);
652c393a 10796
dc257cf1 10797 dpll = I915_READ(dpll_reg);
652c393a
JB		 10798 dpll |= DISPLAY_RATE_SELECT_FPA1;
10799 I915_WRITE(dpll_reg, dpll);
9d0498a2 10800 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10801 dpll = I915_READ(dpll_reg);
10802 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10803 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10804 }
10805
10806}
10807
f047e395
CW		 10808void intel_mark_busy(struct drm_device *dev)
10809{
c67a470b
PZ		 10810 struct drm_i915_private *dev_priv = dev->dev_private;
10811
f62a0076
CW		 10812 if (dev_priv->mm.busy)
10813 return;
10814
43694d69 10815 intel_runtime_pm_get(dev_priv);
c67a470b 10816 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10817 if (INTEL_INFO(dev)->gen >= 6)
10818 gen6_rps_busy(dev_priv);
f62a0076 10819 dev_priv->mm.busy = true;
f047e395
CW		 10820}
10821
10822void intel_mark_idle(struct drm_device *dev)
652c393a 10823{
c67a470b 10824 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10825 struct drm_crtc *crtc;
652c393a 10826
f62a0076
CW		 10827 if (!dev_priv->mm.busy)
10828 return;
10829
10830 dev_priv->mm.busy = false;
10831
70e1e0ec 10832 for_each_crtc(dev, crtc) {
f4510a27 10833 if (!crtc->primary->fb)
652c393a
JB		 10834 continue;
10835
725a5b54 10836 intel_decrease_pllclock(crtc);
652c393a 10837 }
b29c19b6 10838
3d13ef2e 10839 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10840 gen6_rps_idle(dev->dev_private);
bb4cdd53 10841
43694d69 10842 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10843}
10844
79e53945
JB		 10845static void intel_crtc_destroy(struct drm_crtc *crtc)
10846{
10847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10848 struct drm_device *dev = crtc->dev;
10849 struct intel_unpin_work *work;
67e77c5a 10850
5e2d7afc 10851 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10852 work = intel_crtc->unpin_work;
10853 intel_crtc->unpin_work = NULL;
5e2d7afc 10854 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10855
10856 if (work) {
10857 cancel_work_sync(&work->work);
10858 kfree(work);
10859 }
79e53945
JB		 10860
10861 drm_crtc_cleanup(crtc);
67e77c5a 10862
79e53945
JB		 10863 kfree(intel_crtc);
10864}
10865
6b95a207
KH		 10866static void intel_unpin_work_fn(struct work_struct *__work)
10867{
10868 struct intel_unpin_work *work =
10869 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10870 struct drm_device *dev = work->crtc->dev;
f99d7069 10871 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10872
b4a98e57 10873 mutex_lock(&dev->struct_mutex);
82bc3b2d 10874 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10875 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10876
7ff0ebcc 10877 intel_fbc_update(dev);
f06cc1b9
JH		 10878
10879 if (work->flip_queued_req)
146d84f0 10880 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10881 mutex_unlock(&dev->struct_mutex);
10882
f99d7069 10883 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10884 drm_framebuffer_unreference(work->old_fb);
f99d7069 10885
b4a98e57
CW		 10886 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10887 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10888
6b95a207
KH		 10889 kfree(work);
10890}
10891
1afe3e9d 10892static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10893 struct drm_crtc *crtc)
6b95a207 10894{
6b95a207
KH		 10895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10896 struct intel_unpin_work *work;
6b95a207
KH		 10897 unsigned long flags;
10898
10899 /* Ignore early vblank irqs */
10900 if (intel_crtc == NULL)
10901 return;
10902
f326038a
DV		 10903 /*
10904 * This is called both by irq handlers and the reset code (to complete
10905 * lost pageflips) so needs the full irqsave spinlocks.
10906 */
6b95a207
KH		 10907 spin_lock_irqsave(&dev->event_lock, flags);
10908 work = intel_crtc->unpin_work;
e7d841ca
CW		 10909
10910 /* Ensure we don't miss a work->pending update ... */
10911 smp_rmb();
10912
10913 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10914 spin_unlock_irqrestore(&dev->event_lock, flags);
10915 return;
10916 }
10917
d6bbafa1 10918 page_flip_completed(intel_crtc);
0af7e4df 10919
6b95a207 10920 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10921}
10922
1afe3e9d
JB		 10923void intel_finish_page_flip(struct drm_device *dev, int pipe)
10924{
fbee40df 10925 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10926 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10927
49b14a5c 10928 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10929}
10930
10931void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10932{
fbee40df 10933 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10934 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10935
49b14a5c 10936 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10937}
10938
75f7f3ec
VS		 10939/* Is 'a' after or equal to 'b'? */
10940static bool g4x_flip_count_after_eq(u32 a, u32 b)
10941{
10942 return !((a - b) & 0x80000000);
10943}
10944
10945static bool page_flip_finished(struct intel_crtc *crtc)
10946{
10947 struct drm_device *dev = crtc->base.dev;
10948 struct drm_i915_private *dev_priv = dev->dev_private;
10949
bdfa7542
VS		 10950 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10951 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10952 return true;
10953
75f7f3ec
VS		 10954 /*
10955 * The relevant registers doen't exist on pre-ctg.
10956 * As the flip done interrupt doesn't trigger for mmio
10957 * flips on gmch platforms, a flip count check isn't
10958 * really needed there. But since ctg has the registers,
10959 * include it in the check anyway.
10960 */
10961 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10962 return true;
10963
10964 /*
10965 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10966 * used the same base address. In that case the mmio flip might
10967 * have completed, but the CS hasn't even executed the flip yet.
10968 *
10969 * A flip count check isn't enough as the CS might have updated
10970 * the base address just after start of vblank, but before we
10971 * managed to process the interrupt. This means we'd complete the
10972 * CS flip too soon.
10973 *
10974 * Combining both checks should get us a good enough result. It may
10975 * still happen that the CS flip has been executed, but has not
10976 * yet actually completed. But in case the base address is the same
10977 * anyway, we don't really care.
10978 */
10979 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10980 crtc->unpin_work->gtt_offset &&
10981 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10982 crtc->unpin_work->flip_count);
10983}
10984
6b95a207
KH		 10985void intel_prepare_page_flip(struct drm_device *dev, int plane)
10986{
fbee40df 10987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10988 struct intel_crtc *intel_crtc =
10989 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10990 unsigned long flags;
10991
f326038a
DV		 10992
10993 /*
10994 * This is called both by irq handlers and the reset code (to complete
10995 * lost pageflips) so needs the full irqsave spinlocks.
10996 *
10997 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10998 * generate a page-flip completion irq, i.e. every modeset
10999 * is also accompanied by a spurious intel_prepare_page_flip().
11000 */
6b95a207 11001 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 11002 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 11003 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 11004 spin_unlock_irqrestore(&dev->event_lock, flags);
11005}
11006
eba905b2 11007static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 11008{
11009 /* Ensure that the work item is consistent when activating it ... */
11010 smp_wmb();
11011 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11012 /* and that it is marked active as soon as the irq could fire. */
11013 smp_wmb();
11014}
11015
8c9f3aaf
JB		 11016static int intel_gen2_queue_flip(struct drm_device *dev,
11017 struct drm_crtc *crtc,
11018 struct drm_framebuffer *fb,
ed8d1975 11019 struct drm_i915_gem_object *obj,
a4872ba6 11020 struct intel_engine_cs *ring,
ed8d1975 11021 uint32_t flags)
8c9f3aaf 11022{
8c9f3aaf 11023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11024 u32 flip_mask;
11025 int ret;
11026
6d90c952 11027 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11028 if (ret)
4fa62c89 11029 return ret;
8c9f3aaf
JB		 11030
11031 /* Can't queue multiple flips, so wait for the previous
11032 * one to finish before executing the next.
11033 */
11034 if (intel_crtc->plane)
11035 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11036 else
11037 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11038 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11039 intel_ring_emit(ring, MI_NOOP);
11040 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11041 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11042 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11043 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11044 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11045
11046 intel_mark_page_flip_active(intel_crtc);
09246732 11047 __intel_ring_advance(ring);
83d4092b 11048 return 0;
8c9f3aaf
JB		 11049}
11050
11051static int intel_gen3_queue_flip(struct drm_device *dev,
11052 struct drm_crtc *crtc,
11053 struct drm_framebuffer *fb,
ed8d1975 11054 struct drm_i915_gem_object *obj,
a4872ba6 11055 struct intel_engine_cs *ring,
ed8d1975 11056 uint32_t flags)
8c9f3aaf 11057{
8c9f3aaf 11058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11059 u32 flip_mask;
11060 int ret;
11061
6d90c952 11062 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11063 if (ret)
4fa62c89 11064 return ret;
8c9f3aaf
JB		 11065
11066 if (intel_crtc->plane)
11067 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11068 else
11069 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11070 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11071 intel_ring_emit(ring, MI_NOOP);
11072 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11073 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11074 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11075 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11076 intel_ring_emit(ring, MI_NOOP);
11077
e7d841ca 11078 intel_mark_page_flip_active(intel_crtc);
09246732 11079 __intel_ring_advance(ring);
83d4092b 11080 return 0;
8c9f3aaf
JB		 11081}
11082
11083static int intel_gen4_queue_flip(struct drm_device *dev,
11084 struct drm_crtc *crtc,
11085 struct drm_framebuffer *fb,
ed8d1975 11086 struct drm_i915_gem_object *obj,
a4872ba6 11087 struct intel_engine_cs *ring,
ed8d1975 11088 uint32_t flags)
8c9f3aaf
JB		 11089{
11090 struct drm_i915_private *dev_priv = dev->dev_private;
11091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11092 uint32_t pf, pipesrc;
11093 int ret;
11094
6d90c952 11095 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11096 if (ret)
4fa62c89 11097 return ret;
8c9f3aaf
JB		 11098
11099 /* i965+ uses the linear or tiled offsets from the
11100 * Display Registers (which do not change across a page-flip)
11101 * so we need only reprogram the base address.
11102 */
6d90c952
DV		 11103 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11104 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11105 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11106 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11107 obj->tiling_mode);
8c9f3aaf
JB		 11108
11109 /* XXX Enabling the panel-fitter across page-flip is so far
11110 * untested on non-native modes, so ignore it for now.
11111 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11112 */
11113 pf = 0;
11114 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11115 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11116
11117 intel_mark_page_flip_active(intel_crtc);
09246732 11118 __intel_ring_advance(ring);
83d4092b 11119 return 0;
8c9f3aaf
JB		 11120}
11121
11122static int intel_gen6_queue_flip(struct drm_device *dev,
11123 struct drm_crtc *crtc,
11124 struct drm_framebuffer *fb,
ed8d1975 11125 struct drm_i915_gem_object *obj,
a4872ba6 11126 struct intel_engine_cs *ring,
ed8d1975 11127 uint32_t flags)
8c9f3aaf
JB		 11128{
11129 struct drm_i915_private *dev_priv = dev->dev_private;
11130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11131 uint32_t pf, pipesrc;
11132 int ret;
11133
6d90c952 11134 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11135 if (ret)
4fa62c89 11136 return ret;
8c9f3aaf 11137
6d90c952
DV		 11138 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11139 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11140 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11141 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11142
dc257cf1
DV		 11143 /* Contrary to the suggestions in the documentation,
11144 * "Enable Panel Fitter" does not seem to be required when page
11145 * flipping with a non-native mode, and worse causes a normal
11146 * modeset to fail.
11147 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11148 */
11149 pf = 0;
8c9f3aaf 11150 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11151 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11152
11153 intel_mark_page_flip_active(intel_crtc);
09246732 11154 __intel_ring_advance(ring);
83d4092b 11155 return 0;
8c9f3aaf
JB		 11156}
11157
7c9017e5
JB		 11158static int intel_gen7_queue_flip(struct drm_device *dev,
11159 struct drm_crtc *crtc,
11160 struct drm_framebuffer *fb,
ed8d1975 11161 struct drm_i915_gem_object *obj,
a4872ba6 11162 struct intel_engine_cs *ring,
ed8d1975 11163 uint32_t flags)
7c9017e5 11164{
7c9017e5 11165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11166 uint32_t plane_bit = 0;
ffe74d75
CW		 11167 int len, ret;
11168
eba905b2 11169 switch (intel_crtc->plane) {
cb05d8de
DV		 11170 case PLANE_A:
11171 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11172 break;
11173 case PLANE_B:
11174 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11175 break;
11176 case PLANE_C:
11177 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11178 break;
11179 default:
11180 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11181 return -ENODEV;
cb05d8de
DV		 11182 }
11183
ffe74d75 11184 len = 4;
f476828a 11185 if (ring->id == RCS) {
ffe74d75 11186 len += 6;
f476828a
DL		 11187 /*
11188 * On Gen 8, SRM is now taking an extra dword to accommodate
11189 * 48bits addresses, and we need a NOOP for the batch size to
11190 * stay even.
11191 */
11192 if (IS_GEN8(dev))
11193 len += 2;
11194 }
ffe74d75 11195
f66fab8e
VS		 11196 /*
11197 * BSpec MI_DISPLAY_FLIP for IVB:
11198 * "The full packet must be contained within the same cache line."
11199 *
11200 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11201 * cacheline, if we ever start emitting more commands before
11202 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11203 * then do the cacheline alignment, and finally emit the
11204 * MI_DISPLAY_FLIP.
11205 */
11206 ret = intel_ring_cacheline_align(ring);
11207 if (ret)
4fa62c89 11208 return ret;
f66fab8e 11209
ffe74d75 11210 ret = intel_ring_begin(ring, len);
7c9017e5 11211 if (ret)
4fa62c89 11212 return ret;
7c9017e5 11213
ffe74d75
CW		 11214 /* Unmask the flip-done completion message. Note that the bspec says that
11215 * we should do this for both the BCS and RCS, and that we must not unmask
11216 * more than one flip event at any time (or ensure that one flip message
11217 * can be sent by waiting for flip-done prior to queueing new flips).
11218 * Experimentation says that BCS works despite DERRMR masking all
11219 * flip-done completion events and that unmasking all planes at once
11220 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11221 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11222 */
11223 if (ring->id == RCS) {
11224 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11225 intel_ring_emit(ring, DERRMR);
11226 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11227 DERRMR_PIPEB_PRI_FLIP_DONE |
11228 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11229 if (IS_GEN8(dev))
11230 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11231 MI_SRM_LRM_GLOBAL_GTT);
11232 else
11233 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11234 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11235 intel_ring_emit(ring, DERRMR);
11236 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11237 if (IS_GEN8(dev)) {
11238 intel_ring_emit(ring, 0);
11239 intel_ring_emit(ring, MI_NOOP);
11240 }
ffe74d75
CW		 11241 }
11242
cb05d8de 11243 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11244 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11245 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11246 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11247
11248 intel_mark_page_flip_active(intel_crtc);
09246732 11249 __intel_ring_advance(ring);
83d4092b 11250 return 0;
7c9017e5
JB		 11251}
11252
84c33a64
SG		 11253static bool use_mmio_flip(struct intel_engine_cs *ring,
11254 struct drm_i915_gem_object *obj)
11255{
11256 /*
11257 * This is not being used for older platforms, because
11258 * non-availability of flip done interrupt forces us to use
11259 * CS flips. Older platforms derive flip done using some clever
11260 * tricks involving the flip_pending status bits and vblank irqs.
11261 * So using MMIO flips there would disrupt this mechanism.
11262 */
11263
8e09bf83
CW		 11264 if (ring == NULL)
11265 return true;
11266
84c33a64
SG		 11267 if (INTEL_INFO(ring->dev)->gen < 5)
11268 return false;
11269
11270 if (i915.use_mmio_flip < 0)
11271 return false;
11272 else if (i915.use_mmio_flip > 0)
11273 return true;
14bf993e
OM		 11274 else if (i915.enable_execlists)
11275 return true;
84c33a64 11276 else
b4716185 11277 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11278}
11279
ff944564
DL		 11280static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11281{
11282 struct drm_device *dev = intel_crtc->base.dev;
11283 struct drm_i915_private *dev_priv = dev->dev_private;
11284 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11285 const enum pipe pipe = intel_crtc->pipe;
11286 u32 ctl, stride;
11287
11288 ctl = I915_READ(PLANE_CTL(pipe, 0));
11289 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11290 switch (fb->modifier[0]) {
11291 case DRM_FORMAT_MOD_NONE:
11292 break;
11293 case I915_FORMAT_MOD_X_TILED:
ff944564 11294 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11295 break;
11296 case I915_FORMAT_MOD_Y_TILED:
11297 ctl |= PLANE_CTL_TILED_Y;
11298 break;
11299 case I915_FORMAT_MOD_Yf_TILED:
11300 ctl |= PLANE_CTL_TILED_YF;
11301 break;
11302 default:
11303 MISSING_CASE(fb->modifier[0]);
11304 }
ff944564
DL		 11305
11306 /*
11307 * The stride is either expressed as a multiple of 64 bytes chunks for
11308 * linear buffers or in number of tiles for tiled buffers.
11309 */
2ebef630
TU		 11310 stride = fb->pitches[0] /
11311 intel_fb_stride_alignment(dev, fb->modifier[0],
11312 fb->pixel_format);
ff944564
DL		 11313
11314 /*
11315 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11316 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11317 */
11318 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11319 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11320
11321 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11322 POSTING_READ(PLANE_SURF(pipe, 0));
11323}
11324
11325static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11326{
11327 struct drm_device *dev = intel_crtc->base.dev;
11328 struct drm_i915_private *dev_priv = dev->dev_private;
11329 struct intel_framebuffer *intel_fb =
11330 to_intel_framebuffer(intel_crtc->base.primary->fb);
11331 struct drm_i915_gem_object *obj = intel_fb->obj;
11332 u32 dspcntr;
11333 u32 reg;
11334
84c33a64
SG		 11335 reg = DSPCNTR(intel_crtc->plane);
11336 dspcntr = I915_READ(reg);
11337
c5d97472
DL		 11338 if (obj->tiling_mode != I915_TILING_NONE)
11339 dspcntr |= DISPPLANE_TILED;
11340 else
11341 dspcntr &= ~DISPPLANE_TILED;
11342
84c33a64
SG		 11343 I915_WRITE(reg, dspcntr);
11344
11345 I915_WRITE(DSPSURF(intel_crtc->plane),
11346 intel_crtc->unpin_work->gtt_offset);
11347 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11348
ff944564
DL		 11349}
11350
11351/*
11352 * XXX: This is the temporary way to update the plane registers until we get
11353 * around to using the usual plane update functions for MMIO flips
11354 */
11355static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11356{
11357 struct drm_device *dev = intel_crtc->base.dev;
11358 bool atomic_update;
11359 u32 start_vbl_count;
11360
11361 intel_mark_page_flip_active(intel_crtc);
11362
11363 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11364
11365 if (INTEL_INFO(dev)->gen >= 9)
11366 skl_do_mmio_flip(intel_crtc);
11367 else
11368 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11369 ilk_do_mmio_flip(intel_crtc);
11370
9362c7c5
ACO		 11371 if (atomic_update)
11372 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11373}
11374
9362c7c5 11375static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11376{
b2cfe0ab
CW		 11377 struct intel_mmio_flip *mmio_flip =
11378 container_of(work, struct intel_mmio_flip, work);
84c33a64 11379
eed29a5b
DV		 11380 if (mmio_flip->req)
11381 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11382 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11383 false, NULL,
11384 &mmio_flip->i915->rps.mmioflips));
84c33a64 11385
b2cfe0ab
CW		 11386 intel_do_mmio_flip(mmio_flip->crtc);
11387
eed29a5b 11388 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11389 kfree(mmio_flip);
84c33a64
SG		 11390}
11391
11392static int intel_queue_mmio_flip(struct drm_device *dev,
11393 struct drm_crtc *crtc,
11394 struct drm_framebuffer *fb,
11395 struct drm_i915_gem_object *obj,
11396 struct intel_engine_cs *ring,
11397 uint32_t flags)
11398{
b2cfe0ab
CW		 11399 struct intel_mmio_flip *mmio_flip;
11400
11401 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11402 if (mmio_flip == NULL)
11403 return -ENOMEM;
84c33a64 11404
bcafc4e3 11405 mmio_flip->i915 = to_i915(dev);
eed29a5b 11406 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11407 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11408
b2cfe0ab
CW		 11409 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11410 schedule_work(&mmio_flip->work);
84c33a64 11411
84c33a64
SG		 11412 return 0;
11413}
11414
8c9f3aaf
JB		 11415static int intel_default_queue_flip(struct drm_device *dev,
11416 struct drm_crtc *crtc,
11417 struct drm_framebuffer *fb,
ed8d1975 11418 struct drm_i915_gem_object *obj,
a4872ba6 11419 struct intel_engine_cs *ring,
ed8d1975 11420 uint32_t flags)
8c9f3aaf
JB		 11421{
11422 return -ENODEV;
11423}
11424
d6bbafa1
CW		 11425static bool __intel_pageflip_stall_check(struct drm_device *dev,
11426 struct drm_crtc *crtc)
11427{
11428 struct drm_i915_private *dev_priv = dev->dev_private;
11429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11430 struct intel_unpin_work *work = intel_crtc->unpin_work;
11431 u32 addr;
11432
11433 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11434 return true;
11435
11436 if (!work->enable_stall_check)
11437 return false;
11438
11439 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11440 if (work->flip_queued_req &&
11441 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11442 return false;
11443
1e3feefd 11444 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11445 }
11446
1e3feefd 11447 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11448 return false;
11449
11450 /* Potential stall - if we see that the flip has happened,
11451 * assume a missed interrupt. */
11452 if (INTEL_INFO(dev)->gen >= 4)
11453 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11454 else
11455 addr = I915_READ(DSPADDR(intel_crtc->plane));
11456
11457 /* There is a potential issue here with a false positive after a flip
11458 * to the same address. We could address this by checking for a
11459 * non-incrementing frame counter.
11460 */
11461 return addr == work->gtt_offset;
11462}
11463
11464void intel_check_page_flip(struct drm_device *dev, int pipe)
11465{
11466 struct drm_i915_private *dev_priv = dev->dev_private;
11467 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11469 struct intel_unpin_work *work;
f326038a 11470
6c51d46f 11471 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11472
11473 if (crtc == NULL)
11474 return;
11475
f326038a 11476 spin_lock(&dev->event_lock);
6ad790c0
CW		 11477 work = intel_crtc->unpin_work;
11478 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11479 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11480 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11481 page_flip_completed(intel_crtc);
6ad790c0 11482 work = NULL;
d6bbafa1 11483 }
6ad790c0
CW		 11484 if (work != NULL &&
11485 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11486 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11487 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11488}
11489
6b95a207
KH		 11490static int intel_crtc_page_flip(struct drm_crtc *crtc,
11491 struct drm_framebuffer *fb,
ed8d1975
KP		 11492 struct drm_pending_vblank_event *event,
11493 uint32_t page_flip_flags)
6b95a207
KH		 11494{
11495 struct drm_device *dev = crtc->dev;
11496 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11497 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11498 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11500 struct drm_plane *primary = crtc->primary;
a071fa00 11501 enum pipe pipe = intel_crtc->pipe;
6b95a207 11502 struct intel_unpin_work *work;
a4872ba6 11503 struct intel_engine_cs *ring;
cf5d8a46 11504 bool mmio_flip;
52e68630 11505 int ret;
6b95a207 11506
2ff8fde1
MR		 11507 /*
11508 * drm_mode_page_flip_ioctl() should already catch this, but double
11509 * check to be safe. In the future we may enable pageflipping from
11510 * a disabled primary plane.
11511 */
11512 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11513 return -EBUSY;
11514
e6a595d2 11515 /* Can't change pixel format via MI display flips. */
f4510a27 11516 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11517 return -EINVAL;
11518
11519 /*
11520 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11521 * Note that pitch changes could also affect these register.
11522 */
11523 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11524 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11525 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11526 return -EINVAL;
11527
f900db47
CW		 11528 if (i915_terminally_wedged(&dev_priv->gpu_error))
11529 goto out_hang;
11530
b14c5679 11531 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11532 if (work == NULL)
11533 return -ENOMEM;
11534
6b95a207 11535 work->event = event;
b4a98e57 11536 work->crtc = crtc;
ab8d6675 11537 work->old_fb = old_fb;
6b95a207
KH		 11538 INIT_WORK(&work->work, intel_unpin_work_fn);
11539
87b6b101 11540 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11541 if (ret)
11542 goto free_work;
11543
6b95a207 11544 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11545 spin_lock_irq(&dev->event_lock);
6b95a207 11546 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11547 /* Before declaring the flip queue wedged, check if
11548 * the hardware completed the operation behind our backs.
11549 */
11550 if (__intel_pageflip_stall_check(dev, crtc)) {
11551 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11552 page_flip_completed(intel_crtc);
11553 } else {
11554 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11555 spin_unlock_irq(&dev->event_lock);
468f0b44 11556
d6bbafa1
CW		 11557 drm_crtc_vblank_put(crtc);
11558 kfree(work);
11559 return -EBUSY;
11560 }
6b95a207
KH		 11561 }
11562 intel_crtc->unpin_work = work;
5e2d7afc 11563 spin_unlock_irq(&dev->event_lock);
6b95a207 11564
b4a98e57
CW		 11565 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11566 flush_workqueue(dev_priv->wq);
11567
75dfca80 11568 /* Reference the objects for the scheduled work. */
ab8d6675 11569 drm_framebuffer_reference(work->old_fb);
05394f39 11570 drm_gem_object_reference(&obj->base);
6b95a207 11571
f4510a27 11572 crtc->primary->fb = fb;
afd65eb4 11573 update_state_fb(crtc->primary);
1ed1f968 11574
e1f99ce6 11575 work->pending_flip_obj = obj;
e1f99ce6 11576
89ed88ba
CW		 11577 ret = i915_mutex_lock_interruptible(dev);
11578 if (ret)
11579 goto cleanup;
11580
b4a98e57 11581 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11582 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11583
75f7f3ec 11584 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11585 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11586
4fa62c89
VS		 11587 if (IS_VALLEYVIEW(dev)) {
11588 ring = &dev_priv->ring[BCS];
ab8d6675 11589 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11590 /* vlv: DISPLAY_FLIP fails to change tiling */
11591 ring = NULL;
48bf5b2d 11592 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11593 ring = &dev_priv->ring[BCS];
4fa62c89 11594 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11595 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11596 if (ring == NULL || ring->id != RCS)
11597 ring = &dev_priv->ring[BCS];
11598 } else {
11599 ring = &dev_priv->ring[RCS];
11600 }
11601
cf5d8a46
CW		 11602 mmio_flip = use_mmio_flip(ring, obj);
11603
11604 /* When using CS flips, we want to emit semaphores between rings.
11605 * However, when using mmio flips we will create a task to do the
11606 * synchronisation, so all we want here is to pin the framebuffer
11607 * into the display plane and skip any waits.
11608 */
82bc3b2d 11609 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11610 crtc->primary->state,
b4716185 11611 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11612 if (ret)
11613 goto cleanup_pending;
6b95a207 11614
121920fa
TU		 11615 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11616 + intel_crtc->dspaddr_offset;
4fa62c89 11617
cf5d8a46 11618 if (mmio_flip) {
84c33a64
SG		 11619 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11620 page_flip_flags);
d6bbafa1
CW		 11621 if (ret)
11622 goto cleanup_unpin;
11623
f06cc1b9
JH		 11624 i915_gem_request_assign(&work->flip_queued_req,
11625 obj->last_write_req);
d6bbafa1 11626 } else {
d94b5030
CW		 11627 if (obj->last_write_req) {
11628 ret = i915_gem_check_olr(obj->last_write_req);
11629 if (ret)
11630 goto cleanup_unpin;
11631 }
11632
84c33a64 11633 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11634 page_flip_flags);
11635 if (ret)
11636 goto cleanup_unpin;
11637
f06cc1b9
JH		 11638 i915_gem_request_assign(&work->flip_queued_req,
11639 intel_ring_get_request(ring));
d6bbafa1
CW		 11640 }
11641
1e3feefd 11642 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11643 work->enable_stall_check = true;
4fa62c89 11644
ab8d6675 11645 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11646 INTEL_FRONTBUFFER_PRIMARY(pipe));
11647
7ff0ebcc 11648 intel_fbc_disable(dev);
f99d7069 11649 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11650 mutex_unlock(&dev->struct_mutex);
11651
e5510fac
JB		 11652 trace_i915_flip_request(intel_crtc->plane, obj);
11653
6b95a207 11654 return 0;
96b099fd 11655
4fa62c89 11656cleanup_unpin:
82bc3b2d 11657 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11658cleanup_pending:
b4a98e57 11659 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11660 mutex_unlock(&dev->struct_mutex);
11661cleanup:
f4510a27 11662 crtc->primary->fb = old_fb;
afd65eb4 11663 update_state_fb(crtc->primary);
89ed88ba
CW		 11664
11665 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11666 drm_framebuffer_unreference(work->old_fb);
96b099fd 11667
5e2d7afc 11668 spin_lock_irq(&dev->event_lock);
96b099fd 11669 intel_crtc->unpin_work = NULL;
5e2d7afc 11670 spin_unlock_irq(&dev->event_lock);
96b099fd 11671
87b6b101 11672 drm_crtc_vblank_put(crtc);
7317c75e 11673free_work:
96b099fd
CW		 11674 kfree(work);
11675
f900db47
CW		 11676 if (ret == -EIO) {
11677out_hang:
53a366b9 11678 ret = intel_plane_restore(primary);
f0d3dad3 11679 if (ret == 0 && event) {
5e2d7afc 11680 spin_lock_irq(&dev->event_lock);
a071fa00 11681 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11682 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11683 }
f900db47 11684 }
96b099fd 11685 return ret;
6b95a207
KH		 11686}
11687
65b38e0d 11688static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11689 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11690 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11691 .atomic_begin = intel_begin_crtc_commit,
11692 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11693};
11694
9a935856
DV		 11695/**
11696 * intel_modeset_update_staged_output_state
11697 *
11698 * Updates the staged output configuration state, e.g. after we've read out the
11699 * current hw state.
11700 */
11701static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11702{
7668851f 11703 struct intel_crtc *crtc;
9a935856
DV		 11704 struct intel_encoder *encoder;
11705 struct intel_connector *connector;
f6e5b160 11706
3a3371ff 11707 for_each_intel_connector(dev, connector) {
9a935856
DV		 11708 connector->new_encoder =
11709 to_intel_encoder(connector->base.encoder);
11710 }
f6e5b160 11711
b2784e15 11712 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11713 encoder->new_crtc =
11714 to_intel_crtc(encoder->base.crtc);
11715 }
7668851f 11716
d3fcc808 11717 for_each_intel_crtc(dev, crtc) {
83d65738 11718 crtc->new_enabled = crtc->base.state->enable;
7668851f 11719 }
f6e5b160
CW		 11720}
11721
d29b2f9d
ACO		 11722/* Transitional helper to copy current connector/encoder state to
11723 * connector->state. This is needed so that code that is partially
11724 * converted to atomic does the right thing.
11725 */
11726static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11727{
11728 struct intel_connector *connector;
11729
11730 for_each_intel_connector(dev, connector) {
11731 if (connector->base.encoder) {
11732 connector->base.state->best_encoder =
11733 connector->base.encoder;
11734 connector->base.state->crtc =
11735 connector->base.encoder->crtc;
11736 } else {
11737 connector->base.state->best_encoder = NULL;
11738 connector->base.state->crtc = NULL;
11739 }
11740 }
11741}
11742
050f7aeb 11743static void
eba905b2 11744connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11745 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11746{
11747 int bpp = pipe_config->pipe_bpp;
11748
11749 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11750 connector->base.base.id,
c23cc417 11751 connector->base.name);
050f7aeb
DV		 11752
11753 /* Don't use an invalid EDID bpc value */
11754 if (connector->base.display_info.bpc &&
11755 connector->base.display_info.bpc * 3 < bpp) {
11756 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11757 bpp, connector->base.display_info.bpc*3);
11758 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11759 }
11760
11761 /* Clamp bpp to 8 on screens without EDID 1.4 */
11762 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11763 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11764 bpp);
11765 pipe_config->pipe_bpp = 24;
11766 }
11767}
11768
4e53c2e0 11769static int
050f7aeb 11770compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11771 struct intel_crtc_state *pipe_config)
4e53c2e0 11772{
050f7aeb 11773 struct drm_device *dev = crtc->base.dev;
1486017f 11774 struct drm_atomic_state *state;
da3ced29
ACO		 11775 struct drm_connector *connector;
11776 struct drm_connector_state *connector_state;
1486017f 11777 int bpp, i;
4e53c2e0 11778
d328c9d7 11779 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11780 bpp = 10*3;
d328c9d7
DV		 11781 else if (INTEL_INFO(dev)->gen >= 5)
11782 bpp = 12*3;
11783 else
11784 bpp = 8*3;
11785
4e53c2e0 11786
4e53c2e0
DV		 11787 pipe_config->pipe_bpp = bpp;
11788
1486017f
ACO		 11789 state = pipe_config->base.state;
11790
4e53c2e0 11791 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11792 for_each_connector_in_state(state, connector, connector_state, i) {
11793 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11794 continue;
11795
da3ced29
ACO		 11796 connected_sink_compute_bpp(to_intel_connector(connector),
11797 pipe_config);
4e53c2e0
DV		 11798 }
11799
11800 return bpp;
11801}
11802
644db711
DV		 11803static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11804{
11805 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11806 "type: 0x%x flags: 0x%x\n",
1342830c 11807 mode->crtc_clock,
644db711
DV		 11808 mode->crtc_hdisplay, mode->crtc_hsync_start,
11809 mode->crtc_hsync_end, mode->crtc_htotal,
11810 mode->crtc_vdisplay, mode->crtc_vsync_start,
11811 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11812}
11813
c0b03411 11814static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11815 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11816 const char *context)
11817{
6a60cd87
CK		 11818 struct drm_device *dev = crtc->base.dev;
11819 struct drm_plane *plane;
11820 struct intel_plane *intel_plane;
11821 struct intel_plane_state *state;
11822 struct drm_framebuffer *fb;
11823
11824 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11825 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11826
11827 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11828 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11829 pipe_config->pipe_bpp, pipe_config->dither);
11830 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11831 pipe_config->has_pch_encoder,
11832 pipe_config->fdi_lanes,
11833 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11834 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11835 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11836 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11837 pipe_config->has_dp_encoder,
11838 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11839 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11840 pipe_config->dp_m_n.tu);
b95af8be
VK		 11841
11842 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11843 pipe_config->has_dp_encoder,
11844 pipe_config->dp_m2_n2.gmch_m,
11845 pipe_config->dp_m2_n2.gmch_n,
11846 pipe_config->dp_m2_n2.link_m,
11847 pipe_config->dp_m2_n2.link_n,
11848 pipe_config->dp_m2_n2.tu);
11849
55072d19
DV		 11850 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11851 pipe_config->has_audio,
11852 pipe_config->has_infoframe);
11853
c0b03411 11854 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11855 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11856 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11857 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11858 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11859 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11860 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11861 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11862 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11863 crtc->num_scalers,
11864 pipe_config->scaler_state.scaler_users,
11865 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11866 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11867 pipe_config->gmch_pfit.control,
11868 pipe_config->gmch_pfit.pgm_ratios,
11869 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11870 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11871 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11872 pipe_config->pch_pfit.size,
11873 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11874 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11875 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11876
415ff0f6
TU		 11877 if (IS_BROXTON(dev)) {
11878 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11879 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11880 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11881 pipe_config->ddi_pll_sel,
11882 pipe_config->dpll_hw_state.ebb0,
11883 pipe_config->dpll_hw_state.pll0,
11884 pipe_config->dpll_hw_state.pll1,
11885 pipe_config->dpll_hw_state.pll2,
11886 pipe_config->dpll_hw_state.pll3,
11887 pipe_config->dpll_hw_state.pll6,
11888 pipe_config->dpll_hw_state.pll8,
11889 pipe_config->dpll_hw_state.pcsdw12);
11890 } else if (IS_SKYLAKE(dev)) {
11891 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11892 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11893 pipe_config->ddi_pll_sel,
11894 pipe_config->dpll_hw_state.ctrl1,
11895 pipe_config->dpll_hw_state.cfgcr1,
11896 pipe_config->dpll_hw_state.cfgcr2);
11897 } else if (HAS_DDI(dev)) {
11898 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11899 pipe_config->ddi_pll_sel,
11900 pipe_config->dpll_hw_state.wrpll);
11901 } else {
11902 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11903 "fp0: 0x%x, fp1: 0x%x\n",
11904 pipe_config->dpll_hw_state.dpll,
11905 pipe_config->dpll_hw_state.dpll_md,
11906 pipe_config->dpll_hw_state.fp0,
11907 pipe_config->dpll_hw_state.fp1);
11908 }
11909
6a60cd87
CK		 11910 DRM_DEBUG_KMS("planes on this crtc\n");
11911 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11912 intel_plane = to_intel_plane(plane);
11913 if (intel_plane->pipe != crtc->pipe)
11914 continue;
11915
11916 state = to_intel_plane_state(plane->state);
11917 fb = state->base.fb;
11918 if (!fb) {
11919 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11920 "disabled, scaler_id = %d\n",
11921 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11922 plane->base.id, intel_plane->pipe,
11923 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11924 drm_plane_index(plane), state->scaler_id);
11925 continue;
11926 }
11927
11928 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11929 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11930 plane->base.id, intel_plane->pipe,
11931 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11932 drm_plane_index(plane));
11933 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11934 fb->base.id, fb->width, fb->height, fb->pixel_format);
11935 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11936 state->scaler_id,
11937 state->src.x1 >> 16, state->src.y1 >> 16,
11938 drm_rect_width(&state->src) >> 16,
11939 drm_rect_height(&state->src) >> 16,
11940 state->dst.x1, state->dst.y1,
11941 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11942 }
c0b03411
DV		 11943}
11944
bc079e8b
VS		 11945static bool encoders_cloneable(const struct intel_encoder *a,
11946 const struct intel_encoder *b)
accfc0c5 11947{
bc079e8b
VS		 11948 /* masks could be asymmetric, so check both ways */
11949 return a == b || (a->cloneable & (1 << b->type) &&
11950 b->cloneable & (1 << a->type));
11951}
11952
98a221da
ACO		 11953static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11954 struct intel_crtc *crtc,
bc079e8b
VS		 11955 struct intel_encoder *encoder)
11956{
bc079e8b 11957 struct intel_encoder *source_encoder;
da3ced29 11958 struct drm_connector *connector;
98a221da
ACO		 11959 struct drm_connector_state *connector_state;
11960 int i;
bc079e8b 11961
da3ced29 11962 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11963 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11964 continue;
11965
98a221da
ACO		 11966 source_encoder =
11967 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11968 if (!encoders_cloneable(encoder, source_encoder))
11969 return false;
11970 }
11971
11972 return true;
11973}
11974
98a221da
ACO		 11975static bool check_encoder_cloning(struct drm_atomic_state *state,
11976 struct intel_crtc *crtc)
bc079e8b 11977{
accfc0c5 11978 struct intel_encoder *encoder;
da3ced29 11979 struct drm_connector *connector;
98a221da
ACO		 11980 struct drm_connector_state *connector_state;
11981 int i;
accfc0c5 11982
da3ced29 11983 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11984 if (connector_state->crtc != &crtc->base)
11985 continue;
11986
11987 encoder = to_intel_encoder(connector_state->best_encoder);
11988 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11989 return false;
accfc0c5
DV		 11990 }
11991
bc079e8b 11992 return true;
accfc0c5
DV		 11993}
11994
5448a00d 11995static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11996{
5448a00d
ACO		 11997 struct drm_device *dev = state->dev;
11998 struct intel_encoder *encoder;
da3ced29 11999 struct drm_connector *connector;
5448a00d 12000 struct drm_connector_state *connector_state;
00f0b378 12001 unsigned int used_ports = 0;
5448a00d 12002 int i;
00f0b378
VS		 12003
12004 /*
12005 * Walk the connector list instead of the encoder
12006 * list to detect the problem on ddi platforms
12007 * where there's just one encoder per digital port.
12008 */
da3ced29 12009 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12010 if (!connector_state->best_encoder)
00f0b378
VS		 12011 continue;
12012
5448a00d
ACO		 12013 encoder = to_intel_encoder(connector_state->best_encoder);
12014
12015 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12016
12017 switch (encoder->type) {
12018 unsigned int port_mask;
12019 case INTEL_OUTPUT_UNKNOWN:
12020 if (WARN_ON(!HAS_DDI(dev)))
12021 break;
12022 case INTEL_OUTPUT_DISPLAYPORT:
12023 case INTEL_OUTPUT_HDMI:
12024 case INTEL_OUTPUT_EDP:
12025 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12026
12027 /* the same port mustn't appear more than once */
12028 if (used_ports & port_mask)
12029 return false;
12030
12031 used_ports |= port_mask;
12032 default:
12033 break;
12034 }
12035 }
12036
12037 return true;
12038}
12039
83a57153
ACO		 12040static void
12041clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12042{
12043 struct drm_crtc_state tmp_state;
663a3640 12044 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12045 struct intel_dpll_hw_state dpll_hw_state;
12046 enum intel_dpll_id shared_dpll;
8504c74c 12047 uint32_t ddi_pll_sel;
83a57153 12048
7546a384
ACO		 12049 /* FIXME: before the switch to atomic started, a new pipe_config was
12050 * kzalloc'd. Code that depends on any field being zero should be
12051 * fixed, so that the crtc_state can be safely duplicated. For now,
12052 * only fields that are know to not cause problems are preserved. */
12053
83a57153 12054 tmp_state = crtc_state->base;
663a3640 12055 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12056 shared_dpll = crtc_state->shared_dpll;
12057 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12058 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12059
83a57153 12060 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12061
83a57153 12062 crtc_state->base = tmp_state;
663a3640 12063 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12064 crtc_state->shared_dpll = shared_dpll;
12065 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12066 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12067}
12068
548ee15b 12069static int
b8cecdf5 12070intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 12071 struct drm_atomic_state *state,
12072 struct intel_crtc_state *pipe_config)
ee7b9f93 12073{
7758a113 12074 struct intel_encoder *encoder;
da3ced29 12075 struct drm_connector *connector;
0b901879 12076 struct drm_connector_state *connector_state;
d328c9d7 12077 int base_bpp, ret = -EINVAL;
0b901879 12078 int i;
e29c22c0 12079 bool retry = true;
ee7b9f93 12080
98a221da 12081 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 12082 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 12083 return -EINVAL;
accfc0c5
DV		 12084 }
12085
5448a00d 12086 if (!check_digital_port_conflicts(state)) {
00f0b378 12087 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 12088 return -EINVAL;
00f0b378
VS		 12089 }
12090
cdba954e
ACO		 12091 /*
12092 * XXX: Add all connectors to make the crtc state match the encoders.
12093 */
12094 if (!needs_modeset(&pipe_config->base)) {
12095 ret = drm_atomic_add_affected_connectors(state, crtc);
12096 if (ret)
12097 return ret;
12098 }
12099
83a57153 12100 clear_intel_crtc_state(pipe_config);
7758a113 12101
e143a21c
DV		 12102 pipe_config->cpu_transcoder =
12103 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12104
2960bc9c
ID		 12105 /*
12106 * Sanitize sync polarity flags based on requested ones. If neither
12107 * positive or negative polarity is requested, treat this as meaning
12108 * negative polarity.
12109 */
2d112de7 12110 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12111 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12112 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12113
2d112de7 12114 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12115 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12116 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12117
050f7aeb
DV		 12118 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12119 * plane pixel format and any sink constraints into account. Returns the
12120 * source plane bpp so that dithering can be selected on mismatches
12121 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12122 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12123 pipe_config);
12124 if (base_bpp < 0)
4e53c2e0
DV		 12125 goto fail;
12126
e41a56be
VS		 12127 /*
12128 * Determine the real pipe dimensions. Note that stereo modes can
12129 * increase the actual pipe size due to the frame doubling and
12130 * insertion of additional space for blanks between the frame. This
12131 * is stored in the crtc timings. We use the requested mode to do this
12132 * computation to clearly distinguish it from the adjusted mode, which
12133 * can be changed by the connectors in the below retry loop.
12134 */
2d112de7 12135 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12136 &pipe_config->pipe_src_w,
12137 &pipe_config->pipe_src_h);
e41a56be 12138
e29c22c0 12139encoder_retry:
ef1b460d 12140 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12141 pipe_config->port_clock = 0;
ef1b460d 12142 pipe_config->pixel_multiplier = 1;
ff9a6750 12143
135c81b8 12144 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12145 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12146 CRTC_STEREO_DOUBLE);
135c81b8 12147
7758a113
DV		 12148 /* Pass our mode to the connectors and the CRTC to give them a chance to
12149 * adjust it according to limitations or connector properties, and also
12150 * a chance to reject the mode entirely.
47f1c6c9 12151 */
da3ced29 12152 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12153 if (connector_state->crtc != crtc)
7758a113 12154 continue;
7ae89233 12155
0b901879
ACO		 12156 encoder = to_intel_encoder(connector_state->best_encoder);
12157
efea6e8e
DV		 12158 if (!(encoder->compute_config(encoder, pipe_config))) {
12159 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12160 goto fail;
12161 }
ee7b9f93 12162 }
47f1c6c9 12163
ff9a6750
DV		 12164 /* Set default port clock if not overwritten by the encoder. Needs to be
12165 * done afterwards in case the encoder adjusts the mode. */
12166 if (!pipe_config->port_clock)
2d112de7 12167 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12168 * pipe_config->pixel_multiplier;
ff9a6750 12169
a43f6e0f 12170 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12171 if (ret < 0) {
7758a113
DV		 12172 DRM_DEBUG_KMS("CRTC fixup failed\n");
12173 goto fail;
ee7b9f93 12174 }
e29c22c0
DV		 12175
12176 if (ret == RETRY) {
12177 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12178 ret = -EINVAL;
12179 goto fail;
12180 }
12181
12182 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12183 retry = false;
12184 goto encoder_retry;
12185 }
12186
d328c9d7 12187 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12188 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12189 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12190
cdba954e
ACO		 12191 /* Check if we need to force a modeset */
12192 if (pipe_config->has_audio !=
85a96e7a 12193 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12194 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12195 ret = drm_atomic_add_affected_planes(state, crtc);
12196 }
cdba954e
ACO		 12197
12198 /*
12199 * Note we have an issue here with infoframes: current code
12200 * only updates them on the full mode set path per hw
12201 * requirements. So here we should be checking for any
12202 * required changes and forcing a mode set.
12203 */
7758a113 12204fail:
548ee15b 12205 return ret;
ee7b9f93 12206}
47f1c6c9 12207
ea9d758d 12208static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12209{
ea9d758d 12210 struct drm_encoder *encoder;
f6e5b160 12211 struct drm_device *dev = crtc->dev;
f6e5b160 12212
ea9d758d
DV		 12213 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12214 if (encoder->crtc == crtc)
12215 return true;
12216
12217 return false;
12218}
12219
12220static void
0a9ab303 12221intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12222{
0a9ab303 12223 struct drm_device *dev = state->dev;
ba41c0de 12224 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12225 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12226 struct drm_crtc *crtc;
12227 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12228 struct drm_connector *connector;
12229
ba41c0de 12230 intel_shared_dpll_commit(dev_priv);
69024de8 12231 drm_atomic_helper_swap_state(state->dev, state);
ba41c0de 12232
b2784e15 12233 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12234 if (!intel_encoder->base.crtc)
12235 continue;
12236
69024de8
ML		 12237 crtc = intel_encoder->base.crtc;
12238 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12239 if (!crtc_state || !needs_modeset(crtc->state))
12240 continue;
ea9d758d 12241
69024de8 12242 intel_encoder->connectors_active = false;
ea9d758d
DV		 12243 }
12244
3cb480bc
ML		 12245 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12246 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12247
7668851f 12248 /* Double check state. */
0a9ab303
ACO		 12249 for_each_crtc(dev, crtc) {
12250 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12251
12252 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
ea9d758d
DV		 12253 }
12254
12255 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12256 if (!connector->encoder || !connector->encoder->crtc)
12257 continue;
12258
69024de8
ML		 12259 crtc = connector->encoder->crtc;
12260 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12261 if (!crtc_state || !needs_modeset(crtc->state))
12262 continue;
ea9d758d 12263
53d9f4e9 12264 if (crtc->state->active) {
69024de8
ML		 12265 struct drm_property *dpms_property =
12266 dev->mode_config.dpms_property;
68d34720 12267
69024de8
ML		 12268 connector->dpms = DRM_MODE_DPMS_ON;
12269 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12270
69024de8
ML		 12271 intel_encoder = to_intel_encoder(connector->encoder);
12272 intel_encoder->connectors_active = true;
12273 } else
12274 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12275 }
ea9d758d
DV		 12276}
12277
3bd26263 12278static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12279{
3bd26263 12280 int diff;
f1f644dc
JB		 12281
12282 if (clock1 == clock2)
12283 return true;
12284
12285 if (!clock1 || !clock2)
12286 return false;
12287
12288 diff = abs(clock1 - clock2);
12289
12290 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12291 return true;
12292
12293 return false;
12294}
12295
25c5b266
DV		 12296#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12297 list_for_each_entry((intel_crtc), \
12298 &(dev)->mode_config.crtc_list, \
12299 base.head) \
0973f18f 12300 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12301
0e8ffe1b 12302static bool
2fa2fe9a 12303intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12304 struct intel_crtc_state *current_config,
12305 struct intel_crtc_state *pipe_config)
0e8ffe1b 12306{
66e985c0
DV		 12307#define PIPE_CONF_CHECK_X(name) \
12308 if (current_config->name != pipe_config->name) { \
12309 DRM_ERROR("mismatch in " #name " " \
12310 "(expected 0x%08x, found 0x%08x)\n", \
12311 current_config->name, \
12312 pipe_config->name); \
12313 return false; \
12314 }
12315
08a24034
DV		 12316#define PIPE_CONF_CHECK_I(name) \
12317 if (current_config->name != pipe_config->name) { \
12318 DRM_ERROR("mismatch in " #name " " \
12319 "(expected %i, found %i)\n", \
12320 current_config->name, \
12321 pipe_config->name); \
12322 return false; \
88adfff1
DV		 12323 }
12324
b95af8be
VK		 12325/* This is required for BDW+ where there is only one set of registers for
12326 * switching between high and low RR.
12327 * This macro can be used whenever a comparison has to be made between one
12328 * hw state and multiple sw state variables.
12329 */
12330#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12331 if ((current_config->name != pipe_config->name) && \
12332 (current_config->alt_name != pipe_config->name)) { \
12333 DRM_ERROR("mismatch in " #name " " \
12334 "(expected %i or %i, found %i)\n", \
12335 current_config->name, \
12336 current_config->alt_name, \
12337 pipe_config->name); \
12338 return false; \
12339 }
12340
1bd1bd80
DV		 12341#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12342 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12343 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12344 "(expected %i, found %i)\n", \
12345 current_config->name & (mask), \
12346 pipe_config->name & (mask)); \
12347 return false; \
12348 }
12349
5e550656
VS		 12350#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12351 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12352 DRM_ERROR("mismatch in " #name " " \
12353 "(expected %i, found %i)\n", \
12354 current_config->name, \
12355 pipe_config->name); \
12356 return false; \
12357 }
12358
bb760063
DV		 12359#define PIPE_CONF_QUIRK(quirk) \
12360 ((current_config->quirks | pipe_config->quirks) & (quirk))
12361
eccb140b
DV		 12362 PIPE_CONF_CHECK_I(cpu_transcoder);
12363
08a24034
DV		 12364 PIPE_CONF_CHECK_I(has_pch_encoder);
12365 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12366 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12367 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12368 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12369 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12370 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12371
eb14cb74 12372 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12373
12374 if (INTEL_INFO(dev)->gen < 8) {
12375 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12376 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12377 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12378 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12379 PIPE_CONF_CHECK_I(dp_m_n.tu);
12380
12381 if (current_config->has_drrs) {
12382 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12383 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12384 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12385 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12386 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12387 }
12388 } else {
12389 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12390 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12391 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12392 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12393 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12394 }
eb14cb74 12395
2d112de7
ACO		 12396 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12397 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12398 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12399 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12400 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12401 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12402
2d112de7
ACO		 12403 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12404 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12405 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12406 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12408 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12409
c93f54cf 12410 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12411 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12412 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12413 IS_VALLEYVIEW(dev))
12414 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12415 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12416
9ed109a7
DV		 12417 PIPE_CONF_CHECK_I(has_audio);
12418
2d112de7 12419 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12420 DRM_MODE_FLAG_INTERLACE);
12421
bb760063 12422 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12423 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12424 DRM_MODE_FLAG_PHSYNC);
2d112de7 12425 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12426 DRM_MODE_FLAG_NHSYNC);
2d112de7 12427 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12428 DRM_MODE_FLAG_PVSYNC);
2d112de7 12429 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12430 DRM_MODE_FLAG_NVSYNC);
12431 }
045ac3b5 12432
37327abd
VS		 12433 PIPE_CONF_CHECK_I(pipe_src_w);
12434 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12435
9953599b
DV		 12436 /*
12437 * FIXME: BIOS likes to set up a cloned config with lvds+external
12438 * screen. Since we don't yet re-compute the pipe config when moving
12439 * just the lvds port away to another pipe the sw tracking won't match.
12440 *
12441 * Proper atomic modesets with recomputed global state will fix this.
12442 * Until then just don't check gmch state for inherited modes.
12443 */
12444 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12445 PIPE_CONF_CHECK_I(gmch_pfit.control);
12446 /* pfit ratios are autocomputed by the hw on gen4+ */
12447 if (INTEL_INFO(dev)->gen < 4)
12448 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12449 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12450 }
12451
fd4daa9c
CW		 12452 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12453 if (current_config->pch_pfit.enabled) {
12454 PIPE_CONF_CHECK_I(pch_pfit.pos);
12455 PIPE_CONF_CHECK_I(pch_pfit.size);
12456 }
2fa2fe9a 12457
a1b2278e
CK		 12458 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12459
e59150dc
JB		 12460 /* BDW+ don't expose a synchronous way to read the state */
12461 if (IS_HASWELL(dev))
12462 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12463
282740f7
VS		 12464 PIPE_CONF_CHECK_I(double_wide);
12465
26804afd
DV		 12466 PIPE_CONF_CHECK_X(ddi_pll_sel);
12467
c0d43d62 12468 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12469 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12470 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12471 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12472 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12473 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12474 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12475 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12476 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12477
42571aef
VS		 12478 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12479 PIPE_CONF_CHECK_I(pipe_bpp);
12480
2d112de7 12481 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12482 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12483
66e985c0 12484#undef PIPE_CONF_CHECK_X
08a24034 12485#undef PIPE_CONF_CHECK_I
b95af8be 12486#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12487#undef PIPE_CONF_CHECK_FLAGS
5e550656 12488#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12489#undef PIPE_CONF_QUIRK
88adfff1 12490
0e8ffe1b
DV		 12491 return true;
12492}
12493
08db6652
DL		 12494static void check_wm_state(struct drm_device *dev)
12495{
12496 struct drm_i915_private *dev_priv = dev->dev_private;
12497 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12498 struct intel_crtc *intel_crtc;
12499 int plane;
12500
12501 if (INTEL_INFO(dev)->gen < 9)
12502 return;
12503
12504 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12505 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12506
12507 for_each_intel_crtc(dev, intel_crtc) {
12508 struct skl_ddb_entry *hw_entry, *sw_entry;
12509 const enum pipe pipe = intel_crtc->pipe;
12510
12511 if (!intel_crtc->active)
12512 continue;
12513
12514 /* planes */
dd740780 12515 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12516 hw_entry = &hw_ddb.plane[pipe][plane];
12517 sw_entry = &sw_ddb->plane[pipe][plane];
12518
12519 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12520 continue;
12521
12522 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12523 "(expected (%u,%u), found (%u,%u))\n",
12524 pipe_name(pipe), plane + 1,
12525 sw_entry->start, sw_entry->end,
12526 hw_entry->start, hw_entry->end);
12527 }
12528
12529 /* cursor */
12530 hw_entry = &hw_ddb.cursor[pipe];
12531 sw_entry = &sw_ddb->cursor[pipe];
12532
12533 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12534 continue;
12535
12536 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12537 "(expected (%u,%u), found (%u,%u))\n",
12538 pipe_name(pipe),
12539 sw_entry->start, sw_entry->end,
12540 hw_entry->start, hw_entry->end);
12541 }
12542}
12543
91d1b4bd
DV		 12544static void
12545check_connector_state(struct drm_device *dev)
8af6cf88 12546{
8af6cf88
DV		 12547 struct intel_connector *connector;
12548
3a3371ff 12549 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12550 /* This also checks the encoder/connector hw state with the
12551 * ->get_hw_state callbacks. */
12552 intel_connector_check_state(connector);
12553
e2c719b7 12554 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12555 "connector's staged encoder doesn't match current encoder\n");
12556 }
91d1b4bd
DV		 12557}
12558
12559static void
12560check_encoder_state(struct drm_device *dev)
12561{
12562 struct intel_encoder *encoder;
12563 struct intel_connector *connector;
8af6cf88 12564
b2784e15 12565 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12566 bool enabled = false;
12567 bool active = false;
12568 enum pipe pipe, tracked_pipe;
12569
12570 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12571 encoder->base.base.id,
8e329a03 12572 encoder->base.name);
8af6cf88 12573
e2c719b7 12574 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12575 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12576 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12577 "encoder's active_connectors set, but no crtc\n");
12578
3a3371ff 12579 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12580 if (connector->base.encoder != &encoder->base)
12581 continue;
12582 enabled = true;
12583 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12584 active = true;
12585 }
0e32b39c
DA		 12586 /*
12587 * for MST connectors if we unplug the connector is gone
12588 * away but the encoder is still connected to a crtc
12589 * until a modeset happens in response to the hotplug.
12590 */
12591 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12592 continue;
12593
e2c719b7 12594 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12595 "encoder's enabled state mismatch "
12596 "(expected %i, found %i)\n",
12597 !!encoder->base.crtc, enabled);
e2c719b7 12598 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12599 "active encoder with no crtc\n");
12600
e2c719b7 12601 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12602 "encoder's computed active state doesn't match tracked active state "
12603 "(expected %i, found %i)\n", active, encoder->connectors_active);
12604
12605 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12606 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12607 "encoder's hw state doesn't match sw tracking "
12608 "(expected %i, found %i)\n",
12609 encoder->connectors_active, active);
12610
12611 if (!encoder->base.crtc)
12612 continue;
12613
12614 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12615 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12616 "active encoder's pipe doesn't match"
12617 "(expected %i, found %i)\n",
12618 tracked_pipe, pipe);
12619
12620 }
91d1b4bd
DV		 12621}
12622
12623static void
12624check_crtc_state(struct drm_device *dev)
12625{
fbee40df 12626 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12627 struct intel_crtc *crtc;
12628 struct intel_encoder *encoder;
5cec258b 12629 struct intel_crtc_state pipe_config;
8af6cf88 12630
d3fcc808 12631 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12632 bool enabled = false;
12633 bool active = false;
12634
045ac3b5
JB		 12635 memset(&pipe_config, 0, sizeof(pipe_config));
12636
8af6cf88
DV		 12637 DRM_DEBUG_KMS("[CRTC:%d]\n",
12638 crtc->base.base.id);
12639
83d65738 12640 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12641 "active crtc, but not enabled in sw tracking\n");
12642
b2784e15 12643 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12644 if (encoder->base.crtc != &crtc->base)
12645 continue;
12646 enabled = true;
12647 if (encoder->connectors_active)
12648 active = true;
12649 }
6c49f241 12650
e2c719b7 12651 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12652 "crtc's computed active state doesn't match tracked active state "
12653 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12654 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12655 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12656 "(expected %i, found %i)\n", enabled,
12657 crtc->base.state->enable);
8af6cf88 12658
0e8ffe1b
DV		 12659 active = dev_priv->display.get_pipe_config(crtc,
12660 &pipe_config);
d62cf62a 12661
b6b5d049
VS		 12662 /* hw state is inconsistent with the pipe quirk */
12663 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12664 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12665 active = crtc->active;
12666
b2784e15 12667 for_each_intel_encoder(dev, encoder) {
3eaba51c 12668 enum pipe pipe;
6c49f241
DV		 12669 if (encoder->base.crtc != &crtc->base)
12670 continue;
1d37b689 12671 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12672 encoder->get_config(encoder, &pipe_config);
12673 }
12674
e2c719b7 12675 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12676 "crtc active state doesn't match with hw state "
12677 "(expected %i, found %i)\n", crtc->active, active);
12678
53d9f4e9
ML		 12679 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12680 "transitional active state does not match atomic hw state "
12681 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12682
c0b03411 12683 if (active &&
6e3c9717 12684 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12685 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12686 intel_dump_pipe_config(crtc, &pipe_config,
12687 "[hw state]");
6e3c9717 12688 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12689 "[sw state]");
12690 }
8af6cf88
DV		 12691 }
12692}
12693
91d1b4bd
DV		 12694static void
12695check_shared_dpll_state(struct drm_device *dev)
12696{
fbee40df 12697 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12698 struct intel_crtc *crtc;
12699 struct intel_dpll_hw_state dpll_hw_state;
12700 int i;
5358901f
DV		 12701
12702 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12703 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12704 int enabled_crtcs = 0, active_crtcs = 0;
12705 bool active;
12706
12707 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12708
12709 DRM_DEBUG_KMS("%s\n", pll->name);
12710
12711 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12712
e2c719b7 12713 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12714 "more active pll users than references: %i vs %i\n",
3e369b76 12715 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12716 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12717 "pll in active use but not on in sw tracking\n");
e2c719b7 12718 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12719 "pll in on but not on in use in sw tracking\n");
e2c719b7 12720 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12721 "pll on state mismatch (expected %i, found %i)\n",
12722 pll->on, active);
12723
d3fcc808 12724 for_each_intel_crtc(dev, crtc) {
83d65738 12725 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12726 enabled_crtcs++;
12727 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12728 active_crtcs++;
12729 }
e2c719b7 12730 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12731 "pll active crtcs mismatch (expected %i, found %i)\n",
12732 pll->active, active_crtcs);
e2c719b7 12733 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12734 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12735 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12736
e2c719b7 12737 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12738 sizeof(dpll_hw_state)),
12739 "pll hw state mismatch\n");
5358901f 12740 }
8af6cf88
DV		 12741}
12742
91d1b4bd
DV		 12743void
12744intel_modeset_check_state(struct drm_device *dev)
12745{
08db6652 12746 check_wm_state(dev);
91d1b4bd
DV		 12747 check_connector_state(dev);
12748 check_encoder_state(dev);
12749 check_crtc_state(dev);
12750 check_shared_dpll_state(dev);
12751}
12752
5cec258b 12753void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12754 int dotclock)
12755{
12756 /*
12757 * FDI already provided one idea for the dotclock.
12758 * Yell if the encoder disagrees.
12759 */
2d112de7 12760 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12761 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12762 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12763}
12764
80715b2f
VS		 12765static void update_scanline_offset(struct intel_crtc *crtc)
12766{
12767 struct drm_device *dev = crtc->base.dev;
12768
12769 /*
12770 * The scanline counter increments at the leading edge of hsync.
12771 *
12772 * On most platforms it starts counting from vtotal-1 on the
12773 * first active line. That means the scanline counter value is
12774 * always one less than what we would expect. Ie. just after
12775 * start of vblank, which also occurs at start of hsync (on the
12776 * last active line), the scanline counter will read vblank_start-1.
12777 *
12778 * On gen2 the scanline counter starts counting from 1 instead
12779 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12780 * to keep the value positive), instead of adding one.
12781 *
12782 * On HSW+ the behaviour of the scanline counter depends on the output
12783 * type. For DP ports it behaves like most other platforms, but on HDMI
12784 * there's an extra 1 line difference. So we need to add two instead of
12785 * one to the value.
12786 */
12787 if (IS_GEN2(dev)) {
6e3c9717 12788 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12789 int vtotal;
12790
12791 vtotal = mode->crtc_vtotal;
12792 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12793 vtotal /= 2;
12794
12795 crtc->scanline_offset = vtotal - 1;
12796 } else if (HAS_DDI(dev) &&
409ee761 12797 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12798 crtc->scanline_offset = 2;
12799 } else
12800 crtc->scanline_offset = 1;
12801}
12802
5cec258b 12803static struct intel_crtc_state *
7f27126e 12804intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12805 struct drm_atomic_state *state)
7f27126e 12806{
548ee15b 12807 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12808 int ret = 0;
12809
8c7b5ccb
ACO		 12810 ret = drm_atomic_helper_check_modeset(state->dev, state);
12811 if (ret)
12812 return ERR_PTR(ret);
7f27126e 12813
7f27126e
JB		 12814 /*
12815 * Note this needs changes when we start tracking multiple modes
12816 * and crtcs. At that point we'll need to compute the whole config
12817 * (i.e. one pipe_config for each crtc) rather than just the one
12818 * for this crtc.
12819 */
548ee15b
ACO		 12820 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12821 if (IS_ERR(pipe_config))
12822 return pipe_config;
83a57153 12823
53d9f4e9
ML		 12824 if (!pipe_config->base.enable &&
12825 WARN_ON(pipe_config->base.active))
12826 pipe_config->base.active = false;
12827
4fed33f6 12828 if (!pipe_config->base.enable)
548ee15b 12829 return pipe_config;
7f27126e 12830
8c7b5ccb 12831 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12832 if (ret)
12833 return ERR_PTR(ret);
12834
cdba954e 12835 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, "[modeset]");
db7542dd 12836
8c7b5ccb
ACO		 12837 ret = drm_atomic_helper_check_planes(state->dev, state);
12838 if (ret)
12839 return ERR_PTR(ret);
12840
548ee15b 12841 return pipe_config;
7f27126e
JB		 12842}
12843
0a9ab303 12844static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12845{
225da59b 12846 struct drm_device *dev = state->dev;
ed6739ef 12847 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12848 unsigned clear_pipes = 0;
ed6739ef 12849 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12850 struct intel_crtc_state *intel_crtc_state;
12851 struct drm_crtc *crtc;
12852 struct drm_crtc_state *crtc_state;
ed6739ef 12853 int ret = 0;
0a9ab303 12854 int i;
ed6739ef
ACO		 12855
12856 if (!dev_priv->display.crtc_compute_clock)
12857 return 0;
12858
0a9ab303
ACO		 12859 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12860 intel_crtc = to_intel_crtc(crtc);
4978cc93 12861 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12862
4978cc93 12863 if (needs_modeset(crtc_state)) {
0a9ab303 12864 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12865 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12866 }
0a9ab303
ACO		 12867 }
12868
ed6739ef
ACO		 12869 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12870 if (ret)
12871 goto done;
12872
0a9ab303
ACO		 12873 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12874 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12875 continue;
12876
0a9ab303
ACO		 12877 intel_crtc = to_intel_crtc(crtc);
12878 intel_crtc_state = to_intel_crtc_state(crtc_state);
12879
ed6739ef 12880 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12881 intel_crtc_state);
ed6739ef
ACO		 12882 if (ret) {
12883 intel_shared_dpll_abort_config(dev_priv);
12884 goto done;
12885 }
12886 }
12887
12888done:
12889 return ret;
12890}
12891
054518dd
ACO		 12892/* Code that should eventually be part of atomic_check() */
12893static int __intel_set_mode_checks(struct drm_atomic_state *state)
12894{
12895 struct drm_device *dev = state->dev;
12896 int ret;
12897
12898 /*
12899 * See if the config requires any additional preparation, e.g.
12900 * to adjust global state with pipes off. We need to do this
12901 * here so we can get the modeset_pipe updated config for the new
12902 * mode set on this crtc. For other crtcs we need to use the
12903 * adjusted_mode bits in the crtc directly.
12904 */
b432e5cf
VS		 12905 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12906 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12907 ret = valleyview_modeset_global_pipes(state);
12908 else
12909 ret = broadwell_modeset_global_pipes(state);
12910
054518dd
ACO		 12911 if (ret)
12912 return ret;
12913 }
12914
12915 ret = __intel_set_mode_setup_plls(state);
12916 if (ret)
12917 return ret;
12918
12919 return 0;
12920}
12921
c72d969b 12922static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 12923{
c72d969b 12924 struct drm_device *dev = state->dev;
fbee40df 12925 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 12926 struct drm_crtc *crtc;
12927 struct drm_crtc_state *crtc_state;
c0c36b94 12928 int ret = 0;
0a9ab303 12929 int i;
a6778b3c 12930
054518dd
ACO		 12931 ret = __intel_set_mode_checks(state);
12932 if (ret < 0)
12933 return ret;
12934
d4afb8cc
ACO		 12935 ret = drm_atomic_helper_prepare_planes(dev, state);
12936 if (ret)
12937 return ret;
12938
0a9ab303 12939 for_each_crtc_in_state(state, crtc, crtc_state, i) {
53d9f4e9 12940 if (!needs_modeset(crtc_state) || !crtc->state->active)
0a9ab303 12941 continue;
460da916 12942
69024de8
ML		 12943 intel_crtc_disable_planes(crtc);
12944 dev_priv->display.crtc_disable(crtc);
12945 if (!crtc_state->enable)
12946 drm_plane_helper_disable(crtc->primary);
ea9d758d 12947 }
a6778b3c 12948
ea9d758d
DV		 12949 /* Only after disabling all output pipelines that will be changed can we
12950 * update the the output configuration. */
0a9ab303 12951 intel_modeset_update_state(state);
f6e5b160 12952
a821fc46
ACO		 12953 /* The state has been swaped above, so state actually contains the
12954 * old state now. */
12955
304603f4 12956 modeset_update_crtc_power_domains(state);
47fab737 12957
d4afb8cc 12958 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12959
12960 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12961 for_each_crtc_in_state(state, crtc, crtc_state, i) {
53d9f4e9 12962 if (!needs_modeset(crtc->state) || !crtc->state->active)
0a9ab303
ACO		 12963 continue;
12964
12965 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12966
0a9ab303
ACO		 12967 dev_priv->display.crtc_enable(crtc);
12968 intel_crtc_enable_planes(crtc);
80715b2f 12969 }
a6778b3c 12970
a6778b3c 12971 /* FIXME: add subpixel order */
83a57153 12972
d4afb8cc
ACO		 12973 drm_atomic_helper_cleanup_planes(dev, state);
12974
2bfb4627
ACO		 12975 drm_atomic_state_free(state);
12976
9eb45f22 12977 return 0;
f6e5b160
CW		 12978}
12979
0a9ab303 12980static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12981 struct intel_crtc_state *pipe_config)
f30da187
DV		 12982{
12983 int ret;
12984
c72d969b 12985 ret = __intel_set_mode(pipe_config->base.state);
f30da187
DV		 12986
12987 if (ret == 0)
12988 intel_modeset_check_state(crtc->dev);
12989
12990 return ret;
12991}
12992
7f27126e 12993static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12994 struct drm_atomic_state *state)
7f27126e 12995{
5cec258b 12996 struct intel_crtc_state *pipe_config;
83a57153 12997 int ret = 0;
7f27126e 12998
8c7b5ccb 12999 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 13000 if (IS_ERR(pipe_config)) {
13001 ret = PTR_ERR(pipe_config);
13002 goto out;
13003 }
13004
8c7b5ccb 13005 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 13006 if (ret)
13007 goto out;
7f27126e 13008
83a57153
ACO		 13009out:
13010 return ret;
7f27126e
JB		 13011}
13012
c0c36b94
CW		 13013void intel_crtc_restore_mode(struct drm_crtc *crtc)
13014{
83a57153
ACO		 13015 struct drm_device *dev = crtc->dev;
13016 struct drm_atomic_state *state;
4be07317 13017 struct intel_crtc *intel_crtc;
83a57153
ACO		 13018 struct intel_encoder *encoder;
13019 struct intel_connector *connector;
13020 struct drm_connector_state *connector_state;
4be07317 13021 struct intel_crtc_state *crtc_state;
2bfb4627 13022 int ret;
83a57153
ACO		 13023
13024 state = drm_atomic_state_alloc(dev);
13025 if (!state) {
13026 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13027 crtc->base.id);
13028 return;
13029 }
13030
13031 state->acquire_ctx = dev->mode_config.acquire_ctx;
13032
13033 /* The force restore path in the HW readout code relies on the staged
13034 * config still keeping the user requested config while the actual
13035 * state has been overwritten by the configuration read from HW. We
13036 * need to copy the staged config to the atomic state, otherwise the
13037 * mode set will just reapply the state the HW is already in. */
13038 for_each_intel_encoder(dev, encoder) {
13039 if (&encoder->new_crtc->base != crtc)
13040 continue;
13041
13042 for_each_intel_connector(dev, connector) {
13043 if (connector->new_encoder != encoder)
13044 continue;
13045
13046 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13047 if (IS_ERR(connector_state)) {
13048 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13049 connector->base.base.id,
13050 connector->base.name,
13051 PTR_ERR(connector_state));
13052 continue;
13053 }
13054
13055 connector_state->crtc = crtc;
13056 connector_state->best_encoder = &encoder->base;
13057 }
13058 }
13059
4be07317
ACO		 13060 for_each_intel_crtc(dev, intel_crtc) {
13061 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13062 continue;
13063
13064 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13065 if (IS_ERR(crtc_state)) {
13066 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13067 intel_crtc->base.base.id,
13068 PTR_ERR(crtc_state));
13069 continue;
13070 }
13071
49d6fa21
ML		 13072 crtc_state->base.active = crtc_state->base.enable =
13073 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13074
13075 if (&intel_crtc->base == crtc)
13076 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13077 }
13078
d3a40d1b
ACO		 13079 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13080 crtc->primary->fb, crtc->x, crtc->y);
13081
2bfb4627
ACO		 13082 ret = intel_set_mode(crtc, state);
13083 if (ret)
13084 drm_atomic_state_free(state);
c0c36b94
CW		 13085}
13086
25c5b266
DV		 13087#undef for_each_intel_crtc_masked
13088
b7885264
ACO		 13089static bool intel_connector_in_mode_set(struct intel_connector *connector,
13090 struct drm_mode_set *set)
13091{
13092 int ro;
13093
13094 for (ro = 0; ro < set->num_connectors; ro++)
13095 if (set->connectors[ro] == &connector->base)
13096 return true;
13097
13098 return false;
13099}
13100
2e431051 13101static int
9a935856
DV		 13102intel_modeset_stage_output_state(struct drm_device *dev,
13103 struct drm_mode_set *set,
944b0c76 13104 struct drm_atomic_state *state)
50f56119 13105{
9a935856 13106 struct intel_connector *connector;
d5432a9d 13107 struct drm_connector *drm_connector;
944b0c76 13108 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13109 struct drm_crtc *crtc;
13110 struct drm_crtc_state *crtc_state;
13111 int i, ret;
50f56119 13112
9abdda74 13113 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13114 * of connectors. For paranoia, double-check this. */
13115 WARN_ON(!set->fb && (set->num_connectors != 0));
13116 WARN_ON(set->fb && (set->num_connectors == 0));
13117
3a3371ff 13118 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13119 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13120
d5432a9d
ACO		 13121 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13122 continue;
13123
13124 connector_state =
13125 drm_atomic_get_connector_state(state, &connector->base);
13126 if (IS_ERR(connector_state))
13127 return PTR_ERR(connector_state);
13128
b7885264
ACO		 13129 if (in_mode_set) {
13130 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13131 connector_state->best_encoder =
13132 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13133 }
13134
d5432a9d 13135 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13136 continue;
13137
9a935856
DV		 13138 /* If we disable the crtc, disable all its connectors. Also, if
13139 * the connector is on the changing crtc but not on the new
13140 * connector list, disable it. */
b7885264 13141 if (!set->fb || !in_mode_set) {
d5432a9d 13142 connector_state->best_encoder = NULL;
9a935856
DV		 13143
13144 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13145 connector->base.base.id,
c23cc417 13146 connector->base.name);
9a935856 13147 }
50f56119 13148 }
9a935856 13149 /* connector->new_encoder is now updated for all connectors. */
50f56119 13150
d5432a9d
ACO		 13151 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13152 connector = to_intel_connector(drm_connector);
13153
13154 if (!connector_state->best_encoder) {
13155 ret = drm_atomic_set_crtc_for_connector(connector_state,
13156 NULL);
13157 if (ret)
13158 return ret;
7668851f 13159
50f56119 13160 continue;
d5432a9d 13161 }
50f56119 13162
d5432a9d
ACO		 13163 if (intel_connector_in_mode_set(connector, set)) {
13164 struct drm_crtc *crtc = connector->base.state->crtc;
13165
13166 /* If this connector was in a previous crtc, add it
13167 * to the state. We might need to disable it. */
13168 if (crtc) {
13169 crtc_state =
13170 drm_atomic_get_crtc_state(state, crtc);
13171 if (IS_ERR(crtc_state))
13172 return PTR_ERR(crtc_state);
13173 }
13174
13175 ret = drm_atomic_set_crtc_for_connector(connector_state,
13176 set->crtc);
13177 if (ret)
13178 return ret;
13179 }
50f56119
DV		 13180
13181 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13182 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13183 connector_state->crtc)) {
5e2b584e 13184 return -EINVAL;
50f56119 13185 }
944b0c76 13186
9a935856
DV		 13187 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13188 connector->base.base.id,
c23cc417 13189 connector->base.name,
d5432a9d 13190 connector_state->crtc->base.id);
944b0c76 13191
d5432a9d
ACO		 13192 if (connector_state->best_encoder != &connector->encoder->base)
13193 connector->encoder =
13194 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13195 }
7668851f 13196
d5432a9d 13197 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13198 bool has_connectors;
13199
d5432a9d
ACO		 13200 ret = drm_atomic_add_affected_connectors(state, crtc);
13201 if (ret)
13202 return ret;
4be07317 13203
49d6fa21
ML		 13204 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13205 if (has_connectors != crtc_state->enable)
13206 crtc_state->enable =
13207 crtc_state->active = has_connectors;
7668851f
VS		 13208 }
13209
8c7b5ccb
ACO		 13210 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13211 set->fb, set->x, set->y);
13212 if (ret)
13213 return ret;
13214
13215 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13216 if (IS_ERR(crtc_state))
13217 return PTR_ERR(crtc_state);
13218
13219 if (set->mode)
13220 drm_mode_copy(&crtc_state->mode, set->mode);
13221
13222 if (set->num_connectors)
13223 crtc_state->active = true;
13224
2e431051
DV		 13225 return 0;
13226}
13227
bb546623
ACO		 13228static bool primary_plane_visible(struct drm_crtc *crtc)
13229{
13230 struct intel_plane_state *plane_state =
13231 to_intel_plane_state(crtc->primary->state);
13232
13233 return plane_state->visible;
13234}
13235
2e431051
DV		 13236static int intel_crtc_set_config(struct drm_mode_set *set)
13237{
13238 struct drm_device *dev;
83a57153 13239 struct drm_atomic_state *state = NULL;
5cec258b 13240 struct intel_crtc_state *pipe_config;
bb546623 13241 bool primary_plane_was_visible;
2e431051 13242 int ret;
2e431051 13243
8d3e375e
DV		 13244 BUG_ON(!set);
13245 BUG_ON(!set->crtc);
13246 BUG_ON(!set->crtc->helper_private);
2e431051 13247
7e53f3a4
DV		 13248 /* Enforce sane interface api - has been abused by the fb helper. */
13249 BUG_ON(!set->mode && set->fb);
13250 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13251
2e431051
DV		 13252 if (set->fb) {
13253 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13254 set->crtc->base.id, set->fb->base.id,
13255 (int)set->num_connectors, set->x, set->y);
13256 } else {
13257 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13258 }
13259
13260 dev = set->crtc->dev;
13261
83a57153 13262 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13263 if (!state)
13264 return -ENOMEM;
83a57153
ACO		 13265
13266 state->acquire_ctx = dev->mode_config.acquire_ctx;
13267
462a425a 13268 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13269 if (ret)
7cbf41d6 13270 goto out;
2e431051 13271
8c7b5ccb 13272 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13273 if (IS_ERR(pipe_config)) {
6ac0483b 13274 ret = PTR_ERR(pipe_config);
7cbf41d6 13275 goto out;
20664591 13276 }
50f52756 13277
1f9954d0
JB		 13278 intel_update_pipe_size(to_intel_crtc(set->crtc));
13279
bb546623
ACO		 13280 primary_plane_was_visible = primary_plane_visible(set->crtc);
13281
8c7b5ccb 13282 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13283
13284 if (ret == 0 &&
13285 pipe_config->base.enable &&
13286 pipe_config->base.planes_changed &&
13287 !needs_modeset(&pipe_config->base)) {
3b150f08 13288 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13289
13290 /*
13291 * We need to make sure the primary plane is re-enabled if it
13292 * has previously been turned off.
13293 */
bb546623
ACO		 13294 if (ret == 0 && !primary_plane_was_visible &&
13295 primary_plane_visible(set->crtc)) {
3b150f08 13296 WARN_ON(!intel_crtc->active);
87d4300a 13297 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13298 }
13299
7ca51a3a
JB		 13300 /*
13301 * In the fastboot case this may be our only check of the
13302 * state after boot. It would be better to only do it on
13303 * the first update, but we don't have a nice way of doing that
13304 * (and really, set_config isn't used much for high freq page
13305 * flipping, so increasing its cost here shouldn't be a big
13306 * deal).
13307 */
d330a953 13308 if (i915.fastboot && ret == 0)
7ca51a3a 13309 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13310 }
13311
2d05eae1 13312 if (ret) {
bf67dfeb
DV		 13313 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13314 set->crtc->base.id, ret);
2d05eae1 13315 }
50f56119 13316
7cbf41d6 13317out:
2bfb4627
ACO		 13318 if (ret)
13319 drm_atomic_state_free(state);
50f56119
DV		 13320 return ret;
13321}
f6e5b160
CW		 13322
13323static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13324 .gamma_set = intel_crtc_gamma_set,
50f56119 13325 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13326 .destroy = intel_crtc_destroy,
13327 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13328 .atomic_duplicate_state = intel_crtc_duplicate_state,
13329 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13330};
13331
5358901f
DV		 13332static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13333 struct intel_shared_dpll *pll,
13334 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13335{
5358901f 13336 uint32_t val;
ee7b9f93 13337
f458ebbc 13338 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13339 return false;
13340
5358901f 13341 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13342 hw_state->dpll = val;
13343 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13344 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13345
13346 return val & DPLL_VCO_ENABLE;
13347}
13348
15bdd4cf
DV		 13349static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13350 struct intel_shared_dpll *pll)
13351{
3e369b76
ACO		 13352 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13353 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13354}
13355
e7b903d2
DV		 13356static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13357 struct intel_shared_dpll *pll)
13358{
e7b903d2 13359 /* PCH refclock must be enabled first */
89eff4be 13360 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13361
3e369b76 13362 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13363
13364 /* Wait for the clocks to stabilize. */
13365 POSTING_READ(PCH_DPLL(pll->id));
13366 udelay(150);
13367
13368 /* The pixel multiplier can only be updated once the
13369 * DPLL is enabled and the clocks are stable.
13370 *
13371 * So write it again.
13372 */
3e369b76 13373 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13374 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13375 udelay(200);
13376}
13377
13378static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13379 struct intel_shared_dpll *pll)
13380{
13381 struct drm_device *dev = dev_priv->dev;
13382 struct intel_crtc *crtc;
e7b903d2
DV		 13383
13384 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13385 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13386 if (intel_crtc_to_shared_dpll(crtc) == pll)
13387 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13388 }
13389
15bdd4cf
DV		 13390 I915_WRITE(PCH_DPLL(pll->id), 0);
13391 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13392 udelay(200);
13393}
13394
46edb027
DV		 13395static char *ibx_pch_dpll_names[] = {
13396 "PCH DPLL A",
13397 "PCH DPLL B",
13398};
13399
7c74ade1 13400static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13401{
e7b903d2 13402 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13403 int i;
13404
7c74ade1 13405 dev_priv->num_shared_dpll = 2;
ee7b9f93 13406
e72f9fbf 13407 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13408 dev_priv->shared_dplls[i].id = i;
13409 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13410 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13411 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13412 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13413 dev_priv->shared_dplls[i].get_hw_state =
13414 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13415 }
13416}
13417
7c74ade1
DV		 13418static void intel_shared_dpll_init(struct drm_device *dev)
13419{
e7b903d2 13420 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13421
b6283055
VS		 13422 intel_update_cdclk(dev);
13423
9cd86933
DV		 13424 if (HAS_DDI(dev))
13425 intel_ddi_pll_init(dev);
13426 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13427 ibx_pch_dpll_init(dev);
13428 else
13429 dev_priv->num_shared_dpll = 0;
13430
13431 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13432}
13433
1fc0a8f7
TU		 13434/**
13435 * intel_wm_need_update - Check whether watermarks need updating
13436 * @plane: drm plane
13437 * @state: new plane state
13438 *
13439 * Check current plane state versus the new one to determine whether
13440 * watermarks need to be recalculated.
13441 *
13442 * Returns true or false.
13443 */
13444bool intel_wm_need_update(struct drm_plane *plane,
13445 struct drm_plane_state *state)
13446{
13447 /* Update watermarks on tiling changes. */
13448 if (!plane->state->fb || !state->fb ||
13449 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13450 plane->state->rotation != state->rotation)
13451 return true;
13452
13453 return false;
13454}
13455
6beb8c23
MR		 13456/**
13457 * intel_prepare_plane_fb - Prepare fb for usage on plane
13458 * @plane: drm plane to prepare for
13459 * @fb: framebuffer to prepare for presentation
13460 *
13461 * Prepares a framebuffer for usage on a display plane. Generally this
13462 * involves pinning the underlying object and updating the frontbuffer tracking
13463 * bits. Some older platforms need special physical address handling for
13464 * cursor planes.
13465 *
13466 * Returns 0 on success, negative error code on failure.
13467 */
13468int
13469intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13470 struct drm_framebuffer *fb,
13471 const struct drm_plane_state *new_state)
465c120c
MR		 13472{
13473 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13474 struct intel_plane *intel_plane = to_intel_plane(plane);
13475 enum pipe pipe = intel_plane->pipe;
13476 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13477 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13478 unsigned frontbuffer_bits = 0;
13479 int ret = 0;
465c120c 13480
ea2c67bb 13481 if (!obj)
465c120c
MR		 13482 return 0;
13483
6beb8c23
MR		 13484 switch (plane->type) {
13485 case DRM_PLANE_TYPE_PRIMARY:
13486 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13487 break;
13488 case DRM_PLANE_TYPE_CURSOR:
13489 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13490 break;
13491 case DRM_PLANE_TYPE_OVERLAY:
13492 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13493 break;
13494 }
465c120c 13495
6beb8c23 13496 mutex_lock(&dev->struct_mutex);
465c120c 13497
6beb8c23
MR		 13498 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13499 INTEL_INFO(dev)->cursor_needs_physical) {
13500 int align = IS_I830(dev) ? 16 * 1024 : 256;
13501 ret = i915_gem_object_attach_phys(obj, align);
13502 if (ret)
13503 DRM_DEBUG_KMS("failed to attach phys object\n");
13504 } else {
82bc3b2d 13505 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13506 }
465c120c 13507
6beb8c23
MR		 13508 if (ret == 0)
13509 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13510
4c34574f 13511 mutex_unlock(&dev->struct_mutex);
465c120c 13512
6beb8c23
MR		 13513 return ret;
13514}
13515
38f3ce3a
MR		 13516/**
13517 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13518 * @plane: drm plane to clean up for
13519 * @fb: old framebuffer that was on plane
13520 *
13521 * Cleans up a framebuffer that has just been removed from a plane.
13522 */
13523void
13524intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13525 struct drm_framebuffer *fb,
13526 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13527{
13528 struct drm_device *dev = plane->dev;
13529 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13530
13531 if (WARN_ON(!obj))
13532 return;
13533
13534 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13535 !INTEL_INFO(dev)->cursor_needs_physical) {
13536 mutex_lock(&dev->struct_mutex);
82bc3b2d 13537 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13538 mutex_unlock(&dev->struct_mutex);
13539 }
465c120c
MR		 13540}
13541
6156a456
CK		 13542int
13543skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13544{
13545 int max_scale;
13546 struct drm_device *dev;
13547 struct drm_i915_private *dev_priv;
13548 int crtc_clock, cdclk;
13549
13550 if (!intel_crtc || !crtc_state)
13551 return DRM_PLANE_HELPER_NO_SCALING;
13552
13553 dev = intel_crtc->base.dev;
13554 dev_priv = dev->dev_private;
13555 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13556 cdclk = dev_priv->display.get_display_clock_speed(dev);
13557
13558 if (!crtc_clock || !cdclk)
13559 return DRM_PLANE_HELPER_NO_SCALING;
13560
13561 /*
13562 * skl max scale is lower of:
13563 * close to 3 but not 3, -1 is for that purpose
13564 * or
13565 * cdclk/crtc_clock
13566 */
13567 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13568
13569 return max_scale;
13570}
13571
465c120c 13572static int
3c692a41
GP		 13573intel_check_primary_plane(struct drm_plane *plane,
13574 struct intel_plane_state *state)
13575{
32b7eeec
MR		 13576 struct drm_device *dev = plane->dev;
13577 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13578 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13579 struct intel_crtc *intel_crtc;
6156a456 13580 struct intel_crtc_state *crtc_state;
2b875c22 13581 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13582 struct drm_rect *dest = &state->dst;
13583 struct drm_rect *src = &state->src;
13584 const struct drm_rect *clip = &state->clip;
d8106366 13585 bool can_position = false;
6156a456
CK		 13586 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13587 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13588 int ret;
13589
ea2c67bb
MR		 13590 crtc = crtc ? crtc : plane->crtc;
13591 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13592 crtc_state = state->base.state ?
13593 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13594
6156a456 13595 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13596 /* use scaler when colorkey is not required */
13597 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13598 min_scale = 1;
13599 max_scale = skl_max_scale(intel_crtc, crtc_state);
13600 }
d8106366 13601 can_position = true;
6156a456 13602 }
d8106366 13603
c59cb179
MR		 13604 ret = drm_plane_helper_check_update(plane, crtc, fb,
13605 src, dest, clip,
6156a456
CK		 13606 min_scale,
13607 max_scale,
d8106366
SJ		 13608 can_position, true,
13609 &state->visible);
c59cb179
MR		 13610 if (ret)
13611 return ret;
465c120c 13612
32b7eeec 13613 if (intel_crtc->active) {
b70709a6
ML		 13614 struct intel_plane_state *old_state =
13615 to_intel_plane_state(plane->state);
13616
32b7eeec
MR		 13617 intel_crtc->atomic.wait_for_flips = true;
13618
13619 /*
13620 * FBC does not work on some platforms for rotated
13621 * planes, so disable it when rotation is not 0 and
13622 * update it when rotation is set back to 0.
13623 *
13624 * FIXME: This is redundant with the fbc update done in
13625 * the primary plane enable function except that that
13626 * one is done too late. We eventually need to unify
13627 * this.
13628 */
b70709a6 13629 if (state->visible &&
32b7eeec 13630 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13631 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13632 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13633 intel_crtc->atomic.disable_fbc = true;
13634 }
13635
b70709a6 13636 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13637 /*
13638 * BDW signals flip done immediately if the plane
13639 * is disabled, even if the plane enable is already
13640 * armed to occur at the next vblank :(
13641 */
b70709a6 13642 if (IS_BROADWELL(dev))
32b7eeec
MR		 13643 intel_crtc->atomic.wait_vblank = true;
13644 }
13645
13646 intel_crtc->atomic.fb_bits |=
13647 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13648
13649 intel_crtc->atomic.update_fbc = true;
0fda6568 13650
1fc0a8f7 13651 if (intel_wm_need_update(plane, &state->base))
0fda6568 13652 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13653 }
13654
6156a456
CK		 13655 if (INTEL_INFO(dev)->gen >= 9) {
13656 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13657 to_intel_plane(plane), state, 0);
13658 if (ret)
13659 return ret;
13660 }
13661
14af293f
GP		 13662 return 0;
13663}
13664
13665static void
13666intel_commit_primary_plane(struct drm_plane *plane,
13667 struct intel_plane_state *state)
13668{
2b875c22
MR		 13669 struct drm_crtc *crtc = state->base.crtc;
13670 struct drm_framebuffer *fb = state->base.fb;
13671 struct drm_device *dev = plane->dev;
14af293f 13672 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13673 struct intel_crtc *intel_crtc;
14af293f
GP		 13674 struct drm_rect *src = &state->src;
13675
ea2c67bb
MR		 13676 crtc = crtc ? crtc : plane->crtc;
13677 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13678
13679 plane->fb = fb;
9dc806fc
MR		 13680 crtc->x = src->x1 >> 16;
13681 crtc->y = src->y1 >> 16;
ccc759dc 13682
ccc759dc 13683 if (intel_crtc->active) {
27321ae8 13684 if (state->visible)
ccc759dc
GP		 13685 /* FIXME: kill this fastboot hack */
13686 intel_update_pipe_size(intel_crtc);
465c120c 13687
27321ae8
ML		 13688 dev_priv->display.update_primary_plane(crtc, plane->fb,
13689 crtc->x, crtc->y);
ccc759dc 13690 }
465c120c
MR		 13691}
13692
a8ad0d8e
ML		 13693static void
13694intel_disable_primary_plane(struct drm_plane *plane,
13695 struct drm_crtc *crtc,
13696 bool force)
13697{
13698 struct drm_device *dev = plane->dev;
13699 struct drm_i915_private *dev_priv = dev->dev_private;
13700
a8ad0d8e
ML		 13701 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13702}
13703
32b7eeec 13704static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13705{
32b7eeec 13706 struct drm_device *dev = crtc->dev;
140fd38d 13707 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13709 struct intel_plane *intel_plane;
13710 struct drm_plane *p;
13711 unsigned fb_bits = 0;
13712
13713 /* Track fb's for any planes being disabled */
13714 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13715 intel_plane = to_intel_plane(p);
13716
13717 if (intel_crtc->atomic.disabled_planes &
13718 (1 << drm_plane_index(p))) {
13719 switch (p->type) {
13720 case DRM_PLANE_TYPE_PRIMARY:
13721 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13722 break;
13723 case DRM_PLANE_TYPE_CURSOR:
13724 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13725 break;
13726 case DRM_PLANE_TYPE_OVERLAY:
13727 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13728 break;
13729 }
3c692a41 13730
ea2c67bb
MR		 13731 mutex_lock(&dev->struct_mutex);
13732 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13733 mutex_unlock(&dev->struct_mutex);
13734 }
13735 }
3c692a41 13736
32b7eeec
MR		 13737 if (intel_crtc->atomic.wait_for_flips)
13738 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13739
32b7eeec
MR		 13740 if (intel_crtc->atomic.disable_fbc)
13741 intel_fbc_disable(dev);
3c692a41 13742
32b7eeec
MR		 13743 if (intel_crtc->atomic.pre_disable_primary)
13744 intel_pre_disable_primary(crtc);
3c692a41 13745
32b7eeec
MR		 13746 if (intel_crtc->atomic.update_wm)
13747 intel_update_watermarks(crtc);
3c692a41 13748
32b7eeec 13749 intel_runtime_pm_get(dev_priv);
3c692a41 13750
c34c9ee4
MR		 13751 /* Perform vblank evasion around commit operation */
13752 if (intel_crtc->active)
13753 intel_crtc->atomic.evade =
13754 intel_pipe_update_start(intel_crtc,
13755 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13756}
13757
13758static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13759{
13760 struct drm_device *dev = crtc->dev;
13761 struct drm_i915_private *dev_priv = dev->dev_private;
13762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13763 struct drm_plane *p;
13764
c34c9ee4
MR		 13765 if (intel_crtc->atomic.evade)
13766 intel_pipe_update_end(intel_crtc,
13767 intel_crtc->atomic.start_vbl_count);
3c692a41 13768
140fd38d 13769 intel_runtime_pm_put(dev_priv);
3c692a41 13770
32b7eeec
MR		 13771 if (intel_crtc->atomic.wait_vblank)
13772 intel_wait_for_vblank(dev, intel_crtc->pipe);
13773
13774 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13775
13776 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13777 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13778 intel_fbc_update(dev);
ccc759dc 13779 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13780 }
3c692a41 13781
32b7eeec
MR		 13782 if (intel_crtc->atomic.post_enable_primary)
13783 intel_post_enable_primary(crtc);
3c692a41 13784
32b7eeec
MR		 13785 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13786 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13787 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13788 false, false);
13789
13790 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13791}
13792
cf4c7c12 13793/**
4a3b8769
MR		 13794 * intel_plane_destroy - destroy a plane
13795 * @plane: plane to destroy
cf4c7c12 13796 *
4a3b8769
MR		 13797 * Common destruction function for all types of planes (primary, cursor,
13798 * sprite).
cf4c7c12 13799 */
4a3b8769 13800void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13801{
13802 struct intel_plane *intel_plane = to_intel_plane(plane);
13803 drm_plane_cleanup(plane);
13804 kfree(intel_plane);
13805}
13806
65a3fea0 13807const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13808 .update_plane = drm_atomic_helper_update_plane,
13809 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13810 .destroy = intel_plane_destroy,
c196e1d6 13811 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13812 .atomic_get_property = intel_plane_atomic_get_property,
13813 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13814 .atomic_duplicate_state = intel_plane_duplicate_state,
13815 .atomic_destroy_state = intel_plane_destroy_state,
13816
465c120c
MR		 13817};
13818
13819static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13820 int pipe)
13821{
13822 struct intel_plane *primary;
8e7d688b 13823 struct intel_plane_state *state;
465c120c
MR		 13824 const uint32_t *intel_primary_formats;
13825 int num_formats;
13826
13827 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13828 if (primary == NULL)
13829 return NULL;
13830
8e7d688b
MR		 13831 state = intel_create_plane_state(&primary->base);
13832 if (!state) {
ea2c67bb
MR		 13833 kfree(primary);
13834 return NULL;
13835 }
8e7d688b 13836 primary->base.state = &state->base;
ea2c67bb 13837
465c120c
MR		 13838 primary->can_scale = false;
13839 primary->max_downscale = 1;
6156a456
CK		 13840 if (INTEL_INFO(dev)->gen >= 9) {
13841 primary->can_scale = true;
af99ceda 13842 state->scaler_id = -1;
6156a456 13843 }
465c120c
MR		 13844 primary->pipe = pipe;
13845 primary->plane = pipe;
c59cb179
MR		 13846 primary->check_plane = intel_check_primary_plane;
13847 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13848 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13849 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13850 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13851 primary->plane = !pipe;
13852
6c0fd451
DL		 13853 if (INTEL_INFO(dev)->gen >= 9) {
13854 intel_primary_formats = skl_primary_formats;
13855 num_formats = ARRAY_SIZE(skl_primary_formats);
13856 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13857 intel_primary_formats = i965_primary_formats;
13858 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13859 } else {
13860 intel_primary_formats = i8xx_primary_formats;
13861 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13862 }
13863
13864 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13865 &intel_plane_funcs,
465c120c
MR		 13866 intel_primary_formats, num_formats,
13867 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13868
3b7a5119
SJ		 13869 if (INTEL_INFO(dev)->gen >= 4)
13870 intel_create_rotation_property(dev, primary);
48404c1e 13871
ea2c67bb
MR		 13872 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13873
465c120c
MR		 13874 return &primary->base;
13875}
13876
3b7a5119
SJ		 13877void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13878{
13879 if (!dev->mode_config.rotation_property) {
13880 unsigned long flags = BIT(DRM_ROTATE_0) |
13881 BIT(DRM_ROTATE_180);
13882
13883 if (INTEL_INFO(dev)->gen >= 9)
13884 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13885
13886 dev->mode_config.rotation_property =
13887 drm_mode_create_rotation_property(dev, flags);
13888 }
13889 if (dev->mode_config.rotation_property)
13890 drm_object_attach_property(&plane->base.base,
13891 dev->mode_config.rotation_property,
13892 plane->base.state->rotation);
13893}
13894
3d7d6510 13895static int
852e787c
GP		 13896intel_check_cursor_plane(struct drm_plane *plane,
13897 struct intel_plane_state *state)
3d7d6510 13898{
2b875c22 13899 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13900 struct drm_device *dev = plane->dev;
2b875c22 13901 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13902 struct drm_rect *dest = &state->dst;
13903 struct drm_rect *src = &state->src;
13904 const struct drm_rect *clip = &state->clip;
757f9a3e 13905 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13906 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13907 unsigned stride;
13908 int ret;
3d7d6510 13909
ea2c67bb
MR		 13910 crtc = crtc ? crtc : plane->crtc;
13911 intel_crtc = to_intel_crtc(crtc);
13912
757f9a3e 13913 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13914 src, dest, clip,
3d7d6510
MR		 13915 DRM_PLANE_HELPER_NO_SCALING,
13916 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13917 true, true, &state->visible);
757f9a3e
GP		 13918 if (ret)
13919 return ret;
13920
13921
13922 /* if we want to turn off the cursor ignore width and height */
13923 if (!obj)
32b7eeec 13924 goto finish;
757f9a3e 13925
757f9a3e 13926 /* Check for which cursor types we support */
ea2c67bb
MR		 13927 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13928 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13929 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13930 return -EINVAL;
13931 }
13932
ea2c67bb
MR		 13933 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13934 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13935 DRM_DEBUG_KMS("buffer is too small\n");
13936 return -ENOMEM;
13937 }
13938
3a656b54 13939 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13940 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13941 ret = -EINVAL;
13942 }
757f9a3e 13943
32b7eeec
MR		 13944finish:
13945 if (intel_crtc->active) {
3749f463 13946 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13947 intel_crtc->atomic.update_wm = true;
13948
13949 intel_crtc->atomic.fb_bits |=
13950 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13951 }
13952
757f9a3e 13953 return ret;
852e787c 13954}
3d7d6510 13955
a8ad0d8e
ML		 13956static void
13957intel_disable_cursor_plane(struct drm_plane *plane,
13958 struct drm_crtc *crtc,
13959 bool force)
13960{
13961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13962
13963 if (!force) {
13964 plane->fb = NULL;
13965 intel_crtc->cursor_bo = NULL;
13966 intel_crtc->cursor_addr = 0;
13967 }
13968
13969 intel_crtc_update_cursor(crtc, false);
13970}
13971
f4a2cf29 13972static void
852e787c
GP		 13973intel_commit_cursor_plane(struct drm_plane *plane,
13974 struct intel_plane_state *state)
13975{
2b875c22 13976 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13977 struct drm_device *dev = plane->dev;
13978 struct intel_crtc *intel_crtc;
2b875c22 13979 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13980 uint32_t addr;
852e787c 13981
ea2c67bb
MR		 13982 crtc = crtc ? crtc : plane->crtc;
13983 intel_crtc = to_intel_crtc(crtc);
13984
2b875c22 13985 plane->fb = state->base.fb;
ea2c67bb
MR		 13986 crtc->cursor_x = state->base.crtc_x;
13987 crtc->cursor_y = state->base.crtc_y;
13988
a912f12f
GP		 13989 if (intel_crtc->cursor_bo == obj)
13990 goto update;
4ed91096 13991
f4a2cf29 13992 if (!obj)
a912f12f 13993 addr = 0;
f4a2cf29 13994 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13995 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13996 else
a912f12f 13997 addr = obj->phys_handle->busaddr;
852e787c 13998
a912f12f
GP		 13999 intel_crtc->cursor_addr = addr;
14000 intel_crtc->cursor_bo = obj;
14001update:
852e787c 14002
32b7eeec 14003 if (intel_crtc->active)
a912f12f 14004 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14005}
14006
3d7d6510
MR		 14007static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14008 int pipe)
14009{
14010 struct intel_plane *cursor;
8e7d688b 14011 struct intel_plane_state *state;
3d7d6510
MR		 14012
14013 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14014 if (cursor == NULL)
14015 return NULL;
14016
8e7d688b
MR		 14017 state = intel_create_plane_state(&cursor->base);
14018 if (!state) {
ea2c67bb
MR		 14019 kfree(cursor);
14020 return NULL;
14021 }
8e7d688b 14022 cursor->base.state = &state->base;
ea2c67bb 14023
3d7d6510
MR		 14024 cursor->can_scale = false;
14025 cursor->max_downscale = 1;
14026 cursor->pipe = pipe;
14027 cursor->plane = pipe;
c59cb179
MR		 14028 cursor->check_plane = intel_check_cursor_plane;
14029 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14030 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14031
14032 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14033 &intel_plane_funcs,
3d7d6510
MR		 14034 intel_cursor_formats,
14035 ARRAY_SIZE(intel_cursor_formats),
14036 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14037
14038 if (INTEL_INFO(dev)->gen >= 4) {
14039 if (!dev->mode_config.rotation_property)
14040 dev->mode_config.rotation_property =
14041 drm_mode_create_rotation_property(dev,
14042 BIT(DRM_ROTATE_0) |
14043 BIT(DRM_ROTATE_180));
14044 if (dev->mode_config.rotation_property)
14045 drm_object_attach_property(&cursor->base.base,
14046 dev->mode_config.rotation_property,
8e7d688b 14047 state->base.rotation);
4398ad45
VS		 14048 }
14049
af99ceda
CK		 14050 if (INTEL_INFO(dev)->gen >=9)
14051 state->scaler_id = -1;
14052
ea2c67bb
MR		 14053 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14054
3d7d6510
MR		 14055 return &cursor->base;
14056}
14057
549e2bfb
CK		 14058static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14059 struct intel_crtc_state *crtc_state)
14060{
14061 int i;
14062 struct intel_scaler *intel_scaler;
14063 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14064
14065 for (i = 0; i < intel_crtc->num_scalers; i++) {
14066 intel_scaler = &scaler_state->scalers[i];
14067 intel_scaler->in_use = 0;
14068 intel_scaler->id = i;
14069
14070 intel_scaler->mode = PS_SCALER_MODE_DYN;
14071 }
14072
14073 scaler_state->scaler_id = -1;
14074}
14075
b358d0a6 14076static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14077{
fbee40df 14078 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14079 struct intel_crtc *intel_crtc;
f5de6e07 14080 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14081 struct drm_plane *primary = NULL;
14082 struct drm_plane *cursor = NULL;
465c120c 14083 int i, ret;
79e53945 14084
955382f3 14085 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14086 if (intel_crtc == NULL)
14087 return;
14088
f5de6e07
ACO		 14089 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14090 if (!crtc_state)
14091 goto fail;
550acefd
ACO		 14092 intel_crtc->config = crtc_state;
14093 intel_crtc->base.state = &crtc_state->base;
07878248 14094 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14095
549e2bfb
CK		 14096 /* initialize shared scalers */
14097 if (INTEL_INFO(dev)->gen >= 9) {
14098 if (pipe == PIPE_C)
14099 intel_crtc->num_scalers = 1;
14100 else
14101 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14102
14103 skl_init_scalers(dev, intel_crtc, crtc_state);
14104 }
14105
465c120c 14106 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14107 if (!primary)
14108 goto fail;
14109
14110 cursor = intel_cursor_plane_create(dev, pipe);
14111 if (!cursor)
14112 goto fail;
14113
465c120c 14114 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14115 cursor, &intel_crtc_funcs);
14116 if (ret)
14117 goto fail;
79e53945
JB		 14118
14119 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14120 for (i = 0; i < 256; i++) {
14121 intel_crtc->lut_r[i] = i;
14122 intel_crtc->lut_g[i] = i;
14123 intel_crtc->lut_b[i] = i;
14124 }
14125
1f1c2e24
VS		 14126 /*
14127 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14128 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14129 */
80824003
JB		 14130 intel_crtc->pipe = pipe;
14131 intel_crtc->plane = pipe;
3a77c4c4 14132 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14133 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14134 intel_crtc->plane = !pipe;
80824003
JB		 14135 }
14136
4b0e333e
CW		 14137 intel_crtc->cursor_base = ~0;
14138 intel_crtc->cursor_cntl = ~0;
dc41c154 14139 intel_crtc->cursor_size = ~0;
8d7849db 14140
22fd0fab
JB		 14141 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14142 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14143 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14144 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14145
79e53945 14146 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14147
14148 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14149 return;
14150
14151fail:
14152 if (primary)
14153 drm_plane_cleanup(primary);
14154 if (cursor)
14155 drm_plane_cleanup(cursor);
f5de6e07 14156 kfree(crtc_state);
3d7d6510 14157 kfree(intel_crtc);
79e53945
JB		 14158}
14159
752aa88a
JB		 14160enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14161{
14162 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14163 struct drm_device *dev = connector->base.dev;
752aa88a 14164
51fd371b 14165 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14166
d3babd3f 14167 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14168 return INVALID_PIPE;
14169
14170 return to_intel_crtc(encoder->crtc)->pipe;
14171}
14172
08d7b3d1 14173int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14174 struct drm_file *file)
08d7b3d1 14175{
08d7b3d1 14176 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14177 struct drm_crtc *drmmode_crtc;
c05422d5 14178 struct intel_crtc *crtc;
08d7b3d1 14179
7707e653 14180 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14181
7707e653 14182 if (!drmmode_crtc) {
08d7b3d1 14183 DRM_ERROR("no such CRTC id\n");
3f2c2057 14184 return -ENOENT;
08d7b3d1
CW		 14185 }
14186
7707e653 14187 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14188 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14189
c05422d5 14190 return 0;
08d7b3d1
CW		 14191}
14192
66a9278e 14193static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14194{
66a9278e
DV		 14195 struct drm_device *dev = encoder->base.dev;
14196 struct intel_encoder *source_encoder;
79e53945 14197 int index_mask = 0;
79e53945
JB		 14198 int entry = 0;
14199
b2784e15 14200 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14201 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14202 index_mask |= (1 << entry);
14203
79e53945
JB		 14204 entry++;
14205 }
4ef69c7a 14206
79e53945
JB		 14207 return index_mask;
14208}
14209
4d302442
CW		 14210static bool has_edp_a(struct drm_device *dev)
14211{
14212 struct drm_i915_private *dev_priv = dev->dev_private;
14213
14214 if (!IS_MOBILE(dev))
14215 return false;
14216
14217 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14218 return false;
14219
e3589908 14220 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14221 return false;
14222
14223 return true;
14224}
14225
84b4e042
JB		 14226static bool intel_crt_present(struct drm_device *dev)
14227{
14228 struct drm_i915_private *dev_priv = dev->dev_private;
14229
884497ed
DL		 14230 if (INTEL_INFO(dev)->gen >= 9)
14231 return false;
14232
cf404ce4 14233 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14234 return false;
14235
14236 if (IS_CHERRYVIEW(dev))
14237 return false;
14238
14239 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14240 return false;
14241
14242 return true;
14243}
14244
79e53945
JB		 14245static void intel_setup_outputs(struct drm_device *dev)
14246{
725e30ad 14247 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14248 struct intel_encoder *encoder;
cb0953d7 14249 bool dpd_is_edp = false;
79e53945 14250
c9093354 14251 intel_lvds_init(dev);
79e53945 14252
84b4e042 14253 if (intel_crt_present(dev))
79935fca 14254 intel_crt_init(dev);
cb0953d7 14255
c776eb2e
VK		 14256 if (IS_BROXTON(dev)) {
14257 /*
14258 * FIXME: Broxton doesn't support port detection via the
14259 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14260 * detect the ports.
14261 */
14262 intel_ddi_init(dev, PORT_A);
14263 intel_ddi_init(dev, PORT_B);
14264 intel_ddi_init(dev, PORT_C);
14265 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14266 int found;
14267
de31facd
JB		 14268 /*
14269 * Haswell uses DDI functions to detect digital outputs.
14270 * On SKL pre-D0 the strap isn't connected, so we assume
14271 * it's there.
14272 */
0e72a5b5 14273 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14274 /* WaIgnoreDDIAStrap: skl */
14275 if (found ||
14276 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14277 intel_ddi_init(dev, PORT_A);
14278
14279 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14280 * register */
14281 found = I915_READ(SFUSE_STRAP);
14282
14283 if (found & SFUSE_STRAP_DDIB_DETECTED)
14284 intel_ddi_init(dev, PORT_B);
14285 if (found & SFUSE_STRAP_DDIC_DETECTED)
14286 intel_ddi_init(dev, PORT_C);
14287 if (found & SFUSE_STRAP_DDID_DETECTED)
14288 intel_ddi_init(dev, PORT_D);
14289 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14290 int found;
5d8a7752 14291 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14292
14293 if (has_edp_a(dev))
14294 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14295
dc0fa718 14296 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14297 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14298 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14299 if (!found)
e2debe91 14300 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14301 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14302 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14303 }
14304
dc0fa718 14305 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14306 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14307
dc0fa718 14308 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14309 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14310
5eb08b69 14311 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14312 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14313
270b3042 14314 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14315 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14316 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14317 /*
14318 * The DP_DETECTED bit is the latched state of the DDC
14319 * SDA pin at boot. However since eDP doesn't require DDC
14320 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14321 * eDP ports may have been muxed to an alternate function.
14322 * Thus we can't rely on the DP_DETECTED bit alone to detect
14323 * eDP ports. Consult the VBT as well as DP_DETECTED to
14324 * detect eDP ports.
14325 */
d2182a66
VS		 14326 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14327 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14328 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14329 PORT_B);
e17ac6db
VS		 14330 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14331 intel_dp_is_edp(dev, PORT_B))
14332 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14333
d2182a66
VS		 14334 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14335 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14336 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14337 PORT_C);
e17ac6db
VS		 14338 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14339 intel_dp_is_edp(dev, PORT_C))
14340 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14341
9418c1f1 14342 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14343 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14344 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14345 PORT_D);
e17ac6db
VS		 14346 /* eDP not supported on port D, so don't check VBT */
14347 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14348 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14349 }
14350
3cfca973 14351 intel_dsi_init(dev);
103a196f 14352 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14353 bool found = false;
7d57382e 14354
e2debe91 14355 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14356 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14357 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14358 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14359 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14360 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14361 }
27185ae1 14362
e7281eab 14363 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14364 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14365 }
13520b05
KH		 14366
14367 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14368
e2debe91 14369 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14370 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14371 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14372 }
27185ae1 14373
e2debe91 14374 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14375
b01f2c3a
JB		 14376 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14377 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14378 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14379 }
e7281eab 14380 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14381 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14382 }
27185ae1 14383
b01f2c3a 14384 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14385 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14386 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14387 } else if (IS_GEN2(dev))
79e53945
JB		 14388 intel_dvo_init(dev);
14389
103a196f 14390 if (SUPPORTS_TV(dev))
79e53945
JB		 14391 intel_tv_init(dev);
14392
0bc12bcb 14393 intel_psr_init(dev);
7c8f8a70 14394
b2784e15 14395 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14396 encoder->base.possible_crtcs = encoder->crtc_mask;
14397 encoder->base.possible_clones =
66a9278e 14398 intel_encoder_clones(encoder);
79e53945 14399 }
47356eb6 14400
dde86e2d 14401 intel_init_pch_refclk(dev);
270b3042
DV		 14402
14403 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14404}
14405
14406static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14407{
60a5ca01 14408 struct drm_device *dev = fb->dev;
79e53945 14409 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14410
ef2d633e 14411 drm_framebuffer_cleanup(fb);
60a5ca01 14412 mutex_lock(&dev->struct_mutex);
ef2d633e 14413 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14414 drm_gem_object_unreference(&intel_fb->obj->base);
14415 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14416 kfree(intel_fb);
14417}
14418
14419static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14420 struct drm_file *file,
79e53945
JB		 14421 unsigned int *handle)
14422{
14423 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14424 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14425
05394f39 14426 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14427}
14428
14429static const struct drm_framebuffer_funcs intel_fb_funcs = {
14430 .destroy = intel_user_framebuffer_destroy,
14431 .create_handle = intel_user_framebuffer_create_handle,
14432};
14433
b321803d
DL		 14434static
14435u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14436 uint32_t pixel_format)
14437{
14438 u32 gen = INTEL_INFO(dev)->gen;
14439
14440 if (gen >= 9) {
14441 /* "The stride in bytes must not exceed the of the size of 8K
14442 * pixels and 32K bytes."
14443 */
14444 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14445 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14446 return 32*1024;
14447 } else if (gen >= 4) {
14448 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14449 return 16*1024;
14450 else
14451 return 32*1024;
14452 } else if (gen >= 3) {
14453 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14454 return 8*1024;
14455 else
14456 return 16*1024;
14457 } else {
14458 /* XXX DSPC is limited to 4k tiled */
14459 return 8*1024;
14460 }
14461}
14462
b5ea642a
DV		 14463static int intel_framebuffer_init(struct drm_device *dev,
14464 struct intel_framebuffer *intel_fb,
14465 struct drm_mode_fb_cmd2 *mode_cmd,
14466 struct drm_i915_gem_object *obj)
79e53945 14467{
6761dd31 14468 unsigned int aligned_height;
79e53945 14469 int ret;
b321803d 14470 u32 pitch_limit, stride_alignment;
79e53945 14471
dd4916c5
DV		 14472 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14473
2a80eada
DV		 14474 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14475 /* Enforce that fb modifier and tiling mode match, but only for
14476 * X-tiled. This is needed for FBC. */
14477 if (!!(obj->tiling_mode == I915_TILING_X) !=
14478 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14479 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14480 return -EINVAL;
14481 }
14482 } else {
14483 if (obj->tiling_mode == I915_TILING_X)
14484 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14485 else if (obj->tiling_mode == I915_TILING_Y) {
14486 DRM_DEBUG("No Y tiling for legacy addfb\n");
14487 return -EINVAL;
14488 }
14489 }
14490
9a8f0a12
TU		 14491 /* Passed in modifier sanity checking. */
14492 switch (mode_cmd->modifier[0]) {
14493 case I915_FORMAT_MOD_Y_TILED:
14494 case I915_FORMAT_MOD_Yf_TILED:
14495 if (INTEL_INFO(dev)->gen < 9) {
14496 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14497 mode_cmd->modifier[0]);
14498 return -EINVAL;
14499 }
14500 case DRM_FORMAT_MOD_NONE:
14501 case I915_FORMAT_MOD_X_TILED:
14502 break;
14503 default:
c0f40428
JB		 14504 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14505 mode_cmd->modifier[0]);
57cd6508 14506 return -EINVAL;
c16ed4be 14507 }
57cd6508 14508
b321803d
DL		 14509 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14510 mode_cmd->pixel_format);
14511 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14512 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14513 mode_cmd->pitches[0], stride_alignment);
57cd6508 14514 return -EINVAL;
c16ed4be 14515 }
57cd6508 14516
b321803d
DL		 14517 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14518 mode_cmd->pixel_format);
a35cdaa0 14519 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14520 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14521 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14522 "tiled" : "linear",
a35cdaa0 14523 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14524 return -EINVAL;
c16ed4be 14525 }
5d7bd705 14526
2a80eada 14527 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14528 mode_cmd->pitches[0] != obj->stride) {
14529 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14530 mode_cmd->pitches[0], obj->stride);
5d7bd705 14531 return -EINVAL;
c16ed4be 14532 }
5d7bd705 14533
57779d06 14534 /* Reject formats not supported by any plane early. */
308e5bcb 14535 switch (mode_cmd->pixel_format) {
57779d06 14536 case DRM_FORMAT_C8:
04b3924d
VS		 14537 case DRM_FORMAT_RGB565:
14538 case DRM_FORMAT_XRGB8888:
14539 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14540 break;
14541 case DRM_FORMAT_XRGB1555:
c16ed4be 14542 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14543 DRM_DEBUG("unsupported pixel format: %s\n",
14544 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14545 return -EINVAL;
c16ed4be 14546 }
57779d06 14547 break;
57779d06 14548 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14549 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14550 DRM_DEBUG("unsupported pixel format: %s\n",
14551 drm_get_format_name(mode_cmd->pixel_format));
14552 return -EINVAL;
14553 }
14554 break;
14555 case DRM_FORMAT_XBGR8888:
04b3924d 14556 case DRM_FORMAT_XRGB2101010:
57779d06 14557 case DRM_FORMAT_XBGR2101010:
c16ed4be 14558 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14559 DRM_DEBUG("unsupported pixel format: %s\n",
14560 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14561 return -EINVAL;
c16ed4be 14562 }
b5626747 14563 break;
7531208b
DL		 14564 case DRM_FORMAT_ABGR2101010:
14565 if (!IS_VALLEYVIEW(dev)) {
14566 DRM_DEBUG("unsupported pixel format: %s\n",
14567 drm_get_format_name(mode_cmd->pixel_format));
14568 return -EINVAL;
14569 }
14570 break;
04b3924d
VS		 14571 case DRM_FORMAT_YUYV:
14572 case DRM_FORMAT_UYVY:
14573 case DRM_FORMAT_YVYU:
14574 case DRM_FORMAT_VYUY:
c16ed4be 14575 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14576 DRM_DEBUG("unsupported pixel format: %s\n",
14577 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14578 return -EINVAL;
c16ed4be 14579 }
57cd6508
CW		 14580 break;
14581 default:
4ee62c76
VS		 14582 DRM_DEBUG("unsupported pixel format: %s\n",
14583 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14584 return -EINVAL;
14585 }
14586
90f9a336
VS		 14587 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14588 if (mode_cmd->offsets[0] != 0)
14589 return -EINVAL;
14590
ec2c981e 14591 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14592 mode_cmd->pixel_format,
14593 mode_cmd->modifier[0]);
53155c0a
DV		 14594 /* FIXME drm helper for size checks (especially planar formats)? */
14595 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14596 return -EINVAL;
14597
c7d73f6a
DV		 14598 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14599 intel_fb->obj = obj;
80075d49 14600 intel_fb->obj->framebuffer_references++;
c7d73f6a 14601
79e53945
JB		 14602 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14603 if (ret) {
14604 DRM_ERROR("framebuffer init failed %d\n", ret);
14605 return ret;
14606 }
14607
79e53945
JB		 14608 return 0;
14609}
14610
79e53945
JB		 14611static struct drm_framebuffer *
14612intel_user_framebuffer_create(struct drm_device *dev,
14613 struct drm_file *filp,
308e5bcb 14614 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14615{
05394f39 14616 struct drm_i915_gem_object *obj;
79e53945 14617
308e5bcb
JB		 14618 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14619 mode_cmd->handles[0]));
c8725226 14620 if (&obj->base == NULL)
cce13ff7 14621 return ERR_PTR(-ENOENT);
79e53945 14622
d2dff872 14623 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14624}
14625
4520f53a 14626#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14627static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14628{
14629}
14630#endif
14631
79e53945 14632static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14633 .fb_create = intel_user_framebuffer_create,
0632fef6 14634 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14635 .atomic_check = intel_atomic_check,
14636 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14637};
14638
e70236a8
JB		 14639/* Set up chip specific display functions */
14640static void intel_init_display(struct drm_device *dev)
14641{
14642 struct drm_i915_private *dev_priv = dev->dev_private;
14643
ee9300bb
DV		 14644 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14645 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14646 else if (IS_CHERRYVIEW(dev))
14647 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14648 else if (IS_VALLEYVIEW(dev))
14649 dev_priv->display.find_dpll = vlv_find_best_dpll;
14650 else if (IS_PINEVIEW(dev))
14651 dev_priv->display.find_dpll = pnv_find_best_dpll;
14652 else
14653 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14654
bc8d7dff
DL		 14655 if (INTEL_INFO(dev)->gen >= 9) {
14656 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14657 dev_priv->display.get_initial_plane_config =
14658 skylake_get_initial_plane_config;
bc8d7dff
DL		 14659 dev_priv->display.crtc_compute_clock =
14660 haswell_crtc_compute_clock;
14661 dev_priv->display.crtc_enable = haswell_crtc_enable;
14662 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14663 dev_priv->display.update_primary_plane =
14664 skylake_update_primary_plane;
14665 } else if (HAS_DDI(dev)) {
0e8ffe1b 14666 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14667 dev_priv->display.get_initial_plane_config =
14668 ironlake_get_initial_plane_config;
797d0259
ACO		 14669 dev_priv->display.crtc_compute_clock =
14670 haswell_crtc_compute_clock;
4f771f10
PZ		 14671 dev_priv->display.crtc_enable = haswell_crtc_enable;
14672 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14673 dev_priv->display.update_primary_plane =
14674 ironlake_update_primary_plane;
09b4ddf9 14675 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14676 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14677 dev_priv->display.get_initial_plane_config =
14678 ironlake_get_initial_plane_config;
3fb37703
ACO		 14679 dev_priv->display.crtc_compute_clock =
14680 ironlake_crtc_compute_clock;
76e5a89c
DV		 14681 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14682 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14683 dev_priv->display.update_primary_plane =
14684 ironlake_update_primary_plane;
89b667f8
JB		 14685 } else if (IS_VALLEYVIEW(dev)) {
14686 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14687 dev_priv->display.get_initial_plane_config =
14688 i9xx_get_initial_plane_config;
d6dfee7a 14689 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14690 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14691 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14692 dev_priv->display.update_primary_plane =
14693 i9xx_update_primary_plane;
f564048e 14694 } else {
0e8ffe1b 14695 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14696 dev_priv->display.get_initial_plane_config =
14697 i9xx_get_initial_plane_config;
d6dfee7a 14698 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14699 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14700 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14701 dev_priv->display.update_primary_plane =
14702 i9xx_update_primary_plane;
f564048e 14703 }
e70236a8 14704
e70236a8 14705 /* Returns the core display clock speed */
1652d19e
VS		 14706 if (IS_SKYLAKE(dev))
14707 dev_priv->display.get_display_clock_speed =
14708 skylake_get_display_clock_speed;
14709 else if (IS_BROADWELL(dev))
14710 dev_priv->display.get_display_clock_speed =
14711 broadwell_get_display_clock_speed;
14712 else if (IS_HASWELL(dev))
14713 dev_priv->display.get_display_clock_speed =
14714 haswell_get_display_clock_speed;
14715 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14716 dev_priv->display.get_display_clock_speed =
14717 valleyview_get_display_clock_speed;
b37a6434
VS		 14718 else if (IS_GEN5(dev))
14719 dev_priv->display.get_display_clock_speed =
14720 ilk_get_display_clock_speed;
a7c66cd8 14721 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14722 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14723 dev_priv->display.get_display_clock_speed =
14724 i945_get_display_clock_speed;
34edce2f
VS		 14725 else if (IS_GM45(dev))
14726 dev_priv->display.get_display_clock_speed =
14727 gm45_get_display_clock_speed;
14728 else if (IS_CRESTLINE(dev))
14729 dev_priv->display.get_display_clock_speed =
14730 i965gm_get_display_clock_speed;
14731 else if (IS_PINEVIEW(dev))
14732 dev_priv->display.get_display_clock_speed =
14733 pnv_get_display_clock_speed;
14734 else if (IS_G33(dev) || IS_G4X(dev))
14735 dev_priv->display.get_display_clock_speed =
14736 g33_get_display_clock_speed;
e70236a8
JB		 14737 else if (IS_I915G(dev))
14738 dev_priv->display.get_display_clock_speed =
14739 i915_get_display_clock_speed;
257a7ffc 14740 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14741 dev_priv->display.get_display_clock_speed =
14742 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14743 else if (IS_PINEVIEW(dev))
14744 dev_priv->display.get_display_clock_speed =
14745 pnv_get_display_clock_speed;
e70236a8
JB		 14746 else if (IS_I915GM(dev))
14747 dev_priv->display.get_display_clock_speed =
14748 i915gm_get_display_clock_speed;
14749 else if (IS_I865G(dev))
14750 dev_priv->display.get_display_clock_speed =
14751 i865_get_display_clock_speed;
f0f8a9ce 14752 else if (IS_I85X(dev))
e70236a8 14753 dev_priv->display.get_display_clock_speed =
1b1d2716 14754 i85x_get_display_clock_speed;
623e01e5
VS		 14755 else { /* 830 */
14756 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14757 dev_priv->display.get_display_clock_speed =
14758 i830_get_display_clock_speed;
623e01e5 14759 }
e70236a8 14760
7c10a2b5 14761 if (IS_GEN5(dev)) {
3bb11b53 14762 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14763 } else if (IS_GEN6(dev)) {
14764 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14765 } else if (IS_IVYBRIDGE(dev)) {
14766 /* FIXME: detect B0+ stepping and use auto training */
14767 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14768 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14769 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14770 if (IS_BROADWELL(dev))
14771 dev_priv->display.modeset_global_resources =
14772 broadwell_modeset_global_resources;
30a970c6
JB		 14773 } else if (IS_VALLEYVIEW(dev)) {
14774 dev_priv->display.modeset_global_resources =
14775 valleyview_modeset_global_resources;
f8437dd1
VK		 14776 } else if (IS_BROXTON(dev)) {
14777 dev_priv->display.modeset_global_resources =
14778 broxton_modeset_global_resources;
e70236a8 14779 }
8c9f3aaf 14780
8c9f3aaf
JB		 14781 switch (INTEL_INFO(dev)->gen) {
14782 case 2:
14783 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14784 break;
14785
14786 case 3:
14787 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14788 break;
14789
14790 case 4:
14791 case 5:
14792 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14793 break;
14794
14795 case 6:
14796 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14797 break;
7c9017e5 14798 case 7:
4e0bbc31 14799 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14800 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14801 break;
830c81db 14802 case 9:
ba343e02
TU		 14803 /* Drop through - unsupported since execlist only. */
14804 default:
14805 /* Default just returns -ENODEV to indicate unsupported */
14806 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14807 }
7bd688cd
JN		 14808
14809 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14810
14811 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14812}
14813
b690e96c
JB		 14814/*
14815 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14816 * resume, or other times. This quirk makes sure that's the case for
14817 * affected systems.
14818 */
0206e353 14819static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14820{
14821 struct drm_i915_private *dev_priv = dev->dev_private;
14822
14823 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14824 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14825}
14826
b6b5d049
VS		 14827static void quirk_pipeb_force(struct drm_device *dev)
14828{
14829 struct drm_i915_private *dev_priv = dev->dev_private;
14830
14831 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14832 DRM_INFO("applying pipe b force quirk\n");
14833}
14834
435793df
KP		 14835/*
14836 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14837 */
14838static void quirk_ssc_force_disable(struct drm_device *dev)
14839{
14840 struct drm_i915_private *dev_priv = dev->dev_private;
14841 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14842 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14843}
14844
4dca20ef 14845/*
5a15ab5b
CE		 14846 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14847 * brightness value
4dca20ef
CE		 14848 */
14849static void quirk_invert_brightness(struct drm_device *dev)
14850{
14851 struct drm_i915_private *dev_priv = dev->dev_private;
14852 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14853 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14854}
14855
9c72cc6f
SD		 14856/* Some VBT's incorrectly indicate no backlight is present */
14857static void quirk_backlight_present(struct drm_device *dev)
14858{
14859 struct drm_i915_private *dev_priv = dev->dev_private;
14860 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14861 DRM_INFO("applying backlight present quirk\n");
14862}
14863
b690e96c
JB		 14864struct intel_quirk {
14865 int device;
14866 int subsystem_vendor;
14867 int subsystem_device;
14868 void (*hook)(struct drm_device *dev);
14869};
14870
5f85f176
EE		 14871/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14872struct intel_dmi_quirk {
14873 void (*hook)(struct drm_device *dev);
14874 const struct dmi_system_id (*dmi_id_list)[];
14875};
14876
14877static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14878{
14879 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14880 return 1;
14881}
14882
14883static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14884 {
14885 .dmi_id_list = &(const struct dmi_system_id[]) {
14886 {
14887 .callback = intel_dmi_reverse_brightness,
14888 .ident = "NCR Corporation",
14889 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14890 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14891 },
14892 },
14893 { } /* terminating entry */
14894 },
14895 .hook = quirk_invert_brightness,
14896 },
14897};
14898
c43b5634 14899static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14900 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14901 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14902
b690e96c
JB		 14903 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14904 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14905
5f080c0f
VS		 14906 /* 830 needs to leave pipe A & dpll A up */
14907 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14908
b6b5d049
VS		 14909 /* 830 needs to leave pipe B & dpll B up */
14910 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14911
435793df
KP		 14912 /* Lenovo U160 cannot use SSC on LVDS */
14913 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14914
14915 /* Sony Vaio Y cannot use SSC on LVDS */
14916 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14917
be505f64
AH		 14918 /* Acer Aspire 5734Z must invert backlight brightness */
14919 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14920
14921 /* Acer/eMachines G725 */
14922 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14923
14924 /* Acer/eMachines e725 */
14925 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14926
14927 /* Acer/Packard Bell NCL20 */
14928 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14929
14930 /* Acer Aspire 4736Z */
14931 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14932
14933 /* Acer Aspire 5336 */
14934 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14935
14936 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14937 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14938
dfb3d47b
SD		 14939 /* Acer C720 Chromebook (Core i3 4005U) */
14940 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14941
b2a9601c 14942 /* Apple Macbook 2,1 (Core 2 T7400) */
14943 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14944
d4967d8c
SD		 14945 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14946 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14947
14948 /* HP Chromebook 14 (Celeron 2955U) */
14949 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14950
14951 /* Dell Chromebook 11 */
14952 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14953};
14954
14955static void intel_init_quirks(struct drm_device *dev)
14956{
14957 struct pci_dev *d = dev->pdev;
14958 int i;
14959
14960 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14961 struct intel_quirk *q = &intel_quirks[i];
14962
14963 if (d->device == q->device &&
14964 (d->subsystem_vendor == q->subsystem_vendor ||
14965 q->subsystem_vendor == PCI_ANY_ID) &&
14966 (d->subsystem_device == q->subsystem_device ||
14967 q->subsystem_device == PCI_ANY_ID))
14968 q->hook(dev);
14969 }
5f85f176
EE		 14970 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14971 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14972 intel_dmi_quirks[i].hook(dev);
14973 }
b690e96c
JB		 14974}
14975
9cce37f4
JB		 14976/* Disable the VGA plane that we never use */
14977static void i915_disable_vga(struct drm_device *dev)
14978{
14979 struct drm_i915_private *dev_priv = dev->dev_private;
14980 u8 sr1;
766aa1c4 14981 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14982
2b37c616 14983 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14984 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14985 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14986 sr1 = inb(VGA_SR_DATA);
14987 outb(sr1 | 1<<5, VGA_SR_DATA);
14988 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14989 udelay(300);
14990
01f5a626 14991 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14992 POSTING_READ(vga_reg);
14993}
14994
f817586c
DV		 14995void intel_modeset_init_hw(struct drm_device *dev)
14996{
b6283055 14997 intel_update_cdclk(dev);
a8f78b58 14998 intel_prepare_ddi(dev);
f817586c 14999 intel_init_clock_gating(dev);
8090c6b9 15000 intel_enable_gt_powersave(dev);
f817586c
DV		 15001}
15002
79e53945
JB		 15003void intel_modeset_init(struct drm_device *dev)
15004{
652c393a 15005 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15006 int sprite, ret;
8cc87b75 15007 enum pipe pipe;
46f297fb 15008 struct intel_crtc *crtc;
79e53945
JB		 15009
15010 drm_mode_config_init(dev);
15011
15012 dev->mode_config.min_width = 0;
15013 dev->mode_config.min_height = 0;
15014
019d96cb
DA		 15015 dev->mode_config.preferred_depth = 24;
15016 dev->mode_config.prefer_shadow = 1;
15017
25bab385
TU		 15018 dev->mode_config.allow_fb_modifiers = true;
15019
e6ecefaa 15020 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15021
b690e96c
JB		 15022 intel_init_quirks(dev);
15023
1fa61106
ED		 15024 intel_init_pm(dev);
15025
e3c74757
BW		 15026 if (INTEL_INFO(dev)->num_pipes == 0)
15027 return;
15028
e70236a8 15029 intel_init_display(dev);
7c10a2b5 15030 intel_init_audio(dev);
e70236a8 15031
a6c45cf0
CW		 15032 if (IS_GEN2(dev)) {
15033 dev->mode_config.max_width = 2048;
15034 dev->mode_config.max_height = 2048;
15035 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15036 dev->mode_config.max_width = 4096;
15037 dev->mode_config.max_height = 4096;
79e53945 15038 } else {
a6c45cf0
CW		 15039 dev->mode_config.max_width = 8192;
15040 dev->mode_config.max_height = 8192;
79e53945 15041 }
068be561 15042
dc41c154
VS		 15043 if (IS_845G(dev) || IS_I865G(dev)) {
15044 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15045 dev->mode_config.cursor_height = 1023;
15046 } else if (IS_GEN2(dev)) {
068be561
DL		 15047 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15048 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15049 } else {
15050 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15051 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15052 }
15053
5d4545ae 15054 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15055
28c97730 15056 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15057 INTEL_INFO(dev)->num_pipes,
15058 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15059
055e393f 15060 for_each_pipe(dev_priv, pipe) {
8cc87b75 15061 intel_crtc_init(dev, pipe);
3bdcfc0c 15062 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15063 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15064 if (ret)
06da8da2 15065 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15066 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15067 }
79e53945
JB		 15068 }
15069
f42bb70d
JB		 15070 intel_init_dpio(dev);
15071
e72f9fbf 15072 intel_shared_dpll_init(dev);
ee7b9f93 15073
9cce37f4
JB		 15074 /* Just disable it once at startup */
15075 i915_disable_vga(dev);
79e53945 15076 intel_setup_outputs(dev);
11be49eb
CW		 15077
15078 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15079 intel_fbc_disable(dev);
fa9fa083 15080
6e9f798d 15081 drm_modeset_lock_all(dev);
fa9fa083 15082 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15083 drm_modeset_unlock_all(dev);
46f297fb 15084
d3fcc808 15085 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15086 if (!crtc->active)
15087 continue;
15088
46f297fb 15089 /*
46f297fb
JB		 15090 * Note that reserving the BIOS fb up front prevents us
15091 * from stuffing other stolen allocations like the ring
15092 * on top. This prevents some ugliness at boot time, and
15093 * can even allow for smooth boot transitions if the BIOS
15094 * fb is large enough for the active pipe configuration.
15095 */
5724dbd1
DL		 15096 if (dev_priv->display.get_initial_plane_config) {
15097 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15098 &crtc->plane_config);
15099 /*
15100 * If the fb is shared between multiple heads, we'll
15101 * just get the first one.
15102 */
f6936e29 15103 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15104 }
46f297fb 15105 }
2c7111db
CW		 15106}
15107
7fad798e
DV		 15108static void intel_enable_pipe_a(struct drm_device *dev)
15109{
15110 struct intel_connector *connector;
15111 struct drm_connector *crt = NULL;
15112 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15113 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15114
15115 /* We can't just switch on the pipe A, we need to set things up with a
15116 * proper mode and output configuration. As a gross hack, enable pipe A
15117 * by enabling the load detect pipe once. */
3a3371ff 15118 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15119 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15120 crt = &connector->base;
15121 break;
15122 }
15123 }
15124
15125 if (!crt)
15126 return;
15127
208bf9fd 15128 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15129 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15130}
15131
fa555837
DV		 15132static bool
15133intel_check_plane_mapping(struct intel_crtc *crtc)
15134{
7eb552ae
BW		 15135 struct drm_device *dev = crtc->base.dev;
15136 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15137 u32 reg, val;
15138
7eb552ae 15139 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15140 return true;
15141
15142 reg = DSPCNTR(!crtc->plane);
15143 val = I915_READ(reg);
15144
15145 if ((val & DISPLAY_PLANE_ENABLE) &&
15146 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15147 return false;
15148
15149 return true;
15150}
15151
24929352
DV		 15152static void intel_sanitize_crtc(struct intel_crtc *crtc)
15153{
15154 struct drm_device *dev = crtc->base.dev;
15155 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15156 u32 reg;
24929352 15157
24929352 15158 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15159 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15160 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15161
d3eaf884 15162 /* restore vblank interrupts to correct state */
9625604c 15163 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15164 if (crtc->active) {
15165 update_scanline_offset(crtc);
9625604c
DV		 15166 drm_crtc_vblank_on(&crtc->base);
15167 }
d3eaf884 15168
24929352 15169 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15170 * disable the crtc (and hence change the state) if it is wrong. Note
15171 * that gen4+ has a fixed plane -> pipe mapping. */
15172 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15173 struct intel_connector *connector;
15174 bool plane;
15175
24929352
DV		 15176 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15177 crtc->base.base.id);
15178
15179 /* Pipe has the wrong plane attached and the plane is active.
15180 * Temporarily change the plane mapping and disable everything
15181 * ... */
15182 plane = crtc->plane;
b70709a6 15183 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15184 crtc->plane = !plane;
1b509259 15185 intel_crtc_control(&crtc->base, false);
24929352
DV		 15186 crtc->plane = plane;
15187
15188 /* ... and break all links. */
3a3371ff 15189 for_each_intel_connector(dev, connector) {
24929352
DV		 15190 if (connector->encoder->base.crtc != &crtc->base)
15191 continue;
15192
7f1950fb
EE		 15193 connector->base.dpms = DRM_MODE_DPMS_OFF;
15194 connector->base.encoder = NULL;
24929352 15195 }
7f1950fb
EE		 15196 /* multiple connectors may have the same encoder:
15197 * handle them and break crtc link separately */
3a3371ff 15198 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15199 if (connector->encoder->base.crtc == &crtc->base) {
15200 connector->encoder->base.crtc = NULL;
15201 connector->encoder->connectors_active = false;
15202 }
24929352
DV		 15203
15204 WARN_ON(crtc->active);
83d65738 15205 crtc->base.state->enable = false;
49d6fa21 15206 crtc->base.state->active = false;
24929352
DV		 15207 crtc->base.enabled = false;
15208 }
24929352 15209
7fad798e
DV		 15210 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15211 crtc->pipe == PIPE_A && !crtc->active) {
15212 /* BIOS forgot to enable pipe A, this mostly happens after
15213 * resume. Force-enable the pipe to fix this, the update_dpms
15214 * call below we restore the pipe to the right state, but leave
15215 * the required bits on. */
15216 intel_enable_pipe_a(dev);
15217 }
15218
24929352
DV		 15219 /* Adjust the state of the output pipe according to whether we
15220 * have active connectors/encoders. */
15221 intel_crtc_update_dpms(&crtc->base);
15222
53d9f4e9 15223 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15224 struct intel_encoder *encoder;
15225
15226 /* This can happen either due to bugs in the get_hw_state
15227 * functions or because the pipe is force-enabled due to the
15228 * pipe A quirk. */
15229 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15230 crtc->base.base.id,
83d65738 15231 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15232 crtc->active ? "enabled" : "disabled");
15233
83d65738 15234 crtc->base.state->enable = crtc->active;
49d6fa21 15235 crtc->base.state->active = crtc->active;
24929352
DV		 15236 crtc->base.enabled = crtc->active;
15237
15238 /* Because we only establish the connector -> encoder ->
15239 * crtc links if something is active, this means the
15240 * crtc is now deactivated. Break the links. connector
15241 * -> encoder links are only establish when things are
15242 * actually up, hence no need to break them. */
15243 WARN_ON(crtc->active);
15244
15245 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15246 WARN_ON(encoder->connectors_active);
15247 encoder->base.crtc = NULL;
15248 }
15249 }
c5ab3bc0 15250
a3ed6aad 15251 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15252 /*
15253 * We start out with underrun reporting disabled to avoid races.
15254 * For correct bookkeeping mark this on active crtcs.
15255 *
c5ab3bc0
DV		 15256 * Also on gmch platforms we dont have any hardware bits to
15257 * disable the underrun reporting. Which means we need to start
15258 * out with underrun reporting disabled also on inactive pipes,
15259 * since otherwise we'll complain about the garbage we read when
15260 * e.g. coming up after runtime pm.
15261 *
4cc31489
DV		 15262 * No protection against concurrent access is required - at
15263 * worst a fifo underrun happens which also sets this to false.
15264 */
15265 crtc->cpu_fifo_underrun_disabled = true;
15266 crtc->pch_fifo_underrun_disabled = true;
15267 }
24929352
DV		 15268}
15269
15270static void intel_sanitize_encoder(struct intel_encoder *encoder)
15271{
15272 struct intel_connector *connector;
15273 struct drm_device *dev = encoder->base.dev;
15274
15275 /* We need to check both for a crtc link (meaning that the
15276 * encoder is active and trying to read from a pipe) and the
15277 * pipe itself being active. */
15278 bool has_active_crtc = encoder->base.crtc &&
15279 to_intel_crtc(encoder->base.crtc)->active;
15280
15281 if (encoder->connectors_active && !has_active_crtc) {
15282 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15283 encoder->base.base.id,
8e329a03 15284 encoder->base.name);
24929352
DV		 15285
15286 /* Connector is active, but has no active pipe. This is
15287 * fallout from our resume register restoring. Disable
15288 * the encoder manually again. */
15289 if (encoder->base.crtc) {
15290 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15291 encoder->base.base.id,
8e329a03 15292 encoder->base.name);
24929352 15293 encoder->disable(encoder);
a62d1497
VS		 15294 if (encoder->post_disable)
15295 encoder->post_disable(encoder);
24929352 15296 }
7f1950fb
EE		 15297 encoder->base.crtc = NULL;
15298 encoder->connectors_active = false;
24929352
DV		 15299
15300 /* Inconsistent output/port/pipe state happens presumably due to
15301 * a bug in one of the get_hw_state functions. Or someplace else
15302 * in our code, like the register restore mess on resume. Clamp
15303 * things to off as a safer default. */
3a3371ff 15304 for_each_intel_connector(dev, connector) {
24929352
DV		 15305 if (connector->encoder != encoder)
15306 continue;
7f1950fb
EE		 15307 connector->base.dpms = DRM_MODE_DPMS_OFF;
15308 connector->base.encoder = NULL;
24929352
DV		 15309 }
15310 }
15311 /* Enabled encoders without active connectors will be fixed in
15312 * the crtc fixup. */
15313}
15314
04098753 15315void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15316{
15317 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15318 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15319
04098753
ID		 15320 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15321 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15322 i915_disable_vga(dev);
15323 }
15324}
15325
15326void i915_redisable_vga(struct drm_device *dev)
15327{
15328 struct drm_i915_private *dev_priv = dev->dev_private;
15329
8dc8a27c
PZ		 15330 /* This function can be called both from intel_modeset_setup_hw_state or
15331 * at a very early point in our resume sequence, where the power well
15332 * structures are not yet restored. Since this function is at a very
15333 * paranoid "someone might have enabled VGA while we were not looking"
15334 * level, just check if the power well is enabled instead of trying to
15335 * follow the "don't touch the power well if we don't need it" policy
15336 * the rest of the driver uses. */
f458ebbc 15337 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15338 return;
15339
04098753 15340 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15341}
15342
98ec7739
VS		 15343static bool primary_get_hw_state(struct intel_crtc *crtc)
15344{
15345 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15346
15347 if (!crtc->active)
15348 return false;
15349
15350 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15351}
15352
30e984df 15353static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15354{
15355 struct drm_i915_private *dev_priv = dev->dev_private;
15356 enum pipe pipe;
24929352
DV		 15357 struct intel_crtc *crtc;
15358 struct intel_encoder *encoder;
15359 struct intel_connector *connector;
5358901f 15360 int i;
24929352 15361
d3fcc808 15362 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15363 struct drm_plane *primary = crtc->base.primary;
15364 struct intel_plane_state *plane_state;
15365
6e3c9717 15366 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15367
6e3c9717 15368 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15369
0e8ffe1b 15370 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15371 crtc->config);
24929352 15372
83d65738 15373 crtc->base.state->enable = crtc->active;
49d6fa21 15374 crtc->base.state->active = crtc->active;
24929352 15375 crtc->base.enabled = crtc->active;
b70709a6
ML		 15376
15377 plane_state = to_intel_plane_state(primary->state);
15378 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15379
15380 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15381 crtc->base.base.id,
15382 crtc->active ? "enabled" : "disabled");
15383 }
15384
5358901f
DV		 15385 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15386 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15387
3e369b76
ACO		 15388 pll->on = pll->get_hw_state(dev_priv, pll,
15389 &pll->config.hw_state);
5358901f 15390 pll->active = 0;
3e369b76 15391 pll->config.crtc_mask = 0;
d3fcc808 15392 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15393 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15394 pll->active++;
3e369b76 15395 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15396 }
5358901f 15397 }
5358901f 15398
1e6f2ddc 15399 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15400 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15401
3e369b76 15402 if (pll->config.crtc_mask)
bd2bb1b9 15403 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15404 }
15405
b2784e15 15406 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15407 pipe = 0;
15408
15409 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15410 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15411 encoder->base.crtc = &crtc->base;
6e3c9717 15412 encoder->get_config(encoder, crtc->config);
24929352
DV		 15413 } else {
15414 encoder->base.crtc = NULL;
15415 }
15416
15417 encoder->connectors_active = false;
6f2bcceb 15418 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15419 encoder->base.base.id,
8e329a03 15420 encoder->base.name,
24929352 15421 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15422 pipe_name(pipe));
24929352
DV		 15423 }
15424
3a3371ff 15425 for_each_intel_connector(dev, connector) {
24929352
DV		 15426 if (connector->get_hw_state(connector)) {
15427 connector->base.dpms = DRM_MODE_DPMS_ON;
15428 connector->encoder->connectors_active = true;
15429 connector->base.encoder = &connector->encoder->base;
15430 } else {
15431 connector->base.dpms = DRM_MODE_DPMS_OFF;
15432 connector->base.encoder = NULL;
15433 }
15434 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15435 connector->base.base.id,
c23cc417 15436 connector->base.name,
24929352
DV		 15437 connector->base.encoder ? "enabled" : "disabled");
15438 }
30e984df
DV		 15439}
15440
15441/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15442 * and i915 state tracking structures. */
15443void intel_modeset_setup_hw_state(struct drm_device *dev,
15444 bool force_restore)
15445{
15446 struct drm_i915_private *dev_priv = dev->dev_private;
15447 enum pipe pipe;
30e984df
DV		 15448 struct intel_crtc *crtc;
15449 struct intel_encoder *encoder;
35c95375 15450 int i;
30e984df
DV		 15451
15452 intel_modeset_readout_hw_state(dev);
24929352 15453
babea61d
JB		 15454 /*
15455 * Now that we have the config, copy it to each CRTC struct
15456 * Note that this could go away if we move to using crtc_config
15457 * checking everywhere.
15458 */
d3fcc808 15459 for_each_intel_crtc(dev, crtc) {
d330a953 15460 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15461 intel_mode_from_pipe_config(&crtc->base.mode,
15462 crtc->config);
babea61d
JB		 15463 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15464 crtc->base.base.id);
15465 drm_mode_debug_printmodeline(&crtc->base.mode);
15466 }
15467 }
15468
24929352 15469 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15470 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15471 intel_sanitize_encoder(encoder);
15472 }
15473
055e393f 15474 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15475 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15476 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15477 intel_dump_pipe_config(crtc, crtc->config,
15478 "[setup_hw_state]");
24929352 15479 }
9a935856 15480
d29b2f9d
ACO		 15481 intel_modeset_update_connector_atomic_state(dev);
15482
35c95375
DV		 15483 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15484 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15485
15486 if (!pll->on || pll->active)
15487 continue;
15488
15489 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15490
15491 pll->disable(dev_priv, pll);
15492 pll->on = false;
15493 }
15494
3078999f
PB		 15495 if (IS_GEN9(dev))
15496 skl_wm_get_hw_state(dev);
15497 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15498 ilk_wm_get_hw_state(dev);
15499
45e2b5f6 15500 if (force_restore) {
7d0bc1ea
VS		 15501 i915_redisable_vga(dev);
15502
f30da187
DV		 15503 /*
15504 * We need to use raw interfaces for restoring state to avoid
15505 * checking (bogus) intermediate states.
15506 */
055e393f 15507 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15508 struct drm_crtc *crtc =
15509 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15510
83a57153 15511 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15512 }
15513 } else {
15514 intel_modeset_update_staged_output_state(dev);
15515 }
8af6cf88
DV		 15516
15517 intel_modeset_check_state(dev);
2c7111db
CW		 15518}
15519
15520void intel_modeset_gem_init(struct drm_device *dev)
15521{
92122789 15522 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15523 struct drm_crtc *c;
2ff8fde1 15524 struct drm_i915_gem_object *obj;
e0d6149b 15525 int ret;
484b41dd 15526
ae48434c
ID		 15527 mutex_lock(&dev->struct_mutex);
15528 intel_init_gt_powersave(dev);
15529 mutex_unlock(&dev->struct_mutex);
15530
92122789
JB		 15531 /*
15532 * There may be no VBT; and if the BIOS enabled SSC we can
15533 * just keep using it to avoid unnecessary flicker. Whereas if the
15534 * BIOS isn't using it, don't assume it will work even if the VBT
15535 * indicates as much.
15536 */
15537 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15538 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15539 DREF_SSC1_ENABLE);
15540
1833b134 15541 intel_modeset_init_hw(dev);
02e792fb
DV		 15542
15543 intel_setup_overlay(dev);
484b41dd
JB		 15544
15545 /*
15546 * Make sure any fbs we allocated at startup are properly
15547 * pinned & fenced. When we do the allocation it's too early
15548 * for this.
15549 */
70e1e0ec 15550 for_each_crtc(dev, c) {
2ff8fde1
MR		 15551 obj = intel_fb_obj(c->primary->fb);
15552 if (obj == NULL)
484b41dd
JB		 15553 continue;
15554
e0d6149b
TU		 15555 mutex_lock(&dev->struct_mutex);
15556 ret = intel_pin_and_fence_fb_obj(c->primary,
15557 c->primary->fb,
15558 c->primary->state,
15559 NULL);
15560 mutex_unlock(&dev->struct_mutex);
15561 if (ret) {
484b41dd
JB		 15562 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15563 to_intel_crtc(c)->pipe);
66e514c1
DA		 15564 drm_framebuffer_unreference(c->primary->fb);
15565 c->primary->fb = NULL;
afd65eb4 15566 update_state_fb(c->primary);
484b41dd
JB		 15567 }
15568 }
0962c3c9
VS		 15569
15570 intel_backlight_register(dev);
79e53945
JB		 15571}
15572
4932e2c3
ID		 15573void intel_connector_unregister(struct intel_connector *intel_connector)
15574{
15575 struct drm_connector *connector = &intel_connector->base;
15576
15577 intel_panel_destroy_backlight(connector);
34ea3d38 15578 drm_connector_unregister(connector);
4932e2c3
ID		 15579}
15580
79e53945
JB		 15581void intel_modeset_cleanup(struct drm_device *dev)
15582{
652c393a 15583 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15584 struct drm_connector *connector;
652c393a 15585
2eb5252e
ID		 15586 intel_disable_gt_powersave(dev);
15587
0962c3c9
VS		 15588 intel_backlight_unregister(dev);
15589
fd0c0642
DV		 15590 /*
15591 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15592 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15593 * experience fancy races otherwise.
15594 */
2aeb7d3a 15595 intel_irq_uninstall(dev_priv);
eb21b92b 15596
fd0c0642
DV		 15597 /*
15598 * Due to the hpd irq storm handling the hotplug work can re-arm the
15599 * poll handlers. Hence disable polling after hpd handling is shut down.
15600 */
f87ea761 15601 drm_kms_helper_poll_fini(dev);
fd0c0642 15602
652c393a
JB		 15603 mutex_lock(&dev->struct_mutex);
15604
723bfd70
JB		 15605 intel_unregister_dsm_handler();
15606
7ff0ebcc 15607 intel_fbc_disable(dev);
e70236a8 15608
69341a5e
KH		 15609 mutex_unlock(&dev->struct_mutex);
15610
1630fe75
CW		 15611 /* flush any delayed tasks or pending work */
15612 flush_scheduled_work();
15613
db31af1d
JN		 15614 /* destroy the backlight and sysfs files before encoders/connectors */
15615 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15616 struct intel_connector *intel_connector;
15617
15618 intel_connector = to_intel_connector(connector);
15619 intel_connector->unregister(intel_connector);
db31af1d 15620 }
d9255d57 15621
79e53945 15622 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15623
15624 intel_cleanup_overlay(dev);
ae48434c
ID		 15625
15626 mutex_lock(&dev->struct_mutex);
15627 intel_cleanup_gt_powersave(dev);
15628 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15629}
15630
f1c79df3
ZW		 15631/*
15632 * Return which encoder is currently attached for connector.
15633 */
df0e9248 15634struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15635{
df0e9248
CW		 15636 return &intel_attached_encoder(connector)->base;
15637}
f1c79df3 15638
df0e9248
CW		 15639void intel_connector_attach_encoder(struct intel_connector *connector,
15640 struct intel_encoder *encoder)
15641{
15642 connector->encoder = encoder;
15643 drm_mode_connector_attach_encoder(&connector->base,
15644 &encoder->base);
79e53945 15645}
28d52043
DA		 15646
15647/*
15648 * set vga decode state - true == enable VGA decode
15649 */
15650int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15651{
15652 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15653 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15654 u16 gmch_ctrl;
15655
75fa041d
CW		 15656 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15657 DRM_ERROR("failed to read control word\n");
15658 return -EIO;
15659 }
15660
c0cc8a55
CW		 15661 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15662 return 0;
15663
28d52043
DA		 15664 if (state)
15665 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15666 else
15667 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15668
15669 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15670 DRM_ERROR("failed to write control word\n");
15671 return -EIO;
15672 }
15673
28d52043
DA		 15674 return 0;
15675}
c4a1d9e4 15676
c4a1d9e4 15677struct intel_display_error_state {
ff57f1b0
PZ		 15678
15679 u32 power_well_driver;
15680
63b66e5b
CW		 15681 int num_transcoders;
15682
c4a1d9e4
CW		 15683 struct intel_cursor_error_state {
15684 u32 control;
15685 u32 position;
15686 u32 base;
15687 u32 size;
52331309 15688 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15689
15690 struct intel_pipe_error_state {
ddf9c536 15691 bool power_domain_on;
c4a1d9e4 15692 u32 source;
f301b1e1 15693 u32 stat;
52331309 15694 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15695
15696 struct intel_plane_error_state {
15697 u32 control;
15698 u32 stride;
15699 u32 size;
15700 u32 pos;
15701 u32 addr;
15702 u32 surface;
15703 u32 tile_offset;
52331309 15704 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15705
15706 struct intel_transcoder_error_state {
ddf9c536 15707 bool power_domain_on;
63b66e5b
CW		 15708 enum transcoder cpu_transcoder;
15709
15710 u32 conf;
15711
15712 u32 htotal;
15713 u32 hblank;
15714 u32 hsync;
15715 u32 vtotal;
15716 u32 vblank;
15717 u32 vsync;
15718 } transcoder[4];
c4a1d9e4
CW		 15719};
15720
15721struct intel_display_error_state *
15722intel_display_capture_error_state(struct drm_device *dev)
15723{
fbee40df 15724 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15725 struct intel_display_error_state *error;
63b66e5b
CW		 15726 int transcoders[] = {
15727 TRANSCODER_A,
15728 TRANSCODER_B,
15729 TRANSCODER_C,
15730 TRANSCODER_EDP,
15731 };
c4a1d9e4
CW		 15732 int i;
15733
63b66e5b
CW		 15734 if (INTEL_INFO(dev)->num_pipes == 0)
15735 return NULL;
15736
9d1cb914 15737 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15738 if (error == NULL)
15739 return NULL;
15740
190be112 15741 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15742 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15743
055e393f 15744 for_each_pipe(dev_priv, i) {
ddf9c536 15745 error->pipe[i].power_domain_on =
f458ebbc
DV		 15746 __intel_display_power_is_enabled(dev_priv,
15747 POWER_DOMAIN_PIPE(i));
ddf9c536 15748 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15749 continue;
15750
5efb3e28
VS		 15751 error->cursor[i].control = I915_READ(CURCNTR(i));
15752 error->cursor[i].position = I915_READ(CURPOS(i));
15753 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15754
15755 error->plane[i].control = I915_READ(DSPCNTR(i));
15756 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15757 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15758 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15759 error->plane[i].pos = I915_READ(DSPPOS(i));
15760 }
ca291363
PZ		 15761 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15762 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15763 if (INTEL_INFO(dev)->gen >= 4) {
15764 error->plane[i].surface = I915_READ(DSPSURF(i));
15765 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15766 }
15767
c4a1d9e4 15768 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15769
3abfce77 15770 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15771 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15772 }
15773
15774 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15775 if (HAS_DDI(dev_priv->dev))
15776 error->num_transcoders++; /* Account for eDP. */
15777
15778 for (i = 0; i < error->num_transcoders; i++) {
15779 enum transcoder cpu_transcoder = transcoders[i];
15780
ddf9c536 15781 error->transcoder[i].power_domain_on =
f458ebbc 15782 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15783 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15784 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15785 continue;
15786
63b66e5b
CW		 15787 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15788
15789 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15790 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15791 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15792 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15793 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15794 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15795 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15796 }
15797
15798 return error;
15799}
15800
edc3d884
MK		 15801#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15802
c4a1d9e4 15803void
edc3d884 15804intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15805 struct drm_device *dev,
15806 struct intel_display_error_state *error)
15807{
055e393f 15808 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15809 int i;
15810
63b66e5b
CW		 15811 if (!error)
15812 return;
15813
edc3d884 15814 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15815 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15816 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15817 error->power_well_driver);
055e393f 15818 for_each_pipe(dev_priv, i) {
edc3d884 15819 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15820 err_printf(m, " Power: %s\n",
15821 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15822 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15823 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15824
15825 err_printf(m, "Plane [%d]:\n", i);
15826 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15827 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15828 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15829 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15830 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15831 }
4b71a570 15832 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15833 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15834 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15835 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15836 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15837 }
15838
edc3d884
MK		 15839 err_printf(m, "Cursor [%d]:\n", i);
15840 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15841 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15842 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15843 }
63b66e5b
CW		 15844
15845 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15846 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15847 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15848 err_printf(m, " Power: %s\n",
15849 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15850 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15851 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15852 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15853 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15854 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15855 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15856 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15857 }
c4a1d9e4 15858}
e2fcdaa9
VS		 15859
15860void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15861{
15862 struct intel_crtc *crtc;
15863
15864 for_each_intel_crtc(dev, crtc) {
15865 struct intel_unpin_work *work;
e2fcdaa9 15866
5e2d7afc 15867 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15868
15869 work = crtc->unpin_work;
15870
15871 if (work && work->event &&
15872 work->event->base.file_priv == file) {
15873 kfree(work->event);
15874 work->event = NULL;
15875 }
15876
5e2d7afc 15877 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15878 }
15879}
Linux kernel - Deliverables
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