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drm/i915: move encoder pre enable hooks togther on ilk+
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
79e53945
JB		 490{
491 struct drm_device *dev = crtc->dev;
79e53945 492 intel_clock_t clock;
79e53945
JB		 493 int err = target;
494
a210b028 495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 496 /*
a210b028
DV		 497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
79e53945 500 */
1974cad0 501 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
0206e353 512 memset(best_clock, 0, sizeof(*best_clock));
79e53945 513
42158660
ZY		 514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
42158660
ZY		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 524 int this_err;
525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
55607e8a
DV		 895void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
b24e7179
JB		 897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
b24e7179 909
55607e8a 910struct intel_shared_dpll *
e2b78267
DV		 911intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
912{
913 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
914
a43f6e0f 915 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 916 return NULL;
917
a43f6e0f 918 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 919}
920
040484af 921/* For ILK+ */
55607e8a
DV		 922void assert_shared_dpll(struct drm_i915_private *dev_priv,
923 struct intel_shared_dpll *pll,
924 bool state)
040484af 925{
040484af 926 bool cur_state;
5358901f 927 struct intel_dpll_hw_state hw_state;
040484af 928
9d82aa17
ED		 929 if (HAS_PCH_LPT(dev_priv->dev)) {
930 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
931 return;
932 }
933
92b27b08 934 if (WARN (!pll,
46edb027 935 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 936 return;
ee7b9f93 937
5358901f 938 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 939 WARN(cur_state != state,
5358901f
DV		 940 "%s assertion failure (expected %s, current %s)\n",
941 pll->name, state_string(state), state_string(cur_state));
040484af 942}
040484af
JB		 943
944static void assert_fdi_tx(struct drm_i915_private *dev_priv,
945 enum pipe pipe, bool state)
946{
947 int reg;
948 u32 val;
949 bool cur_state;
ad80a810
PZ		 950 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
951 pipe);
040484af 952
affa9354
PZ		 953 if (HAS_DDI(dev_priv->dev)) {
954 /* DDI does not have a specific FDI_TX register */
ad80a810 955 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 956 val = I915_READ(reg);
ad80a810 957 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 958 } else {
959 reg = FDI_TX_CTL(pipe);
960 val = I915_READ(reg);
961 cur_state = !!(val & FDI_TX_ENABLE);
962 }
040484af
JB		 963 WARN(cur_state != state,
964 "FDI TX state assertion failure (expected %s, current %s)\n",
965 state_string(state), state_string(cur_state));
966}
967#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
968#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
969
970static void assert_fdi_rx(struct drm_i915_private *dev_priv,
971 enum pipe pipe, bool state)
972{
973 int reg;
974 u32 val;
975 bool cur_state;
976
d63fa0dc
PZ		 977 reg = FDI_RX_CTL(pipe);
978 val = I915_READ(reg);
979 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 980 WARN(cur_state != state,
981 "FDI RX state assertion failure (expected %s, current %s)\n",
982 state_string(state), state_string(cur_state));
983}
984#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
985#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
986
987static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
988 enum pipe pipe)
989{
990 int reg;
991 u32 val;
992
993 /* ILK FDI PLL is always enabled */
994 if (dev_priv->info->gen == 5)
995 return;
996
bf507ef7 997 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 998 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 999 return;
1000
040484af
JB		 1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1004}
1005
55607e8a
DV		 1006void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1007 enum pipe pipe, bool state)
040484af
JB		 1008{
1009 int reg;
1010 u32 val;
55607e8a 1011 bool cur_state;
040484af
JB		 1012
1013 reg = FDI_RX_CTL(pipe);
1014 val = I915_READ(reg);
55607e8a
DV		 1015 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1016 WARN(cur_state != state,
1017 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018 state_string(state), state_string(cur_state));
040484af
JB		 1019}
1020
ea0760cf
JB		 1021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
0de3b485 1027 bool locked = true;
ea0760cf
JB		 1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1047 pipe_name(pipe));
ea0760cf
JB		 1048}
1049
b840d907
JB		 1050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
b24e7179
JB		 1052{
1053 int reg;
1054 u32 val;
63d7bbe9 1055 bool cur_state;
702e7a56
PZ		 1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
b24e7179 1058
8e636784
DV		 1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
b97186f0
PZ		 1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
63d7bbe9
JB		 1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
653e1026 1098 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
653e1026
VS		 1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
19ec1358 1110 return;
28c05794 1111 }
19ec1358 1112
b24e7179 1113 /* Need to check both planes against the pipe */
653e1026 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1122 }
1123}
1124
19332d7a
JB		 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
20674eef 1128 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1129 int reg, i;
1130 u32 val;
1131
20674eef
VS		 1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
19332d7a 1142 val = I915_READ(reg);
20674eef 1143 WARN((val & SPRITE_ENABLE),
06da8da2 1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
19332d7a 1148 val = I915_READ(reg);
20674eef 1149 WARN((val & DVS_ENABLE),
06da8da2 1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1151 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1152 }
1153}
1154
92f2584a
JB		 1155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
9d82aa17
ED		 1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
92f2584a
JB		 1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
ab9412ba
DV		 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
92f2584a
JB		 1173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
ab9412ba 1178 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
92f2584a
JB		 1184}
1185
4e634389
KP		 1186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
1519b995
KP		 1204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
dc0fa718 1207 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1212 return false;
1213 } else {
dc0fa718 1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
291906f1 1251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1252 enum pipe pipe, int reg, u32 port_sel)
291906f1 1253{
47a05eca 1254 u32 val = I915_READ(reg);
4e634389 1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1257 reg, pipe_name(pipe));
de9a35ab 1258
75c5da27
DV		 1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
de9a35ab 1261 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
47a05eca 1267 u32 val = I915_READ(reg);
b70ad586 1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1270 reg, pipe_name(pipe));
de9a35ab 1271
dc0fa718 1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1273 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1274 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
291906f1 1282
f0575e92
KP		 1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
b70ad586 1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 pipe_name(pipe));
291906f1
JB		 1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
b70ad586 1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 pipe_name(pipe));
291906f1 1298
e2debe91
PZ		 1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1302}
1303
87442f73
DV		 1304static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1305{
1306 int reg;
1307 u32 val;
1308
1309 assert_pipe_disabled(dev_priv, pipe);
1310
1311 /* No really, not for ILK+ */
1312 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1313
1314 /* PLL is protected by panel, make sure we can write it */
1315 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1316 assert_panel_unlocked(dev_priv, pipe);
1317
1318 reg = DPLL(pipe);
1319 val = I915_READ(reg);
1320 val |= DPLL_VCO_ENABLE;
1321
1322 /* We do this three times for luck */
1323 I915_WRITE(reg, val);
1324 POSTING_READ(reg);
1325 udelay(150); /* wait for warmup */
1326 I915_WRITE(reg, val);
1327 POSTING_READ(reg);
1328 udelay(150); /* wait for warmup */
1329 I915_WRITE(reg, val);
1330 POSTING_READ(reg);
1331 udelay(150); /* wait for warmup */
1332}
1333
1334static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1335{
1336 int reg;
1337 u32 val;
1338
58c6eaa2
DV		 1339 assert_pipe_disabled(dev_priv, pipe);
1340
63d7bbe9 1341 /* No really, not for ILK+ */
87442f73 1342 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1343
1344 /* PLL is protected by panel, make sure we can write it */
1345 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1346 assert_panel_unlocked(dev_priv, pipe);
1347
1348 reg = DPLL(pipe);
1349 val = I915_READ(reg);
1350 val |= DPLL_VCO_ENABLE;
1351
1352 /* We do this three times for luck */
1353 I915_WRITE(reg, val);
1354 POSTING_READ(reg);
1355 udelay(150); /* wait for warmup */
1356 I915_WRITE(reg, val);
1357 POSTING_READ(reg);
1358 udelay(150); /* wait for warmup */
1359 I915_WRITE(reg, val);
1360 POSTING_READ(reg);
1361 udelay(150); /* wait for warmup */
1362}
1363
1364/**
1365 * intel_disable_pll - disable a PLL
1366 * @dev_priv: i915 private structure
1367 * @pipe: pipe PLL to disable
1368 *
1369 * Disable the PLL for @pipe, making sure the pipe is off first.
1370 *
1371 * Note! This is for pre-ILK only.
1372 */
1373static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1374{
1375 int reg;
1376 u32 val;
1377
1378 /* Don't disable pipe A or pipe A PLLs if needed */
1379 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1380 return;
1381
1382 /* Make sure the pipe isn't still relying on us */
1383 assert_pipe_disabled(dev_priv, pipe);
1384
1385 reg = DPLL(pipe);
1386 val = I915_READ(reg);
1387 val &= ~DPLL_VCO_ENABLE;
1388 I915_WRITE(reg, val);
1389 POSTING_READ(reg);
1390}
1391
89b667f8
JB		 1392void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1393{
1394 u32 port_mask;
1395
1396 if (!port)
1397 port_mask = DPLL_PORTB_READY_MASK;
1398 else
1399 port_mask = DPLL_PORTC_READY_MASK;
1400
1401 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1402 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1403 'B' + port, I915_READ(DPLL(0)));
1404}
1405
92f2584a 1406/**
e72f9fbf 1407 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1408 * @dev_priv: i915 private structure
1409 * @pipe: pipe PLL to enable
1410 *
1411 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1412 * drives the transcoder clock.
1413 */
e2b78267 1414static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1415{
e2b78267
DV		 1416 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1417 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1418
48da64a8 1419 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1420 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1421 if (WARN_ON(pll == NULL))
48da64a8
CW		 1422 return;
1423
1424 if (WARN_ON(pll->refcount == 0))
1425 return;
ee7b9f93 1426
46edb027
DV		 1427 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1428 pll->name, pll->active, pll->on,
e2b78267 1429 crtc->base.base.id);
92f2584a 1430
cdbd2316
DV		 1431 if (pll->active++) {
1432 WARN_ON(!pll->on);
e9d6944e 1433 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1434 return;
1435 }
f4a091c7 1436 WARN_ON(pll->on);
ee7b9f93 1437
46edb027 1438 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1439 pll->enable(dev_priv, pll);
ee7b9f93 1440 pll->on = true;
92f2584a
JB		 1441}
1442
e2b78267 1443static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1444{
e2b78267
DV		 1445 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1446 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1447
92f2584a
JB		 1448 /* PCH only available on ILK+ */
1449 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1450 if (WARN_ON(pll == NULL))
ee7b9f93 1451 return;
92f2584a 1452
48da64a8
CW		 1453 if (WARN_ON(pll->refcount == 0))
1454 return;
7a419866 1455
46edb027
DV		 1456 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1457 pll->name, pll->active, pll->on,
e2b78267 1458 crtc->base.base.id);
7a419866 1459
48da64a8 1460 if (WARN_ON(pll->active == 0)) {
e9d6944e 1461 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1462 return;
1463 }
1464
e9d6944e 1465 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1466 WARN_ON(!pll->on);
cdbd2316 1467 if (--pll->active)
7a419866 1468 return;
ee7b9f93 1469
46edb027 1470 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1471 pll->disable(dev_priv, pll);
ee7b9f93 1472 pll->on = false;
92f2584a
JB		 1473}
1474
b8a4f404
PZ		 1475static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1476 enum pipe pipe)
040484af 1477{
23670b32 1478 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1479 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1481 uint32_t reg, val, pipeconf_val;
040484af
JB		 1482
1483 /* PCH only available on ILK+ */
1484 BUG_ON(dev_priv->info->gen < 5);
1485
1486 /* Make sure PCH DPLL is enabled */
e72f9fbf 1487 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1488 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1489
1490 /* FDI must be feeding us bits for PCH ports */
1491 assert_fdi_tx_enabled(dev_priv, pipe);
1492 assert_fdi_rx_enabled(dev_priv, pipe);
1493
23670b32
DV		 1494 if (HAS_PCH_CPT(dev)) {
1495 /* Workaround: Set the timing override bit before enabling the
1496 * pch transcoder. */
1497 reg = TRANS_CHICKEN2(pipe);
1498 val = I915_READ(reg);
1499 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1500 I915_WRITE(reg, val);
59c859d6 1501 }
23670b32 1502
ab9412ba 1503 reg = PCH_TRANSCONF(pipe);
040484af 1504 val = I915_READ(reg);
5f7f726d 1505 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1506
1507 if (HAS_PCH_IBX(dev_priv->dev)) {
1508 /*
1509 * make the BPC in transcoder be consistent with
1510 * that in pipeconf reg.
1511 */
dfd07d72
DV		 1512 val &= ~PIPECONF_BPC_MASK;
1513 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1514 }
5f7f726d
PZ		 1515
1516 val &= ~TRANS_INTERLACE_MASK;
1517 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1518 if (HAS_PCH_IBX(dev_priv->dev) &&
1519 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1520 val |= TRANS_LEGACY_INTERLACED_ILK;
1521 else
1522 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1523 else
1524 val |= TRANS_PROGRESSIVE;
1525
040484af
JB		 1526 I915_WRITE(reg, val | TRANS_ENABLE);
1527 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1528 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1529}
1530
8fb033d7 1531static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1532 enum transcoder cpu_transcoder)
040484af 1533{
8fb033d7 1534 u32 val, pipeconf_val;
8fb033d7
PZ		 1535
1536 /* PCH only available on ILK+ */
1537 BUG_ON(dev_priv->info->gen < 5);
1538
8fb033d7 1539 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1540 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1541 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1542
223a6fdf
PZ		 1543 /* Workaround: set timing override bit. */
1544 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1545 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1546 I915_WRITE(_TRANSA_CHICKEN2, val);
1547
25f3ef11 1548 val = TRANS_ENABLE;
937bb610 1549 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1550
9a76b1c6
PZ		 1551 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1552 PIPECONF_INTERLACED_ILK)
a35f2679 1553 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1554 else
1555 val |= TRANS_PROGRESSIVE;
1556
ab9412ba
DV		 1557 I915_WRITE(LPT_TRANSCONF, val);
1558 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1559 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1560}
1561
b8a4f404
PZ		 1562static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1563 enum pipe pipe)
040484af 1564{
23670b32
DV		 1565 struct drm_device *dev = dev_priv->dev;
1566 uint32_t reg, val;
040484af
JB		 1567
1568 /* FDI relies on the transcoder */
1569 assert_fdi_tx_disabled(dev_priv, pipe);
1570 assert_fdi_rx_disabled(dev_priv, pipe);
1571
291906f1
JB		 1572 /* Ports must be off as well */
1573 assert_pch_ports_disabled(dev_priv, pipe);
1574
ab9412ba 1575 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1576 val = I915_READ(reg);
1577 val &= ~TRANS_ENABLE;
1578 I915_WRITE(reg, val);
1579 /* wait for PCH transcoder off, transcoder state */
1580 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1581 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1582
1583 if (!HAS_PCH_IBX(dev)) {
1584 /* Workaround: Clear the timing override chicken bit again. */
1585 reg = TRANS_CHICKEN2(pipe);
1586 val = I915_READ(reg);
1587 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1588 I915_WRITE(reg, val);
1589 }
040484af
JB		 1590}
1591
ab4d966c 1592static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1593{
8fb033d7
PZ		 1594 u32 val;
1595
ab9412ba 1596 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1597 val &= ~TRANS_ENABLE;
ab9412ba 1598 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1599 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1600 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1601 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1602
1603 /* Workaround: clear timing override bit. */
1604 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1605 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1606 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1607}
1608
b24e7179 1609/**
309cfea8 1610 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1611 * @dev_priv: i915 private structure
1612 * @pipe: pipe to enable
040484af 1613 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1614 *
1615 * Enable @pipe, making sure that various hardware specific requirements
1616 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1617 *
1618 * @pipe should be %PIPE_A or %PIPE_B.
1619 *
1620 * Will wait until the pipe is actually running (i.e. first vblank) before
1621 * returning.
1622 */
040484af
JB		 1623static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1624 bool pch_port)
b24e7179 1625{
702e7a56
PZ		 1626 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1627 pipe);
1a240d4d 1628 enum pipe pch_transcoder;
b24e7179
JB		 1629 int reg;
1630 u32 val;
1631
58c6eaa2
DV		 1632 assert_planes_disabled(dev_priv, pipe);
1633 assert_sprites_disabled(dev_priv, pipe);
1634
681e5811 1635 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1636 pch_transcoder = TRANSCODER_A;
1637 else
1638 pch_transcoder = pipe;
1639
b24e7179
JB		 1640 /*
1641 * A pipe without a PLL won't actually be able to drive bits from
1642 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1643 * need the check.
1644 */
1645 if (!HAS_PCH_SPLIT(dev_priv->dev))
1646 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1647 else {
1648 if (pch_port) {
1649 /* if driving the PCH, we need FDI enabled */
cc391bbb 1650 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1651 assert_fdi_tx_pll_enabled(dev_priv,
1652 (enum pipe) cpu_transcoder);
040484af
JB		 1653 }
1654 /* FIXME: assert CPU port conditions for SNB+ */
1655 }
b24e7179 1656
702e7a56 1657 reg = PIPECONF(cpu_transcoder);
b24e7179 1658 val = I915_READ(reg);
00d70b15
CW		 1659 if (val & PIPECONF_ENABLE)
1660 return;
1661
1662 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1663 intel_wait_for_vblank(dev_priv->dev, pipe);
1664}
1665
1666/**
309cfea8 1667 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1668 * @dev_priv: i915 private structure
1669 * @pipe: pipe to disable
1670 *
1671 * Disable @pipe, making sure that various hardware specific requirements
1672 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1673 *
1674 * @pipe should be %PIPE_A or %PIPE_B.
1675 *
1676 * Will wait until the pipe has shut down before returning.
1677 */
1678static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1679 enum pipe pipe)
1680{
702e7a56
PZ		 1681 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1682 pipe);
b24e7179
JB		 1683 int reg;
1684 u32 val;
1685
1686 /*
1687 * Make sure planes won't keep trying to pump pixels to us,
1688 * or we might hang the display.
1689 */
1690 assert_planes_disabled(dev_priv, pipe);
19332d7a 1691 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1692
1693 /* Don't disable pipe A or pipe A PLLs if needed */
1694 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1695 return;
1696
702e7a56 1697 reg = PIPECONF(cpu_transcoder);
b24e7179 1698 val = I915_READ(reg);
00d70b15
CW		 1699 if ((val & PIPECONF_ENABLE) == 0)
1700 return;
1701
1702 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1703 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1704}
1705
d74362c9
KP		 1706/*
1707 * Plane regs are double buffered, going from enabled->disabled needs a
1708 * trigger in order to latch. The display address reg provides this.
1709 */
6f1d69b0 1710void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1711 enum plane plane)
1712{
14f86147
DL		 1713 if (dev_priv->info->gen >= 4)
1714 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1715 else
1716 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1717}
1718
b24e7179
JB		 1719/**
1720 * intel_enable_plane - enable a display plane on a given pipe
1721 * @dev_priv: i915 private structure
1722 * @plane: plane to enable
1723 * @pipe: pipe being fed
1724 *
1725 * Enable @plane on @pipe, making sure that @pipe is running first.
1726 */
1727static void intel_enable_plane(struct drm_i915_private *dev_priv,
1728 enum plane plane, enum pipe pipe)
1729{
1730 int reg;
1731 u32 val;
1732
1733 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1734 assert_pipe_enabled(dev_priv, pipe);
1735
1736 reg = DSPCNTR(plane);
1737 val = I915_READ(reg);
00d70b15
CW		 1738 if (val & DISPLAY_PLANE_ENABLE)
1739 return;
1740
1741 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1742 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1743 intel_wait_for_vblank(dev_priv->dev, pipe);
1744}
1745
b24e7179
JB		 1746/**
1747 * intel_disable_plane - disable a display plane
1748 * @dev_priv: i915 private structure
1749 * @plane: plane to disable
1750 * @pipe: pipe consuming the data
1751 *
1752 * Disable @plane; should be an independent operation.
1753 */
1754static void intel_disable_plane(struct drm_i915_private *dev_priv,
1755 enum plane plane, enum pipe pipe)
1756{
1757 int reg;
1758 u32 val;
1759
1760 reg = DSPCNTR(plane);
1761 val = I915_READ(reg);
00d70b15
CW		 1762 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1763 return;
1764
1765 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1766 intel_flush_display_plane(dev_priv, plane);
1767 intel_wait_for_vblank(dev_priv->dev, pipe);
1768}
1769
693db184
CW		 1770static bool need_vtd_wa(struct drm_device *dev)
1771{
1772#ifdef CONFIG_INTEL_IOMMU
1773 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1774 return true;
1775#endif
1776 return false;
1777}
1778
127bd2ac 1779int
48b956c5 1780intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1781 struct drm_i915_gem_object *obj,
919926ae 1782 struct intel_ring_buffer *pipelined)
6b95a207 1783{
ce453d81 1784 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1785 u32 alignment;
1786 int ret;
1787
05394f39 1788 switch (obj->tiling_mode) {
6b95a207 1789 case I915_TILING_NONE:
534843da
CW		 1790 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791 alignment = 128 * 1024;
a6c45cf0 1792 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1793 alignment = 4 * 1024;
1794 else
1795 alignment = 64 * 1024;
6b95a207
KH		 1796 break;
1797 case I915_TILING_X:
1798 /* pin() will align the object as required by fence */
1799 alignment = 0;
1800 break;
1801 case I915_TILING_Y:
8bb6e959
DV		 1802 /* Despite that we check this in framebuffer_init userspace can
1803 * screw us over and change the tiling after the fact. Only
1804 * pinned buffers can't change their tiling. */
1805 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1806 return -EINVAL;
1807 default:
1808 BUG();
1809 }
1810
693db184
CW		 1811 /* Note that the w/a also requires 64 PTE of padding following the
1812 * bo. We currently fill all unused PTE with the shadow page and so
1813 * we should always have valid PTE following the scanout preventing
1814 * the VT-d warning.
1815 */
1816 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1817 alignment = 256 * 1024;
1818
ce453d81 1819 dev_priv->mm.interruptible = false;
2da3b9b9 1820 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1821 if (ret)
ce453d81 1822 goto err_interruptible;
6b95a207
KH		 1823
1824 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1825 * fence, whereas 965+ only requires a fence if using
1826 * framebuffer compression. For simplicity, we always install
1827 * a fence as the cost is not that onerous.
1828 */
06d98131 1829 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1830 if (ret)
1831 goto err_unpin;
1690e1eb 1832
9a5a53b3 1833 i915_gem_object_pin_fence(obj);
6b95a207 1834
ce453d81 1835 dev_priv->mm.interruptible = true;
6b95a207 1836 return 0;
48b956c5
CW		 1837
1838err_unpin:
1839 i915_gem_object_unpin(obj);
ce453d81
CW		 1840err_interruptible:
1841 dev_priv->mm.interruptible = true;
48b956c5 1842 return ret;
6b95a207
KH		 1843}
1844
1690e1eb
CW		 1845void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1846{
1847 i915_gem_object_unpin_fence(obj);
1848 i915_gem_object_unpin(obj);
1849}
1850
c2c75131
DV		 1851/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1852 * is assumed to be a power-of-two. */
bc752862
CW		 1853unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1854 unsigned int tiling_mode,
1855 unsigned int cpp,
1856 unsigned int pitch)
c2c75131 1857{
bc752862
CW		 1858 if (tiling_mode != I915_TILING_NONE) {
1859 unsigned int tile_rows, tiles;
c2c75131 1860
bc752862
CW		 1861 tile_rows = *y / 8;
1862 *y %= 8;
c2c75131 1863
bc752862
CW		 1864 tiles = *x / (512/cpp);
1865 *x %= 512/cpp;
1866
1867 return tile_rows * pitch * 8 + tiles * 4096;
1868 } else {
1869 unsigned int offset;
1870
1871 offset = *y * pitch + *x * cpp;
1872 *y = 0;
1873 *x = (offset & 4095) / cpp;
1874 return offset & -4096;
1875 }
c2c75131
DV		 1876}
1877
17638cd6
JB		 1878static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1879 int x, int y)
81255565
JB		 1880{
1881 struct drm_device *dev = crtc->dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
1883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1884 struct intel_framebuffer *intel_fb;
05394f39 1885 struct drm_i915_gem_object *obj;
81255565 1886 int plane = intel_crtc->plane;
e506a0c6 1887 unsigned long linear_offset;
81255565 1888 u32 dspcntr;
5eddb70b 1889 u32 reg;
81255565
JB		 1890
1891 switch (plane) {
1892 case 0:
1893 case 1:
1894 break;
1895 default:
84f44ce7 1896 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1897 return -EINVAL;
1898 }
1899
1900 intel_fb = to_intel_framebuffer(fb);
1901 obj = intel_fb->obj;
81255565 1902
5eddb70b
CW		 1903 reg = DSPCNTR(plane);
1904 dspcntr = I915_READ(reg);
81255565
JB		 1905 /* Mask out pixel format bits in case we change it */
1906 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1907 switch (fb->pixel_format) {
1908 case DRM_FORMAT_C8:
81255565
JB		 1909 dspcntr |= DISPPLANE_8BPP;
1910 break;
57779d06
VS		 1911 case DRM_FORMAT_XRGB1555:
1912 case DRM_FORMAT_ARGB1555:
1913 dspcntr |= DISPPLANE_BGRX555;
81255565 1914 break;
57779d06
VS		 1915 case DRM_FORMAT_RGB565:
1916 dspcntr |= DISPPLANE_BGRX565;
1917 break;
1918 case DRM_FORMAT_XRGB8888:
1919 case DRM_FORMAT_ARGB8888:
1920 dspcntr |= DISPPLANE_BGRX888;
1921 break;
1922 case DRM_FORMAT_XBGR8888:
1923 case DRM_FORMAT_ABGR8888:
1924 dspcntr |= DISPPLANE_RGBX888;
1925 break;
1926 case DRM_FORMAT_XRGB2101010:
1927 case DRM_FORMAT_ARGB2101010:
1928 dspcntr |= DISPPLANE_BGRX101010;
1929 break;
1930 case DRM_FORMAT_XBGR2101010:
1931 case DRM_FORMAT_ABGR2101010:
1932 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1933 break;
1934 default:
baba133a 1935 BUG();
81255565 1936 }
57779d06 1937
a6c45cf0 1938 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1939 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1940 dspcntr |= DISPPLANE_TILED;
1941 else
1942 dspcntr &= ~DISPPLANE_TILED;
1943 }
1944
de1aa629
VS		 1945 if (IS_G4X(dev))
1946 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1947
5eddb70b 1948 I915_WRITE(reg, dspcntr);
81255565 1949
e506a0c6 1950 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1951
c2c75131
DV		 1952 if (INTEL_INFO(dev)->gen >= 4) {
1953 intel_crtc->dspaddr_offset =
bc752862
CW		 1954 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1955 fb->bits_per_pixel / 8,
1956 fb->pitches[0]);
c2c75131
DV		 1957 linear_offset -= intel_crtc->dspaddr_offset;
1958 } else {
e506a0c6 1959 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1960 }
e506a0c6
DV		 1961
1962 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1963 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1964 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1965 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1966 I915_MODIFY_DISPBASE(DSPSURF(plane),
1967 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1968 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1969 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1970 } else
e506a0c6 1971 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1972 POSTING_READ(reg);
81255565 1973
17638cd6
JB		 1974 return 0;
1975}
1976
1977static int ironlake_update_plane(struct drm_crtc *crtc,
1978 struct drm_framebuffer *fb, int x, int y)
1979{
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
1984 struct drm_i915_gem_object *obj;
1985 int plane = intel_crtc->plane;
e506a0c6 1986 unsigned long linear_offset;
17638cd6
JB		 1987 u32 dspcntr;
1988 u32 reg;
1989
1990 switch (plane) {
1991 case 0:
1992 case 1:
27f8227b 1993 case 2:
17638cd6
JB		 1994 break;
1995 default:
84f44ce7 1996 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1997 return -EINVAL;
1998 }
1999
2000 intel_fb = to_intel_framebuffer(fb);
2001 obj = intel_fb->obj;
2002
2003 reg = DSPCNTR(plane);
2004 dspcntr = I915_READ(reg);
2005 /* Mask out pixel format bits in case we change it */
2006 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2007 switch (fb->pixel_format) {
2008 case DRM_FORMAT_C8:
17638cd6
JB		 2009 dspcntr |= DISPPLANE_8BPP;
2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2013 break;
57779d06
VS		 2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2029 break;
2030 default:
baba133a 2031 BUG();
17638cd6
JB		 2032 }
2033
2034 if (obj->tiling_mode != I915_TILING_NONE)
2035 dspcntr |= DISPPLANE_TILED;
2036 else
2037 dspcntr &= ~DISPPLANE_TILED;
2038
2039 /* must disable */
2040 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2041
2042 I915_WRITE(reg, dspcntr);
2043
e506a0c6 2044 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2045 intel_crtc->dspaddr_offset =
bc752862
CW		 2046 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2047 fb->bits_per_pixel / 8,
2048 fb->pitches[0]);
c2c75131 2049 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2050
e506a0c6
DV		 2051 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2052 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2053 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2054 I915_MODIFY_DISPBASE(DSPSURF(plane),
2055 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2056 if (IS_HASWELL(dev)) {
2057 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2058 } else {
2059 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2060 I915_WRITE(DSPLINOFF(plane), linear_offset);
2061 }
17638cd6
JB		 2062 POSTING_READ(reg);
2063
2064 return 0;
2065}
2066
2067/* Assume fb object is pinned & idle & fenced and just update base pointers */
2068static int
2069intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2070 int x, int y, enum mode_set_atomic state)
2071{
2072 struct drm_device *dev = crtc->dev;
2073 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2074
6b8e6ed0
CW		 2075 if (dev_priv->display.disable_fbc)
2076 dev_priv->display.disable_fbc(dev);
3dec0095 2077 intel_increase_pllclock(crtc);
81255565 2078
6b8e6ed0 2079 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2080}
2081
96a02917
VS		 2082void intel_display_handle_reset(struct drm_device *dev)
2083{
2084 struct drm_i915_private *dev_priv = dev->dev_private;
2085 struct drm_crtc *crtc;
2086
2087 /*
2088 * Flips in the rings have been nuked by the reset,
2089 * so complete all pending flips so that user space
2090 * will get its events and not get stuck.
2091 *
2092 * Also update the base address of all primary
2093 * planes to the the last fb to make sure we're
2094 * showing the correct fb after a reset.
2095 *
2096 * Need to make two loops over the crtcs so that we
2097 * don't try to grab a crtc mutex before the
2098 * pending_flip_queue really got woken up.
2099 */
2100
2101 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 enum plane plane = intel_crtc->plane;
2104
2105 intel_prepare_page_flip(dev, plane);
2106 intel_finish_page_flip_plane(dev, plane);
2107 }
2108
2109 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112 mutex_lock(&crtc->mutex);
2113 if (intel_crtc->active)
2114 dev_priv->display.update_plane(crtc, crtc->fb,
2115 crtc->x, crtc->y);
2116 mutex_unlock(&crtc->mutex);
2117 }
2118}
2119
14667a4b
CW		 2120static int
2121intel_finish_fb(struct drm_framebuffer *old_fb)
2122{
2123 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2124 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2125 bool was_interruptible = dev_priv->mm.interruptible;
2126 int ret;
2127
14667a4b
CW		 2128 /* Big Hammer, we also need to ensure that any pending
2129 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2130 * current scanout is retired before unpinning the old
2131 * framebuffer.
2132 *
2133 * This should only fail upon a hung GPU, in which case we
2134 * can safely continue.
2135 */
2136 dev_priv->mm.interruptible = false;
2137 ret = i915_gem_object_finish_gpu(obj);
2138 dev_priv->mm.interruptible = was_interruptible;
2139
2140 return ret;
2141}
2142
198598d0
VS		 2143static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2144{
2145 struct drm_device *dev = crtc->dev;
2146 struct drm_i915_master_private *master_priv;
2147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2148
2149 if (!dev->primary->master)
2150 return;
2151
2152 master_priv = dev->primary->master->driver_priv;
2153 if (!master_priv->sarea_priv)
2154 return;
2155
2156 switch (intel_crtc->pipe) {
2157 case 0:
2158 master_priv->sarea_priv->pipeA_x = x;
2159 master_priv->sarea_priv->pipeA_y = y;
2160 break;
2161 case 1:
2162 master_priv->sarea_priv->pipeB_x = x;
2163 master_priv->sarea_priv->pipeB_y = y;
2164 break;
2165 default:
2166 break;
2167 }
2168}
2169
5c3b82e2 2170static int
3c4fdcfb 2171intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2172 struct drm_framebuffer *fb)
79e53945
JB		 2173{
2174 struct drm_device *dev = crtc->dev;
6b8e6ed0 2175 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2177 struct drm_framebuffer *old_fb;
5c3b82e2 2178 int ret;
79e53945
JB		 2179
2180 /* no fb bound */
94352cf9 2181 if (!fb) {
a5071c2f 2182 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2183 return 0;
2184 }
2185
7eb552ae 2186 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2187 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2188 plane_name(intel_crtc->plane),
2189 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2190 return -EINVAL;
79e53945
JB		 2191 }
2192
5c3b82e2 2193 mutex_lock(&dev->struct_mutex);
265db958 2194 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2195 to_intel_framebuffer(fb)->obj,
919926ae 2196 NULL);
5c3b82e2
CW		 2197 if (ret != 0) {
2198 mutex_unlock(&dev->struct_mutex);
a5071c2f 2199 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2200 return ret;
2201 }
79e53945 2202
94352cf9 2203 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2204 if (ret) {
94352cf9 2205 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2206 mutex_unlock(&dev->struct_mutex);
a5071c2f 2207 DRM_ERROR("failed to update base address\n");
4e6cfefc 2208 return ret;
79e53945 2209 }
3c4fdcfb 2210
94352cf9
DV		 2211 old_fb = crtc->fb;
2212 crtc->fb = fb;
6c4c86f5
DV		 2213 crtc->x = x;
2214 crtc->y = y;
94352cf9 2215
b7f1de28 2216 if (old_fb) {
d7697eea
DV		 2217 if (intel_crtc->active && old_fb != fb)
2218 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2219 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2220 }
652c393a 2221
6b8e6ed0 2222 intel_update_fbc(dev);
5c3b82e2 2223 mutex_unlock(&dev->struct_mutex);
79e53945 2224
198598d0 2225 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2226
2227 return 0;
79e53945
JB		 2228}
2229
5e84e1a4
ZW		 2230static void intel_fdi_normal_train(struct drm_crtc *crtc)
2231{
2232 struct drm_device *dev = crtc->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235 int pipe = intel_crtc->pipe;
2236 u32 reg, temp;
2237
2238 /* enable normal train */
2239 reg = FDI_TX_CTL(pipe);
2240 temp = I915_READ(reg);
61e499bf 2241 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2242 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2243 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2244 } else {
2245 temp &= ~FDI_LINK_TRAIN_NONE;
2246 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2247 }
5e84e1a4
ZW		 2248 I915_WRITE(reg, temp);
2249
2250 reg = FDI_RX_CTL(pipe);
2251 temp = I915_READ(reg);
2252 if (HAS_PCH_CPT(dev)) {
2253 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2254 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2255 } else {
2256 temp &= ~FDI_LINK_TRAIN_NONE;
2257 temp |= FDI_LINK_TRAIN_NONE;
2258 }
2259 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2260
2261 /* wait one idle pattern time */
2262 POSTING_READ(reg);
2263 udelay(1000);
357555c0
JB		 2264
2265 /* IVB wants error correction enabled */
2266 if (IS_IVYBRIDGE(dev))
2267 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2268 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2269}
2270
1e833f40
DV		 2271static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2272{
2273 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2274}
2275
01a415fd
DV		 2276static void ivb_modeset_global_resources(struct drm_device *dev)
2277{
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct intel_crtc *pipe_B_crtc =
2280 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2281 struct intel_crtc *pipe_C_crtc =
2282 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2283 uint32_t temp;
2284
1e833f40
DV		 2285 /*
2286 * When everything is off disable fdi C so that we could enable fdi B
2287 * with all lanes. Note that we don't care about enabled pipes without
2288 * an enabled pch encoder.
2289 */
2290 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2291 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2292 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2294
2295 temp = I915_READ(SOUTH_CHICKEN1);
2296 temp &= ~FDI_BC_BIFURCATION_SELECT;
2297 DRM_DEBUG_KMS("disabling fdi C rx\n");
2298 I915_WRITE(SOUTH_CHICKEN1, temp);
2299 }
2300}
2301
8db9d77b
ZW		 2302/* The FDI link training functions for ILK/Ibexpeak. */
2303static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2304{
2305 struct drm_device *dev = crtc->dev;
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308 int pipe = intel_crtc->pipe;
0fc932b8 2309 int plane = intel_crtc->plane;
5eddb70b 2310 u32 reg, temp, tries;
8db9d77b 2311
0fc932b8
JB		 2312 /* FDI needs bits from pipe & plane first */
2313 assert_pipe_enabled(dev_priv, pipe);
2314 assert_plane_enabled(dev_priv, plane);
2315
e1a44743
AJ		 2316 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2317 for train result */
5eddb70b
CW		 2318 reg = FDI_RX_IMR(pipe);
2319 temp = I915_READ(reg);
e1a44743
AJ		 2320 temp &= ~FDI_RX_SYMBOL_LOCK;
2321 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2322 I915_WRITE(reg, temp);
2323 I915_READ(reg);
e1a44743
AJ		 2324 udelay(150);
2325
8db9d77b 2326 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
627eb5a3
DV		 2329 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2330 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2331 temp &= ~FDI_LINK_TRAIN_NONE;
2332 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2333 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2334
5eddb70b
CW		 2335 reg = FDI_RX_CTL(pipe);
2336 temp = I915_READ(reg);
8db9d77b
ZW		 2337 temp &= ~FDI_LINK_TRAIN_NONE;
2338 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2339 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2340
2341 POSTING_READ(reg);
8db9d77b
ZW		 2342 udelay(150);
2343
5b2adf89 2344 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2345 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2347 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2348
5eddb70b 2349 reg = FDI_RX_IIR(pipe);
e1a44743 2350 for (tries = 0; tries < 5; tries++) {
5eddb70b 2351 temp = I915_READ(reg);
8db9d77b
ZW		 2352 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2353
2354 if ((temp & FDI_RX_BIT_LOCK)) {
2355 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2356 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2357 break;
2358 }
8db9d77b 2359 }
e1a44743 2360 if (tries == 5)
5eddb70b 2361 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2362
2363 /* Train 2 */
5eddb70b
CW		 2364 reg = FDI_TX_CTL(pipe);
2365 temp = I915_READ(reg);
8db9d77b
ZW		 2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2368 I915_WRITE(reg, temp);
8db9d77b 2369
5eddb70b
CW		 2370 reg = FDI_RX_CTL(pipe);
2371 temp = I915_READ(reg);
8db9d77b
ZW		 2372 temp &= ~FDI_LINK_TRAIN_NONE;
2373 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2374 I915_WRITE(reg, temp);
8db9d77b 2375
5eddb70b
CW		 2376 POSTING_READ(reg);
2377 udelay(150);
8db9d77b 2378
5eddb70b 2379 reg = FDI_RX_IIR(pipe);
e1a44743 2380 for (tries = 0; tries < 5; tries++) {
5eddb70b 2381 temp = I915_READ(reg);
8db9d77b
ZW		 2382 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2383
2384 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2385 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2386 DRM_DEBUG_KMS("FDI train 2 done.\n");
2387 break;
2388 }
8db9d77b 2389 }
e1a44743 2390 if (tries == 5)
5eddb70b 2391 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2392
2393 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2394
8db9d77b
ZW		 2395}
2396
0206e353 2397static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2398 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2399 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2400 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2401 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2402};
2403
2404/* The FDI link training functions for SNB/Cougarpoint. */
2405static void gen6_fdi_link_train(struct drm_crtc *crtc)
2406{
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 int pipe = intel_crtc->pipe;
fa37d39e 2411 u32 reg, temp, i, retry;
8db9d77b 2412
e1a44743
AJ		 2413 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2414 for train result */
5eddb70b
CW		 2415 reg = FDI_RX_IMR(pipe);
2416 temp = I915_READ(reg);
e1a44743
AJ		 2417 temp &= ~FDI_RX_SYMBOL_LOCK;
2418 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2419 I915_WRITE(reg, temp);
2420
2421 POSTING_READ(reg);
e1a44743
AJ		 2422 udelay(150);
2423
8db9d77b 2424 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2425 reg = FDI_TX_CTL(pipe);
2426 temp = I915_READ(reg);
627eb5a3
DV		 2427 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2428 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_PATTERN_1;
2431 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2432 /* SNB-B */
2433 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
d74cf324
DV		 2436 I915_WRITE(FDI_RX_MISC(pipe),
2437 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2438
5eddb70b
CW		 2439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 if (HAS_PCH_CPT(dev)) {
2442 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2443 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2444 } else {
2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 }
5eddb70b
CW		 2448 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2449
2450 POSTING_READ(reg);
8db9d77b
ZW		 2451 udelay(150);
2452
0206e353 2453 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
8db9d77b
ZW		 2456 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2457 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2458 I915_WRITE(reg, temp);
2459
2460 POSTING_READ(reg);
8db9d77b
ZW		 2461 udelay(500);
2462
fa37d39e
SP		 2463 for (retry = 0; retry < 5; retry++) {
2464 reg = FDI_RX_IIR(pipe);
2465 temp = I915_READ(reg);
2466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467 if (temp & FDI_RX_BIT_LOCK) {
2468 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2469 DRM_DEBUG_KMS("FDI train 1 done.\n");
2470 break;
2471 }
2472 udelay(50);
8db9d77b 2473 }
fa37d39e
SP		 2474 if (retry < 5)
2475 break;
8db9d77b
ZW		 2476 }
2477 if (i == 4)
5eddb70b 2478 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2479
2480 /* Train 2 */
5eddb70b
CW		 2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_2;
2485 if (IS_GEN6(dev)) {
2486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487 /* SNB-B */
2488 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2489 }
5eddb70b 2490 I915_WRITE(reg, temp);
8db9d77b 2491
5eddb70b
CW		 2492 reg = FDI_RX_CTL(pipe);
2493 temp = I915_READ(reg);
8db9d77b
ZW		 2494 if (HAS_PCH_CPT(dev)) {
2495 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2496 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2497 } else {
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_2;
2500 }
5eddb70b
CW		 2501 I915_WRITE(reg, temp);
2502
2503 POSTING_READ(reg);
8db9d77b
ZW		 2504 udelay(150);
2505
0206e353 2506 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2507 reg = FDI_TX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2510 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2511 I915_WRITE(reg, temp);
2512
2513 POSTING_READ(reg);
8db9d77b
ZW		 2514 udelay(500);
2515
fa37d39e
SP		 2516 for (retry = 0; retry < 5; retry++) {
2517 reg = FDI_RX_IIR(pipe);
2518 temp = I915_READ(reg);
2519 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2520 if (temp & FDI_RX_SYMBOL_LOCK) {
2521 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2522 DRM_DEBUG_KMS("FDI train 2 done.\n");
2523 break;
2524 }
2525 udelay(50);
8db9d77b 2526 }
fa37d39e
SP		 2527 if (retry < 5)
2528 break;
8db9d77b
ZW		 2529 }
2530 if (i == 4)
5eddb70b 2531 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2532
2533 DRM_DEBUG_KMS("FDI train done.\n");
2534}
2535
357555c0
JB		 2536/* Manual link training for Ivy Bridge A0 parts */
2537static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2538{
2539 struct drm_device *dev = crtc->dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2542 int pipe = intel_crtc->pipe;
2543 u32 reg, temp, i;
2544
2545 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2546 for train result */
2547 reg = FDI_RX_IMR(pipe);
2548 temp = I915_READ(reg);
2549 temp &= ~FDI_RX_SYMBOL_LOCK;
2550 temp &= ~FDI_RX_BIT_LOCK;
2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
2554 udelay(150);
2555
01a415fd
DV		 2556 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2557 I915_READ(FDI_RX_IIR(pipe)));
2558
357555c0
JB		 2559 /* enable CPU FDI TX and PCH FDI RX */
2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
627eb5a3
DV		 2562 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2563 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2564 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2565 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2568 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2569 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2570
d74cf324
DV		 2571 I915_WRITE(FDI_RX_MISC(pipe),
2572 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2573
357555c0
JB		 2574 reg = FDI_RX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~FDI_LINK_TRAIN_AUTO;
2577 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2578 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2579 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2580 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2581
2582 POSTING_READ(reg);
2583 udelay(150);
2584
0206e353 2585 for (i = 0; i < 4; i++) {
357555c0
JB		 2586 reg = FDI_TX_CTL(pipe);
2587 temp = I915_READ(reg);
2588 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589 temp |= snb_b_fdi_train_param[i];
2590 I915_WRITE(reg, temp);
2591
2592 POSTING_READ(reg);
2593 udelay(500);
2594
2595 reg = FDI_RX_IIR(pipe);
2596 temp = I915_READ(reg);
2597 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2598
2599 if (temp & FDI_RX_BIT_LOCK ||
2600 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2601 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2602 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2603 break;
2604 }
2605 }
2606 if (i == 4)
2607 DRM_ERROR("FDI train 1 fail!\n");
2608
2609 /* Train 2 */
2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2613 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2616 I915_WRITE(reg, temp);
2617
2618 reg = FDI_RX_CTL(pipe);
2619 temp = I915_READ(reg);
2620 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2622 I915_WRITE(reg, temp);
2623
2624 POSTING_READ(reg);
2625 udelay(150);
2626
0206e353 2627 for (i = 0; i < 4; i++) {
357555c0
JB		 2628 reg = FDI_TX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= snb_b_fdi_train_param[i];
2632 I915_WRITE(reg, temp);
2633
2634 POSTING_READ(reg);
2635 udelay(500);
2636
2637 reg = FDI_RX_IIR(pipe);
2638 temp = I915_READ(reg);
2639 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2640
2641 if (temp & FDI_RX_SYMBOL_LOCK) {
2642 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2643 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2644 break;
2645 }
2646 }
2647 if (i == 4)
2648 DRM_ERROR("FDI train 2 fail!\n");
2649
2650 DRM_DEBUG_KMS("FDI train done.\n");
2651}
2652
88cefb6c 2653static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2654{
88cefb6c 2655 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2656 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2657 int pipe = intel_crtc->pipe;
5eddb70b 2658 u32 reg, temp;
79e53945 2659
c64e311e 2660
c98e9dcf 2661 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2662 reg = FDI_RX_CTL(pipe);
2663 temp = I915_READ(reg);
627eb5a3
DV		 2664 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2665 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2666 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2667 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2668
2669 POSTING_READ(reg);
c98e9dcf
JB		 2670 udelay(200);
2671
2672 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2673 temp = I915_READ(reg);
2674 I915_WRITE(reg, temp | FDI_PCDCLK);
2675
2676 POSTING_READ(reg);
c98e9dcf
JB		 2677 udelay(200);
2678
20749730
PZ		 2679 /* Enable CPU FDI TX PLL, always on for Ironlake */
2680 reg = FDI_TX_CTL(pipe);
2681 temp = I915_READ(reg);
2682 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2683 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2684
20749730
PZ		 2685 POSTING_READ(reg);
2686 udelay(100);
6be4a607 2687 }
0e23b99d
JB		 2688}
2689
88cefb6c
DV		 2690static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2691{
2692 struct drm_device *dev = intel_crtc->base.dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 int pipe = intel_crtc->pipe;
2695 u32 reg, temp;
2696
2697 /* Switch from PCDclk to Rawclk */
2698 reg = FDI_RX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2701
2702 /* Disable CPU FDI TX PLL */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2706
2707 POSTING_READ(reg);
2708 udelay(100);
2709
2710 reg = FDI_RX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2713
2714 /* Wait for the clocks to turn off. */
2715 POSTING_READ(reg);
2716 udelay(100);
2717}
2718
0fc932b8
JB		 2719static void ironlake_fdi_disable(struct drm_crtc *crtc)
2720{
2721 struct drm_device *dev = crtc->dev;
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724 int pipe = intel_crtc->pipe;
2725 u32 reg, temp;
2726
2727 /* disable CPU FDI tx and PCH FDI rx */
2728 reg = FDI_TX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2731 POSTING_READ(reg);
2732
2733 reg = FDI_RX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~(0x7 << 16);
dfd07d72 2736 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2737 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2738
2739 POSTING_READ(reg);
2740 udelay(100);
2741
2742 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2743 if (HAS_PCH_IBX(dev)) {
2744 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2745 }
0fc932b8
JB		 2746
2747 /* still set train pattern 1 */
2748 reg = FDI_TX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~FDI_LINK_TRAIN_NONE;
2751 temp |= FDI_LINK_TRAIN_PATTERN_1;
2752 I915_WRITE(reg, temp);
2753
2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 if (HAS_PCH_CPT(dev)) {
2757 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2758 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2759 } else {
2760 temp &= ~FDI_LINK_TRAIN_NONE;
2761 temp |= FDI_LINK_TRAIN_PATTERN_1;
2762 }
2763 /* BPC in FDI rx is consistent with that in PIPECONF */
2764 temp &= ~(0x07 << 16);
dfd07d72 2765 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2766 I915_WRITE(reg, temp);
2767
2768 POSTING_READ(reg);
2769 udelay(100);
2770}
2771
5bb61643
CW		 2772static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2773{
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2777 unsigned long flags;
2778 bool pending;
2779
10d83730
VS		 2780 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2781 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2782 return false;
2783
2784 spin_lock_irqsave(&dev->event_lock, flags);
2785 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2786 spin_unlock_irqrestore(&dev->event_lock, flags);
2787
2788 return pending;
2789}
2790
e6c3a2a6
CW		 2791static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2792{
0f91128d 2793 struct drm_device *dev = crtc->dev;
5bb61643 2794 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2795
2796 if (crtc->fb == NULL)
2797 return;
2798
2c10d571
DV		 2799 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2800
5bb61643
CW		 2801 wait_event(dev_priv->pending_flip_queue,
2802 !intel_crtc_has_pending_flip(crtc));
2803
0f91128d
CW		 2804 mutex_lock(&dev->struct_mutex);
2805 intel_finish_fb(crtc->fb);
2806 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2807}
2808
e615efe4
ED		 2809/* Program iCLKIP clock to the desired frequency */
2810static void lpt_program_iclkip(struct drm_crtc *crtc)
2811{
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2815 u32 temp;
2816
09153000
DV		 2817 mutex_lock(&dev_priv->dpio_lock);
2818
e615efe4
ED		 2819 /* It is necessary to ungate the pixclk gate prior to programming
2820 * the divisors, and gate it back when it is done.
2821 */
2822 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2823
2824 /* Disable SSCCTL */
2825 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2826 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2827 SBI_SSCCTL_DISABLE,
2828 SBI_ICLK);
e615efe4
ED		 2829
2830 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2831 if (crtc->mode.clock == 20000) {
2832 auxdiv = 1;
2833 divsel = 0x41;
2834 phaseinc = 0x20;
2835 } else {
2836 /* The iCLK virtual clock root frequency is in MHz,
2837 * but the crtc->mode.clock in in KHz. To get the divisors,
2838 * it is necessary to divide one by another, so we
2839 * convert the virtual clock precision to KHz here for higher
2840 * precision.
2841 */
2842 u32 iclk_virtual_root_freq = 172800 * 1000;
2843 u32 iclk_pi_range = 64;
2844 u32 desired_divisor, msb_divisor_value, pi_value;
2845
2846 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2847 msb_divisor_value = desired_divisor / iclk_pi_range;
2848 pi_value = desired_divisor % iclk_pi_range;
2849
2850 auxdiv = 0;
2851 divsel = msb_divisor_value - 2;
2852 phaseinc = pi_value;
2853 }
2854
2855 /* This should not happen with any sane values */
2856 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2857 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2858 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2859 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2860
2861 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2862 crtc->mode.clock,
2863 auxdiv,
2864 divsel,
2865 phasedir,
2866 phaseinc);
2867
2868 /* Program SSCDIVINTPHASE6 */
988d6ee8 2869 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2870 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2871 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2872 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2873 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2874 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2875 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2876 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2877
2878 /* Program SSCAUXDIV */
988d6ee8 2879 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2880 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2881 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2882 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2883
2884 /* Enable modulator and associated divider */
988d6ee8 2885 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2886 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2887 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2888
2889 /* Wait for initialization time */
2890 udelay(24);
2891
2892 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2893
2894 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2895}
2896
275f01b2
DV		 2897static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2898 enum pipe pch_transcoder)
2899{
2900 struct drm_device *dev = crtc->base.dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2903
2904 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2905 I915_READ(HTOTAL(cpu_transcoder)));
2906 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2907 I915_READ(HBLANK(cpu_transcoder)));
2908 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2909 I915_READ(HSYNC(cpu_transcoder)));
2910
2911 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2912 I915_READ(VTOTAL(cpu_transcoder)));
2913 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2914 I915_READ(VBLANK(cpu_transcoder)));
2915 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2916 I915_READ(VSYNC(cpu_transcoder)));
2917 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2918 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2919}
2920
f67a559d
JB		 2921/*
2922 * Enable PCH resources required for PCH ports:
2923 * - PCH PLLs
2924 * - FDI training & RX/TX
2925 * - update transcoder timings
2926 * - DP transcoding bits
2927 * - transcoder
2928 */
2929static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2930{
2931 struct drm_device *dev = crtc->dev;
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2934 int pipe = intel_crtc->pipe;
ee7b9f93 2935 u32 reg, temp;
2c07245f 2936
ab9412ba 2937 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2938
cd986abb
DV		 2939 /* Write the TU size bits before fdi link training, so that error
2940 * detection works. */
2941 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2942 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2943
c98e9dcf 2944 /* For PCH output, training FDI link */
674cf967 2945 dev_priv->display.fdi_link_train(crtc);
2c07245f 2946
572deb37
DV		 2947 /* XXX: pch pll's can be enabled any time before we enable the PCH
2948 * transcoder, and we actually should do this to not upset any PCH
2949 * transcoder that already use the clock when we share it.
2950 *
e72f9fbf
DV		 2951 * Note that enable_shared_dpll tries to do the right thing, but
2952 * get_shared_dpll unconditionally resets the pll - we need that to have
2953 * the right LVDS enable sequence. */
2954 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2955
303b81e0 2956 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2957 u32 sel;
4b645f14 2958
c98e9dcf 2959 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2960 temp |= TRANS_DPLL_ENABLE(pipe);
2961 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2962 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2963 temp |= sel;
2964 else
2965 temp &= ~sel;
c98e9dcf 2966 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2967 }
5eddb70b 2968
d9b6cb56
JB		 2969 /* set transcoder timing, panel must allow it */
2970 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2971 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2972
303b81e0 2973 intel_fdi_normal_train(crtc);
5e84e1a4 2974
c98e9dcf
JB		 2975 /* For PCH DP, enable TRANS_DP_CTL */
2976 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2977 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2978 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2979 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2980 reg = TRANS_DP_CTL(pipe);
2981 temp = I915_READ(reg);
2982 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2983 TRANS_DP_SYNC_MASK |
2984 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2985 temp |= (TRANS_DP_OUTPUT_ENABLE |
2986 TRANS_DP_ENH_FRAMING);
9325c9f0 2987 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2988
2989 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2990 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2991 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2992 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2993
2994 switch (intel_trans_dp_port_sel(crtc)) {
2995 case PCH_DP_B:
5eddb70b 2996 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2997 break;
2998 case PCH_DP_C:
5eddb70b 2999 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3000 break;
3001 case PCH_DP_D:
5eddb70b 3002 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3003 break;
3004 default:
e95d41e1 3005 BUG();
32f9d658 3006 }
2c07245f 3007
5eddb70b 3008 I915_WRITE(reg, temp);
6be4a607 3009 }
b52eb4dc 3010
b8a4f404 3011 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3012}
3013
1507e5bd
PZ		 3014static void lpt_pch_enable(struct drm_crtc *crtc)
3015{
3016 struct drm_device *dev = crtc->dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3019 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3020
ab9412ba 3021 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3022
8c52b5e8 3023 lpt_program_iclkip(crtc);
1507e5bd 3024
0540e488 3025 /* Set transcoder timing. */
275f01b2 3026 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3027
937bb610 3028 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3029}
3030
e2b78267 3031static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3032{
e2b78267 3033 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3034
3035 if (pll == NULL)
3036 return;
3037
3038 if (pll->refcount == 0) {
46edb027 3039 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3040 return;
3041 }
3042
f4a091c7
DV		 3043 if (--pll->refcount == 0) {
3044 WARN_ON(pll->on);
3045 WARN_ON(pll->active);
3046 }
3047
a43f6e0f 3048 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3049}
3050
b89a1d39 3051static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3052{
e2b78267
DV		 3053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3054 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3055 enum intel_dpll_id i;
ee7b9f93 3056
ee7b9f93 3057 if (pll) {
46edb027
DV		 3058 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3059 crtc->base.base.id, pll->name);
e2b78267 3060 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3061 }
3062
98b6bd99
DV		 3063 if (HAS_PCH_IBX(dev_priv->dev)) {
3064 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3065 i = crtc->pipe;
e72f9fbf 3066 pll = &dev_priv->shared_dplls[i];
98b6bd99 3067
46edb027
DV		 3068 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3069 crtc->base.base.id, pll->name);
98b6bd99
DV		 3070
3071 goto found;
3072 }
3073
e72f9fbf
DV		 3074 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3075 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3076
3077 /* Only want to check enabled timings first */
3078 if (pll->refcount == 0)
3079 continue;
3080
b89a1d39
DV		 3081 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3082 sizeof(pll->hw_state)) == 0) {
46edb027 3083 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3084 crtc->base.base.id,
46edb027 3085 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3086
3087 goto found;
3088 }
3089 }
3090
3091 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3092 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3093 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3094 if (pll->refcount == 0) {
46edb027
DV		 3095 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3096 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3097 goto found;
3098 }
3099 }
3100
3101 return NULL;
3102
3103found:
a43f6e0f 3104 crtc->config.shared_dpll = i;
46edb027
DV		 3105 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3106 pipe_name(crtc->pipe));
ee7b9f93 3107
cdbd2316 3108 if (pll->active == 0) {
66e985c0
DV		 3109 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3110 sizeof(pll->hw_state));
3111
46edb027 3112 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3113 WARN_ON(pll->on);
e9d6944e 3114 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3115
15bdd4cf 3116 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3117 }
3118 pll->refcount++;
e04c7350 3119
ee7b9f93
JB		 3120 return pll;
3121}
3122
a1520318 3123static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3124{
3125 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3126 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3127 u32 temp;
3128
3129 temp = I915_READ(dslreg);
3130 udelay(500);
3131 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3132 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3133 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3134 }
3135}
3136
b074cec8
JB		 3137static void ironlake_pfit_enable(struct intel_crtc *crtc)
3138{
3139 struct drm_device *dev = crtc->base.dev;
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 int pipe = crtc->pipe;
3142
0ef37f3f 3143 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3144 /* Force use of hard-coded filter coefficients
3145 * as some pre-programmed values are broken,
3146 * e.g. x201.
3147 */
3148 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3149 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3150 PF_PIPE_SEL_IVB(pipe));
3151 else
3152 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3153 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3154 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3155 }
3156}
3157
bb53d4ae
VS		 3158static void intel_enable_planes(struct drm_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_restore(&intel_plane->base);
3167}
3168
3169static void intel_disable_planes(struct drm_crtc *crtc)
3170{
3171 struct drm_device *dev = crtc->dev;
3172 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3173 struct intel_plane *intel_plane;
3174
3175 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3176 if (intel_plane->pipe == pipe)
3177 intel_plane_disable(&intel_plane->base);
3178}
3179
f67a559d
JB		 3180static void ironlake_crtc_enable(struct drm_crtc *crtc)
3181{
3182 struct drm_device *dev = crtc->dev;
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3185 struct intel_encoder *encoder;
f67a559d
JB		 3186 int pipe = intel_crtc->pipe;
3187 int plane = intel_crtc->plane;
f67a559d 3188
08a48469
DV		 3189 WARN_ON(!crtc->enabled);
3190
f67a559d
JB		 3191 if (intel_crtc->active)
3192 return;
3193
3194 intel_crtc->active = true;
8664281b
PZ		 3195
3196 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3197 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3198
f67a559d
JB		 3199 intel_update_watermarks(dev);
3200
952735ee 3201 for_each_encoder_on_crtc(dev, crtc, encoder) {
15bdd4cf
DV		 3202 if (encoder->pre_pll_enable)
3203 encoder->pre_pll_enable(encoder);
952735ee
DV		 3204 if (encoder->pre_enable)
3205 encoder->pre_enable(encoder);
3206 }
f67a559d 3207
5bfe2ac0 3208 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3209 /* Note: FDI PLL enabling _must_ be done before we enable the
3210 * cpu pipes, hence this is separate from all the other fdi/pch
3211 * enabling. */
88cefb6c 3212 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3213 } else {
3214 assert_fdi_tx_disabled(dev_priv, pipe);
3215 assert_fdi_rx_disabled(dev_priv, pipe);
3216 }
f67a559d 3217
b074cec8 3218 ironlake_pfit_enable(intel_crtc);
f67a559d 3219
9c54c0dd
JB		 3220 /*
3221 * On ILK+ LUT must be loaded before the pipe is running but with
3222 * clocks enabled
3223 */
3224 intel_crtc_load_lut(crtc);
3225
5bfe2ac0
DV		 3226 intel_enable_pipe(dev_priv, pipe,
3227 intel_crtc->config.has_pch_encoder);
f67a559d 3228 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3229 intel_enable_planes(crtc);
5c38d48c 3230 intel_crtc_update_cursor(crtc, true);
f67a559d 3231
5bfe2ac0 3232 if (intel_crtc->config.has_pch_encoder)
f67a559d 3233 ironlake_pch_enable(crtc);
c98e9dcf 3234
d1ebd816 3235 mutex_lock(&dev->struct_mutex);
bed4a673 3236 intel_update_fbc(dev);
d1ebd816
BW		 3237 mutex_unlock(&dev->struct_mutex);
3238
fa5c73b1
DV		 3239 for_each_encoder_on_crtc(dev, crtc, encoder)
3240 encoder->enable(encoder);
61b77ddd
DV		 3241
3242 if (HAS_PCH_CPT(dev))
a1520318 3243 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3244
3245 /*
3246 * There seems to be a race in PCH platform hw (at least on some
3247 * outputs) where an enabled pipe still completes any pageflip right
3248 * away (as if the pipe is off) instead of waiting for vblank. As soon
3249 * as the first vblank happend, everything works as expected. Hence just
3250 * wait for one vblank before returning to avoid strange things
3251 * happening.
3252 */
3253 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3254}
3255
42db64ef
PZ		 3256/* IPS only exists on ULT machines and is tied to pipe A. */
3257static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3258{
f5adf94e 3259 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3260}
3261
3262static void hsw_enable_ips(struct intel_crtc *crtc)
3263{
3264 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3265
3266 if (!crtc->config.ips_enabled)
3267 return;
3268
3269 /* We can only enable IPS after we enable a plane and wait for a vblank.
3270 * We guarantee that the plane is enabled by calling intel_enable_ips
3271 * only after intel_enable_plane. And intel_enable_plane already waits
3272 * for a vblank, so all we need to do here is to enable the IPS bit. */
3273 assert_plane_enabled(dev_priv, crtc->plane);
3274 I915_WRITE(IPS_CTL, IPS_ENABLE);
3275}
3276
3277static void hsw_disable_ips(struct intel_crtc *crtc)
3278{
3279 struct drm_device *dev = crtc->base.dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282 if (!crtc->config.ips_enabled)
3283 return;
3284
3285 assert_plane_enabled(dev_priv, crtc->plane);
3286 I915_WRITE(IPS_CTL, 0);
3287
3288 /* We need to wait for a vblank before we can disable the plane. */
3289 intel_wait_for_vblank(dev, crtc->pipe);
3290}
3291
4f771f10
PZ		 3292static void haswell_crtc_enable(struct drm_crtc *crtc)
3293{
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3297 struct intel_encoder *encoder;
3298 int pipe = intel_crtc->pipe;
3299 int plane = intel_crtc->plane;
4f771f10
PZ		 3300
3301 WARN_ON(!crtc->enabled);
3302
3303 if (intel_crtc->active)
3304 return;
3305
3306 intel_crtc->active = true;
8664281b
PZ		 3307
3308 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3309 if (intel_crtc->config.has_pch_encoder)
3310 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3311
4f771f10
PZ		 3312 intel_update_watermarks(dev);
3313
5bfe2ac0 3314 if (intel_crtc->config.has_pch_encoder)
04945641 3315 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3316
3317 for_each_encoder_on_crtc(dev, crtc, encoder)
3318 if (encoder->pre_enable)
3319 encoder->pre_enable(encoder);
3320
1f544388 3321 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3322
b074cec8 3323 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3324
3325 /*
3326 * On ILK+ LUT must be loaded before the pipe is running but with
3327 * clocks enabled
3328 */
3329 intel_crtc_load_lut(crtc);
3330
1f544388 3331 intel_ddi_set_pipe_settings(crtc);
8228c251 3332 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3333
5bfe2ac0
DV		 3334 intel_enable_pipe(dev_priv, pipe,
3335 intel_crtc->config.has_pch_encoder);
4f771f10 3336 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3337 intel_enable_planes(crtc);
5c38d48c 3338 intel_crtc_update_cursor(crtc, true);
4f771f10 3339
42db64ef
PZ		 3340 hsw_enable_ips(intel_crtc);
3341
5bfe2ac0 3342 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3343 lpt_pch_enable(crtc);
4f771f10
PZ		 3344
3345 mutex_lock(&dev->struct_mutex);
3346 intel_update_fbc(dev);
3347 mutex_unlock(&dev->struct_mutex);
3348
4f771f10
PZ		 3349 for_each_encoder_on_crtc(dev, crtc, encoder)
3350 encoder->enable(encoder);
3351
4f771f10
PZ		 3352 /*
3353 * There seems to be a race in PCH platform hw (at least on some
3354 * outputs) where an enabled pipe still completes any pageflip right
3355 * away (as if the pipe is off) instead of waiting for vblank. As soon
3356 * as the first vblank happend, everything works as expected. Hence just
3357 * wait for one vblank before returning to avoid strange things
3358 * happening.
3359 */
3360 intel_wait_for_vblank(dev, intel_crtc->pipe);
3361}
3362
3f8dce3a
DV		 3363static void ironlake_pfit_disable(struct intel_crtc *crtc)
3364{
3365 struct drm_device *dev = crtc->base.dev;
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 int pipe = crtc->pipe;
3368
3369 /* To avoid upsetting the power well on haswell only disable the pfit if
3370 * it's in use. The hw state code will make sure we get this right. */
3371 if (crtc->config.pch_pfit.size) {
3372 I915_WRITE(PF_CTL(pipe), 0);
3373 I915_WRITE(PF_WIN_POS(pipe), 0);
3374 I915_WRITE(PF_WIN_SZ(pipe), 0);
3375 }
3376}
3377
6be4a607
JB		 3378static void ironlake_crtc_disable(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3383 struct intel_encoder *encoder;
6be4a607
JB		 3384 int pipe = intel_crtc->pipe;
3385 int plane = intel_crtc->plane;
5eddb70b 3386 u32 reg, temp;
b52eb4dc 3387
ef9c3aee 3388
f7abfe8b
CW		 3389 if (!intel_crtc->active)
3390 return;
3391
ea9d758d
DV		 3392 for_each_encoder_on_crtc(dev, crtc, encoder)
3393 encoder->disable(encoder);
3394
e6c3a2a6 3395 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3396 drm_vblank_off(dev, pipe);
913d8d11 3397
973d04f9
CW		 3398 if (dev_priv->cfb_plane == plane)
3399 intel_disable_fbc(dev);
2c07245f 3400
0d5b8c61 3401 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3402 intel_disable_planes(crtc);
0d5b8c61
VS		 3403 intel_disable_plane(dev_priv, plane, pipe);
3404
d925c59a
DV		 3405 if (intel_crtc->config.has_pch_encoder)
3406 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3407
b24e7179 3408 intel_disable_pipe(dev_priv, pipe);
32f9d658 3409
3f8dce3a 3410 ironlake_pfit_disable(intel_crtc);
2c07245f 3411
bf49ec8c
DV		 3412 for_each_encoder_on_crtc(dev, crtc, encoder)
3413 if (encoder->post_disable)
3414 encoder->post_disable(encoder);
2c07245f 3415
d925c59a
DV		 3416 if (intel_crtc->config.has_pch_encoder) {
3417 ironlake_fdi_disable(crtc);
913d8d11 3418
d925c59a
DV		 3419 ironlake_disable_pch_transcoder(dev_priv, pipe);
3420 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3421
d925c59a
DV		 3422 if (HAS_PCH_CPT(dev)) {
3423 /* disable TRANS_DP_CTL */
3424 reg = TRANS_DP_CTL(pipe);
3425 temp = I915_READ(reg);
3426 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3427 TRANS_DP_PORT_SEL_MASK);
3428 temp |= TRANS_DP_PORT_SEL_NONE;
3429 I915_WRITE(reg, temp);
3430
3431 /* disable DPLL_SEL */
3432 temp = I915_READ(PCH_DPLL_SEL);
11887397 3433 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3434 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3435 }
e3421a18 3436
d925c59a 3437 /* disable PCH DPLL */
e72f9fbf 3438 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3439
d925c59a
DV		 3440 ironlake_fdi_pll_disable(intel_crtc);
3441 }
6b383a7f 3442
f7abfe8b 3443 intel_crtc->active = false;
6b383a7f 3444 intel_update_watermarks(dev);
d1ebd816
BW		 3445
3446 mutex_lock(&dev->struct_mutex);
6b383a7f 3447 intel_update_fbc(dev);
d1ebd816 3448 mutex_unlock(&dev->struct_mutex);
6be4a607 3449}
1b3c7a47 3450
4f771f10 3451static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3452{
4f771f10
PZ		 3453 struct drm_device *dev = crtc->dev;
3454 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3456 struct intel_encoder *encoder;
3457 int pipe = intel_crtc->pipe;
3458 int plane = intel_crtc->plane;
3b117c8f 3459 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3460
4f771f10
PZ		 3461 if (!intel_crtc->active)
3462 return;
3463
3464 for_each_encoder_on_crtc(dev, crtc, encoder)
3465 encoder->disable(encoder);
3466
3467 intel_crtc_wait_for_pending_flips(crtc);
3468 drm_vblank_off(dev, pipe);
4f771f10 3469
891348b2 3470 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3471 if (dev_priv->cfb_plane == plane)
3472 intel_disable_fbc(dev);
3473
42db64ef
PZ		 3474 hsw_disable_ips(intel_crtc);
3475
0d5b8c61 3476 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3477 intel_disable_planes(crtc);
891348b2
RV		 3478 intel_disable_plane(dev_priv, plane, pipe);
3479
8664281b
PZ		 3480 if (intel_crtc->config.has_pch_encoder)
3481 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3482 intel_disable_pipe(dev_priv, pipe);
3483
ad80a810 3484 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3485
3f8dce3a 3486 ironlake_pfit_disable(intel_crtc);
4f771f10 3487
1f544388 3488 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3489
3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 if (encoder->post_disable)
3492 encoder->post_disable(encoder);
3493
88adfff1 3494 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3495 lpt_disable_pch_transcoder(dev_priv);
8664281b 3496 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3497 intel_ddi_fdi_disable(crtc);
83616634 3498 }
4f771f10
PZ		 3499
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3502
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3506}
3507
ee7b9f93
JB		 3508static void ironlake_crtc_off(struct drm_crtc *crtc)
3509{
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3511 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3512}
3513
6441ab5f
PZ		 3514static void haswell_crtc_off(struct drm_crtc *crtc)
3515{
3516 intel_ddi_put_crtc_pll(crtc);
3517}
3518
02e792fb
DV		 3519static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520{
02e792fb 3521 if (!enable && intel_crtc->overlay) {
23f09ce3 3522 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3523 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3524
23f09ce3 3525 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3526 dev_priv->mm.interruptible = false;
3527 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528 dev_priv->mm.interruptible = true;
23f09ce3 3529 mutex_unlock(&dev->struct_mutex);
02e792fb 3530 }
02e792fb 3531
5dcdbcb0
CW		 3532 /* Let userspace switch the overlay on again. In most cases userspace
3533 * has to recompute where to put it anyway.
3534 */
02e792fb
DV		 3535}
3536
61bc95c1
EE		 3537/**
3538 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3539 * cursor plane briefly if not already running after enabling the display
3540 * plane.
3541 * This workaround avoids occasional blank screens when self refresh is
3542 * enabled.
3543 */
3544static void
3545g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3546{
3547 u32 cntl = I915_READ(CURCNTR(pipe));
3548
3549 if ((cntl & CURSOR_MODE) == 0) {
3550 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3551
3552 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3553 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3554 intel_wait_for_vblank(dev_priv->dev, pipe);
3555 I915_WRITE(CURCNTR(pipe), cntl);
3556 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3557 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3558 }
3559}
3560
2dd24552
JB		 3561static void i9xx_pfit_enable(struct intel_crtc *crtc)
3562{
3563 struct drm_device *dev = crtc->base.dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_crtc_config *pipe_config = &crtc->config;
3566
328d8e82 3567 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3568 return;
3569
2dd24552 3570 /*
c0b03411
DV		 3571 * The panel fitter should only be adjusted whilst the pipe is disabled,
3572 * according to register description and PRM.
2dd24552 3573 */
c0b03411
DV		 3574 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3575 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3576
b074cec8
JB		 3577 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3578 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3579
3580 /* Border color in case we don't scale up to the full screen. Black by
3581 * default, change to something else for debugging. */
3582 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3583}
3584
89b667f8
JB		 3585static void valleyview_crtc_enable(struct drm_crtc *crtc)
3586{
3587 struct drm_device *dev = crtc->dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590 struct intel_encoder *encoder;
3591 int pipe = intel_crtc->pipe;
3592 int plane = intel_crtc->plane;
3593
3594 WARN_ON(!crtc->enabled);
3595
3596 if (intel_crtc->active)
3597 return;
3598
3599 intel_crtc->active = true;
3600 intel_update_watermarks(dev);
3601
3602 mutex_lock(&dev_priv->dpio_lock);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_pll_enable)
3606 encoder->pre_pll_enable(encoder);
3607
87442f73 3608 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3609
3610 for_each_encoder_on_crtc(dev, crtc, encoder)
3611 if (encoder->pre_enable)
3612 encoder->pre_enable(encoder);
3613
3614 /* VLV wants encoder enabling _before_ the pipe is up. */
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 encoder->enable(encoder);
3617
2dd24552
JB		 3618 i9xx_pfit_enable(intel_crtc);
3619
63cbb074
VS		 3620 intel_crtc_load_lut(crtc);
3621
89b667f8
JB		 3622 intel_enable_pipe(dev_priv, pipe, false);
3623 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3624 intel_enable_planes(crtc);
5c38d48c 3625 intel_crtc_update_cursor(crtc, true);
89b667f8 3626
89b667f8
JB		 3627 intel_update_fbc(dev);
3628
89b667f8
JB		 3629 mutex_unlock(&dev_priv->dpio_lock);
3630}
3631
0b8765c6 3632static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3633{
3634 struct drm_device *dev = crtc->dev;
79e53945
JB		 3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3637 struct intel_encoder *encoder;
79e53945 3638 int pipe = intel_crtc->pipe;
80824003 3639 int plane = intel_crtc->plane;
79e53945 3640
08a48469
DV		 3641 WARN_ON(!crtc->enabled);
3642
f7abfe8b
CW		 3643 if (intel_crtc->active)
3644 return;
3645
3646 intel_crtc->active = true;
6b383a7f
CW		 3647 intel_update_watermarks(dev);
3648
87442f73 3649 i9xx_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3650
3651 for_each_encoder_on_crtc(dev, crtc, encoder)
3652 if (encoder->pre_enable)
3653 encoder->pre_enable(encoder);
3654
2dd24552
JB		 3655 i9xx_pfit_enable(intel_crtc);
3656
63cbb074
VS		 3657 intel_crtc_load_lut(crtc);
3658
040484af 3659 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3660 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3661 intel_enable_planes(crtc);
22e407d7 3662 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3663 if (IS_G4X(dev))
3664 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3665 intel_crtc_update_cursor(crtc, true);
79e53945 3666
0b8765c6
JB		 3667 /* Give the overlay scaler a chance to enable if it's on this pipe */
3668 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3669
f440eb13 3670 intel_update_fbc(dev);
ef9c3aee 3671
fa5c73b1
DV		 3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 encoder->enable(encoder);
0b8765c6 3674}
79e53945 3675
87476d63
DV		 3676static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677{
3678 struct drm_device *dev = crtc->base.dev;
3679 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3680
328d8e82
DV		 3681 if (!crtc->config.gmch_pfit.control)
3682 return;
87476d63 3683
328d8e82 3684 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3685
328d8e82
DV		 3686 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687 I915_READ(PFIT_CONTROL));
3688 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3689}
3690
0b8765c6
JB		 3691static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692{
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3696 struct intel_encoder *encoder;
0b8765c6
JB		 3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
ef9c3aee 3699
f7abfe8b
CW		 3700 if (!intel_crtc->active)
3701 return;
3702
ea9d758d
DV		 3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 encoder->disable(encoder);
3705
0b8765c6 3706 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3707 intel_crtc_wait_for_pending_flips(crtc);
3708 drm_vblank_off(dev, pipe);
0b8765c6 3709
973d04f9
CW		 3710 if (dev_priv->cfb_plane == plane)
3711 intel_disable_fbc(dev);
79e53945 3712
0d5b8c61
VS		 3713 intel_crtc_dpms_overlay(intel_crtc, false);
3714 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3715 intel_disable_planes(crtc);
b24e7179 3716 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3717
b24e7179 3718 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3719
87476d63 3720 i9xx_pfit_disable(intel_crtc);
24a1f16d 3721
89b667f8
JB		 3722 for_each_encoder_on_crtc(dev, crtc, encoder)
3723 if (encoder->post_disable)
3724 encoder->post_disable(encoder);
3725
63d7bbe9 3726 intel_disable_pll(dev_priv, pipe);
0b8765c6 3727
f7abfe8b 3728 intel_crtc->active = false;
6b383a7f
CW		 3729 intel_update_fbc(dev);
3730 intel_update_watermarks(dev);
0b8765c6
JB		 3731}
3732
ee7b9f93
JB		 3733static void i9xx_crtc_off(struct drm_crtc *crtc)
3734{
3735}
3736
976f8a20
DV		 3737static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3738 bool enabled)
2c07245f
ZW		 3739{
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_master_private *master_priv;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
79e53945
JB		 3744
3745 if (!dev->primary->master)
3746 return;
3747
3748 master_priv = dev->primary->master->driver_priv;
3749 if (!master_priv->sarea_priv)
3750 return;
3751
79e53945
JB		 3752 switch (pipe) {
3753 case 0:
3754 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3755 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3756 break;
3757 case 1:
3758 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3759 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3760 break;
3761 default:
9db4a9c7 3762 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3763 break;
3764 }
79e53945
JB		 3765}
3766
976f8a20
DV		 3767/**
3768 * Sets the power management mode of the pipe and plane.
3769 */
3770void intel_crtc_update_dpms(struct drm_crtc *crtc)
3771{
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 struct intel_encoder *intel_encoder;
3775 bool enable = false;
3776
3777 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3778 enable |= intel_encoder->connectors_active;
3779
3780 if (enable)
3781 dev_priv->display.crtc_enable(crtc);
3782 else
3783 dev_priv->display.crtc_disable(crtc);
3784
3785 intel_crtc_update_sarea(crtc, enable);
3786}
3787
cdd59983
CW		 3788static void intel_crtc_disable(struct drm_crtc *crtc)
3789{
cdd59983 3790 struct drm_device *dev = crtc->dev;
976f8a20 3791 struct drm_connector *connector;
ee7b9f93 3792 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3794
976f8a20
DV		 3795 /* crtc should still be enabled when we disable it. */
3796 WARN_ON(!crtc->enabled);
3797
3798 dev_priv->display.crtc_disable(crtc);
c77bf565 3799 intel_crtc->eld_vld = false;
976f8a20 3800 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3801 dev_priv->display.off(crtc);
3802
931872fc
CW		 3803 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3804 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3805
3806 if (crtc->fb) {
3807 mutex_lock(&dev->struct_mutex);
1690e1eb 3808 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3809 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3810 crtc->fb = NULL;
3811 }
3812
3813 /* Update computed state. */
3814 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3815 if (!connector->encoder || !connector->encoder->crtc)
3816 continue;
3817
3818 if (connector->encoder->crtc != crtc)
3819 continue;
3820
3821 connector->dpms = DRM_MODE_DPMS_OFF;
3822 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3823 }
3824}
3825
a261b246 3826void intel_modeset_disable(struct drm_device *dev)
79e53945 3827{
a261b246
DV		 3828 struct drm_crtc *crtc;
3829
3830 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3831 if (crtc->enabled)
3832 intel_crtc_disable(crtc);
3833 }
79e53945
JB		 3834}
3835
ea5b213a 3836void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3837{
4ef69c7a 3838 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3839
ea5b213a
CW		 3840 drm_encoder_cleanup(encoder);
3841 kfree(intel_encoder);
7e7d76c3
JB		 3842}
3843
5ab432ef
DV		 3844/* Simple dpms helper for encodres with just one connector, no cloning and only
3845 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3846 * state of the entire output pipe. */
3847void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3848{
5ab432ef
DV		 3849 if (mode == DRM_MODE_DPMS_ON) {
3850 encoder->connectors_active = true;
3851
b2cabb0e 3852 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3853 } else {
3854 encoder->connectors_active = false;
3855
b2cabb0e 3856 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3857 }
79e53945
JB		 3858}
3859
0a91ca29
DV		 3860/* Cross check the actual hw state with our own modeset state tracking (and it's
3861 * internal consistency). */
b980514c 3862static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3863{
0a91ca29
DV		 3864 if (connector->get_hw_state(connector)) {
3865 struct intel_encoder *encoder = connector->encoder;
3866 struct drm_crtc *crtc;
3867 bool encoder_enabled;
3868 enum pipe pipe;
3869
3870 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3871 connector->base.base.id,
3872 drm_get_connector_name(&connector->base));
3873
3874 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3875 "wrong connector dpms state\n");
3876 WARN(connector->base.encoder != &encoder->base,
3877 "active connector not linked to encoder\n");
3878 WARN(!encoder->connectors_active,
3879 "encoder->connectors_active not set\n");
3880
3881 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3882 WARN(!encoder_enabled, "encoder not enabled\n");
3883 if (WARN_ON(!encoder->base.crtc))
3884 return;
3885
3886 crtc = encoder->base.crtc;
3887
3888 WARN(!crtc->enabled, "crtc not enabled\n");
3889 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3890 WARN(pipe != to_intel_crtc(crtc)->pipe,
3891 "encoder active on the wrong pipe\n");
3892 }
79e53945
JB		 3893}
3894
5ab432ef
DV		 3895/* Even simpler default implementation, if there's really no special case to
3896 * consider. */
3897void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3898{
5ab432ef 3899 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3900
5ab432ef
DV		 3901 /* All the simple cases only support two dpms states. */
3902 if (mode != DRM_MODE_DPMS_ON)
3903 mode = DRM_MODE_DPMS_OFF;
d4270e57 3904
5ab432ef
DV		 3905 if (mode == connector->dpms)
3906 return;
3907
3908 connector->dpms = mode;
3909
3910 /* Only need to change hw state when actually enabled */
3911 if (encoder->base.crtc)
3912 intel_encoder_dpms(encoder, mode);
3913 else
8af6cf88 3914 WARN_ON(encoder->connectors_active != false);
0a91ca29 3915
b980514c 3916 intel_modeset_check_state(connector->dev);
79e53945
JB		 3917}
3918
f0947c37
DV		 3919/* Simple connector->get_hw_state implementation for encoders that support only
3920 * one connector and no cloning and hence the encoder state determines the state
3921 * of the connector. */
3922bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3923{
24929352 3924 enum pipe pipe = 0;
f0947c37 3925 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3926
f0947c37 3927 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3928}
3929
1857e1da
DV		 3930static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3931 struct intel_crtc_config *pipe_config)
3932{
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 struct intel_crtc *pipe_B_crtc =
3935 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3936
3937 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3938 pipe_name(pipe), pipe_config->fdi_lanes);
3939 if (pipe_config->fdi_lanes > 4) {
3940 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3941 pipe_name(pipe), pipe_config->fdi_lanes);
3942 return false;
3943 }
3944
3945 if (IS_HASWELL(dev)) {
3946 if (pipe_config->fdi_lanes > 2) {
3947 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3948 pipe_config->fdi_lanes);
3949 return false;
3950 } else {
3951 return true;
3952 }
3953 }
3954
3955 if (INTEL_INFO(dev)->num_pipes == 2)
3956 return true;
3957
3958 /* Ivybridge 3 pipe is really complicated */
3959 switch (pipe) {
3960 case PIPE_A:
3961 return true;
3962 case PIPE_B:
3963 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3964 pipe_config->fdi_lanes > 2) {
3965 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3966 pipe_name(pipe), pipe_config->fdi_lanes);
3967 return false;
3968 }
3969 return true;
3970 case PIPE_C:
1e833f40 3971 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3972 pipe_B_crtc->config.fdi_lanes <= 2) {
3973 if (pipe_config->fdi_lanes > 2) {
3974 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3975 pipe_name(pipe), pipe_config->fdi_lanes);
3976 return false;
3977 }
3978 } else {
3979 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3980 return false;
3981 }
3982 return true;
3983 default:
3984 BUG();
3985 }
3986}
3987
e29c22c0
DV		 3988#define RETRY 1
3989static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3990 struct intel_crtc_config *pipe_config)
877d48d5 3991{
1857e1da 3992 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3993 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3994 int lane, link_bw, fdi_dotclock;
e29c22c0 3995 bool setup_ok, needs_recompute = false;
877d48d5 3996
e29c22c0 3997retry:
877d48d5
DV		 3998 /* FDI is a binary signal running at ~2.7GHz, encoding
3999 * each output octet as 10 bits. The actual frequency
4000 * is stored as a divider into a 100MHz clock, and the
4001 * mode pixel clock is stored in units of 1KHz.
4002 * Hence the bw of each lane in terms of the mode signal
4003 * is:
4004 */
4005 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4006
ff9a6750 4007 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4008 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4009
2bd89a07 4010 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4011 pipe_config->pipe_bpp);
4012
4013 pipe_config->fdi_lanes = lane;
4014
2bd89a07 4015 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4016 link_bw, &pipe_config->fdi_m_n);
1857e1da 4017
e29c22c0
DV		 4018 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4019 intel_crtc->pipe, pipe_config);
4020 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4021 pipe_config->pipe_bpp -= 2*3;
4022 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4023 pipe_config->pipe_bpp);
4024 needs_recompute = true;
4025 pipe_config->bw_constrained = true;
4026
4027 goto retry;
4028 }
4029
4030 if (needs_recompute)
4031 return RETRY;
4032
4033 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4034}
4035
42db64ef
PZ		 4036static void hsw_compute_ips_config(struct intel_crtc *crtc,
4037 struct intel_crtc_config *pipe_config)
4038{
3c4ca58c
PZ		 4039 pipe_config->ips_enabled = i915_enable_ips &&
4040 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4041 pipe_config->pipe_bpp == 24;
4042}
4043
a43f6e0f 4044static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4045 struct intel_crtc_config *pipe_config)
79e53945 4046{
a43f6e0f 4047 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4049
bad720ff 4050 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4051 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4052 if (pipe_config->requested_mode.clock * 3
4053 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4054 return -EINVAL;
2c07245f 4055 }
89749350 4056
f9bef081
DV		 4057 /* All interlaced capable intel hw wants timings in frames. Note though
4058 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059 * timings, so we need to be careful not to clobber these.*/
7ae89233 4060 if (!pipe_config->timings_set)
f9bef081 4061 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4062
8693a824
DL		 4063 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4064 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4065 */
4066 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4068 return -EINVAL;
44f46b42 4069
bd080ee5 4070 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4071 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4072 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4073 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074 * for lvds. */
4075 pipe_config->pipe_bpp = 8*3;
4076 }
4077
f5adf94e 4078 if (HAS_IPS(dev))
a43f6e0f
DV		 4079 hsw_compute_ips_config(crtc, pipe_config);
4080
4081 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4082 * clock survives for now. */
4083 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4084 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4085
877d48d5 4086 if (pipe_config->has_pch_encoder)
a43f6e0f 4087 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4088
e29c22c0 4089 return 0;
79e53945
JB		 4090}
4091
25eb05fc
JB		 4092static int valleyview_get_display_clock_speed(struct drm_device *dev)
4093{
4094 return 400000; /* FIXME */
4095}
4096
e70236a8
JB		 4097static int i945_get_display_clock_speed(struct drm_device *dev)
4098{
4099 return 400000;
4100}
79e53945 4101
e70236a8 4102static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4103{
e70236a8
JB		 4104 return 333000;
4105}
79e53945 4106
e70236a8
JB		 4107static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4108{
4109 return 200000;
4110}
79e53945 4111
e70236a8
JB		 4112static int i915gm_get_display_clock_speed(struct drm_device *dev)
4113{
4114 u16 gcfgc = 0;
79e53945 4115
e70236a8
JB		 4116 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4117
4118 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4119 return 133000;
4120 else {
4121 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4122 case GC_DISPLAY_CLOCK_333_MHZ:
4123 return 333000;
4124 default:
4125 case GC_DISPLAY_CLOCK_190_200_MHZ:
4126 return 190000;
79e53945 4127 }
e70236a8
JB		 4128 }
4129}
4130
4131static int i865_get_display_clock_speed(struct drm_device *dev)
4132{
4133 return 266000;
4134}
4135
4136static int i855_get_display_clock_speed(struct drm_device *dev)
4137{
4138 u16 hpllcc = 0;
4139 /* Assume that the hardware is in the high speed state. This
4140 * should be the default.
4141 */
4142 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4143 case GC_CLOCK_133_200:
4144 case GC_CLOCK_100_200:
4145 return 200000;
4146 case GC_CLOCK_166_250:
4147 return 250000;
4148 case GC_CLOCK_100_133:
79e53945 4149 return 133000;
e70236a8 4150 }
79e53945 4151
e70236a8
JB		 4152 /* Shouldn't happen */
4153 return 0;
4154}
79e53945 4155
e70236a8
JB		 4156static int i830_get_display_clock_speed(struct drm_device *dev)
4157{
4158 return 133000;
79e53945
JB		 4159}
4160
2c07245f 4161static void
a65851af 4162intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4163{
a65851af
VS		 4164 while (*num > DATA_LINK_M_N_MASK ||
4165 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4166 *num >>= 1;
4167 *den >>= 1;
4168 }
4169}
4170
a65851af
VS		 4171static void compute_m_n(unsigned int m, unsigned int n,
4172 uint32_t *ret_m, uint32_t *ret_n)
4173{
4174 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4175 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4176 intel_reduce_m_n_ratio(ret_m, ret_n);
4177}
4178
e69d0bc1
DV		 4179void
4180intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4181 int pixel_clock, int link_clock,
4182 struct intel_link_m_n *m_n)
2c07245f 4183{
e69d0bc1 4184 m_n->tu = 64;
a65851af
VS		 4185
4186 compute_m_n(bits_per_pixel * pixel_clock,
4187 link_clock * nlanes * 8,
4188 &m_n->gmch_m, &m_n->gmch_n);
4189
4190 compute_m_n(pixel_clock, link_clock,
4191 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4192}
4193
a7615030
CW		 4194static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4195{
72bbe58c
KP		 4196 if (i915_panel_use_ssc >= 0)
4197 return i915_panel_use_ssc != 0;
41aa3448 4198 return dev_priv->vbt.lvds_use_ssc
435793df 4199 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4200}
4201
a0c4da24
JB		 4202static int vlv_get_refclk(struct drm_crtc *crtc)
4203{
4204 struct drm_device *dev = crtc->dev;
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 int refclk = 27000; /* for DP & HDMI */
4207
4208 return 100000; /* only one validated so far */
4209
4210 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4213 if (intel_panel_use_ssc(dev_priv))
4214 refclk = 100000;
4215 else
4216 refclk = 96000;
4217 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4218 refclk = 100000;
4219 }
4220
4221 return refclk;
4222}
4223
c65d77d8
JB		 4224static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 int refclk;
4229
a0c4da24
JB		 4230 if (IS_VALLEYVIEW(dev)) {
4231 refclk = vlv_get_refclk(crtc);
4232 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4233 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4234 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4235 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4236 refclk / 1000);
4237 } else if (!IS_GEN2(dev)) {
4238 refclk = 96000;
4239 } else {
4240 refclk = 48000;
4241 }
4242
4243 return refclk;
4244}
4245
7429e9d4 4246static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4247{
7df00d7a 4248 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4249}
f47709a9 4250
7429e9d4
DV		 4251static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4252{
4253 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4254}
4255
f47709a9 4256static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4257 intel_clock_t *reduced_clock)
4258{
f47709a9 4259 struct drm_device *dev = crtc->base.dev;
a7516a05 4260 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4261 int pipe = crtc->pipe;
a7516a05
JB		 4262 u32 fp, fp2 = 0;
4263
4264 if (IS_PINEVIEW(dev)) {
7429e9d4 4265 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4266 if (reduced_clock)
7429e9d4 4267 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4268 } else {
7429e9d4 4269 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4270 if (reduced_clock)
7429e9d4 4271 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4272 }
4273
4274 I915_WRITE(FP0(pipe), fp);
4275
f47709a9
DV		 4276 crtc->lowfreq_avail = false;
4277 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4278 reduced_clock && i915_powersave) {
4279 I915_WRITE(FP1(pipe), fp2);
f47709a9 4280 crtc->lowfreq_avail = true;
a7516a05
JB		 4281 } else {
4282 I915_WRITE(FP1(pipe), fp);
4283 }
4284}
4285
89b667f8
JB		 4286static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4287{
4288 u32 reg_val;
4289
4290 /*
4291 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4292 * and set it to a reasonable value instead.
4293 */
ae99258f 4294 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4295 reg_val &= 0xffffff00;
4296 reg_val |= 0x00000030;
ae99258f 4297 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4298
ae99258f 4299 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4300 reg_val &= 0x8cffffff;
4301 reg_val = 0x8c000000;
ae99258f 4302 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4303
ae99258f 4304 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4305 reg_val &= 0xffffff00;
ae99258f 4306 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4307
ae99258f 4308 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4309 reg_val &= 0x00ffffff;
4310 reg_val |= 0xb0000000;
ae99258f 4311 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4312}
4313
b551842d
DV		 4314static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4315 struct intel_link_m_n *m_n)
4316{
4317 struct drm_device *dev = crtc->base.dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 int pipe = crtc->pipe;
4320
e3b95f1e
DV		 4321 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4322 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4323 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4324 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4325}
4326
4327static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4328 struct intel_link_m_n *m_n)
4329{
4330 struct drm_device *dev = crtc->base.dev;
4331 struct drm_i915_private *dev_priv = dev->dev_private;
4332 int pipe = crtc->pipe;
4333 enum transcoder transcoder = crtc->config.cpu_transcoder;
4334
4335 if (INTEL_INFO(dev)->gen >= 5) {
4336 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4338 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4339 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4340 } else {
e3b95f1e
DV		 4341 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4342 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4343 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4344 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4345 }
4346}
4347
03afc4a2
DV		 4348static void intel_dp_set_m_n(struct intel_crtc *crtc)
4349{
4350 if (crtc->config.has_pch_encoder)
4351 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4352 else
4353 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4354}
4355
f47709a9 4356static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4357{
f47709a9 4358 struct drm_device *dev = crtc->base.dev;
a0c4da24 4359 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4360 struct intel_encoder *encoder;
f47709a9 4361 int pipe = crtc->pipe;
89b667f8 4362 u32 dpll, mdiv;
a0c4da24 4363 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4364 bool is_hdmi;
198a037f 4365 u32 coreclk, reg_val, dpll_md;
a0c4da24 4366
09153000
DV		 4367 mutex_lock(&dev_priv->dpio_lock);
4368
89b667f8 4369 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4370
f47709a9
DV		 4371 bestn = crtc->config.dpll.n;
4372 bestm1 = crtc->config.dpll.m1;
4373 bestm2 = crtc->config.dpll.m2;
4374 bestp1 = crtc->config.dpll.p1;
4375 bestp2 = crtc->config.dpll.p2;
a0c4da24 4376
89b667f8
JB		 4377 /* See eDP HDMI DPIO driver vbios notes doc */
4378
4379 /* PLL B needs special handling */
4380 if (pipe)
4381 vlv_pllb_recal_opamp(dev_priv);
4382
4383 /* Set up Tx target for periodic Rcomp update */
ae99258f 4384 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4385
4386 /* Disable target IRef on PLL */
ae99258f 4387 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4388 reg_val &= 0x00ffffff;
ae99258f 4389 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4390
4391 /* Disable fast lock */
ae99258f 4392 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4393
4394 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4395 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4396 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4397 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4398 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4399
4400 /*
4401 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4402 * but we don't support that).
4403 * Note: don't use the DAC post divider as it seems unstable.
4404 */
4405 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4406 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4407
a0c4da24 4408 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4409 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4410
89b667f8 4411 /* Set HBR and RBR LPF coefficients */
ff9a6750 4412 if (crtc->config.port_clock == 162000 ||
99750bd4 4413 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4414 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4415 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4416 0x005f0021);
4417 else
4abb2c39 4418 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4419 0x00d0000f);
4420
4421 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4422 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4423 /* Use SSC source */
4424 if (!pipe)
ae99258f 4425 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4426 0x0df40000);
4427 else
ae99258f 4428 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4429 0x0df70000);
4430 } else { /* HDMI or VGA */
4431 /* Use bend source */
4432 if (!pipe)
ae99258f 4433 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4434 0x0df70000);
4435 else
ae99258f 4436 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4437 0x0df40000);
4438 }
a0c4da24 4439
ae99258f 4440 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4441 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4442 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4443 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4444 coreclk |= 0x01000000;
ae99258f 4445 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4446
ae99258f 4447 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4448
89b667f8
JB		 4449 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4450 if (encoder->pre_pll_enable)
4451 encoder->pre_pll_enable(encoder);
a0c4da24 4452
89b667f8
JB		 4453 /* Enable DPIO clock input */
4454 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4455 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4456 if (pipe)
4457 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4458
4459 dpll |= DPLL_VCO_ENABLE;
4460 I915_WRITE(DPLL(pipe), dpll);
4461 POSTING_READ(DPLL(pipe));
2a8f64ca 4462 udelay(150);
a0c4da24 4463
a0c4da24
JB		 4464 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4465 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4466
ef1b460d
DV		 4467 dpll_md = (crtc->config.pixel_multiplier - 1)
4468 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4469 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4470 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4471
89b667f8
JB		 4472 if (crtc->config.has_dp_encoder)
4473 intel_dp_set_m_n(crtc);
09153000
DV		 4474
4475 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4476}
4477
f47709a9
DV		 4478static void i9xx_update_pll(struct intel_crtc *crtc,
4479 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4480 int num_connectors)
4481{
f47709a9 4482 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4483 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4484 struct intel_encoder *encoder;
f47709a9 4485 int pipe = crtc->pipe;
eb1cbe48
DV		 4486 u32 dpll;
4487 bool is_sdvo;
f47709a9 4488 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4489
f47709a9 4490 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4491
f47709a9
DV		 4492 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4493 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4494
4495 dpll = DPLL_VGA_MODE_DIS;
4496
f47709a9 4497 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4498 dpll |= DPLLB_MODE_LVDS;
4499 else
4500 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4501
ef1b460d 4502 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4503 dpll |= (crtc->config.pixel_multiplier - 1)
4504 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4505 }
198a037f
DV		 4506
4507 if (is_sdvo)
4508 dpll |= DPLL_DVO_HIGH_SPEED;
4509
f47709a9 4510 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4511 dpll |= DPLL_DVO_HIGH_SPEED;
4512
4513 /* compute bitmask from p1 value */
4514 if (IS_PINEVIEW(dev))
4515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4516 else {
4517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4518 if (IS_G4X(dev) && reduced_clock)
4519 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4520 }
4521 switch (clock->p2) {
4522 case 5:
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4524 break;
4525 case 7:
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4527 break;
4528 case 10:
4529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4530 break;
4531 case 14:
4532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4533 break;
4534 }
4535 if (INTEL_INFO(dev)->gen >= 4)
4536 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4537
09ede541 4538 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4539 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4540 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4541 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4542 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4543 else
4544 dpll |= PLL_REF_INPUT_DREFCLK;
4545
4546 dpll |= DPLL_VCO_ENABLE;
4547 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4548 POSTING_READ(DPLL(pipe));
4549 udelay(150);
4550
f47709a9 4551 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4552 if (encoder->pre_pll_enable)
4553 encoder->pre_pll_enable(encoder);
eb1cbe48 4554
f47709a9
DV		 4555 if (crtc->config.has_dp_encoder)
4556 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4557
4558 I915_WRITE(DPLL(pipe), dpll);
4559
4560 /* Wait for the clocks to stabilize. */
4561 POSTING_READ(DPLL(pipe));
4562 udelay(150);
4563
4564 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4565 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4566 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4567 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4568 } else {
4569 /* The pixel multiplier can only be updated once the
4570 * DPLL is enabled and the clocks are stable.
4571 *
4572 * So write it again.
4573 */
4574 I915_WRITE(DPLL(pipe), dpll);
4575 }
4576}
4577
f47709a9 4578static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4579 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4580 int num_connectors)
4581{
f47709a9 4582 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4583 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4584 struct intel_encoder *encoder;
f47709a9 4585 int pipe = crtc->pipe;
eb1cbe48 4586 u32 dpll;
f47709a9 4587 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4588
f47709a9 4589 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4590
eb1cbe48
DV		 4591 dpll = DPLL_VGA_MODE_DIS;
4592
f47709a9 4593 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4595 } else {
4596 if (clock->p1 == 2)
4597 dpll |= PLL_P1_DIVIDE_BY_TWO;
4598 else
4599 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4600 if (clock->p2 == 4)
4601 dpll |= PLL_P2_DIVIDE_BY_4;
4602 }
4603
f47709a9 4604 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4605 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4607 else
4608 dpll |= PLL_REF_INPUT_DREFCLK;
4609
4610 dpll |= DPLL_VCO_ENABLE;
4611 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4612 POSTING_READ(DPLL(pipe));
4613 udelay(150);
4614
f47709a9 4615 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4616 if (encoder->pre_pll_enable)
4617 encoder->pre_pll_enable(encoder);
eb1cbe48 4618
5b5896e4
DV		 4619 I915_WRITE(DPLL(pipe), dpll);
4620
4621 /* Wait for the clocks to stabilize. */
4622 POSTING_READ(DPLL(pipe));
4623 udelay(150);
4624
eb1cbe48
DV		 4625 /* The pixel multiplier can only be updated once the
4626 * DPLL is enabled and the clocks are stable.
4627 *
4628 * So write it again.
4629 */
4630 I915_WRITE(DPLL(pipe), dpll);
4631}
4632
8a654f3b 4633static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4634{
4635 struct drm_device *dev = intel_crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4638 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4639 struct drm_display_mode *adjusted_mode =
4640 &intel_crtc->config.adjusted_mode;
4641 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4642 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4643
4644 /* We need to be careful not to changed the adjusted mode, for otherwise
4645 * the hw state checker will get angry at the mismatch. */
4646 crtc_vtotal = adjusted_mode->crtc_vtotal;
4647 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4648
4649 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4650 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4651 crtc_vtotal -= 1;
4652 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4653 vsyncshift = adjusted_mode->crtc_hsync_start
4654 - adjusted_mode->crtc_htotal / 2;
4655 } else {
4656 vsyncshift = 0;
4657 }
4658
4659 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4660 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4661
fe2b8f9d 4662 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hdisplay - 1) |
4664 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4665 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4666 (adjusted_mode->crtc_hblank_start - 1) |
4667 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4668 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4669 (adjusted_mode->crtc_hsync_start - 1) |
4670 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4671
fe2b8f9d 4672 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4673 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4674 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4675 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4676 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4677 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4678 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4679 (adjusted_mode->crtc_vsync_start - 1) |
4680 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4681
b5e508d4
PZ		 4682 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4683 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4684 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4685 * bits. */
4686 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4687 (pipe == PIPE_B || pipe == PIPE_C))
4688 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4689
b0e77b9c
PZ		 4690 /* pipesrc controls the size that is scaled from, which should
4691 * always be the user's requested size.
4692 */
4693 I915_WRITE(PIPESRC(pipe),
4694 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4695}
4696
1bd1bd80
DV		 4697static void intel_get_pipe_timings(struct intel_crtc *crtc,
4698 struct intel_crtc_config *pipe_config)
4699{
4700 struct drm_device *dev = crtc->base.dev;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4703 uint32_t tmp;
4704
4705 tmp = I915_READ(HTOTAL(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4708 tmp = I915_READ(HBLANK(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4711 tmp = I915_READ(HSYNC(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4714
4715 tmp = I915_READ(VTOTAL(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4718 tmp = I915_READ(VBLANK(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4721 tmp = I915_READ(VSYNC(cpu_transcoder));
4722 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4723 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4724
4725 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4726 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4727 pipe_config->adjusted_mode.crtc_vtotal += 1;
4728 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4729 }
4730
4731 tmp = I915_READ(PIPESRC(crtc->pipe));
4732 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4733 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4734}
4735
84b046f3
DV		 4736static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4737{
4738 struct drm_device *dev = intel_crtc->base.dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 uint32_t pipeconf;
4741
9f11a9e4 4742 pipeconf = 0;
84b046f3
DV		 4743
4744 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4745 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4746 * core speed.
4747 *
4748 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4749 * pipe == 0 check?
4750 */
4751 if (intel_crtc->config.requested_mode.clock >
4752 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4753 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4754 }
4755
ff9ce46e
DV		 4756 /* only g4x and later have fancy bpc/dither controls */
4757 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4758 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4759 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4760 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4761 PIPECONF_DITHER_TYPE_SP;
84b046f3 4762
ff9ce46e
DV		 4763 switch (intel_crtc->config.pipe_bpp) {
4764 case 18:
4765 pipeconf |= PIPECONF_6BPC;
4766 break;
4767 case 24:
4768 pipeconf |= PIPECONF_8BPC;
4769 break;
4770 case 30:
4771 pipeconf |= PIPECONF_10BPC;
4772 break;
4773 default:
4774 /* Case prevented by intel_choose_pipe_bpp_dither. */
4775 BUG();
84b046f3
DV		 4776 }
4777 }
4778
4779 if (HAS_PIPE_CXSR(dev)) {
4780 if (intel_crtc->lowfreq_avail) {
4781 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4782 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4783 } else {
4784 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4785 }
4786 }
4787
84b046f3
DV		 4788 if (!IS_GEN2(dev) &&
4789 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4790 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4791 else
4792 pipeconf |= PIPECONF_PROGRESSIVE;
4793
9f11a9e4
DV		 4794 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4795 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4796
84b046f3
DV		 4797 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4798 POSTING_READ(PIPECONF(intel_crtc->pipe));
4799}
4800
f564048e 4801static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4802 int x, int y,
94352cf9 4803 struct drm_framebuffer *fb)
79e53945
JB		 4804{
4805 struct drm_device *dev = crtc->dev;
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4808 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4809 int pipe = intel_crtc->pipe;
80824003 4810 int plane = intel_crtc->plane;
c751ce4f 4811 int refclk, num_connectors = 0;
652c393a 4812 intel_clock_t clock, reduced_clock;
84b046f3 4813 u32 dspcntr;
a16af721
DV		 4814 bool ok, has_reduced_clock = false;
4815 bool is_lvds = false;
5eddb70b 4816 struct intel_encoder *encoder;
d4906093 4817 const intel_limit_t *limit;
5c3b82e2 4818 int ret;
79e53945 4819
6c2b7c12 4820 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4821 switch (encoder->type) {
79e53945
JB		 4822 case INTEL_OUTPUT_LVDS:
4823 is_lvds = true;
4824 break;
79e53945 4825 }
43565a06 4826
c751ce4f 4827 num_connectors++;
79e53945
JB		 4828 }
4829
c65d77d8 4830 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4831
d4906093
ML		 4832 /*
4833 * Returns a set of divisors for the desired target clock with the given
4834 * refclk, or FALSE. The returned values represent the clock equation:
4835 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4836 */
1b894b59 4837 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4838 ok = dev_priv->display.find_dpll(limit, crtc,
4839 intel_crtc->config.port_clock,
ee9300bb
DV		 4840 refclk, NULL, &clock);
4841 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4842 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4843 return -EINVAL;
79e53945
JB		 4844 }
4845
cda4b7d3 4846 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4847 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4848
ddc9003c 4849 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4850 /*
4851 * Ensure we match the reduced clock's P to the target clock.
4852 * If the clocks don't match, we can't switch the display clock
4853 * by using the FP0/FP1. In such case we will disable the LVDS
4854 * downclock feature.
4855 */
ee9300bb
DV		 4856 has_reduced_clock =
4857 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4858 dev_priv->lvds_downclock,
ee9300bb 4859 refclk, &clock,
5eddb70b 4860 &reduced_clock);
7026d4ac 4861 }
f47709a9
DV		 4862 /* Compat-code for transition, will disappear. */
4863 if (!intel_crtc->config.clock_set) {
4864 intel_crtc->config.dpll.n = clock.n;
4865 intel_crtc->config.dpll.m1 = clock.m1;
4866 intel_crtc->config.dpll.m2 = clock.m2;
4867 intel_crtc->config.dpll.p1 = clock.p1;
4868 intel_crtc->config.dpll.p2 = clock.p2;
4869 }
7026d4ac 4870
eb1cbe48 4871 if (IS_GEN2(dev))
8a654f3b 4872 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4873 has_reduced_clock ? &reduced_clock : NULL,
4874 num_connectors);
a0c4da24 4875 else if (IS_VALLEYVIEW(dev))
f47709a9 4876 vlv_update_pll(intel_crtc);
79e53945 4877 else
f47709a9 4878 i9xx_update_pll(intel_crtc,
eb1cbe48 4879 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4880 num_connectors);
79e53945 4881
79e53945
JB		 4882 /* Set up the display plane register */
4883 dspcntr = DISPPLANE_GAMMA_ENABLE;
4884
da6ecc5d
JB		 4885 if (!IS_VALLEYVIEW(dev)) {
4886 if (pipe == 0)
4887 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4888 else
4889 dspcntr |= DISPPLANE_SEL_PIPE_B;
4890 }
79e53945 4891
8a654f3b 4892 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4893
4894 /* pipesrc and dspsize control the size that is scaled from,
4895 * which should always be the user's requested size.
79e53945 4896 */
929c77fb
EA		 4897 I915_WRITE(DSPSIZE(plane),
4898 ((mode->vdisplay - 1) << 16) |
4899 (mode->hdisplay - 1));
4900 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4901
84b046f3
DV		 4902 i9xx_set_pipeconf(intel_crtc);
4903
f564048e
EA		 4904 I915_WRITE(DSPCNTR(plane), dspcntr);
4905 POSTING_READ(DSPCNTR(plane));
4906
94352cf9 4907 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4908
4909 intel_update_watermarks(dev);
4910
f564048e
EA		 4911 return ret;
4912}
4913
2fa2fe9a
DV		 4914static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4915 struct intel_crtc_config *pipe_config)
4916{
4917 struct drm_device *dev = crtc->base.dev;
4918 struct drm_i915_private *dev_priv = dev->dev_private;
4919 uint32_t tmp;
4920
4921 tmp = I915_READ(PFIT_CONTROL);
4922
4923 if (INTEL_INFO(dev)->gen < 4) {
4924 if (crtc->pipe != PIPE_B)
4925 return;
4926
4927 /* gen2/3 store dither state in pfit control, needs to match */
4928 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4929 } else {
4930 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4931 return;
4932 }
4933
4934 if (!(tmp & PFIT_ENABLE))
4935 return;
4936
4937 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4938 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4939 if (INTEL_INFO(dev)->gen < 5)
4940 pipe_config->gmch_pfit.lvds_border_bits =
4941 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4942}
4943
0e8ffe1b
DV		 4944static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4945 struct intel_crtc_config *pipe_config)
4946{
4947 struct drm_device *dev = crtc->base.dev;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 uint32_t tmp;
4950
eccb140b 4951 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4952 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4953
0e8ffe1b
DV		 4954 tmp = I915_READ(PIPECONF(crtc->pipe));
4955 if (!(tmp & PIPECONF_ENABLE))
4956 return false;
4957
1bd1bd80
DV		 4958 intel_get_pipe_timings(crtc, pipe_config);
4959
2fa2fe9a
DV		 4960 i9xx_get_pfit_config(crtc, pipe_config);
4961
6c49f241
DV		 4962 if (INTEL_INFO(dev)->gen >= 4) {
4963 tmp = I915_READ(DPLL_MD(crtc->pipe));
4964 pipe_config->pixel_multiplier =
4965 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4966 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4967 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4968 tmp = I915_READ(DPLL(crtc->pipe));
4969 pipe_config->pixel_multiplier =
4970 ((tmp & SDVO_MULTIPLIER_MASK)
4971 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4972 } else {
4973 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4974 * port and will be fixed up in the encoder->get_config
4975 * function. */
4976 pipe_config->pixel_multiplier = 1;
4977 }
4978
0e8ffe1b
DV		 4979 return true;
4980}
4981
dde86e2d 4982static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4986 struct intel_encoder *encoder;
74cfd7ac 4987 u32 val, final;
13d83a67 4988 bool has_lvds = false;
199e5d79 4989 bool has_cpu_edp = false;
199e5d79 4990 bool has_panel = false;
99eb6a01
KP		 4991 bool has_ck505 = false;
4992 bool can_ssc = false;
13d83a67
JB		 4993
4994 /* We need to take the global config into account */
199e5d79
KP		 4995 list_for_each_entry(encoder, &mode_config->encoder_list,
4996 base.head) {
4997 switch (encoder->type) {
4998 case INTEL_OUTPUT_LVDS:
4999 has_panel = true;
5000 has_lvds = true;
5001 break;
5002 case INTEL_OUTPUT_EDP:
5003 has_panel = true;
2de6905f 5004 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5005 has_cpu_edp = true;
5006 break;
13d83a67
JB		 5007 }
5008 }
5009
99eb6a01 5010 if (HAS_PCH_IBX(dev)) {
41aa3448 5011 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5012 can_ssc = has_ck505;
5013 } else {
5014 has_ck505 = false;
5015 can_ssc = true;
5016 }
5017
2de6905f
ID		 5018 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5019 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5020
5021 /* Ironlake: try to setup display ref clock before DPLL
5022 * enabling. This is only under driver's control after
5023 * PCH B stepping, previous chipset stepping should be
5024 * ignoring this setting.
5025 */
74cfd7ac
CW		 5026 val = I915_READ(PCH_DREF_CONTROL);
5027
5028 /* As we must carefully and slowly disable/enable each source in turn,
5029 * compute the final state we want first and check if we need to
5030 * make any changes at all.
5031 */
5032 final = val;
5033 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5034 if (has_ck505)
5035 final |= DREF_NONSPREAD_CK505_ENABLE;
5036 else
5037 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5038
5039 final &= ~DREF_SSC_SOURCE_MASK;
5040 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5041 final &= ~DREF_SSC1_ENABLE;
5042
5043 if (has_panel) {
5044 final |= DREF_SSC_SOURCE_ENABLE;
5045
5046 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5047 final |= DREF_SSC1_ENABLE;
5048
5049 if (has_cpu_edp) {
5050 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5051 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5052 else
5053 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5054 } else
5055 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5056 } else {
5057 final |= DREF_SSC_SOURCE_DISABLE;
5058 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5059 }
5060
5061 if (final == val)
5062 return;
5063
13d83a67 5064 /* Always enable nonspread source */
74cfd7ac 5065 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5066
99eb6a01 5067 if (has_ck505)
74cfd7ac 5068 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5069 else
74cfd7ac 5070 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5071
199e5d79 5072 if (has_panel) {
74cfd7ac
CW		 5073 val &= ~DREF_SSC_SOURCE_MASK;
5074 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5075
199e5d79 5076 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5077 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5078 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5079 val |= DREF_SSC1_ENABLE;
e77166b5 5080 } else
74cfd7ac 5081 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5082
5083 /* Get SSC going before enabling the outputs */
74cfd7ac 5084 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5085 POSTING_READ(PCH_DREF_CONTROL);
5086 udelay(200);
5087
74cfd7ac 5088 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5089
5090 /* Enable CPU source on CPU attached eDP */
199e5d79 5091 if (has_cpu_edp) {
99eb6a01 5092 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5093 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5094 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5095 }
13d83a67 5096 else
74cfd7ac 5097 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5098 } else
74cfd7ac 5099 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5100
74cfd7ac 5101 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5102 POSTING_READ(PCH_DREF_CONTROL);
5103 udelay(200);
5104 } else {
5105 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5106
74cfd7ac 5107 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5108
5109 /* Turn off CPU output */
74cfd7ac 5110 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5111
74cfd7ac 5112 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5113 POSTING_READ(PCH_DREF_CONTROL);
5114 udelay(200);
5115
5116 /* Turn off the SSC source */
74cfd7ac
CW		 5117 val &= ~DREF_SSC_SOURCE_MASK;
5118 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5119
5120 /* Turn off SSC1 */
74cfd7ac 5121 val &= ~DREF_SSC1_ENABLE;
199e5d79 5122
74cfd7ac 5123 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5124 POSTING_READ(PCH_DREF_CONTROL);
5125 udelay(200);
5126 }
74cfd7ac
CW		 5127
5128 BUG_ON(val != final);
13d83a67
JB		 5129}
5130
dde86e2d
PZ		 5131/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5132static void lpt_init_pch_refclk(struct drm_device *dev)
5133{
5134 struct drm_i915_private *dev_priv = dev->dev_private;
5135 struct drm_mode_config *mode_config = &dev->mode_config;
5136 struct intel_encoder *encoder;
5137 bool has_vga = false;
5138 bool is_sdv = false;
5139 u32 tmp;
5140
5141 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5142 switch (encoder->type) {
5143 case INTEL_OUTPUT_ANALOG:
5144 has_vga = true;
5145 break;
5146 }
5147 }
5148
5149 if (!has_vga)
5150 return;
5151
c00db246
DV		 5152 mutex_lock(&dev_priv->dpio_lock);
5153
dde86e2d
PZ		 5154 /* XXX: Rip out SDV support once Haswell ships for real. */
5155 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5156 is_sdv = true;
5157
5158 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5159 tmp &= ~SBI_SSCCTL_DISABLE;
5160 tmp |= SBI_SSCCTL_PATHALT;
5161 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5162
5163 udelay(24);
5164
5165 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5166 tmp &= ~SBI_SSCCTL_PATHALT;
5167 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5168
5169 if (!is_sdv) {
5170 tmp = I915_READ(SOUTH_CHICKEN2);
5171 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5172 I915_WRITE(SOUTH_CHICKEN2, tmp);
5173
5174 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5175 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5176 DRM_ERROR("FDI mPHY reset assert timeout\n");
5177
5178 tmp = I915_READ(SOUTH_CHICKEN2);
5179 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5180 I915_WRITE(SOUTH_CHICKEN2, tmp);
5181
5182 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5183 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5184 100))
5185 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5186 }
5187
5188 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5189 tmp &= ~(0xFF << 24);
5190 tmp |= (0x12 << 24);
5191 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5192
dde86e2d
PZ		 5193 if (is_sdv) {
5194 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5195 tmp |= 0x7FFF;
5196 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5197 }
5198
5199 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5200 tmp |= (1 << 11);
5201 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5202
5203 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5204 tmp |= (1 << 11);
5205 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5206
5207 if (is_sdv) {
5208 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5209 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5210 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5211
5212 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5213 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5214 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5215
5216 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5217 tmp |= (0x3F << 8);
5218 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5221 tmp |= (0x3F << 8);
5222 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5223 }
5224
5225 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5226 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5227 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5228
5229 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5230 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5231 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5232
5233 if (!is_sdv) {
5234 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5235 tmp &= ~(7 << 13);
5236 tmp |= (5 << 13);
5237 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5240 tmp &= ~(7 << 13);
5241 tmp |= (5 << 13);
5242 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5243 }
5244
5245 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5246 tmp &= ~0xFF;
5247 tmp |= 0x1C;
5248 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5249
5250 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5251 tmp &= ~0xFF;
5252 tmp |= 0x1C;
5253 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5254
5255 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5256 tmp &= ~(0xFF << 16);
5257 tmp |= (0x1C << 16);
5258 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5261 tmp &= ~(0xFF << 16);
5262 tmp |= (0x1C << 16);
5263 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5264
5265 if (!is_sdv) {
5266 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5267 tmp |= (1 << 27);
5268 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5271 tmp |= (1 << 27);
5272 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5275 tmp &= ~(0xF << 28);
5276 tmp |= (4 << 28);
5277 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5280 tmp &= ~(0xF << 28);
5281 tmp |= (4 << 28);
5282 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5283 }
5284
5285 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5286 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5287 tmp |= SBI_DBUFF0_ENABLE;
5288 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5289
5290 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5291}
5292
5293/*
5294 * Initialize reference clocks when the driver loads
5295 */
5296void intel_init_pch_refclk(struct drm_device *dev)
5297{
5298 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5299 ironlake_init_pch_refclk(dev);
5300 else if (HAS_PCH_LPT(dev))
5301 lpt_init_pch_refclk(dev);
5302}
5303
d9d444cb
JB		 5304static int ironlake_get_refclk(struct drm_crtc *crtc)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_encoder *encoder;
d9d444cb
JB		 5309 int num_connectors = 0;
5310 bool is_lvds = false;
5311
6c2b7c12 5312 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5313 switch (encoder->type) {
5314 case INTEL_OUTPUT_LVDS:
5315 is_lvds = true;
5316 break;
d9d444cb
JB		 5317 }
5318 num_connectors++;
5319 }
5320
5321 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5322 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5323 dev_priv->vbt.lvds_ssc_freq);
5324 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5325 }
5326
5327 return 120000;
5328}
5329
6ff93609 5330static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5331{
c8203565 5332 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5334 int pipe = intel_crtc->pipe;
c8203565
PZ		 5335 uint32_t val;
5336
78114071 5337 val = 0;
c8203565 5338
965e0c48 5339 switch (intel_crtc->config.pipe_bpp) {
c8203565 5340 case 18:
dfd07d72 5341 val |= PIPECONF_6BPC;
c8203565
PZ		 5342 break;
5343 case 24:
dfd07d72 5344 val |= PIPECONF_8BPC;
c8203565
PZ		 5345 break;
5346 case 30:
dfd07d72 5347 val |= PIPECONF_10BPC;
c8203565
PZ		 5348 break;
5349 case 36:
dfd07d72 5350 val |= PIPECONF_12BPC;
c8203565
PZ		 5351 break;
5352 default:
cc769b62
PZ		 5353 /* Case prevented by intel_choose_pipe_bpp_dither. */
5354 BUG();
c8203565
PZ		 5355 }
5356
d8b32247 5357 if (intel_crtc->config.dither)
c8203565
PZ		 5358 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5359
6ff93609 5360 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5361 val |= PIPECONF_INTERLACED_ILK;
5362 else
5363 val |= PIPECONF_PROGRESSIVE;
5364
50f3b016 5365 if (intel_crtc->config.limited_color_range)
3685a8f3 5366 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5367
c8203565
PZ		 5368 I915_WRITE(PIPECONF(pipe), val);
5369 POSTING_READ(PIPECONF(pipe));
5370}
5371
86d3efce
VS		 5372/*
5373 * Set up the pipe CSC unit.
5374 *
5375 * Currently only full range RGB to limited range RGB conversion
5376 * is supported, but eventually this should handle various
5377 * RGB<->YCbCr scenarios as well.
5378 */
50f3b016 5379static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5380{
5381 struct drm_device *dev = crtc->dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
5383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5384 int pipe = intel_crtc->pipe;
5385 uint16_t coeff = 0x7800; /* 1.0 */
5386
5387 /*
5388 * TODO: Check what kind of values actually come out of the pipe
5389 * with these coeff/postoff values and adjust to get the best
5390 * accuracy. Perhaps we even need to take the bpc value into
5391 * consideration.
5392 */
5393
50f3b016 5394 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5395 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5396
5397 /*
5398 * GY/GU and RY/RU should be the other way around according
5399 * to BSpec, but reality doesn't agree. Just set them up in
5400 * a way that results in the correct picture.
5401 */
5402 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5403 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5404
5405 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5406 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5407
5408 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5409 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5410
5411 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5412 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5413 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5414
5415 if (INTEL_INFO(dev)->gen > 6) {
5416 uint16_t postoff = 0;
5417
50f3b016 5418 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5419 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5420
5421 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5422 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5423 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5424
5425 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5426 } else {
5427 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5428
50f3b016 5429 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5430 mode |= CSC_BLACK_SCREEN_OFFSET;
5431
5432 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5433 }
5434}
5435
6ff93609 5436static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5437{
5438 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5440 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5441 uint32_t val;
5442
3eff4faa 5443 val = 0;
ee2b0b38 5444
d8b32247 5445 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5446 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5447
6ff93609 5448 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5449 val |= PIPECONF_INTERLACED_ILK;
5450 else
5451 val |= PIPECONF_PROGRESSIVE;
5452
702e7a56
PZ		 5453 I915_WRITE(PIPECONF(cpu_transcoder), val);
5454 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5455
5456 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5457 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5458}
5459
6591c6e4 5460static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5461 intel_clock_t *clock,
5462 bool *has_reduced_clock,
5463 intel_clock_t *reduced_clock)
5464{
5465 struct drm_device *dev = crtc->dev;
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467 struct intel_encoder *intel_encoder;
5468 int refclk;
d4906093 5469 const intel_limit_t *limit;
a16af721 5470 bool ret, is_lvds = false;
79e53945 5471
6591c6e4
PZ		 5472 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5473 switch (intel_encoder->type) {
79e53945
JB		 5474 case INTEL_OUTPUT_LVDS:
5475 is_lvds = true;
5476 break;
79e53945
JB		 5477 }
5478 }
5479
d9d444cb 5480 refclk = ironlake_get_refclk(crtc);
79e53945 5481
d4906093
ML		 5482 /*
5483 * Returns a set of divisors for the desired target clock with the given
5484 * refclk, or FALSE. The returned values represent the clock equation:
5485 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5486 */
1b894b59 5487 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5488 ret = dev_priv->display.find_dpll(limit, crtc,
5489 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5490 refclk, NULL, clock);
6591c6e4
PZ		 5491 if (!ret)
5492 return false;
cda4b7d3 5493
ddc9003c 5494 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5495 /*
5496 * Ensure we match the reduced clock's P to the target clock.
5497 * If the clocks don't match, we can't switch the display clock
5498 * by using the FP0/FP1. In such case we will disable the LVDS
5499 * downclock feature.
5500 */
ee9300bb
DV		 5501 *has_reduced_clock =
5502 dev_priv->display.find_dpll(limit, crtc,
5503 dev_priv->lvds_downclock,
5504 refclk, clock,
5505 reduced_clock);
652c393a 5506 }
61e9653f 5507
6591c6e4
PZ		 5508 return true;
5509}
5510
01a415fd
DV		 5511static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5512{
5513 struct drm_i915_private *dev_priv = dev->dev_private;
5514 uint32_t temp;
5515
5516 temp = I915_READ(SOUTH_CHICKEN1);
5517 if (temp & FDI_BC_BIFURCATION_SELECT)
5518 return;
5519
5520 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5521 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5522
5523 temp |= FDI_BC_BIFURCATION_SELECT;
5524 DRM_DEBUG_KMS("enabling fdi C rx\n");
5525 I915_WRITE(SOUTH_CHICKEN1, temp);
5526 POSTING_READ(SOUTH_CHICKEN1);
5527}
5528
ebfd86fd 5529static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5530{
5531 struct drm_device *dev = intel_crtc->base.dev;
5532 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5533
5534 switch (intel_crtc->pipe) {
5535 case PIPE_A:
ebfd86fd 5536 break;
01a415fd 5537 case PIPE_B:
ebfd86fd 5538 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5539 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5540 else
5541 cpt_enable_fdi_bc_bifurcation(dev);
5542
ebfd86fd 5543 break;
01a415fd 5544 case PIPE_C:
01a415fd
DV		 5545 cpt_enable_fdi_bc_bifurcation(dev);
5546
ebfd86fd 5547 break;
01a415fd
DV		 5548 default:
5549 BUG();
5550 }
5551}
5552
d4b1931c
PZ		 5553int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5554{
5555 /*
5556 * Account for spread spectrum to avoid
5557 * oversubscribing the link. Max center spread
5558 * is 2.5%; use 5% for safety's sake.
5559 */
5560 u32 bps = target_clock * bpp * 21 / 20;
5561 return bps / (link_bw * 8) + 1;
5562}
5563
7429e9d4 5564static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5565{
7429e9d4 5566 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5567}
5568
de13a2e3 5569static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5570 u32 *fp,
9a7c7890 5571 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5572{
de13a2e3 5573 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5574 struct drm_device *dev = crtc->dev;
5575 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5576 struct intel_encoder *intel_encoder;
5577 uint32_t dpll;
6cc5f341 5578 int factor, num_connectors = 0;
09ede541 5579 bool is_lvds = false, is_sdvo = false;
79e53945 5580
de13a2e3
PZ		 5581 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5582 switch (intel_encoder->type) {
79e53945
JB		 5583 case INTEL_OUTPUT_LVDS:
5584 is_lvds = true;
5585 break;
5586 case INTEL_OUTPUT_SDVO:
7d57382e 5587 case INTEL_OUTPUT_HDMI:
79e53945 5588 is_sdvo = true;
79e53945 5589 break;
79e53945 5590 }
43565a06 5591
c751ce4f 5592 num_connectors++;
79e53945 5593 }
79e53945 5594
c1858123 5595 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5596 factor = 21;
5597 if (is_lvds) {
5598 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5599 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5600 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5601 factor = 25;
09ede541 5602 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5603 factor = 20;
c1858123 5604
7429e9d4 5605 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5606 *fp |= FP_CB_TUNE;
2c07245f 5607
9a7c7890
DV		 5608 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5609 *fp2 |= FP_CB_TUNE;
5610
5eddb70b 5611 dpll = 0;
2c07245f 5612
a07d6787
EA		 5613 if (is_lvds)
5614 dpll |= DPLLB_MODE_LVDS;
5615 else
5616 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5617
ef1b460d
DV		 5618 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5619 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5620
5621 if (is_sdvo)
5622 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5623 if (intel_crtc->config.has_dp_encoder)
a07d6787 5624 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5625
a07d6787 5626 /* compute bitmask from p1 value */
7429e9d4 5627 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5628 /* also FPA1 */
7429e9d4 5629 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5630
7429e9d4 5631 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5632 case 5:
5633 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5634 break;
5635 case 7:
5636 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5637 break;
5638 case 10:
5639 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5640 break;
5641 case 14:
5642 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5643 break;
79e53945
JB		 5644 }
5645
b4c09f3b 5646 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5647 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5648 else
5649 dpll |= PLL_REF_INPUT_DREFCLK;
5650
959e16d6 5651 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5652}
5653
5654static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5655 int x, int y,
5656 struct drm_framebuffer *fb)
5657{
5658 struct drm_device *dev = crtc->dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5661 int pipe = intel_crtc->pipe;
5662 int plane = intel_crtc->plane;
5663 int num_connectors = 0;
5664 intel_clock_t clock, reduced_clock;
cbbab5bd 5665 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5666 bool ok, has_reduced_clock = false;
8b47047b 5667 bool is_lvds = false;
de13a2e3 5668 struct intel_encoder *encoder;
e2b78267 5669 struct intel_shared_dpll *pll;
de13a2e3 5670 int ret;
de13a2e3
PZ		 5671
5672 for_each_encoder_on_crtc(dev, crtc, encoder) {
5673 switch (encoder->type) {
5674 case INTEL_OUTPUT_LVDS:
5675 is_lvds = true;
5676 break;
de13a2e3
PZ		 5677 }
5678
5679 num_connectors++;
a07d6787 5680 }
79e53945 5681
5dc5298b
PZ		 5682 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5683 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5684
ff9a6750 5685 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5686 &has_reduced_clock, &reduced_clock);
ee9300bb 5687 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5688 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5689 return -EINVAL;
79e53945 5690 }
f47709a9
DV		 5691 /* Compat-code for transition, will disappear. */
5692 if (!intel_crtc->config.clock_set) {
5693 intel_crtc->config.dpll.n = clock.n;
5694 intel_crtc->config.dpll.m1 = clock.m1;
5695 intel_crtc->config.dpll.m2 = clock.m2;
5696 intel_crtc->config.dpll.p1 = clock.p1;
5697 intel_crtc->config.dpll.p2 = clock.p2;
5698 }
79e53945 5699
de13a2e3
PZ		 5700 /* Ensure that the cursor is valid for the new mode before changing... */
5701 intel_crtc_update_cursor(crtc, true);
5702
5dc5298b 5703 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5704 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5705 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5706 if (has_reduced_clock)
7429e9d4 5707 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5708
7429e9d4 5709 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5710 &fp, &reduced_clock,
5711 has_reduced_clock ? &fp2 : NULL);
5712
959e16d6 5713 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5714 intel_crtc->config.dpll_hw_state.fp0 = fp;
5715 if (has_reduced_clock)
5716 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5717 else
5718 intel_crtc->config.dpll_hw_state.fp1 = fp;
5719
b89a1d39 5720 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5721 if (pll == NULL) {
84f44ce7
VS		 5722 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5723 pipe_name(pipe));
4b645f14
JB		 5724 return -EINVAL;
5725 }
ee7b9f93 5726 } else
e72f9fbf 5727 intel_put_shared_dpll(intel_crtc);
79e53945 5728
03afc4a2
DV		 5729 if (intel_crtc->config.has_dp_encoder)
5730 intel_dp_set_m_n(intel_crtc);
79e53945 5731
bcd644e0
DV		 5732 if (is_lvds && has_reduced_clock && i915_powersave)
5733 intel_crtc->lowfreq_avail = true;
5734 else
5735 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5736
5737 if (intel_crtc->config.has_pch_encoder) {
5738 pll = intel_crtc_to_shared_dpll(intel_crtc);
5739
652c393a
JB		 5740 }
5741
8a654f3b 5742 intel_set_pipe_timings(intel_crtc);
5eddb70b 5743
ca3a0ff8 5744 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5745 intel_cpu_transcoder_set_m_n(intel_crtc,
5746 &intel_crtc->config.fdi_m_n);
5747 }
2c07245f 5748
ebfd86fd
DV		 5749 if (IS_IVYBRIDGE(dev))
5750 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5751
6ff93609 5752 ironlake_set_pipeconf(crtc);
79e53945 5753
a1f9e77e
PZ		 5754 /* Set up the display plane register */
5755 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5756 POSTING_READ(DSPCNTR(plane));
79e53945 5757
94352cf9 5758 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5759
5760 intel_update_watermarks(dev);
5761
1857e1da 5762 return ret;
79e53945
JB		 5763}
5764
72419203
DV		 5765static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5766 struct intel_crtc_config *pipe_config)
5767{
5768 struct drm_device *dev = crtc->base.dev;
5769 struct drm_i915_private *dev_priv = dev->dev_private;
5770 enum transcoder transcoder = pipe_config->cpu_transcoder;
5771
5772 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5773 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5774 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5775 & ~TU_SIZE_MASK;
5776 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5777 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5778 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5779}
5780
2fa2fe9a
DV		 5781static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5782 struct intel_crtc_config *pipe_config)
5783{
5784 struct drm_device *dev = crtc->base.dev;
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786 uint32_t tmp;
5787
5788 tmp = I915_READ(PF_CTL(crtc->pipe));
5789
5790 if (tmp & PF_ENABLE) {
5791 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5792 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5793
5794 /* We currently do not free assignements of panel fitters on
5795 * ivb/hsw (since we don't use the higher upscaling modes which
5796 * differentiates them) so just WARN about this case for now. */
5797 if (IS_GEN7(dev)) {
5798 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5799 PF_PIPE_SEL_IVB(crtc->pipe));
5800 }
2fa2fe9a 5801 }
79e53945
JB		 5802}
5803
0e8ffe1b
DV		 5804static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5805 struct intel_crtc_config *pipe_config)
5806{
5807 struct drm_device *dev = crtc->base.dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 uint32_t tmp;
5810
eccb140b 5811 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5812 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5813
0e8ffe1b
DV		 5814 tmp = I915_READ(PIPECONF(crtc->pipe));
5815 if (!(tmp & PIPECONF_ENABLE))
5816 return false;
5817
ab9412ba 5818 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5819 struct intel_shared_dpll *pll;
5820
88adfff1
DV		 5821 pipe_config->has_pch_encoder = true;
5822
627eb5a3
DV		 5823 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5824 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5825 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5826
5827 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5828
5829 /* XXX: Can't properly read out the pch dpll pixel multiplier
5830 * since we don't have state tracking for pch clocks yet. */
5831 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5832
5833 if (HAS_PCH_IBX(dev_priv->dev)) {
5834 pipe_config->shared_dpll = crtc->pipe;
5835 } else {
5836 tmp = I915_READ(PCH_DPLL_SEL);
5837 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5838 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5839 else
5840 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5841 }
66e985c0
DV		 5842
5843 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5844
5845 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5846 &pipe_config->dpll_hw_state));
6c49f241
DV		 5847 } else {
5848 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5849 }
5850
1bd1bd80
DV		 5851 intel_get_pipe_timings(crtc, pipe_config);
5852
2fa2fe9a
DV		 5853 ironlake_get_pfit_config(crtc, pipe_config);
5854
0e8ffe1b
DV		 5855 return true;
5856}
5857
d6dd9eb1
DV		 5858static void haswell_modeset_global_resources(struct drm_device *dev)
5859{
d6dd9eb1
DV		 5860 bool enable = false;
5861 struct intel_crtc *crtc;
d6dd9eb1
DV		 5862
5863 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5864 if (!crtc->base.enabled)
5865 continue;
d6dd9eb1 5866
e7a639c4
DV		 5867 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5868 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5869 enable = true;
5870 }
5871
d6dd9eb1
DV		 5872 intel_set_power_well(dev, enable);
5873}
5874
09b4ddf9 5875static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5876 int x, int y,
5877 struct drm_framebuffer *fb)
5878{
5879 struct drm_device *dev = crtc->dev;
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5882 int plane = intel_crtc->plane;
09b4ddf9 5883 int ret;
09b4ddf9 5884
ff9a6750 5885 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5886 return -EINVAL;
5887
09b4ddf9
PZ		 5888 /* Ensure that the cursor is valid for the new mode before changing... */
5889 intel_crtc_update_cursor(crtc, true);
5890
03afc4a2
DV		 5891 if (intel_crtc->config.has_dp_encoder)
5892 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5893
5894 intel_crtc->lowfreq_avail = false;
09b4ddf9 5895
8a654f3b 5896 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5897
ca3a0ff8 5898 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5899 intel_cpu_transcoder_set_m_n(intel_crtc,
5900 &intel_crtc->config.fdi_m_n);
5901 }
09b4ddf9 5902
6ff93609 5903 haswell_set_pipeconf(crtc);
09b4ddf9 5904
50f3b016 5905 intel_set_pipe_csc(crtc);
86d3efce 5906
09b4ddf9 5907 /* Set up the display plane register */
86d3efce 5908 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5909 POSTING_READ(DSPCNTR(plane));
5910
5911 ret = intel_pipe_set_base(crtc, x, y, fb);
5912
5913 intel_update_watermarks(dev);
5914
1f803ee5 5915 return ret;
79e53945
JB		 5916}
5917
0e8ffe1b
DV		 5918static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5919 struct intel_crtc_config *pipe_config)
5920{
5921 struct drm_device *dev = crtc->base.dev;
5922 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5923 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5924 uint32_t tmp;
5925
eccb140b 5926 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5927 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5928
eccb140b
DV		 5929 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5930 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5931 enum pipe trans_edp_pipe;
5932 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5933 default:
5934 WARN(1, "unknown pipe linked to edp transcoder\n");
5935 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5936 case TRANS_DDI_EDP_INPUT_A_ON:
5937 trans_edp_pipe = PIPE_A;
5938 break;
5939 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5940 trans_edp_pipe = PIPE_B;
5941 break;
5942 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5943 trans_edp_pipe = PIPE_C;
5944 break;
5945 }
5946
5947 if (trans_edp_pipe == crtc->pipe)
5948 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5949 }
5950
b97186f0 5951 if (!intel_display_power_enabled(dev,
eccb140b 5952 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5953 return false;
5954
eccb140b 5955 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5956 if (!(tmp & PIPECONF_ENABLE))
5957 return false;
5958
88adfff1 5959 /*
f196e6be 5960 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5961 * DDI E. So just check whether this pipe is wired to DDI E and whether
5962 * the PCH transcoder is on.
5963 */
eccb140b 5964 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5965 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5966 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5967 pipe_config->has_pch_encoder = true;
5968
627eb5a3
DV		 5969 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5970 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5971 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5972
5973 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5974 }
5975
1bd1bd80
DV		 5976 intel_get_pipe_timings(crtc, pipe_config);
5977
2fa2fe9a
DV		 5978 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5979 if (intel_display_power_enabled(dev, pfit_domain))
5980 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 5981
42db64ef
PZ		 5982 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5983 (I915_READ(IPS_CTL) & IPS_ENABLE);
5984
6c49f241
DV		 5985 pipe_config->pixel_multiplier = 1;
5986
0e8ffe1b
DV		 5987 return true;
5988}
5989
f564048e 5990static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5991 int x, int y,
94352cf9 5992 struct drm_framebuffer *fb)
f564048e
EA		 5993{
5994 struct drm_device *dev = crtc->dev;
5995 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5996 struct drm_encoder_helper_funcs *encoder_funcs;
5997 struct intel_encoder *encoder;
0b701d27 5998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5999 struct drm_display_mode *adjusted_mode =
6000 &intel_crtc->config.adjusted_mode;
6001 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6002 int pipe = intel_crtc->pipe;
f564048e
EA		 6003 int ret;
6004
0b701d27 6005 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6006
b8cecdf5
DV		 6007 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6008
79e53945 6009 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6010
9256aa19
DV		 6011 if (ret != 0)
6012 return ret;
6013
6014 for_each_encoder_on_crtc(dev, crtc, encoder) {
6015 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6016 encoder->base.base.id,
6017 drm_get_encoder_name(&encoder->base),
6018 mode->base.id, mode->name);
6cc5f341
DV		 6019 if (encoder->mode_set) {
6020 encoder->mode_set(encoder);
6021 } else {
6022 encoder_funcs = encoder->base.helper_private;
6023 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6024 }
9256aa19
DV		 6025 }
6026
6027 return 0;
79e53945
JB		 6028}
6029
3a9627f4
WF		 6030static bool intel_eld_uptodate(struct drm_connector *connector,
6031 int reg_eldv, uint32_t bits_eldv,
6032 int reg_elda, uint32_t bits_elda,
6033 int reg_edid)
6034{
6035 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6036 uint8_t *eld = connector->eld;
6037 uint32_t i;
6038
6039 i = I915_READ(reg_eldv);
6040 i &= bits_eldv;
6041
6042 if (!eld[0])
6043 return !i;
6044
6045 if (!i)
6046 return false;
6047
6048 i = I915_READ(reg_elda);
6049 i &= ~bits_elda;
6050 I915_WRITE(reg_elda, i);
6051
6052 for (i = 0; i < eld[2]; i++)
6053 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6054 return false;
6055
6056 return true;
6057}
6058
e0dac65e
WF		 6059static void g4x_write_eld(struct drm_connector *connector,
6060 struct drm_crtc *crtc)
6061{
6062 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6063 uint8_t *eld = connector->eld;
6064 uint32_t eldv;
6065 uint32_t len;
6066 uint32_t i;
6067
6068 i = I915_READ(G4X_AUD_VID_DID);
6069
6070 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6071 eldv = G4X_ELDV_DEVCL_DEVBLC;
6072 else
6073 eldv = G4X_ELDV_DEVCTG;
6074
3a9627f4
WF		 6075 if (intel_eld_uptodate(connector,
6076 G4X_AUD_CNTL_ST, eldv,
6077 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6078 G4X_HDMIW_HDMIEDID))
6079 return;
6080
e0dac65e
WF		 6081 i = I915_READ(G4X_AUD_CNTL_ST);
6082 i &= ~(eldv | G4X_ELD_ADDR);
6083 len = (i >> 9) & 0x1f; /* ELD buffer size */
6084 I915_WRITE(G4X_AUD_CNTL_ST, i);
6085
6086 if (!eld[0])
6087 return;
6088
6089 len = min_t(uint8_t, eld[2], len);
6090 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6091 for (i = 0; i < len; i++)
6092 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6093
6094 i = I915_READ(G4X_AUD_CNTL_ST);
6095 i |= eldv;
6096 I915_WRITE(G4X_AUD_CNTL_ST, i);
6097}
6098
83358c85
WX		 6099static void haswell_write_eld(struct drm_connector *connector,
6100 struct drm_crtc *crtc)
6101{
6102 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6103 uint8_t *eld = connector->eld;
6104 struct drm_device *dev = crtc->dev;
7b9f35a6 6105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6106 uint32_t eldv;
6107 uint32_t i;
6108 int len;
6109 int pipe = to_intel_crtc(crtc)->pipe;
6110 int tmp;
6111
6112 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6113 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6114 int aud_config = HSW_AUD_CFG(pipe);
6115 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6116
6117
6118 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6119
6120 /* Audio output enable */
6121 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6122 tmp = I915_READ(aud_cntrl_st2);
6123 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6124 I915_WRITE(aud_cntrl_st2, tmp);
6125
6126 /* Wait for 1 vertical blank */
6127 intel_wait_for_vblank(dev, pipe);
6128
6129 /* Set ELD valid state */
6130 tmp = I915_READ(aud_cntrl_st2);
6131 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6132 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6133 I915_WRITE(aud_cntrl_st2, tmp);
6134 tmp = I915_READ(aud_cntrl_st2);
6135 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6136
6137 /* Enable HDMI mode */
6138 tmp = I915_READ(aud_config);
6139 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6140 /* clear N_programing_enable and N_value_index */
6141 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6142 I915_WRITE(aud_config, tmp);
6143
6144 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6145
6146 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6147 intel_crtc->eld_vld = true;
83358c85
WX		 6148
6149 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6150 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6151 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6152 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6153 } else
6154 I915_WRITE(aud_config, 0);
6155
6156 if (intel_eld_uptodate(connector,
6157 aud_cntrl_st2, eldv,
6158 aud_cntl_st, IBX_ELD_ADDRESS,
6159 hdmiw_hdmiedid))
6160 return;
6161
6162 i = I915_READ(aud_cntrl_st2);
6163 i &= ~eldv;
6164 I915_WRITE(aud_cntrl_st2, i);
6165
6166 if (!eld[0])
6167 return;
6168
6169 i = I915_READ(aud_cntl_st);
6170 i &= ~IBX_ELD_ADDRESS;
6171 I915_WRITE(aud_cntl_st, i);
6172 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6173 DRM_DEBUG_DRIVER("port num:%d\n", i);
6174
6175 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6176 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6177 for (i = 0; i < len; i++)
6178 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6179
6180 i = I915_READ(aud_cntrl_st2);
6181 i |= eldv;
6182 I915_WRITE(aud_cntrl_st2, i);
6183
6184}
6185
e0dac65e
WF		 6186static void ironlake_write_eld(struct drm_connector *connector,
6187 struct drm_crtc *crtc)
6188{
6189 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6190 uint8_t *eld = connector->eld;
6191 uint32_t eldv;
6192 uint32_t i;
6193 int len;
6194 int hdmiw_hdmiedid;
b6daa025 6195 int aud_config;
e0dac65e
WF		 6196 int aud_cntl_st;
6197 int aud_cntrl_st2;
9b138a83 6198 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6199
b3f33cbf 6200 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6201 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6202 aud_config = IBX_AUD_CFG(pipe);
6203 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6204 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6205 } else {
9b138a83
WX		 6206 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6207 aud_config = CPT_AUD_CFG(pipe);
6208 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6209 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6210 }
6211
9b138a83 6212 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6213
6214 i = I915_READ(aud_cntl_st);
9b138a83 6215 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6216 if (!i) {
6217 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6218 /* operate blindly on all ports */
1202b4c6
WF		 6219 eldv = IBX_ELD_VALIDB;
6220 eldv |= IBX_ELD_VALIDB << 4;
6221 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6222 } else {
2582a850 6223 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6224 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6225 }
6226
3a9627f4
WF		 6227 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6228 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6229 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6230 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6231 } else
6232 I915_WRITE(aud_config, 0);
e0dac65e 6233
3a9627f4
WF		 6234 if (intel_eld_uptodate(connector,
6235 aud_cntrl_st2, eldv,
6236 aud_cntl_st, IBX_ELD_ADDRESS,
6237 hdmiw_hdmiedid))
6238 return;
6239
e0dac65e
WF		 6240 i = I915_READ(aud_cntrl_st2);
6241 i &= ~eldv;
6242 I915_WRITE(aud_cntrl_st2, i);
6243
6244 if (!eld[0])
6245 return;
6246
e0dac65e 6247 i = I915_READ(aud_cntl_st);
1202b4c6 6248 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6249 I915_WRITE(aud_cntl_st, i);
6250
6251 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6252 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6253 for (i = 0; i < len; i++)
6254 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6255
6256 i = I915_READ(aud_cntrl_st2);
6257 i |= eldv;
6258 I915_WRITE(aud_cntrl_st2, i);
6259}
6260
6261void intel_write_eld(struct drm_encoder *encoder,
6262 struct drm_display_mode *mode)
6263{
6264 struct drm_crtc *crtc = encoder->crtc;
6265 struct drm_connector *connector;
6266 struct drm_device *dev = encoder->dev;
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268
6269 connector = drm_select_eld(encoder, mode);
6270 if (!connector)
6271 return;
6272
6273 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6274 connector->base.id,
6275 drm_get_connector_name(connector),
6276 connector->encoder->base.id,
6277 drm_get_encoder_name(connector->encoder));
6278
6279 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6280
6281 if (dev_priv->display.write_eld)
6282 dev_priv->display.write_eld(connector, crtc);
6283}
6284
79e53945
JB		 6285/** Loads the palette/gamma unit for the CRTC with the prepared values */
6286void intel_crtc_load_lut(struct drm_crtc *crtc)
6287{
6288 struct drm_device *dev = crtc->dev;
6289 struct drm_i915_private *dev_priv = dev->dev_private;
6290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6291 enum pipe pipe = intel_crtc->pipe;
6292 int palreg = PALETTE(pipe);
79e53945 6293 int i;
42db64ef 6294 bool reenable_ips = false;
79e53945
JB		 6295
6296 /* The clocks have to be on to load the palette. */
aed3f09d 6297 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6298 return;
6299
14420bd0
VS		 6300 if (!HAS_PCH_SPLIT(dev_priv->dev))
6301 assert_pll_enabled(dev_priv, pipe);
6302
f2b115e6 6303 /* use legacy palette for Ironlake */
bad720ff 6304 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6305 palreg = LGC_PALETTE(pipe);
6306
6307 /* Workaround : Do not read or write the pipe palette/gamma data while
6308 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6309 */
6310 if (intel_crtc->config.ips_enabled &&
6311 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6312 GAMMA_MODE_MODE_SPLIT)) {
6313 hsw_disable_ips(intel_crtc);
6314 reenable_ips = true;
6315 }
2c07245f 6316
79e53945
JB		 6317 for (i = 0; i < 256; i++) {
6318 I915_WRITE(palreg + 4 * i,
6319 (intel_crtc->lut_r[i] << 16) |
6320 (intel_crtc->lut_g[i] << 8) |
6321 intel_crtc->lut_b[i]);
6322 }
42db64ef
PZ		 6323
6324 if (reenable_ips)
6325 hsw_enable_ips(intel_crtc);
79e53945
JB		 6326}
6327
560b85bb
CW		 6328static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6329{
6330 struct drm_device *dev = crtc->dev;
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6333 bool visible = base != 0;
6334 u32 cntl;
6335
6336 if (intel_crtc->cursor_visible == visible)
6337 return;
6338
9db4a9c7 6339 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6340 if (visible) {
6341 /* On these chipsets we can only modify the base whilst
6342 * the cursor is disabled.
6343 */
9db4a9c7 6344 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6345
6346 cntl &= ~(CURSOR_FORMAT_MASK);
6347 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6348 cntl |= CURSOR_ENABLE |
6349 CURSOR_GAMMA_ENABLE |
6350 CURSOR_FORMAT_ARGB;
6351 } else
6352 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6353 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6354
6355 intel_crtc->cursor_visible = visible;
6356}
6357
6358static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6359{
6360 struct drm_device *dev = crtc->dev;
6361 struct drm_i915_private *dev_priv = dev->dev_private;
6362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363 int pipe = intel_crtc->pipe;
6364 bool visible = base != 0;
6365
6366 if (intel_crtc->cursor_visible != visible) {
548f245b 6367 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6368 if (base) {
6369 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6370 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6371 cntl |= pipe << 28; /* Connect to correct pipe */
6372 } else {
6373 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6374 cntl |= CURSOR_MODE_DISABLE;
6375 }
9db4a9c7 6376 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6377
6378 intel_crtc->cursor_visible = visible;
6379 }
6380 /* and commit changes on next vblank */
9db4a9c7 6381 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6382}
6383
65a21cd6
JB		 6384static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6385{
6386 struct drm_device *dev = crtc->dev;
6387 struct drm_i915_private *dev_priv = dev->dev_private;
6388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389 int pipe = intel_crtc->pipe;
6390 bool visible = base != 0;
6391
6392 if (intel_crtc->cursor_visible != visible) {
6393 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6394 if (base) {
6395 cntl &= ~CURSOR_MODE;
6396 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6397 } else {
6398 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6399 cntl |= CURSOR_MODE_DISABLE;
6400 }
86d3efce
VS		 6401 if (IS_HASWELL(dev))
6402 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6403 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6404
6405 intel_crtc->cursor_visible = visible;
6406 }
6407 /* and commit changes on next vblank */
6408 I915_WRITE(CURBASE_IVB(pipe), base);
6409}
6410
cda4b7d3 6411/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6412static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6413 bool on)
cda4b7d3
CW		 6414{
6415 struct drm_device *dev = crtc->dev;
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418 int pipe = intel_crtc->pipe;
6419 int x = intel_crtc->cursor_x;
6420 int y = intel_crtc->cursor_y;
560b85bb 6421 u32 base, pos;
cda4b7d3
CW		 6422 bool visible;
6423
6424 pos = 0;
6425
6b383a7f 6426 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6427 base = intel_crtc->cursor_addr;
6428 if (x > (int) crtc->fb->width)
6429 base = 0;
6430
6431 if (y > (int) crtc->fb->height)
6432 base = 0;
6433 } else
6434 base = 0;
6435
6436 if (x < 0) {
6437 if (x + intel_crtc->cursor_width < 0)
6438 base = 0;
6439
6440 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6441 x = -x;
6442 }
6443 pos |= x << CURSOR_X_SHIFT;
6444
6445 if (y < 0) {
6446 if (y + intel_crtc->cursor_height < 0)
6447 base = 0;
6448
6449 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6450 y = -y;
6451 }
6452 pos |= y << CURSOR_Y_SHIFT;
6453
6454 visible = base != 0;
560b85bb 6455 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6456 return;
6457
0cd83aa9 6458 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6459 I915_WRITE(CURPOS_IVB(pipe), pos);
6460 ivb_update_cursor(crtc, base);
6461 } else {
6462 I915_WRITE(CURPOS(pipe), pos);
6463 if (IS_845G(dev) || IS_I865G(dev))
6464 i845_update_cursor(crtc, base);
6465 else
6466 i9xx_update_cursor(crtc, base);
6467 }
cda4b7d3
CW		 6468}
6469
79e53945 6470static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6471 struct drm_file *file,
79e53945
JB		 6472 uint32_t handle,
6473 uint32_t width, uint32_t height)
6474{
6475 struct drm_device *dev = crtc->dev;
6476 struct drm_i915_private *dev_priv = dev->dev_private;
6477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6478 struct drm_i915_gem_object *obj;
cda4b7d3 6479 uint32_t addr;
3f8bc370 6480 int ret;
79e53945 6481
79e53945
JB		 6482 /* if we want to turn off the cursor ignore width and height */
6483 if (!handle) {
28c97730 6484 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6485 addr = 0;
05394f39 6486 obj = NULL;
5004417d 6487 mutex_lock(&dev->struct_mutex);
3f8bc370 6488 goto finish;
79e53945
JB		 6489 }
6490
6491 /* Currently we only support 64x64 cursors */
6492 if (width != 64 || height != 64) {
6493 DRM_ERROR("we currently only support 64x64 cursors\n");
6494 return -EINVAL;
6495 }
6496
05394f39 6497 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6498 if (&obj->base == NULL)
79e53945
JB		 6499 return -ENOENT;
6500
05394f39 6501 if (obj->base.size < width * height * 4) {
79e53945 6502 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6503 ret = -ENOMEM;
6504 goto fail;
79e53945
JB		 6505 }
6506
71acb5eb 6507 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6508 mutex_lock(&dev->struct_mutex);
b295d1b6 6509 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6510 unsigned alignment;
6511
d9e86c0e
CW		 6512 if (obj->tiling_mode) {
6513 DRM_ERROR("cursor cannot be tiled\n");
6514 ret = -EINVAL;
6515 goto fail_locked;
6516 }
6517
693db184
CW		 6518 /* Note that the w/a also requires 2 PTE of padding following
6519 * the bo. We currently fill all unused PTE with the shadow
6520 * page and so we should always have valid PTE following the
6521 * cursor preventing the VT-d warning.
6522 */
6523 alignment = 0;
6524 if (need_vtd_wa(dev))
6525 alignment = 64*1024;
6526
6527 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6528 if (ret) {
6529 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6530 goto fail_locked;
e7b526bb
CW		 6531 }
6532
d9e86c0e
CW		 6533 ret = i915_gem_object_put_fence(obj);
6534 if (ret) {
2da3b9b9 6535 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6536 goto fail_unpin;
6537 }
6538
05394f39 6539 addr = obj->gtt_offset;
71acb5eb 6540 } else {
6eeefaf3 6541 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6542 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6543 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6544 align);
71acb5eb
DA		 6545 if (ret) {
6546 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6547 goto fail_locked;
71acb5eb 6548 }
05394f39 6549 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6550 }
6551
a6c45cf0 6552 if (IS_GEN2(dev))
14b60391
JB		 6553 I915_WRITE(CURSIZE, (height << 12) | width);
6554
3f8bc370 6555 finish:
3f8bc370 6556 if (intel_crtc->cursor_bo) {
b295d1b6 6557 if (dev_priv->info->cursor_needs_physical) {
05394f39 6558 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6559 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6560 } else
6561 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6562 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6563 }
80824003 6564
7f9872e0 6565 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6566
6567 intel_crtc->cursor_addr = addr;
05394f39 6568 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6569 intel_crtc->cursor_width = width;
6570 intel_crtc->cursor_height = height;
6571
40ccc72b 6572 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6573
79e53945 6574 return 0;
e7b526bb 6575fail_unpin:
05394f39 6576 i915_gem_object_unpin(obj);
7f9872e0 6577fail_locked:
34b8686e 6578 mutex_unlock(&dev->struct_mutex);
bc9025bd 6579fail:
05394f39 6580 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6581 return ret;
79e53945
JB		 6582}
6583
6584static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6585{
79e53945 6586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6587
cda4b7d3
CW		 6588 intel_crtc->cursor_x = x;
6589 intel_crtc->cursor_y = y;
652c393a 6590
40ccc72b 6591 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6592
6593 return 0;
6594}
6595
6596/** Sets the color ramps on behalf of RandR */
6597void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6598 u16 blue, int regno)
6599{
6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601
6602 intel_crtc->lut_r[regno] = red >> 8;
6603 intel_crtc->lut_g[regno] = green >> 8;
6604 intel_crtc->lut_b[regno] = blue >> 8;
6605}
6606
b8c00ac5
DA		 6607void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6608 u16 *blue, int regno)
6609{
6610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6611
6612 *red = intel_crtc->lut_r[regno] << 8;
6613 *green = intel_crtc->lut_g[regno] << 8;
6614 *blue = intel_crtc->lut_b[regno] << 8;
6615}
6616
79e53945 6617static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6618 u16 *blue, uint32_t start, uint32_t size)
79e53945 6619{
7203425a 6620 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6622
7203425a 6623 for (i = start; i < end; i++) {
79e53945
JB		 6624 intel_crtc->lut_r[i] = red[i] >> 8;
6625 intel_crtc->lut_g[i] = green[i] >> 8;
6626 intel_crtc->lut_b[i] = blue[i] >> 8;
6627 }
6628
6629 intel_crtc_load_lut(crtc);
6630}
6631
79e53945
JB		 6632/* VESA 640x480x72Hz mode to set on the pipe */
6633static struct drm_display_mode load_detect_mode = {
6634 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6635 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6636};
6637
d2dff872
CW		 6638static struct drm_framebuffer *
6639intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6640 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6641 struct drm_i915_gem_object *obj)
6642{
6643 struct intel_framebuffer *intel_fb;
6644 int ret;
6645
6646 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6647 if (!intel_fb) {
6648 drm_gem_object_unreference_unlocked(&obj->base);
6649 return ERR_PTR(-ENOMEM);
6650 }
6651
6652 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6653 if (ret) {
6654 drm_gem_object_unreference_unlocked(&obj->base);
6655 kfree(intel_fb);
6656 return ERR_PTR(ret);
6657 }
6658
6659 return &intel_fb->base;
6660}
6661
6662static u32
6663intel_framebuffer_pitch_for_width(int width, int bpp)
6664{
6665 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6666 return ALIGN(pitch, 64);
6667}
6668
6669static u32
6670intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6671{
6672 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6673 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6674}
6675
6676static struct drm_framebuffer *
6677intel_framebuffer_create_for_mode(struct drm_device *dev,
6678 struct drm_display_mode *mode,
6679 int depth, int bpp)
6680{
6681 struct drm_i915_gem_object *obj;
0fed39bd 6682 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6683
6684 obj = i915_gem_alloc_object(dev,
6685 intel_framebuffer_size_for_mode(mode, bpp));
6686 if (obj == NULL)
6687 return ERR_PTR(-ENOMEM);
6688
6689 mode_cmd.width = mode->hdisplay;
6690 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6691 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6692 bpp);
5ca0c34a 6693 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6694
6695 return intel_framebuffer_create(dev, &mode_cmd, obj);
6696}
6697
6698static struct drm_framebuffer *
6699mode_fits_in_fbdev(struct drm_device *dev,
6700 struct drm_display_mode *mode)
6701{
6702 struct drm_i915_private *dev_priv = dev->dev_private;
6703 struct drm_i915_gem_object *obj;
6704 struct drm_framebuffer *fb;
6705
6706 if (dev_priv->fbdev == NULL)
6707 return NULL;
6708
6709 obj = dev_priv->fbdev->ifb.obj;
6710 if (obj == NULL)
6711 return NULL;
6712
6713 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6714 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6715 fb->bits_per_pixel))
d2dff872
CW		 6716 return NULL;
6717
01f2c773 6718 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6719 return NULL;
6720
6721 return fb;
6722}
6723
d2434ab7 6724bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6725 struct drm_display_mode *mode,
8261b191 6726 struct intel_load_detect_pipe *old)
79e53945
JB		 6727{
6728 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6729 struct intel_encoder *intel_encoder =
6730 intel_attached_encoder(connector);
79e53945 6731 struct drm_crtc *possible_crtc;
4ef69c7a 6732 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6733 struct drm_crtc *crtc = NULL;
6734 struct drm_device *dev = encoder->dev;
94352cf9 6735 struct drm_framebuffer *fb;
79e53945
JB		 6736 int i = -1;
6737
d2dff872
CW		 6738 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6739 connector->base.id, drm_get_connector_name(connector),
6740 encoder->base.id, drm_get_encoder_name(encoder));
6741
79e53945
JB		 6742 /*
6743 * Algorithm gets a little messy:
7a5e4805 6744 *
79e53945
JB		 6745 * - if the connector already has an assigned crtc, use it (but make
6746 * sure it's on first)
7a5e4805 6747 *
79e53945
JB		 6748 * - try to find the first unused crtc that can drive this connector,
6749 * and use that if we find one
79e53945
JB		 6750 */
6751
6752 /* See if we already have a CRTC for this connector */
6753 if (encoder->crtc) {
6754 crtc = encoder->crtc;
8261b191 6755
7b24056b
DV		 6756 mutex_lock(&crtc->mutex);
6757
24218aac 6758 old->dpms_mode = connector->dpms;
8261b191
CW		 6759 old->load_detect_temp = false;
6760
6761 /* Make sure the crtc and connector are running */
24218aac
DV		 6762 if (connector->dpms != DRM_MODE_DPMS_ON)
6763 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6764
7173188d 6765 return true;
79e53945
JB		 6766 }
6767
6768 /* Find an unused one (if possible) */
6769 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6770 i++;
6771 if (!(encoder->possible_crtcs & (1 << i)))
6772 continue;
6773 if (!possible_crtc->enabled) {
6774 crtc = possible_crtc;
6775 break;
6776 }
79e53945
JB		 6777 }
6778
6779 /*
6780 * If we didn't find an unused CRTC, don't use any.
6781 */
6782 if (!crtc) {
7173188d
CW		 6783 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6784 return false;
79e53945
JB		 6785 }
6786
7b24056b 6787 mutex_lock(&crtc->mutex);
fc303101
DV		 6788 intel_encoder->new_crtc = to_intel_crtc(crtc);
6789 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6790
6791 intel_crtc = to_intel_crtc(crtc);
24218aac 6792 old->dpms_mode = connector->dpms;
8261b191 6793 old->load_detect_temp = true;
d2dff872 6794 old->release_fb = NULL;
79e53945 6795
6492711d
CW		 6796 if (!mode)
6797 mode = &load_detect_mode;
79e53945 6798
d2dff872
CW		 6799 /* We need a framebuffer large enough to accommodate all accesses
6800 * that the plane may generate whilst we perform load detection.
6801 * We can not rely on the fbcon either being present (we get called
6802 * during its initialisation to detect all boot displays, or it may
6803 * not even exist) or that it is large enough to satisfy the
6804 * requested mode.
6805 */
94352cf9
DV		 6806 fb = mode_fits_in_fbdev(dev, mode);
6807 if (fb == NULL) {
d2dff872 6808 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6809 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6810 old->release_fb = fb;
d2dff872
CW		 6811 } else
6812 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6813 if (IS_ERR(fb)) {
d2dff872 6814 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6815 mutex_unlock(&crtc->mutex);
0e8b3d3e 6816 return false;
79e53945 6817 }
79e53945 6818
c0c36b94 6819 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6820 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6821 if (old->release_fb)
6822 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6823 mutex_unlock(&crtc->mutex);
0e8b3d3e 6824 return false;
79e53945 6825 }
7173188d 6826
79e53945 6827 /* let the connector get through one full cycle before testing */
9d0498a2 6828 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6829 return true;
79e53945
JB		 6830}
6831
d2434ab7 6832void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6833 struct intel_load_detect_pipe *old)
79e53945 6834{
d2434ab7
DV		 6835 struct intel_encoder *intel_encoder =
6836 intel_attached_encoder(connector);
4ef69c7a 6837 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6838 struct drm_crtc *crtc = encoder->crtc;
79e53945 6839
d2dff872
CW		 6840 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6841 connector->base.id, drm_get_connector_name(connector),
6842 encoder->base.id, drm_get_encoder_name(encoder));
6843
8261b191 6844 if (old->load_detect_temp) {
fc303101
DV		 6845 to_intel_connector(connector)->new_encoder = NULL;
6846 intel_encoder->new_crtc = NULL;
6847 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6848
36206361
DV		 6849 if (old->release_fb) {
6850 drm_framebuffer_unregister_private(old->release_fb);
6851 drm_framebuffer_unreference(old->release_fb);
6852 }
d2dff872 6853
67c96400 6854 mutex_unlock(&crtc->mutex);
0622a53c 6855 return;
79e53945
JB		 6856 }
6857
c751ce4f 6858 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6859 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6860 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6861
6862 mutex_unlock(&crtc->mutex);
79e53945
JB		 6863}
6864
6865/* Returns the clock of the currently programmed mode of the given pipe. */
6866static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6867{
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870 int pipe = intel_crtc->pipe;
548f245b 6871 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6872 u32 fp;
6873 intel_clock_t clock;
6874
6875 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6876 fp = I915_READ(FP0(pipe));
79e53945 6877 else
39adb7a5 6878 fp = I915_READ(FP1(pipe));
79e53945
JB		 6879
6880 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6881 if (IS_PINEVIEW(dev)) {
6882 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6883 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6884 } else {
6885 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6886 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6887 }
6888
a6c45cf0 6889 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6890 if (IS_PINEVIEW(dev))
6891 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6892 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6893 else
6894 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6895 DPLL_FPA01_P1_POST_DIV_SHIFT);
6896
6897 switch (dpll & DPLL_MODE_MASK) {
6898 case DPLLB_MODE_DAC_SERIAL:
6899 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6900 5 : 10;
6901 break;
6902 case DPLLB_MODE_LVDS:
6903 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6904 7 : 14;
6905 break;
6906 default:
28c97730 6907 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6908 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6909 return 0;
6910 }
6911
ac58c3f0
DV		 6912 if (IS_PINEVIEW(dev))
6913 pineview_clock(96000, &clock);
6914 else
6915 i9xx_clock(96000, &clock);
79e53945
JB		 6916 } else {
6917 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6918
6919 if (is_lvds) {
6920 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6921 DPLL_FPA01_P1_POST_DIV_SHIFT);
6922 clock.p2 = 14;
6923
6924 if ((dpll & PLL_REF_INPUT_MASK) ==
6925 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6926 /* XXX: might not be 66MHz */
ac58c3f0 6927 i9xx_clock(66000, &clock);
79e53945 6928 } else
ac58c3f0 6929 i9xx_clock(48000, &clock);
79e53945
JB		 6930 } else {
6931 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6932 clock.p1 = 2;
6933 else {
6934 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6935 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6936 }
6937 if (dpll & PLL_P2_DIVIDE_BY_4)
6938 clock.p2 = 4;
6939 else
6940 clock.p2 = 2;
6941
ac58c3f0 6942 i9xx_clock(48000, &clock);
79e53945
JB		 6943 }
6944 }
6945
6946 /* XXX: It would be nice to validate the clocks, but we can't reuse
6947 * i830PllIsValid() because it relies on the xf86_config connector
6948 * configuration being accurate, which it isn't necessarily.
6949 */
6950
6951 return clock.dot;
6952}
6953
6954/** Returns the currently programmed mode of the given pipe. */
6955struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6956 struct drm_crtc *crtc)
6957{
548f245b 6958 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6960 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6961 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6962 int htot = I915_READ(HTOTAL(cpu_transcoder));
6963 int hsync = I915_READ(HSYNC(cpu_transcoder));
6964 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6965 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6966
6967 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6968 if (!mode)
6969 return NULL;
6970
6971 mode->clock = intel_crtc_clock_get(dev, crtc);
6972 mode->hdisplay = (htot & 0xffff) + 1;
6973 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6974 mode->hsync_start = (hsync & 0xffff) + 1;
6975 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6976 mode->vdisplay = (vtot & 0xffff) + 1;
6977 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6978 mode->vsync_start = (vsync & 0xffff) + 1;
6979 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6980
6981 drm_mode_set_name(mode);
79e53945
JB		 6982
6983 return mode;
6984}
6985
3dec0095 6986static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6987{
6988 struct drm_device *dev = crtc->dev;
6989 drm_i915_private_t *dev_priv = dev->dev_private;
6990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6991 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6992 int dpll_reg = DPLL(pipe);
6993 int dpll;
652c393a 6994
bad720ff 6995 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6996 return;
6997
6998 if (!dev_priv->lvds_downclock_avail)
6999 return;
7000
dbdc6479 7001 dpll = I915_READ(dpll_reg);
652c393a 7002 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7003 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7004
8ac5a6d5 7005 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7006
7007 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7008 I915_WRITE(dpll_reg, dpll);
9d0498a2 7009 intel_wait_for_vblank(dev, pipe);
dbdc6479 7010
652c393a
JB		 7011 dpll = I915_READ(dpll_reg);
7012 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7013 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7014 }
652c393a
JB		 7015}
7016
7017static void intel_decrease_pllclock(struct drm_crtc *crtc)
7018{
7019 struct drm_device *dev = crtc->dev;
7020 drm_i915_private_t *dev_priv = dev->dev_private;
7021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7022
bad720ff 7023 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7024 return;
7025
7026 if (!dev_priv->lvds_downclock_avail)
7027 return;
7028
7029 /*
7030 * Since this is called by a timer, we should never get here in
7031 * the manual case.
7032 */
7033 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7034 int pipe = intel_crtc->pipe;
7035 int dpll_reg = DPLL(pipe);
7036 int dpll;
f6e5b160 7037
44d98a61 7038 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7039
8ac5a6d5 7040 assert_panel_unlocked(dev_priv, pipe);
652c393a 7041
dc257cf1 7042 dpll = I915_READ(dpll_reg);
652c393a
JB		 7043 dpll |= DISPLAY_RATE_SELECT_FPA1;
7044 I915_WRITE(dpll_reg, dpll);
9d0498a2 7045 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7046 dpll = I915_READ(dpll_reg);
7047 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7048 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7049 }
7050
7051}
7052
f047e395
CW		 7053void intel_mark_busy(struct drm_device *dev)
7054{
f047e395
CW		 7055 i915_update_gfx_val(dev->dev_private);
7056}
7057
7058void intel_mark_idle(struct drm_device *dev)
652c393a 7059{
652c393a 7060 struct drm_crtc *crtc;
652c393a
JB		 7061
7062 if (!i915_powersave)
7063 return;
7064
652c393a 7065 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7066 if (!crtc->fb)
7067 continue;
7068
725a5b54 7069 intel_decrease_pllclock(crtc);
652c393a 7070 }
652c393a
JB		 7071}
7072
c65355bb
CW		 7073void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7074 struct intel_ring_buffer *ring)
652c393a 7075{
f047e395
CW		 7076 struct drm_device *dev = obj->base.dev;
7077 struct drm_crtc *crtc;
652c393a 7078
f047e395 7079 if (!i915_powersave)
acb87dfb
CW		 7080 return;
7081
652c393a
JB		 7082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7083 if (!crtc->fb)
7084 continue;
7085
c65355bb
CW		 7086 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7087 continue;
7088
7089 intel_increase_pllclock(crtc);
7090 if (ring && intel_fbc_enabled(dev))
7091 ring->fbc_dirty = true;
652c393a
JB		 7092 }
7093}
7094
79e53945
JB		 7095static void intel_crtc_destroy(struct drm_crtc *crtc)
7096{
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7098 struct drm_device *dev = crtc->dev;
7099 struct intel_unpin_work *work;
7100 unsigned long flags;
7101
7102 spin_lock_irqsave(&dev->event_lock, flags);
7103 work = intel_crtc->unpin_work;
7104 intel_crtc->unpin_work = NULL;
7105 spin_unlock_irqrestore(&dev->event_lock, flags);
7106
7107 if (work) {
7108 cancel_work_sync(&work->work);
7109 kfree(work);
7110 }
79e53945 7111
40ccc72b
MK		 7112 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7113
79e53945 7114 drm_crtc_cleanup(crtc);
67e77c5a 7115
79e53945
JB		 7116 kfree(intel_crtc);
7117}
7118
6b95a207
KH		 7119static void intel_unpin_work_fn(struct work_struct *__work)
7120{
7121 struct intel_unpin_work *work =
7122 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7123 struct drm_device *dev = work->crtc->dev;
6b95a207 7124
b4a98e57 7125 mutex_lock(&dev->struct_mutex);
1690e1eb 7126 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7127 drm_gem_object_unreference(&work->pending_flip_obj->base);
7128 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7129
b4a98e57
CW		 7130 intel_update_fbc(dev);
7131 mutex_unlock(&dev->struct_mutex);
7132
7133 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7134 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7135
6b95a207
KH		 7136 kfree(work);
7137}
7138
1afe3e9d 7139static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7140 struct drm_crtc *crtc)
6b95a207
KH		 7141{
7142 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7144 struct intel_unpin_work *work;
6b95a207
KH		 7145 unsigned long flags;
7146
7147 /* Ignore early vblank irqs */
7148 if (intel_crtc == NULL)
7149 return;
7150
7151 spin_lock_irqsave(&dev->event_lock, flags);
7152 work = intel_crtc->unpin_work;
e7d841ca
CW		 7153
7154 /* Ensure we don't miss a work->pending update ... */
7155 smp_rmb();
7156
7157 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7158 spin_unlock_irqrestore(&dev->event_lock, flags);
7159 return;
7160 }
7161
e7d841ca
CW		 7162 /* and that the unpin work is consistent wrt ->pending. */
7163 smp_rmb();
7164
6b95a207 7165 intel_crtc->unpin_work = NULL;
6b95a207 7166
45a066eb
RC		 7167 if (work->event)
7168 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7169
0af7e4df
MK		 7170 drm_vblank_put(dev, intel_crtc->pipe);
7171
6b95a207
KH		 7172 spin_unlock_irqrestore(&dev->event_lock, flags);
7173
2c10d571 7174 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7175
7176 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7177
7178 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7179}
7180
1afe3e9d
JB		 7181void intel_finish_page_flip(struct drm_device *dev, int pipe)
7182{
7183 drm_i915_private_t *dev_priv = dev->dev_private;
7184 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7185
49b14a5c 7186 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7187}
7188
7189void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7190{
7191 drm_i915_private_t *dev_priv = dev->dev_private;
7192 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7193
49b14a5c 7194 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7195}
7196
6b95a207
KH		 7197void intel_prepare_page_flip(struct drm_device *dev, int plane)
7198{
7199 drm_i915_private_t *dev_priv = dev->dev_private;
7200 struct intel_crtc *intel_crtc =
7201 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7202 unsigned long flags;
7203
e7d841ca
CW		 7204 /* NB: An MMIO update of the plane base pointer will also
7205 * generate a page-flip completion irq, i.e. every modeset
7206 * is also accompanied by a spurious intel_prepare_page_flip().
7207 */
6b95a207 7208 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7209 if (intel_crtc->unpin_work)
7210 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7211 spin_unlock_irqrestore(&dev->event_lock, flags);
7212}
7213
e7d841ca
CW		 7214inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7215{
7216 /* Ensure that the work item is consistent when activating it ... */
7217 smp_wmb();
7218 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7219 /* and that it is marked active as soon as the irq could fire. */
7220 smp_wmb();
7221}
7222
8c9f3aaf
JB		 7223static int intel_gen2_queue_flip(struct drm_device *dev,
7224 struct drm_crtc *crtc,
7225 struct drm_framebuffer *fb,
7226 struct drm_i915_gem_object *obj)
7227{
7228 struct drm_i915_private *dev_priv = dev->dev_private;
7229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7230 u32 flip_mask;
6d90c952 7231 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7232 int ret;
7233
6d90c952 7234 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7235 if (ret)
83d4092b 7236 goto err;
8c9f3aaf 7237
6d90c952 7238 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7239 if (ret)
83d4092b 7240 goto err_unpin;
8c9f3aaf
JB		 7241
7242 /* Can't queue multiple flips, so wait for the previous
7243 * one to finish before executing the next.
7244 */
7245 if (intel_crtc->plane)
7246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7247 else
7248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7250 intel_ring_emit(ring, MI_NOOP);
7251 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7253 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7254 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7255 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7256
7257 intel_mark_page_flip_active(intel_crtc);
6d90c952 7258 intel_ring_advance(ring);
83d4092b
CW		 7259 return 0;
7260
7261err_unpin:
7262 intel_unpin_fb_obj(obj);
7263err:
8c9f3aaf
JB		 7264 return ret;
7265}
7266
7267static int intel_gen3_queue_flip(struct drm_device *dev,
7268 struct drm_crtc *crtc,
7269 struct drm_framebuffer *fb,
7270 struct drm_i915_gem_object *obj)
7271{
7272 struct drm_i915_private *dev_priv = dev->dev_private;
7273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7274 u32 flip_mask;
6d90c952 7275 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7276 int ret;
7277
6d90c952 7278 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7279 if (ret)
83d4092b 7280 goto err;
8c9f3aaf 7281
6d90c952 7282 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7283 if (ret)
83d4092b 7284 goto err_unpin;
8c9f3aaf
JB		 7285
7286 if (intel_crtc->plane)
7287 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7288 else
7289 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7290 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7291 intel_ring_emit(ring, MI_NOOP);
7292 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7293 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7294 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7295 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7296 intel_ring_emit(ring, MI_NOOP);
7297
e7d841ca 7298 intel_mark_page_flip_active(intel_crtc);
6d90c952 7299 intel_ring_advance(ring);
83d4092b
CW		 7300 return 0;
7301
7302err_unpin:
7303 intel_unpin_fb_obj(obj);
7304err:
8c9f3aaf
JB		 7305 return ret;
7306}
7307
7308static int intel_gen4_queue_flip(struct drm_device *dev,
7309 struct drm_crtc *crtc,
7310 struct drm_framebuffer *fb,
7311 struct drm_i915_gem_object *obj)
7312{
7313 struct drm_i915_private *dev_priv = dev->dev_private;
7314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7315 uint32_t pf, pipesrc;
6d90c952 7316 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7317 int ret;
7318
6d90c952 7319 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7320 if (ret)
83d4092b 7321 goto err;
8c9f3aaf 7322
6d90c952 7323 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7324 if (ret)
83d4092b 7325 goto err_unpin;
8c9f3aaf
JB		 7326
7327 /* i965+ uses the linear or tiled offsets from the
7328 * Display Registers (which do not change across a page-flip)
7329 * so we need only reprogram the base address.
7330 */
6d90c952
DV		 7331 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7332 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7333 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7334 intel_ring_emit(ring,
7335 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7336 obj->tiling_mode);
8c9f3aaf
JB		 7337
7338 /* XXX Enabling the panel-fitter across page-flip is so far
7339 * untested on non-native modes, so ignore it for now.
7340 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7341 */
7342 pf = 0;
7343 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7344 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7345
7346 intel_mark_page_flip_active(intel_crtc);
6d90c952 7347 intel_ring_advance(ring);
83d4092b
CW		 7348 return 0;
7349
7350err_unpin:
7351 intel_unpin_fb_obj(obj);
7352err:
8c9f3aaf
JB		 7353 return ret;
7354}
7355
7356static int intel_gen6_queue_flip(struct drm_device *dev,
7357 struct drm_crtc *crtc,
7358 struct drm_framebuffer *fb,
7359 struct drm_i915_gem_object *obj)
7360{
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7363 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7364 uint32_t pf, pipesrc;
7365 int ret;
7366
6d90c952 7367 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7368 if (ret)
83d4092b 7369 goto err;
8c9f3aaf 7370
6d90c952 7371 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7372 if (ret)
83d4092b 7373 goto err_unpin;
8c9f3aaf 7374
6d90c952
DV		 7375 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7376 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7377 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7378 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7379
dc257cf1
DV		 7380 /* Contrary to the suggestions in the documentation,
7381 * "Enable Panel Fitter" does not seem to be required when page
7382 * flipping with a non-native mode, and worse causes a normal
7383 * modeset to fail.
7384 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7385 */
7386 pf = 0;
8c9f3aaf 7387 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7388 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7389
7390 intel_mark_page_flip_active(intel_crtc);
6d90c952 7391 intel_ring_advance(ring);
83d4092b
CW		 7392 return 0;
7393
7394err_unpin:
7395 intel_unpin_fb_obj(obj);
7396err:
8c9f3aaf
JB		 7397 return ret;
7398}
7399
7c9017e5
JB		 7400/*
7401 * On gen7 we currently use the blit ring because (in early silicon at least)
7402 * the render ring doesn't give us interrpts for page flip completion, which
7403 * means clients will hang after the first flip is queued. Fortunately the
7404 * blit ring generates interrupts properly, so use it instead.
7405 */
7406static int intel_gen7_queue_flip(struct drm_device *dev,
7407 struct drm_crtc *crtc,
7408 struct drm_framebuffer *fb,
7409 struct drm_i915_gem_object *obj)
7410{
7411 struct drm_i915_private *dev_priv = dev->dev_private;
7412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7414 uint32_t plane_bit = 0;
7c9017e5
JB		 7415 int ret;
7416
7417 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7418 if (ret)
83d4092b 7419 goto err;
7c9017e5 7420
cb05d8de
DV		 7421 switch(intel_crtc->plane) {
7422 case PLANE_A:
7423 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7424 break;
7425 case PLANE_B:
7426 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7427 break;
7428 case PLANE_C:
7429 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7430 break;
7431 default:
7432 WARN_ONCE(1, "unknown plane in flip command\n");
7433 ret = -ENODEV;
ab3951eb 7434 goto err_unpin;
cb05d8de
DV		 7435 }
7436
7c9017e5
JB		 7437 ret = intel_ring_begin(ring, 4);
7438 if (ret)
83d4092b 7439 goto err_unpin;
7c9017e5 7440
cb05d8de 7441 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7442 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7443 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7444 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7445
7446 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7447 intel_ring_advance(ring);
83d4092b
CW		 7448 return 0;
7449
7450err_unpin:
7451 intel_unpin_fb_obj(obj);
7452err:
7c9017e5
JB		 7453 return ret;
7454}
7455
8c9f3aaf
JB		 7456static int intel_default_queue_flip(struct drm_device *dev,
7457 struct drm_crtc *crtc,
7458 struct drm_framebuffer *fb,
7459 struct drm_i915_gem_object *obj)
7460{
7461 return -ENODEV;
7462}
7463
6b95a207
KH		 7464static int intel_crtc_page_flip(struct drm_crtc *crtc,
7465 struct drm_framebuffer *fb,
7466 struct drm_pending_vblank_event *event)
7467{
7468 struct drm_device *dev = crtc->dev;
7469 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7470 struct drm_framebuffer *old_fb = crtc->fb;
7471 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7473 struct intel_unpin_work *work;
8c9f3aaf 7474 unsigned long flags;
52e68630 7475 int ret;
6b95a207 7476
e6a595d2
VS		 7477 /* Can't change pixel format via MI display flips. */
7478 if (fb->pixel_format != crtc->fb->pixel_format)
7479 return -EINVAL;
7480
7481 /*
7482 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7483 * Note that pitch changes could also affect these register.
7484 */
7485 if (INTEL_INFO(dev)->gen > 3 &&
7486 (fb->offsets[0] != crtc->fb->offsets[0] ||
7487 fb->pitches[0] != crtc->fb->pitches[0]))
7488 return -EINVAL;
7489
6b95a207
KH		 7490 work = kzalloc(sizeof *work, GFP_KERNEL);
7491 if (work == NULL)
7492 return -ENOMEM;
7493
6b95a207 7494 work->event = event;
b4a98e57 7495 work->crtc = crtc;
4a35f83b 7496 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7497 INIT_WORK(&work->work, intel_unpin_work_fn);
7498
7317c75e
JB		 7499 ret = drm_vblank_get(dev, intel_crtc->pipe);
7500 if (ret)
7501 goto free_work;
7502
6b95a207
KH		 7503 /* We borrow the event spin lock for protecting unpin_work */
7504 spin_lock_irqsave(&dev->event_lock, flags);
7505 if (intel_crtc->unpin_work) {
7506 spin_unlock_irqrestore(&dev->event_lock, flags);
7507 kfree(work);
7317c75e 7508 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7509
7510 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7511 return -EBUSY;
7512 }
7513 intel_crtc->unpin_work = work;
7514 spin_unlock_irqrestore(&dev->event_lock, flags);
7515
b4a98e57
CW		 7516 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7517 flush_workqueue(dev_priv->wq);
7518
79158103
CW		 7519 ret = i915_mutex_lock_interruptible(dev);
7520 if (ret)
7521 goto cleanup;
6b95a207 7522
75dfca80 7523 /* Reference the objects for the scheduled work. */
05394f39
CW		 7524 drm_gem_object_reference(&work->old_fb_obj->base);
7525 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7526
7527 crtc->fb = fb;
96b099fd 7528
e1f99ce6 7529 work->pending_flip_obj = obj;
e1f99ce6 7530
4e5359cd
SF		 7531 work->enable_stall_check = true;
7532
b4a98e57 7533 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7534 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7535
8c9f3aaf
JB		 7536 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7537 if (ret)
7538 goto cleanup_pending;
6b95a207 7539
7782de3b 7540 intel_disable_fbc(dev);
c65355bb 7541 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7542 mutex_unlock(&dev->struct_mutex);
7543
e5510fac
JB		 7544 trace_i915_flip_request(intel_crtc->plane, obj);
7545
6b95a207 7546 return 0;
96b099fd 7547
8c9f3aaf 7548cleanup_pending:
b4a98e57 7549 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7550 crtc->fb = old_fb;
05394f39
CW		 7551 drm_gem_object_unreference(&work->old_fb_obj->base);
7552 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7553 mutex_unlock(&dev->struct_mutex);
7554
79158103 7555cleanup:
96b099fd
CW		 7556 spin_lock_irqsave(&dev->event_lock, flags);
7557 intel_crtc->unpin_work = NULL;
7558 spin_unlock_irqrestore(&dev->event_lock, flags);
7559
7317c75e
JB		 7560 drm_vblank_put(dev, intel_crtc->pipe);
7561free_work:
96b099fd
CW		 7562 kfree(work);
7563
7564 return ret;
6b95a207
KH		 7565}
7566
f6e5b160 7567static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7568 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7569 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7570};
7571
50f56119
DV		 7572static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7573 struct drm_crtc *crtc)
7574{
7575 struct drm_device *dev;
7576 struct drm_crtc *tmp;
7577 int crtc_mask = 1;
47f1c6c9 7578
50f56119 7579 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7580
50f56119 7581 dev = crtc->dev;
47f1c6c9 7582
50f56119
DV		 7583 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7584 if (tmp == crtc)
7585 break;
7586 crtc_mask <<= 1;
7587 }
47f1c6c9 7588
50f56119
DV		 7589 if (encoder->possible_crtcs & crtc_mask)
7590 return true;
7591 return false;
47f1c6c9 7592}
79e53945 7593
9a935856
DV		 7594/**
7595 * intel_modeset_update_staged_output_state
7596 *
7597 * Updates the staged output configuration state, e.g. after we've read out the
7598 * current hw state.
7599 */
7600static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7601{
9a935856
DV		 7602 struct intel_encoder *encoder;
7603 struct intel_connector *connector;
f6e5b160 7604
9a935856
DV		 7605 list_for_each_entry(connector, &dev->mode_config.connector_list,
7606 base.head) {
7607 connector->new_encoder =
7608 to_intel_encoder(connector->base.encoder);
7609 }
f6e5b160 7610
9a935856
DV		 7611 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7612 base.head) {
7613 encoder->new_crtc =
7614 to_intel_crtc(encoder->base.crtc);
7615 }
f6e5b160
CW		 7616}
7617
9a935856
DV		 7618/**
7619 * intel_modeset_commit_output_state
7620 *
7621 * This function copies the stage display pipe configuration to the real one.
7622 */
7623static void intel_modeset_commit_output_state(struct drm_device *dev)
7624{
7625 struct intel_encoder *encoder;
7626 struct intel_connector *connector;
f6e5b160 7627
9a935856
DV		 7628 list_for_each_entry(connector, &dev->mode_config.connector_list,
7629 base.head) {
7630 connector->base.encoder = &connector->new_encoder->base;
7631 }
f6e5b160 7632
9a935856
DV		 7633 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7634 base.head) {
7635 encoder->base.crtc = &encoder->new_crtc->base;
7636 }
7637}
7638
050f7aeb
DV		 7639static void
7640connected_sink_compute_bpp(struct intel_connector * connector,
7641 struct intel_crtc_config *pipe_config)
7642{
7643 int bpp = pipe_config->pipe_bpp;
7644
7645 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7646 connector->base.base.id,
7647 drm_get_connector_name(&connector->base));
7648
7649 /* Don't use an invalid EDID bpc value */
7650 if (connector->base.display_info.bpc &&
7651 connector->base.display_info.bpc * 3 < bpp) {
7652 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7653 bpp, connector->base.display_info.bpc*3);
7654 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7655 }
7656
7657 /* Clamp bpp to 8 on screens without EDID 1.4 */
7658 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7659 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7660 bpp);
7661 pipe_config->pipe_bpp = 24;
7662 }
7663}
7664
4e53c2e0 7665static int
050f7aeb
DV		 7666compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7667 struct drm_framebuffer *fb,
7668 struct intel_crtc_config *pipe_config)
4e53c2e0 7669{
050f7aeb
DV		 7670 struct drm_device *dev = crtc->base.dev;
7671 struct intel_connector *connector;
4e53c2e0
DV		 7672 int bpp;
7673
d42264b1
DV		 7674 switch (fb->pixel_format) {
7675 case DRM_FORMAT_C8:
4e53c2e0
DV		 7676 bpp = 8*3; /* since we go through a colormap */
7677 break;
d42264b1
DV		 7678 case DRM_FORMAT_XRGB1555:
7679 case DRM_FORMAT_ARGB1555:
7680 /* checked in intel_framebuffer_init already */
7681 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7682 return -EINVAL;
7683 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7684 bpp = 6*3; /* min is 18bpp */
7685 break;
d42264b1
DV		 7686 case DRM_FORMAT_XBGR8888:
7687 case DRM_FORMAT_ABGR8888:
7688 /* checked in intel_framebuffer_init already */
7689 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7690 return -EINVAL;
7691 case DRM_FORMAT_XRGB8888:
7692 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7693 bpp = 8*3;
7694 break;
d42264b1
DV		 7695 case DRM_FORMAT_XRGB2101010:
7696 case DRM_FORMAT_ARGB2101010:
7697 case DRM_FORMAT_XBGR2101010:
7698 case DRM_FORMAT_ABGR2101010:
7699 /* checked in intel_framebuffer_init already */
7700 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7701 return -EINVAL;
4e53c2e0
DV		 7702 bpp = 10*3;
7703 break;
baba133a 7704 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7705 default:
7706 DRM_DEBUG_KMS("unsupported depth\n");
7707 return -EINVAL;
7708 }
7709
4e53c2e0
DV		 7710 pipe_config->pipe_bpp = bpp;
7711
7712 /* Clamp display bpp to EDID value */
7713 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7714 base.head) {
1b829e05
DV		 7715 if (!connector->new_encoder ||
7716 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7717 continue;
7718
050f7aeb 7719 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7720 }
7721
7722 return bpp;
7723}
7724
c0b03411
DV		 7725static void intel_dump_pipe_config(struct intel_crtc *crtc,
7726 struct intel_crtc_config *pipe_config,
7727 const char *context)
7728{
7729 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7730 context, pipe_name(crtc->pipe));
7731
7732 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7733 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7734 pipe_config->pipe_bpp, pipe_config->dither);
7735 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7736 pipe_config->has_pch_encoder,
7737 pipe_config->fdi_lanes,
7738 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7739 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7740 pipe_config->fdi_m_n.tu);
7741 DRM_DEBUG_KMS("requested mode:\n");
7742 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7743 DRM_DEBUG_KMS("adjusted mode:\n");
7744 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7745 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7746 pipe_config->gmch_pfit.control,
7747 pipe_config->gmch_pfit.pgm_ratios,
7748 pipe_config->gmch_pfit.lvds_border_bits);
7749 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7750 pipe_config->pch_pfit.pos,
7751 pipe_config->pch_pfit.size);
42db64ef 7752 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7753}
7754
accfc0c5
DV		 7755static bool check_encoder_cloning(struct drm_crtc *crtc)
7756{
7757 int num_encoders = 0;
7758 bool uncloneable_encoders = false;
7759 struct intel_encoder *encoder;
7760
7761 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7762 base.head) {
7763 if (&encoder->new_crtc->base != crtc)
7764 continue;
7765
7766 num_encoders++;
7767 if (!encoder->cloneable)
7768 uncloneable_encoders = true;
7769 }
7770
7771 return !(num_encoders > 1 && uncloneable_encoders);
7772}
7773
b8cecdf5
DV		 7774static struct intel_crtc_config *
7775intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7776 struct drm_framebuffer *fb,
b8cecdf5 7777 struct drm_display_mode *mode)
ee7b9f93 7778{
7758a113 7779 struct drm_device *dev = crtc->dev;
7758a113
DV		 7780 struct drm_encoder_helper_funcs *encoder_funcs;
7781 struct intel_encoder *encoder;
b8cecdf5 7782 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7783 int plane_bpp, ret = -EINVAL;
7784 bool retry = true;
ee7b9f93 7785
accfc0c5
DV		 7786 if (!check_encoder_cloning(crtc)) {
7787 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7788 return ERR_PTR(-EINVAL);
7789 }
7790
b8cecdf5
DV		 7791 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7792 if (!pipe_config)
7758a113
DV		 7793 return ERR_PTR(-ENOMEM);
7794
b8cecdf5
DV		 7795 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7796 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7797 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7798 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7799
050f7aeb
DV		 7800 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7801 * plane pixel format and any sink constraints into account. Returns the
7802 * source plane bpp so that dithering can be selected on mismatches
7803 * after encoders and crtc also have had their say. */
7804 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7805 fb, pipe_config);
4e53c2e0
DV		 7806 if (plane_bpp < 0)
7807 goto fail;
7808
e29c22c0 7809encoder_retry:
ef1b460d 7810 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7811 pipe_config->port_clock = 0;
ef1b460d 7812 pipe_config->pixel_multiplier = 1;
ff9a6750 7813
7758a113
DV		 7814 /* Pass our mode to the connectors and the CRTC to give them a chance to
7815 * adjust it according to limitations or connector properties, and also
7816 * a chance to reject the mode entirely.
47f1c6c9 7817 */
7758a113
DV		 7818 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7819 base.head) {
47f1c6c9 7820
7758a113
DV		 7821 if (&encoder->new_crtc->base != crtc)
7822 continue;
7ae89233
DV		 7823
7824 if (encoder->compute_config) {
7825 if (!(encoder->compute_config(encoder, pipe_config))) {
7826 DRM_DEBUG_KMS("Encoder config failure\n");
7827 goto fail;
7828 }
7829
7830 continue;
7831 }
7832
7758a113 7833 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7834 if (!(encoder_funcs->mode_fixup(&encoder->base,
7835 &pipe_config->requested_mode,
7836 &pipe_config->adjusted_mode))) {
7758a113
DV		 7837 DRM_DEBUG_KMS("Encoder fixup failed\n");
7838 goto fail;
7839 }
ee7b9f93 7840 }
47f1c6c9 7841
ff9a6750
DV		 7842 /* Set default port clock if not overwritten by the encoder. Needs to be
7843 * done afterwards in case the encoder adjusts the mode. */
7844 if (!pipe_config->port_clock)
7845 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7846
a43f6e0f 7847 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7848 if (ret < 0) {
7758a113
DV		 7849 DRM_DEBUG_KMS("CRTC fixup failed\n");
7850 goto fail;
ee7b9f93 7851 }
e29c22c0
DV		 7852
7853 if (ret == RETRY) {
7854 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7855 ret = -EINVAL;
7856 goto fail;
7857 }
7858
7859 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7860 retry = false;
7861 goto encoder_retry;
7862 }
7863
4e53c2e0
DV		 7864 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7865 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7866 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7867
b8cecdf5 7868 return pipe_config;
7758a113 7869fail:
b8cecdf5 7870 kfree(pipe_config);
e29c22c0 7871 return ERR_PTR(ret);
ee7b9f93 7872}
47f1c6c9 7873
e2e1ed41
DV		 7874/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7875 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7876static void
7877intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7878 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7879{
7880 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7881 struct drm_device *dev = crtc->dev;
7882 struct intel_encoder *encoder;
7883 struct intel_connector *connector;
7884 struct drm_crtc *tmp_crtc;
79e53945 7885
e2e1ed41 7886 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7887
e2e1ed41
DV		 7888 /* Check which crtcs have changed outputs connected to them, these need
7889 * to be part of the prepare_pipes mask. We don't (yet) support global
7890 * modeset across multiple crtcs, so modeset_pipes will only have one
7891 * bit set at most. */
7892 list_for_each_entry(connector, &dev->mode_config.connector_list,
7893 base.head) {
7894 if (connector->base.encoder == &connector->new_encoder->base)
7895 continue;
79e53945 7896
e2e1ed41
DV		 7897 if (connector->base.encoder) {
7898 tmp_crtc = connector->base.encoder->crtc;
7899
7900 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7901 }
7902
7903 if (connector->new_encoder)
7904 *prepare_pipes |=
7905 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7906 }
7907
e2e1ed41
DV		 7908 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7909 base.head) {
7910 if (encoder->base.crtc == &encoder->new_crtc->base)
7911 continue;
7912
7913 if (encoder->base.crtc) {
7914 tmp_crtc = encoder->base.crtc;
7915
7916 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7917 }
7918
7919 if (encoder->new_crtc)
7920 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7921 }
7922
e2e1ed41
DV		 7923 /* Check for any pipes that will be fully disabled ... */
7924 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7925 base.head) {
7926 bool used = false;
22fd0fab 7927
e2e1ed41
DV		 7928 /* Don't try to disable disabled crtcs. */
7929 if (!intel_crtc->base.enabled)
7930 continue;
7e7d76c3 7931
e2e1ed41
DV		 7932 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7933 base.head) {
7934 if (encoder->new_crtc == intel_crtc)
7935 used = true;
7936 }
7937
7938 if (!used)
7939 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7940 }
7941
e2e1ed41
DV		 7942
7943 /* set_mode is also used to update properties on life display pipes. */
7944 intel_crtc = to_intel_crtc(crtc);
7945 if (crtc->enabled)
7946 *prepare_pipes |= 1 << intel_crtc->pipe;
7947
b6c5164d
DV		 7948 /*
7949 * For simplicity do a full modeset on any pipe where the output routing
7950 * changed. We could be more clever, but that would require us to be
7951 * more careful with calling the relevant encoder->mode_set functions.
7952 */
e2e1ed41
DV		 7953 if (*prepare_pipes)
7954 *modeset_pipes = *prepare_pipes;
7955
7956 /* ... and mask these out. */
7957 *modeset_pipes &= ~(*disable_pipes);
7958 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7959
7960 /*
7961 * HACK: We don't (yet) fully support global modesets. intel_set_config
7962 * obies this rule, but the modeset restore mode of
7963 * intel_modeset_setup_hw_state does not.
7964 */
7965 *modeset_pipes &= 1 << intel_crtc->pipe;
7966 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7967
7968 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7969 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7970}
79e53945 7971
ea9d758d 7972static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7973{
ea9d758d 7974 struct drm_encoder *encoder;
f6e5b160 7975 struct drm_device *dev = crtc->dev;
f6e5b160 7976
ea9d758d
DV		 7977 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7978 if (encoder->crtc == crtc)
7979 return true;
7980
7981 return false;
7982}
7983
7984static void
7985intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7986{
7987 struct intel_encoder *intel_encoder;
7988 struct intel_crtc *intel_crtc;
7989 struct drm_connector *connector;
7990
7991 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7992 base.head) {
7993 if (!intel_encoder->base.crtc)
7994 continue;
7995
7996 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7997
7998 if (prepare_pipes & (1 << intel_crtc->pipe))
7999 intel_encoder->connectors_active = false;
8000 }
8001
8002 intel_modeset_commit_output_state(dev);
8003
8004 /* Update computed state. */
8005 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8006 base.head) {
8007 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8008 }
8009
8010 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8011 if (!connector->encoder || !connector->encoder->crtc)
8012 continue;
8013
8014 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8015
8016 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8017 struct drm_property *dpms_property =
8018 dev->mode_config.dpms_property;
8019
ea9d758d 8020 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8021 drm_object_property_set_value(&connector->base,
68d34720
DV		 8022 dpms_property,
8023 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8024
8025 intel_encoder = to_intel_encoder(connector->encoder);
8026 intel_encoder->connectors_active = true;
8027 }
8028 }
8029
8030}
8031
25c5b266
DV		 8032#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8033 list_for_each_entry((intel_crtc), \
8034 &(dev)->mode_config.crtc_list, \
8035 base.head) \
0973f18f 8036 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8037
0e8ffe1b 8038static bool
2fa2fe9a
DV		 8039intel_pipe_config_compare(struct drm_device *dev,
8040 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8041 struct intel_crtc_config *pipe_config)
8042{
66e985c0
DV		 8043#define PIPE_CONF_CHECK_X(name) \
8044 if (current_config->name != pipe_config->name) { \
8045 DRM_ERROR("mismatch in " #name " " \
8046 "(expected 0x%08x, found 0x%08x)\n", \
8047 current_config->name, \
8048 pipe_config->name); \
8049 return false; \
8050 }
8051
08a24034
DV		 8052#define PIPE_CONF_CHECK_I(name) \
8053 if (current_config->name != pipe_config->name) { \
8054 DRM_ERROR("mismatch in " #name " " \
8055 "(expected %i, found %i)\n", \
8056 current_config->name, \
8057 pipe_config->name); \
8058 return false; \
88adfff1
DV		 8059 }
8060
1bd1bd80
DV		 8061#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8062 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8063 DRM_ERROR("mismatch in " #name " " \
8064 "(expected %i, found %i)\n", \
8065 current_config->name & (mask), \
8066 pipe_config->name & (mask)); \
8067 return false; \
8068 }
8069
bb760063
DV		 8070#define PIPE_CONF_QUIRK(quirk) \
8071 ((current_config->quirks | pipe_config->quirks) & (quirk))
8072
eccb140b
DV		 8073 PIPE_CONF_CHECK_I(cpu_transcoder);
8074
08a24034
DV		 8075 PIPE_CONF_CHECK_I(has_pch_encoder);
8076 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8077 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8078 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8079 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8080 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8081 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8082
1bd1bd80
DV		 8083 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8084 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8085 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8086 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8087 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8088 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8089
8090 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8091 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8092 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8093 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8094 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8095 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8096
6c49f241
DV		 8097 if (!HAS_PCH_SPLIT(dev))
8098 PIPE_CONF_CHECK_I(pixel_multiplier);
8099
1bd1bd80
DV		 8100 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8101 DRM_MODE_FLAG_INTERLACE);
8102
bb760063
DV		 8103 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8104 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8105 DRM_MODE_FLAG_PHSYNC);
8106 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8107 DRM_MODE_FLAG_NHSYNC);
8108 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8109 DRM_MODE_FLAG_PVSYNC);
8110 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8111 DRM_MODE_FLAG_NVSYNC);
8112 }
045ac3b5 8113
1bd1bd80
DV		 8114 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8115 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8116
2fa2fe9a
DV		 8117 PIPE_CONF_CHECK_I(gmch_pfit.control);
8118 /* pfit ratios are autocomputed by the hw on gen4+ */
8119 if (INTEL_INFO(dev)->gen < 4)
8120 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8121 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8122 PIPE_CONF_CHECK_I(pch_pfit.pos);
8123 PIPE_CONF_CHECK_I(pch_pfit.size);
8124
42db64ef
PZ		 8125 PIPE_CONF_CHECK_I(ips_enabled);
8126
c0d43d62 8127 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0
DV		 8128 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8129 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8130 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8131
66e985c0 8132#undef PIPE_CONF_CHECK_X
08a24034 8133#undef PIPE_CONF_CHECK_I
1bd1bd80 8134#undef PIPE_CONF_CHECK_FLAGS
bb760063 8135#undef PIPE_CONF_QUIRK
88adfff1 8136
0e8ffe1b
DV		 8137 return true;
8138}
8139
91d1b4bd
DV		 8140static void
8141check_connector_state(struct drm_device *dev)
8af6cf88 8142{
8af6cf88
DV		 8143 struct intel_connector *connector;
8144
8145 list_for_each_entry(connector, &dev->mode_config.connector_list,
8146 base.head) {
8147 /* This also checks the encoder/connector hw state with the
8148 * ->get_hw_state callbacks. */
8149 intel_connector_check_state(connector);
8150
8151 WARN(&connector->new_encoder->base != connector->base.encoder,
8152 "connector's staged encoder doesn't match current encoder\n");
8153 }
91d1b4bd
DV		 8154}
8155
8156static void
8157check_encoder_state(struct drm_device *dev)
8158{
8159 struct intel_encoder *encoder;
8160 struct intel_connector *connector;
8af6cf88
DV		 8161
8162 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8163 base.head) {
8164 bool enabled = false;
8165 bool active = false;
8166 enum pipe pipe, tracked_pipe;
8167
8168 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8169 encoder->base.base.id,
8170 drm_get_encoder_name(&encoder->base));
8171
8172 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8173 "encoder's stage crtc doesn't match current crtc\n");
8174 WARN(encoder->connectors_active && !encoder->base.crtc,
8175 "encoder's active_connectors set, but no crtc\n");
8176
8177 list_for_each_entry(connector, &dev->mode_config.connector_list,
8178 base.head) {
8179 if (connector->base.encoder != &encoder->base)
8180 continue;
8181 enabled = true;
8182 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8183 active = true;
8184 }
8185 WARN(!!encoder->base.crtc != enabled,
8186 "encoder's enabled state mismatch "
8187 "(expected %i, found %i)\n",
8188 !!encoder->base.crtc, enabled);
8189 WARN(active && !encoder->base.crtc,
8190 "active encoder with no crtc\n");
8191
8192 WARN(encoder->connectors_active != active,
8193 "encoder's computed active state doesn't match tracked active state "
8194 "(expected %i, found %i)\n", active, encoder->connectors_active);
8195
8196 active = encoder->get_hw_state(encoder, &pipe);
8197 WARN(active != encoder->connectors_active,
8198 "encoder's hw state doesn't match sw tracking "
8199 "(expected %i, found %i)\n",
8200 encoder->connectors_active, active);
8201
8202 if (!encoder->base.crtc)
8203 continue;
8204
8205 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8206 WARN(active && pipe != tracked_pipe,
8207 "active encoder's pipe doesn't match"
8208 "(expected %i, found %i)\n",
8209 tracked_pipe, pipe);
8210
8211 }
91d1b4bd
DV		 8212}
8213
8214static void
8215check_crtc_state(struct drm_device *dev)
8216{
8217 drm_i915_private_t *dev_priv = dev->dev_private;
8218 struct intel_crtc *crtc;
8219 struct intel_encoder *encoder;
8220 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8221
8222 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8223 base.head) {
8224 bool enabled = false;
8225 bool active = false;
8226
045ac3b5
JB		 8227 memset(&pipe_config, 0, sizeof(pipe_config));
8228
8af6cf88
DV		 8229 DRM_DEBUG_KMS("[CRTC:%d]\n",
8230 crtc->base.base.id);
8231
8232 WARN(crtc->active && !crtc->base.enabled,
8233 "active crtc, but not enabled in sw tracking\n");
8234
8235 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8236 base.head) {
8237 if (encoder->base.crtc != &crtc->base)
8238 continue;
8239 enabled = true;
8240 if (encoder->connectors_active)
8241 active = true;
8242 }
6c49f241 8243
8af6cf88
DV		 8244 WARN(active != crtc->active,
8245 "crtc's computed active state doesn't match tracked active state "
8246 "(expected %i, found %i)\n", active, crtc->active);
8247 WARN(enabled != crtc->base.enabled,
8248 "crtc's computed enabled state doesn't match tracked enabled state "
8249 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8250
0e8ffe1b
DV		 8251 active = dev_priv->display.get_pipe_config(crtc,
8252 &pipe_config);
d62cf62a
DV		 8253
8254 /* hw state is inconsistent with the pipe A quirk */
8255 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8256 active = crtc->active;
8257
6c49f241
DV		 8258 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8259 base.head) {
8260 if (encoder->base.crtc != &crtc->base)
8261 continue;
8262 if (encoder->get_config)
8263 encoder->get_config(encoder, &pipe_config);
8264 }
8265
0e8ffe1b
DV		 8266 WARN(crtc->active != active,
8267 "crtc active state doesn't match with hw state "
8268 "(expected %i, found %i)\n", crtc->active, active);
8269
c0b03411
DV		 8270 if (active &&
8271 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8272 WARN(1, "pipe state doesn't match!\n");
8273 intel_dump_pipe_config(crtc, &pipe_config,
8274 "[hw state]");
8275 intel_dump_pipe_config(crtc, &crtc->config,
8276 "[sw state]");
8277 }
8af6cf88
DV		 8278 }
8279}
8280
91d1b4bd
DV		 8281static void
8282check_shared_dpll_state(struct drm_device *dev)
8283{
8284 drm_i915_private_t *dev_priv = dev->dev_private;
8285 struct intel_crtc *crtc;
8286 struct intel_dpll_hw_state dpll_hw_state;
8287 int i;
5358901f
DV		 8288
8289 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8290 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8291 int enabled_crtcs = 0, active_crtcs = 0;
8292 bool active;
8293
8294 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8295
8296 DRM_DEBUG_KMS("%s\n", pll->name);
8297
8298 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8299
8300 WARN(pll->active > pll->refcount,
8301 "more active pll users than references: %i vs %i\n",
8302 pll->active, pll->refcount);
8303 WARN(pll->active && !pll->on,
8304 "pll in active use but not on in sw tracking\n");
8305 WARN(pll->on != active,
8306 "pll on state mismatch (expected %i, found %i)\n",
8307 pll->on, active);
8308
8309 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8310 base.head) {
8311 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8312 enabled_crtcs++;
8313 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8314 active_crtcs++;
8315 }
8316 WARN(pll->active != active_crtcs,
8317 "pll active crtcs mismatch (expected %i, found %i)\n",
8318 pll->active, active_crtcs);
8319 WARN(pll->refcount != enabled_crtcs,
8320 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8321 pll->refcount, enabled_crtcs);
66e985c0
DV		 8322
8323 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8324 sizeof(dpll_hw_state)),
8325 "pll hw state mismatch\n");
5358901f 8326 }
8af6cf88
DV		 8327}
8328
91d1b4bd
DV		 8329void
8330intel_modeset_check_state(struct drm_device *dev)
8331{
8332 check_connector_state(dev);
8333 check_encoder_state(dev);
8334 check_crtc_state(dev);
8335 check_shared_dpll_state(dev);
8336}
8337
f30da187
DV		 8338static int __intel_set_mode(struct drm_crtc *crtc,
8339 struct drm_display_mode *mode,
8340 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8341{
8342 struct drm_device *dev = crtc->dev;
dbf2b54e 8343 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8344 struct drm_display_mode *saved_mode, *saved_hwmode;
8345 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8346 struct intel_crtc *intel_crtc;
8347 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8348 int ret = 0;
a6778b3c 8349
3ac18232 8350 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8351 if (!saved_mode)
8352 return -ENOMEM;
3ac18232 8353 saved_hwmode = saved_mode + 1;
a6778b3c 8354
e2e1ed41 8355 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8356 &prepare_pipes, &disable_pipes);
8357
3ac18232
TG		 8358 *saved_hwmode = crtc->hwmode;
8359 *saved_mode = crtc->mode;
a6778b3c 8360
25c5b266
DV		 8361 /* Hack: Because we don't (yet) support global modeset on multiple
8362 * crtcs, we don't keep track of the new mode for more than one crtc.
8363 * Hence simply check whether any bit is set in modeset_pipes in all the
8364 * pieces of code that are not yet converted to deal with mutliple crtcs
8365 * changing their mode at the same time. */
25c5b266 8366 if (modeset_pipes) {
4e53c2e0 8367 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8368 if (IS_ERR(pipe_config)) {
8369 ret = PTR_ERR(pipe_config);
8370 pipe_config = NULL;
8371
3ac18232 8372 goto out;
25c5b266 8373 }
c0b03411
DV		 8374 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8375 "[modeset]");
25c5b266 8376 }
a6778b3c 8377
460da916
DV		 8378 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8379 intel_crtc_disable(&intel_crtc->base);
8380
ea9d758d
DV		 8381 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8382 if (intel_crtc->base.enabled)
8383 dev_priv->display.crtc_disable(&intel_crtc->base);
8384 }
a6778b3c 8385
6c4c86f5
DV		 8386 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8387 * to set it here already despite that we pass it down the callchain.
f6e5b160 8388 */
b8cecdf5 8389 if (modeset_pipes) {
25c5b266 8390 crtc->mode = *mode;
b8cecdf5
DV		 8391 /* mode_set/enable/disable functions rely on a correct pipe
8392 * config. */
8393 to_intel_crtc(crtc)->config = *pipe_config;
8394 }
7758a113 8395
ea9d758d
DV		 8396 /* Only after disabling all output pipelines that will be changed can we
8397 * update the the output configuration. */
8398 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8399
47fab737
DV		 8400 if (dev_priv->display.modeset_global_resources)
8401 dev_priv->display.modeset_global_resources(dev);
8402
a6778b3c
DV		 8403 /* Set up the DPLL and any encoders state that needs to adjust or depend
8404 * on the DPLL.
f6e5b160 8405 */
25c5b266 8406 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8407 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8408 x, y, fb);
8409 if (ret)
8410 goto done;
a6778b3c
DV		 8411 }
8412
8413 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8414 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8415 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8416
25c5b266
DV		 8417 if (modeset_pipes) {
8418 /* Store real post-adjustment hardware mode. */
b8cecdf5 8419 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8420
25c5b266
DV		 8421 /* Calculate and store various constants which
8422 * are later needed by vblank and swap-completion
8423 * timestamping. They are derived from true hwmode.
8424 */
8425 drm_calc_timestamping_constants(crtc);
8426 }
a6778b3c
DV		 8427
8428 /* FIXME: add subpixel order */
8429done:
c0c36b94 8430 if (ret && crtc->enabled) {
3ac18232
TG		 8431 crtc->hwmode = *saved_hwmode;
8432 crtc->mode = *saved_mode;
a6778b3c
DV		 8433 }
8434
3ac18232 8435out:
b8cecdf5 8436 kfree(pipe_config);
3ac18232 8437 kfree(saved_mode);
a6778b3c 8438 return ret;
f6e5b160
CW		 8439}
8440
f30da187
DV		 8441int intel_set_mode(struct drm_crtc *crtc,
8442 struct drm_display_mode *mode,
8443 int x, int y, struct drm_framebuffer *fb)
8444{
8445 int ret;
8446
8447 ret = __intel_set_mode(crtc, mode, x, y, fb);
8448
8449 if (ret == 0)
8450 intel_modeset_check_state(crtc->dev);
8451
8452 return ret;
8453}
8454
c0c36b94
CW		 8455void intel_crtc_restore_mode(struct drm_crtc *crtc)
8456{
8457 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8458}
8459
25c5b266
DV		 8460#undef for_each_intel_crtc_masked
8461
d9e55608
DV		 8462static void intel_set_config_free(struct intel_set_config *config)
8463{
8464 if (!config)
8465 return;
8466
1aa4b628
DV		 8467 kfree(config->save_connector_encoders);
8468 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8469 kfree(config);
8470}
8471
85f9eb71
DV		 8472static int intel_set_config_save_state(struct drm_device *dev,
8473 struct intel_set_config *config)
8474{
85f9eb71
DV		 8475 struct drm_encoder *encoder;
8476 struct drm_connector *connector;
8477 int count;
8478
1aa4b628
DV		 8479 config->save_encoder_crtcs =
8480 kcalloc(dev->mode_config.num_encoder,
8481 sizeof(struct drm_crtc *), GFP_KERNEL);
8482 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8483 return -ENOMEM;
8484
1aa4b628
DV		 8485 config->save_connector_encoders =
8486 kcalloc(dev->mode_config.num_connector,
8487 sizeof(struct drm_encoder *), GFP_KERNEL);
8488 if (!config->save_connector_encoders)
85f9eb71
DV		 8489 return -ENOMEM;
8490
8491 /* Copy data. Note that driver private data is not affected.
8492 * Should anything bad happen only the expected state is
8493 * restored, not the drivers personal bookkeeping.
8494 */
85f9eb71
DV		 8495 count = 0;
8496 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8497 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8498 }
8499
8500 count = 0;
8501 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8502 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8503 }
8504
8505 return 0;
8506}
8507
8508static void intel_set_config_restore_state(struct drm_device *dev,
8509 struct intel_set_config *config)
8510{
9a935856
DV		 8511 struct intel_encoder *encoder;
8512 struct intel_connector *connector;
85f9eb71
DV		 8513 int count;
8514
85f9eb71 8515 count = 0;
9a935856
DV		 8516 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8517 encoder->new_crtc =
8518 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8519 }
8520
8521 count = 0;
9a935856
DV		 8522 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8523 connector->new_encoder =
8524 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8525 }
8526}
8527
e3de42b6
ID		 8528static bool
8529is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8530 int num_connectors)
8531{
8532 int i;
8533
8534 for (i = 0; i < num_connectors; i++)
8535 if (connectors[i].encoder &&
8536 connectors[i].encoder->crtc == crtc &&
8537 connectors[i].dpms != DRM_MODE_DPMS_ON)
8538 return true;
8539
8540 return false;
8541}
8542
5e2b584e
DV		 8543static void
8544intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8545 struct intel_set_config *config)
8546{
8547
8548 /* We should be able to check here if the fb has the same properties
8549 * and then just flip_or_move it */
e3de42b6
ID		 8550 if (set->connectors != NULL &&
8551 is_crtc_connector_off(set->crtc, *set->connectors,
8552 set->num_connectors)) {
8553 config->mode_changed = true;
8554 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8555 /* If we have no fb then treat it as a full mode set */
8556 if (set->crtc->fb == NULL) {
8557 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8558 config->mode_changed = true;
8559 } else if (set->fb == NULL) {
8560 config->mode_changed = true;
72f4901e
DV		 8561 } else if (set->fb->pixel_format !=
8562 set->crtc->fb->pixel_format) {
5e2b584e 8563 config->mode_changed = true;
e3de42b6 8564 } else {
5e2b584e 8565 config->fb_changed = true;
e3de42b6 8566 }
5e2b584e
DV		 8567 }
8568
835c5873 8569 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8570 config->fb_changed = true;
8571
8572 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8573 DRM_DEBUG_KMS("modes are different, full mode set\n");
8574 drm_mode_debug_printmodeline(&set->crtc->mode);
8575 drm_mode_debug_printmodeline(set->mode);
8576 config->mode_changed = true;
8577 }
8578}
8579
2e431051 8580static int
9a935856
DV		 8581intel_modeset_stage_output_state(struct drm_device *dev,
8582 struct drm_mode_set *set,
8583 struct intel_set_config *config)
50f56119 8584{
85f9eb71 8585 struct drm_crtc *new_crtc;
9a935856
DV		 8586 struct intel_connector *connector;
8587 struct intel_encoder *encoder;
2e431051 8588 int count, ro;
50f56119 8589
9abdda74 8590 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8591 * of connectors. For paranoia, double-check this. */
8592 WARN_ON(!set->fb && (set->num_connectors != 0));
8593 WARN_ON(set->fb && (set->num_connectors == 0));
8594
50f56119 8595 count = 0;
9a935856
DV		 8596 list_for_each_entry(connector, &dev->mode_config.connector_list,
8597 base.head) {
8598 /* Otherwise traverse passed in connector list and get encoders
8599 * for them. */
50f56119 8600 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8601 if (set->connectors[ro] == &connector->base) {
8602 connector->new_encoder = connector->encoder;
50f56119
DV		 8603 break;
8604 }
8605 }
8606
9a935856
DV		 8607 /* If we disable the crtc, disable all its connectors. Also, if
8608 * the connector is on the changing crtc but not on the new
8609 * connector list, disable it. */
8610 if ((!set->fb || ro == set->num_connectors) &&
8611 connector->base.encoder &&
8612 connector->base.encoder->crtc == set->crtc) {
8613 connector->new_encoder = NULL;
8614
8615 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8616 connector->base.base.id,
8617 drm_get_connector_name(&connector->base));
8618 }
8619
8620
8621 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8622 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8623 config->mode_changed = true;
50f56119
DV		 8624 }
8625 }
9a935856 8626 /* connector->new_encoder is now updated for all connectors. */
50f56119 8627
9a935856 8628 /* Update crtc of enabled connectors. */
50f56119 8629 count = 0;
9a935856
DV		 8630 list_for_each_entry(connector, &dev->mode_config.connector_list,
8631 base.head) {
8632 if (!connector->new_encoder)
50f56119
DV		 8633 continue;
8634
9a935856 8635 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8636
8637 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8638 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8639 new_crtc = set->crtc;
8640 }
8641
8642 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8643 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8644 new_crtc)) {
5e2b584e 8645 return -EINVAL;
50f56119 8646 }
9a935856
DV		 8647 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8648
8649 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8650 connector->base.base.id,
8651 drm_get_connector_name(&connector->base),
8652 new_crtc->base.id);
8653 }
8654
8655 /* Check for any encoders that needs to be disabled. */
8656 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8657 base.head) {
8658 list_for_each_entry(connector,
8659 &dev->mode_config.connector_list,
8660 base.head) {
8661 if (connector->new_encoder == encoder) {
8662 WARN_ON(!connector->new_encoder->new_crtc);
8663
8664 goto next_encoder;
8665 }
8666 }
8667 encoder->new_crtc = NULL;
8668next_encoder:
8669 /* Only now check for crtc changes so we don't miss encoders
8670 * that will be disabled. */
8671 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8672 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8673 config->mode_changed = true;
50f56119
DV		 8674 }
8675 }
9a935856 8676 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8677
2e431051
DV		 8678 return 0;
8679}
8680
8681static int intel_crtc_set_config(struct drm_mode_set *set)
8682{
8683 struct drm_device *dev;
2e431051
DV		 8684 struct drm_mode_set save_set;
8685 struct intel_set_config *config;
8686 int ret;
2e431051 8687
8d3e375e
DV		 8688 BUG_ON(!set);
8689 BUG_ON(!set->crtc);
8690 BUG_ON(!set->crtc->helper_private);
2e431051 8691
7e53f3a4
DV		 8692 /* Enforce sane interface api - has been abused by the fb helper. */
8693 BUG_ON(!set->mode && set->fb);
8694 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8695
2e431051
DV		 8696 if (set->fb) {
8697 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8698 set->crtc->base.id, set->fb->base.id,
8699 (int)set->num_connectors, set->x, set->y);
8700 } else {
8701 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8702 }
8703
8704 dev = set->crtc->dev;
8705
8706 ret = -ENOMEM;
8707 config = kzalloc(sizeof(*config), GFP_KERNEL);
8708 if (!config)
8709 goto out_config;
8710
8711 ret = intel_set_config_save_state(dev, config);
8712 if (ret)
8713 goto out_config;
8714
8715 save_set.crtc = set->crtc;
8716 save_set.mode = &set->crtc->mode;
8717 save_set.x = set->crtc->x;
8718 save_set.y = set->crtc->y;
8719 save_set.fb = set->crtc->fb;
8720
8721 /* Compute whether we need a full modeset, only an fb base update or no
8722 * change at all. In the future we might also check whether only the
8723 * mode changed, e.g. for LVDS where we only change the panel fitter in
8724 * such cases. */
8725 intel_set_config_compute_mode_changes(set, config);
8726
9a935856 8727 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8728 if (ret)
8729 goto fail;
8730
5e2b584e 8731 if (config->mode_changed) {
c0c36b94
CW		 8732 ret = intel_set_mode(set->crtc, set->mode,
8733 set->x, set->y, set->fb);
5e2b584e 8734 } else if (config->fb_changed) {
4878cae2
VS		 8735 intel_crtc_wait_for_pending_flips(set->crtc);
8736
4f660f49 8737 ret = intel_pipe_set_base(set->crtc,
94352cf9 8738 set->x, set->y, set->fb);
50f56119
DV		 8739 }
8740
2d05eae1 8741 if (ret) {
bf67dfeb
DV		 8742 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8743 set->crtc->base.id, ret);
50f56119 8744fail:
2d05eae1 8745 intel_set_config_restore_state(dev, config);
50f56119 8746
2d05eae1
CW		 8747 /* Try to restore the config */
8748 if (config->mode_changed &&
8749 intel_set_mode(save_set.crtc, save_set.mode,
8750 save_set.x, save_set.y, save_set.fb))
8751 DRM_ERROR("failed to restore config after modeset failure\n");
8752 }
50f56119 8753
d9e55608
DV		 8754out_config:
8755 intel_set_config_free(config);
50f56119
DV		 8756 return ret;
8757}
f6e5b160
CW		 8758
8759static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8760 .cursor_set = intel_crtc_cursor_set,
8761 .cursor_move = intel_crtc_cursor_move,
8762 .gamma_set = intel_crtc_gamma_set,
50f56119 8763 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8764 .destroy = intel_crtc_destroy,
8765 .page_flip = intel_crtc_page_flip,
8766};
8767
79f689aa
PZ		 8768static void intel_cpu_pll_init(struct drm_device *dev)
8769{
affa9354 8770 if (HAS_DDI(dev))
79f689aa
PZ		 8771 intel_ddi_pll_init(dev);
8772}
8773
5358901f
DV		 8774static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8775 struct intel_shared_dpll *pll,
8776 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8777{
5358901f 8778 uint32_t val;
ee7b9f93 8779
5358901f 8780 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8781 hw_state->dpll = val;
8782 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8783 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8784
8785 return val & DPLL_VCO_ENABLE;
8786}
8787
15bdd4cf
DV		 8788static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8789 struct intel_shared_dpll *pll)
8790{
8791 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8792 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8793}
8794
e7b903d2
DV		 8795static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8796 struct intel_shared_dpll *pll)
8797{
e7b903d2
DV		 8798 /* PCH refclock must be enabled first */
8799 assert_pch_refclk_enabled(dev_priv);
8800
15bdd4cf
DV		 8801 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8802
8803 /* Wait for the clocks to stabilize. */
8804 POSTING_READ(PCH_DPLL(pll->id));
8805 udelay(150);
8806
8807 /* The pixel multiplier can only be updated once the
8808 * DPLL is enabled and the clocks are stable.
8809 *
8810 * So write it again.
8811 */
8812 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8813 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8814 udelay(200);
8815}
8816
8817static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8818 struct intel_shared_dpll *pll)
8819{
8820 struct drm_device *dev = dev_priv->dev;
8821 struct intel_crtc *crtc;
e7b903d2
DV		 8822
8823 /* Make sure no transcoder isn't still depending on us. */
8824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8825 if (intel_crtc_to_shared_dpll(crtc) == pll)
8826 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8827 }
8828
15bdd4cf
DV		 8829 I915_WRITE(PCH_DPLL(pll->id), 0);
8830 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8831 udelay(200);
8832}
8833
46edb027
DV		 8834static char *ibx_pch_dpll_names[] = {
8835 "PCH DPLL A",
8836 "PCH DPLL B",
8837};
8838
7c74ade1 8839static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8840{
e7b903d2 8841 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8842 int i;
8843
7c74ade1 8844 dev_priv->num_shared_dpll = 2;
ee7b9f93 8845
e72f9fbf 8846 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8847 dev_priv->shared_dplls[i].id = i;
8848 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8849 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8850 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8851 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8852 dev_priv->shared_dplls[i].get_hw_state =
8853 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8854 }
8855}
8856
7c74ade1
DV		 8857static void intel_shared_dpll_init(struct drm_device *dev)
8858{
e7b903d2 8859 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8860
8861 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8862 ibx_pch_dpll_init(dev);
8863 else
8864 dev_priv->num_shared_dpll = 0;
8865
8866 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8867 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8868 dev_priv->num_shared_dpll);
8869}
8870
b358d0a6 8871static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8872{
22fd0fab 8873 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8874 struct intel_crtc *intel_crtc;
8875 int i;
8876
8877 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8878 if (intel_crtc == NULL)
8879 return;
8880
8881 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8882
8883 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8884 for (i = 0; i < 256; i++) {
8885 intel_crtc->lut_r[i] = i;
8886 intel_crtc->lut_g[i] = i;
8887 intel_crtc->lut_b[i] = i;
8888 }
8889
80824003
JB		 8890 /* Swap pipes & planes for FBC on pre-965 */
8891 intel_crtc->pipe = pipe;
8892 intel_crtc->plane = pipe;
e2e767ab 8893 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8894 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8895 intel_crtc->plane = !pipe;
80824003
JB		 8896 }
8897
22fd0fab
JB		 8898 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8899 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8900 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8901 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8902
79e53945 8903 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8904}
8905
08d7b3d1 8906int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8907 struct drm_file *file)
08d7b3d1 8908{
08d7b3d1 8909 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8910 struct drm_mode_object *drmmode_obj;
8911 struct intel_crtc *crtc;
08d7b3d1 8912
1cff8f6b
DV		 8913 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8914 return -ENODEV;
08d7b3d1 8915
c05422d5
DV		 8916 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8917 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8918
c05422d5 8919 if (!drmmode_obj) {
08d7b3d1
CW		 8920 DRM_ERROR("no such CRTC id\n");
8921 return -EINVAL;
8922 }
8923
c05422d5
DV		 8924 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8925 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8926
c05422d5 8927 return 0;
08d7b3d1
CW		 8928}
8929
66a9278e 8930static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8931{
66a9278e
DV		 8932 struct drm_device *dev = encoder->base.dev;
8933 struct intel_encoder *source_encoder;
79e53945 8934 int index_mask = 0;
79e53945
JB		 8935 int entry = 0;
8936
66a9278e
DV		 8937 list_for_each_entry(source_encoder,
8938 &dev->mode_config.encoder_list, base.head) {
8939
8940 if (encoder == source_encoder)
79e53945 8941 index_mask |= (1 << entry);
66a9278e
DV		 8942
8943 /* Intel hw has only one MUX where enocoders could be cloned. */
8944 if (encoder->cloneable && source_encoder->cloneable)
8945 index_mask |= (1 << entry);
8946
79e53945
JB		 8947 entry++;
8948 }
4ef69c7a 8949
79e53945
JB		 8950 return index_mask;
8951}
8952
4d302442
CW		 8953static bool has_edp_a(struct drm_device *dev)
8954{
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956
8957 if (!IS_MOBILE(dev))
8958 return false;
8959
8960 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8961 return false;
8962
8963 if (IS_GEN5(dev) &&
8964 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8965 return false;
8966
8967 return true;
8968}
8969
79e53945
JB		 8970static void intel_setup_outputs(struct drm_device *dev)
8971{
725e30ad 8972 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8973 struct intel_encoder *encoder;
cb0953d7 8974 bool dpd_is_edp = false;
79e53945 8975
c9093354 8976 intel_lvds_init(dev);
79e53945 8977
c40c0f5b 8978 if (!IS_ULT(dev))
79935fca 8979 intel_crt_init(dev);
cb0953d7 8980
affa9354 8981 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8982 int found;
8983
8984 /* Haswell uses DDI functions to detect digital outputs */
8985 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8986 /* DDI A only supports eDP */
8987 if (found)
8988 intel_ddi_init(dev, PORT_A);
8989
8990 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8991 * register */
8992 found = I915_READ(SFUSE_STRAP);
8993
8994 if (found & SFUSE_STRAP_DDIB_DETECTED)
8995 intel_ddi_init(dev, PORT_B);
8996 if (found & SFUSE_STRAP_DDIC_DETECTED)
8997 intel_ddi_init(dev, PORT_C);
8998 if (found & SFUSE_STRAP_DDID_DETECTED)
8999 intel_ddi_init(dev, PORT_D);
9000 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9001 int found;
270b3042
DV		 9002 dpd_is_edp = intel_dpd_is_edp(dev);
9003
9004 if (has_edp_a(dev))
9005 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9006
dc0fa718 9007 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9008 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9009 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9010 if (!found)
e2debe91 9011 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9012 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9013 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9014 }
9015
dc0fa718 9016 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9017 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9018
dc0fa718 9019 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9020 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9021
5eb08b69 9022 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9023 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9024
270b3042 9025 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9026 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9027 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9028 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9029 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9030 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9031
dc0fa718 9032 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9033 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9034 PORT_B);
67cfc203
VS		 9035 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9036 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9037 }
103a196f 9038 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9039 bool found = false;
7d57382e 9040
e2debe91 9041 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9042 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9043 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9044 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9045 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9046 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9047 }
27185ae1 9048
e7281eab 9049 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9050 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9051 }
13520b05
KH		 9052
9053 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9054
e2debe91 9055 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9056 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9057 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9058 }
27185ae1 9059
e2debe91 9060 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9061
b01f2c3a
JB		 9062 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9063 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9064 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9065 }
e7281eab 9066 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9067 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9068 }
27185ae1 9069
b01f2c3a 9070 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9071 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9072 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9073 } else if (IS_GEN2(dev))
79e53945
JB		 9074 intel_dvo_init(dev);
9075
103a196f 9076 if (SUPPORTS_TV(dev))
79e53945
JB		 9077 intel_tv_init(dev);
9078
4ef69c7a
CW		 9079 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9080 encoder->base.possible_crtcs = encoder->crtc_mask;
9081 encoder->base.possible_clones =
66a9278e 9082 intel_encoder_clones(encoder);
79e53945 9083 }
47356eb6 9084
dde86e2d 9085 intel_init_pch_refclk(dev);
270b3042
DV		 9086
9087 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9088}
9089
9090static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9091{
9092 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9093
9094 drm_framebuffer_cleanup(fb);
05394f39 9095 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9096
9097 kfree(intel_fb);
9098}
9099
9100static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9101 struct drm_file *file,
79e53945
JB		 9102 unsigned int *handle)
9103{
9104 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9105 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9106
05394f39 9107 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9108}
9109
9110static const struct drm_framebuffer_funcs intel_fb_funcs = {
9111 .destroy = intel_user_framebuffer_destroy,
9112 .create_handle = intel_user_framebuffer_create_handle,
9113};
9114
38651674
DA		 9115int intel_framebuffer_init(struct drm_device *dev,
9116 struct intel_framebuffer *intel_fb,
308e5bcb 9117 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9118 struct drm_i915_gem_object *obj)
79e53945 9119{
a35cdaa0 9120 int pitch_limit;
79e53945
JB		 9121 int ret;
9122
c16ed4be
CW		 9123 if (obj->tiling_mode == I915_TILING_Y) {
9124 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9125 return -EINVAL;
c16ed4be 9126 }
57cd6508 9127
c16ed4be
CW		 9128 if (mode_cmd->pitches[0] & 63) {
9129 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9130 mode_cmd->pitches[0]);
57cd6508 9131 return -EINVAL;
c16ed4be 9132 }
57cd6508 9133
a35cdaa0
CW		 9134 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9135 pitch_limit = 32*1024;
9136 } else if (INTEL_INFO(dev)->gen >= 4) {
9137 if (obj->tiling_mode)
9138 pitch_limit = 16*1024;
9139 else
9140 pitch_limit = 32*1024;
9141 } else if (INTEL_INFO(dev)->gen >= 3) {
9142 if (obj->tiling_mode)
9143 pitch_limit = 8*1024;
9144 else
9145 pitch_limit = 16*1024;
9146 } else
9147 /* XXX DSPC is limited to 4k tiled */
9148 pitch_limit = 8*1024;
9149
9150 if (mode_cmd->pitches[0] > pitch_limit) {
9151 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9152 obj->tiling_mode ? "tiled" : "linear",
9153 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9154 return -EINVAL;
c16ed4be 9155 }
5d7bd705
VS		 9156
9157 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9158 mode_cmd->pitches[0] != obj->stride) {
9159 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9160 mode_cmd->pitches[0], obj->stride);
5d7bd705 9161 return -EINVAL;
c16ed4be 9162 }
5d7bd705 9163
57779d06 9164 /* Reject formats not supported by any plane early. */
308e5bcb 9165 switch (mode_cmd->pixel_format) {
57779d06 9166 case DRM_FORMAT_C8:
04b3924d
VS		 9167 case DRM_FORMAT_RGB565:
9168 case DRM_FORMAT_XRGB8888:
9169 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9170 break;
9171 case DRM_FORMAT_XRGB1555:
9172 case DRM_FORMAT_ARGB1555:
c16ed4be 9173 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9174 DRM_DEBUG("unsupported pixel format: %s\n",
9175 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9176 return -EINVAL;
c16ed4be 9177 }
57779d06
VS		 9178 break;
9179 case DRM_FORMAT_XBGR8888:
9180 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9181 case DRM_FORMAT_XRGB2101010:
9182 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9183 case DRM_FORMAT_XBGR2101010:
9184 case DRM_FORMAT_ABGR2101010:
c16ed4be 9185 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9186 DRM_DEBUG("unsupported pixel format: %s\n",
9187 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9188 return -EINVAL;
c16ed4be 9189 }
b5626747 9190 break;
04b3924d
VS		 9191 case DRM_FORMAT_YUYV:
9192 case DRM_FORMAT_UYVY:
9193 case DRM_FORMAT_YVYU:
9194 case DRM_FORMAT_VYUY:
c16ed4be 9195 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9196 DRM_DEBUG("unsupported pixel format: %s\n",
9197 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9198 return -EINVAL;
c16ed4be 9199 }
57cd6508
CW		 9200 break;
9201 default:
4ee62c76
VS		 9202 DRM_DEBUG("unsupported pixel format: %s\n",
9203 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9204 return -EINVAL;
9205 }
9206
90f9a336
VS		 9207 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9208 if (mode_cmd->offsets[0] != 0)
9209 return -EINVAL;
9210
c7d73f6a
DV		 9211 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9212 intel_fb->obj = obj;
9213
79e53945
JB		 9214 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9215 if (ret) {
9216 DRM_ERROR("framebuffer init failed %d\n", ret);
9217 return ret;
9218 }
9219
79e53945
JB		 9220 return 0;
9221}
9222
79e53945
JB		 9223static struct drm_framebuffer *
9224intel_user_framebuffer_create(struct drm_device *dev,
9225 struct drm_file *filp,
308e5bcb 9226 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9227{
05394f39 9228 struct drm_i915_gem_object *obj;
79e53945 9229
308e5bcb
JB		 9230 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9231 mode_cmd->handles[0]));
c8725226 9232 if (&obj->base == NULL)
cce13ff7 9233 return ERR_PTR(-ENOENT);
79e53945 9234
d2dff872 9235 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9236}
9237
79e53945 9238static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9239 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9240 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9241};
9242
e70236a8
JB		 9243/* Set up chip specific display functions */
9244static void intel_init_display(struct drm_device *dev)
9245{
9246 struct drm_i915_private *dev_priv = dev->dev_private;
9247
ee9300bb
DV		 9248 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9249 dev_priv->display.find_dpll = g4x_find_best_dpll;
9250 else if (IS_VALLEYVIEW(dev))
9251 dev_priv->display.find_dpll = vlv_find_best_dpll;
9252 else if (IS_PINEVIEW(dev))
9253 dev_priv->display.find_dpll = pnv_find_best_dpll;
9254 else
9255 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9256
affa9354 9257 if (HAS_DDI(dev)) {
0e8ffe1b 9258 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9259 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9260 dev_priv->display.crtc_enable = haswell_crtc_enable;
9261 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9262 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9263 dev_priv->display.update_plane = ironlake_update_plane;
9264 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9265 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9266 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9267 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9268 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9269 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9270 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9271 } else if (IS_VALLEYVIEW(dev)) {
9272 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9273 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9274 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9275 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9276 dev_priv->display.off = i9xx_crtc_off;
9277 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9278 } else {
0e8ffe1b 9279 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9280 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9281 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9282 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9283 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9284 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9285 }
e70236a8 9286
e70236a8 9287 /* Returns the core display clock speed */
25eb05fc
JB		 9288 if (IS_VALLEYVIEW(dev))
9289 dev_priv->display.get_display_clock_speed =
9290 valleyview_get_display_clock_speed;
9291 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9292 dev_priv->display.get_display_clock_speed =
9293 i945_get_display_clock_speed;
9294 else if (IS_I915G(dev))
9295 dev_priv->display.get_display_clock_speed =
9296 i915_get_display_clock_speed;
f2b115e6 9297 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9298 dev_priv->display.get_display_clock_speed =
9299 i9xx_misc_get_display_clock_speed;
9300 else if (IS_I915GM(dev))
9301 dev_priv->display.get_display_clock_speed =
9302 i915gm_get_display_clock_speed;
9303 else if (IS_I865G(dev))
9304 dev_priv->display.get_display_clock_speed =
9305 i865_get_display_clock_speed;
f0f8a9ce 9306 else if (IS_I85X(dev))
e70236a8
JB		 9307 dev_priv->display.get_display_clock_speed =
9308 i855_get_display_clock_speed;
9309 else /* 852, 830 */
9310 dev_priv->display.get_display_clock_speed =
9311 i830_get_display_clock_speed;
9312
7f8a8569 9313 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9314 if (IS_GEN5(dev)) {
674cf967 9315 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9316 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9317 } else if (IS_GEN6(dev)) {
674cf967 9318 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9319 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9320 } else if (IS_IVYBRIDGE(dev)) {
9321 /* FIXME: detect B0+ stepping and use auto training */
9322 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9323 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9324 dev_priv->display.modeset_global_resources =
9325 ivb_modeset_global_resources;
c82e4d26
ED		 9326 } else if (IS_HASWELL(dev)) {
9327 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9328 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9329 dev_priv->display.modeset_global_resources =
9330 haswell_modeset_global_resources;
a0e63c22 9331 }
6067aaea 9332 } else if (IS_G4X(dev)) {
e0dac65e 9333 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9334 }
8c9f3aaf
JB		 9335
9336 /* Default just returns -ENODEV to indicate unsupported */
9337 dev_priv->display.queue_flip = intel_default_queue_flip;
9338
9339 switch (INTEL_INFO(dev)->gen) {
9340 case 2:
9341 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9342 break;
9343
9344 case 3:
9345 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9346 break;
9347
9348 case 4:
9349 case 5:
9350 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9351 break;
9352
9353 case 6:
9354 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9355 break;
7c9017e5
JB		 9356 case 7:
9357 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9358 break;
8c9f3aaf 9359 }
e70236a8
JB		 9360}
9361
b690e96c
JB		 9362/*
9363 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9364 * resume, or other times. This quirk makes sure that's the case for
9365 * affected systems.
9366 */
0206e353 9367static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9368{
9369 struct drm_i915_private *dev_priv = dev->dev_private;
9370
9371 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9372 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9373}
9374
435793df
KP		 9375/*
9376 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9377 */
9378static void quirk_ssc_force_disable(struct drm_device *dev)
9379{
9380 struct drm_i915_private *dev_priv = dev->dev_private;
9381 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9382 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9383}
9384
4dca20ef 9385/*
5a15ab5b
CE		 9386 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9387 * brightness value
4dca20ef
CE		 9388 */
9389static void quirk_invert_brightness(struct drm_device *dev)
9390{
9391 struct drm_i915_private *dev_priv = dev->dev_private;
9392 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9393 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9394}
9395
b690e96c
JB		 9396struct intel_quirk {
9397 int device;
9398 int subsystem_vendor;
9399 int subsystem_device;
9400 void (*hook)(struct drm_device *dev);
9401};
9402
5f85f176
EE		 9403/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9404struct intel_dmi_quirk {
9405 void (*hook)(struct drm_device *dev);
9406 const struct dmi_system_id (*dmi_id_list)[];
9407};
9408
9409static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9410{
9411 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9412 return 1;
9413}
9414
9415static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9416 {
9417 .dmi_id_list = &(const struct dmi_system_id[]) {
9418 {
9419 .callback = intel_dmi_reverse_brightness,
9420 .ident = "NCR Corporation",
9421 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9422 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9423 },
9424 },
9425 { } /* terminating entry */
9426 },
9427 .hook = quirk_invert_brightness,
9428 },
9429};
9430
c43b5634 9431static struct intel_quirk intel_quirks[] = {
b690e96c 9432 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9433 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9434
b690e96c
JB		 9435 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9436 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9437
b690e96c
JB		 9438 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9439 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9440
ccd0d36e 9441 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9442 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9443 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9444
9445 /* Lenovo U160 cannot use SSC on LVDS */
9446 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9447
9448 /* Sony Vaio Y cannot use SSC on LVDS */
9449 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9450
9451 /* Acer Aspire 5734Z must invert backlight brightness */
9452 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9453
9454 /* Acer/eMachines G725 */
9455 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9456
9457 /* Acer/eMachines e725 */
9458 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9459
9460 /* Acer/Packard Bell NCL20 */
9461 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9462
9463 /* Acer Aspire 4736Z */
9464 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9465};
9466
9467static void intel_init_quirks(struct drm_device *dev)
9468{
9469 struct pci_dev *d = dev->pdev;
9470 int i;
9471
9472 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9473 struct intel_quirk *q = &intel_quirks[i];
9474
9475 if (d->device == q->device &&
9476 (d->subsystem_vendor == q->subsystem_vendor ||
9477 q->subsystem_vendor == PCI_ANY_ID) &&
9478 (d->subsystem_device == q->subsystem_device ||
9479 q->subsystem_device == PCI_ANY_ID))
9480 q->hook(dev);
9481 }
5f85f176
EE		 9482 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9483 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9484 intel_dmi_quirks[i].hook(dev);
9485 }
b690e96c
JB		 9486}
9487
9cce37f4
JB		 9488/* Disable the VGA plane that we never use */
9489static void i915_disable_vga(struct drm_device *dev)
9490{
9491 struct drm_i915_private *dev_priv = dev->dev_private;
9492 u8 sr1;
766aa1c4 9493 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9494
9495 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9496 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9497 sr1 = inb(VGA_SR_DATA);
9498 outb(sr1 | 1<<5, VGA_SR_DATA);
9499 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9500 udelay(300);
9501
9502 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9503 POSTING_READ(vga_reg);
9504}
9505
f817586c
DV		 9506void intel_modeset_init_hw(struct drm_device *dev)
9507{
fa42e23c 9508 intel_init_power_well(dev);
0232e927 9509
a8f78b58
ED		 9510 intel_prepare_ddi(dev);
9511
f817586c
DV		 9512 intel_init_clock_gating(dev);
9513
79f5b2c7 9514 mutex_lock(&dev->struct_mutex);
8090c6b9 9515 intel_enable_gt_powersave(dev);
79f5b2c7 9516 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9517}
9518
7d708ee4
ID		 9519void intel_modeset_suspend_hw(struct drm_device *dev)
9520{
9521 intel_suspend_hw(dev);
9522}
9523
79e53945
JB		 9524void intel_modeset_init(struct drm_device *dev)
9525{
652c393a 9526 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9527 int i, j, ret;
79e53945
JB		 9528
9529 drm_mode_config_init(dev);
9530
9531 dev->mode_config.min_width = 0;
9532 dev->mode_config.min_height = 0;
9533
019d96cb
DA		 9534 dev->mode_config.preferred_depth = 24;
9535 dev->mode_config.prefer_shadow = 1;
9536
e6ecefaa 9537 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9538
b690e96c
JB		 9539 intel_init_quirks(dev);
9540
1fa61106
ED		 9541 intel_init_pm(dev);
9542
e3c74757
BW		 9543 if (INTEL_INFO(dev)->num_pipes == 0)
9544 return;
9545
e70236a8
JB		 9546 intel_init_display(dev);
9547
a6c45cf0
CW		 9548 if (IS_GEN2(dev)) {
9549 dev->mode_config.max_width = 2048;
9550 dev->mode_config.max_height = 2048;
9551 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9552 dev->mode_config.max_width = 4096;
9553 dev->mode_config.max_height = 4096;
79e53945 9554 } else {
a6c45cf0
CW		 9555 dev->mode_config.max_width = 8192;
9556 dev->mode_config.max_height = 8192;
79e53945 9557 }
5d4545ae 9558 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9559
28c97730 9560 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9561 INTEL_INFO(dev)->num_pipes,
9562 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9563
7eb552ae 9564 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9565 intel_crtc_init(dev, i);
7f1f3851
JB		 9566 for (j = 0; j < dev_priv->num_plane; j++) {
9567 ret = intel_plane_init(dev, i, j);
9568 if (ret)
06da8da2
VS		 9569 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9570 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9571 }
79e53945
JB		 9572 }
9573
79f689aa 9574 intel_cpu_pll_init(dev);
e72f9fbf 9575 intel_shared_dpll_init(dev);
ee7b9f93 9576
9cce37f4
JB		 9577 /* Just disable it once at startup */
9578 i915_disable_vga(dev);
79e53945 9579 intel_setup_outputs(dev);
11be49eb
CW		 9580
9581 /* Just in case the BIOS is doing something questionable. */
9582 intel_disable_fbc(dev);
2c7111db
CW		 9583}
9584
24929352
DV		 9585static void
9586intel_connector_break_all_links(struct intel_connector *connector)
9587{
9588 connector->base.dpms = DRM_MODE_DPMS_OFF;
9589 connector->base.encoder = NULL;
9590 connector->encoder->connectors_active = false;
9591 connector->encoder->base.crtc = NULL;
9592}
9593
7fad798e
DV		 9594static void intel_enable_pipe_a(struct drm_device *dev)
9595{
9596 struct intel_connector *connector;
9597 struct drm_connector *crt = NULL;
9598 struct intel_load_detect_pipe load_detect_temp;
9599
9600 /* We can't just switch on the pipe A, we need to set things up with a
9601 * proper mode and output configuration. As a gross hack, enable pipe A
9602 * by enabling the load detect pipe once. */
9603 list_for_each_entry(connector,
9604 &dev->mode_config.connector_list,
9605 base.head) {
9606 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9607 crt = &connector->base;
9608 break;
9609 }
9610 }
9611
9612 if (!crt)
9613 return;
9614
9615 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9616 intel_release_load_detect_pipe(crt, &load_detect_temp);
9617
652c393a 9618
7fad798e
DV		 9619}
9620
fa555837
DV		 9621static bool
9622intel_check_plane_mapping(struct intel_crtc *crtc)
9623{
7eb552ae
BW		 9624 struct drm_device *dev = crtc->base.dev;
9625 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9626 u32 reg, val;
9627
7eb552ae 9628 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9629 return true;
9630
9631 reg = DSPCNTR(!crtc->plane);
9632 val = I915_READ(reg);
9633
9634 if ((val & DISPLAY_PLANE_ENABLE) &&
9635 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9636 return false;
9637
9638 return true;
9639}
9640
24929352
DV		 9641static void intel_sanitize_crtc(struct intel_crtc *crtc)
9642{
9643 struct drm_device *dev = crtc->base.dev;
9644 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9645 u32 reg;
24929352 9646
24929352 9647 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9648 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9649 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9650
9651 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9652 * disable the crtc (and hence change the state) if it is wrong. Note
9653 * that gen4+ has a fixed plane -> pipe mapping. */
9654 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9655 struct intel_connector *connector;
9656 bool plane;
9657
24929352
DV		 9658 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9659 crtc->base.base.id);
9660
9661 /* Pipe has the wrong plane attached and the plane is active.
9662 * Temporarily change the plane mapping and disable everything
9663 * ... */
9664 plane = crtc->plane;
9665 crtc->plane = !plane;
9666 dev_priv->display.crtc_disable(&crtc->base);
9667 crtc->plane = plane;
9668
9669 /* ... and break all links. */
9670 list_for_each_entry(connector, &dev->mode_config.connector_list,
9671 base.head) {
9672 if (connector->encoder->base.crtc != &crtc->base)
9673 continue;
9674
9675 intel_connector_break_all_links(connector);
9676 }
9677
9678 WARN_ON(crtc->active);
9679 crtc->base.enabled = false;
9680 }
24929352 9681
7fad798e
DV		 9682 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9683 crtc->pipe == PIPE_A && !crtc->active) {
9684 /* BIOS forgot to enable pipe A, this mostly happens after
9685 * resume. Force-enable the pipe to fix this, the update_dpms
9686 * call below we restore the pipe to the right state, but leave
9687 * the required bits on. */
9688 intel_enable_pipe_a(dev);
9689 }
9690
24929352
DV		 9691 /* Adjust the state of the output pipe according to whether we
9692 * have active connectors/encoders. */
9693 intel_crtc_update_dpms(&crtc->base);
9694
9695 if (crtc->active != crtc->base.enabled) {
9696 struct intel_encoder *encoder;
9697
9698 /* This can happen either due to bugs in the get_hw_state
9699 * functions or because the pipe is force-enabled due to the
9700 * pipe A quirk. */
9701 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9702 crtc->base.base.id,
9703 crtc->base.enabled ? "enabled" : "disabled",
9704 crtc->active ? "enabled" : "disabled");
9705
9706 crtc->base.enabled = crtc->active;
9707
9708 /* Because we only establish the connector -> encoder ->
9709 * crtc links if something is active, this means the
9710 * crtc is now deactivated. Break the links. connector
9711 * -> encoder links are only establish when things are
9712 * actually up, hence no need to break them. */
9713 WARN_ON(crtc->active);
9714
9715 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9716 WARN_ON(encoder->connectors_active);
9717 encoder->base.crtc = NULL;
9718 }
9719 }
9720}
9721
9722static void intel_sanitize_encoder(struct intel_encoder *encoder)
9723{
9724 struct intel_connector *connector;
9725 struct drm_device *dev = encoder->base.dev;
9726
9727 /* We need to check both for a crtc link (meaning that the
9728 * encoder is active and trying to read from a pipe) and the
9729 * pipe itself being active. */
9730 bool has_active_crtc = encoder->base.crtc &&
9731 to_intel_crtc(encoder->base.crtc)->active;
9732
9733 if (encoder->connectors_active && !has_active_crtc) {
9734 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9735 encoder->base.base.id,
9736 drm_get_encoder_name(&encoder->base));
9737
9738 /* Connector is active, but has no active pipe. This is
9739 * fallout from our resume register restoring. Disable
9740 * the encoder manually again. */
9741 if (encoder->base.crtc) {
9742 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9743 encoder->base.base.id,
9744 drm_get_encoder_name(&encoder->base));
9745 encoder->disable(encoder);
9746 }
9747
9748 /* Inconsistent output/port/pipe state happens presumably due to
9749 * a bug in one of the get_hw_state functions. Or someplace else
9750 * in our code, like the register restore mess on resume. Clamp
9751 * things to off as a safer default. */
9752 list_for_each_entry(connector,
9753 &dev->mode_config.connector_list,
9754 base.head) {
9755 if (connector->encoder != encoder)
9756 continue;
9757
9758 intel_connector_break_all_links(connector);
9759 }
9760 }
9761 /* Enabled encoders without active connectors will be fixed in
9762 * the crtc fixup. */
9763}
9764
44cec740 9765void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9766{
9767 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9768 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9769
9770 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9771 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9772 i915_disable_vga(dev);
0fde901f
KM		 9773 }
9774}
9775
30e984df 9776static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9777{
9778 struct drm_i915_private *dev_priv = dev->dev_private;
9779 enum pipe pipe;
24929352
DV		 9780 struct intel_crtc *crtc;
9781 struct intel_encoder *encoder;
9782 struct intel_connector *connector;
5358901f 9783 int i;
24929352 9784
0e8ffe1b
DV		 9785 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9786 base.head) {
88adfff1 9787 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9788
0e8ffe1b
DV		 9789 crtc->active = dev_priv->display.get_pipe_config(crtc,
9790 &crtc->config);
24929352
DV		 9791
9792 crtc->base.enabled = crtc->active;
9793
9794 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9795 crtc->base.base.id,
9796 crtc->active ? "enabled" : "disabled");
9797 }
9798
5358901f 9799 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9800 if (HAS_DDI(dev))
6441ab5f
PZ		 9801 intel_ddi_setup_hw_pll_state(dev);
9802
5358901f
DV		 9803 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9804 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9805
9806 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9807 pll->active = 0;
9808 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9809 base.head) {
9810 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9811 pll->active++;
9812 }
9813 pll->refcount = pll->active;
9814
9815 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9816 pll->name, pll->refcount);
9817 }
9818
24929352
DV		 9819 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9820 base.head) {
9821 pipe = 0;
9822
9823 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9824 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9825 encoder->base.crtc = &crtc->base;
9826 if (encoder->get_config)
9827 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9828 } else {
9829 encoder->base.crtc = NULL;
9830 }
9831
9832 encoder->connectors_active = false;
9833 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9834 encoder->base.base.id,
9835 drm_get_encoder_name(&encoder->base),
9836 encoder->base.crtc ? "enabled" : "disabled",
9837 pipe);
9838 }
9839
9840 list_for_each_entry(connector, &dev->mode_config.connector_list,
9841 base.head) {
9842 if (connector->get_hw_state(connector)) {
9843 connector->base.dpms = DRM_MODE_DPMS_ON;
9844 connector->encoder->connectors_active = true;
9845 connector->base.encoder = &connector->encoder->base;
9846 } else {
9847 connector->base.dpms = DRM_MODE_DPMS_OFF;
9848 connector->base.encoder = NULL;
9849 }
9850 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9851 connector->base.base.id,
9852 drm_get_connector_name(&connector->base),
9853 connector->base.encoder ? "enabled" : "disabled");
9854 }
30e984df
DV		 9855}
9856
9857/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9858 * and i915 state tracking structures. */
9859void intel_modeset_setup_hw_state(struct drm_device *dev,
9860 bool force_restore)
9861{
9862 struct drm_i915_private *dev_priv = dev->dev_private;
9863 enum pipe pipe;
9864 struct drm_plane *plane;
9865 struct intel_crtc *crtc;
9866 struct intel_encoder *encoder;
9867
9868 intel_modeset_readout_hw_state(dev);
24929352
DV		 9869
9870 /* HW state is read out, now we need to sanitize this mess. */
9871 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9872 base.head) {
9873 intel_sanitize_encoder(encoder);
9874 }
9875
9876 for_each_pipe(pipe) {
9877 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9878 intel_sanitize_crtc(crtc);
c0b03411 9879 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9880 }
9a935856 9881
45e2b5f6 9882 if (force_restore) {
f30da187
DV		 9883 /*
9884 * We need to use raw interfaces for restoring state to avoid
9885 * checking (bogus) intermediate states.
9886 */
45e2b5f6 9887 for_each_pipe(pipe) {
b5644d05
JB		 9888 struct drm_crtc *crtc =
9889 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9890
9891 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9892 crtc->fb);
45e2b5f6 9893 }
b5644d05
JB		 9894 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9895 intel_plane_restore(plane);
0fde901f
KM		 9896
9897 i915_redisable_vga(dev);
45e2b5f6
DV		 9898 } else {
9899 intel_modeset_update_staged_output_state(dev);
9900 }
8af6cf88
DV		 9901
9902 intel_modeset_check_state(dev);
2e938892
DV		 9903
9904 drm_mode_config_reset(dev);
2c7111db
CW		 9905}
9906
9907void intel_modeset_gem_init(struct drm_device *dev)
9908{
1833b134 9909 intel_modeset_init_hw(dev);
02e792fb
DV		 9910
9911 intel_setup_overlay(dev);
24929352 9912
45e2b5f6 9913 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9914}
9915
9916void intel_modeset_cleanup(struct drm_device *dev)
9917{
652c393a
JB		 9918 struct drm_i915_private *dev_priv = dev->dev_private;
9919 struct drm_crtc *crtc;
9920 struct intel_crtc *intel_crtc;
9921
fd0c0642
DV		 9922 /*
9923 * Interrupts and polling as the first thing to avoid creating havoc.
9924 * Too much stuff here (turning of rps, connectors, ...) would
9925 * experience fancy races otherwise.
9926 */
9927 drm_irq_uninstall(dev);
9928 cancel_work_sync(&dev_priv->hotplug_work);
9929 /*
9930 * Due to the hpd irq storm handling the hotplug work can re-arm the
9931 * poll handlers. Hence disable polling after hpd handling is shut down.
9932 */
f87ea761 9933 drm_kms_helper_poll_fini(dev);
fd0c0642 9934
652c393a
JB		 9935 mutex_lock(&dev->struct_mutex);
9936
723bfd70
JB		 9937 intel_unregister_dsm_handler();
9938
652c393a
JB		 9939 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9940 /* Skip inactive CRTCs */
9941 if (!crtc->fb)
9942 continue;
9943
9944 intel_crtc = to_intel_crtc(crtc);
3dec0095 9945 intel_increase_pllclock(crtc);
652c393a
JB		 9946 }
9947
973d04f9 9948 intel_disable_fbc(dev);
e70236a8 9949
8090c6b9 9950 intel_disable_gt_powersave(dev);
0cdab21f 9951
930ebb46
DV		 9952 ironlake_teardown_rc6(dev);
9953
69341a5e
KH		 9954 mutex_unlock(&dev->struct_mutex);
9955
1630fe75
CW		 9956 /* flush any delayed tasks or pending work */
9957 flush_scheduled_work();
9958
dc652f90
JN		 9959 /* destroy backlight, if any, before the connectors */
9960 intel_panel_destroy_backlight(dev);
9961
79e53945 9962 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9963
9964 intel_cleanup_overlay(dev);
79e53945
JB		 9965}
9966
f1c79df3
ZW		 9967/*
9968 * Return which encoder is currently attached for connector.
9969 */
df0e9248 9970struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9971{
df0e9248
CW		 9972 return &intel_attached_encoder(connector)->base;
9973}
f1c79df3 9974
df0e9248
CW		 9975void intel_connector_attach_encoder(struct intel_connector *connector,
9976 struct intel_encoder *encoder)
9977{
9978 connector->encoder = encoder;
9979 drm_mode_connector_attach_encoder(&connector->base,
9980 &encoder->base);
79e53945 9981}
28d52043
DA		 9982
9983/*
9984 * set vga decode state - true == enable VGA decode
9985 */
9986int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9987{
9988 struct drm_i915_private *dev_priv = dev->dev_private;
9989 u16 gmch_ctrl;
9990
9991 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9992 if (state)
9993 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9994 else
9995 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9996 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9997 return 0;
9998}
c4a1d9e4
CW		 9999
10000#ifdef CONFIG_DEBUG_FS
10001#include <linux/seq_file.h>
10002
10003struct intel_display_error_state {
ff57f1b0
PZ		 10004
10005 u32 power_well_driver;
10006
c4a1d9e4
CW		 10007 struct intel_cursor_error_state {
10008 u32 control;
10009 u32 position;
10010 u32 base;
10011 u32 size;
52331309 10012 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10013
10014 struct intel_pipe_error_state {
ff57f1b0 10015 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10016 u32 conf;
10017 u32 source;
10018
10019 u32 htotal;
10020 u32 hblank;
10021 u32 hsync;
10022 u32 vtotal;
10023 u32 vblank;
10024 u32 vsync;
52331309 10025 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10026
10027 struct intel_plane_error_state {
10028 u32 control;
10029 u32 stride;
10030 u32 size;
10031 u32 pos;
10032 u32 addr;
10033 u32 surface;
10034 u32 tile_offset;
52331309 10035 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10036};
10037
10038struct intel_display_error_state *
10039intel_display_capture_error_state(struct drm_device *dev)
10040{
0206e353 10041 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10042 struct intel_display_error_state *error;
702e7a56 10043 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10044 int i;
10045
10046 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10047 if (error == NULL)
10048 return NULL;
10049
ff57f1b0
PZ		 10050 if (HAS_POWER_WELL(dev))
10051 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10052
52331309 10053 for_each_pipe(i) {
702e7a56 10054 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10055 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10056
a18c4c3d
PZ		 10057 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10058 error->cursor[i].control = I915_READ(CURCNTR(i));
10059 error->cursor[i].position = I915_READ(CURPOS(i));
10060 error->cursor[i].base = I915_READ(CURBASE(i));
10061 } else {
10062 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10063 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10064 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10065 }
c4a1d9e4
CW		 10066
10067 error->plane[i].control = I915_READ(DSPCNTR(i));
10068 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10069 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10070 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10071 error->plane[i].pos = I915_READ(DSPPOS(i));
10072 }
ca291363
PZ		 10073 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10074 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10075 if (INTEL_INFO(dev)->gen >= 4) {
10076 error->plane[i].surface = I915_READ(DSPSURF(i));
10077 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10078 }
10079
702e7a56 10080 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10081 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10082 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10083 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10084 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10085 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10086 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10087 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10088 }
10089
12d217c7
PZ		 10090 /* In the code above we read the registers without checking if the power
10091 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10092 * prevent the next I915_WRITE from detecting it and printing an error
10093 * message. */
10094 if (HAS_POWER_WELL(dev))
10095 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10096
c4a1d9e4
CW		 10097 return error;
10098}
10099
edc3d884
MK		 10100#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10101
c4a1d9e4 10102void
edc3d884 10103intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10104 struct drm_device *dev,
10105 struct intel_display_error_state *error)
10106{
10107 int i;
10108
edc3d884 10109 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10110 if (HAS_POWER_WELL(dev))
edc3d884 10111 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10112 error->power_well_driver);
52331309 10113 for_each_pipe(i) {
edc3d884
MK		 10114 err_printf(m, "Pipe [%d]:\n", i);
10115 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10116 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10117 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10118 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10119 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10120 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10121 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10122 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10123 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10124 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10125
10126 err_printf(m, "Plane [%d]:\n", i);
10127 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10128 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10129 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10130 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10131 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10132 }
4b71a570 10133 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10134 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10135 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10136 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10137 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10138 }
10139
edc3d884
MK		 10140 err_printf(m, "Cursor [%d]:\n", i);
10141 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10142 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10143 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10144 }
10145}
10146#endif
Linux kernel - Deliverables
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