projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Modify DP set clock to accomodate more eDP timings v2
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
2377b741
JB		 72/* FDI */
73#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
d2acd215
DV		 75int
76intel_pch_rawclk(struct drm_device *dev)
77{
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83}
84
021357ac
CW		 85static inline u32 /* units of 100MHz */
86intel_fdi_link_freq(struct drm_device *dev)
87{
8b99e68c
CW		 88 if (IS_GEN5(dev)) {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 } else
92 return 27;
021357ac
CW		 93}
94
5d536e28 95static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 106};
107
5d536e28
DV		 108static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
119};
120
e4b36699 121static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 145};
146
147static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 158};
159
273e27ca 160
e4b36699 161static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
171 .p2_slow = 10,
172 .p2_fast = 10
044c7c41 173 },
e4b36699
KP		 174};
175
176static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
044c7c41 200 },
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
044c7c41 214 },
e4b36699
KP		 215};
216
f2b115e6 217static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 220 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
273e27ca 223 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 230};
231
f2b115e6 232static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 243};
244
273e27ca
EA		 245/* Ironlake / Sandybridge
246 *
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
249 */
b91ad0ec 250static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 261};
262
b91ad0ec 263static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 274};
275
276static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 287};
288
273e27ca 289/* LVDS 100mhz refclk limits. */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
0206e353 298 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
0206e353 311 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 314};
315
a0c4da24
JB		 316static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
75e53986 324 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 327};
328
329static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 340};
341
342static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 345 .n = { .min = 1, .max = 7 },
74a4dd2e 346 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 353};
354
1b894b59
CW		 355static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 int refclk)
2c07245f 357{
b91ad0ec 358 struct drm_device *dev = crtc->dev;
2c07245f 359 const intel_limit_t *limit;
b91ad0ec
ZW		 360
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 362 if (intel_is_dual_link_lvds(dev)) {
1b894b59 363 if (refclk == 100000)
b91ad0ec
ZW		 364 limit = &intel_limits_ironlake_dual_lvds_100m;
365 else
366 limit = &intel_limits_ironlake_dual_lvds;
367 } else {
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_single_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_single_lvds;
372 }
c6bb3538 373 } else
b91ad0ec 374 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 375
376 return limit;
377}
378
044c7c41
ML		 379static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
380{
381 struct drm_device *dev = crtc->dev;
044c7c41
ML		 382 const intel_limit_t *limit;
383
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 385 if (intel_is_dual_link_lvds(dev))
e4b36699 386 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 387 else
e4b36699 388 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 391 limit = &intel_limits_g4x_hdmi;
044c7c41 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 393 limit = &intel_limits_g4x_sdvo;
044c7c41 394 } else /* The option is for other outputs */
e4b36699 395 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 396
397 return limit;
398}
399
1b894b59 400static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 401{
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
404
bad720ff 405 if (HAS_PCH_SPLIT(dev))
1b894b59 406 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 407 else if (IS_G4X(dev)) {
044c7c41 408 limit = intel_g4x_limit(crtc);
f2b115e6 409 } else if (IS_PINEVIEW(dev)) {
2177832f 410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 411 limit = &intel_limits_pineview_lvds;
2177832f 412 else
f2b115e6 413 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
419 else
420 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 428 limit = &intel_limits_i8xx_lvds;
5d536e28 429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 430 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 431 else
432 limit = &intel_limits_i8xx_dac;
79e53945
JB		 433 }
434 return limit;
435}
436
f2b115e6
AJ		 437/* m1 is reserved as 0 in Pineview, n is a ring counter */
438static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 439{
2177832f
SL		 440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444}
445
7429e9d4
DV		 446static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447{
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449}
450
ac58c3f0 451static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 452{
7429e9d4 453 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457}
458
79e53945
JB		 459/**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
4ef69c7a 462bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 463{
4ef69c7a 464 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 465 struct intel_encoder *encoder;
466
6c2b7c12
DV		 467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
4ef69c7a
CW		 469 return true;
470
471 return false;
79e53945
JB		 472}
473
7c04d1d9 474#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 475/**
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
478 */
479
1b894b59
CW		 480static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
79e53945 483{
79e53945 484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 485 INTELPllInvalid("p1 out of range\n");
79e53945 486 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 487 INTELPllInvalid("p out of range\n");
79e53945 488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 489 INTELPllInvalid("m2 out of range\n");
79e53945 490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 491 INTELPllInvalid("m1 out of range\n");
f2b115e6 492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 493 INTELPllInvalid("m1 <= m2\n");
79e53945 494 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 495 INTELPllInvalid("m out of range\n");
79e53945 496 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 497 INTELPllInvalid("n out of range\n");
79e53945 498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 499 INTELPllInvalid("vco out of range\n");
79e53945
JB		 500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
502 */
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 504 INTELPllInvalid("dot out of range\n");
79e53945
JB		 505
506 return true;
507}
508
d4906093 509static bool
ee9300bb 510i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
79e53945
JB		 513{
514 struct drm_device *dev = crtc->dev;
79e53945 515 intel_clock_t clock;
79e53945
JB		 516 int err = target;
517
a210b028 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 519 /*
a210b028
DV		 520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
79e53945 523 */
1974cad0 524 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 525 clock.p2 = limit->p2.p2_fast;
526 else
527 clock.p2 = limit->p2.p2_slow;
528 } else {
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
531 else
532 clock.p2 = limit->p2.p2_fast;
533 }
534
0206e353 535 memset(best_clock, 0, sizeof(*best_clock));
79e53945 536
42158660
ZY		 537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
538 clock.m1++) {
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 541 if (clock.m2 >= clock.m1)
42158660
ZY		 542 break;
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 547 int this_err;
548
ac58c3f0
DV		 549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
551 &clock))
552 continue;
553 if (match_clock &&
554 clock.p != match_clock->p)
555 continue;
556
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
559 *best_clock = clock;
560 err = this_err;
561 }
562 }
563 }
564 }
565 }
566
567 return (err != target);
568}
569
570static bool
ee9300bb
DV		 571pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
79e53945
JB		 574{
575 struct drm_device *dev = crtc->dev;
79e53945 576 intel_clock_t clock;
79e53945
JB		 577 int err = target;
578
a210b028 579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 580 /*
a210b028
DV		 581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
79e53945 584 */
1974cad0 585 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 586 clock.p2 = limit->p2.p2_fast;
587 else
588 clock.p2 = limit->p2.p2_slow;
589 } else {
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
592 else
593 clock.p2 = limit->p2.p2_fast;
594 }
595
0206e353 596 memset(best_clock, 0, sizeof(*best_clock));
79e53945 597
42158660
ZY		 598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
599 clock.m1++) {
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 606 int this_err;
607
ac58c3f0 608 pineview_clock(refclk, &clock);
1b894b59
CW		 609 if (!intel_PLL_is_valid(dev, limit,
610 &clock))
79e53945 611 continue;
cec2f356
SP		 612 if (match_clock &&
613 clock.p != match_clock->p)
614 continue;
79e53945
JB		 615
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
618 *best_clock = clock;
619 err = this_err;
620 }
621 }
622 }
623 }
624 }
625
626 return (err != target);
627}
628
d4906093 629static bool
ee9300bb
DV		 630g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
d4906093
ML		 633{
634 struct drm_device *dev = crtc->dev;
d4906093
ML		 635 intel_clock_t clock;
636 int max_n;
637 bool found;
6ba770dc
AJ		 638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 640 found = false;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 643 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 644 clock.p2 = limit->p2.p2_fast;
645 else
646 clock.p2 = limit->p2.p2_slow;
647 } else {
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
650 else
651 clock.p2 = limit->p2.p2_fast;
652 }
653
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
f77f13e2 656 /* based on hardware requirement, prefer smaller n to precision */
d4906093 657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 658 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
665 int this_err;
666
ac58c3f0 667 i9xx_clock(refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
d4906093 670 continue;
1b894b59
CW		 671
672 this_err = abs(clock.dot - target);
d4906093
ML		 673 if (this_err < err_most) {
674 *best_clock = clock;
675 err_most = this_err;
676 max_n = clock.n;
677 found = true;
678 }
679 }
680 }
681 }
682 }
2c07245f
ZW		 683 return found;
684}
685
a0c4da24 686static bool
ee9300bb
DV		 687vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
a0c4da24
JB		 690{
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
692 u32 m, n, fastclk;
f3f08572 693 u32 updrate, minupdate, p;
a0c4da24
JB		 694 unsigned long bestppm, ppm, absppm;
695 int dotclk, flag;
696
af447bd3 697 flag = 0;
a0c4da24
JB		 698 dotclk = target * 1000;
699 bestppm = 1000000;
700 ppm = absppm = 0;
701 fastclk = dotclk / (2*100);
702 updrate = 0;
703 minupdate = 19200;
a0c4da24
JB		 704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
706
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
712 if (p2 > 10)
713 p2 = p2 - 1;
714 p = p1 * p2;
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
719 m = m1 * m2;
720 vco = updrate * m;
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
725 bestppm = 0;
726 flag = 1;
727 }
728 if (absppm < bestppm - 10) {
729 bestppm = absppm;
730 flag = 1;
731 }
732 if (flag) {
733 bestn = n;
734 bestm1 = m1;
735 bestm2 = m2;
736 bestp1 = p1;
737 bestp2 = p2;
738 flag = 0;
739 }
740 }
741 }
742 }
743 }
744 }
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
750
751 return true;
752}
a4fc5ed6 753
a5c961d1
PZ		 754enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756{
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
3b117c8f 760 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 761}
762
a928d536
PZ		 763static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772}
773
9d0498a2
JB		 774/**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 783{
9d0498a2 784 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 785 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 786
a928d536
PZ		 787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
300387c0
CW		 792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
9d0498a2 808 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
9d0498a2
JB		 812 DRM_DEBUG_KMS("vblank wait timed out\n");
813}
814
ab7ad7f6
KP		 815/*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
ab7ad7f6
KP		 824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
58e10eb9 830 *
9d0498a2 831 */
58e10eb9 832void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
ab7ad7f6
KP		 837
838 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 839 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 840
841 /* Wait for the Pipe State to go off */
58e10eb9
CW		 842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 } else {
837ba00f 846 u32 last_line, line_mask;
58e10eb9 847 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
837ba00f
PZ		 850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
ab7ad7f6
KP		 855 /* Wait for the display line to settle */
856 do {
837ba00f 857 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 858 mdelay(5);
837ba00f 859 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 }
79e53945
JB		 864}
865
b0ea7d37
DL		 866/*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875{
876 u32 bit;
877
c36346e3
DL		 878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
b0ea7d37
DL		 906 }
907
908 return I915_READ(SDEISR) & bit;
909}
910
b24e7179
JB		 911static const char *state_string(bool enabled)
912{
913 return enabled ? "on" : "off";
914}
915
916/* Only for pre-ILK configs */
55607e8a
DV		 917void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
b24e7179
JB		 919{
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930}
b24e7179 931
23538ef1
JN		 932/* XXX: the dsi pll is shared between MIPI DSI ports */
933static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
934{
935 u32 val;
936 bool cur_state;
937
938 mutex_lock(&dev_priv->dpio_lock);
939 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
940 mutex_unlock(&dev_priv->dpio_lock);
941
942 cur_state = val & DSI_PLL_VCO_EN;
943 WARN(cur_state != state,
944 "DSI PLL state assertion failure (expected %s, current %s)\n",
945 state_string(state), state_string(cur_state));
946}
947#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
948#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949
55607e8a 950struct intel_shared_dpll *
e2b78267
DV		 951intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952{
953 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954
a43f6e0f 955 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 956 return NULL;
957
a43f6e0f 958 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 959}
960
040484af 961/* For ILK+ */
55607e8a
DV		 962void assert_shared_dpll(struct drm_i915_private *dev_priv,
963 struct intel_shared_dpll *pll,
964 bool state)
040484af 965{
040484af 966 bool cur_state;
5358901f 967 struct intel_dpll_hw_state hw_state;
040484af 968
9d82aa17
ED		 969 if (HAS_PCH_LPT(dev_priv->dev)) {
970 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
971 return;
972 }
973
92b27b08 974 if (WARN (!pll,
46edb027 975 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 976 return;
ee7b9f93 977
5358901f 978 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 979 WARN(cur_state != state,
5358901f
DV		 980 "%s assertion failure (expected %s, current %s)\n",
981 pll->name, state_string(state), state_string(cur_state));
040484af 982}
040484af
JB		 983
984static void assert_fdi_tx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
ad80a810
PZ		 990 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
991 pipe);
040484af 992
affa9354
PZ		 993 if (HAS_DDI(dev_priv->dev)) {
994 /* DDI does not have a specific FDI_TX register */
ad80a810 995 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 996 val = I915_READ(reg);
ad80a810 997 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 998 } else {
999 reg = FDI_TX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_TX_ENABLE);
1002 }
040484af
JB		 1003 WARN(cur_state != state,
1004 "FDI TX state assertion failure (expected %s, current %s)\n",
1005 state_string(state), state_string(cur_state));
1006}
1007#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1008#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009
1010static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1011 enum pipe pipe, bool state)
1012{
1013 int reg;
1014 u32 val;
1015 bool cur_state;
1016
d63fa0dc
PZ		 1017 reg = FDI_RX_CTL(pipe);
1018 val = I915_READ(reg);
1019 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1020 WARN(cur_state != state,
1021 "FDI RX state assertion failure (expected %s, current %s)\n",
1022 state_string(state), state_string(cur_state));
1023}
1024#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1025#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026
1027static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029{
1030 int reg;
1031 u32 val;
1032
1033 /* ILK FDI PLL is always enabled */
1034 if (dev_priv->info->gen == 5)
1035 return;
1036
bf507ef7 1037 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1038 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1039 return;
1040
040484af
JB		 1041 reg = FDI_TX_CTL(pipe);
1042 val = I915_READ(reg);
1043 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1044}
1045
55607e8a
DV		 1046void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1047 enum pipe pipe, bool state)
040484af
JB		 1048{
1049 int reg;
1050 u32 val;
55607e8a 1051 bool cur_state;
040484af
JB		 1052
1053 reg = FDI_RX_CTL(pipe);
1054 val = I915_READ(reg);
55607e8a
DV		 1055 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1056 WARN(cur_state != state,
1057 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1058 state_string(state), state_string(cur_state));
040484af
JB		 1059}
1060
ea0760cf
JB		 1061static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1062 enum pipe pipe)
1063{
1064 int pp_reg, lvds_reg;
1065 u32 val;
1066 enum pipe panel_pipe = PIPE_A;
0de3b485 1067 bool locked = true;
ea0760cf
JB		 1068
1069 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1070 pp_reg = PCH_PP_CONTROL;
1071 lvds_reg = PCH_LVDS;
1072 } else {
1073 pp_reg = PP_CONTROL;
1074 lvds_reg = LVDS;
1075 }
1076
1077 val = I915_READ(pp_reg);
1078 if (!(val & PANEL_POWER_ON) ||
1079 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1080 locked = false;
1081
1082 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1083 panel_pipe = PIPE_B;
1084
1085 WARN(panel_pipe == pipe && locked,
1086 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1087 pipe_name(pipe));
ea0760cf
JB		 1088}
1089
b840d907
JB		 1090void assert_pipe(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
b24e7179
JB		 1092{
1093 int reg;
1094 u32 val;
63d7bbe9 1095 bool cur_state;
702e7a56
PZ		 1096 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1097 pipe);
b24e7179 1098
8e636784
DV		 1099 /* if we need the pipe A quirk it must be always on */
1100 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1101 state = true;
1102
b97186f0
PZ		 1103 if (!intel_display_power_enabled(dev_priv->dev,
1104 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1105 cur_state = false;
1106 } else {
1107 reg = PIPECONF(cpu_transcoder);
1108 val = I915_READ(reg);
1109 cur_state = !!(val & PIPECONF_ENABLE);
1110 }
1111
63d7bbe9
JB		 1112 WARN(cur_state != state,
1113 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1114 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1115}
1116
931872fc
CW		 1117static void assert_plane(struct drm_i915_private *dev_priv,
1118 enum plane plane, bool state)
b24e7179
JB		 1119{
1120 int reg;
1121 u32 val;
931872fc 1122 bool cur_state;
b24e7179
JB		 1123
1124 reg = DSPCNTR(plane);
1125 val = I915_READ(reg);
931872fc
CW		 1126 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1127 WARN(cur_state != state,
1128 "plane %c assertion failure (expected %s, current %s)\n",
1129 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1130}
1131
931872fc
CW		 1132#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1133#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1134
b24e7179
JB		 1135static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
653e1026 1138 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1139 int reg, i;
1140 u32 val;
1141 int cur_pipe;
1142
653e1026
VS		 1143 /* Primary planes are fixed to pipes on gen4+ */
1144 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1145 reg = DSPCNTR(pipe);
1146 val = I915_READ(reg);
1147 WARN((val & DISPLAY_PLANE_ENABLE),
1148 "plane %c assertion failure, should be disabled but not\n",
1149 plane_name(pipe));
19ec1358 1150 return;
28c05794 1151 }
19ec1358 1152
b24e7179 1153 /* Need to check both planes against the pipe */
08e2a7de 1154 for_each_pipe(i) {
b24e7179
JB		 1155 reg = DSPCNTR(i);
1156 val = I915_READ(reg);
1157 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1158 DISPPLANE_SEL_PIPE_SHIFT;
1159 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1160 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1161 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1162 }
1163}
1164
19332d7a
JB		 1165static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
20674eef 1168 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1169 int reg, i;
1170 u32 val;
1171
20674eef
VS		 1172 if (IS_VALLEYVIEW(dev)) {
1173 for (i = 0; i < dev_priv->num_plane; i++) {
1174 reg = SPCNTR(pipe, i);
1175 val = I915_READ(reg);
1176 WARN((val & SP_ENABLE),
1177 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1178 sprite_name(pipe, i), pipe_name(pipe));
1179 }
1180 } else if (INTEL_INFO(dev)->gen >= 7) {
1181 reg = SPRCTL(pipe);
19332d7a 1182 val = I915_READ(reg);
20674eef 1183 WARN((val & SPRITE_ENABLE),
06da8da2 1184 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1185 plane_name(pipe), pipe_name(pipe));
1186 } else if (INTEL_INFO(dev)->gen >= 5) {
1187 reg = DVSCNTR(pipe);
19332d7a 1188 val = I915_READ(reg);
20674eef 1189 WARN((val & DVS_ENABLE),
06da8da2 1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1191 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1192 }
1193}
1194
92f2584a
JB		 1195static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1196{
1197 u32 val;
1198 bool enabled;
1199
9d82aa17
ED		 1200 if (HAS_PCH_LPT(dev_priv->dev)) {
1201 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1202 return;
1203 }
1204
92f2584a
JB		 1205 val = I915_READ(PCH_DREF_CONTROL);
1206 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1207 DREF_SUPERSPREAD_SOURCE_MASK));
1208 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1209}
1210
ab9412ba
DV		 1211static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1212 enum pipe pipe)
92f2584a
JB		 1213{
1214 int reg;
1215 u32 val;
1216 bool enabled;
1217
ab9412ba 1218 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1219 val = I915_READ(reg);
1220 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1221 WARN(enabled,
1222 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1223 pipe_name(pipe));
92f2584a
JB		 1224}
1225
4e634389
KP		 1226static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1228{
1229 if ((val & DP_PORT_EN) == 0)
1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1234 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1235 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1236 return false;
1237 } else {
1238 if ((val & DP_PIPE_MASK) != (pipe << 30))
1239 return false;
1240 }
1241 return true;
1242}
1243
1519b995
KP		 1244static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, u32 val)
1246{
dc0fa718 1247 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1248 return false;
1249
1250 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1251 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1252 return false;
1253 } else {
dc0fa718 1254 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1255 return false;
1256 }
1257 return true;
1258}
1259
1260static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe, u32 val)
1262{
1263 if ((val & LVDS_PORT_EN) == 0)
1264 return false;
1265
1266 if (HAS_PCH_CPT(dev_priv->dev)) {
1267 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1268 return false;
1269 } else {
1270 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1271 return false;
1272 }
1273 return true;
1274}
1275
1276static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, u32 val)
1278{
1279 if ((val & ADPA_DAC_ENABLE) == 0)
1280 return false;
1281 if (HAS_PCH_CPT(dev_priv->dev)) {
1282 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 return false;
1284 } else {
1285 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1286 return false;
1287 }
1288 return true;
1289}
1290
291906f1 1291static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1292 enum pipe pipe, int reg, u32 port_sel)
291906f1 1293{
47a05eca 1294 u32 val = I915_READ(reg);
4e634389 1295 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1296 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 reg, pipe_name(pipe));
de9a35ab 1298
75c5da27
DV		 1299 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1300 && (val & DP_PIPEB_SELECT),
de9a35ab 1301 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1302}
1303
1304static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, int reg)
1306{
47a05eca 1307 u32 val = I915_READ(reg);
b70ad586 1308 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1309 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1310 reg, pipe_name(pipe));
de9a35ab 1311
dc0fa718 1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1313 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1314 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1315}
1316
1317static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe)
1319{
1320 int reg;
1321 u32 val;
291906f1 1322
f0575e92
KP		 1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1324 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1326
1327 reg = PCH_ADPA;
1328 val = I915_READ(reg);
b70ad586 1329 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1330 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1331 pipe_name(pipe));
291906f1
JB		 1332
1333 reg = PCH_LVDS;
1334 val = I915_READ(reg);
b70ad586 1335 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1336 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1337 pipe_name(pipe));
291906f1 1338
e2debe91
PZ		 1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1340 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1342}
1343
426115cf 1344static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1345{
426115cf
DV		 1346 struct drm_device *dev = crtc->base.dev;
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 int reg = DPLL(crtc->pipe);
1349 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1350
426115cf 1351 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1352
1353 /* No really, not for ILK+ */
1354 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1355
1356 /* PLL is protected by panel, make sure we can write it */
1357 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1358 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1359
426115cf
DV		 1360 I915_WRITE(reg, dpll);
1361 POSTING_READ(reg);
1362 udelay(150);
1363
1364 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1365 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1366
1367 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1368 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1369
1370 /* We do this three times for luck */
426115cf 1371 I915_WRITE(reg, dpll);
87442f73
DV		 1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
426115cf 1374 I915_WRITE(reg, dpll);
87442f73
DV		 1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
426115cf 1377 I915_WRITE(reg, dpll);
87442f73
DV		 1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380}
1381
66e3d5c0 1382static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1383{
66e3d5c0
DV		 1384 struct drm_device *dev = crtc->base.dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 int reg = DPLL(crtc->pipe);
1387 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1388
66e3d5c0 1389 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1390
63d7bbe9 1391 /* No really, not for ILK+ */
87442f73 1392 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1393
1394 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1395 if (IS_MOBILE(dev) && !IS_I830(dev))
1396 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1397
66e3d5c0
DV		 1398 I915_WRITE(reg, dpll);
1399
1400 /* Wait for the clocks to stabilize. */
1401 POSTING_READ(reg);
1402 udelay(150);
1403
1404 if (INTEL_INFO(dev)->gen >= 4) {
1405 I915_WRITE(DPLL_MD(crtc->pipe),
1406 crtc->config.dpll_hw_state.dpll_md);
1407 } else {
1408 /* The pixel multiplier can only be updated once the
1409 * DPLL is enabled and the clocks are stable.
1410 *
1411 * So write it again.
1412 */
1413 I915_WRITE(reg, dpll);
1414 }
63d7bbe9
JB		 1415
1416 /* We do this three times for luck */
66e3d5c0 1417 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1418 POSTING_READ(reg);
1419 udelay(150); /* wait for warmup */
66e3d5c0 1420 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1421 POSTING_READ(reg);
1422 udelay(150); /* wait for warmup */
66e3d5c0 1423 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1424 POSTING_READ(reg);
1425 udelay(150); /* wait for warmup */
1426}
1427
1428/**
50b44a44 1429 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1430 * @dev_priv: i915 private structure
1431 * @pipe: pipe PLL to disable
1432 *
1433 * Disable the PLL for @pipe, making sure the pipe is off first.
1434 *
1435 * Note! This is for pre-ILK only.
1436 */
50b44a44 1437static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1438{
63d7bbe9
JB		 1439 /* Don't disable pipe A or pipe A PLLs if needed */
1440 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1441 return;
1442
1443 /* Make sure the pipe isn't still relying on us */
1444 assert_pipe_disabled(dev_priv, pipe);
1445
50b44a44
DV		 1446 I915_WRITE(DPLL(pipe), 0);
1447 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1448}
1449
89b667f8
JB		 1450void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1451{
1452 u32 port_mask;
1453
1454 if (!port)
1455 port_mask = DPLL_PORTB_READY_MASK;
1456 else
1457 port_mask = DPLL_PORTC_READY_MASK;
1458
1459 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1460 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1461 'B' + port, I915_READ(DPLL(0)));
1462}
1463
92f2584a 1464/**
e72f9fbf 1465 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1466 * @dev_priv: i915 private structure
1467 * @pipe: pipe PLL to enable
1468 *
1469 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1470 * drives the transcoder clock.
1471 */
e2b78267 1472static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1473{
e2b78267
DV		 1474 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1475 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1476
48da64a8 1477 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1478 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1479 if (WARN_ON(pll == NULL))
48da64a8
CW		 1480 return;
1481
1482 if (WARN_ON(pll->refcount == 0))
1483 return;
ee7b9f93 1484
46edb027
DV		 1485 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1486 pll->name, pll->active, pll->on,
e2b78267 1487 crtc->base.base.id);
92f2584a 1488
cdbd2316
DV		 1489 if (pll->active++) {
1490 WARN_ON(!pll->on);
e9d6944e 1491 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1492 return;
1493 }
f4a091c7 1494 WARN_ON(pll->on);
ee7b9f93 1495
46edb027 1496 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1497 pll->enable(dev_priv, pll);
ee7b9f93 1498 pll->on = true;
92f2584a
JB		 1499}
1500
e2b78267 1501static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1502{
e2b78267
DV		 1503 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1504 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1505
92f2584a
JB		 1506 /* PCH only available on ILK+ */
1507 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1508 if (WARN_ON(pll == NULL))
ee7b9f93 1509 return;
92f2584a 1510
48da64a8
CW		 1511 if (WARN_ON(pll->refcount == 0))
1512 return;
7a419866 1513
46edb027
DV		 1514 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1515 pll->name, pll->active, pll->on,
e2b78267 1516 crtc->base.base.id);
7a419866 1517
48da64a8 1518 if (WARN_ON(pll->active == 0)) {
e9d6944e 1519 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1520 return;
1521 }
1522
e9d6944e 1523 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1524 WARN_ON(!pll->on);
cdbd2316 1525 if (--pll->active)
7a419866 1526 return;
ee7b9f93 1527
46edb027 1528 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1529 pll->disable(dev_priv, pll);
ee7b9f93 1530 pll->on = false;
92f2584a
JB		 1531}
1532
b8a4f404
PZ		 1533static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1534 enum pipe pipe)
040484af 1535{
23670b32 1536 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1537 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1539 uint32_t reg, val, pipeconf_val;
040484af
JB		 1540
1541 /* PCH only available on ILK+ */
1542 BUG_ON(dev_priv->info->gen < 5);
1543
1544 /* Make sure PCH DPLL is enabled */
e72f9fbf 1545 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1546 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1547
1548 /* FDI must be feeding us bits for PCH ports */
1549 assert_fdi_tx_enabled(dev_priv, pipe);
1550 assert_fdi_rx_enabled(dev_priv, pipe);
1551
23670b32
DV		 1552 if (HAS_PCH_CPT(dev)) {
1553 /* Workaround: Set the timing override bit before enabling the
1554 * pch transcoder. */
1555 reg = TRANS_CHICKEN2(pipe);
1556 val = I915_READ(reg);
1557 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1558 I915_WRITE(reg, val);
59c859d6 1559 }
23670b32 1560
ab9412ba 1561 reg = PCH_TRANSCONF(pipe);
040484af 1562 val = I915_READ(reg);
5f7f726d 1563 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1564
1565 if (HAS_PCH_IBX(dev_priv->dev)) {
1566 /*
1567 * make the BPC in transcoder be consistent with
1568 * that in pipeconf reg.
1569 */
dfd07d72
DV		 1570 val &= ~PIPECONF_BPC_MASK;
1571 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1572 }
5f7f726d
PZ		 1573
1574 val &= ~TRANS_INTERLACE_MASK;
1575 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1576 if (HAS_PCH_IBX(dev_priv->dev) &&
1577 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1578 val |= TRANS_LEGACY_INTERLACED_ILK;
1579 else
1580 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1581 else
1582 val |= TRANS_PROGRESSIVE;
1583
040484af
JB		 1584 I915_WRITE(reg, val | TRANS_ENABLE);
1585 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1586 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1587}
1588
8fb033d7 1589static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1590 enum transcoder cpu_transcoder)
040484af 1591{
8fb033d7 1592 u32 val, pipeconf_val;
8fb033d7
PZ		 1593
1594 /* PCH only available on ILK+ */
1595 BUG_ON(dev_priv->info->gen < 5);
1596
8fb033d7 1597 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1598 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1599 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1600
223a6fdf
PZ		 1601 /* Workaround: set timing override bit. */
1602 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1603 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1604 I915_WRITE(_TRANSA_CHICKEN2, val);
1605
25f3ef11 1606 val = TRANS_ENABLE;
937bb610 1607 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1608
9a76b1c6
PZ		 1609 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1610 PIPECONF_INTERLACED_ILK)
a35f2679 1611 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1612 else
1613 val |= TRANS_PROGRESSIVE;
1614
ab9412ba
DV		 1615 I915_WRITE(LPT_TRANSCONF, val);
1616 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1617 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1618}
1619
b8a4f404
PZ		 1620static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1621 enum pipe pipe)
040484af 1622{
23670b32
DV		 1623 struct drm_device *dev = dev_priv->dev;
1624 uint32_t reg, val;
040484af
JB		 1625
1626 /* FDI relies on the transcoder */
1627 assert_fdi_tx_disabled(dev_priv, pipe);
1628 assert_fdi_rx_disabled(dev_priv, pipe);
1629
291906f1
JB		 1630 /* Ports must be off as well */
1631 assert_pch_ports_disabled(dev_priv, pipe);
1632
ab9412ba 1633 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1634 val = I915_READ(reg);
1635 val &= ~TRANS_ENABLE;
1636 I915_WRITE(reg, val);
1637 /* wait for PCH transcoder off, transcoder state */
1638 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1639 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1640
1641 if (!HAS_PCH_IBX(dev)) {
1642 /* Workaround: Clear the timing override chicken bit again. */
1643 reg = TRANS_CHICKEN2(pipe);
1644 val = I915_READ(reg);
1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(reg, val);
1647 }
040484af
JB		 1648}
1649
ab4d966c 1650static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1651{
8fb033d7
PZ		 1652 u32 val;
1653
ab9412ba 1654 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1655 val &= ~TRANS_ENABLE;
ab9412ba 1656 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1657 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1658 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1659 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1660
1661 /* Workaround: clear timing override bit. */
1662 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1663 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1664 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1665}
1666
b24e7179 1667/**
309cfea8 1668 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1669 * @dev_priv: i915 private structure
1670 * @pipe: pipe to enable
040484af 1671 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1672 *
1673 * Enable @pipe, making sure that various hardware specific requirements
1674 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1675 *
1676 * @pipe should be %PIPE_A or %PIPE_B.
1677 *
1678 * Will wait until the pipe is actually running (i.e. first vblank) before
1679 * returning.
1680 */
040484af 1681static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1682 bool pch_port, bool dsi)
b24e7179 1683{
702e7a56
PZ		 1684 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1685 pipe);
1a240d4d 1686 enum pipe pch_transcoder;
b24e7179
JB		 1687 int reg;
1688 u32 val;
1689
58c6eaa2
DV		 1690 assert_planes_disabled(dev_priv, pipe);
1691 assert_sprites_disabled(dev_priv, pipe);
1692
681e5811 1693 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1694 pch_transcoder = TRANSCODER_A;
1695 else
1696 pch_transcoder = pipe;
1697
b24e7179
JB		 1698 /*
1699 * A pipe without a PLL won't actually be able to drive bits from
1700 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1701 * need the check.
1702 */
1703 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1704 if (dsi)
1705 assert_dsi_pll_enabled(dev_priv);
1706 else
1707 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1708 else {
1709 if (pch_port) {
1710 /* if driving the PCH, we need FDI enabled */
cc391bbb 1711 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1712 assert_fdi_tx_pll_enabled(dev_priv,
1713 (enum pipe) cpu_transcoder);
040484af
JB		 1714 }
1715 /* FIXME: assert CPU port conditions for SNB+ */
1716 }
b24e7179 1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if (val & PIPECONF_ENABLE)
1721 return;
1722
1723 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_vblank(dev_priv->dev, pipe);
1725}
1726
1727/**
309cfea8 1728 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe to disable
1731 *
1732 * Disable @pipe, making sure that various hardware specific requirements
1733 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1734 *
1735 * @pipe should be %PIPE_A or %PIPE_B.
1736 *
1737 * Will wait until the pipe has shut down before returning.
1738 */
1739static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1740 enum pipe pipe)
1741{
702e7a56
PZ		 1742 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1743 pipe);
b24e7179
JB		 1744 int reg;
1745 u32 val;
1746
1747 /*
1748 * Make sure planes won't keep trying to pump pixels to us,
1749 * or we might hang the display.
1750 */
1751 assert_planes_disabled(dev_priv, pipe);
19332d7a 1752 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1753
1754 /* Don't disable pipe A or pipe A PLLs if needed */
1755 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1756 return;
1757
702e7a56 1758 reg = PIPECONF(cpu_transcoder);
b24e7179 1759 val = I915_READ(reg);
00d70b15
CW		 1760 if ((val & PIPECONF_ENABLE) == 0)
1761 return;
1762
1763 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1764 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1765}
1766
d74362c9
KP		 1767/*
1768 * Plane regs are double buffered, going from enabled->disabled needs a
1769 * trigger in order to latch. The display address reg provides this.
1770 */
6f1d69b0 1771void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1772 enum plane plane)
1773{
14f86147
DL		 1774 if (dev_priv->info->gen >= 4)
1775 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1776 else
1777 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1778}
1779
b24e7179
JB		 1780/**
1781 * intel_enable_plane - enable a display plane on a given pipe
1782 * @dev_priv: i915 private structure
1783 * @plane: plane to enable
1784 * @pipe: pipe being fed
1785 *
1786 * Enable @plane on @pipe, making sure that @pipe is running first.
1787 */
1788static void intel_enable_plane(struct drm_i915_private *dev_priv,
1789 enum plane plane, enum pipe pipe)
1790{
1791 int reg;
1792 u32 val;
1793
1794 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1795 assert_pipe_enabled(dev_priv, pipe);
1796
1797 reg = DSPCNTR(plane);
1798 val = I915_READ(reg);
00d70b15
CW		 1799 if (val & DISPLAY_PLANE_ENABLE)
1800 return;
1801
1802 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1803 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1804 intel_wait_for_vblank(dev_priv->dev, pipe);
1805}
1806
b24e7179
JB		 1807/**
1808 * intel_disable_plane - disable a display plane
1809 * @dev_priv: i915 private structure
1810 * @plane: plane to disable
1811 * @pipe: pipe consuming the data
1812 *
1813 * Disable @plane; should be an independent operation.
1814 */
1815static void intel_disable_plane(struct drm_i915_private *dev_priv,
1816 enum plane plane, enum pipe pipe)
1817{
1818 int reg;
1819 u32 val;
1820
1821 reg = DSPCNTR(plane);
1822 val = I915_READ(reg);
00d70b15
CW		 1823 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1824 return;
1825
1826 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1827 intel_flush_display_plane(dev_priv, plane);
1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
693db184
CW		 1831static bool need_vtd_wa(struct drm_device *dev)
1832{
1833#ifdef CONFIG_INTEL_IOMMU
1834 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1835 return true;
1836#endif
1837 return false;
1838}
1839
127bd2ac 1840int
48b956c5 1841intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1842 struct drm_i915_gem_object *obj,
919926ae 1843 struct intel_ring_buffer *pipelined)
6b95a207 1844{
ce453d81 1845 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1846 u32 alignment;
1847 int ret;
1848
05394f39 1849 switch (obj->tiling_mode) {
6b95a207 1850 case I915_TILING_NONE:
534843da
CW		 1851 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1852 alignment = 128 * 1024;
a6c45cf0 1853 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1854 alignment = 4 * 1024;
1855 else
1856 alignment = 64 * 1024;
6b95a207
KH		 1857 break;
1858 case I915_TILING_X:
1859 /* pin() will align the object as required by fence */
1860 alignment = 0;
1861 break;
1862 case I915_TILING_Y:
8bb6e959
DV		 1863 /* Despite that we check this in framebuffer_init userspace can
1864 * screw us over and change the tiling after the fact. Only
1865 * pinned buffers can't change their tiling. */
1866 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1867 return -EINVAL;
1868 default:
1869 BUG();
1870 }
1871
693db184
CW		 1872 /* Note that the w/a also requires 64 PTE of padding following the
1873 * bo. We currently fill all unused PTE with the shadow page and so
1874 * we should always have valid PTE following the scanout preventing
1875 * the VT-d warning.
1876 */
1877 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1878 alignment = 256 * 1024;
1879
ce453d81 1880 dev_priv->mm.interruptible = false;
2da3b9b9 1881 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1882 if (ret)
ce453d81 1883 goto err_interruptible;
6b95a207
KH		 1884
1885 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1886 * fence, whereas 965+ only requires a fence if using
1887 * framebuffer compression. For simplicity, we always install
1888 * a fence as the cost is not that onerous.
1889 */
06d98131 1890 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1891 if (ret)
1892 goto err_unpin;
1690e1eb 1893
9a5a53b3 1894 i915_gem_object_pin_fence(obj);
6b95a207 1895
ce453d81 1896 dev_priv->mm.interruptible = true;
6b95a207 1897 return 0;
48b956c5
CW		 1898
1899err_unpin:
cc98b413 1900 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1901err_interruptible:
1902 dev_priv->mm.interruptible = true;
48b956c5 1903 return ret;
6b95a207
KH		 1904}
1905
1690e1eb
CW		 1906void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1907{
1908 i915_gem_object_unpin_fence(obj);
cc98b413 1909 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1910}
1911
c2c75131
DV		 1912/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1913 * is assumed to be a power-of-two. */
bc752862
CW		 1914unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1915 unsigned int tiling_mode,
1916 unsigned int cpp,
1917 unsigned int pitch)
c2c75131 1918{
bc752862
CW		 1919 if (tiling_mode != I915_TILING_NONE) {
1920 unsigned int tile_rows, tiles;
c2c75131 1921
bc752862
CW		 1922 tile_rows = *y / 8;
1923 *y %= 8;
c2c75131 1924
bc752862
CW		 1925 tiles = *x / (512/cpp);
1926 *x %= 512/cpp;
1927
1928 return tile_rows * pitch * 8 + tiles * 4096;
1929 } else {
1930 unsigned int offset;
1931
1932 offset = *y * pitch + *x * cpp;
1933 *y = 0;
1934 *x = (offset & 4095) / cpp;
1935 return offset & -4096;
1936 }
c2c75131
DV		 1937}
1938
17638cd6
JB		 1939static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1940 int x, int y)
81255565
JB		 1941{
1942 struct drm_device *dev = crtc->dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1945 struct intel_framebuffer *intel_fb;
05394f39 1946 struct drm_i915_gem_object *obj;
81255565 1947 int plane = intel_crtc->plane;
e506a0c6 1948 unsigned long linear_offset;
81255565 1949 u32 dspcntr;
5eddb70b 1950 u32 reg;
81255565
JB		 1951
1952 switch (plane) {
1953 case 0:
1954 case 1:
1955 break;
1956 default:
84f44ce7 1957 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1958 return -EINVAL;
1959 }
1960
1961 intel_fb = to_intel_framebuffer(fb);
1962 obj = intel_fb->obj;
81255565 1963
5eddb70b
CW		 1964 reg = DSPCNTR(plane);
1965 dspcntr = I915_READ(reg);
81255565
JB		 1966 /* Mask out pixel format bits in case we change it */
1967 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1968 switch (fb->pixel_format) {
1969 case DRM_FORMAT_C8:
81255565
JB		 1970 dspcntr |= DISPPLANE_8BPP;
1971 break;
57779d06
VS		 1972 case DRM_FORMAT_XRGB1555:
1973 case DRM_FORMAT_ARGB1555:
1974 dspcntr |= DISPPLANE_BGRX555;
81255565 1975 break;
57779d06
VS		 1976 case DRM_FORMAT_RGB565:
1977 dspcntr |= DISPPLANE_BGRX565;
1978 break;
1979 case DRM_FORMAT_XRGB8888:
1980 case DRM_FORMAT_ARGB8888:
1981 dspcntr |= DISPPLANE_BGRX888;
1982 break;
1983 case DRM_FORMAT_XBGR8888:
1984 case DRM_FORMAT_ABGR8888:
1985 dspcntr |= DISPPLANE_RGBX888;
1986 break;
1987 case DRM_FORMAT_XRGB2101010:
1988 case DRM_FORMAT_ARGB2101010:
1989 dspcntr |= DISPPLANE_BGRX101010;
1990 break;
1991 case DRM_FORMAT_XBGR2101010:
1992 case DRM_FORMAT_ABGR2101010:
1993 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1994 break;
1995 default:
baba133a 1996 BUG();
81255565 1997 }
57779d06 1998
a6c45cf0 1999 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2000 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2001 dspcntr |= DISPPLANE_TILED;
2002 else
2003 dspcntr &= ~DISPPLANE_TILED;
2004 }
2005
de1aa629
VS		 2006 if (IS_G4X(dev))
2007 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2008
5eddb70b 2009 I915_WRITE(reg, dspcntr);
81255565 2010
e506a0c6 2011 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2012
c2c75131
DV		 2013 if (INTEL_INFO(dev)->gen >= 4) {
2014 intel_crtc->dspaddr_offset =
bc752862
CW		 2015 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2016 fb->bits_per_pixel / 8,
2017 fb->pitches[0]);
c2c75131
DV		 2018 linear_offset -= intel_crtc->dspaddr_offset;
2019 } else {
e506a0c6 2020 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2021 }
e506a0c6 2022
f343c5f6
BW		 2023 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2024 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2025 fb->pitches[0]);
01f2c773 2026 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2027 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2028 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2029 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2030 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2031 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2032 } else
f343c5f6 2033 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2034 POSTING_READ(reg);
81255565 2035
17638cd6
JB		 2036 return 0;
2037}
2038
2039static int ironlake_update_plane(struct drm_crtc *crtc,
2040 struct drm_framebuffer *fb, int x, int y)
2041{
2042 struct drm_device *dev = crtc->dev;
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2045 struct intel_framebuffer *intel_fb;
2046 struct drm_i915_gem_object *obj;
2047 int plane = intel_crtc->plane;
e506a0c6 2048 unsigned long linear_offset;
17638cd6
JB		 2049 u32 dspcntr;
2050 u32 reg;
2051
2052 switch (plane) {
2053 case 0:
2054 case 1:
27f8227b 2055 case 2:
17638cd6
JB		 2056 break;
2057 default:
84f44ce7 2058 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2059 return -EINVAL;
2060 }
2061
2062 intel_fb = to_intel_framebuffer(fb);
2063 obj = intel_fb->obj;
2064
2065 reg = DSPCNTR(plane);
2066 dspcntr = I915_READ(reg);
2067 /* Mask out pixel format bits in case we change it */
2068 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2069 switch (fb->pixel_format) {
2070 case DRM_FORMAT_C8:
17638cd6
JB		 2071 dspcntr |= DISPPLANE_8BPP;
2072 break;
57779d06
VS		 2073 case DRM_FORMAT_RGB565:
2074 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2075 break;
57779d06
VS		 2076 case DRM_FORMAT_XRGB8888:
2077 case DRM_FORMAT_ARGB8888:
2078 dspcntr |= DISPPLANE_BGRX888;
2079 break;
2080 case DRM_FORMAT_XBGR8888:
2081 case DRM_FORMAT_ABGR8888:
2082 dspcntr |= DISPPLANE_RGBX888;
2083 break;
2084 case DRM_FORMAT_XRGB2101010:
2085 case DRM_FORMAT_ARGB2101010:
2086 dspcntr |= DISPPLANE_BGRX101010;
2087 break;
2088 case DRM_FORMAT_XBGR2101010:
2089 case DRM_FORMAT_ABGR2101010:
2090 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2091 break;
2092 default:
baba133a 2093 BUG();
17638cd6
JB		 2094 }
2095
2096 if (obj->tiling_mode != I915_TILING_NONE)
2097 dspcntr |= DISPPLANE_TILED;
2098 else
2099 dspcntr &= ~DISPPLANE_TILED;
2100
1f5d76db
PZ		 2101 if (IS_HASWELL(dev))
2102 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2103 else
2104 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2105
2106 I915_WRITE(reg, dspcntr);
2107
e506a0c6 2108 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2109 intel_crtc->dspaddr_offset =
bc752862
CW		 2110 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2111 fb->bits_per_pixel / 8,
2112 fb->pitches[0]);
c2c75131 2113 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2114
f343c5f6
BW		 2115 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2116 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2117 fb->pitches[0]);
01f2c773 2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2120 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2121 if (IS_HASWELL(dev)) {
2122 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2123 } else {
2124 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2125 I915_WRITE(DSPLINOFF(plane), linear_offset);
2126 }
17638cd6
JB		 2127 POSTING_READ(reg);
2128
2129 return 0;
2130}
2131
2132/* Assume fb object is pinned & idle & fenced and just update base pointers */
2133static int
2134intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2135 int x, int y, enum mode_set_atomic state)
2136{
2137 struct drm_device *dev = crtc->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2139
6b8e6ed0
CW		 2140 if (dev_priv->display.disable_fbc)
2141 dev_priv->display.disable_fbc(dev);
3dec0095 2142 intel_increase_pllclock(crtc);
81255565 2143
6b8e6ed0 2144 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2145}
2146
96a02917
VS		 2147void intel_display_handle_reset(struct drm_device *dev)
2148{
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 struct drm_crtc *crtc;
2151
2152 /*
2153 * Flips in the rings have been nuked by the reset,
2154 * so complete all pending flips so that user space
2155 * will get its events and not get stuck.
2156 *
2157 * Also update the base address of all primary
2158 * planes to the the last fb to make sure we're
2159 * showing the correct fb after a reset.
2160 *
2161 * Need to make two loops over the crtcs so that we
2162 * don't try to grab a crtc mutex before the
2163 * pending_flip_queue really got woken up.
2164 */
2165
2166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 enum plane plane = intel_crtc->plane;
2169
2170 intel_prepare_page_flip(dev, plane);
2171 intel_finish_page_flip_plane(dev, plane);
2172 }
2173
2174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176
2177 mutex_lock(&crtc->mutex);
2178 if (intel_crtc->active)
2179 dev_priv->display.update_plane(crtc, crtc->fb,
2180 crtc->x, crtc->y);
2181 mutex_unlock(&crtc->mutex);
2182 }
2183}
2184
14667a4b
CW		 2185static int
2186intel_finish_fb(struct drm_framebuffer *old_fb)
2187{
2188 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2189 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2190 bool was_interruptible = dev_priv->mm.interruptible;
2191 int ret;
2192
14667a4b
CW		 2193 /* Big Hammer, we also need to ensure that any pending
2194 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2195 * current scanout is retired before unpinning the old
2196 * framebuffer.
2197 *
2198 * This should only fail upon a hung GPU, in which case we
2199 * can safely continue.
2200 */
2201 dev_priv->mm.interruptible = false;
2202 ret = i915_gem_object_finish_gpu(obj);
2203 dev_priv->mm.interruptible = was_interruptible;
2204
2205 return ret;
2206}
2207
198598d0
VS		 2208static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2209{
2210 struct drm_device *dev = crtc->dev;
2211 struct drm_i915_master_private *master_priv;
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 if (!dev->primary->master)
2215 return;
2216
2217 master_priv = dev->primary->master->driver_priv;
2218 if (!master_priv->sarea_priv)
2219 return;
2220
2221 switch (intel_crtc->pipe) {
2222 case 0:
2223 master_priv->sarea_priv->pipeA_x = x;
2224 master_priv->sarea_priv->pipeA_y = y;
2225 break;
2226 case 1:
2227 master_priv->sarea_priv->pipeB_x = x;
2228 master_priv->sarea_priv->pipeB_y = y;
2229 break;
2230 default:
2231 break;
2232 }
2233}
2234
5c3b82e2 2235static int
3c4fdcfb 2236intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2237 struct drm_framebuffer *fb)
79e53945
JB		 2238{
2239 struct drm_device *dev = crtc->dev;
6b8e6ed0 2240 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2242 struct drm_framebuffer *old_fb;
5c3b82e2 2243 int ret;
79e53945
JB		 2244
2245 /* no fb bound */
94352cf9 2246 if (!fb) {
a5071c2f 2247 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2248 return 0;
2249 }
2250
7eb552ae 2251 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2252 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2253 plane_name(intel_crtc->plane),
2254 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2255 return -EINVAL;
79e53945
JB		 2256 }
2257
5c3b82e2 2258 mutex_lock(&dev->struct_mutex);
265db958 2259 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2260 to_intel_framebuffer(fb)->obj,
919926ae 2261 NULL);
5c3b82e2
CW		 2262 if (ret != 0) {
2263 mutex_unlock(&dev->struct_mutex);
a5071c2f 2264 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2265 return ret;
2266 }
79e53945 2267
4d6a3e63
JB		 2268 /* Update pipe size and adjust fitter if needed */
2269 if (i915_fastboot) {
2270 I915_WRITE(PIPESRC(intel_crtc->pipe),
2271 ((crtc->mode.hdisplay - 1) << 16) |
2272 (crtc->mode.vdisplay - 1));
2273 if (!intel_crtc->config.pch_pfit.size &&
2274 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2275 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2276 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2277 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2278 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2279 }
2280 }
2281
94352cf9 2282 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2283 if (ret) {
94352cf9 2284 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2285 mutex_unlock(&dev->struct_mutex);
a5071c2f 2286 DRM_ERROR("failed to update base address\n");
4e6cfefc 2287 return ret;
79e53945 2288 }
3c4fdcfb 2289
94352cf9
DV		 2290 old_fb = crtc->fb;
2291 crtc->fb = fb;
6c4c86f5
DV		 2292 crtc->x = x;
2293 crtc->y = y;
94352cf9 2294
b7f1de28 2295 if (old_fb) {
d7697eea
DV		 2296 if (intel_crtc->active && old_fb != fb)
2297 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2298 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2299 }
652c393a 2300
6b8e6ed0 2301 intel_update_fbc(dev);
4906557e 2302 intel_edp_psr_update(dev);
5c3b82e2 2303 mutex_unlock(&dev->struct_mutex);
79e53945 2304
198598d0 2305 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2306
2307 return 0;
79e53945
JB		 2308}
2309
5e84e1a4
ZW		 2310static void intel_fdi_normal_train(struct drm_crtc *crtc)
2311{
2312 struct drm_device *dev = crtc->dev;
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2315 int pipe = intel_crtc->pipe;
2316 u32 reg, temp;
2317
2318 /* enable normal train */
2319 reg = FDI_TX_CTL(pipe);
2320 temp = I915_READ(reg);
61e499bf 2321 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2322 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2323 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2327 }
5e84e1a4
ZW		 2328 I915_WRITE(reg, temp);
2329
2330 reg = FDI_RX_CTL(pipe);
2331 temp = I915_READ(reg);
2332 if (HAS_PCH_CPT(dev)) {
2333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2334 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2335 } else {
2336 temp &= ~FDI_LINK_TRAIN_NONE;
2337 temp |= FDI_LINK_TRAIN_NONE;
2338 }
2339 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2340
2341 /* wait one idle pattern time */
2342 POSTING_READ(reg);
2343 udelay(1000);
357555c0
JB		 2344
2345 /* IVB wants error correction enabled */
2346 if (IS_IVYBRIDGE(dev))
2347 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2348 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2349}
2350
1e833f40
DV		 2351static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2352{
2353 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2354}
2355
01a415fd
DV		 2356static void ivb_modeset_global_resources(struct drm_device *dev)
2357{
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *pipe_B_crtc =
2360 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2361 struct intel_crtc *pipe_C_crtc =
2362 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2363 uint32_t temp;
2364
1e833f40
DV		 2365 /*
2366 * When everything is off disable fdi C so that we could enable fdi B
2367 * with all lanes. Note that we don't care about enabled pipes without
2368 * an enabled pch encoder.
2369 */
2370 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2371 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2372 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2373 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2374
2375 temp = I915_READ(SOUTH_CHICKEN1);
2376 temp &= ~FDI_BC_BIFURCATION_SELECT;
2377 DRM_DEBUG_KMS("disabling fdi C rx\n");
2378 I915_WRITE(SOUTH_CHICKEN1, temp);
2379 }
2380}
2381
8db9d77b
ZW		 2382/* The FDI link training functions for ILK/Ibexpeak. */
2383static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
0fc932b8 2389 int plane = intel_crtc->plane;
5eddb70b 2390 u32 reg, temp, tries;
8db9d77b 2391
0fc932b8
JB		 2392 /* FDI needs bits from pipe & plane first */
2393 assert_pipe_enabled(dev_priv, pipe);
2394 assert_plane_enabled(dev_priv, plane);
2395
e1a44743
AJ		 2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW		 2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ		 2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2402 I915_WRITE(reg, temp);
2403 I915_READ(reg);
e1a44743
AJ		 2404 udelay(150);
2405
8db9d77b 2406 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2407 reg = FDI_TX_CTL(pipe);
2408 temp = I915_READ(reg);
627eb5a3
DV		 2409 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2410 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2411 temp &= ~FDI_LINK_TRAIN_NONE;
2412 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2413 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2414
5eddb70b
CW		 2415 reg = FDI_RX_CTL(pipe);
2416 temp = I915_READ(reg);
8db9d77b
ZW		 2417 temp &= ~FDI_LINK_TRAIN_NONE;
2418 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2419 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2420
2421 POSTING_READ(reg);
8db9d77b
ZW		 2422 udelay(150);
2423
5b2adf89 2424 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2428
5eddb70b 2429 reg = FDI_RX_IIR(pipe);
e1a44743 2430 for (tries = 0; tries < 5; tries++) {
5eddb70b 2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434 if ((temp & FDI_RX_BIT_LOCK)) {
2435 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2436 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2437 break;
2438 }
8db9d77b 2439 }
e1a44743 2440 if (tries == 5)
5eddb70b 2441 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2442
2443 /* Train 2 */
5eddb70b
CW		 2444 reg = FDI_TX_CTL(pipe);
2445 temp = I915_READ(reg);
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2448 I915_WRITE(reg, temp);
8db9d77b 2449
5eddb70b
CW		 2450 reg = FDI_RX_CTL(pipe);
2451 temp = I915_READ(reg);
8db9d77b
ZW		 2452 temp &= ~FDI_LINK_TRAIN_NONE;
2453 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2454 I915_WRITE(reg, temp);
8db9d77b 2455
5eddb70b
CW		 2456 POSTING_READ(reg);
2457 udelay(150);
8db9d77b 2458
5eddb70b 2459 reg = FDI_RX_IIR(pipe);
e1a44743 2460 for (tries = 0; tries < 5; tries++) {
5eddb70b 2461 temp = I915_READ(reg);
8db9d77b
ZW		 2462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463
2464 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2466 DRM_DEBUG_KMS("FDI train 2 done.\n");
2467 break;
2468 }
8db9d77b 2469 }
e1a44743 2470 if (tries == 5)
5eddb70b 2471 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2472
2473 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2474
8db9d77b
ZW		 2475}
2476
0206e353 2477static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2478 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2479 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2480 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2481 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2482};
2483
2484/* The FDI link training functions for SNB/Cougarpoint. */
2485static void gen6_fdi_link_train(struct drm_crtc *crtc)
2486{
2487 struct drm_device *dev = crtc->dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490 int pipe = intel_crtc->pipe;
fa37d39e 2491 u32 reg, temp, i, retry;
8db9d77b 2492
e1a44743
AJ		 2493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2494 for train result */
5eddb70b
CW		 2495 reg = FDI_RX_IMR(pipe);
2496 temp = I915_READ(reg);
e1a44743
AJ		 2497 temp &= ~FDI_RX_SYMBOL_LOCK;
2498 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2499 I915_WRITE(reg, temp);
2500
2501 POSTING_READ(reg);
e1a44743
AJ		 2502 udelay(150);
2503
8db9d77b 2504 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
627eb5a3
DV		 2507 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2508 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2509 temp &= ~FDI_LINK_TRAIN_NONE;
2510 temp |= FDI_LINK_TRAIN_PATTERN_1;
2511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512 /* SNB-B */
2513 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2514 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2515
d74cf324
DV		 2516 I915_WRITE(FDI_RX_MISC(pipe),
2517 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2518
5eddb70b
CW		 2519 reg = FDI_RX_CTL(pipe);
2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 if (HAS_PCH_CPT(dev)) {
2522 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2524 } else {
2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527 }
5eddb70b
CW		 2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(150);
2532
0206e353 2533 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2534 reg = FDI_TX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2538 I915_WRITE(reg, temp);
2539
2540 POSTING_READ(reg);
8db9d77b
ZW		 2541 udelay(500);
2542
fa37d39e
SP		 2543 for (retry = 0; retry < 5; retry++) {
2544 reg = FDI_RX_IIR(pipe);
2545 temp = I915_READ(reg);
2546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547 if (temp & FDI_RX_BIT_LOCK) {
2548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549 DRM_DEBUG_KMS("FDI train 1 done.\n");
2550 break;
2551 }
2552 udelay(50);
8db9d77b 2553 }
fa37d39e
SP		 2554 if (retry < 5)
2555 break;
8db9d77b
ZW		 2556 }
2557 if (i == 4)
5eddb70b 2558 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2559
2560 /* Train 2 */
5eddb70b
CW		 2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW		 2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
2565 if (IS_GEN6(dev)) {
2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 /* SNB-B */
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569 }
5eddb70b 2570 I915_WRITE(reg, temp);
8db9d77b 2571
5eddb70b
CW		 2572 reg = FDI_RX_CTL(pipe);
2573 temp = I915_READ(reg);
8db9d77b
ZW		 2574 if (HAS_PCH_CPT(dev)) {
2575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2576 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2577 } else {
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 }
5eddb70b
CW		 2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
8db9d77b
ZW		 2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
8db9d77b
ZW		 2594 udelay(500);
2595
fa37d39e
SP		 2596 for (retry = 0; retry < 5; retry++) {
2597 reg = FDI_RX_IIR(pipe);
2598 temp = I915_READ(reg);
2599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2600 if (temp & FDI_RX_SYMBOL_LOCK) {
2601 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2602 DRM_DEBUG_KMS("FDI train 2 done.\n");
2603 break;
2604 }
2605 udelay(50);
8db9d77b 2606 }
fa37d39e
SP		 2607 if (retry < 5)
2608 break;
8db9d77b
ZW		 2609 }
2610 if (i == 4)
5eddb70b 2611 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2612
2613 DRM_DEBUG_KMS("FDI train done.\n");
2614}
2615
357555c0
JB		 2616/* Manual link training for Ivy Bridge A0 parts */
2617static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2618{
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 int pipe = intel_crtc->pipe;
139ccd3f 2623 u32 reg, temp, i, j;
357555c0
JB		 2624
2625 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2626 for train result */
2627 reg = FDI_RX_IMR(pipe);
2628 temp = I915_READ(reg);
2629 temp &= ~FDI_RX_SYMBOL_LOCK;
2630 temp &= ~FDI_RX_BIT_LOCK;
2631 I915_WRITE(reg, temp);
2632
2633 POSTING_READ(reg);
2634 udelay(150);
2635
01a415fd
DV		 2636 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2637 I915_READ(FDI_RX_IIR(pipe)));
2638
139ccd3f
JB		 2639 /* Try each vswing and preemphasis setting twice before moving on */
2640 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2641 /* disable first in case we need to retry */
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2645 temp &= ~FDI_TX_ENABLE;
2646 I915_WRITE(reg, temp);
357555c0 2647
139ccd3f
JB		 2648 reg = FDI_RX_CTL(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_LINK_TRAIN_AUTO;
2651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652 temp &= ~FDI_RX_ENABLE;
2653 I915_WRITE(reg, temp);
357555c0 2654
139ccd3f 2655 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2656 reg = FDI_TX_CTL(pipe);
2657 temp = I915_READ(reg);
139ccd3f
JB		 2658 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2659 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2662 temp |= snb_b_fdi_train_param[j/2];
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2665
139ccd3f
JB		 2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2668
139ccd3f 2669 reg = FDI_RX_CTL(pipe);
357555c0 2670 temp = I915_READ(reg);
139ccd3f
JB		 2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672 temp |= FDI_COMPOSITE_SYNC;
2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2674
139ccd3f
JB		 2675 POSTING_READ(reg);
2676 udelay(1); /* should be 0.5us */
357555c0 2677
139ccd3f
JB		 2678 for (i = 0; i < 4; i++) {
2679 reg = FDI_RX_IIR(pipe);
2680 temp = I915_READ(reg);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2682
139ccd3f
JB		 2683 if (temp & FDI_RX_BIT_LOCK ||
2684 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2685 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2686 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2687 i);
2688 break;
2689 }
2690 udelay(1); /* should be 0.5us */
2691 }
2692 if (i == 4) {
2693 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2694 continue;
2695 }
357555c0 2696
139ccd3f 2697 /* Train 2 */
357555c0
JB		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
139ccd3f
JB		 2700 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2701 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2702 I915_WRITE(reg, temp);
2703
2704 reg = FDI_RX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2707 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2708 I915_WRITE(reg, temp);
2709
2710 POSTING_READ(reg);
139ccd3f 2711 udelay(2); /* should be 1.5us */
357555c0 2712
139ccd3f
JB		 2713 for (i = 0; i < 4; i++) {
2714 reg = FDI_RX_IIR(pipe);
2715 temp = I915_READ(reg);
2716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2717
139ccd3f
JB		 2718 if (temp & FDI_RX_SYMBOL_LOCK ||
2719 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2720 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2721 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2722 i);
2723 goto train_done;
2724 }
2725 udelay(2); /* should be 1.5us */
357555c0 2726 }
139ccd3f
JB		 2727 if (i == 4)
2728 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2729 }
357555c0 2730
139ccd3f 2731train_done:
357555c0
JB		 2732 DRM_DEBUG_KMS("FDI train done.\n");
2733}
2734
88cefb6c 2735static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2736{
88cefb6c 2737 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2738 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2739 int pipe = intel_crtc->pipe;
5eddb70b 2740 u32 reg, temp;
79e53945 2741
c64e311e 2742
c98e9dcf 2743 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2744 reg = FDI_RX_CTL(pipe);
2745 temp = I915_READ(reg);
627eb5a3
DV		 2746 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2747 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2749 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2750
2751 POSTING_READ(reg);
c98e9dcf
JB		 2752 udelay(200);
2753
2754 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2755 temp = I915_READ(reg);
2756 I915_WRITE(reg, temp | FDI_PCDCLK);
2757
2758 POSTING_READ(reg);
c98e9dcf
JB		 2759 udelay(200);
2760
20749730
PZ		 2761 /* Enable CPU FDI TX PLL, always on for Ironlake */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2765 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2766
20749730
PZ		 2767 POSTING_READ(reg);
2768 udelay(100);
6be4a607 2769 }
0e23b99d
JB		 2770}
2771
88cefb6c
DV		 2772static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2773{
2774 struct drm_device *dev = intel_crtc->base.dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 int pipe = intel_crtc->pipe;
2777 u32 reg, temp;
2778
2779 /* Switch from PCDclk to Rawclk */
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2783
2784 /* Disable CPU FDI TX PLL */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2788
2789 POSTING_READ(reg);
2790 udelay(100);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2795
2796 /* Wait for the clocks to turn off. */
2797 POSTING_READ(reg);
2798 udelay(100);
2799}
2800
0fc932b8
JB		 2801static void ironlake_fdi_disable(struct drm_crtc *crtc)
2802{
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 int pipe = intel_crtc->pipe;
2807 u32 reg, temp;
2808
2809 /* disable CPU FDI tx and PCH FDI rx */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2813 POSTING_READ(reg);
2814
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 temp &= ~(0x7 << 16);
dfd07d72 2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2819 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2820
2821 POSTING_READ(reg);
2822 udelay(100);
2823
2824 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2825 if (HAS_PCH_IBX(dev)) {
2826 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2827 }
0fc932b8
JB		 2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
dfd07d72 2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
5bb61643
CW		 2854static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2855{
2856 struct drm_device *dev = crtc->dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2859 unsigned long flags;
2860 bool pending;
2861
10d83730
VS		 2862 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2863 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2864 return false;
2865
2866 spin_lock_irqsave(&dev->event_lock, flags);
2867 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2868 spin_unlock_irqrestore(&dev->event_lock, flags);
2869
2870 return pending;
2871}
2872
e6c3a2a6
CW		 2873static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2874{
0f91128d 2875 struct drm_device *dev = crtc->dev;
5bb61643 2876 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2877
2878 if (crtc->fb == NULL)
2879 return;
2880
2c10d571
DV		 2881 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2882
5bb61643
CW		 2883 wait_event(dev_priv->pending_flip_queue,
2884 !intel_crtc_has_pending_flip(crtc));
2885
0f91128d
CW		 2886 mutex_lock(&dev->struct_mutex);
2887 intel_finish_fb(crtc->fb);
2888 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2889}
2890
e615efe4
ED		 2891/* Program iCLKIP clock to the desired frequency */
2892static void lpt_program_iclkip(struct drm_crtc *crtc)
2893{
2894 struct drm_device *dev = crtc->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2897 u32 temp;
2898
09153000
DV		 2899 mutex_lock(&dev_priv->dpio_lock);
2900
e615efe4
ED		 2901 /* It is necessary to ungate the pixclk gate prior to programming
2902 * the divisors, and gate it back when it is done.
2903 */
2904 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2905
2906 /* Disable SSCCTL */
2907 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2908 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2909 SBI_SSCCTL_DISABLE,
2910 SBI_ICLK);
e615efe4
ED		 2911
2912 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2913 if (crtc->mode.clock == 20000) {
2914 auxdiv = 1;
2915 divsel = 0x41;
2916 phaseinc = 0x20;
2917 } else {
2918 /* The iCLK virtual clock root frequency is in MHz,
2919 * but the crtc->mode.clock in in KHz. To get the divisors,
2920 * it is necessary to divide one by another, so we
2921 * convert the virtual clock precision to KHz here for higher
2922 * precision.
2923 */
2924 u32 iclk_virtual_root_freq = 172800 * 1000;
2925 u32 iclk_pi_range = 64;
2926 u32 desired_divisor, msb_divisor_value, pi_value;
2927
2928 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2929 msb_divisor_value = desired_divisor / iclk_pi_range;
2930 pi_value = desired_divisor % iclk_pi_range;
2931
2932 auxdiv = 0;
2933 divsel = msb_divisor_value - 2;
2934 phaseinc = pi_value;
2935 }
2936
2937 /* This should not happen with any sane values */
2938 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2939 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2940 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2941 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2942
2943 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2944 crtc->mode.clock,
2945 auxdiv,
2946 divsel,
2947 phasedir,
2948 phaseinc);
2949
2950 /* Program SSCDIVINTPHASE6 */
988d6ee8 2951 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2952 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2953 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2954 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2955 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2956 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2957 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2958 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2959
2960 /* Program SSCAUXDIV */
988d6ee8 2961 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2962 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2963 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2964 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2965
2966 /* Enable modulator and associated divider */
988d6ee8 2967 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2968 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2970
2971 /* Wait for initialization time */
2972 udelay(24);
2973
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2975
2976 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2977}
2978
275f01b2
DV		 2979static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2980 enum pipe pch_transcoder)
2981{
2982 struct drm_device *dev = crtc->base.dev;
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2985
2986 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2987 I915_READ(HTOTAL(cpu_transcoder)));
2988 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2989 I915_READ(HBLANK(cpu_transcoder)));
2990 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2991 I915_READ(HSYNC(cpu_transcoder)));
2992
2993 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2994 I915_READ(VTOTAL(cpu_transcoder)));
2995 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2996 I915_READ(VBLANK(cpu_transcoder)));
2997 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2998 I915_READ(VSYNC(cpu_transcoder)));
2999 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3000 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3001}
3002
f67a559d
JB		 3003/*
3004 * Enable PCH resources required for PCH ports:
3005 * - PCH PLLs
3006 * - FDI training & RX/TX
3007 * - update transcoder timings
3008 * - DP transcoding bits
3009 * - transcoder
3010 */
3011static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3012{
3013 struct drm_device *dev = crtc->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3016 int pipe = intel_crtc->pipe;
ee7b9f93 3017 u32 reg, temp;
2c07245f 3018
ab9412ba 3019 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3020
cd986abb
DV		 3021 /* Write the TU size bits before fdi link training, so that error
3022 * detection works. */
3023 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3024 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3025
c98e9dcf 3026 /* For PCH output, training FDI link */
674cf967 3027 dev_priv->display.fdi_link_train(crtc);
2c07245f 3028
3ad8a208
DV		 3029 /* We need to program the right clock selection before writing the pixel
3030 * mutliplier into the DPLL. */
303b81e0 3031 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3032 u32 sel;
4b645f14 3033
c98e9dcf 3034 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3035 temp |= TRANS_DPLL_ENABLE(pipe);
3036 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3037 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3038 temp |= sel;
3039 else
3040 temp &= ~sel;
c98e9dcf 3041 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3042 }
5eddb70b 3043
3ad8a208
DV		 3044 /* XXX: pch pll's can be enabled any time before we enable the PCH
3045 * transcoder, and we actually should do this to not upset any PCH
3046 * transcoder that already use the clock when we share it.
3047 *
3048 * Note that enable_shared_dpll tries to do the right thing, but
3049 * get_shared_dpll unconditionally resets the pll - we need that to have
3050 * the right LVDS enable sequence. */
3051 ironlake_enable_shared_dpll(intel_crtc);
3052
d9b6cb56
JB		 3053 /* set transcoder timing, panel must allow it */
3054 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3056
303b81e0 3057 intel_fdi_normal_train(crtc);
5e84e1a4 3058
c98e9dcf
JB		 3059 /* For PCH DP, enable TRANS_DP_CTL */
3060 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3061 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3062 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3063 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3064 reg = TRANS_DP_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3067 TRANS_DP_SYNC_MASK |
3068 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3069 temp |= (TRANS_DP_OUTPUT_ENABLE |
3070 TRANS_DP_ENH_FRAMING);
9325c9f0 3071 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3072
3073 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3074 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3075 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3076 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3077
3078 switch (intel_trans_dp_port_sel(crtc)) {
3079 case PCH_DP_B:
5eddb70b 3080 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3081 break;
3082 case PCH_DP_C:
5eddb70b 3083 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3084 break;
3085 case PCH_DP_D:
5eddb70b 3086 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3087 break;
3088 default:
e95d41e1 3089 BUG();
32f9d658 3090 }
2c07245f 3091
5eddb70b 3092 I915_WRITE(reg, temp);
6be4a607 3093 }
b52eb4dc 3094
b8a4f404 3095 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3096}
3097
1507e5bd
PZ		 3098static void lpt_pch_enable(struct drm_crtc *crtc)
3099{
3100 struct drm_device *dev = crtc->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3103 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3104
ab9412ba 3105 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3106
8c52b5e8 3107 lpt_program_iclkip(crtc);
1507e5bd 3108
0540e488 3109 /* Set transcoder timing. */
275f01b2 3110 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3111
937bb610 3112 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3113}
3114
e2b78267 3115static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3116{
e2b78267 3117 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3118
3119 if (pll == NULL)
3120 return;
3121
3122 if (pll->refcount == 0) {
46edb027 3123 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3124 return;
3125 }
3126
f4a091c7
DV		 3127 if (--pll->refcount == 0) {
3128 WARN_ON(pll->on);
3129 WARN_ON(pll->active);
3130 }
3131
a43f6e0f 3132 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3133}
3134
b89a1d39 3135static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3136{
e2b78267
DV		 3137 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3138 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3139 enum intel_dpll_id i;
ee7b9f93 3140
ee7b9f93 3141 if (pll) {
46edb027
DV		 3142 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3143 crtc->base.base.id, pll->name);
e2b78267 3144 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3145 }
3146
98b6bd99
DV		 3147 if (HAS_PCH_IBX(dev_priv->dev)) {
3148 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3149 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3150 pll = &dev_priv->shared_dplls[i];
98b6bd99 3151
46edb027
DV		 3152 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3153 crtc->base.base.id, pll->name);
98b6bd99
DV		 3154
3155 goto found;
3156 }
3157
e72f9fbf
DV		 3158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3159 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3160
3161 /* Only want to check enabled timings first */
3162 if (pll->refcount == 0)
3163 continue;
3164
b89a1d39
DV		 3165 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3166 sizeof(pll->hw_state)) == 0) {
46edb027 3167 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3168 crtc->base.base.id,
46edb027 3169 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3170
3171 goto found;
3172 }
3173 }
3174
3175 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3176 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3177 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3178 if (pll->refcount == 0) {
46edb027
DV		 3179 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3180 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3181 goto found;
3182 }
3183 }
3184
3185 return NULL;
3186
3187found:
a43f6e0f 3188 crtc->config.shared_dpll = i;
46edb027
DV		 3189 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3190 pipe_name(crtc->pipe));
ee7b9f93 3191
cdbd2316 3192 if (pll->active == 0) {
66e985c0
DV		 3193 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3194 sizeof(pll->hw_state));
3195
46edb027 3196 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3197 WARN_ON(pll->on);
e9d6944e 3198 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3199
15bdd4cf 3200 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3201 }
3202 pll->refcount++;
e04c7350 3203
ee7b9f93
JB		 3204 return pll;
3205}
3206
a1520318 3207static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3208{
3209 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3210 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3211 u32 temp;
3212
3213 temp = I915_READ(dslreg);
3214 udelay(500);
3215 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3216 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3217 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3218 }
3219}
3220
b074cec8
JB		 3221static void ironlake_pfit_enable(struct intel_crtc *crtc)
3222{
3223 struct drm_device *dev = crtc->base.dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 int pipe = crtc->pipe;
3226
0ef37f3f 3227 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3228 /* Force use of hard-coded filter coefficients
3229 * as some pre-programmed values are broken,
3230 * e.g. x201.
3231 */
3232 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3233 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3234 PF_PIPE_SEL_IVB(pipe));
3235 else
3236 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3237 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3238 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3239 }
3240}
3241
bb53d4ae
VS		 3242static void intel_enable_planes(struct drm_crtc *crtc)
3243{
3244 struct drm_device *dev = crtc->dev;
3245 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3246 struct intel_plane *intel_plane;
3247
3248 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3249 if (intel_plane->pipe == pipe)
3250 intel_plane_restore(&intel_plane->base);
3251}
3252
3253static void intel_disable_planes(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3257 struct intel_plane *intel_plane;
3258
3259 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3260 if (intel_plane->pipe == pipe)
3261 intel_plane_disable(&intel_plane->base);
3262}
3263
f67a559d
JB		 3264static void ironlake_crtc_enable(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3269 struct intel_encoder *encoder;
f67a559d
JB		 3270 int pipe = intel_crtc->pipe;
3271 int plane = intel_crtc->plane;
f67a559d 3272
08a48469
DV		 3273 WARN_ON(!crtc->enabled);
3274
f67a559d
JB		 3275 if (intel_crtc->active)
3276 return;
3277
3278 intel_crtc->active = true;
8664281b
PZ		 3279
3280 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3281 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3282
f67a559d
JB		 3283 intel_update_watermarks(dev);
3284
f6736a1a 3285 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3286 if (encoder->pre_enable)
3287 encoder->pre_enable(encoder);
f67a559d 3288
5bfe2ac0 3289 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3290 /* Note: FDI PLL enabling _must_ be done before we enable the
3291 * cpu pipes, hence this is separate from all the other fdi/pch
3292 * enabling. */
88cefb6c 3293 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3294 } else {
3295 assert_fdi_tx_disabled(dev_priv, pipe);
3296 assert_fdi_rx_disabled(dev_priv, pipe);
3297 }
f67a559d 3298
b074cec8 3299 ironlake_pfit_enable(intel_crtc);
f67a559d 3300
9c54c0dd
JB		 3301 /*
3302 * On ILK+ LUT must be loaded before the pipe is running but with
3303 * clocks enabled
3304 */
3305 intel_crtc_load_lut(crtc);
3306
5bfe2ac0 3307 intel_enable_pipe(dev_priv, pipe,
23538ef1 3308 intel_crtc->config.has_pch_encoder, false);
f67a559d 3309 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3310 intel_enable_planes(crtc);
5c38d48c 3311 intel_crtc_update_cursor(crtc, true);
f67a559d 3312
5bfe2ac0 3313 if (intel_crtc->config.has_pch_encoder)
f67a559d 3314 ironlake_pch_enable(crtc);
c98e9dcf 3315
d1ebd816 3316 mutex_lock(&dev->struct_mutex);
bed4a673 3317 intel_update_fbc(dev);
d1ebd816
BW		 3318 mutex_unlock(&dev->struct_mutex);
3319
fa5c73b1
DV		 3320 for_each_encoder_on_crtc(dev, crtc, encoder)
3321 encoder->enable(encoder);
61b77ddd
DV		 3322
3323 if (HAS_PCH_CPT(dev))
a1520318 3324 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3325
3326 /*
3327 * There seems to be a race in PCH platform hw (at least on some
3328 * outputs) where an enabled pipe still completes any pageflip right
3329 * away (as if the pipe is off) instead of waiting for vblank. As soon
3330 * as the first vblank happend, everything works as expected. Hence just
3331 * wait for one vblank before returning to avoid strange things
3332 * happening.
3333 */
3334 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3335}
3336
42db64ef
PZ		 3337/* IPS only exists on ULT machines and is tied to pipe A. */
3338static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3339{
f5adf94e 3340 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3341}
3342
3343static void hsw_enable_ips(struct intel_crtc *crtc)
3344{
3345 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3346
3347 if (!crtc->config.ips_enabled)
3348 return;
3349
3350 /* We can only enable IPS after we enable a plane and wait for a vblank.
3351 * We guarantee that the plane is enabled by calling intel_enable_ips
3352 * only after intel_enable_plane. And intel_enable_plane already waits
3353 * for a vblank, so all we need to do here is to enable the IPS bit. */
3354 assert_plane_enabled(dev_priv, crtc->plane);
3355 I915_WRITE(IPS_CTL, IPS_ENABLE);
3356}
3357
3358static void hsw_disable_ips(struct intel_crtc *crtc)
3359{
3360 struct drm_device *dev = crtc->base.dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362
3363 if (!crtc->config.ips_enabled)
3364 return;
3365
3366 assert_plane_enabled(dev_priv, crtc->plane);
3367 I915_WRITE(IPS_CTL, 0);
3368
3369 /* We need to wait for a vblank before we can disable the plane. */
3370 intel_wait_for_vblank(dev, crtc->pipe);
3371}
3372
4f771f10
PZ		 3373static void haswell_crtc_enable(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3378 struct intel_encoder *encoder;
3379 int pipe = intel_crtc->pipe;
3380 int plane = intel_crtc->plane;
4f771f10
PZ		 3381
3382 WARN_ON(!crtc->enabled);
3383
3384 if (intel_crtc->active)
3385 return;
3386
3387 intel_crtc->active = true;
8664281b
PZ		 3388
3389 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3390 if (intel_crtc->config.has_pch_encoder)
3391 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3392
4f771f10
PZ		 3393 intel_update_watermarks(dev);
3394
5bfe2ac0 3395 if (intel_crtc->config.has_pch_encoder)
04945641 3396 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3397
3398 for_each_encoder_on_crtc(dev, crtc, encoder)
3399 if (encoder->pre_enable)
3400 encoder->pre_enable(encoder);
3401
1f544388 3402 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3403
b074cec8 3404 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3405
3406 /*
3407 * On ILK+ LUT must be loaded before the pipe is running but with
3408 * clocks enabled
3409 */
3410 intel_crtc_load_lut(crtc);
3411
1f544388 3412 intel_ddi_set_pipe_settings(crtc);
8228c251 3413 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3414
5bfe2ac0 3415 intel_enable_pipe(dev_priv, pipe,
23538ef1 3416 intel_crtc->config.has_pch_encoder, false);
4f771f10 3417 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3418 intel_enable_planes(crtc);
5c38d48c 3419 intel_crtc_update_cursor(crtc, true);
4f771f10 3420
42db64ef
PZ		 3421 hsw_enable_ips(intel_crtc);
3422
5bfe2ac0 3423 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3424 lpt_pch_enable(crtc);
4f771f10
PZ		 3425
3426 mutex_lock(&dev->struct_mutex);
3427 intel_update_fbc(dev);
3428 mutex_unlock(&dev->struct_mutex);
3429
8807e55b 3430 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3431 encoder->enable(encoder);
8807e55b
JN		 3432 intel_opregion_notify_encoder(encoder, true);
3433 }
4f771f10 3434
4f771f10
PZ		 3435 /*
3436 * There seems to be a race in PCH platform hw (at least on some
3437 * outputs) where an enabled pipe still completes any pageflip right
3438 * away (as if the pipe is off) instead of waiting for vblank. As soon
3439 * as the first vblank happend, everything works as expected. Hence just
3440 * wait for one vblank before returning to avoid strange things
3441 * happening.
3442 */
3443 intel_wait_for_vblank(dev, intel_crtc->pipe);
3444}
3445
3f8dce3a
DV		 3446static void ironlake_pfit_disable(struct intel_crtc *crtc)
3447{
3448 struct drm_device *dev = crtc->base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 int pipe = crtc->pipe;
3451
3452 /* To avoid upsetting the power well on haswell only disable the pfit if
3453 * it's in use. The hw state code will make sure we get this right. */
3454 if (crtc->config.pch_pfit.size) {
3455 I915_WRITE(PF_CTL(pipe), 0);
3456 I915_WRITE(PF_WIN_POS(pipe), 0);
3457 I915_WRITE(PF_WIN_SZ(pipe), 0);
3458 }
3459}
3460
6be4a607
JB		 3461static void ironlake_crtc_disable(struct drm_crtc *crtc)
3462{
3463 struct drm_device *dev = crtc->dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3466 struct intel_encoder *encoder;
6be4a607
JB		 3467 int pipe = intel_crtc->pipe;
3468 int plane = intel_crtc->plane;
5eddb70b 3469 u32 reg, temp;
b52eb4dc 3470
ef9c3aee 3471
f7abfe8b
CW		 3472 if (!intel_crtc->active)
3473 return;
3474
ea9d758d
DV		 3475 for_each_encoder_on_crtc(dev, crtc, encoder)
3476 encoder->disable(encoder);
3477
e6c3a2a6 3478 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3479 drm_vblank_off(dev, pipe);
913d8d11 3480
5c3fe8b0 3481 if (dev_priv->fbc.plane == plane)
973d04f9 3482 intel_disable_fbc(dev);
2c07245f 3483
0d5b8c61 3484 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3485 intel_disable_planes(crtc);
0d5b8c61
VS		 3486 intel_disable_plane(dev_priv, plane, pipe);
3487
d925c59a
DV		 3488 if (intel_crtc->config.has_pch_encoder)
3489 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3490
b24e7179 3491 intel_disable_pipe(dev_priv, pipe);
32f9d658 3492
3f8dce3a 3493 ironlake_pfit_disable(intel_crtc);
2c07245f 3494
bf49ec8c
DV		 3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 if (encoder->post_disable)
3497 encoder->post_disable(encoder);
2c07245f 3498
d925c59a
DV		 3499 if (intel_crtc->config.has_pch_encoder) {
3500 ironlake_fdi_disable(crtc);
913d8d11 3501
d925c59a
DV		 3502 ironlake_disable_pch_transcoder(dev_priv, pipe);
3503 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3504
d925c59a
DV		 3505 if (HAS_PCH_CPT(dev)) {
3506 /* disable TRANS_DP_CTL */
3507 reg = TRANS_DP_CTL(pipe);
3508 temp = I915_READ(reg);
3509 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3510 TRANS_DP_PORT_SEL_MASK);
3511 temp |= TRANS_DP_PORT_SEL_NONE;
3512 I915_WRITE(reg, temp);
3513
3514 /* disable DPLL_SEL */
3515 temp = I915_READ(PCH_DPLL_SEL);
11887397 3516 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3517 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3518 }
e3421a18 3519
d925c59a 3520 /* disable PCH DPLL */
e72f9fbf 3521 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3522
d925c59a
DV		 3523 ironlake_fdi_pll_disable(intel_crtc);
3524 }
6b383a7f 3525
f7abfe8b 3526 intel_crtc->active = false;
6b383a7f 3527 intel_update_watermarks(dev);
d1ebd816
BW		 3528
3529 mutex_lock(&dev->struct_mutex);
6b383a7f 3530 intel_update_fbc(dev);
d1ebd816 3531 mutex_unlock(&dev->struct_mutex);
6be4a607 3532}
1b3c7a47 3533
4f771f10 3534static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3535{
4f771f10
PZ		 3536 struct drm_device *dev = crtc->dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3539 struct intel_encoder *encoder;
3540 int pipe = intel_crtc->pipe;
3541 int plane = intel_crtc->plane;
3b117c8f 3542 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3543
4f771f10
PZ		 3544 if (!intel_crtc->active)
3545 return;
3546
8807e55b
JN		 3547 for_each_encoder_on_crtc(dev, crtc, encoder) {
3548 intel_opregion_notify_encoder(encoder, false);
4f771f10 3549 encoder->disable(encoder);
8807e55b 3550 }
4f771f10
PZ		 3551
3552 intel_crtc_wait_for_pending_flips(crtc);
3553 drm_vblank_off(dev, pipe);
4f771f10 3554
891348b2 3555 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3556 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3557 intel_disable_fbc(dev);
3558
42db64ef
PZ		 3559 hsw_disable_ips(intel_crtc);
3560
0d5b8c61 3561 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3562 intel_disable_planes(crtc);
891348b2
RV		 3563 intel_disable_plane(dev_priv, plane, pipe);
3564
8664281b
PZ		 3565 if (intel_crtc->config.has_pch_encoder)
3566 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3567 intel_disable_pipe(dev_priv, pipe);
3568
ad80a810 3569 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3570
3f8dce3a 3571 ironlake_pfit_disable(intel_crtc);
4f771f10 3572
1f544388 3573 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3574
3575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 if (encoder->post_disable)
3577 encoder->post_disable(encoder);
3578
88adfff1 3579 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3580 lpt_disable_pch_transcoder(dev_priv);
8664281b 3581 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3582 intel_ddi_fdi_disable(crtc);
83616634 3583 }
4f771f10
PZ		 3584
3585 intel_crtc->active = false;
3586 intel_update_watermarks(dev);
3587
3588 mutex_lock(&dev->struct_mutex);
3589 intel_update_fbc(dev);
3590 mutex_unlock(&dev->struct_mutex);
3591}
3592
ee7b9f93
JB		 3593static void ironlake_crtc_off(struct drm_crtc *crtc)
3594{
3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3596 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3597}
3598
6441ab5f
PZ		 3599static void haswell_crtc_off(struct drm_crtc *crtc)
3600{
3601 intel_ddi_put_crtc_pll(crtc);
3602}
3603
02e792fb
DV		 3604static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3605{
02e792fb 3606 if (!enable && intel_crtc->overlay) {
23f09ce3 3607 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3608 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3609
23f09ce3 3610 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3611 dev_priv->mm.interruptible = false;
3612 (void) intel_overlay_switch_off(intel_crtc->overlay);
3613 dev_priv->mm.interruptible = true;
23f09ce3 3614 mutex_unlock(&dev->struct_mutex);
02e792fb 3615 }
02e792fb 3616
5dcdbcb0
CW		 3617 /* Let userspace switch the overlay on again. In most cases userspace
3618 * has to recompute where to put it anyway.
3619 */
02e792fb
DV		 3620}
3621
61bc95c1
EE		 3622/**
3623 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3624 * cursor plane briefly if not already running after enabling the display
3625 * plane.
3626 * This workaround avoids occasional blank screens when self refresh is
3627 * enabled.
3628 */
3629static void
3630g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3631{
3632 u32 cntl = I915_READ(CURCNTR(pipe));
3633
3634 if ((cntl & CURSOR_MODE) == 0) {
3635 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3636
3637 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3638 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3639 intel_wait_for_vblank(dev_priv->dev, pipe);
3640 I915_WRITE(CURCNTR(pipe), cntl);
3641 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3642 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3643 }
3644}
3645
2dd24552
JB		 3646static void i9xx_pfit_enable(struct intel_crtc *crtc)
3647{
3648 struct drm_device *dev = crtc->base.dev;
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650 struct intel_crtc_config *pipe_config = &crtc->config;
3651
328d8e82 3652 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3653 return;
3654
2dd24552 3655 /*
c0b03411
DV		 3656 * The panel fitter should only be adjusted whilst the pipe is disabled,
3657 * according to register description and PRM.
2dd24552 3658 */
c0b03411
DV		 3659 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3660 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3661
b074cec8
JB		 3662 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3663 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3664
3665 /* Border color in case we don't scale up to the full screen. Black by
3666 * default, change to something else for debugging. */
3667 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3668}
3669
89b667f8
JB		 3670static void valleyview_crtc_enable(struct drm_crtc *crtc)
3671{
3672 struct drm_device *dev = crtc->dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3675 struct intel_encoder *encoder;
3676 int pipe = intel_crtc->pipe;
3677 int plane = intel_crtc->plane;
23538ef1 3678 bool is_dsi;
89b667f8
JB		 3679
3680 WARN_ON(!crtc->enabled);
3681
3682 if (intel_crtc->active)
3683 return;
3684
3685 intel_crtc->active = true;
3686 intel_update_watermarks(dev);
3687
89b667f8
JB		 3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 if (encoder->pre_pll_enable)
3690 encoder->pre_pll_enable(encoder);
3691
23538ef1
JN		 3692 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3693
e9fd1c02
JN		 3694 if (!is_dsi)
3695 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3696
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 if (encoder->pre_enable)
3699 encoder->pre_enable(encoder);
3700
2dd24552
JB		 3701 i9xx_pfit_enable(intel_crtc);
3702
63cbb074
VS		 3703 intel_crtc_load_lut(crtc);
3704
23538ef1 3705 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3706 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3707 intel_enable_planes(crtc);
5c38d48c 3708 intel_crtc_update_cursor(crtc, true);
89b667f8 3709
89b667f8 3710 intel_update_fbc(dev);
5004945f
JN		 3711
3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 encoder->enable(encoder);
89b667f8
JB		 3714}
3715
0b8765c6 3716static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3717{
3718 struct drm_device *dev = crtc->dev;
79e53945
JB		 3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3721 struct intel_encoder *encoder;
79e53945 3722 int pipe = intel_crtc->pipe;
80824003 3723 int plane = intel_crtc->plane;
79e53945 3724
08a48469
DV		 3725 WARN_ON(!crtc->enabled);
3726
f7abfe8b
CW		 3727 if (intel_crtc->active)
3728 return;
3729
3730 intel_crtc->active = true;
6b383a7f
CW		 3731 intel_update_watermarks(dev);
3732
9d6d9f19
MK		 3733 for_each_encoder_on_crtc(dev, crtc, encoder)
3734 if (encoder->pre_enable)
3735 encoder->pre_enable(encoder);
3736
f6736a1a
DV		 3737 i9xx_enable_pll(intel_crtc);
3738
2dd24552
JB		 3739 i9xx_pfit_enable(intel_crtc);
3740
63cbb074
VS		 3741 intel_crtc_load_lut(crtc);
3742
23538ef1 3743 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3744 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3745 intel_enable_planes(crtc);
22e407d7 3746 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3747 if (IS_G4X(dev))
3748 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3749 intel_crtc_update_cursor(crtc, true);
79e53945 3750
0b8765c6
JB		 3751 /* Give the overlay scaler a chance to enable if it's on this pipe */
3752 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3753
f440eb13 3754 intel_update_fbc(dev);
ef9c3aee 3755
fa5c73b1
DV		 3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 encoder->enable(encoder);
0b8765c6 3758}
79e53945 3759
87476d63
DV		 3760static void i9xx_pfit_disable(struct intel_crtc *crtc)
3761{
3762 struct drm_device *dev = crtc->base.dev;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3764
328d8e82
DV		 3765 if (!crtc->config.gmch_pfit.control)
3766 return;
87476d63 3767
328d8e82 3768 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3769
328d8e82
DV		 3770 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3771 I915_READ(PFIT_CONTROL));
3772 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3773}
3774
0b8765c6
JB		 3775static void i9xx_crtc_disable(struct drm_crtc *crtc)
3776{
3777 struct drm_device *dev = crtc->dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3780 struct intel_encoder *encoder;
0b8765c6
JB		 3781 int pipe = intel_crtc->pipe;
3782 int plane = intel_crtc->plane;
ef9c3aee 3783
f7abfe8b
CW		 3784 if (!intel_crtc->active)
3785 return;
3786
ea9d758d
DV		 3787 for_each_encoder_on_crtc(dev, crtc, encoder)
3788 encoder->disable(encoder);
3789
0b8765c6 3790 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3791 intel_crtc_wait_for_pending_flips(crtc);
3792 drm_vblank_off(dev, pipe);
0b8765c6 3793
5c3fe8b0 3794 if (dev_priv->fbc.plane == plane)
973d04f9 3795 intel_disable_fbc(dev);
79e53945 3796
0d5b8c61
VS		 3797 intel_crtc_dpms_overlay(intel_crtc, false);
3798 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3799 intel_disable_planes(crtc);
b24e7179 3800 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3801
b24e7179 3802 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3803
87476d63 3804 i9xx_pfit_disable(intel_crtc);
24a1f16d 3805
89b667f8
JB		 3806 for_each_encoder_on_crtc(dev, crtc, encoder)
3807 if (encoder->post_disable)
3808 encoder->post_disable(encoder);
3809
e9fd1c02
JN		 3810 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3811 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3812
f7abfe8b 3813 intel_crtc->active = false;
6b383a7f
CW		 3814 intel_update_fbc(dev);
3815 intel_update_watermarks(dev);
0b8765c6
JB		 3816}
3817
ee7b9f93
JB		 3818static void i9xx_crtc_off(struct drm_crtc *crtc)
3819{
3820}
3821
976f8a20
DV		 3822static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3823 bool enabled)
2c07245f
ZW		 3824{
3825 struct drm_device *dev = crtc->dev;
3826 struct drm_i915_master_private *master_priv;
3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828 int pipe = intel_crtc->pipe;
79e53945
JB		 3829
3830 if (!dev->primary->master)
3831 return;
3832
3833 master_priv = dev->primary->master->driver_priv;
3834 if (!master_priv->sarea_priv)
3835 return;
3836
79e53945
JB		 3837 switch (pipe) {
3838 case 0:
3839 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3840 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3841 break;
3842 case 1:
3843 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3844 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3845 break;
3846 default:
9db4a9c7 3847 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3848 break;
3849 }
79e53945
JB		 3850}
3851
976f8a20
DV		 3852/**
3853 * Sets the power management mode of the pipe and plane.
3854 */
3855void intel_crtc_update_dpms(struct drm_crtc *crtc)
3856{
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 struct intel_encoder *intel_encoder;
3860 bool enable = false;
3861
3862 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3863 enable |= intel_encoder->connectors_active;
3864
3865 if (enable)
3866 dev_priv->display.crtc_enable(crtc);
3867 else
3868 dev_priv->display.crtc_disable(crtc);
3869
3870 intel_crtc_update_sarea(crtc, enable);
3871}
3872
cdd59983
CW		 3873static void intel_crtc_disable(struct drm_crtc *crtc)
3874{
cdd59983 3875 struct drm_device *dev = crtc->dev;
976f8a20 3876 struct drm_connector *connector;
ee7b9f93 3877 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3879
976f8a20
DV		 3880 /* crtc should still be enabled when we disable it. */
3881 WARN_ON(!crtc->enabled);
3882
3883 dev_priv->display.crtc_disable(crtc);
c77bf565 3884 intel_crtc->eld_vld = false;
976f8a20 3885 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3886 dev_priv->display.off(crtc);
3887
931872fc
CW		 3888 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3889 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3890
3891 if (crtc->fb) {
3892 mutex_lock(&dev->struct_mutex);
1690e1eb 3893 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3894 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3895 crtc->fb = NULL;
3896 }
3897
3898 /* Update computed state. */
3899 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3900 if (!connector->encoder || !connector->encoder->crtc)
3901 continue;
3902
3903 if (connector->encoder->crtc != crtc)
3904 continue;
3905
3906 connector->dpms = DRM_MODE_DPMS_OFF;
3907 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3908 }
3909}
3910
ea5b213a 3911void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3912{
4ef69c7a 3913 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3914
ea5b213a
CW		 3915 drm_encoder_cleanup(encoder);
3916 kfree(intel_encoder);
7e7d76c3
JB		 3917}
3918
9237329d 3919/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3920 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3921 * state of the entire output pipe. */
9237329d 3922static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3923{
5ab432ef
DV		 3924 if (mode == DRM_MODE_DPMS_ON) {
3925 encoder->connectors_active = true;
3926
b2cabb0e 3927 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3928 } else {
3929 encoder->connectors_active = false;
3930
b2cabb0e 3931 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3932 }
79e53945
JB		 3933}
3934
0a91ca29
DV		 3935/* Cross check the actual hw state with our own modeset state tracking (and it's
3936 * internal consistency). */
b980514c 3937static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3938{
0a91ca29
DV		 3939 if (connector->get_hw_state(connector)) {
3940 struct intel_encoder *encoder = connector->encoder;
3941 struct drm_crtc *crtc;
3942 bool encoder_enabled;
3943 enum pipe pipe;
3944
3945 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3946 connector->base.base.id,
3947 drm_get_connector_name(&connector->base));
3948
3949 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3950 "wrong connector dpms state\n");
3951 WARN(connector->base.encoder != &encoder->base,
3952 "active connector not linked to encoder\n");
3953 WARN(!encoder->connectors_active,
3954 "encoder->connectors_active not set\n");
3955
3956 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3957 WARN(!encoder_enabled, "encoder not enabled\n");
3958 if (WARN_ON(!encoder->base.crtc))
3959 return;
3960
3961 crtc = encoder->base.crtc;
3962
3963 WARN(!crtc->enabled, "crtc not enabled\n");
3964 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3965 WARN(pipe != to_intel_crtc(crtc)->pipe,
3966 "encoder active on the wrong pipe\n");
3967 }
79e53945
JB		 3968}
3969
5ab432ef
DV		 3970/* Even simpler default implementation, if there's really no special case to
3971 * consider. */
3972void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3973{
5ab432ef 3974 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3975
5ab432ef
DV		 3976 /* All the simple cases only support two dpms states. */
3977 if (mode != DRM_MODE_DPMS_ON)
3978 mode = DRM_MODE_DPMS_OFF;
d4270e57 3979
5ab432ef
DV		 3980 if (mode == connector->dpms)
3981 return;
3982
3983 connector->dpms = mode;
3984
3985 /* Only need to change hw state when actually enabled */
3986 if (encoder->base.crtc)
3987 intel_encoder_dpms(encoder, mode);
3988 else
8af6cf88 3989 WARN_ON(encoder->connectors_active != false);
0a91ca29 3990
b980514c 3991 intel_modeset_check_state(connector->dev);
79e53945
JB		 3992}
3993
f0947c37
DV		 3994/* Simple connector->get_hw_state implementation for encoders that support only
3995 * one connector and no cloning and hence the encoder state determines the state
3996 * of the connector. */
3997bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3998{
24929352 3999 enum pipe pipe = 0;
f0947c37 4000 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4001
f0947c37 4002 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4003}
4004
1857e1da
DV		 4005static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4006 struct intel_crtc_config *pipe_config)
4007{
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 struct intel_crtc *pipe_B_crtc =
4010 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4011
4012 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4013 pipe_name(pipe), pipe_config->fdi_lanes);
4014 if (pipe_config->fdi_lanes > 4) {
4015 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4016 pipe_name(pipe), pipe_config->fdi_lanes);
4017 return false;
4018 }
4019
4020 if (IS_HASWELL(dev)) {
4021 if (pipe_config->fdi_lanes > 2) {
4022 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4023 pipe_config->fdi_lanes);
4024 return false;
4025 } else {
4026 return true;
4027 }
4028 }
4029
4030 if (INTEL_INFO(dev)->num_pipes == 2)
4031 return true;
4032
4033 /* Ivybridge 3 pipe is really complicated */
4034 switch (pipe) {
4035 case PIPE_A:
4036 return true;
4037 case PIPE_B:
4038 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4039 pipe_config->fdi_lanes > 2) {
4040 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4041 pipe_name(pipe), pipe_config->fdi_lanes);
4042 return false;
4043 }
4044 return true;
4045 case PIPE_C:
1e833f40 4046 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4047 pipe_B_crtc->config.fdi_lanes <= 2) {
4048 if (pipe_config->fdi_lanes > 2) {
4049 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4050 pipe_name(pipe), pipe_config->fdi_lanes);
4051 return false;
4052 }
4053 } else {
4054 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4055 return false;
4056 }
4057 return true;
4058 default:
4059 BUG();
4060 }
4061}
4062
e29c22c0
DV		 4063#define RETRY 1
4064static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4065 struct intel_crtc_config *pipe_config)
877d48d5 4066{
1857e1da 4067 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4068 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4069 int lane, link_bw, fdi_dotclock;
e29c22c0 4070 bool setup_ok, needs_recompute = false;
877d48d5 4071
e29c22c0 4072retry:
877d48d5
DV		 4073 /* FDI is a binary signal running at ~2.7GHz, encoding
4074 * each output octet as 10 bits. The actual frequency
4075 * is stored as a divider into a 100MHz clock, and the
4076 * mode pixel clock is stored in units of 1KHz.
4077 * Hence the bw of each lane in terms of the mode signal
4078 * is:
4079 */
4080 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4081
ff9a6750 4082 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4083 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4084
2bd89a07 4085 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4086 pipe_config->pipe_bpp);
4087
4088 pipe_config->fdi_lanes = lane;
4089
2bd89a07 4090 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4091 link_bw, &pipe_config->fdi_m_n);
1857e1da 4092
e29c22c0
DV		 4093 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4094 intel_crtc->pipe, pipe_config);
4095 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4096 pipe_config->pipe_bpp -= 2*3;
4097 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4098 pipe_config->pipe_bpp);
4099 needs_recompute = true;
4100 pipe_config->bw_constrained = true;
4101
4102 goto retry;
4103 }
4104
4105 if (needs_recompute)
4106 return RETRY;
4107
4108 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4109}
4110
42db64ef
PZ		 4111static void hsw_compute_ips_config(struct intel_crtc *crtc,
4112 struct intel_crtc_config *pipe_config)
4113{
3c4ca58c
PZ		 4114 pipe_config->ips_enabled = i915_enable_ips &&
4115 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4116 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4117}
4118
a43f6e0f 4119static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4120 struct intel_crtc_config *pipe_config)
79e53945 4121{
a43f6e0f 4122 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4123 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4124
bad720ff 4125 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4126 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4127 if (pipe_config->requested_mode.clock * 3
4128 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4129 return -EINVAL;
2c07245f 4130 }
89749350 4131
8693a824
DL		 4132 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4133 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4134 */
4135 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4136 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4137 return -EINVAL;
44f46b42 4138
bd080ee5 4139 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4140 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4141 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4142 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4143 * for lvds. */
4144 pipe_config->pipe_bpp = 8*3;
4145 }
4146
f5adf94e 4147 if (HAS_IPS(dev))
a43f6e0f
DV		 4148 hsw_compute_ips_config(crtc, pipe_config);
4149
4150 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4151 * clock survives for now. */
4152 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4153 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4154
877d48d5 4155 if (pipe_config->has_pch_encoder)
a43f6e0f 4156 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4157
e29c22c0 4158 return 0;
79e53945
JB		 4159}
4160
25eb05fc
JB		 4161static int valleyview_get_display_clock_speed(struct drm_device *dev)
4162{
4163 return 400000; /* FIXME */
4164}
4165
e70236a8
JB		 4166static int i945_get_display_clock_speed(struct drm_device *dev)
4167{
4168 return 400000;
4169}
79e53945 4170
e70236a8 4171static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4172{
e70236a8
JB		 4173 return 333000;
4174}
79e53945 4175
e70236a8
JB		 4176static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4177{
4178 return 200000;
4179}
79e53945 4180
257a7ffc
DV		 4181static int pnv_get_display_clock_speed(struct drm_device *dev)
4182{
4183 u16 gcfgc = 0;
4184
4185 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4186
4187 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4188 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4189 return 267000;
4190 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4191 return 333000;
4192 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4193 return 444000;
4194 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4195 return 200000;
4196 default:
4197 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4198 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4199 return 133000;
4200 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4201 return 167000;
4202 }
4203}
4204
e70236a8
JB		 4205static int i915gm_get_display_clock_speed(struct drm_device *dev)
4206{
4207 u16 gcfgc = 0;
79e53945 4208
e70236a8
JB		 4209 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4210
4211 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4212 return 133000;
4213 else {
4214 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4215 case GC_DISPLAY_CLOCK_333_MHZ:
4216 return 333000;
4217 default:
4218 case GC_DISPLAY_CLOCK_190_200_MHZ:
4219 return 190000;
79e53945 4220 }
e70236a8
JB		 4221 }
4222}
4223
4224static int i865_get_display_clock_speed(struct drm_device *dev)
4225{
4226 return 266000;
4227}
4228
4229static int i855_get_display_clock_speed(struct drm_device *dev)
4230{
4231 u16 hpllcc = 0;
4232 /* Assume that the hardware is in the high speed state. This
4233 * should be the default.
4234 */
4235 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4236 case GC_CLOCK_133_200:
4237 case GC_CLOCK_100_200:
4238 return 200000;
4239 case GC_CLOCK_166_250:
4240 return 250000;
4241 case GC_CLOCK_100_133:
79e53945 4242 return 133000;
e70236a8 4243 }
79e53945 4244
e70236a8
JB		 4245 /* Shouldn't happen */
4246 return 0;
4247}
79e53945 4248
e70236a8
JB		 4249static int i830_get_display_clock_speed(struct drm_device *dev)
4250{
4251 return 133000;
79e53945
JB		 4252}
4253
2c07245f 4254static void
a65851af 4255intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4256{
a65851af
VS		 4257 while (*num > DATA_LINK_M_N_MASK ||
4258 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4259 *num >>= 1;
4260 *den >>= 1;
4261 }
4262}
4263
a65851af
VS		 4264static void compute_m_n(unsigned int m, unsigned int n,
4265 uint32_t *ret_m, uint32_t *ret_n)
4266{
4267 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4268 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4269 intel_reduce_m_n_ratio(ret_m, ret_n);
4270}
4271
e69d0bc1
DV		 4272void
4273intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4274 int pixel_clock, int link_clock,
4275 struct intel_link_m_n *m_n)
2c07245f 4276{
e69d0bc1 4277 m_n->tu = 64;
a65851af
VS		 4278
4279 compute_m_n(bits_per_pixel * pixel_clock,
4280 link_clock * nlanes * 8,
4281 &m_n->gmch_m, &m_n->gmch_n);
4282
4283 compute_m_n(pixel_clock, link_clock,
4284 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4285}
4286
a7615030
CW		 4287static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4288{
72bbe58c
KP		 4289 if (i915_panel_use_ssc >= 0)
4290 return i915_panel_use_ssc != 0;
41aa3448 4291 return dev_priv->vbt.lvds_use_ssc
435793df 4292 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4293}
4294
a0c4da24
JB		 4295static int vlv_get_refclk(struct drm_crtc *crtc)
4296{
4297 struct drm_device *dev = crtc->dev;
4298 struct drm_i915_private *dev_priv = dev->dev_private;
4299 int refclk = 27000; /* for DP & HDMI */
4300
4301 return 100000; /* only one validated so far */
4302
4303 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4304 refclk = 96000;
4305 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4306 if (intel_panel_use_ssc(dev_priv))
4307 refclk = 100000;
4308 else
4309 refclk = 96000;
4310 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4311 refclk = 100000;
4312 }
4313
4314 return refclk;
4315}
4316
c65d77d8
JB		 4317static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4318{
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 int refclk;
4322
a0c4da24
JB		 4323 if (IS_VALLEYVIEW(dev)) {
4324 refclk = vlv_get_refclk(crtc);
4325 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4326 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4327 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4328 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4329 refclk / 1000);
4330 } else if (!IS_GEN2(dev)) {
4331 refclk = 96000;
4332 } else {
4333 refclk = 48000;
4334 }
4335
4336 return refclk;
4337}
4338
7429e9d4 4339static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4340{
7df00d7a 4341 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4342}
f47709a9 4343
7429e9d4
DV		 4344static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4345{
4346 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4347}
4348
f47709a9 4349static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4350 intel_clock_t *reduced_clock)
4351{
f47709a9 4352 struct drm_device *dev = crtc->base.dev;
a7516a05 4353 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4354 int pipe = crtc->pipe;
a7516a05
JB		 4355 u32 fp, fp2 = 0;
4356
4357 if (IS_PINEVIEW(dev)) {
7429e9d4 4358 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4359 if (reduced_clock)
7429e9d4 4360 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4361 } else {
7429e9d4 4362 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4363 if (reduced_clock)
7429e9d4 4364 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4365 }
4366
4367 I915_WRITE(FP0(pipe), fp);
8bcc2795 4368 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4369
f47709a9
DV		 4370 crtc->lowfreq_avail = false;
4371 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4372 reduced_clock && i915_powersave) {
4373 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4374 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4375 crtc->lowfreq_avail = true;
a7516a05
JB		 4376 } else {
4377 I915_WRITE(FP1(pipe), fp);
8bcc2795 4378 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4379 }
4380}
4381
89b667f8
JB		 4382static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4383{
4384 u32 reg_val;
4385
4386 /*
4387 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4388 * and set it to a reasonable value instead.
4389 */
ae99258f 4390 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4391 reg_val &= 0xffffff00;
4392 reg_val |= 0x00000030;
ae99258f 4393 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4394
ae99258f 4395 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4396 reg_val &= 0x8cffffff;
4397 reg_val = 0x8c000000;
ae99258f 4398 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4399
ae99258f 4400 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4401 reg_val &= 0xffffff00;
ae99258f 4402 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4403
ae99258f 4404 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4405 reg_val &= 0x00ffffff;
4406 reg_val |= 0xb0000000;
ae99258f 4407 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4408}
4409
b551842d
DV		 4410static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4411 struct intel_link_m_n *m_n)
4412{
4413 struct drm_device *dev = crtc->base.dev;
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415 int pipe = crtc->pipe;
4416
e3b95f1e
DV		 4417 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4418 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4419 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4420 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4421}
4422
4423static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4424 struct intel_link_m_n *m_n)
4425{
4426 struct drm_device *dev = crtc->base.dev;
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4428 int pipe = crtc->pipe;
4429 enum transcoder transcoder = crtc->config.cpu_transcoder;
4430
4431 if (INTEL_INFO(dev)->gen >= 5) {
4432 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4433 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4434 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4435 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4436 } else {
e3b95f1e
DV		 4437 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4438 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4439 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4440 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4441 }
4442}
4443
03afc4a2
DV		 4444static void intel_dp_set_m_n(struct intel_crtc *crtc)
4445{
4446 if (crtc->config.has_pch_encoder)
4447 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4448 else
4449 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4450}
4451
f47709a9 4452static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4453{
f47709a9 4454 struct drm_device *dev = crtc->base.dev;
a0c4da24 4455 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4456 int pipe = crtc->pipe;
89b667f8 4457 u32 dpll, mdiv;
a0c4da24 4458 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4459 u32 coreclk, reg_val, dpll_md;
a0c4da24 4460
09153000
DV		 4461 mutex_lock(&dev_priv->dpio_lock);
4462
f47709a9
DV		 4463 bestn = crtc->config.dpll.n;
4464 bestm1 = crtc->config.dpll.m1;
4465 bestm2 = crtc->config.dpll.m2;
4466 bestp1 = crtc->config.dpll.p1;
4467 bestp2 = crtc->config.dpll.p2;
a0c4da24 4468
89b667f8
JB		 4469 /* See eDP HDMI DPIO driver vbios notes doc */
4470
4471 /* PLL B needs special handling */
4472 if (pipe)
4473 vlv_pllb_recal_opamp(dev_priv);
4474
4475 /* Set up Tx target for periodic Rcomp update */
ae99258f 4476 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4477
4478 /* Disable target IRef on PLL */
ae99258f 4479 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4480 reg_val &= 0x00ffffff;
ae99258f 4481 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4482
4483 /* Disable fast lock */
ae99258f 4484 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4485
4486 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4487 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4488 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4489 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4490 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4491
4492 /*
4493 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4494 * but we don't support that).
4495 * Note: don't use the DAC post divider as it seems unstable.
4496 */
4497 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4498 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4499
a0c4da24 4500 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4501 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4502
89b667f8 4503 /* Set HBR and RBR LPF coefficients */
ff9a6750 4504 if (crtc->config.port_clock == 162000 ||
99750bd4 4505 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4506 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4507 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4508 0x009f0003);
89b667f8 4509 else
4abb2c39 4510 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4511 0x00d0000f);
4512
4513 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4514 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4515 /* Use SSC source */
4516 if (!pipe)
ae99258f 4517 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4518 0x0df40000);
4519 else
ae99258f 4520 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4521 0x0df70000);
4522 } else { /* HDMI or VGA */
4523 /* Use bend source */
4524 if (!pipe)
ae99258f 4525 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4526 0x0df70000);
4527 else
ae99258f 4528 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4529 0x0df40000);
4530 }
a0c4da24 4531
ae99258f 4532 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4533 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4534 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4535 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4536 coreclk |= 0x01000000;
ae99258f 4537 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4538
ae99258f 4539 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4540
89b667f8
JB		 4541 /* Enable DPIO clock input */
4542 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4543 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4544 if (pipe)
4545 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4546
4547 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4548 crtc->config.dpll_hw_state.dpll = dpll;
4549
ef1b460d
DV		 4550 dpll_md = (crtc->config.pixel_multiplier - 1)
4551 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4552 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4553
89b667f8
JB		 4554 if (crtc->config.has_dp_encoder)
4555 intel_dp_set_m_n(crtc);
09153000
DV		 4556
4557 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4558}
4559
f47709a9
DV		 4560static void i9xx_update_pll(struct intel_crtc *crtc,
4561 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4562 int num_connectors)
4563{
f47709a9 4564 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4565 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4566 u32 dpll;
4567 bool is_sdvo;
f47709a9 4568 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4569
f47709a9 4570 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4571
f47709a9
DV		 4572 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4573 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4574
4575 dpll = DPLL_VGA_MODE_DIS;
4576
f47709a9 4577 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4578 dpll |= DPLLB_MODE_LVDS;
4579 else
4580 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4581
ef1b460d 4582 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4583 dpll |= (crtc->config.pixel_multiplier - 1)
4584 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4585 }
198a037f
DV		 4586
4587 if (is_sdvo)
4a33e48d 4588 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4589
f47709a9 4590 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4591 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4592
4593 /* compute bitmask from p1 value */
4594 if (IS_PINEVIEW(dev))
4595 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4596 else {
4597 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4598 if (IS_G4X(dev) && reduced_clock)
4599 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4600 }
4601 switch (clock->p2) {
4602 case 5:
4603 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4604 break;
4605 case 7:
4606 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4607 break;
4608 case 10:
4609 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4610 break;
4611 case 14:
4612 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4613 break;
4614 }
4615 if (INTEL_INFO(dev)->gen >= 4)
4616 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4617
09ede541 4618 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4619 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4620 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4621 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4622 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4623 else
4624 dpll |= PLL_REF_INPUT_DREFCLK;
4625
4626 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4627 crtc->config.dpll_hw_state.dpll = dpll;
4628
eb1cbe48 4629 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4630 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4631 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4632 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4633 }
66e3d5c0
DV		 4634
4635 if (crtc->config.has_dp_encoder)
4636 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4637}
4638
f47709a9 4639static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4640 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4641 int num_connectors)
4642{
f47709a9 4643 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4644 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4645 u32 dpll;
f47709a9 4646 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4647
f47709a9 4648 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4649
eb1cbe48
DV		 4650 dpll = DPLL_VGA_MODE_DIS;
4651
f47709a9 4652 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4653 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4654 } else {
4655 if (clock->p1 == 2)
4656 dpll |= PLL_P1_DIVIDE_BY_TWO;
4657 else
4658 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4659 if (clock->p2 == 4)
4660 dpll |= PLL_P2_DIVIDE_BY_4;
4661 }
4662
4a33e48d
DV		 4663 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4664 dpll |= DPLL_DVO_2X_MODE;
4665
f47709a9 4666 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4667 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4668 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4669 else
4670 dpll |= PLL_REF_INPUT_DREFCLK;
4671
4672 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4673 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4674}
4675
8a654f3b 4676static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4677{
4678 struct drm_device *dev = intel_crtc->base.dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4681 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4682 struct drm_display_mode *adjusted_mode =
4683 &intel_crtc->config.adjusted_mode;
4684 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4685 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4686
4687 /* We need to be careful not to changed the adjusted mode, for otherwise
4688 * the hw state checker will get angry at the mismatch. */
4689 crtc_vtotal = adjusted_mode->crtc_vtotal;
4690 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4691
4692 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4693 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4694 crtc_vtotal -= 1;
4695 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4696 vsyncshift = adjusted_mode->crtc_hsync_start
4697 - adjusted_mode->crtc_htotal / 2;
4698 } else {
4699 vsyncshift = 0;
4700 }
4701
4702 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4703 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4704
fe2b8f9d 4705 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4706 (adjusted_mode->crtc_hdisplay - 1) |
4707 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4708 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4709 (adjusted_mode->crtc_hblank_start - 1) |
4710 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4711 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4712 (adjusted_mode->crtc_hsync_start - 1) |
4713 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4714
fe2b8f9d 4715 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4716 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4717 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4718 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4719 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4720 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4721 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4722 (adjusted_mode->crtc_vsync_start - 1) |
4723 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4724
b5e508d4
PZ		 4725 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4726 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4727 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4728 * bits. */
4729 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4730 (pipe == PIPE_B || pipe == PIPE_C))
4731 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4732
b0e77b9c
PZ		 4733 /* pipesrc controls the size that is scaled from, which should
4734 * always be the user's requested size.
4735 */
4736 I915_WRITE(PIPESRC(pipe),
4737 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4738}
4739
1bd1bd80
DV		 4740static void intel_get_pipe_timings(struct intel_crtc *crtc,
4741 struct intel_crtc_config *pipe_config)
4742{
4743 struct drm_device *dev = crtc->base.dev;
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4746 uint32_t tmp;
4747
4748 tmp = I915_READ(HTOTAL(cpu_transcoder));
4749 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4750 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4751 tmp = I915_READ(HBLANK(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4754 tmp = I915_READ(HSYNC(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4757
4758 tmp = I915_READ(VTOTAL(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(VBLANK(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4764 tmp = I915_READ(VSYNC(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4767
4768 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4769 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4770 pipe_config->adjusted_mode.crtc_vtotal += 1;
4771 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4772 }
4773
4774 tmp = I915_READ(PIPESRC(crtc->pipe));
4775 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4776 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4777}
4778
babea61d
JB		 4779static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4780 struct intel_crtc_config *pipe_config)
4781{
4782 struct drm_crtc *crtc = &intel_crtc->base;
4783
4784 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4785 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4786 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4787 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4788
4789 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4790 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4791 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4792 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4793
4794 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4795
4796 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4797 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4798}
4799
84b046f3
DV		 4800static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4801{
4802 struct drm_device *dev = intel_crtc->base.dev;
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4804 uint32_t pipeconf;
4805
9f11a9e4 4806 pipeconf = 0;
84b046f3
DV		 4807
4808 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4809 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4810 * core speed.
4811 *
4812 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4813 * pipe == 0 check?
4814 */
4815 if (intel_crtc->config.requested_mode.clock >
4816 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4817 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4818 }
4819
ff9ce46e
DV		 4820 /* only g4x and later have fancy bpc/dither controls */
4821 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4822 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4823 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4824 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4825 PIPECONF_DITHER_TYPE_SP;
84b046f3 4826
ff9ce46e
DV		 4827 switch (intel_crtc->config.pipe_bpp) {
4828 case 18:
4829 pipeconf |= PIPECONF_6BPC;
4830 break;
4831 case 24:
4832 pipeconf |= PIPECONF_8BPC;
4833 break;
4834 case 30:
4835 pipeconf |= PIPECONF_10BPC;
4836 break;
4837 default:
4838 /* Case prevented by intel_choose_pipe_bpp_dither. */
4839 BUG();
84b046f3
DV		 4840 }
4841 }
4842
4843 if (HAS_PIPE_CXSR(dev)) {
4844 if (intel_crtc->lowfreq_avail) {
4845 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4846 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4847 } else {
4848 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4849 }
4850 }
4851
84b046f3
DV		 4852 if (!IS_GEN2(dev) &&
4853 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4854 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4855 else
4856 pipeconf |= PIPECONF_PROGRESSIVE;
4857
9f11a9e4
DV		 4858 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4859 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4860
84b046f3
DV		 4861 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4862 POSTING_READ(PIPECONF(intel_crtc->pipe));
4863}
4864
f564048e 4865static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4866 int x, int y,
94352cf9 4867 struct drm_framebuffer *fb)
79e53945
JB		 4868{
4869 struct drm_device *dev = crtc->dev;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4872 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4873 int pipe = intel_crtc->pipe;
80824003 4874 int plane = intel_crtc->plane;
c751ce4f 4875 int refclk, num_connectors = 0;
652c393a 4876 intel_clock_t clock, reduced_clock;
84b046f3 4877 u32 dspcntr;
a16af721 4878 bool ok, has_reduced_clock = false;
e9fd1c02 4879 bool is_lvds = false, is_dsi = false;
5eddb70b 4880 struct intel_encoder *encoder;
d4906093 4881 const intel_limit_t *limit;
5c3b82e2 4882 int ret;
79e53945 4883
6c2b7c12 4884 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4885 switch (encoder->type) {
79e53945
JB		 4886 case INTEL_OUTPUT_LVDS:
4887 is_lvds = true;
4888 break;
e9fd1c02
JN		 4889 case INTEL_OUTPUT_DSI:
4890 is_dsi = true;
4891 break;
79e53945 4892 }
43565a06 4893
c751ce4f 4894 num_connectors++;
79e53945
JB		 4895 }
4896
c65d77d8 4897 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4898
e9fd1c02
JN		 4899 if (!is_dsi) {
4900 /*
4901 * Returns a set of divisors for the desired target clock with
4902 * the given refclk, or FALSE. The returned values represent
4903 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4904 * 2) / p1 / p2.
4905 */
4906 limit = intel_limit(crtc, refclk);
4907 ok = dev_priv->display.find_dpll(limit, crtc,
4908 intel_crtc->config.port_clock,
4909 refclk, NULL, &clock);
4910 if (!ok && !intel_crtc->config.clock_set) {
4911 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4912 return -EINVAL;
4913 }
79e53945
JB		 4914 }
4915
cda4b7d3 4916 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4917 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4918
e9fd1c02 4919 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4920 /*
4921 * Ensure we match the reduced clock's P to the target clock.
4922 * If the clocks don't match, we can't switch the display clock
4923 * by using the FP0/FP1. In such case we will disable the LVDS
4924 * downclock feature.
4925 */
ee9300bb
DV		 4926 has_reduced_clock =
4927 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4928 dev_priv->lvds_downclock,
ee9300bb 4929 refclk, &clock,
5eddb70b 4930 &reduced_clock);
7026d4ac 4931 }
f47709a9
DV		 4932 /* Compat-code for transition, will disappear. */
4933 if (!intel_crtc->config.clock_set) {
4934 intel_crtc->config.dpll.n = clock.n;
4935 intel_crtc->config.dpll.m1 = clock.m1;
4936 intel_crtc->config.dpll.m2 = clock.m2;
4937 intel_crtc->config.dpll.p1 = clock.p1;
4938 intel_crtc->config.dpll.p2 = clock.p2;
4939 }
7026d4ac 4940
e9fd1c02 4941 if (IS_GEN2(dev)) {
8a654f3b 4942 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4943 has_reduced_clock ? &reduced_clock : NULL,
4944 num_connectors);
e9fd1c02
JN		 4945 } else if (IS_VALLEYVIEW(dev)) {
4946 if (!is_dsi)
4947 vlv_update_pll(intel_crtc);
4948 } else {
f47709a9 4949 i9xx_update_pll(intel_crtc,
eb1cbe48 4950 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4951 num_connectors);
e9fd1c02 4952 }
79e53945 4953
79e53945
JB		 4954 /* Set up the display plane register */
4955 dspcntr = DISPPLANE_GAMMA_ENABLE;
4956
da6ecc5d
JB		 4957 if (!IS_VALLEYVIEW(dev)) {
4958 if (pipe == 0)
4959 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4960 else
4961 dspcntr |= DISPPLANE_SEL_PIPE_B;
4962 }
79e53945 4963
8a654f3b 4964 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4965
4966 /* pipesrc and dspsize control the size that is scaled from,
4967 * which should always be the user's requested size.
79e53945 4968 */
929c77fb
EA		 4969 I915_WRITE(DSPSIZE(plane),
4970 ((mode->vdisplay - 1) << 16) |
4971 (mode->hdisplay - 1));
4972 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4973
84b046f3
DV		 4974 i9xx_set_pipeconf(intel_crtc);
4975
f564048e
EA		 4976 I915_WRITE(DSPCNTR(plane), dspcntr);
4977 POSTING_READ(DSPCNTR(plane));
4978
94352cf9 4979 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4980
4981 intel_update_watermarks(dev);
4982
f564048e
EA		 4983 return ret;
4984}
4985
2fa2fe9a
DV		 4986static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4987 struct intel_crtc_config *pipe_config)
4988{
4989 struct drm_device *dev = crtc->base.dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 uint32_t tmp;
4992
4993 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4994 if (!(tmp & PFIT_ENABLE))
4995 return;
2fa2fe9a 4996
06922821 4997 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4998 if (INTEL_INFO(dev)->gen < 4) {
4999 if (crtc->pipe != PIPE_B)
5000 return;
2fa2fe9a
DV		 5001 } else {
5002 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5003 return;
5004 }
5005
06922821 5006 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5007 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5008 if (INTEL_INFO(dev)->gen < 5)
5009 pipe_config->gmch_pfit.lvds_border_bits =
5010 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5011}
5012
0e8ffe1b
DV		 5013static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5014 struct intel_crtc_config *pipe_config)
5015{
5016 struct drm_device *dev = crtc->base.dev;
5017 struct drm_i915_private *dev_priv = dev->dev_private;
5018 uint32_t tmp;
5019
e143a21c 5020 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5021 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5022
0e8ffe1b
DV		 5023 tmp = I915_READ(PIPECONF(crtc->pipe));
5024 if (!(tmp & PIPECONF_ENABLE))
5025 return false;
5026
1bd1bd80
DV		 5027 intel_get_pipe_timings(crtc, pipe_config);
5028
2fa2fe9a
DV		 5029 i9xx_get_pfit_config(crtc, pipe_config);
5030
6c49f241
DV		 5031 if (INTEL_INFO(dev)->gen >= 4) {
5032 tmp = I915_READ(DPLL_MD(crtc->pipe));
5033 pipe_config->pixel_multiplier =
5034 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5035 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5036 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5037 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5038 tmp = I915_READ(DPLL(crtc->pipe));
5039 pipe_config->pixel_multiplier =
5040 ((tmp & SDVO_MULTIPLIER_MASK)
5041 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5042 } else {
5043 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5044 * port and will be fixed up in the encoder->get_config
5045 * function. */
5046 pipe_config->pixel_multiplier = 1;
5047 }
8bcc2795
DV		 5048 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5049 if (!IS_VALLEYVIEW(dev)) {
5050 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5051 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5052 } else {
5053 /* Mask out read-only status bits. */
5054 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5055 DPLL_PORTC_READY_MASK |
5056 DPLL_PORTB_READY_MASK);
8bcc2795 5057 }
6c49f241 5058
0e8ffe1b
DV		 5059 return true;
5060}
5061
dde86e2d 5062static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5063{
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5066 struct intel_encoder *encoder;
74cfd7ac 5067 u32 val, final;
13d83a67 5068 bool has_lvds = false;
199e5d79 5069 bool has_cpu_edp = false;
199e5d79 5070 bool has_panel = false;
99eb6a01
KP		 5071 bool has_ck505 = false;
5072 bool can_ssc = false;
13d83a67
JB		 5073
5074 /* We need to take the global config into account */
199e5d79
KP		 5075 list_for_each_entry(encoder, &mode_config->encoder_list,
5076 base.head) {
5077 switch (encoder->type) {
5078 case INTEL_OUTPUT_LVDS:
5079 has_panel = true;
5080 has_lvds = true;
5081 break;
5082 case INTEL_OUTPUT_EDP:
5083 has_panel = true;
2de6905f 5084 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5085 has_cpu_edp = true;
5086 break;
13d83a67
JB		 5087 }
5088 }
5089
99eb6a01 5090 if (HAS_PCH_IBX(dev)) {
41aa3448 5091 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5092 can_ssc = has_ck505;
5093 } else {
5094 has_ck505 = false;
5095 can_ssc = true;
5096 }
5097
2de6905f
ID		 5098 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5099 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5100
5101 /* Ironlake: try to setup display ref clock before DPLL
5102 * enabling. This is only under driver's control after
5103 * PCH B stepping, previous chipset stepping should be
5104 * ignoring this setting.
5105 */
74cfd7ac
CW		 5106 val = I915_READ(PCH_DREF_CONTROL);
5107
5108 /* As we must carefully and slowly disable/enable each source in turn,
5109 * compute the final state we want first and check if we need to
5110 * make any changes at all.
5111 */
5112 final = val;
5113 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5114 if (has_ck505)
5115 final |= DREF_NONSPREAD_CK505_ENABLE;
5116 else
5117 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5118
5119 final &= ~DREF_SSC_SOURCE_MASK;
5120 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5121 final &= ~DREF_SSC1_ENABLE;
5122
5123 if (has_panel) {
5124 final |= DREF_SSC_SOURCE_ENABLE;
5125
5126 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5127 final |= DREF_SSC1_ENABLE;
5128
5129 if (has_cpu_edp) {
5130 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5131 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5132 else
5133 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5134 } else
5135 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5136 } else {
5137 final |= DREF_SSC_SOURCE_DISABLE;
5138 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5139 }
5140
5141 if (final == val)
5142 return;
5143
13d83a67 5144 /* Always enable nonspread source */
74cfd7ac 5145 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5146
99eb6a01 5147 if (has_ck505)
74cfd7ac 5148 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5149 else
74cfd7ac 5150 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5151
199e5d79 5152 if (has_panel) {
74cfd7ac
CW		 5153 val &= ~DREF_SSC_SOURCE_MASK;
5154 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5155
199e5d79 5156 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5157 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5158 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5159 val |= DREF_SSC1_ENABLE;
e77166b5 5160 } else
74cfd7ac 5161 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5162
5163 /* Get SSC going before enabling the outputs */
74cfd7ac 5164 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5165 POSTING_READ(PCH_DREF_CONTROL);
5166 udelay(200);
5167
74cfd7ac 5168 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5169
5170 /* Enable CPU source on CPU attached eDP */
199e5d79 5171 if (has_cpu_edp) {
99eb6a01 5172 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5173 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5174 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5175 }
13d83a67 5176 else
74cfd7ac 5177 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5178 } else
74cfd7ac 5179 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5180
74cfd7ac 5181 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5182 POSTING_READ(PCH_DREF_CONTROL);
5183 udelay(200);
5184 } else {
5185 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5186
74cfd7ac 5187 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5188
5189 /* Turn off CPU output */
74cfd7ac 5190 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5191
74cfd7ac 5192 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5193 POSTING_READ(PCH_DREF_CONTROL);
5194 udelay(200);
5195
5196 /* Turn off the SSC source */
74cfd7ac
CW		 5197 val &= ~DREF_SSC_SOURCE_MASK;
5198 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5199
5200 /* Turn off SSC1 */
74cfd7ac 5201 val &= ~DREF_SSC1_ENABLE;
199e5d79 5202
74cfd7ac 5203 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5204 POSTING_READ(PCH_DREF_CONTROL);
5205 udelay(200);
5206 }
74cfd7ac
CW		 5207
5208 BUG_ON(val != final);
13d83a67
JB		 5209}
5210
f31f2d55 5211static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5212{
f31f2d55 5213 uint32_t tmp;
dde86e2d 5214
0ff066a9
PZ		 5215 tmp = I915_READ(SOUTH_CHICKEN2);
5216 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5217 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5218
0ff066a9
PZ		 5219 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5220 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5221 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5222
0ff066a9
PZ		 5223 tmp = I915_READ(SOUTH_CHICKEN2);
5224 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5225 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5226
0ff066a9
PZ		 5227 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5228 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5229 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5230}
5231
5232/* WaMPhyProgramming:hsw */
5233static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5234{
5235 uint32_t tmp;
dde86e2d
PZ		 5236
5237 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5238 tmp &= ~(0xFF << 24);
5239 tmp |= (0x12 << 24);
5240 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5241
dde86e2d
PZ		 5242 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5243 tmp |= (1 << 11);
5244 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5245
5246 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5247 tmp |= (1 << 11);
5248 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5249
dde86e2d
PZ		 5250 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5251 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5252 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5255 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5256 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5257
0ff066a9
PZ		 5258 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5259 tmp &= ~(7 << 13);
5260 tmp |= (5 << 13);
5261 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5262
0ff066a9
PZ		 5263 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5264 tmp &= ~(7 << 13);
5265 tmp |= (5 << 13);
5266 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5267
5268 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5269 tmp &= ~0xFF;
5270 tmp |= 0x1C;
5271 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5274 tmp &= ~0xFF;
5275 tmp |= 0x1C;
5276 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5279 tmp &= ~(0xFF << 16);
5280 tmp |= (0x1C << 16);
5281 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5282
5283 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5284 tmp &= ~(0xFF << 16);
5285 tmp |= (0x1C << 16);
5286 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5287
0ff066a9
PZ		 5288 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5289 tmp |= (1 << 27);
5290 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5291
0ff066a9
PZ		 5292 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5293 tmp |= (1 << 27);
5294 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5295
0ff066a9
PZ		 5296 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5297 tmp &= ~(0xF << 28);
5298 tmp |= (4 << 28);
5299 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5300
0ff066a9
PZ		 5301 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5302 tmp &= ~(0xF << 28);
5303 tmp |= (4 << 28);
5304 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5305}
5306
2fa86a1f
PZ		 5307/* Implements 3 different sequences from BSpec chapter "Display iCLK
5308 * Programming" based on the parameters passed:
5309 * - Sequence to enable CLKOUT_DP
5310 * - Sequence to enable CLKOUT_DP without spread
5311 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5312 */
5313static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5314 bool with_fdi)
f31f2d55
PZ		 5315{
5316 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5317 uint32_t reg, tmp;
5318
5319 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5320 with_spread = true;
5321 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5322 with_fdi, "LP PCH doesn't have FDI\n"))
5323 with_fdi = false;
f31f2d55
PZ		 5324
5325 mutex_lock(&dev_priv->dpio_lock);
5326
5327 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5328 tmp &= ~SBI_SSCCTL_DISABLE;
5329 tmp |= SBI_SSCCTL_PATHALT;
5330 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5331
5332 udelay(24);
5333
2fa86a1f
PZ		 5334 if (with_spread) {
5335 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5336 tmp &= ~SBI_SSCCTL_PATHALT;
5337 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5338
2fa86a1f
PZ		 5339 if (with_fdi) {
5340 lpt_reset_fdi_mphy(dev_priv);
5341 lpt_program_fdi_mphy(dev_priv);
5342 }
5343 }
dde86e2d 5344
2fa86a1f
PZ		 5345 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5346 SBI_GEN0 : SBI_DBUFF0;
5347 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5348 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5349 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5350
5351 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5352}
5353
47701c3b
PZ		 5354/* Sequence to disable CLKOUT_DP */
5355static void lpt_disable_clkout_dp(struct drm_device *dev)
5356{
5357 struct drm_i915_private *dev_priv = dev->dev_private;
5358 uint32_t reg, tmp;
5359
5360 mutex_lock(&dev_priv->dpio_lock);
5361
5362 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5363 SBI_GEN0 : SBI_DBUFF0;
5364 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5365 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5366 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5367
5368 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5369 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5370 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5371 tmp |= SBI_SSCCTL_PATHALT;
5372 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5373 udelay(32);
5374 }
5375 tmp |= SBI_SSCCTL_DISABLE;
5376 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5377 }
5378
5379 mutex_unlock(&dev_priv->dpio_lock);
5380}
5381
bf8fa3d3
PZ		 5382static void lpt_init_pch_refclk(struct drm_device *dev)
5383{
5384 struct drm_mode_config *mode_config = &dev->mode_config;
5385 struct intel_encoder *encoder;
5386 bool has_vga = false;
5387
5388 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5389 switch (encoder->type) {
5390 case INTEL_OUTPUT_ANALOG:
5391 has_vga = true;
5392 break;
5393 }
5394 }
5395
47701c3b
PZ		 5396 if (has_vga)
5397 lpt_enable_clkout_dp(dev, true, true);
5398 else
5399 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5400}
5401
dde86e2d
PZ		 5402/*
5403 * Initialize reference clocks when the driver loads
5404 */
5405void intel_init_pch_refclk(struct drm_device *dev)
5406{
5407 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5408 ironlake_init_pch_refclk(dev);
5409 else if (HAS_PCH_LPT(dev))
5410 lpt_init_pch_refclk(dev);
5411}
5412
d9d444cb
JB		 5413static int ironlake_get_refclk(struct drm_crtc *crtc)
5414{
5415 struct drm_device *dev = crtc->dev;
5416 struct drm_i915_private *dev_priv = dev->dev_private;
5417 struct intel_encoder *encoder;
d9d444cb
JB		 5418 int num_connectors = 0;
5419 bool is_lvds = false;
5420
6c2b7c12 5421 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5422 switch (encoder->type) {
5423 case INTEL_OUTPUT_LVDS:
5424 is_lvds = true;
5425 break;
d9d444cb
JB		 5426 }
5427 num_connectors++;
5428 }
5429
5430 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5431 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5432 dev_priv->vbt.lvds_ssc_freq);
5433 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5434 }
5435
5436 return 120000;
5437}
5438
6ff93609 5439static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5440{
c8203565 5441 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5443 int pipe = intel_crtc->pipe;
c8203565
PZ		 5444 uint32_t val;
5445
78114071 5446 val = 0;
c8203565 5447
965e0c48 5448 switch (intel_crtc->config.pipe_bpp) {
c8203565 5449 case 18:
dfd07d72 5450 val |= PIPECONF_6BPC;
c8203565
PZ		 5451 break;
5452 case 24:
dfd07d72 5453 val |= PIPECONF_8BPC;
c8203565
PZ		 5454 break;
5455 case 30:
dfd07d72 5456 val |= PIPECONF_10BPC;
c8203565
PZ		 5457 break;
5458 case 36:
dfd07d72 5459 val |= PIPECONF_12BPC;
c8203565
PZ		 5460 break;
5461 default:
cc769b62
PZ		 5462 /* Case prevented by intel_choose_pipe_bpp_dither. */
5463 BUG();
c8203565
PZ		 5464 }
5465
d8b32247 5466 if (intel_crtc->config.dither)
c8203565
PZ		 5467 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5468
6ff93609 5469 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5470 val |= PIPECONF_INTERLACED_ILK;
5471 else
5472 val |= PIPECONF_PROGRESSIVE;
5473
50f3b016 5474 if (intel_crtc->config.limited_color_range)
3685a8f3 5475 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5476
c8203565
PZ		 5477 I915_WRITE(PIPECONF(pipe), val);
5478 POSTING_READ(PIPECONF(pipe));
5479}
5480
86d3efce
VS		 5481/*
5482 * Set up the pipe CSC unit.
5483 *
5484 * Currently only full range RGB to limited range RGB conversion
5485 * is supported, but eventually this should handle various
5486 * RGB<->YCbCr scenarios as well.
5487 */
50f3b016 5488static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5489{
5490 struct drm_device *dev = crtc->dev;
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5493 int pipe = intel_crtc->pipe;
5494 uint16_t coeff = 0x7800; /* 1.0 */
5495
5496 /*
5497 * TODO: Check what kind of values actually come out of the pipe
5498 * with these coeff/postoff values and adjust to get the best
5499 * accuracy. Perhaps we even need to take the bpc value into
5500 * consideration.
5501 */
5502
50f3b016 5503 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5504 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5505
5506 /*
5507 * GY/GU and RY/RU should be the other way around according
5508 * to BSpec, but reality doesn't agree. Just set them up in
5509 * a way that results in the correct picture.
5510 */
5511 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5512 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5513
5514 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5515 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5516
5517 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5518 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5519
5520 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5521 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5522 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5523
5524 if (INTEL_INFO(dev)->gen > 6) {
5525 uint16_t postoff = 0;
5526
50f3b016 5527 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5528 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5529
5530 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5531 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5532 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5533
5534 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5535 } else {
5536 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5537
50f3b016 5538 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5539 mode |= CSC_BLACK_SCREEN_OFFSET;
5540
5541 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5542 }
5543}
5544
6ff93609 5545static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5546{
5547 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5549 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5550 uint32_t val;
5551
3eff4faa 5552 val = 0;
ee2b0b38 5553
d8b32247 5554 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5555 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5556
6ff93609 5557 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5558 val |= PIPECONF_INTERLACED_ILK;
5559 else
5560 val |= PIPECONF_PROGRESSIVE;
5561
702e7a56
PZ		 5562 I915_WRITE(PIPECONF(cpu_transcoder), val);
5563 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5564
5565 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5566 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5567}
5568
6591c6e4 5569static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5570 intel_clock_t *clock,
5571 bool *has_reduced_clock,
5572 intel_clock_t *reduced_clock)
5573{
5574 struct drm_device *dev = crtc->dev;
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 struct intel_encoder *intel_encoder;
5577 int refclk;
d4906093 5578 const intel_limit_t *limit;
a16af721 5579 bool ret, is_lvds = false;
79e53945 5580
6591c6e4
PZ		 5581 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5582 switch (intel_encoder->type) {
79e53945
JB		 5583 case INTEL_OUTPUT_LVDS:
5584 is_lvds = true;
5585 break;
79e53945
JB		 5586 }
5587 }
5588
d9d444cb 5589 refclk = ironlake_get_refclk(crtc);
79e53945 5590
d4906093
ML		 5591 /*
5592 * Returns a set of divisors for the desired target clock with the given
5593 * refclk, or FALSE. The returned values represent the clock equation:
5594 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5595 */
1b894b59 5596 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5597 ret = dev_priv->display.find_dpll(limit, crtc,
5598 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5599 refclk, NULL, clock);
6591c6e4
PZ		 5600 if (!ret)
5601 return false;
cda4b7d3 5602
ddc9003c 5603 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5604 /*
5605 * Ensure we match the reduced clock's P to the target clock.
5606 * If the clocks don't match, we can't switch the display clock
5607 * by using the FP0/FP1. In such case we will disable the LVDS
5608 * downclock feature.
5609 */
ee9300bb
DV		 5610 *has_reduced_clock =
5611 dev_priv->display.find_dpll(limit, crtc,
5612 dev_priv->lvds_downclock,
5613 refclk, clock,
5614 reduced_clock);
652c393a 5615 }
61e9653f 5616
6591c6e4
PZ		 5617 return true;
5618}
5619
01a415fd
DV		 5620static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5621{
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 uint32_t temp;
5624
5625 temp = I915_READ(SOUTH_CHICKEN1);
5626 if (temp & FDI_BC_BIFURCATION_SELECT)
5627 return;
5628
5629 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5630 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5631
5632 temp |= FDI_BC_BIFURCATION_SELECT;
5633 DRM_DEBUG_KMS("enabling fdi C rx\n");
5634 I915_WRITE(SOUTH_CHICKEN1, temp);
5635 POSTING_READ(SOUTH_CHICKEN1);
5636}
5637
ebfd86fd 5638static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5639{
5640 struct drm_device *dev = intel_crtc->base.dev;
5641 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5642
5643 switch (intel_crtc->pipe) {
5644 case PIPE_A:
ebfd86fd 5645 break;
01a415fd 5646 case PIPE_B:
ebfd86fd 5647 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5648 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5649 else
5650 cpt_enable_fdi_bc_bifurcation(dev);
5651
ebfd86fd 5652 break;
01a415fd 5653 case PIPE_C:
01a415fd
DV		 5654 cpt_enable_fdi_bc_bifurcation(dev);
5655
ebfd86fd 5656 break;
01a415fd
DV		 5657 default:
5658 BUG();
5659 }
5660}
5661
d4b1931c
PZ		 5662int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5663{
5664 /*
5665 * Account for spread spectrum to avoid
5666 * oversubscribing the link. Max center spread
5667 * is 2.5%; use 5% for safety's sake.
5668 */
5669 u32 bps = target_clock * bpp * 21 / 20;
5670 return bps / (link_bw * 8) + 1;
5671}
5672
7429e9d4 5673static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5674{
7429e9d4 5675 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5676}
5677
de13a2e3 5678static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5679 u32 *fp,
9a7c7890 5680 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5681{
de13a2e3 5682 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5683 struct drm_device *dev = crtc->dev;
5684 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5685 struct intel_encoder *intel_encoder;
5686 uint32_t dpll;
6cc5f341 5687 int factor, num_connectors = 0;
09ede541 5688 bool is_lvds = false, is_sdvo = false;
79e53945 5689
de13a2e3
PZ		 5690 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5691 switch (intel_encoder->type) {
79e53945
JB		 5692 case INTEL_OUTPUT_LVDS:
5693 is_lvds = true;
5694 break;
5695 case INTEL_OUTPUT_SDVO:
7d57382e 5696 case INTEL_OUTPUT_HDMI:
79e53945 5697 is_sdvo = true;
79e53945 5698 break;
79e53945 5699 }
43565a06 5700
c751ce4f 5701 num_connectors++;
79e53945 5702 }
79e53945 5703
c1858123 5704 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5705 factor = 21;
5706 if (is_lvds) {
5707 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5708 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5709 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5710 factor = 25;
09ede541 5711 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5712 factor = 20;
c1858123 5713
7429e9d4 5714 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5715 *fp |= FP_CB_TUNE;
2c07245f 5716
9a7c7890
DV		 5717 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5718 *fp2 |= FP_CB_TUNE;
5719
5eddb70b 5720 dpll = 0;
2c07245f 5721
a07d6787
EA		 5722 if (is_lvds)
5723 dpll |= DPLLB_MODE_LVDS;
5724 else
5725 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5726
ef1b460d
DV		 5727 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5728 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5729
5730 if (is_sdvo)
4a33e48d 5731 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5732 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5733 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5734
a07d6787 5735 /* compute bitmask from p1 value */
7429e9d4 5736 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5737 /* also FPA1 */
7429e9d4 5738 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5739
7429e9d4 5740 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5741 case 5:
5742 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5743 break;
5744 case 7:
5745 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5746 break;
5747 case 10:
5748 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5749 break;
5750 case 14:
5751 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5752 break;
79e53945
JB		 5753 }
5754
b4c09f3b 5755 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5756 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5757 else
5758 dpll |= PLL_REF_INPUT_DREFCLK;
5759
959e16d6 5760 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5761}
5762
5763static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5764 int x, int y,
5765 struct drm_framebuffer *fb)
5766{
5767 struct drm_device *dev = crtc->dev;
5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5770 int pipe = intel_crtc->pipe;
5771 int plane = intel_crtc->plane;
5772 int num_connectors = 0;
5773 intel_clock_t clock, reduced_clock;
cbbab5bd 5774 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5775 bool ok, has_reduced_clock = false;
8b47047b 5776 bool is_lvds = false;
de13a2e3 5777 struct intel_encoder *encoder;
e2b78267 5778 struct intel_shared_dpll *pll;
de13a2e3 5779 int ret;
de13a2e3
PZ		 5780
5781 for_each_encoder_on_crtc(dev, crtc, encoder) {
5782 switch (encoder->type) {
5783 case INTEL_OUTPUT_LVDS:
5784 is_lvds = true;
5785 break;
de13a2e3
PZ		 5786 }
5787
5788 num_connectors++;
a07d6787 5789 }
79e53945 5790
5dc5298b
PZ		 5791 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5792 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5793
ff9a6750 5794 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5795 &has_reduced_clock, &reduced_clock);
ee9300bb 5796 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5797 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5798 return -EINVAL;
79e53945 5799 }
f47709a9
DV		 5800 /* Compat-code for transition, will disappear. */
5801 if (!intel_crtc->config.clock_set) {
5802 intel_crtc->config.dpll.n = clock.n;
5803 intel_crtc->config.dpll.m1 = clock.m1;
5804 intel_crtc->config.dpll.m2 = clock.m2;
5805 intel_crtc->config.dpll.p1 = clock.p1;
5806 intel_crtc->config.dpll.p2 = clock.p2;
5807 }
79e53945 5808
de13a2e3
PZ		 5809 /* Ensure that the cursor is valid for the new mode before changing... */
5810 intel_crtc_update_cursor(crtc, true);
5811
5dc5298b 5812 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5813 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5814 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5815 if (has_reduced_clock)
7429e9d4 5816 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5817
7429e9d4 5818 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5819 &fp, &reduced_clock,
5820 has_reduced_clock ? &fp2 : NULL);
5821
959e16d6 5822 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5823 intel_crtc->config.dpll_hw_state.fp0 = fp;
5824 if (has_reduced_clock)
5825 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5826 else
5827 intel_crtc->config.dpll_hw_state.fp1 = fp;
5828
b89a1d39 5829 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5830 if (pll == NULL) {
84f44ce7
VS		 5831 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5832 pipe_name(pipe));
4b645f14
JB		 5833 return -EINVAL;
5834 }
ee7b9f93 5835 } else
e72f9fbf 5836 intel_put_shared_dpll(intel_crtc);
79e53945 5837
03afc4a2
DV		 5838 if (intel_crtc->config.has_dp_encoder)
5839 intel_dp_set_m_n(intel_crtc);
79e53945 5840
bcd644e0
DV		 5841 if (is_lvds && has_reduced_clock && i915_powersave)
5842 intel_crtc->lowfreq_avail = true;
5843 else
5844 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5845
5846 if (intel_crtc->config.has_pch_encoder) {
5847 pll = intel_crtc_to_shared_dpll(intel_crtc);
5848
652c393a
JB		 5849 }
5850
8a654f3b 5851 intel_set_pipe_timings(intel_crtc);
5eddb70b 5852
ca3a0ff8 5853 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5854 intel_cpu_transcoder_set_m_n(intel_crtc,
5855 &intel_crtc->config.fdi_m_n);
5856 }
2c07245f 5857
ebfd86fd
DV		 5858 if (IS_IVYBRIDGE(dev))
5859 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5860
6ff93609 5861 ironlake_set_pipeconf(crtc);
79e53945 5862
a1f9e77e
PZ		 5863 /* Set up the display plane register */
5864 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5865 POSTING_READ(DSPCNTR(plane));
79e53945 5866
94352cf9 5867 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5868
5869 intel_update_watermarks(dev);
5870
1857e1da 5871 return ret;
79e53945
JB		 5872}
5873
72419203
DV		 5874static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5875 struct intel_crtc_config *pipe_config)
5876{
5877 struct drm_device *dev = crtc->base.dev;
5878 struct drm_i915_private *dev_priv = dev->dev_private;
5879 enum transcoder transcoder = pipe_config->cpu_transcoder;
5880
5881 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5882 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5883 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5884 & ~TU_SIZE_MASK;
5885 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5886 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5887 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5888}
5889
2fa2fe9a
DV		 5890static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5891 struct intel_crtc_config *pipe_config)
5892{
5893 struct drm_device *dev = crtc->base.dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 uint32_t tmp;
5896
5897 tmp = I915_READ(PF_CTL(crtc->pipe));
5898
5899 if (tmp & PF_ENABLE) {
5900 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5901 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5902
5903 /* We currently do not free assignements of panel fitters on
5904 * ivb/hsw (since we don't use the higher upscaling modes which
5905 * differentiates them) so just WARN about this case for now. */
5906 if (IS_GEN7(dev)) {
5907 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5908 PF_PIPE_SEL_IVB(crtc->pipe));
5909 }
2fa2fe9a 5910 }
79e53945
JB		 5911}
5912
0e8ffe1b
DV		 5913static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5914 struct intel_crtc_config *pipe_config)
5915{
5916 struct drm_device *dev = crtc->base.dev;
5917 struct drm_i915_private *dev_priv = dev->dev_private;
5918 uint32_t tmp;
5919
e143a21c 5920 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5921 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5922
0e8ffe1b
DV		 5923 tmp = I915_READ(PIPECONF(crtc->pipe));
5924 if (!(tmp & PIPECONF_ENABLE))
5925 return false;
5926
ab9412ba 5927 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5928 struct intel_shared_dpll *pll;
5929
88adfff1
DV		 5930 pipe_config->has_pch_encoder = true;
5931
627eb5a3
DV		 5932 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5933 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5934 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5935
5936 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5937
c0d43d62 5938 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5939 pipe_config->shared_dpll =
5940 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5941 } else {
5942 tmp = I915_READ(PCH_DPLL_SEL);
5943 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5944 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5945 else
5946 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5947 }
66e985c0
DV		 5948
5949 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5950
5951 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5952 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5953
5954 tmp = pipe_config->dpll_hw_state.dpll;
5955 pipe_config->pixel_multiplier =
5956 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5957 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5958 } else {
5959 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5960 }
5961
1bd1bd80
DV		 5962 intel_get_pipe_timings(crtc, pipe_config);
5963
2fa2fe9a
DV		 5964 ironlake_get_pfit_config(crtc, pipe_config);
5965
0e8ffe1b
DV		 5966 return true;
5967}
5968
be256dc7
PZ		 5969static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5970{
5971 struct drm_device *dev = dev_priv->dev;
5972 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5973 struct intel_crtc *crtc;
5974 unsigned long irqflags;
bd633a7c 5975 uint32_t val;
be256dc7
PZ		 5976
5977 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5978 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5979 pipe_name(crtc->pipe));
5980
5981 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5982 WARN(plls->spll_refcount, "SPLL enabled\n");
5983 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5984 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5985 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5986 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5987 "CPU PWM1 enabled\n");
5988 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5989 "CPU PWM2 enabled\n");
5990 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5991 "PCH PWM1 enabled\n");
5992 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5993 "Utility pin enabled\n");
5994 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5995
5996 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5997 val = I915_READ(DEIMR);
5998 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5999 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6000 val = I915_READ(SDEIMR);
bd633a7c 6001 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6002 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6003 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6004}
6005
6006/*
6007 * This function implements pieces of two sequences from BSpec:
6008 * - Sequence for display software to disable LCPLL
6009 * - Sequence for display software to allow package C8+
6010 * The steps implemented here are just the steps that actually touch the LCPLL
6011 * register. Callers should take care of disabling all the display engine
6012 * functions, doing the mode unset, fixing interrupts, etc.
6013 */
6014void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6015 bool switch_to_fclk, bool allow_power_down)
6016{
6017 uint32_t val;
6018
6019 assert_can_disable_lcpll(dev_priv);
6020
6021 val = I915_READ(LCPLL_CTL);
6022
6023 if (switch_to_fclk) {
6024 val |= LCPLL_CD_SOURCE_FCLK;
6025 I915_WRITE(LCPLL_CTL, val);
6026
6027 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6028 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6029 DRM_ERROR("Switching to FCLK failed\n");
6030
6031 val = I915_READ(LCPLL_CTL);
6032 }
6033
6034 val |= LCPLL_PLL_DISABLE;
6035 I915_WRITE(LCPLL_CTL, val);
6036 POSTING_READ(LCPLL_CTL);
6037
6038 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6039 DRM_ERROR("LCPLL still locked\n");
6040
6041 val = I915_READ(D_COMP);
6042 val |= D_COMP_COMP_DISABLE;
6043 I915_WRITE(D_COMP, val);
6044 POSTING_READ(D_COMP);
6045 ndelay(100);
6046
6047 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6048 DRM_ERROR("D_COMP RCOMP still in progress\n");
6049
6050 if (allow_power_down) {
6051 val = I915_READ(LCPLL_CTL);
6052 val |= LCPLL_POWER_DOWN_ALLOW;
6053 I915_WRITE(LCPLL_CTL, val);
6054 POSTING_READ(LCPLL_CTL);
6055 }
6056}
6057
6058/*
6059 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6060 * source.
6061 */
6062void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6063{
6064 uint32_t val;
6065
6066 val = I915_READ(LCPLL_CTL);
6067
6068 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6069 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6070 return;
6071
215733fa
PZ		 6072 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6073 * we'll hang the machine! */
6074 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6075
be256dc7
PZ		 6076 if (val & LCPLL_POWER_DOWN_ALLOW) {
6077 val &= ~LCPLL_POWER_DOWN_ALLOW;
6078 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6079 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6080 }
6081
6082 val = I915_READ(D_COMP);
6083 val |= D_COMP_COMP_FORCE;
6084 val &= ~D_COMP_COMP_DISABLE;
6085 I915_WRITE(D_COMP, val);
35d8f2eb 6086 POSTING_READ(D_COMP);
be256dc7
PZ		 6087
6088 val = I915_READ(LCPLL_CTL);
6089 val &= ~LCPLL_PLL_DISABLE;
6090 I915_WRITE(LCPLL_CTL, val);
6091
6092 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6093 DRM_ERROR("LCPLL not locked yet\n");
6094
6095 if (val & LCPLL_CD_SOURCE_FCLK) {
6096 val = I915_READ(LCPLL_CTL);
6097 val &= ~LCPLL_CD_SOURCE_FCLK;
6098 I915_WRITE(LCPLL_CTL, val);
6099
6100 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6101 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6102 DRM_ERROR("Switching back to LCPLL failed\n");
6103 }
215733fa
PZ		 6104
6105 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6106}
6107
c67a470b
PZ		 6108void hsw_enable_pc8_work(struct work_struct *__work)
6109{
6110 struct drm_i915_private *dev_priv =
6111 container_of(to_delayed_work(__work), struct drm_i915_private,
6112 pc8.enable_work);
6113 struct drm_device *dev = dev_priv->dev;
6114 uint32_t val;
6115
6116 if (dev_priv->pc8.enabled)
6117 return;
6118
6119 DRM_DEBUG_KMS("Enabling package C8+\n");
6120
6121 dev_priv->pc8.enabled = true;
6122
6123 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6124 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6125 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6126 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6127 }
6128
6129 lpt_disable_clkout_dp(dev);
6130 hsw_pc8_disable_interrupts(dev);
6131 hsw_disable_lcpll(dev_priv, true, true);
6132}
6133
6134static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6135{
6136 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6137 WARN(dev_priv->pc8.disable_count < 1,
6138 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6139
6140 dev_priv->pc8.disable_count--;
6141 if (dev_priv->pc8.disable_count != 0)
6142 return;
6143
6144 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6145 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6146}
6147
6148static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6149{
6150 struct drm_device *dev = dev_priv->dev;
6151 uint32_t val;
6152
6153 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6154 WARN(dev_priv->pc8.disable_count < 0,
6155 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6156
6157 dev_priv->pc8.disable_count++;
6158 if (dev_priv->pc8.disable_count != 1)
6159 return;
6160
6161 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6162 if (!dev_priv->pc8.enabled)
6163 return;
6164
6165 DRM_DEBUG_KMS("Disabling package C8+\n");
6166
6167 hsw_restore_lcpll(dev_priv);
6168 hsw_pc8_restore_interrupts(dev);
6169 lpt_init_pch_refclk(dev);
6170
6171 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6172 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6173 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6174 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6175 }
6176
6177 intel_prepare_ddi(dev);
6178 i915_gem_init_swizzling(dev);
6179 mutex_lock(&dev_priv->rps.hw_lock);
6180 gen6_update_ring_freq(dev);
6181 mutex_unlock(&dev_priv->rps.hw_lock);
6182 dev_priv->pc8.enabled = false;
6183}
6184
6185void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6186{
6187 mutex_lock(&dev_priv->pc8.lock);
6188 __hsw_enable_package_c8(dev_priv);
6189 mutex_unlock(&dev_priv->pc8.lock);
6190}
6191
6192void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6193{
6194 mutex_lock(&dev_priv->pc8.lock);
6195 __hsw_disable_package_c8(dev_priv);
6196 mutex_unlock(&dev_priv->pc8.lock);
6197}
6198
6199static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6200{
6201 struct drm_device *dev = dev_priv->dev;
6202 struct intel_crtc *crtc;
6203 uint32_t val;
6204
6205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6206 if (crtc->base.enabled)
6207 return false;
6208
6209 /* This case is still possible since we have the i915.disable_power_well
6210 * parameter and also the KVMr or something else might be requesting the
6211 * power well. */
6212 val = I915_READ(HSW_PWR_WELL_DRIVER);
6213 if (val != 0) {
6214 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6215 return false;
6216 }
6217
6218 return true;
6219}
6220
6221/* Since we're called from modeset_global_resources there's no way to
6222 * symmetrically increase and decrease the refcount, so we use
6223 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6224 * or not.
6225 */
6226static void hsw_update_package_c8(struct drm_device *dev)
6227{
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 bool allow;
6230
6231 if (!i915_enable_pc8)
6232 return;
6233
6234 mutex_lock(&dev_priv->pc8.lock);
6235
6236 allow = hsw_can_enable_package_c8(dev_priv);
6237
6238 if (allow == dev_priv->pc8.requirements_met)
6239 goto done;
6240
6241 dev_priv->pc8.requirements_met = allow;
6242
6243 if (allow)
6244 __hsw_enable_package_c8(dev_priv);
6245 else
6246 __hsw_disable_package_c8(dev_priv);
6247
6248done:
6249 mutex_unlock(&dev_priv->pc8.lock);
6250}
6251
6252static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6253{
6254 if (!dev_priv->pc8.gpu_idle) {
6255 dev_priv->pc8.gpu_idle = true;
6256 hsw_enable_package_c8(dev_priv);
6257 }
6258}
6259
6260static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6261{
6262 if (dev_priv->pc8.gpu_idle) {
6263 dev_priv->pc8.gpu_idle = false;
6264 hsw_disable_package_c8(dev_priv);
6265 }
be256dc7
PZ		 6266}
6267
d6dd9eb1
DV		 6268static void haswell_modeset_global_resources(struct drm_device *dev)
6269{
d6dd9eb1
DV		 6270 bool enable = false;
6271 struct intel_crtc *crtc;
d6dd9eb1
DV		 6272
6273 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6274 if (!crtc->base.enabled)
6275 continue;
d6dd9eb1 6276
e7a639c4
DV		 6277 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6278 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6279 enable = true;
6280 }
6281
d6dd9eb1 6282 intel_set_power_well(dev, enable);
c67a470b
PZ		 6283
6284 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6285}
6286
09b4ddf9 6287static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6288 int x, int y,
6289 struct drm_framebuffer *fb)
6290{
6291 struct drm_device *dev = crtc->dev;
6292 struct drm_i915_private *dev_priv = dev->dev_private;
6293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6294 int plane = intel_crtc->plane;
09b4ddf9 6295 int ret;
09b4ddf9 6296
ff9a6750 6297 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6298 return -EINVAL;
6299
09b4ddf9
PZ		 6300 /* Ensure that the cursor is valid for the new mode before changing... */
6301 intel_crtc_update_cursor(crtc, true);
6302
03afc4a2
DV		 6303 if (intel_crtc->config.has_dp_encoder)
6304 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6305
6306 intel_crtc->lowfreq_avail = false;
09b4ddf9 6307
8a654f3b 6308 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6309
ca3a0ff8 6310 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6311 intel_cpu_transcoder_set_m_n(intel_crtc,
6312 &intel_crtc->config.fdi_m_n);
6313 }
09b4ddf9 6314
6ff93609 6315 haswell_set_pipeconf(crtc);
09b4ddf9 6316
50f3b016 6317 intel_set_pipe_csc(crtc);
86d3efce 6318
09b4ddf9 6319 /* Set up the display plane register */
86d3efce 6320 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6321 POSTING_READ(DSPCNTR(plane));
6322
6323 ret = intel_pipe_set_base(crtc, x, y, fb);
6324
6325 intel_update_watermarks(dev);
6326
1f803ee5 6327 return ret;
79e53945
JB		 6328}
6329
0e8ffe1b
DV		 6330static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6331 struct intel_crtc_config *pipe_config)
6332{
6333 struct drm_device *dev = crtc->base.dev;
6334 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6335 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6336 uint32_t tmp;
6337
e143a21c 6338 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6339 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6340
eccb140b
DV		 6341 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6342 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6343 enum pipe trans_edp_pipe;
6344 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6345 default:
6346 WARN(1, "unknown pipe linked to edp transcoder\n");
6347 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6348 case TRANS_DDI_EDP_INPUT_A_ON:
6349 trans_edp_pipe = PIPE_A;
6350 break;
6351 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6352 trans_edp_pipe = PIPE_B;
6353 break;
6354 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6355 trans_edp_pipe = PIPE_C;
6356 break;
6357 }
6358
6359 if (trans_edp_pipe == crtc->pipe)
6360 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6361 }
6362
b97186f0 6363 if (!intel_display_power_enabled(dev,
eccb140b 6364 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6365 return false;
6366
eccb140b 6367 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6368 if (!(tmp & PIPECONF_ENABLE))
6369 return false;
6370
88adfff1 6371 /*
f196e6be 6372 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6373 * DDI E. So just check whether this pipe is wired to DDI E and whether
6374 * the PCH transcoder is on.
6375 */
eccb140b 6376 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6377 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6378 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6379 pipe_config->has_pch_encoder = true;
6380
627eb5a3
DV		 6381 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6382 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6383 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6384
6385 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6386 }
6387
1bd1bd80
DV		 6388 intel_get_pipe_timings(crtc, pipe_config);
6389
2fa2fe9a
DV		 6390 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6391 if (intel_display_power_enabled(dev, pfit_domain))
6392 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6393
42db64ef
PZ		 6394 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6395 (I915_READ(IPS_CTL) & IPS_ENABLE);
6396
6c49f241
DV		 6397 pipe_config->pixel_multiplier = 1;
6398
0e8ffe1b
DV		 6399 return true;
6400}
6401
f564048e 6402static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6403 int x, int y,
94352cf9 6404 struct drm_framebuffer *fb)
f564048e
EA		 6405{
6406 struct drm_device *dev = crtc->dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6408 struct intel_encoder *encoder;
0b701d27 6409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6410 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6411 int pipe = intel_crtc->pipe;
f564048e
EA		 6412 int ret;
6413
0b701d27 6414 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6415
b8cecdf5
DV		 6416 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6417
79e53945 6418 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6419
9256aa19
DV		 6420 if (ret != 0)
6421 return ret;
6422
6423 for_each_encoder_on_crtc(dev, crtc, encoder) {
6424 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6425 encoder->base.base.id,
6426 drm_get_encoder_name(&encoder->base),
6427 mode->base.id, mode->name);
36f2d1f1 6428 encoder->mode_set(encoder);
9256aa19
DV		 6429 }
6430
6431 return 0;
79e53945
JB		 6432}
6433
3a9627f4
WF		 6434static bool intel_eld_uptodate(struct drm_connector *connector,
6435 int reg_eldv, uint32_t bits_eldv,
6436 int reg_elda, uint32_t bits_elda,
6437 int reg_edid)
6438{
6439 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6440 uint8_t *eld = connector->eld;
6441 uint32_t i;
6442
6443 i = I915_READ(reg_eldv);
6444 i &= bits_eldv;
6445
6446 if (!eld[0])
6447 return !i;
6448
6449 if (!i)
6450 return false;
6451
6452 i = I915_READ(reg_elda);
6453 i &= ~bits_elda;
6454 I915_WRITE(reg_elda, i);
6455
6456 for (i = 0; i < eld[2]; i++)
6457 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6458 return false;
6459
6460 return true;
6461}
6462
e0dac65e
WF		 6463static void g4x_write_eld(struct drm_connector *connector,
6464 struct drm_crtc *crtc)
6465{
6466 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6467 uint8_t *eld = connector->eld;
6468 uint32_t eldv;
6469 uint32_t len;
6470 uint32_t i;
6471
6472 i = I915_READ(G4X_AUD_VID_DID);
6473
6474 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6475 eldv = G4X_ELDV_DEVCL_DEVBLC;
6476 else
6477 eldv = G4X_ELDV_DEVCTG;
6478
3a9627f4
WF		 6479 if (intel_eld_uptodate(connector,
6480 G4X_AUD_CNTL_ST, eldv,
6481 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6482 G4X_HDMIW_HDMIEDID))
6483 return;
6484
e0dac65e
WF		 6485 i = I915_READ(G4X_AUD_CNTL_ST);
6486 i &= ~(eldv | G4X_ELD_ADDR);
6487 len = (i >> 9) & 0x1f; /* ELD buffer size */
6488 I915_WRITE(G4X_AUD_CNTL_ST, i);
6489
6490 if (!eld[0])
6491 return;
6492
6493 len = min_t(uint8_t, eld[2], len);
6494 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6495 for (i = 0; i < len; i++)
6496 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6497
6498 i = I915_READ(G4X_AUD_CNTL_ST);
6499 i |= eldv;
6500 I915_WRITE(G4X_AUD_CNTL_ST, i);
6501}
6502
83358c85
WX		 6503static void haswell_write_eld(struct drm_connector *connector,
6504 struct drm_crtc *crtc)
6505{
6506 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6507 uint8_t *eld = connector->eld;
6508 struct drm_device *dev = crtc->dev;
7b9f35a6 6509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6510 uint32_t eldv;
6511 uint32_t i;
6512 int len;
6513 int pipe = to_intel_crtc(crtc)->pipe;
6514 int tmp;
6515
6516 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6517 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6518 int aud_config = HSW_AUD_CFG(pipe);
6519 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6520
6521
6522 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6523
6524 /* Audio output enable */
6525 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6526 tmp = I915_READ(aud_cntrl_st2);
6527 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6528 I915_WRITE(aud_cntrl_st2, tmp);
6529
6530 /* Wait for 1 vertical blank */
6531 intel_wait_for_vblank(dev, pipe);
6532
6533 /* Set ELD valid state */
6534 tmp = I915_READ(aud_cntrl_st2);
6535 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6536 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6537 I915_WRITE(aud_cntrl_st2, tmp);
6538 tmp = I915_READ(aud_cntrl_st2);
6539 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6540
6541 /* Enable HDMI mode */
6542 tmp = I915_READ(aud_config);
6543 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6544 /* clear N_programing_enable and N_value_index */
6545 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6546 I915_WRITE(aud_config, tmp);
6547
6548 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6549
6550 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6551 intel_crtc->eld_vld = true;
83358c85
WX		 6552
6553 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6554 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6555 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6556 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6557 } else
6558 I915_WRITE(aud_config, 0);
6559
6560 if (intel_eld_uptodate(connector,
6561 aud_cntrl_st2, eldv,
6562 aud_cntl_st, IBX_ELD_ADDRESS,
6563 hdmiw_hdmiedid))
6564 return;
6565
6566 i = I915_READ(aud_cntrl_st2);
6567 i &= ~eldv;
6568 I915_WRITE(aud_cntrl_st2, i);
6569
6570 if (!eld[0])
6571 return;
6572
6573 i = I915_READ(aud_cntl_st);
6574 i &= ~IBX_ELD_ADDRESS;
6575 I915_WRITE(aud_cntl_st, i);
6576 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6577 DRM_DEBUG_DRIVER("port num:%d\n", i);
6578
6579 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6580 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6581 for (i = 0; i < len; i++)
6582 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6583
6584 i = I915_READ(aud_cntrl_st2);
6585 i |= eldv;
6586 I915_WRITE(aud_cntrl_st2, i);
6587
6588}
6589
e0dac65e
WF		 6590static void ironlake_write_eld(struct drm_connector *connector,
6591 struct drm_crtc *crtc)
6592{
6593 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6594 uint8_t *eld = connector->eld;
6595 uint32_t eldv;
6596 uint32_t i;
6597 int len;
6598 int hdmiw_hdmiedid;
b6daa025 6599 int aud_config;
e0dac65e
WF		 6600 int aud_cntl_st;
6601 int aud_cntrl_st2;
9b138a83 6602 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6603
b3f33cbf 6604 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6605 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6606 aud_config = IBX_AUD_CFG(pipe);
6607 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6608 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6609 } else {
9b138a83
WX		 6610 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6611 aud_config = CPT_AUD_CFG(pipe);
6612 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6613 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6614 }
6615
9b138a83 6616 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6617
6618 i = I915_READ(aud_cntl_st);
9b138a83 6619 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6620 if (!i) {
6621 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6622 /* operate blindly on all ports */
1202b4c6
WF		 6623 eldv = IBX_ELD_VALIDB;
6624 eldv |= IBX_ELD_VALIDB << 4;
6625 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6626 } else {
2582a850 6627 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6628 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6629 }
6630
3a9627f4
WF		 6631 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6632 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6633 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6634 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6635 } else
6636 I915_WRITE(aud_config, 0);
e0dac65e 6637
3a9627f4
WF		 6638 if (intel_eld_uptodate(connector,
6639 aud_cntrl_st2, eldv,
6640 aud_cntl_st, IBX_ELD_ADDRESS,
6641 hdmiw_hdmiedid))
6642 return;
6643
e0dac65e
WF		 6644 i = I915_READ(aud_cntrl_st2);
6645 i &= ~eldv;
6646 I915_WRITE(aud_cntrl_st2, i);
6647
6648 if (!eld[0])
6649 return;
6650
e0dac65e 6651 i = I915_READ(aud_cntl_st);
1202b4c6 6652 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6653 I915_WRITE(aud_cntl_st, i);
6654
6655 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6656 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6657 for (i = 0; i < len; i++)
6658 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6659
6660 i = I915_READ(aud_cntrl_st2);
6661 i |= eldv;
6662 I915_WRITE(aud_cntrl_st2, i);
6663}
6664
6665void intel_write_eld(struct drm_encoder *encoder,
6666 struct drm_display_mode *mode)
6667{
6668 struct drm_crtc *crtc = encoder->crtc;
6669 struct drm_connector *connector;
6670 struct drm_device *dev = encoder->dev;
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672
6673 connector = drm_select_eld(encoder, mode);
6674 if (!connector)
6675 return;
6676
6677 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6678 connector->base.id,
6679 drm_get_connector_name(connector),
6680 connector->encoder->base.id,
6681 drm_get_encoder_name(connector->encoder));
6682
6683 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6684
6685 if (dev_priv->display.write_eld)
6686 dev_priv->display.write_eld(connector, crtc);
6687}
6688
79e53945
JB		 6689/** Loads the palette/gamma unit for the CRTC with the prepared values */
6690void intel_crtc_load_lut(struct drm_crtc *crtc)
6691{
6692 struct drm_device *dev = crtc->dev;
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6695 enum pipe pipe = intel_crtc->pipe;
6696 int palreg = PALETTE(pipe);
79e53945 6697 int i;
42db64ef 6698 bool reenable_ips = false;
79e53945
JB		 6699
6700 /* The clocks have to be on to load the palette. */
aed3f09d 6701 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6702 return;
6703
23538ef1
JN		 6704 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6706 assert_dsi_pll_enabled(dev_priv);
6707 else
6708 assert_pll_enabled(dev_priv, pipe);
6709 }
14420bd0 6710
f2b115e6 6711 /* use legacy palette for Ironlake */
bad720ff 6712 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6713 palreg = LGC_PALETTE(pipe);
6714
6715 /* Workaround : Do not read or write the pipe palette/gamma data while
6716 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6717 */
6718 if (intel_crtc->config.ips_enabled &&
6719 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6720 GAMMA_MODE_MODE_SPLIT)) {
6721 hsw_disable_ips(intel_crtc);
6722 reenable_ips = true;
6723 }
2c07245f 6724
79e53945
JB		 6725 for (i = 0; i < 256; i++) {
6726 I915_WRITE(palreg + 4 * i,
6727 (intel_crtc->lut_r[i] << 16) |
6728 (intel_crtc->lut_g[i] << 8) |
6729 intel_crtc->lut_b[i]);
6730 }
42db64ef
PZ		 6731
6732 if (reenable_ips)
6733 hsw_enable_ips(intel_crtc);
79e53945
JB		 6734}
6735
560b85bb
CW		 6736static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6737{
6738 struct drm_device *dev = crtc->dev;
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6741 bool visible = base != 0;
6742 u32 cntl;
6743
6744 if (intel_crtc->cursor_visible == visible)
6745 return;
6746
9db4a9c7 6747 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6748 if (visible) {
6749 /* On these chipsets we can only modify the base whilst
6750 * the cursor is disabled.
6751 */
9db4a9c7 6752 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6753
6754 cntl &= ~(CURSOR_FORMAT_MASK);
6755 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6756 cntl |= CURSOR_ENABLE |
6757 CURSOR_GAMMA_ENABLE |
6758 CURSOR_FORMAT_ARGB;
6759 } else
6760 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6761 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6762
6763 intel_crtc->cursor_visible = visible;
6764}
6765
6766static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6767{
6768 struct drm_device *dev = crtc->dev;
6769 struct drm_i915_private *dev_priv = dev->dev_private;
6770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6771 int pipe = intel_crtc->pipe;
6772 bool visible = base != 0;
6773
6774 if (intel_crtc->cursor_visible != visible) {
548f245b 6775 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6776 if (base) {
6777 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6778 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6779 cntl |= pipe << 28; /* Connect to correct pipe */
6780 } else {
6781 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6782 cntl |= CURSOR_MODE_DISABLE;
6783 }
9db4a9c7 6784 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6785
6786 intel_crtc->cursor_visible = visible;
6787 }
6788 /* and commit changes on next vblank */
9db4a9c7 6789 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6790}
6791
65a21cd6
JB		 6792static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6793{
6794 struct drm_device *dev = crtc->dev;
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 int pipe = intel_crtc->pipe;
6798 bool visible = base != 0;
6799
6800 if (intel_crtc->cursor_visible != visible) {
6801 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6802 if (base) {
6803 cntl &= ~CURSOR_MODE;
6804 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6805 } else {
6806 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6807 cntl |= CURSOR_MODE_DISABLE;
6808 }
1f5d76db 6809 if (IS_HASWELL(dev)) {
86d3efce 6810 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6811 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6812 }
65a21cd6
JB		 6813 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6814
6815 intel_crtc->cursor_visible = visible;
6816 }
6817 /* and commit changes on next vblank */
6818 I915_WRITE(CURBASE_IVB(pipe), base);
6819}
6820
cda4b7d3 6821/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6822static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6823 bool on)
cda4b7d3
CW		 6824{
6825 struct drm_device *dev = crtc->dev;
6826 struct drm_i915_private *dev_priv = dev->dev_private;
6827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6828 int pipe = intel_crtc->pipe;
6829 int x = intel_crtc->cursor_x;
6830 int y = intel_crtc->cursor_y;
560b85bb 6831 u32 base, pos;
cda4b7d3
CW		 6832 bool visible;
6833
6834 pos = 0;
6835
6b383a7f 6836 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6837 base = intel_crtc->cursor_addr;
6838 if (x > (int) crtc->fb->width)
6839 base = 0;
6840
6841 if (y > (int) crtc->fb->height)
6842 base = 0;
6843 } else
6844 base = 0;
6845
6846 if (x < 0) {
6847 if (x + intel_crtc->cursor_width < 0)
6848 base = 0;
6849
6850 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6851 x = -x;
6852 }
6853 pos |= x << CURSOR_X_SHIFT;
6854
6855 if (y < 0) {
6856 if (y + intel_crtc->cursor_height < 0)
6857 base = 0;
6858
6859 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6860 y = -y;
6861 }
6862 pos |= y << CURSOR_Y_SHIFT;
6863
6864 visible = base != 0;
560b85bb 6865 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6866 return;
6867
0cd83aa9 6868 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6869 I915_WRITE(CURPOS_IVB(pipe), pos);
6870 ivb_update_cursor(crtc, base);
6871 } else {
6872 I915_WRITE(CURPOS(pipe), pos);
6873 if (IS_845G(dev) || IS_I865G(dev))
6874 i845_update_cursor(crtc, base);
6875 else
6876 i9xx_update_cursor(crtc, base);
6877 }
cda4b7d3
CW		 6878}
6879
79e53945 6880static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6881 struct drm_file *file,
79e53945
JB		 6882 uint32_t handle,
6883 uint32_t width, uint32_t height)
6884{
6885 struct drm_device *dev = crtc->dev;
6886 struct drm_i915_private *dev_priv = dev->dev_private;
6887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6888 struct drm_i915_gem_object *obj;
cda4b7d3 6889 uint32_t addr;
3f8bc370 6890 int ret;
79e53945 6891
79e53945
JB		 6892 /* if we want to turn off the cursor ignore width and height */
6893 if (!handle) {
28c97730 6894 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6895 addr = 0;
05394f39 6896 obj = NULL;
5004417d 6897 mutex_lock(&dev->struct_mutex);
3f8bc370 6898 goto finish;
79e53945
JB		 6899 }
6900
6901 /* Currently we only support 64x64 cursors */
6902 if (width != 64 || height != 64) {
6903 DRM_ERROR("we currently only support 64x64 cursors\n");
6904 return -EINVAL;
6905 }
6906
05394f39 6907 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6908 if (&obj->base == NULL)
79e53945
JB		 6909 return -ENOENT;
6910
05394f39 6911 if (obj->base.size < width * height * 4) {
79e53945 6912 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6913 ret = -ENOMEM;
6914 goto fail;
79e53945
JB		 6915 }
6916
71acb5eb 6917 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6918 mutex_lock(&dev->struct_mutex);
b295d1b6 6919 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6920 unsigned alignment;
6921
d9e86c0e
CW		 6922 if (obj->tiling_mode) {
6923 DRM_ERROR("cursor cannot be tiled\n");
6924 ret = -EINVAL;
6925 goto fail_locked;
6926 }
6927
693db184
CW		 6928 /* Note that the w/a also requires 2 PTE of padding following
6929 * the bo. We currently fill all unused PTE with the shadow
6930 * page and so we should always have valid PTE following the
6931 * cursor preventing the VT-d warning.
6932 */
6933 alignment = 0;
6934 if (need_vtd_wa(dev))
6935 alignment = 64*1024;
6936
6937 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6938 if (ret) {
6939 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6940 goto fail_locked;
e7b526bb
CW		 6941 }
6942
d9e86c0e
CW		 6943 ret = i915_gem_object_put_fence(obj);
6944 if (ret) {
2da3b9b9 6945 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6946 goto fail_unpin;
6947 }
6948
f343c5f6 6949 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6950 } else {
6eeefaf3 6951 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6952 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6953 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6954 align);
71acb5eb
DA		 6955 if (ret) {
6956 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6957 goto fail_locked;
71acb5eb 6958 }
05394f39 6959 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6960 }
6961
a6c45cf0 6962 if (IS_GEN2(dev))
14b60391
JB		 6963 I915_WRITE(CURSIZE, (height << 12) | width);
6964
3f8bc370 6965 finish:
3f8bc370 6966 if (intel_crtc->cursor_bo) {
b295d1b6 6967 if (dev_priv->info->cursor_needs_physical) {
05394f39 6968 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6969 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6970 } else
cc98b413 6971 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6972 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6973 }
80824003 6974
7f9872e0 6975 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6976
6977 intel_crtc->cursor_addr = addr;
05394f39 6978 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6979 intel_crtc->cursor_width = width;
6980 intel_crtc->cursor_height = height;
6981
40ccc72b 6982 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6983
79e53945 6984 return 0;
e7b526bb 6985fail_unpin:
cc98b413 6986 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6987fail_locked:
34b8686e 6988 mutex_unlock(&dev->struct_mutex);
bc9025bd 6989fail:
05394f39 6990 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6991 return ret;
79e53945
JB		 6992}
6993
6994static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6995{
79e53945 6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6997
cda4b7d3
CW		 6998 intel_crtc->cursor_x = x;
6999 intel_crtc->cursor_y = y;
652c393a 7000
40ccc72b 7001 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7002
7003 return 0;
7004}
7005
7006/** Sets the color ramps on behalf of RandR */
7007void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7008 u16 blue, int regno)
7009{
7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7011
7012 intel_crtc->lut_r[regno] = red >> 8;
7013 intel_crtc->lut_g[regno] = green >> 8;
7014 intel_crtc->lut_b[regno] = blue >> 8;
7015}
7016
b8c00ac5
DA		 7017void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7018 u16 *blue, int regno)
7019{
7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7021
7022 *red = intel_crtc->lut_r[regno] << 8;
7023 *green = intel_crtc->lut_g[regno] << 8;
7024 *blue = intel_crtc->lut_b[regno] << 8;
7025}
7026
79e53945 7027static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7028 u16 *blue, uint32_t start, uint32_t size)
79e53945 7029{
7203425a 7030 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7032
7203425a 7033 for (i = start; i < end; i++) {
79e53945
JB		 7034 intel_crtc->lut_r[i] = red[i] >> 8;
7035 intel_crtc->lut_g[i] = green[i] >> 8;
7036 intel_crtc->lut_b[i] = blue[i] >> 8;
7037 }
7038
7039 intel_crtc_load_lut(crtc);
7040}
7041
79e53945
JB		 7042/* VESA 640x480x72Hz mode to set on the pipe */
7043static struct drm_display_mode load_detect_mode = {
7044 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7045 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7046};
7047
d2dff872
CW		 7048static struct drm_framebuffer *
7049intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7050 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7051 struct drm_i915_gem_object *obj)
7052{
7053 struct intel_framebuffer *intel_fb;
7054 int ret;
7055
7056 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7057 if (!intel_fb) {
7058 drm_gem_object_unreference_unlocked(&obj->base);
7059 return ERR_PTR(-ENOMEM);
7060 }
7061
7062 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7063 if (ret) {
7064 drm_gem_object_unreference_unlocked(&obj->base);
7065 kfree(intel_fb);
7066 return ERR_PTR(ret);
7067 }
7068
7069 return &intel_fb->base;
7070}
7071
7072static u32
7073intel_framebuffer_pitch_for_width(int width, int bpp)
7074{
7075 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7076 return ALIGN(pitch, 64);
7077}
7078
7079static u32
7080intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7081{
7082 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7083 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7084}
7085
7086static struct drm_framebuffer *
7087intel_framebuffer_create_for_mode(struct drm_device *dev,
7088 struct drm_display_mode *mode,
7089 int depth, int bpp)
7090{
7091 struct drm_i915_gem_object *obj;
0fed39bd 7092 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7093
7094 obj = i915_gem_alloc_object(dev,
7095 intel_framebuffer_size_for_mode(mode, bpp));
7096 if (obj == NULL)
7097 return ERR_PTR(-ENOMEM);
7098
7099 mode_cmd.width = mode->hdisplay;
7100 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7101 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7102 bpp);
5ca0c34a 7103 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7104
7105 return intel_framebuffer_create(dev, &mode_cmd, obj);
7106}
7107
7108static struct drm_framebuffer *
7109mode_fits_in_fbdev(struct drm_device *dev,
7110 struct drm_display_mode *mode)
7111{
7112 struct drm_i915_private *dev_priv = dev->dev_private;
7113 struct drm_i915_gem_object *obj;
7114 struct drm_framebuffer *fb;
7115
7116 if (dev_priv->fbdev == NULL)
7117 return NULL;
7118
7119 obj = dev_priv->fbdev->ifb.obj;
7120 if (obj == NULL)
7121 return NULL;
7122
7123 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7124 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7125 fb->bits_per_pixel))
d2dff872
CW		 7126 return NULL;
7127
01f2c773 7128 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7129 return NULL;
7130
7131 return fb;
7132}
7133
d2434ab7 7134bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7135 struct drm_display_mode *mode,
8261b191 7136 struct intel_load_detect_pipe *old)
79e53945
JB		 7137{
7138 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7139 struct intel_encoder *intel_encoder =
7140 intel_attached_encoder(connector);
79e53945 7141 struct drm_crtc *possible_crtc;
4ef69c7a 7142 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7143 struct drm_crtc *crtc = NULL;
7144 struct drm_device *dev = encoder->dev;
94352cf9 7145 struct drm_framebuffer *fb;
79e53945
JB		 7146 int i = -1;
7147
d2dff872
CW		 7148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7149 connector->base.id, drm_get_connector_name(connector),
7150 encoder->base.id, drm_get_encoder_name(encoder));
7151
79e53945
JB		 7152 /*
7153 * Algorithm gets a little messy:
7a5e4805 7154 *
79e53945
JB		 7155 * - if the connector already has an assigned crtc, use it (but make
7156 * sure it's on first)
7a5e4805 7157 *
79e53945
JB		 7158 * - try to find the first unused crtc that can drive this connector,
7159 * and use that if we find one
79e53945
JB		 7160 */
7161
7162 /* See if we already have a CRTC for this connector */
7163 if (encoder->crtc) {
7164 crtc = encoder->crtc;
8261b191 7165
7b24056b
DV		 7166 mutex_lock(&crtc->mutex);
7167
24218aac 7168 old->dpms_mode = connector->dpms;
8261b191
CW		 7169 old->load_detect_temp = false;
7170
7171 /* Make sure the crtc and connector are running */
24218aac
DV		 7172 if (connector->dpms != DRM_MODE_DPMS_ON)
7173 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7174
7173188d 7175 return true;
79e53945
JB		 7176 }
7177
7178 /* Find an unused one (if possible) */
7179 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7180 i++;
7181 if (!(encoder->possible_crtcs & (1 << i)))
7182 continue;
7183 if (!possible_crtc->enabled) {
7184 crtc = possible_crtc;
7185 break;
7186 }
79e53945
JB		 7187 }
7188
7189 /*
7190 * If we didn't find an unused CRTC, don't use any.
7191 */
7192 if (!crtc) {
7173188d
CW		 7193 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7194 return false;
79e53945
JB		 7195 }
7196
7b24056b 7197 mutex_lock(&crtc->mutex);
fc303101
DV		 7198 intel_encoder->new_crtc = to_intel_crtc(crtc);
7199 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7200
7201 intel_crtc = to_intel_crtc(crtc);
24218aac 7202 old->dpms_mode = connector->dpms;
8261b191 7203 old->load_detect_temp = true;
d2dff872 7204 old->release_fb = NULL;
79e53945 7205
6492711d
CW		 7206 if (!mode)
7207 mode = &load_detect_mode;
79e53945 7208
d2dff872
CW		 7209 /* We need a framebuffer large enough to accommodate all accesses
7210 * that the plane may generate whilst we perform load detection.
7211 * We can not rely on the fbcon either being present (we get called
7212 * during its initialisation to detect all boot displays, or it may
7213 * not even exist) or that it is large enough to satisfy the
7214 * requested mode.
7215 */
94352cf9
DV		 7216 fb = mode_fits_in_fbdev(dev, mode);
7217 if (fb == NULL) {
d2dff872 7218 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7219 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7220 old->release_fb = fb;
d2dff872
CW		 7221 } else
7222 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7223 if (IS_ERR(fb)) {
d2dff872 7224 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7225 mutex_unlock(&crtc->mutex);
0e8b3d3e 7226 return false;
79e53945 7227 }
79e53945 7228
c0c36b94 7229 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7230 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7231 if (old->release_fb)
7232 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7233 mutex_unlock(&crtc->mutex);
0e8b3d3e 7234 return false;
79e53945 7235 }
7173188d 7236
79e53945 7237 /* let the connector get through one full cycle before testing */
9d0498a2 7238 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7239 return true;
79e53945
JB		 7240}
7241
d2434ab7 7242void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7243 struct intel_load_detect_pipe *old)
79e53945 7244{
d2434ab7
DV		 7245 struct intel_encoder *intel_encoder =
7246 intel_attached_encoder(connector);
4ef69c7a 7247 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7248 struct drm_crtc *crtc = encoder->crtc;
79e53945 7249
d2dff872
CW		 7250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7251 connector->base.id, drm_get_connector_name(connector),
7252 encoder->base.id, drm_get_encoder_name(encoder));
7253
8261b191 7254 if (old->load_detect_temp) {
fc303101
DV		 7255 to_intel_connector(connector)->new_encoder = NULL;
7256 intel_encoder->new_crtc = NULL;
7257 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7258
36206361
DV		 7259 if (old->release_fb) {
7260 drm_framebuffer_unregister_private(old->release_fb);
7261 drm_framebuffer_unreference(old->release_fb);
7262 }
d2dff872 7263
67c96400 7264 mutex_unlock(&crtc->mutex);
0622a53c 7265 return;
79e53945
JB		 7266 }
7267
c751ce4f 7268 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7269 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7270 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7271
7272 mutex_unlock(&crtc->mutex);
79e53945
JB		 7273}
7274
7275/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7276static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7277 struct intel_crtc_config *pipe_config)
79e53945 7278{
f1f644dc 7279 struct drm_device *dev = crtc->base.dev;
79e53945 7280 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7281 int pipe = pipe_config->cpu_transcoder;
548f245b 7282 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7283 u32 fp;
7284 intel_clock_t clock;
7285
7286 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7287 fp = I915_READ(FP0(pipe));
79e53945 7288 else
39adb7a5 7289 fp = I915_READ(FP1(pipe));
79e53945
JB		 7290
7291 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7292 if (IS_PINEVIEW(dev)) {
7293 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7294 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7295 } else {
7296 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7297 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7298 }
7299
a6c45cf0 7300 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7301 if (IS_PINEVIEW(dev))
7302 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7303 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7304 else
7305 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7306 DPLL_FPA01_P1_POST_DIV_SHIFT);
7307
7308 switch (dpll & DPLL_MODE_MASK) {
7309 case DPLLB_MODE_DAC_SERIAL:
7310 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7311 5 : 10;
7312 break;
7313 case DPLLB_MODE_LVDS:
7314 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7315 7 : 14;
7316 break;
7317 default:
28c97730 7318 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7319 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7320 pipe_config->adjusted_mode.clock = 0;
7321 return;
79e53945
JB		 7322 }
7323
ac58c3f0
DV		 7324 if (IS_PINEVIEW(dev))
7325 pineview_clock(96000, &clock);
7326 else
7327 i9xx_clock(96000, &clock);
79e53945
JB		 7328 } else {
7329 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7330
7331 if (is_lvds) {
7332 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7333 DPLL_FPA01_P1_POST_DIV_SHIFT);
7334 clock.p2 = 14;
7335
7336 if ((dpll & PLL_REF_INPUT_MASK) ==
7337 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7338 /* XXX: might not be 66MHz */
ac58c3f0 7339 i9xx_clock(66000, &clock);
79e53945 7340 } else
ac58c3f0 7341 i9xx_clock(48000, &clock);
79e53945
JB		 7342 } else {
7343 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7344 clock.p1 = 2;
7345 else {
7346 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7347 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7348 }
7349 if (dpll & PLL_P2_DIVIDE_BY_4)
7350 clock.p2 = 4;
7351 else
7352 clock.p2 = 2;
7353
ac58c3f0 7354 i9xx_clock(48000, &clock);
79e53945
JB		 7355 }
7356 }
7357
a2dc53e7 7358 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB		 7359}
7360
7361static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7362 struct intel_crtc_config *pipe_config)
7363{
7364 struct drm_device *dev = crtc->base.dev;
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7367 int link_freq, repeat;
7368 u64 clock;
7369 u32 link_m, link_n;
7370
7371 repeat = pipe_config->pixel_multiplier;
7372
7373 /*
7374 * The calculation for the data clock is:
7375 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7376 * But we want to avoid losing precison if possible, so:
7377 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7378 *
7379 * and the link clock is simpler:
7380 * link_clock = (m * link_clock * repeat) / n
7381 */
7382
7383 /*
7384 * We need to get the FDI or DP link clock here to derive
7385 * the M/N dividers.
7386 *
7387 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7388 * For DP, it's either 1.62GHz or 2.7GHz.
7389 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7390 */
f1f644dc
JB		 7391 if (pipe_config->has_pch_encoder)
7392 link_freq = intel_fdi_link_freq(dev) * 10000;
7393 else
7394 link_freq = pipe_config->port_clock;
7395
7396 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7397 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7398
7399 if (!link_m || !link_n)
7400 return;
79e53945 7401
f1f644dc
JB		 7402 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7403 do_div(clock, link_n);
7404
7405 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7406}
7407
7408/** Returns the currently programmed mode of the given pipe. */
7409struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7410 struct drm_crtc *crtc)
7411{
548f245b 7412 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7414 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7415 struct drm_display_mode *mode;
f1f644dc 7416 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7417 int htot = I915_READ(HTOTAL(cpu_transcoder));
7418 int hsync = I915_READ(HSYNC(cpu_transcoder));
7419 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7420 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7421
7422 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7423 if (!mode)
7424 return NULL;
7425
f1f644dc
JB		 7426 /*
7427 * Construct a pipe_config sufficient for getting the clock info
7428 * back out of crtc_clock_get.
7429 *
7430 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7431 * to use a real value here instead.
7432 */
e143a21c 7433 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7434 pipe_config.pixel_multiplier = 1;
7435 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7436
7437 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7438 mode->hdisplay = (htot & 0xffff) + 1;
7439 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7440 mode->hsync_start = (hsync & 0xffff) + 1;
7441 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7442 mode->vdisplay = (vtot & 0xffff) + 1;
7443 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7444 mode->vsync_start = (vsync & 0xffff) + 1;
7445 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7446
7447 drm_mode_set_name(mode);
79e53945
JB		 7448
7449 return mode;
7450}
7451
3dec0095 7452static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7453{
7454 struct drm_device *dev = crtc->dev;
7455 drm_i915_private_t *dev_priv = dev->dev_private;
7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7458 int dpll_reg = DPLL(pipe);
7459 int dpll;
652c393a 7460
bad720ff 7461 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7462 return;
7463
7464 if (!dev_priv->lvds_downclock_avail)
7465 return;
7466
dbdc6479 7467 dpll = I915_READ(dpll_reg);
652c393a 7468 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7469 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7470
8ac5a6d5 7471 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7472
7473 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7474 I915_WRITE(dpll_reg, dpll);
9d0498a2 7475 intel_wait_for_vblank(dev, pipe);
dbdc6479 7476
652c393a
JB		 7477 dpll = I915_READ(dpll_reg);
7478 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7479 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7480 }
652c393a
JB		 7481}
7482
7483static void intel_decrease_pllclock(struct drm_crtc *crtc)
7484{
7485 struct drm_device *dev = crtc->dev;
7486 drm_i915_private_t *dev_priv = dev->dev_private;
7487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7488
bad720ff 7489 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7490 return;
7491
7492 if (!dev_priv->lvds_downclock_avail)
7493 return;
7494
7495 /*
7496 * Since this is called by a timer, we should never get here in
7497 * the manual case.
7498 */
7499 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7500 int pipe = intel_crtc->pipe;
7501 int dpll_reg = DPLL(pipe);
7502 int dpll;
f6e5b160 7503
44d98a61 7504 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7505
8ac5a6d5 7506 assert_panel_unlocked(dev_priv, pipe);
652c393a 7507
dc257cf1 7508 dpll = I915_READ(dpll_reg);
652c393a
JB		 7509 dpll |= DISPLAY_RATE_SELECT_FPA1;
7510 I915_WRITE(dpll_reg, dpll);
9d0498a2 7511 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7512 dpll = I915_READ(dpll_reg);
7513 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7514 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7515 }
7516
7517}
7518
f047e395
CW		 7519void intel_mark_busy(struct drm_device *dev)
7520{
c67a470b
PZ		 7521 struct drm_i915_private *dev_priv = dev->dev_private;
7522
7523 hsw_package_c8_gpu_busy(dev_priv);
7524 i915_update_gfx_val(dev_priv);
f047e395
CW		 7525}
7526
7527void intel_mark_idle(struct drm_device *dev)
652c393a 7528{
c67a470b 7529 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7530 struct drm_crtc *crtc;
652c393a 7531
c67a470b
PZ		 7532 hsw_package_c8_gpu_idle(dev_priv);
7533
652c393a
JB		 7534 if (!i915_powersave)
7535 return;
7536
652c393a 7537 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7538 if (!crtc->fb)
7539 continue;
7540
725a5b54 7541 intel_decrease_pllclock(crtc);
652c393a 7542 }
652c393a
JB		 7543}
7544
c65355bb
CW		 7545void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7546 struct intel_ring_buffer *ring)
652c393a 7547{
f047e395
CW		 7548 struct drm_device *dev = obj->base.dev;
7549 struct drm_crtc *crtc;
652c393a 7550
f047e395 7551 if (!i915_powersave)
acb87dfb
CW		 7552 return;
7553
652c393a
JB		 7554 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7555 if (!crtc->fb)
7556 continue;
7557
c65355bb
CW		 7558 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7559 continue;
7560
7561 intel_increase_pllclock(crtc);
7562 if (ring && intel_fbc_enabled(dev))
7563 ring->fbc_dirty = true;
652c393a
JB		 7564 }
7565}
7566
79e53945
JB		 7567static void intel_crtc_destroy(struct drm_crtc *crtc)
7568{
7569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7570 struct drm_device *dev = crtc->dev;
7571 struct intel_unpin_work *work;
7572 unsigned long flags;
7573
7574 spin_lock_irqsave(&dev->event_lock, flags);
7575 work = intel_crtc->unpin_work;
7576 intel_crtc->unpin_work = NULL;
7577 spin_unlock_irqrestore(&dev->event_lock, flags);
7578
7579 if (work) {
7580 cancel_work_sync(&work->work);
7581 kfree(work);
7582 }
79e53945 7583
40ccc72b
MK		 7584 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7585
79e53945 7586 drm_crtc_cleanup(crtc);
67e77c5a 7587
79e53945
JB		 7588 kfree(intel_crtc);
7589}
7590
6b95a207
KH		 7591static void intel_unpin_work_fn(struct work_struct *__work)
7592{
7593 struct intel_unpin_work *work =
7594 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7595 struct drm_device *dev = work->crtc->dev;
6b95a207 7596
b4a98e57 7597 mutex_lock(&dev->struct_mutex);
1690e1eb 7598 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7599 drm_gem_object_unreference(&work->pending_flip_obj->base);
7600 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7601
b4a98e57
CW		 7602 intel_update_fbc(dev);
7603 mutex_unlock(&dev->struct_mutex);
7604
7605 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7606 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7607
6b95a207
KH		 7608 kfree(work);
7609}
7610
1afe3e9d 7611static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7612 struct drm_crtc *crtc)
6b95a207
KH		 7613{
7614 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7616 struct intel_unpin_work *work;
6b95a207
KH		 7617 unsigned long flags;
7618
7619 /* Ignore early vblank irqs */
7620 if (intel_crtc == NULL)
7621 return;
7622
7623 spin_lock_irqsave(&dev->event_lock, flags);
7624 work = intel_crtc->unpin_work;
e7d841ca
CW		 7625
7626 /* Ensure we don't miss a work->pending update ... */
7627 smp_rmb();
7628
7629 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7630 spin_unlock_irqrestore(&dev->event_lock, flags);
7631 return;
7632 }
7633
e7d841ca
CW		 7634 /* and that the unpin work is consistent wrt ->pending. */
7635 smp_rmb();
7636
6b95a207 7637 intel_crtc->unpin_work = NULL;
6b95a207 7638
45a066eb
RC		 7639 if (work->event)
7640 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7641
0af7e4df
MK		 7642 drm_vblank_put(dev, intel_crtc->pipe);
7643
6b95a207
KH		 7644 spin_unlock_irqrestore(&dev->event_lock, flags);
7645
2c10d571 7646 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7647
7648 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7649
7650 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7651}
7652
1afe3e9d
JB		 7653void intel_finish_page_flip(struct drm_device *dev, int pipe)
7654{
7655 drm_i915_private_t *dev_priv = dev->dev_private;
7656 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7657
49b14a5c 7658 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7659}
7660
7661void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7662{
7663 drm_i915_private_t *dev_priv = dev->dev_private;
7664 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7665
49b14a5c 7666 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7667}
7668
6b95a207
KH		 7669void intel_prepare_page_flip(struct drm_device *dev, int plane)
7670{
7671 drm_i915_private_t *dev_priv = dev->dev_private;
7672 struct intel_crtc *intel_crtc =
7673 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7674 unsigned long flags;
7675
e7d841ca
CW		 7676 /* NB: An MMIO update of the plane base pointer will also
7677 * generate a page-flip completion irq, i.e. every modeset
7678 * is also accompanied by a spurious intel_prepare_page_flip().
7679 */
6b95a207 7680 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7681 if (intel_crtc->unpin_work)
7682 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7683 spin_unlock_irqrestore(&dev->event_lock, flags);
7684}
7685
e7d841ca
CW		 7686inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7687{
7688 /* Ensure that the work item is consistent when activating it ... */
7689 smp_wmb();
7690 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7691 /* and that it is marked active as soon as the irq could fire. */
7692 smp_wmb();
7693}
7694
8c9f3aaf
JB		 7695static int intel_gen2_queue_flip(struct drm_device *dev,
7696 struct drm_crtc *crtc,
7697 struct drm_framebuffer *fb,
ed8d1975
KP		 7698 struct drm_i915_gem_object *obj,
7699 uint32_t flags)
8c9f3aaf
JB		 7700{
7701 struct drm_i915_private *dev_priv = dev->dev_private;
7702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7703 u32 flip_mask;
6d90c952 7704 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7705 int ret;
7706
6d90c952 7707 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7708 if (ret)
83d4092b 7709 goto err;
8c9f3aaf 7710
6d90c952 7711 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7712 if (ret)
83d4092b 7713 goto err_unpin;
8c9f3aaf
JB		 7714
7715 /* Can't queue multiple flips, so wait for the previous
7716 * one to finish before executing the next.
7717 */
7718 if (intel_crtc->plane)
7719 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7720 else
7721 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7722 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7723 intel_ring_emit(ring, MI_NOOP);
7724 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7725 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7726 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7727 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7728 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7729
7730 intel_mark_page_flip_active(intel_crtc);
6d90c952 7731 intel_ring_advance(ring);
83d4092b
CW		 7732 return 0;
7733
7734err_unpin:
7735 intel_unpin_fb_obj(obj);
7736err:
8c9f3aaf
JB		 7737 return ret;
7738}
7739
7740static int intel_gen3_queue_flip(struct drm_device *dev,
7741 struct drm_crtc *crtc,
7742 struct drm_framebuffer *fb,
ed8d1975
KP		 7743 struct drm_i915_gem_object *obj,
7744 uint32_t flags)
8c9f3aaf
JB		 7745{
7746 struct drm_i915_private *dev_priv = dev->dev_private;
7747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7748 u32 flip_mask;
6d90c952 7749 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7750 int ret;
7751
6d90c952 7752 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7753 if (ret)
83d4092b 7754 goto err;
8c9f3aaf 7755
6d90c952 7756 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7757 if (ret)
83d4092b 7758 goto err_unpin;
8c9f3aaf
JB		 7759
7760 if (intel_crtc->plane)
7761 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7762 else
7763 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7764 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7765 intel_ring_emit(ring, MI_NOOP);
7766 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7767 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7768 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7769 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7770 intel_ring_emit(ring, MI_NOOP);
7771
e7d841ca 7772 intel_mark_page_flip_active(intel_crtc);
6d90c952 7773 intel_ring_advance(ring);
83d4092b
CW		 7774 return 0;
7775
7776err_unpin:
7777 intel_unpin_fb_obj(obj);
7778err:
8c9f3aaf
JB		 7779 return ret;
7780}
7781
7782static int intel_gen4_queue_flip(struct drm_device *dev,
7783 struct drm_crtc *crtc,
7784 struct drm_framebuffer *fb,
ed8d1975
KP		 7785 struct drm_i915_gem_object *obj,
7786 uint32_t flags)
8c9f3aaf
JB		 7787{
7788 struct drm_i915_private *dev_priv = dev->dev_private;
7789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7790 uint32_t pf, pipesrc;
6d90c952 7791 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7792 int ret;
7793
6d90c952 7794 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7795 if (ret)
83d4092b 7796 goto err;
8c9f3aaf 7797
6d90c952 7798 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7799 if (ret)
83d4092b 7800 goto err_unpin;
8c9f3aaf
JB		 7801
7802 /* i965+ uses the linear or tiled offsets from the
7803 * Display Registers (which do not change across a page-flip)
7804 * so we need only reprogram the base address.
7805 */
6d90c952
DV		 7806 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7807 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7808 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7809 intel_ring_emit(ring,
f343c5f6 7810 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7811 obj->tiling_mode);
8c9f3aaf
JB		 7812
7813 /* XXX Enabling the panel-fitter across page-flip is so far
7814 * untested on non-native modes, so ignore it for now.
7815 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7816 */
7817 pf = 0;
7818 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7819 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7820
7821 intel_mark_page_flip_active(intel_crtc);
6d90c952 7822 intel_ring_advance(ring);
83d4092b
CW		 7823 return 0;
7824
7825err_unpin:
7826 intel_unpin_fb_obj(obj);
7827err:
8c9f3aaf
JB		 7828 return ret;
7829}
7830
7831static int intel_gen6_queue_flip(struct drm_device *dev,
7832 struct drm_crtc *crtc,
7833 struct drm_framebuffer *fb,
ed8d1975
KP		 7834 struct drm_i915_gem_object *obj,
7835 uint32_t flags)
8c9f3aaf
JB		 7836{
7837 struct drm_i915_private *dev_priv = dev->dev_private;
7838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7839 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7840 uint32_t pf, pipesrc;
7841 int ret;
7842
6d90c952 7843 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7844 if (ret)
83d4092b 7845 goto err;
8c9f3aaf 7846
6d90c952 7847 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7848 if (ret)
83d4092b 7849 goto err_unpin;
8c9f3aaf 7850
6d90c952
DV		 7851 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7852 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7853 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7854 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7855
dc257cf1
DV		 7856 /* Contrary to the suggestions in the documentation,
7857 * "Enable Panel Fitter" does not seem to be required when page
7858 * flipping with a non-native mode, and worse causes a normal
7859 * modeset to fail.
7860 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7861 */
7862 pf = 0;
8c9f3aaf 7863 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7864 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7865
7866 intel_mark_page_flip_active(intel_crtc);
6d90c952 7867 intel_ring_advance(ring);
83d4092b
CW		 7868 return 0;
7869
7870err_unpin:
7871 intel_unpin_fb_obj(obj);
7872err:
8c9f3aaf
JB		 7873 return ret;
7874}
7875
7c9017e5
JB		 7876static int intel_gen7_queue_flip(struct drm_device *dev,
7877 struct drm_crtc *crtc,
7878 struct drm_framebuffer *fb,
ed8d1975
KP		 7879 struct drm_i915_gem_object *obj,
7880 uint32_t flags)
7c9017e5
JB		 7881{
7882 struct drm_i915_private *dev_priv = dev->dev_private;
7883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7884 struct intel_ring_buffer *ring;
cb05d8de 7885 uint32_t plane_bit = 0;
ffe74d75
CW		 7886 int len, ret;
7887
7888 ring = obj->ring;
7889 if (ring == NULL || ring->id != RCS)
7890 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7891
7892 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7893 if (ret)
83d4092b 7894 goto err;
7c9017e5 7895
cb05d8de
DV		 7896 switch(intel_crtc->plane) {
7897 case PLANE_A:
7898 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7899 break;
7900 case PLANE_B:
7901 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7902 break;
7903 case PLANE_C:
7904 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7905 break;
7906 default:
7907 WARN_ONCE(1, "unknown plane in flip command\n");
7908 ret = -ENODEV;
ab3951eb 7909 goto err_unpin;
cb05d8de
DV		 7910 }
7911
ffe74d75
CW		 7912 len = 4;
7913 if (ring->id == RCS)
7914 len += 6;
7915
7916 ret = intel_ring_begin(ring, len);
7c9017e5 7917 if (ret)
83d4092b 7918 goto err_unpin;
7c9017e5 7919
ffe74d75
CW		 7920 /* Unmask the flip-done completion message. Note that the bspec says that
7921 * we should do this for both the BCS and RCS, and that we must not unmask
7922 * more than one flip event at any time (or ensure that one flip message
7923 * can be sent by waiting for flip-done prior to queueing new flips).
7924 * Experimentation says that BCS works despite DERRMR masking all
7925 * flip-done completion events and that unmasking all planes at once
7926 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7927 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7928 */
7929 if (ring->id == RCS) {
7930 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7931 intel_ring_emit(ring, DERRMR);
7932 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7933 DERRMR_PIPEB_PRI_FLIP_DONE |
7934 DERRMR_PIPEC_PRI_FLIP_DONE));
7935 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7936 intel_ring_emit(ring, DERRMR);
7937 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7938 }
7939
cb05d8de 7940 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7941 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7942 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7943 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7944
7945 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7946 intel_ring_advance(ring);
83d4092b
CW		 7947 return 0;
7948
7949err_unpin:
7950 intel_unpin_fb_obj(obj);
7951err:
7c9017e5
JB		 7952 return ret;
7953}
7954
8c9f3aaf
JB		 7955static int intel_default_queue_flip(struct drm_device *dev,
7956 struct drm_crtc *crtc,
7957 struct drm_framebuffer *fb,
ed8d1975
KP		 7958 struct drm_i915_gem_object *obj,
7959 uint32_t flags)
8c9f3aaf
JB		 7960{
7961 return -ENODEV;
7962}
7963
6b95a207
KH		 7964static int intel_crtc_page_flip(struct drm_crtc *crtc,
7965 struct drm_framebuffer *fb,
ed8d1975
KP		 7966 struct drm_pending_vblank_event *event,
7967 uint32_t page_flip_flags)
6b95a207
KH		 7968{
7969 struct drm_device *dev = crtc->dev;
7970 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7971 struct drm_framebuffer *old_fb = crtc->fb;
7972 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7974 struct intel_unpin_work *work;
8c9f3aaf 7975 unsigned long flags;
52e68630 7976 int ret;
6b95a207 7977
e6a595d2
VS		 7978 /* Can't change pixel format via MI display flips. */
7979 if (fb->pixel_format != crtc->fb->pixel_format)
7980 return -EINVAL;
7981
7982 /*
7983 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7984 * Note that pitch changes could also affect these register.
7985 */
7986 if (INTEL_INFO(dev)->gen > 3 &&
7987 (fb->offsets[0] != crtc->fb->offsets[0] ||
7988 fb->pitches[0] != crtc->fb->pitches[0]))
7989 return -EINVAL;
7990
6b95a207
KH		 7991 work = kzalloc(sizeof *work, GFP_KERNEL);
7992 if (work == NULL)
7993 return -ENOMEM;
7994
6b95a207 7995 work->event = event;
b4a98e57 7996 work->crtc = crtc;
4a35f83b 7997 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7998 INIT_WORK(&work->work, intel_unpin_work_fn);
7999
7317c75e
JB		 8000 ret = drm_vblank_get(dev, intel_crtc->pipe);
8001 if (ret)
8002 goto free_work;
8003
6b95a207
KH		 8004 /* We borrow the event spin lock for protecting unpin_work */
8005 spin_lock_irqsave(&dev->event_lock, flags);
8006 if (intel_crtc->unpin_work) {
8007 spin_unlock_irqrestore(&dev->event_lock, flags);
8008 kfree(work);
7317c75e 8009 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8010
8011 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8012 return -EBUSY;
8013 }
8014 intel_crtc->unpin_work = work;
8015 spin_unlock_irqrestore(&dev->event_lock, flags);
8016
b4a98e57
CW		 8017 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8018 flush_workqueue(dev_priv->wq);
8019
79158103
CW		 8020 ret = i915_mutex_lock_interruptible(dev);
8021 if (ret)
8022 goto cleanup;
6b95a207 8023
75dfca80 8024 /* Reference the objects for the scheduled work. */
05394f39
CW		 8025 drm_gem_object_reference(&work->old_fb_obj->base);
8026 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8027
8028 crtc->fb = fb;
96b099fd 8029
e1f99ce6 8030 work->pending_flip_obj = obj;
e1f99ce6 8031
4e5359cd
SF		 8032 work->enable_stall_check = true;
8033
b4a98e57 8034 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8035 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8036
ed8d1975 8037 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8038 if (ret)
8039 goto cleanup_pending;
6b95a207 8040
7782de3b 8041 intel_disable_fbc(dev);
c65355bb 8042 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8043 mutex_unlock(&dev->struct_mutex);
8044
e5510fac
JB		 8045 trace_i915_flip_request(intel_crtc->plane, obj);
8046
6b95a207 8047 return 0;
96b099fd 8048
8c9f3aaf 8049cleanup_pending:
b4a98e57 8050 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8051 crtc->fb = old_fb;
05394f39
CW		 8052 drm_gem_object_unreference(&work->old_fb_obj->base);
8053 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8054 mutex_unlock(&dev->struct_mutex);
8055
79158103 8056cleanup:
96b099fd
CW		 8057 spin_lock_irqsave(&dev->event_lock, flags);
8058 intel_crtc->unpin_work = NULL;
8059 spin_unlock_irqrestore(&dev->event_lock, flags);
8060
7317c75e
JB		 8061 drm_vblank_put(dev, intel_crtc->pipe);
8062free_work:
96b099fd
CW		 8063 kfree(work);
8064
8065 return ret;
6b95a207
KH		 8066}
8067
f6e5b160 8068static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8069 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8070 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8071};
8072
50f56119
DV		 8073static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8074 struct drm_crtc *crtc)
8075{
8076 struct drm_device *dev;
8077 struct drm_crtc *tmp;
8078 int crtc_mask = 1;
47f1c6c9 8079
50f56119 8080 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8081
50f56119 8082 dev = crtc->dev;
47f1c6c9 8083
50f56119
DV		 8084 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8085 if (tmp == crtc)
8086 break;
8087 crtc_mask <<= 1;
8088 }
47f1c6c9 8089
50f56119
DV		 8090 if (encoder->possible_crtcs & crtc_mask)
8091 return true;
8092 return false;
47f1c6c9 8093}
79e53945 8094
9a935856
DV		 8095/**
8096 * intel_modeset_update_staged_output_state
8097 *
8098 * Updates the staged output configuration state, e.g. after we've read out the
8099 * current hw state.
8100 */
8101static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8102{
9a935856
DV		 8103 struct intel_encoder *encoder;
8104 struct intel_connector *connector;
f6e5b160 8105
9a935856
DV		 8106 list_for_each_entry(connector, &dev->mode_config.connector_list,
8107 base.head) {
8108 connector->new_encoder =
8109 to_intel_encoder(connector->base.encoder);
8110 }
f6e5b160 8111
9a935856
DV		 8112 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8113 base.head) {
8114 encoder->new_crtc =
8115 to_intel_crtc(encoder->base.crtc);
8116 }
f6e5b160
CW		 8117}
8118
9a935856
DV		 8119/**
8120 * intel_modeset_commit_output_state
8121 *
8122 * This function copies the stage display pipe configuration to the real one.
8123 */
8124static void intel_modeset_commit_output_state(struct drm_device *dev)
8125{
8126 struct intel_encoder *encoder;
8127 struct intel_connector *connector;
f6e5b160 8128
9a935856
DV		 8129 list_for_each_entry(connector, &dev->mode_config.connector_list,
8130 base.head) {
8131 connector->base.encoder = &connector->new_encoder->base;
8132 }
f6e5b160 8133
9a935856
DV		 8134 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8135 base.head) {
8136 encoder->base.crtc = &encoder->new_crtc->base;
8137 }
8138}
8139
050f7aeb
DV		 8140static void
8141connected_sink_compute_bpp(struct intel_connector * connector,
8142 struct intel_crtc_config *pipe_config)
8143{
8144 int bpp = pipe_config->pipe_bpp;
8145
8146 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8147 connector->base.base.id,
8148 drm_get_connector_name(&connector->base));
8149
8150 /* Don't use an invalid EDID bpc value */
8151 if (connector->base.display_info.bpc &&
8152 connector->base.display_info.bpc * 3 < bpp) {
8153 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8154 bpp, connector->base.display_info.bpc*3);
8155 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8156 }
8157
8158 /* Clamp bpp to 8 on screens without EDID 1.4 */
8159 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8160 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8161 bpp);
8162 pipe_config->pipe_bpp = 24;
8163 }
8164}
8165
4e53c2e0 8166static int
050f7aeb
DV		 8167compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8168 struct drm_framebuffer *fb,
8169 struct intel_crtc_config *pipe_config)
4e53c2e0 8170{
050f7aeb
DV		 8171 struct drm_device *dev = crtc->base.dev;
8172 struct intel_connector *connector;
4e53c2e0
DV		 8173 int bpp;
8174
d42264b1
DV		 8175 switch (fb->pixel_format) {
8176 case DRM_FORMAT_C8:
4e53c2e0
DV		 8177 bpp = 8*3; /* since we go through a colormap */
8178 break;
d42264b1
DV		 8179 case DRM_FORMAT_XRGB1555:
8180 case DRM_FORMAT_ARGB1555:
8181 /* checked in intel_framebuffer_init already */
8182 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8183 return -EINVAL;
8184 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8185 bpp = 6*3; /* min is 18bpp */
8186 break;
d42264b1
DV		 8187 case DRM_FORMAT_XBGR8888:
8188 case DRM_FORMAT_ABGR8888:
8189 /* checked in intel_framebuffer_init already */
8190 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8191 return -EINVAL;
8192 case DRM_FORMAT_XRGB8888:
8193 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8194 bpp = 8*3;
8195 break;
d42264b1
DV		 8196 case DRM_FORMAT_XRGB2101010:
8197 case DRM_FORMAT_ARGB2101010:
8198 case DRM_FORMAT_XBGR2101010:
8199 case DRM_FORMAT_ABGR2101010:
8200 /* checked in intel_framebuffer_init already */
8201 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8202 return -EINVAL;
4e53c2e0
DV		 8203 bpp = 10*3;
8204 break;
baba133a 8205 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8206 default:
8207 DRM_DEBUG_KMS("unsupported depth\n");
8208 return -EINVAL;
8209 }
8210
4e53c2e0
DV		 8211 pipe_config->pipe_bpp = bpp;
8212
8213 /* Clamp display bpp to EDID value */
8214 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8215 base.head) {
1b829e05
DV		 8216 if (!connector->new_encoder ||
8217 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8218 continue;
8219
050f7aeb 8220 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8221 }
8222
8223 return bpp;
8224}
8225
c0b03411
DV		 8226static void intel_dump_pipe_config(struct intel_crtc *crtc,
8227 struct intel_crtc_config *pipe_config,
8228 const char *context)
8229{
8230 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8231 context, pipe_name(crtc->pipe));
8232
8233 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8234 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8235 pipe_config->pipe_bpp, pipe_config->dither);
8236 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8237 pipe_config->has_pch_encoder,
8238 pipe_config->fdi_lanes,
8239 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8240 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8241 pipe_config->fdi_m_n.tu);
8242 DRM_DEBUG_KMS("requested mode:\n");
8243 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8244 DRM_DEBUG_KMS("adjusted mode:\n");
8245 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8246 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8247 pipe_config->gmch_pfit.control,
8248 pipe_config->gmch_pfit.pgm_ratios,
8249 pipe_config->gmch_pfit.lvds_border_bits);
8250 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8251 pipe_config->pch_pfit.pos,
8252 pipe_config->pch_pfit.size);
42db64ef 8253 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8254}
8255
accfc0c5
DV		 8256static bool check_encoder_cloning(struct drm_crtc *crtc)
8257{
8258 int num_encoders = 0;
8259 bool uncloneable_encoders = false;
8260 struct intel_encoder *encoder;
8261
8262 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8263 base.head) {
8264 if (&encoder->new_crtc->base != crtc)
8265 continue;
8266
8267 num_encoders++;
8268 if (!encoder->cloneable)
8269 uncloneable_encoders = true;
8270 }
8271
8272 return !(num_encoders > 1 && uncloneable_encoders);
8273}
8274
b8cecdf5
DV		 8275static struct intel_crtc_config *
8276intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8277 struct drm_framebuffer *fb,
b8cecdf5 8278 struct drm_display_mode *mode)
ee7b9f93 8279{
7758a113 8280 struct drm_device *dev = crtc->dev;
7758a113 8281 struct intel_encoder *encoder;
b8cecdf5 8282 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8283 int plane_bpp, ret = -EINVAL;
8284 bool retry = true;
ee7b9f93 8285
accfc0c5
DV		 8286 if (!check_encoder_cloning(crtc)) {
8287 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8288 return ERR_PTR(-EINVAL);
8289 }
8290
b8cecdf5
DV		 8291 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8292 if (!pipe_config)
7758a113
DV		 8293 return ERR_PTR(-ENOMEM);
8294
b8cecdf5
DV		 8295 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8296 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8297 pipe_config->cpu_transcoder =
8298 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8299 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8300
2960bc9c
ID		 8301 /*
8302 * Sanitize sync polarity flags based on requested ones. If neither
8303 * positive or negative polarity is requested, treat this as meaning
8304 * negative polarity.
8305 */
8306 if (!(pipe_config->adjusted_mode.flags &
8307 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8308 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8309
8310 if (!(pipe_config->adjusted_mode.flags &
8311 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8312 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8313
050f7aeb
DV		 8314 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8315 * plane pixel format and any sink constraints into account. Returns the
8316 * source plane bpp so that dithering can be selected on mismatches
8317 * after encoders and crtc also have had their say. */
8318 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8319 fb, pipe_config);
4e53c2e0
DV		 8320 if (plane_bpp < 0)
8321 goto fail;
8322
e29c22c0 8323encoder_retry:
ef1b460d 8324 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8325 pipe_config->port_clock = 0;
ef1b460d 8326 pipe_config->pixel_multiplier = 1;
ff9a6750 8327
135c81b8
DV		 8328 /* Fill in default crtc timings, allow encoders to overwrite them. */
8329 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8330
7758a113
DV		 8331 /* Pass our mode to the connectors and the CRTC to give them a chance to
8332 * adjust it according to limitations or connector properties, and also
8333 * a chance to reject the mode entirely.
47f1c6c9 8334 */
7758a113
DV		 8335 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8336 base.head) {
47f1c6c9 8337
7758a113
DV		 8338 if (&encoder->new_crtc->base != crtc)
8339 continue;
7ae89233 8340
efea6e8e
DV		 8341 if (!(encoder->compute_config(encoder, pipe_config))) {
8342 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8343 goto fail;
8344 }
ee7b9f93 8345 }
47f1c6c9 8346
ff9a6750
DV		 8347 /* Set default port clock if not overwritten by the encoder. Needs to be
8348 * done afterwards in case the encoder adjusts the mode. */
8349 if (!pipe_config->port_clock)
8350 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8351
a43f6e0f 8352 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8353 if (ret < 0) {
7758a113
DV		 8354 DRM_DEBUG_KMS("CRTC fixup failed\n");
8355 goto fail;
ee7b9f93 8356 }
e29c22c0
DV		 8357
8358 if (ret == RETRY) {
8359 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8360 ret = -EINVAL;
8361 goto fail;
8362 }
8363
8364 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8365 retry = false;
8366 goto encoder_retry;
8367 }
8368
4e53c2e0
DV		 8369 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8370 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8371 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8372
b8cecdf5 8373 return pipe_config;
7758a113 8374fail:
b8cecdf5 8375 kfree(pipe_config);
e29c22c0 8376 return ERR_PTR(ret);
ee7b9f93 8377}
47f1c6c9 8378
e2e1ed41
DV		 8379/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8380 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8381static void
8382intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8383 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8384{
8385 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8386 struct drm_device *dev = crtc->dev;
8387 struct intel_encoder *encoder;
8388 struct intel_connector *connector;
8389 struct drm_crtc *tmp_crtc;
79e53945 8390
e2e1ed41 8391 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8392
e2e1ed41
DV		 8393 /* Check which crtcs have changed outputs connected to them, these need
8394 * to be part of the prepare_pipes mask. We don't (yet) support global
8395 * modeset across multiple crtcs, so modeset_pipes will only have one
8396 * bit set at most. */
8397 list_for_each_entry(connector, &dev->mode_config.connector_list,
8398 base.head) {
8399 if (connector->base.encoder == &connector->new_encoder->base)
8400 continue;
79e53945 8401
e2e1ed41
DV		 8402 if (connector->base.encoder) {
8403 tmp_crtc = connector->base.encoder->crtc;
8404
8405 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8406 }
8407
8408 if (connector->new_encoder)
8409 *prepare_pipes |=
8410 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8411 }
8412
e2e1ed41
DV		 8413 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8414 base.head) {
8415 if (encoder->base.crtc == &encoder->new_crtc->base)
8416 continue;
8417
8418 if (encoder->base.crtc) {
8419 tmp_crtc = encoder->base.crtc;
8420
8421 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8422 }
8423
8424 if (encoder->new_crtc)
8425 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8426 }
8427
e2e1ed41
DV		 8428 /* Check for any pipes that will be fully disabled ... */
8429 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8430 base.head) {
8431 bool used = false;
22fd0fab 8432
e2e1ed41
DV		 8433 /* Don't try to disable disabled crtcs. */
8434 if (!intel_crtc->base.enabled)
8435 continue;
7e7d76c3 8436
e2e1ed41
DV		 8437 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8438 base.head) {
8439 if (encoder->new_crtc == intel_crtc)
8440 used = true;
8441 }
8442
8443 if (!used)
8444 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8445 }
8446
e2e1ed41
DV		 8447
8448 /* set_mode is also used to update properties on life display pipes. */
8449 intel_crtc = to_intel_crtc(crtc);
8450 if (crtc->enabled)
8451 *prepare_pipes |= 1 << intel_crtc->pipe;
8452
b6c5164d
DV		 8453 /*
8454 * For simplicity do a full modeset on any pipe where the output routing
8455 * changed. We could be more clever, but that would require us to be
8456 * more careful with calling the relevant encoder->mode_set functions.
8457 */
e2e1ed41
DV		 8458 if (*prepare_pipes)
8459 *modeset_pipes = *prepare_pipes;
8460
8461 /* ... and mask these out. */
8462 *modeset_pipes &= ~(*disable_pipes);
8463 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8464
8465 /*
8466 * HACK: We don't (yet) fully support global modesets. intel_set_config
8467 * obies this rule, but the modeset restore mode of
8468 * intel_modeset_setup_hw_state does not.
8469 */
8470 *modeset_pipes &= 1 << intel_crtc->pipe;
8471 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8472
8473 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8474 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8475}
79e53945 8476
ea9d758d 8477static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8478{
ea9d758d 8479 struct drm_encoder *encoder;
f6e5b160 8480 struct drm_device *dev = crtc->dev;
f6e5b160 8481
ea9d758d
DV		 8482 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8483 if (encoder->crtc == crtc)
8484 return true;
8485
8486 return false;
8487}
8488
8489static void
8490intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8491{
8492 struct intel_encoder *intel_encoder;
8493 struct intel_crtc *intel_crtc;
8494 struct drm_connector *connector;
8495
8496 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8497 base.head) {
8498 if (!intel_encoder->base.crtc)
8499 continue;
8500
8501 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8502
8503 if (prepare_pipes & (1 << intel_crtc->pipe))
8504 intel_encoder->connectors_active = false;
8505 }
8506
8507 intel_modeset_commit_output_state(dev);
8508
8509 /* Update computed state. */
8510 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8511 base.head) {
8512 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8513 }
8514
8515 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8516 if (!connector->encoder || !connector->encoder->crtc)
8517 continue;
8518
8519 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8520
8521 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8522 struct drm_property *dpms_property =
8523 dev->mode_config.dpms_property;
8524
ea9d758d 8525 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8526 drm_object_property_set_value(&connector->base,
68d34720
DV		 8527 dpms_property,
8528 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8529
8530 intel_encoder = to_intel_encoder(connector->encoder);
8531 intel_encoder->connectors_active = true;
8532 }
8533 }
8534
8535}
8536
f1f644dc
JB		 8537static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8538 struct intel_crtc_config *new)
8539{
8540 int clock1, clock2, diff;
8541
8542 clock1 = cur->adjusted_mode.clock;
8543 clock2 = new->adjusted_mode.clock;
8544
8545 if (clock1 == clock2)
8546 return true;
8547
8548 if (!clock1 || !clock2)
8549 return false;
8550
8551 diff = abs(clock1 - clock2);
8552
8553 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8554 return true;
8555
8556 return false;
8557}
8558
25c5b266
DV		 8559#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8560 list_for_each_entry((intel_crtc), \
8561 &(dev)->mode_config.crtc_list, \
8562 base.head) \
0973f18f 8563 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8564
0e8ffe1b 8565static bool
2fa2fe9a
DV		 8566intel_pipe_config_compare(struct drm_device *dev,
8567 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8568 struct intel_crtc_config *pipe_config)
8569{
66e985c0
DV		 8570#define PIPE_CONF_CHECK_X(name) \
8571 if (current_config->name != pipe_config->name) { \
8572 DRM_ERROR("mismatch in " #name " " \
8573 "(expected 0x%08x, found 0x%08x)\n", \
8574 current_config->name, \
8575 pipe_config->name); \
8576 return false; \
8577 }
8578
08a24034
DV		 8579#define PIPE_CONF_CHECK_I(name) \
8580 if (current_config->name != pipe_config->name) { \
8581 DRM_ERROR("mismatch in " #name " " \
8582 "(expected %i, found %i)\n", \
8583 current_config->name, \
8584 pipe_config->name); \
8585 return false; \
88adfff1
DV		 8586 }
8587
1bd1bd80
DV		 8588#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8589 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8590 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8591 "(expected %i, found %i)\n", \
8592 current_config->name & (mask), \
8593 pipe_config->name & (mask)); \
8594 return false; \
8595 }
8596
bb760063
DV		 8597#define PIPE_CONF_QUIRK(quirk) \
8598 ((current_config->quirks | pipe_config->quirks) & (quirk))
8599
eccb140b
DV		 8600 PIPE_CONF_CHECK_I(cpu_transcoder);
8601
08a24034
DV		 8602 PIPE_CONF_CHECK_I(has_pch_encoder);
8603 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8604 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8605 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8606 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8607 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8608 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8609
1bd1bd80
DV		 8610 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8611 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8612 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8613 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8614 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8615 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8616
8617 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8618 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8619 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8620 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8621 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8622 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8623
c93f54cf 8624 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8625
1bd1bd80
DV		 8626 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8627 DRM_MODE_FLAG_INTERLACE);
8628
bb760063
DV		 8629 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8630 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8631 DRM_MODE_FLAG_PHSYNC);
8632 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8633 DRM_MODE_FLAG_NHSYNC);
8634 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8635 DRM_MODE_FLAG_PVSYNC);
8636 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8637 DRM_MODE_FLAG_NVSYNC);
8638 }
045ac3b5 8639
1bd1bd80
DV		 8640 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8641 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8642
2fa2fe9a
DV		 8643 PIPE_CONF_CHECK_I(gmch_pfit.control);
8644 /* pfit ratios are autocomputed by the hw on gen4+ */
8645 if (INTEL_INFO(dev)->gen < 4)
8646 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8647 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8648 PIPE_CONF_CHECK_I(pch_pfit.pos);
8649 PIPE_CONF_CHECK_I(pch_pfit.size);
8650
42db64ef
PZ		 8651 PIPE_CONF_CHECK_I(ips_enabled);
8652
c0d43d62 8653 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8654 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8655 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8656 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8657 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8658
66e985c0 8659#undef PIPE_CONF_CHECK_X
08a24034 8660#undef PIPE_CONF_CHECK_I
1bd1bd80 8661#undef PIPE_CONF_CHECK_FLAGS
bb760063 8662#undef PIPE_CONF_QUIRK
88adfff1 8663
f1f644dc
JB		 8664 if (!IS_HASWELL(dev)) {
8665 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8666 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8667 current_config->adjusted_mode.clock,
8668 pipe_config->adjusted_mode.clock);
8669 return false;
8670 }
8671 }
8672
0e8ffe1b
DV		 8673 return true;
8674}
8675
91d1b4bd
DV		 8676static void
8677check_connector_state(struct drm_device *dev)
8af6cf88 8678{
8af6cf88
DV		 8679 struct intel_connector *connector;
8680
8681 list_for_each_entry(connector, &dev->mode_config.connector_list,
8682 base.head) {
8683 /* This also checks the encoder/connector hw state with the
8684 * ->get_hw_state callbacks. */
8685 intel_connector_check_state(connector);
8686
8687 WARN(&connector->new_encoder->base != connector->base.encoder,
8688 "connector's staged encoder doesn't match current encoder\n");
8689 }
91d1b4bd
DV		 8690}
8691
8692static void
8693check_encoder_state(struct drm_device *dev)
8694{
8695 struct intel_encoder *encoder;
8696 struct intel_connector *connector;
8af6cf88
DV		 8697
8698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8699 base.head) {
8700 bool enabled = false;
8701 bool active = false;
8702 enum pipe pipe, tracked_pipe;
8703
8704 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8705 encoder->base.base.id,
8706 drm_get_encoder_name(&encoder->base));
8707
8708 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8709 "encoder's stage crtc doesn't match current crtc\n");
8710 WARN(encoder->connectors_active && !encoder->base.crtc,
8711 "encoder's active_connectors set, but no crtc\n");
8712
8713 list_for_each_entry(connector, &dev->mode_config.connector_list,
8714 base.head) {
8715 if (connector->base.encoder != &encoder->base)
8716 continue;
8717 enabled = true;
8718 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8719 active = true;
8720 }
8721 WARN(!!encoder->base.crtc != enabled,
8722 "encoder's enabled state mismatch "
8723 "(expected %i, found %i)\n",
8724 !!encoder->base.crtc, enabled);
8725 WARN(active && !encoder->base.crtc,
8726 "active encoder with no crtc\n");
8727
8728 WARN(encoder->connectors_active != active,
8729 "encoder's computed active state doesn't match tracked active state "
8730 "(expected %i, found %i)\n", active, encoder->connectors_active);
8731
8732 active = encoder->get_hw_state(encoder, &pipe);
8733 WARN(active != encoder->connectors_active,
8734 "encoder's hw state doesn't match sw tracking "
8735 "(expected %i, found %i)\n",
8736 encoder->connectors_active, active);
8737
8738 if (!encoder->base.crtc)
8739 continue;
8740
8741 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8742 WARN(active && pipe != tracked_pipe,
8743 "active encoder's pipe doesn't match"
8744 "(expected %i, found %i)\n",
8745 tracked_pipe, pipe);
8746
8747 }
91d1b4bd
DV		 8748}
8749
8750static void
8751check_crtc_state(struct drm_device *dev)
8752{
8753 drm_i915_private_t *dev_priv = dev->dev_private;
8754 struct intel_crtc *crtc;
8755 struct intel_encoder *encoder;
8756 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8757
8758 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8759 base.head) {
8760 bool enabled = false;
8761 bool active = false;
8762
045ac3b5
JB		 8763 memset(&pipe_config, 0, sizeof(pipe_config));
8764
8af6cf88
DV		 8765 DRM_DEBUG_KMS("[CRTC:%d]\n",
8766 crtc->base.base.id);
8767
8768 WARN(crtc->active && !crtc->base.enabled,
8769 "active crtc, but not enabled in sw tracking\n");
8770
8771 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8772 base.head) {
8773 if (encoder->base.crtc != &crtc->base)
8774 continue;
8775 enabled = true;
8776 if (encoder->connectors_active)
8777 active = true;
8778 }
6c49f241 8779
8af6cf88
DV		 8780 WARN(active != crtc->active,
8781 "crtc's computed active state doesn't match tracked active state "
8782 "(expected %i, found %i)\n", active, crtc->active);
8783 WARN(enabled != crtc->base.enabled,
8784 "crtc's computed enabled state doesn't match tracked enabled state "
8785 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8786
0e8ffe1b
DV		 8787 active = dev_priv->display.get_pipe_config(crtc,
8788 &pipe_config);
d62cf62a
DV		 8789
8790 /* hw state is inconsistent with the pipe A quirk */
8791 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8792 active = crtc->active;
8793
6c49f241
DV		 8794 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8795 base.head) {
3eaba51c 8796 enum pipe pipe;
6c49f241
DV		 8797 if (encoder->base.crtc != &crtc->base)
8798 continue;
3eaba51c
VS		 8799 if (encoder->get_config &&
8800 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8801 encoder->get_config(encoder, &pipe_config);
8802 }
8803
510d5f2f
JB		 8804 if (dev_priv->display.get_clock)
8805 dev_priv->display.get_clock(crtc, &pipe_config);
8806
0e8ffe1b
DV		 8807 WARN(crtc->active != active,
8808 "crtc active state doesn't match with hw state "
8809 "(expected %i, found %i)\n", crtc->active, active);
8810
c0b03411
DV		 8811 if (active &&
8812 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8813 WARN(1, "pipe state doesn't match!\n");
8814 intel_dump_pipe_config(crtc, &pipe_config,
8815 "[hw state]");
8816 intel_dump_pipe_config(crtc, &crtc->config,
8817 "[sw state]");
8818 }
8af6cf88
DV		 8819 }
8820}
8821
91d1b4bd
DV		 8822static void
8823check_shared_dpll_state(struct drm_device *dev)
8824{
8825 drm_i915_private_t *dev_priv = dev->dev_private;
8826 struct intel_crtc *crtc;
8827 struct intel_dpll_hw_state dpll_hw_state;
8828 int i;
5358901f
DV		 8829
8830 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8831 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8832 int enabled_crtcs = 0, active_crtcs = 0;
8833 bool active;
8834
8835 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8836
8837 DRM_DEBUG_KMS("%s\n", pll->name);
8838
8839 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8840
8841 WARN(pll->active > pll->refcount,
8842 "more active pll users than references: %i vs %i\n",
8843 pll->active, pll->refcount);
8844 WARN(pll->active && !pll->on,
8845 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8846 WARN(pll->on && !pll->active,
8847 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8848 WARN(pll->on != active,
8849 "pll on state mismatch (expected %i, found %i)\n",
8850 pll->on, active);
8851
8852 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8853 base.head) {
8854 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8855 enabled_crtcs++;
8856 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8857 active_crtcs++;
8858 }
8859 WARN(pll->active != active_crtcs,
8860 "pll active crtcs mismatch (expected %i, found %i)\n",
8861 pll->active, active_crtcs);
8862 WARN(pll->refcount != enabled_crtcs,
8863 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8864 pll->refcount, enabled_crtcs);
66e985c0
DV		 8865
8866 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8867 sizeof(dpll_hw_state)),
8868 "pll hw state mismatch\n");
5358901f 8869 }
8af6cf88
DV		 8870}
8871
91d1b4bd
DV		 8872void
8873intel_modeset_check_state(struct drm_device *dev)
8874{
8875 check_connector_state(dev);
8876 check_encoder_state(dev);
8877 check_crtc_state(dev);
8878 check_shared_dpll_state(dev);
8879}
8880
f30da187
DV		 8881static int __intel_set_mode(struct drm_crtc *crtc,
8882 struct drm_display_mode *mode,
8883 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8884{
8885 struct drm_device *dev = crtc->dev;
dbf2b54e 8886 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8887 struct drm_display_mode *saved_mode, *saved_hwmode;
8888 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8889 struct intel_crtc *intel_crtc;
8890 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8891 int ret = 0;
a6778b3c 8892
3ac18232 8893 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8894 if (!saved_mode)
8895 return -ENOMEM;
3ac18232 8896 saved_hwmode = saved_mode + 1;
a6778b3c 8897
e2e1ed41 8898 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8899 &prepare_pipes, &disable_pipes);
8900
3ac18232
TG		 8901 *saved_hwmode = crtc->hwmode;
8902 *saved_mode = crtc->mode;
a6778b3c 8903
25c5b266
DV		 8904 /* Hack: Because we don't (yet) support global modeset on multiple
8905 * crtcs, we don't keep track of the new mode for more than one crtc.
8906 * Hence simply check whether any bit is set in modeset_pipes in all the
8907 * pieces of code that are not yet converted to deal with mutliple crtcs
8908 * changing their mode at the same time. */
25c5b266 8909 if (modeset_pipes) {
4e53c2e0 8910 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8911 if (IS_ERR(pipe_config)) {
8912 ret = PTR_ERR(pipe_config);
8913 pipe_config = NULL;
8914
3ac18232 8915 goto out;
25c5b266 8916 }
c0b03411
DV		 8917 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8918 "[modeset]");
25c5b266 8919 }
a6778b3c 8920
460da916
DV		 8921 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8922 intel_crtc_disable(&intel_crtc->base);
8923
ea9d758d
DV		 8924 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8925 if (intel_crtc->base.enabled)
8926 dev_priv->display.crtc_disable(&intel_crtc->base);
8927 }
a6778b3c 8928
6c4c86f5
DV		 8929 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8930 * to set it here already despite that we pass it down the callchain.
f6e5b160 8931 */
b8cecdf5 8932 if (modeset_pipes) {
25c5b266 8933 crtc->mode = *mode;
b8cecdf5
DV		 8934 /* mode_set/enable/disable functions rely on a correct pipe
8935 * config. */
8936 to_intel_crtc(crtc)->config = *pipe_config;
8937 }
7758a113 8938
ea9d758d
DV		 8939 /* Only after disabling all output pipelines that will be changed can we
8940 * update the the output configuration. */
8941 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8942
47fab737
DV		 8943 if (dev_priv->display.modeset_global_resources)
8944 dev_priv->display.modeset_global_resources(dev);
8945
a6778b3c
DV		 8946 /* Set up the DPLL and any encoders state that needs to adjust or depend
8947 * on the DPLL.
f6e5b160 8948 */
25c5b266 8949 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8950 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8951 x, y, fb);
8952 if (ret)
8953 goto done;
a6778b3c
DV		 8954 }
8955
8956 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8957 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8958 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8959
25c5b266
DV		 8960 if (modeset_pipes) {
8961 /* Store real post-adjustment hardware mode. */
b8cecdf5 8962 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8963
25c5b266
DV		 8964 /* Calculate and store various constants which
8965 * are later needed by vblank and swap-completion
8966 * timestamping. They are derived from true hwmode.
8967 */
8968 drm_calc_timestamping_constants(crtc);
8969 }
a6778b3c
DV		 8970
8971 /* FIXME: add subpixel order */
8972done:
c0c36b94 8973 if (ret && crtc->enabled) {
3ac18232
TG		 8974 crtc->hwmode = *saved_hwmode;
8975 crtc->mode = *saved_mode;
a6778b3c
DV		 8976 }
8977
3ac18232 8978out:
b8cecdf5 8979 kfree(pipe_config);
3ac18232 8980 kfree(saved_mode);
a6778b3c 8981 return ret;
f6e5b160
CW		 8982}
8983
e7457a9a
DL		 8984static int intel_set_mode(struct drm_crtc *crtc,
8985 struct drm_display_mode *mode,
8986 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 8987{
8988 int ret;
8989
8990 ret = __intel_set_mode(crtc, mode, x, y, fb);
8991
8992 if (ret == 0)
8993 intel_modeset_check_state(crtc->dev);
8994
8995 return ret;
8996}
8997
c0c36b94
CW		 8998void intel_crtc_restore_mode(struct drm_crtc *crtc)
8999{
9000 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9001}
9002
25c5b266
DV		 9003#undef for_each_intel_crtc_masked
9004
d9e55608
DV		 9005static void intel_set_config_free(struct intel_set_config *config)
9006{
9007 if (!config)
9008 return;
9009
1aa4b628
DV		 9010 kfree(config->save_connector_encoders);
9011 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9012 kfree(config);
9013}
9014
85f9eb71
DV		 9015static int intel_set_config_save_state(struct drm_device *dev,
9016 struct intel_set_config *config)
9017{
85f9eb71
DV		 9018 struct drm_encoder *encoder;
9019 struct drm_connector *connector;
9020 int count;
9021
1aa4b628
DV		 9022 config->save_encoder_crtcs =
9023 kcalloc(dev->mode_config.num_encoder,
9024 sizeof(struct drm_crtc *), GFP_KERNEL);
9025 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9026 return -ENOMEM;
9027
1aa4b628
DV		 9028 config->save_connector_encoders =
9029 kcalloc(dev->mode_config.num_connector,
9030 sizeof(struct drm_encoder *), GFP_KERNEL);
9031 if (!config->save_connector_encoders)
85f9eb71
DV		 9032 return -ENOMEM;
9033
9034 /* Copy data. Note that driver private data is not affected.
9035 * Should anything bad happen only the expected state is
9036 * restored, not the drivers personal bookkeeping.
9037 */
85f9eb71
DV		 9038 count = 0;
9039 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9040 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9041 }
9042
9043 count = 0;
9044 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9045 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9046 }
9047
9048 return 0;
9049}
9050
9051static void intel_set_config_restore_state(struct drm_device *dev,
9052 struct intel_set_config *config)
9053{
9a935856
DV		 9054 struct intel_encoder *encoder;
9055 struct intel_connector *connector;
85f9eb71
DV		 9056 int count;
9057
85f9eb71 9058 count = 0;
9a935856
DV		 9059 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9060 encoder->new_crtc =
9061 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9062 }
9063
9064 count = 0;
9a935856
DV		 9065 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9066 connector->new_encoder =
9067 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9068 }
9069}
9070
e3de42b6 9071static bool
2e57f47d 9072is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9073{
9074 int i;
9075
2e57f47d
CW		 9076 if (set->num_connectors == 0)
9077 return false;
9078
9079 if (WARN_ON(set->connectors == NULL))
9080 return false;
9081
9082 for (i = 0; i < set->num_connectors; i++)
9083 if (set->connectors[i]->encoder &&
9084 set->connectors[i]->encoder->crtc == set->crtc &&
9085 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9086 return true;
9087
9088 return false;
9089}
9090
5e2b584e
DV		 9091static void
9092intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9093 struct intel_set_config *config)
9094{
9095
9096 /* We should be able to check here if the fb has the same properties
9097 * and then just flip_or_move it */
2e57f47d
CW		 9098 if (is_crtc_connector_off(set)) {
9099 config->mode_changed = true;
e3de42b6 9100 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9101 /* If we have no fb then treat it as a full mode set */
9102 if (set->crtc->fb == NULL) {
319d9827
JB		 9103 struct intel_crtc *intel_crtc =
9104 to_intel_crtc(set->crtc);
9105
9106 if (intel_crtc->active && i915_fastboot) {
9107 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9108 config->fb_changed = true;
9109 } else {
9110 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9111 config->mode_changed = true;
9112 }
5e2b584e
DV		 9113 } else if (set->fb == NULL) {
9114 config->mode_changed = true;
72f4901e
DV		 9115 } else if (set->fb->pixel_format !=
9116 set->crtc->fb->pixel_format) {
5e2b584e 9117 config->mode_changed = true;
e3de42b6 9118 } else {
5e2b584e 9119 config->fb_changed = true;
e3de42b6 9120 }
5e2b584e
DV		 9121 }
9122
835c5873 9123 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9124 config->fb_changed = true;
9125
9126 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9127 DRM_DEBUG_KMS("modes are different, full mode set\n");
9128 drm_mode_debug_printmodeline(&set->crtc->mode);
9129 drm_mode_debug_printmodeline(set->mode);
9130 config->mode_changed = true;
9131 }
a1d95703
CW		 9132
9133 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9134 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9135}
9136
2e431051 9137static int
9a935856
DV		 9138intel_modeset_stage_output_state(struct drm_device *dev,
9139 struct drm_mode_set *set,
9140 struct intel_set_config *config)
50f56119 9141{
85f9eb71 9142 struct drm_crtc *new_crtc;
9a935856
DV		 9143 struct intel_connector *connector;
9144 struct intel_encoder *encoder;
f3f08572 9145 int ro;
50f56119 9146
9abdda74 9147 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9148 * of connectors. For paranoia, double-check this. */
9149 WARN_ON(!set->fb && (set->num_connectors != 0));
9150 WARN_ON(set->fb && (set->num_connectors == 0));
9151
9a935856
DV		 9152 list_for_each_entry(connector, &dev->mode_config.connector_list,
9153 base.head) {
9154 /* Otherwise traverse passed in connector list and get encoders
9155 * for them. */
50f56119 9156 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9157 if (set->connectors[ro] == &connector->base) {
9158 connector->new_encoder = connector->encoder;
50f56119
DV		 9159 break;
9160 }
9161 }
9162
9a935856
DV		 9163 /* If we disable the crtc, disable all its connectors. Also, if
9164 * the connector is on the changing crtc but not on the new
9165 * connector list, disable it. */
9166 if ((!set->fb || ro == set->num_connectors) &&
9167 connector->base.encoder &&
9168 connector->base.encoder->crtc == set->crtc) {
9169 connector->new_encoder = NULL;
9170
9171 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9172 connector->base.base.id,
9173 drm_get_connector_name(&connector->base));
9174 }
9175
9176
9177 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9178 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9179 config->mode_changed = true;
50f56119
DV		 9180 }
9181 }
9a935856 9182 /* connector->new_encoder is now updated for all connectors. */
50f56119 9183
9a935856 9184 /* Update crtc of enabled connectors. */
9a935856
DV		 9185 list_for_each_entry(connector, &dev->mode_config.connector_list,
9186 base.head) {
9187 if (!connector->new_encoder)
50f56119
DV		 9188 continue;
9189
9a935856 9190 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9191
9192 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9193 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9194 new_crtc = set->crtc;
9195 }
9196
9197 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9198 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9199 new_crtc)) {
5e2b584e 9200 return -EINVAL;
50f56119 9201 }
9a935856
DV		 9202 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9203
9204 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9205 connector->base.base.id,
9206 drm_get_connector_name(&connector->base),
9207 new_crtc->base.id);
9208 }
9209
9210 /* Check for any encoders that needs to be disabled. */
9211 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9212 base.head) {
9213 list_for_each_entry(connector,
9214 &dev->mode_config.connector_list,
9215 base.head) {
9216 if (connector->new_encoder == encoder) {
9217 WARN_ON(!connector->new_encoder->new_crtc);
9218
9219 goto next_encoder;
9220 }
9221 }
9222 encoder->new_crtc = NULL;
9223next_encoder:
9224 /* Only now check for crtc changes so we don't miss encoders
9225 * that will be disabled. */
9226 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9227 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9228 config->mode_changed = true;
50f56119
DV		 9229 }
9230 }
9a935856 9231 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9232
2e431051
DV		 9233 return 0;
9234}
9235
9236static int intel_crtc_set_config(struct drm_mode_set *set)
9237{
9238 struct drm_device *dev;
2e431051
DV		 9239 struct drm_mode_set save_set;
9240 struct intel_set_config *config;
9241 int ret;
2e431051 9242
8d3e375e
DV		 9243 BUG_ON(!set);
9244 BUG_ON(!set->crtc);
9245 BUG_ON(!set->crtc->helper_private);
2e431051 9246
7e53f3a4
DV		 9247 /* Enforce sane interface api - has been abused by the fb helper. */
9248 BUG_ON(!set->mode && set->fb);
9249 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9250
2e431051
DV		 9251 if (set->fb) {
9252 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9253 set->crtc->base.id, set->fb->base.id,
9254 (int)set->num_connectors, set->x, set->y);
9255 } else {
9256 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9257 }
9258
9259 dev = set->crtc->dev;
9260
9261 ret = -ENOMEM;
9262 config = kzalloc(sizeof(*config), GFP_KERNEL);
9263 if (!config)
9264 goto out_config;
9265
9266 ret = intel_set_config_save_state(dev, config);
9267 if (ret)
9268 goto out_config;
9269
9270 save_set.crtc = set->crtc;
9271 save_set.mode = &set->crtc->mode;
9272 save_set.x = set->crtc->x;
9273 save_set.y = set->crtc->y;
9274 save_set.fb = set->crtc->fb;
9275
9276 /* Compute whether we need a full modeset, only an fb base update or no
9277 * change at all. In the future we might also check whether only the
9278 * mode changed, e.g. for LVDS where we only change the panel fitter in
9279 * such cases. */
9280 intel_set_config_compute_mode_changes(set, config);
9281
9a935856 9282 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9283 if (ret)
9284 goto fail;
9285
5e2b584e 9286 if (config->mode_changed) {
c0c36b94
CW		 9287 ret = intel_set_mode(set->crtc, set->mode,
9288 set->x, set->y, set->fb);
5e2b584e 9289 } else if (config->fb_changed) {
4878cae2
VS		 9290 intel_crtc_wait_for_pending_flips(set->crtc);
9291
4f660f49 9292 ret = intel_pipe_set_base(set->crtc,
94352cf9 9293 set->x, set->y, set->fb);
50f56119
DV		 9294 }
9295
2d05eae1 9296 if (ret) {
bf67dfeb
DV		 9297 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9298 set->crtc->base.id, ret);
50f56119 9299fail:
2d05eae1 9300 intel_set_config_restore_state(dev, config);
50f56119 9301
2d05eae1
CW		 9302 /* Try to restore the config */
9303 if (config->mode_changed &&
9304 intel_set_mode(save_set.crtc, save_set.mode,
9305 save_set.x, save_set.y, save_set.fb))
9306 DRM_ERROR("failed to restore config after modeset failure\n");
9307 }
50f56119 9308
d9e55608
DV		 9309out_config:
9310 intel_set_config_free(config);
50f56119
DV		 9311 return ret;
9312}
f6e5b160
CW		 9313
9314static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9315 .cursor_set = intel_crtc_cursor_set,
9316 .cursor_move = intel_crtc_cursor_move,
9317 .gamma_set = intel_crtc_gamma_set,
50f56119 9318 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9319 .destroy = intel_crtc_destroy,
9320 .page_flip = intel_crtc_page_flip,
9321};
9322
79f689aa
PZ		 9323static void intel_cpu_pll_init(struct drm_device *dev)
9324{
affa9354 9325 if (HAS_DDI(dev))
79f689aa
PZ		 9326 intel_ddi_pll_init(dev);
9327}
9328
5358901f
DV		 9329static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9330 struct intel_shared_dpll *pll,
9331 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9332{
5358901f 9333 uint32_t val;
ee7b9f93 9334
5358901f 9335 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9336 hw_state->dpll = val;
9337 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9338 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9339
9340 return val & DPLL_VCO_ENABLE;
9341}
9342
15bdd4cf
DV		 9343static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9344 struct intel_shared_dpll *pll)
9345{
9346 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9347 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9348}
9349
e7b903d2
DV		 9350static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9351 struct intel_shared_dpll *pll)
9352{
e7b903d2
DV		 9353 /* PCH refclock must be enabled first */
9354 assert_pch_refclk_enabled(dev_priv);
9355
15bdd4cf
DV		 9356 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9357
9358 /* Wait for the clocks to stabilize. */
9359 POSTING_READ(PCH_DPLL(pll->id));
9360 udelay(150);
9361
9362 /* The pixel multiplier can only be updated once the
9363 * DPLL is enabled and the clocks are stable.
9364 *
9365 * So write it again.
9366 */
9367 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9368 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9369 udelay(200);
9370}
9371
9372static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9373 struct intel_shared_dpll *pll)
9374{
9375 struct drm_device *dev = dev_priv->dev;
9376 struct intel_crtc *crtc;
e7b903d2
DV		 9377
9378 /* Make sure no transcoder isn't still depending on us. */
9379 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9380 if (intel_crtc_to_shared_dpll(crtc) == pll)
9381 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9382 }
9383
15bdd4cf
DV		 9384 I915_WRITE(PCH_DPLL(pll->id), 0);
9385 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9386 udelay(200);
9387}
9388
46edb027
DV		 9389static char *ibx_pch_dpll_names[] = {
9390 "PCH DPLL A",
9391 "PCH DPLL B",
9392};
9393
7c74ade1 9394static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9395{
e7b903d2 9396 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9397 int i;
9398
7c74ade1 9399 dev_priv->num_shared_dpll = 2;
ee7b9f93 9400
e72f9fbf 9401 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9402 dev_priv->shared_dplls[i].id = i;
9403 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9404 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9405 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9406 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9407 dev_priv->shared_dplls[i].get_hw_state =
9408 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9409 }
9410}
9411
7c74ade1
DV		 9412static void intel_shared_dpll_init(struct drm_device *dev)
9413{
e7b903d2 9414 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9415
9416 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9417 ibx_pch_dpll_init(dev);
9418 else
9419 dev_priv->num_shared_dpll = 0;
9420
9421 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9422 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9423 dev_priv->num_shared_dpll);
9424}
9425
b358d0a6 9426static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9427{
22fd0fab 9428 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9429 struct intel_crtc *intel_crtc;
9430 int i;
9431
9432 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9433 if (intel_crtc == NULL)
9434 return;
9435
9436 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9437
9438 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9439 for (i = 0; i < 256; i++) {
9440 intel_crtc->lut_r[i] = i;
9441 intel_crtc->lut_g[i] = i;
9442 intel_crtc->lut_b[i] = i;
9443 }
9444
80824003
JB		 9445 /* Swap pipes & planes for FBC on pre-965 */
9446 intel_crtc->pipe = pipe;
9447 intel_crtc->plane = pipe;
e2e767ab 9448 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9449 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9450 intel_crtc->plane = !pipe;
80824003
JB		 9451 }
9452
22fd0fab
JB		 9453 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9454 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9455 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9456 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9457
79e53945 9458 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9459}
9460
08d7b3d1 9461int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9462 struct drm_file *file)
08d7b3d1 9463{
08d7b3d1 9464 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9465 struct drm_mode_object *drmmode_obj;
9466 struct intel_crtc *crtc;
08d7b3d1 9467
1cff8f6b
DV		 9468 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9469 return -ENODEV;
08d7b3d1 9470
c05422d5
DV		 9471 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9472 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9473
c05422d5 9474 if (!drmmode_obj) {
08d7b3d1
CW		 9475 DRM_ERROR("no such CRTC id\n");
9476 return -EINVAL;
9477 }
9478
c05422d5
DV		 9479 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9480 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9481
c05422d5 9482 return 0;
08d7b3d1
CW		 9483}
9484
66a9278e 9485static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9486{
66a9278e
DV		 9487 struct drm_device *dev = encoder->base.dev;
9488 struct intel_encoder *source_encoder;
79e53945 9489 int index_mask = 0;
79e53945
JB		 9490 int entry = 0;
9491
66a9278e
DV		 9492 list_for_each_entry(source_encoder,
9493 &dev->mode_config.encoder_list, base.head) {
9494
9495 if (encoder == source_encoder)
79e53945 9496 index_mask |= (1 << entry);
66a9278e
DV		 9497
9498 /* Intel hw has only one MUX where enocoders could be cloned. */
9499 if (encoder->cloneable && source_encoder->cloneable)
9500 index_mask |= (1 << entry);
9501
79e53945
JB		 9502 entry++;
9503 }
4ef69c7a 9504
79e53945
JB		 9505 return index_mask;
9506}
9507
4d302442
CW		 9508static bool has_edp_a(struct drm_device *dev)
9509{
9510 struct drm_i915_private *dev_priv = dev->dev_private;
9511
9512 if (!IS_MOBILE(dev))
9513 return false;
9514
9515 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9516 return false;
9517
9518 if (IS_GEN5(dev) &&
9519 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9520 return false;
9521
9522 return true;
9523}
9524
79e53945
JB		 9525static void intel_setup_outputs(struct drm_device *dev)
9526{
725e30ad 9527 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9528 struct intel_encoder *encoder;
cb0953d7 9529 bool dpd_is_edp = false;
79e53945 9530
c9093354 9531 intel_lvds_init(dev);
79e53945 9532
c40c0f5b 9533 if (!IS_ULT(dev))
79935fca 9534 intel_crt_init(dev);
cb0953d7 9535
affa9354 9536 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9537 int found;
9538
9539 /* Haswell uses DDI functions to detect digital outputs */
9540 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9541 /* DDI A only supports eDP */
9542 if (found)
9543 intel_ddi_init(dev, PORT_A);
9544
9545 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9546 * register */
9547 found = I915_READ(SFUSE_STRAP);
9548
9549 if (found & SFUSE_STRAP_DDIB_DETECTED)
9550 intel_ddi_init(dev, PORT_B);
9551 if (found & SFUSE_STRAP_DDIC_DETECTED)
9552 intel_ddi_init(dev, PORT_C);
9553 if (found & SFUSE_STRAP_DDID_DETECTED)
9554 intel_ddi_init(dev, PORT_D);
9555 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9556 int found;
270b3042
DV		 9557 dpd_is_edp = intel_dpd_is_edp(dev);
9558
9559 if (has_edp_a(dev))
9560 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9561
dc0fa718 9562 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9563 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9564 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9565 if (!found)
e2debe91 9566 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9567 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9568 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9569 }
9570
dc0fa718 9571 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9572 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9573
dc0fa718 9574 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9575 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9576
5eb08b69 9577 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9578 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9579
270b3042 9580 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9581 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9582 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9583 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9584 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9585 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9586 PORT_C);
9587 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9588 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9589 PORT_C);
9590 }
19c03924 9591
dc0fa718 9592 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9593 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9594 PORT_B);
67cfc203
VS		 9595 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9596 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9597 }
3cfca973
JN		 9598
9599 intel_dsi_init(dev);
103a196f 9600 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9601 bool found = false;
7d57382e 9602
e2debe91 9603 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9604 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9605 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9606 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9607 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9608 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9609 }
27185ae1 9610
e7281eab 9611 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9612 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9613 }
13520b05
KH		 9614
9615 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9616
e2debe91 9617 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9618 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9619 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9620 }
27185ae1 9621
e2debe91 9622 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9623
b01f2c3a
JB		 9624 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9625 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9626 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9627 }
e7281eab 9628 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9629 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9630 }
27185ae1 9631
b01f2c3a 9632 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9633 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9634 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9635 } else if (IS_GEN2(dev))
79e53945
JB		 9636 intel_dvo_init(dev);
9637
103a196f 9638 if (SUPPORTS_TV(dev))
79e53945
JB		 9639 intel_tv_init(dev);
9640
4ef69c7a
CW		 9641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9642 encoder->base.possible_crtcs = encoder->crtc_mask;
9643 encoder->base.possible_clones =
66a9278e 9644 intel_encoder_clones(encoder);
79e53945 9645 }
47356eb6 9646
dde86e2d 9647 intel_init_pch_refclk(dev);
270b3042
DV		 9648
9649 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9650}
9651
ddfe1567
CW		 9652void intel_framebuffer_fini(struct intel_framebuffer *fb)
9653{
9654 drm_framebuffer_cleanup(&fb->base);
9655 drm_gem_object_unreference_unlocked(&fb->obj->base);
9656}
9657
79e53945
JB		 9658static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9659{
9660 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9661
ddfe1567 9662 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9663 kfree(intel_fb);
9664}
9665
9666static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9667 struct drm_file *file,
79e53945
JB		 9668 unsigned int *handle)
9669{
9670 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9671 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9672
05394f39 9673 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9674}
9675
9676static const struct drm_framebuffer_funcs intel_fb_funcs = {
9677 .destroy = intel_user_framebuffer_destroy,
9678 .create_handle = intel_user_framebuffer_create_handle,
9679};
9680
38651674
DA		 9681int intel_framebuffer_init(struct drm_device *dev,
9682 struct intel_framebuffer *intel_fb,
308e5bcb 9683 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9684 struct drm_i915_gem_object *obj)
79e53945 9685{
a35cdaa0 9686 int pitch_limit;
79e53945
JB		 9687 int ret;
9688
c16ed4be
CW		 9689 if (obj->tiling_mode == I915_TILING_Y) {
9690 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9691 return -EINVAL;
c16ed4be 9692 }
57cd6508 9693
c16ed4be
CW		 9694 if (mode_cmd->pitches[0] & 63) {
9695 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9696 mode_cmd->pitches[0]);
57cd6508 9697 return -EINVAL;
c16ed4be 9698 }
57cd6508 9699
a35cdaa0
CW		 9700 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9701 pitch_limit = 32*1024;
9702 } else if (INTEL_INFO(dev)->gen >= 4) {
9703 if (obj->tiling_mode)
9704 pitch_limit = 16*1024;
9705 else
9706 pitch_limit = 32*1024;
9707 } else if (INTEL_INFO(dev)->gen >= 3) {
9708 if (obj->tiling_mode)
9709 pitch_limit = 8*1024;
9710 else
9711 pitch_limit = 16*1024;
9712 } else
9713 /* XXX DSPC is limited to 4k tiled */
9714 pitch_limit = 8*1024;
9715
9716 if (mode_cmd->pitches[0] > pitch_limit) {
9717 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9718 obj->tiling_mode ? "tiled" : "linear",
9719 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9720 return -EINVAL;
c16ed4be 9721 }
5d7bd705
VS		 9722
9723 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9724 mode_cmd->pitches[0] != obj->stride) {
9725 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9726 mode_cmd->pitches[0], obj->stride);
5d7bd705 9727 return -EINVAL;
c16ed4be 9728 }
5d7bd705 9729
57779d06 9730 /* Reject formats not supported by any plane early. */
308e5bcb 9731 switch (mode_cmd->pixel_format) {
57779d06 9732 case DRM_FORMAT_C8:
04b3924d
VS		 9733 case DRM_FORMAT_RGB565:
9734 case DRM_FORMAT_XRGB8888:
9735 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9736 break;
9737 case DRM_FORMAT_XRGB1555:
9738 case DRM_FORMAT_ARGB1555:
c16ed4be 9739 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9740 DRM_DEBUG("unsupported pixel format: %s\n",
9741 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9742 return -EINVAL;
c16ed4be 9743 }
57779d06
VS		 9744 break;
9745 case DRM_FORMAT_XBGR8888:
9746 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9747 case DRM_FORMAT_XRGB2101010:
9748 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9749 case DRM_FORMAT_XBGR2101010:
9750 case DRM_FORMAT_ABGR2101010:
c16ed4be 9751 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9752 DRM_DEBUG("unsupported pixel format: %s\n",
9753 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9754 return -EINVAL;
c16ed4be 9755 }
b5626747 9756 break;
04b3924d
VS		 9757 case DRM_FORMAT_YUYV:
9758 case DRM_FORMAT_UYVY:
9759 case DRM_FORMAT_YVYU:
9760 case DRM_FORMAT_VYUY:
c16ed4be 9761 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9762 DRM_DEBUG("unsupported pixel format: %s\n",
9763 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9764 return -EINVAL;
c16ed4be 9765 }
57cd6508
CW		 9766 break;
9767 default:
4ee62c76
VS		 9768 DRM_DEBUG("unsupported pixel format: %s\n",
9769 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9770 return -EINVAL;
9771 }
9772
90f9a336
VS		 9773 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9774 if (mode_cmd->offsets[0] != 0)
9775 return -EINVAL;
9776
c7d73f6a
DV		 9777 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9778 intel_fb->obj = obj;
9779
79e53945
JB		 9780 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9781 if (ret) {
9782 DRM_ERROR("framebuffer init failed %d\n", ret);
9783 return ret;
9784 }
9785
79e53945
JB		 9786 return 0;
9787}
9788
79e53945
JB		 9789static struct drm_framebuffer *
9790intel_user_framebuffer_create(struct drm_device *dev,
9791 struct drm_file *filp,
308e5bcb 9792 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9793{
05394f39 9794 struct drm_i915_gem_object *obj;
79e53945 9795
308e5bcb
JB		 9796 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9797 mode_cmd->handles[0]));
c8725226 9798 if (&obj->base == NULL)
cce13ff7 9799 return ERR_PTR(-ENOENT);
79e53945 9800
d2dff872 9801 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9802}
9803
79e53945 9804static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9805 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9806 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9807};
9808
e70236a8
JB		 9809/* Set up chip specific display functions */
9810static void intel_init_display(struct drm_device *dev)
9811{
9812 struct drm_i915_private *dev_priv = dev->dev_private;
9813
ee9300bb
DV		 9814 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9815 dev_priv->display.find_dpll = g4x_find_best_dpll;
9816 else if (IS_VALLEYVIEW(dev))
9817 dev_priv->display.find_dpll = vlv_find_best_dpll;
9818 else if (IS_PINEVIEW(dev))
9819 dev_priv->display.find_dpll = pnv_find_best_dpll;
9820 else
9821 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9822
affa9354 9823 if (HAS_DDI(dev)) {
0e8ffe1b 9824 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9825 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9826 dev_priv->display.crtc_enable = haswell_crtc_enable;
9827 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9828 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9829 dev_priv->display.update_plane = ironlake_update_plane;
9830 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9831 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9832 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9833 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9834 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9835 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9836 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9837 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9838 } else if (IS_VALLEYVIEW(dev)) {
9839 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9840 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9841 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9842 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9843 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9844 dev_priv->display.off = i9xx_crtc_off;
9845 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9846 } else {
0e8ffe1b 9847 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9848 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9849 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9850 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9851 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9852 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9853 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9854 }
e70236a8 9855
e70236a8 9856 /* Returns the core display clock speed */
25eb05fc
JB		 9857 if (IS_VALLEYVIEW(dev))
9858 dev_priv->display.get_display_clock_speed =
9859 valleyview_get_display_clock_speed;
9860 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9861 dev_priv->display.get_display_clock_speed =
9862 i945_get_display_clock_speed;
9863 else if (IS_I915G(dev))
9864 dev_priv->display.get_display_clock_speed =
9865 i915_get_display_clock_speed;
257a7ffc 9866 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9867 dev_priv->display.get_display_clock_speed =
9868 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9869 else if (IS_PINEVIEW(dev))
9870 dev_priv->display.get_display_clock_speed =
9871 pnv_get_display_clock_speed;
e70236a8
JB		 9872 else if (IS_I915GM(dev))
9873 dev_priv->display.get_display_clock_speed =
9874 i915gm_get_display_clock_speed;
9875 else if (IS_I865G(dev))
9876 dev_priv->display.get_display_clock_speed =
9877 i865_get_display_clock_speed;
f0f8a9ce 9878 else if (IS_I85X(dev))
e70236a8
JB		 9879 dev_priv->display.get_display_clock_speed =
9880 i855_get_display_clock_speed;
9881 else /* 852, 830 */
9882 dev_priv->display.get_display_clock_speed =
9883 i830_get_display_clock_speed;
9884
7f8a8569 9885 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9886 if (IS_GEN5(dev)) {
674cf967 9887 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9888 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9889 } else if (IS_GEN6(dev)) {
674cf967 9890 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9891 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9892 } else if (IS_IVYBRIDGE(dev)) {
9893 /* FIXME: detect B0+ stepping and use auto training */
9894 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9895 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9896 dev_priv->display.modeset_global_resources =
9897 ivb_modeset_global_resources;
c82e4d26
ED		 9898 } else if (IS_HASWELL(dev)) {
9899 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9900 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9901 dev_priv->display.modeset_global_resources =
9902 haswell_modeset_global_resources;
a0e63c22 9903 }
6067aaea 9904 } else if (IS_G4X(dev)) {
e0dac65e 9905 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9906 }
8c9f3aaf
JB		 9907
9908 /* Default just returns -ENODEV to indicate unsupported */
9909 dev_priv->display.queue_flip = intel_default_queue_flip;
9910
9911 switch (INTEL_INFO(dev)->gen) {
9912 case 2:
9913 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9914 break;
9915
9916 case 3:
9917 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9918 break;
9919
9920 case 4:
9921 case 5:
9922 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9923 break;
9924
9925 case 6:
9926 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9927 break;
7c9017e5
JB		 9928 case 7:
9929 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9930 break;
8c9f3aaf 9931 }
e70236a8
JB		 9932}
9933
b690e96c
JB		 9934/*
9935 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9936 * resume, or other times. This quirk makes sure that's the case for
9937 * affected systems.
9938 */
0206e353 9939static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9940{
9941 struct drm_i915_private *dev_priv = dev->dev_private;
9942
9943 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9944 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9945}
9946
435793df
KP		 9947/*
9948 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9949 */
9950static void quirk_ssc_force_disable(struct drm_device *dev)
9951{
9952 struct drm_i915_private *dev_priv = dev->dev_private;
9953 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9954 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9955}
9956
4dca20ef 9957/*
5a15ab5b
CE		 9958 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9959 * brightness value
4dca20ef
CE		 9960 */
9961static void quirk_invert_brightness(struct drm_device *dev)
9962{
9963 struct drm_i915_private *dev_priv = dev->dev_private;
9964 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9965 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9966}
9967
e85843be
KM		 9968/*
9969 * Some machines (Dell XPS13) suffer broken backlight controls if
9970 * BLM_PCH_PWM_ENABLE is set.
9971 */
9972static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9973{
9974 struct drm_i915_private *dev_priv = dev->dev_private;
9975 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9976 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9977}
9978
b690e96c
JB		 9979struct intel_quirk {
9980 int device;
9981 int subsystem_vendor;
9982 int subsystem_device;
9983 void (*hook)(struct drm_device *dev);
9984};
9985
5f85f176
EE		 9986/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9987struct intel_dmi_quirk {
9988 void (*hook)(struct drm_device *dev);
9989 const struct dmi_system_id (*dmi_id_list)[];
9990};
9991
9992static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9993{
9994 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9995 return 1;
9996}
9997
9998static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9999 {
10000 .dmi_id_list = &(const struct dmi_system_id[]) {
10001 {
10002 .callback = intel_dmi_reverse_brightness,
10003 .ident = "NCR Corporation",
10004 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10005 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10006 },
10007 },
10008 { } /* terminating entry */
10009 },
10010 .hook = quirk_invert_brightness,
10011 },
10012};
10013
c43b5634 10014static struct intel_quirk intel_quirks[] = {
b690e96c 10015 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10016 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10017
b690e96c
JB		 10018 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10019 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10020
b690e96c
JB		 10021 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10022 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10023
ccd0d36e 10024 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10025 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10026 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10027
10028 /* Lenovo U160 cannot use SSC on LVDS */
10029 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10030
10031 /* Sony Vaio Y cannot use SSC on LVDS */
10032 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10033
10034 /* Acer Aspire 5734Z must invert backlight brightness */
10035 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10036
10037 /* Acer/eMachines G725 */
10038 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10039
10040 /* Acer/eMachines e725 */
10041 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10042
10043 /* Acer/Packard Bell NCL20 */
10044 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10045
10046 /* Acer Aspire 4736Z */
10047 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10048
10049 /* Dell XPS13 HD Sandy Bridge */
10050 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10051 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10052 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10053};
10054
10055static void intel_init_quirks(struct drm_device *dev)
10056{
10057 struct pci_dev *d = dev->pdev;
10058 int i;
10059
10060 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10061 struct intel_quirk *q = &intel_quirks[i];
10062
10063 if (d->device == q->device &&
10064 (d->subsystem_vendor == q->subsystem_vendor ||
10065 q->subsystem_vendor == PCI_ANY_ID) &&
10066 (d->subsystem_device == q->subsystem_device ||
10067 q->subsystem_device == PCI_ANY_ID))
10068 q->hook(dev);
10069 }
5f85f176
EE		 10070 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10071 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10072 intel_dmi_quirks[i].hook(dev);
10073 }
b690e96c
JB		 10074}
10075
9cce37f4
JB		 10076/* Disable the VGA plane that we never use */
10077static void i915_disable_vga(struct drm_device *dev)
10078{
10079 struct drm_i915_private *dev_priv = dev->dev_private;
10080 u8 sr1;
766aa1c4 10081 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10082
10083 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10084 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10085 sr1 = inb(VGA_SR_DATA);
10086 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10087
10088 /* Disable VGA memory on Intel HD */
10089 if (HAS_PCH_SPLIT(dev)) {
10090 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10091 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10092 VGA_RSRC_NORMAL_IO |
10093 VGA_RSRC_NORMAL_MEM);
10094 }
10095
9cce37f4
JB		 10096 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10097 udelay(300);
10098
10099 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10100 POSTING_READ(vga_reg);
10101}
10102
81b5c7bc
AW		 10103static void i915_enable_vga(struct drm_device *dev)
10104{
10105 /* Enable VGA memory on Intel HD */
10106 if (HAS_PCH_SPLIT(dev)) {
10107 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10108 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10109 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10110 VGA_RSRC_LEGACY_MEM |
10111 VGA_RSRC_NORMAL_IO |
10112 VGA_RSRC_NORMAL_MEM);
10113 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10114 }
10115}
10116
f817586c
DV		 10117void intel_modeset_init_hw(struct drm_device *dev)
10118{
fa42e23c 10119 intel_init_power_well(dev);
0232e927 10120
a8f78b58
ED		 10121 intel_prepare_ddi(dev);
10122
f817586c
DV		 10123 intel_init_clock_gating(dev);
10124
79f5b2c7 10125 mutex_lock(&dev->struct_mutex);
8090c6b9 10126 intel_enable_gt_powersave(dev);
79f5b2c7 10127 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10128}
10129
7d708ee4
ID		 10130void intel_modeset_suspend_hw(struct drm_device *dev)
10131{
10132 intel_suspend_hw(dev);
10133}
10134
79e53945
JB		 10135void intel_modeset_init(struct drm_device *dev)
10136{
652c393a 10137 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10138 int i, j, ret;
79e53945
JB		 10139
10140 drm_mode_config_init(dev);
10141
10142 dev->mode_config.min_width = 0;
10143 dev->mode_config.min_height = 0;
10144
019d96cb
DA		 10145 dev->mode_config.preferred_depth = 24;
10146 dev->mode_config.prefer_shadow = 1;
10147
e6ecefaa 10148 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10149
b690e96c
JB		 10150 intel_init_quirks(dev);
10151
1fa61106
ED		 10152 intel_init_pm(dev);
10153
e3c74757
BW		 10154 if (INTEL_INFO(dev)->num_pipes == 0)
10155 return;
10156
e70236a8
JB		 10157 intel_init_display(dev);
10158
a6c45cf0
CW		 10159 if (IS_GEN2(dev)) {
10160 dev->mode_config.max_width = 2048;
10161 dev->mode_config.max_height = 2048;
10162 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10163 dev->mode_config.max_width = 4096;
10164 dev->mode_config.max_height = 4096;
79e53945 10165 } else {
a6c45cf0
CW		 10166 dev->mode_config.max_width = 8192;
10167 dev->mode_config.max_height = 8192;
79e53945 10168 }
5d4545ae 10169 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10170
28c97730 10171 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10172 INTEL_INFO(dev)->num_pipes,
10173 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10174
08e2a7de 10175 for_each_pipe(i) {
79e53945 10176 intel_crtc_init(dev, i);
7f1f3851
JB		 10177 for (j = 0; j < dev_priv->num_plane; j++) {
10178 ret = intel_plane_init(dev, i, j);
10179 if (ret)
06da8da2
VS		 10180 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10181 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10182 }
79e53945
JB		 10183 }
10184
79f689aa 10185 intel_cpu_pll_init(dev);
e72f9fbf 10186 intel_shared_dpll_init(dev);
ee7b9f93 10187
9cce37f4
JB		 10188 /* Just disable it once at startup */
10189 i915_disable_vga(dev);
79e53945 10190 intel_setup_outputs(dev);
11be49eb
CW		 10191
10192 /* Just in case the BIOS is doing something questionable. */
10193 intel_disable_fbc(dev);
2c7111db
CW		 10194}
10195
24929352
DV		 10196static void
10197intel_connector_break_all_links(struct intel_connector *connector)
10198{
10199 connector->base.dpms = DRM_MODE_DPMS_OFF;
10200 connector->base.encoder = NULL;
10201 connector->encoder->connectors_active = false;
10202 connector->encoder->base.crtc = NULL;
10203}
10204
7fad798e
DV		 10205static void intel_enable_pipe_a(struct drm_device *dev)
10206{
10207 struct intel_connector *connector;
10208 struct drm_connector *crt = NULL;
10209 struct intel_load_detect_pipe load_detect_temp;
10210
10211 /* We can't just switch on the pipe A, we need to set things up with a
10212 * proper mode and output configuration. As a gross hack, enable pipe A
10213 * by enabling the load detect pipe once. */
10214 list_for_each_entry(connector,
10215 &dev->mode_config.connector_list,
10216 base.head) {
10217 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10218 crt = &connector->base;
10219 break;
10220 }
10221 }
10222
10223 if (!crt)
10224 return;
10225
10226 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10227 intel_release_load_detect_pipe(crt, &load_detect_temp);
10228
652c393a 10229
7fad798e
DV		 10230}
10231
fa555837
DV		 10232static bool
10233intel_check_plane_mapping(struct intel_crtc *crtc)
10234{
7eb552ae
BW		 10235 struct drm_device *dev = crtc->base.dev;
10236 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10237 u32 reg, val;
10238
7eb552ae 10239 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10240 return true;
10241
10242 reg = DSPCNTR(!crtc->plane);
10243 val = I915_READ(reg);
10244
10245 if ((val & DISPLAY_PLANE_ENABLE) &&
10246 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10247 return false;
10248
10249 return true;
10250}
10251
24929352
DV		 10252static void intel_sanitize_crtc(struct intel_crtc *crtc)
10253{
10254 struct drm_device *dev = crtc->base.dev;
10255 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10256 u32 reg;
24929352 10257
24929352 10258 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10259 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10260 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10261
10262 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10263 * disable the crtc (and hence change the state) if it is wrong. Note
10264 * that gen4+ has a fixed plane -> pipe mapping. */
10265 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10266 struct intel_connector *connector;
10267 bool plane;
10268
24929352
DV		 10269 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10270 crtc->base.base.id);
10271
10272 /* Pipe has the wrong plane attached and the plane is active.
10273 * Temporarily change the plane mapping and disable everything
10274 * ... */
10275 plane = crtc->plane;
10276 crtc->plane = !plane;
10277 dev_priv->display.crtc_disable(&crtc->base);
10278 crtc->plane = plane;
10279
10280 /* ... and break all links. */
10281 list_for_each_entry(connector, &dev->mode_config.connector_list,
10282 base.head) {
10283 if (connector->encoder->base.crtc != &crtc->base)
10284 continue;
10285
10286 intel_connector_break_all_links(connector);
10287 }
10288
10289 WARN_ON(crtc->active);
10290 crtc->base.enabled = false;
10291 }
24929352 10292
7fad798e
DV		 10293 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10294 crtc->pipe == PIPE_A && !crtc->active) {
10295 /* BIOS forgot to enable pipe A, this mostly happens after
10296 * resume. Force-enable the pipe to fix this, the update_dpms
10297 * call below we restore the pipe to the right state, but leave
10298 * the required bits on. */
10299 intel_enable_pipe_a(dev);
10300 }
10301
24929352
DV		 10302 /* Adjust the state of the output pipe according to whether we
10303 * have active connectors/encoders. */
10304 intel_crtc_update_dpms(&crtc->base);
10305
10306 if (crtc->active != crtc->base.enabled) {
10307 struct intel_encoder *encoder;
10308
10309 /* This can happen either due to bugs in the get_hw_state
10310 * functions or because the pipe is force-enabled due to the
10311 * pipe A quirk. */
10312 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10313 crtc->base.base.id,
10314 crtc->base.enabled ? "enabled" : "disabled",
10315 crtc->active ? "enabled" : "disabled");
10316
10317 crtc->base.enabled = crtc->active;
10318
10319 /* Because we only establish the connector -> encoder ->
10320 * crtc links if something is active, this means the
10321 * crtc is now deactivated. Break the links. connector
10322 * -> encoder links are only establish when things are
10323 * actually up, hence no need to break them. */
10324 WARN_ON(crtc->active);
10325
10326 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10327 WARN_ON(encoder->connectors_active);
10328 encoder->base.crtc = NULL;
10329 }
10330 }
10331}
10332
10333static void intel_sanitize_encoder(struct intel_encoder *encoder)
10334{
10335 struct intel_connector *connector;
10336 struct drm_device *dev = encoder->base.dev;
10337
10338 /* We need to check both for a crtc link (meaning that the
10339 * encoder is active and trying to read from a pipe) and the
10340 * pipe itself being active. */
10341 bool has_active_crtc = encoder->base.crtc &&
10342 to_intel_crtc(encoder->base.crtc)->active;
10343
10344 if (encoder->connectors_active && !has_active_crtc) {
10345 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10346 encoder->base.base.id,
10347 drm_get_encoder_name(&encoder->base));
10348
10349 /* Connector is active, but has no active pipe. This is
10350 * fallout from our resume register restoring. Disable
10351 * the encoder manually again. */
10352 if (encoder->base.crtc) {
10353 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10354 encoder->base.base.id,
10355 drm_get_encoder_name(&encoder->base));
10356 encoder->disable(encoder);
10357 }
10358
10359 /* Inconsistent output/port/pipe state happens presumably due to
10360 * a bug in one of the get_hw_state functions. Or someplace else
10361 * in our code, like the register restore mess on resume. Clamp
10362 * things to off as a safer default. */
10363 list_for_each_entry(connector,
10364 &dev->mode_config.connector_list,
10365 base.head) {
10366 if (connector->encoder != encoder)
10367 continue;
10368
10369 intel_connector_break_all_links(connector);
10370 }
10371 }
10372 /* Enabled encoders without active connectors will be fixed in
10373 * the crtc fixup. */
10374}
10375
44cec740 10376void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10377{
10378 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10379 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10380
8dc8a27c
PZ		 10381 /* This function can be called both from intel_modeset_setup_hw_state or
10382 * at a very early point in our resume sequence, where the power well
10383 * structures are not yet restored. Since this function is at a very
10384 * paranoid "someone might have enabled VGA while we were not looking"
10385 * level, just check if the power well is enabled instead of trying to
10386 * follow the "don't touch the power well if we don't need it" policy
10387 * the rest of the driver uses. */
10388 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10389 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10390 return;
10391
0fde901f
KM		 10392 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10393 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10394 i915_disable_vga(dev);
0fde901f
KM		 10395 }
10396}
10397
30e984df 10398static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10399{
10400 struct drm_i915_private *dev_priv = dev->dev_private;
10401 enum pipe pipe;
24929352
DV		 10402 struct intel_crtc *crtc;
10403 struct intel_encoder *encoder;
10404 struct intel_connector *connector;
5358901f 10405 int i;
24929352 10406
0e8ffe1b
DV		 10407 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10408 base.head) {
88adfff1 10409 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10410
0e8ffe1b
DV		 10411 crtc->active = dev_priv->display.get_pipe_config(crtc,
10412 &crtc->config);
24929352
DV		 10413
10414 crtc->base.enabled = crtc->active;
10415
10416 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10417 crtc->base.base.id,
10418 crtc->active ? "enabled" : "disabled");
10419 }
10420
5358901f 10421 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10422 if (HAS_DDI(dev))
6441ab5f
PZ		 10423 intel_ddi_setup_hw_pll_state(dev);
10424
5358901f
DV		 10425 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10426 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10427
10428 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10429 pll->active = 0;
10430 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10431 base.head) {
10432 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10433 pll->active++;
10434 }
10435 pll->refcount = pll->active;
10436
35c95375
DV		 10437 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10438 pll->name, pll->refcount, pll->on);
5358901f
DV		 10439 }
10440
24929352
DV		 10441 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10442 base.head) {
10443 pipe = 0;
10444
10445 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10446 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10447 encoder->base.crtc = &crtc->base;
510d5f2f 10448 if (encoder->get_config)
045ac3b5 10449 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10450 } else {
10451 encoder->base.crtc = NULL;
10452 }
10453
10454 encoder->connectors_active = false;
10455 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10456 encoder->base.base.id,
10457 drm_get_encoder_name(&encoder->base),
10458 encoder->base.crtc ? "enabled" : "disabled",
10459 pipe);
10460 }
10461
510d5f2f
JB		 10462 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10463 base.head) {
10464 if (!crtc->active)
10465 continue;
10466 if (dev_priv->display.get_clock)
10467 dev_priv->display.get_clock(crtc,
10468 &crtc->config);
10469 }
10470
24929352
DV		 10471 list_for_each_entry(connector, &dev->mode_config.connector_list,
10472 base.head) {
10473 if (connector->get_hw_state(connector)) {
10474 connector->base.dpms = DRM_MODE_DPMS_ON;
10475 connector->encoder->connectors_active = true;
10476 connector->base.encoder = &connector->encoder->base;
10477 } else {
10478 connector->base.dpms = DRM_MODE_DPMS_OFF;
10479 connector->base.encoder = NULL;
10480 }
10481 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10482 connector->base.base.id,
10483 drm_get_connector_name(&connector->base),
10484 connector->base.encoder ? "enabled" : "disabled");
10485 }
30e984df
DV		 10486}
10487
10488/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10489 * and i915 state tracking structures. */
10490void intel_modeset_setup_hw_state(struct drm_device *dev,
10491 bool force_restore)
10492{
10493 struct drm_i915_private *dev_priv = dev->dev_private;
10494 enum pipe pipe;
10495 struct drm_plane *plane;
10496 struct intel_crtc *crtc;
10497 struct intel_encoder *encoder;
35c95375 10498 int i;
30e984df
DV		 10499
10500 intel_modeset_readout_hw_state(dev);
24929352 10501
babea61d
JB		 10502 /*
10503 * Now that we have the config, copy it to each CRTC struct
10504 * Note that this could go away if we move to using crtc_config
10505 * checking everywhere.
10506 */
10507 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10508 base.head) {
10509 if (crtc->active && i915_fastboot) {
10510 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10511
10512 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10513 crtc->base.base.id);
10514 drm_mode_debug_printmodeline(&crtc->base.mode);
10515 }
10516 }
10517
24929352
DV		 10518 /* HW state is read out, now we need to sanitize this mess. */
10519 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10520 base.head) {
10521 intel_sanitize_encoder(encoder);
10522 }
10523
10524 for_each_pipe(pipe) {
10525 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10526 intel_sanitize_crtc(crtc);
c0b03411 10527 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10528 }
9a935856 10529
35c95375
DV		 10530 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10531 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10532
10533 if (!pll->on || pll->active)
10534 continue;
10535
10536 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10537
10538 pll->disable(dev_priv, pll);
10539 pll->on = false;
10540 }
10541
45e2b5f6 10542 if (force_restore) {
f30da187
DV		 10543 /*
10544 * We need to use raw interfaces for restoring state to avoid
10545 * checking (bogus) intermediate states.
10546 */
45e2b5f6 10547 for_each_pipe(pipe) {
b5644d05
JB		 10548 struct drm_crtc *crtc =
10549 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10550
10551 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10552 crtc->fb);
45e2b5f6 10553 }
b5644d05
JB		 10554 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10555 intel_plane_restore(plane);
0fde901f
KM		 10556
10557 i915_redisable_vga(dev);
45e2b5f6
DV		 10558 } else {
10559 intel_modeset_update_staged_output_state(dev);
10560 }
8af6cf88
DV		 10561
10562 intel_modeset_check_state(dev);
2e938892
DV		 10563
10564 drm_mode_config_reset(dev);
2c7111db
CW		 10565}
10566
10567void intel_modeset_gem_init(struct drm_device *dev)
10568{
1833b134 10569 intel_modeset_init_hw(dev);
02e792fb
DV		 10570
10571 intel_setup_overlay(dev);
24929352 10572
45e2b5f6 10573 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10574}
10575
10576void intel_modeset_cleanup(struct drm_device *dev)
10577{
652c393a
JB		 10578 struct drm_i915_private *dev_priv = dev->dev_private;
10579 struct drm_crtc *crtc;
652c393a 10580
fd0c0642
DV		 10581 /*
10582 * Interrupts and polling as the first thing to avoid creating havoc.
10583 * Too much stuff here (turning of rps, connectors, ...) would
10584 * experience fancy races otherwise.
10585 */
10586 drm_irq_uninstall(dev);
10587 cancel_work_sync(&dev_priv->hotplug_work);
10588 /*
10589 * Due to the hpd irq storm handling the hotplug work can re-arm the
10590 * poll handlers. Hence disable polling after hpd handling is shut down.
10591 */
f87ea761 10592 drm_kms_helper_poll_fini(dev);
fd0c0642 10593
652c393a
JB		 10594 mutex_lock(&dev->struct_mutex);
10595
723bfd70
JB		 10596 intel_unregister_dsm_handler();
10597
652c393a
JB		 10598 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10599 /* Skip inactive CRTCs */
10600 if (!crtc->fb)
10601 continue;
10602
3dec0095 10603 intel_increase_pllclock(crtc);
652c393a
JB		 10604 }
10605
973d04f9 10606 intel_disable_fbc(dev);
e70236a8 10607
81b5c7bc
AW		 10608 i915_enable_vga(dev);
10609
8090c6b9 10610 intel_disable_gt_powersave(dev);
0cdab21f 10611
930ebb46
DV		 10612 ironlake_teardown_rc6(dev);
10613
69341a5e
KH		 10614 mutex_unlock(&dev->struct_mutex);
10615
1630fe75
CW		 10616 /* flush any delayed tasks or pending work */
10617 flush_scheduled_work();
10618
dc652f90
JN		 10619 /* destroy backlight, if any, before the connectors */
10620 intel_panel_destroy_backlight(dev);
10621
79e53945 10622 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10623
10624 intel_cleanup_overlay(dev);
79e53945
JB		 10625}
10626
f1c79df3
ZW		 10627/*
10628 * Return which encoder is currently attached for connector.
10629 */
df0e9248 10630struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10631{
df0e9248
CW		 10632 return &intel_attached_encoder(connector)->base;
10633}
f1c79df3 10634
df0e9248
CW		 10635void intel_connector_attach_encoder(struct intel_connector *connector,
10636 struct intel_encoder *encoder)
10637{
10638 connector->encoder = encoder;
10639 drm_mode_connector_attach_encoder(&connector->base,
10640 &encoder->base);
79e53945 10641}
28d52043
DA		 10642
10643/*
10644 * set vga decode state - true == enable VGA decode
10645 */
10646int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10647{
10648 struct drm_i915_private *dev_priv = dev->dev_private;
10649 u16 gmch_ctrl;
10650
10651 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10652 if (state)
10653 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10654 else
10655 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10656 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10657 return 0;
10658}
c4a1d9e4 10659
c4a1d9e4 10660struct intel_display_error_state {
ff57f1b0
PZ		 10661
10662 u32 power_well_driver;
10663
63b66e5b
CW		 10664 int num_transcoders;
10665
c4a1d9e4
CW		 10666 struct intel_cursor_error_state {
10667 u32 control;
10668 u32 position;
10669 u32 base;
10670 u32 size;
52331309 10671 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10672
10673 struct intel_pipe_error_state {
c4a1d9e4 10674 u32 source;
52331309 10675 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10676
10677 struct intel_plane_error_state {
10678 u32 control;
10679 u32 stride;
10680 u32 size;
10681 u32 pos;
10682 u32 addr;
10683 u32 surface;
10684 u32 tile_offset;
52331309 10685 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10686
10687 struct intel_transcoder_error_state {
10688 enum transcoder cpu_transcoder;
10689
10690 u32 conf;
10691
10692 u32 htotal;
10693 u32 hblank;
10694 u32 hsync;
10695 u32 vtotal;
10696 u32 vblank;
10697 u32 vsync;
10698 } transcoder[4];
c4a1d9e4
CW		 10699};
10700
10701struct intel_display_error_state *
10702intel_display_capture_error_state(struct drm_device *dev)
10703{
0206e353 10704 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10705 struct intel_display_error_state *error;
63b66e5b
CW		 10706 int transcoders[] = {
10707 TRANSCODER_A,
10708 TRANSCODER_B,
10709 TRANSCODER_C,
10710 TRANSCODER_EDP,
10711 };
c4a1d9e4
CW		 10712 int i;
10713
63b66e5b
CW		 10714 if (INTEL_INFO(dev)->num_pipes == 0)
10715 return NULL;
10716
c4a1d9e4
CW		 10717 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10718 if (error == NULL)
10719 return NULL;
10720
ff57f1b0
PZ		 10721 if (HAS_POWER_WELL(dev))
10722 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10723
52331309 10724 for_each_pipe(i) {
a18c4c3d
PZ		 10725 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10726 error->cursor[i].control = I915_READ(CURCNTR(i));
10727 error->cursor[i].position = I915_READ(CURPOS(i));
10728 error->cursor[i].base = I915_READ(CURBASE(i));
10729 } else {
10730 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10731 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10732 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10733 }
c4a1d9e4
CW		 10734
10735 error->plane[i].control = I915_READ(DSPCNTR(i));
10736 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10737 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10738 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10739 error->plane[i].pos = I915_READ(DSPPOS(i));
10740 }
ca291363
PZ		 10741 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10742 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10743 if (INTEL_INFO(dev)->gen >= 4) {
10744 error->plane[i].surface = I915_READ(DSPSURF(i));
10745 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10746 }
10747
c4a1d9e4 10748 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10749 }
10750
10751 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10752 if (HAS_DDI(dev_priv->dev))
10753 error->num_transcoders++; /* Account for eDP. */
10754
10755 for (i = 0; i < error->num_transcoders; i++) {
10756 enum transcoder cpu_transcoder = transcoders[i];
10757
10758 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10759
10760 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10761 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10762 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10763 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10764 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10765 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10766 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10767 }
10768
12d217c7
PZ		 10769 /* In the code above we read the registers without checking if the power
10770 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10771 * prevent the next I915_WRITE from detecting it and printing an error
10772 * message. */
907b28c5 10773 intel_uncore_clear_errors(dev);
12d217c7 10774
c4a1d9e4
CW		 10775 return error;
10776}
10777
edc3d884
MK		 10778#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10779
c4a1d9e4 10780void
edc3d884 10781intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10782 struct drm_device *dev,
10783 struct intel_display_error_state *error)
10784{
10785 int i;
10786
63b66e5b
CW		 10787 if (!error)
10788 return;
10789
edc3d884 10790 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10791 if (HAS_POWER_WELL(dev))
edc3d884 10792 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10793 error->power_well_driver);
52331309 10794 for_each_pipe(i) {
edc3d884 10795 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10796 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10797
10798 err_printf(m, "Plane [%d]:\n", i);
10799 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10800 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10801 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10802 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10803 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10804 }
4b71a570 10805 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10806 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10807 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10808 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10809 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10810 }
10811
edc3d884
MK		 10812 err_printf(m, "Cursor [%d]:\n", i);
10813 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10814 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10815 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10816 }
63b66e5b
CW		 10817
10818 for (i = 0; i < error->num_transcoders; i++) {
10819 err_printf(m, " CPU transcoder: %c\n",
10820 transcoder_name(error->transcoder[i].cpu_transcoder));
10821 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10822 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10823 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10824 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10825 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10826 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10827 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10828 }
c4a1d9e4 10829}
Linux kernel - Deliverables
This page took 2.404738 seconds and 5 git commands to generate.