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drm/i915: Add the ddi get cdclk code for BXT (v3)
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
6b4bf1c4
VS		 421static void vlv_clock(int refclk, intel_clock_t *clock)
422{
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
fb03ac01
VS		 427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 429}
430
cdba954e
ACO		 431static bool
432needs_modeset(struct drm_crtc_state *state)
433{
434 return state->mode_changed || state->active_changed;
435}
436
e0638cdf
PZ		 437/**
438 * Returns whether any output on the specified pipe is of the specified type
439 */
4093561b 440bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 441{
409ee761 442 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 443 struct intel_encoder *encoder;
444
409ee761 445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 446 if (encoder->type == type)
447 return true;
448
449 return false;
450}
451
d0737e1d
ACO		 452/**
453 * Returns whether any output on the specified pipe will have the specified
454 * type after a staged modeset is complete, i.e., the same as
455 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
456 * encoder->crtc.
457 */
a93e255f
ACO		 458static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
459 int type)
d0737e1d 460{
a93e255f 461 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 462 struct drm_connector *connector;
a93e255f 463 struct drm_connector_state *connector_state;
d0737e1d 464 struct intel_encoder *encoder;
a93e255f
ACO		 465 int i, num_connectors = 0;
466
da3ced29 467 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 468 if (connector_state->crtc != crtc_state->base.crtc)
469 continue;
470
471 num_connectors++;
d0737e1d 472
a93e255f
ACO		 473 encoder = to_intel_encoder(connector_state->best_encoder);
474 if (encoder->type == type)
d0737e1d 475 return true;
a93e255f
ACO		 476 }
477
478 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 479
480 return false;
481}
482
a93e255f
ACO		 483static const intel_limit_t *
484intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 485{
a93e255f 486 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 487 const intel_limit_t *limit;
b91ad0ec 488
a93e255f 489 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 490 if (intel_is_dual_link_lvds(dev)) {
1b894b59 491 if (refclk == 100000)
b91ad0ec
ZW		 492 limit = &intel_limits_ironlake_dual_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_dual_lvds;
495 } else {
1b894b59 496 if (refclk == 100000)
b91ad0ec
ZW		 497 limit = &intel_limits_ironlake_single_lvds_100m;
498 else
499 limit = &intel_limits_ironlake_single_lvds;
500 }
c6bb3538 501 } else
b91ad0ec 502 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 503
504 return limit;
505}
506
a93e255f
ACO		 507static const intel_limit_t *
508intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 509{
a93e255f 510 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 511 const intel_limit_t *limit;
512
a93e255f 513 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 514 if (intel_is_dual_link_lvds(dev))
e4b36699 515 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 516 else
e4b36699 517 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
519 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 520 limit = &intel_limits_g4x_hdmi;
a93e255f 521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 522 limit = &intel_limits_g4x_sdvo;
044c7c41 523 } else /* The option is for other outputs */
e4b36699 524 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 525
526 return limit;
527}
528
a93e255f
ACO		 529static const intel_limit_t *
530intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 531{
a93e255f 532 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 533 const intel_limit_t *limit;
534
5ab7b0b7
ID		 535 if (IS_BROXTON(dev))
536 limit = &intel_limits_bxt;
537 else if (HAS_PCH_SPLIT(dev))
a93e255f 538 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
a93e255f 540 limit = intel_g4x_limit(crtc_state);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
a93e255f 542 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 546 } else if (IS_CHERRYVIEW(dev)) {
547 limit = &intel_limits_chv;
a0c4da24 548 } else if (IS_VALLEYVIEW(dev)) {
dc730512 549 limit = &intel_limits_vlv;
a6c45cf0 550 } else if (!IS_GEN2(dev)) {
a93e255f 551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 552 limit = &intel_limits_i9xx_lvds;
553 else
554 limit = &intel_limits_i9xx_sdvo;
79e53945 555 } else {
a93e255f 556 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 557 limit = &intel_limits_i8xx_lvds;
a93e255f 558 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 559 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 560 else
561 limit = &intel_limits_i8xx_dac;
79e53945
JB		 562 }
563 return limit;
564}
565
f2b115e6
AJ		 566/* m1 is reserved as 0 in Pineview, n is a ring counter */
567static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 568{
2177832f
SL		 569 clock->m = clock->m2 + 2;
570 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 571 if (WARN_ON(clock->n == 0 || clock->p == 0))
572 return;
fb03ac01
VS		 573 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
574 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 575}
576
7429e9d4
DV		 577static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578{
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580}
581
ac58c3f0 582static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 583{
7429e9d4 584 clock->m = i9xx_dpll_compute_m(clock);
79e53945 585 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
587 return;
fb03ac01
VS		 588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 590}
591
ef9348c8
CML		 592static void chv_clock(int refclk, intel_clock_t *clock)
593{
594 clock->m = clock->m1 * clock->m2;
595 clock->p = clock->p1 * clock->p2;
596 if (WARN_ON(clock->n == 0 || clock->p == 0))
597 return;
598 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
599 clock->n << 22);
600 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
f01b7962
VS		 613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
79e53945 615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 616 INTELPllInvalid("p1 out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f01b7962 621
5ab7b0b7 622 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 623 if (clock->m1 <= clock->m2)
624 INTELPllInvalid("m1 <= m2\n");
625
5ab7b0b7 626 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 627 if (clock->p < limit->p.min || limit->p.max < clock->p)
628 INTELPllInvalid("p out of range\n");
629 if (clock->m < limit->m.min || limit->m.max < clock->m)
630 INTELPllInvalid("m out of range\n");
631 }
632
79e53945 633 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 634 INTELPllInvalid("vco out of range\n");
79e53945
JB		 635 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
636 * connector, etc., rather than just a single range.
637 */
638 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 639 INTELPllInvalid("dot out of range\n");
79e53945
JB		 640
641 return true;
642}
643
3b1429d9
VS		 644static int
645i9xx_select_p2_div(const intel_limit_t *limit,
646 const struct intel_crtc_state *crtc_state,
647 int target)
79e53945 648{
3b1429d9 649 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 650
a93e255f 651 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 652 /*
a210b028
DV		 653 * For LVDS just rely on its current settings for dual-channel.
654 * We haven't figured out how to reliably set up different
655 * single/dual channel state, if we even can.
79e53945 656 */
1974cad0 657 if (intel_is_dual_link_lvds(dev))
3b1429d9 658 return limit->p2.p2_fast;
79e53945 659 else
3b1429d9 660 return limit->p2.p2_slow;
79e53945
JB		 661 } else {
662 if (target < limit->p2.dot_limit)
3b1429d9 663 return limit->p2.p2_slow;
79e53945 664 else
3b1429d9 665 return limit->p2.p2_fast;
79e53945 666 }
3b1429d9
VS		 667}
668
669static bool
670i9xx_find_best_dpll(const intel_limit_t *limit,
671 struct intel_crtc_state *crtc_state,
672 int target, int refclk, intel_clock_t *match_clock,
673 intel_clock_t *best_clock)
674{
675 struct drm_device *dev = crtc_state->base.crtc->dev;
676 intel_clock_t clock;
677 int err = target;
79e53945 678
0206e353 679 memset(best_clock, 0, sizeof(*best_clock));
79e53945 680
3b1429d9
VS		 681 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
682
42158660
ZY		 683 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
684 clock.m1++) {
685 for (clock.m2 = limit->m2.min;
686 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 687 if (clock.m2 >= clock.m1)
42158660
ZY		 688 break;
689 for (clock.n = limit->n.min;
690 clock.n <= limit->n.max; clock.n++) {
691 for (clock.p1 = limit->p1.min;
692 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 693 int this_err;
694
ac58c3f0
DV		 695 i9xx_clock(refclk, &clock);
696 if (!intel_PLL_is_valid(dev, limit,
697 &clock))
698 continue;
699 if (match_clock &&
700 clock.p != match_clock->p)
701 continue;
702
703 this_err = abs(clock.dot - target);
704 if (this_err < err) {
705 *best_clock = clock;
706 err = this_err;
707 }
708 }
709 }
710 }
711 }
712
713 return (err != target);
714}
715
716static bool
a93e255f
ACO		 717pnv_find_best_dpll(const intel_limit_t *limit,
718 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 719 int target, int refclk, intel_clock_t *match_clock,
720 intel_clock_t *best_clock)
79e53945 721{
3b1429d9 722 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 723 intel_clock_t clock;
79e53945
JB		 724 int err = target;
725
0206e353 726 memset(best_clock, 0, sizeof(*best_clock));
79e53945 727
3b1429d9
VS		 728 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
729
42158660
ZY		 730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 738 int this_err;
739
ac58c3f0 740 pineview_clock(refclk, &clock);
1b894b59
CW		 741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
79e53945 743 continue;
cec2f356
SP		 744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
79e53945
JB		 747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
d4906093 761static bool
a93e255f
ACO		 762g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
d4906093 766{
3b1429d9 767 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 768 intel_clock_t clock;
769 int max_n;
3b1429d9 770 bool found = false;
6ba770dc
AJ		 771 /* approximately equals target * 0.00585 */
772 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 773
774 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
d4906093 778 max_n = limit->n.max;
f77f13e2 779 /* based on hardware requirement, prefer smaller n to precision */
d4906093 780 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 781 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 782 for (clock.m1 = limit->m1.max;
783 clock.m1 >= limit->m1.min; clock.m1--) {
784 for (clock.m2 = limit->m2.max;
785 clock.m2 >= limit->m2.min; clock.m2--) {
786 for (clock.p1 = limit->p1.max;
787 clock.p1 >= limit->p1.min; clock.p1--) {
788 int this_err;
789
ac58c3f0 790 i9xx_clock(refclk, &clock);
1b894b59
CW		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
d4906093 793 continue;
1b894b59
CW		 794
795 this_err = abs(clock.dot - target);
d4906093
ML		 796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 }
802 }
803 }
804 }
805 }
2c07245f
ZW		 806 return found;
807}
808
d5dd62bd
ID		 809/*
810 * Check if the calculated PLL configuration is more optimal compared to the
811 * best configuration and error found so far. Return the calculated error.
812 */
813static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
814 const intel_clock_t *calculated_clock,
815 const intel_clock_t *best_clock,
816 unsigned int best_error_ppm,
817 unsigned int *error_ppm)
818{
9ca3ba01
ID		 819 /*
820 * For CHV ignore the error and consider only the P value.
821 * Prefer a bigger P value based on HW requirements.
822 */
823 if (IS_CHERRYVIEW(dev)) {
824 *error_ppm = 0;
825
826 return calculated_clock->p > best_clock->p;
827 }
828
24be4e46
ID		 829 if (WARN_ON_ONCE(!target_freq))
830 return false;
831
d5dd62bd
ID		 832 *error_ppm = div_u64(1000000ULL *
833 abs(target_freq - calculated_clock->dot),
834 target_freq);
835 /*
836 * Prefer a better P value over a better (smaller) error if the error
837 * is small. Ensure this preference for future configurations too by
838 * setting the error to 0.
839 */
840 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
841 *error_ppm = 0;
842
843 return true;
844 }
845
846 return *error_ppm + 10 < best_error_ppm;
847}
848
a0c4da24 849static bool
a93e255f
ACO		 850vlv_find_best_dpll(const intel_limit_t *limit,
851 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 852 int target, int refclk, intel_clock_t *match_clock,
853 intel_clock_t *best_clock)
a0c4da24 854{
a93e255f 855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 856 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 857 intel_clock_t clock;
69e4f900 858 unsigned int bestppm = 1000000;
27e639bf
VS		 859 /* min update 19.2 MHz */
860 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 861 bool found = false;
a0c4da24 862
6b4bf1c4
VS		 863 target *= 5; /* fast clock */
864
865 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 866
867 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 868 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 869 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 870 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 871 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 872 clock.p = clock.p1 * clock.p2;
a0c4da24 873 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 874 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 875 unsigned int ppm;
69e4f900 876
6b4bf1c4
VS		 877 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
878 refclk * clock.m1);
879
880 vlv_clock(refclk, &clock);
43b0ac53 881
f01b7962
VS		 882 if (!intel_PLL_is_valid(dev, limit,
883 &clock))
43b0ac53
VS		 884 continue;
885
d5dd62bd
ID		 886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
6b4bf1c4 891
d5dd62bd
ID		 892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
a0c4da24
JB		 895 }
896 }
897 }
898 }
a0c4da24 899
49e497ef 900 return found;
a0c4da24 901}
a4fc5ed6 902
ef9348c8 903static bool
a93e255f
ACO		 904chv_find_best_dpll(const intel_limit_t *limit,
905 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 906 int target, int refclk, intel_clock_t *match_clock,
907 intel_clock_t *best_clock)
908{
a93e255f 909 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 910 struct drm_device *dev = crtc->base.dev;
9ca3ba01 911 unsigned int best_error_ppm;
ef9348c8
CML		 912 intel_clock_t clock;
913 uint64_t m2;
914 int found = false;
915
916 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 917 best_error_ppm = 1000000;
ef9348c8
CML		 918
919 /*
920 * Based on hardware doc, the n always set to 1, and m1 always
921 * set to 2. If requires to support 200Mhz refclk, we need to
922 * revisit this because n may not 1 anymore.
923 */
924 clock.n = 1, clock.m1 = 2;
925 target *= 5; /* fast clock */
926
927 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
928 for (clock.p2 = limit->p2.p2_fast;
929 clock.p2 >= limit->p2.p2_slow;
930 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 931 unsigned int error_ppm;
ef9348c8
CML		 932
933 clock.p = clock.p1 * clock.p2;
934
935 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
936 clock.n) << 22, refclk * clock.m1);
937
938 if (m2 > INT_MAX/clock.m1)
939 continue;
940
941 clock.m2 = m2;
942
943 chv_clock(refclk, &clock);
944
945 if (!intel_PLL_is_valid(dev, limit, &clock))
946 continue;
947
9ca3ba01
ID		 948 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
949 best_error_ppm, &error_ppm))
950 continue;
951
952 *best_clock = clock;
953 best_error_ppm = error_ppm;
954 found = true;
ef9348c8
CML		 955 }
956 }
957
958 return found;
959}
960
5ab7b0b7
ID		 961bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
962 intel_clock_t *best_clock)
963{
964 int refclk = i9xx_get_refclk(crtc_state, 0);
965
966 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
967 target_clock, refclk, NULL, best_clock);
968}
969
20ddf665
VS		 970bool intel_crtc_active(struct drm_crtc *crtc)
971{
972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
973
974 /* Be paranoid as we can arrive here with only partial
975 * state retrieved from the hardware during setup.
976 *
241bfc38 977 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 978 * as Haswell has gained clock readout/fastboot support.
979 *
66e514c1 980 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 981 * properly reconstruct framebuffers.
c3d1f436
MR		 982 *
983 * FIXME: The intel_crtc->active here should be switched to
984 * crtc->state->active once we have proper CRTC states wired up
985 * for atomic.
20ddf665 986 */
c3d1f436 987 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 988 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 989}
990
a5c961d1
PZ		 991enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993{
994 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
996
6e3c9717 997 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 998}
999
fbf49ea2
VS		 1000static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1001{
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 u32 reg = PIPEDSL(pipe);
1004 u32 line1, line2;
1005 u32 line_mask;
1006
1007 if (IS_GEN2(dev))
1008 line_mask = DSL_LINEMASK_GEN2;
1009 else
1010 line_mask = DSL_LINEMASK_GEN3;
1011
1012 line1 = I915_READ(reg) & line_mask;
1013 mdelay(5);
1014 line2 = I915_READ(reg) & line_mask;
1015
1016 return line1 == line2;
1017}
1018
ab7ad7f6
KP		 1019/*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1021 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1022 *
1023 * After disabling a pipe, we can't wait for vblank in the usual way,
1024 * spinning on the vblank interrupt status bit, since we won't actually
1025 * see an interrupt when the pipe is disabled.
1026 *
ab7ad7f6
KP		 1027 * On Gen4 and above:
1028 * wait for the pipe register state bit to turn off
1029 *
1030 * Otherwise:
1031 * wait for the display line value to settle (it usually
1032 * ends up stopping at the start of the next frame).
58e10eb9 1033 *
9d0498a2 1034 */
575f7ab7 1035static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1036{
575f7ab7 1037 struct drm_device *dev = crtc->base.dev;
9d0498a2 1038 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1039 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1040 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1041
1042 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1043 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1044
1045 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1046 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1047 100))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 } else {
ab7ad7f6 1050 /* Wait for the display line to settle */
fbf49ea2 1051 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1052 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1053 }
79e53945
JB		 1054}
1055
b0ea7d37
DL		 1056/*
1057 * ibx_digital_port_connected - is the specified port connected?
1058 * @dev_priv: i915 private structure
1059 * @port: the port to test
1060 *
1061 * Returns true if @port is connected, false otherwise.
1062 */
1063bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1064 struct intel_digital_port *port)
1065{
1066 u32 bit;
1067
c36346e3 1068 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1069 switch (port->port) {
c36346e3
DL		 1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG;
1078 break;
1079 default:
1080 return true;
1081 }
1082 } else {
eba905b2 1083 switch (port->port) {
c36346e3
DL		 1084 case PORT_B:
1085 bit = SDE_PORTB_HOTPLUG_CPT;
1086 break;
1087 case PORT_C:
1088 bit = SDE_PORTC_HOTPLUG_CPT;
1089 break;
1090 case PORT_D:
1091 bit = SDE_PORTD_HOTPLUG_CPT;
1092 break;
1093 default:
1094 return true;
1095 }
b0ea7d37
DL		 1096 }
1097
1098 return I915_READ(SDEISR) & bit;
1099}
1100
b24e7179
JB		 1101static const char *state_string(bool enabled)
1102{
1103 return enabled ? "on" : "off";
1104}
1105
1106/* Only for pre-ILK configs */
55607e8a
DV		 1107void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
b24e7179
JB		 1109{
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = DPLL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1117 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
b24e7179 1121
23538ef1
JN		 1122/* XXX: the dsi pll is shared between MIPI DSI ports */
1123static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124{
1125 u32 val;
1126 bool cur_state;
1127
a580516d 1128 mutex_lock(&dev_priv->sb_lock);
23538ef1 1129 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1130 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1131
1132 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
1137#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
55607e8a 1140struct intel_shared_dpll *
e2b78267
DV		 1141intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142{
1143 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
6e3c9717 1145 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1146 return NULL;
1147
6e3c9717 1148 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1149}
1150
040484af 1151/* For ILK+ */
55607e8a
DV		 1152void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153 struct intel_shared_dpll *pll,
1154 bool state)
040484af 1155{
040484af 1156 bool cur_state;
5358901f 1157 struct intel_dpll_hw_state hw_state;
040484af 1158
92b27b08 1159 if (WARN (!pll,
46edb027 1160 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1161 return;
ee7b9f93 1162
5358901f 1163 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1164 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll->name, state_string(state), state_string(cur_state));
040484af 1167}
040484af
JB		 1168
1169static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171{
1172 int reg;
1173 u32 val;
1174 bool cur_state;
ad80a810
PZ		 1175 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176 pipe);
040484af 1177
affa9354
PZ		 1178 if (HAS_DDI(dev_priv->dev)) {
1179 /* DDI does not have a specific FDI_TX register */
ad80a810 1180 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1181 val = I915_READ(reg);
ad80a810 1182 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1183 } else {
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_TX_ENABLE);
1187 }
e2c719b7 1188 I915_STATE_WARN(cur_state != state,
040484af
JB		 1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191}
1192#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197{
1198 int reg;
1199 u32 val;
1200 bool cur_state;
1201
d63fa0dc
PZ		 1202 reg = FDI_RX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1205 I915_STATE_WARN(cur_state != state,
040484af
JB		 1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208}
1209#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214{
1215 int reg;
1216 u32 val;
1217
1218 /* ILK FDI PLL is always enabled */
3d13ef2e 1219 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1220 return;
1221
bf507ef7 1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1223 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1224 return;
1225
040484af
JB		 1226 reg = FDI_TX_CTL(pipe);
1227 val = I915_READ(reg);
e2c719b7 1228 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1229}
1230
55607e8a
DV		 1231void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
040484af
JB		 1233{
1234 int reg;
1235 u32 val;
55607e8a 1236 bool cur_state;
040484af
JB		 1237
1238 reg = FDI_RX_CTL(pipe);
1239 val = I915_READ(reg);
55607e8a 1240 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1241 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state), state_string(cur_state));
040484af
JB		 1244}
1245
b680c37a
DV		 1246void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
ea0760cf 1248{
bedd4dba
JN		 1249 struct drm_device *dev = dev_priv->dev;
1250 int pp_reg;
ea0760cf
JB		 1251 u32 val;
1252 enum pipe panel_pipe = PIPE_A;
0de3b485 1253 bool locked = true;
ea0760cf 1254
bedd4dba
JN		 1255 if (WARN_ON(HAS_DDI(dev)))
1256 return;
1257
1258 if (HAS_PCH_SPLIT(dev)) {
1259 u32 port_sel;
1260
ea0760cf 1261 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1262 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266 panel_pipe = PIPE_B;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271 panel_pipe = pipe;
ea0760cf
JB		 1272 } else {
1273 pp_reg = PP_CONTROL;
bedd4dba
JN		 1274 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275 panel_pipe = PIPE_B;
ea0760cf
JB		 1276 }
1277
1278 val = I915_READ(pp_reg);
1279 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1280 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1281 locked = false;
1282
e2c719b7 1283 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1284 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1285 pipe_name(pipe));
ea0760cf
JB		 1286}
1287
93ce0ba6
JN		 1288static void assert_cursor(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290{
1291 struct drm_device *dev = dev_priv->dev;
1292 bool cur_state;
1293
d9d82081 1294 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1295 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1296 else
5efb3e28 1297 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1298
e2c719b7 1299 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe), state_string(state), state_string(cur_state));
1302}
1303#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
b840d907
JB		 1306void assert_pipe(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
b24e7179
JB		 1308{
1309 int reg;
1310 u32 val;
63d7bbe9 1311 bool cur_state;
702e7a56
PZ		 1312 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313 pipe);
b24e7179 1314
b6b5d049
VS		 1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1318 state = true;
1319
f458ebbc 1320 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1322 cur_state = false;
1323 } else {
1324 reg = PIPECONF(cpu_transcoder);
1325 val = I915_READ(reg);
1326 cur_state = !!(val & PIPECONF_ENABLE);
1327 }
1328
e2c719b7 1329 I915_STATE_WARN(cur_state != state,
63d7bbe9 1330 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1331 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1332}
1333
931872fc
CW		 1334static void assert_plane(struct drm_i915_private *dev_priv,
1335 enum plane plane, bool state)
b24e7179
JB		 1336{
1337 int reg;
1338 u32 val;
931872fc 1339 bool cur_state;
b24e7179
JB		 1340
1341 reg = DSPCNTR(plane);
1342 val = I915_READ(reg);
931872fc 1343 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
b24e7179
JB		 1352static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354{
653e1026 1355 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1356 int reg, i;
1357 u32 val;
1358 int cur_pipe;
1359
653e1026
VS		 1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1362 reg = DSPCNTR(pipe);
1363 val = I915_READ(reg);
e2c719b7 1364 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1365 "plane %c assertion failure, should be disabled but not\n",
1366 plane_name(pipe));
19ec1358 1367 return;
28c05794 1368 }
19ec1358 1369
b24e7179 1370 /* Need to check both planes against the pipe */
055e393f 1371 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1372 reg = DSPCNTR(i);
1373 val = I915_READ(reg);
1374 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1376 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1379 }
1380}
1381
19332d7a
JB		 1382static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384{
20674eef 1385 struct drm_device *dev = dev_priv->dev;
1fe47785 1386 int reg, sprite;
19332d7a
JB		 1387 u32 val;
1388
7feb8b88 1389 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1390 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1391 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1392 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite, pipe_name(pipe));
1395 }
1396 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1397 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1398 reg = SPCNTR(pipe, sprite);
20674eef 1399 val = I915_READ(reg);
e2c719b7 1400 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1402 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1403 }
1404 } else if (INTEL_INFO(dev)->gen >= 7) {
1405 reg = SPRCTL(pipe);
19332d7a 1406 val = I915_READ(reg);
e2c719b7 1407 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1409 plane_name(pipe), pipe_name(pipe));
1410 } else if (INTEL_INFO(dev)->gen >= 5) {
1411 reg = DVSCNTR(pipe);
19332d7a 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1415 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1416 }
1417}
1418
08c71e5e
VS		 1419static void assert_vblank_disabled(struct drm_crtc *crtc)
1420{
e2c719b7 1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1422 drm_crtc_vblank_put(crtc);
1423}
1424
89eff4be 1425static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1426{
1427 u32 val;
1428 bool enabled;
1429
e2c719b7 1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1431
92f2584a
JB		 1432 val = I915_READ(PCH_DREF_CONTROL);
1433 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1435 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1436}
1437
ab9412ba
DV		 1438static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
92f2584a
JB		 1440{
1441 int reg;
1442 u32 val;
1443 bool enabled;
1444
ab9412ba 1445 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1446 val = I915_READ(reg);
1447 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1448 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450 pipe_name(pipe));
92f2584a
JB		 1451}
1452
4e634389
KP		 1453static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1455{
1456 if ((val & DP_PORT_EN) == 0)
1457 return false;
1458
1459 if (HAS_PCH_CPT(dev_priv->dev)) {
1460 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463 return false;
44f37d1f
CML		 1464 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466 return false;
f0575e92
KP		 1467 } else {
1468 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469 return false;
1470 }
1471 return true;
1472}
1473
1519b995
KP		 1474static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 val)
1476{
dc0fa718 1477 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1481 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1482 return false;
44f37d1f
CML		 1483 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485 return false;
1519b995 1486 } else {
dc0fa718 1487 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1488 return false;
1489 }
1490 return true;
1491}
1492
1493static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, u32 val)
1495{
1496 if ((val & LVDS_PORT_EN) == 0)
1497 return false;
1498
1499 if (HAS_PCH_CPT(dev_priv->dev)) {
1500 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501 return false;
1502 } else {
1503 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & ADPA_DAC_ENABLE) == 0)
1513 return false;
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
291906f1 1524static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1525 enum pipe pipe, int reg, u32 port_sel)
291906f1 1526{
47a05eca 1527 u32 val = I915_READ(reg);
e2c719b7 1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1530 reg, pipe_name(pipe));
de9a35ab 1531
e2c719b7 1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1533 && (val & DP_PIPEB_SELECT),
de9a35ab 1534 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1535}
1536
1537static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, int reg)
1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1546 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1547 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe)
1552{
1553 int reg;
1554 u32 val;
291906f1 1555
f0575e92
KP		 1556 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1559
1560 reg = PCH_ADPA;
1561 val = I915_READ(reg);
e2c719b7 1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1564 pipe_name(pipe));
291906f1
JB		 1565
1566 reg = PCH_LVDS;
1567 val = I915_READ(reg);
e2c719b7 1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1570 pipe_name(pipe));
291906f1 1571
e2debe91
PZ		 1572 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1575}
1576
40e9cf64
JB		 1577static void intel_init_dpio(struct drm_device *dev)
1578{
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 if (!IS_VALLEYVIEW(dev))
1582 return;
1583
a09caddd
CML		 1584 /*
1585 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1586 * CHV x1 PHY (DP/HDMI D)
1587 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588 */
1589 if (IS_CHERRYVIEW(dev)) {
1590 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592 } else {
1593 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594 }
5382f5f3
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
50b44a44
DV		 1777 I915_WRITE(DPLL(pipe), 0);
1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
1783 u32 val = 0;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
f6071166 1792 if (pipe == PIPE_B)
e5cbfbfb 1793 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1794 I915_WRITE(DPLL(pipe), val);
1795 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1796
1797}
1798
1799static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800{
d752048d 1801 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1802 u32 val;
1803
a11b0703
VS		 1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1806
a11b0703 1807 /* Set PLL en = 0 */
d17ec4ce 1808 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1809 if (pipe != PIPE_A)
1810 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
d752048d 1813
a580516d 1814 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1815
1816 /* Disable 10bit clock to display controller */
1817 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1818 val &= ~DPIO_DCLKP_EN;
1819 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1820
61407f6d
VS		 1821 /* disable left/right clock distribution */
1822 if (pipe != PIPE_B) {
1823 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1824 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1825 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1826 } else {
1827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830 }
1831
a580516d 1832 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1833}
1834
e4607fcf 1835void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
89b667f8
JB		 1838{
1839 u32 port_mask;
00fc31b7 1840 int dpll_reg;
89b667f8 1841
e4607fcf
CML		 1842 switch (dport->port) {
1843 case PORT_B:
89b667f8 1844 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1845 dpll_reg = DPLL(0);
e4607fcf
CML		 1846 break;
1847 case PORT_C:
89b667f8 1848 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1849 dpll_reg = DPLL(0);
9b6de0a1 1850 expected_mask <<= 4;
00fc31b7
CML		 1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1855 break;
1856 default:
1857 BUG();
1858 }
89b667f8 1859
9b6de0a1
VS		 1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1863}
1864
b14b1055
DV		 1865static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866{
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
be19f0ff
CW		 1871 if (WARN_ON(pll == NULL))
1872 return;
1873
3e369b76 1874 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882}
1883
92f2584a 1884/**
85b3894f 1885 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
85b3894f 1892static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1893{
3d13ef2e
DL		 1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1897
87a875bb 1898 if (WARN_ON(pll == NULL))
48da64a8
CW		 1899 return;
1900
3e369b76 1901 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1902 return;
ee7b9f93 1903
74dd6928 1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1905 pll->name, pll->active, pll->on,
e2b78267 1906 crtc->base.base.id);
92f2584a 1907
cdbd2316
DV		 1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
e9d6944e 1910 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1911 return;
1912 }
f4a091c7 1913 WARN_ON(pll->on);
ee7b9f93 1914
bd2bb1b9
PZ		 1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
46edb027 1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1918 pll->enable(dev_priv, pll);
ee7b9f93 1919 pll->on = true;
92f2584a
JB		 1920}
1921
f6daaec2 1922static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1923{
3d13ef2e
DL		 1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1927
92f2584a 1928 /* PCH only available on ILK+ */
3d13ef2e 1929 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1930 if (pll == NULL)
1931 return;
92f2584a 1932
eddfcbcd 1933 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1934 return;
7a419866 1935
46edb027
DV		 1936 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937 pll->name, pll->active, pll->on,
e2b78267 1938 crtc->base.base.id);
7a419866 1939
48da64a8 1940 if (WARN_ON(pll->active == 0)) {
e9d6944e 1941 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1942 return;
1943 }
1944
e9d6944e 1945 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1946 WARN_ON(!pll->on);
cdbd2316 1947 if (--pll->active)
7a419866 1948 return;
ee7b9f93 1949
46edb027 1950 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1951 pll->disable(dev_priv, pll);
ee7b9f93 1952 pll->on = false;
bd2bb1b9
PZ		 1953
1954 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1955}
1956
b8a4f404
PZ		 1957static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 enum pipe pipe)
040484af 1959{
23670b32 1960 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1961 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1963 uint32_t reg, val, pipeconf_val;
040484af
JB		 1964
1965 /* PCH only available on ILK+ */
55522f37 1966 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1967
1968 /* Make sure PCH DPLL is enabled */
e72f9fbf 1969 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1970 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1971
1972 /* FDI must be feeding us bits for PCH ports */
1973 assert_fdi_tx_enabled(dev_priv, pipe);
1974 assert_fdi_rx_enabled(dev_priv, pipe);
1975
23670b32
DV		 1976 if (HAS_PCH_CPT(dev)) {
1977 /* Workaround: Set the timing override bit before enabling the
1978 * pch transcoder. */
1979 reg = TRANS_CHICKEN2(pipe);
1980 val = I915_READ(reg);
1981 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982 I915_WRITE(reg, val);
59c859d6 1983 }
23670b32 1984
ab9412ba 1985 reg = PCH_TRANSCONF(pipe);
040484af 1986 val = I915_READ(reg);
5f7f726d 1987 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1988
1989 if (HAS_PCH_IBX(dev_priv->dev)) {
1990 /*
c5de7c6f
VS		 1991 * Make the BPC in transcoder be consistent with
1992 * that in pipeconf reg. For HDMI we must use 8bpc
1993 * here for both 8bpc and 12bpc.
e9bcff5c 1994 */
dfd07d72 1995 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1996 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997 val |= PIPECONF_8BPC;
1998 else
1999 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2000 }
5f7f726d
PZ		 2001
2002 val &= ~TRANS_INTERLACE_MASK;
2003 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2004 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2005 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2006 val |= TRANS_LEGACY_INTERLACED_ILK;
2007 else
2008 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2009 else
2010 val |= TRANS_PROGRESSIVE;
2011
040484af
JB		 2012 I915_WRITE(reg, val | TRANS_ENABLE);
2013 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2014 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2015}
2016
8fb033d7 2017static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2018 enum transcoder cpu_transcoder)
040484af 2019{
8fb033d7 2020 u32 val, pipeconf_val;
8fb033d7
PZ		 2021
2022 /* PCH only available on ILK+ */
55522f37 2023 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2024
8fb033d7 2025 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2026 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2027 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2028
223a6fdf
PZ		 2029 /* Workaround: set timing override bit. */
2030 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2031 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2032 I915_WRITE(_TRANSA_CHICKEN2, val);
2033
25f3ef11 2034 val = TRANS_ENABLE;
937bb610 2035 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2036
9a76b1c6
PZ		 2037 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038 PIPECONF_INTERLACED_ILK)
a35f2679 2039 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2040 else
2041 val |= TRANS_PROGRESSIVE;
2042
ab9412ba
DV		 2043 I915_WRITE(LPT_TRANSCONF, val);
2044 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2045 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2046}
2047
b8a4f404
PZ		 2048static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049 enum pipe pipe)
040484af 2050{
23670b32
DV		 2051 struct drm_device *dev = dev_priv->dev;
2052 uint32_t reg, val;
040484af
JB		 2053
2054 /* FDI relies on the transcoder */
2055 assert_fdi_tx_disabled(dev_priv, pipe);
2056 assert_fdi_rx_disabled(dev_priv, pipe);
2057
291906f1
JB		 2058 /* Ports must be off as well */
2059 assert_pch_ports_disabled(dev_priv, pipe);
2060
ab9412ba 2061 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2062 val = I915_READ(reg);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(reg, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2067 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2068
2069 if (!HAS_PCH_IBX(dev)) {
2070 /* Workaround: Clear the timing override chicken bit again. */
2071 reg = TRANS_CHICKEN2(pipe);
2072 val = I915_READ(reg);
2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2074 I915_WRITE(reg, val);
2075 }
040484af
JB		 2076}
2077
ab4d966c 2078static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2079{
8fb033d7
PZ		 2080 u32 val;
2081
ab9412ba 2082 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2083 val &= ~TRANS_ENABLE;
ab9412ba 2084 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2085 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2086 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2087 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2088
2089 /* Workaround: clear timing override bit. */
2090 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2092 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2093}
2094
b24e7179 2095/**
309cfea8 2096 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2097 * @crtc: crtc responsible for the pipe
b24e7179 2098 *
0372264a 2099 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2100 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2101 */
e1fdc473 2102static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2103{
0372264a
PZ		 2104 struct drm_device *dev = crtc->base.dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2107 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2108 pipe);
1a240d4d 2109 enum pipe pch_transcoder;
b24e7179
JB		 2110 int reg;
2111 u32 val;
2112
58c6eaa2 2113 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2114 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2115 assert_sprites_disabled(dev_priv, pipe);
2116
681e5811 2117 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2118 pch_transcoder = TRANSCODER_A;
2119 else
2120 pch_transcoder = pipe;
2121
b24e7179
JB		 2122 /*
2123 * A pipe without a PLL won't actually be able to drive bits from
2124 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2125 * need the check.
2126 */
50360403 2127 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2129 assert_dsi_pll_enabled(dev_priv);
2130 else
2131 assert_pll_enabled(dev_priv, pipe);
040484af 2132 else {
6e3c9717 2133 if (crtc->config->has_pch_encoder) {
040484af 2134 /* if driving the PCH, we need FDI enabled */
cc391bbb 2135 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2136 assert_fdi_tx_pll_enabled(dev_priv,
2137 (enum pipe) cpu_transcoder);
040484af
JB		 2138 }
2139 /* FIXME: assert CPU port conditions for SNB+ */
2140 }
b24e7179 2141
702e7a56 2142 reg = PIPECONF(cpu_transcoder);
b24e7179 2143 val = I915_READ(reg);
7ad25d48 2144 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2145 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2146 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2147 return;
7ad25d48 2148 }
00d70b15
CW		 2149
2150 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2151 POSTING_READ(reg);
b24e7179
JB		 2152}
2153
2154/**
309cfea8 2155 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2156 * @crtc: crtc whose pipes is to be disabled
b24e7179 2157 *
575f7ab7
VS		 2158 * Disable the pipe of @crtc, making sure that various hardware
2159 * specific requirements are met, if applicable, e.g. plane
2160 * disabled, panel fitter off, etc.
b24e7179
JB		 2161 *
2162 * Will wait until the pipe has shut down before returning.
2163 */
575f7ab7 2164static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2165{
575f7ab7 2166 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2167 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2168 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2169 int reg;
2170 u32 val;
2171
2172 /*
2173 * Make sure planes won't keep trying to pump pixels to us,
2174 * or we might hang the display.
2175 */
2176 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2177 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2178 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2179
702e7a56 2180 reg = PIPECONF(cpu_transcoder);
b24e7179 2181 val = I915_READ(reg);
00d70b15
CW		 2182 if ((val & PIPECONF_ENABLE) == 0)
2183 return;
2184
67adc644
VS		 2185 /*
2186 * Double wide has implications for planes
2187 * so best keep it disabled when not needed.
2188 */
6e3c9717 2189 if (crtc->config->double_wide)
67adc644
VS		 2190 val &= ~PIPECONF_DOUBLE_WIDE;
2191
2192 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2193 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2194 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2195 val &= ~PIPECONF_ENABLE;
2196
2197 I915_WRITE(reg, val);
2198 if ((val & PIPECONF_ENABLE) == 0)
2199 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2200}
2201
693db184
CW		 2202static bool need_vtd_wa(struct drm_device *dev)
2203{
2204#ifdef CONFIG_INTEL_IOMMU
2205 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2206 return true;
2207#endif
2208 return false;
2209}
2210
50470bb0 2211unsigned int
6761dd31
TU		 2212intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2213 uint64_t fb_format_modifier)
a57ce0b2 2214{
6761dd31
TU		 2215 unsigned int tile_height;
2216 uint32_t pixel_bytes;
a57ce0b2 2217
b5d0e9bf
DL		 2218 switch (fb_format_modifier) {
2219 case DRM_FORMAT_MOD_NONE:
2220 tile_height = 1;
2221 break;
2222 case I915_FORMAT_MOD_X_TILED:
2223 tile_height = IS_GEN2(dev) ? 16 : 8;
2224 break;
2225 case I915_FORMAT_MOD_Y_TILED:
2226 tile_height = 32;
2227 break;
2228 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2229 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2230 switch (pixel_bytes) {
b5d0e9bf 2231 default:
6761dd31 2232 case 1:
b5d0e9bf
DL		 2233 tile_height = 64;
2234 break;
6761dd31
TU		 2235 case 2:
2236 case 4:
b5d0e9bf
DL		 2237 tile_height = 32;
2238 break;
6761dd31 2239 case 8:
b5d0e9bf
DL		 2240 tile_height = 16;
2241 break;
6761dd31 2242 case 16:
b5d0e9bf
DL		 2243 WARN_ONCE(1,
2244 "128-bit pixels are not supported for display!");
2245 tile_height = 16;
2246 break;
2247 }
2248 break;
2249 default:
2250 MISSING_CASE(fb_format_modifier);
2251 tile_height = 1;
2252 break;
2253 }
091df6cb 2254
6761dd31
TU		 2255 return tile_height;
2256}
2257
2258unsigned int
2259intel_fb_align_height(struct drm_device *dev, unsigned int height,
2260 uint32_t pixel_format, uint64_t fb_format_modifier)
2261{
2262 return ALIGN(height, intel_tile_height(dev, pixel_format,
2263 fb_format_modifier));
a57ce0b2
JB		 2264}
2265
f64b98cd
TU		 2266static int
2267intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2268 const struct drm_plane_state *plane_state)
2269{
50470bb0 2270 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2271 unsigned int tile_height, tile_pitch;
50470bb0 2272
f64b98cd
TU		 2273 *view = i915_ggtt_view_normal;
2274
50470bb0
TU		 2275 if (!plane_state)
2276 return 0;
2277
121920fa 2278 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2279 return 0;
2280
9abc4648 2281 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2282
2283 info->height = fb->height;
2284 info->pixel_format = fb->pixel_format;
2285 info->pitch = fb->pitches[0];
2286 info->fb_modifier = fb->modifier[0];
2287
84fe03f7
TU		 2288 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2289 fb->modifier[0]);
2290 tile_pitch = PAGE_SIZE / tile_height;
2291 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2292 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2293 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2294
f64b98cd
TU		 2295 return 0;
2296}
2297
4e9a86b6
VS		 2298static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2299{
2300 if (INTEL_INFO(dev_priv)->gen >= 9)
2301 return 256 * 1024;
985b8bb4
VS		 2302 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2303 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2304 return 128 * 1024;
2305 else if (INTEL_INFO(dev_priv)->gen >= 4)
2306 return 4 * 1024;
2307 else
44c5905e 2308 return 0;
4e9a86b6
VS		 2309}
2310
127bd2ac 2311int
850c4cdc
TU		 2312intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2313 struct drm_framebuffer *fb,
82bc3b2d 2314 const struct drm_plane_state *plane_state,
91af127f
JH		 2315 struct intel_engine_cs *pipelined,
2316 struct drm_i915_gem_request **pipelined_request)
6b95a207 2317{
850c4cdc 2318 struct drm_device *dev = fb->dev;
ce453d81 2319 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2320 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2321 struct i915_ggtt_view view;
6b95a207
KH		 2322 u32 alignment;
2323 int ret;
2324
ebcdd39e
MR		 2325 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2326
7b911adc
TU		 2327 switch (fb->modifier[0]) {
2328 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2329 alignment = intel_linear_alignment(dev_priv);
6b95a207 2330 break;
7b911adc 2331 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2332 if (INTEL_INFO(dev)->gen >= 9)
2333 alignment = 256 * 1024;
2334 else {
2335 /* pin() will align the object as required by fence */
2336 alignment = 0;
2337 }
6b95a207 2338 break;
7b911adc 2339 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2340 case I915_FORMAT_MOD_Yf_TILED:
2341 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2342 "Y tiling bo slipped through, driver bug!\n"))
2343 return -EINVAL;
2344 alignment = 1 * 1024 * 1024;
2345 break;
6b95a207 2346 default:
7b911adc
TU		 2347 MISSING_CASE(fb->modifier[0]);
2348 return -EINVAL;
6b95a207
KH		 2349 }
2350
f64b98cd
TU		 2351 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2352 if (ret)
2353 return ret;
2354
693db184
CW		 2355 /* Note that the w/a also requires 64 PTE of padding following the
2356 * bo. We currently fill all unused PTE with the shadow page and so
2357 * we should always have valid PTE following the scanout preventing
2358 * the VT-d warning.
2359 */
2360 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2361 alignment = 256 * 1024;
2362
d6dd6843
PZ		 2363 /*
2364 * Global gtt pte registers are special registers which actually forward
2365 * writes to a chunk of system memory. Which means that there is no risk
2366 * that the register values disappear as soon as we call
2367 * intel_runtime_pm_put(), so it is correct to wrap only the
2368 * pin/unpin/fence and not more.
2369 */
2370 intel_runtime_pm_get(dev_priv);
2371
ce453d81 2372 dev_priv->mm.interruptible = false;
e6617330 2373 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2374 pipelined_request, &view);
48b956c5 2375 if (ret)
ce453d81 2376 goto err_interruptible;
6b95a207
KH		 2377
2378 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2379 * fence, whereas 965+ only requires a fence if using
2380 * framebuffer compression. For simplicity, we always install
2381 * a fence as the cost is not that onerous.
2382 */
06d98131 2383 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2384 if (ret)
2385 goto err_unpin;
1690e1eb 2386
9a5a53b3 2387 i915_gem_object_pin_fence(obj);
6b95a207 2388
ce453d81 2389 dev_priv->mm.interruptible = true;
d6dd6843 2390 intel_runtime_pm_put(dev_priv);
6b95a207 2391 return 0;
48b956c5
CW		 2392
2393err_unpin:
f64b98cd 2394 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2395err_interruptible:
2396 dev_priv->mm.interruptible = true;
d6dd6843 2397 intel_runtime_pm_put(dev_priv);
48b956c5 2398 return ret;
6b95a207
KH		 2399}
2400
82bc3b2d
TU		 2401static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2402 const struct drm_plane_state *plane_state)
1690e1eb 2403{
82bc3b2d 2404 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2405 struct i915_ggtt_view view;
2406 int ret;
82bc3b2d 2407
ebcdd39e
MR		 2408 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2409
f64b98cd
TU		 2410 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2411 WARN_ONCE(ret, "Couldn't get view from plane state!");
2412
1690e1eb 2413 i915_gem_object_unpin_fence(obj);
f64b98cd 2414 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2415}
2416
c2c75131
DV		 2417/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2418 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2419unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2420 int *x, int *y,
bc752862
CW		 2421 unsigned int tiling_mode,
2422 unsigned int cpp,
2423 unsigned int pitch)
c2c75131 2424{
bc752862
CW		 2425 if (tiling_mode != I915_TILING_NONE) {
2426 unsigned int tile_rows, tiles;
c2c75131 2427
bc752862
CW		 2428 tile_rows = *y / 8;
2429 *y %= 8;
c2c75131 2430
bc752862
CW		 2431 tiles = *x / (512/cpp);
2432 *x %= 512/cpp;
2433
2434 return tile_rows * pitch * 8 + tiles * 4096;
2435 } else {
4e9a86b6 2436 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2437 unsigned int offset;
2438
2439 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2440 *y = (offset & alignment) / pitch;
2441 *x = ((offset & alignment) - *y * pitch) / cpp;
2442 return offset & ~alignment;
bc752862 2443 }
c2c75131
DV		 2444}
2445
b35d63fa 2446static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2447{
2448 switch (format) {
2449 case DISPPLANE_8BPP:
2450 return DRM_FORMAT_C8;
2451 case DISPPLANE_BGRX555:
2452 return DRM_FORMAT_XRGB1555;
2453 case DISPPLANE_BGRX565:
2454 return DRM_FORMAT_RGB565;
2455 default:
2456 case DISPPLANE_BGRX888:
2457 return DRM_FORMAT_XRGB8888;
2458 case DISPPLANE_RGBX888:
2459 return DRM_FORMAT_XBGR8888;
2460 case DISPPLANE_BGRX101010:
2461 return DRM_FORMAT_XRGB2101010;
2462 case DISPPLANE_RGBX101010:
2463 return DRM_FORMAT_XBGR2101010;
2464 }
2465}
2466
bc8d7dff
DL		 2467static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2468{
2469 switch (format) {
2470 case PLANE_CTL_FORMAT_RGB_565:
2471 return DRM_FORMAT_RGB565;
2472 default:
2473 case PLANE_CTL_FORMAT_XRGB_8888:
2474 if (rgb_order) {
2475 if (alpha)
2476 return DRM_FORMAT_ABGR8888;
2477 else
2478 return DRM_FORMAT_XBGR8888;
2479 } else {
2480 if (alpha)
2481 return DRM_FORMAT_ARGB8888;
2482 else
2483 return DRM_FORMAT_XRGB8888;
2484 }
2485 case PLANE_CTL_FORMAT_XRGB_2101010:
2486 if (rgb_order)
2487 return DRM_FORMAT_XBGR2101010;
2488 else
2489 return DRM_FORMAT_XRGB2101010;
2490 }
2491}
2492
5724dbd1 2493static bool
f6936e29
DV		 2494intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2495 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2496{
2497 struct drm_device *dev = crtc->base.dev;
2498 struct drm_i915_gem_object *obj = NULL;
2499 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2500 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2501 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2502 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2503 PAGE_SIZE);
2504
2505 size_aligned -= base_aligned;
46f297fb 2506
ff2652ea
CW		 2507 if (plane_config->size == 0)
2508 return false;
2509
f37b5c2b
DV		 2510 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2511 base_aligned,
2512 base_aligned,
2513 size_aligned);
46f297fb 2514 if (!obj)
484b41dd 2515 return false;
46f297fb 2516
49af449b
DL		 2517 obj->tiling_mode = plane_config->tiling;
2518 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2519 obj->stride = fb->pitches[0];
46f297fb 2520
6bf129df
DL		 2521 mode_cmd.pixel_format = fb->pixel_format;
2522 mode_cmd.width = fb->width;
2523 mode_cmd.height = fb->height;
2524 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2525 mode_cmd.modifier[0] = fb->modifier[0];
2526 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2527
2528 mutex_lock(&dev->struct_mutex);
6bf129df 2529 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2530 &mode_cmd, obj)) {
46f297fb
JB		 2531 DRM_DEBUG_KMS("intel fb init failed\n");
2532 goto out_unref_obj;
2533 }
46f297fb 2534 mutex_unlock(&dev->struct_mutex);
484b41dd 2535
f6936e29 2536 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2537 return true;
46f297fb
JB		 2538
2539out_unref_obj:
2540 drm_gem_object_unreference(&obj->base);
2541 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2542 return false;
2543}
2544
afd65eb4
MR		 2545/* Update plane->state->fb to match plane->fb after driver-internal updates */
2546static void
2547update_state_fb(struct drm_plane *plane)
2548{
2549 if (plane->fb == plane->state->fb)
2550 return;
2551
2552 if (plane->state->fb)
2553 drm_framebuffer_unreference(plane->state->fb);
2554 plane->state->fb = plane->fb;
2555 if (plane->state->fb)
2556 drm_framebuffer_reference(plane->state->fb);
2557}
2558
5724dbd1 2559static void
f6936e29
DV		 2560intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2561 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2562{
2563 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2564 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2565 struct drm_crtc *c;
2566 struct intel_crtc *i;
2ff8fde1 2567 struct drm_i915_gem_object *obj;
88595ac9
DV		 2568 struct drm_plane *primary = intel_crtc->base.primary;
2569 struct drm_framebuffer *fb;
484b41dd 2570
2d14030b 2571 if (!plane_config->fb)
484b41dd
JB		 2572 return;
2573
f6936e29 2574 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2575 fb = &plane_config->fb->base;
2576 goto valid_fb;
f55548b5 2577 }
484b41dd 2578
2d14030b 2579 kfree(plane_config->fb);
484b41dd
JB		 2580
2581 /*
2582 * Failed to alloc the obj, check to see if we should share
2583 * an fb with another CRTC instead
2584 */
70e1e0ec 2585 for_each_crtc(dev, c) {
484b41dd
JB		 2586 i = to_intel_crtc(c);
2587
2588 if (c == &intel_crtc->base)
2589 continue;
2590
2ff8fde1
MR		 2591 if (!i->active)
2592 continue;
2593
88595ac9
DV		 2594 fb = c->primary->fb;
2595 if (!fb)
484b41dd
JB		 2596 continue;
2597
88595ac9 2598 obj = intel_fb_obj(fb);
2ff8fde1 2599 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2600 drm_framebuffer_reference(fb);
2601 goto valid_fb;
484b41dd
JB		 2602 }
2603 }
88595ac9
DV		 2604
2605 return;
2606
2607valid_fb:
2608 obj = intel_fb_obj(fb);
2609 if (obj->tiling_mode != I915_TILING_NONE)
2610 dev_priv->preserve_bios_swizzle = true;
2611
2612 primary->fb = fb;
36750f28 2613 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2614 update_state_fb(primary);
36750f28 2615 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
88595ac9 2616 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2617}
2618
29b9bde6
DV		 2619static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2620 struct drm_framebuffer *fb,
2621 int x, int y)
81255565
JB		 2622{
2623 struct drm_device *dev = crtc->dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2626 struct drm_plane *primary = crtc->primary;
2627 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2628 struct drm_i915_gem_object *obj;
81255565 2629 int plane = intel_crtc->plane;
e506a0c6 2630 unsigned long linear_offset;
81255565 2631 u32 dspcntr;
f45651ba 2632 u32 reg = DSPCNTR(plane);
48404c1e 2633 int pixel_size;
f45651ba 2634
b70709a6 2635 if (!visible || !fb) {
fdd508a6
VS		 2636 I915_WRITE(reg, 0);
2637 if (INTEL_INFO(dev)->gen >= 4)
2638 I915_WRITE(DSPSURF(plane), 0);
2639 else
2640 I915_WRITE(DSPADDR(plane), 0);
2641 POSTING_READ(reg);
2642 return;
2643 }
2644
c9ba6fad
VS		 2645 obj = intel_fb_obj(fb);
2646 if (WARN_ON(obj == NULL))
2647 return;
2648
2649 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2650
f45651ba
VS		 2651 dspcntr = DISPPLANE_GAMMA_ENABLE;
2652
fdd508a6 2653 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2654
2655 if (INTEL_INFO(dev)->gen < 4) {
2656 if (intel_crtc->pipe == PIPE_B)
2657 dspcntr |= DISPPLANE_SEL_PIPE_B;
2658
2659 /* pipesrc and dspsize control the size that is scaled from,
2660 * which should always be the user's requested size.
2661 */
2662 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2663 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2664 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2665 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2666 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2667 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2668 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2669 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2670 I915_WRITE(PRIMPOS(plane), 0);
2671 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2672 }
81255565 2673
57779d06
VS		 2674 switch (fb->pixel_format) {
2675 case DRM_FORMAT_C8:
81255565
JB		 2676 dspcntr |= DISPPLANE_8BPP;
2677 break;
57779d06 2678 case DRM_FORMAT_XRGB1555:
57779d06 2679 dspcntr |= DISPPLANE_BGRX555;
81255565 2680 break;
57779d06
VS		 2681 case DRM_FORMAT_RGB565:
2682 dspcntr |= DISPPLANE_BGRX565;
2683 break;
2684 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2685 dspcntr |= DISPPLANE_BGRX888;
2686 break;
2687 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2688 dspcntr |= DISPPLANE_RGBX888;
2689 break;
2690 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2691 dspcntr |= DISPPLANE_BGRX101010;
2692 break;
2693 case DRM_FORMAT_XBGR2101010:
57779d06 2694 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2695 break;
2696 default:
baba133a 2697 BUG();
81255565 2698 }
57779d06 2699
f45651ba
VS		 2700 if (INTEL_INFO(dev)->gen >= 4 &&
2701 obj->tiling_mode != I915_TILING_NONE)
2702 dspcntr |= DISPPLANE_TILED;
81255565 2703
de1aa629
VS		 2704 if (IS_G4X(dev))
2705 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2706
b9897127 2707 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2708
c2c75131
DV		 2709 if (INTEL_INFO(dev)->gen >= 4) {
2710 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2711 intel_gen4_compute_page_offset(dev_priv,
2712 &x, &y, obj->tiling_mode,
b9897127 2713 pixel_size,
bc752862 2714 fb->pitches[0]);
c2c75131
DV		 2715 linear_offset -= intel_crtc->dspaddr_offset;
2716 } else {
e506a0c6 2717 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2718 }
e506a0c6 2719
8e7d688b 2720 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2721 dspcntr |= DISPPLANE_ROTATE_180;
2722
6e3c9717
ACO		 2723 x += (intel_crtc->config->pipe_src_w - 1);
2724 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2725
2726 /* Finding the last pixel of the last line of the display
2727 data and adding to linear_offset*/
2728 linear_offset +=
6e3c9717
ACO		 2729 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2730 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2731 }
2732
2733 I915_WRITE(reg, dspcntr);
2734
01f2c773 2735 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2736 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2737 I915_WRITE(DSPSURF(plane),
2738 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2739 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2740 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2741 } else
f343c5f6 2742 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2743 POSTING_READ(reg);
17638cd6
JB		 2744}
2745
29b9bde6
DV		 2746static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2747 struct drm_framebuffer *fb,
2748 int x, int y)
17638cd6
JB		 2749{
2750 struct drm_device *dev = crtc->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2753 struct drm_plane *primary = crtc->primary;
2754 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2755 struct drm_i915_gem_object *obj;
17638cd6 2756 int plane = intel_crtc->plane;
e506a0c6 2757 unsigned long linear_offset;
17638cd6 2758 u32 dspcntr;
f45651ba 2759 u32 reg = DSPCNTR(plane);
48404c1e 2760 int pixel_size;
f45651ba 2761
b70709a6 2762 if (!visible || !fb) {
fdd508a6
VS		 2763 I915_WRITE(reg, 0);
2764 I915_WRITE(DSPSURF(plane), 0);
2765 POSTING_READ(reg);
2766 return;
2767 }
2768
c9ba6fad
VS		 2769 obj = intel_fb_obj(fb);
2770 if (WARN_ON(obj == NULL))
2771 return;
2772
2773 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2774
f45651ba
VS		 2775 dspcntr = DISPPLANE_GAMMA_ENABLE;
2776
fdd508a6 2777 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2778
2779 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2780 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2781
57779d06
VS		 2782 switch (fb->pixel_format) {
2783 case DRM_FORMAT_C8:
17638cd6
JB		 2784 dspcntr |= DISPPLANE_8BPP;
2785 break;
57779d06
VS		 2786 case DRM_FORMAT_RGB565:
2787 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2788 break;
57779d06 2789 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2790 dspcntr |= DISPPLANE_BGRX888;
2791 break;
2792 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2793 dspcntr |= DISPPLANE_RGBX888;
2794 break;
2795 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2796 dspcntr |= DISPPLANE_BGRX101010;
2797 break;
2798 case DRM_FORMAT_XBGR2101010:
57779d06 2799 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2800 break;
2801 default:
baba133a 2802 BUG();
17638cd6
JB		 2803 }
2804
2805 if (obj->tiling_mode != I915_TILING_NONE)
2806 dspcntr |= DISPPLANE_TILED;
17638cd6 2807
f45651ba 2808 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2809 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2810
b9897127 2811 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2812 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2813 intel_gen4_compute_page_offset(dev_priv,
2814 &x, &y, obj->tiling_mode,
b9897127 2815 pixel_size,
bc752862 2816 fb->pitches[0]);
c2c75131 2817 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2818 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2819 dspcntr |= DISPPLANE_ROTATE_180;
2820
2821 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2822 x += (intel_crtc->config->pipe_src_w - 1);
2823 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2824
2825 /* Finding the last pixel of the last line of the display
2826 data and adding to linear_offset*/
2827 linear_offset +=
6e3c9717
ACO		 2828 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2829 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2830 }
2831 }
2832
2833 I915_WRITE(reg, dspcntr);
17638cd6 2834
01f2c773 2835 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2836 I915_WRITE(DSPSURF(plane),
2837 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2838 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2839 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2840 } else {
2841 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2842 I915_WRITE(DSPLINOFF(plane), linear_offset);
2843 }
17638cd6 2844 POSTING_READ(reg);
17638cd6
JB		 2845}
2846
b321803d
DL		 2847u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2848 uint32_t pixel_format)
2849{
2850 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2851
2852 /*
2853 * The stride is either expressed as a multiple of 64 bytes
2854 * chunks for linear buffers or in number of tiles for tiled
2855 * buffers.
2856 */
2857 switch (fb_modifier) {
2858 case DRM_FORMAT_MOD_NONE:
2859 return 64;
2860 case I915_FORMAT_MOD_X_TILED:
2861 if (INTEL_INFO(dev)->gen == 2)
2862 return 128;
2863 return 512;
2864 case I915_FORMAT_MOD_Y_TILED:
2865 /* No need to check for old gens and Y tiling since this is
2866 * about the display engine and those will be blocked before
2867 * we get here.
2868 */
2869 return 128;
2870 case I915_FORMAT_MOD_Yf_TILED:
2871 if (bits_per_pixel == 8)
2872 return 64;
2873 else
2874 return 128;
2875 default:
2876 MISSING_CASE(fb_modifier);
2877 return 64;
2878 }
2879}
2880
121920fa
TU		 2881unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2882 struct drm_i915_gem_object *obj)
2883{
9abc4648 2884 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2885
2886 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2887 view = &i915_ggtt_view_rotated;
121920fa
TU		 2888
2889 return i915_gem_obj_ggtt_offset_view(obj, view);
2890}
2891
a1b2278e
CK		 2892/*
2893 * This function detaches (aka. unbinds) unused scalers in hardware
2894 */
0583236e 2895static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e
CK		 2896{
2897 struct drm_device *dev;
2898 struct drm_i915_private *dev_priv;
2899 struct intel_crtc_scaler_state *scaler_state;
2900 int i;
2901
a1b2278e
CK		 2902 dev = intel_crtc->base.dev;
2903 dev_priv = dev->dev_private;
2904 scaler_state = &intel_crtc->config->scaler_state;
2905
2906 /* loop through and disable scalers that aren't in use */
2907 for (i = 0; i < intel_crtc->num_scalers; i++) {
2908 if (!scaler_state->scalers[i].in_use) {
2909 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2910 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2911 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2912 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2913 intel_crtc->base.base.id, intel_crtc->pipe, i);
2914 }
2915 }
2916}
2917
6156a456 2918u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2919{
6156a456 2920 switch (pixel_format) {
d161cf7a 2921 case DRM_FORMAT_C8:
c34ce3d1 2922 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2923 case DRM_FORMAT_RGB565:
c34ce3d1 2924 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2925 case DRM_FORMAT_XBGR8888:
c34ce3d1 2926 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2927 case DRM_FORMAT_XRGB8888:
c34ce3d1 2928 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2929 /*
2930 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2931 * to be already pre-multiplied. We need to add a knob (or a different
2932 * DRM_FORMAT) for user-space to configure that.
2933 */
f75fb42a 2934 case DRM_FORMAT_ABGR8888:
c34ce3d1 2935 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2936 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2937 case DRM_FORMAT_ARGB8888:
c34ce3d1 2938 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2939 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2940 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2941 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2942 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2943 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2944 case DRM_FORMAT_YUYV:
c34ce3d1 2945 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2946 case DRM_FORMAT_YVYU:
c34ce3d1 2947 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2948 case DRM_FORMAT_UYVY:
c34ce3d1 2949 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2950 case DRM_FORMAT_VYUY:
c34ce3d1 2951 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2952 default:
4249eeef 2953 MISSING_CASE(pixel_format);
70d21f0e 2954 }
8cfcba41 2955
c34ce3d1 2956 return 0;
6156a456 2957}
70d21f0e 2958
6156a456
CK		 2959u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2960{
6156a456 2961 switch (fb_modifier) {
30af77c4 2962 case DRM_FORMAT_MOD_NONE:
70d21f0e 2963 break;
30af77c4 2964 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2965 return PLANE_CTL_TILED_X;
b321803d 2966 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2967 return PLANE_CTL_TILED_Y;
b321803d 2968 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2969 return PLANE_CTL_TILED_YF;
70d21f0e 2970 default:
6156a456 2971 MISSING_CASE(fb_modifier);
70d21f0e 2972 }
8cfcba41 2973
c34ce3d1 2974 return 0;
6156a456 2975}
70d21f0e 2976
6156a456
CK		 2977u32 skl_plane_ctl_rotation(unsigned int rotation)
2978{
3b7a5119 2979 switch (rotation) {
6156a456
CK		 2980 case BIT(DRM_ROTATE_0):
2981 break;
1e8df167
SJ		 2982 /*
2983 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2984 * while i915 HW rotation is clockwise, thats why this swapping.
2985 */
3b7a5119 2986 case BIT(DRM_ROTATE_90):
1e8df167 2987 return PLANE_CTL_ROTATE_270;
3b7a5119 2988 case BIT(DRM_ROTATE_180):
c34ce3d1 2989 return PLANE_CTL_ROTATE_180;
3b7a5119 2990 case BIT(DRM_ROTATE_270):
1e8df167 2991 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2992 default:
2993 MISSING_CASE(rotation);
2994 }
2995
c34ce3d1 2996 return 0;
6156a456
CK		 2997}
2998
2999static void skylake_update_primary_plane(struct drm_crtc *crtc,
3000 struct drm_framebuffer *fb,
3001 int x, int y)
3002{
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3006 struct drm_plane *plane = crtc->primary;
3007 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3008 struct drm_i915_gem_object *obj;
3009 int pipe = intel_crtc->pipe;
3010 u32 plane_ctl, stride_div, stride;
3011 u32 tile_height, plane_offset, plane_size;
3012 unsigned int rotation;
3013 int x_offset, y_offset;
3014 unsigned long surf_addr;
6156a456
CK		 3015 struct intel_crtc_state *crtc_state = intel_crtc->config;
3016 struct intel_plane_state *plane_state;
3017 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3018 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3019 int scaler_id = -1;
3020
6156a456
CK		 3021 plane_state = to_intel_plane_state(plane->state);
3022
b70709a6 3023 if (!visible || !fb) {
6156a456
CK		 3024 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3025 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3026 POSTING_READ(PLANE_CTL(pipe, 0));
3027 return;
3b7a5119 3028 }
70d21f0e 3029
6156a456
CK		 3030 plane_ctl = PLANE_CTL_ENABLE |
3031 PLANE_CTL_PIPE_GAMMA_ENABLE |
3032 PLANE_CTL_PIPE_CSC_ENABLE;
3033
3034 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3035 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3036 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3037
3038 rotation = plane->state->rotation;
3039 plane_ctl |= skl_plane_ctl_rotation(rotation);
3040
b321803d
DL		 3041 obj = intel_fb_obj(fb);
3042 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3043 fb->pixel_format);
3b7a5119
SJ		 3044 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3045
6156a456
CK		 3046 /*
3047 * FIXME: intel_plane_state->src, dst aren't set when transitional
3048 * update_plane helpers are called from legacy paths.
3049 * Once full atomic crtc is available, below check can be avoided.
3050 */
3051 if (drm_rect_width(&plane_state->src)) {
3052 scaler_id = plane_state->scaler_id;
3053 src_x = plane_state->src.x1 >> 16;
3054 src_y = plane_state->src.y1 >> 16;
3055 src_w = drm_rect_width(&plane_state->src) >> 16;
3056 src_h = drm_rect_height(&plane_state->src) >> 16;
3057 dst_x = plane_state->dst.x1;
3058 dst_y = plane_state->dst.y1;
3059 dst_w = drm_rect_width(&plane_state->dst);
3060 dst_h = drm_rect_height(&plane_state->dst);
3061
3062 WARN_ON(x != src_x || y != src_y);
3063 } else {
3064 src_w = intel_crtc->config->pipe_src_w;
3065 src_h = intel_crtc->config->pipe_src_h;
3066 }
3067
3b7a5119
SJ		 3068 if (intel_rotation_90_or_270(rotation)) {
3069 /* stride = Surface height in tiles */
2614f17d 3070 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3071 fb->modifier[0]);
3072 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3073 x_offset = stride * tile_height - y - src_h;
3b7a5119 3074 y_offset = x;
6156a456 3075 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3076 } else {
3077 stride = fb->pitches[0] / stride_div;
3078 x_offset = x;
3079 y_offset = y;
6156a456 3080 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3081 }
3082 plane_offset = y_offset << 16 | x_offset;
b321803d 3083
70d21f0e 3084 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3085 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3086 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3087 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3088
3089 if (scaler_id >= 0) {
3090 uint32_t ps_ctrl = 0;
3091
3092 WARN_ON(!dst_w || !dst_h);
3093 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3094 crtc_state->scaler_state.scalers[scaler_id].mode;
3095 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3096 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3097 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3098 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3099 I915_WRITE(PLANE_POS(pipe, 0), 0);
3100 } else {
3101 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3102 }
3103
121920fa 3104 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3105
3106 POSTING_READ(PLANE_SURF(pipe, 0));
3107}
3108
17638cd6
JB		 3109/* Assume fb object is pinned & idle & fenced and just update base pointers */
3110static int
3111intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3112 int x, int y, enum mode_set_atomic state)
3113{
3114 struct drm_device *dev = crtc->dev;
3115 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3116
6b8e6ed0
CW		 3117 if (dev_priv->display.disable_fbc)
3118 dev_priv->display.disable_fbc(dev);
81255565 3119
29b9bde6
DV		 3120 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3121
3122 return 0;
81255565
JB		 3123}
3124
7514747d 3125static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3126{
96a02917
VS		 3127 struct drm_crtc *crtc;
3128
70e1e0ec 3129 for_each_crtc(dev, crtc) {
96a02917
VS		 3130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3131 enum plane plane = intel_crtc->plane;
3132
3133 intel_prepare_page_flip(dev, plane);
3134 intel_finish_page_flip_plane(dev, plane);
3135 }
7514747d
VS		 3136}
3137
3138static void intel_update_primary_planes(struct drm_device *dev)
3139{
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 struct drm_crtc *crtc;
96a02917 3142
70e1e0ec 3143 for_each_crtc(dev, crtc) {
96a02917
VS		 3144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3145
51fd371b 3146 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3147 /*
3148 * FIXME: Once we have proper support for primary planes (and
3149 * disabling them without disabling the entire crtc) allow again
66e514c1 3150 * a NULL crtc->primary->fb.
947fdaad 3151 */
f4510a27 3152 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3153 dev_priv->display.update_primary_plane(crtc,
66e514c1 3154 crtc->primary->fb,
262ca2b0
MR		 3155 crtc->x,
3156 crtc->y);
51fd371b 3157 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3158 }
3159}
3160
7514747d
VS		 3161void intel_prepare_reset(struct drm_device *dev)
3162{
3163 /* no reset support for gen2 */
3164 if (IS_GEN2(dev))
3165 return;
3166
3167 /* reset doesn't touch the display */
3168 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3169 return;
3170
3171 drm_modeset_lock_all(dev);
f98ce92f
VS		 3172 /*
3173 * Disabling the crtcs gracefully seems nicer. Also the
3174 * g33 docs say we should at least disable all the planes.
3175 */
6b72d486 3176 intel_display_suspend(dev);
7514747d
VS		 3177}
3178
3179void intel_finish_reset(struct drm_device *dev)
3180{
3181 struct drm_i915_private *dev_priv = to_i915(dev);
3182
3183 /*
3184 * Flips in the rings will be nuked by the reset,
3185 * so complete all pending flips so that user space
3186 * will get its events and not get stuck.
3187 */
3188 intel_complete_page_flips(dev);
3189
3190 /* no reset support for gen2 */
3191 if (IS_GEN2(dev))
3192 return;
3193
3194 /* reset doesn't touch the display */
3195 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3196 /*
3197 * Flips in the rings have been nuked by the reset,
3198 * so update the base address of all primary
3199 * planes to the the last fb to make sure we're
3200 * showing the correct fb after a reset.
3201 */
3202 intel_update_primary_planes(dev);
3203 return;
3204 }
3205
3206 /*
3207 * The display has been reset as well,
3208 * so need a full re-initialization.
3209 */
3210 intel_runtime_pm_disable_interrupts(dev_priv);
3211 intel_runtime_pm_enable_interrupts(dev_priv);
3212
3213 intel_modeset_init_hw(dev);
3214
3215 spin_lock_irq(&dev_priv->irq_lock);
3216 if (dev_priv->display.hpd_irq_setup)
3217 dev_priv->display.hpd_irq_setup(dev);
3218 spin_unlock_irq(&dev_priv->irq_lock);
3219
3220 intel_modeset_setup_hw_state(dev, true);
3221
3222 intel_hpd_init(dev_priv);
3223
3224 drm_modeset_unlock_all(dev);
3225}
3226
2e2f351d 3227static void
14667a4b
CW		 3228intel_finish_fb(struct drm_framebuffer *old_fb)
3229{
2ff8fde1 3230 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3231 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3232 bool was_interruptible = dev_priv->mm.interruptible;
3233 int ret;
3234
14667a4b
CW		 3235 /* Big Hammer, we also need to ensure that any pending
3236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3237 * current scanout is retired before unpinning the old
2e2f351d
CW		 3238 * framebuffer. Note that we rely on userspace rendering
3239 * into the buffer attached to the pipe they are waiting
3240 * on. If not, userspace generates a GPU hang with IPEHR
3241 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3242 *
3243 * This should only fail upon a hung GPU, in which case we
3244 * can safely continue.
3245 */
3246 dev_priv->mm.interruptible = false;
2e2f351d 3247 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3248 dev_priv->mm.interruptible = was_interruptible;
3249
2e2f351d 3250 WARN_ON(ret);
14667a4b
CW		 3251}
3252
7d5e3799
CW		 3253static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3258 bool pending;
3259
3260 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3261 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3262 return false;
3263
5e2d7afc 3264 spin_lock_irq(&dev->event_lock);
7d5e3799 3265 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3266 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3267
3268 return pending;
3269}
3270
e30e8f75
GP		 3271static void intel_update_pipe_size(struct intel_crtc *crtc)
3272{
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 const struct drm_display_mode *adjusted_mode;
3276
3277 if (!i915.fastboot)
3278 return;
3279
3280 /*
3281 * Update pipe size and adjust fitter if needed: the reason for this is
3282 * that in compute_mode_changes we check the native mode (not the pfit
3283 * mode) to see if we can flip rather than do a full mode set. In the
3284 * fastboot case, we'll flip, but if we don't update the pipesrc and
3285 * pfit state, we'll end up with a big fb scanned out into the wrong
3286 * sized surface.
3287 *
3288 * To fix this properly, we need to hoist the checks up into
3289 * compute_mode_changes (or above), check the actual pfit state and
3290 * whether the platform allows pfit disable with pipe active, and only
3291 * then update the pipesrc and pfit state, even on the flip path.
3292 */
3293
6e3c9717 3294 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3295
3296 I915_WRITE(PIPESRC(crtc->pipe),
3297 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3298 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3299 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3300 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3301 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3302 I915_WRITE(PF_CTL(crtc->pipe), 0);
3303 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3304 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3305 }
6e3c9717
ACO		 3306 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3307 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3308}
3309
5e84e1a4
ZW		 3310static void intel_fdi_normal_train(struct drm_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315 int pipe = intel_crtc->pipe;
3316 u32 reg, temp;
3317
3318 /* enable normal train */
3319 reg = FDI_TX_CTL(pipe);
3320 temp = I915_READ(reg);
61e499bf 3321 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3322 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3323 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3324 } else {
3325 temp &= ~FDI_LINK_TRAIN_NONE;
3326 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3327 }
5e84e1a4
ZW		 3328 I915_WRITE(reg, temp);
3329
3330 reg = FDI_RX_CTL(pipe);
3331 temp = I915_READ(reg);
3332 if (HAS_PCH_CPT(dev)) {
3333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3334 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3335 } else {
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_NONE;
3338 }
3339 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3340
3341 /* wait one idle pattern time */
3342 POSTING_READ(reg);
3343 udelay(1000);
357555c0
JB		 3344
3345 /* IVB wants error correction enabled */
3346 if (IS_IVYBRIDGE(dev))
3347 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3348 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3349}
3350
8db9d77b
ZW		 3351/* The FDI link training functions for ILK/Ibexpeak. */
3352static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3353{
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
5eddb70b 3358 u32 reg, temp, tries;
8db9d77b 3359
1c8562f6 3360 /* FDI needs bits from pipe first */
0fc932b8 3361 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3362
e1a44743
AJ		 3363 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3364 for train result */
5eddb70b
CW		 3365 reg = FDI_RX_IMR(pipe);
3366 temp = I915_READ(reg);
e1a44743
AJ		 3367 temp &= ~FDI_RX_SYMBOL_LOCK;
3368 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3369 I915_WRITE(reg, temp);
3370 I915_READ(reg);
e1a44743
AJ		 3371 udelay(150);
3372
8db9d77b 3373 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3374 reg = FDI_TX_CTL(pipe);
3375 temp = I915_READ(reg);
627eb5a3 3376 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3377 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3380 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3381
5eddb70b
CW		 3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
8db9d77b
ZW		 3384 temp &= ~FDI_LINK_TRAIN_NONE;
3385 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3386 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3387
3388 POSTING_READ(reg);
8db9d77b
ZW		 3389 udelay(150);
3390
5b2adf89 3391 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3392 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3393 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3394 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3395
5eddb70b 3396 reg = FDI_RX_IIR(pipe);
e1a44743 3397 for (tries = 0; tries < 5; tries++) {
5eddb70b 3398 temp = I915_READ(reg);
8db9d77b
ZW		 3399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3400
3401 if ((temp & FDI_RX_BIT_LOCK)) {
3402 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3403 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3404 break;
3405 }
8db9d77b 3406 }
e1a44743 3407 if (tries == 5)
5eddb70b 3408 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3409
3410 /* Train 2 */
5eddb70b
CW		 3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
8db9d77b
ZW		 3413 temp &= ~FDI_LINK_TRAIN_NONE;
3414 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3415 I915_WRITE(reg, temp);
8db9d77b 3416
5eddb70b
CW		 3417 reg = FDI_RX_CTL(pipe);
3418 temp = I915_READ(reg);
8db9d77b
ZW		 3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3421 I915_WRITE(reg, temp);
8db9d77b 3422
5eddb70b
CW		 3423 POSTING_READ(reg);
3424 udelay(150);
8db9d77b 3425
5eddb70b 3426 reg = FDI_RX_IIR(pipe);
e1a44743 3427 for (tries = 0; tries < 5; tries++) {
5eddb70b 3428 temp = I915_READ(reg);
8db9d77b
ZW		 3429 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3430
3431 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3432 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3433 DRM_DEBUG_KMS("FDI train 2 done.\n");
3434 break;
3435 }
8db9d77b 3436 }
e1a44743 3437 if (tries == 5)
5eddb70b 3438 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3439
3440 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3441
8db9d77b
ZW		 3442}
3443
0206e353 3444static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3445 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3446 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3447 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3448 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3449};
3450
3451/* The FDI link training functions for SNB/Cougarpoint. */
3452static void gen6_fdi_link_train(struct drm_crtc *crtc)
3453{
3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457 int pipe = intel_crtc->pipe;
fa37d39e 3458 u32 reg, temp, i, retry;
8db9d77b 3459
e1a44743
AJ		 3460 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3461 for train result */
5eddb70b
CW		 3462 reg = FDI_RX_IMR(pipe);
3463 temp = I915_READ(reg);
e1a44743
AJ		 3464 temp &= ~FDI_RX_SYMBOL_LOCK;
3465 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3466 I915_WRITE(reg, temp);
3467
3468 POSTING_READ(reg);
e1a44743
AJ		 3469 udelay(150);
3470
8db9d77b 3471 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
627eb5a3 3474 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3475 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3476 temp &= ~FDI_LINK_TRAIN_NONE;
3477 temp |= FDI_LINK_TRAIN_PATTERN_1;
3478 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3479 /* SNB-B */
3480 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3482
d74cf324
DV		 3483 I915_WRITE(FDI_RX_MISC(pipe),
3484 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3485
5eddb70b
CW		 3486 reg = FDI_RX_CTL(pipe);
3487 temp = I915_READ(reg);
8db9d77b
ZW		 3488 if (HAS_PCH_CPT(dev)) {
3489 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3491 } else {
3492 temp &= ~FDI_LINK_TRAIN_NONE;
3493 temp |= FDI_LINK_TRAIN_PATTERN_1;
3494 }
5eddb70b
CW		 3495 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3496
3497 POSTING_READ(reg);
8db9d77b
ZW		 3498 udelay(150);
3499
0206e353 3500 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3501 reg = FDI_TX_CTL(pipe);
3502 temp = I915_READ(reg);
8db9d77b
ZW		 3503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3504 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3505 I915_WRITE(reg, temp);
3506
3507 POSTING_READ(reg);
8db9d77b
ZW		 3508 udelay(500);
3509
fa37d39e
SP		 3510 for (retry = 0; retry < 5; retry++) {
3511 reg = FDI_RX_IIR(pipe);
3512 temp = I915_READ(reg);
3513 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3514 if (temp & FDI_RX_BIT_LOCK) {
3515 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3516 DRM_DEBUG_KMS("FDI train 1 done.\n");
3517 break;
3518 }
3519 udelay(50);
8db9d77b 3520 }
fa37d39e
SP		 3521 if (retry < 5)
3522 break;
8db9d77b
ZW		 3523 }
3524 if (i == 4)
5eddb70b 3525 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3526
3527 /* Train 2 */
5eddb70b
CW		 3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_2;
3532 if (IS_GEN6(dev)) {
3533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3534 /* SNB-B */
3535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3536 }
5eddb70b 3537 I915_WRITE(reg, temp);
8db9d77b 3538
5eddb70b
CW		 3539 reg = FDI_RX_CTL(pipe);
3540 temp = I915_READ(reg);
8db9d77b
ZW		 3541 if (HAS_PCH_CPT(dev)) {
3542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3543 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3544 } else {
3545 temp &= ~FDI_LINK_TRAIN_NONE;
3546 temp |= FDI_LINK_TRAIN_PATTERN_2;
3547 }
5eddb70b
CW		 3548 I915_WRITE(reg, temp);
3549
3550 POSTING_READ(reg);
8db9d77b
ZW		 3551 udelay(150);
3552
0206e353 3553 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
8db9d77b
ZW		 3556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3557 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3558 I915_WRITE(reg, temp);
3559
3560 POSTING_READ(reg);
8db9d77b
ZW		 3561 udelay(500);
3562
fa37d39e
SP		 3563 for (retry = 0; retry < 5; retry++) {
3564 reg = FDI_RX_IIR(pipe);
3565 temp = I915_READ(reg);
3566 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3567 if (temp & FDI_RX_SYMBOL_LOCK) {
3568 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3569 DRM_DEBUG_KMS("FDI train 2 done.\n");
3570 break;
3571 }
3572 udelay(50);
8db9d77b 3573 }
fa37d39e
SP		 3574 if (retry < 5)
3575 break;
8db9d77b
ZW		 3576 }
3577 if (i == 4)
5eddb70b 3578 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3579
3580 DRM_DEBUG_KMS("FDI train done.\n");
3581}
3582
357555c0
JB		 3583/* Manual link training for Ivy Bridge A0 parts */
3584static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3585{
3586 struct drm_device *dev = crtc->dev;
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3589 int pipe = intel_crtc->pipe;
139ccd3f 3590 u32 reg, temp, i, j;
357555c0
JB		 3591
3592 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3593 for train result */
3594 reg = FDI_RX_IMR(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_RX_SYMBOL_LOCK;
3597 temp &= ~FDI_RX_BIT_LOCK;
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
3601 udelay(150);
3602
01a415fd
DV		 3603 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3604 I915_READ(FDI_RX_IIR(pipe)));
3605
139ccd3f
JB		 3606 /* Try each vswing and preemphasis setting twice before moving on */
3607 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3608 /* disable first in case we need to retry */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3612 temp &= ~FDI_TX_ENABLE;
3613 I915_WRITE(reg, temp);
357555c0 3614
139ccd3f
JB		 3615 reg = FDI_RX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 temp &= ~FDI_LINK_TRAIN_AUTO;
3618 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3619 temp &= ~FDI_RX_ENABLE;
3620 I915_WRITE(reg, temp);
357555c0 3621
139ccd3f 3622 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3623 reg = FDI_TX_CTL(pipe);
3624 temp = I915_READ(reg);
139ccd3f 3625 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3626 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3627 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3629 temp |= snb_b_fdi_train_param[j/2];
3630 temp |= FDI_COMPOSITE_SYNC;
3631 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3632
139ccd3f
JB		 3633 I915_WRITE(FDI_RX_MISC(pipe),
3634 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3635
139ccd3f 3636 reg = FDI_RX_CTL(pipe);
357555c0 3637 temp = I915_READ(reg);
139ccd3f
JB		 3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639 temp |= FDI_COMPOSITE_SYNC;
3640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3641
139ccd3f
JB		 3642 POSTING_READ(reg);
3643 udelay(1); /* should be 0.5us */
357555c0 3644
139ccd3f
JB		 3645 for (i = 0; i < 4; i++) {
3646 reg = FDI_RX_IIR(pipe);
3647 temp = I915_READ(reg);
3648 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3649
139ccd3f
JB		 3650 if (temp & FDI_RX_BIT_LOCK ||
3651 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3652 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3653 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3654 i);
3655 break;
3656 }
3657 udelay(1); /* should be 0.5us */
3658 }
3659 if (i == 4) {
3660 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3661 continue;
3662 }
357555c0 3663
139ccd3f 3664 /* Train 2 */
357555c0
JB		 3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
139ccd3f
JB		 3667 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3668 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3669 I915_WRITE(reg, temp);
3670
3671 reg = FDI_RX_CTL(pipe);
3672 temp = I915_READ(reg);
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3675 I915_WRITE(reg, temp);
3676
3677 POSTING_READ(reg);
139ccd3f 3678 udelay(2); /* should be 1.5us */
357555c0 3679
139ccd3f
JB		 3680 for (i = 0; i < 4; i++) {
3681 reg = FDI_RX_IIR(pipe);
3682 temp = I915_READ(reg);
3683 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3684
139ccd3f
JB		 3685 if (temp & FDI_RX_SYMBOL_LOCK ||
3686 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3687 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3688 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3689 i);
3690 goto train_done;
3691 }
3692 udelay(2); /* should be 1.5us */
357555c0 3693 }
139ccd3f
JB		 3694 if (i == 4)
3695 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3696 }
357555c0 3697
139ccd3f 3698train_done:
357555c0
JB		 3699 DRM_DEBUG_KMS("FDI train done.\n");
3700}
3701
88cefb6c 3702static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3703{
88cefb6c 3704 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3705 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3706 int pipe = intel_crtc->pipe;
5eddb70b 3707 u32 reg, temp;
79e53945 3708
c64e311e 3709
c98e9dcf 3710 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
627eb5a3 3713 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3714 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3715 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3716 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3717
3718 POSTING_READ(reg);
c98e9dcf
JB		 3719 udelay(200);
3720
3721 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3722 temp = I915_READ(reg);
3723 I915_WRITE(reg, temp | FDI_PCDCLK);
3724
3725 POSTING_READ(reg);
c98e9dcf
JB		 3726 udelay(200);
3727
20749730
PZ		 3728 /* Enable CPU FDI TX PLL, always on for Ironlake */
3729 reg = FDI_TX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3732 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3733
20749730
PZ		 3734 POSTING_READ(reg);
3735 udelay(100);
6be4a607 3736 }
0e23b99d
JB		 3737}
3738
88cefb6c
DV		 3739static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3740{
3741 struct drm_device *dev = intel_crtc->base.dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 /* Switch from PCDclk to Rawclk */
3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3750
3751 /* Disable CPU FDI TX PLL */
3752 reg = FDI_TX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 reg = FDI_RX_CTL(pipe);
3760 temp = I915_READ(reg);
3761 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3762
3763 /* Wait for the clocks to turn off. */
3764 POSTING_READ(reg);
3765 udelay(100);
3766}
3767
0fc932b8
JB		 3768static void ironlake_fdi_disable(struct drm_crtc *crtc)
3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773 int pipe = intel_crtc->pipe;
3774 u32 reg, temp;
3775
3776 /* disable CPU FDI tx and PCH FDI rx */
3777 reg = FDI_TX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3780 POSTING_READ(reg);
3781
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 temp &= ~(0x7 << 16);
dfd07d72 3785 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3786 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3787
3788 POSTING_READ(reg);
3789 udelay(100);
3790
3791 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3792 if (HAS_PCH_IBX(dev))
6f06ce18 3793 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3794
3795 /* still set train pattern 1 */
3796 reg = FDI_TX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 temp &= ~FDI_LINK_TRAIN_NONE;
3799 temp |= FDI_LINK_TRAIN_PATTERN_1;
3800 I915_WRITE(reg, temp);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 if (HAS_PCH_CPT(dev)) {
3805 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3806 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3807 } else {
3808 temp &= ~FDI_LINK_TRAIN_NONE;
3809 temp |= FDI_LINK_TRAIN_PATTERN_1;
3810 }
3811 /* BPC in FDI rx is consistent with that in PIPECONF */
3812 temp &= ~(0x07 << 16);
dfd07d72 3813 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3814 I915_WRITE(reg, temp);
3815
3816 POSTING_READ(reg);
3817 udelay(100);
3818}
3819
5dce5b93
CW		 3820bool intel_has_pending_fb_unpin(struct drm_device *dev)
3821{
3822 struct intel_crtc *crtc;
3823
3824 /* Note that we don't need to be called with mode_config.lock here
3825 * as our list of CRTC objects is static for the lifetime of the
3826 * device and so cannot disappear as we iterate. Similarly, we can
3827 * happily treat the predicates as racy, atomic checks as userspace
3828 * cannot claim and pin a new fb without at least acquring the
3829 * struct_mutex and so serialising with us.
3830 */
d3fcc808 3831 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3832 if (atomic_read(&crtc->unpin_work_count) == 0)
3833 continue;
3834
3835 if (crtc->unpin_work)
3836 intel_wait_for_vblank(dev, crtc->pipe);
3837
3838 return true;
3839 }
3840
3841 return false;
3842}
3843
d6bbafa1
CW		 3844static void page_flip_completed(struct intel_crtc *intel_crtc)
3845{
3846 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3847 struct intel_unpin_work *work = intel_crtc->unpin_work;
3848
3849 /* ensure that the unpin work is consistent wrt ->pending. */
3850 smp_rmb();
3851 intel_crtc->unpin_work = NULL;
3852
3853 if (work->event)
3854 drm_send_vblank_event(intel_crtc->base.dev,
3855 intel_crtc->pipe,
3856 work->event);
3857
3858 drm_crtc_vblank_put(&intel_crtc->base);
3859
3860 wake_up_all(&dev_priv->pending_flip_queue);
3861 queue_work(dev_priv->wq, &work->work);
3862
3863 trace_i915_flip_complete(intel_crtc->plane,
3864 work->pending_flip_obj);
3865}
3866
46a55d30 3867void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3868{
0f91128d 3869 struct drm_device *dev = crtc->dev;
5bb61643 3870 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3871
2c10d571 3872 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3873 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3874 !intel_crtc_has_pending_flip(crtc),
3875 60*HZ) == 0)) {
3876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3877
5e2d7afc 3878 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3879 if (intel_crtc->unpin_work) {
3880 WARN_ONCE(1, "Removing stuck page flip\n");
3881 page_flip_completed(intel_crtc);
3882 }
5e2d7afc 3883 spin_unlock_irq(&dev->event_lock);
9c787942 3884 }
5bb61643 3885
975d568a
CW		 3886 if (crtc->primary->fb) {
3887 mutex_lock(&dev->struct_mutex);
3888 intel_finish_fb(crtc->primary->fb);
3889 mutex_unlock(&dev->struct_mutex);
3890 }
e6c3a2a6
CW		 3891}
3892
e615efe4
ED		 3893/* Program iCLKIP clock to the desired frequency */
3894static void lpt_program_iclkip(struct drm_crtc *crtc)
3895{
3896 struct drm_device *dev = crtc->dev;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3898 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3899 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3900 u32 temp;
3901
a580516d 3902 mutex_lock(&dev_priv->sb_lock);
09153000 3903
e615efe4
ED		 3904 /* It is necessary to ungate the pixclk gate prior to programming
3905 * the divisors, and gate it back when it is done.
3906 */
3907 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3908
3909 /* Disable SSCCTL */
3910 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3911 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3912 SBI_SSCCTL_DISABLE,
3913 SBI_ICLK);
e615efe4
ED		 3914
3915 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3916 if (clock == 20000) {
e615efe4
ED		 3917 auxdiv = 1;
3918 divsel = 0x41;
3919 phaseinc = 0x20;
3920 } else {
3921 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3922 * but the adjusted_mode->crtc_clock in in KHz. To get the
3923 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3924 * convert the virtual clock precision to KHz here for higher
3925 * precision.
3926 */
3927 u32 iclk_virtual_root_freq = 172800 * 1000;
3928 u32 iclk_pi_range = 64;
3929 u32 desired_divisor, msb_divisor_value, pi_value;
3930
12d7ceed 3931 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3932 msb_divisor_value = desired_divisor / iclk_pi_range;
3933 pi_value = desired_divisor % iclk_pi_range;
3934
3935 auxdiv = 0;
3936 divsel = msb_divisor_value - 2;
3937 phaseinc = pi_value;
3938 }
3939
3940 /* This should not happen with any sane values */
3941 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3942 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3943 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3944 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3945
3946 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3947 clock,
e615efe4
ED		 3948 auxdiv,
3949 divsel,
3950 phasedir,
3951 phaseinc);
3952
3953 /* Program SSCDIVINTPHASE6 */
988d6ee8 3954 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3955 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3956 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3957 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3958 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3959 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3960 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3961 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3962
3963 /* Program SSCAUXDIV */
988d6ee8 3964 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3965 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3966 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3967 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3968
3969 /* Enable modulator and associated divider */
988d6ee8 3970 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3971 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3972 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3973
3974 /* Wait for initialization time */
3975 udelay(24);
3976
3977 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3978
a580516d 3979 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3980}
3981
275f01b2
DV		 3982static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3983 enum pipe pch_transcoder)
3984{
3985 struct drm_device *dev = crtc->base.dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3987 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3988
3989 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3990 I915_READ(HTOTAL(cpu_transcoder)));
3991 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3992 I915_READ(HBLANK(cpu_transcoder)));
3993 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3994 I915_READ(HSYNC(cpu_transcoder)));
3995
3996 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3997 I915_READ(VTOTAL(cpu_transcoder)));
3998 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3999 I915_READ(VBLANK(cpu_transcoder)));
4000 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4001 I915_READ(VSYNC(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4003 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4004}
4005
003632d9 4006static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4007{
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 uint32_t temp;
4010
4011 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4012 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4013 return;
4014
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4016 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4017
003632d9
ACO		 4018 temp &= ~FDI_BC_BIFURCATION_SELECT;
4019 if (enable)
4020 temp |= FDI_BC_BIFURCATION_SELECT;
4021
4022 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4023 I915_WRITE(SOUTH_CHICKEN1, temp);
4024 POSTING_READ(SOUTH_CHICKEN1);
4025}
4026
4027static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4028{
4029 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4030
4031 switch (intel_crtc->pipe) {
4032 case PIPE_A:
4033 break;
4034 case PIPE_B:
6e3c9717 4035 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4036 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4037 else
003632d9 4038 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4039
4040 break;
4041 case PIPE_C:
003632d9 4042 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4043
4044 break;
4045 default:
4046 BUG();
4047 }
4048}
4049
f67a559d
JB		 4050/*
4051 * Enable PCH resources required for PCH ports:
4052 * - PCH PLLs
4053 * - FDI training & RX/TX
4054 * - update transcoder timings
4055 * - DP transcoding bits
4056 * - transcoder
4057 */
4058static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4059{
4060 struct drm_device *dev = crtc->dev;
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063 int pipe = intel_crtc->pipe;
ee7b9f93 4064 u32 reg, temp;
2c07245f 4065
ab9412ba 4066 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4067
1fbc0d78
DV		 4068 if (IS_IVYBRIDGE(dev))
4069 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4070
cd986abb
DV		 4071 /* Write the TU size bits before fdi link training, so that error
4072 * detection works. */
4073 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4074 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4075
c98e9dcf 4076 /* For PCH output, training FDI link */
674cf967 4077 dev_priv->display.fdi_link_train(crtc);
2c07245f 4078
3ad8a208
DV		 4079 /* We need to program the right clock selection before writing the pixel
4080 * mutliplier into the DPLL. */
303b81e0 4081 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4082 u32 sel;
4b645f14 4083
c98e9dcf 4084 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4085 temp |= TRANS_DPLL_ENABLE(pipe);
4086 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4087 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4088 temp |= sel;
4089 else
4090 temp &= ~sel;
c98e9dcf 4091 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4092 }
5eddb70b 4093
3ad8a208
DV		 4094 /* XXX: pch pll's can be enabled any time before we enable the PCH
4095 * transcoder, and we actually should do this to not upset any PCH
4096 * transcoder that already use the clock when we share it.
4097 *
4098 * Note that enable_shared_dpll tries to do the right thing, but
4099 * get_shared_dpll unconditionally resets the pll - we need that to have
4100 * the right LVDS enable sequence. */
85b3894f 4101 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4102
d9b6cb56
JB		 4103 /* set transcoder timing, panel must allow it */
4104 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4105 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4106
303b81e0 4107 intel_fdi_normal_train(crtc);
5e84e1a4 4108
c98e9dcf 4109 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4110 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4111 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4112 reg = TRANS_DP_CTL(pipe);
4113 temp = I915_READ(reg);
4114 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4115 TRANS_DP_SYNC_MASK |
4116 TRANS_DP_BPC_MASK);
e3ef4479 4117 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4118 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4119
4120 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4121 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4122 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4123 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4124
4125 switch (intel_trans_dp_port_sel(crtc)) {
4126 case PCH_DP_B:
5eddb70b 4127 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4128 break;
4129 case PCH_DP_C:
5eddb70b 4130 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4131 break;
4132 case PCH_DP_D:
5eddb70b 4133 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4134 break;
4135 default:
e95d41e1 4136 BUG();
32f9d658 4137 }
2c07245f 4138
5eddb70b 4139 I915_WRITE(reg, temp);
6be4a607 4140 }
b52eb4dc 4141
b8a4f404 4142 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4143}
4144
1507e5bd
PZ		 4145static void lpt_pch_enable(struct drm_crtc *crtc)
4146{
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4150 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4151
ab9412ba 4152 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4153
8c52b5e8 4154 lpt_program_iclkip(crtc);
1507e5bd 4155
0540e488 4156 /* Set transcoder timing. */
275f01b2 4157 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4158
937bb610 4159 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4160}
4161
190f68c5
ACO		 4162struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4163 struct intel_crtc_state *crtc_state)
ee7b9f93 4164{
e2b78267 4165 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4166 struct intel_shared_dpll *pll;
de419ab6 4167 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4168 enum intel_dpll_id i;
ee7b9f93 4169
de419ab6
ML		 4170 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4171
98b6bd99
DV		 4172 if (HAS_PCH_IBX(dev_priv->dev)) {
4173 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4174 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4175 pll = &dev_priv->shared_dplls[i];
98b6bd99 4176
46edb027
DV		 4177 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4178 crtc->base.base.id, pll->name);
98b6bd99 4179
de419ab6 4180 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4181
98b6bd99
DV		 4182 goto found;
4183 }
4184
bcddf610
S		 4185 if (IS_BROXTON(dev_priv->dev)) {
4186 /* PLL is attached to port in bxt */
4187 struct intel_encoder *encoder;
4188 struct intel_digital_port *intel_dig_port;
4189
4190 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4191 if (WARN_ON(!encoder))
4192 return NULL;
4193
4194 intel_dig_port = enc_to_dig_port(&encoder->base);
4195 /* 1:1 mapping between ports and PLLs */
4196 i = (enum intel_dpll_id)intel_dig_port->port;
4197 pll = &dev_priv->shared_dplls[i];
4198 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4199 crtc->base.base.id, pll->name);
de419ab6 4200 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4201
4202 goto found;
4203 }
4204
e72f9fbf
DV		 4205 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4206 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4207
4208 /* Only want to check enabled timings first */
de419ab6 4209 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4210 continue;
4211
190f68c5 4212 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4213 &shared_dpll[i].hw_state,
4214 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4215 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4216 crtc->base.base.id, pll->name,
de419ab6 4217 shared_dpll[i].crtc_mask,
8bd31e67 4218 pll->active);
ee7b9f93
JB		 4219 goto found;
4220 }
4221 }
4222
4223 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4224 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4225 pll = &dev_priv->shared_dplls[i];
de419ab6 4226 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4227 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4228 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4229 goto found;
4230 }
4231 }
4232
4233 return NULL;
4234
4235found:
de419ab6
ML		 4236 if (shared_dpll[i].crtc_mask == 0)
4237 shared_dpll[i].hw_state =
4238 crtc_state->dpll_hw_state;
f2a69f44 4239
190f68c5 4240 crtc_state->shared_dpll = i;
46edb027
DV		 4241 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4242 pipe_name(crtc->pipe));
ee7b9f93 4243
de419ab6 4244 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4245
ee7b9f93
JB		 4246 return pll;
4247}
4248
de419ab6 4249static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4250{
de419ab6
ML		 4251 struct drm_i915_private *dev_priv = to_i915(state->dev);
4252 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4253 struct intel_shared_dpll *pll;
4254 enum intel_dpll_id i;
4255
de419ab6
ML		 4256 if (!to_intel_atomic_state(state)->dpll_set)
4257 return;
8bd31e67 4258
de419ab6 4259 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4260 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261 pll = &dev_priv->shared_dplls[i];
de419ab6 4262 pll->config = shared_dpll[i];
8bd31e67
ACO		 4263 }
4264}
4265
a1520318 4266static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4267{
4268 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4269 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4270 u32 temp;
4271
4272 temp = I915_READ(dslreg);
4273 udelay(500);
4274 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4275 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4276 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4277 }
4278}
4279
86adf9d7
ML		 4280static int
4281skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4282 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4283 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4284{
86adf9d7
ML		 4285 struct intel_crtc_scaler_state *scaler_state =
4286 &crtc_state->scaler_state;
4287 struct intel_crtc *intel_crtc =
4288 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4289 int need_scaling;
6156a456
CK		 4290
4291 need_scaling = intel_rotation_90_or_270(rotation) ?
4292 (src_h != dst_w || src_w != dst_h):
4293 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4294
4295 /*
4296 * if plane is being disabled or scaler is no more required or force detach
4297 * - free scaler binded to this plane/crtc
4298 * - in order to do this, update crtc->scaler_usage
4299 *
4300 * Here scaler state in crtc_state is set free so that
4301 * scaler can be assigned to other user. Actual register
4302 * update to free the scaler is done in plane/panel-fit programming.
4303 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4304 */
86adf9d7 4305 if (force_detach || !need_scaling) {
a1b2278e 4306 if (*scaler_id >= 0) {
86adf9d7 4307 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4308 scaler_state->scalers[*scaler_id].in_use = 0;
4309
86adf9d7
ML		 4310 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4311 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4312 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4313 scaler_state->scaler_users);
4314 *scaler_id = -1;
4315 }
4316 return 0;
4317 }
4318
4319 /* range checks */
4320 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4321 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4322
4323 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4324 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4325 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4326 "size is out of scaler range\n",
86adf9d7 4327 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4328 return -EINVAL;
4329 }
4330
86adf9d7
ML		 4331 /* mark this plane as a scaler user in crtc_state */
4332 scaler_state->scaler_users |= (1 << scaler_user);
4333 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4334 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4335 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4336 scaler_state->scaler_users);
4337
4338 return 0;
4339}
4340
4341/**
4342 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4343 *
4344 * @state: crtc's scaler state
4345 * @force_detach: whether to forcibly disable scaler
4346 *
4347 * Return
4348 * 0 - scaler_usage updated successfully
4349 * error - requested scaling cannot be supported or other error condition
4350 */
4351int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4352{
4353 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4354 struct drm_display_mode *adjusted_mode =
4355 &state->base.adjusted_mode;
4356
4357 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4358 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4359
4360 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4361 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4362 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4363 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4364}
4365
4366/**
4367 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4368 *
4369 * @state: crtc's scaler state
86adf9d7
ML		 4370 * @plane_state: atomic plane state to update
4371 *
4372 * Return
4373 * 0 - scaler_usage updated successfully
4374 * error - requested scaling cannot be supported or other error condition
4375 */
da20eabd
ML		 4376static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4377 struct intel_plane_state *plane_state)
86adf9d7
ML		 4378{
4379
4380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4381 struct intel_plane *intel_plane =
4382 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4383 struct drm_framebuffer *fb = plane_state->base.fb;
4384 int ret;
4385
4386 bool force_detach = !fb || !plane_state->visible;
4387
4388 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4389 intel_plane->base.base.id, intel_crtc->pipe,
4390 drm_plane_index(&intel_plane->base));
4391
4392 ret = skl_update_scaler(crtc_state, force_detach,
4393 drm_plane_index(&intel_plane->base),
4394 &plane_state->scaler_id,
4395 plane_state->base.rotation,
4396 drm_rect_width(&plane_state->src) >> 16,
4397 drm_rect_height(&plane_state->src) >> 16,
4398 drm_rect_width(&plane_state->dst),
4399 drm_rect_height(&plane_state->dst));
4400
4401 if (ret || plane_state->scaler_id < 0)
4402 return ret;
4403
a1b2278e 4404 /* check colorkey */
818ed961 4405 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4406 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4407 intel_plane->base.base.id);
a1b2278e
CK		 4408 return -EINVAL;
4409 }
4410
4411 /* Check src format */
86adf9d7
ML		 4412 switch (fb->pixel_format) {
4413 case DRM_FORMAT_RGB565:
4414 case DRM_FORMAT_XBGR8888:
4415 case DRM_FORMAT_XRGB8888:
4416 case DRM_FORMAT_ABGR8888:
4417 case DRM_FORMAT_ARGB8888:
4418 case DRM_FORMAT_XRGB2101010:
4419 case DRM_FORMAT_XBGR2101010:
4420 case DRM_FORMAT_YUYV:
4421 case DRM_FORMAT_YVYU:
4422 case DRM_FORMAT_UYVY:
4423 case DRM_FORMAT_VYUY:
4424 break;
4425 default:
4426 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4427 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4428 return -EINVAL;
a1b2278e
CK		 4429 }
4430
a1b2278e
CK		 4431 return 0;
4432}
4433
4434static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4435{
4436 struct drm_device *dev = crtc->base.dev;
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438 int pipe = crtc->pipe;
a1b2278e
CK		 4439 struct intel_crtc_scaler_state *scaler_state =
4440 &crtc->config->scaler_state;
4441
4442 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4443
4444 /* To update pfit, first update scaler state */
86adf9d7 4445 skl_update_scaler_crtc(crtc->config, !enable);
a1b2278e
CK		 4446 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4447 skl_detach_scalers(crtc);
4448 if (!enable)
4449 return;
bd2e244f 4450
6e3c9717 4451 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4452 int id;
4453
4454 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4455 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4456 return;
4457 }
4458
4459 id = scaler_state->scaler_id;
4460 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4461 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4462 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4463 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4464
4465 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4466 }
4467}
4468
b074cec8
JB		 4469static void ironlake_pfit_enable(struct intel_crtc *crtc)
4470{
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 int pipe = crtc->pipe;
4474
6e3c9717 4475 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4476 /* Force use of hard-coded filter coefficients
4477 * as some pre-programmed values are broken,
4478 * e.g. x201.
4479 */
4480 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4481 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4482 PF_PIPE_SEL_IVB(pipe));
4483 else
4484 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4485 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4486 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4487 }
4488}
4489
20bc8673 4490void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4491{
cea165c3
VS		 4492 struct drm_device *dev = crtc->base.dev;
4493 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4494
6e3c9717 4495 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4496 return;
4497
cea165c3
VS		 4498 /* We can only enable IPS after we enable a plane and wait for a vblank */
4499 intel_wait_for_vblank(dev, crtc->pipe);
4500
d77e4531 4501 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4502 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4503 mutex_lock(&dev_priv->rps.hw_lock);
4504 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4505 mutex_unlock(&dev_priv->rps.hw_lock);
4506 /* Quoting Art Runyan: "its not safe to expect any particular
4507 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4508 * mailbox." Moreover, the mailbox may return a bogus state,
4509 * so we need to just enable it and continue on.
2a114cc1
BW		 4510 */
4511 } else {
4512 I915_WRITE(IPS_CTL, IPS_ENABLE);
4513 /* The bit only becomes 1 in the next vblank, so this wait here
4514 * is essentially intel_wait_for_vblank. If we don't have this
4515 * and don't wait for vblanks until the end of crtc_enable, then
4516 * the HW state readout code will complain that the expected
4517 * IPS_CTL value is not the one we read. */
4518 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4519 DRM_ERROR("Timed out waiting for IPS enable\n");
4520 }
d77e4531
PZ		 4521}
4522
20bc8673 4523void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4524{
4525 struct drm_device *dev = crtc->base.dev;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527
6e3c9717 4528 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4529 return;
4530
4531 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4532 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4533 mutex_lock(&dev_priv->rps.hw_lock);
4534 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4535 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4536 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4537 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4538 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4539 } else {
2a114cc1 4540 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4541 POSTING_READ(IPS_CTL);
4542 }
d77e4531
PZ		 4543
4544 /* We need to wait for a vblank before we can disable the plane. */
4545 intel_wait_for_vblank(dev, crtc->pipe);
4546}
4547
4548/** Loads the palette/gamma unit for the CRTC with the prepared values */
4549static void intel_crtc_load_lut(struct drm_crtc *crtc)
4550{
4551 struct drm_device *dev = crtc->dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4554 enum pipe pipe = intel_crtc->pipe;
4555 int palreg = PALETTE(pipe);
4556 int i;
4557 bool reenable_ips = false;
4558
4559 /* The clocks have to be on to load the palette. */
53d9f4e9 4560 if (!crtc->state->active)
d77e4531
PZ		 4561 return;
4562
50360403 4563 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4564 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4565 assert_dsi_pll_enabled(dev_priv);
4566 else
4567 assert_pll_enabled(dev_priv, pipe);
4568 }
4569
4570 /* use legacy palette for Ironlake */
7a1db49a 4571 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4572 palreg = LGC_PALETTE(pipe);
4573
4574 /* Workaround : Do not read or write the pipe palette/gamma data while
4575 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4576 */
6e3c9717 4577 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4578 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4579 GAMMA_MODE_MODE_SPLIT)) {
4580 hsw_disable_ips(intel_crtc);
4581 reenable_ips = true;
4582 }
4583
4584 for (i = 0; i < 256; i++) {
4585 I915_WRITE(palreg + 4 * i,
4586 (intel_crtc->lut_r[i] << 16) |
4587 (intel_crtc->lut_g[i] << 8) |
4588 intel_crtc->lut_b[i]);
4589 }
4590
4591 if (reenable_ips)
4592 hsw_enable_ips(intel_crtc);
4593}
4594
7cac945f 4595static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4596{
7cac945f 4597 if (intel_crtc->overlay) {
d3eedb1a
VS		 4598 struct drm_device *dev = intel_crtc->base.dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600
4601 mutex_lock(&dev->struct_mutex);
4602 dev_priv->mm.interruptible = false;
4603 (void) intel_overlay_switch_off(intel_crtc->overlay);
4604 dev_priv->mm.interruptible = true;
4605 mutex_unlock(&dev->struct_mutex);
4606 }
4607
4608 /* Let userspace switch the overlay on again. In most cases userspace
4609 * has to recompute where to put it anyway.
4610 */
4611}
4612
87d4300a
ML		 4613/**
4614 * intel_post_enable_primary - Perform operations after enabling primary plane
4615 * @crtc: the CRTC whose primary plane was just enabled
4616 *
4617 * Performs potentially sleeping operations that must be done after the primary
4618 * plane is enabled, such as updating FBC and IPS. Note that this may be
4619 * called due to an explicit primary plane update, or due to an implicit
4620 * re-enable that is caused when a sprite plane is updated to no longer
4621 * completely hide the primary plane.
4622 */
4623static void
4624intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4625{
4626 struct drm_device *dev = crtc->dev;
87d4300a 4627 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 int pipe = intel_crtc->pipe;
a5c4d7bc 4630
87d4300a
ML		 4631 /*
4632 * BDW signals flip done immediately if the plane
4633 * is disabled, even if the plane enable is already
4634 * armed to occur at the next vblank :(
4635 */
4636 if (IS_BROADWELL(dev))
4637 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4638
87d4300a
ML		 4639 /*
4640 * FIXME IPS should be fine as long as one plane is
4641 * enabled, but in practice it seems to have problems
4642 * when going from primary only to sprite only and vice
4643 * versa.
4644 */
a5c4d7bc
VS		 4645 hsw_enable_ips(intel_crtc);
4646
f99d7069 4647 /*
87d4300a
ML		 4648 * Gen2 reports pipe underruns whenever all planes are disabled.
4649 * So don't enable underrun reporting before at least some planes
4650 * are enabled.
4651 * FIXME: Need to fix the logic to work when we turn off all planes
4652 * but leave the pipe running.
f99d7069 4653 */
87d4300a
ML		 4654 if (IS_GEN2(dev))
4655 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4656
4657 /* Underruns don't raise interrupts, so check manually. */
4658 if (HAS_GMCH_DISPLAY(dev))
4659 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4660}
4661
87d4300a
ML		 4662/**
4663 * intel_pre_disable_primary - Perform operations before disabling primary plane
4664 * @crtc: the CRTC whose primary plane is to be disabled
4665 *
4666 * Performs potentially sleeping operations that must be done before the
4667 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4668 * be called due to an explicit primary plane update, or due to an implicit
4669 * disable that is caused when a sprite plane completely hides the primary
4670 * plane.
4671 */
4672static void
4673intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4674{
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 int pipe = intel_crtc->pipe;
a5c4d7bc 4679
87d4300a
ML		 4680 /*
4681 * Gen2 reports pipe underruns whenever all planes are disabled.
4682 * So diasble underrun reporting before all the planes get disabled.
4683 * FIXME: Need to fix the logic to work when we turn off all planes
4684 * but leave the pipe running.
4685 */
4686 if (IS_GEN2(dev))
4687 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4688
87d4300a
ML		 4689 /*
4690 * Vblank time updates from the shadow to live plane control register
4691 * are blocked if the memory self-refresh mode is active at that
4692 * moment. So to make sure the plane gets truly disabled, disable
4693 * first the self-refresh mode. The self-refresh enable bit in turn
4694 * will be checked/applied by the HW only at the next frame start
4695 * event which is after the vblank start event, so we need to have a
4696 * wait-for-vblank between disabling the plane and the pipe.
4697 */
4698 if (HAS_GMCH_DISPLAY(dev))
4699 intel_set_memory_cxsr(dev_priv, false);
4700
87d4300a
ML		 4701 /*
4702 * FIXME IPS should be fine as long as one plane is
4703 * enabled, but in practice it seems to have problems
4704 * when going from primary only to sprite only and vice
4705 * versa.
4706 */
a5c4d7bc 4707 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4708}
4709
ac21b225
ML		 4710static void intel_post_plane_update(struct intel_crtc *crtc)
4711{
4712 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4713 struct drm_device *dev = crtc->base.dev;
4714 struct drm_plane *plane;
4715
4716 if (atomic->wait_vblank)
4717 intel_wait_for_vblank(dev, crtc->pipe);
4718
4719 intel_frontbuffer_flip(dev, atomic->fb_bits);
4720
4721 if (atomic->update_fbc) {
4722 mutex_lock(&dev->struct_mutex);
4723 intel_fbc_update(dev);
4724 mutex_unlock(&dev->struct_mutex);
4725 }
4726
4727 if (atomic->post_enable_primary)
4728 intel_post_enable_primary(&crtc->base);
4729
4730 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4731 intel_update_sprite_watermarks(plane, &crtc->base,
4732 0, 0, 0, false, false);
4733
4734 memset(atomic, 0, sizeof(*atomic));
4735}
4736
4737static void intel_pre_plane_update(struct intel_crtc *crtc)
4738{
4739 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4740 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4741 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4742 struct drm_plane *p;
4743
4744 /* Track fb's for any planes being disabled */
4745
4746 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4747 struct intel_plane *plane = to_intel_plane(p);
4748 unsigned fb_bits = 0;
4749
4750 switch (p->type) {
4751 case DRM_PLANE_TYPE_PRIMARY:
4752 fb_bits = INTEL_FRONTBUFFER_PRIMARY(plane->pipe);
4753 break;
4754 case DRM_PLANE_TYPE_CURSOR:
4755 fb_bits = INTEL_FRONTBUFFER_CURSOR(plane->pipe);
4756 break;
4757 case DRM_PLANE_TYPE_OVERLAY:
4758 fb_bits = INTEL_FRONTBUFFER_SPRITE(plane->pipe);
4759 break;
4760 }
4761
4762 mutex_lock(&dev->struct_mutex);
4763 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, fb_bits);
4764 mutex_unlock(&dev->struct_mutex);
4765 }
4766
4767 if (atomic->wait_for_flips)
4768 intel_crtc_wait_for_pending_flips(&crtc->base);
4769
eddfcbcd
ML		 4770 if (atomic->disable_fbc &&
4771 dev_priv->fbc.crtc == crtc) {
4772 mutex_lock(&dev->struct_mutex);
4773 if (dev_priv->fbc.crtc == crtc)
4774 intel_fbc_disable(dev);
4775 mutex_unlock(&dev->struct_mutex);
4776 }
ac21b225
ML		 4777
4778 if (atomic->pre_disable_primary)
4779 intel_pre_disable_primary(&crtc->base);
4780}
4781
d032ffa0 4782static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4783{
4784 struct drm_device *dev = crtc->dev;
4785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4786 struct drm_plane *p;
87d4300a
ML		 4787 int pipe = intel_crtc->pipe;
4788
7cac945f 4789 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4790
d032ffa0
ML		 4791 drm_for_each_plane_mask(p, dev, plane_mask)
4792 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4793
f99d7069
DV		 4794 /*
4795 * FIXME: Once we grow proper nuclear flip support out of this we need
4796 * to compute the mask of flip planes precisely. For the time being
4797 * consider this a flip to a NULL plane.
4798 */
4799 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4800}
4801
f67a559d
JB		 4802static void ironlake_crtc_enable(struct drm_crtc *crtc)
4803{
4804 struct drm_device *dev = crtc->dev;
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4807 struct intel_encoder *encoder;
f67a559d 4808 int pipe = intel_crtc->pipe;
f67a559d 4809
53d9f4e9 4810 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4811 return;
4812
6e3c9717 4813 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4814 intel_prepare_shared_dpll(intel_crtc);
4815
6e3c9717 4816 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4817 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4818
4819 intel_set_pipe_timings(intel_crtc);
4820
6e3c9717 4821 if (intel_crtc->config->has_pch_encoder) {
29407aab 4822 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4823 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4824 }
4825
4826 ironlake_set_pipeconf(crtc);
4827
f67a559d 4828 intel_crtc->active = true;
8664281b 4829
a72e4c9f
DV		 4830 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4831 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4832
f6736a1a 4833 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4834 if (encoder->pre_enable)
4835 encoder->pre_enable(encoder);
f67a559d 4836
6e3c9717 4837 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4838 /* Note: FDI PLL enabling _must_ be done before we enable the
4839 * cpu pipes, hence this is separate from all the other fdi/pch
4840 * enabling. */
88cefb6c 4841 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4842 } else {
4843 assert_fdi_tx_disabled(dev_priv, pipe);
4844 assert_fdi_rx_disabled(dev_priv, pipe);
4845 }
f67a559d 4846
b074cec8 4847 ironlake_pfit_enable(intel_crtc);
f67a559d 4848
9c54c0dd
JB		 4849 /*
4850 * On ILK+ LUT must be loaded before the pipe is running but with
4851 * clocks enabled
4852 */
4853 intel_crtc_load_lut(crtc);
4854
f37fcc2a 4855 intel_update_watermarks(crtc);
e1fdc473 4856 intel_enable_pipe(intel_crtc);
f67a559d 4857
6e3c9717 4858 if (intel_crtc->config->has_pch_encoder)
f67a559d 4859 ironlake_pch_enable(crtc);
c98e9dcf 4860
f9b61ff6
DV		 4861 assert_vblank_disabled(crtc);
4862 drm_crtc_vblank_on(crtc);
4863
fa5c73b1
DV		 4864 for_each_encoder_on_crtc(dev, crtc, encoder)
4865 encoder->enable(encoder);
61b77ddd
DV		 4866
4867 if (HAS_PCH_CPT(dev))
a1520318 4868 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4869}
4870
42db64ef
PZ		 4871/* IPS only exists on ULT machines and is tied to pipe A. */
4872static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4873{
f5adf94e 4874 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4875}
4876
4f771f10
PZ		 4877static void haswell_crtc_enable(struct drm_crtc *crtc)
4878{
4879 struct drm_device *dev = crtc->dev;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882 struct intel_encoder *encoder;
99d736a2
ML		 4883 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4884 struct intel_crtc_state *pipe_config =
4885 to_intel_crtc_state(crtc->state);
4f771f10 4886
53d9f4e9 4887 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4888 return;
4889
df8ad70c
DV		 4890 if (intel_crtc_to_shared_dpll(intel_crtc))
4891 intel_enable_shared_dpll(intel_crtc);
4892
6e3c9717 4893 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4894 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4895
4896 intel_set_pipe_timings(intel_crtc);
4897
6e3c9717
ACO		 4898 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4899 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4900 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4901 }
4902
6e3c9717 4903 if (intel_crtc->config->has_pch_encoder) {
229fca97 4904 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4905 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4906 }
4907
4908 haswell_set_pipeconf(crtc);
4909
4910 intel_set_pipe_csc(crtc);
4911
4f771f10 4912 intel_crtc->active = true;
8664281b 4913
a72e4c9f 4914 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4915 for_each_encoder_on_crtc(dev, crtc, encoder)
4916 if (encoder->pre_enable)
4917 encoder->pre_enable(encoder);
4918
6e3c9717 4919 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4920 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4921 true);
4fe9467d
ID		 4922 dev_priv->display.fdi_link_train(crtc);
4923 }
4924
1f544388 4925 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4926
ff6d9f55 4927 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4928 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4929 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4930 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4931 else
4932 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4933
4934 /*
4935 * On ILK+ LUT must be loaded before the pipe is running but with
4936 * clocks enabled
4937 */
4938 intel_crtc_load_lut(crtc);
4939
1f544388 4940 intel_ddi_set_pipe_settings(crtc);
8228c251 4941 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4942
f37fcc2a 4943 intel_update_watermarks(crtc);
e1fdc473 4944 intel_enable_pipe(intel_crtc);
42db64ef 4945
6e3c9717 4946 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4947 lpt_pch_enable(crtc);
4f771f10 4948
6e3c9717 4949 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4950 intel_ddi_set_vc_payload_alloc(crtc, true);
4951
f9b61ff6
DV		 4952 assert_vblank_disabled(crtc);
4953 drm_crtc_vblank_on(crtc);
4954
8807e55b 4955 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4956 encoder->enable(encoder);
8807e55b
JN		 4957 intel_opregion_notify_encoder(encoder, true);
4958 }
4f771f10 4959
e4916946
PZ		 4960 /* If we change the relative order between pipe/planes enabling, we need
4961 * to change the workaround. */
99d736a2
ML		 4962 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4963 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4964 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4965 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4966 }
4f771f10
PZ		 4967}
4968
3f8dce3a
DV		 4969static void ironlake_pfit_disable(struct intel_crtc *crtc)
4970{
4971 struct drm_device *dev = crtc->base.dev;
4972 struct drm_i915_private *dev_priv = dev->dev_private;
4973 int pipe = crtc->pipe;
4974
4975 /* To avoid upsetting the power well on haswell only disable the pfit if
4976 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4977 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4978 I915_WRITE(PF_CTL(pipe), 0);
4979 I915_WRITE(PF_WIN_POS(pipe), 0);
4980 I915_WRITE(PF_WIN_SZ(pipe), 0);
4981 }
4982}
4983
6be4a607
JB		 4984static void ironlake_crtc_disable(struct drm_crtc *crtc)
4985{
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4989 struct intel_encoder *encoder;
6be4a607 4990 int pipe = intel_crtc->pipe;
5eddb70b 4991 u32 reg, temp;
b52eb4dc 4992
ea9d758d
DV		 4993 for_each_encoder_on_crtc(dev, crtc, encoder)
4994 encoder->disable(encoder);
4995
f9b61ff6
DV		 4996 drm_crtc_vblank_off(crtc);
4997 assert_vblank_disabled(crtc);
4998
6e3c9717 4999 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5000 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5001
575f7ab7 5002 intel_disable_pipe(intel_crtc);
32f9d658 5003
3f8dce3a 5004 ironlake_pfit_disable(intel_crtc);
2c07245f 5005
5a74f70a
VS		 5006 if (intel_crtc->config->has_pch_encoder)
5007 ironlake_fdi_disable(crtc);
5008
bf49ec8c
DV		 5009 for_each_encoder_on_crtc(dev, crtc, encoder)
5010 if (encoder->post_disable)
5011 encoder->post_disable(encoder);
2c07245f 5012
6e3c9717 5013 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5014 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5015
d925c59a
DV		 5016 if (HAS_PCH_CPT(dev)) {
5017 /* disable TRANS_DP_CTL */
5018 reg = TRANS_DP_CTL(pipe);
5019 temp = I915_READ(reg);
5020 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5021 TRANS_DP_PORT_SEL_MASK);
5022 temp |= TRANS_DP_PORT_SEL_NONE;
5023 I915_WRITE(reg, temp);
5024
5025 /* disable DPLL_SEL */
5026 temp = I915_READ(PCH_DPLL_SEL);
11887397 5027 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5028 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5029 }
e3421a18 5030
d925c59a
DV		 5031 ironlake_fdi_pll_disable(intel_crtc);
5032 }
6be4a607 5033}
1b3c7a47 5034
4f771f10 5035static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5036{
4f771f10
PZ		 5037 struct drm_device *dev = crtc->dev;
5038 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5040 struct intel_encoder *encoder;
6e3c9717 5041 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5042
8807e55b
JN		 5043 for_each_encoder_on_crtc(dev, crtc, encoder) {
5044 intel_opregion_notify_encoder(encoder, false);
4f771f10 5045 encoder->disable(encoder);
8807e55b 5046 }
4f771f10 5047
f9b61ff6
DV		 5048 drm_crtc_vblank_off(crtc);
5049 assert_vblank_disabled(crtc);
5050
6e3c9717 5051 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5052 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5053 false);
575f7ab7 5054 intel_disable_pipe(intel_crtc);
4f771f10 5055
6e3c9717 5056 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5057 intel_ddi_set_vc_payload_alloc(crtc, false);
5058
ad80a810 5059 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5060
ff6d9f55 5061 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5062 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5063 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5064 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5065 else
5066 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5067
1f544388 5068 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5069
6e3c9717 5070 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5071 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5072 intel_ddi_fdi_disable(crtc);
83616634 5073 }
4f771f10 5074
97b040aa
ID		 5075 for_each_encoder_on_crtc(dev, crtc, encoder)
5076 if (encoder->post_disable)
5077 encoder->post_disable(encoder);
4f771f10
PZ		 5078}
5079
2dd24552
JB		 5080static void i9xx_pfit_enable(struct intel_crtc *crtc)
5081{
5082 struct drm_device *dev = crtc->base.dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5084 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5085
681a8504 5086 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5087 return;
5088
2dd24552 5089 /*
c0b03411
DV		 5090 * The panel fitter should only be adjusted whilst the pipe is disabled,
5091 * according to register description and PRM.
2dd24552 5092 */
c0b03411
DV		 5093 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5094 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5095
b074cec8
JB		 5096 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5097 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5098
5099 /* Border color in case we don't scale up to the full screen. Black by
5100 * default, change to something else for debugging. */
5101 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5102}
5103
d05410f9
DA		 5104static enum intel_display_power_domain port_to_power_domain(enum port port)
5105{
5106 switch (port) {
5107 case PORT_A:
5108 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5109 case PORT_B:
5110 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5111 case PORT_C:
5112 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5113 case PORT_D:
5114 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5115 default:
5116 WARN_ON_ONCE(1);
5117 return POWER_DOMAIN_PORT_OTHER;
5118 }
5119}
5120
77d22dca
ID		 5121#define for_each_power_domain(domain, mask) \
5122 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5123 if ((1 << (domain)) & (mask))
5124
319be8ae
ID		 5125enum intel_display_power_domain
5126intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5127{
5128 struct drm_device *dev = intel_encoder->base.dev;
5129 struct intel_digital_port *intel_dig_port;
5130
5131 switch (intel_encoder->type) {
5132 case INTEL_OUTPUT_UNKNOWN:
5133 /* Only DDI platforms should ever use this output type */
5134 WARN_ON_ONCE(!HAS_DDI(dev));
5135 case INTEL_OUTPUT_DISPLAYPORT:
5136 case INTEL_OUTPUT_HDMI:
5137 case INTEL_OUTPUT_EDP:
5138 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5139 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5140 case INTEL_OUTPUT_DP_MST:
5141 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5142 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5143 case INTEL_OUTPUT_ANALOG:
5144 return POWER_DOMAIN_PORT_CRT;
5145 case INTEL_OUTPUT_DSI:
5146 return POWER_DOMAIN_PORT_DSI;
5147 default:
5148 return POWER_DOMAIN_PORT_OTHER;
5149 }
5150}
5151
5152static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5153{
319be8ae
ID		 5154 struct drm_device *dev = crtc->dev;
5155 struct intel_encoder *intel_encoder;
5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5157 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5158 unsigned long mask;
5159 enum transcoder transcoder;
5160
5161 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5162
5163 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5164 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5165 if (intel_crtc->config->pch_pfit.enabled ||
5166 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5167 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5168
319be8ae
ID		 5169 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5170 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5171
77d22dca
ID		 5172 return mask;
5173}
5174
679dacd4 5175static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5176{
679dacd4 5177 struct drm_device *dev = state->dev;
77d22dca
ID		 5178 struct drm_i915_private *dev_priv = dev->dev_private;
5179 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5180 struct intel_crtc *crtc;
5181
5182 /*
5183 * First get all needed power domains, then put all unneeded, to avoid
5184 * any unnecessary toggling of the power wells.
5185 */
d3fcc808 5186 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5187 enum intel_display_power_domain domain;
5188
83d65738 5189 if (!crtc->base.state->enable)
77d22dca
ID		 5190 continue;
5191
319be8ae 5192 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5193
5194 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5195 intel_display_power_get(dev_priv, domain);
5196 }
5197
27c329ed
ML		 5198 if (dev_priv->display.modeset_commit_cdclk) {
5199 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5200
5201 if (cdclk != dev_priv->cdclk_freq &&
5202 !WARN_ON(!state->allow_modeset))
5203 dev_priv->display.modeset_commit_cdclk(state);
5204 }
50f6e502 5205
d3fcc808 5206 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5207 enum intel_display_power_domain domain;
5208
5209 for_each_power_domain(domain, crtc->enabled_power_domains)
5210 intel_display_power_put(dev_priv, domain);
5211
5212 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5213 }
5214
5215 intel_display_set_init_power(dev_priv, false);
5216}
5217
560a7ae4
DL		 5218static void intel_update_max_cdclk(struct drm_device *dev)
5219{
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5221
5222 if (IS_SKYLAKE(dev)) {
5223 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5224
5225 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5226 dev_priv->max_cdclk_freq = 675000;
5227 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5228 dev_priv->max_cdclk_freq = 540000;
5229 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5230 dev_priv->max_cdclk_freq = 450000;
5231 else
5232 dev_priv->max_cdclk_freq = 337500;
5233 } else if (IS_BROADWELL(dev)) {
5234 /*
5235 * FIXME with extra cooling we can allow
5236 * 540 MHz for ULX and 675 Mhz for ULT.
5237 * How can we know if extra cooling is
5238 * available? PCI ID, VTB, something else?
5239 */
5240 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5241 dev_priv->max_cdclk_freq = 450000;
5242 else if (IS_BDW_ULX(dev))
5243 dev_priv->max_cdclk_freq = 450000;
5244 else if (IS_BDW_ULT(dev))
5245 dev_priv->max_cdclk_freq = 540000;
5246 else
5247 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5248 } else if (IS_CHERRYVIEW(dev)) {
5249 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5250 } else if (IS_VALLEYVIEW(dev)) {
5251 dev_priv->max_cdclk_freq = 400000;
5252 } else {
5253 /* otherwise assume cdclk is fixed */
5254 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5255 }
5256
5257 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5258 dev_priv->max_cdclk_freq);
5259}
5260
5261static void intel_update_cdclk(struct drm_device *dev)
5262{
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264
5265 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5266 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5267 dev_priv->cdclk_freq);
5268
5269 /*
5270 * Program the gmbus_freq based on the cdclk frequency.
5271 * BSpec erroneously claims we should aim for 4MHz, but
5272 * in fact 1MHz is the correct frequency.
5273 */
5274 if (IS_VALLEYVIEW(dev)) {
5275 /*
5276 * Program the gmbus_freq based on the cdclk frequency.
5277 * BSpec erroneously claims we should aim for 4MHz, but
5278 * in fact 1MHz is the correct frequency.
5279 */
5280 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5281 }
5282
5283 if (dev_priv->max_cdclk_freq == 0)
5284 intel_update_max_cdclk(dev);
5285}
5286
70d0c574 5287static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5288{
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5290 uint32_t divider;
5291 uint32_t ratio;
5292 uint32_t current_freq;
5293 int ret;
5294
5295 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5296 switch (frequency) {
5297 case 144000:
5298 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5299 ratio = BXT_DE_PLL_RATIO(60);
5300 break;
5301 case 288000:
5302 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5303 ratio = BXT_DE_PLL_RATIO(60);
5304 break;
5305 case 384000:
5306 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5307 ratio = BXT_DE_PLL_RATIO(60);
5308 break;
5309 case 576000:
5310 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5311 ratio = BXT_DE_PLL_RATIO(60);
5312 break;
5313 case 624000:
5314 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5315 ratio = BXT_DE_PLL_RATIO(65);
5316 break;
5317 case 19200:
5318 /*
5319 * Bypass frequency with DE PLL disabled. Init ratio, divider
5320 * to suppress GCC warning.
5321 */
5322 ratio = 0;
5323 divider = 0;
5324 break;
5325 default:
5326 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5327
5328 return;
5329 }
5330
5331 mutex_lock(&dev_priv->rps.hw_lock);
5332 /* Inform power controller of upcoming frequency change */
5333 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5334 0x80000000);
5335 mutex_unlock(&dev_priv->rps.hw_lock);
5336
5337 if (ret) {
5338 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5339 ret, frequency);
5340 return;
5341 }
5342
5343 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5344 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5345 current_freq = current_freq * 500 + 1000;
5346
5347 /*
5348 * DE PLL has to be disabled when
5349 * - setting to 19.2MHz (bypass, PLL isn't used)
5350 * - before setting to 624MHz (PLL needs toggling)
5351 * - before setting to any frequency from 624MHz (PLL needs toggling)
5352 */
5353 if (frequency == 19200 || frequency == 624000 ||
5354 current_freq == 624000) {
5355 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5356 /* Timeout 200us */
5357 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5358 1))
5359 DRM_ERROR("timout waiting for DE PLL unlock\n");
5360 }
5361
5362 if (frequency != 19200) {
5363 uint32_t val;
5364
5365 val = I915_READ(BXT_DE_PLL_CTL);
5366 val &= ~BXT_DE_PLL_RATIO_MASK;
5367 val |= ratio;
5368 I915_WRITE(BXT_DE_PLL_CTL, val);
5369
5370 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5371 /* Timeout 200us */
5372 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5373 DRM_ERROR("timeout waiting for DE PLL lock\n");
5374
5375 val = I915_READ(CDCLK_CTL);
5376 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5377 val |= divider;
5378 /*
5379 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5380 * enable otherwise.
5381 */
5382 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5383 if (frequency >= 500000)
5384 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5385
5386 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5387 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5388 val |= (frequency - 1000) / 500;
5389 I915_WRITE(CDCLK_CTL, val);
5390 }
5391
5392 mutex_lock(&dev_priv->rps.hw_lock);
5393 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5394 DIV_ROUND_UP(frequency, 25000));
5395 mutex_unlock(&dev_priv->rps.hw_lock);
5396
5397 if (ret) {
5398 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5399 ret, frequency);
5400 return;
5401 }
5402
a47871bd 5403 intel_update_cdclk(dev);
f8437dd1
VK		 5404}
5405
5406void broxton_init_cdclk(struct drm_device *dev)
5407{
5408 struct drm_i915_private *dev_priv = dev->dev_private;
5409 uint32_t val;
5410
5411 /*
5412 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5413 * or else the reset will hang because there is no PCH to respond.
5414 * Move the handshake programming to initialization sequence.
5415 * Previously was left up to BIOS.
5416 */
5417 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5418 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5419 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5420
5421 /* Enable PG1 for cdclk */
5422 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5423
5424 /* check if cd clock is enabled */
5425 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5426 DRM_DEBUG_KMS("Display already initialized\n");
5427 return;
5428 }
5429
5430 /*
5431 * FIXME:
5432 * - The initial CDCLK needs to be read from VBT.
5433 * Need to make this change after VBT has changes for BXT.
5434 * - check if setting the max (or any) cdclk freq is really necessary
5435 * here, it belongs to modeset time
5436 */
5437 broxton_set_cdclk(dev, 624000);
5438
5439 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5440 POSTING_READ(DBUF_CTL);
5441
f8437dd1
VK		 5442 udelay(10);
5443
5444 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5445 DRM_ERROR("DBuf power enable timeout!\n");
5446}
5447
5448void broxton_uninit_cdclk(struct drm_device *dev)
5449{
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451
5452 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5453 POSTING_READ(DBUF_CTL);
5454
f8437dd1
VK		 5455 udelay(10);
5456
5457 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5458 DRM_ERROR("DBuf power disable timeout!\n");
5459
5460 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5461 broxton_set_cdclk(dev, 19200);
5462
5463 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5464}
5465
5d96d8af
DL		 5466static const struct skl_cdclk_entry {
5467 unsigned int freq;
5468 unsigned int vco;
5469} skl_cdclk_frequencies[] = {
5470 { .freq = 308570, .vco = 8640 },
5471 { .freq = 337500, .vco = 8100 },
5472 { .freq = 432000, .vco = 8640 },
5473 { .freq = 450000, .vco = 8100 },
5474 { .freq = 540000, .vco = 8100 },
5475 { .freq = 617140, .vco = 8640 },
5476 { .freq = 675000, .vco = 8100 },
5477};
5478
5479static unsigned int skl_cdclk_decimal(unsigned int freq)
5480{
5481 return (freq - 1000) / 500;
5482}
5483
5484static unsigned int skl_cdclk_get_vco(unsigned int freq)
5485{
5486 unsigned int i;
5487
5488 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5489 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5490
5491 if (e->freq == freq)
5492 return e->vco;
5493 }
5494
5495 return 8100;
5496}
5497
5498static void
5499skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5500{
5501 unsigned int min_freq;
5502 u32 val;
5503
5504 /* select the minimum CDCLK before enabling DPLL 0 */
5505 val = I915_READ(CDCLK_CTL);
5506 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5507 val |= CDCLK_FREQ_337_308;
5508
5509 if (required_vco == 8640)
5510 min_freq = 308570;
5511 else
5512 min_freq = 337500;
5513
5514 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5515
5516 I915_WRITE(CDCLK_CTL, val);
5517 POSTING_READ(CDCLK_CTL);
5518
5519 /*
5520 * We always enable DPLL0 with the lowest link rate possible, but still
5521 * taking into account the VCO required to operate the eDP panel at the
5522 * desired frequency. The usual DP link rates operate with a VCO of
5523 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5524 * The modeset code is responsible for the selection of the exact link
5525 * rate later on, with the constraint of choosing a frequency that
5526 * works with required_vco.
5527 */
5528 val = I915_READ(DPLL_CTRL1);
5529
5530 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5531 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5532 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5533 if (required_vco == 8640)
5534 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5535 SKL_DPLL0);
5536 else
5537 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5538 SKL_DPLL0);
5539
5540 I915_WRITE(DPLL_CTRL1, val);
5541 POSTING_READ(DPLL_CTRL1);
5542
5543 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5544
5545 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5546 DRM_ERROR("DPLL0 not locked\n");
5547}
5548
5549static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5550{
5551 int ret;
5552 u32 val;
5553
5554 /* inform PCU we want to change CDCLK */
5555 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5556 mutex_lock(&dev_priv->rps.hw_lock);
5557 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5558 mutex_unlock(&dev_priv->rps.hw_lock);
5559
5560 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5561}
5562
5563static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5564{
5565 unsigned int i;
5566
5567 for (i = 0; i < 15; i++) {
5568 if (skl_cdclk_pcu_ready(dev_priv))
5569 return true;
5570 udelay(10);
5571 }
5572
5573 return false;
5574}
5575
5576static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5577{
560a7ae4 5578 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5579 u32 freq_select, pcu_ack;
5580
5581 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5582
5583 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5584 DRM_ERROR("failed to inform PCU about cdclk change\n");
5585 return;
5586 }
5587
5588 /* set CDCLK_CTL */
5589 switch(freq) {
5590 case 450000:
5591 case 432000:
5592 freq_select = CDCLK_FREQ_450_432;
5593 pcu_ack = 1;
5594 break;
5595 case 540000:
5596 freq_select = CDCLK_FREQ_540;
5597 pcu_ack = 2;
5598 break;
5599 case 308570:
5600 case 337500:
5601 default:
5602 freq_select = CDCLK_FREQ_337_308;
5603 pcu_ack = 0;
5604 break;
5605 case 617140:
5606 case 675000:
5607 freq_select = CDCLK_FREQ_675_617;
5608 pcu_ack = 3;
5609 break;
5610 }
5611
5612 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5613 POSTING_READ(CDCLK_CTL);
5614
5615 /* inform PCU of the change */
5616 mutex_lock(&dev_priv->rps.hw_lock);
5617 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5618 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5619
5620 intel_update_cdclk(dev);
5d96d8af
DL		 5621}
5622
5623void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5624{
5625 /* disable DBUF power */
5626 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5627 POSTING_READ(DBUF_CTL);
5628
5629 udelay(10);
5630
5631 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5632 DRM_ERROR("DBuf power disable timeout\n");
5633
5634 /* disable DPLL0 */
5635 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5636 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5637 DRM_ERROR("Couldn't disable DPLL0\n");
5638
5639 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5640}
5641
5642void skl_init_cdclk(struct drm_i915_private *dev_priv)
5643{
5644 u32 val;
5645 unsigned int required_vco;
5646
5647 /* enable PCH reset handshake */
5648 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5649 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5650
5651 /* enable PG1 and Misc I/O */
5652 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5653
5654 /* DPLL0 already enabed !? */
5655 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5656 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5657 return;
5658 }
5659
5660 /* enable DPLL0 */
5661 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5662 skl_dpll0_enable(dev_priv, required_vco);
5663
5664 /* set CDCLK to the frequency the BIOS chose */
5665 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5666
5667 /* enable DBUF power */
5668 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5669 POSTING_READ(DBUF_CTL);
5670
5671 udelay(10);
5672
5673 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5674 DRM_ERROR("DBuf power enable timeout\n");
5675}
5676
dfcab17e 5677/* returns HPLL frequency in kHz */
f8bf63fd 5678static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5679{
586f49dc 5680 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5681
586f49dc 5682 /* Obtain SKU information */
a580516d 5683 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5684 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5685 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5686 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5687
dfcab17e 5688 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5689}
5690
5691/* Adjust CDclk dividers to allow high res or save power if possible */
5692static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5693{
5694 struct drm_i915_private *dev_priv = dev->dev_private;
5695 u32 val, cmd;
5696
164dfd28
VK		 5697 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5698 != dev_priv->cdclk_freq);
d60c4473 5699
dfcab17e 5700 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5701 cmd = 2;
dfcab17e 5702 else if (cdclk == 266667)
30a970c6
JB		 5703 cmd = 1;
5704 else
5705 cmd = 0;
5706
5707 mutex_lock(&dev_priv->rps.hw_lock);
5708 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5709 val &= ~DSPFREQGUAR_MASK;
5710 val |= (cmd << DSPFREQGUAR_SHIFT);
5711 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5712 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5713 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5714 50)) {
5715 DRM_ERROR("timed out waiting for CDclk change\n");
5716 }
5717 mutex_unlock(&dev_priv->rps.hw_lock);
5718
54433e91
VS		 5719 mutex_lock(&dev_priv->sb_lock);
5720
dfcab17e 5721 if (cdclk == 400000) {
6bcda4f0 5722 u32 divider;
30a970c6 5723
6bcda4f0 5724 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5725
30a970c6
JB		 5726 /* adjust cdclk divider */
5727 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5728 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5729 val |= divider;
5730 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5731
5732 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5733 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5734 50))
5735 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5736 }
5737
30a970c6
JB		 5738 /* adjust self-refresh exit latency value */
5739 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5740 val &= ~0x7f;
5741
5742 /*
5743 * For high bandwidth configs, we set a higher latency in the bunit
5744 * so that the core display fetch happens in time to avoid underruns.
5745 */
dfcab17e 5746 if (cdclk == 400000)
30a970c6
JB		 5747 val |= 4500 / 250; /* 4.5 usec */
5748 else
5749 val |= 3000 / 250; /* 3.0 usec */
5750 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5751
a580516d 5752 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5753
b6283055 5754 intel_update_cdclk(dev);
30a970c6
JB		 5755}
5756
383c5a6a
VS		 5757static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5758{
5759 struct drm_i915_private *dev_priv = dev->dev_private;
5760 u32 val, cmd;
5761
164dfd28
VK		 5762 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5763 != dev_priv->cdclk_freq);
383c5a6a
VS		 5764
5765 switch (cdclk) {
383c5a6a
VS		 5766 case 333333:
5767 case 320000:
383c5a6a 5768 case 266667:
383c5a6a 5769 case 200000:
383c5a6a
VS		 5770 break;
5771 default:
5f77eeb0 5772 MISSING_CASE(cdclk);
383c5a6a
VS		 5773 return;
5774 }
5775
9d0d3fda
VS		 5776 /*
5777 * Specs are full of misinformation, but testing on actual
5778 * hardware has shown that we just need to write the desired
5779 * CCK divider into the Punit register.
5780 */
5781 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5782
383c5a6a
VS		 5783 mutex_lock(&dev_priv->rps.hw_lock);
5784 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5785 val &= ~DSPFREQGUAR_MASK_CHV;
5786 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5787 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5788 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5789 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5790 50)) {
5791 DRM_ERROR("timed out waiting for CDclk change\n");
5792 }
5793 mutex_unlock(&dev_priv->rps.hw_lock);
5794
b6283055 5795 intel_update_cdclk(dev);
383c5a6a
VS		 5796}
5797
30a970c6
JB		 5798static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5799 int max_pixclk)
5800{
6bcda4f0 5801 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5802 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5803
30a970c6
JB		 5804 /*
5805 * Really only a few cases to deal with, as only 4 CDclks are supported:
5806 * 200MHz
5807 * 267MHz
29dc7ef3 5808 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5809 * 400MHz (VLV only)
5810 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5811 * of the lower bin and adjust if needed.
e37c67a1
VS		 5812 *
5813 * We seem to get an unstable or solid color picture at 200MHz.
5814 * Not sure what's wrong. For now use 200MHz only when all pipes
5815 * are off.
30a970c6 5816 */
6cca3195
VS		 5817 if (!IS_CHERRYVIEW(dev_priv) &&
5818 max_pixclk > freq_320*limit/100)
dfcab17e 5819 return 400000;
6cca3195 5820 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5821 return freq_320;
e37c67a1 5822 else if (max_pixclk > 0)
dfcab17e 5823 return 266667;
e37c67a1
VS		 5824 else
5825 return 200000;
30a970c6
JB		 5826}
5827
f8437dd1
VK		 5828static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5829 int max_pixclk)
5830{
5831 /*
5832 * FIXME:
5833 * - remove the guardband, it's not needed on BXT
5834 * - set 19.2MHz bypass frequency if there are no active pipes
5835 */
5836 if (max_pixclk > 576000*9/10)
5837 return 624000;
5838 else if (max_pixclk > 384000*9/10)
5839 return 576000;
5840 else if (max_pixclk > 288000*9/10)
5841 return 384000;
5842 else if (max_pixclk > 144000*9/10)
5843 return 288000;
5844 else
5845 return 144000;
5846}
5847
a821fc46
ACO		 5848/* Compute the max pixel clock for new configuration. Uses atomic state if
5849 * that's non-NULL, look at current state otherwise. */
5850static int intel_mode_max_pixclk(struct drm_device *dev,
5851 struct drm_atomic_state *state)
30a970c6 5852{
30a970c6 5853 struct intel_crtc *intel_crtc;
304603f4 5854 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5855 int max_pixclk = 0;
5856
d3fcc808 5857 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5858 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5859 if (IS_ERR(crtc_state))
5860 return PTR_ERR(crtc_state);
5861
5862 if (!crtc_state->base.enable)
5863 continue;
5864
5865 max_pixclk = max(max_pixclk,
5866 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5867 }
5868
5869 return max_pixclk;
5870}
5871
27c329ed 5872static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5873{
27c329ed
ML		 5874 struct drm_device *dev = state->dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5877
304603f4
ACO		 5878 if (max_pixclk < 0)
5879 return max_pixclk;
30a970c6 5880
27c329ed
ML		 5881 to_intel_atomic_state(state)->cdclk =
5882 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5883
27c329ed
ML		 5884 return 0;
5885}
304603f4 5886
27c329ed
ML		 5887static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5888{
5889 struct drm_device *dev = state->dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5892
27c329ed
ML		 5893 if (max_pixclk < 0)
5894 return max_pixclk;
85a96e7a 5895
27c329ed
ML		 5896 to_intel_atomic_state(state)->cdclk =
5897 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5898
27c329ed 5899 return 0;
30a970c6
JB		 5900}
5901
1e69cd74
VS		 5902static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5903{
5904 unsigned int credits, default_credits;
5905
5906 if (IS_CHERRYVIEW(dev_priv))
5907 default_credits = PFI_CREDIT(12);
5908 else
5909 default_credits = PFI_CREDIT(8);
5910
164dfd28 5911 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5912 /* CHV suggested value is 31 or 63 */
5913 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5914 credits = PFI_CREDIT_63;
1e69cd74
VS		 5915 else
5916 credits = PFI_CREDIT(15);
5917 } else {
5918 credits = default_credits;
5919 }
5920
5921 /*
5922 * WA - write default credits before re-programming
5923 * FIXME: should we also set the resend bit here?
5924 */
5925 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5926 default_credits);
5927
5928 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5929 credits | PFI_CREDIT_RESEND);
5930
5931 /*
5932 * FIXME is this guaranteed to clear
5933 * immediately or should we poll for it?
5934 */
5935 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5936}
5937
27c329ed 5938static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5939{
a821fc46 5940 struct drm_device *dev = old_state->dev;
27c329ed 5941 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5942 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5943
27c329ed
ML		 5944 /*
5945 * FIXME: We can end up here with all power domains off, yet
5946 * with a CDCLK frequency other than the minimum. To account
5947 * for this take the PIPE-A power domain, which covers the HW
5948 * blocks needed for the following programming. This can be
5949 * removed once it's guaranteed that we get here either with
5950 * the minimum CDCLK set, or the required power domains
5951 * enabled.
5952 */
5953 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5954
27c329ed
ML		 5955 if (IS_CHERRYVIEW(dev))
5956 cherryview_set_cdclk(dev, req_cdclk);
5957 else
5958 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5959
27c329ed 5960 vlv_program_pfi_credits(dev_priv);
1e69cd74 5961
27c329ed 5962 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5963}
5964
89b667f8
JB		 5965static void valleyview_crtc_enable(struct drm_crtc *crtc)
5966{
5967 struct drm_device *dev = crtc->dev;
a72e4c9f 5968 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970 struct intel_encoder *encoder;
5971 int pipe = intel_crtc->pipe;
23538ef1 5972 bool is_dsi;
89b667f8 5973
53d9f4e9 5974 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 5975 return;
5976
409ee761 5977 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5978
1ae0d137
VS		 5979 if (!is_dsi) {
5980 if (IS_CHERRYVIEW(dev))
6e3c9717 5981 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5982 else
6e3c9717 5983 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5984 }
5b18e57c 5985
6e3c9717 5986 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5987 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5988
5989 intel_set_pipe_timings(intel_crtc);
5990
c14b0485
VS		 5991 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5992 struct drm_i915_private *dev_priv = dev->dev_private;
5993
5994 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5995 I915_WRITE(CHV_CANVAS(pipe), 0);
5996 }
5997
5b18e57c
DV		 5998 i9xx_set_pipeconf(intel_crtc);
5999
89b667f8 6000 intel_crtc->active = true;
89b667f8 6001
a72e4c9f 6002 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6003
89b667f8
JB		 6004 for_each_encoder_on_crtc(dev, crtc, encoder)
6005 if (encoder->pre_pll_enable)
6006 encoder->pre_pll_enable(encoder);
6007
9d556c99
CML		 6008 if (!is_dsi) {
6009 if (IS_CHERRYVIEW(dev))
6e3c9717 6010 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6011 else
6e3c9717 6012 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6013 }
89b667f8
JB		 6014
6015 for_each_encoder_on_crtc(dev, crtc, encoder)
6016 if (encoder->pre_enable)
6017 encoder->pre_enable(encoder);
6018
2dd24552
JB		 6019 i9xx_pfit_enable(intel_crtc);
6020
63cbb074
VS		 6021 intel_crtc_load_lut(crtc);
6022
f37fcc2a 6023 intel_update_watermarks(crtc);
e1fdc473 6024 intel_enable_pipe(intel_crtc);
be6a6f8e 6025
4b3a9526
VS		 6026 assert_vblank_disabled(crtc);
6027 drm_crtc_vblank_on(crtc);
6028
f9b61ff6
DV		 6029 for_each_encoder_on_crtc(dev, crtc, encoder)
6030 encoder->enable(encoder);
89b667f8
JB		 6031}
6032
f13c2ef3
DV		 6033static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6034{
6035 struct drm_device *dev = crtc->base.dev;
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037
6e3c9717
ACO		 6038 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6039 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6040}
6041
0b8765c6 6042static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6043{
6044 struct drm_device *dev = crtc->dev;
a72e4c9f 6045 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6047 struct intel_encoder *encoder;
79e53945 6048 int pipe = intel_crtc->pipe;
79e53945 6049
53d9f4e9 6050 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6051 return;
6052
f13c2ef3
DV		 6053 i9xx_set_pll_dividers(intel_crtc);
6054
6e3c9717 6055 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6056 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6057
6058 intel_set_pipe_timings(intel_crtc);
6059
5b18e57c
DV		 6060 i9xx_set_pipeconf(intel_crtc);
6061
f7abfe8b 6062 intel_crtc->active = true;
6b383a7f 6063
4a3436e8 6064 if (!IS_GEN2(dev))
a72e4c9f 6065 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6066
9d6d9f19
MK		 6067 for_each_encoder_on_crtc(dev, crtc, encoder)
6068 if (encoder->pre_enable)
6069 encoder->pre_enable(encoder);
6070
f6736a1a
DV		 6071 i9xx_enable_pll(intel_crtc);
6072
2dd24552
JB		 6073 i9xx_pfit_enable(intel_crtc);
6074
63cbb074
VS		 6075 intel_crtc_load_lut(crtc);
6076
f37fcc2a 6077 intel_update_watermarks(crtc);
e1fdc473 6078 intel_enable_pipe(intel_crtc);
be6a6f8e 6079
4b3a9526
VS		 6080 assert_vblank_disabled(crtc);
6081 drm_crtc_vblank_on(crtc);
6082
f9b61ff6
DV		 6083 for_each_encoder_on_crtc(dev, crtc, encoder)
6084 encoder->enable(encoder);
0b8765c6 6085}
79e53945 6086
87476d63
DV		 6087static void i9xx_pfit_disable(struct intel_crtc *crtc)
6088{
6089 struct drm_device *dev = crtc->base.dev;
6090 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6091
6e3c9717 6092 if (!crtc->config->gmch_pfit.control)
328d8e82 6093 return;
87476d63 6094
328d8e82 6095 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6096
328d8e82
DV		 6097 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6098 I915_READ(PFIT_CONTROL));
6099 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6100}
6101
0b8765c6
JB		 6102static void i9xx_crtc_disable(struct drm_crtc *crtc)
6103{
6104 struct drm_device *dev = crtc->dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6107 struct intel_encoder *encoder;
0b8765c6 6108 int pipe = intel_crtc->pipe;
ef9c3aee 6109
6304cd91
VS		 6110 /*
6111 * On gen2 planes are double buffered but the pipe isn't, so we must
6112 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6113 * We also need to wait on all gmch platforms because of the
6114 * self-refresh mode constraint explained above.
6304cd91 6115 */
564ed191 6116 intel_wait_for_vblank(dev, pipe);
6304cd91 6117
4b3a9526
VS		 6118 for_each_encoder_on_crtc(dev, crtc, encoder)
6119 encoder->disable(encoder);
6120
f9b61ff6
DV		 6121 drm_crtc_vblank_off(crtc);
6122 assert_vblank_disabled(crtc);
6123
575f7ab7 6124 intel_disable_pipe(intel_crtc);
24a1f16d 6125
87476d63 6126 i9xx_pfit_disable(intel_crtc);
24a1f16d 6127
89b667f8
JB		 6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 if (encoder->post_disable)
6130 encoder->post_disable(encoder);
6131
409ee761 6132 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6133 if (IS_CHERRYVIEW(dev))
6134 chv_disable_pll(dev_priv, pipe);
6135 else if (IS_VALLEYVIEW(dev))
6136 vlv_disable_pll(dev_priv, pipe);
6137 else
1c4e0274 6138 i9xx_disable_pll(intel_crtc);
076ed3b2 6139 }
0b8765c6 6140
4a3436e8 6141 if (!IS_GEN2(dev))
a72e4c9f 6142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6143}
6144
b17d48e2
ML		 6145static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6146{
6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6149 enum intel_display_power_domain domain;
6150 unsigned long domains;
6151
6152 if (!intel_crtc->active)
6153 return;
6154
a539205a
ML		 6155 if (to_intel_plane_state(crtc->primary->state)->visible) {
6156 intel_crtc_wait_for_pending_flips(crtc);
6157 intel_pre_disable_primary(crtc);
6158 }
6159
d032ffa0 6160 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6161 dev_priv->display.crtc_disable(crtc);
6162
6163 domains = intel_crtc->enabled_power_domains;
6164 for_each_power_domain(domain, domains)
6165 intel_display_power_put(dev_priv, domain);
6166 intel_crtc->enabled_power_domains = 0;
6167}
6168
6b72d486
ML		 6169/*
6170 * turn all crtc's off, but do not adjust state
6171 * This has to be paired with a call to intel_modeset_setup_hw_state.
6172 */
9716c691 6173void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6174{
6b72d486
ML		 6175 struct drm_crtc *crtc;
6176
b17d48e2
ML		 6177 for_each_crtc(dev, crtc)
6178 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6179}
6180
b04c5bd6 6181/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6182int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6183{
6184 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6185 struct drm_mode_config *config = &dev->mode_config;
6186 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6188 struct intel_crtc_state *pipe_config;
6189 struct drm_atomic_state *state;
6190 int ret;
976f8a20 6191
1b509259 6192 if (enable == intel_crtc->active)
5da76e94 6193 return 0;
0e572fe7 6194
1b509259 6195 if (enable && !crtc->state->enable)
5da76e94 6196 return 0;
1b509259 6197
5da76e94
ML		 6198 /* this function should be called with drm_modeset_lock_all for now */
6199 if (WARN_ON(!ctx))
6200 return -EIO;
6201 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6202
5da76e94
ML		 6203 state = drm_atomic_state_alloc(dev);
6204 if (WARN_ON(!state))
6205 return -ENOMEM;
1b509259 6206
5da76e94
ML		 6207 state->acquire_ctx = ctx;
6208 state->allow_modeset = true;
6209
6210 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6211 if (IS_ERR(pipe_config)) {
6212 ret = PTR_ERR(pipe_config);
6213 goto err;
0e572fe7 6214 }
5da76e94
ML		 6215 pipe_config->base.active = enable;
6216
6217 ret = intel_set_mode(state);
6218 if (!ret)
6219 return ret;
6220
6221err:
6222 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6223 drm_atomic_state_free(state);
6224 return ret;
b04c5bd6
BF		 6225}
6226
6227/**
6228 * Sets the power management mode of the pipe and plane.
6229 */
6230void intel_crtc_update_dpms(struct drm_crtc *crtc)
6231{
6232 struct drm_device *dev = crtc->dev;
6233 struct intel_encoder *intel_encoder;
6234 bool enable = false;
6235
6236 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6237 enable |= intel_encoder->connectors_active;
6238
6239 intel_crtc_control(crtc, enable);
cdd59983
CW		 6240}
6241
ea5b213a 6242void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6243{
4ef69c7a 6244 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6245
ea5b213a
CW		 6246 drm_encoder_cleanup(encoder);
6247 kfree(intel_encoder);
7e7d76c3
JB		 6248}
6249
9237329d 6250/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6251 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6252 * state of the entire output pipe. */
9237329d 6253static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6254{
5ab432ef
DV		 6255 if (mode == DRM_MODE_DPMS_ON) {
6256 encoder->connectors_active = true;
6257
b2cabb0e 6258 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6259 } else {
6260 encoder->connectors_active = false;
6261
b2cabb0e 6262 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6263 }
79e53945
JB		 6264}
6265
0a91ca29
DV		 6266/* Cross check the actual hw state with our own modeset state tracking (and it's
6267 * internal consistency). */
b980514c 6268static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6269{
0a91ca29
DV		 6270 if (connector->get_hw_state(connector)) {
6271 struct intel_encoder *encoder = connector->encoder;
6272 struct drm_crtc *crtc;
6273 bool encoder_enabled;
6274 enum pipe pipe;
6275
6276 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6277 connector->base.base.id,
c23cc417 6278 connector->base.name);
0a91ca29 6279
0e32b39c
DA		 6280 /* there is no real hw state for MST connectors */
6281 if (connector->mst_port)
6282 return;
6283
e2c719b7 6284 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6285 "wrong connector dpms state\n");
e2c719b7 6286 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6287 "active connector not linked to encoder\n");
0a91ca29 6288
36cd7444 6289 if (encoder) {
e2c719b7 6290 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6291 "encoder->connectors_active not set\n");
6292
6293 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6294 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6295 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6296 return;
0a91ca29 6297
36cd7444 6298 crtc = encoder->base.crtc;
0a91ca29 6299
83d65738
MR		 6300 I915_STATE_WARN(!crtc->state->enable,
6301 "crtc not enabled\n");
e2c719b7
RC		 6302 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6303 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6304 "encoder active on the wrong pipe\n");
6305 }
0a91ca29 6306 }
79e53945
JB		 6307}
6308
08d9bc92
ACO		 6309int intel_connector_init(struct intel_connector *connector)
6310{
6311 struct drm_connector_state *connector_state;
6312
6313 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6314 if (!connector_state)
6315 return -ENOMEM;
6316
6317 connector->base.state = connector_state;
6318 return 0;
6319}
6320
6321struct intel_connector *intel_connector_alloc(void)
6322{
6323 struct intel_connector *connector;
6324
6325 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6326 if (!connector)
6327 return NULL;
6328
6329 if (intel_connector_init(connector) < 0) {
6330 kfree(connector);
6331 return NULL;
6332 }
6333
6334 return connector;
6335}
6336
5ab432ef
DV		 6337/* Even simpler default implementation, if there's really no special case to
6338 * consider. */
6339void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6340{
5ab432ef
DV		 6341 /* All the simple cases only support two dpms states. */
6342 if (mode != DRM_MODE_DPMS_ON)
6343 mode = DRM_MODE_DPMS_OFF;
d4270e57 6344
5ab432ef
DV		 6345 if (mode == connector->dpms)
6346 return;
6347
6348 connector->dpms = mode;
6349
6350 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6351 if (connector->encoder)
6352 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6353
b980514c 6354 intel_modeset_check_state(connector->dev);
79e53945
JB		 6355}
6356
f0947c37
DV		 6357/* Simple connector->get_hw_state implementation for encoders that support only
6358 * one connector and no cloning and hence the encoder state determines the state
6359 * of the connector. */
6360bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6361{
24929352 6362 enum pipe pipe = 0;
f0947c37 6363 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6364
f0947c37 6365 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6366}
6367
6d293983 6368static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6369{
6d293983
ACO		 6370 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6371 return crtc_state->fdi_lanes;
d272ddfa
VS		 6372
6373 return 0;
6374}
6375
6d293983 6376static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6377 struct intel_crtc_state *pipe_config)
1857e1da 6378{
6d293983
ACO		 6379 struct drm_atomic_state *state = pipe_config->base.state;
6380 struct intel_crtc *other_crtc;
6381 struct intel_crtc_state *other_crtc_state;
6382
1857e1da
DV		 6383 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6384 pipe_name(pipe), pipe_config->fdi_lanes);
6385 if (pipe_config->fdi_lanes > 4) {
6386 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6387 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6388 return -EINVAL;
1857e1da
DV		 6389 }
6390
bafb6553 6391 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6392 if (pipe_config->fdi_lanes > 2) {
6393 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6394 pipe_config->fdi_lanes);
6d293983 6395 return -EINVAL;
1857e1da 6396 } else {
6d293983 6397 return 0;
1857e1da
DV		 6398 }
6399 }
6400
6401 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6402 return 0;
1857e1da
DV		 6403
6404 /* Ivybridge 3 pipe is really complicated */
6405 switch (pipe) {
6406 case PIPE_A:
6d293983 6407 return 0;
1857e1da 6408 case PIPE_B:
6d293983
ACO		 6409 if (pipe_config->fdi_lanes <= 2)
6410 return 0;
6411
6412 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6413 other_crtc_state =
6414 intel_atomic_get_crtc_state(state, other_crtc);
6415 if (IS_ERR(other_crtc_state))
6416 return PTR_ERR(other_crtc_state);
6417
6418 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6419 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6420 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6421 return -EINVAL;
1857e1da 6422 }
6d293983 6423 return 0;
1857e1da 6424 case PIPE_C:
251cc67c
VS		 6425 if (pipe_config->fdi_lanes > 2) {
6426 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6427 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6428 return -EINVAL;
251cc67c 6429 }
6d293983
ACO		 6430
6431 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6432 other_crtc_state =
6433 intel_atomic_get_crtc_state(state, other_crtc);
6434 if (IS_ERR(other_crtc_state))
6435 return PTR_ERR(other_crtc_state);
6436
6437 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6438 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6439 return -EINVAL;
1857e1da 6440 }
6d293983 6441 return 0;
1857e1da
DV		 6442 default:
6443 BUG();
6444 }
6445}
6446
e29c22c0
DV		 6447#define RETRY 1
6448static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6449 struct intel_crtc_state *pipe_config)
877d48d5 6450{
1857e1da 6451 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6452 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6453 int lane, link_bw, fdi_dotclock, ret;
6454 bool needs_recompute = false;
877d48d5 6455
e29c22c0 6456retry:
877d48d5
DV		 6457 /* FDI is a binary signal running at ~2.7GHz, encoding
6458 * each output octet as 10 bits. The actual frequency
6459 * is stored as a divider into a 100MHz clock, and the
6460 * mode pixel clock is stored in units of 1KHz.
6461 * Hence the bw of each lane in terms of the mode signal
6462 * is:
6463 */
6464 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6465
241bfc38 6466 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6467
2bd89a07 6468 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6469 pipe_config->pipe_bpp);
6470
6471 pipe_config->fdi_lanes = lane;
6472
2bd89a07 6473 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6474 link_bw, &pipe_config->fdi_m_n);
1857e1da 6475
6d293983
ACO		 6476 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6477 intel_crtc->pipe, pipe_config);
6478 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6479 pipe_config->pipe_bpp -= 2*3;
6480 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6481 pipe_config->pipe_bpp);
6482 needs_recompute = true;
6483 pipe_config->bw_constrained = true;
6484
6485 goto retry;
6486 }
6487
6488 if (needs_recompute)
6489 return RETRY;
6490
6d293983 6491 return ret;
877d48d5
DV		 6492}
6493
8cfb3407
VS		 6494static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6495 struct intel_crtc_state *pipe_config)
6496{
6497 if (pipe_config->pipe_bpp > 24)
6498 return false;
6499
6500 /* HSW can handle pixel rate up to cdclk? */
6501 if (IS_HASWELL(dev_priv->dev))
6502 return true;
6503
6504 /*
b432e5cf
VS		 6505 * We compare against max which means we must take
6506 * the increased cdclk requirement into account when
6507 * calculating the new cdclk.
6508 *
6509 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6510 */
6511 return ilk_pipe_pixel_rate(pipe_config) <=
6512 dev_priv->max_cdclk_freq * 95 / 100;
6513}
6514
42db64ef 6515static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6516 struct intel_crtc_state *pipe_config)
42db64ef 6517{
8cfb3407
VS		 6518 struct drm_device *dev = crtc->base.dev;
6519 struct drm_i915_private *dev_priv = dev->dev_private;
6520
d330a953 6521 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6522 hsw_crtc_supports_ips(crtc) &&
6523 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6524}
6525
a43f6e0f 6526static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6527 struct intel_crtc_state *pipe_config)
79e53945 6528{
a43f6e0f 6529 struct drm_device *dev = crtc->base.dev;
8bd31e67 6530 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6531 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6532
ad3a4479 6533 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6534 if (INTEL_INFO(dev)->gen < 4) {
44913155 6535 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6536
6537 /*
6538 * Enable pixel doubling when the dot clock
6539 * is > 90% of the (display) core speed.
6540 *
b397c96b
VS		 6541 * GDG double wide on either pipe,
6542 * otherwise pipe A only.
cf532bb2 6543 */
b397c96b 6544 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6545 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6546 clock_limit *= 2;
cf532bb2 6547 pipe_config->double_wide = true;
ad3a4479
VS		 6548 }
6549
241bfc38 6550 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6551 return -EINVAL;
2c07245f 6552 }
89749350 6553
1d1d0e27
VS		 6554 /*
6555 * Pipe horizontal size must be even in:
6556 * - DVO ganged mode
6557 * - LVDS dual channel mode
6558 * - Double wide pipe
6559 */
a93e255f 6560 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6561 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6562 pipe_config->pipe_src_w &= ~1;
6563
8693a824
DL		 6564 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6565 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6566 */
6567 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6568 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6569 return -EINVAL;
44f46b42 6570
f5adf94e 6571 if (HAS_IPS(dev))
a43f6e0f
DV		 6572 hsw_compute_ips_config(crtc, pipe_config);
6573
877d48d5 6574 if (pipe_config->has_pch_encoder)
a43f6e0f 6575 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6576
cf5a15be 6577 return 0;
79e53945
JB		 6578}
6579
1652d19e
VS		 6580static int skylake_get_display_clock_speed(struct drm_device *dev)
6581{
6582 struct drm_i915_private *dev_priv = to_i915(dev);
6583 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6584 uint32_t cdctl = I915_READ(CDCLK_CTL);
6585 uint32_t linkrate;
6586
414355a7 6587 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6588 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6589
6590 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6591 return 540000;
6592
6593 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6594 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6595
71cd8423
DL		 6596 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6597 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6598 /* vco 8640 */
6599 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6600 case CDCLK_FREQ_450_432:
6601 return 432000;
6602 case CDCLK_FREQ_337_308:
6603 return 308570;
6604 case CDCLK_FREQ_675_617:
6605 return 617140;
6606 default:
6607 WARN(1, "Unknown cd freq selection\n");
6608 }
6609 } else {
6610 /* vco 8100 */
6611 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6612 case CDCLK_FREQ_450_432:
6613 return 450000;
6614 case CDCLK_FREQ_337_308:
6615 return 337500;
6616 case CDCLK_FREQ_675_617:
6617 return 675000;
6618 default:
6619 WARN(1, "Unknown cd freq selection\n");
6620 }
6621 }
6622
6623 /* error case, do as if DPLL0 isn't enabled */
6624 return 24000;
6625}
6626
acd3f3d3
BP		 6627static int broxton_get_display_clock_speed(struct drm_device *dev)
6628{
6629 struct drm_i915_private *dev_priv = to_i915(dev);
6630 uint32_t cdctl = I915_READ(CDCLK_CTL);
6631 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6632 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6633 int cdclk;
6634
6635 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6636 return 19200;
6637
6638 cdclk = 19200 * pll_ratio / 2;
6639
6640 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6641 case BXT_CDCLK_CD2X_DIV_SEL_1:
6642 return cdclk; /* 576MHz or 624MHz */
6643 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6644 return cdclk * 2 / 3; /* 384MHz */
6645 case BXT_CDCLK_CD2X_DIV_SEL_2:
6646 return cdclk / 2; /* 288MHz */
6647 case BXT_CDCLK_CD2X_DIV_SEL_4:
6648 return cdclk / 4; /* 144MHz */
6649 }
6650
6651 /* error case, do as if DE PLL isn't enabled */
6652 return 19200;
6653}
6654
1652d19e
VS		 6655static int broadwell_get_display_clock_speed(struct drm_device *dev)
6656{
6657 struct drm_i915_private *dev_priv = dev->dev_private;
6658 uint32_t lcpll = I915_READ(LCPLL_CTL);
6659 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6660
6661 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6662 return 800000;
6663 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6664 return 450000;
6665 else if (freq == LCPLL_CLK_FREQ_450)
6666 return 450000;
6667 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6668 return 540000;
6669 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6670 return 337500;
6671 else
6672 return 675000;
6673}
6674
6675static int haswell_get_display_clock_speed(struct drm_device *dev)
6676{
6677 struct drm_i915_private *dev_priv = dev->dev_private;
6678 uint32_t lcpll = I915_READ(LCPLL_CTL);
6679 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6680
6681 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6682 return 800000;
6683 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6684 return 450000;
6685 else if (freq == LCPLL_CLK_FREQ_450)
6686 return 450000;
6687 else if (IS_HSW_ULT(dev))
6688 return 337500;
6689 else
6690 return 540000;
79e53945
JB		 6691}
6692
25eb05fc
JB		 6693static int valleyview_get_display_clock_speed(struct drm_device *dev)
6694{
d197b7d3 6695 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6696 u32 val;
6697 int divider;
6698
6bcda4f0
VS		 6699 if (dev_priv->hpll_freq == 0)
6700 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6701
a580516d 6702 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6703 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6704 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6705
6706 divider = val & DISPLAY_FREQUENCY_VALUES;
6707
7d007f40
VS		 6708 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6709 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6710 "cdclk change in progress\n");
6711
6bcda4f0 6712 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6713}
6714
b37a6434
VS		 6715static int ilk_get_display_clock_speed(struct drm_device *dev)
6716{
6717 return 450000;
6718}
6719
e70236a8
JB		 6720static int i945_get_display_clock_speed(struct drm_device *dev)
6721{
6722 return 400000;
6723}
79e53945 6724
e70236a8 6725static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6726{
e907f170 6727 return 333333;
e70236a8 6728}
79e53945 6729
e70236a8
JB		 6730static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6731{
6732 return 200000;
6733}
79e53945 6734
257a7ffc
DV		 6735static int pnv_get_display_clock_speed(struct drm_device *dev)
6736{
6737 u16 gcfgc = 0;
6738
6739 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6740
6741 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6742 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6743 return 266667;
257a7ffc 6744 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6745 return 333333;
257a7ffc 6746 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6747 return 444444;
257a7ffc
DV		 6748 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6749 return 200000;
6750 default:
6751 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6752 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6753 return 133333;
257a7ffc 6754 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6755 return 166667;
257a7ffc
DV		 6756 }
6757}
6758
e70236a8
JB		 6759static int i915gm_get_display_clock_speed(struct drm_device *dev)
6760{
6761 u16 gcfgc = 0;
79e53945 6762
e70236a8
JB		 6763 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6764
6765 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6766 return 133333;
e70236a8
JB		 6767 else {
6768 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6769 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6770 return 333333;
e70236a8
JB		 6771 default:
6772 case GC_DISPLAY_CLOCK_190_200_MHZ:
6773 return 190000;
79e53945 6774 }
e70236a8
JB		 6775 }
6776}
6777
6778static int i865_get_display_clock_speed(struct drm_device *dev)
6779{
e907f170 6780 return 266667;
e70236a8
JB		 6781}
6782
1b1d2716 6783static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6784{
6785 u16 hpllcc = 0;
1b1d2716 6786
65cd2b3f
VS		 6787 /*
6788 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6789 * encoding is different :(
6790 * FIXME is this the right way to detect 852GM/852GMV?
6791 */
6792 if (dev->pdev->revision == 0x1)
6793 return 133333;
6794
1b1d2716
VS		 6795 pci_bus_read_config_word(dev->pdev->bus,
6796 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6797
e70236a8
JB		 6798 /* Assume that the hardware is in the high speed state. This
6799 * should be the default.
6800 */
6801 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6802 case GC_CLOCK_133_200:
1b1d2716 6803 case GC_CLOCK_133_200_2:
e70236a8
JB		 6804 case GC_CLOCK_100_200:
6805 return 200000;
6806 case GC_CLOCK_166_250:
6807 return 250000;
6808 case GC_CLOCK_100_133:
e907f170 6809 return 133333;
1b1d2716
VS		 6810 case GC_CLOCK_133_266:
6811 case GC_CLOCK_133_266_2:
6812 case GC_CLOCK_166_266:
6813 return 266667;
e70236a8 6814 }
79e53945 6815
e70236a8
JB		 6816 /* Shouldn't happen */
6817 return 0;
6818}
79e53945 6819
e70236a8
JB		 6820static int i830_get_display_clock_speed(struct drm_device *dev)
6821{
e907f170 6822 return 133333;
79e53945
JB		 6823}
6824
34edce2f
VS		 6825static unsigned int intel_hpll_vco(struct drm_device *dev)
6826{
6827 struct drm_i915_private *dev_priv = dev->dev_private;
6828 static const unsigned int blb_vco[8] = {
6829 [0] = 3200000,
6830 [1] = 4000000,
6831 [2] = 5333333,
6832 [3] = 4800000,
6833 [4] = 6400000,
6834 };
6835 static const unsigned int pnv_vco[8] = {
6836 [0] = 3200000,
6837 [1] = 4000000,
6838 [2] = 5333333,
6839 [3] = 4800000,
6840 [4] = 2666667,
6841 };
6842 static const unsigned int cl_vco[8] = {
6843 [0] = 3200000,
6844 [1] = 4000000,
6845 [2] = 5333333,
6846 [3] = 6400000,
6847 [4] = 3333333,
6848 [5] = 3566667,
6849 [6] = 4266667,
6850 };
6851 static const unsigned int elk_vco[8] = {
6852 [0] = 3200000,
6853 [1] = 4000000,
6854 [2] = 5333333,
6855 [3] = 4800000,
6856 };
6857 static const unsigned int ctg_vco[8] = {
6858 [0] = 3200000,
6859 [1] = 4000000,
6860 [2] = 5333333,
6861 [3] = 6400000,
6862 [4] = 2666667,
6863 [5] = 4266667,
6864 };
6865 const unsigned int *vco_table;
6866 unsigned int vco;
6867 uint8_t tmp = 0;
6868
6869 /* FIXME other chipsets? */
6870 if (IS_GM45(dev))
6871 vco_table = ctg_vco;
6872 else if (IS_G4X(dev))
6873 vco_table = elk_vco;
6874 else if (IS_CRESTLINE(dev))
6875 vco_table = cl_vco;
6876 else if (IS_PINEVIEW(dev))
6877 vco_table = pnv_vco;
6878 else if (IS_G33(dev))
6879 vco_table = blb_vco;
6880 else
6881 return 0;
6882
6883 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6884
6885 vco = vco_table[tmp & 0x7];
6886 if (vco == 0)
6887 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6888 else
6889 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6890
6891 return vco;
6892}
6893
6894static int gm45_get_display_clock_speed(struct drm_device *dev)
6895{
6896 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6897 uint16_t tmp = 0;
6898
6899 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6900
6901 cdclk_sel = (tmp >> 12) & 0x1;
6902
6903 switch (vco) {
6904 case 2666667:
6905 case 4000000:
6906 case 5333333:
6907 return cdclk_sel ? 333333 : 222222;
6908 case 3200000:
6909 return cdclk_sel ? 320000 : 228571;
6910 default:
6911 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6912 return 222222;
6913 }
6914}
6915
6916static int i965gm_get_display_clock_speed(struct drm_device *dev)
6917{
6918 static const uint8_t div_3200[] = { 16, 10, 8 };
6919 static const uint8_t div_4000[] = { 20, 12, 10 };
6920 static const uint8_t div_5333[] = { 24, 16, 14 };
6921 const uint8_t *div_table;
6922 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6923 uint16_t tmp = 0;
6924
6925 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6926
6927 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6928
6929 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6930 goto fail;
6931
6932 switch (vco) {
6933 case 3200000:
6934 div_table = div_3200;
6935 break;
6936 case 4000000:
6937 div_table = div_4000;
6938 break;
6939 case 5333333:
6940 div_table = div_5333;
6941 break;
6942 default:
6943 goto fail;
6944 }
6945
6946 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6947
caf4e252 6948fail:
34edce2f
VS		 6949 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6950 return 200000;
6951}
6952
6953static int g33_get_display_clock_speed(struct drm_device *dev)
6954{
6955 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6956 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6957 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6958 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6959 const uint8_t *div_table;
6960 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6961 uint16_t tmp = 0;
6962
6963 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6964
6965 cdclk_sel = (tmp >> 4) & 0x7;
6966
6967 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6968 goto fail;
6969
6970 switch (vco) {
6971 case 3200000:
6972 div_table = div_3200;
6973 break;
6974 case 4000000:
6975 div_table = div_4000;
6976 break;
6977 case 4800000:
6978 div_table = div_4800;
6979 break;
6980 case 5333333:
6981 div_table = div_5333;
6982 break;
6983 default:
6984 goto fail;
6985 }
6986
6987 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6988
caf4e252 6989fail:
34edce2f
VS		 6990 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6991 return 190476;
6992}
6993
2c07245f 6994static void
a65851af 6995intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6996{
a65851af
VS		 6997 while (*num > DATA_LINK_M_N_MASK ||
6998 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6999 *num >>= 1;
7000 *den >>= 1;
7001 }
7002}
7003
a65851af
VS		 7004static void compute_m_n(unsigned int m, unsigned int n,
7005 uint32_t *ret_m, uint32_t *ret_n)
7006{
7007 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7008 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7009 intel_reduce_m_n_ratio(ret_m, ret_n);
7010}
7011
e69d0bc1
DV		 7012void
7013intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7014 int pixel_clock, int link_clock,
7015 struct intel_link_m_n *m_n)
2c07245f 7016{
e69d0bc1 7017 m_n->tu = 64;
a65851af
VS		 7018
7019 compute_m_n(bits_per_pixel * pixel_clock,
7020 link_clock * nlanes * 8,
7021 &m_n->gmch_m, &m_n->gmch_n);
7022
7023 compute_m_n(pixel_clock, link_clock,
7024 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7025}
7026
a7615030
CW		 7027static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7028{
d330a953
JN		 7029 if (i915.panel_use_ssc >= 0)
7030 return i915.panel_use_ssc != 0;
41aa3448 7031 return dev_priv->vbt.lvds_use_ssc
435793df 7032 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7033}
7034
a93e255f
ACO		 7035static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7036 int num_connectors)
c65d77d8 7037{
a93e255f 7038 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7039 struct drm_i915_private *dev_priv = dev->dev_private;
7040 int refclk;
7041
a93e255f
ACO		 7042 WARN_ON(!crtc_state->base.state);
7043
5ab7b0b7 7044 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7045 refclk = 100000;
a93e255f 7046 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7047 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7048 refclk = dev_priv->vbt.lvds_ssc_freq;
7049 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7050 } else if (!IS_GEN2(dev)) {
7051 refclk = 96000;
7052 } else {
7053 refclk = 48000;
7054 }
7055
7056 return refclk;
7057}
7058
7429e9d4 7059static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7060{
7df00d7a 7061 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7062}
f47709a9 7063
7429e9d4
DV		 7064static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7065{
7066 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7067}
7068
f47709a9 7069static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7070 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7071 intel_clock_t *reduced_clock)
7072{
f47709a9 7073 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7074 u32 fp, fp2 = 0;
7075
7076 if (IS_PINEVIEW(dev)) {
190f68c5 7077 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7078 if (reduced_clock)
7429e9d4 7079 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7080 } else {
190f68c5 7081 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7082 if (reduced_clock)
7429e9d4 7083 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7084 }
7085
190f68c5 7086 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7087
f47709a9 7088 crtc->lowfreq_avail = false;
a93e255f 7089 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7090 reduced_clock) {
190f68c5 7091 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7092 crtc->lowfreq_avail = true;
a7516a05 7093 } else {
190f68c5 7094 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7095 }
7096}
7097
5e69f97f
CML		 7098static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7099 pipe)
89b667f8
JB		 7100{
7101 u32 reg_val;
7102
7103 /*
7104 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7105 * and set it to a reasonable value instead.
7106 */
ab3c759a 7107 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7108 reg_val &= 0xffffff00;
7109 reg_val |= 0x00000030;
ab3c759a 7110 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7111
ab3c759a 7112 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7113 reg_val &= 0x8cffffff;
7114 reg_val = 0x8c000000;
ab3c759a 7115 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7116
ab3c759a 7117 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7118 reg_val &= 0xffffff00;
ab3c759a 7119 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7120
ab3c759a 7121 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7122 reg_val &= 0x00ffffff;
7123 reg_val |= 0xb0000000;
ab3c759a 7124 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7125}
7126
b551842d
DV		 7127static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7128 struct intel_link_m_n *m_n)
7129{
7130 struct drm_device *dev = crtc->base.dev;
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 int pipe = crtc->pipe;
7133
e3b95f1e
DV		 7134 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7135 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7136 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7137 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7138}
7139
7140static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7141 struct intel_link_m_n *m_n,
7142 struct intel_link_m_n *m2_n2)
b551842d
DV		 7143{
7144 struct drm_device *dev = crtc->base.dev;
7145 struct drm_i915_private *dev_priv = dev->dev_private;
7146 int pipe = crtc->pipe;
6e3c9717 7147 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7148
7149 if (INTEL_INFO(dev)->gen >= 5) {
7150 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7151 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7152 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7153 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7154 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7155 * for gen < 8) and if DRRS is supported (to make sure the
7156 * registers are not unnecessarily accessed).
7157 */
44395bfe 7158 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7159 crtc->config->has_drrs) {
f769cd24
VK		 7160 I915_WRITE(PIPE_DATA_M2(transcoder),
7161 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7162 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7163 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7164 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7165 }
b551842d 7166 } else {
e3b95f1e
DV		 7167 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7168 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7169 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7170 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7171 }
7172}
7173
fe3cd48d 7174void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7175{
fe3cd48d
R		 7176 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7177
7178 if (m_n == M1_N1) {
7179 dp_m_n = &crtc->config->dp_m_n;
7180 dp_m2_n2 = &crtc->config->dp_m2_n2;
7181 } else if (m_n == M2_N2) {
7182
7183 /*
7184 * M2_N2 registers are not supported. Hence m2_n2 divider value
7185 * needs to be programmed into M1_N1.
7186 */
7187 dp_m_n = &crtc->config->dp_m2_n2;
7188 } else {
7189 DRM_ERROR("Unsupported divider value\n");
7190 return;
7191 }
7192
6e3c9717
ACO		 7193 if (crtc->config->has_pch_encoder)
7194 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7195 else
fe3cd48d 7196 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7197}
7198
251ac862
DV		 7199static void vlv_compute_dpll(struct intel_crtc *crtc,
7200 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7201{
7202 u32 dpll, dpll_md;
7203
7204 /*
7205 * Enable DPIO clock input. We should never disable the reference
7206 * clock for pipe B, since VGA hotplug / manual detection depends
7207 * on it.
7208 */
7209 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7210 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7211 /* We should never disable this, set it here for state tracking */
7212 if (crtc->pipe == PIPE_B)
7213 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7214 dpll |= DPLL_VCO_ENABLE;
d288f65f 7215 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7216
d288f65f 7217 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7218 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7219 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7220}
7221
d288f65f 7222static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7223 const struct intel_crtc_state *pipe_config)
a0c4da24 7224{
f47709a9 7225 struct drm_device *dev = crtc->base.dev;
a0c4da24 7226 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7227 int pipe = crtc->pipe;
bdd4b6a6 7228 u32 mdiv;
a0c4da24 7229 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7230 u32 coreclk, reg_val;
a0c4da24 7231
a580516d 7232 mutex_lock(&dev_priv->sb_lock);
09153000 7233
d288f65f
VS		 7234 bestn = pipe_config->dpll.n;
7235 bestm1 = pipe_config->dpll.m1;
7236 bestm2 = pipe_config->dpll.m2;
7237 bestp1 = pipe_config->dpll.p1;
7238 bestp2 = pipe_config->dpll.p2;
a0c4da24 7239
89b667f8
JB		 7240 /* See eDP HDMI DPIO driver vbios notes doc */
7241
7242 /* PLL B needs special handling */
bdd4b6a6 7243 if (pipe == PIPE_B)
5e69f97f 7244 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7245
7246 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7247 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7248
7249 /* Disable target IRef on PLL */
ab3c759a 7250 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7251 reg_val &= 0x00ffffff;
ab3c759a 7252 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7253
7254 /* Disable fast lock */
ab3c759a 7255 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7256
7257 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7258 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7259 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7260 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7261 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7262
7263 /*
7264 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7265 * but we don't support that).
7266 * Note: don't use the DAC post divider as it seems unstable.
7267 */
7268 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7270
a0c4da24 7271 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7273
89b667f8 7274 /* Set HBR and RBR LPF coefficients */
d288f65f 7275 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7276 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7277 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7279 0x009f0003);
89b667f8 7280 else
ab3c759a 7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7282 0x00d0000f);
7283
681a8504 7284 if (pipe_config->has_dp_encoder) {
89b667f8 7285 /* Use SSC source */
bdd4b6a6 7286 if (pipe == PIPE_A)
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7288 0x0df40000);
7289 else
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7291 0x0df70000);
7292 } else { /* HDMI or VGA */
7293 /* Use bend source */
bdd4b6a6 7294 if (pipe == PIPE_A)
ab3c759a 7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7296 0x0df70000);
7297 else
ab3c759a 7298 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7299 0x0df40000);
7300 }
a0c4da24 7301
ab3c759a 7302 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7303 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7304 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7305 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7306 coreclk |= 0x01000000;
ab3c759a 7307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7308
ab3c759a 7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7310 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7311}
7312
251ac862
DV		 7313static void chv_compute_dpll(struct intel_crtc *crtc,
7314 struct intel_crtc_state *pipe_config)
1ae0d137 7315{
d288f65f 7316 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7317 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7318 DPLL_VCO_ENABLE;
7319 if (crtc->pipe != PIPE_A)
d288f65f 7320 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7321
d288f65f
VS		 7322 pipe_config->dpll_hw_state.dpll_md =
7323 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7324}
7325
d288f65f 7326static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7327 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7328{
7329 struct drm_device *dev = crtc->base.dev;
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 int pipe = crtc->pipe;
7332 int dpll_reg = DPLL(crtc->pipe);
7333 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7334 u32 loopfilter, tribuf_calcntr;
9d556c99 7335 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7336 u32 dpio_val;
9cbe40c1 7337 int vco;
9d556c99 7338
d288f65f
VS		 7339 bestn = pipe_config->dpll.n;
7340 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7341 bestm1 = pipe_config->dpll.m1;
7342 bestm2 = pipe_config->dpll.m2 >> 22;
7343 bestp1 = pipe_config->dpll.p1;
7344 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7345 vco = pipe_config->dpll.vco;
a945ce7e 7346 dpio_val = 0;
9cbe40c1 7347 loopfilter = 0;
9d556c99
CML		 7348
7349 /*
7350 * Enable Refclk and SSC
7351 */
a11b0703 7352 I915_WRITE(dpll_reg,
d288f65f 7353 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7354
a580516d 7355 mutex_lock(&dev_priv->sb_lock);
9d556c99 7356
9d556c99
CML		 7357 /* p1 and p2 divider */
7358 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7359 5 << DPIO_CHV_S1_DIV_SHIFT |
7360 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7361 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7362 1 << DPIO_CHV_K_DIV_SHIFT);
7363
7364 /* Feedback post-divider - m2 */
7365 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7366
7367 /* Feedback refclk divider - n and m1 */
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7369 DPIO_CHV_M1_DIV_BY_2 |
7370 1 << DPIO_CHV_N_DIV_SHIFT);
7371
7372 /* M2 fraction division */
a945ce7e
VP		 7373 if (bestm2_frac)
7374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7375
7376 /* M2 fraction division enable */
a945ce7e
VP		 7377 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7378 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7379 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7380 if (bestm2_frac)
7381 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7382 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7383
de3a0fde
VP		 7384 /* Program digital lock detect threshold */
7385 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7386 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7387 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7388 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7389 if (!bestm2_frac)
7390 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7391 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7392
9d556c99 7393 /* Loop filter */
9cbe40c1
VP		 7394 if (vco == 5400000) {
7395 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7396 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7397 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7398 tribuf_calcntr = 0x9;
7399 } else if (vco <= 6200000) {
7400 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7401 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7402 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7403 tribuf_calcntr = 0x9;
7404 } else if (vco <= 6480000) {
7405 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7406 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7407 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7408 tribuf_calcntr = 0x8;
7409 } else {
7410 /* Not supported. Apply the same limits as in the max case */
7411 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7412 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7413 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414 tribuf_calcntr = 0;
7415 }
9d556c99
CML		 7416 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7417
968040b2 7418 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7419 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7420 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7421 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7422
9d556c99
CML		 7423 /* AFC Recal */
7424 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7425 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7426 DPIO_AFC_RECAL);
7427
a580516d 7428 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7429}
7430
d288f65f
VS		 7431/**
7432 * vlv_force_pll_on - forcibly enable just the PLL
7433 * @dev_priv: i915 private structure
7434 * @pipe: pipe PLL to enable
7435 * @dpll: PLL configuration
7436 *
7437 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7438 * in cases where we need the PLL enabled even when @pipe is not going to
7439 * be enabled.
7440 */
7441void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7442 const struct dpll *dpll)
7443{
7444 struct intel_crtc *crtc =
7445 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7446 struct intel_crtc_state pipe_config = {
a93e255f 7447 .base.crtc = &crtc->base,
d288f65f
VS		 7448 .pixel_multiplier = 1,
7449 .dpll = *dpll,
7450 };
7451
7452 if (IS_CHERRYVIEW(dev)) {
251ac862 7453 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7454 chv_prepare_pll(crtc, &pipe_config);
7455 chv_enable_pll(crtc, &pipe_config);
7456 } else {
251ac862 7457 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7458 vlv_prepare_pll(crtc, &pipe_config);
7459 vlv_enable_pll(crtc, &pipe_config);
7460 }
7461}
7462
7463/**
7464 * vlv_force_pll_off - forcibly disable just the PLL
7465 * @dev_priv: i915 private structure
7466 * @pipe: pipe PLL to disable
7467 *
7468 * Disable the PLL for @pipe. To be used in cases where we need
7469 * the PLL enabled even when @pipe is not going to be enabled.
7470 */
7471void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7472{
7473 if (IS_CHERRYVIEW(dev))
7474 chv_disable_pll(to_i915(dev), pipe);
7475 else
7476 vlv_disable_pll(to_i915(dev), pipe);
7477}
7478
251ac862
DV		 7479static void i9xx_compute_dpll(struct intel_crtc *crtc,
7480 struct intel_crtc_state *crtc_state,
7481 intel_clock_t *reduced_clock,
7482 int num_connectors)
eb1cbe48 7483{
f47709a9 7484 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7485 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7486 u32 dpll;
7487 bool is_sdvo;
190f68c5 7488 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7489
190f68c5 7490 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7491
a93e255f
ACO		 7492 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7493 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7494
7495 dpll = DPLL_VGA_MODE_DIS;
7496
a93e255f 7497 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7498 dpll |= DPLLB_MODE_LVDS;
7499 else
7500 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7501
ef1b460d 7502 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7503 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7504 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7505 }
198a037f
DV		 7506
7507 if (is_sdvo)
4a33e48d 7508 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7509
190f68c5 7510 if (crtc_state->has_dp_encoder)
4a33e48d 7511 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7512
7513 /* compute bitmask from p1 value */
7514 if (IS_PINEVIEW(dev))
7515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7516 else {
7517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7518 if (IS_G4X(dev) && reduced_clock)
7519 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7520 }
7521 switch (clock->p2) {
7522 case 5:
7523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7524 break;
7525 case 7:
7526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7527 break;
7528 case 10:
7529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7530 break;
7531 case 14:
7532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7533 break;
7534 }
7535 if (INTEL_INFO(dev)->gen >= 4)
7536 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7537
190f68c5 7538 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7539 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7541 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7542 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7543 else
7544 dpll |= PLL_REF_INPUT_DREFCLK;
7545
7546 dpll |= DPLL_VCO_ENABLE;
190f68c5 7547 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7548
eb1cbe48 7549 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7550 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7551 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7552 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7553 }
7554}
7555
251ac862
DV		 7556static void i8xx_compute_dpll(struct intel_crtc *crtc,
7557 struct intel_crtc_state *crtc_state,
7558 intel_clock_t *reduced_clock,
7559 int num_connectors)
eb1cbe48 7560{
f47709a9 7561 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7562 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7563 u32 dpll;
190f68c5 7564 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7565
190f68c5 7566 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7567
eb1cbe48
DV		 7568 dpll = DPLL_VGA_MODE_DIS;
7569
a93e255f 7570 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7571 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7572 } else {
7573 if (clock->p1 == 2)
7574 dpll |= PLL_P1_DIVIDE_BY_TWO;
7575 else
7576 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7577 if (clock->p2 == 4)
7578 dpll |= PLL_P2_DIVIDE_BY_4;
7579 }
7580
a93e255f 7581 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7582 dpll |= DPLL_DVO_2X_MODE;
7583
a93e255f 7584 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7585 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7586 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7587 else
7588 dpll |= PLL_REF_INPUT_DREFCLK;
7589
7590 dpll |= DPLL_VCO_ENABLE;
190f68c5 7591 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7592}
7593
8a654f3b 7594static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7595{
7596 struct drm_device *dev = intel_crtc->base.dev;
7597 struct drm_i915_private *dev_priv = dev->dev_private;
7598 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7599 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7600 struct drm_display_mode *adjusted_mode =
6e3c9717 7601 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7602 uint32_t crtc_vtotal, crtc_vblank_end;
7603 int vsyncshift = 0;
4d8a62ea
DV		 7604
7605 /* We need to be careful not to changed the adjusted mode, for otherwise
7606 * the hw state checker will get angry at the mismatch. */
7607 crtc_vtotal = adjusted_mode->crtc_vtotal;
7608 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7609
609aeaca 7610 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7611 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7612 crtc_vtotal -= 1;
7613 crtc_vblank_end -= 1;
609aeaca 7614
409ee761 7615 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7616 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7617 else
7618 vsyncshift = adjusted_mode->crtc_hsync_start -
7619 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7620 if (vsyncshift < 0)
7621 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7622 }
7623
7624 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7625 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7626
fe2b8f9d 7627 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7628 (adjusted_mode->crtc_hdisplay - 1) |
7629 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7630 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7631 (adjusted_mode->crtc_hblank_start - 1) |
7632 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7633 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7634 (adjusted_mode->crtc_hsync_start - 1) |
7635 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7636
fe2b8f9d 7637 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7638 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7639 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7640 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7641 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7642 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7643 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7644 (adjusted_mode->crtc_vsync_start - 1) |
7645 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7646
b5e508d4
PZ		 7647 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7648 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7649 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7650 * bits. */
7651 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7652 (pipe == PIPE_B || pipe == PIPE_C))
7653 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7654
b0e77b9c
PZ		 7655 /* pipesrc controls the size that is scaled from, which should
7656 * always be the user's requested size.
7657 */
7658 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7659 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7660 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7661}
7662
1bd1bd80 7663static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7664 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7665{
7666 struct drm_device *dev = crtc->base.dev;
7667 struct drm_i915_private *dev_priv = dev->dev_private;
7668 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7669 uint32_t tmp;
7670
7671 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7672 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7673 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7674 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7675 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7676 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7677 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7678 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7679 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7680
7681 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7682 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7684 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7685 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7686 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7687 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7688 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7690
7691 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7692 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7693 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7694 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7695 }
7696
7697 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7698 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7699 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7700
2d112de7
ACO		 7701 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7702 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7703}
7704
f6a83288 7705void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7706 struct intel_crtc_state *pipe_config)
babea61d 7707{
2d112de7
ACO		 7708 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7709 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7710 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7711 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7712
2d112de7
ACO		 7713 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7714 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7715 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7716 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7717
2d112de7 7718 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7719
2d112de7
ACO		 7720 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7721 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7722}
7723
84b046f3
DV		 7724static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7725{
7726 struct drm_device *dev = intel_crtc->base.dev;
7727 struct drm_i915_private *dev_priv = dev->dev_private;
7728 uint32_t pipeconf;
7729
9f11a9e4 7730 pipeconf = 0;
84b046f3 7731
b6b5d049
VS		 7732 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7733 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7734 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7735
6e3c9717 7736 if (intel_crtc->config->double_wide)
cf532bb2 7737 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7738
ff9ce46e
DV		 7739 /* only g4x and later have fancy bpc/dither controls */
7740 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7741 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7742 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7743 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7744 PIPECONF_DITHER_TYPE_SP;
84b046f3 7745
6e3c9717 7746 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7747 case 18:
7748 pipeconf |= PIPECONF_6BPC;
7749 break;
7750 case 24:
7751 pipeconf |= PIPECONF_8BPC;
7752 break;
7753 case 30:
7754 pipeconf |= PIPECONF_10BPC;
7755 break;
7756 default:
7757 /* Case prevented by intel_choose_pipe_bpp_dither. */
7758 BUG();
84b046f3
DV		 7759 }
7760 }
7761
7762 if (HAS_PIPE_CXSR(dev)) {
7763 if (intel_crtc->lowfreq_avail) {
7764 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7765 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7766 } else {
7767 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7768 }
7769 }
7770
6e3c9717 7771 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7772 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7773 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7774 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7775 else
7776 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7777 } else
84b046f3
DV		 7778 pipeconf |= PIPECONF_PROGRESSIVE;
7779
6e3c9717 7780 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7781 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7782
84b046f3
DV		 7783 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7784 POSTING_READ(PIPECONF(intel_crtc->pipe));
7785}
7786
190f68c5
ACO		 7787static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7788 struct intel_crtc_state *crtc_state)
79e53945 7789{
c7653199 7790 struct drm_device *dev = crtc->base.dev;
79e53945 7791 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7792 int refclk, num_connectors = 0;
c329a4ec
DV		 7793 intel_clock_t clock;
7794 bool ok;
7795 bool is_dsi = false;
5eddb70b 7796 struct intel_encoder *encoder;
d4906093 7797 const intel_limit_t *limit;
55bb9992 7798 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7799 struct drm_connector *connector;
55bb9992
ACO		 7800 struct drm_connector_state *connector_state;
7801 int i;
79e53945 7802
dd3cd74a
ACO		 7803 memset(&crtc_state->dpll_hw_state, 0,
7804 sizeof(crtc_state->dpll_hw_state));
7805
da3ced29 7806 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7807 if (connector_state->crtc != &crtc->base)
7808 continue;
7809
7810 encoder = to_intel_encoder(connector_state->best_encoder);
7811
5eddb70b 7812 switch (encoder->type) {
e9fd1c02
JN		 7813 case INTEL_OUTPUT_DSI:
7814 is_dsi = true;
7815 break;
6847d71b
PZ		 7816 default:
7817 break;
79e53945 7818 }
43565a06 7819
c751ce4f 7820 num_connectors++;
79e53945
JB		 7821 }
7822
f2335330 7823 if (is_dsi)
5b18e57c 7824 return 0;
f2335330 7825
190f68c5 7826 if (!crtc_state->clock_set) {
a93e255f 7827 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7828
e9fd1c02
JN		 7829 /*
7830 * Returns a set of divisors for the desired target clock with
7831 * the given refclk, or FALSE. The returned values represent
7832 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7833 * 2) / p1 / p2.
7834 */
a93e255f
ACO		 7835 limit = intel_limit(crtc_state, refclk);
7836 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7837 crtc_state->port_clock,
e9fd1c02 7838 refclk, NULL, &clock);
f2335330 7839 if (!ok) {
e9fd1c02
JN		 7840 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7841 return -EINVAL;
7842 }
79e53945 7843
f2335330 7844 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7845 crtc_state->dpll.n = clock.n;
7846 crtc_state->dpll.m1 = clock.m1;
7847 crtc_state->dpll.m2 = clock.m2;
7848 crtc_state->dpll.p1 = clock.p1;
7849 crtc_state->dpll.p2 = clock.p2;
f47709a9 7850 }
7026d4ac 7851
e9fd1c02 7852 if (IS_GEN2(dev)) {
c329a4ec 7853 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7854 num_connectors);
9d556c99 7855 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7856 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7857 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7858 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7859 } else {
c329a4ec 7860 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7861 num_connectors);
e9fd1c02 7862 }
79e53945 7863
c8f7a0db 7864 return 0;
f564048e
EA		 7865}
7866
2fa2fe9a 7867static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7868 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7869{
7870 struct drm_device *dev = crtc->base.dev;
7871 struct drm_i915_private *dev_priv = dev->dev_private;
7872 uint32_t tmp;
7873
dc9e7dec
VS		 7874 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7875 return;
7876
2fa2fe9a 7877 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7878 if (!(tmp & PFIT_ENABLE))
7879 return;
2fa2fe9a 7880
06922821 7881 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7882 if (INTEL_INFO(dev)->gen < 4) {
7883 if (crtc->pipe != PIPE_B)
7884 return;
2fa2fe9a
DV		 7885 } else {
7886 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7887 return;
7888 }
7889
06922821 7890 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7891 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7892 if (INTEL_INFO(dev)->gen < 5)
7893 pipe_config->gmch_pfit.lvds_border_bits =
7894 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7895}
7896
acbec814 7897static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7898 struct intel_crtc_state *pipe_config)
acbec814
JB		 7899{
7900 struct drm_device *dev = crtc->base.dev;
7901 struct drm_i915_private *dev_priv = dev->dev_private;
7902 int pipe = pipe_config->cpu_transcoder;
7903 intel_clock_t clock;
7904 u32 mdiv;
662c6ecb 7905 int refclk = 100000;
acbec814 7906
f573de5a
SK		 7907 /* In case of MIPI DPLL will not even be used */
7908 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7909 return;
7910
a580516d 7911 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7912 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7913 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7914
7915 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7916 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7917 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7918 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7919 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7920
f646628b 7921 vlv_clock(refclk, &clock);
acbec814 7922
f646628b
VS		 7923 /* clock.dot is the fast clock */
7924 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7925}
7926
5724dbd1
DL		 7927static void
7928i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7929 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7930{
7931 struct drm_device *dev = crtc->base.dev;
7932 struct drm_i915_private *dev_priv = dev->dev_private;
7933 u32 val, base, offset;
7934 int pipe = crtc->pipe, plane = crtc->plane;
7935 int fourcc, pixel_format;
6761dd31 7936 unsigned int aligned_height;
b113d5ee 7937 struct drm_framebuffer *fb;
1b842c89 7938 struct intel_framebuffer *intel_fb;
1ad292b5 7939
42a7b088
DL		 7940 val = I915_READ(DSPCNTR(plane));
7941 if (!(val & DISPLAY_PLANE_ENABLE))
7942 return;
7943
d9806c9f 7944 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7945 if (!intel_fb) {
1ad292b5
JB		 7946 DRM_DEBUG_KMS("failed to alloc fb\n");
7947 return;
7948 }
7949
1b842c89
DL		 7950 fb = &intel_fb->base;
7951
18c5247e
DV		 7952 if (INTEL_INFO(dev)->gen >= 4) {
7953 if (val & DISPPLANE_TILED) {
49af449b 7954 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7955 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7956 }
7957 }
1ad292b5
JB		 7958
7959 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7960 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7961 fb->pixel_format = fourcc;
7962 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7963
7964 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7965 if (plane_config->tiling)
1ad292b5
JB		 7966 offset = I915_READ(DSPTILEOFF(plane));
7967 else
7968 offset = I915_READ(DSPLINOFF(plane));
7969 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7970 } else {
7971 base = I915_READ(DSPADDR(plane));
7972 }
7973 plane_config->base = base;
7974
7975 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7976 fb->width = ((val >> 16) & 0xfff) + 1;
7977 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7978
7979 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7980 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7981
b113d5ee 7982 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7983 fb->pixel_format,
7984 fb->modifier[0]);
1ad292b5 7985
f37b5c2b 7986 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7987
2844a921
DL		 7988 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7989 pipe_name(pipe), plane, fb->width, fb->height,
7990 fb->bits_per_pixel, base, fb->pitches[0],
7991 plane_config->size);
1ad292b5 7992
2d14030b 7993 plane_config->fb = intel_fb;
1ad292b5
JB		 7994}
7995
70b23a98 7996static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7997 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7998{
7999 struct drm_device *dev = crtc->base.dev;
8000 struct drm_i915_private *dev_priv = dev->dev_private;
8001 int pipe = pipe_config->cpu_transcoder;
8002 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8003 intel_clock_t clock;
8004 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8005 int refclk = 100000;
8006
a580516d 8007 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8008 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8009 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8010 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8011 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8012 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8013
8014 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8015 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8016 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8017 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8018 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8019
8020 chv_clock(refclk, &clock);
8021
8022 /* clock.dot is the fast clock */
8023 pipe_config->port_clock = clock.dot / 5;
8024}
8025
0e8ffe1b 8026static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8027 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8028{
8029 struct drm_device *dev = crtc->base.dev;
8030 struct drm_i915_private *dev_priv = dev->dev_private;
8031 uint32_t tmp;
8032
f458ebbc
DV		 8033 if (!intel_display_power_is_enabled(dev_priv,
8034 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8035 return false;
8036
e143a21c 8037 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8038 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8039
0e8ffe1b
DV		 8040 tmp = I915_READ(PIPECONF(crtc->pipe));
8041 if (!(tmp & PIPECONF_ENABLE))
8042 return false;
8043
42571aef
VS		 8044 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8045 switch (tmp & PIPECONF_BPC_MASK) {
8046 case PIPECONF_6BPC:
8047 pipe_config->pipe_bpp = 18;
8048 break;
8049 case PIPECONF_8BPC:
8050 pipe_config->pipe_bpp = 24;
8051 break;
8052 case PIPECONF_10BPC:
8053 pipe_config->pipe_bpp = 30;
8054 break;
8055 default:
8056 break;
8057 }
8058 }
8059
b5a9fa09
DV		 8060 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8061 pipe_config->limited_color_range = true;
8062
282740f7
VS		 8063 if (INTEL_INFO(dev)->gen < 4)
8064 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8065
1bd1bd80
DV		 8066 intel_get_pipe_timings(crtc, pipe_config);
8067
2fa2fe9a
DV		 8068 i9xx_get_pfit_config(crtc, pipe_config);
8069
6c49f241
DV		 8070 if (INTEL_INFO(dev)->gen >= 4) {
8071 tmp = I915_READ(DPLL_MD(crtc->pipe));
8072 pipe_config->pixel_multiplier =
8073 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8074 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8075 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8076 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8077 tmp = I915_READ(DPLL(crtc->pipe));
8078 pipe_config->pixel_multiplier =
8079 ((tmp & SDVO_MULTIPLIER_MASK)
8080 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8081 } else {
8082 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8083 * port and will be fixed up in the encoder->get_config
8084 * function. */
8085 pipe_config->pixel_multiplier = 1;
8086 }
8bcc2795
DV		 8087 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8088 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8089 /*
8090 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8091 * on 830. Filter it out here so that we don't
8092 * report errors due to that.
8093 */
8094 if (IS_I830(dev))
8095 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8096
8bcc2795
DV		 8097 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8098 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8099 } else {
8100 /* Mask out read-only status bits. */
8101 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8102 DPLL_PORTC_READY_MASK |
8103 DPLL_PORTB_READY_MASK);
8bcc2795 8104 }
6c49f241 8105
70b23a98
VS		 8106 if (IS_CHERRYVIEW(dev))
8107 chv_crtc_clock_get(crtc, pipe_config);
8108 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8109 vlv_crtc_clock_get(crtc, pipe_config);
8110 else
8111 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8112
0e8ffe1b
DV		 8113 return true;
8114}
8115
dde86e2d 8116static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8117{
8118 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8119 struct intel_encoder *encoder;
74cfd7ac 8120 u32 val, final;
13d83a67 8121 bool has_lvds = false;
199e5d79 8122 bool has_cpu_edp = false;
199e5d79 8123 bool has_panel = false;
99eb6a01
KP		 8124 bool has_ck505 = false;
8125 bool can_ssc = false;
13d83a67
JB		 8126
8127 /* We need to take the global config into account */
b2784e15 8128 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8129 switch (encoder->type) {
8130 case INTEL_OUTPUT_LVDS:
8131 has_panel = true;
8132 has_lvds = true;
8133 break;
8134 case INTEL_OUTPUT_EDP:
8135 has_panel = true;
2de6905f 8136 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8137 has_cpu_edp = true;
8138 break;
6847d71b
PZ		 8139 default:
8140 break;
13d83a67
JB		 8141 }
8142 }
8143
99eb6a01 8144 if (HAS_PCH_IBX(dev)) {
41aa3448 8145 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8146 can_ssc = has_ck505;
8147 } else {
8148 has_ck505 = false;
8149 can_ssc = true;
8150 }
8151
2de6905f
ID		 8152 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8153 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8154
8155 /* Ironlake: try to setup display ref clock before DPLL
8156 * enabling. This is only under driver's control after
8157 * PCH B stepping, previous chipset stepping should be
8158 * ignoring this setting.
8159 */
74cfd7ac
CW		 8160 val = I915_READ(PCH_DREF_CONTROL);
8161
8162 /* As we must carefully and slowly disable/enable each source in turn,
8163 * compute the final state we want first and check if we need to
8164 * make any changes at all.
8165 */
8166 final = val;
8167 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8168 if (has_ck505)
8169 final |= DREF_NONSPREAD_CK505_ENABLE;
8170 else
8171 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8172
8173 final &= ~DREF_SSC_SOURCE_MASK;
8174 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8175 final &= ~DREF_SSC1_ENABLE;
8176
8177 if (has_panel) {
8178 final |= DREF_SSC_SOURCE_ENABLE;
8179
8180 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8181 final |= DREF_SSC1_ENABLE;
8182
8183 if (has_cpu_edp) {
8184 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8185 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8186 else
8187 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8188 } else
8189 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8190 } else {
8191 final |= DREF_SSC_SOURCE_DISABLE;
8192 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8193 }
8194
8195 if (final == val)
8196 return;
8197
13d83a67 8198 /* Always enable nonspread source */
74cfd7ac 8199 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8200
99eb6a01 8201 if (has_ck505)
74cfd7ac 8202 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8203 else
74cfd7ac 8204 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8205
199e5d79 8206 if (has_panel) {
74cfd7ac
CW		 8207 val &= ~DREF_SSC_SOURCE_MASK;
8208 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8209
199e5d79 8210 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8211 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8212 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8213 val |= DREF_SSC1_ENABLE;
e77166b5 8214 } else
74cfd7ac 8215 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8216
8217 /* Get SSC going before enabling the outputs */
74cfd7ac 8218 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8219 POSTING_READ(PCH_DREF_CONTROL);
8220 udelay(200);
8221
74cfd7ac 8222 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8223
8224 /* Enable CPU source on CPU attached eDP */
199e5d79 8225 if (has_cpu_edp) {
99eb6a01 8226 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8227 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8228 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8229 } else
74cfd7ac 8230 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8231 } else
74cfd7ac 8232 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8233
74cfd7ac 8234 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8235 POSTING_READ(PCH_DREF_CONTROL);
8236 udelay(200);
8237 } else {
8238 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8239
74cfd7ac 8240 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8241
8242 /* Turn off CPU output */
74cfd7ac 8243 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8244
74cfd7ac 8245 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8246 POSTING_READ(PCH_DREF_CONTROL);
8247 udelay(200);
8248
8249 /* Turn off the SSC source */
74cfd7ac
CW		 8250 val &= ~DREF_SSC_SOURCE_MASK;
8251 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8252
8253 /* Turn off SSC1 */
74cfd7ac 8254 val &= ~DREF_SSC1_ENABLE;
199e5d79 8255
74cfd7ac 8256 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8257 POSTING_READ(PCH_DREF_CONTROL);
8258 udelay(200);
8259 }
74cfd7ac
CW		 8260
8261 BUG_ON(val != final);
13d83a67
JB		 8262}
8263
f31f2d55 8264static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8265{
f31f2d55 8266 uint32_t tmp;
dde86e2d 8267
0ff066a9
PZ		 8268 tmp = I915_READ(SOUTH_CHICKEN2);
8269 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8270 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8271
0ff066a9
PZ		 8272 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8273 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8274 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8275
0ff066a9
PZ		 8276 tmp = I915_READ(SOUTH_CHICKEN2);
8277 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8278 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8279
0ff066a9
PZ		 8280 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8281 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8282 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8283}
8284
8285/* WaMPhyProgramming:hsw */
8286static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8287{
8288 uint32_t tmp;
dde86e2d
PZ		 8289
8290 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8291 tmp &= ~(0xFF << 24);
8292 tmp |= (0x12 << 24);
8293 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8294
dde86e2d
PZ		 8295 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8296 tmp |= (1 << 11);
8297 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8298
8299 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8300 tmp |= (1 << 11);
8301 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8302
dde86e2d
PZ		 8303 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8304 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8305 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8306
8307 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8308 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8309 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8310
0ff066a9
PZ		 8311 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8312 tmp &= ~(7 << 13);
8313 tmp |= (5 << 13);
8314 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8315
0ff066a9
PZ		 8316 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8317 tmp &= ~(7 << 13);
8318 tmp |= (5 << 13);
8319 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8320
8321 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8322 tmp &= ~0xFF;
8323 tmp |= 0x1C;
8324 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8325
8326 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8327 tmp &= ~0xFF;
8328 tmp |= 0x1C;
8329 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8330
8331 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8332 tmp &= ~(0xFF << 16);
8333 tmp |= (0x1C << 16);
8334 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8335
8336 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8337 tmp &= ~(0xFF << 16);
8338 tmp |= (0x1C << 16);
8339 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8340
0ff066a9
PZ		 8341 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8342 tmp |= (1 << 27);
8343 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8344
0ff066a9
PZ		 8345 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8346 tmp |= (1 << 27);
8347 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8348
0ff066a9
PZ		 8349 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8350 tmp &= ~(0xF << 28);
8351 tmp |= (4 << 28);
8352 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8353
0ff066a9
PZ		 8354 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8355 tmp &= ~(0xF << 28);
8356 tmp |= (4 << 28);
8357 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8358}
8359
2fa86a1f
PZ		 8360/* Implements 3 different sequences from BSpec chapter "Display iCLK
8361 * Programming" based on the parameters passed:
8362 * - Sequence to enable CLKOUT_DP
8363 * - Sequence to enable CLKOUT_DP without spread
8364 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8365 */
8366static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8367 bool with_fdi)
f31f2d55
PZ		 8368{
8369 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8370 uint32_t reg, tmp;
8371
8372 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8373 with_spread = true;
8374 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8375 with_fdi, "LP PCH doesn't have FDI\n"))
8376 with_fdi = false;
f31f2d55 8377
a580516d 8378 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8379
8380 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8381 tmp &= ~SBI_SSCCTL_DISABLE;
8382 tmp |= SBI_SSCCTL_PATHALT;
8383 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8384
8385 udelay(24);
8386
2fa86a1f
PZ		 8387 if (with_spread) {
8388 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8389 tmp &= ~SBI_SSCCTL_PATHALT;
8390 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8391
2fa86a1f
PZ		 8392 if (with_fdi) {
8393 lpt_reset_fdi_mphy(dev_priv);
8394 lpt_program_fdi_mphy(dev_priv);
8395 }
8396 }
dde86e2d 8397
2fa86a1f
PZ		 8398 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8399 SBI_GEN0 : SBI_DBUFF0;
8400 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8401 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8402 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8403
a580516d 8404 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8405}
8406
47701c3b
PZ		 8407/* Sequence to disable CLKOUT_DP */
8408static void lpt_disable_clkout_dp(struct drm_device *dev)
8409{
8410 struct drm_i915_private *dev_priv = dev->dev_private;
8411 uint32_t reg, tmp;
8412
a580516d 8413 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8414
8415 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8416 SBI_GEN0 : SBI_DBUFF0;
8417 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8418 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8419 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8420
8421 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8422 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8423 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8424 tmp |= SBI_SSCCTL_PATHALT;
8425 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8426 udelay(32);
8427 }
8428 tmp |= SBI_SSCCTL_DISABLE;
8429 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8430 }
8431
a580516d 8432 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8433}
8434
bf8fa3d3
PZ		 8435static void lpt_init_pch_refclk(struct drm_device *dev)
8436{
bf8fa3d3
PZ		 8437 struct intel_encoder *encoder;
8438 bool has_vga = false;
8439
b2784e15 8440 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8441 switch (encoder->type) {
8442 case INTEL_OUTPUT_ANALOG:
8443 has_vga = true;
8444 break;
6847d71b
PZ		 8445 default:
8446 break;
bf8fa3d3
PZ		 8447 }
8448 }
8449
47701c3b
PZ		 8450 if (has_vga)
8451 lpt_enable_clkout_dp(dev, true, true);
8452 else
8453 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8454}
8455
dde86e2d
PZ		 8456/*
8457 * Initialize reference clocks when the driver loads
8458 */
8459void intel_init_pch_refclk(struct drm_device *dev)
8460{
8461 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8462 ironlake_init_pch_refclk(dev);
8463 else if (HAS_PCH_LPT(dev))
8464 lpt_init_pch_refclk(dev);
8465}
8466
55bb9992 8467static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8468{
55bb9992 8469 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8470 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8471 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8472 struct drm_connector *connector;
55bb9992 8473 struct drm_connector_state *connector_state;
d9d444cb 8474 struct intel_encoder *encoder;
55bb9992 8475 int num_connectors = 0, i;
d9d444cb
JB		 8476 bool is_lvds = false;
8477
da3ced29 8478 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8479 if (connector_state->crtc != crtc_state->base.crtc)
8480 continue;
8481
8482 encoder = to_intel_encoder(connector_state->best_encoder);
8483
d9d444cb
JB		 8484 switch (encoder->type) {
8485 case INTEL_OUTPUT_LVDS:
8486 is_lvds = true;
8487 break;
6847d71b
PZ		 8488 default:
8489 break;
d9d444cb
JB		 8490 }
8491 num_connectors++;
8492 }
8493
8494 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8495 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8496 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8497 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8498 }
8499
8500 return 120000;
8501}
8502
6ff93609 8503static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8504{
c8203565 8505 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8507 int pipe = intel_crtc->pipe;
c8203565
PZ		 8508 uint32_t val;
8509
78114071 8510 val = 0;
c8203565 8511
6e3c9717 8512 switch (intel_crtc->config->pipe_bpp) {
c8203565 8513 case 18:
dfd07d72 8514 val |= PIPECONF_6BPC;
c8203565
PZ		 8515 break;
8516 case 24:
dfd07d72 8517 val |= PIPECONF_8BPC;
c8203565
PZ		 8518 break;
8519 case 30:
dfd07d72 8520 val |= PIPECONF_10BPC;
c8203565
PZ		 8521 break;
8522 case 36:
dfd07d72 8523 val |= PIPECONF_12BPC;
c8203565
PZ		 8524 break;
8525 default:
cc769b62
PZ		 8526 /* Case prevented by intel_choose_pipe_bpp_dither. */
8527 BUG();
c8203565
PZ		 8528 }
8529
6e3c9717 8530 if (intel_crtc->config->dither)
c8203565
PZ		 8531 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8532
6e3c9717 8533 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8534 val |= PIPECONF_INTERLACED_ILK;
8535 else
8536 val |= PIPECONF_PROGRESSIVE;
8537
6e3c9717 8538 if (intel_crtc->config->limited_color_range)
3685a8f3 8539 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8540
c8203565
PZ		 8541 I915_WRITE(PIPECONF(pipe), val);
8542 POSTING_READ(PIPECONF(pipe));
8543}
8544
86d3efce
VS		 8545/*
8546 * Set up the pipe CSC unit.
8547 *
8548 * Currently only full range RGB to limited range RGB conversion
8549 * is supported, but eventually this should handle various
8550 * RGB<->YCbCr scenarios as well.
8551 */
50f3b016 8552static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8553{
8554 struct drm_device *dev = crtc->dev;
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8557 int pipe = intel_crtc->pipe;
8558 uint16_t coeff = 0x7800; /* 1.0 */
8559
8560 /*
8561 * TODO: Check what kind of values actually come out of the pipe
8562 * with these coeff/postoff values and adjust to get the best
8563 * accuracy. Perhaps we even need to take the bpc value into
8564 * consideration.
8565 */
8566
6e3c9717 8567 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8568 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8569
8570 /*
8571 * GY/GU and RY/RU should be the other way around according
8572 * to BSpec, but reality doesn't agree. Just set them up in
8573 * a way that results in the correct picture.
8574 */
8575 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8576 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8577
8578 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8579 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8580
8581 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8582 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8583
8584 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8585 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8586 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8587
8588 if (INTEL_INFO(dev)->gen > 6) {
8589 uint16_t postoff = 0;
8590
6e3c9717 8591 if (intel_crtc->config->limited_color_range)
32cf0cb0 8592 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8593
8594 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8595 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8596 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8597
8598 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8599 } else {
8600 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8601
6e3c9717 8602 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8603 mode |= CSC_BLACK_SCREEN_OFFSET;
8604
8605 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8606 }
8607}
8608
6ff93609 8609static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8610{
756f85cf
PZ		 8611 struct drm_device *dev = crtc->dev;
8612 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8614 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8615 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8616 uint32_t val;
8617
3eff4faa 8618 val = 0;
ee2b0b38 8619
6e3c9717 8620 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8621 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8622
6e3c9717 8623 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8624 val |= PIPECONF_INTERLACED_ILK;
8625 else
8626 val |= PIPECONF_PROGRESSIVE;
8627
702e7a56
PZ		 8628 I915_WRITE(PIPECONF(cpu_transcoder), val);
8629 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8630
8631 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8632 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8633
3cdf122c 8634 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8635 val = 0;
8636
6e3c9717 8637 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8638 case 18:
8639 val |= PIPEMISC_DITHER_6_BPC;
8640 break;
8641 case 24:
8642 val |= PIPEMISC_DITHER_8_BPC;
8643 break;
8644 case 30:
8645 val |= PIPEMISC_DITHER_10_BPC;
8646 break;
8647 case 36:
8648 val |= PIPEMISC_DITHER_12_BPC;
8649 break;
8650 default:
8651 /* Case prevented by pipe_config_set_bpp. */
8652 BUG();
8653 }
8654
6e3c9717 8655 if (intel_crtc->config->dither)
756f85cf
PZ		 8656 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8657
8658 I915_WRITE(PIPEMISC(pipe), val);
8659 }
ee2b0b38
PZ		 8660}
8661
6591c6e4 8662static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8663 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8664 intel_clock_t *clock,
8665 bool *has_reduced_clock,
8666 intel_clock_t *reduced_clock)
8667{
8668 struct drm_device *dev = crtc->dev;
8669 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8670 int refclk;
d4906093 8671 const intel_limit_t *limit;
c329a4ec 8672 bool ret;
79e53945 8673
55bb9992 8674 refclk = ironlake_get_refclk(crtc_state);
79e53945 8675
d4906093
ML		 8676 /*
8677 * Returns a set of divisors for the desired target clock with the given
8678 * refclk, or FALSE. The returned values represent the clock equation:
8679 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8680 */
a93e255f
ACO		 8681 limit = intel_limit(crtc_state, refclk);
8682 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8683 crtc_state->port_clock,
ee9300bb 8684 refclk, NULL, clock);
6591c6e4
PZ		 8685 if (!ret)
8686 return false;
cda4b7d3 8687
6591c6e4
PZ		 8688 return true;
8689}
8690
d4b1931c
PZ		 8691int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8692{
8693 /*
8694 * Account for spread spectrum to avoid
8695 * oversubscribing the link. Max center spread
8696 * is 2.5%; use 5% for safety's sake.
8697 */
8698 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8699 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8700}
8701
7429e9d4 8702static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8703{
7429e9d4 8704 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8705}
8706
de13a2e3 8707static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8708 struct intel_crtc_state *crtc_state,
7429e9d4 8709 u32 *fp,
9a7c7890 8710 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8711{
de13a2e3 8712 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8713 struct drm_device *dev = crtc->dev;
8714 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8715 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8716 struct drm_connector *connector;
55bb9992
ACO		 8717 struct drm_connector_state *connector_state;
8718 struct intel_encoder *encoder;
de13a2e3 8719 uint32_t dpll;
55bb9992 8720 int factor, num_connectors = 0, i;
09ede541 8721 bool is_lvds = false, is_sdvo = false;
79e53945 8722
da3ced29 8723 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8724 if (connector_state->crtc != crtc_state->base.crtc)
8725 continue;
8726
8727 encoder = to_intel_encoder(connector_state->best_encoder);
8728
8729 switch (encoder->type) {
79e53945
JB		 8730 case INTEL_OUTPUT_LVDS:
8731 is_lvds = true;
8732 break;
8733 case INTEL_OUTPUT_SDVO:
7d57382e 8734 case INTEL_OUTPUT_HDMI:
79e53945 8735 is_sdvo = true;
79e53945 8736 break;
6847d71b
PZ		 8737 default:
8738 break;
79e53945 8739 }
43565a06 8740
c751ce4f 8741 num_connectors++;
79e53945 8742 }
79e53945 8743
c1858123 8744 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8745 factor = 21;
8746 if (is_lvds) {
8747 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8748 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8749 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8750 factor = 25;
190f68c5 8751 } else if (crtc_state->sdvo_tv_clock)
8febb297 8752 factor = 20;
c1858123 8753
190f68c5 8754 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8755 *fp |= FP_CB_TUNE;
2c07245f 8756
9a7c7890
DV		 8757 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8758 *fp2 |= FP_CB_TUNE;
8759
5eddb70b 8760 dpll = 0;
2c07245f 8761
a07d6787
EA		 8762 if (is_lvds)
8763 dpll |= DPLLB_MODE_LVDS;
8764 else
8765 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8766
190f68c5 8767 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8768 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8769
8770 if (is_sdvo)
4a33e48d 8771 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8772 if (crtc_state->has_dp_encoder)
4a33e48d 8773 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8774
a07d6787 8775 /* compute bitmask from p1 value */
190f68c5 8776 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8777 /* also FPA1 */
190f68c5 8778 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8779
190f68c5 8780 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8781 case 5:
8782 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8783 break;
8784 case 7:
8785 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8786 break;
8787 case 10:
8788 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8789 break;
8790 case 14:
8791 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8792 break;
79e53945
JB		 8793 }
8794
b4c09f3b 8795 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8796 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8797 else
8798 dpll |= PLL_REF_INPUT_DREFCLK;
8799
959e16d6 8800 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8801}
8802
190f68c5
ACO		 8803static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8804 struct intel_crtc_state *crtc_state)
de13a2e3 8805{
c7653199 8806 struct drm_device *dev = crtc->base.dev;
de13a2e3 8807 intel_clock_t clock, reduced_clock;
cbbab5bd 8808 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8809 bool ok, has_reduced_clock = false;
8b47047b 8810 bool is_lvds = false;
e2b78267 8811 struct intel_shared_dpll *pll;
de13a2e3 8812
dd3cd74a
ACO		 8813 memset(&crtc_state->dpll_hw_state, 0,
8814 sizeof(crtc_state->dpll_hw_state));
8815
409ee761 8816 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8817
5dc5298b
PZ		 8818 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8819 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8820
190f68c5 8821 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8822 &has_reduced_clock, &reduced_clock);
190f68c5 8823 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8824 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8825 return -EINVAL;
79e53945 8826 }
f47709a9 8827 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8828 if (!crtc_state->clock_set) {
8829 crtc_state->dpll.n = clock.n;
8830 crtc_state->dpll.m1 = clock.m1;
8831 crtc_state->dpll.m2 = clock.m2;
8832 crtc_state->dpll.p1 = clock.p1;
8833 crtc_state->dpll.p2 = clock.p2;
f47709a9 8834 }
79e53945 8835
5dc5298b 8836 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8837 if (crtc_state->has_pch_encoder) {
8838 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8839 if (has_reduced_clock)
7429e9d4 8840 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8841
190f68c5 8842 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8843 &fp, &reduced_clock,
8844 has_reduced_clock ? &fp2 : NULL);
8845
190f68c5
ACO		 8846 crtc_state->dpll_hw_state.dpll = dpll;
8847 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8848 if (has_reduced_clock)
190f68c5 8849 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8850 else
190f68c5 8851 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8852
190f68c5 8853 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8854 if (pll == NULL) {
84f44ce7 8855 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8856 pipe_name(crtc->pipe));
4b645f14
JB		 8857 return -EINVAL;
8858 }
3fb37703 8859 }
79e53945 8860
ab585dea 8861 if (is_lvds && has_reduced_clock)
c7653199 8862 crtc->lowfreq_avail = true;
bcd644e0 8863 else
c7653199 8864 crtc->lowfreq_avail = false;
e2b78267 8865
c8f7a0db 8866 return 0;
79e53945
JB		 8867}
8868
eb14cb74
VS		 8869static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8870 struct intel_link_m_n *m_n)
8871{
8872 struct drm_device *dev = crtc->base.dev;
8873 struct drm_i915_private *dev_priv = dev->dev_private;
8874 enum pipe pipe = crtc->pipe;
8875
8876 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8877 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8878 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8879 & ~TU_SIZE_MASK;
8880 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8881 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8882 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8883}
8884
8885static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8886 enum transcoder transcoder,
b95af8be
VK		 8887 struct intel_link_m_n *m_n,
8888 struct intel_link_m_n *m2_n2)
72419203
DV		 8889{
8890 struct drm_device *dev = crtc->base.dev;
8891 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8892 enum pipe pipe = crtc->pipe;
72419203 8893
eb14cb74
VS		 8894 if (INTEL_INFO(dev)->gen >= 5) {
8895 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8896 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8897 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8898 & ~TU_SIZE_MASK;
8899 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8900 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8901 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8902 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8903 * gen < 8) and if DRRS is supported (to make sure the
8904 * registers are not unnecessarily read).
8905 */
8906 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8907 crtc->config->has_drrs) {
b95af8be
VK		 8908 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8909 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8910 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8911 & ~TU_SIZE_MASK;
8912 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8913 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8914 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8915 }
eb14cb74
VS		 8916 } else {
8917 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8918 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8919 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8920 & ~TU_SIZE_MASK;
8921 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8922 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8923 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8924 }
8925}
8926
8927void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8928 struct intel_crtc_state *pipe_config)
eb14cb74 8929{
681a8504 8930 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8931 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8932 else
8933 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8934 &pipe_config->dp_m_n,
8935 &pipe_config->dp_m2_n2);
eb14cb74 8936}
72419203 8937
eb14cb74 8938static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8939 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8940{
8941 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8942 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8943}
8944
bd2e244f 8945static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8946 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8947{
8948 struct drm_device *dev = crtc->base.dev;
8949 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8950 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8951 uint32_t ps_ctrl = 0;
8952 int id = -1;
8953 int i;
bd2e244f 8954
a1b2278e
CK		 8955 /* find scaler attached to this pipe */
8956 for (i = 0; i < crtc->num_scalers; i++) {
8957 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8958 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8959 id = i;
8960 pipe_config->pch_pfit.enabled = true;
8961 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8962 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8963 break;
8964 }
8965 }
bd2e244f 8966
a1b2278e
CK		 8967 scaler_state->scaler_id = id;
8968 if (id >= 0) {
8969 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8970 } else {
8971 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8972 }
8973}
8974
5724dbd1
DL		 8975static void
8976skylake_get_initial_plane_config(struct intel_crtc *crtc,
8977 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8978{
8979 struct drm_device *dev = crtc->base.dev;
8980 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8981 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8982 int pipe = crtc->pipe;
8983 int fourcc, pixel_format;
6761dd31 8984 unsigned int aligned_height;
bc8d7dff 8985 struct drm_framebuffer *fb;
1b842c89 8986 struct intel_framebuffer *intel_fb;
bc8d7dff 8987
d9806c9f 8988 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8989 if (!intel_fb) {
bc8d7dff
DL		 8990 DRM_DEBUG_KMS("failed to alloc fb\n");
8991 return;
8992 }
8993
1b842c89
DL		 8994 fb = &intel_fb->base;
8995
bc8d7dff 8996 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8997 if (!(val & PLANE_CTL_ENABLE))
8998 goto error;
8999
bc8d7dff
DL		 9000 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9001 fourcc = skl_format_to_fourcc(pixel_format,
9002 val & PLANE_CTL_ORDER_RGBX,
9003 val & PLANE_CTL_ALPHA_MASK);
9004 fb->pixel_format = fourcc;
9005 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9006
40f46283
DL		 9007 tiling = val & PLANE_CTL_TILED_MASK;
9008 switch (tiling) {
9009 case PLANE_CTL_TILED_LINEAR:
9010 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9011 break;
9012 case PLANE_CTL_TILED_X:
9013 plane_config->tiling = I915_TILING_X;
9014 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9015 break;
9016 case PLANE_CTL_TILED_Y:
9017 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9018 break;
9019 case PLANE_CTL_TILED_YF:
9020 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9021 break;
9022 default:
9023 MISSING_CASE(tiling);
9024 goto error;
9025 }
9026
bc8d7dff
DL		 9027 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9028 plane_config->base = base;
9029
9030 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9031
9032 val = I915_READ(PLANE_SIZE(pipe, 0));
9033 fb->height = ((val >> 16) & 0xfff) + 1;
9034 fb->width = ((val >> 0) & 0x1fff) + 1;
9035
9036 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9037 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9038 fb->pixel_format);
bc8d7dff
DL		 9039 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9040
9041 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9042 fb->pixel_format,
9043 fb->modifier[0]);
bc8d7dff 9044
f37b5c2b 9045 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9046
9047 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9048 pipe_name(pipe), fb->width, fb->height,
9049 fb->bits_per_pixel, base, fb->pitches[0],
9050 plane_config->size);
9051
2d14030b 9052 plane_config->fb = intel_fb;
bc8d7dff
DL		 9053 return;
9054
9055error:
9056 kfree(fb);
9057}
9058
2fa2fe9a 9059static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9060 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9061{
9062 struct drm_device *dev = crtc->base.dev;
9063 struct drm_i915_private *dev_priv = dev->dev_private;
9064 uint32_t tmp;
9065
9066 tmp = I915_READ(PF_CTL(crtc->pipe));
9067
9068 if (tmp & PF_ENABLE) {
fd4daa9c 9069 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9070 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9071 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9072
9073 /* We currently do not free assignements of panel fitters on
9074 * ivb/hsw (since we don't use the higher upscaling modes which
9075 * differentiates them) so just WARN about this case for now. */
9076 if (IS_GEN7(dev)) {
9077 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9078 PF_PIPE_SEL_IVB(crtc->pipe));
9079 }
2fa2fe9a 9080 }
79e53945
JB		 9081}
9082
5724dbd1
DL		 9083static void
9084ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9085 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9086{
9087 struct drm_device *dev = crtc->base.dev;
9088 struct drm_i915_private *dev_priv = dev->dev_private;
9089 u32 val, base, offset;
aeee5a49 9090 int pipe = crtc->pipe;
4c6baa59 9091 int fourcc, pixel_format;
6761dd31 9092 unsigned int aligned_height;
b113d5ee 9093 struct drm_framebuffer *fb;
1b842c89 9094 struct intel_framebuffer *intel_fb;
4c6baa59 9095
42a7b088
DL		 9096 val = I915_READ(DSPCNTR(pipe));
9097 if (!(val & DISPLAY_PLANE_ENABLE))
9098 return;
9099
d9806c9f 9100 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9101 if (!intel_fb) {
4c6baa59
JB		 9102 DRM_DEBUG_KMS("failed to alloc fb\n");
9103 return;
9104 }
9105
1b842c89
DL		 9106 fb = &intel_fb->base;
9107
18c5247e
DV		 9108 if (INTEL_INFO(dev)->gen >= 4) {
9109 if (val & DISPPLANE_TILED) {
49af449b 9110 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9111 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9112 }
9113 }
4c6baa59
JB		 9114
9115 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9116 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9117 fb->pixel_format = fourcc;
9118 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9119
aeee5a49 9120 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9121 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9122 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9123 } else {
49af449b 9124 if (plane_config->tiling)
aeee5a49 9125 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9126 else
aeee5a49 9127 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9128 }
9129 plane_config->base = base;
9130
9131 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9132 fb->width = ((val >> 16) & 0xfff) + 1;
9133 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9134
9135 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9136 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9137
b113d5ee 9138 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9139 fb->pixel_format,
9140 fb->modifier[0]);
4c6baa59 9141
f37b5c2b 9142 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9143
2844a921
DL		 9144 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9145 pipe_name(pipe), fb->width, fb->height,
9146 fb->bits_per_pixel, base, fb->pitches[0],
9147 plane_config->size);
b113d5ee 9148
2d14030b 9149 plane_config->fb = intel_fb;
4c6baa59
JB		 9150}
9151
0e8ffe1b 9152static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9153 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9154{
9155 struct drm_device *dev = crtc->base.dev;
9156 struct drm_i915_private *dev_priv = dev->dev_private;
9157 uint32_t tmp;
9158
f458ebbc
DV		 9159 if (!intel_display_power_is_enabled(dev_priv,
9160 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9161 return false;
9162
e143a21c 9163 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9164 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9165
0e8ffe1b
DV		 9166 tmp = I915_READ(PIPECONF(crtc->pipe));
9167 if (!(tmp & PIPECONF_ENABLE))
9168 return false;
9169
42571aef
VS		 9170 switch (tmp & PIPECONF_BPC_MASK) {
9171 case PIPECONF_6BPC:
9172 pipe_config->pipe_bpp = 18;
9173 break;
9174 case PIPECONF_8BPC:
9175 pipe_config->pipe_bpp = 24;
9176 break;
9177 case PIPECONF_10BPC:
9178 pipe_config->pipe_bpp = 30;
9179 break;
9180 case PIPECONF_12BPC:
9181 pipe_config->pipe_bpp = 36;
9182 break;
9183 default:
9184 break;
9185 }
9186
b5a9fa09
DV		 9187 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9188 pipe_config->limited_color_range = true;
9189
ab9412ba 9190 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9191 struct intel_shared_dpll *pll;
9192
88adfff1
DV		 9193 pipe_config->has_pch_encoder = true;
9194
627eb5a3
DV		 9195 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9196 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9197 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9198
9199 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9200
c0d43d62 9201 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9202 pipe_config->shared_dpll =
9203 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9204 } else {
9205 tmp = I915_READ(PCH_DPLL_SEL);
9206 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9207 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9208 else
9209 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9210 }
66e985c0
DV		 9211
9212 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9213
9214 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9215 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9216
9217 tmp = pipe_config->dpll_hw_state.dpll;
9218 pipe_config->pixel_multiplier =
9219 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9220 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9221
9222 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9223 } else {
9224 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9225 }
9226
1bd1bd80
DV		 9227 intel_get_pipe_timings(crtc, pipe_config);
9228
2fa2fe9a
DV		 9229 ironlake_get_pfit_config(crtc, pipe_config);
9230
0e8ffe1b
DV		 9231 return true;
9232}
9233
be256dc7
PZ		 9234static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9235{
9236 struct drm_device *dev = dev_priv->dev;
be256dc7 9237 struct intel_crtc *crtc;
be256dc7 9238
d3fcc808 9239 for_each_intel_crtc(dev, crtc)
e2c719b7 9240 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9241 pipe_name(crtc->pipe));
9242
e2c719b7
RC		 9243 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9244 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9245 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9246 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9247 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9248 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9249 "CPU PWM1 enabled\n");
c5107b87 9250 if (IS_HASWELL(dev))
e2c719b7 9251 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9252 "CPU PWM2 enabled\n");
e2c719b7 9253 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9254 "PCH PWM1 enabled\n");
e2c719b7 9255 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9256 "Utility pin enabled\n");
e2c719b7 9257 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9258
9926ada1
PZ		 9259 /*
9260 * In theory we can still leave IRQs enabled, as long as only the HPD
9261 * interrupts remain enabled. We used to check for that, but since it's
9262 * gen-specific and since we only disable LCPLL after we fully disable
9263 * the interrupts, the check below should be enough.
9264 */
e2c719b7 9265 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9266}
9267
9ccd5aeb
PZ		 9268static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9269{
9270 struct drm_device *dev = dev_priv->dev;
9271
9272 if (IS_HASWELL(dev))
9273 return I915_READ(D_COMP_HSW);
9274 else
9275 return I915_READ(D_COMP_BDW);
9276}
9277
3c4c9b81
PZ		 9278static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9279{
9280 struct drm_device *dev = dev_priv->dev;
9281
9282 if (IS_HASWELL(dev)) {
9283 mutex_lock(&dev_priv->rps.hw_lock);
9284 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9285 val))
f475dadf 9286 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9287 mutex_unlock(&dev_priv->rps.hw_lock);
9288 } else {
9ccd5aeb
PZ		 9289 I915_WRITE(D_COMP_BDW, val);
9290 POSTING_READ(D_COMP_BDW);
3c4c9b81 9291 }
be256dc7
PZ		 9292}
9293
9294/*
9295 * This function implements pieces of two sequences from BSpec:
9296 * - Sequence for display software to disable LCPLL
9297 * - Sequence for display software to allow package C8+
9298 * The steps implemented here are just the steps that actually touch the LCPLL
9299 * register. Callers should take care of disabling all the display engine
9300 * functions, doing the mode unset, fixing interrupts, etc.
9301 */
6ff58d53
PZ		 9302static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9303 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9304{
9305 uint32_t val;
9306
9307 assert_can_disable_lcpll(dev_priv);
9308
9309 val = I915_READ(LCPLL_CTL);
9310
9311 if (switch_to_fclk) {
9312 val |= LCPLL_CD_SOURCE_FCLK;
9313 I915_WRITE(LCPLL_CTL, val);
9314
9315 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9316 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9317 DRM_ERROR("Switching to FCLK failed\n");
9318
9319 val = I915_READ(LCPLL_CTL);
9320 }
9321
9322 val |= LCPLL_PLL_DISABLE;
9323 I915_WRITE(LCPLL_CTL, val);
9324 POSTING_READ(LCPLL_CTL);
9325
9326 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9327 DRM_ERROR("LCPLL still locked\n");
9328
9ccd5aeb 9329 val = hsw_read_dcomp(dev_priv);
be256dc7 9330 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9331 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9332 ndelay(100);
9333
9ccd5aeb
PZ		 9334 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9335 1))
be256dc7
PZ		 9336 DRM_ERROR("D_COMP RCOMP still in progress\n");
9337
9338 if (allow_power_down) {
9339 val = I915_READ(LCPLL_CTL);
9340 val |= LCPLL_POWER_DOWN_ALLOW;
9341 I915_WRITE(LCPLL_CTL, val);
9342 POSTING_READ(LCPLL_CTL);
9343 }
9344}
9345
9346/*
9347 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9348 * source.
9349 */
6ff58d53 9350static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9351{
9352 uint32_t val;
9353
9354 val = I915_READ(LCPLL_CTL);
9355
9356 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9357 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9358 return;
9359
a8a8bd54
PZ		 9360 /*
9361 * Make sure we're not on PC8 state before disabling PC8, otherwise
9362 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9363 */
59bad947 9364 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9365
be256dc7
PZ		 9366 if (val & LCPLL_POWER_DOWN_ALLOW) {
9367 val &= ~LCPLL_POWER_DOWN_ALLOW;
9368 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9369 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9370 }
9371
9ccd5aeb 9372 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9373 val |= D_COMP_COMP_FORCE;
9374 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9375 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9376
9377 val = I915_READ(LCPLL_CTL);
9378 val &= ~LCPLL_PLL_DISABLE;
9379 I915_WRITE(LCPLL_CTL, val);
9380
9381 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9382 DRM_ERROR("LCPLL not locked yet\n");
9383
9384 if (val & LCPLL_CD_SOURCE_FCLK) {
9385 val = I915_READ(LCPLL_CTL);
9386 val &= ~LCPLL_CD_SOURCE_FCLK;
9387 I915_WRITE(LCPLL_CTL, val);
9388
9389 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9390 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9391 DRM_ERROR("Switching back to LCPLL failed\n");
9392 }
215733fa 9393
59bad947 9394 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9395 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9396}
9397
765dab67
PZ		 9398/*
9399 * Package states C8 and deeper are really deep PC states that can only be
9400 * reached when all the devices on the system allow it, so even if the graphics
9401 * device allows PC8+, it doesn't mean the system will actually get to these
9402 * states. Our driver only allows PC8+ when going into runtime PM.
9403 *
9404 * The requirements for PC8+ are that all the outputs are disabled, the power
9405 * well is disabled and most interrupts are disabled, and these are also
9406 * requirements for runtime PM. When these conditions are met, we manually do
9407 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9408 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9409 * hang the machine.
9410 *
9411 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9412 * the state of some registers, so when we come back from PC8+ we need to
9413 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9414 * need to take care of the registers kept by RC6. Notice that this happens even
9415 * if we don't put the device in PCI D3 state (which is what currently happens
9416 * because of the runtime PM support).
9417 *
9418 * For more, read "Display Sequences for Package C8" on the hardware
9419 * documentation.
9420 */
a14cb6fc 9421void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9422{
c67a470b
PZ		 9423 struct drm_device *dev = dev_priv->dev;
9424 uint32_t val;
9425
c67a470b
PZ		 9426 DRM_DEBUG_KMS("Enabling package C8+\n");
9427
c67a470b
PZ		 9428 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9429 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9430 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9431 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9432 }
9433
9434 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9435 hsw_disable_lcpll(dev_priv, true, true);
9436}
9437
a14cb6fc 9438void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9439{
9440 struct drm_device *dev = dev_priv->dev;
9441 uint32_t val;
9442
c67a470b
PZ		 9443 DRM_DEBUG_KMS("Disabling package C8+\n");
9444
9445 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9446 lpt_init_pch_refclk(dev);
9447
9448 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9449 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9450 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9451 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9452 }
9453
9454 intel_prepare_ddi(dev);
c67a470b
PZ		 9455}
9456
27c329ed 9457static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9458{
a821fc46 9459 struct drm_device *dev = old_state->dev;
27c329ed 9460 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9461
27c329ed 9462 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9463}
9464
b432e5cf 9465/* compute the max rate for new configuration */
27c329ed 9466static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9467{
b432e5cf 9468 struct intel_crtc *intel_crtc;
27c329ed 9469 struct intel_crtc_state *crtc_state;
b432e5cf 9470 int max_pixel_rate = 0;
b432e5cf 9471
27c329ed
ML		 9472 for_each_intel_crtc(state->dev, intel_crtc) {
9473 int pixel_rate;
9474
9475 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9476 if (IS_ERR(crtc_state))
9477 return PTR_ERR(crtc_state);
9478
9479 if (!crtc_state->base.enable)
b432e5cf
VS		 9480 continue;
9481
27c329ed 9482 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9483
9484 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9485 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9486 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9487
9488 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9489 }
9490
9491 return max_pixel_rate;
9492}
9493
9494static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9495{
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9497 uint32_t val, data;
9498 int ret;
9499
9500 if (WARN((I915_READ(LCPLL_CTL) &
9501 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9502 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9503 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9504 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9505 "trying to change cdclk frequency with cdclk not enabled\n"))
9506 return;
9507
9508 mutex_lock(&dev_priv->rps.hw_lock);
9509 ret = sandybridge_pcode_write(dev_priv,
9510 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9511 mutex_unlock(&dev_priv->rps.hw_lock);
9512 if (ret) {
9513 DRM_ERROR("failed to inform pcode about cdclk change\n");
9514 return;
9515 }
9516
9517 val = I915_READ(LCPLL_CTL);
9518 val |= LCPLL_CD_SOURCE_FCLK;
9519 I915_WRITE(LCPLL_CTL, val);
9520
9521 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9522 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9523 DRM_ERROR("Switching to FCLK failed\n");
9524
9525 val = I915_READ(LCPLL_CTL);
9526 val &= ~LCPLL_CLK_FREQ_MASK;
9527
9528 switch (cdclk) {
9529 case 450000:
9530 val |= LCPLL_CLK_FREQ_450;
9531 data = 0;
9532 break;
9533 case 540000:
9534 val |= LCPLL_CLK_FREQ_54O_BDW;
9535 data = 1;
9536 break;
9537 case 337500:
9538 val |= LCPLL_CLK_FREQ_337_5_BDW;
9539 data = 2;
9540 break;
9541 case 675000:
9542 val |= LCPLL_CLK_FREQ_675_BDW;
9543 data = 3;
9544 break;
9545 default:
9546 WARN(1, "invalid cdclk frequency\n");
9547 return;
9548 }
9549
9550 I915_WRITE(LCPLL_CTL, val);
9551
9552 val = I915_READ(LCPLL_CTL);
9553 val &= ~LCPLL_CD_SOURCE_FCLK;
9554 I915_WRITE(LCPLL_CTL, val);
9555
9556 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9557 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9558 DRM_ERROR("Switching back to LCPLL failed\n");
9559
9560 mutex_lock(&dev_priv->rps.hw_lock);
9561 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9562 mutex_unlock(&dev_priv->rps.hw_lock);
9563
9564 intel_update_cdclk(dev);
9565
9566 WARN(cdclk != dev_priv->cdclk_freq,
9567 "cdclk requested %d kHz but got %d kHz\n",
9568 cdclk, dev_priv->cdclk_freq);
9569}
9570
27c329ed 9571static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9572{
27c329ed
ML		 9573 struct drm_i915_private *dev_priv = to_i915(state->dev);
9574 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9575 int cdclk;
9576
9577 /*
9578 * FIXME should also account for plane ratio
9579 * once 64bpp pixel formats are supported.
9580 */
27c329ed 9581 if (max_pixclk > 540000)
b432e5cf 9582 cdclk = 675000;
27c329ed 9583 else if (max_pixclk > 450000)
b432e5cf 9584 cdclk = 540000;
27c329ed 9585 else if (max_pixclk > 337500)
b432e5cf
VS		 9586 cdclk = 450000;
9587 else
9588 cdclk = 337500;
9589
9590 /*
9591 * FIXME move the cdclk caclulation to
9592 * compute_config() so we can fail gracegully.
9593 */
9594 if (cdclk > dev_priv->max_cdclk_freq) {
9595 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9596 cdclk, dev_priv->max_cdclk_freq);
9597 cdclk = dev_priv->max_cdclk_freq;
9598 }
9599
27c329ed 9600 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9601
9602 return 0;
9603}
9604
27c329ed 9605static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9606{
27c329ed
ML		 9607 struct drm_device *dev = old_state->dev;
9608 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9609
27c329ed 9610 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9611}
9612
190f68c5
ACO		 9613static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9614 struct intel_crtc_state *crtc_state)
09b4ddf9 9615{
190f68c5 9616 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9617 return -EINVAL;
716c2e55 9618
c7653199 9619 crtc->lowfreq_avail = false;
644cef34 9620
c8f7a0db 9621 return 0;
79e53945
JB		 9622}
9623
3760b59c
S		 9624static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9625 enum port port,
9626 struct intel_crtc_state *pipe_config)
9627{
9628 switch (port) {
9629 case PORT_A:
9630 pipe_config->ddi_pll_sel = SKL_DPLL0;
9631 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9632 break;
9633 case PORT_B:
9634 pipe_config->ddi_pll_sel = SKL_DPLL1;
9635 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9636 break;
9637 case PORT_C:
9638 pipe_config->ddi_pll_sel = SKL_DPLL2;
9639 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9640 break;
9641 default:
9642 DRM_ERROR("Incorrect port type\n");
9643 }
9644}
9645
96b7dfb7
S		 9646static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9647 enum port port,
5cec258b 9648 struct intel_crtc_state *pipe_config)
96b7dfb7 9649{
3148ade7 9650 u32 temp, dpll_ctl1;
96b7dfb7
S		 9651
9652 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9653 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9654
9655 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9656 case SKL_DPLL0:
9657 /*
9658 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9659 * of the shared DPLL framework and thus needs to be read out
9660 * separately
9661 */
9662 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9663 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9664 break;
96b7dfb7
S		 9665 case SKL_DPLL1:
9666 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9667 break;
9668 case SKL_DPLL2:
9669 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9670 break;
9671 case SKL_DPLL3:
9672 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9673 break;
96b7dfb7
S		 9674 }
9675}
9676
7d2c8175
DL		 9677static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9678 enum port port,
5cec258b 9679 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9680{
9681 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9682
9683 switch (pipe_config->ddi_pll_sel) {
9684 case PORT_CLK_SEL_WRPLL1:
9685 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9686 break;
9687 case PORT_CLK_SEL_WRPLL2:
9688 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9689 break;
9690 }
9691}
9692
26804afd 9693static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9694 struct intel_crtc_state *pipe_config)
26804afd
DV		 9695{
9696 struct drm_device *dev = crtc->base.dev;
9697 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9698 struct intel_shared_dpll *pll;
26804afd
DV		 9699 enum port port;
9700 uint32_t tmp;
9701
9702 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9703
9704 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9705
96b7dfb7
S		 9706 if (IS_SKYLAKE(dev))
9707 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9708 else if (IS_BROXTON(dev))
9709 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9710 else
9711 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9712
d452c5b6
DV		 9713 if (pipe_config->shared_dpll >= 0) {
9714 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9715
9716 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9717 &pipe_config->dpll_hw_state));
9718 }
9719
26804afd
DV		 9720 /*
9721 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9722 * DDI E. So just check whether this pipe is wired to DDI E and whether
9723 * the PCH transcoder is on.
9724 */
ca370455
DL		 9725 if (INTEL_INFO(dev)->gen < 9 &&
9726 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9727 pipe_config->has_pch_encoder = true;
9728
9729 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9730 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9731 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9732
9733 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9734 }
9735}
9736
0e8ffe1b 9737static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9738 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9739{
9740 struct drm_device *dev = crtc->base.dev;
9741 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9742 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9743 uint32_t tmp;
9744
f458ebbc 9745 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9746 POWER_DOMAIN_PIPE(crtc->pipe)))
9747 return false;
9748
e143a21c 9749 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9750 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9751
eccb140b
DV		 9752 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9753 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9754 enum pipe trans_edp_pipe;
9755 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9756 default:
9757 WARN(1, "unknown pipe linked to edp transcoder\n");
9758 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9759 case TRANS_DDI_EDP_INPUT_A_ON:
9760 trans_edp_pipe = PIPE_A;
9761 break;
9762 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9763 trans_edp_pipe = PIPE_B;
9764 break;
9765 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9766 trans_edp_pipe = PIPE_C;
9767 break;
9768 }
9769
9770 if (trans_edp_pipe == crtc->pipe)
9771 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9772 }
9773
f458ebbc 9774 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9775 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9776 return false;
9777
eccb140b 9778 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9779 if (!(tmp & PIPECONF_ENABLE))
9780 return false;
9781
26804afd 9782 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9783
1bd1bd80
DV		 9784 intel_get_pipe_timings(crtc, pipe_config);
9785
a1b2278e
CK		 9786 if (INTEL_INFO(dev)->gen >= 9) {
9787 skl_init_scalers(dev, crtc, pipe_config);
9788 }
9789
2fa2fe9a 9790 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9791
9792 if (INTEL_INFO(dev)->gen >= 9) {
9793 pipe_config->scaler_state.scaler_id = -1;
9794 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9795 }
9796
bd2e244f 9797 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9798 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9799 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9800 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9801 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9802 else
9803 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9804 }
88adfff1 9805
e59150dc
JB		 9806 if (IS_HASWELL(dev))
9807 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9808 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9809
ebb69c95
CT		 9810 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9811 pipe_config->pixel_multiplier =
9812 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9813 } else {
9814 pipe_config->pixel_multiplier = 1;
9815 }
6c49f241 9816
0e8ffe1b
DV		 9817 return true;
9818}
9819
560b85bb
CW		 9820static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9821{
9822 struct drm_device *dev = crtc->dev;
9823 struct drm_i915_private *dev_priv = dev->dev_private;
9824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9825 uint32_t cntl = 0, size = 0;
560b85bb 9826
dc41c154 9827 if (base) {
3dd512fb
MR		 9828 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9829 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9830 unsigned int stride = roundup_pow_of_two(width) * 4;
9831
9832 switch (stride) {
9833 default:
9834 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9835 width, stride);
9836 stride = 256;
9837 /* fallthrough */
9838 case 256:
9839 case 512:
9840 case 1024:
9841 case 2048:
9842 break;
4b0e333e
CW		 9843 }
9844
dc41c154
VS		 9845 cntl |= CURSOR_ENABLE |
9846 CURSOR_GAMMA_ENABLE |
9847 CURSOR_FORMAT_ARGB |
9848 CURSOR_STRIDE(stride);
9849
9850 size = (height << 12) | width;
4b0e333e 9851 }
560b85bb 9852
dc41c154
VS		 9853 if (intel_crtc->cursor_cntl != 0 &&
9854 (intel_crtc->cursor_base != base ||
9855 intel_crtc->cursor_size != size ||
9856 intel_crtc->cursor_cntl != cntl)) {
9857 /* On these chipsets we can only modify the base/size/stride
9858 * whilst the cursor is disabled.
9859 */
9860 I915_WRITE(_CURACNTR, 0);
4b0e333e 9861 POSTING_READ(_CURACNTR);
dc41c154 9862 intel_crtc->cursor_cntl = 0;
4b0e333e 9863 }
560b85bb 9864
99d1f387 9865 if (intel_crtc->cursor_base != base) {
9db4a9c7 9866 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9867 intel_crtc->cursor_base = base;
9868 }
4726e0b0 9869
dc41c154
VS		 9870 if (intel_crtc->cursor_size != size) {
9871 I915_WRITE(CURSIZE, size);
9872 intel_crtc->cursor_size = size;
4b0e333e 9873 }
560b85bb 9874
4b0e333e 9875 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9876 I915_WRITE(_CURACNTR, cntl);
9877 POSTING_READ(_CURACNTR);
4b0e333e 9878 intel_crtc->cursor_cntl = cntl;
560b85bb 9879 }
560b85bb
CW		 9880}
9881
560b85bb 9882static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9883{
9884 struct drm_device *dev = crtc->dev;
9885 struct drm_i915_private *dev_priv = dev->dev_private;
9886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9887 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9888 uint32_t cntl;
9889
9890 cntl = 0;
9891 if (base) {
9892 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9893 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9894 case 64:
9895 cntl |= CURSOR_MODE_64_ARGB_AX;
9896 break;
9897 case 128:
9898 cntl |= CURSOR_MODE_128_ARGB_AX;
9899 break;
9900 case 256:
9901 cntl |= CURSOR_MODE_256_ARGB_AX;
9902 break;
9903 default:
3dd512fb 9904 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9905 return;
65a21cd6 9906 }
4b0e333e 9907 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9908
9909 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9910 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9911 }
65a21cd6 9912
8e7d688b 9913 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9914 cntl |= CURSOR_ROTATE_180;
9915
4b0e333e
CW		 9916 if (intel_crtc->cursor_cntl != cntl) {
9917 I915_WRITE(CURCNTR(pipe), cntl);
9918 POSTING_READ(CURCNTR(pipe));
9919 intel_crtc->cursor_cntl = cntl;
65a21cd6 9920 }
4b0e333e 9921
65a21cd6 9922 /* and commit changes on next vblank */
5efb3e28
VS		 9923 I915_WRITE(CURBASE(pipe), base);
9924 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9925
9926 intel_crtc->cursor_base = base;
65a21cd6
JB		 9927}
9928
cda4b7d3 9929/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9930static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9931 bool on)
cda4b7d3
CW		 9932{
9933 struct drm_device *dev = crtc->dev;
9934 struct drm_i915_private *dev_priv = dev->dev_private;
9935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9936 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9937 int x = crtc->cursor_x;
9938 int y = crtc->cursor_y;
d6e4db15 9939 u32 base = 0, pos = 0;
cda4b7d3 9940
d6e4db15 9941 if (on)
cda4b7d3 9942 base = intel_crtc->cursor_addr;
cda4b7d3 9943
6e3c9717 9944 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9945 base = 0;
9946
6e3c9717 9947 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9948 base = 0;
9949
9950 if (x < 0) {
3dd512fb 9951 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9952 base = 0;
9953
9954 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9955 x = -x;
9956 }
9957 pos |= x << CURSOR_X_SHIFT;
9958
9959 if (y < 0) {
3dd512fb 9960 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9961 base = 0;
9962
9963 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9964 y = -y;
9965 }
9966 pos |= y << CURSOR_Y_SHIFT;
9967
4b0e333e 9968 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9969 return;
9970
5efb3e28
VS		 9971 I915_WRITE(CURPOS(pipe), pos);
9972
4398ad45
VS		 9973 /* ILK+ do this automagically */
9974 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9975 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9976 base += (intel_crtc->base.cursor->state->crtc_h *
9977 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9978 }
9979
8ac54669 9980 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9981 i845_update_cursor(crtc, base);
9982 else
9983 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9984}
9985
dc41c154
VS		 9986static bool cursor_size_ok(struct drm_device *dev,
9987 uint32_t width, uint32_t height)
9988{
9989 if (width == 0 || height == 0)
9990 return false;
9991
9992 /*
9993 * 845g/865g are special in that they are only limited by
9994 * the width of their cursors, the height is arbitrary up to
9995 * the precision of the register. Everything else requires
9996 * square cursors, limited to a few power-of-two sizes.
9997 */
9998 if (IS_845G(dev) || IS_I865G(dev)) {
9999 if ((width & 63) != 0)
10000 return false;
10001
10002 if (width > (IS_845G(dev) ? 64 : 512))
10003 return false;
10004
10005 if (height > 1023)
10006 return false;
10007 } else {
10008 switch (width | height) {
10009 case 256:
10010 case 128:
10011 if (IS_GEN2(dev))
10012 return false;
10013 case 64:
10014 break;
10015 default:
10016 return false;
10017 }
10018 }
10019
10020 return true;
10021}
10022
79e53945 10023static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10024 u16 *blue, uint32_t start, uint32_t size)
79e53945 10025{
7203425a 10026 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10028
7203425a 10029 for (i = start; i < end; i++) {
79e53945
JB		 10030 intel_crtc->lut_r[i] = red[i] >> 8;
10031 intel_crtc->lut_g[i] = green[i] >> 8;
10032 intel_crtc->lut_b[i] = blue[i] >> 8;
10033 }
10034
10035 intel_crtc_load_lut(crtc);
10036}
10037
79e53945
JB		 10038/* VESA 640x480x72Hz mode to set on the pipe */
10039static struct drm_display_mode load_detect_mode = {
10040 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10041 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10042};
10043
a8bb6818
DV		 10044struct drm_framebuffer *
10045__intel_framebuffer_create(struct drm_device *dev,
10046 struct drm_mode_fb_cmd2 *mode_cmd,
10047 struct drm_i915_gem_object *obj)
d2dff872
CW		 10048{
10049 struct intel_framebuffer *intel_fb;
10050 int ret;
10051
10052 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10053 if (!intel_fb) {
6ccb81f2 10054 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10055 return ERR_PTR(-ENOMEM);
10056 }
10057
10058 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10059 if (ret)
10060 goto err;
d2dff872
CW		 10061
10062 return &intel_fb->base;
dd4916c5 10063err:
6ccb81f2 10064 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10065 kfree(intel_fb);
10066
10067 return ERR_PTR(ret);
d2dff872
CW		 10068}
10069
b5ea642a 10070static struct drm_framebuffer *
a8bb6818
DV		 10071intel_framebuffer_create(struct drm_device *dev,
10072 struct drm_mode_fb_cmd2 *mode_cmd,
10073 struct drm_i915_gem_object *obj)
10074{
10075 struct drm_framebuffer *fb;
10076 int ret;
10077
10078 ret = i915_mutex_lock_interruptible(dev);
10079 if (ret)
10080 return ERR_PTR(ret);
10081 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10082 mutex_unlock(&dev->struct_mutex);
10083
10084 return fb;
10085}
10086
d2dff872
CW		 10087static u32
10088intel_framebuffer_pitch_for_width(int width, int bpp)
10089{
10090 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10091 return ALIGN(pitch, 64);
10092}
10093
10094static u32
10095intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10096{
10097 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10098 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10099}
10100
10101static struct drm_framebuffer *
10102intel_framebuffer_create_for_mode(struct drm_device *dev,
10103 struct drm_display_mode *mode,
10104 int depth, int bpp)
10105{
10106 struct drm_i915_gem_object *obj;
0fed39bd 10107 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10108
10109 obj = i915_gem_alloc_object(dev,
10110 intel_framebuffer_size_for_mode(mode, bpp));
10111 if (obj == NULL)
10112 return ERR_PTR(-ENOMEM);
10113
10114 mode_cmd.width = mode->hdisplay;
10115 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10116 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10117 bpp);
5ca0c34a 10118 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10119
10120 return intel_framebuffer_create(dev, &mode_cmd, obj);
10121}
10122
10123static struct drm_framebuffer *
10124mode_fits_in_fbdev(struct drm_device *dev,
10125 struct drm_display_mode *mode)
10126{
4520f53a 10127#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10128 struct drm_i915_private *dev_priv = dev->dev_private;
10129 struct drm_i915_gem_object *obj;
10130 struct drm_framebuffer *fb;
10131
4c0e5528 10132 if (!dev_priv->fbdev)
d2dff872
CW		 10133 return NULL;
10134
4c0e5528 10135 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10136 return NULL;
10137
4c0e5528
DV		 10138 obj = dev_priv->fbdev->fb->obj;
10139 BUG_ON(!obj);
10140
8bcd4553 10141 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10142 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10143 fb->bits_per_pixel))
d2dff872
CW		 10144 return NULL;
10145
01f2c773 10146 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10147 return NULL;
10148
10149 return fb;
4520f53a
DV		 10150#else
10151 return NULL;
10152#endif
d2dff872
CW		 10153}
10154
d3a40d1b
ACO		 10155static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10156 struct drm_crtc *crtc,
10157 struct drm_display_mode *mode,
10158 struct drm_framebuffer *fb,
10159 int x, int y)
10160{
10161 struct drm_plane_state *plane_state;
10162 int hdisplay, vdisplay;
10163 int ret;
10164
10165 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10166 if (IS_ERR(plane_state))
10167 return PTR_ERR(plane_state);
10168
10169 if (mode)
10170 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10171 else
10172 hdisplay = vdisplay = 0;
10173
10174 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10175 if (ret)
10176 return ret;
10177 drm_atomic_set_fb_for_plane(plane_state, fb);
10178 plane_state->crtc_x = 0;
10179 plane_state->crtc_y = 0;
10180 plane_state->crtc_w = hdisplay;
10181 plane_state->crtc_h = vdisplay;
10182 plane_state->src_x = x << 16;
10183 plane_state->src_y = y << 16;
10184 plane_state->src_w = hdisplay << 16;
10185 plane_state->src_h = vdisplay << 16;
10186
10187 return 0;
10188}
10189
d2434ab7 10190bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10191 struct drm_display_mode *mode,
51fd371b
RC		 10192 struct intel_load_detect_pipe *old,
10193 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10194{
10195 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10196 struct intel_encoder *intel_encoder =
10197 intel_attached_encoder(connector);
79e53945 10198 struct drm_crtc *possible_crtc;
4ef69c7a 10199 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10200 struct drm_crtc *crtc = NULL;
10201 struct drm_device *dev = encoder->dev;
94352cf9 10202 struct drm_framebuffer *fb;
51fd371b 10203 struct drm_mode_config *config = &dev->mode_config;
83a57153 10204 struct drm_atomic_state *state = NULL;
944b0c76 10205 struct drm_connector_state *connector_state;
4be07317 10206 struct intel_crtc_state *crtc_state;
51fd371b 10207 int ret, i = -1;
79e53945 10208
d2dff872 10209 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10210 connector->base.id, connector->name,
8e329a03 10211 encoder->base.id, encoder->name);
d2dff872 10212
51fd371b
RC		 10213retry:
10214 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10215 if (ret)
10216 goto fail_unlock;
6e9f798d 10217
79e53945
JB		 10218 /*
10219 * Algorithm gets a little messy:
7a5e4805 10220 *
79e53945
JB		 10221 * - if the connector already has an assigned crtc, use it (but make
10222 * sure it's on first)
7a5e4805 10223 *
79e53945
JB		 10224 * - try to find the first unused crtc that can drive this connector,
10225 * and use that if we find one
79e53945
JB		 10226 */
10227
10228 /* See if we already have a CRTC for this connector */
10229 if (encoder->crtc) {
10230 crtc = encoder->crtc;
8261b191 10231
51fd371b 10232 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10233 if (ret)
10234 goto fail_unlock;
10235 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10236 if (ret)
10237 goto fail_unlock;
7b24056b 10238
24218aac 10239 old->dpms_mode = connector->dpms;
8261b191
CW		 10240 old->load_detect_temp = false;
10241
10242 /* Make sure the crtc and connector are running */
24218aac
DV		 10243 if (connector->dpms != DRM_MODE_DPMS_ON)
10244 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10245
7173188d 10246 return true;
79e53945
JB		 10247 }
10248
10249 /* Find an unused one (if possible) */
70e1e0ec 10250 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10251 i++;
10252 if (!(encoder->possible_crtcs & (1 << i)))
10253 continue;
83d65738 10254 if (possible_crtc->state->enable)
a459249c
VS		 10255 continue;
10256 /* This can occur when applying the pipe A quirk on resume. */
10257 if (to_intel_crtc(possible_crtc)->new_enabled)
10258 continue;
10259
10260 crtc = possible_crtc;
10261 break;
79e53945
JB		 10262 }
10263
10264 /*
10265 * If we didn't find an unused CRTC, don't use any.
10266 */
10267 if (!crtc) {
7173188d 10268 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10269 goto fail_unlock;
79e53945
JB		 10270 }
10271
51fd371b
RC		 10272 ret = drm_modeset_lock(&crtc->mutex, ctx);
10273 if (ret)
4d02e2de
DV		 10274 goto fail_unlock;
10275 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10276 if (ret)
51fd371b 10277 goto fail_unlock;
fc303101
DV		 10278 intel_encoder->new_crtc = to_intel_crtc(crtc);
10279 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10280
10281 intel_crtc = to_intel_crtc(crtc);
412b61d8 10282 intel_crtc->new_enabled = true;
24218aac 10283 old->dpms_mode = connector->dpms;
8261b191 10284 old->load_detect_temp = true;
d2dff872 10285 old->release_fb = NULL;
79e53945 10286
83a57153
ACO		 10287 state = drm_atomic_state_alloc(dev);
10288 if (!state)
10289 return false;
10290
10291 state->acquire_ctx = ctx;
10292
944b0c76
ACO		 10293 connector_state = drm_atomic_get_connector_state(state, connector);
10294 if (IS_ERR(connector_state)) {
10295 ret = PTR_ERR(connector_state);
10296 goto fail;
10297 }
10298
10299 connector_state->crtc = crtc;
10300 connector_state->best_encoder = &intel_encoder->base;
10301
4be07317
ACO		 10302 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10303 if (IS_ERR(crtc_state)) {
10304 ret = PTR_ERR(crtc_state);
10305 goto fail;
10306 }
10307
49d6fa21 10308 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10309
6492711d
CW		 10310 if (!mode)
10311 mode = &load_detect_mode;
79e53945 10312
d2dff872
CW		 10313 /* We need a framebuffer large enough to accommodate all accesses
10314 * that the plane may generate whilst we perform load detection.
10315 * We can not rely on the fbcon either being present (we get called
10316 * during its initialisation to detect all boot displays, or it may
10317 * not even exist) or that it is large enough to satisfy the
10318 * requested mode.
10319 */
94352cf9
DV		 10320 fb = mode_fits_in_fbdev(dev, mode);
10321 if (fb == NULL) {
d2dff872 10322 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10323 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10324 old->release_fb = fb;
d2dff872
CW		 10325 } else
10326 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10327 if (IS_ERR(fb)) {
d2dff872 10328 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10329 goto fail;
79e53945 10330 }
79e53945 10331
d3a40d1b
ACO		 10332 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10333 if (ret)
10334 goto fail;
10335
8c7b5ccb
ACO		 10336 drm_mode_copy(&crtc_state->base.mode, mode);
10337
568c634a 10338 if (intel_set_mode(state)) {
6492711d 10339 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10340 if (old->release_fb)
10341 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10342 goto fail;
79e53945 10343 }
9128b040 10344 crtc->primary->crtc = crtc;
7173188d 10345
79e53945 10346 /* let the connector get through one full cycle before testing */
9d0498a2 10347 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10348 return true;
412b61d8
VS		 10349
10350 fail:
83d65738 10351 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10352fail_unlock:
e5d958ef
ACO		 10353 drm_atomic_state_free(state);
10354 state = NULL;
83a57153 10355
51fd371b
RC		 10356 if (ret == -EDEADLK) {
10357 drm_modeset_backoff(ctx);
10358 goto retry;
10359 }
10360
412b61d8 10361 return false;
79e53945
JB		 10362}
10363
d2434ab7 10364void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10365 struct intel_load_detect_pipe *old,
10366 struct drm_modeset_acquire_ctx *ctx)
79e53945 10367{
83a57153 10368 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10369 struct intel_encoder *intel_encoder =
10370 intel_attached_encoder(connector);
4ef69c7a 10371 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10372 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10374 struct drm_atomic_state *state;
944b0c76 10375 struct drm_connector_state *connector_state;
4be07317 10376 struct intel_crtc_state *crtc_state;
d3a40d1b 10377 int ret;
79e53945 10378
d2dff872 10379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10380 connector->base.id, connector->name,
8e329a03 10381 encoder->base.id, encoder->name);
d2dff872 10382
8261b191 10383 if (old->load_detect_temp) {
83a57153 10384 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10385 if (!state)
10386 goto fail;
83a57153
ACO		 10387
10388 state->acquire_ctx = ctx;
10389
944b0c76
ACO		 10390 connector_state = drm_atomic_get_connector_state(state, connector);
10391 if (IS_ERR(connector_state))
10392 goto fail;
10393
4be07317
ACO		 10394 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10395 if (IS_ERR(crtc_state))
10396 goto fail;
10397
fc303101
DV		 10398 to_intel_connector(connector)->new_encoder = NULL;
10399 intel_encoder->new_crtc = NULL;
412b61d8 10400 intel_crtc->new_enabled = false;
944b0c76
ACO		 10401
10402 connector_state->best_encoder = NULL;
10403 connector_state->crtc = NULL;
10404
49d6fa21 10405 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10406
d3a40d1b
ACO		 10407 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10408 0, 0);
10409 if (ret)
10410 goto fail;
10411
568c634a 10412 ret = intel_set_mode(state);
2bfb4627
ACO		 10413 if (ret)
10414 goto fail;
d2dff872 10415
36206361
DV		 10416 if (old->release_fb) {
10417 drm_framebuffer_unregister_private(old->release_fb);
10418 drm_framebuffer_unreference(old->release_fb);
10419 }
d2dff872 10420
0622a53c 10421 return;
79e53945
JB		 10422 }
10423
c751ce4f 10424 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10425 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10426 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10427
10428 return;
10429fail:
10430 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10431 drm_atomic_state_free(state);
79e53945
JB		 10432}
10433
da4a1efa 10434static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10435 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10436{
10437 struct drm_i915_private *dev_priv = dev->dev_private;
10438 u32 dpll = pipe_config->dpll_hw_state.dpll;
10439
10440 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10441 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10442 else if (HAS_PCH_SPLIT(dev))
10443 return 120000;
10444 else if (!IS_GEN2(dev))
10445 return 96000;
10446 else
10447 return 48000;
10448}
10449
79e53945 10450/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10451static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10452 struct intel_crtc_state *pipe_config)
79e53945 10453{
f1f644dc 10454 struct drm_device *dev = crtc->base.dev;
79e53945 10455 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10456 int pipe = pipe_config->cpu_transcoder;
293623f7 10457 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10458 u32 fp;
10459 intel_clock_t clock;
da4a1efa 10460 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10461
10462 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10463 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10464 else
293623f7 10465 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10466
10467 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10468 if (IS_PINEVIEW(dev)) {
10469 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10470 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10471 } else {
10472 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10473 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10474 }
10475
a6c45cf0 10476 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10477 if (IS_PINEVIEW(dev))
10478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10479 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10480 else
10481 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10482 DPLL_FPA01_P1_POST_DIV_SHIFT);
10483
10484 switch (dpll & DPLL_MODE_MASK) {
10485 case DPLLB_MODE_DAC_SERIAL:
10486 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10487 5 : 10;
10488 break;
10489 case DPLLB_MODE_LVDS:
10490 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10491 7 : 14;
10492 break;
10493 default:
28c97730 10494 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10495 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10496 return;
79e53945
JB		 10497 }
10498
ac58c3f0 10499 if (IS_PINEVIEW(dev))
da4a1efa 10500 pineview_clock(refclk, &clock);
ac58c3f0 10501 else
da4a1efa 10502 i9xx_clock(refclk, &clock);
79e53945 10503 } else {
0fb58223 10504 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10505 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10506
10507 if (is_lvds) {
10508 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10509 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10510
10511 if (lvds & LVDS_CLKB_POWER_UP)
10512 clock.p2 = 7;
10513 else
10514 clock.p2 = 14;
79e53945
JB		 10515 } else {
10516 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10517 clock.p1 = 2;
10518 else {
10519 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10520 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10521 }
10522 if (dpll & PLL_P2_DIVIDE_BY_4)
10523 clock.p2 = 4;
10524 else
10525 clock.p2 = 2;
79e53945 10526 }
da4a1efa
VS		 10527
10528 i9xx_clock(refclk, &clock);
79e53945
JB		 10529 }
10530
18442d08
VS		 10531 /*
10532 * This value includes pixel_multiplier. We will use
241bfc38 10533 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10534 * encoder's get_config() function.
10535 */
10536 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10537}
10538
6878da05
VS		 10539int intel_dotclock_calculate(int link_freq,
10540 const struct intel_link_m_n *m_n)
f1f644dc 10541{
f1f644dc
JB		 10542 /*
10543 * The calculation for the data clock is:
1041a02f 10544 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10545 * But we want to avoid losing precison if possible, so:
1041a02f 10546 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10547 *
10548 * and the link clock is simpler:
1041a02f 10549 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10550 */
10551
6878da05
VS		 10552 if (!m_n->link_n)
10553 return 0;
f1f644dc 10554
6878da05
VS		 10555 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10556}
f1f644dc 10557
18442d08 10558static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10559 struct intel_crtc_state *pipe_config)
6878da05
VS		 10560{
10561 struct drm_device *dev = crtc->base.dev;
79e53945 10562
18442d08
VS		 10563 /* read out port_clock from the DPLL */
10564 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10565
f1f644dc 10566 /*
18442d08 10567 * This value does not include pixel_multiplier.
241bfc38 10568 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10569 * agree once we know their relationship in the encoder's
10570 * get_config() function.
79e53945 10571 */
2d112de7 10572 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10573 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10574 &pipe_config->fdi_m_n);
79e53945
JB		 10575}
10576
10577/** Returns the currently programmed mode of the given pipe. */
10578struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10579 struct drm_crtc *crtc)
10580{
548f245b 10581 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10583 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10584 struct drm_display_mode *mode;
5cec258b 10585 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10586 int htot = I915_READ(HTOTAL(cpu_transcoder));
10587 int hsync = I915_READ(HSYNC(cpu_transcoder));
10588 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10589 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10590 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10591
10592 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10593 if (!mode)
10594 return NULL;
10595
f1f644dc
JB		 10596 /*
10597 * Construct a pipe_config sufficient for getting the clock info
10598 * back out of crtc_clock_get.
10599 *
10600 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10601 * to use a real value here instead.
10602 */
293623f7 10603 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10604 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10605 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10606 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10607 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10608 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10609
773ae034 10610 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10611 mode->hdisplay = (htot & 0xffff) + 1;
10612 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10613 mode->hsync_start = (hsync & 0xffff) + 1;
10614 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10615 mode->vdisplay = (vtot & 0xffff) + 1;
10616 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10617 mode->vsync_start = (vsync & 0xffff) + 1;
10618 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10619
10620 drm_mode_set_name(mode);
79e53945
JB		 10621
10622 return mode;
10623}
10624
f047e395
CW		 10625void intel_mark_busy(struct drm_device *dev)
10626{
c67a470b
PZ		 10627 struct drm_i915_private *dev_priv = dev->dev_private;
10628
f62a0076
CW		 10629 if (dev_priv->mm.busy)
10630 return;
10631
43694d69 10632 intel_runtime_pm_get(dev_priv);
c67a470b 10633 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10634 if (INTEL_INFO(dev)->gen >= 6)
10635 gen6_rps_busy(dev_priv);
f62a0076 10636 dev_priv->mm.busy = true;
f047e395
CW		 10637}
10638
10639void intel_mark_idle(struct drm_device *dev)
652c393a 10640{
c67a470b 10641 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10642
f62a0076
CW		 10643 if (!dev_priv->mm.busy)
10644 return;
10645
10646 dev_priv->mm.busy = false;
10647
3d13ef2e 10648 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10649 gen6_rps_idle(dev->dev_private);
bb4cdd53 10650
43694d69 10651 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10652}
10653
79e53945
JB		 10654static void intel_crtc_destroy(struct drm_crtc *crtc)
10655{
10656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10657 struct drm_device *dev = crtc->dev;
10658 struct intel_unpin_work *work;
67e77c5a 10659
5e2d7afc 10660 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10661 work = intel_crtc->unpin_work;
10662 intel_crtc->unpin_work = NULL;
5e2d7afc 10663 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10664
10665 if (work) {
10666 cancel_work_sync(&work->work);
10667 kfree(work);
10668 }
79e53945
JB		 10669
10670 drm_crtc_cleanup(crtc);
67e77c5a 10671
79e53945
JB		 10672 kfree(intel_crtc);
10673}
10674
6b95a207
KH		 10675static void intel_unpin_work_fn(struct work_struct *__work)
10676{
10677 struct intel_unpin_work *work =
10678 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10679 struct drm_device *dev = work->crtc->dev;
f99d7069 10680 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10681
b4a98e57 10682 mutex_lock(&dev->struct_mutex);
82bc3b2d 10683 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10684 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10685
7ff0ebcc 10686 intel_fbc_update(dev);
f06cc1b9
JH		 10687
10688 if (work->flip_queued_req)
146d84f0 10689 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10690 mutex_unlock(&dev->struct_mutex);
10691
f99d7069 10692 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10693 drm_framebuffer_unreference(work->old_fb);
f99d7069 10694
b4a98e57
CW		 10695 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10696 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10697
6b95a207
KH		 10698 kfree(work);
10699}
10700
1afe3e9d 10701static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10702 struct drm_crtc *crtc)
6b95a207 10703{
6b95a207
KH		 10704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10705 struct intel_unpin_work *work;
6b95a207
KH		 10706 unsigned long flags;
10707
10708 /* Ignore early vblank irqs */
10709 if (intel_crtc == NULL)
10710 return;
10711
f326038a
DV		 10712 /*
10713 * This is called both by irq handlers and the reset code (to complete
10714 * lost pageflips) so needs the full irqsave spinlocks.
10715 */
6b95a207
KH		 10716 spin_lock_irqsave(&dev->event_lock, flags);
10717 work = intel_crtc->unpin_work;
e7d841ca
CW		 10718
10719 /* Ensure we don't miss a work->pending update ... */
10720 smp_rmb();
10721
10722 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10723 spin_unlock_irqrestore(&dev->event_lock, flags);
10724 return;
10725 }
10726
d6bbafa1 10727 page_flip_completed(intel_crtc);
0af7e4df 10728
6b95a207 10729 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10730}
10731
1afe3e9d
JB		 10732void intel_finish_page_flip(struct drm_device *dev, int pipe)
10733{
fbee40df 10734 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10736
49b14a5c 10737 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10738}
10739
10740void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10741{
fbee40df 10742 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10743 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10744
49b14a5c 10745 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10746}
10747
75f7f3ec
VS		 10748/* Is 'a' after or equal to 'b'? */
10749static bool g4x_flip_count_after_eq(u32 a, u32 b)
10750{
10751 return !((a - b) & 0x80000000);
10752}
10753
10754static bool page_flip_finished(struct intel_crtc *crtc)
10755{
10756 struct drm_device *dev = crtc->base.dev;
10757 struct drm_i915_private *dev_priv = dev->dev_private;
10758
bdfa7542
VS		 10759 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10760 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10761 return true;
10762
75f7f3ec
VS		 10763 /*
10764 * The relevant registers doen't exist on pre-ctg.
10765 * As the flip done interrupt doesn't trigger for mmio
10766 * flips on gmch platforms, a flip count check isn't
10767 * really needed there. But since ctg has the registers,
10768 * include it in the check anyway.
10769 */
10770 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10771 return true;
10772
10773 /*
10774 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10775 * used the same base address. In that case the mmio flip might
10776 * have completed, but the CS hasn't even executed the flip yet.
10777 *
10778 * A flip count check isn't enough as the CS might have updated
10779 * the base address just after start of vblank, but before we
10780 * managed to process the interrupt. This means we'd complete the
10781 * CS flip too soon.
10782 *
10783 * Combining both checks should get us a good enough result. It may
10784 * still happen that the CS flip has been executed, but has not
10785 * yet actually completed. But in case the base address is the same
10786 * anyway, we don't really care.
10787 */
10788 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10789 crtc->unpin_work->gtt_offset &&
10790 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10791 crtc->unpin_work->flip_count);
10792}
10793
6b95a207
KH		 10794void intel_prepare_page_flip(struct drm_device *dev, int plane)
10795{
fbee40df 10796 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10797 struct intel_crtc *intel_crtc =
10798 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10799 unsigned long flags;
10800
f326038a
DV		 10801
10802 /*
10803 * This is called both by irq handlers and the reset code (to complete
10804 * lost pageflips) so needs the full irqsave spinlocks.
10805 *
10806 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10807 * generate a page-flip completion irq, i.e. every modeset
10808 * is also accompanied by a spurious intel_prepare_page_flip().
10809 */
6b95a207 10810 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10811 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10812 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10813 spin_unlock_irqrestore(&dev->event_lock, flags);
10814}
10815
eba905b2 10816static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10817{
10818 /* Ensure that the work item is consistent when activating it ... */
10819 smp_wmb();
10820 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10821 /* and that it is marked active as soon as the irq could fire. */
10822 smp_wmb();
10823}
10824
8c9f3aaf
JB		 10825static int intel_gen2_queue_flip(struct drm_device *dev,
10826 struct drm_crtc *crtc,
10827 struct drm_framebuffer *fb,
ed8d1975 10828 struct drm_i915_gem_object *obj,
6258fbe2 10829 struct drm_i915_gem_request *req,
ed8d1975 10830 uint32_t flags)
8c9f3aaf 10831{
6258fbe2 10832 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10834 u32 flip_mask;
10835 int ret;
10836
5fb9de1a 10837 ret = intel_ring_begin(req, 6);
8c9f3aaf 10838 if (ret)
4fa62c89 10839 return ret;
8c9f3aaf
JB		 10840
10841 /* Can't queue multiple flips, so wait for the previous
10842 * one to finish before executing the next.
10843 */
10844 if (intel_crtc->plane)
10845 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10846 else
10847 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10848 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10849 intel_ring_emit(ring, MI_NOOP);
10850 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10851 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10852 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10853 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10854 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10855
10856 intel_mark_page_flip_active(intel_crtc);
83d4092b 10857 return 0;
8c9f3aaf
JB		 10858}
10859
10860static int intel_gen3_queue_flip(struct drm_device *dev,
10861 struct drm_crtc *crtc,
10862 struct drm_framebuffer *fb,
ed8d1975 10863 struct drm_i915_gem_object *obj,
6258fbe2 10864 struct drm_i915_gem_request *req,
ed8d1975 10865 uint32_t flags)
8c9f3aaf 10866{
6258fbe2 10867 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10869 u32 flip_mask;
10870 int ret;
10871
5fb9de1a 10872 ret = intel_ring_begin(req, 6);
8c9f3aaf 10873 if (ret)
4fa62c89 10874 return ret;
8c9f3aaf
JB		 10875
10876 if (intel_crtc->plane)
10877 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10878 else
10879 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10880 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10881 intel_ring_emit(ring, MI_NOOP);
10882 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10883 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10884 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10885 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10886 intel_ring_emit(ring, MI_NOOP);
10887
e7d841ca 10888 intel_mark_page_flip_active(intel_crtc);
83d4092b 10889 return 0;
8c9f3aaf
JB		 10890}
10891
10892static int intel_gen4_queue_flip(struct drm_device *dev,
10893 struct drm_crtc *crtc,
10894 struct drm_framebuffer *fb,
ed8d1975 10895 struct drm_i915_gem_object *obj,
6258fbe2 10896 struct drm_i915_gem_request *req,
ed8d1975 10897 uint32_t flags)
8c9f3aaf 10898{
6258fbe2 10899 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10900 struct drm_i915_private *dev_priv = dev->dev_private;
10901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10902 uint32_t pf, pipesrc;
10903 int ret;
10904
5fb9de1a 10905 ret = intel_ring_begin(req, 4);
8c9f3aaf 10906 if (ret)
4fa62c89 10907 return ret;
8c9f3aaf
JB		 10908
10909 /* i965+ uses the linear or tiled offsets from the
10910 * Display Registers (which do not change across a page-flip)
10911 * so we need only reprogram the base address.
10912 */
6d90c952
DV		 10913 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10914 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10915 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10916 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10917 obj->tiling_mode);
8c9f3aaf
JB		 10918
10919 /* XXX Enabling the panel-fitter across page-flip is so far
10920 * untested on non-native modes, so ignore it for now.
10921 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10922 */
10923 pf = 0;
10924 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10925 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10926
10927 intel_mark_page_flip_active(intel_crtc);
83d4092b 10928 return 0;
8c9f3aaf
JB		 10929}
10930
10931static int intel_gen6_queue_flip(struct drm_device *dev,
10932 struct drm_crtc *crtc,
10933 struct drm_framebuffer *fb,
ed8d1975 10934 struct drm_i915_gem_object *obj,
6258fbe2 10935 struct drm_i915_gem_request *req,
ed8d1975 10936 uint32_t flags)
8c9f3aaf 10937{
6258fbe2 10938 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10939 struct drm_i915_private *dev_priv = dev->dev_private;
10940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10941 uint32_t pf, pipesrc;
10942 int ret;
10943
5fb9de1a 10944 ret = intel_ring_begin(req, 4);
8c9f3aaf 10945 if (ret)
4fa62c89 10946 return ret;
8c9f3aaf 10947
6d90c952
DV		 10948 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10949 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10950 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10951 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10952
dc257cf1
DV		 10953 /* Contrary to the suggestions in the documentation,
10954 * "Enable Panel Fitter" does not seem to be required when page
10955 * flipping with a non-native mode, and worse causes a normal
10956 * modeset to fail.
10957 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10958 */
10959 pf = 0;
8c9f3aaf 10960 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10961 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10962
10963 intel_mark_page_flip_active(intel_crtc);
83d4092b 10964 return 0;
8c9f3aaf
JB		 10965}
10966
7c9017e5
JB		 10967static int intel_gen7_queue_flip(struct drm_device *dev,
10968 struct drm_crtc *crtc,
10969 struct drm_framebuffer *fb,
ed8d1975 10970 struct drm_i915_gem_object *obj,
6258fbe2 10971 struct drm_i915_gem_request *req,
ed8d1975 10972 uint32_t flags)
7c9017e5 10973{
6258fbe2 10974 struct intel_engine_cs *ring = req->ring;
7c9017e5 10975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10976 uint32_t plane_bit = 0;
ffe74d75
CW		 10977 int len, ret;
10978
eba905b2 10979 switch (intel_crtc->plane) {
cb05d8de
DV		 10980 case PLANE_A:
10981 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10982 break;
10983 case PLANE_B:
10984 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10985 break;
10986 case PLANE_C:
10987 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10988 break;
10989 default:
10990 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10991 return -ENODEV;
cb05d8de
DV		 10992 }
10993
ffe74d75 10994 len = 4;
f476828a 10995 if (ring->id == RCS) {
ffe74d75 10996 len += 6;
f476828a
DL		 10997 /*
10998 * On Gen 8, SRM is now taking an extra dword to accommodate
10999 * 48bits addresses, and we need a NOOP for the batch size to
11000 * stay even.
11001 */
11002 if (IS_GEN8(dev))
11003 len += 2;
11004 }
ffe74d75 11005
f66fab8e
VS		 11006 /*
11007 * BSpec MI_DISPLAY_FLIP for IVB:
11008 * "The full packet must be contained within the same cache line."
11009 *
11010 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11011 * cacheline, if we ever start emitting more commands before
11012 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11013 * then do the cacheline alignment, and finally emit the
11014 * MI_DISPLAY_FLIP.
11015 */
bba09b12 11016 ret = intel_ring_cacheline_align(req);
f66fab8e 11017 if (ret)
4fa62c89 11018 return ret;
f66fab8e 11019
5fb9de1a 11020 ret = intel_ring_begin(req, len);
7c9017e5 11021 if (ret)
4fa62c89 11022 return ret;
7c9017e5 11023
ffe74d75
CW		 11024 /* Unmask the flip-done completion message. Note that the bspec says that
11025 * we should do this for both the BCS and RCS, and that we must not unmask
11026 * more than one flip event at any time (or ensure that one flip message
11027 * can be sent by waiting for flip-done prior to queueing new flips).
11028 * Experimentation says that BCS works despite DERRMR masking all
11029 * flip-done completion events and that unmasking all planes at once
11030 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11031 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11032 */
11033 if (ring->id == RCS) {
11034 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11035 intel_ring_emit(ring, DERRMR);
11036 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11037 DERRMR_PIPEB_PRI_FLIP_DONE |
11038 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11039 if (IS_GEN8(dev))
11040 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11041 MI_SRM_LRM_GLOBAL_GTT);
11042 else
11043 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11044 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11045 intel_ring_emit(ring, DERRMR);
11046 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11047 if (IS_GEN8(dev)) {
11048 intel_ring_emit(ring, 0);
11049 intel_ring_emit(ring, MI_NOOP);
11050 }
ffe74d75
CW		 11051 }
11052
cb05d8de 11053 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11054 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11055 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11056 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11057
11058 intel_mark_page_flip_active(intel_crtc);
83d4092b 11059 return 0;
7c9017e5
JB		 11060}
11061
84c33a64
SG		 11062static bool use_mmio_flip(struct intel_engine_cs *ring,
11063 struct drm_i915_gem_object *obj)
11064{
11065 /*
11066 * This is not being used for older platforms, because
11067 * non-availability of flip done interrupt forces us to use
11068 * CS flips. Older platforms derive flip done using some clever
11069 * tricks involving the flip_pending status bits and vblank irqs.
11070 * So using MMIO flips there would disrupt this mechanism.
11071 */
11072
8e09bf83
CW		 11073 if (ring == NULL)
11074 return true;
11075
84c33a64
SG		 11076 if (INTEL_INFO(ring->dev)->gen < 5)
11077 return false;
11078
11079 if (i915.use_mmio_flip < 0)
11080 return false;
11081 else if (i915.use_mmio_flip > 0)
11082 return true;
14bf993e
OM		 11083 else if (i915.enable_execlists)
11084 return true;
84c33a64 11085 else
b4716185 11086 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11087}
11088
ff944564
DL		 11089static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11090{
11091 struct drm_device *dev = intel_crtc->base.dev;
11092 struct drm_i915_private *dev_priv = dev->dev_private;
11093 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11094 const enum pipe pipe = intel_crtc->pipe;
11095 u32 ctl, stride;
11096
11097 ctl = I915_READ(PLANE_CTL(pipe, 0));
11098 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11099 switch (fb->modifier[0]) {
11100 case DRM_FORMAT_MOD_NONE:
11101 break;
11102 case I915_FORMAT_MOD_X_TILED:
ff944564 11103 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11104 break;
11105 case I915_FORMAT_MOD_Y_TILED:
11106 ctl |= PLANE_CTL_TILED_Y;
11107 break;
11108 case I915_FORMAT_MOD_Yf_TILED:
11109 ctl |= PLANE_CTL_TILED_YF;
11110 break;
11111 default:
11112 MISSING_CASE(fb->modifier[0]);
11113 }
ff944564
DL		 11114
11115 /*
11116 * The stride is either expressed as a multiple of 64 bytes chunks for
11117 * linear buffers or in number of tiles for tiled buffers.
11118 */
2ebef630
TU		 11119 stride = fb->pitches[0] /
11120 intel_fb_stride_alignment(dev, fb->modifier[0],
11121 fb->pixel_format);
ff944564
DL		 11122
11123 /*
11124 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11125 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11126 */
11127 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11128 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11129
11130 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11131 POSTING_READ(PLANE_SURF(pipe, 0));
11132}
11133
11134static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11135{
11136 struct drm_device *dev = intel_crtc->base.dev;
11137 struct drm_i915_private *dev_priv = dev->dev_private;
11138 struct intel_framebuffer *intel_fb =
11139 to_intel_framebuffer(intel_crtc->base.primary->fb);
11140 struct drm_i915_gem_object *obj = intel_fb->obj;
11141 u32 dspcntr;
11142 u32 reg;
11143
84c33a64
SG		 11144 reg = DSPCNTR(intel_crtc->plane);
11145 dspcntr = I915_READ(reg);
11146
c5d97472
DL		 11147 if (obj->tiling_mode != I915_TILING_NONE)
11148 dspcntr |= DISPPLANE_TILED;
11149 else
11150 dspcntr &= ~DISPPLANE_TILED;
11151
84c33a64
SG		 11152 I915_WRITE(reg, dspcntr);
11153
11154 I915_WRITE(DSPSURF(intel_crtc->plane),
11155 intel_crtc->unpin_work->gtt_offset);
11156 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11157
ff944564
DL		 11158}
11159
11160/*
11161 * XXX: This is the temporary way to update the plane registers until we get
11162 * around to using the usual plane update functions for MMIO flips
11163 */
11164static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11165{
11166 struct drm_device *dev = intel_crtc->base.dev;
11167 bool atomic_update;
11168 u32 start_vbl_count;
11169
11170 intel_mark_page_flip_active(intel_crtc);
11171
11172 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11173
11174 if (INTEL_INFO(dev)->gen >= 9)
11175 skl_do_mmio_flip(intel_crtc);
11176 else
11177 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11178 ilk_do_mmio_flip(intel_crtc);
11179
9362c7c5
ACO		 11180 if (atomic_update)
11181 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11182}
11183
9362c7c5 11184static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11185{
b2cfe0ab
CW		 11186 struct intel_mmio_flip *mmio_flip =
11187 container_of(work, struct intel_mmio_flip, work);
84c33a64 11188
eed29a5b
DV		 11189 if (mmio_flip->req)
11190 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11191 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11192 false, NULL,
11193 &mmio_flip->i915->rps.mmioflips));
84c33a64 11194
b2cfe0ab
CW		 11195 intel_do_mmio_flip(mmio_flip->crtc);
11196
eed29a5b 11197 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11198 kfree(mmio_flip);
84c33a64
SG		 11199}
11200
11201static int intel_queue_mmio_flip(struct drm_device *dev,
11202 struct drm_crtc *crtc,
11203 struct drm_framebuffer *fb,
11204 struct drm_i915_gem_object *obj,
11205 struct intel_engine_cs *ring,
11206 uint32_t flags)
11207{
b2cfe0ab
CW		 11208 struct intel_mmio_flip *mmio_flip;
11209
11210 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11211 if (mmio_flip == NULL)
11212 return -ENOMEM;
84c33a64 11213
bcafc4e3 11214 mmio_flip->i915 = to_i915(dev);
eed29a5b 11215 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11216 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11217
b2cfe0ab
CW		 11218 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11219 schedule_work(&mmio_flip->work);
84c33a64 11220
84c33a64
SG		 11221 return 0;
11222}
11223
8c9f3aaf
JB		 11224static int intel_default_queue_flip(struct drm_device *dev,
11225 struct drm_crtc *crtc,
11226 struct drm_framebuffer *fb,
ed8d1975 11227 struct drm_i915_gem_object *obj,
6258fbe2 11228 struct drm_i915_gem_request *req,
ed8d1975 11229 uint32_t flags)
8c9f3aaf
JB		 11230{
11231 return -ENODEV;
11232}
11233
d6bbafa1
CW		 11234static bool __intel_pageflip_stall_check(struct drm_device *dev,
11235 struct drm_crtc *crtc)
11236{
11237 struct drm_i915_private *dev_priv = dev->dev_private;
11238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11239 struct intel_unpin_work *work = intel_crtc->unpin_work;
11240 u32 addr;
11241
11242 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11243 return true;
11244
11245 if (!work->enable_stall_check)
11246 return false;
11247
11248 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11249 if (work->flip_queued_req &&
11250 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11251 return false;
11252
1e3feefd 11253 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11254 }
11255
1e3feefd 11256 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11257 return false;
11258
11259 /* Potential stall - if we see that the flip has happened,
11260 * assume a missed interrupt. */
11261 if (INTEL_INFO(dev)->gen >= 4)
11262 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11263 else
11264 addr = I915_READ(DSPADDR(intel_crtc->plane));
11265
11266 /* There is a potential issue here with a false positive after a flip
11267 * to the same address. We could address this by checking for a
11268 * non-incrementing frame counter.
11269 */
11270 return addr == work->gtt_offset;
11271}
11272
11273void intel_check_page_flip(struct drm_device *dev, int pipe)
11274{
11275 struct drm_i915_private *dev_priv = dev->dev_private;
11276 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11278 struct intel_unpin_work *work;
f326038a 11279
6c51d46f 11280 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11281
11282 if (crtc == NULL)
11283 return;
11284
f326038a 11285 spin_lock(&dev->event_lock);
6ad790c0
CW		 11286 work = intel_crtc->unpin_work;
11287 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11288 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11289 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11290 page_flip_completed(intel_crtc);
6ad790c0 11291 work = NULL;
d6bbafa1 11292 }
6ad790c0
CW		 11293 if (work != NULL &&
11294 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11295 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11296 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11297}
11298
6b95a207
KH		 11299static int intel_crtc_page_flip(struct drm_crtc *crtc,
11300 struct drm_framebuffer *fb,
ed8d1975
KP		 11301 struct drm_pending_vblank_event *event,
11302 uint32_t page_flip_flags)
6b95a207
KH		 11303{
11304 struct drm_device *dev = crtc->dev;
11305 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11306 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11307 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11309 struct drm_plane *primary = crtc->primary;
a071fa00 11310 enum pipe pipe = intel_crtc->pipe;
6b95a207 11311 struct intel_unpin_work *work;
a4872ba6 11312 struct intel_engine_cs *ring;
cf5d8a46 11313 bool mmio_flip;
91af127f 11314 struct drm_i915_gem_request *request = NULL;
52e68630 11315 int ret;
6b95a207 11316
2ff8fde1
MR		 11317 /*
11318 * drm_mode_page_flip_ioctl() should already catch this, but double
11319 * check to be safe. In the future we may enable pageflipping from
11320 * a disabled primary plane.
11321 */
11322 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11323 return -EBUSY;
11324
e6a595d2 11325 /* Can't change pixel format via MI display flips. */
f4510a27 11326 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11327 return -EINVAL;
11328
11329 /*
11330 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11331 * Note that pitch changes could also affect these register.
11332 */
11333 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11334 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11335 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11336 return -EINVAL;
11337
f900db47
CW		 11338 if (i915_terminally_wedged(&dev_priv->gpu_error))
11339 goto out_hang;
11340
b14c5679 11341 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11342 if (work == NULL)
11343 return -ENOMEM;
11344
6b95a207 11345 work->event = event;
b4a98e57 11346 work->crtc = crtc;
ab8d6675 11347 work->old_fb = old_fb;
6b95a207
KH		 11348 INIT_WORK(&work->work, intel_unpin_work_fn);
11349
87b6b101 11350 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11351 if (ret)
11352 goto free_work;
11353
6b95a207 11354 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11355 spin_lock_irq(&dev->event_lock);
6b95a207 11356 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11357 /* Before declaring the flip queue wedged, check if
11358 * the hardware completed the operation behind our backs.
11359 */
11360 if (__intel_pageflip_stall_check(dev, crtc)) {
11361 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11362 page_flip_completed(intel_crtc);
11363 } else {
11364 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11365 spin_unlock_irq(&dev->event_lock);
468f0b44 11366
d6bbafa1
CW		 11367 drm_crtc_vblank_put(crtc);
11368 kfree(work);
11369 return -EBUSY;
11370 }
6b95a207
KH		 11371 }
11372 intel_crtc->unpin_work = work;
5e2d7afc 11373 spin_unlock_irq(&dev->event_lock);
6b95a207 11374
b4a98e57
CW		 11375 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11376 flush_workqueue(dev_priv->wq);
11377
75dfca80 11378 /* Reference the objects for the scheduled work. */
ab8d6675 11379 drm_framebuffer_reference(work->old_fb);
05394f39 11380 drm_gem_object_reference(&obj->base);
6b95a207 11381
f4510a27 11382 crtc->primary->fb = fb;
afd65eb4 11383 update_state_fb(crtc->primary);
1ed1f968 11384
e1f99ce6 11385 work->pending_flip_obj = obj;
e1f99ce6 11386
89ed88ba
CW		 11387 ret = i915_mutex_lock_interruptible(dev);
11388 if (ret)
11389 goto cleanup;
11390
b4a98e57 11391 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11392 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11393
75f7f3ec 11394 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11395 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11396
4fa62c89
VS		 11397 if (IS_VALLEYVIEW(dev)) {
11398 ring = &dev_priv->ring[BCS];
ab8d6675 11399 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11400 /* vlv: DISPLAY_FLIP fails to change tiling */
11401 ring = NULL;
48bf5b2d 11402 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11403 ring = &dev_priv->ring[BCS];
4fa62c89 11404 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11405 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11406 if (ring == NULL || ring->id != RCS)
11407 ring = &dev_priv->ring[BCS];
11408 } else {
11409 ring = &dev_priv->ring[RCS];
11410 }
11411
cf5d8a46
CW		 11412 mmio_flip = use_mmio_flip(ring, obj);
11413
11414 /* When using CS flips, we want to emit semaphores between rings.
11415 * However, when using mmio flips we will create a task to do the
11416 * synchronisation, so all we want here is to pin the framebuffer
11417 * into the display plane and skip any waits.
11418 */
82bc3b2d 11419 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11420 crtc->primary->state,
91af127f 11421 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11422 if (ret)
11423 goto cleanup_pending;
6b95a207 11424
121920fa
TU		 11425 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11426 + intel_crtc->dspaddr_offset;
4fa62c89 11427
cf5d8a46 11428 if (mmio_flip) {
84c33a64
SG		 11429 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11430 page_flip_flags);
d6bbafa1
CW		 11431 if (ret)
11432 goto cleanup_unpin;
11433
f06cc1b9
JH		 11434 i915_gem_request_assign(&work->flip_queued_req,
11435 obj->last_write_req);
d6bbafa1 11436 } else {
6258fbe2
JH		 11437 if (!request) {
11438 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11439 if (ret)
11440 goto cleanup_unpin;
11441 }
11442
11443 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11444 page_flip_flags);
11445 if (ret)
11446 goto cleanup_unpin;
11447
6258fbe2 11448 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11449 }
11450
91af127f 11451 if (request)
75289874 11452 i915_add_request_no_flush(request);
91af127f 11453
1e3feefd 11454 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11455 work->enable_stall_check = true;
4fa62c89 11456
ab8d6675 11457 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11458 INTEL_FRONTBUFFER_PRIMARY(pipe));
11459
7ff0ebcc 11460 intel_fbc_disable(dev);
f99d7069 11461 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11462 mutex_unlock(&dev->struct_mutex);
11463
e5510fac
JB		 11464 trace_i915_flip_request(intel_crtc->plane, obj);
11465
6b95a207 11466 return 0;
96b099fd 11467
4fa62c89 11468cleanup_unpin:
82bc3b2d 11469 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11470cleanup_pending:
91af127f
JH		 11471 if (request)
11472 i915_gem_request_cancel(request);
b4a98e57 11473 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11474 mutex_unlock(&dev->struct_mutex);
11475cleanup:
f4510a27 11476 crtc->primary->fb = old_fb;
afd65eb4 11477 update_state_fb(crtc->primary);
89ed88ba
CW		 11478
11479 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11480 drm_framebuffer_unreference(work->old_fb);
96b099fd 11481
5e2d7afc 11482 spin_lock_irq(&dev->event_lock);
96b099fd 11483 intel_crtc->unpin_work = NULL;
5e2d7afc 11484 spin_unlock_irq(&dev->event_lock);
96b099fd 11485
87b6b101 11486 drm_crtc_vblank_put(crtc);
7317c75e 11487free_work:
96b099fd
CW		 11488 kfree(work);
11489
f900db47 11490 if (ret == -EIO) {
02e0efb5
ML		 11491 struct drm_atomic_state *state;
11492 struct drm_plane_state *plane_state;
11493
f900db47 11494out_hang:
02e0efb5
ML		 11495 state = drm_atomic_state_alloc(dev);
11496 if (!state)
11497 return -ENOMEM;
11498 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11499
11500retry:
11501 plane_state = drm_atomic_get_plane_state(state, primary);
11502 ret = PTR_ERR_OR_ZERO(plane_state);
11503 if (!ret) {
11504 drm_atomic_set_fb_for_plane(plane_state, fb);
11505
11506 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11507 if (!ret)
11508 ret = drm_atomic_commit(state);
11509 }
11510
11511 if (ret == -EDEADLK) {
11512 drm_modeset_backoff(state->acquire_ctx);
11513 drm_atomic_state_clear(state);
11514 goto retry;
11515 }
11516
11517 if (ret)
11518 drm_atomic_state_free(state);
11519
f0d3dad3 11520 if (ret == 0 && event) {
5e2d7afc 11521 spin_lock_irq(&dev->event_lock);
a071fa00 11522 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11523 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11524 }
f900db47 11525 }
96b099fd 11526 return ret;
6b95a207
KH		 11527}
11528
da20eabd
ML		 11529
11530/**
11531 * intel_wm_need_update - Check whether watermarks need updating
11532 * @plane: drm plane
11533 * @state: new plane state
11534 *
11535 * Check current plane state versus the new one to determine whether
11536 * watermarks need to be recalculated.
11537 *
11538 * Returns true or false.
11539 */
11540static bool intel_wm_need_update(struct drm_plane *plane,
11541 struct drm_plane_state *state)
11542{
11543 /* Update watermarks on tiling changes. */
11544 if (!plane->state->fb || !state->fb ||
11545 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11546 plane->state->rotation != state->rotation)
11547 return true;
11548
11549 if (plane->state->crtc_w != state->crtc_w)
11550 return true;
11551
11552 return false;
11553}
11554
11555int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11556 struct drm_plane_state *plane_state)
11557{
11558 struct drm_crtc *crtc = crtc_state->crtc;
11559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11560 struct drm_plane *plane = plane_state->plane;
11561 struct drm_device *dev = crtc->dev;
11562 struct drm_i915_private *dev_priv = dev->dev_private;
11563 struct intel_plane_state *old_plane_state =
11564 to_intel_plane_state(plane->state);
11565 int idx = intel_crtc->base.base.id, ret;
11566 int i = drm_plane_index(plane);
11567 bool mode_changed = needs_modeset(crtc_state);
11568 bool was_crtc_enabled = crtc->state->active;
11569 bool is_crtc_enabled = crtc_state->active;
11570
11571 bool turn_off, turn_on, visible, was_visible;
11572 struct drm_framebuffer *fb = plane_state->fb;
11573
11574 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11575 plane->type != DRM_PLANE_TYPE_CURSOR) {
11576 ret = skl_update_scaler_plane(
11577 to_intel_crtc_state(crtc_state),
11578 to_intel_plane_state(plane_state));
11579 if (ret)
11580 return ret;
11581 }
11582
11583 /*
11584 * Disabling a plane is always okay; we just need to update
11585 * fb tracking in a special way since cleanup_fb() won't
11586 * get called by the plane helpers.
11587 */
11588 if (old_plane_state->base.fb && !fb)
11589 intel_crtc->atomic.disabled_planes |= 1 << i;
11590
da20eabd
ML		 11591 was_visible = old_plane_state->visible;
11592 visible = to_intel_plane_state(plane_state)->visible;
11593
11594 if (!was_crtc_enabled && WARN_ON(was_visible))
11595 was_visible = false;
11596
11597 if (!is_crtc_enabled && WARN_ON(visible))
11598 visible = false;
11599
11600 if (!was_visible && !visible)
11601 return 0;
11602
11603 turn_off = was_visible && (!visible || mode_changed);
11604 turn_on = visible && (!was_visible || mode_changed);
11605
11606 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11607 plane->base.id, fb ? fb->base.id : -1);
11608
11609 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11610 plane->base.id, was_visible, visible,
11611 turn_off, turn_on, mode_changed);
11612
11613 if (intel_wm_need_update(plane, plane_state))
11614 intel_crtc->atomic.update_wm = true;
11615
11616 switch (plane->type) {
11617 case DRM_PLANE_TYPE_PRIMARY:
11618 if (visible)
11619 intel_crtc->atomic.fb_bits |=
11620 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11621
11622 intel_crtc->atomic.wait_for_flips = true;
11623 intel_crtc->atomic.pre_disable_primary = turn_off;
11624 intel_crtc->atomic.post_enable_primary = turn_on;
11625
11626 if (turn_off)
11627 intel_crtc->atomic.disable_fbc = true;
11628
11629 /*
11630 * FBC does not work on some platforms for rotated
11631 * planes, so disable it when rotation is not 0 and
11632 * update it when rotation is set back to 0.
11633 *
11634 * FIXME: This is redundant with the fbc update done in
11635 * the primary plane enable function except that that
11636 * one is done too late. We eventually need to unify
11637 * this.
11638 */
11639
11640 if (visible &&
11641 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11642 dev_priv->fbc.crtc == intel_crtc &&
11643 plane_state->rotation != BIT(DRM_ROTATE_0))
11644 intel_crtc->atomic.disable_fbc = true;
11645
11646 /*
11647 * BDW signals flip done immediately if the plane
11648 * is disabled, even if the plane enable is already
11649 * armed to occur at the next vblank :(
11650 */
11651 if (turn_on && IS_BROADWELL(dev))
11652 intel_crtc->atomic.wait_vblank = true;
11653
11654 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11655 break;
11656 case DRM_PLANE_TYPE_CURSOR:
11657 if (visible)
11658 intel_crtc->atomic.fb_bits |=
11659 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
11660 break;
11661 case DRM_PLANE_TYPE_OVERLAY:
11662 /*
11663 * 'prepare' is never called when plane is being disabled, so
11664 * we need to handle frontbuffer tracking as a special case
11665 */
11666 if (visible)
11667 intel_crtc->atomic.fb_bits |=
11668 INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe);
11669
d032ffa0 11670 if (turn_off && !mode_changed) {
da20eabd
ML		 11671 intel_crtc->atomic.wait_vblank = true;
11672 intel_crtc->atomic.update_sprite_watermarks |=
11673 1 << i;
11674 }
11675 break;
11676 }
11677 return 0;
11678}
11679
6d3a1ce7
ML		 11680static bool encoders_cloneable(const struct intel_encoder *a,
11681 const struct intel_encoder *b)
11682{
11683 /* masks could be asymmetric, so check both ways */
11684 return a == b || (a->cloneable & (1 << b->type) &&
11685 b->cloneable & (1 << a->type));
11686}
11687
11688static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11689 struct intel_crtc *crtc,
11690 struct intel_encoder *encoder)
11691{
11692 struct intel_encoder *source_encoder;
11693 struct drm_connector *connector;
11694 struct drm_connector_state *connector_state;
11695 int i;
11696
11697 for_each_connector_in_state(state, connector, connector_state, i) {
11698 if (connector_state->crtc != &crtc->base)
11699 continue;
11700
11701 source_encoder =
11702 to_intel_encoder(connector_state->best_encoder);
11703 if (!encoders_cloneable(encoder, source_encoder))
11704 return false;
11705 }
11706
11707 return true;
11708}
11709
11710static bool check_encoder_cloning(struct drm_atomic_state *state,
11711 struct intel_crtc *crtc)
11712{
11713 struct intel_encoder *encoder;
11714 struct drm_connector *connector;
11715 struct drm_connector_state *connector_state;
11716 int i;
11717
11718 for_each_connector_in_state(state, connector, connector_state, i) {
11719 if (connector_state->crtc != &crtc->base)
11720 continue;
11721
11722 encoder = to_intel_encoder(connector_state->best_encoder);
11723 if (!check_single_encoder_cloning(state, crtc, encoder))
11724 return false;
11725 }
11726
11727 return true;
11728}
11729
d032ffa0
ML		 11730static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11731 struct drm_crtc_state *crtc_state)
11732{
11733 struct intel_crtc_state *pipe_config =
11734 to_intel_crtc_state(crtc_state);
11735 struct drm_plane *p;
11736 unsigned visible_mask = 0;
11737
11738 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11739 struct drm_plane_state *plane_state =
11740 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11741
11742 if (WARN_ON(!plane_state))
11743 continue;
11744
11745 if (!plane_state->fb)
11746 crtc_state->plane_mask &=
11747 ~(1 << drm_plane_index(p));
11748 else if (to_intel_plane_state(plane_state)->visible)
11749 visible_mask |= 1 << drm_plane_index(p);
11750 }
11751
11752 if (!visible_mask)
11753 return;
11754
11755 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11756}
11757
6d3a1ce7
ML		 11758static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11759 struct drm_crtc_state *crtc_state)
11760{
cf5a15be 11761 struct drm_device *dev = crtc->dev;
ad421372 11762 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11764 struct intel_crtc_state *pipe_config =
11765 to_intel_crtc_state(crtc_state);
6d3a1ce7 11766 struct drm_atomic_state *state = crtc_state->state;
ad421372 11767 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11768 bool mode_changed = needs_modeset(crtc_state);
11769
11770 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11771 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11772 return -EINVAL;
11773 }
11774
11775 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11776 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11777 idx, crtc->state->active, intel_crtc->active);
11778
d032ffa0
ML		 11779 /* plane mask is fixed up after all initial planes are calculated */
11780 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11781 intel_crtc_check_initial_planes(crtc, crtc_state);
11782
eddfcbcd
ML		 11783 if (mode_changed)
11784 intel_crtc->atomic.update_wm = !crtc_state->active;
11785
ad421372
ML		 11786 if (mode_changed && crtc_state->enable &&
11787 dev_priv->display.crtc_compute_clock &&
11788 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11789 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11790 pipe_config);
11791 if (ret)
11792 return ret;
11793 }
11794
cf5a15be 11795 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
6d3a1ce7
ML		 11796}
11797
65b38e0d 11798static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11799 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11800 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11801 .atomic_begin = intel_begin_crtc_commit,
11802 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11803 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11804};
11805
9a935856
DV		 11806/**
11807 * intel_modeset_update_staged_output_state
11808 *
11809 * Updates the staged output configuration state, e.g. after we've read out the
11810 * current hw state.
11811 */
11812static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11813{
7668851f 11814 struct intel_crtc *crtc;
9a935856
DV		 11815 struct intel_encoder *encoder;
11816 struct intel_connector *connector;
f6e5b160 11817
3a3371ff 11818 for_each_intel_connector(dev, connector) {
9a935856
DV		 11819 connector->new_encoder =
11820 to_intel_encoder(connector->base.encoder);
11821 }
f6e5b160 11822
b2784e15 11823 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11824 encoder->new_crtc =
11825 to_intel_crtc(encoder->base.crtc);
11826 }
7668851f 11827
d3fcc808 11828 for_each_intel_crtc(dev, crtc) {
83d65738 11829 crtc->new_enabled = crtc->base.state->enable;
7668851f 11830 }
f6e5b160
CW		 11831}
11832
d29b2f9d
ACO		 11833/* Transitional helper to copy current connector/encoder state to
11834 * connector->state. This is needed so that code that is partially
11835 * converted to atomic does the right thing.
11836 */
11837static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11838{
11839 struct intel_connector *connector;
11840
11841 for_each_intel_connector(dev, connector) {
11842 if (connector->base.encoder) {
11843 connector->base.state->best_encoder =
11844 connector->base.encoder;
11845 connector->base.state->crtc =
11846 connector->base.encoder->crtc;
11847 } else {
11848 connector->base.state->best_encoder = NULL;
11849 connector->base.state->crtc = NULL;
11850 }
11851 }
11852}
11853
050f7aeb 11854static void
eba905b2 11855connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11856 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11857{
11858 int bpp = pipe_config->pipe_bpp;
11859
11860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11861 connector->base.base.id,
c23cc417 11862 connector->base.name);
050f7aeb
DV		 11863
11864 /* Don't use an invalid EDID bpc value */
11865 if (connector->base.display_info.bpc &&
11866 connector->base.display_info.bpc * 3 < bpp) {
11867 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11868 bpp, connector->base.display_info.bpc*3);
11869 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11870 }
11871
11872 /* Clamp bpp to 8 on screens without EDID 1.4 */
11873 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11874 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11875 bpp);
11876 pipe_config->pipe_bpp = 24;
11877 }
11878}
11879
4e53c2e0 11880static int
050f7aeb 11881compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11882 struct intel_crtc_state *pipe_config)
4e53c2e0 11883{
050f7aeb 11884 struct drm_device *dev = crtc->base.dev;
1486017f 11885 struct drm_atomic_state *state;
da3ced29
ACO		 11886 struct drm_connector *connector;
11887 struct drm_connector_state *connector_state;
1486017f 11888 int bpp, i;
4e53c2e0 11889
d328c9d7 11890 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11891 bpp = 10*3;
d328c9d7
DV		 11892 else if (INTEL_INFO(dev)->gen >= 5)
11893 bpp = 12*3;
11894 else
11895 bpp = 8*3;
11896
4e53c2e0 11897
4e53c2e0
DV		 11898 pipe_config->pipe_bpp = bpp;
11899
1486017f
ACO		 11900 state = pipe_config->base.state;
11901
4e53c2e0 11902 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11903 for_each_connector_in_state(state, connector, connector_state, i) {
11904 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11905 continue;
11906
da3ced29
ACO		 11907 connected_sink_compute_bpp(to_intel_connector(connector),
11908 pipe_config);
4e53c2e0
DV		 11909 }
11910
11911 return bpp;
11912}
11913
644db711
DV		 11914static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11915{
11916 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11917 "type: 0x%x flags: 0x%x\n",
1342830c 11918 mode->crtc_clock,
644db711
DV		 11919 mode->crtc_hdisplay, mode->crtc_hsync_start,
11920 mode->crtc_hsync_end, mode->crtc_htotal,
11921 mode->crtc_vdisplay, mode->crtc_vsync_start,
11922 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11923}
11924
c0b03411 11925static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11926 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11927 const char *context)
11928{
6a60cd87
CK		 11929 struct drm_device *dev = crtc->base.dev;
11930 struct drm_plane *plane;
11931 struct intel_plane *intel_plane;
11932 struct intel_plane_state *state;
11933 struct drm_framebuffer *fb;
11934
11935 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11936 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11937
11938 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11939 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11940 pipe_config->pipe_bpp, pipe_config->dither);
11941 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11942 pipe_config->has_pch_encoder,
11943 pipe_config->fdi_lanes,
11944 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11945 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11946 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11947 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11948 pipe_config->has_dp_encoder,
11949 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11950 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11951 pipe_config->dp_m_n.tu);
b95af8be
VK		 11952
11953 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11954 pipe_config->has_dp_encoder,
11955 pipe_config->dp_m2_n2.gmch_m,
11956 pipe_config->dp_m2_n2.gmch_n,
11957 pipe_config->dp_m2_n2.link_m,
11958 pipe_config->dp_m2_n2.link_n,
11959 pipe_config->dp_m2_n2.tu);
11960
55072d19
DV		 11961 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11962 pipe_config->has_audio,
11963 pipe_config->has_infoframe);
11964
c0b03411 11965 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11966 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11967 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11968 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11969 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11970 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11971 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11972 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11973 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11974 crtc->num_scalers,
11975 pipe_config->scaler_state.scaler_users,
11976 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11977 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11978 pipe_config->gmch_pfit.control,
11979 pipe_config->gmch_pfit.pgm_ratios,
11980 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11981 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11982 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11983 pipe_config->pch_pfit.size,
11984 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11985 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11986 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11987
415ff0f6
TU		 11988 if (IS_BROXTON(dev)) {
11989 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11990 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11991 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11992 pipe_config->ddi_pll_sel,
11993 pipe_config->dpll_hw_state.ebb0,
11994 pipe_config->dpll_hw_state.pll0,
11995 pipe_config->dpll_hw_state.pll1,
11996 pipe_config->dpll_hw_state.pll2,
11997 pipe_config->dpll_hw_state.pll3,
11998 pipe_config->dpll_hw_state.pll6,
11999 pipe_config->dpll_hw_state.pll8,
12000 pipe_config->dpll_hw_state.pcsdw12);
12001 } else if (IS_SKYLAKE(dev)) {
12002 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12003 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12004 pipe_config->ddi_pll_sel,
12005 pipe_config->dpll_hw_state.ctrl1,
12006 pipe_config->dpll_hw_state.cfgcr1,
12007 pipe_config->dpll_hw_state.cfgcr2);
12008 } else if (HAS_DDI(dev)) {
12009 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12010 pipe_config->ddi_pll_sel,
12011 pipe_config->dpll_hw_state.wrpll);
12012 } else {
12013 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12014 "fp0: 0x%x, fp1: 0x%x\n",
12015 pipe_config->dpll_hw_state.dpll,
12016 pipe_config->dpll_hw_state.dpll_md,
12017 pipe_config->dpll_hw_state.fp0,
12018 pipe_config->dpll_hw_state.fp1);
12019 }
12020
6a60cd87
CK		 12021 DRM_DEBUG_KMS("planes on this crtc\n");
12022 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12023 intel_plane = to_intel_plane(plane);
12024 if (intel_plane->pipe != crtc->pipe)
12025 continue;
12026
12027 state = to_intel_plane_state(plane->state);
12028 fb = state->base.fb;
12029 if (!fb) {
12030 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12031 "disabled, scaler_id = %d\n",
12032 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12033 plane->base.id, intel_plane->pipe,
12034 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12035 drm_plane_index(plane), state->scaler_id);
12036 continue;
12037 }
12038
12039 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12040 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12041 plane->base.id, intel_plane->pipe,
12042 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12043 drm_plane_index(plane));
12044 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12045 fb->base.id, fb->width, fb->height, fb->pixel_format);
12046 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12047 state->scaler_id,
12048 state->src.x1 >> 16, state->src.y1 >> 16,
12049 drm_rect_width(&state->src) >> 16,
12050 drm_rect_height(&state->src) >> 16,
12051 state->dst.x1, state->dst.y1,
12052 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12053 }
c0b03411
DV		 12054}
12055
5448a00d 12056static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12057{
5448a00d
ACO		 12058 struct drm_device *dev = state->dev;
12059 struct intel_encoder *encoder;
da3ced29 12060 struct drm_connector *connector;
5448a00d 12061 struct drm_connector_state *connector_state;
00f0b378 12062 unsigned int used_ports = 0;
5448a00d 12063 int i;
00f0b378
VS		 12064
12065 /*
12066 * Walk the connector list instead of the encoder
12067 * list to detect the problem on ddi platforms
12068 * where there's just one encoder per digital port.
12069 */
da3ced29 12070 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12071 if (!connector_state->best_encoder)
00f0b378
VS		 12072 continue;
12073
5448a00d
ACO		 12074 encoder = to_intel_encoder(connector_state->best_encoder);
12075
12076 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12077
12078 switch (encoder->type) {
12079 unsigned int port_mask;
12080 case INTEL_OUTPUT_UNKNOWN:
12081 if (WARN_ON(!HAS_DDI(dev)))
12082 break;
12083 case INTEL_OUTPUT_DISPLAYPORT:
12084 case INTEL_OUTPUT_HDMI:
12085 case INTEL_OUTPUT_EDP:
12086 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12087
12088 /* the same port mustn't appear more than once */
12089 if (used_ports & port_mask)
12090 return false;
12091
12092 used_ports |= port_mask;
12093 default:
12094 break;
12095 }
12096 }
12097
12098 return true;
12099}
12100
83a57153
ACO		 12101static void
12102clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12103{
12104 struct drm_crtc_state tmp_state;
663a3640 12105 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12106 struct intel_dpll_hw_state dpll_hw_state;
12107 enum intel_dpll_id shared_dpll;
8504c74c 12108 uint32_t ddi_pll_sel;
83a57153 12109
7546a384
ACO		 12110 /* FIXME: before the switch to atomic started, a new pipe_config was
12111 * kzalloc'd. Code that depends on any field being zero should be
12112 * fixed, so that the crtc_state can be safely duplicated. For now,
12113 * only fields that are know to not cause problems are preserved. */
12114
83a57153 12115 tmp_state = crtc_state->base;
663a3640 12116 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12117 shared_dpll = crtc_state->shared_dpll;
12118 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12119 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12120
83a57153 12121 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12122
83a57153 12123 crtc_state->base = tmp_state;
663a3640 12124 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12125 crtc_state->shared_dpll = shared_dpll;
12126 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12127 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12128}
12129
548ee15b 12130static int
b8cecdf5 12131intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12132 struct intel_crtc_state *pipe_config)
ee7b9f93 12133{
b359283a 12134 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12135 struct intel_encoder *encoder;
da3ced29 12136 struct drm_connector *connector;
0b901879 12137 struct drm_connector_state *connector_state;
d328c9d7 12138 int base_bpp, ret = -EINVAL;
0b901879 12139 int i;
e29c22c0 12140 bool retry = true;
ee7b9f93 12141
83a57153 12142 clear_intel_crtc_state(pipe_config);
7758a113 12143
e143a21c
DV		 12144 pipe_config->cpu_transcoder =
12145 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12146
2960bc9c
ID		 12147 /*
12148 * Sanitize sync polarity flags based on requested ones. If neither
12149 * positive or negative polarity is requested, treat this as meaning
12150 * negative polarity.
12151 */
2d112de7 12152 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12153 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12154 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12155
2d112de7 12156 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12157 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12158 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12159
050f7aeb
DV		 12160 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12161 * plane pixel format and any sink constraints into account. Returns the
12162 * source plane bpp so that dithering can be selected on mismatches
12163 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12164 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12165 pipe_config);
12166 if (base_bpp < 0)
4e53c2e0
DV		 12167 goto fail;
12168
e41a56be
VS		 12169 /*
12170 * Determine the real pipe dimensions. Note that stereo modes can
12171 * increase the actual pipe size due to the frame doubling and
12172 * insertion of additional space for blanks between the frame. This
12173 * is stored in the crtc timings. We use the requested mode to do this
12174 * computation to clearly distinguish it from the adjusted mode, which
12175 * can be changed by the connectors in the below retry loop.
12176 */
2d112de7 12177 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12178 &pipe_config->pipe_src_w,
12179 &pipe_config->pipe_src_h);
e41a56be 12180
e29c22c0 12181encoder_retry:
ef1b460d 12182 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12183 pipe_config->port_clock = 0;
ef1b460d 12184 pipe_config->pixel_multiplier = 1;
ff9a6750 12185
135c81b8 12186 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12187 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12188 CRTC_STEREO_DOUBLE);
135c81b8 12189
7758a113
DV		 12190 /* Pass our mode to the connectors and the CRTC to give them a chance to
12191 * adjust it according to limitations or connector properties, and also
12192 * a chance to reject the mode entirely.
47f1c6c9 12193 */
da3ced29 12194 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12195 if (connector_state->crtc != crtc)
7758a113 12196 continue;
7ae89233 12197
0b901879
ACO		 12198 encoder = to_intel_encoder(connector_state->best_encoder);
12199
efea6e8e
DV		 12200 if (!(encoder->compute_config(encoder, pipe_config))) {
12201 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12202 goto fail;
12203 }
ee7b9f93 12204 }
47f1c6c9 12205
ff9a6750
DV		 12206 /* Set default port clock if not overwritten by the encoder. Needs to be
12207 * done afterwards in case the encoder adjusts the mode. */
12208 if (!pipe_config->port_clock)
2d112de7 12209 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12210 * pipe_config->pixel_multiplier;
ff9a6750 12211
a43f6e0f 12212 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12213 if (ret < 0) {
7758a113
DV		 12214 DRM_DEBUG_KMS("CRTC fixup failed\n");
12215 goto fail;
ee7b9f93 12216 }
e29c22c0
DV		 12217
12218 if (ret == RETRY) {
12219 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12220 ret = -EINVAL;
12221 goto fail;
12222 }
12223
12224 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12225 retry = false;
12226 goto encoder_retry;
12227 }
12228
d328c9d7 12229 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12230 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12231 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12232
cdba954e
ACO		 12233 /* Check if we need to force a modeset */
12234 if (pipe_config->has_audio !=
85a96e7a 12235 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12236 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12237 ret = drm_atomic_add_affected_planes(state, crtc);
12238 }
cdba954e
ACO		 12239
12240 /*
12241 * Note we have an issue here with infoframes: current code
12242 * only updates them on the full mode set path per hw
12243 * requirements. So here we should be checking for any
12244 * required changes and forcing a mode set.
12245 */
7758a113 12246fail:
548ee15b 12247 return ret;
ee7b9f93 12248}
47f1c6c9 12249
ea9d758d 12250static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12251{
ea9d758d 12252 struct drm_encoder *encoder;
f6e5b160 12253 struct drm_device *dev = crtc->dev;
f6e5b160 12254
ea9d758d
DV		 12255 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12256 if (encoder->crtc == crtc)
12257 return true;
12258
12259 return false;
12260}
12261
12262static void
0a9ab303 12263intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12264{
0a9ab303 12265 struct drm_device *dev = state->dev;
ea9d758d 12266 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12267 struct drm_crtc *crtc;
12268 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12269 struct drm_connector *connector;
12270
de419ab6 12271 intel_shared_dpll_commit(state);
ba41c0de 12272
b2784e15 12273 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12274 if (!intel_encoder->base.crtc)
12275 continue;
12276
69024de8
ML		 12277 crtc = intel_encoder->base.crtc;
12278 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12279 if (!crtc_state || !needs_modeset(crtc->state))
12280 continue;
ea9d758d 12281
69024de8 12282 intel_encoder->connectors_active = false;
ea9d758d
DV		 12283 }
12284
3cb480bc 12285 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12286 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12287
7668851f 12288 /* Double check state. */
0a9ab303
ACO		 12289 for_each_crtc(dev, crtc) {
12290 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12291
12292 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12293
12294 /* Update hwmode for vblank functions */
12295 if (crtc->state->active)
12296 crtc->hwmode = crtc->state->adjusted_mode;
12297 else
12298 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12299 }
12300
12301 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12302 if (!connector->encoder || !connector->encoder->crtc)
12303 continue;
12304
69024de8
ML		 12305 crtc = connector->encoder->crtc;
12306 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12307 if (!crtc_state || !needs_modeset(crtc->state))
12308 continue;
ea9d758d 12309
53d9f4e9 12310 if (crtc->state->active) {
69024de8
ML		 12311 struct drm_property *dpms_property =
12312 dev->mode_config.dpms_property;
68d34720 12313
69024de8
ML		 12314 connector->dpms = DRM_MODE_DPMS_ON;
12315 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12316
69024de8
ML		 12317 intel_encoder = to_intel_encoder(connector->encoder);
12318 intel_encoder->connectors_active = true;
12319 } else
12320 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12321 }
ea9d758d
DV		 12322}
12323
3bd26263 12324static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12325{
3bd26263 12326 int diff;
f1f644dc
JB		 12327
12328 if (clock1 == clock2)
12329 return true;
12330
12331 if (!clock1 || !clock2)
12332 return false;
12333
12334 diff = abs(clock1 - clock2);
12335
12336 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12337 return true;
12338
12339 return false;
12340}
12341
25c5b266
DV		 12342#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12343 list_for_each_entry((intel_crtc), \
12344 &(dev)->mode_config.crtc_list, \
12345 base.head) \
0973f18f 12346 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12347
0e8ffe1b 12348static bool
2fa2fe9a 12349intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12350 struct intel_crtc_state *current_config,
12351 struct intel_crtc_state *pipe_config)
0e8ffe1b 12352{
66e985c0
DV		 12353#define PIPE_CONF_CHECK_X(name) \
12354 if (current_config->name != pipe_config->name) { \
12355 DRM_ERROR("mismatch in " #name " " \
12356 "(expected 0x%08x, found 0x%08x)\n", \
12357 current_config->name, \
12358 pipe_config->name); \
12359 return false; \
12360 }
12361
08a24034
DV		 12362#define PIPE_CONF_CHECK_I(name) \
12363 if (current_config->name != pipe_config->name) { \
12364 DRM_ERROR("mismatch in " #name " " \
12365 "(expected %i, found %i)\n", \
12366 current_config->name, \
12367 pipe_config->name); \
12368 return false; \
88adfff1
DV		 12369 }
12370
b95af8be
VK		 12371/* This is required for BDW+ where there is only one set of registers for
12372 * switching between high and low RR.
12373 * This macro can be used whenever a comparison has to be made between one
12374 * hw state and multiple sw state variables.
12375 */
12376#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12377 if ((current_config->name != pipe_config->name) && \
12378 (current_config->alt_name != pipe_config->name)) { \
12379 DRM_ERROR("mismatch in " #name " " \
12380 "(expected %i or %i, found %i)\n", \
12381 current_config->name, \
12382 current_config->alt_name, \
12383 pipe_config->name); \
12384 return false; \
12385 }
12386
1bd1bd80
DV		 12387#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12388 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12389 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12390 "(expected %i, found %i)\n", \
12391 current_config->name & (mask), \
12392 pipe_config->name & (mask)); \
12393 return false; \
12394 }
12395
5e550656
VS		 12396#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12397 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12398 DRM_ERROR("mismatch in " #name " " \
12399 "(expected %i, found %i)\n", \
12400 current_config->name, \
12401 pipe_config->name); \
12402 return false; \
12403 }
12404
bb760063
DV		 12405#define PIPE_CONF_QUIRK(quirk) \
12406 ((current_config->quirks | pipe_config->quirks) & (quirk))
12407
eccb140b
DV		 12408 PIPE_CONF_CHECK_I(cpu_transcoder);
12409
08a24034
DV		 12410 PIPE_CONF_CHECK_I(has_pch_encoder);
12411 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12412 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12413 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12414 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12415 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12416 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12417
eb14cb74 12418 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12419
12420 if (INTEL_INFO(dev)->gen < 8) {
12421 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12422 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12423 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12424 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12425 PIPE_CONF_CHECK_I(dp_m_n.tu);
12426
12427 if (current_config->has_drrs) {
12428 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12429 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12430 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12431 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12432 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12433 }
12434 } else {
12435 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12436 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12437 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12438 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12439 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12440 }
eb14cb74 12441
2d112de7
ACO		 12442 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12443 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12444 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12445 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12446 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12447 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12448
2d112de7
ACO		 12449 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12450 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12451 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12452 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12453 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12454 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12455
c93f54cf 12456 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12457 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12458 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12459 IS_VALLEYVIEW(dev))
12460 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12461 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12462
9ed109a7
DV		 12463 PIPE_CONF_CHECK_I(has_audio);
12464
2d112de7 12465 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12466 DRM_MODE_FLAG_INTERLACE);
12467
bb760063 12468 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12469 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12470 DRM_MODE_FLAG_PHSYNC);
2d112de7 12471 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12472 DRM_MODE_FLAG_NHSYNC);
2d112de7 12473 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12474 DRM_MODE_FLAG_PVSYNC);
2d112de7 12475 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12476 DRM_MODE_FLAG_NVSYNC);
12477 }
045ac3b5 12478
37327abd
VS		 12479 PIPE_CONF_CHECK_I(pipe_src_w);
12480 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12481
9953599b
DV		 12482 /*
12483 * FIXME: BIOS likes to set up a cloned config with lvds+external
12484 * screen. Since we don't yet re-compute the pipe config when moving
12485 * just the lvds port away to another pipe the sw tracking won't match.
12486 *
12487 * Proper atomic modesets with recomputed global state will fix this.
12488 * Until then just don't check gmch state for inherited modes.
12489 */
12490 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12491 PIPE_CONF_CHECK_I(gmch_pfit.control);
12492 /* pfit ratios are autocomputed by the hw on gen4+ */
12493 if (INTEL_INFO(dev)->gen < 4)
12494 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12495 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12496 }
12497
fd4daa9c
CW		 12498 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12499 if (current_config->pch_pfit.enabled) {
12500 PIPE_CONF_CHECK_I(pch_pfit.pos);
12501 PIPE_CONF_CHECK_I(pch_pfit.size);
12502 }
2fa2fe9a 12503
a1b2278e
CK		 12504 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12505
e59150dc
JB		 12506 /* BDW+ don't expose a synchronous way to read the state */
12507 if (IS_HASWELL(dev))
12508 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12509
282740f7
VS		 12510 PIPE_CONF_CHECK_I(double_wide);
12511
26804afd
DV		 12512 PIPE_CONF_CHECK_X(ddi_pll_sel);
12513
c0d43d62 12514 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12515 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12516 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12517 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12518 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12519 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12520 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12521 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12522 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12523
42571aef
VS		 12524 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12525 PIPE_CONF_CHECK_I(pipe_bpp);
12526
2d112de7 12527 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12528 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12529
66e985c0 12530#undef PIPE_CONF_CHECK_X
08a24034 12531#undef PIPE_CONF_CHECK_I
b95af8be 12532#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12533#undef PIPE_CONF_CHECK_FLAGS
5e550656 12534#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12535#undef PIPE_CONF_QUIRK
88adfff1 12536
0e8ffe1b
DV		 12537 return true;
12538}
12539
08db6652
DL		 12540static void check_wm_state(struct drm_device *dev)
12541{
12542 struct drm_i915_private *dev_priv = dev->dev_private;
12543 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12544 struct intel_crtc *intel_crtc;
12545 int plane;
12546
12547 if (INTEL_INFO(dev)->gen < 9)
12548 return;
12549
12550 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12551 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12552
12553 for_each_intel_crtc(dev, intel_crtc) {
12554 struct skl_ddb_entry *hw_entry, *sw_entry;
12555 const enum pipe pipe = intel_crtc->pipe;
12556
12557 if (!intel_crtc->active)
12558 continue;
12559
12560 /* planes */
dd740780 12561 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12562 hw_entry = &hw_ddb.plane[pipe][plane];
12563 sw_entry = &sw_ddb->plane[pipe][plane];
12564
12565 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12566 continue;
12567
12568 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12569 "(expected (%u,%u), found (%u,%u))\n",
12570 pipe_name(pipe), plane + 1,
12571 sw_entry->start, sw_entry->end,
12572 hw_entry->start, hw_entry->end);
12573 }
12574
12575 /* cursor */
12576 hw_entry = &hw_ddb.cursor[pipe];
12577 sw_entry = &sw_ddb->cursor[pipe];
12578
12579 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12580 continue;
12581
12582 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12583 "(expected (%u,%u), found (%u,%u))\n",
12584 pipe_name(pipe),
12585 sw_entry->start, sw_entry->end,
12586 hw_entry->start, hw_entry->end);
12587 }
12588}
12589
91d1b4bd
DV		 12590static void
12591check_connector_state(struct drm_device *dev)
8af6cf88 12592{
8af6cf88
DV		 12593 struct intel_connector *connector;
12594
3a3371ff 12595 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12596 /* This also checks the encoder/connector hw state with the
12597 * ->get_hw_state callbacks. */
12598 intel_connector_check_state(connector);
12599
e2c719b7 12600 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12601 "connector's staged encoder doesn't match current encoder\n");
12602 }
91d1b4bd
DV		 12603}
12604
12605static void
12606check_encoder_state(struct drm_device *dev)
12607{
12608 struct intel_encoder *encoder;
12609 struct intel_connector *connector;
8af6cf88 12610
b2784e15 12611 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12612 bool enabled = false;
12613 bool active = false;
12614 enum pipe pipe, tracked_pipe;
12615
12616 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12617 encoder->base.base.id,
8e329a03 12618 encoder->base.name);
8af6cf88 12619
e2c719b7 12620 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12621 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12622 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12623 "encoder's active_connectors set, but no crtc\n");
12624
3a3371ff 12625 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12626 if (connector->base.encoder != &encoder->base)
12627 continue;
12628 enabled = true;
12629 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12630 active = true;
12631 }
0e32b39c
DA		 12632 /*
12633 * for MST connectors if we unplug the connector is gone
12634 * away but the encoder is still connected to a crtc
12635 * until a modeset happens in response to the hotplug.
12636 */
12637 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12638 continue;
12639
e2c719b7 12640 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12641 "encoder's enabled state mismatch "
12642 "(expected %i, found %i)\n",
12643 !!encoder->base.crtc, enabled);
e2c719b7 12644 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12645 "active encoder with no crtc\n");
12646
e2c719b7 12647 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12648 "encoder's computed active state doesn't match tracked active state "
12649 "(expected %i, found %i)\n", active, encoder->connectors_active);
12650
12651 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12652 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12653 "encoder's hw state doesn't match sw tracking "
12654 "(expected %i, found %i)\n",
12655 encoder->connectors_active, active);
12656
12657 if (!encoder->base.crtc)
12658 continue;
12659
12660 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12661 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12662 "active encoder's pipe doesn't match"
12663 "(expected %i, found %i)\n",
12664 tracked_pipe, pipe);
12665
12666 }
91d1b4bd
DV		 12667}
12668
12669static void
12670check_crtc_state(struct drm_device *dev)
12671{
fbee40df 12672 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12673 struct intel_crtc *crtc;
12674 struct intel_encoder *encoder;
5cec258b 12675 struct intel_crtc_state pipe_config;
8af6cf88 12676
d3fcc808 12677 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12678 bool enabled = false;
12679 bool active = false;
12680
045ac3b5
JB		 12681 memset(&pipe_config, 0, sizeof(pipe_config));
12682
8af6cf88
DV		 12683 DRM_DEBUG_KMS("[CRTC:%d]\n",
12684 crtc->base.base.id);
12685
83d65738 12686 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12687 "active crtc, but not enabled in sw tracking\n");
12688
b2784e15 12689 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12690 if (encoder->base.crtc != &crtc->base)
12691 continue;
12692 enabled = true;
12693 if (encoder->connectors_active)
12694 active = true;
12695 }
6c49f241 12696
e2c719b7 12697 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12698 "crtc's computed active state doesn't match tracked active state "
12699 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12700 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12701 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12702 "(expected %i, found %i)\n", enabled,
12703 crtc->base.state->enable);
8af6cf88 12704
0e8ffe1b
DV		 12705 active = dev_priv->display.get_pipe_config(crtc,
12706 &pipe_config);
d62cf62a 12707
b6b5d049
VS		 12708 /* hw state is inconsistent with the pipe quirk */
12709 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12710 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12711 active = crtc->active;
12712
b2784e15 12713 for_each_intel_encoder(dev, encoder) {
3eaba51c 12714 enum pipe pipe;
6c49f241
DV		 12715 if (encoder->base.crtc != &crtc->base)
12716 continue;
1d37b689 12717 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12718 encoder->get_config(encoder, &pipe_config);
12719 }
12720
e2c719b7 12721 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12722 "crtc active state doesn't match with hw state "
12723 "(expected %i, found %i)\n", crtc->active, active);
12724
53d9f4e9
ML		 12725 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12726 "transitional active state does not match atomic hw state "
12727 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12728
c0b03411 12729 if (active &&
6e3c9717 12730 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12731 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12732 intel_dump_pipe_config(crtc, &pipe_config,
12733 "[hw state]");
6e3c9717 12734 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12735 "[sw state]");
12736 }
8af6cf88
DV		 12737 }
12738}
12739
91d1b4bd
DV		 12740static void
12741check_shared_dpll_state(struct drm_device *dev)
12742{
fbee40df 12743 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12744 struct intel_crtc *crtc;
12745 struct intel_dpll_hw_state dpll_hw_state;
12746 int i;
5358901f
DV		 12747
12748 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12749 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12750 int enabled_crtcs = 0, active_crtcs = 0;
12751 bool active;
12752
12753 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12754
12755 DRM_DEBUG_KMS("%s\n", pll->name);
12756
12757 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12758
e2c719b7 12759 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12760 "more active pll users than references: %i vs %i\n",
3e369b76 12761 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12762 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12763 "pll in active use but not on in sw tracking\n");
e2c719b7 12764 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12765 "pll in on but not on in use in sw tracking\n");
e2c719b7 12766 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12767 "pll on state mismatch (expected %i, found %i)\n",
12768 pll->on, active);
12769
d3fcc808 12770 for_each_intel_crtc(dev, crtc) {
83d65738 12771 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12772 enabled_crtcs++;
12773 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12774 active_crtcs++;
12775 }
e2c719b7 12776 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12777 "pll active crtcs mismatch (expected %i, found %i)\n",
12778 pll->active, active_crtcs);
e2c719b7 12779 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12780 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12781 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12782
e2c719b7 12783 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12784 sizeof(dpll_hw_state)),
12785 "pll hw state mismatch\n");
5358901f 12786 }
8af6cf88
DV		 12787}
12788
91d1b4bd
DV		 12789void
12790intel_modeset_check_state(struct drm_device *dev)
12791{
08db6652 12792 check_wm_state(dev);
91d1b4bd
DV		 12793 check_connector_state(dev);
12794 check_encoder_state(dev);
12795 check_crtc_state(dev);
12796 check_shared_dpll_state(dev);
12797}
12798
5cec258b 12799void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12800 int dotclock)
12801{
12802 /*
12803 * FDI already provided one idea for the dotclock.
12804 * Yell if the encoder disagrees.
12805 */
2d112de7 12806 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12807 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12808 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12809}
12810
80715b2f
VS		 12811static void update_scanline_offset(struct intel_crtc *crtc)
12812{
12813 struct drm_device *dev = crtc->base.dev;
12814
12815 /*
12816 * The scanline counter increments at the leading edge of hsync.
12817 *
12818 * On most platforms it starts counting from vtotal-1 on the
12819 * first active line. That means the scanline counter value is
12820 * always one less than what we would expect. Ie. just after
12821 * start of vblank, which also occurs at start of hsync (on the
12822 * last active line), the scanline counter will read vblank_start-1.
12823 *
12824 * On gen2 the scanline counter starts counting from 1 instead
12825 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12826 * to keep the value positive), instead of adding one.
12827 *
12828 * On HSW+ the behaviour of the scanline counter depends on the output
12829 * type. For DP ports it behaves like most other platforms, but on HDMI
12830 * there's an extra 1 line difference. So we need to add two instead of
12831 * one to the value.
12832 */
12833 if (IS_GEN2(dev)) {
6e3c9717 12834 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12835 int vtotal;
12836
12837 vtotal = mode->crtc_vtotal;
12838 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12839 vtotal /= 2;
12840
12841 crtc->scanline_offset = vtotal - 1;
12842 } else if (HAS_DDI(dev) &&
409ee761 12843 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12844 crtc->scanline_offset = 2;
12845 } else
12846 crtc->scanline_offset = 1;
12847}
12848
ad421372 12849static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12850{
225da59b 12851 struct drm_device *dev = state->dev;
ed6739ef 12852 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12853 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12854 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12855 struct intel_crtc_state *intel_crtc_state;
12856 struct drm_crtc *crtc;
12857 struct drm_crtc_state *crtc_state;
0a9ab303 12858 int i;
ed6739ef
ACO		 12859
12860 if (!dev_priv->display.crtc_compute_clock)
ad421372 12861 return;
ed6739ef 12862
0a9ab303 12863 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12864 int dpll;
12865
0a9ab303 12866 intel_crtc = to_intel_crtc(crtc);
4978cc93 12867 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12868 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12869
ad421372 12870 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12871 continue;
12872
ad421372 12873 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12874
ad421372
ML		 12875 if (!shared_dpll)
12876 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12877
ad421372
ML		 12878 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12879 }
ed6739ef
ACO		 12880}
12881
99d736a2
ML		 12882/*
12883 * This implements the workaround described in the "notes" section of the mode
12884 * set sequence documentation. When going from no pipes or single pipe to
12885 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12886 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12887 */
12888static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12889{
12890 struct drm_crtc_state *crtc_state;
12891 struct intel_crtc *intel_crtc;
12892 struct drm_crtc *crtc;
12893 struct intel_crtc_state *first_crtc_state = NULL;
12894 struct intel_crtc_state *other_crtc_state = NULL;
12895 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12896 int i;
12897
12898 /* look at all crtc's that are going to be enabled in during modeset */
12899 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12900 intel_crtc = to_intel_crtc(crtc);
12901
12902 if (!crtc_state->active || !needs_modeset(crtc_state))
12903 continue;
12904
12905 if (first_crtc_state) {
12906 other_crtc_state = to_intel_crtc_state(crtc_state);
12907 break;
12908 } else {
12909 first_crtc_state = to_intel_crtc_state(crtc_state);
12910 first_pipe = intel_crtc->pipe;
12911 }
12912 }
12913
12914 /* No workaround needed? */
12915 if (!first_crtc_state)
12916 return 0;
12917
12918 /* w/a possibly needed, check how many crtc's are already enabled. */
12919 for_each_intel_crtc(state->dev, intel_crtc) {
12920 struct intel_crtc_state *pipe_config;
12921
12922 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12923 if (IS_ERR(pipe_config))
12924 return PTR_ERR(pipe_config);
12925
12926 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12927
12928 if (!pipe_config->base.active ||
12929 needs_modeset(&pipe_config->base))
12930 continue;
12931
12932 /* 2 or more enabled crtcs means no need for w/a */
12933 if (enabled_pipe != INVALID_PIPE)
12934 return 0;
12935
12936 enabled_pipe = intel_crtc->pipe;
12937 }
12938
12939 if (enabled_pipe != INVALID_PIPE)
12940 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12941 else if (other_crtc_state)
12942 other_crtc_state->hsw_workaround_pipe = first_pipe;
12943
12944 return 0;
12945}
12946
27c329ed
ML		 12947static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12948{
12949 struct drm_crtc *crtc;
12950 struct drm_crtc_state *crtc_state;
12951 int ret = 0;
12952
12953 /* add all active pipes to the state */
12954 for_each_crtc(state->dev, crtc) {
12955 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12956 if (IS_ERR(crtc_state))
12957 return PTR_ERR(crtc_state);
12958
12959 if (!crtc_state->active || needs_modeset(crtc_state))
12960 continue;
12961
12962 crtc_state->mode_changed = true;
12963
12964 ret = drm_atomic_add_affected_connectors(state, crtc);
12965 if (ret)
12966 break;
12967
12968 ret = drm_atomic_add_affected_planes(state, crtc);
12969 if (ret)
12970 break;
12971 }
12972
12973 return ret;
12974}
12975
12976
054518dd 12977/* Code that should eventually be part of atomic_check() */
c347a676 12978static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12979{
12980 struct drm_device *dev = state->dev;
27c329ed 12981 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12982 int ret;
12983
b359283a
ML		 12984 if (!check_digital_port_conflicts(state)) {
12985 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12986 return -EINVAL;
12987 }
12988
054518dd
ACO		 12989 /*
12990 * See if the config requires any additional preparation, e.g.
12991 * to adjust global state with pipes off. We need to do this
12992 * here so we can get the modeset_pipe updated config for the new
12993 * mode set on this crtc. For other crtcs we need to use the
12994 * adjusted_mode bits in the crtc directly.
12995 */
27c329ed
ML		 12996 if (dev_priv->display.modeset_calc_cdclk) {
12997 unsigned int cdclk;
b432e5cf 12998
27c329ed
ML		 12999 ret = dev_priv->display.modeset_calc_cdclk(state);
13000
13001 cdclk = to_intel_atomic_state(state)->cdclk;
13002 if (!ret && cdclk != dev_priv->cdclk_freq)
13003 ret = intel_modeset_all_pipes(state);
13004
13005 if (ret < 0)
054518dd 13006 return ret;
27c329ed
ML		 13007 } else
13008 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13009
ad421372 13010 intel_modeset_clear_plls(state);
054518dd 13011
99d736a2 13012 if (IS_HASWELL(dev))
ad421372 13013 return haswell_mode_set_planes_workaround(state);
99d736a2 13014
ad421372 13015 return 0;
c347a676
ACO		 13016}
13017
13018static int
13019intel_modeset_compute_config(struct drm_atomic_state *state)
13020{
13021 struct drm_crtc *crtc;
13022 struct drm_crtc_state *crtc_state;
13023 int ret, i;
61333b60 13024 bool any_ms = false;
c347a676
ACO		 13025
13026 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13027 if (ret)
13028 return ret;
13029
c347a676 13030 for_each_crtc_in_state(state, crtc, crtc_state, i) {
61333b60
ML		 13031 if (!crtc_state->enable) {
13032 if (needs_modeset(crtc_state))
13033 any_ms = true;
c347a676 13034 continue;
61333b60 13035 }
c347a676 13036
d032ffa0
ML		 13037 if (to_intel_crtc_state(crtc_state)->quirks &
13038 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13039 ret = drm_atomic_add_affected_planes(state, crtc);
13040 if (ret)
13041 return ret;
13042
13043 /*
13044 * We ought to handle i915.fastboot here.
13045 * If no modeset is required and the primary plane has
13046 * a fb, update the members of crtc_state as needed,
13047 * and run the necessary updates during vblank evasion.
13048 */
13049 }
13050
b359283a
ML		 13051 if (!needs_modeset(crtc_state)) {
13052 ret = drm_atomic_add_affected_connectors(state, crtc);
13053 if (ret)
13054 return ret;
13055 }
13056
13057 ret = intel_modeset_pipe_config(crtc,
13058 to_intel_crtc_state(crtc_state));
c347a676
ACO		 13059 if (ret)
13060 return ret;
13061
61333b60
ML		 13062 if (needs_modeset(crtc_state))
13063 any_ms = true;
13064
c347a676
ACO		 13065 intel_dump_pipe_config(to_intel_crtc(crtc),
13066 to_intel_crtc_state(crtc_state),
13067 "[modeset]");
13068 }
13069
61333b60
ML		 13070 if (any_ms) {
13071 ret = intel_modeset_checks(state);
13072
13073 if (ret)
13074 return ret;
27c329ed
ML		 13075 } else
13076 to_intel_atomic_state(state)->cdclk =
13077 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13078
13079 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13080}
13081
c72d969b 13082static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13083{
c72d969b 13084 struct drm_device *dev = state->dev;
fbee40df 13085 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13086 struct drm_crtc *crtc;
13087 struct drm_crtc_state *crtc_state;
c0c36b94 13088 int ret = 0;
0a9ab303 13089 int i;
61333b60 13090 bool any_ms = false;
a6778b3c 13091
d4afb8cc
ACO		 13092 ret = drm_atomic_helper_prepare_planes(dev, state);
13093 if (ret)
13094 return ret;
13095
1c5e19f8
ML		 13096 drm_atomic_helper_swap_state(dev, state);
13097
0a9ab303 13098 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13100
61333b60
ML		 13101 if (!needs_modeset(crtc->state))
13102 continue;
13103
13104 any_ms = true;
a539205a 13105 intel_pre_plane_update(intel_crtc);
460da916 13106
a539205a
ML		 13107 if (crtc_state->active) {
13108 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13109 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13110 intel_crtc->active = false;
13111 intel_disable_shared_dpll(intel_crtc);
a539205a 13112 }
b8cecdf5 13113 }
7758a113 13114
ea9d758d
DV		 13115 /* Only after disabling all output pipelines that will be changed can we
13116 * update the the output configuration. */
0a9ab303 13117 intel_modeset_update_state(state);
f6e5b160 13118
a821fc46
ACO		 13119 /* The state has been swaped above, so state actually contains the
13120 * old state now. */
61333b60
ML		 13121 if (any_ms)
13122 modeset_update_crtc_power_domains(state);
47fab737 13123
a6778b3c 13124 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13125 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13126 if (needs_modeset(crtc->state) && crtc->state->active) {
13127 update_scanline_offset(to_intel_crtc(crtc));
13128 dev_priv->display.crtc_enable(crtc);
13129 }
80715b2f 13130
a539205a 13131 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13132 }
a6778b3c 13133
a6778b3c 13134 /* FIXME: add subpixel order */
83a57153 13135
d4afb8cc
ACO		 13136 drm_atomic_helper_cleanup_planes(dev, state);
13137
2bfb4627
ACO		 13138 drm_atomic_state_free(state);
13139
9eb45f22 13140 return 0;
f6e5b160
CW		 13141}
13142
568c634a 13143static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13144{
568c634a 13145 struct drm_device *dev = state->dev;
f30da187
DV		 13146 int ret;
13147
568c634a 13148 ret = __intel_set_mode(state);
f30da187 13149 if (ret == 0)
568c634a 13150 intel_modeset_check_state(dev);
f30da187
DV		 13151
13152 return ret;
13153}
13154
568c634a 13155static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13156{
568c634a 13157 int ret;
83a57153 13158
568c634a 13159 ret = intel_modeset_compute_config(state);
83a57153 13160 if (ret)
568c634a 13161 return ret;
7f27126e 13162
568c634a 13163 return intel_set_mode_checked(state);
7f27126e
JB		 13164}
13165
c0c36b94
CW		 13166void intel_crtc_restore_mode(struct drm_crtc *crtc)
13167{
83a57153
ACO		 13168 struct drm_device *dev = crtc->dev;
13169 struct drm_atomic_state *state;
13170 struct intel_encoder *encoder;
13171 struct intel_connector *connector;
13172 struct drm_connector_state *connector_state;
4be07317 13173 struct intel_crtc_state *crtc_state;
2bfb4627 13174 int ret;
83a57153
ACO		 13175
13176 state = drm_atomic_state_alloc(dev);
13177 if (!state) {
13178 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13179 crtc->base.id);
13180 return;
13181 }
13182
13183 state->acquire_ctx = dev->mode_config.acquire_ctx;
13184
13185 /* The force restore path in the HW readout code relies on the staged
13186 * config still keeping the user requested config while the actual
13187 * state has been overwritten by the configuration read from HW. We
13188 * need to copy the staged config to the atomic state, otherwise the
13189 * mode set will just reapply the state the HW is already in. */
13190 for_each_intel_encoder(dev, encoder) {
13191 if (&encoder->new_crtc->base != crtc)
13192 continue;
13193
13194 for_each_intel_connector(dev, connector) {
13195 if (connector->new_encoder != encoder)
13196 continue;
13197
13198 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13199 if (IS_ERR(connector_state)) {
13200 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13201 connector->base.base.id,
13202 connector->base.name,
13203 PTR_ERR(connector_state));
13204 continue;
13205 }
13206
13207 connector_state->crtc = crtc;
13208 connector_state->best_encoder = &encoder->base;
13209 }
13210 }
13211
4ed9fb37
ACO		 13212 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13213 if (IS_ERR(crtc_state)) {
13214 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13215 crtc->base.id, PTR_ERR(crtc_state));
13216 drm_atomic_state_free(state);
13217 return;
13218 }
4be07317 13219
4ed9fb37
ACO		 13220 crtc_state->base.active = crtc_state->base.enable =
13221 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13222
4ed9fb37 13223 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13224
d3a40d1b
ACO		 13225 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13226 crtc->primary->fb, crtc->x, crtc->y);
13227
568c634a 13228 ret = intel_set_mode(state);
2bfb4627
ACO		 13229 if (ret)
13230 drm_atomic_state_free(state);
c0c36b94
CW		 13231}
13232
25c5b266
DV		 13233#undef for_each_intel_crtc_masked
13234
b7885264
ACO		 13235static bool intel_connector_in_mode_set(struct intel_connector *connector,
13236 struct drm_mode_set *set)
13237{
13238 int ro;
13239
13240 for (ro = 0; ro < set->num_connectors; ro++)
13241 if (set->connectors[ro] == &connector->base)
13242 return true;
13243
13244 return false;
13245}
13246
2e431051 13247static int
9a935856
DV		 13248intel_modeset_stage_output_state(struct drm_device *dev,
13249 struct drm_mode_set *set,
944b0c76 13250 struct drm_atomic_state *state)
50f56119 13251{
9a935856 13252 struct intel_connector *connector;
d5432a9d 13253 struct drm_connector *drm_connector;
944b0c76 13254 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13255 struct drm_crtc *crtc;
13256 struct drm_crtc_state *crtc_state;
13257 int i, ret;
50f56119 13258
9abdda74 13259 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13260 * of connectors. For paranoia, double-check this. */
13261 WARN_ON(!set->fb && (set->num_connectors != 0));
13262 WARN_ON(set->fb && (set->num_connectors == 0));
13263
3a3371ff 13264 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13265 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13266
d5432a9d
ACO		 13267 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13268 continue;
13269
13270 connector_state =
13271 drm_atomic_get_connector_state(state, &connector->base);
13272 if (IS_ERR(connector_state))
13273 return PTR_ERR(connector_state);
13274
b7885264
ACO		 13275 if (in_mode_set) {
13276 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13277 connector_state->best_encoder =
13278 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13279 }
13280
d5432a9d 13281 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13282 continue;
13283
9a935856
DV		 13284 /* If we disable the crtc, disable all its connectors. Also, if
13285 * the connector is on the changing crtc but not on the new
13286 * connector list, disable it. */
b7885264 13287 if (!set->fb || !in_mode_set) {
d5432a9d 13288 connector_state->best_encoder = NULL;
9a935856
DV		 13289
13290 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13291 connector->base.base.id,
c23cc417 13292 connector->base.name);
9a935856 13293 }
50f56119 13294 }
9a935856 13295 /* connector->new_encoder is now updated for all connectors. */
50f56119 13296
d5432a9d
ACO		 13297 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13298 connector = to_intel_connector(drm_connector);
13299
13300 if (!connector_state->best_encoder) {
13301 ret = drm_atomic_set_crtc_for_connector(connector_state,
13302 NULL);
13303 if (ret)
13304 return ret;
7668851f 13305
50f56119 13306 continue;
d5432a9d 13307 }
50f56119 13308
d5432a9d
ACO		 13309 if (intel_connector_in_mode_set(connector, set)) {
13310 struct drm_crtc *crtc = connector->base.state->crtc;
13311
13312 /* If this connector was in a previous crtc, add it
13313 * to the state. We might need to disable it. */
13314 if (crtc) {
13315 crtc_state =
13316 drm_atomic_get_crtc_state(state, crtc);
13317 if (IS_ERR(crtc_state))
13318 return PTR_ERR(crtc_state);
13319 }
13320
13321 ret = drm_atomic_set_crtc_for_connector(connector_state,
13322 set->crtc);
13323 if (ret)
13324 return ret;
13325 }
50f56119
DV		 13326
13327 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13328 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13329 connector_state->crtc)) {
5e2b584e 13330 return -EINVAL;
50f56119 13331 }
944b0c76 13332
9a935856
DV		 13333 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13334 connector->base.base.id,
c23cc417 13335 connector->base.name,
d5432a9d 13336 connector_state->crtc->base.id);
944b0c76 13337
d5432a9d
ACO		 13338 if (connector_state->best_encoder != &connector->encoder->base)
13339 connector->encoder =
13340 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13341 }
7668851f 13342
d5432a9d 13343 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13344 bool has_connectors;
13345
d5432a9d
ACO		 13346 ret = drm_atomic_add_affected_connectors(state, crtc);
13347 if (ret)
13348 return ret;
4be07317 13349
49d6fa21
ML		 13350 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13351 if (has_connectors != crtc_state->enable)
13352 crtc_state->enable =
13353 crtc_state->active = has_connectors;
7668851f
VS		 13354 }
13355
8c7b5ccb
ACO		 13356 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13357 set->fb, set->x, set->y);
13358 if (ret)
13359 return ret;
13360
13361 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13362 if (IS_ERR(crtc_state))
13363 return PTR_ERR(crtc_state);
13364
ce52299c
MR		 13365 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13366 if (ret)
13367 return ret;
8c7b5ccb
ACO		 13368
13369 if (set->num_connectors)
13370 crtc_state->active = true;
13371
2e431051
DV		 13372 return 0;
13373}
13374
13375static int intel_crtc_set_config(struct drm_mode_set *set)
13376{
13377 struct drm_device *dev;
83a57153 13378 struct drm_atomic_state *state = NULL;
2e431051 13379 int ret;
2e431051 13380
8d3e375e
DV		 13381 BUG_ON(!set);
13382 BUG_ON(!set->crtc);
13383 BUG_ON(!set->crtc->helper_private);
2e431051 13384
7e53f3a4
DV		 13385 /* Enforce sane interface api - has been abused by the fb helper. */
13386 BUG_ON(!set->mode && set->fb);
13387 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13388
2e431051
DV		 13389 if (set->fb) {
13390 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13391 set->crtc->base.id, set->fb->base.id,
13392 (int)set->num_connectors, set->x, set->y);
13393 } else {
13394 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13395 }
13396
13397 dev = set->crtc->dev;
13398
83a57153 13399 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13400 if (!state)
13401 return -ENOMEM;
83a57153
ACO		 13402
13403 state->acquire_ctx = dev->mode_config.acquire_ctx;
13404
462a425a 13405 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13406 if (ret)
7cbf41d6 13407 goto out;
2e431051 13408
568c634a
ACO		 13409 ret = intel_modeset_compute_config(state);
13410 if (ret)
7cbf41d6 13411 goto out;
50f52756 13412
1f9954d0
JB		 13413 intel_update_pipe_size(to_intel_crtc(set->crtc));
13414
568c634a 13415 ret = intel_set_mode_checked(state);
2d05eae1 13416 if (ret) {
bf67dfeb
DV		 13417 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13418 set->crtc->base.id, ret);
2d05eae1 13419 }
50f56119 13420
7cbf41d6 13421out:
2bfb4627
ACO		 13422 if (ret)
13423 drm_atomic_state_free(state);
50f56119
DV		 13424 return ret;
13425}
f6e5b160
CW		 13426
13427static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13428 .gamma_set = intel_crtc_gamma_set,
50f56119 13429 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13430 .destroy = intel_crtc_destroy,
13431 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13432 .atomic_duplicate_state = intel_crtc_duplicate_state,
13433 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13434};
13435
5358901f
DV		 13436static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13437 struct intel_shared_dpll *pll,
13438 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13439{
5358901f 13440 uint32_t val;
ee7b9f93 13441
f458ebbc 13442 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13443 return false;
13444
5358901f 13445 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13446 hw_state->dpll = val;
13447 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13448 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13449
13450 return val & DPLL_VCO_ENABLE;
13451}
13452
15bdd4cf
DV		 13453static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13454 struct intel_shared_dpll *pll)
13455{
3e369b76
ACO		 13456 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13457 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13458}
13459
e7b903d2
DV		 13460static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13461 struct intel_shared_dpll *pll)
13462{
e7b903d2 13463 /* PCH refclock must be enabled first */
89eff4be 13464 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13465
3e369b76 13466 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13467
13468 /* Wait for the clocks to stabilize. */
13469 POSTING_READ(PCH_DPLL(pll->id));
13470 udelay(150);
13471
13472 /* The pixel multiplier can only be updated once the
13473 * DPLL is enabled and the clocks are stable.
13474 *
13475 * So write it again.
13476 */
3e369b76 13477 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13478 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13479 udelay(200);
13480}
13481
13482static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13483 struct intel_shared_dpll *pll)
13484{
13485 struct drm_device *dev = dev_priv->dev;
13486 struct intel_crtc *crtc;
e7b903d2
DV		 13487
13488 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13489 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13490 if (intel_crtc_to_shared_dpll(crtc) == pll)
13491 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13492 }
13493
15bdd4cf
DV		 13494 I915_WRITE(PCH_DPLL(pll->id), 0);
13495 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13496 udelay(200);
13497}
13498
46edb027
DV		 13499static char *ibx_pch_dpll_names[] = {
13500 "PCH DPLL A",
13501 "PCH DPLL B",
13502};
13503
7c74ade1 13504static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13505{
e7b903d2 13506 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13507 int i;
13508
7c74ade1 13509 dev_priv->num_shared_dpll = 2;
ee7b9f93 13510
e72f9fbf 13511 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13512 dev_priv->shared_dplls[i].id = i;
13513 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13514 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13515 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13516 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13517 dev_priv->shared_dplls[i].get_hw_state =
13518 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13519 }
13520}
13521
7c74ade1
DV		 13522static void intel_shared_dpll_init(struct drm_device *dev)
13523{
e7b903d2 13524 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13525
b6283055
VS		 13526 intel_update_cdclk(dev);
13527
9cd86933
DV		 13528 if (HAS_DDI(dev))
13529 intel_ddi_pll_init(dev);
13530 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13531 ibx_pch_dpll_init(dev);
13532 else
13533 dev_priv->num_shared_dpll = 0;
13534
13535 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13536}
13537
6beb8c23
MR		 13538/**
13539 * intel_prepare_plane_fb - Prepare fb for usage on plane
13540 * @plane: drm plane to prepare for
13541 * @fb: framebuffer to prepare for presentation
13542 *
13543 * Prepares a framebuffer for usage on a display plane. Generally this
13544 * involves pinning the underlying object and updating the frontbuffer tracking
13545 * bits. Some older platforms need special physical address handling for
13546 * cursor planes.
13547 *
13548 * Returns 0 on success, negative error code on failure.
13549 */
13550int
13551intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13552 struct drm_framebuffer *fb,
13553 const struct drm_plane_state *new_state)
465c120c
MR		 13554{
13555 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13556 struct intel_plane *intel_plane = to_intel_plane(plane);
13557 enum pipe pipe = intel_plane->pipe;
13558 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13559 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13560 unsigned frontbuffer_bits = 0;
13561 int ret = 0;
465c120c 13562
ea2c67bb 13563 if (!obj)
465c120c
MR		 13564 return 0;
13565
6beb8c23
MR		 13566 switch (plane->type) {
13567 case DRM_PLANE_TYPE_PRIMARY:
13568 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13569 break;
13570 case DRM_PLANE_TYPE_CURSOR:
13571 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13572 break;
13573 case DRM_PLANE_TYPE_OVERLAY:
13574 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13575 break;
13576 }
465c120c 13577
6beb8c23 13578 mutex_lock(&dev->struct_mutex);
465c120c 13579
6beb8c23
MR		 13580 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13581 INTEL_INFO(dev)->cursor_needs_physical) {
13582 int align = IS_I830(dev) ? 16 * 1024 : 256;
13583 ret = i915_gem_object_attach_phys(obj, align);
13584 if (ret)
13585 DRM_DEBUG_KMS("failed to attach phys object\n");
13586 } else {
91af127f 13587 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13588 }
465c120c 13589
6beb8c23
MR		 13590 if (ret == 0)
13591 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13592
4c34574f 13593 mutex_unlock(&dev->struct_mutex);
465c120c 13594
6beb8c23
MR		 13595 return ret;
13596}
13597
38f3ce3a
MR		 13598/**
13599 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13600 * @plane: drm plane to clean up for
13601 * @fb: old framebuffer that was on plane
13602 *
13603 * Cleans up a framebuffer that has just been removed from a plane.
13604 */
13605void
13606intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13607 struct drm_framebuffer *fb,
13608 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13609{
13610 struct drm_device *dev = plane->dev;
13611 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13612
13613 if (WARN_ON(!obj))
13614 return;
13615
13616 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13617 !INTEL_INFO(dev)->cursor_needs_physical) {
13618 mutex_lock(&dev->struct_mutex);
82bc3b2d 13619 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13620 mutex_unlock(&dev->struct_mutex);
13621 }
465c120c
MR		 13622}
13623
6156a456
CK		 13624int
13625skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13626{
13627 int max_scale;
13628 struct drm_device *dev;
13629 struct drm_i915_private *dev_priv;
13630 int crtc_clock, cdclk;
13631
13632 if (!intel_crtc || !crtc_state)
13633 return DRM_PLANE_HELPER_NO_SCALING;
13634
13635 dev = intel_crtc->base.dev;
13636 dev_priv = dev->dev_private;
13637 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13638 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13639
13640 if (!crtc_clock || !cdclk)
13641 return DRM_PLANE_HELPER_NO_SCALING;
13642
13643 /*
13644 * skl max scale is lower of:
13645 * close to 3 but not 3, -1 is for that purpose
13646 * or
13647 * cdclk/crtc_clock
13648 */
13649 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13650
13651 return max_scale;
13652}
13653
465c120c 13654static int
3c692a41 13655intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13656 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13657 struct intel_plane_state *state)
13658{
2b875c22
MR		 13659 struct drm_crtc *crtc = state->base.crtc;
13660 struct drm_framebuffer *fb = state->base.fb;
6156a456 13661 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13662 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13663 bool can_position = false;
465c120c 13664
061e4b8d
ML		 13665 /* use scaler when colorkey is not required */
13666 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13667 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13668 min_scale = 1;
13669 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13670 can_position = true;
6156a456 13671 }
d8106366 13672
061e4b8d
ML		 13673 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13674 &state->dst, &state->clip,
da20eabd
ML		 13675 min_scale, max_scale,
13676 can_position, true,
13677 &state->visible);
14af293f
GP		 13678}
13679
13680static void
13681intel_commit_primary_plane(struct drm_plane *plane,
13682 struct intel_plane_state *state)
13683{
2b875c22
MR		 13684 struct drm_crtc *crtc = state->base.crtc;
13685 struct drm_framebuffer *fb = state->base.fb;
13686 struct drm_device *dev = plane->dev;
14af293f 13687 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13688 struct intel_crtc *intel_crtc;
14af293f
GP		 13689 struct drm_rect *src = &state->src;
13690
ea2c67bb
MR		 13691 crtc = crtc ? crtc : plane->crtc;
13692 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13693
13694 plane->fb = fb;
9dc806fc
MR		 13695 crtc->x = src->x1 >> 16;
13696 crtc->y = src->y1 >> 16;
ccc759dc 13697
a539205a 13698 if (!crtc->state->active)
302d19ac 13699 return;
465c120c 13700
302d19ac
ML		 13701 if (state->visible)
13702 /* FIXME: kill this fastboot hack */
13703 intel_update_pipe_size(intel_crtc);
13704
13705 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13706}
13707
a8ad0d8e
ML		 13708static void
13709intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13710 struct drm_crtc *crtc)
a8ad0d8e
ML		 13711{
13712 struct drm_device *dev = plane->dev;
13713 struct drm_i915_private *dev_priv = dev->dev_private;
13714
a8ad0d8e
ML		 13715 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13716}
13717
32b7eeec 13718static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13719{
32b7eeec 13720 struct drm_device *dev = crtc->dev;
140fd38d 13721 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13723
a539205a
ML		 13724 if (!needs_modeset(crtc->state))
13725 intel_pre_plane_update(intel_crtc);
3c692a41 13726
32b7eeec
MR		 13727 if (intel_crtc->atomic.update_wm)
13728 intel_update_watermarks(crtc);
3c692a41 13729
32b7eeec 13730 intel_runtime_pm_get(dev_priv);
3c692a41 13731
c34c9ee4 13732 /* Perform vblank evasion around commit operation */
a539205a 13733 if (crtc->state->active)
c34c9ee4
MR		 13734 intel_crtc->atomic.evade =
13735 intel_pipe_update_start(intel_crtc,
13736 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13737
13738 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13739 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13740}
13741
13742static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13743{
13744 struct drm_device *dev = crtc->dev;
13745 struct drm_i915_private *dev_priv = dev->dev_private;
13746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13747
c34c9ee4
MR		 13748 if (intel_crtc->atomic.evade)
13749 intel_pipe_update_end(intel_crtc,
13750 intel_crtc->atomic.start_vbl_count);
3c692a41 13751
140fd38d 13752 intel_runtime_pm_put(dev_priv);
3c692a41 13753
ac21b225 13754 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13755}
13756
cf4c7c12 13757/**
4a3b8769
MR		 13758 * intel_plane_destroy - destroy a plane
13759 * @plane: plane to destroy
cf4c7c12 13760 *
4a3b8769
MR		 13761 * Common destruction function for all types of planes (primary, cursor,
13762 * sprite).
cf4c7c12 13763 */
4a3b8769 13764void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13765{
13766 struct intel_plane *intel_plane = to_intel_plane(plane);
13767 drm_plane_cleanup(plane);
13768 kfree(intel_plane);
13769}
13770
65a3fea0 13771const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13772 .update_plane = drm_atomic_helper_update_plane,
13773 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13774 .destroy = intel_plane_destroy,
c196e1d6 13775 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13776 .atomic_get_property = intel_plane_atomic_get_property,
13777 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13778 .atomic_duplicate_state = intel_plane_duplicate_state,
13779 .atomic_destroy_state = intel_plane_destroy_state,
13780
465c120c
MR		 13781};
13782
13783static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13784 int pipe)
13785{
13786 struct intel_plane *primary;
8e7d688b 13787 struct intel_plane_state *state;
465c120c
MR		 13788 const uint32_t *intel_primary_formats;
13789 int num_formats;
13790
13791 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13792 if (primary == NULL)
13793 return NULL;
13794
8e7d688b
MR		 13795 state = intel_create_plane_state(&primary->base);
13796 if (!state) {
ea2c67bb
MR		 13797 kfree(primary);
13798 return NULL;
13799 }
8e7d688b 13800 primary->base.state = &state->base;
ea2c67bb 13801
465c120c
MR		 13802 primary->can_scale = false;
13803 primary->max_downscale = 1;
6156a456
CK		 13804 if (INTEL_INFO(dev)->gen >= 9) {
13805 primary->can_scale = true;
af99ceda 13806 state->scaler_id = -1;
6156a456 13807 }
465c120c
MR		 13808 primary->pipe = pipe;
13809 primary->plane = pipe;
c59cb179
MR		 13810 primary->check_plane = intel_check_primary_plane;
13811 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13812 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13813 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13814 primary->plane = !pipe;
13815
6c0fd451
DL		 13816 if (INTEL_INFO(dev)->gen >= 9) {
13817 intel_primary_formats = skl_primary_formats;
13818 num_formats = ARRAY_SIZE(skl_primary_formats);
13819 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13820 intel_primary_formats = i965_primary_formats;
13821 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13822 } else {
13823 intel_primary_formats = i8xx_primary_formats;
13824 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13825 }
13826
13827 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13828 &intel_plane_funcs,
465c120c
MR		 13829 intel_primary_formats, num_formats,
13830 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13831
3b7a5119
SJ		 13832 if (INTEL_INFO(dev)->gen >= 4)
13833 intel_create_rotation_property(dev, primary);
48404c1e 13834
ea2c67bb
MR		 13835 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13836
465c120c
MR		 13837 return &primary->base;
13838}
13839
3b7a5119
SJ		 13840void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13841{
13842 if (!dev->mode_config.rotation_property) {
13843 unsigned long flags = BIT(DRM_ROTATE_0) |
13844 BIT(DRM_ROTATE_180);
13845
13846 if (INTEL_INFO(dev)->gen >= 9)
13847 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13848
13849 dev->mode_config.rotation_property =
13850 drm_mode_create_rotation_property(dev, flags);
13851 }
13852 if (dev->mode_config.rotation_property)
13853 drm_object_attach_property(&plane->base.base,
13854 dev->mode_config.rotation_property,
13855 plane->base.state->rotation);
13856}
13857
3d7d6510 13858static int
852e787c 13859intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13860 struct intel_crtc_state *crtc_state,
852e787c 13861 struct intel_plane_state *state)
3d7d6510 13862{
061e4b8d 13863 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13864 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13865 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13866 unsigned stride;
13867 int ret;
3d7d6510 13868
061e4b8d
ML		 13869 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13870 &state->dst, &state->clip,
3d7d6510
MR		 13871 DRM_PLANE_HELPER_NO_SCALING,
13872 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13873 true, true, &state->visible);
757f9a3e
GP		 13874 if (ret)
13875 return ret;
13876
757f9a3e
GP		 13877 /* if we want to turn off the cursor ignore width and height */
13878 if (!obj)
da20eabd 13879 return 0;
757f9a3e 13880
757f9a3e 13881 /* Check for which cursor types we support */
061e4b8d 13882 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13883 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13884 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13885 return -EINVAL;
13886 }
13887
ea2c67bb
MR		 13888 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13889 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13890 DRM_DEBUG_KMS("buffer is too small\n");
13891 return -ENOMEM;
13892 }
13893
3a656b54 13894 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13895 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13896 return -EINVAL;
32b7eeec
MR		 13897 }
13898
da20eabd 13899 return 0;
852e787c 13900}
3d7d6510 13901
a8ad0d8e
ML		 13902static void
13903intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13904 struct drm_crtc *crtc)
a8ad0d8e 13905{
a8ad0d8e
ML		 13906 intel_crtc_update_cursor(crtc, false);
13907}
13908
f4a2cf29 13909static void
852e787c
GP		 13910intel_commit_cursor_plane(struct drm_plane *plane,
13911 struct intel_plane_state *state)
13912{
2b875c22 13913 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13914 struct drm_device *dev = plane->dev;
13915 struct intel_crtc *intel_crtc;
2b875c22 13916 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13917 uint32_t addr;
852e787c 13918
ea2c67bb
MR		 13919 crtc = crtc ? crtc : plane->crtc;
13920 intel_crtc = to_intel_crtc(crtc);
13921
2b875c22 13922 plane->fb = state->base.fb;
ea2c67bb
MR		 13923 crtc->cursor_x = state->base.crtc_x;
13924 crtc->cursor_y = state->base.crtc_y;
13925
a912f12f
GP		 13926 if (intel_crtc->cursor_bo == obj)
13927 goto update;
4ed91096 13928
f4a2cf29 13929 if (!obj)
a912f12f 13930 addr = 0;
f4a2cf29 13931 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13932 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13933 else
a912f12f 13934 addr = obj->phys_handle->busaddr;
852e787c 13935
a912f12f
GP		 13936 intel_crtc->cursor_addr = addr;
13937 intel_crtc->cursor_bo = obj;
852e787c 13938
302d19ac 13939update:
a539205a 13940 if (crtc->state->active)
a912f12f 13941 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13942}
13943
3d7d6510
MR		 13944static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13945 int pipe)
13946{
13947 struct intel_plane *cursor;
8e7d688b 13948 struct intel_plane_state *state;
3d7d6510
MR		 13949
13950 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13951 if (cursor == NULL)
13952 return NULL;
13953
8e7d688b
MR		 13954 state = intel_create_plane_state(&cursor->base);
13955 if (!state) {
ea2c67bb
MR		 13956 kfree(cursor);
13957 return NULL;
13958 }
8e7d688b 13959 cursor->base.state = &state->base;
ea2c67bb 13960
3d7d6510
MR		 13961 cursor->can_scale = false;
13962 cursor->max_downscale = 1;
13963 cursor->pipe = pipe;
13964 cursor->plane = pipe;
c59cb179
MR		 13965 cursor->check_plane = intel_check_cursor_plane;
13966 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13967 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13968
13969 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13970 &intel_plane_funcs,
3d7d6510
MR		 13971 intel_cursor_formats,
13972 ARRAY_SIZE(intel_cursor_formats),
13973 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13974
13975 if (INTEL_INFO(dev)->gen >= 4) {
13976 if (!dev->mode_config.rotation_property)
13977 dev->mode_config.rotation_property =
13978 drm_mode_create_rotation_property(dev,
13979 BIT(DRM_ROTATE_0) |
13980 BIT(DRM_ROTATE_180));
13981 if (dev->mode_config.rotation_property)
13982 drm_object_attach_property(&cursor->base.base,
13983 dev->mode_config.rotation_property,
8e7d688b 13984 state->base.rotation);
4398ad45
VS		 13985 }
13986
af99ceda
CK		 13987 if (INTEL_INFO(dev)->gen >=9)
13988 state->scaler_id = -1;
13989
ea2c67bb
MR		 13990 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13991
3d7d6510
MR		 13992 return &cursor->base;
13993}
13994
549e2bfb
CK		 13995static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13996 struct intel_crtc_state *crtc_state)
13997{
13998 int i;
13999 struct intel_scaler *intel_scaler;
14000 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14001
14002 for (i = 0; i < intel_crtc->num_scalers; i++) {
14003 intel_scaler = &scaler_state->scalers[i];
14004 intel_scaler->in_use = 0;
549e2bfb
CK		 14005 intel_scaler->mode = PS_SCALER_MODE_DYN;
14006 }
14007
14008 scaler_state->scaler_id = -1;
14009}
14010
b358d0a6 14011static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14012{
fbee40df 14013 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14014 struct intel_crtc *intel_crtc;
f5de6e07 14015 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14016 struct drm_plane *primary = NULL;
14017 struct drm_plane *cursor = NULL;
465c120c 14018 int i, ret;
79e53945 14019
955382f3 14020 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14021 if (intel_crtc == NULL)
14022 return;
14023
f5de6e07
ACO		 14024 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14025 if (!crtc_state)
14026 goto fail;
550acefd
ACO		 14027 intel_crtc->config = crtc_state;
14028 intel_crtc->base.state = &crtc_state->base;
07878248 14029 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14030
549e2bfb
CK		 14031 /* initialize shared scalers */
14032 if (INTEL_INFO(dev)->gen >= 9) {
14033 if (pipe == PIPE_C)
14034 intel_crtc->num_scalers = 1;
14035 else
14036 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14037
14038 skl_init_scalers(dev, intel_crtc, crtc_state);
14039 }
14040
465c120c 14041 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14042 if (!primary)
14043 goto fail;
14044
14045 cursor = intel_cursor_plane_create(dev, pipe);
14046 if (!cursor)
14047 goto fail;
14048
465c120c 14049 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14050 cursor, &intel_crtc_funcs);
14051 if (ret)
14052 goto fail;
79e53945
JB		 14053
14054 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14055 for (i = 0; i < 256; i++) {
14056 intel_crtc->lut_r[i] = i;
14057 intel_crtc->lut_g[i] = i;
14058 intel_crtc->lut_b[i] = i;
14059 }
14060
1f1c2e24
VS		 14061 /*
14062 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14063 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14064 */
80824003
JB		 14065 intel_crtc->pipe = pipe;
14066 intel_crtc->plane = pipe;
3a77c4c4 14067 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14068 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14069 intel_crtc->plane = !pipe;
80824003
JB		 14070 }
14071
4b0e333e
CW		 14072 intel_crtc->cursor_base = ~0;
14073 intel_crtc->cursor_cntl = ~0;
dc41c154 14074 intel_crtc->cursor_size = ~0;
8d7849db 14075
22fd0fab
JB		 14076 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14077 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14078 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14079 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14080
79e53945 14081 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14082
14083 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14084 return;
14085
14086fail:
14087 if (primary)
14088 drm_plane_cleanup(primary);
14089 if (cursor)
14090 drm_plane_cleanup(cursor);
f5de6e07 14091 kfree(crtc_state);
3d7d6510 14092 kfree(intel_crtc);
79e53945
JB		 14093}
14094
752aa88a
JB		 14095enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14096{
14097 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14098 struct drm_device *dev = connector->base.dev;
752aa88a 14099
51fd371b 14100 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14101
d3babd3f 14102 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14103 return INVALID_PIPE;
14104
14105 return to_intel_crtc(encoder->crtc)->pipe;
14106}
14107
08d7b3d1 14108int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14109 struct drm_file *file)
08d7b3d1 14110{
08d7b3d1 14111 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14112 struct drm_crtc *drmmode_crtc;
c05422d5 14113 struct intel_crtc *crtc;
08d7b3d1 14114
7707e653 14115 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14116
7707e653 14117 if (!drmmode_crtc) {
08d7b3d1 14118 DRM_ERROR("no such CRTC id\n");
3f2c2057 14119 return -ENOENT;
08d7b3d1
CW		 14120 }
14121
7707e653 14122 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14123 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14124
c05422d5 14125 return 0;
08d7b3d1
CW		 14126}
14127
66a9278e 14128static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14129{
66a9278e
DV		 14130 struct drm_device *dev = encoder->base.dev;
14131 struct intel_encoder *source_encoder;
79e53945 14132 int index_mask = 0;
79e53945
JB		 14133 int entry = 0;
14134
b2784e15 14135 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14136 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14137 index_mask |= (1 << entry);
14138
79e53945
JB		 14139 entry++;
14140 }
4ef69c7a 14141
79e53945
JB		 14142 return index_mask;
14143}
14144
4d302442
CW		 14145static bool has_edp_a(struct drm_device *dev)
14146{
14147 struct drm_i915_private *dev_priv = dev->dev_private;
14148
14149 if (!IS_MOBILE(dev))
14150 return false;
14151
14152 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14153 return false;
14154
e3589908 14155 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14156 return false;
14157
14158 return true;
14159}
14160
84b4e042
JB		 14161static bool intel_crt_present(struct drm_device *dev)
14162{
14163 struct drm_i915_private *dev_priv = dev->dev_private;
14164
884497ed
DL		 14165 if (INTEL_INFO(dev)->gen >= 9)
14166 return false;
14167
cf404ce4 14168 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14169 return false;
14170
14171 if (IS_CHERRYVIEW(dev))
14172 return false;
14173
14174 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14175 return false;
14176
14177 return true;
14178}
14179
79e53945
JB		 14180static void intel_setup_outputs(struct drm_device *dev)
14181{
725e30ad 14182 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14183 struct intel_encoder *encoder;
cb0953d7 14184 bool dpd_is_edp = false;
79e53945 14185
c9093354 14186 intel_lvds_init(dev);
79e53945 14187
84b4e042 14188 if (intel_crt_present(dev))
79935fca 14189 intel_crt_init(dev);
cb0953d7 14190
c776eb2e
VK		 14191 if (IS_BROXTON(dev)) {
14192 /*
14193 * FIXME: Broxton doesn't support port detection via the
14194 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14195 * detect the ports.
14196 */
14197 intel_ddi_init(dev, PORT_A);
14198 intel_ddi_init(dev, PORT_B);
14199 intel_ddi_init(dev, PORT_C);
14200 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14201 int found;
14202
de31facd
JB		 14203 /*
14204 * Haswell uses DDI functions to detect digital outputs.
14205 * On SKL pre-D0 the strap isn't connected, so we assume
14206 * it's there.
14207 */
0e72a5b5 14208 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14209 /* WaIgnoreDDIAStrap: skl */
14210 if (found ||
14211 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14212 intel_ddi_init(dev, PORT_A);
14213
14214 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14215 * register */
14216 found = I915_READ(SFUSE_STRAP);
14217
14218 if (found & SFUSE_STRAP_DDIB_DETECTED)
14219 intel_ddi_init(dev, PORT_B);
14220 if (found & SFUSE_STRAP_DDIC_DETECTED)
14221 intel_ddi_init(dev, PORT_C);
14222 if (found & SFUSE_STRAP_DDID_DETECTED)
14223 intel_ddi_init(dev, PORT_D);
14224 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14225 int found;
5d8a7752 14226 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14227
14228 if (has_edp_a(dev))
14229 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14230
dc0fa718 14231 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14232 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14233 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14234 if (!found)
e2debe91 14235 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14236 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14237 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14238 }
14239
dc0fa718 14240 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14241 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14242
dc0fa718 14243 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14244 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14245
5eb08b69 14246 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14247 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14248
270b3042 14249 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14250 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14251 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14252 /*
14253 * The DP_DETECTED bit is the latched state of the DDC
14254 * SDA pin at boot. However since eDP doesn't require DDC
14255 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14256 * eDP ports may have been muxed to an alternate function.
14257 * Thus we can't rely on the DP_DETECTED bit alone to detect
14258 * eDP ports. Consult the VBT as well as DP_DETECTED to
14259 * detect eDP ports.
14260 */
d2182a66
VS		 14261 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14262 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14263 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14264 PORT_B);
e17ac6db
VS		 14265 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14266 intel_dp_is_edp(dev, PORT_B))
14267 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14268
d2182a66
VS		 14269 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14270 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14271 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14272 PORT_C);
e17ac6db
VS		 14273 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14274 intel_dp_is_edp(dev, PORT_C))
14275 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14276
9418c1f1 14277 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14278 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14279 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14280 PORT_D);
e17ac6db
VS		 14281 /* eDP not supported on port D, so don't check VBT */
14282 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14283 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14284 }
14285
3cfca973 14286 intel_dsi_init(dev);
103a196f 14287 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14288 bool found = false;
7d57382e 14289
e2debe91 14290 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14291 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14292 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14293 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14294 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14295 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14296 }
27185ae1 14297
e7281eab 14298 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14299 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14300 }
13520b05
KH		 14301
14302 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14303
e2debe91 14304 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14305 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14306 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14307 }
27185ae1 14308
e2debe91 14309 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14310
b01f2c3a
JB		 14311 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14312 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14313 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14314 }
e7281eab 14315 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14316 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14317 }
27185ae1 14318
b01f2c3a 14319 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14320 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14321 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14322 } else if (IS_GEN2(dev))
79e53945
JB		 14323 intel_dvo_init(dev);
14324
103a196f 14325 if (SUPPORTS_TV(dev))
79e53945
JB		 14326 intel_tv_init(dev);
14327
0bc12bcb 14328 intel_psr_init(dev);
7c8f8a70 14329
b2784e15 14330 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14331 encoder->base.possible_crtcs = encoder->crtc_mask;
14332 encoder->base.possible_clones =
66a9278e 14333 intel_encoder_clones(encoder);
79e53945 14334 }
47356eb6 14335
dde86e2d 14336 intel_init_pch_refclk(dev);
270b3042
DV		 14337
14338 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14339}
14340
14341static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14342{
60a5ca01 14343 struct drm_device *dev = fb->dev;
79e53945 14344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14345
ef2d633e 14346 drm_framebuffer_cleanup(fb);
60a5ca01 14347 mutex_lock(&dev->struct_mutex);
ef2d633e 14348 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14349 drm_gem_object_unreference(&intel_fb->obj->base);
14350 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14351 kfree(intel_fb);
14352}
14353
14354static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14355 struct drm_file *file,
79e53945
JB		 14356 unsigned int *handle)
14357{
14358 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14359 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14360
05394f39 14361 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14362}
14363
14364static const struct drm_framebuffer_funcs intel_fb_funcs = {
14365 .destroy = intel_user_framebuffer_destroy,
14366 .create_handle = intel_user_framebuffer_create_handle,
14367};
14368
b321803d
DL		 14369static
14370u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14371 uint32_t pixel_format)
14372{
14373 u32 gen = INTEL_INFO(dev)->gen;
14374
14375 if (gen >= 9) {
14376 /* "The stride in bytes must not exceed the of the size of 8K
14377 * pixels and 32K bytes."
14378 */
14379 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14380 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14381 return 32*1024;
14382 } else if (gen >= 4) {
14383 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14384 return 16*1024;
14385 else
14386 return 32*1024;
14387 } else if (gen >= 3) {
14388 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14389 return 8*1024;
14390 else
14391 return 16*1024;
14392 } else {
14393 /* XXX DSPC is limited to 4k tiled */
14394 return 8*1024;
14395 }
14396}
14397
b5ea642a
DV		 14398static int intel_framebuffer_init(struct drm_device *dev,
14399 struct intel_framebuffer *intel_fb,
14400 struct drm_mode_fb_cmd2 *mode_cmd,
14401 struct drm_i915_gem_object *obj)
79e53945 14402{
6761dd31 14403 unsigned int aligned_height;
79e53945 14404 int ret;
b321803d 14405 u32 pitch_limit, stride_alignment;
79e53945 14406
dd4916c5
DV		 14407 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14408
2a80eada
DV		 14409 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14410 /* Enforce that fb modifier and tiling mode match, but only for
14411 * X-tiled. This is needed for FBC. */
14412 if (!!(obj->tiling_mode == I915_TILING_X) !=
14413 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14414 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14415 return -EINVAL;
14416 }
14417 } else {
14418 if (obj->tiling_mode == I915_TILING_X)
14419 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14420 else if (obj->tiling_mode == I915_TILING_Y) {
14421 DRM_DEBUG("No Y tiling for legacy addfb\n");
14422 return -EINVAL;
14423 }
14424 }
14425
9a8f0a12
TU		 14426 /* Passed in modifier sanity checking. */
14427 switch (mode_cmd->modifier[0]) {
14428 case I915_FORMAT_MOD_Y_TILED:
14429 case I915_FORMAT_MOD_Yf_TILED:
14430 if (INTEL_INFO(dev)->gen < 9) {
14431 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14432 mode_cmd->modifier[0]);
14433 return -EINVAL;
14434 }
14435 case DRM_FORMAT_MOD_NONE:
14436 case I915_FORMAT_MOD_X_TILED:
14437 break;
14438 default:
c0f40428
JB		 14439 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14440 mode_cmd->modifier[0]);
57cd6508 14441 return -EINVAL;
c16ed4be 14442 }
57cd6508 14443
b321803d
DL		 14444 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14445 mode_cmd->pixel_format);
14446 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14447 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14448 mode_cmd->pitches[0], stride_alignment);
57cd6508 14449 return -EINVAL;
c16ed4be 14450 }
57cd6508 14451
b321803d
DL		 14452 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14453 mode_cmd->pixel_format);
a35cdaa0 14454 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14455 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14456 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14457 "tiled" : "linear",
a35cdaa0 14458 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14459 return -EINVAL;
c16ed4be 14460 }
5d7bd705 14461
2a80eada 14462 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14463 mode_cmd->pitches[0] != obj->stride) {
14464 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14465 mode_cmd->pitches[0], obj->stride);
5d7bd705 14466 return -EINVAL;
c16ed4be 14467 }
5d7bd705 14468
57779d06 14469 /* Reject formats not supported by any plane early. */
308e5bcb 14470 switch (mode_cmd->pixel_format) {
57779d06 14471 case DRM_FORMAT_C8:
04b3924d
VS		 14472 case DRM_FORMAT_RGB565:
14473 case DRM_FORMAT_XRGB8888:
14474 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14475 break;
14476 case DRM_FORMAT_XRGB1555:
c16ed4be 14477 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14478 DRM_DEBUG("unsupported pixel format: %s\n",
14479 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14480 return -EINVAL;
c16ed4be 14481 }
57779d06 14482 break;
57779d06 14483 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14484 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14485 DRM_DEBUG("unsupported pixel format: %s\n",
14486 drm_get_format_name(mode_cmd->pixel_format));
14487 return -EINVAL;
14488 }
14489 break;
14490 case DRM_FORMAT_XBGR8888:
04b3924d 14491 case DRM_FORMAT_XRGB2101010:
57779d06 14492 case DRM_FORMAT_XBGR2101010:
c16ed4be 14493 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14494 DRM_DEBUG("unsupported pixel format: %s\n",
14495 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14496 return -EINVAL;
c16ed4be 14497 }
b5626747 14498 break;
7531208b
DL		 14499 case DRM_FORMAT_ABGR2101010:
14500 if (!IS_VALLEYVIEW(dev)) {
14501 DRM_DEBUG("unsupported pixel format: %s\n",
14502 drm_get_format_name(mode_cmd->pixel_format));
14503 return -EINVAL;
14504 }
14505 break;
04b3924d
VS		 14506 case DRM_FORMAT_YUYV:
14507 case DRM_FORMAT_UYVY:
14508 case DRM_FORMAT_YVYU:
14509 case DRM_FORMAT_VYUY:
c16ed4be 14510 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14511 DRM_DEBUG("unsupported pixel format: %s\n",
14512 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14513 return -EINVAL;
c16ed4be 14514 }
57cd6508
CW		 14515 break;
14516 default:
4ee62c76
VS		 14517 DRM_DEBUG("unsupported pixel format: %s\n",
14518 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14519 return -EINVAL;
14520 }
14521
90f9a336
VS		 14522 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14523 if (mode_cmd->offsets[0] != 0)
14524 return -EINVAL;
14525
ec2c981e 14526 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14527 mode_cmd->pixel_format,
14528 mode_cmd->modifier[0]);
53155c0a
DV		 14529 /* FIXME drm helper for size checks (especially planar formats)? */
14530 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14531 return -EINVAL;
14532
c7d73f6a
DV		 14533 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14534 intel_fb->obj = obj;
80075d49 14535 intel_fb->obj->framebuffer_references++;
c7d73f6a 14536
79e53945
JB		 14537 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14538 if (ret) {
14539 DRM_ERROR("framebuffer init failed %d\n", ret);
14540 return ret;
14541 }
14542
79e53945
JB		 14543 return 0;
14544}
14545
79e53945
JB		 14546static struct drm_framebuffer *
14547intel_user_framebuffer_create(struct drm_device *dev,
14548 struct drm_file *filp,
308e5bcb 14549 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14550{
05394f39 14551 struct drm_i915_gem_object *obj;
79e53945 14552
308e5bcb
JB		 14553 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14554 mode_cmd->handles[0]));
c8725226 14555 if (&obj->base == NULL)
cce13ff7 14556 return ERR_PTR(-ENOENT);
79e53945 14557
d2dff872 14558 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14559}
14560
4520f53a 14561#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14562static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14563{
14564}
14565#endif
14566
79e53945 14567static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14568 .fb_create = intel_user_framebuffer_create,
0632fef6 14569 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14570 .atomic_check = intel_atomic_check,
14571 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14572 .atomic_state_alloc = intel_atomic_state_alloc,
14573 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14574};
14575
e70236a8
JB		 14576/* Set up chip specific display functions */
14577static void intel_init_display(struct drm_device *dev)
14578{
14579 struct drm_i915_private *dev_priv = dev->dev_private;
14580
ee9300bb
DV		 14581 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14582 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14583 else if (IS_CHERRYVIEW(dev))
14584 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14585 else if (IS_VALLEYVIEW(dev))
14586 dev_priv->display.find_dpll = vlv_find_best_dpll;
14587 else if (IS_PINEVIEW(dev))
14588 dev_priv->display.find_dpll = pnv_find_best_dpll;
14589 else
14590 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14591
bc8d7dff
DL		 14592 if (INTEL_INFO(dev)->gen >= 9) {
14593 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14594 dev_priv->display.get_initial_plane_config =
14595 skylake_get_initial_plane_config;
bc8d7dff
DL		 14596 dev_priv->display.crtc_compute_clock =
14597 haswell_crtc_compute_clock;
14598 dev_priv->display.crtc_enable = haswell_crtc_enable;
14599 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14600 dev_priv->display.update_primary_plane =
14601 skylake_update_primary_plane;
14602 } else if (HAS_DDI(dev)) {
0e8ffe1b 14603 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14604 dev_priv->display.get_initial_plane_config =
14605 ironlake_get_initial_plane_config;
797d0259
ACO		 14606 dev_priv->display.crtc_compute_clock =
14607 haswell_crtc_compute_clock;
4f771f10
PZ		 14608 dev_priv->display.crtc_enable = haswell_crtc_enable;
14609 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14610 dev_priv->display.update_primary_plane =
14611 ironlake_update_primary_plane;
09b4ddf9 14612 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14613 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14614 dev_priv->display.get_initial_plane_config =
14615 ironlake_get_initial_plane_config;
3fb37703
ACO		 14616 dev_priv->display.crtc_compute_clock =
14617 ironlake_crtc_compute_clock;
76e5a89c
DV		 14618 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14619 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14620 dev_priv->display.update_primary_plane =
14621 ironlake_update_primary_plane;
89b667f8
JB		 14622 } else if (IS_VALLEYVIEW(dev)) {
14623 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14624 dev_priv->display.get_initial_plane_config =
14625 i9xx_get_initial_plane_config;
d6dfee7a 14626 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14627 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14628 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14629 dev_priv->display.update_primary_plane =
14630 i9xx_update_primary_plane;
f564048e 14631 } else {
0e8ffe1b 14632 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14633 dev_priv->display.get_initial_plane_config =
14634 i9xx_get_initial_plane_config;
d6dfee7a 14635 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14636 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14637 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14638 dev_priv->display.update_primary_plane =
14639 i9xx_update_primary_plane;
f564048e 14640 }
e70236a8 14641
e70236a8 14642 /* Returns the core display clock speed */
1652d19e
VS		 14643 if (IS_SKYLAKE(dev))
14644 dev_priv->display.get_display_clock_speed =
14645 skylake_get_display_clock_speed;
acd3f3d3
BP		 14646 else if (IS_BROXTON(dev))
14647 dev_priv->display.get_display_clock_speed =
14648 broxton_get_display_clock_speed;
1652d19e
VS		 14649 else if (IS_BROADWELL(dev))
14650 dev_priv->display.get_display_clock_speed =
14651 broadwell_get_display_clock_speed;
14652 else if (IS_HASWELL(dev))
14653 dev_priv->display.get_display_clock_speed =
14654 haswell_get_display_clock_speed;
14655 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14656 dev_priv->display.get_display_clock_speed =
14657 valleyview_get_display_clock_speed;
b37a6434
VS		 14658 else if (IS_GEN5(dev))
14659 dev_priv->display.get_display_clock_speed =
14660 ilk_get_display_clock_speed;
a7c66cd8 14661 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14662 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14663 dev_priv->display.get_display_clock_speed =
14664 i945_get_display_clock_speed;
34edce2f
VS		 14665 else if (IS_GM45(dev))
14666 dev_priv->display.get_display_clock_speed =
14667 gm45_get_display_clock_speed;
14668 else if (IS_CRESTLINE(dev))
14669 dev_priv->display.get_display_clock_speed =
14670 i965gm_get_display_clock_speed;
14671 else if (IS_PINEVIEW(dev))
14672 dev_priv->display.get_display_clock_speed =
14673 pnv_get_display_clock_speed;
14674 else if (IS_G33(dev) || IS_G4X(dev))
14675 dev_priv->display.get_display_clock_speed =
14676 g33_get_display_clock_speed;
e70236a8
JB		 14677 else if (IS_I915G(dev))
14678 dev_priv->display.get_display_clock_speed =
14679 i915_get_display_clock_speed;
257a7ffc 14680 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14681 dev_priv->display.get_display_clock_speed =
14682 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14683 else if (IS_PINEVIEW(dev))
14684 dev_priv->display.get_display_clock_speed =
14685 pnv_get_display_clock_speed;
e70236a8
JB		 14686 else if (IS_I915GM(dev))
14687 dev_priv->display.get_display_clock_speed =
14688 i915gm_get_display_clock_speed;
14689 else if (IS_I865G(dev))
14690 dev_priv->display.get_display_clock_speed =
14691 i865_get_display_clock_speed;
f0f8a9ce 14692 else if (IS_I85X(dev))
e70236a8 14693 dev_priv->display.get_display_clock_speed =
1b1d2716 14694 i85x_get_display_clock_speed;
623e01e5
VS		 14695 else { /* 830 */
14696 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14697 dev_priv->display.get_display_clock_speed =
14698 i830_get_display_clock_speed;
623e01e5 14699 }
e70236a8 14700
7c10a2b5 14701 if (IS_GEN5(dev)) {
3bb11b53 14702 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14703 } else if (IS_GEN6(dev)) {
14704 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14705 } else if (IS_IVYBRIDGE(dev)) {
14706 /* FIXME: detect B0+ stepping and use auto training */
14707 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14708 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14709 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14710 if (IS_BROADWELL(dev)) {
14711 dev_priv->display.modeset_commit_cdclk =
14712 broadwell_modeset_commit_cdclk;
14713 dev_priv->display.modeset_calc_cdclk =
14714 broadwell_modeset_calc_cdclk;
14715 }
30a970c6 14716 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14717 dev_priv->display.modeset_commit_cdclk =
14718 valleyview_modeset_commit_cdclk;
14719 dev_priv->display.modeset_calc_cdclk =
14720 valleyview_modeset_calc_cdclk;
f8437dd1 14721 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14722 dev_priv->display.modeset_commit_cdclk =
14723 broxton_modeset_commit_cdclk;
14724 dev_priv->display.modeset_calc_cdclk =
14725 broxton_modeset_calc_cdclk;
e70236a8 14726 }
8c9f3aaf 14727
8c9f3aaf
JB		 14728 switch (INTEL_INFO(dev)->gen) {
14729 case 2:
14730 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14731 break;
14732
14733 case 3:
14734 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14735 break;
14736
14737 case 4:
14738 case 5:
14739 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14740 break;
14741
14742 case 6:
14743 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14744 break;
7c9017e5 14745 case 7:
4e0bbc31 14746 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14747 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14748 break;
830c81db 14749 case 9:
ba343e02
TU		 14750 /* Drop through - unsupported since execlist only. */
14751 default:
14752 /* Default just returns -ENODEV to indicate unsupported */
14753 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14754 }
7bd688cd
JN		 14755
14756 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14757
14758 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14759}
14760
b690e96c
JB		 14761/*
14762 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14763 * resume, or other times. This quirk makes sure that's the case for
14764 * affected systems.
14765 */
0206e353 14766static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14767{
14768 struct drm_i915_private *dev_priv = dev->dev_private;
14769
14770 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14771 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14772}
14773
b6b5d049
VS		 14774static void quirk_pipeb_force(struct drm_device *dev)
14775{
14776 struct drm_i915_private *dev_priv = dev->dev_private;
14777
14778 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14779 DRM_INFO("applying pipe b force quirk\n");
14780}
14781
435793df
KP		 14782/*
14783 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14784 */
14785static void quirk_ssc_force_disable(struct drm_device *dev)
14786{
14787 struct drm_i915_private *dev_priv = dev->dev_private;
14788 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14789 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14790}
14791
4dca20ef 14792/*
5a15ab5b
CE		 14793 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14794 * brightness value
4dca20ef
CE		 14795 */
14796static void quirk_invert_brightness(struct drm_device *dev)
14797{
14798 struct drm_i915_private *dev_priv = dev->dev_private;
14799 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14800 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14801}
14802
9c72cc6f
SD		 14803/* Some VBT's incorrectly indicate no backlight is present */
14804static void quirk_backlight_present(struct drm_device *dev)
14805{
14806 struct drm_i915_private *dev_priv = dev->dev_private;
14807 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14808 DRM_INFO("applying backlight present quirk\n");
14809}
14810
b690e96c
JB		 14811struct intel_quirk {
14812 int device;
14813 int subsystem_vendor;
14814 int subsystem_device;
14815 void (*hook)(struct drm_device *dev);
14816};
14817
5f85f176
EE		 14818/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14819struct intel_dmi_quirk {
14820 void (*hook)(struct drm_device *dev);
14821 const struct dmi_system_id (*dmi_id_list)[];
14822};
14823
14824static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14825{
14826 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14827 return 1;
14828}
14829
14830static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14831 {
14832 .dmi_id_list = &(const struct dmi_system_id[]) {
14833 {
14834 .callback = intel_dmi_reverse_brightness,
14835 .ident = "NCR Corporation",
14836 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14837 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14838 },
14839 },
14840 { } /* terminating entry */
14841 },
14842 .hook = quirk_invert_brightness,
14843 },
14844};
14845
c43b5634 14846static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14847 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14848 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14849
b690e96c
JB		 14850 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14851 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14852
5f080c0f
VS		 14853 /* 830 needs to leave pipe A & dpll A up */
14854 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14855
b6b5d049
VS		 14856 /* 830 needs to leave pipe B & dpll B up */
14857 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14858
435793df
KP		 14859 /* Lenovo U160 cannot use SSC on LVDS */
14860 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14861
14862 /* Sony Vaio Y cannot use SSC on LVDS */
14863 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14864
be505f64
AH		 14865 /* Acer Aspire 5734Z must invert backlight brightness */
14866 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14867
14868 /* Acer/eMachines G725 */
14869 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14870
14871 /* Acer/eMachines e725 */
14872 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14873
14874 /* Acer/Packard Bell NCL20 */
14875 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14876
14877 /* Acer Aspire 4736Z */
14878 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14879
14880 /* Acer Aspire 5336 */
14881 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14882
14883 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14884 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14885
dfb3d47b
SD		 14886 /* Acer C720 Chromebook (Core i3 4005U) */
14887 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14888
b2a9601c 14889 /* Apple Macbook 2,1 (Core 2 T7400) */
14890 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14891
d4967d8c
SD		 14892 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14893 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14894
14895 /* HP Chromebook 14 (Celeron 2955U) */
14896 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14897
14898 /* Dell Chromebook 11 */
14899 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14900};
14901
14902static void intel_init_quirks(struct drm_device *dev)
14903{
14904 struct pci_dev *d = dev->pdev;
14905 int i;
14906
14907 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14908 struct intel_quirk *q = &intel_quirks[i];
14909
14910 if (d->device == q->device &&
14911 (d->subsystem_vendor == q->subsystem_vendor ||
14912 q->subsystem_vendor == PCI_ANY_ID) &&
14913 (d->subsystem_device == q->subsystem_device ||
14914 q->subsystem_device == PCI_ANY_ID))
14915 q->hook(dev);
14916 }
5f85f176
EE		 14917 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14918 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14919 intel_dmi_quirks[i].hook(dev);
14920 }
b690e96c
JB		 14921}
14922
9cce37f4
JB		 14923/* Disable the VGA plane that we never use */
14924static void i915_disable_vga(struct drm_device *dev)
14925{
14926 struct drm_i915_private *dev_priv = dev->dev_private;
14927 u8 sr1;
766aa1c4 14928 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14929
2b37c616 14930 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14931 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14932 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14933 sr1 = inb(VGA_SR_DATA);
14934 outb(sr1 | 1<<5, VGA_SR_DATA);
14935 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14936 udelay(300);
14937
01f5a626 14938 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14939 POSTING_READ(vga_reg);
14940}
14941
f817586c
DV		 14942void intel_modeset_init_hw(struct drm_device *dev)
14943{
b6283055 14944 intel_update_cdclk(dev);
a8f78b58 14945 intel_prepare_ddi(dev);
f817586c 14946 intel_init_clock_gating(dev);
8090c6b9 14947 intel_enable_gt_powersave(dev);
f817586c
DV		 14948}
14949
79e53945
JB		 14950void intel_modeset_init(struct drm_device *dev)
14951{
652c393a 14952 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14953 int sprite, ret;
8cc87b75 14954 enum pipe pipe;
46f297fb 14955 struct intel_crtc *crtc;
79e53945
JB		 14956
14957 drm_mode_config_init(dev);
14958
14959 dev->mode_config.min_width = 0;
14960 dev->mode_config.min_height = 0;
14961
019d96cb
DA		 14962 dev->mode_config.preferred_depth = 24;
14963 dev->mode_config.prefer_shadow = 1;
14964
25bab385
TU		 14965 dev->mode_config.allow_fb_modifiers = true;
14966
e6ecefaa 14967 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14968
b690e96c
JB		 14969 intel_init_quirks(dev);
14970
1fa61106
ED		 14971 intel_init_pm(dev);
14972
e3c74757
BW		 14973 if (INTEL_INFO(dev)->num_pipes == 0)
14974 return;
14975
e70236a8 14976 intel_init_display(dev);
7c10a2b5 14977 intel_init_audio(dev);
e70236a8 14978
a6c45cf0
CW		 14979 if (IS_GEN2(dev)) {
14980 dev->mode_config.max_width = 2048;
14981 dev->mode_config.max_height = 2048;
14982 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14983 dev->mode_config.max_width = 4096;
14984 dev->mode_config.max_height = 4096;
79e53945 14985 } else {
a6c45cf0
CW		 14986 dev->mode_config.max_width = 8192;
14987 dev->mode_config.max_height = 8192;
79e53945 14988 }
068be561 14989
dc41c154
VS		 14990 if (IS_845G(dev) || IS_I865G(dev)) {
14991 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14992 dev->mode_config.cursor_height = 1023;
14993 } else if (IS_GEN2(dev)) {
068be561
DL		 14994 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14995 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14996 } else {
14997 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14998 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14999 }
15000
5d4545ae 15001 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15002
28c97730 15003 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15004 INTEL_INFO(dev)->num_pipes,
15005 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15006
055e393f 15007 for_each_pipe(dev_priv, pipe) {
8cc87b75 15008 intel_crtc_init(dev, pipe);
3bdcfc0c 15009 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15010 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15011 if (ret)
06da8da2 15012 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15013 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15014 }
79e53945
JB		 15015 }
15016
f42bb70d
JB		 15017 intel_init_dpio(dev);
15018
e72f9fbf 15019 intel_shared_dpll_init(dev);
ee7b9f93 15020
9cce37f4
JB		 15021 /* Just disable it once at startup */
15022 i915_disable_vga(dev);
79e53945 15023 intel_setup_outputs(dev);
11be49eb
CW		 15024
15025 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15026 intel_fbc_disable(dev);
fa9fa083 15027
6e9f798d 15028 drm_modeset_lock_all(dev);
fa9fa083 15029 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15030 drm_modeset_unlock_all(dev);
46f297fb 15031
d3fcc808 15032 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15033 if (!crtc->active)
15034 continue;
15035
46f297fb 15036 /*
46f297fb
JB		 15037 * Note that reserving the BIOS fb up front prevents us
15038 * from stuffing other stolen allocations like the ring
15039 * on top. This prevents some ugliness at boot time, and
15040 * can even allow for smooth boot transitions if the BIOS
15041 * fb is large enough for the active pipe configuration.
15042 */
5724dbd1
DL		 15043 if (dev_priv->display.get_initial_plane_config) {
15044 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15045 &crtc->plane_config);
15046 /*
15047 * If the fb is shared between multiple heads, we'll
15048 * just get the first one.
15049 */
f6936e29 15050 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15051 }
46f297fb 15052 }
2c7111db
CW		 15053}
15054
7fad798e
DV		 15055static void intel_enable_pipe_a(struct drm_device *dev)
15056{
15057 struct intel_connector *connector;
15058 struct drm_connector *crt = NULL;
15059 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15060 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15061
15062 /* We can't just switch on the pipe A, we need to set things up with a
15063 * proper mode and output configuration. As a gross hack, enable pipe A
15064 * by enabling the load detect pipe once. */
3a3371ff 15065 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15066 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15067 crt = &connector->base;
15068 break;
15069 }
15070 }
15071
15072 if (!crt)
15073 return;
15074
208bf9fd 15075 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15076 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15077}
15078
fa555837
DV		 15079static bool
15080intel_check_plane_mapping(struct intel_crtc *crtc)
15081{
7eb552ae
BW		 15082 struct drm_device *dev = crtc->base.dev;
15083 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15084 u32 reg, val;
15085
7eb552ae 15086 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15087 return true;
15088
15089 reg = DSPCNTR(!crtc->plane);
15090 val = I915_READ(reg);
15091
15092 if ((val & DISPLAY_PLANE_ENABLE) &&
15093 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15094 return false;
15095
15096 return true;
15097}
15098
24929352
DV		 15099static void intel_sanitize_crtc(struct intel_crtc *crtc)
15100{
15101 struct drm_device *dev = crtc->base.dev;
15102 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15103 struct intel_encoder *encoder;
fa555837 15104 u32 reg;
b17d48e2 15105 bool enable;
24929352 15106
24929352 15107 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15108 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15109 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15110
d3eaf884 15111 /* restore vblank interrupts to correct state */
9625604c 15112 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15113 if (crtc->active) {
15114 update_scanline_offset(crtc);
9625604c
DV		 15115 drm_crtc_vblank_on(&crtc->base);
15116 }
d3eaf884 15117
24929352 15118 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15119 * disable the crtc (and hence change the state) if it is wrong. Note
15120 * that gen4+ has a fixed plane -> pipe mapping. */
15121 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15122 bool plane;
15123
24929352
DV		 15124 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15125 crtc->base.base.id);
15126
15127 /* Pipe has the wrong plane attached and the plane is active.
15128 * Temporarily change the plane mapping and disable everything
15129 * ... */
15130 plane = crtc->plane;
b70709a6 15131 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15132 crtc->plane = !plane;
b17d48e2 15133 intel_crtc_disable_noatomic(&crtc->base);
24929352 15134 crtc->plane = plane;
24929352 15135 }
24929352 15136
7fad798e
DV		 15137 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15138 crtc->pipe == PIPE_A && !crtc->active) {
15139 /* BIOS forgot to enable pipe A, this mostly happens after
15140 * resume. Force-enable the pipe to fix this, the update_dpms
15141 * call below we restore the pipe to the right state, but leave
15142 * the required bits on. */
15143 intel_enable_pipe_a(dev);
15144 }
15145
24929352
DV		 15146 /* Adjust the state of the output pipe according to whether we
15147 * have active connectors/encoders. */
b17d48e2
ML		 15148 enable = false;
15149 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15150 enable |= encoder->connectors_active;
24929352 15151
b17d48e2
ML		 15152 if (!enable)
15153 intel_crtc_disable_noatomic(&crtc->base);
24929352 15154
53d9f4e9 15155 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15156
15157 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15158 * functions or because of calls to intel_crtc_disable_noatomic,
15159 * or because the pipe is force-enabled due to the
24929352
DV		 15160 * pipe A quirk. */
15161 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15162 crtc->base.base.id,
83d65738 15163 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15164 crtc->active ? "enabled" : "disabled");
15165
83d65738 15166 crtc->base.state->enable = crtc->active;
49d6fa21 15167 crtc->base.state->active = crtc->active;
24929352
DV		 15168 crtc->base.enabled = crtc->active;
15169
15170 /* Because we only establish the connector -> encoder ->
15171 * crtc links if something is active, this means the
15172 * crtc is now deactivated. Break the links. connector
15173 * -> encoder links are only establish when things are
15174 * actually up, hence no need to break them. */
15175 WARN_ON(crtc->active);
15176
15177 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15178 WARN_ON(encoder->connectors_active);
15179 encoder->base.crtc = NULL;
15180 }
15181 }
c5ab3bc0 15182
a3ed6aad 15183 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15184 /*
15185 * We start out with underrun reporting disabled to avoid races.
15186 * For correct bookkeeping mark this on active crtcs.
15187 *
c5ab3bc0
DV		 15188 * Also on gmch platforms we dont have any hardware bits to
15189 * disable the underrun reporting. Which means we need to start
15190 * out with underrun reporting disabled also on inactive pipes,
15191 * since otherwise we'll complain about the garbage we read when
15192 * e.g. coming up after runtime pm.
15193 *
4cc31489
DV		 15194 * No protection against concurrent access is required - at
15195 * worst a fifo underrun happens which also sets this to false.
15196 */
15197 crtc->cpu_fifo_underrun_disabled = true;
15198 crtc->pch_fifo_underrun_disabled = true;
15199 }
24929352
DV		 15200}
15201
15202static void intel_sanitize_encoder(struct intel_encoder *encoder)
15203{
15204 struct intel_connector *connector;
15205 struct drm_device *dev = encoder->base.dev;
15206
15207 /* We need to check both for a crtc link (meaning that the
15208 * encoder is active and trying to read from a pipe) and the
15209 * pipe itself being active. */
15210 bool has_active_crtc = encoder->base.crtc &&
15211 to_intel_crtc(encoder->base.crtc)->active;
15212
15213 if (encoder->connectors_active && !has_active_crtc) {
15214 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15215 encoder->base.base.id,
8e329a03 15216 encoder->base.name);
24929352
DV		 15217
15218 /* Connector is active, but has no active pipe. This is
15219 * fallout from our resume register restoring. Disable
15220 * the encoder manually again. */
15221 if (encoder->base.crtc) {
15222 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15223 encoder->base.base.id,
8e329a03 15224 encoder->base.name);
24929352 15225 encoder->disable(encoder);
a62d1497
VS		 15226 if (encoder->post_disable)
15227 encoder->post_disable(encoder);
24929352 15228 }
7f1950fb
EE		 15229 encoder->base.crtc = NULL;
15230 encoder->connectors_active = false;
24929352
DV		 15231
15232 /* Inconsistent output/port/pipe state happens presumably due to
15233 * a bug in one of the get_hw_state functions. Or someplace else
15234 * in our code, like the register restore mess on resume. Clamp
15235 * things to off as a safer default. */
3a3371ff 15236 for_each_intel_connector(dev, connector) {
24929352
DV		 15237 if (connector->encoder != encoder)
15238 continue;
7f1950fb
EE		 15239 connector->base.dpms = DRM_MODE_DPMS_OFF;
15240 connector->base.encoder = NULL;
24929352
DV		 15241 }
15242 }
15243 /* Enabled encoders without active connectors will be fixed in
15244 * the crtc fixup. */
15245}
15246
04098753 15247void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15248{
15249 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15250 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15251
04098753
ID		 15252 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15253 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15254 i915_disable_vga(dev);
15255 }
15256}
15257
15258void i915_redisable_vga(struct drm_device *dev)
15259{
15260 struct drm_i915_private *dev_priv = dev->dev_private;
15261
8dc8a27c
PZ		 15262 /* This function can be called both from intel_modeset_setup_hw_state or
15263 * at a very early point in our resume sequence, where the power well
15264 * structures are not yet restored. Since this function is at a very
15265 * paranoid "someone might have enabled VGA while we were not looking"
15266 * level, just check if the power well is enabled instead of trying to
15267 * follow the "don't touch the power well if we don't need it" policy
15268 * the rest of the driver uses. */
f458ebbc 15269 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15270 return;
15271
04098753 15272 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15273}
15274
98ec7739
VS		 15275static bool primary_get_hw_state(struct intel_crtc *crtc)
15276{
15277 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15278
d032ffa0
ML		 15279 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15280}
15281
15282static void readout_plane_state(struct intel_crtc *crtc,
15283 struct intel_crtc_state *crtc_state)
15284{
15285 struct intel_plane *p;
15286 struct drm_plane_state *drm_plane_state;
15287 bool active = crtc_state->base.active;
15288
15289 if (active) {
15290 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15291
15292 /* apply to previous sw state too */
15293 to_intel_crtc_state(crtc->base.state)->quirks |=
15294 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15295 }
98ec7739 15296
d032ffa0
ML		 15297 for_each_intel_plane(crtc->base.dev, p) {
15298 bool visible = active;
15299
15300 if (crtc->pipe != p->pipe)
15301 continue;
15302
15303 drm_plane_state = p->base.state;
15304 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15305 visible = primary_get_hw_state(crtc);
15306 to_intel_plane_state(drm_plane_state)->visible = visible;
15307 } else {
15308 /*
15309 * unknown state, assume it's off to force a transition
15310 * to on when calculating state changes.
15311 */
15312 to_intel_plane_state(drm_plane_state)->visible = false;
15313 }
15314
15315 if (visible) {
15316 crtc_state->base.plane_mask |=
15317 1 << drm_plane_index(&p->base);
15318 } else if (crtc_state->base.state) {
15319 /* Make this unconditional for atomic hw readout. */
15320 crtc_state->base.plane_mask &=
15321 ~(1 << drm_plane_index(&p->base));
15322 }
15323 }
98ec7739
VS		 15324}
15325
30e984df 15326static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15327{
15328 struct drm_i915_private *dev_priv = dev->dev_private;
15329 enum pipe pipe;
24929352
DV		 15330 struct intel_crtc *crtc;
15331 struct intel_encoder *encoder;
15332 struct intel_connector *connector;
5358901f 15333 int i;
24929352 15334
d3fcc808 15335 for_each_intel_crtc(dev, crtc) {
6e3c9717 15336 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15337 crtc->config->base.crtc = &crtc->base;
3b117c8f 15338
6e3c9717 15339 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15340
0e8ffe1b 15341 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15342 crtc->config);
24929352 15343
83d65738 15344 crtc->base.state->enable = crtc->active;
49d6fa21 15345 crtc->base.state->active = crtc->active;
24929352 15346 crtc->base.enabled = crtc->active;
b8b7fade 15347 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6 15348
d032ffa0 15349 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15350
15351 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15352 crtc->base.base.id,
15353 crtc->active ? "enabled" : "disabled");
15354 }
15355
5358901f
DV		 15356 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15357 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15358
3e369b76
ACO		 15359 pll->on = pll->get_hw_state(dev_priv, pll,
15360 &pll->config.hw_state);
5358901f 15361 pll->active = 0;
3e369b76 15362 pll->config.crtc_mask = 0;
d3fcc808 15363 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15364 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15365 pll->active++;
3e369b76 15366 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15367 }
5358901f 15368 }
5358901f 15369
1e6f2ddc 15370 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15371 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15372
3e369b76 15373 if (pll->config.crtc_mask)
bd2bb1b9 15374 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15375 }
15376
b2784e15 15377 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15378 pipe = 0;
15379
15380 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15381 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15382 encoder->base.crtc = &crtc->base;
6e3c9717 15383 encoder->get_config(encoder, crtc->config);
24929352
DV		 15384 } else {
15385 encoder->base.crtc = NULL;
15386 }
15387
15388 encoder->connectors_active = false;
6f2bcceb 15389 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15390 encoder->base.base.id,
8e329a03 15391 encoder->base.name,
24929352 15392 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15393 pipe_name(pipe));
24929352
DV		 15394 }
15395
3a3371ff 15396 for_each_intel_connector(dev, connector) {
24929352
DV		 15397 if (connector->get_hw_state(connector)) {
15398 connector->base.dpms = DRM_MODE_DPMS_ON;
15399 connector->encoder->connectors_active = true;
15400 connector->base.encoder = &connector->encoder->base;
15401 } else {
15402 connector->base.dpms = DRM_MODE_DPMS_OFF;
15403 connector->base.encoder = NULL;
15404 }
15405 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15406 connector->base.base.id,
c23cc417 15407 connector->base.name,
24929352
DV		 15408 connector->base.encoder ? "enabled" : "disabled");
15409 }
30e984df
DV		 15410}
15411
15412/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15413 * and i915 state tracking structures. */
15414void intel_modeset_setup_hw_state(struct drm_device *dev,
15415 bool force_restore)
15416{
15417 struct drm_i915_private *dev_priv = dev->dev_private;
15418 enum pipe pipe;
30e984df
DV		 15419 struct intel_crtc *crtc;
15420 struct intel_encoder *encoder;
35c95375 15421 int i;
30e984df
DV		 15422
15423 intel_modeset_readout_hw_state(dev);
24929352 15424
babea61d
JB		 15425 /*
15426 * Now that we have the config, copy it to each CRTC struct
15427 * Note that this could go away if we move to using crtc_config
15428 * checking everywhere.
15429 */
d3fcc808 15430 for_each_intel_crtc(dev, crtc) {
d330a953 15431 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15432 intel_mode_from_pipe_config(&crtc->base.mode,
15433 crtc->config);
babea61d
JB		 15434 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15435 crtc->base.base.id);
15436 drm_mode_debug_printmodeline(&crtc->base.mode);
15437 }
15438 }
15439
24929352 15440 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15441 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15442 intel_sanitize_encoder(encoder);
15443 }
15444
055e393f 15445 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15446 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15447 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15448 intel_dump_pipe_config(crtc, crtc->config,
15449 "[setup_hw_state]");
24929352 15450 }
9a935856 15451
d29b2f9d
ACO		 15452 intel_modeset_update_connector_atomic_state(dev);
15453
35c95375
DV		 15454 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15455 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15456
15457 if (!pll->on || pll->active)
15458 continue;
15459
15460 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15461
15462 pll->disable(dev_priv, pll);
15463 pll->on = false;
15464 }
15465
3078999f
PB		 15466 if (IS_GEN9(dev))
15467 skl_wm_get_hw_state(dev);
15468 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15469 ilk_wm_get_hw_state(dev);
15470
45e2b5f6 15471 if (force_restore) {
7d0bc1ea
VS		 15472 i915_redisable_vga(dev);
15473
f30da187
DV		 15474 /*
15475 * We need to use raw interfaces for restoring state to avoid
15476 * checking (bogus) intermediate states.
15477 */
055e393f 15478 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15479 struct drm_crtc *crtc =
15480 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15481
83a57153 15482 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15483 }
15484 } else {
15485 intel_modeset_update_staged_output_state(dev);
15486 }
8af6cf88
DV		 15487
15488 intel_modeset_check_state(dev);
2c7111db
CW		 15489}
15490
15491void intel_modeset_gem_init(struct drm_device *dev)
15492{
92122789 15493 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15494 struct drm_crtc *c;
2ff8fde1 15495 struct drm_i915_gem_object *obj;
e0d6149b 15496 int ret;
484b41dd 15497
ae48434c
ID		 15498 mutex_lock(&dev->struct_mutex);
15499 intel_init_gt_powersave(dev);
15500 mutex_unlock(&dev->struct_mutex);
15501
92122789
JB		 15502 /*
15503 * There may be no VBT; and if the BIOS enabled SSC we can
15504 * just keep using it to avoid unnecessary flicker. Whereas if the
15505 * BIOS isn't using it, don't assume it will work even if the VBT
15506 * indicates as much.
15507 */
15508 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15509 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15510 DREF_SSC1_ENABLE);
15511
1833b134 15512 intel_modeset_init_hw(dev);
02e792fb
DV		 15513
15514 intel_setup_overlay(dev);
484b41dd
JB		 15515
15516 /*
15517 * Make sure any fbs we allocated at startup are properly
15518 * pinned & fenced. When we do the allocation it's too early
15519 * for this.
15520 */
70e1e0ec 15521 for_each_crtc(dev, c) {
2ff8fde1
MR		 15522 obj = intel_fb_obj(c->primary->fb);
15523 if (obj == NULL)
484b41dd
JB		 15524 continue;
15525
e0d6149b
TU		 15526 mutex_lock(&dev->struct_mutex);
15527 ret = intel_pin_and_fence_fb_obj(c->primary,
15528 c->primary->fb,
15529 c->primary->state,
91af127f 15530 NULL, NULL);
e0d6149b
TU		 15531 mutex_unlock(&dev->struct_mutex);
15532 if (ret) {
484b41dd
JB		 15533 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15534 to_intel_crtc(c)->pipe);
66e514c1
DA		 15535 drm_framebuffer_unreference(c->primary->fb);
15536 c->primary->fb = NULL;
36750f28 15537 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15538 update_state_fb(c->primary);
36750f28 15539 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15540 }
15541 }
0962c3c9
VS		 15542
15543 intel_backlight_register(dev);
79e53945
JB		 15544}
15545
4932e2c3
ID		 15546void intel_connector_unregister(struct intel_connector *intel_connector)
15547{
15548 struct drm_connector *connector = &intel_connector->base;
15549
15550 intel_panel_destroy_backlight(connector);
34ea3d38 15551 drm_connector_unregister(connector);
4932e2c3
ID		 15552}
15553
79e53945
JB		 15554void intel_modeset_cleanup(struct drm_device *dev)
15555{
652c393a 15556 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15557 struct drm_connector *connector;
652c393a 15558
2eb5252e
ID		 15559 intel_disable_gt_powersave(dev);
15560
0962c3c9
VS		 15561 intel_backlight_unregister(dev);
15562
fd0c0642
DV		 15563 /*
15564 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15565 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15566 * experience fancy races otherwise.
15567 */
2aeb7d3a 15568 intel_irq_uninstall(dev_priv);
eb21b92b 15569
fd0c0642
DV		 15570 /*
15571 * Due to the hpd irq storm handling the hotplug work can re-arm the
15572 * poll handlers. Hence disable polling after hpd handling is shut down.
15573 */
f87ea761 15574 drm_kms_helper_poll_fini(dev);
fd0c0642 15575
652c393a
JB		 15576 mutex_lock(&dev->struct_mutex);
15577
723bfd70
JB		 15578 intel_unregister_dsm_handler();
15579
7ff0ebcc 15580 intel_fbc_disable(dev);
e70236a8 15581
69341a5e
KH		 15582 mutex_unlock(&dev->struct_mutex);
15583
1630fe75
CW		 15584 /* flush any delayed tasks or pending work */
15585 flush_scheduled_work();
15586
db31af1d
JN		 15587 /* destroy the backlight and sysfs files before encoders/connectors */
15588 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15589 struct intel_connector *intel_connector;
15590
15591 intel_connector = to_intel_connector(connector);
15592 intel_connector->unregister(intel_connector);
db31af1d 15593 }
d9255d57 15594
79e53945 15595 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15596
15597 intel_cleanup_overlay(dev);
ae48434c
ID		 15598
15599 mutex_lock(&dev->struct_mutex);
15600 intel_cleanup_gt_powersave(dev);
15601 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15602}
15603
f1c79df3
ZW		 15604/*
15605 * Return which encoder is currently attached for connector.
15606 */
df0e9248 15607struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15608{
df0e9248
CW		 15609 return &intel_attached_encoder(connector)->base;
15610}
f1c79df3 15611
df0e9248
CW		 15612void intel_connector_attach_encoder(struct intel_connector *connector,
15613 struct intel_encoder *encoder)
15614{
15615 connector->encoder = encoder;
15616 drm_mode_connector_attach_encoder(&connector->base,
15617 &encoder->base);
79e53945 15618}
28d52043
DA		 15619
15620/*
15621 * set vga decode state - true == enable VGA decode
15622 */
15623int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15624{
15625 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15626 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15627 u16 gmch_ctrl;
15628
75fa041d
CW		 15629 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15630 DRM_ERROR("failed to read control word\n");
15631 return -EIO;
15632 }
15633
c0cc8a55
CW		 15634 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15635 return 0;
15636
28d52043
DA		 15637 if (state)
15638 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15639 else
15640 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15641
15642 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15643 DRM_ERROR("failed to write control word\n");
15644 return -EIO;
15645 }
15646
28d52043
DA		 15647 return 0;
15648}
c4a1d9e4 15649
c4a1d9e4 15650struct intel_display_error_state {
ff57f1b0
PZ		 15651
15652 u32 power_well_driver;
15653
63b66e5b
CW		 15654 int num_transcoders;
15655
c4a1d9e4
CW		 15656 struct intel_cursor_error_state {
15657 u32 control;
15658 u32 position;
15659 u32 base;
15660 u32 size;
52331309 15661 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15662
15663 struct intel_pipe_error_state {
ddf9c536 15664 bool power_domain_on;
c4a1d9e4 15665 u32 source;
f301b1e1 15666 u32 stat;
52331309 15667 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15668
15669 struct intel_plane_error_state {
15670 u32 control;
15671 u32 stride;
15672 u32 size;
15673 u32 pos;
15674 u32 addr;
15675 u32 surface;
15676 u32 tile_offset;
52331309 15677 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15678
15679 struct intel_transcoder_error_state {
ddf9c536 15680 bool power_domain_on;
63b66e5b
CW		 15681 enum transcoder cpu_transcoder;
15682
15683 u32 conf;
15684
15685 u32 htotal;
15686 u32 hblank;
15687 u32 hsync;
15688 u32 vtotal;
15689 u32 vblank;
15690 u32 vsync;
15691 } transcoder[4];
c4a1d9e4
CW		 15692};
15693
15694struct intel_display_error_state *
15695intel_display_capture_error_state(struct drm_device *dev)
15696{
fbee40df 15697 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15698 struct intel_display_error_state *error;
63b66e5b
CW		 15699 int transcoders[] = {
15700 TRANSCODER_A,
15701 TRANSCODER_B,
15702 TRANSCODER_C,
15703 TRANSCODER_EDP,
15704 };
c4a1d9e4
CW		 15705 int i;
15706
63b66e5b
CW		 15707 if (INTEL_INFO(dev)->num_pipes == 0)
15708 return NULL;
15709
9d1cb914 15710 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15711 if (error == NULL)
15712 return NULL;
15713
190be112 15714 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15715 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15716
055e393f 15717 for_each_pipe(dev_priv, i) {
ddf9c536 15718 error->pipe[i].power_domain_on =
f458ebbc
DV		 15719 __intel_display_power_is_enabled(dev_priv,
15720 POWER_DOMAIN_PIPE(i));
ddf9c536 15721 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15722 continue;
15723
5efb3e28
VS		 15724 error->cursor[i].control = I915_READ(CURCNTR(i));
15725 error->cursor[i].position = I915_READ(CURPOS(i));
15726 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15727
15728 error->plane[i].control = I915_READ(DSPCNTR(i));
15729 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15730 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15731 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15732 error->plane[i].pos = I915_READ(DSPPOS(i));
15733 }
ca291363
PZ		 15734 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15735 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15736 if (INTEL_INFO(dev)->gen >= 4) {
15737 error->plane[i].surface = I915_READ(DSPSURF(i));
15738 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15739 }
15740
c4a1d9e4 15741 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15742
3abfce77 15743 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15744 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15745 }
15746
15747 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15748 if (HAS_DDI(dev_priv->dev))
15749 error->num_transcoders++; /* Account for eDP. */
15750
15751 for (i = 0; i < error->num_transcoders; i++) {
15752 enum transcoder cpu_transcoder = transcoders[i];
15753
ddf9c536 15754 error->transcoder[i].power_domain_on =
f458ebbc 15755 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15756 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15757 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15758 continue;
15759
63b66e5b
CW		 15760 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15761
15762 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15763 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15764 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15765 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15766 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15767 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15768 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15769 }
15770
15771 return error;
15772}
15773
edc3d884
MK		 15774#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15775
c4a1d9e4 15776void
edc3d884 15777intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15778 struct drm_device *dev,
15779 struct intel_display_error_state *error)
15780{
055e393f 15781 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15782 int i;
15783
63b66e5b
CW		 15784 if (!error)
15785 return;
15786
edc3d884 15787 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15788 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15789 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15790 error->power_well_driver);
055e393f 15791 for_each_pipe(dev_priv, i) {
edc3d884 15792 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15793 err_printf(m, " Power: %s\n",
15794 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15795 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15796 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15797
15798 err_printf(m, "Plane [%d]:\n", i);
15799 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15800 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15801 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15802 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15803 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15804 }
4b71a570 15805 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15806 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15807 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15808 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15809 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15810 }
15811
edc3d884
MK		 15812 err_printf(m, "Cursor [%d]:\n", i);
15813 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15814 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15815 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15816 }
63b66e5b
CW		 15817
15818 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15819 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15820 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15821 err_printf(m, " Power: %s\n",
15822 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15823 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15824 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15825 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15826 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15827 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15828 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15829 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15830 }
c4a1d9e4 15831}
e2fcdaa9
VS		 15832
15833void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15834{
15835 struct intel_crtc *crtc;
15836
15837 for_each_intel_crtc(dev, crtc) {
15838 struct intel_unpin_work *work;
e2fcdaa9 15839
5e2d7afc 15840 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15841
15842 work = crtc->unpin_work;
15843
15844 if (work && work->event &&
15845 work->event->base.file_priv == file) {
15846 kfree(work->event);
15847 work->event = NULL;
15848 }
15849
5e2d7afc 15850 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15851 }
15852}
Linux kernel - Deliverables
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