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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 AJ |
92 | .dot = { .min = 25000, .max = 350000 }, |
93 | .vco = { .min = 930000, .max = 1400000 }, | |
94 | .n = { .min = 3, .max = 16 }, | |
95 | .m = { .min = 96, .max = 140 }, | |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
106 | .vco = { .min = 930000, .max = 1400000 }, | |
107 | .n = { .min = 3, .max = 16 }, | |
108 | .m = { .min = 96, .max = 140 }, | |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 AJ |
118 | .dot = { .min = 25000, .max = 350000 }, |
119 | .vco = { .min = 930000, .max = 1400000 }, | |
120 | .n = { .min = 3, .max = 16 }, | |
121 | .m = { .min = 96, .max = 140 }, | |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
313 | /* |
314 | * These are the data rate limits (measured in fast clocks) | |
315 | * since those are the strictest limits we have. The fast | |
316 | * clock and actual rate limits are more relaxed, so checking | |
317 | * them would make no difference. | |
318 | */ | |
319 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 320 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 321 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
322 | .m1 = { .min = 2, .max = 3 }, |
323 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 324 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 325 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
326 | }; |
327 | ||
6b4bf1c4 VS |
328 | static void vlv_clock(int refclk, intel_clock_t *clock) |
329 | { | |
330 | clock->m = clock->m1 * clock->m2; | |
331 | clock->p = clock->p1 * clock->p2; | |
fb03ac01 VS |
332 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
333 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
334 | } |
335 | ||
e0638cdf PZ |
336 | /** |
337 | * Returns whether any output on the specified pipe is of the specified type | |
338 | */ | |
339 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
340 | { | |
341 | struct drm_device *dev = crtc->dev; | |
342 | struct intel_encoder *encoder; | |
343 | ||
344 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
345 | if (encoder->type == type) | |
346 | return true; | |
347 | ||
348 | return false; | |
349 | } | |
350 | ||
1b894b59 CW |
351 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
352 | int refclk) | |
2c07245f | 353 | { |
b91ad0ec | 354 | struct drm_device *dev = crtc->dev; |
2c07245f | 355 | const intel_limit_t *limit; |
b91ad0ec ZW |
356 | |
357 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 358 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 359 | if (refclk == 100000) |
b91ad0ec ZW |
360 | limit = &intel_limits_ironlake_dual_lvds_100m; |
361 | else | |
362 | limit = &intel_limits_ironlake_dual_lvds; | |
363 | } else { | |
1b894b59 | 364 | if (refclk == 100000) |
b91ad0ec ZW |
365 | limit = &intel_limits_ironlake_single_lvds_100m; |
366 | else | |
367 | limit = &intel_limits_ironlake_single_lvds; | |
368 | } | |
c6bb3538 | 369 | } else |
b91ad0ec | 370 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
371 | |
372 | return limit; | |
373 | } | |
374 | ||
044c7c41 ML |
375 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
376 | { | |
377 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
378 | const intel_limit_t *limit; |
379 | ||
380 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 381 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 382 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 383 | else |
e4b36699 | 384 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
385 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
386 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 387 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 388 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 389 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 390 | } else /* The option is for other outputs */ |
e4b36699 | 391 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
392 | |
393 | return limit; | |
394 | } | |
395 | ||
1b894b59 | 396 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
397 | { |
398 | struct drm_device *dev = crtc->dev; | |
399 | const intel_limit_t *limit; | |
400 | ||
bad720ff | 401 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 402 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 403 | else if (IS_G4X(dev)) { |
044c7c41 | 404 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 405 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 406 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 407 | limit = &intel_limits_pineview_lvds; |
2177832f | 408 | else |
f2b115e6 | 409 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 410 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 411 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
412 | } else if (!IS_GEN2(dev)) { |
413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
414 | limit = &intel_limits_i9xx_lvds; | |
415 | else | |
416 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
417 | } else { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 419 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 420 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 421 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
422 | else |
423 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
424 | } |
425 | return limit; | |
426 | } | |
427 | ||
f2b115e6 AJ |
428 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
429 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 430 | { |
2177832f SL |
431 | clock->m = clock->m2 + 2; |
432 | clock->p = clock->p1 * clock->p2; | |
fb03ac01 VS |
433 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
434 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
435 | } |
436 | ||
7429e9d4 DV |
437 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
438 | { | |
439 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
440 | } | |
441 | ||
ac58c3f0 | 442 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 443 | { |
7429e9d4 | 444 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 445 | clock->p = clock->p1 * clock->p2; |
fb03ac01 VS |
446 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
447 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
448 | } |
449 | ||
7c04d1d9 | 450 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
451 | /** |
452 | * Returns whether the given set of divisors are valid for a given refclk with | |
453 | * the given connectors. | |
454 | */ | |
455 | ||
1b894b59 CW |
456 | static bool intel_PLL_is_valid(struct drm_device *dev, |
457 | const intel_limit_t *limit, | |
458 | const intel_clock_t *clock) | |
79e53945 | 459 | { |
f01b7962 VS |
460 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
461 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 462 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 463 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 464 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 465 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 466 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 467 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
468 | |
469 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
470 | if (clock->m1 <= clock->m2) | |
471 | INTELPllInvalid("m1 <= m2\n"); | |
472 | ||
473 | if (!IS_VALLEYVIEW(dev)) { | |
474 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
475 | INTELPllInvalid("p out of range\n"); | |
476 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
477 | INTELPllInvalid("m out of range\n"); | |
478 | } | |
479 | ||
79e53945 | 480 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 481 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
482 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
483 | * connector, etc., rather than just a single range. | |
484 | */ | |
485 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 486 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
487 | |
488 | return true; | |
489 | } | |
490 | ||
d4906093 | 491 | static bool |
ee9300bb | 492 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
493 | int target, int refclk, intel_clock_t *match_clock, |
494 | intel_clock_t *best_clock) | |
79e53945 JB |
495 | { |
496 | struct drm_device *dev = crtc->dev; | |
79e53945 | 497 | intel_clock_t clock; |
79e53945 JB |
498 | int err = target; |
499 | ||
a210b028 | 500 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 501 | /* |
a210b028 DV |
502 | * For LVDS just rely on its current settings for dual-channel. |
503 | * We haven't figured out how to reliably set up different | |
504 | * single/dual channel state, if we even can. | |
79e53945 | 505 | */ |
1974cad0 | 506 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
507 | clock.p2 = limit->p2.p2_fast; |
508 | else | |
509 | clock.p2 = limit->p2.p2_slow; | |
510 | } else { | |
511 | if (target < limit->p2.dot_limit) | |
512 | clock.p2 = limit->p2.p2_slow; | |
513 | else | |
514 | clock.p2 = limit->p2.p2_fast; | |
515 | } | |
516 | ||
0206e353 | 517 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 518 | |
42158660 ZY |
519 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
520 | clock.m1++) { | |
521 | for (clock.m2 = limit->m2.min; | |
522 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 523 | if (clock.m2 >= clock.m1) |
42158660 ZY |
524 | break; |
525 | for (clock.n = limit->n.min; | |
526 | clock.n <= limit->n.max; clock.n++) { | |
527 | for (clock.p1 = limit->p1.min; | |
528 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
529 | int this_err; |
530 | ||
ac58c3f0 DV |
531 | i9xx_clock(refclk, &clock); |
532 | if (!intel_PLL_is_valid(dev, limit, | |
533 | &clock)) | |
534 | continue; | |
535 | if (match_clock && | |
536 | clock.p != match_clock->p) | |
537 | continue; | |
538 | ||
539 | this_err = abs(clock.dot - target); | |
540 | if (this_err < err) { | |
541 | *best_clock = clock; | |
542 | err = this_err; | |
543 | } | |
544 | } | |
545 | } | |
546 | } | |
547 | } | |
548 | ||
549 | return (err != target); | |
550 | } | |
551 | ||
552 | static bool | |
ee9300bb DV |
553 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
554 | int target, int refclk, intel_clock_t *match_clock, | |
555 | intel_clock_t *best_clock) | |
79e53945 JB |
556 | { |
557 | struct drm_device *dev = crtc->dev; | |
79e53945 | 558 | intel_clock_t clock; |
79e53945 JB |
559 | int err = target; |
560 | ||
a210b028 | 561 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 562 | /* |
a210b028 DV |
563 | * For LVDS just rely on its current settings for dual-channel. |
564 | * We haven't figured out how to reliably set up different | |
565 | * single/dual channel state, if we even can. | |
79e53945 | 566 | */ |
1974cad0 | 567 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
568 | clock.p2 = limit->p2.p2_fast; |
569 | else | |
570 | clock.p2 = limit->p2.p2_slow; | |
571 | } else { | |
572 | if (target < limit->p2.dot_limit) | |
573 | clock.p2 = limit->p2.p2_slow; | |
574 | else | |
575 | clock.p2 = limit->p2.p2_fast; | |
576 | } | |
577 | ||
0206e353 | 578 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 579 | |
42158660 ZY |
580 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
581 | clock.m1++) { | |
582 | for (clock.m2 = limit->m2.min; | |
583 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
584 | for (clock.n = limit->n.min; |
585 | clock.n <= limit->n.max; clock.n++) { | |
586 | for (clock.p1 = limit->p1.min; | |
587 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
588 | int this_err; |
589 | ||
ac58c3f0 | 590 | pineview_clock(refclk, &clock); |
1b894b59 CW |
591 | if (!intel_PLL_is_valid(dev, limit, |
592 | &clock)) | |
79e53945 | 593 | continue; |
cec2f356 SP |
594 | if (match_clock && |
595 | clock.p != match_clock->p) | |
596 | continue; | |
79e53945 JB |
597 | |
598 | this_err = abs(clock.dot - target); | |
599 | if (this_err < err) { | |
600 | *best_clock = clock; | |
601 | err = this_err; | |
602 | } | |
603 | } | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
608 | return (err != target); | |
609 | } | |
610 | ||
d4906093 | 611 | static bool |
ee9300bb DV |
612 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
613 | int target, int refclk, intel_clock_t *match_clock, | |
614 | intel_clock_t *best_clock) | |
d4906093 ML |
615 | { |
616 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
617 | intel_clock_t clock; |
618 | int max_n; | |
619 | bool found; | |
6ba770dc AJ |
620 | /* approximately equals target * 0.00585 */ |
621 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
622 | found = false; |
623 | ||
624 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 625 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
626 | clock.p2 = limit->p2.p2_fast; |
627 | else | |
628 | clock.p2 = limit->p2.p2_slow; | |
629 | } else { | |
630 | if (target < limit->p2.dot_limit) | |
631 | clock.p2 = limit->p2.p2_slow; | |
632 | else | |
633 | clock.p2 = limit->p2.p2_fast; | |
634 | } | |
635 | ||
636 | memset(best_clock, 0, sizeof(*best_clock)); | |
637 | max_n = limit->n.max; | |
f77f13e2 | 638 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 639 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 640 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
641 | for (clock.m1 = limit->m1.max; |
642 | clock.m1 >= limit->m1.min; clock.m1--) { | |
643 | for (clock.m2 = limit->m2.max; | |
644 | clock.m2 >= limit->m2.min; clock.m2--) { | |
645 | for (clock.p1 = limit->p1.max; | |
646 | clock.p1 >= limit->p1.min; clock.p1--) { | |
647 | int this_err; | |
648 | ||
ac58c3f0 | 649 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
650 | if (!intel_PLL_is_valid(dev, limit, |
651 | &clock)) | |
d4906093 | 652 | continue; |
1b894b59 CW |
653 | |
654 | this_err = abs(clock.dot - target); | |
d4906093 ML |
655 | if (this_err < err_most) { |
656 | *best_clock = clock; | |
657 | err_most = this_err; | |
658 | max_n = clock.n; | |
659 | found = true; | |
660 | } | |
661 | } | |
662 | } | |
663 | } | |
664 | } | |
2c07245f ZW |
665 | return found; |
666 | } | |
667 | ||
a0c4da24 | 668 | static bool |
ee9300bb DV |
669 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
670 | int target, int refclk, intel_clock_t *match_clock, | |
671 | intel_clock_t *best_clock) | |
a0c4da24 | 672 | { |
f01b7962 | 673 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 674 | intel_clock_t clock; |
69e4f900 | 675 | unsigned int bestppm = 1000000; |
27e639bf VS |
676 | /* min update 19.2 MHz */ |
677 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 678 | bool found = false; |
a0c4da24 | 679 | |
6b4bf1c4 VS |
680 | target *= 5; /* fast clock */ |
681 | ||
682 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
683 | |
684 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 685 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 686 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 687 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 688 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 689 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 690 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 691 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
692 | unsigned int ppm, diff; |
693 | ||
6b4bf1c4 VS |
694 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
695 | refclk * clock.m1); | |
696 | ||
697 | vlv_clock(refclk, &clock); | |
43b0ac53 | 698 | |
f01b7962 VS |
699 | if (!intel_PLL_is_valid(dev, limit, |
700 | &clock)) | |
43b0ac53 VS |
701 | continue; |
702 | ||
6b4bf1c4 VS |
703 | diff = abs(clock.dot - target); |
704 | ppm = div_u64(1000000ULL * diff, target); | |
705 | ||
706 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 707 | bestppm = 0; |
6b4bf1c4 | 708 | *best_clock = clock; |
49e497ef | 709 | found = true; |
43b0ac53 | 710 | } |
6b4bf1c4 | 711 | |
c686122c | 712 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 713 | bestppm = ppm; |
6b4bf1c4 | 714 | *best_clock = clock; |
49e497ef | 715 | found = true; |
a0c4da24 JB |
716 | } |
717 | } | |
718 | } | |
719 | } | |
720 | } | |
a0c4da24 | 721 | |
49e497ef | 722 | return found; |
a0c4da24 | 723 | } |
a4fc5ed6 | 724 | |
20ddf665 VS |
725 | bool intel_crtc_active(struct drm_crtc *crtc) |
726 | { | |
727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
728 | ||
729 | /* Be paranoid as we can arrive here with only partial | |
730 | * state retrieved from the hardware during setup. | |
731 | * | |
241bfc38 | 732 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
733 | * as Haswell has gained clock readout/fastboot support. |
734 | * | |
735 | * We can ditch the crtc->fb check as soon as we can | |
736 | * properly reconstruct framebuffers. | |
737 | */ | |
738 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 739 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
740 | } |
741 | ||
a5c961d1 PZ |
742 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
743 | enum pipe pipe) | |
744 | { | |
745 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
747 | ||
3b117c8f | 748 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
749 | } |
750 | ||
57e22f4a | 751 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
752 | { |
753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 754 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
755 | |
756 | frame = I915_READ(frame_reg); | |
757 | ||
758 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
759 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
760 | } | |
761 | ||
9d0498a2 JB |
762 | /** |
763 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
764 | * @dev: drm device | |
765 | * @pipe: pipe to wait for | |
766 | * | |
767 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
768 | * mode setting code. | |
769 | */ | |
770 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 771 | { |
9d0498a2 | 772 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 773 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 774 | |
57e22f4a VS |
775 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
776 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
777 | return; |
778 | } | |
779 | ||
300387c0 CW |
780 | /* Clear existing vblank status. Note this will clear any other |
781 | * sticky status fields as well. | |
782 | * | |
783 | * This races with i915_driver_irq_handler() with the result | |
784 | * that either function could miss a vblank event. Here it is not | |
785 | * fatal, as we will either wait upon the next vblank interrupt or | |
786 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
787 | * called during modeset at which time the GPU should be idle and | |
788 | * should *not* be performing page flips and thus not waiting on | |
789 | * vblanks... | |
790 | * Currently, the result of us stealing a vblank from the irq | |
791 | * handler is that a single frame will be skipped during swapbuffers. | |
792 | */ | |
793 | I915_WRITE(pipestat_reg, | |
794 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
795 | ||
9d0498a2 | 796 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
797 | if (wait_for(I915_READ(pipestat_reg) & |
798 | PIPE_VBLANK_INTERRUPT_STATUS, | |
799 | 50)) | |
9d0498a2 JB |
800 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
801 | } | |
802 | ||
fbf49ea2 VS |
803 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
804 | { | |
805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
806 | u32 reg = PIPEDSL(pipe); | |
807 | u32 line1, line2; | |
808 | u32 line_mask; | |
809 | ||
810 | if (IS_GEN2(dev)) | |
811 | line_mask = DSL_LINEMASK_GEN2; | |
812 | else | |
813 | line_mask = DSL_LINEMASK_GEN3; | |
814 | ||
815 | line1 = I915_READ(reg) & line_mask; | |
816 | mdelay(5); | |
817 | line2 = I915_READ(reg) & line_mask; | |
818 | ||
819 | return line1 == line2; | |
820 | } | |
821 | ||
ab7ad7f6 KP |
822 | /* |
823 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
824 | * @dev: drm device |
825 | * @pipe: pipe to wait for | |
826 | * | |
827 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
828 | * spinning on the vblank interrupt status bit, since we won't actually | |
829 | * see an interrupt when the pipe is disabled. | |
830 | * | |
ab7ad7f6 KP |
831 | * On Gen4 and above: |
832 | * wait for the pipe register state bit to turn off | |
833 | * | |
834 | * Otherwise: | |
835 | * wait for the display line value to settle (it usually | |
836 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 837 | * |
9d0498a2 | 838 | */ |
58e10eb9 | 839 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
840 | { |
841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
842 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
843 | pipe); | |
ab7ad7f6 KP |
844 | |
845 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 846 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
847 | |
848 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
849 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
850 | 100)) | |
284637d9 | 851 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 852 | } else { |
ab7ad7f6 | 853 | /* Wait for the display line to settle */ |
fbf49ea2 | 854 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 855 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 856 | } |
79e53945 JB |
857 | } |
858 | ||
b0ea7d37 DL |
859 | /* |
860 | * ibx_digital_port_connected - is the specified port connected? | |
861 | * @dev_priv: i915 private structure | |
862 | * @port: the port to test | |
863 | * | |
864 | * Returns true if @port is connected, false otherwise. | |
865 | */ | |
866 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
867 | struct intel_digital_port *port) | |
868 | { | |
869 | u32 bit; | |
870 | ||
c36346e3 DL |
871 | if (HAS_PCH_IBX(dev_priv->dev)) { |
872 | switch(port->port) { | |
873 | case PORT_B: | |
874 | bit = SDE_PORTB_HOTPLUG; | |
875 | break; | |
876 | case PORT_C: | |
877 | bit = SDE_PORTC_HOTPLUG; | |
878 | break; | |
879 | case PORT_D: | |
880 | bit = SDE_PORTD_HOTPLUG; | |
881 | break; | |
882 | default: | |
883 | return true; | |
884 | } | |
885 | } else { | |
886 | switch(port->port) { | |
887 | case PORT_B: | |
888 | bit = SDE_PORTB_HOTPLUG_CPT; | |
889 | break; | |
890 | case PORT_C: | |
891 | bit = SDE_PORTC_HOTPLUG_CPT; | |
892 | break; | |
893 | case PORT_D: | |
894 | bit = SDE_PORTD_HOTPLUG_CPT; | |
895 | break; | |
896 | default: | |
897 | return true; | |
898 | } | |
b0ea7d37 DL |
899 | } |
900 | ||
901 | return I915_READ(SDEISR) & bit; | |
902 | } | |
903 | ||
b24e7179 JB |
904 | static const char *state_string(bool enabled) |
905 | { | |
906 | return enabled ? "on" : "off"; | |
907 | } | |
908 | ||
909 | /* Only for pre-ILK configs */ | |
55607e8a DV |
910 | void assert_pll(struct drm_i915_private *dev_priv, |
911 | enum pipe pipe, bool state) | |
b24e7179 JB |
912 | { |
913 | int reg; | |
914 | u32 val; | |
915 | bool cur_state; | |
916 | ||
917 | reg = DPLL(pipe); | |
918 | val = I915_READ(reg); | |
919 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
920 | WARN(cur_state != state, | |
921 | "PLL state assertion failure (expected %s, current %s)\n", | |
922 | state_string(state), state_string(cur_state)); | |
923 | } | |
b24e7179 | 924 | |
23538ef1 JN |
925 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
926 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
927 | { | |
928 | u32 val; | |
929 | bool cur_state; | |
930 | ||
931 | mutex_lock(&dev_priv->dpio_lock); | |
932 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
933 | mutex_unlock(&dev_priv->dpio_lock); | |
934 | ||
935 | cur_state = val & DSI_PLL_VCO_EN; | |
936 | WARN(cur_state != state, | |
937 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
938 | state_string(state), state_string(cur_state)); | |
939 | } | |
940 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
941 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
942 | ||
55607e8a | 943 | struct intel_shared_dpll * |
e2b78267 DV |
944 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
945 | { | |
946 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
947 | ||
a43f6e0f | 948 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
949 | return NULL; |
950 | ||
a43f6e0f | 951 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
952 | } |
953 | ||
040484af | 954 | /* For ILK+ */ |
55607e8a DV |
955 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
956 | struct intel_shared_dpll *pll, | |
957 | bool state) | |
040484af | 958 | { |
040484af | 959 | bool cur_state; |
5358901f | 960 | struct intel_dpll_hw_state hw_state; |
040484af | 961 | |
9d82aa17 ED |
962 | if (HAS_PCH_LPT(dev_priv->dev)) { |
963 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
964 | return; | |
965 | } | |
966 | ||
92b27b08 | 967 | if (WARN (!pll, |
46edb027 | 968 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 969 | return; |
ee7b9f93 | 970 | |
5358901f | 971 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 972 | WARN(cur_state != state, |
5358901f DV |
973 | "%s assertion failure (expected %s, current %s)\n", |
974 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 975 | } |
040484af JB |
976 | |
977 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
978 | enum pipe pipe, bool state) | |
979 | { | |
980 | int reg; | |
981 | u32 val; | |
982 | bool cur_state; | |
ad80a810 PZ |
983 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
984 | pipe); | |
040484af | 985 | |
affa9354 PZ |
986 | if (HAS_DDI(dev_priv->dev)) { |
987 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 988 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 989 | val = I915_READ(reg); |
ad80a810 | 990 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
991 | } else { |
992 | reg = FDI_TX_CTL(pipe); | |
993 | val = I915_READ(reg); | |
994 | cur_state = !!(val & FDI_TX_ENABLE); | |
995 | } | |
040484af JB |
996 | WARN(cur_state != state, |
997 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
998 | state_string(state), state_string(cur_state)); | |
999 | } | |
1000 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1001 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1002 | ||
1003 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1004 | enum pipe pipe, bool state) | |
1005 | { | |
1006 | int reg; | |
1007 | u32 val; | |
1008 | bool cur_state; | |
1009 | ||
d63fa0dc PZ |
1010 | reg = FDI_RX_CTL(pipe); |
1011 | val = I915_READ(reg); | |
1012 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1013 | WARN(cur_state != state, |
1014 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1015 | state_string(state), state_string(cur_state)); | |
1016 | } | |
1017 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1018 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1019 | ||
1020 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1021 | enum pipe pipe) | |
1022 | { | |
1023 | int reg; | |
1024 | u32 val; | |
1025 | ||
1026 | /* ILK FDI PLL is always enabled */ | |
1027 | if (dev_priv->info->gen == 5) | |
1028 | return; | |
1029 | ||
bf507ef7 | 1030 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1031 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1032 | return; |
1033 | ||
040484af JB |
1034 | reg = FDI_TX_CTL(pipe); |
1035 | val = I915_READ(reg); | |
1036 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1037 | } | |
1038 | ||
55607e8a DV |
1039 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1040 | enum pipe pipe, bool state) | |
040484af JB |
1041 | { |
1042 | int reg; | |
1043 | u32 val; | |
55607e8a | 1044 | bool cur_state; |
040484af JB |
1045 | |
1046 | reg = FDI_RX_CTL(pipe); | |
1047 | val = I915_READ(reg); | |
55607e8a DV |
1048 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1049 | WARN(cur_state != state, | |
1050 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1051 | state_string(state), state_string(cur_state)); | |
040484af JB |
1052 | } |
1053 | ||
ea0760cf JB |
1054 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1055 | enum pipe pipe) | |
1056 | { | |
1057 | int pp_reg, lvds_reg; | |
1058 | u32 val; | |
1059 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1060 | bool locked = true; |
ea0760cf JB |
1061 | |
1062 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1063 | pp_reg = PCH_PP_CONTROL; | |
1064 | lvds_reg = PCH_LVDS; | |
1065 | } else { | |
1066 | pp_reg = PP_CONTROL; | |
1067 | lvds_reg = LVDS; | |
1068 | } | |
1069 | ||
1070 | val = I915_READ(pp_reg); | |
1071 | if (!(val & PANEL_POWER_ON) || | |
1072 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1073 | locked = false; | |
1074 | ||
1075 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1076 | panel_pipe = PIPE_B; | |
1077 | ||
1078 | WARN(panel_pipe == pipe && locked, | |
1079 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1080 | pipe_name(pipe)); |
ea0760cf JB |
1081 | } |
1082 | ||
93ce0ba6 JN |
1083 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1084 | enum pipe pipe, bool state) | |
1085 | { | |
1086 | struct drm_device *dev = dev_priv->dev; | |
1087 | bool cur_state; | |
1088 | ||
1089 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1090 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1091 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1092 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1093 | else | |
1094 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1095 | ||
1096 | WARN(cur_state != state, | |
1097 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1098 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1099 | } | |
1100 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1101 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1102 | ||
b840d907 JB |
1103 | void assert_pipe(struct drm_i915_private *dev_priv, |
1104 | enum pipe pipe, bool state) | |
b24e7179 JB |
1105 | { |
1106 | int reg; | |
1107 | u32 val; | |
63d7bbe9 | 1108 | bool cur_state; |
702e7a56 PZ |
1109 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1110 | pipe); | |
b24e7179 | 1111 | |
8e636784 DV |
1112 | /* if we need the pipe A quirk it must be always on */ |
1113 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1114 | state = true; | |
1115 | ||
b97186f0 PZ |
1116 | if (!intel_display_power_enabled(dev_priv->dev, |
1117 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1118 | cur_state = false; |
1119 | } else { | |
1120 | reg = PIPECONF(cpu_transcoder); | |
1121 | val = I915_READ(reg); | |
1122 | cur_state = !!(val & PIPECONF_ENABLE); | |
1123 | } | |
1124 | ||
63d7bbe9 JB |
1125 | WARN(cur_state != state, |
1126 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1127 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1128 | } |
1129 | ||
931872fc CW |
1130 | static void assert_plane(struct drm_i915_private *dev_priv, |
1131 | enum plane plane, bool state) | |
b24e7179 JB |
1132 | { |
1133 | int reg; | |
1134 | u32 val; | |
931872fc | 1135 | bool cur_state; |
b24e7179 JB |
1136 | |
1137 | reg = DSPCNTR(plane); | |
1138 | val = I915_READ(reg); | |
931872fc CW |
1139 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1140 | WARN(cur_state != state, | |
1141 | "plane %c assertion failure (expected %s, current %s)\n", | |
1142 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1143 | } |
1144 | ||
931872fc CW |
1145 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1146 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1147 | ||
b24e7179 JB |
1148 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1149 | enum pipe pipe) | |
1150 | { | |
653e1026 | 1151 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1152 | int reg, i; |
1153 | u32 val; | |
1154 | int cur_pipe; | |
1155 | ||
653e1026 VS |
1156 | /* Primary planes are fixed to pipes on gen4+ */ |
1157 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1158 | reg = DSPCNTR(pipe); |
1159 | val = I915_READ(reg); | |
1160 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1161 | "plane %c assertion failure, should be disabled but not\n", | |
1162 | plane_name(pipe)); | |
19ec1358 | 1163 | return; |
28c05794 | 1164 | } |
19ec1358 | 1165 | |
b24e7179 | 1166 | /* Need to check both planes against the pipe */ |
08e2a7de | 1167 | for_each_pipe(i) { |
b24e7179 JB |
1168 | reg = DSPCNTR(i); |
1169 | val = I915_READ(reg); | |
1170 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1171 | DISPPLANE_SEL_PIPE_SHIFT; | |
1172 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1173 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1174 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1175 | } |
1176 | } | |
1177 | ||
19332d7a JB |
1178 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1179 | enum pipe pipe) | |
1180 | { | |
20674eef | 1181 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1182 | int reg, i; |
1183 | u32 val; | |
1184 | ||
20674eef VS |
1185 | if (IS_VALLEYVIEW(dev)) { |
1186 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1187 | reg = SPCNTR(pipe, i); | |
1188 | val = I915_READ(reg); | |
1189 | WARN((val & SP_ENABLE), | |
1190 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1191 | sprite_name(pipe, i), pipe_name(pipe)); | |
1192 | } | |
1193 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1194 | reg = SPRCTL(pipe); | |
19332d7a | 1195 | val = I915_READ(reg); |
20674eef | 1196 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1197 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1198 | plane_name(pipe), pipe_name(pipe)); |
1199 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1200 | reg = DVSCNTR(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & DVS_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1204 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1205 | } |
1206 | } | |
1207 | ||
92f2584a JB |
1208 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1209 | { | |
1210 | u32 val; | |
1211 | bool enabled; | |
1212 | ||
9d82aa17 ED |
1213 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1214 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1215 | return; | |
1216 | } | |
1217 | ||
92f2584a JB |
1218 | val = I915_READ(PCH_DREF_CONTROL); |
1219 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1220 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1221 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1222 | } | |
1223 | ||
ab9412ba DV |
1224 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1225 | enum pipe pipe) | |
92f2584a JB |
1226 | { |
1227 | int reg; | |
1228 | u32 val; | |
1229 | bool enabled; | |
1230 | ||
ab9412ba | 1231 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1232 | val = I915_READ(reg); |
1233 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1234 | WARN(enabled, |
1235 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1236 | pipe_name(pipe)); | |
92f2584a JB |
1237 | } |
1238 | ||
4e634389 KP |
1239 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1240 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1241 | { |
1242 | if ((val & DP_PORT_EN) == 0) | |
1243 | return false; | |
1244 | ||
1245 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1246 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1247 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1248 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1249 | return false; | |
1250 | } else { | |
1251 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1252 | return false; | |
1253 | } | |
1254 | return true; | |
1255 | } | |
1256 | ||
1519b995 KP |
1257 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1258 | enum pipe pipe, u32 val) | |
1259 | { | |
dc0fa718 | 1260 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1261 | return false; |
1262 | ||
1263 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1264 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1265 | return false; |
1266 | } else { | |
dc0fa718 | 1267 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1268 | return false; |
1269 | } | |
1270 | return true; | |
1271 | } | |
1272 | ||
1273 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1274 | enum pipe pipe, u32 val) | |
1275 | { | |
1276 | if ((val & LVDS_PORT_EN) == 0) | |
1277 | return false; | |
1278 | ||
1279 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1280 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1281 | return false; | |
1282 | } else { | |
1283 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1284 | return false; | |
1285 | } | |
1286 | return true; | |
1287 | } | |
1288 | ||
1289 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1290 | enum pipe pipe, u32 val) | |
1291 | { | |
1292 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1293 | return false; | |
1294 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1295 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1296 | return false; | |
1297 | } else { | |
1298 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1299 | return false; | |
1300 | } | |
1301 | return true; | |
1302 | } | |
1303 | ||
291906f1 | 1304 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1305 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1306 | { |
47a05eca | 1307 | u32 val = I915_READ(reg); |
4e634389 | 1308 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1309 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1310 | reg, pipe_name(pipe)); |
de9a35ab | 1311 | |
75c5da27 DV |
1312 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1313 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1314 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1315 | } |
1316 | ||
1317 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1318 | enum pipe pipe, int reg) | |
1319 | { | |
47a05eca | 1320 | u32 val = I915_READ(reg); |
b70ad586 | 1321 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1322 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1323 | reg, pipe_name(pipe)); |
de9a35ab | 1324 | |
dc0fa718 | 1325 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1326 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1327 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1328 | } |
1329 | ||
1330 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1331 | enum pipe pipe) | |
1332 | { | |
1333 | int reg; | |
1334 | u32 val; | |
291906f1 | 1335 | |
f0575e92 KP |
1336 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1337 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1338 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1339 | |
1340 | reg = PCH_ADPA; | |
1341 | val = I915_READ(reg); | |
b70ad586 | 1342 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1343 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1344 | pipe_name(pipe)); |
291906f1 JB |
1345 | |
1346 | reg = PCH_LVDS; | |
1347 | val = I915_READ(reg); | |
b70ad586 | 1348 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1349 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1350 | pipe_name(pipe)); |
291906f1 | 1351 | |
e2debe91 PZ |
1352 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1353 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1354 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1355 | } |
1356 | ||
40e9cf64 JB |
1357 | static void intel_init_dpio(struct drm_device *dev) |
1358 | { | |
1359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1360 | ||
1361 | if (!IS_VALLEYVIEW(dev)) | |
1362 | return; | |
1363 | ||
e4607fcf | 1364 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
40e9cf64 JB |
1365 | /* |
1366 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1367 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1368 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1369 | * b. The other bits such as sfr settings / modesel may all be set | |
1370 | * to 0. | |
1371 | * | |
1372 | * This should only be done on init and resume from S3 with both | |
1373 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1374 | */ | |
1375 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1376 | } | |
1377 | ||
426115cf | 1378 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1379 | { |
426115cf DV |
1380 | struct drm_device *dev = crtc->base.dev; |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1382 | int reg = DPLL(crtc->pipe); | |
1383 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1384 | |
426115cf | 1385 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1386 | |
1387 | /* No really, not for ILK+ */ | |
1388 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1389 | ||
1390 | /* PLL is protected by panel, make sure we can write it */ | |
1391 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1392 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1393 | |
426115cf DV |
1394 | I915_WRITE(reg, dpll); |
1395 | POSTING_READ(reg); | |
1396 | udelay(150); | |
1397 | ||
1398 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1399 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1400 | ||
1401 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1402 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1403 | |
1404 | /* We do this three times for luck */ | |
426115cf | 1405 | I915_WRITE(reg, dpll); |
87442f73 DV |
1406 | POSTING_READ(reg); |
1407 | udelay(150); /* wait for warmup */ | |
426115cf | 1408 | I915_WRITE(reg, dpll); |
87442f73 DV |
1409 | POSTING_READ(reg); |
1410 | udelay(150); /* wait for warmup */ | |
426115cf | 1411 | I915_WRITE(reg, dpll); |
87442f73 DV |
1412 | POSTING_READ(reg); |
1413 | udelay(150); /* wait for warmup */ | |
1414 | } | |
1415 | ||
66e3d5c0 | 1416 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1417 | { |
66e3d5c0 DV |
1418 | struct drm_device *dev = crtc->base.dev; |
1419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1420 | int reg = DPLL(crtc->pipe); | |
1421 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1422 | |
66e3d5c0 | 1423 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1424 | |
63d7bbe9 | 1425 | /* No really, not for ILK+ */ |
87442f73 | 1426 | BUG_ON(dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1427 | |
1428 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1429 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1430 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1431 | |
66e3d5c0 DV |
1432 | I915_WRITE(reg, dpll); |
1433 | ||
1434 | /* Wait for the clocks to stabilize. */ | |
1435 | POSTING_READ(reg); | |
1436 | udelay(150); | |
1437 | ||
1438 | if (INTEL_INFO(dev)->gen >= 4) { | |
1439 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1440 | crtc->config.dpll_hw_state.dpll_md); | |
1441 | } else { | |
1442 | /* The pixel multiplier can only be updated once the | |
1443 | * DPLL is enabled and the clocks are stable. | |
1444 | * | |
1445 | * So write it again. | |
1446 | */ | |
1447 | I915_WRITE(reg, dpll); | |
1448 | } | |
63d7bbe9 JB |
1449 | |
1450 | /* We do this three times for luck */ | |
66e3d5c0 | 1451 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1452 | POSTING_READ(reg); |
1453 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1454 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1455 | POSTING_READ(reg); |
1456 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1457 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1458 | POSTING_READ(reg); |
1459 | udelay(150); /* wait for warmup */ | |
1460 | } | |
1461 | ||
1462 | /** | |
50b44a44 | 1463 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1464 | * @dev_priv: i915 private structure |
1465 | * @pipe: pipe PLL to disable | |
1466 | * | |
1467 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1468 | * | |
1469 | * Note! This is for pre-ILK only. | |
1470 | */ | |
50b44a44 | 1471 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1472 | { |
63d7bbe9 JB |
1473 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1474 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1475 | return; | |
1476 | ||
1477 | /* Make sure the pipe isn't still relying on us */ | |
1478 | assert_pipe_disabled(dev_priv, pipe); | |
1479 | ||
50b44a44 DV |
1480 | I915_WRITE(DPLL(pipe), 0); |
1481 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1482 | } |
1483 | ||
f6071166 JB |
1484 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1485 | { | |
1486 | u32 val = 0; | |
1487 | ||
1488 | /* Make sure the pipe isn't still relying on us */ | |
1489 | assert_pipe_disabled(dev_priv, pipe); | |
1490 | ||
1491 | /* Leave integrated clock source enabled */ | |
1492 | if (pipe == PIPE_B) | |
1493 | val = DPLL_INTEGRATED_CRI_CLK_VLV; | |
1494 | I915_WRITE(DPLL(pipe), val); | |
1495 | POSTING_READ(DPLL(pipe)); | |
1496 | } | |
1497 | ||
e4607fcf CML |
1498 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1499 | struct intel_digital_port *dport) | |
89b667f8 JB |
1500 | { |
1501 | u32 port_mask; | |
1502 | ||
e4607fcf CML |
1503 | switch (dport->port) { |
1504 | case PORT_B: | |
89b667f8 | 1505 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1506 | break; |
1507 | case PORT_C: | |
89b667f8 | 1508 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1509 | break; |
1510 | default: | |
1511 | BUG(); | |
1512 | } | |
89b667f8 JB |
1513 | |
1514 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1515 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
e4607fcf | 1516 | 'B' + dport->port, I915_READ(DPLL(0))); |
89b667f8 JB |
1517 | } |
1518 | ||
92f2584a | 1519 | /** |
e72f9fbf | 1520 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1521 | * @dev_priv: i915 private structure |
1522 | * @pipe: pipe PLL to enable | |
1523 | * | |
1524 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1525 | * drives the transcoder clock. | |
1526 | */ | |
e2b78267 | 1527 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1528 | { |
e2b78267 DV |
1529 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1530 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
92f2584a | 1531 | |
48da64a8 | 1532 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1533 | BUG_ON(dev_priv->info->gen < 5); |
87a875bb | 1534 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1535 | return; |
1536 | ||
1537 | if (WARN_ON(pll->refcount == 0)) | |
1538 | return; | |
ee7b9f93 | 1539 | |
46edb027 DV |
1540 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1541 | pll->name, pll->active, pll->on, | |
e2b78267 | 1542 | crtc->base.base.id); |
92f2584a | 1543 | |
cdbd2316 DV |
1544 | if (pll->active++) { |
1545 | WARN_ON(!pll->on); | |
e9d6944e | 1546 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1547 | return; |
1548 | } | |
f4a091c7 | 1549 | WARN_ON(pll->on); |
ee7b9f93 | 1550 | |
46edb027 | 1551 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1552 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1553 | pll->on = true; |
92f2584a JB |
1554 | } |
1555 | ||
e2b78267 | 1556 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1557 | { |
e2b78267 DV |
1558 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1559 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
4c609cb8 | 1560 | |
92f2584a JB |
1561 | /* PCH only available on ILK+ */ |
1562 | BUG_ON(dev_priv->info->gen < 5); | |
87a875bb | 1563 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1564 | return; |
92f2584a | 1565 | |
48da64a8 CW |
1566 | if (WARN_ON(pll->refcount == 0)) |
1567 | return; | |
7a419866 | 1568 | |
46edb027 DV |
1569 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1570 | pll->name, pll->active, pll->on, | |
e2b78267 | 1571 | crtc->base.base.id); |
7a419866 | 1572 | |
48da64a8 | 1573 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1574 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1575 | return; |
1576 | } | |
1577 | ||
e9d6944e | 1578 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1579 | WARN_ON(!pll->on); |
cdbd2316 | 1580 | if (--pll->active) |
7a419866 | 1581 | return; |
ee7b9f93 | 1582 | |
46edb027 | 1583 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1584 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1585 | pll->on = false; |
92f2584a JB |
1586 | } |
1587 | ||
b8a4f404 PZ |
1588 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1589 | enum pipe pipe) | |
040484af | 1590 | { |
23670b32 | 1591 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1592 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1593 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1594 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1595 | |
1596 | /* PCH only available on ILK+ */ | |
1597 | BUG_ON(dev_priv->info->gen < 5); | |
1598 | ||
1599 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1600 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1601 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1602 | |
1603 | /* FDI must be feeding us bits for PCH ports */ | |
1604 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1605 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1606 | ||
23670b32 DV |
1607 | if (HAS_PCH_CPT(dev)) { |
1608 | /* Workaround: Set the timing override bit before enabling the | |
1609 | * pch transcoder. */ | |
1610 | reg = TRANS_CHICKEN2(pipe); | |
1611 | val = I915_READ(reg); | |
1612 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1613 | I915_WRITE(reg, val); | |
59c859d6 | 1614 | } |
23670b32 | 1615 | |
ab9412ba | 1616 | reg = PCH_TRANSCONF(pipe); |
040484af | 1617 | val = I915_READ(reg); |
5f7f726d | 1618 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1619 | |
1620 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1621 | /* | |
1622 | * make the BPC in transcoder be consistent with | |
1623 | * that in pipeconf reg. | |
1624 | */ | |
dfd07d72 DV |
1625 | val &= ~PIPECONF_BPC_MASK; |
1626 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1627 | } |
5f7f726d PZ |
1628 | |
1629 | val &= ~TRANS_INTERLACE_MASK; | |
1630 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1631 | if (HAS_PCH_IBX(dev_priv->dev) && |
1632 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1633 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1634 | else | |
1635 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1636 | else |
1637 | val |= TRANS_PROGRESSIVE; | |
1638 | ||
040484af JB |
1639 | I915_WRITE(reg, val | TRANS_ENABLE); |
1640 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1641 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1642 | } |
1643 | ||
8fb033d7 | 1644 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1645 | enum transcoder cpu_transcoder) |
040484af | 1646 | { |
8fb033d7 | 1647 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1648 | |
1649 | /* PCH only available on ILK+ */ | |
1650 | BUG_ON(dev_priv->info->gen < 5); | |
1651 | ||
8fb033d7 | 1652 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1653 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1654 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1655 | |
223a6fdf PZ |
1656 | /* Workaround: set timing override bit. */ |
1657 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1658 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1659 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1660 | ||
25f3ef11 | 1661 | val = TRANS_ENABLE; |
937bb610 | 1662 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1663 | |
9a76b1c6 PZ |
1664 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1665 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1666 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1667 | else |
1668 | val |= TRANS_PROGRESSIVE; | |
1669 | ||
ab9412ba DV |
1670 | I915_WRITE(LPT_TRANSCONF, val); |
1671 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1672 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1673 | } |
1674 | ||
b8a4f404 PZ |
1675 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1676 | enum pipe pipe) | |
040484af | 1677 | { |
23670b32 DV |
1678 | struct drm_device *dev = dev_priv->dev; |
1679 | uint32_t reg, val; | |
040484af JB |
1680 | |
1681 | /* FDI relies on the transcoder */ | |
1682 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1683 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1684 | ||
291906f1 JB |
1685 | /* Ports must be off as well */ |
1686 | assert_pch_ports_disabled(dev_priv, pipe); | |
1687 | ||
ab9412ba | 1688 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1689 | val = I915_READ(reg); |
1690 | val &= ~TRANS_ENABLE; | |
1691 | I915_WRITE(reg, val); | |
1692 | /* wait for PCH transcoder off, transcoder state */ | |
1693 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1694 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1695 | |
1696 | if (!HAS_PCH_IBX(dev)) { | |
1697 | /* Workaround: Clear the timing override chicken bit again. */ | |
1698 | reg = TRANS_CHICKEN2(pipe); | |
1699 | val = I915_READ(reg); | |
1700 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1701 | I915_WRITE(reg, val); | |
1702 | } | |
040484af JB |
1703 | } |
1704 | ||
ab4d966c | 1705 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1706 | { |
8fb033d7 PZ |
1707 | u32 val; |
1708 | ||
ab9412ba | 1709 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1710 | val &= ~TRANS_ENABLE; |
ab9412ba | 1711 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1712 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1713 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1714 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1715 | |
1716 | /* Workaround: clear timing override bit. */ | |
1717 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1718 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1719 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1720 | } |
1721 | ||
b24e7179 | 1722 | /** |
309cfea8 | 1723 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1724 | * @dev_priv: i915 private structure |
1725 | * @pipe: pipe to enable | |
040484af | 1726 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1727 | * |
1728 | * Enable @pipe, making sure that various hardware specific requirements | |
1729 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1730 | * | |
1731 | * @pipe should be %PIPE_A or %PIPE_B. | |
1732 | * | |
1733 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1734 | * returning. | |
1735 | */ | |
040484af | 1736 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1737 | bool pch_port, bool dsi) |
b24e7179 | 1738 | { |
702e7a56 PZ |
1739 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1740 | pipe); | |
1a240d4d | 1741 | enum pipe pch_transcoder; |
b24e7179 JB |
1742 | int reg; |
1743 | u32 val; | |
1744 | ||
58c6eaa2 | 1745 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1746 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1747 | assert_sprites_disabled(dev_priv, pipe); |
1748 | ||
681e5811 | 1749 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1750 | pch_transcoder = TRANSCODER_A; |
1751 | else | |
1752 | pch_transcoder = pipe; | |
1753 | ||
b24e7179 JB |
1754 | /* |
1755 | * A pipe without a PLL won't actually be able to drive bits from | |
1756 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1757 | * need the check. | |
1758 | */ | |
1759 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1760 | if (dsi) |
1761 | assert_dsi_pll_enabled(dev_priv); | |
1762 | else | |
1763 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1764 | else { |
1765 | if (pch_port) { | |
1766 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1767 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1768 | assert_fdi_tx_pll_enabled(dev_priv, |
1769 | (enum pipe) cpu_transcoder); | |
040484af JB |
1770 | } |
1771 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1772 | } | |
b24e7179 | 1773 | |
702e7a56 | 1774 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1775 | val = I915_READ(reg); |
00d70b15 CW |
1776 | if (val & PIPECONF_ENABLE) |
1777 | return; | |
1778 | ||
1779 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1780 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1781 | } | |
1782 | ||
1783 | /** | |
309cfea8 | 1784 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1785 | * @dev_priv: i915 private structure |
1786 | * @pipe: pipe to disable | |
1787 | * | |
1788 | * Disable @pipe, making sure that various hardware specific requirements | |
1789 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1790 | * | |
1791 | * @pipe should be %PIPE_A or %PIPE_B. | |
1792 | * | |
1793 | * Will wait until the pipe has shut down before returning. | |
1794 | */ | |
1795 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1796 | enum pipe pipe) | |
1797 | { | |
702e7a56 PZ |
1798 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1799 | pipe); | |
b24e7179 JB |
1800 | int reg; |
1801 | u32 val; | |
1802 | ||
1803 | /* | |
1804 | * Make sure planes won't keep trying to pump pixels to us, | |
1805 | * or we might hang the display. | |
1806 | */ | |
1807 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1808 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1809 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1810 | |
1811 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1812 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1813 | return; | |
1814 | ||
702e7a56 | 1815 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1816 | val = I915_READ(reg); |
00d70b15 CW |
1817 | if ((val & PIPECONF_ENABLE) == 0) |
1818 | return; | |
1819 | ||
1820 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1821 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1822 | } | |
1823 | ||
d74362c9 KP |
1824 | /* |
1825 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1826 | * trigger in order to latch. The display address reg provides this. | |
1827 | */ | |
1dba99f4 VS |
1828 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1829 | enum plane plane) | |
d74362c9 | 1830 | { |
1dba99f4 VS |
1831 | u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
1832 | ||
1833 | I915_WRITE(reg, I915_READ(reg)); | |
1834 | POSTING_READ(reg); | |
d74362c9 KP |
1835 | } |
1836 | ||
b24e7179 | 1837 | /** |
d1de00ef | 1838 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1839 | * @dev_priv: i915 private structure |
1840 | * @plane: plane to enable | |
1841 | * @pipe: pipe being fed | |
1842 | * | |
1843 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1844 | */ | |
d1de00ef VS |
1845 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1846 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1847 | { |
939c2fe8 VS |
1848 | struct intel_crtc *intel_crtc = |
1849 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1850 | int reg; |
1851 | u32 val; | |
1852 | ||
1853 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1854 | assert_pipe_enabled(dev_priv, pipe); | |
1855 | ||
4c445e0e | 1856 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1857 | |
4c445e0e | 1858 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1859 | |
b24e7179 JB |
1860 | reg = DSPCNTR(plane); |
1861 | val = I915_READ(reg); | |
00d70b15 CW |
1862 | if (val & DISPLAY_PLANE_ENABLE) |
1863 | return; | |
1864 | ||
1865 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1866 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1867 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1868 | } | |
1869 | ||
b24e7179 | 1870 | /** |
d1de00ef | 1871 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1872 | * @dev_priv: i915 private structure |
1873 | * @plane: plane to disable | |
1874 | * @pipe: pipe consuming the data | |
1875 | * | |
1876 | * Disable @plane; should be an independent operation. | |
1877 | */ | |
d1de00ef VS |
1878 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1879 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1880 | { |
939c2fe8 VS |
1881 | struct intel_crtc *intel_crtc = |
1882 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1883 | int reg; |
1884 | u32 val; | |
1885 | ||
4c445e0e | 1886 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1887 | |
4c445e0e | 1888 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1889 | |
b24e7179 JB |
1890 | reg = DSPCNTR(plane); |
1891 | val = I915_READ(reg); | |
00d70b15 CW |
1892 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1893 | return; | |
1894 | ||
1895 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1896 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1897 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1898 | } | |
1899 | ||
693db184 CW |
1900 | static bool need_vtd_wa(struct drm_device *dev) |
1901 | { | |
1902 | #ifdef CONFIG_INTEL_IOMMU | |
1903 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1904 | return true; | |
1905 | #endif | |
1906 | return false; | |
1907 | } | |
1908 | ||
127bd2ac | 1909 | int |
48b956c5 | 1910 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1911 | struct drm_i915_gem_object *obj, |
919926ae | 1912 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1913 | { |
ce453d81 | 1914 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1915 | u32 alignment; |
1916 | int ret; | |
1917 | ||
05394f39 | 1918 | switch (obj->tiling_mode) { |
6b95a207 | 1919 | case I915_TILING_NONE: |
534843da CW |
1920 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1921 | alignment = 128 * 1024; | |
a6c45cf0 | 1922 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1923 | alignment = 4 * 1024; |
1924 | else | |
1925 | alignment = 64 * 1024; | |
6b95a207 KH |
1926 | break; |
1927 | case I915_TILING_X: | |
1928 | /* pin() will align the object as required by fence */ | |
1929 | alignment = 0; | |
1930 | break; | |
1931 | case I915_TILING_Y: | |
80075d49 | 1932 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1933 | return -EINVAL; |
1934 | default: | |
1935 | BUG(); | |
1936 | } | |
1937 | ||
693db184 CW |
1938 | /* Note that the w/a also requires 64 PTE of padding following the |
1939 | * bo. We currently fill all unused PTE with the shadow page and so | |
1940 | * we should always have valid PTE following the scanout preventing | |
1941 | * the VT-d warning. | |
1942 | */ | |
1943 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1944 | alignment = 256 * 1024; | |
1945 | ||
ce453d81 | 1946 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1947 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1948 | if (ret) |
ce453d81 | 1949 | goto err_interruptible; |
6b95a207 KH |
1950 | |
1951 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1952 | * fence, whereas 965+ only requires a fence if using | |
1953 | * framebuffer compression. For simplicity, we always install | |
1954 | * a fence as the cost is not that onerous. | |
1955 | */ | |
06d98131 | 1956 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1957 | if (ret) |
1958 | goto err_unpin; | |
1690e1eb | 1959 | |
9a5a53b3 | 1960 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1961 | |
ce453d81 | 1962 | dev_priv->mm.interruptible = true; |
6b95a207 | 1963 | return 0; |
48b956c5 CW |
1964 | |
1965 | err_unpin: | |
cc98b413 | 1966 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1967 | err_interruptible: |
1968 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1969 | return ret; |
6b95a207 KH |
1970 | } |
1971 | ||
1690e1eb CW |
1972 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1973 | { | |
1974 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 1975 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
1976 | } |
1977 | ||
c2c75131 DV |
1978 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1979 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1980 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1981 | unsigned int tiling_mode, | |
1982 | unsigned int cpp, | |
1983 | unsigned int pitch) | |
c2c75131 | 1984 | { |
bc752862 CW |
1985 | if (tiling_mode != I915_TILING_NONE) { |
1986 | unsigned int tile_rows, tiles; | |
c2c75131 | 1987 | |
bc752862 CW |
1988 | tile_rows = *y / 8; |
1989 | *y %= 8; | |
c2c75131 | 1990 | |
bc752862 CW |
1991 | tiles = *x / (512/cpp); |
1992 | *x %= 512/cpp; | |
1993 | ||
1994 | return tile_rows * pitch * 8 + tiles * 4096; | |
1995 | } else { | |
1996 | unsigned int offset; | |
1997 | ||
1998 | offset = *y * pitch + *x * cpp; | |
1999 | *y = 0; | |
2000 | *x = (offset & 4095) / cpp; | |
2001 | return offset & -4096; | |
2002 | } | |
c2c75131 DV |
2003 | } |
2004 | ||
17638cd6 JB |
2005 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2006 | int x, int y) | |
81255565 JB |
2007 | { |
2008 | struct drm_device *dev = crtc->dev; | |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2011 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2012 | struct drm_i915_gem_object *obj; |
81255565 | 2013 | int plane = intel_crtc->plane; |
e506a0c6 | 2014 | unsigned long linear_offset; |
81255565 | 2015 | u32 dspcntr; |
5eddb70b | 2016 | u32 reg; |
81255565 JB |
2017 | |
2018 | switch (plane) { | |
2019 | case 0: | |
2020 | case 1: | |
2021 | break; | |
2022 | default: | |
84f44ce7 | 2023 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2024 | return -EINVAL; |
2025 | } | |
2026 | ||
2027 | intel_fb = to_intel_framebuffer(fb); | |
2028 | obj = intel_fb->obj; | |
81255565 | 2029 | |
5eddb70b CW |
2030 | reg = DSPCNTR(plane); |
2031 | dspcntr = I915_READ(reg); | |
81255565 JB |
2032 | /* Mask out pixel format bits in case we change it */ |
2033 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2034 | switch (fb->pixel_format) { |
2035 | case DRM_FORMAT_C8: | |
81255565 JB |
2036 | dspcntr |= DISPPLANE_8BPP; |
2037 | break; | |
57779d06 VS |
2038 | case DRM_FORMAT_XRGB1555: |
2039 | case DRM_FORMAT_ARGB1555: | |
2040 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2041 | break; |
57779d06 VS |
2042 | case DRM_FORMAT_RGB565: |
2043 | dspcntr |= DISPPLANE_BGRX565; | |
2044 | break; | |
2045 | case DRM_FORMAT_XRGB8888: | |
2046 | case DRM_FORMAT_ARGB8888: | |
2047 | dspcntr |= DISPPLANE_BGRX888; | |
2048 | break; | |
2049 | case DRM_FORMAT_XBGR8888: | |
2050 | case DRM_FORMAT_ABGR8888: | |
2051 | dspcntr |= DISPPLANE_RGBX888; | |
2052 | break; | |
2053 | case DRM_FORMAT_XRGB2101010: | |
2054 | case DRM_FORMAT_ARGB2101010: | |
2055 | dspcntr |= DISPPLANE_BGRX101010; | |
2056 | break; | |
2057 | case DRM_FORMAT_XBGR2101010: | |
2058 | case DRM_FORMAT_ABGR2101010: | |
2059 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2060 | break; |
2061 | default: | |
baba133a | 2062 | BUG(); |
81255565 | 2063 | } |
57779d06 | 2064 | |
a6c45cf0 | 2065 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2066 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2067 | dspcntr |= DISPPLANE_TILED; |
2068 | else | |
2069 | dspcntr &= ~DISPPLANE_TILED; | |
2070 | } | |
2071 | ||
de1aa629 VS |
2072 | if (IS_G4X(dev)) |
2073 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2074 | ||
5eddb70b | 2075 | I915_WRITE(reg, dspcntr); |
81255565 | 2076 | |
e506a0c6 | 2077 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2078 | |
c2c75131 DV |
2079 | if (INTEL_INFO(dev)->gen >= 4) { |
2080 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2081 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2082 | fb->bits_per_pixel / 8, | |
2083 | fb->pitches[0]); | |
c2c75131 DV |
2084 | linear_offset -= intel_crtc->dspaddr_offset; |
2085 | } else { | |
e506a0c6 | 2086 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2087 | } |
e506a0c6 | 2088 | |
f343c5f6 BW |
2089 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2090 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2091 | fb->pitches[0]); | |
01f2c773 | 2092 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2093 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 | 2094 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2095 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
5eddb70b | 2096 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2097 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2098 | } else |
f343c5f6 | 2099 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2100 | POSTING_READ(reg); |
81255565 | 2101 | |
17638cd6 JB |
2102 | return 0; |
2103 | } | |
2104 | ||
2105 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2106 | struct drm_framebuffer *fb, int x, int y) | |
2107 | { | |
2108 | struct drm_device *dev = crtc->dev; | |
2109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2111 | struct intel_framebuffer *intel_fb; | |
2112 | struct drm_i915_gem_object *obj; | |
2113 | int plane = intel_crtc->plane; | |
e506a0c6 | 2114 | unsigned long linear_offset; |
17638cd6 JB |
2115 | u32 dspcntr; |
2116 | u32 reg; | |
2117 | ||
2118 | switch (plane) { | |
2119 | case 0: | |
2120 | case 1: | |
27f8227b | 2121 | case 2: |
17638cd6 JB |
2122 | break; |
2123 | default: | |
84f44ce7 | 2124 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2125 | return -EINVAL; |
2126 | } | |
2127 | ||
2128 | intel_fb = to_intel_framebuffer(fb); | |
2129 | obj = intel_fb->obj; | |
2130 | ||
2131 | reg = DSPCNTR(plane); | |
2132 | dspcntr = I915_READ(reg); | |
2133 | /* Mask out pixel format bits in case we change it */ | |
2134 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2135 | switch (fb->pixel_format) { |
2136 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2137 | dspcntr |= DISPPLANE_8BPP; |
2138 | break; | |
57779d06 VS |
2139 | case DRM_FORMAT_RGB565: |
2140 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2141 | break; |
57779d06 VS |
2142 | case DRM_FORMAT_XRGB8888: |
2143 | case DRM_FORMAT_ARGB8888: | |
2144 | dspcntr |= DISPPLANE_BGRX888; | |
2145 | break; | |
2146 | case DRM_FORMAT_XBGR8888: | |
2147 | case DRM_FORMAT_ABGR8888: | |
2148 | dspcntr |= DISPPLANE_RGBX888; | |
2149 | break; | |
2150 | case DRM_FORMAT_XRGB2101010: | |
2151 | case DRM_FORMAT_ARGB2101010: | |
2152 | dspcntr |= DISPPLANE_BGRX101010; | |
2153 | break; | |
2154 | case DRM_FORMAT_XBGR2101010: | |
2155 | case DRM_FORMAT_ABGR2101010: | |
2156 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2157 | break; |
2158 | default: | |
baba133a | 2159 | BUG(); |
17638cd6 JB |
2160 | } |
2161 | ||
2162 | if (obj->tiling_mode != I915_TILING_NONE) | |
2163 | dspcntr |= DISPPLANE_TILED; | |
2164 | else | |
2165 | dspcntr &= ~DISPPLANE_TILED; | |
2166 | ||
b42c6009 | 2167 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2168 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2169 | else | |
2170 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2171 | |
2172 | I915_WRITE(reg, dspcntr); | |
2173 | ||
e506a0c6 | 2174 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2175 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2176 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2177 | fb->bits_per_pixel / 8, | |
2178 | fb->pitches[0]); | |
c2c75131 | 2179 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2180 | |
f343c5f6 BW |
2181 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2182 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2183 | fb->pitches[0]); | |
01f2c773 | 2184 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 | 2185 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2186 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
b3dc685e | 2187 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2188 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2189 | } else { | |
2190 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2191 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2192 | } | |
17638cd6 JB |
2193 | POSTING_READ(reg); |
2194 | ||
2195 | return 0; | |
2196 | } | |
2197 | ||
2198 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2199 | static int | |
2200 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2201 | int x, int y, enum mode_set_atomic state) | |
2202 | { | |
2203 | struct drm_device *dev = crtc->dev; | |
2204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2205 | |
6b8e6ed0 CW |
2206 | if (dev_priv->display.disable_fbc) |
2207 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2208 | intel_increase_pllclock(crtc); |
81255565 | 2209 | |
6b8e6ed0 | 2210 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2211 | } |
2212 | ||
96a02917 VS |
2213 | void intel_display_handle_reset(struct drm_device *dev) |
2214 | { | |
2215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2216 | struct drm_crtc *crtc; | |
2217 | ||
2218 | /* | |
2219 | * Flips in the rings have been nuked by the reset, | |
2220 | * so complete all pending flips so that user space | |
2221 | * will get its events and not get stuck. | |
2222 | * | |
2223 | * Also update the base address of all primary | |
2224 | * planes to the the last fb to make sure we're | |
2225 | * showing the correct fb after a reset. | |
2226 | * | |
2227 | * Need to make two loops over the crtcs so that we | |
2228 | * don't try to grab a crtc mutex before the | |
2229 | * pending_flip_queue really got woken up. | |
2230 | */ | |
2231 | ||
2232 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2234 | enum plane plane = intel_crtc->plane; | |
2235 | ||
2236 | intel_prepare_page_flip(dev, plane); | |
2237 | intel_finish_page_flip_plane(dev, plane); | |
2238 | } | |
2239 | ||
2240 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2242 | ||
2243 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2244 | /* |
2245 | * FIXME: Once we have proper support for primary planes (and | |
2246 | * disabling them without disabling the entire crtc) allow again | |
2247 | * a NULL crtc->fb. | |
2248 | */ | |
2249 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2250 | dev_priv->display.update_plane(crtc, crtc->fb, |
2251 | crtc->x, crtc->y); | |
2252 | mutex_unlock(&crtc->mutex); | |
2253 | } | |
2254 | } | |
2255 | ||
14667a4b CW |
2256 | static int |
2257 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2258 | { | |
2259 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2260 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2261 | bool was_interruptible = dev_priv->mm.interruptible; | |
2262 | int ret; | |
2263 | ||
14667a4b CW |
2264 | /* Big Hammer, we also need to ensure that any pending |
2265 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2266 | * current scanout is retired before unpinning the old | |
2267 | * framebuffer. | |
2268 | * | |
2269 | * This should only fail upon a hung GPU, in which case we | |
2270 | * can safely continue. | |
2271 | */ | |
2272 | dev_priv->mm.interruptible = false; | |
2273 | ret = i915_gem_object_finish_gpu(obj); | |
2274 | dev_priv->mm.interruptible = was_interruptible; | |
2275 | ||
2276 | return ret; | |
2277 | } | |
2278 | ||
198598d0 VS |
2279 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2280 | { | |
2281 | struct drm_device *dev = crtc->dev; | |
2282 | struct drm_i915_master_private *master_priv; | |
2283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2284 | ||
2285 | if (!dev->primary->master) | |
2286 | return; | |
2287 | ||
2288 | master_priv = dev->primary->master->driver_priv; | |
2289 | if (!master_priv->sarea_priv) | |
2290 | return; | |
2291 | ||
2292 | switch (intel_crtc->pipe) { | |
2293 | case 0: | |
2294 | master_priv->sarea_priv->pipeA_x = x; | |
2295 | master_priv->sarea_priv->pipeA_y = y; | |
2296 | break; | |
2297 | case 1: | |
2298 | master_priv->sarea_priv->pipeB_x = x; | |
2299 | master_priv->sarea_priv->pipeB_y = y; | |
2300 | break; | |
2301 | default: | |
2302 | break; | |
2303 | } | |
2304 | } | |
2305 | ||
5c3b82e2 | 2306 | static int |
3c4fdcfb | 2307 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2308 | struct drm_framebuffer *fb) |
79e53945 JB |
2309 | { |
2310 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2311 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2313 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2314 | int ret; |
79e53945 JB |
2315 | |
2316 | /* no fb bound */ | |
94352cf9 | 2317 | if (!fb) { |
a5071c2f | 2318 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2319 | return 0; |
2320 | } | |
2321 | ||
7eb552ae | 2322 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2323 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2324 | plane_name(intel_crtc->plane), | |
2325 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2326 | return -EINVAL; |
79e53945 JB |
2327 | } |
2328 | ||
5c3b82e2 | 2329 | mutex_lock(&dev->struct_mutex); |
265db958 | 2330 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2331 | to_intel_framebuffer(fb)->obj, |
919926ae | 2332 | NULL); |
5c3b82e2 CW |
2333 | if (ret != 0) { |
2334 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2335 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2336 | return ret; |
2337 | } | |
79e53945 | 2338 | |
bb2043de DL |
2339 | /* |
2340 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2341 | * that in compute_mode_changes we check the native mode (not the pfit | |
2342 | * mode) to see if we can flip rather than do a full mode set. In the | |
2343 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2344 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2345 | * sized surface. | |
2346 | * | |
2347 | * To fix this properly, we need to hoist the checks up into | |
2348 | * compute_mode_changes (or above), check the actual pfit state and | |
2349 | * whether the platform allows pfit disable with pipe active, and only | |
2350 | * then update the pipesrc and pfit state, even on the flip path. | |
2351 | */ | |
4d6a3e63 | 2352 | if (i915_fastboot) { |
d7bf63f2 DL |
2353 | const struct drm_display_mode *adjusted_mode = |
2354 | &intel_crtc->config.adjusted_mode; | |
2355 | ||
4d6a3e63 | 2356 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2357 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2358 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2359 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2360 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2361 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2362 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2363 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2364 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2365 | } | |
2366 | } | |
2367 | ||
94352cf9 | 2368 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2369 | if (ret) { |
94352cf9 | 2370 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2371 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2372 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2373 | return ret; |
79e53945 | 2374 | } |
3c4fdcfb | 2375 | |
94352cf9 DV |
2376 | old_fb = crtc->fb; |
2377 | crtc->fb = fb; | |
6c4c86f5 DV |
2378 | crtc->x = x; |
2379 | crtc->y = y; | |
94352cf9 | 2380 | |
b7f1de28 | 2381 | if (old_fb) { |
d7697eea DV |
2382 | if (intel_crtc->active && old_fb != fb) |
2383 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2384 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2385 | } |
652c393a | 2386 | |
6b8e6ed0 | 2387 | intel_update_fbc(dev); |
4906557e | 2388 | intel_edp_psr_update(dev); |
5c3b82e2 | 2389 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2390 | |
198598d0 | 2391 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2392 | |
2393 | return 0; | |
79e53945 JB |
2394 | } |
2395 | ||
5e84e1a4 ZW |
2396 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2397 | { | |
2398 | struct drm_device *dev = crtc->dev; | |
2399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2401 | int pipe = intel_crtc->pipe; | |
2402 | u32 reg, temp; | |
2403 | ||
2404 | /* enable normal train */ | |
2405 | reg = FDI_TX_CTL(pipe); | |
2406 | temp = I915_READ(reg); | |
61e499bf | 2407 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2408 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2409 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2410 | } else { |
2411 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2412 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2413 | } |
5e84e1a4 ZW |
2414 | I915_WRITE(reg, temp); |
2415 | ||
2416 | reg = FDI_RX_CTL(pipe); | |
2417 | temp = I915_READ(reg); | |
2418 | if (HAS_PCH_CPT(dev)) { | |
2419 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2420 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2421 | } else { | |
2422 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2423 | temp |= FDI_LINK_TRAIN_NONE; | |
2424 | } | |
2425 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2426 | ||
2427 | /* wait one idle pattern time */ | |
2428 | POSTING_READ(reg); | |
2429 | udelay(1000); | |
357555c0 JB |
2430 | |
2431 | /* IVB wants error correction enabled */ | |
2432 | if (IS_IVYBRIDGE(dev)) | |
2433 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2434 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2435 | } |
2436 | ||
1fbc0d78 | 2437 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2438 | { |
1fbc0d78 DV |
2439 | return crtc->base.enabled && crtc->active && |
2440 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2441 | } |
2442 | ||
01a415fd DV |
2443 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2444 | { | |
2445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2446 | struct intel_crtc *pipe_B_crtc = | |
2447 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2448 | struct intel_crtc *pipe_C_crtc = | |
2449 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2450 | uint32_t temp; | |
2451 | ||
1e833f40 DV |
2452 | /* |
2453 | * When everything is off disable fdi C so that we could enable fdi B | |
2454 | * with all lanes. Note that we don't care about enabled pipes without | |
2455 | * an enabled pch encoder. | |
2456 | */ | |
2457 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2458 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2459 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2460 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2461 | ||
2462 | temp = I915_READ(SOUTH_CHICKEN1); | |
2463 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2464 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2465 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2466 | } | |
2467 | } | |
2468 | ||
8db9d77b ZW |
2469 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2470 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2471 | { | |
2472 | struct drm_device *dev = crtc->dev; | |
2473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2475 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2476 | int plane = intel_crtc->plane; |
5eddb70b | 2477 | u32 reg, temp, tries; |
8db9d77b | 2478 | |
0fc932b8 JB |
2479 | /* FDI needs bits from pipe & plane first */ |
2480 | assert_pipe_enabled(dev_priv, pipe); | |
2481 | assert_plane_enabled(dev_priv, plane); | |
2482 | ||
e1a44743 AJ |
2483 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2484 | for train result */ | |
5eddb70b CW |
2485 | reg = FDI_RX_IMR(pipe); |
2486 | temp = I915_READ(reg); | |
e1a44743 AJ |
2487 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2488 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2489 | I915_WRITE(reg, temp); |
2490 | I915_READ(reg); | |
e1a44743 AJ |
2491 | udelay(150); |
2492 | ||
8db9d77b | 2493 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2494 | reg = FDI_TX_CTL(pipe); |
2495 | temp = I915_READ(reg); | |
627eb5a3 DV |
2496 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2497 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2498 | temp &= ~FDI_LINK_TRAIN_NONE; |
2499 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2500 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2501 | |
5eddb70b CW |
2502 | reg = FDI_RX_CTL(pipe); |
2503 | temp = I915_READ(reg); | |
8db9d77b ZW |
2504 | temp &= ~FDI_LINK_TRAIN_NONE; |
2505 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2506 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2507 | ||
2508 | POSTING_READ(reg); | |
8db9d77b ZW |
2509 | udelay(150); |
2510 | ||
5b2adf89 | 2511 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2512 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2513 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2514 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2515 | |
5eddb70b | 2516 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2517 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2518 | temp = I915_READ(reg); |
8db9d77b ZW |
2519 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2520 | ||
2521 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2522 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2523 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2524 | break; |
2525 | } | |
8db9d77b | 2526 | } |
e1a44743 | 2527 | if (tries == 5) |
5eddb70b | 2528 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2529 | |
2530 | /* Train 2 */ | |
5eddb70b CW |
2531 | reg = FDI_TX_CTL(pipe); |
2532 | temp = I915_READ(reg); | |
8db9d77b ZW |
2533 | temp &= ~FDI_LINK_TRAIN_NONE; |
2534 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2535 | I915_WRITE(reg, temp); |
8db9d77b | 2536 | |
5eddb70b CW |
2537 | reg = FDI_RX_CTL(pipe); |
2538 | temp = I915_READ(reg); | |
8db9d77b ZW |
2539 | temp &= ~FDI_LINK_TRAIN_NONE; |
2540 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2541 | I915_WRITE(reg, temp); |
8db9d77b | 2542 | |
5eddb70b CW |
2543 | POSTING_READ(reg); |
2544 | udelay(150); | |
8db9d77b | 2545 | |
5eddb70b | 2546 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2547 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2548 | temp = I915_READ(reg); |
8db9d77b ZW |
2549 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2550 | ||
2551 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2552 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2553 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2554 | break; | |
2555 | } | |
8db9d77b | 2556 | } |
e1a44743 | 2557 | if (tries == 5) |
5eddb70b | 2558 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2559 | |
2560 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2561 | |
8db9d77b ZW |
2562 | } |
2563 | ||
0206e353 | 2564 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2565 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2566 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2567 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2568 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2569 | }; | |
2570 | ||
2571 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2572 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2573 | { | |
2574 | struct drm_device *dev = crtc->dev; | |
2575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2577 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2578 | u32 reg, temp, i, retry; |
8db9d77b | 2579 | |
e1a44743 AJ |
2580 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2581 | for train result */ | |
5eddb70b CW |
2582 | reg = FDI_RX_IMR(pipe); |
2583 | temp = I915_READ(reg); | |
e1a44743 AJ |
2584 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2585 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2586 | I915_WRITE(reg, temp); |
2587 | ||
2588 | POSTING_READ(reg); | |
e1a44743 AJ |
2589 | udelay(150); |
2590 | ||
8db9d77b | 2591 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2592 | reg = FDI_TX_CTL(pipe); |
2593 | temp = I915_READ(reg); | |
627eb5a3 DV |
2594 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2595 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2596 | temp &= ~FDI_LINK_TRAIN_NONE; |
2597 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2598 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2599 | /* SNB-B */ | |
2600 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2601 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2602 | |
d74cf324 DV |
2603 | I915_WRITE(FDI_RX_MISC(pipe), |
2604 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2605 | ||
5eddb70b CW |
2606 | reg = FDI_RX_CTL(pipe); |
2607 | temp = I915_READ(reg); | |
8db9d77b ZW |
2608 | if (HAS_PCH_CPT(dev)) { |
2609 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2610 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2611 | } else { | |
2612 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2613 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2614 | } | |
5eddb70b CW |
2615 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2616 | ||
2617 | POSTING_READ(reg); | |
8db9d77b ZW |
2618 | udelay(150); |
2619 | ||
0206e353 | 2620 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2621 | reg = FDI_TX_CTL(pipe); |
2622 | temp = I915_READ(reg); | |
8db9d77b ZW |
2623 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2624 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2625 | I915_WRITE(reg, temp); |
2626 | ||
2627 | POSTING_READ(reg); | |
8db9d77b ZW |
2628 | udelay(500); |
2629 | ||
fa37d39e SP |
2630 | for (retry = 0; retry < 5; retry++) { |
2631 | reg = FDI_RX_IIR(pipe); | |
2632 | temp = I915_READ(reg); | |
2633 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2634 | if (temp & FDI_RX_BIT_LOCK) { | |
2635 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2636 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2637 | break; | |
2638 | } | |
2639 | udelay(50); | |
8db9d77b | 2640 | } |
fa37d39e SP |
2641 | if (retry < 5) |
2642 | break; | |
8db9d77b ZW |
2643 | } |
2644 | if (i == 4) | |
5eddb70b | 2645 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2646 | |
2647 | /* Train 2 */ | |
5eddb70b CW |
2648 | reg = FDI_TX_CTL(pipe); |
2649 | temp = I915_READ(reg); | |
8db9d77b ZW |
2650 | temp &= ~FDI_LINK_TRAIN_NONE; |
2651 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2652 | if (IS_GEN6(dev)) { | |
2653 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2654 | /* SNB-B */ | |
2655 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2656 | } | |
5eddb70b | 2657 | I915_WRITE(reg, temp); |
8db9d77b | 2658 | |
5eddb70b CW |
2659 | reg = FDI_RX_CTL(pipe); |
2660 | temp = I915_READ(reg); | |
8db9d77b ZW |
2661 | if (HAS_PCH_CPT(dev)) { |
2662 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2663 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2664 | } else { | |
2665 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2666 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2667 | } | |
5eddb70b CW |
2668 | I915_WRITE(reg, temp); |
2669 | ||
2670 | POSTING_READ(reg); | |
8db9d77b ZW |
2671 | udelay(150); |
2672 | ||
0206e353 | 2673 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2674 | reg = FDI_TX_CTL(pipe); |
2675 | temp = I915_READ(reg); | |
8db9d77b ZW |
2676 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2677 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2678 | I915_WRITE(reg, temp); |
2679 | ||
2680 | POSTING_READ(reg); | |
8db9d77b ZW |
2681 | udelay(500); |
2682 | ||
fa37d39e SP |
2683 | for (retry = 0; retry < 5; retry++) { |
2684 | reg = FDI_RX_IIR(pipe); | |
2685 | temp = I915_READ(reg); | |
2686 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2687 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2688 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2689 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2690 | break; | |
2691 | } | |
2692 | udelay(50); | |
8db9d77b | 2693 | } |
fa37d39e SP |
2694 | if (retry < 5) |
2695 | break; | |
8db9d77b ZW |
2696 | } |
2697 | if (i == 4) | |
5eddb70b | 2698 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2699 | |
2700 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2701 | } | |
2702 | ||
357555c0 JB |
2703 | /* Manual link training for Ivy Bridge A0 parts */ |
2704 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2705 | { | |
2706 | struct drm_device *dev = crtc->dev; | |
2707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2709 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2710 | u32 reg, temp, i, j; |
357555c0 JB |
2711 | |
2712 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2713 | for train result */ | |
2714 | reg = FDI_RX_IMR(pipe); | |
2715 | temp = I915_READ(reg); | |
2716 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2717 | temp &= ~FDI_RX_BIT_LOCK; | |
2718 | I915_WRITE(reg, temp); | |
2719 | ||
2720 | POSTING_READ(reg); | |
2721 | udelay(150); | |
2722 | ||
01a415fd DV |
2723 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2724 | I915_READ(FDI_RX_IIR(pipe))); | |
2725 | ||
139ccd3f JB |
2726 | /* Try each vswing and preemphasis setting twice before moving on */ |
2727 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2728 | /* disable first in case we need to retry */ | |
2729 | reg = FDI_TX_CTL(pipe); | |
2730 | temp = I915_READ(reg); | |
2731 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2732 | temp &= ~FDI_TX_ENABLE; | |
2733 | I915_WRITE(reg, temp); | |
357555c0 | 2734 | |
139ccd3f JB |
2735 | reg = FDI_RX_CTL(pipe); |
2736 | temp = I915_READ(reg); | |
2737 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2738 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2739 | temp &= ~FDI_RX_ENABLE; | |
2740 | I915_WRITE(reg, temp); | |
357555c0 | 2741 | |
139ccd3f | 2742 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2743 | reg = FDI_TX_CTL(pipe); |
2744 | temp = I915_READ(reg); | |
139ccd3f JB |
2745 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2746 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2747 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2748 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2749 | temp |= snb_b_fdi_train_param[j/2]; |
2750 | temp |= FDI_COMPOSITE_SYNC; | |
2751 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2752 | |
139ccd3f JB |
2753 | I915_WRITE(FDI_RX_MISC(pipe), |
2754 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2755 | |
139ccd3f | 2756 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2757 | temp = I915_READ(reg); |
139ccd3f JB |
2758 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2759 | temp |= FDI_COMPOSITE_SYNC; | |
2760 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2761 | |
139ccd3f JB |
2762 | POSTING_READ(reg); |
2763 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2764 | |
139ccd3f JB |
2765 | for (i = 0; i < 4; i++) { |
2766 | reg = FDI_RX_IIR(pipe); | |
2767 | temp = I915_READ(reg); | |
2768 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2769 | |
139ccd3f JB |
2770 | if (temp & FDI_RX_BIT_LOCK || |
2771 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2772 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2773 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2774 | i); | |
2775 | break; | |
2776 | } | |
2777 | udelay(1); /* should be 0.5us */ | |
2778 | } | |
2779 | if (i == 4) { | |
2780 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2781 | continue; | |
2782 | } | |
357555c0 | 2783 | |
139ccd3f | 2784 | /* Train 2 */ |
357555c0 JB |
2785 | reg = FDI_TX_CTL(pipe); |
2786 | temp = I915_READ(reg); | |
139ccd3f JB |
2787 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2788 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2789 | I915_WRITE(reg, temp); | |
2790 | ||
2791 | reg = FDI_RX_CTL(pipe); | |
2792 | temp = I915_READ(reg); | |
2793 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2794 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2795 | I915_WRITE(reg, temp); |
2796 | ||
2797 | POSTING_READ(reg); | |
139ccd3f | 2798 | udelay(2); /* should be 1.5us */ |
357555c0 | 2799 | |
139ccd3f JB |
2800 | for (i = 0; i < 4; i++) { |
2801 | reg = FDI_RX_IIR(pipe); | |
2802 | temp = I915_READ(reg); | |
2803 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2804 | |
139ccd3f JB |
2805 | if (temp & FDI_RX_SYMBOL_LOCK || |
2806 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2807 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2808 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2809 | i); | |
2810 | goto train_done; | |
2811 | } | |
2812 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2813 | } |
139ccd3f JB |
2814 | if (i == 4) |
2815 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2816 | } |
357555c0 | 2817 | |
139ccd3f | 2818 | train_done: |
357555c0 JB |
2819 | DRM_DEBUG_KMS("FDI train done.\n"); |
2820 | } | |
2821 | ||
88cefb6c | 2822 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2823 | { |
88cefb6c | 2824 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2825 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2826 | int pipe = intel_crtc->pipe; |
5eddb70b | 2827 | u32 reg, temp; |
79e53945 | 2828 | |
c64e311e | 2829 | |
c98e9dcf | 2830 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2831 | reg = FDI_RX_CTL(pipe); |
2832 | temp = I915_READ(reg); | |
627eb5a3 DV |
2833 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2834 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2835 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2836 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2837 | ||
2838 | POSTING_READ(reg); | |
c98e9dcf JB |
2839 | udelay(200); |
2840 | ||
2841 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2842 | temp = I915_READ(reg); |
2843 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2844 | ||
2845 | POSTING_READ(reg); | |
c98e9dcf JB |
2846 | udelay(200); |
2847 | ||
20749730 PZ |
2848 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2849 | reg = FDI_TX_CTL(pipe); | |
2850 | temp = I915_READ(reg); | |
2851 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2852 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2853 | |
20749730 PZ |
2854 | POSTING_READ(reg); |
2855 | udelay(100); | |
6be4a607 | 2856 | } |
0e23b99d JB |
2857 | } |
2858 | ||
88cefb6c DV |
2859 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2860 | { | |
2861 | struct drm_device *dev = intel_crtc->base.dev; | |
2862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2863 | int pipe = intel_crtc->pipe; | |
2864 | u32 reg, temp; | |
2865 | ||
2866 | /* Switch from PCDclk to Rawclk */ | |
2867 | reg = FDI_RX_CTL(pipe); | |
2868 | temp = I915_READ(reg); | |
2869 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2870 | ||
2871 | /* Disable CPU FDI TX PLL */ | |
2872 | reg = FDI_TX_CTL(pipe); | |
2873 | temp = I915_READ(reg); | |
2874 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2875 | ||
2876 | POSTING_READ(reg); | |
2877 | udelay(100); | |
2878 | ||
2879 | reg = FDI_RX_CTL(pipe); | |
2880 | temp = I915_READ(reg); | |
2881 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2882 | ||
2883 | /* Wait for the clocks to turn off. */ | |
2884 | POSTING_READ(reg); | |
2885 | udelay(100); | |
2886 | } | |
2887 | ||
0fc932b8 JB |
2888 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2889 | { | |
2890 | struct drm_device *dev = crtc->dev; | |
2891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2892 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2893 | int pipe = intel_crtc->pipe; | |
2894 | u32 reg, temp; | |
2895 | ||
2896 | /* disable CPU FDI tx and PCH FDI rx */ | |
2897 | reg = FDI_TX_CTL(pipe); | |
2898 | temp = I915_READ(reg); | |
2899 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2900 | POSTING_READ(reg); | |
2901 | ||
2902 | reg = FDI_RX_CTL(pipe); | |
2903 | temp = I915_READ(reg); | |
2904 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2905 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2906 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2907 | ||
2908 | POSTING_READ(reg); | |
2909 | udelay(100); | |
2910 | ||
2911 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2912 | if (HAS_PCH_IBX(dev)) { |
2913 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2914 | } |
0fc932b8 JB |
2915 | |
2916 | /* still set train pattern 1 */ | |
2917 | reg = FDI_TX_CTL(pipe); | |
2918 | temp = I915_READ(reg); | |
2919 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2920 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2921 | I915_WRITE(reg, temp); | |
2922 | ||
2923 | reg = FDI_RX_CTL(pipe); | |
2924 | temp = I915_READ(reg); | |
2925 | if (HAS_PCH_CPT(dev)) { | |
2926 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2927 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2928 | } else { | |
2929 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2930 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2931 | } | |
2932 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2933 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2934 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2935 | I915_WRITE(reg, temp); |
2936 | ||
2937 | POSTING_READ(reg); | |
2938 | udelay(100); | |
2939 | } | |
2940 | ||
5bb61643 CW |
2941 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2942 | { | |
2943 | struct drm_device *dev = crtc->dev; | |
2944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2946 | unsigned long flags; |
2947 | bool pending; | |
2948 | ||
10d83730 VS |
2949 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2950 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2951 | return false; |
2952 | ||
2953 | spin_lock_irqsave(&dev->event_lock, flags); | |
2954 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2955 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2956 | ||
2957 | return pending; | |
2958 | } | |
2959 | ||
e6c3a2a6 CW |
2960 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2961 | { | |
0f91128d | 2962 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2963 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2964 | |
2965 | if (crtc->fb == NULL) | |
2966 | return; | |
2967 | ||
2c10d571 DV |
2968 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2969 | ||
5bb61643 CW |
2970 | wait_event(dev_priv->pending_flip_queue, |
2971 | !intel_crtc_has_pending_flip(crtc)); | |
2972 | ||
0f91128d CW |
2973 | mutex_lock(&dev->struct_mutex); |
2974 | intel_finish_fb(crtc->fb); | |
2975 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2976 | } |
2977 | ||
e615efe4 ED |
2978 | /* Program iCLKIP clock to the desired frequency */ |
2979 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2980 | { | |
2981 | struct drm_device *dev = crtc->dev; | |
2982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 2983 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
2984 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2985 | u32 temp; | |
2986 | ||
09153000 DV |
2987 | mutex_lock(&dev_priv->dpio_lock); |
2988 | ||
e615efe4 ED |
2989 | /* It is necessary to ungate the pixclk gate prior to programming |
2990 | * the divisors, and gate it back when it is done. | |
2991 | */ | |
2992 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2993 | ||
2994 | /* Disable SSCCTL */ | |
2995 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2996 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2997 | SBI_SSCCTL_DISABLE, | |
2998 | SBI_ICLK); | |
e615efe4 ED |
2999 | |
3000 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3001 | if (clock == 20000) { |
e615efe4 ED |
3002 | auxdiv = 1; |
3003 | divsel = 0x41; | |
3004 | phaseinc = 0x20; | |
3005 | } else { | |
3006 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3007 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3008 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3009 | * convert the virtual clock precision to KHz here for higher |
3010 | * precision. | |
3011 | */ | |
3012 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3013 | u32 iclk_pi_range = 64; | |
3014 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3015 | ||
12d7ceed | 3016 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3017 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3018 | pi_value = desired_divisor % iclk_pi_range; | |
3019 | ||
3020 | auxdiv = 0; | |
3021 | divsel = msb_divisor_value - 2; | |
3022 | phaseinc = pi_value; | |
3023 | } | |
3024 | ||
3025 | /* This should not happen with any sane values */ | |
3026 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3027 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3028 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3029 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3030 | ||
3031 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3032 | clock, |
e615efe4 ED |
3033 | auxdiv, |
3034 | divsel, | |
3035 | phasedir, | |
3036 | phaseinc); | |
3037 | ||
3038 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3039 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3040 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3041 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3042 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3043 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3044 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3045 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3046 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3047 | |
3048 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3049 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3050 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3051 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3052 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3053 | |
3054 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3055 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3056 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3057 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3058 | |
3059 | /* Wait for initialization time */ | |
3060 | udelay(24); | |
3061 | ||
3062 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3063 | |
3064 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3065 | } |
3066 | ||
275f01b2 DV |
3067 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3068 | enum pipe pch_transcoder) | |
3069 | { | |
3070 | struct drm_device *dev = crtc->base.dev; | |
3071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3072 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3073 | ||
3074 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3075 | I915_READ(HTOTAL(cpu_transcoder))); | |
3076 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3077 | I915_READ(HBLANK(cpu_transcoder))); | |
3078 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3079 | I915_READ(HSYNC(cpu_transcoder))); | |
3080 | ||
3081 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3082 | I915_READ(VTOTAL(cpu_transcoder))); | |
3083 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3084 | I915_READ(VBLANK(cpu_transcoder))); | |
3085 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3086 | I915_READ(VSYNC(cpu_transcoder))); | |
3087 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3088 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3089 | } | |
3090 | ||
1fbc0d78 DV |
3091 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3092 | { | |
3093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3094 | uint32_t temp; | |
3095 | ||
3096 | temp = I915_READ(SOUTH_CHICKEN1); | |
3097 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3098 | return; | |
3099 | ||
3100 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3101 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3102 | ||
3103 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3104 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3105 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3106 | POSTING_READ(SOUTH_CHICKEN1); | |
3107 | } | |
3108 | ||
3109 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3110 | { | |
3111 | struct drm_device *dev = intel_crtc->base.dev; | |
3112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3113 | ||
3114 | switch (intel_crtc->pipe) { | |
3115 | case PIPE_A: | |
3116 | break; | |
3117 | case PIPE_B: | |
3118 | if (intel_crtc->config.fdi_lanes > 2) | |
3119 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3120 | else | |
3121 | cpt_enable_fdi_bc_bifurcation(dev); | |
3122 | ||
3123 | break; | |
3124 | case PIPE_C: | |
3125 | cpt_enable_fdi_bc_bifurcation(dev); | |
3126 | ||
3127 | break; | |
3128 | default: | |
3129 | BUG(); | |
3130 | } | |
3131 | } | |
3132 | ||
f67a559d JB |
3133 | /* |
3134 | * Enable PCH resources required for PCH ports: | |
3135 | * - PCH PLLs | |
3136 | * - FDI training & RX/TX | |
3137 | * - update transcoder timings | |
3138 | * - DP transcoding bits | |
3139 | * - transcoder | |
3140 | */ | |
3141 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3142 | { |
3143 | struct drm_device *dev = crtc->dev; | |
3144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3146 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3147 | u32 reg, temp; |
2c07245f | 3148 | |
ab9412ba | 3149 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3150 | |
1fbc0d78 DV |
3151 | if (IS_IVYBRIDGE(dev)) |
3152 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3153 | ||
cd986abb DV |
3154 | /* Write the TU size bits before fdi link training, so that error |
3155 | * detection works. */ | |
3156 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3157 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3158 | ||
c98e9dcf | 3159 | /* For PCH output, training FDI link */ |
674cf967 | 3160 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3161 | |
3ad8a208 DV |
3162 | /* We need to program the right clock selection before writing the pixel |
3163 | * mutliplier into the DPLL. */ | |
303b81e0 | 3164 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3165 | u32 sel; |
4b645f14 | 3166 | |
c98e9dcf | 3167 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3168 | temp |= TRANS_DPLL_ENABLE(pipe); |
3169 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3170 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3171 | temp |= sel; |
3172 | else | |
3173 | temp &= ~sel; | |
c98e9dcf | 3174 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3175 | } |
5eddb70b | 3176 | |
3ad8a208 DV |
3177 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3178 | * transcoder, and we actually should do this to not upset any PCH | |
3179 | * transcoder that already use the clock when we share it. | |
3180 | * | |
3181 | * Note that enable_shared_dpll tries to do the right thing, but | |
3182 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3183 | * the right LVDS enable sequence. */ | |
3184 | ironlake_enable_shared_dpll(intel_crtc); | |
3185 | ||
d9b6cb56 JB |
3186 | /* set transcoder timing, panel must allow it */ |
3187 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3188 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3189 | |
303b81e0 | 3190 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3191 | |
c98e9dcf JB |
3192 | /* For PCH DP, enable TRANS_DP_CTL */ |
3193 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3194 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3195 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3196 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3197 | reg = TRANS_DP_CTL(pipe); |
3198 | temp = I915_READ(reg); | |
3199 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3200 | TRANS_DP_SYNC_MASK | |
3201 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3202 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3203 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3204 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3205 | |
3206 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3207 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3208 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3209 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3210 | |
3211 | switch (intel_trans_dp_port_sel(crtc)) { | |
3212 | case PCH_DP_B: | |
5eddb70b | 3213 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3214 | break; |
3215 | case PCH_DP_C: | |
5eddb70b | 3216 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3217 | break; |
3218 | case PCH_DP_D: | |
5eddb70b | 3219 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3220 | break; |
3221 | default: | |
e95d41e1 | 3222 | BUG(); |
32f9d658 | 3223 | } |
2c07245f | 3224 | |
5eddb70b | 3225 | I915_WRITE(reg, temp); |
6be4a607 | 3226 | } |
b52eb4dc | 3227 | |
b8a4f404 | 3228 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3229 | } |
3230 | ||
1507e5bd PZ |
3231 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3232 | { | |
3233 | struct drm_device *dev = crtc->dev; | |
3234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3236 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3237 | |
ab9412ba | 3238 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3239 | |
8c52b5e8 | 3240 | lpt_program_iclkip(crtc); |
1507e5bd | 3241 | |
0540e488 | 3242 | /* Set transcoder timing. */ |
275f01b2 | 3243 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3244 | |
937bb610 | 3245 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3246 | } |
3247 | ||
e2b78267 | 3248 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3249 | { |
e2b78267 | 3250 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3251 | |
3252 | if (pll == NULL) | |
3253 | return; | |
3254 | ||
3255 | if (pll->refcount == 0) { | |
46edb027 | 3256 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3257 | return; |
3258 | } | |
3259 | ||
f4a091c7 DV |
3260 | if (--pll->refcount == 0) { |
3261 | WARN_ON(pll->on); | |
3262 | WARN_ON(pll->active); | |
3263 | } | |
3264 | ||
a43f6e0f | 3265 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3266 | } |
3267 | ||
b89a1d39 | 3268 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3269 | { |
e2b78267 DV |
3270 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3271 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3272 | enum intel_dpll_id i; | |
ee7b9f93 | 3273 | |
ee7b9f93 | 3274 | if (pll) { |
46edb027 DV |
3275 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3276 | crtc->base.base.id, pll->name); | |
e2b78267 | 3277 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3278 | } |
3279 | ||
98b6bd99 DV |
3280 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3281 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3282 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3283 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3284 | |
46edb027 DV |
3285 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3286 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3287 | |
3288 | goto found; | |
3289 | } | |
3290 | ||
e72f9fbf DV |
3291 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3292 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3293 | |
3294 | /* Only want to check enabled timings first */ | |
3295 | if (pll->refcount == 0) | |
3296 | continue; | |
3297 | ||
b89a1d39 DV |
3298 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3299 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3300 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3301 | crtc->base.base.id, |
46edb027 | 3302 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3303 | |
3304 | goto found; | |
3305 | } | |
3306 | } | |
3307 | ||
3308 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3309 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3310 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3311 | if (pll->refcount == 0) { |
46edb027 DV |
3312 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3313 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3314 | goto found; |
3315 | } | |
3316 | } | |
3317 | ||
3318 | return NULL; | |
3319 | ||
3320 | found: | |
a43f6e0f | 3321 | crtc->config.shared_dpll = i; |
46edb027 DV |
3322 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3323 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3324 | |
cdbd2316 | 3325 | if (pll->active == 0) { |
66e985c0 DV |
3326 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3327 | sizeof(pll->hw_state)); | |
3328 | ||
46edb027 | 3329 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3330 | WARN_ON(pll->on); |
e9d6944e | 3331 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3332 | |
15bdd4cf | 3333 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3334 | } |
3335 | pll->refcount++; | |
e04c7350 | 3336 | |
ee7b9f93 JB |
3337 | return pll; |
3338 | } | |
3339 | ||
a1520318 | 3340 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3341 | { |
3342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3343 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3344 | u32 temp; |
3345 | ||
3346 | temp = I915_READ(dslreg); | |
3347 | udelay(500); | |
3348 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3349 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3350 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3351 | } |
3352 | } | |
3353 | ||
b074cec8 JB |
3354 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3355 | { | |
3356 | struct drm_device *dev = crtc->base.dev; | |
3357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3358 | int pipe = crtc->pipe; | |
3359 | ||
fd4daa9c | 3360 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3361 | /* Force use of hard-coded filter coefficients |
3362 | * as some pre-programmed values are broken, | |
3363 | * e.g. x201. | |
3364 | */ | |
3365 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3366 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3367 | PF_PIPE_SEL_IVB(pipe)); | |
3368 | else | |
3369 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3370 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3371 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3372 | } |
3373 | } | |
3374 | ||
bb53d4ae VS |
3375 | static void intel_enable_planes(struct drm_crtc *crtc) |
3376 | { | |
3377 | struct drm_device *dev = crtc->dev; | |
3378 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3379 | struct intel_plane *intel_plane; | |
3380 | ||
3381 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3382 | if (intel_plane->pipe == pipe) | |
3383 | intel_plane_restore(&intel_plane->base); | |
3384 | } | |
3385 | ||
3386 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3387 | { | |
3388 | struct drm_device *dev = crtc->dev; | |
3389 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3390 | struct intel_plane *intel_plane; | |
3391 | ||
3392 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3393 | if (intel_plane->pipe == pipe) | |
3394 | intel_plane_disable(&intel_plane->base); | |
3395 | } | |
3396 | ||
20bc8673 | 3397 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3398 | { |
3399 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3400 | ||
3401 | if (!crtc->config.ips_enabled) | |
3402 | return; | |
3403 | ||
3404 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3405 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3406 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3407 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3408 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3409 | if (IS_BROADWELL(crtc->base.dev)) { |
3410 | mutex_lock(&dev_priv->rps.hw_lock); | |
3411 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3412 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3413 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3414 | * value in IPS_CTL bit 31 after enabling IPS through the | |
3415 | * mailbox." Therefore we need to defer waiting on the state | |
3416 | * change. | |
3417 | * TODO: need to fix this for state checker | |
3418 | */ | |
3419 | } else { | |
3420 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3421 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3422 | * is essentially intel_wait_for_vblank. If we don't have this | |
3423 | * and don't wait for vblanks until the end of crtc_enable, then | |
3424 | * the HW state readout code will complain that the expected | |
3425 | * IPS_CTL value is not the one we read. */ | |
3426 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3427 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3428 | } | |
d77e4531 PZ |
3429 | } |
3430 | ||
20bc8673 | 3431 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3432 | { |
3433 | struct drm_device *dev = crtc->base.dev; | |
3434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3435 | ||
3436 | if (!crtc->config.ips_enabled) | |
3437 | return; | |
3438 | ||
3439 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3440 | if (IS_BROADWELL(crtc->base.dev)) { |
3441 | mutex_lock(&dev_priv->rps.hw_lock); | |
3442 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3443 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3444 | } else | |
3445 | I915_WRITE(IPS_CTL, 0); | |
d77e4531 PZ |
3446 | POSTING_READ(IPS_CTL); |
3447 | ||
3448 | /* We need to wait for a vblank before we can disable the plane. */ | |
3449 | intel_wait_for_vblank(dev, crtc->pipe); | |
3450 | } | |
3451 | ||
3452 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3453 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3454 | { | |
3455 | struct drm_device *dev = crtc->dev; | |
3456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3458 | enum pipe pipe = intel_crtc->pipe; | |
3459 | int palreg = PALETTE(pipe); | |
3460 | int i; | |
3461 | bool reenable_ips = false; | |
3462 | ||
3463 | /* The clocks have to be on to load the palette. */ | |
3464 | if (!crtc->enabled || !intel_crtc->active) | |
3465 | return; | |
3466 | ||
3467 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3468 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3469 | assert_dsi_pll_enabled(dev_priv); | |
3470 | else | |
3471 | assert_pll_enabled(dev_priv, pipe); | |
3472 | } | |
3473 | ||
3474 | /* use legacy palette for Ironlake */ | |
3475 | if (HAS_PCH_SPLIT(dev)) | |
3476 | palreg = LGC_PALETTE(pipe); | |
3477 | ||
3478 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3479 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3480 | */ | |
3481 | if (intel_crtc->config.ips_enabled && | |
3482 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == | |
3483 | GAMMA_MODE_MODE_SPLIT)) { | |
3484 | hsw_disable_ips(intel_crtc); | |
3485 | reenable_ips = true; | |
3486 | } | |
3487 | ||
3488 | for (i = 0; i < 256; i++) { | |
3489 | I915_WRITE(palreg + 4 * i, | |
3490 | (intel_crtc->lut_r[i] << 16) | | |
3491 | (intel_crtc->lut_g[i] << 8) | | |
3492 | intel_crtc->lut_b[i]); | |
3493 | } | |
3494 | ||
3495 | if (reenable_ips) | |
3496 | hsw_enable_ips(intel_crtc); | |
3497 | } | |
3498 | ||
f67a559d JB |
3499 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3500 | { | |
3501 | struct drm_device *dev = crtc->dev; | |
3502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3504 | struct intel_encoder *encoder; |
f67a559d JB |
3505 | int pipe = intel_crtc->pipe; |
3506 | int plane = intel_crtc->plane; | |
f67a559d | 3507 | |
08a48469 DV |
3508 | WARN_ON(!crtc->enabled); |
3509 | ||
f67a559d JB |
3510 | if (intel_crtc->active) |
3511 | return; | |
3512 | ||
3513 | intel_crtc->active = true; | |
8664281b PZ |
3514 | |
3515 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3516 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3517 | ||
f6736a1a | 3518 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3519 | if (encoder->pre_enable) |
3520 | encoder->pre_enable(encoder); | |
f67a559d | 3521 | |
5bfe2ac0 | 3522 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3523 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3524 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3525 | * enabling. */ | |
88cefb6c | 3526 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3527 | } else { |
3528 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3529 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3530 | } | |
f67a559d | 3531 | |
b074cec8 | 3532 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3533 | |
9c54c0dd JB |
3534 | /* |
3535 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3536 | * clocks enabled | |
3537 | */ | |
3538 | intel_crtc_load_lut(crtc); | |
3539 | ||
f37fcc2a | 3540 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3541 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3542 | intel_crtc->config.has_pch_encoder, false); |
d1de00ef | 3543 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3544 | intel_enable_planes(crtc); |
5c38d48c | 3545 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3546 | |
5bfe2ac0 | 3547 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3548 | ironlake_pch_enable(crtc); |
c98e9dcf | 3549 | |
d1ebd816 | 3550 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3551 | intel_update_fbc(dev); |
d1ebd816 BW |
3552 | mutex_unlock(&dev->struct_mutex); |
3553 | ||
fa5c73b1 DV |
3554 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3555 | encoder->enable(encoder); | |
61b77ddd DV |
3556 | |
3557 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3558 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3559 | |
3560 | /* | |
3561 | * There seems to be a race in PCH platform hw (at least on some | |
3562 | * outputs) where an enabled pipe still completes any pageflip right | |
3563 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3564 | * as the first vblank happend, everything works as expected. Hence just | |
3565 | * wait for one vblank before returning to avoid strange things | |
3566 | * happening. | |
3567 | */ | |
3568 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3569 | } |
3570 | ||
42db64ef PZ |
3571 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3572 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3573 | { | |
f5adf94e | 3574 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3575 | } |
3576 | ||
dda9a66a VS |
3577 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3578 | { | |
3579 | struct drm_device *dev = crtc->dev; | |
3580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3582 | int pipe = intel_crtc->pipe; | |
3583 | int plane = intel_crtc->plane; | |
3584 | ||
d1de00ef | 3585 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3586 | intel_enable_planes(crtc); |
3587 | intel_crtc_update_cursor(crtc, true); | |
3588 | ||
3589 | hsw_enable_ips(intel_crtc); | |
3590 | ||
3591 | mutex_lock(&dev->struct_mutex); | |
3592 | intel_update_fbc(dev); | |
3593 | mutex_unlock(&dev->struct_mutex); | |
3594 | } | |
3595 | ||
3596 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3597 | { | |
3598 | struct drm_device *dev = crtc->dev; | |
3599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3601 | int pipe = intel_crtc->pipe; | |
3602 | int plane = intel_crtc->plane; | |
3603 | ||
3604 | intel_crtc_wait_for_pending_flips(crtc); | |
3605 | drm_vblank_off(dev, pipe); | |
3606 | ||
3607 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3608 | if (dev_priv->fbc.plane == plane) | |
3609 | intel_disable_fbc(dev); | |
3610 | ||
3611 | hsw_disable_ips(intel_crtc); | |
3612 | ||
3613 | intel_crtc_update_cursor(crtc, false); | |
3614 | intel_disable_planes(crtc); | |
d1de00ef | 3615 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3616 | } |
3617 | ||
e4916946 PZ |
3618 | /* |
3619 | * This implements the workaround described in the "notes" section of the mode | |
3620 | * set sequence documentation. When going from no pipes or single pipe to | |
3621 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3622 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3623 | */ | |
3624 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3625 | { | |
3626 | struct drm_device *dev = crtc->base.dev; | |
3627 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3628 | ||
3629 | /* We want to get the other_active_crtc only if there's only 1 other | |
3630 | * active crtc. */ | |
3631 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3632 | if (!crtc_it->active || crtc_it == crtc) | |
3633 | continue; | |
3634 | ||
3635 | if (other_active_crtc) | |
3636 | return; | |
3637 | ||
3638 | other_active_crtc = crtc_it; | |
3639 | } | |
3640 | if (!other_active_crtc) | |
3641 | return; | |
3642 | ||
3643 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3644 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3645 | } | |
3646 | ||
4f771f10 PZ |
3647 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3648 | { | |
3649 | struct drm_device *dev = crtc->dev; | |
3650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3652 | struct intel_encoder *encoder; | |
3653 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3654 | |
3655 | WARN_ON(!crtc->enabled); | |
3656 | ||
3657 | if (intel_crtc->active) | |
3658 | return; | |
3659 | ||
3660 | intel_crtc->active = true; | |
8664281b PZ |
3661 | |
3662 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3663 | if (intel_crtc->config.has_pch_encoder) | |
3664 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3665 | ||
5bfe2ac0 | 3666 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3667 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3668 | |
3669 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3670 | if (encoder->pre_enable) | |
3671 | encoder->pre_enable(encoder); | |
3672 | ||
1f544388 | 3673 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3674 | |
b074cec8 | 3675 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3676 | |
3677 | /* | |
3678 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3679 | * clocks enabled | |
3680 | */ | |
3681 | intel_crtc_load_lut(crtc); | |
3682 | ||
1f544388 | 3683 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3684 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3685 | |
f37fcc2a | 3686 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3687 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3688 | intel_crtc->config.has_pch_encoder, false); |
42db64ef | 3689 | |
5bfe2ac0 | 3690 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3691 | lpt_pch_enable(crtc); |
4f771f10 | 3692 | |
8807e55b | 3693 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3694 | encoder->enable(encoder); |
8807e55b JN |
3695 | intel_opregion_notify_encoder(encoder, true); |
3696 | } | |
4f771f10 | 3697 | |
e4916946 PZ |
3698 | /* If we change the relative order between pipe/planes enabling, we need |
3699 | * to change the workaround. */ | |
3700 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a VS |
3701 | haswell_crtc_enable_planes(crtc); |
3702 | ||
4f771f10 PZ |
3703 | /* |
3704 | * There seems to be a race in PCH platform hw (at least on some | |
3705 | * outputs) where an enabled pipe still completes any pageflip right | |
3706 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3707 | * as the first vblank happend, everything works as expected. Hence just | |
3708 | * wait for one vblank before returning to avoid strange things | |
3709 | * happening. | |
3710 | */ | |
3711 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3712 | } | |
3713 | ||
3f8dce3a DV |
3714 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3715 | { | |
3716 | struct drm_device *dev = crtc->base.dev; | |
3717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3718 | int pipe = crtc->pipe; | |
3719 | ||
3720 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3721 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3722 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3723 | I915_WRITE(PF_CTL(pipe), 0); |
3724 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3725 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3726 | } | |
3727 | } | |
3728 | ||
6be4a607 JB |
3729 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3730 | { | |
3731 | struct drm_device *dev = crtc->dev; | |
3732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3734 | struct intel_encoder *encoder; |
6be4a607 JB |
3735 | int pipe = intel_crtc->pipe; |
3736 | int plane = intel_crtc->plane; | |
5eddb70b | 3737 | u32 reg, temp; |
b52eb4dc | 3738 | |
ef9c3aee | 3739 | |
f7abfe8b CW |
3740 | if (!intel_crtc->active) |
3741 | return; | |
3742 | ||
ea9d758d DV |
3743 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3744 | encoder->disable(encoder); | |
3745 | ||
e6c3a2a6 | 3746 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3747 | drm_vblank_off(dev, pipe); |
913d8d11 | 3748 | |
5c3fe8b0 | 3749 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3750 | intel_disable_fbc(dev); |
2c07245f | 3751 | |
0d5b8c61 | 3752 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3753 | intel_disable_planes(crtc); |
d1de00ef | 3754 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3755 | |
d925c59a DV |
3756 | if (intel_crtc->config.has_pch_encoder) |
3757 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3758 | ||
b24e7179 | 3759 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3760 | |
3f8dce3a | 3761 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3762 | |
bf49ec8c DV |
3763 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3764 | if (encoder->post_disable) | |
3765 | encoder->post_disable(encoder); | |
2c07245f | 3766 | |
d925c59a DV |
3767 | if (intel_crtc->config.has_pch_encoder) { |
3768 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3769 | |
d925c59a DV |
3770 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3771 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3772 | |
d925c59a DV |
3773 | if (HAS_PCH_CPT(dev)) { |
3774 | /* disable TRANS_DP_CTL */ | |
3775 | reg = TRANS_DP_CTL(pipe); | |
3776 | temp = I915_READ(reg); | |
3777 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3778 | TRANS_DP_PORT_SEL_MASK); | |
3779 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3780 | I915_WRITE(reg, temp); | |
3781 | ||
3782 | /* disable DPLL_SEL */ | |
3783 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3784 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3785 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3786 | } |
e3421a18 | 3787 | |
d925c59a | 3788 | /* disable PCH DPLL */ |
e72f9fbf | 3789 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3790 | |
d925c59a DV |
3791 | ironlake_fdi_pll_disable(intel_crtc); |
3792 | } | |
6b383a7f | 3793 | |
f7abfe8b | 3794 | intel_crtc->active = false; |
46ba614c | 3795 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3796 | |
3797 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3798 | intel_update_fbc(dev); |
d1ebd816 | 3799 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3800 | } |
1b3c7a47 | 3801 | |
4f771f10 | 3802 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3803 | { |
4f771f10 PZ |
3804 | struct drm_device *dev = crtc->dev; |
3805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3807 | struct intel_encoder *encoder; |
3808 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3809 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3810 | |
4f771f10 PZ |
3811 | if (!intel_crtc->active) |
3812 | return; | |
3813 | ||
dda9a66a VS |
3814 | haswell_crtc_disable_planes(crtc); |
3815 | ||
8807e55b JN |
3816 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3817 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3818 | encoder->disable(encoder); |
8807e55b | 3819 | } |
4f771f10 | 3820 | |
8664281b PZ |
3821 | if (intel_crtc->config.has_pch_encoder) |
3822 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3823 | intel_disable_pipe(dev_priv, pipe); |
3824 | ||
ad80a810 | 3825 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3826 | |
3f8dce3a | 3827 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3828 | |
1f544388 | 3829 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3830 | |
3831 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3832 | if (encoder->post_disable) | |
3833 | encoder->post_disable(encoder); | |
3834 | ||
88adfff1 | 3835 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3836 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3837 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3838 | intel_ddi_fdi_disable(crtc); |
83616634 | 3839 | } |
4f771f10 PZ |
3840 | |
3841 | intel_crtc->active = false; | |
46ba614c | 3842 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3843 | |
3844 | mutex_lock(&dev->struct_mutex); | |
3845 | intel_update_fbc(dev); | |
3846 | mutex_unlock(&dev->struct_mutex); | |
3847 | } | |
3848 | ||
ee7b9f93 JB |
3849 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3850 | { | |
3851 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3852 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3853 | } |
3854 | ||
6441ab5f PZ |
3855 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3856 | { | |
3857 | intel_ddi_put_crtc_pll(crtc); | |
3858 | } | |
3859 | ||
02e792fb DV |
3860 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3861 | { | |
02e792fb | 3862 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3863 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3864 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3865 | |
23f09ce3 | 3866 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3867 | dev_priv->mm.interruptible = false; |
3868 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3869 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3870 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3871 | } |
02e792fb | 3872 | |
5dcdbcb0 CW |
3873 | /* Let userspace switch the overlay on again. In most cases userspace |
3874 | * has to recompute where to put it anyway. | |
3875 | */ | |
02e792fb DV |
3876 | } |
3877 | ||
61bc95c1 EE |
3878 | /** |
3879 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3880 | * cursor plane briefly if not already running after enabling the display | |
3881 | * plane. | |
3882 | * This workaround avoids occasional blank screens when self refresh is | |
3883 | * enabled. | |
3884 | */ | |
3885 | static void | |
3886 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3887 | { | |
3888 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3889 | ||
3890 | if ((cntl & CURSOR_MODE) == 0) { | |
3891 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3892 | ||
3893 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3894 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3895 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3896 | I915_WRITE(CURCNTR(pipe), cntl); | |
3897 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3898 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3899 | } | |
3900 | } | |
3901 | ||
2dd24552 JB |
3902 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3903 | { | |
3904 | struct drm_device *dev = crtc->base.dev; | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3906 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3907 | ||
328d8e82 | 3908 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3909 | return; |
3910 | ||
2dd24552 | 3911 | /* |
c0b03411 DV |
3912 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3913 | * according to register description and PRM. | |
2dd24552 | 3914 | */ |
c0b03411 DV |
3915 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3916 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3917 | |
b074cec8 JB |
3918 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3919 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3920 | |
3921 | /* Border color in case we don't scale up to the full screen. Black by | |
3922 | * default, change to something else for debugging. */ | |
3923 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3924 | } |
3925 | ||
586f49dc | 3926 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 3927 | { |
586f49dc | 3928 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 3929 | |
586f49dc JB |
3930 | /* Obtain SKU information */ |
3931 | mutex_lock(&dev_priv->dpio_lock); | |
3932 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
3933 | CCK_FUSE_HPLL_FREQ_MASK; | |
3934 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 3935 | |
586f49dc | 3936 | return vco_freq[hpll_freq]; |
30a970c6 JB |
3937 | } |
3938 | ||
3939 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
3940 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
3941 | { | |
3942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3943 | u32 val, cmd; | |
3944 | ||
3945 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
3946 | cmd = 2; | |
3947 | else if (cdclk == 266) | |
3948 | cmd = 1; | |
3949 | else | |
3950 | cmd = 0; | |
3951 | ||
3952 | mutex_lock(&dev_priv->rps.hw_lock); | |
3953 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
3954 | val &= ~DSPFREQGUAR_MASK; | |
3955 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
3956 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
3957 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
3958 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
3959 | 50)) { | |
3960 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
3961 | } | |
3962 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3963 | ||
3964 | if (cdclk == 400) { | |
3965 | u32 divider, vco; | |
3966 | ||
3967 | vco = valleyview_get_vco(dev_priv); | |
3968 | divider = ((vco << 1) / cdclk) - 1; | |
3969 | ||
3970 | mutex_lock(&dev_priv->dpio_lock); | |
3971 | /* adjust cdclk divider */ | |
3972 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
3973 | val &= ~0xf; | |
3974 | val |= divider; | |
3975 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
3976 | mutex_unlock(&dev_priv->dpio_lock); | |
3977 | } | |
3978 | ||
3979 | mutex_lock(&dev_priv->dpio_lock); | |
3980 | /* adjust self-refresh exit latency value */ | |
3981 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
3982 | val &= ~0x7f; | |
3983 | ||
3984 | /* | |
3985 | * For high bandwidth configs, we set a higher latency in the bunit | |
3986 | * so that the core display fetch happens in time to avoid underruns. | |
3987 | */ | |
3988 | if (cdclk == 400) | |
3989 | val |= 4500 / 250; /* 4.5 usec */ | |
3990 | else | |
3991 | val |= 3000 / 250; /* 3.0 usec */ | |
3992 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
3993 | mutex_unlock(&dev_priv->dpio_lock); | |
3994 | ||
3995 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
3996 | intel_i2c_reset(dev); | |
3997 | } | |
3998 | ||
3999 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4000 | { | |
4001 | int cur_cdclk, vco; | |
4002 | int divider; | |
4003 | ||
4004 | vco = valleyview_get_vco(dev_priv); | |
4005 | ||
4006 | mutex_lock(&dev_priv->dpio_lock); | |
4007 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4008 | mutex_unlock(&dev_priv->dpio_lock); | |
4009 | ||
4010 | divider &= 0xf; | |
4011 | ||
4012 | cur_cdclk = (vco << 1) / (divider + 1); | |
4013 | ||
4014 | return cur_cdclk; | |
4015 | } | |
4016 | ||
4017 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4018 | int max_pixclk) | |
4019 | { | |
4020 | int cur_cdclk; | |
4021 | ||
4022 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4023 | ||
4024 | /* | |
4025 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4026 | * 200MHz | |
4027 | * 267MHz | |
4028 | * 320MHz | |
4029 | * 400MHz | |
4030 | * So we check to see whether we're above 90% of the lower bin and | |
4031 | * adjust if needed. | |
4032 | */ | |
4033 | if (max_pixclk > 288000) { | |
4034 | return 400; | |
4035 | } else if (max_pixclk > 240000) { | |
4036 | return 320; | |
4037 | } else | |
4038 | return 266; | |
4039 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4040 | } | |
4041 | ||
4042 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, | |
4043 | unsigned modeset_pipes, | |
4044 | struct intel_crtc_config *pipe_config) | |
4045 | { | |
4046 | struct drm_device *dev = dev_priv->dev; | |
4047 | struct intel_crtc *intel_crtc; | |
4048 | int max_pixclk = 0; | |
4049 | ||
4050 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4051 | base.head) { | |
4052 | if (modeset_pipes & (1 << intel_crtc->pipe)) | |
4053 | max_pixclk = max(max_pixclk, | |
4054 | pipe_config->adjusted_mode.crtc_clock); | |
4055 | else if (intel_crtc->base.enabled) | |
4056 | max_pixclk = max(max_pixclk, | |
4057 | intel_crtc->config.adjusted_mode.crtc_clock); | |
4058 | } | |
4059 | ||
4060 | return max_pixclk; | |
4061 | } | |
4062 | ||
4063 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
4064 | unsigned *prepare_pipes, | |
4065 | unsigned modeset_pipes, | |
4066 | struct intel_crtc_config *pipe_config) | |
4067 | { | |
4068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4069 | struct intel_crtc *intel_crtc; | |
4070 | int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes, | |
4071 | pipe_config); | |
4072 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4073 | ||
4074 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4075 | return; | |
4076 | ||
4077 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4078 | base.head) | |
4079 | if (intel_crtc->base.enabled) | |
4080 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4081 | } | |
4082 | ||
4083 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4084 | { | |
4085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4086 | int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL); | |
4087 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4088 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4089 | ||
4090 | if (req_cdclk != cur_cdclk) | |
4091 | valleyview_set_cdclk(dev, req_cdclk); | |
4092 | } | |
4093 | ||
89b667f8 JB |
4094 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4095 | { | |
4096 | struct drm_device *dev = crtc->dev; | |
4097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4099 | struct intel_encoder *encoder; | |
4100 | int pipe = intel_crtc->pipe; | |
4101 | int plane = intel_crtc->plane; | |
23538ef1 | 4102 | bool is_dsi; |
89b667f8 JB |
4103 | |
4104 | WARN_ON(!crtc->enabled); | |
4105 | ||
4106 | if (intel_crtc->active) | |
4107 | return; | |
4108 | ||
4109 | intel_crtc->active = true; | |
89b667f8 | 4110 | |
89b667f8 JB |
4111 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4112 | if (encoder->pre_pll_enable) | |
4113 | encoder->pre_pll_enable(encoder); | |
4114 | ||
23538ef1 JN |
4115 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4116 | ||
e9fd1c02 JN |
4117 | if (!is_dsi) |
4118 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4119 | |
4120 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4121 | if (encoder->pre_enable) | |
4122 | encoder->pre_enable(encoder); | |
4123 | ||
2dd24552 JB |
4124 | i9xx_pfit_enable(intel_crtc); |
4125 | ||
63cbb074 VS |
4126 | intel_crtc_load_lut(crtc); |
4127 | ||
f37fcc2a | 4128 | intel_update_watermarks(crtc); |
23538ef1 | 4129 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
d1de00ef | 4130 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4131 | intel_enable_planes(crtc); |
5c38d48c | 4132 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4133 | |
89b667f8 | 4134 | intel_update_fbc(dev); |
5004945f JN |
4135 | |
4136 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4137 | encoder->enable(encoder); | |
89b667f8 JB |
4138 | } |
4139 | ||
0b8765c6 | 4140 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4141 | { |
4142 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4143 | struct drm_i915_private *dev_priv = dev->dev_private; |
4144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4145 | struct intel_encoder *encoder; |
79e53945 | 4146 | int pipe = intel_crtc->pipe; |
80824003 | 4147 | int plane = intel_crtc->plane; |
79e53945 | 4148 | |
08a48469 DV |
4149 | WARN_ON(!crtc->enabled); |
4150 | ||
f7abfe8b CW |
4151 | if (intel_crtc->active) |
4152 | return; | |
4153 | ||
4154 | intel_crtc->active = true; | |
6b383a7f | 4155 | |
9d6d9f19 MK |
4156 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4157 | if (encoder->pre_enable) | |
4158 | encoder->pre_enable(encoder); | |
4159 | ||
f6736a1a DV |
4160 | i9xx_enable_pll(intel_crtc); |
4161 | ||
2dd24552 JB |
4162 | i9xx_pfit_enable(intel_crtc); |
4163 | ||
63cbb074 VS |
4164 | intel_crtc_load_lut(crtc); |
4165 | ||
f37fcc2a | 4166 | intel_update_watermarks(crtc); |
23538ef1 | 4167 | intel_enable_pipe(dev_priv, pipe, false, false); |
d1de00ef | 4168 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4169 | intel_enable_planes(crtc); |
22e407d7 | 4170 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4171 | if (IS_G4X(dev)) |
4172 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4173 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4174 | |
0b8765c6 JB |
4175 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4176 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4177 | |
f440eb13 | 4178 | intel_update_fbc(dev); |
ef9c3aee | 4179 | |
fa5c73b1 DV |
4180 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4181 | encoder->enable(encoder); | |
0b8765c6 | 4182 | } |
79e53945 | 4183 | |
87476d63 DV |
4184 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4185 | { | |
4186 | struct drm_device *dev = crtc->base.dev; | |
4187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4188 | |
328d8e82 DV |
4189 | if (!crtc->config.gmch_pfit.control) |
4190 | return; | |
87476d63 | 4191 | |
328d8e82 | 4192 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4193 | |
328d8e82 DV |
4194 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4195 | I915_READ(PFIT_CONTROL)); | |
4196 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4197 | } |
4198 | ||
0b8765c6 JB |
4199 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4200 | { | |
4201 | struct drm_device *dev = crtc->dev; | |
4202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4204 | struct intel_encoder *encoder; |
0b8765c6 JB |
4205 | int pipe = intel_crtc->pipe; |
4206 | int plane = intel_crtc->plane; | |
ef9c3aee | 4207 | |
f7abfe8b CW |
4208 | if (!intel_crtc->active) |
4209 | return; | |
4210 | ||
ea9d758d DV |
4211 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4212 | encoder->disable(encoder); | |
4213 | ||
0b8765c6 | 4214 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4215 | intel_crtc_wait_for_pending_flips(crtc); |
4216 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4217 | |
5c3fe8b0 | 4218 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4219 | intel_disable_fbc(dev); |
79e53945 | 4220 | |
0d5b8c61 VS |
4221 | intel_crtc_dpms_overlay(intel_crtc, false); |
4222 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4223 | intel_disable_planes(crtc); |
d1de00ef | 4224 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4225 | |
b24e7179 | 4226 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4227 | |
87476d63 | 4228 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4229 | |
89b667f8 JB |
4230 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4231 | if (encoder->post_disable) | |
4232 | encoder->post_disable(encoder); | |
4233 | ||
f6071166 JB |
4234 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4235 | vlv_disable_pll(dev_priv, pipe); | |
4236 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4237 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4238 | |
f7abfe8b | 4239 | intel_crtc->active = false; |
46ba614c | 4240 | intel_update_watermarks(crtc); |
f37fcc2a | 4241 | |
6b383a7f | 4242 | intel_update_fbc(dev); |
0b8765c6 JB |
4243 | } |
4244 | ||
ee7b9f93 JB |
4245 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4246 | { | |
4247 | } | |
4248 | ||
976f8a20 DV |
4249 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4250 | bool enabled) | |
2c07245f ZW |
4251 | { |
4252 | struct drm_device *dev = crtc->dev; | |
4253 | struct drm_i915_master_private *master_priv; | |
4254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4255 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4256 | |
4257 | if (!dev->primary->master) | |
4258 | return; | |
4259 | ||
4260 | master_priv = dev->primary->master->driver_priv; | |
4261 | if (!master_priv->sarea_priv) | |
4262 | return; | |
4263 | ||
79e53945 JB |
4264 | switch (pipe) { |
4265 | case 0: | |
4266 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4267 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4268 | break; | |
4269 | case 1: | |
4270 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4271 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4272 | break; | |
4273 | default: | |
9db4a9c7 | 4274 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4275 | break; |
4276 | } | |
79e53945 JB |
4277 | } |
4278 | ||
976f8a20 DV |
4279 | /** |
4280 | * Sets the power management mode of the pipe and plane. | |
4281 | */ | |
4282 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4283 | { | |
4284 | struct drm_device *dev = crtc->dev; | |
4285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4286 | struct intel_encoder *intel_encoder; | |
4287 | bool enable = false; | |
4288 | ||
4289 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4290 | enable |= intel_encoder->connectors_active; | |
4291 | ||
4292 | if (enable) | |
4293 | dev_priv->display.crtc_enable(crtc); | |
4294 | else | |
4295 | dev_priv->display.crtc_disable(crtc); | |
4296 | ||
4297 | intel_crtc_update_sarea(crtc, enable); | |
4298 | } | |
4299 | ||
cdd59983 CW |
4300 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4301 | { | |
cdd59983 | 4302 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4303 | struct drm_connector *connector; |
ee7b9f93 | 4304 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4306 | |
976f8a20 DV |
4307 | /* crtc should still be enabled when we disable it. */ |
4308 | WARN_ON(!crtc->enabled); | |
4309 | ||
4310 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4311 | intel_crtc->eld_vld = false; |
976f8a20 | 4312 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4313 | dev_priv->display.off(crtc); |
4314 | ||
931872fc | 4315 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4316 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4317 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4318 | |
4319 | if (crtc->fb) { | |
4320 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4321 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4322 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4323 | crtc->fb = NULL; |
4324 | } | |
4325 | ||
4326 | /* Update computed state. */ | |
4327 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4328 | if (!connector->encoder || !connector->encoder->crtc) | |
4329 | continue; | |
4330 | ||
4331 | if (connector->encoder->crtc != crtc) | |
4332 | continue; | |
4333 | ||
4334 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4335 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4336 | } |
4337 | } | |
4338 | ||
ea5b213a | 4339 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4340 | { |
4ef69c7a | 4341 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4342 | |
ea5b213a CW |
4343 | drm_encoder_cleanup(encoder); |
4344 | kfree(intel_encoder); | |
7e7d76c3 JB |
4345 | } |
4346 | ||
9237329d | 4347 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4348 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4349 | * state of the entire output pipe. */ | |
9237329d | 4350 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4351 | { |
5ab432ef DV |
4352 | if (mode == DRM_MODE_DPMS_ON) { |
4353 | encoder->connectors_active = true; | |
4354 | ||
b2cabb0e | 4355 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4356 | } else { |
4357 | encoder->connectors_active = false; | |
4358 | ||
b2cabb0e | 4359 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4360 | } |
79e53945 JB |
4361 | } |
4362 | ||
0a91ca29 DV |
4363 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4364 | * internal consistency). */ | |
b980514c | 4365 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4366 | { |
0a91ca29 DV |
4367 | if (connector->get_hw_state(connector)) { |
4368 | struct intel_encoder *encoder = connector->encoder; | |
4369 | struct drm_crtc *crtc; | |
4370 | bool encoder_enabled; | |
4371 | enum pipe pipe; | |
4372 | ||
4373 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4374 | connector->base.base.id, | |
4375 | drm_get_connector_name(&connector->base)); | |
4376 | ||
4377 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4378 | "wrong connector dpms state\n"); | |
4379 | WARN(connector->base.encoder != &encoder->base, | |
4380 | "active connector not linked to encoder\n"); | |
4381 | WARN(!encoder->connectors_active, | |
4382 | "encoder->connectors_active not set\n"); | |
4383 | ||
4384 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4385 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4386 | if (WARN_ON(!encoder->base.crtc)) | |
4387 | return; | |
4388 | ||
4389 | crtc = encoder->base.crtc; | |
4390 | ||
4391 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4392 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4393 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4394 | "encoder active on the wrong pipe\n"); | |
4395 | } | |
79e53945 JB |
4396 | } |
4397 | ||
5ab432ef DV |
4398 | /* Even simpler default implementation, if there's really no special case to |
4399 | * consider. */ | |
4400 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4401 | { |
5ab432ef DV |
4402 | /* All the simple cases only support two dpms states. */ |
4403 | if (mode != DRM_MODE_DPMS_ON) | |
4404 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4405 | |
5ab432ef DV |
4406 | if (mode == connector->dpms) |
4407 | return; | |
4408 | ||
4409 | connector->dpms = mode; | |
4410 | ||
4411 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4412 | if (connector->encoder) |
4413 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4414 | |
b980514c | 4415 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4416 | } |
4417 | ||
f0947c37 DV |
4418 | /* Simple connector->get_hw_state implementation for encoders that support only |
4419 | * one connector and no cloning and hence the encoder state determines the state | |
4420 | * of the connector. */ | |
4421 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4422 | { |
24929352 | 4423 | enum pipe pipe = 0; |
f0947c37 | 4424 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4425 | |
f0947c37 | 4426 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4427 | } |
4428 | ||
1857e1da DV |
4429 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4430 | struct intel_crtc_config *pipe_config) | |
4431 | { | |
4432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4433 | struct intel_crtc *pipe_B_crtc = | |
4434 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4435 | ||
4436 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4437 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4438 | if (pipe_config->fdi_lanes > 4) { | |
4439 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4440 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4441 | return false; | |
4442 | } | |
4443 | ||
bafb6553 | 4444 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4445 | if (pipe_config->fdi_lanes > 2) { |
4446 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4447 | pipe_config->fdi_lanes); | |
4448 | return false; | |
4449 | } else { | |
4450 | return true; | |
4451 | } | |
4452 | } | |
4453 | ||
4454 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4455 | return true; | |
4456 | ||
4457 | /* Ivybridge 3 pipe is really complicated */ | |
4458 | switch (pipe) { | |
4459 | case PIPE_A: | |
4460 | return true; | |
4461 | case PIPE_B: | |
4462 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4463 | pipe_config->fdi_lanes > 2) { | |
4464 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4465 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4466 | return false; | |
4467 | } | |
4468 | return true; | |
4469 | case PIPE_C: | |
1e833f40 | 4470 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4471 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4472 | if (pipe_config->fdi_lanes > 2) { | |
4473 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4474 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4475 | return false; | |
4476 | } | |
4477 | } else { | |
4478 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4479 | return false; | |
4480 | } | |
4481 | return true; | |
4482 | default: | |
4483 | BUG(); | |
4484 | } | |
4485 | } | |
4486 | ||
e29c22c0 DV |
4487 | #define RETRY 1 |
4488 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4489 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4490 | { |
1857e1da | 4491 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4492 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4493 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4494 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4495 | |
e29c22c0 | 4496 | retry: |
877d48d5 DV |
4497 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4498 | * each output octet as 10 bits. The actual frequency | |
4499 | * is stored as a divider into a 100MHz clock, and the | |
4500 | * mode pixel clock is stored in units of 1KHz. | |
4501 | * Hence the bw of each lane in terms of the mode signal | |
4502 | * is: | |
4503 | */ | |
4504 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4505 | ||
241bfc38 | 4506 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4507 | |
2bd89a07 | 4508 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4509 | pipe_config->pipe_bpp); |
4510 | ||
4511 | pipe_config->fdi_lanes = lane; | |
4512 | ||
2bd89a07 | 4513 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4514 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4515 | |
e29c22c0 DV |
4516 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4517 | intel_crtc->pipe, pipe_config); | |
4518 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4519 | pipe_config->pipe_bpp -= 2*3; | |
4520 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4521 | pipe_config->pipe_bpp); | |
4522 | needs_recompute = true; | |
4523 | pipe_config->bw_constrained = true; | |
4524 | ||
4525 | goto retry; | |
4526 | } | |
4527 | ||
4528 | if (needs_recompute) | |
4529 | return RETRY; | |
4530 | ||
4531 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4532 | } |
4533 | ||
42db64ef PZ |
4534 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4535 | struct intel_crtc_config *pipe_config) | |
4536 | { | |
3c4ca58c PZ |
4537 | pipe_config->ips_enabled = i915_enable_ips && |
4538 | hsw_crtc_supports_ips(crtc) && | |
b6dfdc9b | 4539 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4540 | } |
4541 | ||
a43f6e0f | 4542 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4543 | struct intel_crtc_config *pipe_config) |
79e53945 | 4544 | { |
a43f6e0f | 4545 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4546 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4547 | |
ad3a4479 | 4548 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4549 | if (INTEL_INFO(dev)->gen < 4) { |
4550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4551 | int clock_limit = | |
4552 | dev_priv->display.get_display_clock_speed(dev); | |
4553 | ||
4554 | /* | |
4555 | * Enable pixel doubling when the dot clock | |
4556 | * is > 90% of the (display) core speed. | |
4557 | * | |
b397c96b VS |
4558 | * GDG double wide on either pipe, |
4559 | * otherwise pipe A only. | |
cf532bb2 | 4560 | */ |
b397c96b | 4561 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4562 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4563 | clock_limit *= 2; |
cf532bb2 | 4564 | pipe_config->double_wide = true; |
ad3a4479 VS |
4565 | } |
4566 | ||
241bfc38 | 4567 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4568 | return -EINVAL; |
2c07245f | 4569 | } |
89749350 | 4570 | |
1d1d0e27 VS |
4571 | /* |
4572 | * Pipe horizontal size must be even in: | |
4573 | * - DVO ganged mode | |
4574 | * - LVDS dual channel mode | |
4575 | * - Double wide pipe | |
4576 | */ | |
4577 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4578 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4579 | pipe_config->pipe_src_w &= ~1; | |
4580 | ||
8693a824 DL |
4581 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4582 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4583 | */ |
4584 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4585 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4586 | return -EINVAL; |
44f46b42 | 4587 | |
bd080ee5 | 4588 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4589 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4590 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4591 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4592 | * for lvds. */ | |
4593 | pipe_config->pipe_bpp = 8*3; | |
4594 | } | |
4595 | ||
f5adf94e | 4596 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4597 | hsw_compute_ips_config(crtc, pipe_config); |
4598 | ||
4599 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4600 | * clock survives for now. */ | |
4601 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4602 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4603 | |
877d48d5 | 4604 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4605 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4606 | |
e29c22c0 | 4607 | return 0; |
79e53945 JB |
4608 | } |
4609 | ||
25eb05fc JB |
4610 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4611 | { | |
4612 | return 400000; /* FIXME */ | |
4613 | } | |
4614 | ||
e70236a8 JB |
4615 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4616 | { | |
4617 | return 400000; | |
4618 | } | |
79e53945 | 4619 | |
e70236a8 | 4620 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4621 | { |
e70236a8 JB |
4622 | return 333000; |
4623 | } | |
79e53945 | 4624 | |
e70236a8 JB |
4625 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4626 | { | |
4627 | return 200000; | |
4628 | } | |
79e53945 | 4629 | |
257a7ffc DV |
4630 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4631 | { | |
4632 | u16 gcfgc = 0; | |
4633 | ||
4634 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4635 | ||
4636 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4637 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4638 | return 267000; | |
4639 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4640 | return 333000; | |
4641 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4642 | return 444000; | |
4643 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4644 | return 200000; | |
4645 | default: | |
4646 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4647 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4648 | return 133000; | |
4649 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4650 | return 167000; | |
4651 | } | |
4652 | } | |
4653 | ||
e70236a8 JB |
4654 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4655 | { | |
4656 | u16 gcfgc = 0; | |
79e53945 | 4657 | |
e70236a8 JB |
4658 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4659 | ||
4660 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4661 | return 133000; | |
4662 | else { | |
4663 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4664 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4665 | return 333000; | |
4666 | default: | |
4667 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4668 | return 190000; | |
79e53945 | 4669 | } |
e70236a8 JB |
4670 | } |
4671 | } | |
4672 | ||
4673 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4674 | { | |
4675 | return 266000; | |
4676 | } | |
4677 | ||
4678 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4679 | { | |
4680 | u16 hpllcc = 0; | |
4681 | /* Assume that the hardware is in the high speed state. This | |
4682 | * should be the default. | |
4683 | */ | |
4684 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4685 | case GC_CLOCK_133_200: | |
4686 | case GC_CLOCK_100_200: | |
4687 | return 200000; | |
4688 | case GC_CLOCK_166_250: | |
4689 | return 250000; | |
4690 | case GC_CLOCK_100_133: | |
79e53945 | 4691 | return 133000; |
e70236a8 | 4692 | } |
79e53945 | 4693 | |
e70236a8 JB |
4694 | /* Shouldn't happen */ |
4695 | return 0; | |
4696 | } | |
79e53945 | 4697 | |
e70236a8 JB |
4698 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4699 | { | |
4700 | return 133000; | |
79e53945 JB |
4701 | } |
4702 | ||
2c07245f | 4703 | static void |
a65851af | 4704 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4705 | { |
a65851af VS |
4706 | while (*num > DATA_LINK_M_N_MASK || |
4707 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4708 | *num >>= 1; |
4709 | *den >>= 1; | |
4710 | } | |
4711 | } | |
4712 | ||
a65851af VS |
4713 | static void compute_m_n(unsigned int m, unsigned int n, |
4714 | uint32_t *ret_m, uint32_t *ret_n) | |
4715 | { | |
4716 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4717 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4718 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4719 | } | |
4720 | ||
e69d0bc1 DV |
4721 | void |
4722 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4723 | int pixel_clock, int link_clock, | |
4724 | struct intel_link_m_n *m_n) | |
2c07245f | 4725 | { |
e69d0bc1 | 4726 | m_n->tu = 64; |
a65851af VS |
4727 | |
4728 | compute_m_n(bits_per_pixel * pixel_clock, | |
4729 | link_clock * nlanes * 8, | |
4730 | &m_n->gmch_m, &m_n->gmch_n); | |
4731 | ||
4732 | compute_m_n(pixel_clock, link_clock, | |
4733 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4734 | } |
4735 | ||
a7615030 CW |
4736 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4737 | { | |
72bbe58c KP |
4738 | if (i915_panel_use_ssc >= 0) |
4739 | return i915_panel_use_ssc != 0; | |
41aa3448 | 4740 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4741 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4742 | } |
4743 | ||
c65d77d8 JB |
4744 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4745 | { | |
4746 | struct drm_device *dev = crtc->dev; | |
4747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4748 | int refclk; | |
4749 | ||
a0c4da24 | 4750 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4751 | refclk = 100000; |
a0c4da24 | 4752 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4753 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
41aa3448 | 4754 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
c65d77d8 JB |
4755 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4756 | refclk / 1000); | |
4757 | } else if (!IS_GEN2(dev)) { | |
4758 | refclk = 96000; | |
4759 | } else { | |
4760 | refclk = 48000; | |
4761 | } | |
4762 | ||
4763 | return refclk; | |
4764 | } | |
4765 | ||
7429e9d4 | 4766 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4767 | { |
7df00d7a | 4768 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4769 | } |
f47709a9 | 4770 | |
7429e9d4 DV |
4771 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4772 | { | |
4773 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4774 | } |
4775 | ||
f47709a9 | 4776 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4777 | intel_clock_t *reduced_clock) |
4778 | { | |
f47709a9 | 4779 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4780 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4781 | int pipe = crtc->pipe; |
a7516a05 JB |
4782 | u32 fp, fp2 = 0; |
4783 | ||
4784 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4785 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4786 | if (reduced_clock) |
7429e9d4 | 4787 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4788 | } else { |
7429e9d4 | 4789 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4790 | if (reduced_clock) |
7429e9d4 | 4791 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4792 | } |
4793 | ||
4794 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4795 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4796 | |
f47709a9 DV |
4797 | crtc->lowfreq_avail = false; |
4798 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4799 | reduced_clock && i915_powersave) { |
4800 | I915_WRITE(FP1(pipe), fp2); | |
8bcc2795 | 4801 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4802 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4803 | } else { |
4804 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4805 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4806 | } |
4807 | } | |
4808 | ||
5e69f97f CML |
4809 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4810 | pipe) | |
89b667f8 JB |
4811 | { |
4812 | u32 reg_val; | |
4813 | ||
4814 | /* | |
4815 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4816 | * and set it to a reasonable value instead. | |
4817 | */ | |
ab3c759a | 4818 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4819 | reg_val &= 0xffffff00; |
4820 | reg_val |= 0x00000030; | |
ab3c759a | 4821 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4822 | |
ab3c759a | 4823 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4824 | reg_val &= 0x8cffffff; |
4825 | reg_val = 0x8c000000; | |
ab3c759a | 4826 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4827 | |
ab3c759a | 4828 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4829 | reg_val &= 0xffffff00; |
ab3c759a | 4830 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4831 | |
ab3c759a | 4832 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4833 | reg_val &= 0x00ffffff; |
4834 | reg_val |= 0xb0000000; | |
ab3c759a | 4835 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4836 | } |
4837 | ||
b551842d DV |
4838 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4839 | struct intel_link_m_n *m_n) | |
4840 | { | |
4841 | struct drm_device *dev = crtc->base.dev; | |
4842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4843 | int pipe = crtc->pipe; | |
4844 | ||
e3b95f1e DV |
4845 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4846 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4847 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4848 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4849 | } |
4850 | ||
4851 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4852 | struct intel_link_m_n *m_n) | |
4853 | { | |
4854 | struct drm_device *dev = crtc->base.dev; | |
4855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4856 | int pipe = crtc->pipe; | |
4857 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4858 | ||
4859 | if (INTEL_INFO(dev)->gen >= 5) { | |
4860 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4861 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4862 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4863 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4864 | } else { | |
e3b95f1e DV |
4865 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4866 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4867 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4868 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4869 | } |
4870 | } | |
4871 | ||
03afc4a2 DV |
4872 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4873 | { | |
4874 | if (crtc->config.has_pch_encoder) | |
4875 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4876 | else | |
4877 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4878 | } | |
4879 | ||
f47709a9 | 4880 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4881 | { |
f47709a9 | 4882 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4883 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4884 | int pipe = crtc->pipe; |
89b667f8 | 4885 | u32 dpll, mdiv; |
a0c4da24 | 4886 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4887 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4888 | |
09153000 DV |
4889 | mutex_lock(&dev_priv->dpio_lock); |
4890 | ||
f47709a9 DV |
4891 | bestn = crtc->config.dpll.n; |
4892 | bestm1 = crtc->config.dpll.m1; | |
4893 | bestm2 = crtc->config.dpll.m2; | |
4894 | bestp1 = crtc->config.dpll.p1; | |
4895 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4896 | |
89b667f8 JB |
4897 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4898 | ||
4899 | /* PLL B needs special handling */ | |
4900 | if (pipe) | |
5e69f97f | 4901 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4902 | |
4903 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 4904 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
4905 | |
4906 | /* Disable target IRef on PLL */ | |
ab3c759a | 4907 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 4908 | reg_val &= 0x00ffffff; |
ab3c759a | 4909 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
4910 | |
4911 | /* Disable fast lock */ | |
ab3c759a | 4912 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
4913 | |
4914 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4915 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4916 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4917 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4918 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4919 | |
4920 | /* | |
4921 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4922 | * but we don't support that). | |
4923 | * Note: don't use the DAC post divider as it seems unstable. | |
4924 | */ | |
4925 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 4926 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4927 | |
a0c4da24 | 4928 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 4929 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4930 | |
89b667f8 | 4931 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4932 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4933 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4934 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 4935 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 4936 | 0x009f0003); |
89b667f8 | 4937 | else |
ab3c759a | 4938 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
4939 | 0x00d0000f); |
4940 | ||
4941 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4942 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4943 | /* Use SSC source */ | |
4944 | if (!pipe) | |
ab3c759a | 4945 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4946 | 0x0df40000); |
4947 | else | |
ab3c759a | 4948 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4949 | 0x0df70000); |
4950 | } else { /* HDMI or VGA */ | |
4951 | /* Use bend source */ | |
4952 | if (!pipe) | |
ab3c759a | 4953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4954 | 0x0df70000); |
4955 | else | |
ab3c759a | 4956 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4957 | 0x0df40000); |
4958 | } | |
a0c4da24 | 4959 | |
ab3c759a | 4960 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
4961 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4962 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4963 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4964 | coreclk |= 0x01000000; | |
ab3c759a | 4965 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 4966 | |
ab3c759a | 4967 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 4968 | |
89b667f8 JB |
4969 | /* Enable DPIO clock input */ |
4970 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4971 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
4972 | /* We should never disable this, set it here for state tracking */ |
4973 | if (pipe == PIPE_B) | |
89b667f8 | 4974 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 4975 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
4976 | crtc->config.dpll_hw_state.dpll = dpll; |
4977 | ||
ef1b460d DV |
4978 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4979 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
4980 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4981 | ||
89b667f8 JB |
4982 | if (crtc->config.has_dp_encoder) |
4983 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4984 | |
4985 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4986 | } |
4987 | ||
f47709a9 DV |
4988 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4989 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4990 | int num_connectors) |
4991 | { | |
f47709a9 | 4992 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4993 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
4994 | u32 dpll; |
4995 | bool is_sdvo; | |
f47709a9 | 4996 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4997 | |
f47709a9 | 4998 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4999 | |
f47709a9 DV |
5000 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5001 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5002 | |
5003 | dpll = DPLL_VGA_MODE_DIS; | |
5004 | ||
f47709a9 | 5005 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5006 | dpll |= DPLLB_MODE_LVDS; |
5007 | else | |
5008 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5009 | |
ef1b460d | 5010 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5011 | dpll |= (crtc->config.pixel_multiplier - 1) |
5012 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5013 | } |
198a037f DV |
5014 | |
5015 | if (is_sdvo) | |
4a33e48d | 5016 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5017 | |
f47709a9 | 5018 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5019 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5020 | |
5021 | /* compute bitmask from p1 value */ | |
5022 | if (IS_PINEVIEW(dev)) | |
5023 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5024 | else { | |
5025 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5026 | if (IS_G4X(dev) && reduced_clock) | |
5027 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5028 | } | |
5029 | switch (clock->p2) { | |
5030 | case 5: | |
5031 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5032 | break; | |
5033 | case 7: | |
5034 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5035 | break; | |
5036 | case 10: | |
5037 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5038 | break; | |
5039 | case 14: | |
5040 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5041 | break; | |
5042 | } | |
5043 | if (INTEL_INFO(dev)->gen >= 4) | |
5044 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5045 | ||
09ede541 | 5046 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5047 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5048 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5049 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5050 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5051 | else | |
5052 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5053 | ||
5054 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5055 | crtc->config.dpll_hw_state.dpll = dpll; |
5056 | ||
eb1cbe48 | 5057 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5058 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5059 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5060 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5061 | } |
66e3d5c0 DV |
5062 | |
5063 | if (crtc->config.has_dp_encoder) | |
5064 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5065 | } |
5066 | ||
f47709a9 | 5067 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5068 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5069 | int num_connectors) |
5070 | { | |
f47709a9 | 5071 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5072 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5073 | u32 dpll; |
f47709a9 | 5074 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5075 | |
f47709a9 | 5076 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5077 | |
eb1cbe48 DV |
5078 | dpll = DPLL_VGA_MODE_DIS; |
5079 | ||
f47709a9 | 5080 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5081 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5082 | } else { | |
5083 | if (clock->p1 == 2) | |
5084 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5085 | else | |
5086 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5087 | if (clock->p2 == 4) | |
5088 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5089 | } | |
5090 | ||
4a33e48d DV |
5091 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5092 | dpll |= DPLL_DVO_2X_MODE; | |
5093 | ||
f47709a9 | 5094 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5095 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5096 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5097 | else | |
5098 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5099 | ||
5100 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5101 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5102 | } |
5103 | ||
8a654f3b | 5104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5105 | { |
5106 | struct drm_device *dev = intel_crtc->base.dev; | |
5107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5108 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5109 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5110 | struct drm_display_mode *adjusted_mode = |
5111 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5112 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5113 | ||
5114 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5115 | * the hw state checker will get angry at the mismatch. */ | |
5116 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5117 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5118 | |
5119 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5120 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5121 | crtc_vtotal -= 1; |
5122 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5123 | vsyncshift = adjusted_mode->crtc_hsync_start |
5124 | - adjusted_mode->crtc_htotal / 2; | |
5125 | } else { | |
5126 | vsyncshift = 0; | |
5127 | } | |
5128 | ||
5129 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5130 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5131 | |
fe2b8f9d | 5132 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5133 | (adjusted_mode->crtc_hdisplay - 1) | |
5134 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5135 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5136 | (adjusted_mode->crtc_hblank_start - 1) | |
5137 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5138 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5139 | (adjusted_mode->crtc_hsync_start - 1) | |
5140 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5141 | ||
fe2b8f9d | 5142 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5143 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5144 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5145 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5146 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5147 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5148 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5149 | (adjusted_mode->crtc_vsync_start - 1) | |
5150 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5151 | ||
b5e508d4 PZ |
5152 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5153 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5154 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5155 | * bits. */ | |
5156 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5157 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5158 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5159 | ||
b0e77b9c PZ |
5160 | /* pipesrc controls the size that is scaled from, which should |
5161 | * always be the user's requested size. | |
5162 | */ | |
5163 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5164 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5165 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5166 | } |
5167 | ||
1bd1bd80 DV |
5168 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5169 | struct intel_crtc_config *pipe_config) | |
5170 | { | |
5171 | struct drm_device *dev = crtc->base.dev; | |
5172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5173 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5174 | uint32_t tmp; | |
5175 | ||
5176 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5177 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5178 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5179 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5180 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5181 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5182 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5183 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5184 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5185 | ||
5186 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5187 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5188 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5189 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5190 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5191 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5192 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5193 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5194 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5195 | ||
5196 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5197 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5198 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5199 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5200 | } | |
5201 | ||
5202 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5203 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5204 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5205 | ||
5206 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5207 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5208 | } |
5209 | ||
babea61d JB |
5210 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5211 | struct intel_crtc_config *pipe_config) | |
5212 | { | |
5213 | struct drm_crtc *crtc = &intel_crtc->base; | |
5214 | ||
5215 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
5216 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5217 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5218 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
5219 | ||
5220 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
5221 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5222 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5223 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
5224 | ||
5225 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
5226 | ||
241bfc38 | 5227 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
5228 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5229 | } | |
5230 | ||
84b046f3 DV |
5231 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5232 | { | |
5233 | struct drm_device *dev = intel_crtc->base.dev; | |
5234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5235 | uint32_t pipeconf; | |
5236 | ||
9f11a9e4 | 5237 | pipeconf = 0; |
84b046f3 | 5238 | |
67c72a12 DV |
5239 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5240 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5241 | pipeconf |= PIPECONF_ENABLE; | |
5242 | ||
cf532bb2 VS |
5243 | if (intel_crtc->config.double_wide) |
5244 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5245 | |
ff9ce46e DV |
5246 | /* only g4x and later have fancy bpc/dither controls */ |
5247 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5248 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5249 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5250 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5251 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5252 | |
ff9ce46e DV |
5253 | switch (intel_crtc->config.pipe_bpp) { |
5254 | case 18: | |
5255 | pipeconf |= PIPECONF_6BPC; | |
5256 | break; | |
5257 | case 24: | |
5258 | pipeconf |= PIPECONF_8BPC; | |
5259 | break; | |
5260 | case 30: | |
5261 | pipeconf |= PIPECONF_10BPC; | |
5262 | break; | |
5263 | default: | |
5264 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5265 | BUG(); | |
84b046f3 DV |
5266 | } |
5267 | } | |
5268 | ||
5269 | if (HAS_PIPE_CXSR(dev)) { | |
5270 | if (intel_crtc->lowfreq_avail) { | |
5271 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5272 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5273 | } else { | |
5274 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5275 | } |
5276 | } | |
5277 | ||
84b046f3 DV |
5278 | if (!IS_GEN2(dev) && |
5279 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5280 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5281 | else | |
5282 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5283 | ||
9f11a9e4 DV |
5284 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5285 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5286 | |
84b046f3 DV |
5287 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5288 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5289 | } | |
5290 | ||
f564048e | 5291 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5292 | int x, int y, |
94352cf9 | 5293 | struct drm_framebuffer *fb) |
79e53945 JB |
5294 | { |
5295 | struct drm_device *dev = crtc->dev; | |
5296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5298 | int pipe = intel_crtc->pipe; | |
80824003 | 5299 | int plane = intel_crtc->plane; |
c751ce4f | 5300 | int refclk, num_connectors = 0; |
652c393a | 5301 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5302 | u32 dspcntr; |
a16af721 | 5303 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5304 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5305 | struct intel_encoder *encoder; |
d4906093 | 5306 | const intel_limit_t *limit; |
5c3b82e2 | 5307 | int ret; |
79e53945 | 5308 | |
6c2b7c12 | 5309 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5310 | switch (encoder->type) { |
79e53945 JB |
5311 | case INTEL_OUTPUT_LVDS: |
5312 | is_lvds = true; | |
5313 | break; | |
e9fd1c02 JN |
5314 | case INTEL_OUTPUT_DSI: |
5315 | is_dsi = true; | |
5316 | break; | |
79e53945 | 5317 | } |
43565a06 | 5318 | |
c751ce4f | 5319 | num_connectors++; |
79e53945 JB |
5320 | } |
5321 | ||
f2335330 JN |
5322 | if (is_dsi) |
5323 | goto skip_dpll; | |
5324 | ||
5325 | if (!intel_crtc->config.clock_set) { | |
5326 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5327 | |
e9fd1c02 JN |
5328 | /* |
5329 | * Returns a set of divisors for the desired target clock with | |
5330 | * the given refclk, or FALSE. The returned values represent | |
5331 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5332 | * 2) / p1 / p2. | |
5333 | */ | |
5334 | limit = intel_limit(crtc, refclk); | |
5335 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5336 | intel_crtc->config.port_clock, | |
5337 | refclk, NULL, &clock); | |
f2335330 | 5338 | if (!ok) { |
e9fd1c02 JN |
5339 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5340 | return -EINVAL; | |
5341 | } | |
79e53945 | 5342 | |
f2335330 JN |
5343 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5344 | /* | |
5345 | * Ensure we match the reduced clock's P to the target | |
5346 | * clock. If the clocks don't match, we can't switch | |
5347 | * the display clock by using the FP0/FP1. In such case | |
5348 | * we will disable the LVDS downclock feature. | |
5349 | */ | |
5350 | has_reduced_clock = | |
5351 | dev_priv->display.find_dpll(limit, crtc, | |
5352 | dev_priv->lvds_downclock, | |
5353 | refclk, &clock, | |
5354 | &reduced_clock); | |
5355 | } | |
5356 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5357 | intel_crtc->config.dpll.n = clock.n; |
5358 | intel_crtc->config.dpll.m1 = clock.m1; | |
5359 | intel_crtc->config.dpll.m2 = clock.m2; | |
5360 | intel_crtc->config.dpll.p1 = clock.p1; | |
5361 | intel_crtc->config.dpll.p2 = clock.p2; | |
5362 | } | |
7026d4ac | 5363 | |
e9fd1c02 | 5364 | if (IS_GEN2(dev)) { |
8a654f3b | 5365 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5366 | has_reduced_clock ? &reduced_clock : NULL, |
5367 | num_connectors); | |
e9fd1c02 | 5368 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5369 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5370 | } else { |
f47709a9 | 5371 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5372 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5373 | num_connectors); |
e9fd1c02 | 5374 | } |
79e53945 | 5375 | |
f2335330 | 5376 | skip_dpll: |
79e53945 JB |
5377 | /* Set up the display plane register */ |
5378 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5379 | ||
da6ecc5d JB |
5380 | if (!IS_VALLEYVIEW(dev)) { |
5381 | if (pipe == 0) | |
5382 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5383 | else | |
5384 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5385 | } | |
79e53945 | 5386 | |
8a654f3b | 5387 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5388 | |
5389 | /* pipesrc and dspsize control the size that is scaled from, | |
5390 | * which should always be the user's requested size. | |
79e53945 | 5391 | */ |
929c77fb | 5392 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5393 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5394 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5395 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5396 | |
84b046f3 DV |
5397 | i9xx_set_pipeconf(intel_crtc); |
5398 | ||
f564048e EA |
5399 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5400 | POSTING_READ(DSPCNTR(plane)); | |
5401 | ||
94352cf9 | 5402 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5403 | |
f564048e EA |
5404 | return ret; |
5405 | } | |
5406 | ||
2fa2fe9a DV |
5407 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5408 | struct intel_crtc_config *pipe_config) | |
5409 | { | |
5410 | struct drm_device *dev = crtc->base.dev; | |
5411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5412 | uint32_t tmp; | |
5413 | ||
5414 | tmp = I915_READ(PFIT_CONTROL); | |
06922821 DV |
5415 | if (!(tmp & PFIT_ENABLE)) |
5416 | return; | |
2fa2fe9a | 5417 | |
06922821 | 5418 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5419 | if (INTEL_INFO(dev)->gen < 4) { |
5420 | if (crtc->pipe != PIPE_B) | |
5421 | return; | |
2fa2fe9a DV |
5422 | } else { |
5423 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5424 | return; | |
5425 | } | |
5426 | ||
06922821 | 5427 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5428 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5429 | if (INTEL_INFO(dev)->gen < 5) | |
5430 | pipe_config->gmch_pfit.lvds_border_bits = | |
5431 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5432 | } | |
5433 | ||
acbec814 JB |
5434 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5435 | struct intel_crtc_config *pipe_config) | |
5436 | { | |
5437 | struct drm_device *dev = crtc->base.dev; | |
5438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5439 | int pipe = pipe_config->cpu_transcoder; | |
5440 | intel_clock_t clock; | |
5441 | u32 mdiv; | |
662c6ecb | 5442 | int refclk = 100000; |
acbec814 JB |
5443 | |
5444 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5445 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5446 | mutex_unlock(&dev_priv->dpio_lock); |
5447 | ||
5448 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5449 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5450 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5451 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5452 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5453 | ||
f646628b | 5454 | vlv_clock(refclk, &clock); |
acbec814 | 5455 | |
f646628b VS |
5456 | /* clock.dot is the fast clock */ |
5457 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5458 | } |
5459 | ||
0e8ffe1b DV |
5460 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5461 | struct intel_crtc_config *pipe_config) | |
5462 | { | |
5463 | struct drm_device *dev = crtc->base.dev; | |
5464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5465 | uint32_t tmp; | |
5466 | ||
e143a21c | 5467 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5468 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5469 | |
0e8ffe1b DV |
5470 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5471 | if (!(tmp & PIPECONF_ENABLE)) | |
5472 | return false; | |
5473 | ||
42571aef VS |
5474 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5475 | switch (tmp & PIPECONF_BPC_MASK) { | |
5476 | case PIPECONF_6BPC: | |
5477 | pipe_config->pipe_bpp = 18; | |
5478 | break; | |
5479 | case PIPECONF_8BPC: | |
5480 | pipe_config->pipe_bpp = 24; | |
5481 | break; | |
5482 | case PIPECONF_10BPC: | |
5483 | pipe_config->pipe_bpp = 30; | |
5484 | break; | |
5485 | default: | |
5486 | break; | |
5487 | } | |
5488 | } | |
5489 | ||
282740f7 VS |
5490 | if (INTEL_INFO(dev)->gen < 4) |
5491 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5492 | ||
1bd1bd80 DV |
5493 | intel_get_pipe_timings(crtc, pipe_config); |
5494 | ||
2fa2fe9a DV |
5495 | i9xx_get_pfit_config(crtc, pipe_config); |
5496 | ||
6c49f241 DV |
5497 | if (INTEL_INFO(dev)->gen >= 4) { |
5498 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5499 | pipe_config->pixel_multiplier = | |
5500 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5501 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5502 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5503 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5504 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5505 | pipe_config->pixel_multiplier = | |
5506 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5507 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5508 | } else { | |
5509 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5510 | * port and will be fixed up in the encoder->get_config | |
5511 | * function. */ | |
5512 | pipe_config->pixel_multiplier = 1; | |
5513 | } | |
8bcc2795 DV |
5514 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5515 | if (!IS_VALLEYVIEW(dev)) { | |
5516 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5517 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5518 | } else { |
5519 | /* Mask out read-only status bits. */ | |
5520 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5521 | DPLL_PORTC_READY_MASK | | |
5522 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5523 | } |
6c49f241 | 5524 | |
acbec814 JB |
5525 | if (IS_VALLEYVIEW(dev)) |
5526 | vlv_crtc_clock_get(crtc, pipe_config); | |
5527 | else | |
5528 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5529 | |
0e8ffe1b DV |
5530 | return true; |
5531 | } | |
5532 | ||
dde86e2d | 5533 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5534 | { |
5535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5536 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5537 | struct intel_encoder *encoder; |
74cfd7ac | 5538 | u32 val, final; |
13d83a67 | 5539 | bool has_lvds = false; |
199e5d79 | 5540 | bool has_cpu_edp = false; |
199e5d79 | 5541 | bool has_panel = false; |
99eb6a01 KP |
5542 | bool has_ck505 = false; |
5543 | bool can_ssc = false; | |
13d83a67 JB |
5544 | |
5545 | /* We need to take the global config into account */ | |
199e5d79 KP |
5546 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5547 | base.head) { | |
5548 | switch (encoder->type) { | |
5549 | case INTEL_OUTPUT_LVDS: | |
5550 | has_panel = true; | |
5551 | has_lvds = true; | |
5552 | break; | |
5553 | case INTEL_OUTPUT_EDP: | |
5554 | has_panel = true; | |
2de6905f | 5555 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5556 | has_cpu_edp = true; |
5557 | break; | |
13d83a67 JB |
5558 | } |
5559 | } | |
5560 | ||
99eb6a01 | 5561 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5562 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5563 | can_ssc = has_ck505; |
5564 | } else { | |
5565 | has_ck505 = false; | |
5566 | can_ssc = true; | |
5567 | } | |
5568 | ||
2de6905f ID |
5569 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5570 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5571 | |
5572 | /* Ironlake: try to setup display ref clock before DPLL | |
5573 | * enabling. This is only under driver's control after | |
5574 | * PCH B stepping, previous chipset stepping should be | |
5575 | * ignoring this setting. | |
5576 | */ | |
74cfd7ac CW |
5577 | val = I915_READ(PCH_DREF_CONTROL); |
5578 | ||
5579 | /* As we must carefully and slowly disable/enable each source in turn, | |
5580 | * compute the final state we want first and check if we need to | |
5581 | * make any changes at all. | |
5582 | */ | |
5583 | final = val; | |
5584 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5585 | if (has_ck505) | |
5586 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5587 | else | |
5588 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5589 | ||
5590 | final &= ~DREF_SSC_SOURCE_MASK; | |
5591 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5592 | final &= ~DREF_SSC1_ENABLE; | |
5593 | ||
5594 | if (has_panel) { | |
5595 | final |= DREF_SSC_SOURCE_ENABLE; | |
5596 | ||
5597 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5598 | final |= DREF_SSC1_ENABLE; | |
5599 | ||
5600 | if (has_cpu_edp) { | |
5601 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5602 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5603 | else | |
5604 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5605 | } else | |
5606 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5607 | } else { | |
5608 | final |= DREF_SSC_SOURCE_DISABLE; | |
5609 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5610 | } | |
5611 | ||
5612 | if (final == val) | |
5613 | return; | |
5614 | ||
13d83a67 | 5615 | /* Always enable nonspread source */ |
74cfd7ac | 5616 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5617 | |
99eb6a01 | 5618 | if (has_ck505) |
74cfd7ac | 5619 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5620 | else |
74cfd7ac | 5621 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5622 | |
199e5d79 | 5623 | if (has_panel) { |
74cfd7ac CW |
5624 | val &= ~DREF_SSC_SOURCE_MASK; |
5625 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5626 | |
199e5d79 | 5627 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5628 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5629 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5630 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5631 | } else |
74cfd7ac | 5632 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5633 | |
5634 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5635 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5636 | POSTING_READ(PCH_DREF_CONTROL); |
5637 | udelay(200); | |
5638 | ||
74cfd7ac | 5639 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5640 | |
5641 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5642 | if (has_cpu_edp) { |
99eb6a01 | 5643 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5644 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5645 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5646 | } |
13d83a67 | 5647 | else |
74cfd7ac | 5648 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5649 | } else |
74cfd7ac | 5650 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5651 | |
74cfd7ac | 5652 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5653 | POSTING_READ(PCH_DREF_CONTROL); |
5654 | udelay(200); | |
5655 | } else { | |
5656 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5657 | ||
74cfd7ac | 5658 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5659 | |
5660 | /* Turn off CPU output */ | |
74cfd7ac | 5661 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5662 | |
74cfd7ac | 5663 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5664 | POSTING_READ(PCH_DREF_CONTROL); |
5665 | udelay(200); | |
5666 | ||
5667 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5668 | val &= ~DREF_SSC_SOURCE_MASK; |
5669 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5670 | |
5671 | /* Turn off SSC1 */ | |
74cfd7ac | 5672 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5673 | |
74cfd7ac | 5674 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5675 | POSTING_READ(PCH_DREF_CONTROL); |
5676 | udelay(200); | |
5677 | } | |
74cfd7ac CW |
5678 | |
5679 | BUG_ON(val != final); | |
13d83a67 JB |
5680 | } |
5681 | ||
f31f2d55 | 5682 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5683 | { |
f31f2d55 | 5684 | uint32_t tmp; |
dde86e2d | 5685 | |
0ff066a9 PZ |
5686 | tmp = I915_READ(SOUTH_CHICKEN2); |
5687 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5688 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5689 | |
0ff066a9 PZ |
5690 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5691 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5692 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5693 | |
0ff066a9 PZ |
5694 | tmp = I915_READ(SOUTH_CHICKEN2); |
5695 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5696 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5697 | |
0ff066a9 PZ |
5698 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5699 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5700 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5701 | } |
5702 | ||
5703 | /* WaMPhyProgramming:hsw */ | |
5704 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5705 | { | |
5706 | uint32_t tmp; | |
dde86e2d PZ |
5707 | |
5708 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5709 | tmp &= ~(0xFF << 24); | |
5710 | tmp |= (0x12 << 24); | |
5711 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5712 | ||
dde86e2d PZ |
5713 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5714 | tmp |= (1 << 11); | |
5715 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5716 | ||
5717 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5718 | tmp |= (1 << 11); | |
5719 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5720 | ||
dde86e2d PZ |
5721 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5722 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5723 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5724 | ||
5725 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5726 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5727 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5728 | ||
0ff066a9 PZ |
5729 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5730 | tmp &= ~(7 << 13); | |
5731 | tmp |= (5 << 13); | |
5732 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5733 | |
0ff066a9 PZ |
5734 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5735 | tmp &= ~(7 << 13); | |
5736 | tmp |= (5 << 13); | |
5737 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5738 | |
5739 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5740 | tmp &= ~0xFF; | |
5741 | tmp |= 0x1C; | |
5742 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5743 | ||
5744 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5745 | tmp &= ~0xFF; | |
5746 | tmp |= 0x1C; | |
5747 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5748 | ||
5749 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5750 | tmp &= ~(0xFF << 16); | |
5751 | tmp |= (0x1C << 16); | |
5752 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5753 | ||
5754 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5755 | tmp &= ~(0xFF << 16); | |
5756 | tmp |= (0x1C << 16); | |
5757 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5758 | ||
0ff066a9 PZ |
5759 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5760 | tmp |= (1 << 27); | |
5761 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5762 | |
0ff066a9 PZ |
5763 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5764 | tmp |= (1 << 27); | |
5765 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5766 | |
0ff066a9 PZ |
5767 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5768 | tmp &= ~(0xF << 28); | |
5769 | tmp |= (4 << 28); | |
5770 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5771 | |
0ff066a9 PZ |
5772 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5773 | tmp &= ~(0xF << 28); | |
5774 | tmp |= (4 << 28); | |
5775 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5776 | } |
5777 | ||
2fa86a1f PZ |
5778 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5779 | * Programming" based on the parameters passed: | |
5780 | * - Sequence to enable CLKOUT_DP | |
5781 | * - Sequence to enable CLKOUT_DP without spread | |
5782 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5783 | */ | |
5784 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5785 | bool with_fdi) | |
f31f2d55 PZ |
5786 | { |
5787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5788 | uint32_t reg, tmp; |
5789 | ||
5790 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5791 | with_spread = true; | |
5792 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5793 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5794 | with_fdi = false; | |
f31f2d55 PZ |
5795 | |
5796 | mutex_lock(&dev_priv->dpio_lock); | |
5797 | ||
5798 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5799 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5800 | tmp |= SBI_SSCCTL_PATHALT; | |
5801 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5802 | ||
5803 | udelay(24); | |
5804 | ||
2fa86a1f PZ |
5805 | if (with_spread) { |
5806 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5807 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5808 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5809 | |
2fa86a1f PZ |
5810 | if (with_fdi) { |
5811 | lpt_reset_fdi_mphy(dev_priv); | |
5812 | lpt_program_fdi_mphy(dev_priv); | |
5813 | } | |
5814 | } | |
dde86e2d | 5815 | |
2fa86a1f PZ |
5816 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5817 | SBI_GEN0 : SBI_DBUFF0; | |
5818 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5819 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5820 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5821 | |
5822 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5823 | } |
5824 | ||
47701c3b PZ |
5825 | /* Sequence to disable CLKOUT_DP */ |
5826 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5827 | { | |
5828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5829 | uint32_t reg, tmp; | |
5830 | ||
5831 | mutex_lock(&dev_priv->dpio_lock); | |
5832 | ||
5833 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5834 | SBI_GEN0 : SBI_DBUFF0; | |
5835 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5836 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5837 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5838 | ||
5839 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5840 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5841 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5842 | tmp |= SBI_SSCCTL_PATHALT; | |
5843 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5844 | udelay(32); | |
5845 | } | |
5846 | tmp |= SBI_SSCCTL_DISABLE; | |
5847 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5848 | } | |
5849 | ||
5850 | mutex_unlock(&dev_priv->dpio_lock); | |
5851 | } | |
5852 | ||
bf8fa3d3 PZ |
5853 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5854 | { | |
5855 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5856 | struct intel_encoder *encoder; | |
5857 | bool has_vga = false; | |
5858 | ||
5859 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5860 | switch (encoder->type) { | |
5861 | case INTEL_OUTPUT_ANALOG: | |
5862 | has_vga = true; | |
5863 | break; | |
5864 | } | |
5865 | } | |
5866 | ||
47701c3b PZ |
5867 | if (has_vga) |
5868 | lpt_enable_clkout_dp(dev, true, true); | |
5869 | else | |
5870 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5871 | } |
5872 | ||
dde86e2d PZ |
5873 | /* |
5874 | * Initialize reference clocks when the driver loads | |
5875 | */ | |
5876 | void intel_init_pch_refclk(struct drm_device *dev) | |
5877 | { | |
5878 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5879 | ironlake_init_pch_refclk(dev); | |
5880 | else if (HAS_PCH_LPT(dev)) | |
5881 | lpt_init_pch_refclk(dev); | |
5882 | } | |
5883 | ||
d9d444cb JB |
5884 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5885 | { | |
5886 | struct drm_device *dev = crtc->dev; | |
5887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5888 | struct intel_encoder *encoder; | |
d9d444cb JB |
5889 | int num_connectors = 0; |
5890 | bool is_lvds = false; | |
5891 | ||
6c2b7c12 | 5892 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5893 | switch (encoder->type) { |
5894 | case INTEL_OUTPUT_LVDS: | |
5895 | is_lvds = true; | |
5896 | break; | |
d9d444cb JB |
5897 | } |
5898 | num_connectors++; | |
5899 | } | |
5900 | ||
5901 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5902 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
41aa3448 RV |
5903 | dev_priv->vbt.lvds_ssc_freq); |
5904 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
d9d444cb JB |
5905 | } |
5906 | ||
5907 | return 120000; | |
5908 | } | |
5909 | ||
6ff93609 | 5910 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5911 | { |
c8203565 | 5912 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5914 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5915 | uint32_t val; |
5916 | ||
78114071 | 5917 | val = 0; |
c8203565 | 5918 | |
965e0c48 | 5919 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5920 | case 18: |
dfd07d72 | 5921 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5922 | break; |
5923 | case 24: | |
dfd07d72 | 5924 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5925 | break; |
5926 | case 30: | |
dfd07d72 | 5927 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5928 | break; |
5929 | case 36: | |
dfd07d72 | 5930 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5931 | break; |
5932 | default: | |
cc769b62 PZ |
5933 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5934 | BUG(); | |
c8203565 PZ |
5935 | } |
5936 | ||
d8b32247 | 5937 | if (intel_crtc->config.dither) |
c8203565 PZ |
5938 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5939 | ||
6ff93609 | 5940 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5941 | val |= PIPECONF_INTERLACED_ILK; |
5942 | else | |
5943 | val |= PIPECONF_PROGRESSIVE; | |
5944 | ||
50f3b016 | 5945 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 5946 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 5947 | |
c8203565 PZ |
5948 | I915_WRITE(PIPECONF(pipe), val); |
5949 | POSTING_READ(PIPECONF(pipe)); | |
5950 | } | |
5951 | ||
86d3efce VS |
5952 | /* |
5953 | * Set up the pipe CSC unit. | |
5954 | * | |
5955 | * Currently only full range RGB to limited range RGB conversion | |
5956 | * is supported, but eventually this should handle various | |
5957 | * RGB<->YCbCr scenarios as well. | |
5958 | */ | |
50f3b016 | 5959 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5960 | { |
5961 | struct drm_device *dev = crtc->dev; | |
5962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5964 | int pipe = intel_crtc->pipe; | |
5965 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5966 | ||
5967 | /* | |
5968 | * TODO: Check what kind of values actually come out of the pipe | |
5969 | * with these coeff/postoff values and adjust to get the best | |
5970 | * accuracy. Perhaps we even need to take the bpc value into | |
5971 | * consideration. | |
5972 | */ | |
5973 | ||
50f3b016 | 5974 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5975 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5976 | ||
5977 | /* | |
5978 | * GY/GU and RY/RU should be the other way around according | |
5979 | * to BSpec, but reality doesn't agree. Just set them up in | |
5980 | * a way that results in the correct picture. | |
5981 | */ | |
5982 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5983 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5984 | ||
5985 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5986 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5987 | ||
5988 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5989 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5990 | ||
5991 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5992 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5993 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5994 | ||
5995 | if (INTEL_INFO(dev)->gen > 6) { | |
5996 | uint16_t postoff = 0; | |
5997 | ||
50f3b016 | 5998 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5999 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
6000 | ||
6001 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6002 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6003 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6004 | ||
6005 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6006 | } else { | |
6007 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6008 | ||
50f3b016 | 6009 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6010 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6011 | ||
6012 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6013 | } | |
6014 | } | |
6015 | ||
6ff93609 | 6016 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6017 | { |
756f85cf PZ |
6018 | struct drm_device *dev = crtc->dev; |
6019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6021 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6022 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6023 | uint32_t val; |
6024 | ||
3eff4faa | 6025 | val = 0; |
ee2b0b38 | 6026 | |
756f85cf | 6027 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6028 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6029 | ||
6ff93609 | 6030 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6031 | val |= PIPECONF_INTERLACED_ILK; |
6032 | else | |
6033 | val |= PIPECONF_PROGRESSIVE; | |
6034 | ||
702e7a56 PZ |
6035 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6036 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6037 | |
6038 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6039 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6040 | |
6041 | if (IS_BROADWELL(dev)) { | |
6042 | val = 0; | |
6043 | ||
6044 | switch (intel_crtc->config.pipe_bpp) { | |
6045 | case 18: | |
6046 | val |= PIPEMISC_DITHER_6_BPC; | |
6047 | break; | |
6048 | case 24: | |
6049 | val |= PIPEMISC_DITHER_8_BPC; | |
6050 | break; | |
6051 | case 30: | |
6052 | val |= PIPEMISC_DITHER_10_BPC; | |
6053 | break; | |
6054 | case 36: | |
6055 | val |= PIPEMISC_DITHER_12_BPC; | |
6056 | break; | |
6057 | default: | |
6058 | /* Case prevented by pipe_config_set_bpp. */ | |
6059 | BUG(); | |
6060 | } | |
6061 | ||
6062 | if (intel_crtc->config.dither) | |
6063 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6064 | ||
6065 | I915_WRITE(PIPEMISC(pipe), val); | |
6066 | } | |
ee2b0b38 PZ |
6067 | } |
6068 | ||
6591c6e4 | 6069 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6070 | intel_clock_t *clock, |
6071 | bool *has_reduced_clock, | |
6072 | intel_clock_t *reduced_clock) | |
6073 | { | |
6074 | struct drm_device *dev = crtc->dev; | |
6075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6076 | struct intel_encoder *intel_encoder; | |
6077 | int refclk; | |
d4906093 | 6078 | const intel_limit_t *limit; |
a16af721 | 6079 | bool ret, is_lvds = false; |
79e53945 | 6080 | |
6591c6e4 PZ |
6081 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6082 | switch (intel_encoder->type) { | |
79e53945 JB |
6083 | case INTEL_OUTPUT_LVDS: |
6084 | is_lvds = true; | |
6085 | break; | |
79e53945 JB |
6086 | } |
6087 | } | |
6088 | ||
d9d444cb | 6089 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6090 | |
d4906093 ML |
6091 | /* |
6092 | * Returns a set of divisors for the desired target clock with the given | |
6093 | * refclk, or FALSE. The returned values represent the clock equation: | |
6094 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6095 | */ | |
1b894b59 | 6096 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6097 | ret = dev_priv->display.find_dpll(limit, crtc, |
6098 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6099 | refclk, NULL, clock); |
6591c6e4 PZ |
6100 | if (!ret) |
6101 | return false; | |
cda4b7d3 | 6102 | |
ddc9003c | 6103 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6104 | /* |
6105 | * Ensure we match the reduced clock's P to the target clock. | |
6106 | * If the clocks don't match, we can't switch the display clock | |
6107 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6108 | * downclock feature. | |
6109 | */ | |
ee9300bb DV |
6110 | *has_reduced_clock = |
6111 | dev_priv->display.find_dpll(limit, crtc, | |
6112 | dev_priv->lvds_downclock, | |
6113 | refclk, clock, | |
6114 | reduced_clock); | |
652c393a | 6115 | } |
61e9653f | 6116 | |
6591c6e4 PZ |
6117 | return true; |
6118 | } | |
6119 | ||
d4b1931c PZ |
6120 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6121 | { | |
6122 | /* | |
6123 | * Account for spread spectrum to avoid | |
6124 | * oversubscribing the link. Max center spread | |
6125 | * is 2.5%; use 5% for safety's sake. | |
6126 | */ | |
6127 | u32 bps = target_clock * bpp * 21 / 20; | |
6128 | return bps / (link_bw * 8) + 1; | |
6129 | } | |
6130 | ||
7429e9d4 | 6131 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6132 | { |
7429e9d4 | 6133 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6134 | } |
6135 | ||
de13a2e3 | 6136 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6137 | u32 *fp, |
9a7c7890 | 6138 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6139 | { |
de13a2e3 | 6140 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6141 | struct drm_device *dev = crtc->dev; |
6142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6143 | struct intel_encoder *intel_encoder; |
6144 | uint32_t dpll; | |
6cc5f341 | 6145 | int factor, num_connectors = 0; |
09ede541 | 6146 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6147 | |
de13a2e3 PZ |
6148 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6149 | switch (intel_encoder->type) { | |
79e53945 JB |
6150 | case INTEL_OUTPUT_LVDS: |
6151 | is_lvds = true; | |
6152 | break; | |
6153 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6154 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6155 | is_sdvo = true; |
79e53945 | 6156 | break; |
79e53945 | 6157 | } |
43565a06 | 6158 | |
c751ce4f | 6159 | num_connectors++; |
79e53945 | 6160 | } |
79e53945 | 6161 | |
c1858123 | 6162 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6163 | factor = 21; |
6164 | if (is_lvds) { | |
6165 | if ((intel_panel_use_ssc(dev_priv) && | |
41aa3448 | 6166 | dev_priv->vbt.lvds_ssc_freq == 100) || |
f0b44056 | 6167 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6168 | factor = 25; |
09ede541 | 6169 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6170 | factor = 20; |
c1858123 | 6171 | |
7429e9d4 | 6172 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6173 | *fp |= FP_CB_TUNE; |
2c07245f | 6174 | |
9a7c7890 DV |
6175 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6176 | *fp2 |= FP_CB_TUNE; | |
6177 | ||
5eddb70b | 6178 | dpll = 0; |
2c07245f | 6179 | |
a07d6787 EA |
6180 | if (is_lvds) |
6181 | dpll |= DPLLB_MODE_LVDS; | |
6182 | else | |
6183 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6184 | |
ef1b460d DV |
6185 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6186 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6187 | |
6188 | if (is_sdvo) | |
4a33e48d | 6189 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6190 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6191 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6192 | |
a07d6787 | 6193 | /* compute bitmask from p1 value */ |
7429e9d4 | 6194 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6195 | /* also FPA1 */ |
7429e9d4 | 6196 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6197 | |
7429e9d4 | 6198 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6199 | case 5: |
6200 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6201 | break; | |
6202 | case 7: | |
6203 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6204 | break; | |
6205 | case 10: | |
6206 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6207 | break; | |
6208 | case 14: | |
6209 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6210 | break; | |
79e53945 JB |
6211 | } |
6212 | ||
b4c09f3b | 6213 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6214 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6215 | else |
6216 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6217 | ||
959e16d6 | 6218 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6219 | } |
6220 | ||
6221 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6222 | int x, int y, |
6223 | struct drm_framebuffer *fb) | |
6224 | { | |
6225 | struct drm_device *dev = crtc->dev; | |
6226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6228 | int pipe = intel_crtc->pipe; | |
6229 | int plane = intel_crtc->plane; | |
6230 | int num_connectors = 0; | |
6231 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6232 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6233 | bool ok, has_reduced_clock = false; |
8b47047b | 6234 | bool is_lvds = false; |
de13a2e3 | 6235 | struct intel_encoder *encoder; |
e2b78267 | 6236 | struct intel_shared_dpll *pll; |
de13a2e3 | 6237 | int ret; |
de13a2e3 PZ |
6238 | |
6239 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6240 | switch (encoder->type) { | |
6241 | case INTEL_OUTPUT_LVDS: | |
6242 | is_lvds = true; | |
6243 | break; | |
de13a2e3 PZ |
6244 | } |
6245 | ||
6246 | num_connectors++; | |
a07d6787 | 6247 | } |
79e53945 | 6248 | |
5dc5298b PZ |
6249 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6250 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6251 | |
ff9a6750 | 6252 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6253 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6254 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6255 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6256 | return -EINVAL; | |
79e53945 | 6257 | } |
f47709a9 DV |
6258 | /* Compat-code for transition, will disappear. */ |
6259 | if (!intel_crtc->config.clock_set) { | |
6260 | intel_crtc->config.dpll.n = clock.n; | |
6261 | intel_crtc->config.dpll.m1 = clock.m1; | |
6262 | intel_crtc->config.dpll.m2 = clock.m2; | |
6263 | intel_crtc->config.dpll.p1 = clock.p1; | |
6264 | intel_crtc->config.dpll.p2 = clock.p2; | |
6265 | } | |
79e53945 | 6266 | |
5dc5298b | 6267 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6268 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6269 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6270 | if (has_reduced_clock) |
7429e9d4 | 6271 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6272 | |
7429e9d4 | 6273 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6274 | &fp, &reduced_clock, |
6275 | has_reduced_clock ? &fp2 : NULL); | |
6276 | ||
959e16d6 | 6277 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6278 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6279 | if (has_reduced_clock) | |
6280 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6281 | else | |
6282 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6283 | ||
b89a1d39 | 6284 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6285 | if (pll == NULL) { |
84f44ce7 VS |
6286 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6287 | pipe_name(pipe)); | |
4b645f14 JB |
6288 | return -EINVAL; |
6289 | } | |
ee7b9f93 | 6290 | } else |
e72f9fbf | 6291 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6292 | |
03afc4a2 DV |
6293 | if (intel_crtc->config.has_dp_encoder) |
6294 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6295 | |
bcd644e0 DV |
6296 | if (is_lvds && has_reduced_clock && i915_powersave) |
6297 | intel_crtc->lowfreq_avail = true; | |
6298 | else | |
6299 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6300 | |
8a654f3b | 6301 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6302 | |
ca3a0ff8 | 6303 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6304 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6305 | &intel_crtc->config.fdi_m_n); | |
6306 | } | |
2c07245f | 6307 | |
6ff93609 | 6308 | ironlake_set_pipeconf(crtc); |
79e53945 | 6309 | |
a1f9e77e PZ |
6310 | /* Set up the display plane register */ |
6311 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6312 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6313 | |
94352cf9 | 6314 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6315 | |
1857e1da | 6316 | return ret; |
79e53945 JB |
6317 | } |
6318 | ||
eb14cb74 VS |
6319 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6320 | struct intel_link_m_n *m_n) | |
6321 | { | |
6322 | struct drm_device *dev = crtc->base.dev; | |
6323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6324 | enum pipe pipe = crtc->pipe; | |
6325 | ||
6326 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6327 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6328 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6329 | & ~TU_SIZE_MASK; | |
6330 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6331 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6332 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6333 | } | |
6334 | ||
6335 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6336 | enum transcoder transcoder, | |
6337 | struct intel_link_m_n *m_n) | |
72419203 DV |
6338 | { |
6339 | struct drm_device *dev = crtc->base.dev; | |
6340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6341 | enum pipe pipe = crtc->pipe; |
72419203 | 6342 | |
eb14cb74 VS |
6343 | if (INTEL_INFO(dev)->gen >= 5) { |
6344 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6345 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6346 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6347 | & ~TU_SIZE_MASK; | |
6348 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6349 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6350 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6351 | } else { | |
6352 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6353 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6354 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6355 | & ~TU_SIZE_MASK; | |
6356 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6357 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6358 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6359 | } | |
6360 | } | |
6361 | ||
6362 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6363 | struct intel_crtc_config *pipe_config) | |
6364 | { | |
6365 | if (crtc->config.has_pch_encoder) | |
6366 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6367 | else | |
6368 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6369 | &pipe_config->dp_m_n); | |
6370 | } | |
72419203 | 6371 | |
eb14cb74 VS |
6372 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6373 | struct intel_crtc_config *pipe_config) | |
6374 | { | |
6375 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6376 | &pipe_config->fdi_m_n); | |
72419203 DV |
6377 | } |
6378 | ||
2fa2fe9a DV |
6379 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6380 | struct intel_crtc_config *pipe_config) | |
6381 | { | |
6382 | struct drm_device *dev = crtc->base.dev; | |
6383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6384 | uint32_t tmp; | |
6385 | ||
6386 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6387 | ||
6388 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6389 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6390 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6391 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6392 | |
6393 | /* We currently do not free assignements of panel fitters on | |
6394 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6395 | * differentiates them) so just WARN about this case for now. */ | |
6396 | if (IS_GEN7(dev)) { | |
6397 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6398 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6399 | } | |
2fa2fe9a | 6400 | } |
79e53945 JB |
6401 | } |
6402 | ||
0e8ffe1b DV |
6403 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6404 | struct intel_crtc_config *pipe_config) | |
6405 | { | |
6406 | struct drm_device *dev = crtc->base.dev; | |
6407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6408 | uint32_t tmp; | |
6409 | ||
e143a21c | 6410 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6411 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6412 | |
0e8ffe1b DV |
6413 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6414 | if (!(tmp & PIPECONF_ENABLE)) | |
6415 | return false; | |
6416 | ||
42571aef VS |
6417 | switch (tmp & PIPECONF_BPC_MASK) { |
6418 | case PIPECONF_6BPC: | |
6419 | pipe_config->pipe_bpp = 18; | |
6420 | break; | |
6421 | case PIPECONF_8BPC: | |
6422 | pipe_config->pipe_bpp = 24; | |
6423 | break; | |
6424 | case PIPECONF_10BPC: | |
6425 | pipe_config->pipe_bpp = 30; | |
6426 | break; | |
6427 | case PIPECONF_12BPC: | |
6428 | pipe_config->pipe_bpp = 36; | |
6429 | break; | |
6430 | default: | |
6431 | break; | |
6432 | } | |
6433 | ||
ab9412ba | 6434 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6435 | struct intel_shared_dpll *pll; |
6436 | ||
88adfff1 DV |
6437 | pipe_config->has_pch_encoder = true; |
6438 | ||
627eb5a3 DV |
6439 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6440 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6441 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6442 | |
6443 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6444 | |
c0d43d62 | 6445 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6446 | pipe_config->shared_dpll = |
6447 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6448 | } else { |
6449 | tmp = I915_READ(PCH_DPLL_SEL); | |
6450 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6451 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6452 | else | |
6453 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6454 | } | |
66e985c0 DV |
6455 | |
6456 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6457 | ||
6458 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6459 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6460 | |
6461 | tmp = pipe_config->dpll_hw_state.dpll; | |
6462 | pipe_config->pixel_multiplier = | |
6463 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6464 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6465 | |
6466 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6467 | } else { |
6468 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6469 | } |
6470 | ||
1bd1bd80 DV |
6471 | intel_get_pipe_timings(crtc, pipe_config); |
6472 | ||
2fa2fe9a DV |
6473 | ironlake_get_pfit_config(crtc, pipe_config); |
6474 | ||
0e8ffe1b DV |
6475 | return true; |
6476 | } | |
6477 | ||
be256dc7 PZ |
6478 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6479 | { | |
6480 | struct drm_device *dev = dev_priv->dev; | |
6481 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6482 | struct intel_crtc *crtc; | |
6483 | unsigned long irqflags; | |
bd633a7c | 6484 | uint32_t val; |
be256dc7 PZ |
6485 | |
6486 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6487 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", | |
6488 | pipe_name(crtc->pipe)); | |
6489 | ||
6490 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6491 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6492 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6493 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6494 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6495 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6496 | "CPU PWM1 enabled\n"); | |
6497 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6498 | "CPU PWM2 enabled\n"); | |
6499 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6500 | "PCH PWM1 enabled\n"); | |
6501 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6502 | "Utility pin enabled\n"); | |
6503 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6504 | ||
6505 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6506 | val = I915_READ(DEIMR); | |
6507 | WARN((val & ~DE_PCH_EVENT_IVB) != val, | |
6508 | "Unexpected DEIMR bits enabled: 0x%x\n", val); | |
6509 | val = I915_READ(SDEIMR); | |
bd633a7c | 6510 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6511 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6512 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6513 | } | |
6514 | ||
6515 | /* | |
6516 | * This function implements pieces of two sequences from BSpec: | |
6517 | * - Sequence for display software to disable LCPLL | |
6518 | * - Sequence for display software to allow package C8+ | |
6519 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6520 | * register. Callers should take care of disabling all the display engine | |
6521 | * functions, doing the mode unset, fixing interrupts, etc. | |
6522 | */ | |
6ff58d53 PZ |
6523 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6524 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6525 | { |
6526 | uint32_t val; | |
6527 | ||
6528 | assert_can_disable_lcpll(dev_priv); | |
6529 | ||
6530 | val = I915_READ(LCPLL_CTL); | |
6531 | ||
6532 | if (switch_to_fclk) { | |
6533 | val |= LCPLL_CD_SOURCE_FCLK; | |
6534 | I915_WRITE(LCPLL_CTL, val); | |
6535 | ||
6536 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6537 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6538 | DRM_ERROR("Switching to FCLK failed\n"); | |
6539 | ||
6540 | val = I915_READ(LCPLL_CTL); | |
6541 | } | |
6542 | ||
6543 | val |= LCPLL_PLL_DISABLE; | |
6544 | I915_WRITE(LCPLL_CTL, val); | |
6545 | POSTING_READ(LCPLL_CTL); | |
6546 | ||
6547 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6548 | DRM_ERROR("LCPLL still locked\n"); | |
6549 | ||
6550 | val = I915_READ(D_COMP); | |
6551 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6552 | mutex_lock(&dev_priv->rps.hw_lock); |
6553 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6554 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6555 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6556 | POSTING_READ(D_COMP); |
6557 | ndelay(100); | |
6558 | ||
6559 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6560 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6561 | ||
6562 | if (allow_power_down) { | |
6563 | val = I915_READ(LCPLL_CTL); | |
6564 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6565 | I915_WRITE(LCPLL_CTL, val); | |
6566 | POSTING_READ(LCPLL_CTL); | |
6567 | } | |
6568 | } | |
6569 | ||
6570 | /* | |
6571 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6572 | * source. | |
6573 | */ | |
6ff58d53 | 6574 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6575 | { |
6576 | uint32_t val; | |
6577 | ||
6578 | val = I915_READ(LCPLL_CTL); | |
6579 | ||
6580 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6581 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6582 | return; | |
6583 | ||
215733fa PZ |
6584 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6585 | * we'll hang the machine! */ | |
c8d9a590 | 6586 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6587 | |
be256dc7 PZ |
6588 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6589 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6590 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6591 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6592 | } |
6593 | ||
6594 | val = I915_READ(D_COMP); | |
6595 | val |= D_COMP_COMP_FORCE; | |
6596 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6597 | mutex_lock(&dev_priv->rps.hw_lock); |
6598 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6599 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6600 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6601 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6602 | |
6603 | val = I915_READ(LCPLL_CTL); | |
6604 | val &= ~LCPLL_PLL_DISABLE; | |
6605 | I915_WRITE(LCPLL_CTL, val); | |
6606 | ||
6607 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6608 | DRM_ERROR("LCPLL not locked yet\n"); | |
6609 | ||
6610 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6611 | val = I915_READ(LCPLL_CTL); | |
6612 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6613 | I915_WRITE(LCPLL_CTL, val); | |
6614 | ||
6615 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6616 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6617 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6618 | } | |
215733fa | 6619 | |
c8d9a590 | 6620 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6621 | } |
6622 | ||
c67a470b PZ |
6623 | void hsw_enable_pc8_work(struct work_struct *__work) |
6624 | { | |
6625 | struct drm_i915_private *dev_priv = | |
6626 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6627 | pc8.enable_work); | |
6628 | struct drm_device *dev = dev_priv->dev; | |
6629 | uint32_t val; | |
6630 | ||
6631 | if (dev_priv->pc8.enabled) | |
6632 | return; | |
6633 | ||
6634 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6635 | ||
6636 | dev_priv->pc8.enabled = true; | |
6637 | ||
6638 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6639 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6640 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6641 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6642 | } | |
6643 | ||
6644 | lpt_disable_clkout_dp(dev); | |
6645 | hsw_pc8_disable_interrupts(dev); | |
6646 | hsw_disable_lcpll(dev_priv, true, true); | |
6647 | } | |
6648 | ||
6649 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6650 | { | |
6651 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6652 | WARN(dev_priv->pc8.disable_count < 1, | |
6653 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6654 | ||
6655 | dev_priv->pc8.disable_count--; | |
6656 | if (dev_priv->pc8.disable_count != 0) | |
6657 | return; | |
6658 | ||
6659 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
90058745 | 6660 | msecs_to_jiffies(i915_pc8_timeout)); |
c67a470b PZ |
6661 | } |
6662 | ||
6663 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6664 | { | |
6665 | struct drm_device *dev = dev_priv->dev; | |
6666 | uint32_t val; | |
6667 | ||
6668 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6669 | WARN(dev_priv->pc8.disable_count < 0, | |
6670 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6671 | ||
6672 | dev_priv->pc8.disable_count++; | |
6673 | if (dev_priv->pc8.disable_count != 1) | |
6674 | return; | |
6675 | ||
6676 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); | |
6677 | if (!dev_priv->pc8.enabled) | |
6678 | return; | |
6679 | ||
6680 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6681 | ||
6682 | hsw_restore_lcpll(dev_priv); | |
6683 | hsw_pc8_restore_interrupts(dev); | |
6684 | lpt_init_pch_refclk(dev); | |
6685 | ||
6686 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6687 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6688 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6689 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6690 | } | |
6691 | ||
6692 | intel_prepare_ddi(dev); | |
6693 | i915_gem_init_swizzling(dev); | |
6694 | mutex_lock(&dev_priv->rps.hw_lock); | |
6695 | gen6_update_ring_freq(dev); | |
6696 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6697 | dev_priv->pc8.enabled = false; | |
6698 | } | |
6699 | ||
6700 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6701 | { | |
6702 | mutex_lock(&dev_priv->pc8.lock); | |
6703 | __hsw_enable_package_c8(dev_priv); | |
6704 | mutex_unlock(&dev_priv->pc8.lock); | |
6705 | } | |
6706 | ||
6707 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6708 | { | |
6709 | mutex_lock(&dev_priv->pc8.lock); | |
6710 | __hsw_disable_package_c8(dev_priv); | |
6711 | mutex_unlock(&dev_priv->pc8.lock); | |
6712 | } | |
6713 | ||
6714 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6715 | { | |
6716 | struct drm_device *dev = dev_priv->dev; | |
6717 | struct intel_crtc *crtc; | |
6718 | uint32_t val; | |
6719 | ||
6720 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6721 | if (crtc->base.enabled) | |
6722 | return false; | |
6723 | ||
6724 | /* This case is still possible since we have the i915.disable_power_well | |
6725 | * parameter and also the KVMr or something else might be requesting the | |
6726 | * power well. */ | |
6727 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6728 | if (val != 0) { | |
6729 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6730 | return false; | |
6731 | } | |
6732 | ||
6733 | return true; | |
6734 | } | |
6735 | ||
6736 | /* Since we're called from modeset_global_resources there's no way to | |
6737 | * symmetrically increase and decrease the refcount, so we use | |
6738 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6739 | * or not. | |
6740 | */ | |
6741 | static void hsw_update_package_c8(struct drm_device *dev) | |
6742 | { | |
6743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6744 | bool allow; | |
6745 | ||
6746 | if (!i915_enable_pc8) | |
6747 | return; | |
6748 | ||
6749 | mutex_lock(&dev_priv->pc8.lock); | |
6750 | ||
6751 | allow = hsw_can_enable_package_c8(dev_priv); | |
6752 | ||
6753 | if (allow == dev_priv->pc8.requirements_met) | |
6754 | goto done; | |
6755 | ||
6756 | dev_priv->pc8.requirements_met = allow; | |
6757 | ||
6758 | if (allow) | |
6759 | __hsw_enable_package_c8(dev_priv); | |
6760 | else | |
6761 | __hsw_disable_package_c8(dev_priv); | |
6762 | ||
6763 | done: | |
6764 | mutex_unlock(&dev_priv->pc8.lock); | |
6765 | } | |
6766 | ||
6767 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6768 | { | |
3458122e | 6769 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6770 | if (!dev_priv->pc8.gpu_idle) { |
6771 | dev_priv->pc8.gpu_idle = true; | |
3458122e | 6772 | __hsw_enable_package_c8(dev_priv); |
c67a470b | 6773 | } |
3458122e | 6774 | mutex_unlock(&dev_priv->pc8.lock); |
c67a470b PZ |
6775 | } |
6776 | ||
6777 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6778 | { | |
3458122e | 6779 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6780 | if (dev_priv->pc8.gpu_idle) { |
6781 | dev_priv->pc8.gpu_idle = false; | |
3458122e | 6782 | __hsw_disable_package_c8(dev_priv); |
c67a470b | 6783 | } |
3458122e | 6784 | mutex_unlock(&dev_priv->pc8.lock); |
be256dc7 PZ |
6785 | } |
6786 | ||
6efdf354 ID |
6787 | #define for_each_power_domain(domain, mask) \ |
6788 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
6789 | if ((1 << (domain)) & (mask)) | |
6790 | ||
6791 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | |
6792 | enum pipe pipe, bool pfit_enabled) | |
6793 | { | |
6794 | unsigned long mask; | |
6795 | enum transcoder transcoder; | |
6796 | ||
6797 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
6798 | ||
6799 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
6800 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6801 | if (pfit_enabled) | |
6802 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
6803 | ||
6804 | return mask; | |
6805 | } | |
6806 | ||
baa70707 ID |
6807 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
6808 | { | |
6809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6810 | ||
6811 | if (dev_priv->power_domains.init_power_on == enable) | |
6812 | return; | |
6813 | ||
6814 | if (enable) | |
6815 | intel_display_power_get(dev, POWER_DOMAIN_INIT); | |
6816 | else | |
6817 | intel_display_power_put(dev, POWER_DOMAIN_INIT); | |
6818 | ||
6819 | dev_priv->power_domains.init_power_on = enable; | |
6820 | } | |
6821 | ||
4f074129 | 6822 | static void modeset_update_power_wells(struct drm_device *dev) |
d6dd9eb1 | 6823 | { |
6efdf354 | 6824 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
d6dd9eb1 | 6825 | struct intel_crtc *crtc; |
d6dd9eb1 | 6826 | |
6efdf354 ID |
6827 | /* |
6828 | * First get all needed power domains, then put all unneeded, to avoid | |
6829 | * any unnecessary toggling of the power wells. | |
6830 | */ | |
d6dd9eb1 | 6831 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6efdf354 ID |
6832 | enum intel_display_power_domain domain; |
6833 | ||
e7a639c4 DV |
6834 | if (!crtc->base.enabled) |
6835 | continue; | |
d6dd9eb1 | 6836 | |
6efdf354 ID |
6837 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6838 | crtc->pipe, | |
6839 | crtc->config.pch_pfit.enabled); | |
6840 | ||
6841 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
6842 | intel_display_power_get(dev, domain); | |
d6dd9eb1 DV |
6843 | } |
6844 | ||
6efdf354 ID |
6845 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6846 | enum intel_display_power_domain domain; | |
6847 | ||
6848 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
6849 | intel_display_power_put(dev, domain); | |
6850 | ||
6851 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
6852 | } | |
baa70707 ID |
6853 | |
6854 | intel_display_set_init_power(dev, false); | |
4f074129 | 6855 | } |
c67a470b | 6856 | |
4f074129 ID |
6857 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6858 | { | |
6859 | modeset_update_power_wells(dev); | |
c67a470b | 6860 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6861 | } |
6862 | ||
09b4ddf9 | 6863 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6864 | int x, int y, |
6865 | struct drm_framebuffer *fb) | |
6866 | { | |
6867 | struct drm_device *dev = crtc->dev; | |
6868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6869 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6870 | int plane = intel_crtc->plane; |
09b4ddf9 | 6871 | int ret; |
09b4ddf9 | 6872 | |
ff9a6750 | 6873 | if (!intel_ddi_pll_mode_set(crtc)) |
6441ab5f PZ |
6874 | return -EINVAL; |
6875 | ||
03afc4a2 DV |
6876 | if (intel_crtc->config.has_dp_encoder) |
6877 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6878 | |
6879 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6880 | |
8a654f3b | 6881 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6882 | |
ca3a0ff8 | 6883 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6884 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6885 | &intel_crtc->config.fdi_m_n); | |
6886 | } | |
09b4ddf9 | 6887 | |
6ff93609 | 6888 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6889 | |
50f3b016 | 6890 | intel_set_pipe_csc(crtc); |
86d3efce | 6891 | |
09b4ddf9 | 6892 | /* Set up the display plane register */ |
86d3efce | 6893 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6894 | POSTING_READ(DSPCNTR(plane)); |
6895 | ||
6896 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6897 | ||
1f803ee5 | 6898 | return ret; |
79e53945 JB |
6899 | } |
6900 | ||
0e8ffe1b DV |
6901 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6902 | struct intel_crtc_config *pipe_config) | |
6903 | { | |
6904 | struct drm_device *dev = crtc->base.dev; | |
6905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6906 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6907 | uint32_t tmp; |
6908 | ||
e143a21c | 6909 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6910 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6911 | ||
eccb140b DV |
6912 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6913 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6914 | enum pipe trans_edp_pipe; | |
6915 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6916 | default: | |
6917 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6918 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6919 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6920 | trans_edp_pipe = PIPE_A; | |
6921 | break; | |
6922 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
6923 | trans_edp_pipe = PIPE_B; | |
6924 | break; | |
6925 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
6926 | trans_edp_pipe = PIPE_C; | |
6927 | break; | |
6928 | } | |
6929 | ||
6930 | if (trans_edp_pipe == crtc->pipe) | |
6931 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
6932 | } | |
6933 | ||
b97186f0 | 6934 | if (!intel_display_power_enabled(dev, |
eccb140b | 6935 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
6936 | return false; |
6937 | ||
eccb140b | 6938 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
6939 | if (!(tmp & PIPECONF_ENABLE)) |
6940 | return false; | |
6941 | ||
88adfff1 | 6942 | /* |
f196e6be | 6943 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6944 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6945 | * the PCH transcoder is on. | |
6946 | */ | |
eccb140b | 6947 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 6948 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6949 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6950 | pipe_config->has_pch_encoder = true; |
6951 | ||
627eb5a3 DV |
6952 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6953 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6954 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6955 | |
6956 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6957 | } |
6958 | ||
1bd1bd80 DV |
6959 | intel_get_pipe_timings(crtc, pipe_config); |
6960 | ||
2fa2fe9a DV |
6961 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6962 | if (intel_display_power_enabled(dev, pfit_domain)) | |
6963 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 6964 | |
42db64ef PZ |
6965 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6966 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
6967 | ||
6c49f241 DV |
6968 | pipe_config->pixel_multiplier = 1; |
6969 | ||
0e8ffe1b DV |
6970 | return true; |
6971 | } | |
6972 | ||
f564048e | 6973 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6974 | int x, int y, |
94352cf9 | 6975 | struct drm_framebuffer *fb) |
f564048e EA |
6976 | { |
6977 | struct drm_device *dev = crtc->dev; | |
6978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 6979 | struct intel_encoder *encoder; |
0b701d27 | 6980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 6981 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 6982 | int pipe = intel_crtc->pipe; |
f564048e EA |
6983 | int ret; |
6984 | ||
0b701d27 | 6985 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6986 | |
b8cecdf5 DV |
6987 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6988 | ||
79e53945 | 6989 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6990 | |
9256aa19 DV |
6991 | if (ret != 0) |
6992 | return ret; | |
6993 | ||
6994 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6995 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
6996 | encoder->base.base.id, | |
6997 | drm_get_encoder_name(&encoder->base), | |
6998 | mode->base.id, mode->name); | |
36f2d1f1 | 6999 | encoder->mode_set(encoder); |
9256aa19 DV |
7000 | } |
7001 | ||
7002 | return 0; | |
79e53945 JB |
7003 | } |
7004 | ||
1a91510d JN |
7005 | static struct { |
7006 | int clock; | |
7007 | u32 config; | |
7008 | } hdmi_audio_clock[] = { | |
7009 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7010 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7011 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7012 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7013 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7014 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7015 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7016 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7017 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7018 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7019 | }; | |
7020 | ||
7021 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7022 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7023 | { | |
7024 | int i; | |
7025 | ||
7026 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7027 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7028 | break; | |
7029 | } | |
7030 | ||
7031 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7032 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7033 | i = 1; | |
7034 | } | |
7035 | ||
7036 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7037 | hdmi_audio_clock[i].clock, | |
7038 | hdmi_audio_clock[i].config); | |
7039 | ||
7040 | return hdmi_audio_clock[i].config; | |
7041 | } | |
7042 | ||
3a9627f4 WF |
7043 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7044 | int reg_eldv, uint32_t bits_eldv, | |
7045 | int reg_elda, uint32_t bits_elda, | |
7046 | int reg_edid) | |
7047 | { | |
7048 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7049 | uint8_t *eld = connector->eld; | |
7050 | uint32_t i; | |
7051 | ||
7052 | i = I915_READ(reg_eldv); | |
7053 | i &= bits_eldv; | |
7054 | ||
7055 | if (!eld[0]) | |
7056 | return !i; | |
7057 | ||
7058 | if (!i) | |
7059 | return false; | |
7060 | ||
7061 | i = I915_READ(reg_elda); | |
7062 | i &= ~bits_elda; | |
7063 | I915_WRITE(reg_elda, i); | |
7064 | ||
7065 | for (i = 0; i < eld[2]; i++) | |
7066 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7067 | return false; | |
7068 | ||
7069 | return true; | |
7070 | } | |
7071 | ||
e0dac65e | 7072 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7073 | struct drm_crtc *crtc, |
7074 | struct drm_display_mode *mode) | |
e0dac65e WF |
7075 | { |
7076 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7077 | uint8_t *eld = connector->eld; | |
7078 | uint32_t eldv; | |
7079 | uint32_t len; | |
7080 | uint32_t i; | |
7081 | ||
7082 | i = I915_READ(G4X_AUD_VID_DID); | |
7083 | ||
7084 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7085 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7086 | else | |
7087 | eldv = G4X_ELDV_DEVCTG; | |
7088 | ||
3a9627f4 WF |
7089 | if (intel_eld_uptodate(connector, |
7090 | G4X_AUD_CNTL_ST, eldv, | |
7091 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7092 | G4X_HDMIW_HDMIEDID)) | |
7093 | return; | |
7094 | ||
e0dac65e WF |
7095 | i = I915_READ(G4X_AUD_CNTL_ST); |
7096 | i &= ~(eldv | G4X_ELD_ADDR); | |
7097 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7098 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7099 | ||
7100 | if (!eld[0]) | |
7101 | return; | |
7102 | ||
7103 | len = min_t(uint8_t, eld[2], len); | |
7104 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7105 | for (i = 0; i < len; i++) | |
7106 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7107 | ||
7108 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7109 | i |= eldv; | |
7110 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7111 | } | |
7112 | ||
83358c85 | 7113 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7114 | struct drm_crtc *crtc, |
7115 | struct drm_display_mode *mode) | |
83358c85 WX |
7116 | { |
7117 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7118 | uint8_t *eld = connector->eld; | |
7119 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7121 | uint32_t eldv; |
7122 | uint32_t i; | |
7123 | int len; | |
7124 | int pipe = to_intel_crtc(crtc)->pipe; | |
7125 | int tmp; | |
7126 | ||
7127 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7128 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7129 | int aud_config = HSW_AUD_CFG(pipe); | |
7130 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7131 | ||
7132 | ||
7133 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7134 | ||
7135 | /* Audio output enable */ | |
7136 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7137 | tmp = I915_READ(aud_cntrl_st2); | |
7138 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7139 | I915_WRITE(aud_cntrl_st2, tmp); | |
7140 | ||
7141 | /* Wait for 1 vertical blank */ | |
7142 | intel_wait_for_vblank(dev, pipe); | |
7143 | ||
7144 | /* Set ELD valid state */ | |
7145 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7146 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7147 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7148 | I915_WRITE(aud_cntrl_st2, tmp); | |
7149 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7150 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7151 | |
7152 | /* Enable HDMI mode */ | |
7153 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7154 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7155 | /* clear N_programing_enable and N_value_index */ |
7156 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7157 | I915_WRITE(aud_config, tmp); | |
7158 | ||
7159 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7160 | ||
7161 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7162 | intel_crtc->eld_vld = true; |
83358c85 WX |
7163 | |
7164 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7165 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7166 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7167 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7168 | } else { |
7169 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7170 | } | |
83358c85 WX |
7171 | |
7172 | if (intel_eld_uptodate(connector, | |
7173 | aud_cntrl_st2, eldv, | |
7174 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7175 | hdmiw_hdmiedid)) | |
7176 | return; | |
7177 | ||
7178 | i = I915_READ(aud_cntrl_st2); | |
7179 | i &= ~eldv; | |
7180 | I915_WRITE(aud_cntrl_st2, i); | |
7181 | ||
7182 | if (!eld[0]) | |
7183 | return; | |
7184 | ||
7185 | i = I915_READ(aud_cntl_st); | |
7186 | i &= ~IBX_ELD_ADDRESS; | |
7187 | I915_WRITE(aud_cntl_st, i); | |
7188 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7189 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7190 | ||
7191 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7192 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7193 | for (i = 0; i < len; i++) | |
7194 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7195 | ||
7196 | i = I915_READ(aud_cntrl_st2); | |
7197 | i |= eldv; | |
7198 | I915_WRITE(aud_cntrl_st2, i); | |
7199 | ||
7200 | } | |
7201 | ||
e0dac65e | 7202 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7203 | struct drm_crtc *crtc, |
7204 | struct drm_display_mode *mode) | |
e0dac65e WF |
7205 | { |
7206 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7207 | uint8_t *eld = connector->eld; | |
7208 | uint32_t eldv; | |
7209 | uint32_t i; | |
7210 | int len; | |
7211 | int hdmiw_hdmiedid; | |
b6daa025 | 7212 | int aud_config; |
e0dac65e WF |
7213 | int aud_cntl_st; |
7214 | int aud_cntrl_st2; | |
9b138a83 | 7215 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7216 | |
b3f33cbf | 7217 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7218 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7219 | aud_config = IBX_AUD_CFG(pipe); | |
7220 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7221 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7222 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7223 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7224 | aud_config = VLV_AUD_CFG(pipe); | |
7225 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7226 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7227 | } else { |
9b138a83 WX |
7228 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7229 | aud_config = CPT_AUD_CFG(pipe); | |
7230 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7231 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7232 | } |
7233 | ||
9b138a83 | 7234 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7235 | |
9ca2fe73 ML |
7236 | if (IS_VALLEYVIEW(connector->dev)) { |
7237 | struct intel_encoder *intel_encoder; | |
7238 | struct intel_digital_port *intel_dig_port; | |
7239 | ||
7240 | intel_encoder = intel_attached_encoder(connector); | |
7241 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7242 | i = intel_dig_port->port; | |
7243 | } else { | |
7244 | i = I915_READ(aud_cntl_st); | |
7245 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7246 | /* DIP_Port_Select, 0x1 = PortB */ | |
7247 | } | |
7248 | ||
e0dac65e WF |
7249 | if (!i) { |
7250 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7251 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7252 | eldv = IBX_ELD_VALIDB; |
7253 | eldv |= IBX_ELD_VALIDB << 4; | |
7254 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7255 | } else { |
2582a850 | 7256 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7257 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7258 | } |
7259 | ||
3a9627f4 WF |
7260 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7261 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7262 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7263 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7264 | } else { |
7265 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7266 | } | |
e0dac65e | 7267 | |
3a9627f4 WF |
7268 | if (intel_eld_uptodate(connector, |
7269 | aud_cntrl_st2, eldv, | |
7270 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7271 | hdmiw_hdmiedid)) | |
7272 | return; | |
7273 | ||
e0dac65e WF |
7274 | i = I915_READ(aud_cntrl_st2); |
7275 | i &= ~eldv; | |
7276 | I915_WRITE(aud_cntrl_st2, i); | |
7277 | ||
7278 | if (!eld[0]) | |
7279 | return; | |
7280 | ||
e0dac65e | 7281 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7282 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7283 | I915_WRITE(aud_cntl_st, i); |
7284 | ||
7285 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7286 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7287 | for (i = 0; i < len; i++) | |
7288 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7289 | ||
7290 | i = I915_READ(aud_cntrl_st2); | |
7291 | i |= eldv; | |
7292 | I915_WRITE(aud_cntrl_st2, i); | |
7293 | } | |
7294 | ||
7295 | void intel_write_eld(struct drm_encoder *encoder, | |
7296 | struct drm_display_mode *mode) | |
7297 | { | |
7298 | struct drm_crtc *crtc = encoder->crtc; | |
7299 | struct drm_connector *connector; | |
7300 | struct drm_device *dev = encoder->dev; | |
7301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7302 | ||
7303 | connector = drm_select_eld(encoder, mode); | |
7304 | if (!connector) | |
7305 | return; | |
7306 | ||
7307 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7308 | connector->base.id, | |
7309 | drm_get_connector_name(connector), | |
7310 | connector->encoder->base.id, | |
7311 | drm_get_encoder_name(connector->encoder)); | |
7312 | ||
7313 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7314 | ||
7315 | if (dev_priv->display.write_eld) | |
34427052 | 7316 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7317 | } |
7318 | ||
560b85bb CW |
7319 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7320 | { | |
7321 | struct drm_device *dev = crtc->dev; | |
7322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7324 | bool visible = base != 0; | |
7325 | u32 cntl; | |
7326 | ||
7327 | if (intel_crtc->cursor_visible == visible) | |
7328 | return; | |
7329 | ||
9db4a9c7 | 7330 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7331 | if (visible) { |
7332 | /* On these chipsets we can only modify the base whilst | |
7333 | * the cursor is disabled. | |
7334 | */ | |
9db4a9c7 | 7335 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7336 | |
7337 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7338 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7339 | cntl |= CURSOR_ENABLE | | |
7340 | CURSOR_GAMMA_ENABLE | | |
7341 | CURSOR_FORMAT_ARGB; | |
7342 | } else | |
7343 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7344 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7345 | |
7346 | intel_crtc->cursor_visible = visible; | |
7347 | } | |
7348 | ||
7349 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7350 | { | |
7351 | struct drm_device *dev = crtc->dev; | |
7352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7353 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7354 | int pipe = intel_crtc->pipe; | |
7355 | bool visible = base != 0; | |
7356 | ||
7357 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7358 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7359 | if (base) { |
7360 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7361 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7362 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7363 | } else { | |
7364 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7365 | cntl |= CURSOR_MODE_DISABLE; | |
7366 | } | |
9db4a9c7 | 7367 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7368 | |
7369 | intel_crtc->cursor_visible = visible; | |
7370 | } | |
7371 | /* and commit changes on next vblank */ | |
9db4a9c7 | 7372 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
7373 | } |
7374 | ||
65a21cd6 JB |
7375 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7376 | { | |
7377 | struct drm_device *dev = crtc->dev; | |
7378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7379 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7380 | int pipe = intel_crtc->pipe; | |
7381 | bool visible = base != 0; | |
7382 | ||
7383 | if (intel_crtc->cursor_visible != visible) { | |
7384 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7385 | if (base) { | |
7386 | cntl &= ~CURSOR_MODE; | |
7387 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7388 | } else { | |
7389 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7390 | cntl |= CURSOR_MODE_DISABLE; | |
7391 | } | |
6bbfa1c5 | 7392 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7393 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7394 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7395 | } | |
65a21cd6 JB |
7396 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7397 | ||
7398 | intel_crtc->cursor_visible = visible; | |
7399 | } | |
7400 | /* and commit changes on next vblank */ | |
7401 | I915_WRITE(CURBASE_IVB(pipe), base); | |
7402 | } | |
7403 | ||
cda4b7d3 | 7404 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7405 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7406 | bool on) | |
cda4b7d3 CW |
7407 | { |
7408 | struct drm_device *dev = crtc->dev; | |
7409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7411 | int pipe = intel_crtc->pipe; | |
7412 | int x = intel_crtc->cursor_x; | |
7413 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7414 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7415 | bool visible; |
7416 | ||
d6e4db15 | 7417 | if (on) |
cda4b7d3 | 7418 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7419 | |
d6e4db15 VS |
7420 | if (x >= intel_crtc->config.pipe_src_w) |
7421 | base = 0; | |
7422 | ||
7423 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7424 | base = 0; |
7425 | ||
7426 | if (x < 0) { | |
efc9064e | 7427 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7428 | base = 0; |
7429 | ||
7430 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7431 | x = -x; | |
7432 | } | |
7433 | pos |= x << CURSOR_X_SHIFT; | |
7434 | ||
7435 | if (y < 0) { | |
efc9064e | 7436 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7437 | base = 0; |
7438 | ||
7439 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7440 | y = -y; | |
7441 | } | |
7442 | pos |= y << CURSOR_Y_SHIFT; | |
7443 | ||
7444 | visible = base != 0; | |
560b85bb | 7445 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7446 | return; |
7447 | ||
b3dc685e | 7448 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7449 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7450 | ivb_update_cursor(crtc, base); | |
7451 | } else { | |
7452 | I915_WRITE(CURPOS(pipe), pos); | |
7453 | if (IS_845G(dev) || IS_I865G(dev)) | |
7454 | i845_update_cursor(crtc, base); | |
7455 | else | |
7456 | i9xx_update_cursor(crtc, base); | |
7457 | } | |
cda4b7d3 CW |
7458 | } |
7459 | ||
79e53945 | 7460 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7461 | struct drm_file *file, |
79e53945 JB |
7462 | uint32_t handle, |
7463 | uint32_t width, uint32_t height) | |
7464 | { | |
7465 | struct drm_device *dev = crtc->dev; | |
7466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7468 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7469 | uint32_t addr; |
3f8bc370 | 7470 | int ret; |
79e53945 | 7471 | |
79e53945 JB |
7472 | /* if we want to turn off the cursor ignore width and height */ |
7473 | if (!handle) { | |
28c97730 | 7474 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7475 | addr = 0; |
05394f39 | 7476 | obj = NULL; |
5004417d | 7477 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7478 | goto finish; |
79e53945 JB |
7479 | } |
7480 | ||
7481 | /* Currently we only support 64x64 cursors */ | |
7482 | if (width != 64 || height != 64) { | |
7483 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7484 | return -EINVAL; | |
7485 | } | |
7486 | ||
05394f39 | 7487 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7488 | if (&obj->base == NULL) |
79e53945 JB |
7489 | return -ENOENT; |
7490 | ||
05394f39 | 7491 | if (obj->base.size < width * height * 4) { |
79e53945 | 7492 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7493 | ret = -ENOMEM; |
7494 | goto fail; | |
79e53945 JB |
7495 | } |
7496 | ||
71acb5eb | 7497 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7498 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 7499 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
7500 | unsigned alignment; |
7501 | ||
d9e86c0e CW |
7502 | if (obj->tiling_mode) { |
7503 | DRM_ERROR("cursor cannot be tiled\n"); | |
7504 | ret = -EINVAL; | |
7505 | goto fail_locked; | |
7506 | } | |
7507 | ||
693db184 CW |
7508 | /* Note that the w/a also requires 2 PTE of padding following |
7509 | * the bo. We currently fill all unused PTE with the shadow | |
7510 | * page and so we should always have valid PTE following the | |
7511 | * cursor preventing the VT-d warning. | |
7512 | */ | |
7513 | alignment = 0; | |
7514 | if (need_vtd_wa(dev)) | |
7515 | alignment = 64*1024; | |
7516 | ||
7517 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7518 | if (ret) { |
7519 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7520 | goto fail_locked; |
e7b526bb CW |
7521 | } |
7522 | ||
d9e86c0e CW |
7523 | ret = i915_gem_object_put_fence(obj); |
7524 | if (ret) { | |
2da3b9b9 | 7525 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7526 | goto fail_unpin; |
7527 | } | |
7528 | ||
f343c5f6 | 7529 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7530 | } else { |
6eeefaf3 | 7531 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7532 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7533 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7534 | align); | |
71acb5eb DA |
7535 | if (ret) { |
7536 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7537 | goto fail_locked; |
71acb5eb | 7538 | } |
05394f39 | 7539 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7540 | } |
7541 | ||
a6c45cf0 | 7542 | if (IS_GEN2(dev)) |
14b60391 JB |
7543 | I915_WRITE(CURSIZE, (height << 12) | width); |
7544 | ||
3f8bc370 | 7545 | finish: |
3f8bc370 | 7546 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 7547 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 7548 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7549 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7550 | } else | |
cc98b413 | 7551 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7552 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7553 | } |
80824003 | 7554 | |
7f9872e0 | 7555 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7556 | |
7557 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7558 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7559 | intel_crtc->cursor_width = width; |
7560 | intel_crtc->cursor_height = height; | |
7561 | ||
f2f5f771 VS |
7562 | if (intel_crtc->active) |
7563 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7564 | |
79e53945 | 7565 | return 0; |
e7b526bb | 7566 | fail_unpin: |
cc98b413 | 7567 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7568 | fail_locked: |
34b8686e | 7569 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7570 | fail: |
05394f39 | 7571 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7572 | return ret; |
79e53945 JB |
7573 | } |
7574 | ||
7575 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7576 | { | |
79e53945 | 7577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7578 | |
92e76c8c VS |
7579 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7580 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7581 | |
f2f5f771 VS |
7582 | if (intel_crtc->active) |
7583 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7584 | |
7585 | return 0; | |
b8c00ac5 DA |
7586 | } |
7587 | ||
79e53945 | 7588 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7589 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7590 | { |
7203425a | 7591 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7593 | |
7203425a | 7594 | for (i = start; i < end; i++) { |
79e53945 JB |
7595 | intel_crtc->lut_r[i] = red[i] >> 8; |
7596 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7597 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7598 | } | |
7599 | ||
7600 | intel_crtc_load_lut(crtc); | |
7601 | } | |
7602 | ||
79e53945 JB |
7603 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7604 | static struct drm_display_mode load_detect_mode = { | |
7605 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7606 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7607 | }; | |
7608 | ||
d2dff872 CW |
7609 | static struct drm_framebuffer * |
7610 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7611 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7612 | struct drm_i915_gem_object *obj) |
7613 | { | |
7614 | struct intel_framebuffer *intel_fb; | |
7615 | int ret; | |
7616 | ||
7617 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7618 | if (!intel_fb) { | |
7619 | drm_gem_object_unreference_unlocked(&obj->base); | |
7620 | return ERR_PTR(-ENOMEM); | |
7621 | } | |
7622 | ||
dd4916c5 DV |
7623 | ret = i915_mutex_lock_interruptible(dev); |
7624 | if (ret) | |
7625 | goto err; | |
7626 | ||
d2dff872 | 7627 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
dd4916c5 DV |
7628 | mutex_unlock(&dev->struct_mutex); |
7629 | if (ret) | |
7630 | goto err; | |
d2dff872 CW |
7631 | |
7632 | return &intel_fb->base; | |
dd4916c5 DV |
7633 | err: |
7634 | drm_gem_object_unreference_unlocked(&obj->base); | |
7635 | kfree(intel_fb); | |
7636 | ||
7637 | return ERR_PTR(ret); | |
d2dff872 CW |
7638 | } |
7639 | ||
7640 | static u32 | |
7641 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7642 | { | |
7643 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7644 | return ALIGN(pitch, 64); | |
7645 | } | |
7646 | ||
7647 | static u32 | |
7648 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7649 | { | |
7650 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7651 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7652 | } | |
7653 | ||
7654 | static struct drm_framebuffer * | |
7655 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7656 | struct drm_display_mode *mode, | |
7657 | int depth, int bpp) | |
7658 | { | |
7659 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7660 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7661 | |
7662 | obj = i915_gem_alloc_object(dev, | |
7663 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7664 | if (obj == NULL) | |
7665 | return ERR_PTR(-ENOMEM); | |
7666 | ||
7667 | mode_cmd.width = mode->hdisplay; | |
7668 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7669 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7670 | bpp); | |
5ca0c34a | 7671 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7672 | |
7673 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7674 | } | |
7675 | ||
7676 | static struct drm_framebuffer * | |
7677 | mode_fits_in_fbdev(struct drm_device *dev, | |
7678 | struct drm_display_mode *mode) | |
7679 | { | |
4520f53a | 7680 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7681 | struct drm_i915_private *dev_priv = dev->dev_private; |
7682 | struct drm_i915_gem_object *obj; | |
7683 | struct drm_framebuffer *fb; | |
7684 | ||
7685 | if (dev_priv->fbdev == NULL) | |
7686 | return NULL; | |
7687 | ||
7688 | obj = dev_priv->fbdev->ifb.obj; | |
7689 | if (obj == NULL) | |
7690 | return NULL; | |
7691 | ||
7692 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7693 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7694 | fb->bits_per_pixel)) | |
d2dff872 CW |
7695 | return NULL; |
7696 | ||
01f2c773 | 7697 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7698 | return NULL; |
7699 | ||
7700 | return fb; | |
4520f53a DV |
7701 | #else |
7702 | return NULL; | |
7703 | #endif | |
d2dff872 CW |
7704 | } |
7705 | ||
d2434ab7 | 7706 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7707 | struct drm_display_mode *mode, |
8261b191 | 7708 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7709 | { |
7710 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7711 | struct intel_encoder *intel_encoder = |
7712 | intel_attached_encoder(connector); | |
79e53945 | 7713 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7714 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7715 | struct drm_crtc *crtc = NULL; |
7716 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7717 | struct drm_framebuffer *fb; |
79e53945 JB |
7718 | int i = -1; |
7719 | ||
d2dff872 CW |
7720 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7721 | connector->base.id, drm_get_connector_name(connector), | |
7722 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7723 | ||
79e53945 JB |
7724 | /* |
7725 | * Algorithm gets a little messy: | |
7a5e4805 | 7726 | * |
79e53945 JB |
7727 | * - if the connector already has an assigned crtc, use it (but make |
7728 | * sure it's on first) | |
7a5e4805 | 7729 | * |
79e53945 JB |
7730 | * - try to find the first unused crtc that can drive this connector, |
7731 | * and use that if we find one | |
79e53945 JB |
7732 | */ |
7733 | ||
7734 | /* See if we already have a CRTC for this connector */ | |
7735 | if (encoder->crtc) { | |
7736 | crtc = encoder->crtc; | |
8261b191 | 7737 | |
7b24056b DV |
7738 | mutex_lock(&crtc->mutex); |
7739 | ||
24218aac | 7740 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7741 | old->load_detect_temp = false; |
7742 | ||
7743 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7744 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7745 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7746 | |
7173188d | 7747 | return true; |
79e53945 JB |
7748 | } |
7749 | ||
7750 | /* Find an unused one (if possible) */ | |
7751 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7752 | i++; | |
7753 | if (!(encoder->possible_crtcs & (1 << i))) | |
7754 | continue; | |
7755 | if (!possible_crtc->enabled) { | |
7756 | crtc = possible_crtc; | |
7757 | break; | |
7758 | } | |
79e53945 JB |
7759 | } |
7760 | ||
7761 | /* | |
7762 | * If we didn't find an unused CRTC, don't use any. | |
7763 | */ | |
7764 | if (!crtc) { | |
7173188d CW |
7765 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7766 | return false; | |
79e53945 JB |
7767 | } |
7768 | ||
7b24056b | 7769 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7770 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7771 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7772 | |
7773 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 7774 | old->dpms_mode = connector->dpms; |
8261b191 | 7775 | old->load_detect_temp = true; |
d2dff872 | 7776 | old->release_fb = NULL; |
79e53945 | 7777 | |
6492711d CW |
7778 | if (!mode) |
7779 | mode = &load_detect_mode; | |
79e53945 | 7780 | |
d2dff872 CW |
7781 | /* We need a framebuffer large enough to accommodate all accesses |
7782 | * that the plane may generate whilst we perform load detection. | |
7783 | * We can not rely on the fbcon either being present (we get called | |
7784 | * during its initialisation to detect all boot displays, or it may | |
7785 | * not even exist) or that it is large enough to satisfy the | |
7786 | * requested mode. | |
7787 | */ | |
94352cf9 DV |
7788 | fb = mode_fits_in_fbdev(dev, mode); |
7789 | if (fb == NULL) { | |
d2dff872 | 7790 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7791 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7792 | old->release_fb = fb; | |
d2dff872 CW |
7793 | } else |
7794 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7795 | if (IS_ERR(fb)) { |
d2dff872 | 7796 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 7797 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7798 | return false; |
79e53945 | 7799 | } |
79e53945 | 7800 | |
c0c36b94 | 7801 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7802 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7803 | if (old->release_fb) |
7804 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 7805 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7806 | return false; |
79e53945 | 7807 | } |
7173188d | 7808 | |
79e53945 | 7809 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7810 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7811 | return true; |
79e53945 JB |
7812 | } |
7813 | ||
d2434ab7 | 7814 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7815 | struct intel_load_detect_pipe *old) |
79e53945 | 7816 | { |
d2434ab7 DV |
7817 | struct intel_encoder *intel_encoder = |
7818 | intel_attached_encoder(connector); | |
4ef69c7a | 7819 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7820 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 7821 | |
d2dff872 CW |
7822 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7823 | connector->base.id, drm_get_connector_name(connector), | |
7824 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7825 | ||
8261b191 | 7826 | if (old->load_detect_temp) { |
fc303101 DV |
7827 | to_intel_connector(connector)->new_encoder = NULL; |
7828 | intel_encoder->new_crtc = NULL; | |
7829 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 7830 | |
36206361 DV |
7831 | if (old->release_fb) { |
7832 | drm_framebuffer_unregister_private(old->release_fb); | |
7833 | drm_framebuffer_unreference(old->release_fb); | |
7834 | } | |
d2dff872 | 7835 | |
67c96400 | 7836 | mutex_unlock(&crtc->mutex); |
0622a53c | 7837 | return; |
79e53945 JB |
7838 | } |
7839 | ||
c751ce4f | 7840 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7841 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7842 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7843 | |
7844 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7845 | } |
7846 | ||
da4a1efa VS |
7847 | static int i9xx_pll_refclk(struct drm_device *dev, |
7848 | const struct intel_crtc_config *pipe_config) | |
7849 | { | |
7850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7851 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7852 | ||
7853 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
7854 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
7855 | else if (HAS_PCH_SPLIT(dev)) | |
7856 | return 120000; | |
7857 | else if (!IS_GEN2(dev)) | |
7858 | return 96000; | |
7859 | else | |
7860 | return 48000; | |
7861 | } | |
7862 | ||
79e53945 | 7863 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7864 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7865 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7866 | { |
f1f644dc | 7867 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7868 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7869 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7870 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7871 | u32 fp; |
7872 | intel_clock_t clock; | |
da4a1efa | 7873 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7874 | |
7875 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7876 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7877 | else |
293623f7 | 7878 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7879 | |
7880 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7881 | if (IS_PINEVIEW(dev)) { |
7882 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7883 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7884 | } else { |
7885 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7886 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7887 | } | |
7888 | ||
a6c45cf0 | 7889 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7890 | if (IS_PINEVIEW(dev)) |
7891 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7892 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7893 | else |
7894 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7895 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7896 | ||
7897 | switch (dpll & DPLL_MODE_MASK) { | |
7898 | case DPLLB_MODE_DAC_SERIAL: | |
7899 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7900 | 5 : 10; | |
7901 | break; | |
7902 | case DPLLB_MODE_LVDS: | |
7903 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7904 | 7 : 14; | |
7905 | break; | |
7906 | default: | |
28c97730 | 7907 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 7908 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 7909 | return; |
79e53945 JB |
7910 | } |
7911 | ||
ac58c3f0 | 7912 | if (IS_PINEVIEW(dev)) |
da4a1efa | 7913 | pineview_clock(refclk, &clock); |
ac58c3f0 | 7914 | else |
da4a1efa | 7915 | i9xx_clock(refclk, &clock); |
79e53945 JB |
7916 | } else { |
7917 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
7918 | ||
7919 | if (is_lvds) { | |
7920 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7921 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
7922 | clock.p2 = 14; | |
79e53945 JB |
7923 | } else { |
7924 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7925 | clock.p1 = 2; | |
7926 | else { | |
7927 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7928 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7929 | } | |
7930 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7931 | clock.p2 = 4; | |
7932 | else | |
7933 | clock.p2 = 2; | |
79e53945 | 7934 | } |
da4a1efa VS |
7935 | |
7936 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
7937 | } |
7938 | ||
18442d08 VS |
7939 | /* |
7940 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 7941 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
7942 | * encoder's get_config() function. |
7943 | */ | |
7944 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
7945 | } |
7946 | ||
6878da05 VS |
7947 | int intel_dotclock_calculate(int link_freq, |
7948 | const struct intel_link_m_n *m_n) | |
f1f644dc | 7949 | { |
f1f644dc JB |
7950 | /* |
7951 | * The calculation for the data clock is: | |
1041a02f | 7952 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 7953 | * But we want to avoid losing precison if possible, so: |
1041a02f | 7954 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
7955 | * |
7956 | * and the link clock is simpler: | |
1041a02f | 7957 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
7958 | */ |
7959 | ||
6878da05 VS |
7960 | if (!m_n->link_n) |
7961 | return 0; | |
f1f644dc | 7962 | |
6878da05 VS |
7963 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
7964 | } | |
f1f644dc | 7965 | |
18442d08 VS |
7966 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
7967 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
7968 | { |
7969 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 7970 | |
18442d08 VS |
7971 | /* read out port_clock from the DPLL */ |
7972 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 7973 | |
f1f644dc | 7974 | /* |
18442d08 | 7975 | * This value does not include pixel_multiplier. |
241bfc38 | 7976 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
7977 | * agree once we know their relationship in the encoder's |
7978 | * get_config() function. | |
79e53945 | 7979 | */ |
241bfc38 | 7980 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
7981 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
7982 | &pipe_config->fdi_m_n); | |
79e53945 JB |
7983 | } |
7984 | ||
7985 | /** Returns the currently programmed mode of the given pipe. */ | |
7986 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7987 | struct drm_crtc *crtc) | |
7988 | { | |
548f245b | 7989 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 7990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 7991 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 7992 | struct drm_display_mode *mode; |
f1f644dc | 7993 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
7994 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7995 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
7996 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
7997 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 7998 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
7999 | |
8000 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8001 | if (!mode) | |
8002 | return NULL; | |
8003 | ||
f1f644dc JB |
8004 | /* |
8005 | * Construct a pipe_config sufficient for getting the clock info | |
8006 | * back out of crtc_clock_get. | |
8007 | * | |
8008 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8009 | * to use a real value here instead. | |
8010 | */ | |
293623f7 | 8011 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8012 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8013 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8014 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8015 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8016 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8017 | ||
773ae034 | 8018 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8019 | mode->hdisplay = (htot & 0xffff) + 1; |
8020 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8021 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8022 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8023 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8024 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8025 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8026 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8027 | ||
8028 | drm_mode_set_name(mode); | |
79e53945 JB |
8029 | |
8030 | return mode; | |
8031 | } | |
8032 | ||
3dec0095 | 8033 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8034 | { |
8035 | struct drm_device *dev = crtc->dev; | |
8036 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8037 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8038 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8039 | int dpll_reg = DPLL(pipe); |
8040 | int dpll; | |
652c393a | 8041 | |
bad720ff | 8042 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8043 | return; |
8044 | ||
8045 | if (!dev_priv->lvds_downclock_avail) | |
8046 | return; | |
8047 | ||
dbdc6479 | 8048 | dpll = I915_READ(dpll_reg); |
652c393a | 8049 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8050 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8051 | |
8ac5a6d5 | 8052 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8053 | |
8054 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8055 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8056 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8057 | |
652c393a JB |
8058 | dpll = I915_READ(dpll_reg); |
8059 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8060 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8061 | } |
652c393a JB |
8062 | } |
8063 | ||
8064 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8065 | { | |
8066 | struct drm_device *dev = crtc->dev; | |
8067 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8069 | |
bad720ff | 8070 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8071 | return; |
8072 | ||
8073 | if (!dev_priv->lvds_downclock_avail) | |
8074 | return; | |
8075 | ||
8076 | /* | |
8077 | * Since this is called by a timer, we should never get here in | |
8078 | * the manual case. | |
8079 | */ | |
8080 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8081 | int pipe = intel_crtc->pipe; |
8082 | int dpll_reg = DPLL(pipe); | |
8083 | int dpll; | |
f6e5b160 | 8084 | |
44d98a61 | 8085 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8086 | |
8ac5a6d5 | 8087 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8088 | |
dc257cf1 | 8089 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8090 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8091 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8092 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8093 | dpll = I915_READ(dpll_reg); |
8094 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8095 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8096 | } |
8097 | ||
8098 | } | |
8099 | ||
f047e395 CW |
8100 | void intel_mark_busy(struct drm_device *dev) |
8101 | { | |
c67a470b PZ |
8102 | struct drm_i915_private *dev_priv = dev->dev_private; |
8103 | ||
8104 | hsw_package_c8_gpu_busy(dev_priv); | |
8105 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
8106 | } |
8107 | ||
8108 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8109 | { |
c67a470b | 8110 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8111 | struct drm_crtc *crtc; |
652c393a | 8112 | |
c67a470b PZ |
8113 | hsw_package_c8_gpu_idle(dev_priv); |
8114 | ||
652c393a JB |
8115 | if (!i915_powersave) |
8116 | return; | |
8117 | ||
652c393a | 8118 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8119 | if (!crtc->fb) |
8120 | continue; | |
8121 | ||
725a5b54 | 8122 | intel_decrease_pllclock(crtc); |
652c393a | 8123 | } |
b29c19b6 CW |
8124 | |
8125 | if (dev_priv->info->gen >= 6) | |
8126 | gen6_rps_idle(dev->dev_private); | |
652c393a JB |
8127 | } |
8128 | ||
c65355bb CW |
8129 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8130 | struct intel_ring_buffer *ring) | |
652c393a | 8131 | { |
f047e395 CW |
8132 | struct drm_device *dev = obj->base.dev; |
8133 | struct drm_crtc *crtc; | |
652c393a | 8134 | |
f047e395 | 8135 | if (!i915_powersave) |
acb87dfb CW |
8136 | return; |
8137 | ||
652c393a JB |
8138 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8139 | if (!crtc->fb) | |
8140 | continue; | |
8141 | ||
c65355bb CW |
8142 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8143 | continue; | |
8144 | ||
8145 | intel_increase_pllclock(crtc); | |
8146 | if (ring && intel_fbc_enabled(dev)) | |
8147 | ring->fbc_dirty = true; | |
652c393a JB |
8148 | } |
8149 | } | |
8150 | ||
79e53945 JB |
8151 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8152 | { | |
8153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8154 | struct drm_device *dev = crtc->dev; |
8155 | struct intel_unpin_work *work; | |
8156 | unsigned long flags; | |
8157 | ||
8158 | spin_lock_irqsave(&dev->event_lock, flags); | |
8159 | work = intel_crtc->unpin_work; | |
8160 | intel_crtc->unpin_work = NULL; | |
8161 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8162 | ||
8163 | if (work) { | |
8164 | cancel_work_sync(&work->work); | |
8165 | kfree(work); | |
8166 | } | |
79e53945 | 8167 | |
40ccc72b MK |
8168 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8169 | ||
79e53945 | 8170 | drm_crtc_cleanup(crtc); |
67e77c5a | 8171 | |
79e53945 JB |
8172 | kfree(intel_crtc); |
8173 | } | |
8174 | ||
6b95a207 KH |
8175 | static void intel_unpin_work_fn(struct work_struct *__work) |
8176 | { | |
8177 | struct intel_unpin_work *work = | |
8178 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8179 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8180 | |
b4a98e57 | 8181 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8182 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8183 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8184 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8185 | |
b4a98e57 CW |
8186 | intel_update_fbc(dev); |
8187 | mutex_unlock(&dev->struct_mutex); | |
8188 | ||
8189 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8190 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8191 | ||
6b95a207 KH |
8192 | kfree(work); |
8193 | } | |
8194 | ||
1afe3e9d | 8195 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8196 | struct drm_crtc *crtc) |
6b95a207 KH |
8197 | { |
8198 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8200 | struct intel_unpin_work *work; | |
6b95a207 KH |
8201 | unsigned long flags; |
8202 | ||
8203 | /* Ignore early vblank irqs */ | |
8204 | if (intel_crtc == NULL) | |
8205 | return; | |
8206 | ||
8207 | spin_lock_irqsave(&dev->event_lock, flags); | |
8208 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8209 | |
8210 | /* Ensure we don't miss a work->pending update ... */ | |
8211 | smp_rmb(); | |
8212 | ||
8213 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8214 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8215 | return; | |
8216 | } | |
8217 | ||
e7d841ca CW |
8218 | /* and that the unpin work is consistent wrt ->pending. */ |
8219 | smp_rmb(); | |
8220 | ||
6b95a207 | 8221 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8222 | |
45a066eb RC |
8223 | if (work->event) |
8224 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8225 | |
0af7e4df MK |
8226 | drm_vblank_put(dev, intel_crtc->pipe); |
8227 | ||
6b95a207 KH |
8228 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8229 | ||
2c10d571 | 8230 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8231 | |
8232 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8233 | |
8234 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8235 | } |
8236 | ||
1afe3e9d JB |
8237 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8238 | { | |
8239 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8240 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8241 | ||
49b14a5c | 8242 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8243 | } |
8244 | ||
8245 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8246 | { | |
8247 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8248 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8249 | ||
49b14a5c | 8250 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8251 | } |
8252 | ||
6b95a207 KH |
8253 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8254 | { | |
8255 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8256 | struct intel_crtc *intel_crtc = | |
8257 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8258 | unsigned long flags; | |
8259 | ||
e7d841ca CW |
8260 | /* NB: An MMIO update of the plane base pointer will also |
8261 | * generate a page-flip completion irq, i.e. every modeset | |
8262 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8263 | */ | |
6b95a207 | 8264 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8265 | if (intel_crtc->unpin_work) |
8266 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8267 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8268 | } | |
8269 | ||
e7d841ca CW |
8270 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8271 | { | |
8272 | /* Ensure that the work item is consistent when activating it ... */ | |
8273 | smp_wmb(); | |
8274 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8275 | /* and that it is marked active as soon as the irq could fire. */ | |
8276 | smp_wmb(); | |
8277 | } | |
8278 | ||
8c9f3aaf JB |
8279 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8280 | struct drm_crtc *crtc, | |
8281 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8282 | struct drm_i915_gem_object *obj, |
8283 | uint32_t flags) | |
8c9f3aaf JB |
8284 | { |
8285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8287 | u32 flip_mask; |
6d90c952 | 8288 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8289 | int ret; |
8290 | ||
6d90c952 | 8291 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8292 | if (ret) |
83d4092b | 8293 | goto err; |
8c9f3aaf | 8294 | |
6d90c952 | 8295 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8296 | if (ret) |
83d4092b | 8297 | goto err_unpin; |
8c9f3aaf JB |
8298 | |
8299 | /* Can't queue multiple flips, so wait for the previous | |
8300 | * one to finish before executing the next. | |
8301 | */ | |
8302 | if (intel_crtc->plane) | |
8303 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8304 | else | |
8305 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8306 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8307 | intel_ring_emit(ring, MI_NOOP); | |
8308 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8309 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8310 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8311 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8312 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8313 | |
8314 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8315 | __intel_ring_advance(ring); |
83d4092b CW |
8316 | return 0; |
8317 | ||
8318 | err_unpin: | |
8319 | intel_unpin_fb_obj(obj); | |
8320 | err: | |
8c9f3aaf JB |
8321 | return ret; |
8322 | } | |
8323 | ||
8324 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8325 | struct drm_crtc *crtc, | |
8326 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8327 | struct drm_i915_gem_object *obj, |
8328 | uint32_t flags) | |
8c9f3aaf JB |
8329 | { |
8330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8332 | u32 flip_mask; |
6d90c952 | 8333 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8334 | int ret; |
8335 | ||
6d90c952 | 8336 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8337 | if (ret) |
83d4092b | 8338 | goto err; |
8c9f3aaf | 8339 | |
6d90c952 | 8340 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8341 | if (ret) |
83d4092b | 8342 | goto err_unpin; |
8c9f3aaf JB |
8343 | |
8344 | if (intel_crtc->plane) | |
8345 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8346 | else | |
8347 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8348 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8349 | intel_ring_emit(ring, MI_NOOP); | |
8350 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8351 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8352 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8353 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8354 | intel_ring_emit(ring, MI_NOOP); |
8355 | ||
e7d841ca | 8356 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8357 | __intel_ring_advance(ring); |
83d4092b CW |
8358 | return 0; |
8359 | ||
8360 | err_unpin: | |
8361 | intel_unpin_fb_obj(obj); | |
8362 | err: | |
8c9f3aaf JB |
8363 | return ret; |
8364 | } | |
8365 | ||
8366 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8367 | struct drm_crtc *crtc, | |
8368 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8369 | struct drm_i915_gem_object *obj, |
8370 | uint32_t flags) | |
8c9f3aaf JB |
8371 | { |
8372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8374 | uint32_t pf, pipesrc; | |
6d90c952 | 8375 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8376 | int ret; |
8377 | ||
6d90c952 | 8378 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8379 | if (ret) |
83d4092b | 8380 | goto err; |
8c9f3aaf | 8381 | |
6d90c952 | 8382 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8383 | if (ret) |
83d4092b | 8384 | goto err_unpin; |
8c9f3aaf JB |
8385 | |
8386 | /* i965+ uses the linear or tiled offsets from the | |
8387 | * Display Registers (which do not change across a page-flip) | |
8388 | * so we need only reprogram the base address. | |
8389 | */ | |
6d90c952 DV |
8390 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8391 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8392 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8393 | intel_ring_emit(ring, |
f343c5f6 | 8394 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8395 | obj->tiling_mode); |
8c9f3aaf JB |
8396 | |
8397 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8398 | * untested on non-native modes, so ignore it for now. | |
8399 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8400 | */ | |
8401 | pf = 0; | |
8402 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8403 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8404 | |
8405 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8406 | __intel_ring_advance(ring); |
83d4092b CW |
8407 | return 0; |
8408 | ||
8409 | err_unpin: | |
8410 | intel_unpin_fb_obj(obj); | |
8411 | err: | |
8c9f3aaf JB |
8412 | return ret; |
8413 | } | |
8414 | ||
8415 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8416 | struct drm_crtc *crtc, | |
8417 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8418 | struct drm_i915_gem_object *obj, |
8419 | uint32_t flags) | |
8c9f3aaf JB |
8420 | { |
8421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8423 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8424 | uint32_t pf, pipesrc; |
8425 | int ret; | |
8426 | ||
6d90c952 | 8427 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8428 | if (ret) |
83d4092b | 8429 | goto err; |
8c9f3aaf | 8430 | |
6d90c952 | 8431 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8432 | if (ret) |
83d4092b | 8433 | goto err_unpin; |
8c9f3aaf | 8434 | |
6d90c952 DV |
8435 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8436 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8437 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8438 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8439 | |
dc257cf1 DV |
8440 | /* Contrary to the suggestions in the documentation, |
8441 | * "Enable Panel Fitter" does not seem to be required when page | |
8442 | * flipping with a non-native mode, and worse causes a normal | |
8443 | * modeset to fail. | |
8444 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8445 | */ | |
8446 | pf = 0; | |
8c9f3aaf | 8447 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8448 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8449 | |
8450 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8451 | __intel_ring_advance(ring); |
83d4092b CW |
8452 | return 0; |
8453 | ||
8454 | err_unpin: | |
8455 | intel_unpin_fb_obj(obj); | |
8456 | err: | |
8c9f3aaf JB |
8457 | return ret; |
8458 | } | |
8459 | ||
7c9017e5 JB |
8460 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8461 | struct drm_crtc *crtc, | |
8462 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8463 | struct drm_i915_gem_object *obj, |
8464 | uint32_t flags) | |
7c9017e5 JB |
8465 | { |
8466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8468 | struct intel_ring_buffer *ring; |
cb05d8de | 8469 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8470 | int len, ret; |
8471 | ||
8472 | ring = obj->ring; | |
1c5fd085 | 8473 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8474 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8475 | |
8476 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8477 | if (ret) | |
83d4092b | 8478 | goto err; |
7c9017e5 | 8479 | |
cb05d8de DV |
8480 | switch(intel_crtc->plane) { |
8481 | case PLANE_A: | |
8482 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8483 | break; | |
8484 | case PLANE_B: | |
8485 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8486 | break; | |
8487 | case PLANE_C: | |
8488 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8489 | break; | |
8490 | default: | |
8491 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8492 | ret = -ENODEV; | |
ab3951eb | 8493 | goto err_unpin; |
cb05d8de DV |
8494 | } |
8495 | ||
ffe74d75 CW |
8496 | len = 4; |
8497 | if (ring->id == RCS) | |
8498 | len += 6; | |
8499 | ||
8500 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8501 | if (ret) |
83d4092b | 8502 | goto err_unpin; |
7c9017e5 | 8503 | |
ffe74d75 CW |
8504 | /* Unmask the flip-done completion message. Note that the bspec says that |
8505 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8506 | * more than one flip event at any time (or ensure that one flip message | |
8507 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8508 | * Experimentation says that BCS works despite DERRMR masking all | |
8509 | * flip-done completion events and that unmasking all planes at once | |
8510 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8511 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8512 | */ | |
8513 | if (ring->id == RCS) { | |
8514 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8515 | intel_ring_emit(ring, DERRMR); | |
8516 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8517 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8518 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
8519 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | |
8520 | intel_ring_emit(ring, DERRMR); | |
8521 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8522 | } | |
8523 | ||
cb05d8de | 8524 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8525 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8526 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8527 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8528 | |
8529 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8530 | __intel_ring_advance(ring); |
83d4092b CW |
8531 | return 0; |
8532 | ||
8533 | err_unpin: | |
8534 | intel_unpin_fb_obj(obj); | |
8535 | err: | |
7c9017e5 JB |
8536 | return ret; |
8537 | } | |
8538 | ||
8c9f3aaf JB |
8539 | static int intel_default_queue_flip(struct drm_device *dev, |
8540 | struct drm_crtc *crtc, | |
8541 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8542 | struct drm_i915_gem_object *obj, |
8543 | uint32_t flags) | |
8c9f3aaf JB |
8544 | { |
8545 | return -ENODEV; | |
8546 | } | |
8547 | ||
6b95a207 KH |
8548 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8549 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8550 | struct drm_pending_vblank_event *event, |
8551 | uint32_t page_flip_flags) | |
6b95a207 KH |
8552 | { |
8553 | struct drm_device *dev = crtc->dev; | |
8554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8555 | struct drm_framebuffer *old_fb = crtc->fb; |
8556 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8558 | struct intel_unpin_work *work; | |
8c9f3aaf | 8559 | unsigned long flags; |
52e68630 | 8560 | int ret; |
6b95a207 | 8561 | |
e6a595d2 VS |
8562 | /* Can't change pixel format via MI display flips. */ |
8563 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8564 | return -EINVAL; | |
8565 | ||
8566 | /* | |
8567 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8568 | * Note that pitch changes could also affect these register. | |
8569 | */ | |
8570 | if (INTEL_INFO(dev)->gen > 3 && | |
8571 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8572 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8573 | return -EINVAL; | |
8574 | ||
b14c5679 | 8575 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8576 | if (work == NULL) |
8577 | return -ENOMEM; | |
8578 | ||
6b95a207 | 8579 | work->event = event; |
b4a98e57 | 8580 | work->crtc = crtc; |
4a35f83b | 8581 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8582 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8583 | ||
7317c75e JB |
8584 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8585 | if (ret) | |
8586 | goto free_work; | |
8587 | ||
6b95a207 KH |
8588 | /* We borrow the event spin lock for protecting unpin_work */ |
8589 | spin_lock_irqsave(&dev->event_lock, flags); | |
8590 | if (intel_crtc->unpin_work) { | |
8591 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8592 | kfree(work); | |
7317c75e | 8593 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8594 | |
8595 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8596 | return -EBUSY; |
8597 | } | |
8598 | intel_crtc->unpin_work = work; | |
8599 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8600 | ||
b4a98e57 CW |
8601 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8602 | flush_workqueue(dev_priv->wq); | |
8603 | ||
79158103 CW |
8604 | ret = i915_mutex_lock_interruptible(dev); |
8605 | if (ret) | |
8606 | goto cleanup; | |
6b95a207 | 8607 | |
75dfca80 | 8608 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8609 | drm_gem_object_reference(&work->old_fb_obj->base); |
8610 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8611 | |
8612 | crtc->fb = fb; | |
96b099fd | 8613 | |
e1f99ce6 | 8614 | work->pending_flip_obj = obj; |
e1f99ce6 | 8615 | |
4e5359cd SF |
8616 | work->enable_stall_check = true; |
8617 | ||
b4a98e57 | 8618 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8619 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8620 | |
ed8d1975 | 8621 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8622 | if (ret) |
8623 | goto cleanup_pending; | |
6b95a207 | 8624 | |
7782de3b | 8625 | intel_disable_fbc(dev); |
c65355bb | 8626 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8627 | mutex_unlock(&dev->struct_mutex); |
8628 | ||
e5510fac JB |
8629 | trace_i915_flip_request(intel_crtc->plane, obj); |
8630 | ||
6b95a207 | 8631 | return 0; |
96b099fd | 8632 | |
8c9f3aaf | 8633 | cleanup_pending: |
b4a98e57 | 8634 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8635 | crtc->fb = old_fb; |
05394f39 CW |
8636 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8637 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8638 | mutex_unlock(&dev->struct_mutex); |
8639 | ||
79158103 | 8640 | cleanup: |
96b099fd CW |
8641 | spin_lock_irqsave(&dev->event_lock, flags); |
8642 | intel_crtc->unpin_work = NULL; | |
8643 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8644 | ||
7317c75e JB |
8645 | drm_vblank_put(dev, intel_crtc->pipe); |
8646 | free_work: | |
96b099fd CW |
8647 | kfree(work); |
8648 | ||
8649 | return ret; | |
6b95a207 KH |
8650 | } |
8651 | ||
f6e5b160 | 8652 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8653 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8654 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8655 | }; |
8656 | ||
50f56119 DV |
8657 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8658 | struct drm_crtc *crtc) | |
8659 | { | |
8660 | struct drm_device *dev; | |
8661 | struct drm_crtc *tmp; | |
8662 | int crtc_mask = 1; | |
47f1c6c9 | 8663 | |
50f56119 | 8664 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 8665 | |
50f56119 | 8666 | dev = crtc->dev; |
47f1c6c9 | 8667 | |
50f56119 DV |
8668 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8669 | if (tmp == crtc) | |
8670 | break; | |
8671 | crtc_mask <<= 1; | |
8672 | } | |
47f1c6c9 | 8673 | |
50f56119 DV |
8674 | if (encoder->possible_crtcs & crtc_mask) |
8675 | return true; | |
8676 | return false; | |
47f1c6c9 | 8677 | } |
79e53945 | 8678 | |
9a935856 DV |
8679 | /** |
8680 | * intel_modeset_update_staged_output_state | |
8681 | * | |
8682 | * Updates the staged output configuration state, e.g. after we've read out the | |
8683 | * current hw state. | |
8684 | */ | |
8685 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8686 | { |
9a935856 DV |
8687 | struct intel_encoder *encoder; |
8688 | struct intel_connector *connector; | |
f6e5b160 | 8689 | |
9a935856 DV |
8690 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8691 | base.head) { | |
8692 | connector->new_encoder = | |
8693 | to_intel_encoder(connector->base.encoder); | |
8694 | } | |
f6e5b160 | 8695 | |
9a935856 DV |
8696 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8697 | base.head) { | |
8698 | encoder->new_crtc = | |
8699 | to_intel_crtc(encoder->base.crtc); | |
8700 | } | |
f6e5b160 CW |
8701 | } |
8702 | ||
9a935856 DV |
8703 | /** |
8704 | * intel_modeset_commit_output_state | |
8705 | * | |
8706 | * This function copies the stage display pipe configuration to the real one. | |
8707 | */ | |
8708 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8709 | { | |
8710 | struct intel_encoder *encoder; | |
8711 | struct intel_connector *connector; | |
f6e5b160 | 8712 | |
9a935856 DV |
8713 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8714 | base.head) { | |
8715 | connector->base.encoder = &connector->new_encoder->base; | |
8716 | } | |
f6e5b160 | 8717 | |
9a935856 DV |
8718 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8719 | base.head) { | |
8720 | encoder->base.crtc = &encoder->new_crtc->base; | |
8721 | } | |
8722 | } | |
8723 | ||
050f7aeb DV |
8724 | static void |
8725 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8726 | struct intel_crtc_config *pipe_config) | |
8727 | { | |
8728 | int bpp = pipe_config->pipe_bpp; | |
8729 | ||
8730 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8731 | connector->base.base.id, | |
8732 | drm_get_connector_name(&connector->base)); | |
8733 | ||
8734 | /* Don't use an invalid EDID bpc value */ | |
8735 | if (connector->base.display_info.bpc && | |
8736 | connector->base.display_info.bpc * 3 < bpp) { | |
8737 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8738 | bpp, connector->base.display_info.bpc*3); | |
8739 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8740 | } | |
8741 | ||
8742 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8743 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8744 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8745 | bpp); | |
8746 | pipe_config->pipe_bpp = 24; | |
8747 | } | |
8748 | } | |
8749 | ||
4e53c2e0 | 8750 | static int |
050f7aeb DV |
8751 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8752 | struct drm_framebuffer *fb, | |
8753 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8754 | { |
050f7aeb DV |
8755 | struct drm_device *dev = crtc->base.dev; |
8756 | struct intel_connector *connector; | |
4e53c2e0 DV |
8757 | int bpp; |
8758 | ||
d42264b1 DV |
8759 | switch (fb->pixel_format) { |
8760 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8761 | bpp = 8*3; /* since we go through a colormap */ |
8762 | break; | |
d42264b1 DV |
8763 | case DRM_FORMAT_XRGB1555: |
8764 | case DRM_FORMAT_ARGB1555: | |
8765 | /* checked in intel_framebuffer_init already */ | |
8766 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8767 | return -EINVAL; | |
8768 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8769 | bpp = 6*3; /* min is 18bpp */ |
8770 | break; | |
d42264b1 DV |
8771 | case DRM_FORMAT_XBGR8888: |
8772 | case DRM_FORMAT_ABGR8888: | |
8773 | /* checked in intel_framebuffer_init already */ | |
8774 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8775 | return -EINVAL; | |
8776 | case DRM_FORMAT_XRGB8888: | |
8777 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8778 | bpp = 8*3; |
8779 | break; | |
d42264b1 DV |
8780 | case DRM_FORMAT_XRGB2101010: |
8781 | case DRM_FORMAT_ARGB2101010: | |
8782 | case DRM_FORMAT_XBGR2101010: | |
8783 | case DRM_FORMAT_ABGR2101010: | |
8784 | /* checked in intel_framebuffer_init already */ | |
8785 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8786 | return -EINVAL; |
4e53c2e0 DV |
8787 | bpp = 10*3; |
8788 | break; | |
baba133a | 8789 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8790 | default: |
8791 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8792 | return -EINVAL; | |
8793 | } | |
8794 | ||
4e53c2e0 DV |
8795 | pipe_config->pipe_bpp = bpp; |
8796 | ||
8797 | /* Clamp display bpp to EDID value */ | |
8798 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8799 | base.head) { |
1b829e05 DV |
8800 | if (!connector->new_encoder || |
8801 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8802 | continue; |
8803 | ||
050f7aeb | 8804 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8805 | } |
8806 | ||
8807 | return bpp; | |
8808 | } | |
8809 | ||
644db711 DV |
8810 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8811 | { | |
8812 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8813 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8814 | mode->crtc_clock, |
644db711 DV |
8815 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8816 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8817 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8818 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8819 | } | |
8820 | ||
c0b03411 DV |
8821 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8822 | struct intel_crtc_config *pipe_config, | |
8823 | const char *context) | |
8824 | { | |
8825 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8826 | context, pipe_name(crtc->pipe)); | |
8827 | ||
8828 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8829 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8830 | pipe_config->pipe_bpp, pipe_config->dither); | |
8831 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8832 | pipe_config->has_pch_encoder, | |
8833 | pipe_config->fdi_lanes, | |
8834 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8835 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8836 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8837 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8838 | pipe_config->has_dp_encoder, | |
8839 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8840 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8841 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8842 | DRM_DEBUG_KMS("requested mode:\n"); |
8843 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8844 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8845 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8846 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8847 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8848 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8849 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8850 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8851 | pipe_config->gmch_pfit.control, | |
8852 | pipe_config->gmch_pfit.pgm_ratios, | |
8853 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8854 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8855 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8856 | pipe_config->pch_pfit.size, |
8857 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8858 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8859 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8860 | } |
8861 | ||
accfc0c5 DV |
8862 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8863 | { | |
8864 | int num_encoders = 0; | |
8865 | bool uncloneable_encoders = false; | |
8866 | struct intel_encoder *encoder; | |
8867 | ||
8868 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8869 | base.head) { | |
8870 | if (&encoder->new_crtc->base != crtc) | |
8871 | continue; | |
8872 | ||
8873 | num_encoders++; | |
8874 | if (!encoder->cloneable) | |
8875 | uncloneable_encoders = true; | |
8876 | } | |
8877 | ||
8878 | return !(num_encoders > 1 && uncloneable_encoders); | |
8879 | } | |
8880 | ||
b8cecdf5 DV |
8881 | static struct intel_crtc_config * |
8882 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8883 | struct drm_framebuffer *fb, |
b8cecdf5 | 8884 | struct drm_display_mode *mode) |
ee7b9f93 | 8885 | { |
7758a113 | 8886 | struct drm_device *dev = crtc->dev; |
7758a113 | 8887 | struct intel_encoder *encoder; |
b8cecdf5 | 8888 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8889 | int plane_bpp, ret = -EINVAL; |
8890 | bool retry = true; | |
ee7b9f93 | 8891 | |
accfc0c5 DV |
8892 | if (!check_encoder_cloning(crtc)) { |
8893 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8894 | return ERR_PTR(-EINVAL); | |
8895 | } | |
8896 | ||
b8cecdf5 DV |
8897 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8898 | if (!pipe_config) | |
7758a113 DV |
8899 | return ERR_PTR(-ENOMEM); |
8900 | ||
b8cecdf5 DV |
8901 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8902 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 8903 | |
e143a21c DV |
8904 | pipe_config->cpu_transcoder = |
8905 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 8906 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 8907 | |
2960bc9c ID |
8908 | /* |
8909 | * Sanitize sync polarity flags based on requested ones. If neither | |
8910 | * positive or negative polarity is requested, treat this as meaning | |
8911 | * negative polarity. | |
8912 | */ | |
8913 | if (!(pipe_config->adjusted_mode.flags & | |
8914 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
8915 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
8916 | ||
8917 | if (!(pipe_config->adjusted_mode.flags & | |
8918 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
8919 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
8920 | ||
050f7aeb DV |
8921 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8922 | * plane pixel format and any sink constraints into account. Returns the | |
8923 | * source plane bpp so that dithering can be selected on mismatches | |
8924 | * after encoders and crtc also have had their say. */ | |
8925 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
8926 | fb, pipe_config); | |
4e53c2e0 DV |
8927 | if (plane_bpp < 0) |
8928 | goto fail; | |
8929 | ||
e41a56be VS |
8930 | /* |
8931 | * Determine the real pipe dimensions. Note that stereo modes can | |
8932 | * increase the actual pipe size due to the frame doubling and | |
8933 | * insertion of additional space for blanks between the frame. This | |
8934 | * is stored in the crtc timings. We use the requested mode to do this | |
8935 | * computation to clearly distinguish it from the adjusted mode, which | |
8936 | * can be changed by the connectors in the below retry loop. | |
8937 | */ | |
8938 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
8939 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
8940 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
8941 | ||
e29c22c0 | 8942 | encoder_retry: |
ef1b460d | 8943 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 8944 | pipe_config->port_clock = 0; |
ef1b460d | 8945 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 8946 | |
135c81b8 | 8947 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 8948 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 8949 | |
7758a113 DV |
8950 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8951 | * adjust it according to limitations or connector properties, and also | |
8952 | * a chance to reject the mode entirely. | |
47f1c6c9 | 8953 | */ |
7758a113 DV |
8954 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8955 | base.head) { | |
47f1c6c9 | 8956 | |
7758a113 DV |
8957 | if (&encoder->new_crtc->base != crtc) |
8958 | continue; | |
7ae89233 | 8959 | |
efea6e8e DV |
8960 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8961 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
8962 | goto fail; |
8963 | } | |
ee7b9f93 | 8964 | } |
47f1c6c9 | 8965 | |
ff9a6750 DV |
8966 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8967 | * done afterwards in case the encoder adjusts the mode. */ | |
8968 | if (!pipe_config->port_clock) | |
241bfc38 DL |
8969 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
8970 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 8971 | |
a43f6e0f | 8972 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 8973 | if (ret < 0) { |
7758a113 DV |
8974 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8975 | goto fail; | |
ee7b9f93 | 8976 | } |
e29c22c0 DV |
8977 | |
8978 | if (ret == RETRY) { | |
8979 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
8980 | ret = -EINVAL; | |
8981 | goto fail; | |
8982 | } | |
8983 | ||
8984 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
8985 | retry = false; | |
8986 | goto encoder_retry; | |
8987 | } | |
8988 | ||
4e53c2e0 DV |
8989 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8990 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
8991 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
8992 | ||
b8cecdf5 | 8993 | return pipe_config; |
7758a113 | 8994 | fail: |
b8cecdf5 | 8995 | kfree(pipe_config); |
e29c22c0 | 8996 | return ERR_PTR(ret); |
ee7b9f93 | 8997 | } |
47f1c6c9 | 8998 | |
e2e1ed41 DV |
8999 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9000 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9001 | static void | |
9002 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9003 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9004 | { |
9005 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9006 | struct drm_device *dev = crtc->dev; |
9007 | struct intel_encoder *encoder; | |
9008 | struct intel_connector *connector; | |
9009 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9010 | |
e2e1ed41 | 9011 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9012 | |
e2e1ed41 DV |
9013 | /* Check which crtcs have changed outputs connected to them, these need |
9014 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9015 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9016 | * bit set at most. */ | |
9017 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9018 | base.head) { | |
9019 | if (connector->base.encoder == &connector->new_encoder->base) | |
9020 | continue; | |
79e53945 | 9021 | |
e2e1ed41 DV |
9022 | if (connector->base.encoder) { |
9023 | tmp_crtc = connector->base.encoder->crtc; | |
9024 | ||
9025 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9026 | } | |
9027 | ||
9028 | if (connector->new_encoder) | |
9029 | *prepare_pipes |= | |
9030 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9031 | } |
9032 | ||
e2e1ed41 DV |
9033 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9034 | base.head) { | |
9035 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9036 | continue; | |
9037 | ||
9038 | if (encoder->base.crtc) { | |
9039 | tmp_crtc = encoder->base.crtc; | |
9040 | ||
9041 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9042 | } | |
9043 | ||
9044 | if (encoder->new_crtc) | |
9045 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9046 | } |
9047 | ||
e2e1ed41 DV |
9048 | /* Check for any pipes that will be fully disabled ... */ |
9049 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
9050 | base.head) { | |
9051 | bool used = false; | |
22fd0fab | 9052 | |
e2e1ed41 DV |
9053 | /* Don't try to disable disabled crtcs. */ |
9054 | if (!intel_crtc->base.enabled) | |
9055 | continue; | |
7e7d76c3 | 9056 | |
e2e1ed41 DV |
9057 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9058 | base.head) { | |
9059 | if (encoder->new_crtc == intel_crtc) | |
9060 | used = true; | |
9061 | } | |
9062 | ||
9063 | if (!used) | |
9064 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9065 | } |
9066 | ||
e2e1ed41 DV |
9067 | |
9068 | /* set_mode is also used to update properties on life display pipes. */ | |
9069 | intel_crtc = to_intel_crtc(crtc); | |
9070 | if (crtc->enabled) | |
9071 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
9072 | ||
b6c5164d DV |
9073 | /* |
9074 | * For simplicity do a full modeset on any pipe where the output routing | |
9075 | * changed. We could be more clever, but that would require us to be | |
9076 | * more careful with calling the relevant encoder->mode_set functions. | |
9077 | */ | |
e2e1ed41 DV |
9078 | if (*prepare_pipes) |
9079 | *modeset_pipes = *prepare_pipes; | |
9080 | ||
9081 | /* ... and mask these out. */ | |
9082 | *modeset_pipes &= ~(*disable_pipes); | |
9083 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9084 | |
9085 | /* | |
9086 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9087 | * obies this rule, but the modeset restore mode of | |
9088 | * intel_modeset_setup_hw_state does not. | |
9089 | */ | |
9090 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9091 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9092 | |
9093 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9094 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9095 | } |
79e53945 | 9096 | |
ea9d758d | 9097 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9098 | { |
ea9d758d | 9099 | struct drm_encoder *encoder; |
f6e5b160 | 9100 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9101 | |
ea9d758d DV |
9102 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9103 | if (encoder->crtc == crtc) | |
9104 | return true; | |
9105 | ||
9106 | return false; | |
9107 | } | |
9108 | ||
9109 | static void | |
9110 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9111 | { | |
9112 | struct intel_encoder *intel_encoder; | |
9113 | struct intel_crtc *intel_crtc; | |
9114 | struct drm_connector *connector; | |
9115 | ||
9116 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9117 | base.head) { | |
9118 | if (!intel_encoder->base.crtc) | |
9119 | continue; | |
9120 | ||
9121 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9122 | ||
9123 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9124 | intel_encoder->connectors_active = false; | |
9125 | } | |
9126 | ||
9127 | intel_modeset_commit_output_state(dev); | |
9128 | ||
9129 | /* Update computed state. */ | |
9130 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
9131 | base.head) { | |
9132 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
9133 | } | |
9134 | ||
9135 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9136 | if (!connector->encoder || !connector->encoder->crtc) | |
9137 | continue; | |
9138 | ||
9139 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9140 | ||
9141 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9142 | struct drm_property *dpms_property = |
9143 | dev->mode_config.dpms_property; | |
9144 | ||
ea9d758d | 9145 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9146 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9147 | dpms_property, |
9148 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9149 | |
9150 | intel_encoder = to_intel_encoder(connector->encoder); | |
9151 | intel_encoder->connectors_active = true; | |
9152 | } | |
9153 | } | |
9154 | ||
9155 | } | |
9156 | ||
3bd26263 | 9157 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9158 | { |
3bd26263 | 9159 | int diff; |
f1f644dc JB |
9160 | |
9161 | if (clock1 == clock2) | |
9162 | return true; | |
9163 | ||
9164 | if (!clock1 || !clock2) | |
9165 | return false; | |
9166 | ||
9167 | diff = abs(clock1 - clock2); | |
9168 | ||
9169 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9170 | return true; | |
9171 | ||
9172 | return false; | |
9173 | } | |
9174 | ||
25c5b266 DV |
9175 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9176 | list_for_each_entry((intel_crtc), \ | |
9177 | &(dev)->mode_config.crtc_list, \ | |
9178 | base.head) \ | |
0973f18f | 9179 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9180 | |
0e8ffe1b | 9181 | static bool |
2fa2fe9a DV |
9182 | intel_pipe_config_compare(struct drm_device *dev, |
9183 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9184 | struct intel_crtc_config *pipe_config) |
9185 | { | |
66e985c0 DV |
9186 | #define PIPE_CONF_CHECK_X(name) \ |
9187 | if (current_config->name != pipe_config->name) { \ | |
9188 | DRM_ERROR("mismatch in " #name " " \ | |
9189 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9190 | current_config->name, \ | |
9191 | pipe_config->name); \ | |
9192 | return false; \ | |
9193 | } | |
9194 | ||
08a24034 DV |
9195 | #define PIPE_CONF_CHECK_I(name) \ |
9196 | if (current_config->name != pipe_config->name) { \ | |
9197 | DRM_ERROR("mismatch in " #name " " \ | |
9198 | "(expected %i, found %i)\n", \ | |
9199 | current_config->name, \ | |
9200 | pipe_config->name); \ | |
9201 | return false; \ | |
88adfff1 DV |
9202 | } |
9203 | ||
1bd1bd80 DV |
9204 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9205 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9206 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9207 | "(expected %i, found %i)\n", \ |
9208 | current_config->name & (mask), \ | |
9209 | pipe_config->name & (mask)); \ | |
9210 | return false; \ | |
9211 | } | |
9212 | ||
5e550656 VS |
9213 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9214 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9215 | DRM_ERROR("mismatch in " #name " " \ | |
9216 | "(expected %i, found %i)\n", \ | |
9217 | current_config->name, \ | |
9218 | pipe_config->name); \ | |
9219 | return false; \ | |
9220 | } | |
9221 | ||
bb760063 DV |
9222 | #define PIPE_CONF_QUIRK(quirk) \ |
9223 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9224 | ||
eccb140b DV |
9225 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9226 | ||
08a24034 DV |
9227 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9228 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9229 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9230 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9231 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9232 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9233 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9234 | |
eb14cb74 VS |
9235 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9236 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9237 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9238 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9239 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9240 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9241 | ||
1bd1bd80 DV |
9242 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9243 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9244 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9245 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9246 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9247 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9248 | ||
9249 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9250 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9251 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9252 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9253 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9254 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9255 | ||
c93f54cf | 9256 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9257 | |
1bd1bd80 DV |
9258 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9259 | DRM_MODE_FLAG_INTERLACE); | |
9260 | ||
bb760063 DV |
9261 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9262 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9263 | DRM_MODE_FLAG_PHSYNC); | |
9264 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9265 | DRM_MODE_FLAG_NHSYNC); | |
9266 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9267 | DRM_MODE_FLAG_PVSYNC); | |
9268 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9269 | DRM_MODE_FLAG_NVSYNC); | |
9270 | } | |
045ac3b5 | 9271 | |
37327abd VS |
9272 | PIPE_CONF_CHECK_I(pipe_src_w); |
9273 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9274 | |
2fa2fe9a DV |
9275 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9276 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9277 | if (INTEL_INFO(dev)->gen < 4) | |
9278 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9279 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9280 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9281 | if (current_config->pch_pfit.enabled) { | |
9282 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9283 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9284 | } | |
2fa2fe9a | 9285 | |
42db64ef PZ |
9286 | PIPE_CONF_CHECK_I(ips_enabled); |
9287 | ||
282740f7 VS |
9288 | PIPE_CONF_CHECK_I(double_wide); |
9289 | ||
c0d43d62 | 9290 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9291 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9292 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9293 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9294 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9295 | |
42571aef VS |
9296 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9297 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9298 | ||
d71b8d4a | 9299 | if (!IS_HASWELL(dev)) { |
241bfc38 | 9300 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
d71b8d4a VS |
9301 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
9302 | } | |
5e550656 | 9303 | |
66e985c0 | 9304 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9305 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9306 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9307 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9308 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9309 | |
0e8ffe1b DV |
9310 | return true; |
9311 | } | |
9312 | ||
91d1b4bd DV |
9313 | static void |
9314 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9315 | { |
8af6cf88 DV |
9316 | struct intel_connector *connector; |
9317 | ||
9318 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9319 | base.head) { | |
9320 | /* This also checks the encoder/connector hw state with the | |
9321 | * ->get_hw_state callbacks. */ | |
9322 | intel_connector_check_state(connector); | |
9323 | ||
9324 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9325 | "connector's staged encoder doesn't match current encoder\n"); | |
9326 | } | |
91d1b4bd DV |
9327 | } |
9328 | ||
9329 | static void | |
9330 | check_encoder_state(struct drm_device *dev) | |
9331 | { | |
9332 | struct intel_encoder *encoder; | |
9333 | struct intel_connector *connector; | |
8af6cf88 DV |
9334 | |
9335 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9336 | base.head) { | |
9337 | bool enabled = false; | |
9338 | bool active = false; | |
9339 | enum pipe pipe, tracked_pipe; | |
9340 | ||
9341 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9342 | encoder->base.base.id, | |
9343 | drm_get_encoder_name(&encoder->base)); | |
9344 | ||
9345 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9346 | "encoder's stage crtc doesn't match current crtc\n"); | |
9347 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9348 | "encoder's active_connectors set, but no crtc\n"); | |
9349 | ||
9350 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9351 | base.head) { | |
9352 | if (connector->base.encoder != &encoder->base) | |
9353 | continue; | |
9354 | enabled = true; | |
9355 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9356 | active = true; | |
9357 | } | |
9358 | WARN(!!encoder->base.crtc != enabled, | |
9359 | "encoder's enabled state mismatch " | |
9360 | "(expected %i, found %i)\n", | |
9361 | !!encoder->base.crtc, enabled); | |
9362 | WARN(active && !encoder->base.crtc, | |
9363 | "active encoder with no crtc\n"); | |
9364 | ||
9365 | WARN(encoder->connectors_active != active, | |
9366 | "encoder's computed active state doesn't match tracked active state " | |
9367 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9368 | ||
9369 | active = encoder->get_hw_state(encoder, &pipe); | |
9370 | WARN(active != encoder->connectors_active, | |
9371 | "encoder's hw state doesn't match sw tracking " | |
9372 | "(expected %i, found %i)\n", | |
9373 | encoder->connectors_active, active); | |
9374 | ||
9375 | if (!encoder->base.crtc) | |
9376 | continue; | |
9377 | ||
9378 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9379 | WARN(active && pipe != tracked_pipe, | |
9380 | "active encoder's pipe doesn't match" | |
9381 | "(expected %i, found %i)\n", | |
9382 | tracked_pipe, pipe); | |
9383 | ||
9384 | } | |
91d1b4bd DV |
9385 | } |
9386 | ||
9387 | static void | |
9388 | check_crtc_state(struct drm_device *dev) | |
9389 | { | |
9390 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9391 | struct intel_crtc *crtc; | |
9392 | struct intel_encoder *encoder; | |
9393 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9394 | |
9395 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9396 | base.head) { | |
9397 | bool enabled = false; | |
9398 | bool active = false; | |
9399 | ||
045ac3b5 JB |
9400 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9401 | ||
8af6cf88 DV |
9402 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9403 | crtc->base.base.id); | |
9404 | ||
9405 | WARN(crtc->active && !crtc->base.enabled, | |
9406 | "active crtc, but not enabled in sw tracking\n"); | |
9407 | ||
9408 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9409 | base.head) { | |
9410 | if (encoder->base.crtc != &crtc->base) | |
9411 | continue; | |
9412 | enabled = true; | |
9413 | if (encoder->connectors_active) | |
9414 | active = true; | |
9415 | } | |
6c49f241 | 9416 | |
8af6cf88 DV |
9417 | WARN(active != crtc->active, |
9418 | "crtc's computed active state doesn't match tracked active state " | |
9419 | "(expected %i, found %i)\n", active, crtc->active); | |
9420 | WARN(enabled != crtc->base.enabled, | |
9421 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9422 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9423 | ||
0e8ffe1b DV |
9424 | active = dev_priv->display.get_pipe_config(crtc, |
9425 | &pipe_config); | |
d62cf62a DV |
9426 | |
9427 | /* hw state is inconsistent with the pipe A quirk */ | |
9428 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9429 | active = crtc->active; | |
9430 | ||
6c49f241 DV |
9431 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9432 | base.head) { | |
3eaba51c | 9433 | enum pipe pipe; |
6c49f241 DV |
9434 | if (encoder->base.crtc != &crtc->base) |
9435 | continue; | |
3eaba51c VS |
9436 | if (encoder->get_config && |
9437 | encoder->get_hw_state(encoder, &pipe)) | |
6c49f241 DV |
9438 | encoder->get_config(encoder, &pipe_config); |
9439 | } | |
9440 | ||
0e8ffe1b DV |
9441 | WARN(crtc->active != active, |
9442 | "crtc active state doesn't match with hw state " | |
9443 | "(expected %i, found %i)\n", crtc->active, active); | |
9444 | ||
c0b03411 DV |
9445 | if (active && |
9446 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9447 | WARN(1, "pipe state doesn't match!\n"); | |
9448 | intel_dump_pipe_config(crtc, &pipe_config, | |
9449 | "[hw state]"); | |
9450 | intel_dump_pipe_config(crtc, &crtc->config, | |
9451 | "[sw state]"); | |
9452 | } | |
8af6cf88 DV |
9453 | } |
9454 | } | |
9455 | ||
91d1b4bd DV |
9456 | static void |
9457 | check_shared_dpll_state(struct drm_device *dev) | |
9458 | { | |
9459 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9460 | struct intel_crtc *crtc; | |
9461 | struct intel_dpll_hw_state dpll_hw_state; | |
9462 | int i; | |
5358901f DV |
9463 | |
9464 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9465 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9466 | int enabled_crtcs = 0, active_crtcs = 0; | |
9467 | bool active; | |
9468 | ||
9469 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9470 | ||
9471 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9472 | ||
9473 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9474 | ||
9475 | WARN(pll->active > pll->refcount, | |
9476 | "more active pll users than references: %i vs %i\n", | |
9477 | pll->active, pll->refcount); | |
9478 | WARN(pll->active && !pll->on, | |
9479 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9480 | WARN(pll->on && !pll->active, |
9481 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9482 | WARN(pll->on != active, |
9483 | "pll on state mismatch (expected %i, found %i)\n", | |
9484 | pll->on, active); | |
9485 | ||
9486 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9487 | base.head) { | |
9488 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9489 | enabled_crtcs++; | |
9490 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9491 | active_crtcs++; | |
9492 | } | |
9493 | WARN(pll->active != active_crtcs, | |
9494 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9495 | pll->active, active_crtcs); | |
9496 | WARN(pll->refcount != enabled_crtcs, | |
9497 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9498 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9499 | |
9500 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9501 | sizeof(dpll_hw_state)), | |
9502 | "pll hw state mismatch\n"); | |
5358901f | 9503 | } |
8af6cf88 DV |
9504 | } |
9505 | ||
91d1b4bd DV |
9506 | void |
9507 | intel_modeset_check_state(struct drm_device *dev) | |
9508 | { | |
9509 | check_connector_state(dev); | |
9510 | check_encoder_state(dev); | |
9511 | check_crtc_state(dev); | |
9512 | check_shared_dpll_state(dev); | |
9513 | } | |
9514 | ||
18442d08 VS |
9515 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9516 | int dotclock) | |
9517 | { | |
9518 | /* | |
9519 | * FDI already provided one idea for the dotclock. | |
9520 | * Yell if the encoder disagrees. | |
9521 | */ | |
241bfc38 | 9522 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9523 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9524 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9525 | } |
9526 | ||
f30da187 DV |
9527 | static int __intel_set_mode(struct drm_crtc *crtc, |
9528 | struct drm_display_mode *mode, | |
9529 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9530 | { |
9531 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9532 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
9533 | struct drm_display_mode *saved_mode, *saved_hwmode; |
9534 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
9535 | struct intel_crtc *intel_crtc; |
9536 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9537 | int ret = 0; |
a6778b3c | 9538 | |
a1e22653 | 9539 | saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9540 | if (!saved_mode) |
9541 | return -ENOMEM; | |
3ac18232 | 9542 | saved_hwmode = saved_mode + 1; |
a6778b3c | 9543 | |
e2e1ed41 | 9544 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9545 | &prepare_pipes, &disable_pipes); |
9546 | ||
3ac18232 TG |
9547 | *saved_hwmode = crtc->hwmode; |
9548 | *saved_mode = crtc->mode; | |
a6778b3c | 9549 | |
25c5b266 DV |
9550 | /* Hack: Because we don't (yet) support global modeset on multiple |
9551 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9552 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9553 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9554 | * changing their mode at the same time. */ | |
25c5b266 | 9555 | if (modeset_pipes) { |
4e53c2e0 | 9556 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9557 | if (IS_ERR(pipe_config)) { |
9558 | ret = PTR_ERR(pipe_config); | |
9559 | pipe_config = NULL; | |
9560 | ||
3ac18232 | 9561 | goto out; |
25c5b266 | 9562 | } |
c0b03411 DV |
9563 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9564 | "[modeset]"); | |
25c5b266 | 9565 | } |
a6778b3c | 9566 | |
30a970c6 JB |
9567 | /* |
9568 | * See if the config requires any additional preparation, e.g. | |
9569 | * to adjust global state with pipes off. We need to do this | |
9570 | * here so we can get the modeset_pipe updated config for the new | |
9571 | * mode set on this crtc. For other crtcs we need to use the | |
9572 | * adjusted_mode bits in the crtc directly. | |
9573 | */ | |
c164f833 | 9574 | if (IS_VALLEYVIEW(dev)) { |
30a970c6 JB |
9575 | valleyview_modeset_global_pipes(dev, &prepare_pipes, |
9576 | modeset_pipes, pipe_config); | |
9577 | ||
c164f833 VS |
9578 | /* may have added more to prepare_pipes than we should */ |
9579 | prepare_pipes &= ~disable_pipes; | |
9580 | } | |
9581 | ||
460da916 DV |
9582 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9583 | intel_crtc_disable(&intel_crtc->base); | |
9584 | ||
ea9d758d DV |
9585 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9586 | if (intel_crtc->base.enabled) | |
9587 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9588 | } | |
a6778b3c | 9589 | |
6c4c86f5 DV |
9590 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9591 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9592 | */ |
b8cecdf5 | 9593 | if (modeset_pipes) { |
25c5b266 | 9594 | crtc->mode = *mode; |
b8cecdf5 DV |
9595 | /* mode_set/enable/disable functions rely on a correct pipe |
9596 | * config. */ | |
9597 | to_intel_crtc(crtc)->config = *pipe_config; | |
9598 | } | |
7758a113 | 9599 | |
ea9d758d DV |
9600 | /* Only after disabling all output pipelines that will be changed can we |
9601 | * update the the output configuration. */ | |
9602 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9603 | |
47fab737 DV |
9604 | if (dev_priv->display.modeset_global_resources) |
9605 | dev_priv->display.modeset_global_resources(dev); | |
9606 | ||
a6778b3c DV |
9607 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9608 | * on the DPLL. | |
f6e5b160 | 9609 | */ |
25c5b266 | 9610 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9611 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9612 | x, y, fb); |
9613 | if (ret) | |
9614 | goto done; | |
a6778b3c DV |
9615 | } |
9616 | ||
9617 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9618 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9619 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9620 | |
25c5b266 DV |
9621 | if (modeset_pipes) { |
9622 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 9623 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 9624 | |
25c5b266 DV |
9625 | /* Calculate and store various constants which |
9626 | * are later needed by vblank and swap-completion | |
9627 | * timestamping. They are derived from true hwmode. | |
9628 | */ | |
9629 | drm_calc_timestamping_constants(crtc); | |
9630 | } | |
a6778b3c DV |
9631 | |
9632 | /* FIXME: add subpixel order */ | |
9633 | done: | |
c0c36b94 | 9634 | if (ret && crtc->enabled) { |
3ac18232 TG |
9635 | crtc->hwmode = *saved_hwmode; |
9636 | crtc->mode = *saved_mode; | |
a6778b3c DV |
9637 | } |
9638 | ||
3ac18232 | 9639 | out: |
b8cecdf5 | 9640 | kfree(pipe_config); |
3ac18232 | 9641 | kfree(saved_mode); |
a6778b3c | 9642 | return ret; |
f6e5b160 CW |
9643 | } |
9644 | ||
e7457a9a DL |
9645 | static int intel_set_mode(struct drm_crtc *crtc, |
9646 | struct drm_display_mode *mode, | |
9647 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9648 | { |
9649 | int ret; | |
9650 | ||
9651 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9652 | ||
9653 | if (ret == 0) | |
9654 | intel_modeset_check_state(crtc->dev); | |
9655 | ||
9656 | return ret; | |
9657 | } | |
9658 | ||
c0c36b94 CW |
9659 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9660 | { | |
9661 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9662 | } | |
9663 | ||
25c5b266 DV |
9664 | #undef for_each_intel_crtc_masked |
9665 | ||
d9e55608 DV |
9666 | static void intel_set_config_free(struct intel_set_config *config) |
9667 | { | |
9668 | if (!config) | |
9669 | return; | |
9670 | ||
1aa4b628 DV |
9671 | kfree(config->save_connector_encoders); |
9672 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
9673 | kfree(config); |
9674 | } | |
9675 | ||
85f9eb71 DV |
9676 | static int intel_set_config_save_state(struct drm_device *dev, |
9677 | struct intel_set_config *config) | |
9678 | { | |
85f9eb71 DV |
9679 | struct drm_encoder *encoder; |
9680 | struct drm_connector *connector; | |
9681 | int count; | |
9682 | ||
1aa4b628 DV |
9683 | config->save_encoder_crtcs = |
9684 | kcalloc(dev->mode_config.num_encoder, | |
9685 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9686 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9687 | return -ENOMEM; |
9688 | ||
1aa4b628 DV |
9689 | config->save_connector_encoders = |
9690 | kcalloc(dev->mode_config.num_connector, | |
9691 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9692 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9693 | return -ENOMEM; |
9694 | ||
9695 | /* Copy data. Note that driver private data is not affected. | |
9696 | * Should anything bad happen only the expected state is | |
9697 | * restored, not the drivers personal bookkeeping. | |
9698 | */ | |
85f9eb71 DV |
9699 | count = 0; |
9700 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9701 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9702 | } |
9703 | ||
9704 | count = 0; | |
9705 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9706 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9707 | } |
9708 | ||
9709 | return 0; | |
9710 | } | |
9711 | ||
9712 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9713 | struct intel_set_config *config) | |
9714 | { | |
9a935856 DV |
9715 | struct intel_encoder *encoder; |
9716 | struct intel_connector *connector; | |
85f9eb71 DV |
9717 | int count; |
9718 | ||
85f9eb71 | 9719 | count = 0; |
9a935856 DV |
9720 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9721 | encoder->new_crtc = | |
9722 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9723 | } |
9724 | ||
9725 | count = 0; | |
9a935856 DV |
9726 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9727 | connector->new_encoder = | |
9728 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9729 | } |
9730 | } | |
9731 | ||
e3de42b6 | 9732 | static bool |
2e57f47d | 9733 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9734 | { |
9735 | int i; | |
9736 | ||
2e57f47d CW |
9737 | if (set->num_connectors == 0) |
9738 | return false; | |
9739 | ||
9740 | if (WARN_ON(set->connectors == NULL)) | |
9741 | return false; | |
9742 | ||
9743 | for (i = 0; i < set->num_connectors; i++) | |
9744 | if (set->connectors[i]->encoder && | |
9745 | set->connectors[i]->encoder->crtc == set->crtc && | |
9746 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9747 | return true; |
9748 | ||
9749 | return false; | |
9750 | } | |
9751 | ||
5e2b584e DV |
9752 | static void |
9753 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9754 | struct intel_set_config *config) | |
9755 | { | |
9756 | ||
9757 | /* We should be able to check here if the fb has the same properties | |
9758 | * and then just flip_or_move it */ | |
2e57f47d CW |
9759 | if (is_crtc_connector_off(set)) { |
9760 | config->mode_changed = true; | |
e3de42b6 | 9761 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9762 | /* If we have no fb then treat it as a full mode set */ |
9763 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9764 | struct intel_crtc *intel_crtc = |
9765 | to_intel_crtc(set->crtc); | |
9766 | ||
9767 | if (intel_crtc->active && i915_fastboot) { | |
9768 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); | |
9769 | config->fb_changed = true; | |
9770 | } else { | |
9771 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9772 | config->mode_changed = true; | |
9773 | } | |
5e2b584e DV |
9774 | } else if (set->fb == NULL) { |
9775 | config->mode_changed = true; | |
72f4901e DV |
9776 | } else if (set->fb->pixel_format != |
9777 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9778 | config->mode_changed = true; |
e3de42b6 | 9779 | } else { |
5e2b584e | 9780 | config->fb_changed = true; |
e3de42b6 | 9781 | } |
5e2b584e DV |
9782 | } |
9783 | ||
835c5873 | 9784 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9785 | config->fb_changed = true; |
9786 | ||
9787 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9788 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9789 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9790 | drm_mode_debug_printmodeline(set->mode); | |
9791 | config->mode_changed = true; | |
9792 | } | |
a1d95703 CW |
9793 | |
9794 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9795 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9796 | } |
9797 | ||
2e431051 | 9798 | static int |
9a935856 DV |
9799 | intel_modeset_stage_output_state(struct drm_device *dev, |
9800 | struct drm_mode_set *set, | |
9801 | struct intel_set_config *config) | |
50f56119 | 9802 | { |
85f9eb71 | 9803 | struct drm_crtc *new_crtc; |
9a935856 DV |
9804 | struct intel_connector *connector; |
9805 | struct intel_encoder *encoder; | |
f3f08572 | 9806 | int ro; |
50f56119 | 9807 | |
9abdda74 | 9808 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9809 | * of connectors. For paranoia, double-check this. */ |
9810 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9811 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9812 | ||
9a935856 DV |
9813 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9814 | base.head) { | |
9815 | /* Otherwise traverse passed in connector list and get encoders | |
9816 | * for them. */ | |
50f56119 | 9817 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9818 | if (set->connectors[ro] == &connector->base) { |
9819 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9820 | break; |
9821 | } | |
9822 | } | |
9823 | ||
9a935856 DV |
9824 | /* If we disable the crtc, disable all its connectors. Also, if |
9825 | * the connector is on the changing crtc but not on the new | |
9826 | * connector list, disable it. */ | |
9827 | if ((!set->fb || ro == set->num_connectors) && | |
9828 | connector->base.encoder && | |
9829 | connector->base.encoder->crtc == set->crtc) { | |
9830 | connector->new_encoder = NULL; | |
9831 | ||
9832 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9833 | connector->base.base.id, | |
9834 | drm_get_connector_name(&connector->base)); | |
9835 | } | |
9836 | ||
9837 | ||
9838 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9839 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9840 | config->mode_changed = true; |
50f56119 DV |
9841 | } |
9842 | } | |
9a935856 | 9843 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9844 | |
9a935856 | 9845 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9846 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9847 | base.head) { | |
9848 | if (!connector->new_encoder) | |
50f56119 DV |
9849 | continue; |
9850 | ||
9a935856 | 9851 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9852 | |
9853 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9854 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9855 | new_crtc = set->crtc; |
9856 | } | |
9857 | ||
9858 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
9859 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9860 | new_crtc)) { | |
5e2b584e | 9861 | return -EINVAL; |
50f56119 | 9862 | } |
9a935856 DV |
9863 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9864 | ||
9865 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9866 | connector->base.base.id, | |
9867 | drm_get_connector_name(&connector->base), | |
9868 | new_crtc->base.id); | |
9869 | } | |
9870 | ||
9871 | /* Check for any encoders that needs to be disabled. */ | |
9872 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9873 | base.head) { | |
9874 | list_for_each_entry(connector, | |
9875 | &dev->mode_config.connector_list, | |
9876 | base.head) { | |
9877 | if (connector->new_encoder == encoder) { | |
9878 | WARN_ON(!connector->new_encoder->new_crtc); | |
9879 | ||
9880 | goto next_encoder; | |
9881 | } | |
9882 | } | |
9883 | encoder->new_crtc = NULL; | |
9884 | next_encoder: | |
9885 | /* Only now check for crtc changes so we don't miss encoders | |
9886 | * that will be disabled. */ | |
9887 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 9888 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 9889 | config->mode_changed = true; |
50f56119 DV |
9890 | } |
9891 | } | |
9a935856 | 9892 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 9893 | |
2e431051 DV |
9894 | return 0; |
9895 | } | |
9896 | ||
9897 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
9898 | { | |
9899 | struct drm_device *dev; | |
2e431051 DV |
9900 | struct drm_mode_set save_set; |
9901 | struct intel_set_config *config; | |
9902 | int ret; | |
2e431051 | 9903 | |
8d3e375e DV |
9904 | BUG_ON(!set); |
9905 | BUG_ON(!set->crtc); | |
9906 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 9907 | |
7e53f3a4 DV |
9908 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9909 | BUG_ON(!set->mode && set->fb); | |
9910 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 9911 | |
2e431051 DV |
9912 | if (set->fb) { |
9913 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
9914 | set->crtc->base.id, set->fb->base.id, | |
9915 | (int)set->num_connectors, set->x, set->y); | |
9916 | } else { | |
9917 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
9918 | } |
9919 | ||
9920 | dev = set->crtc->dev; | |
9921 | ||
9922 | ret = -ENOMEM; | |
9923 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
9924 | if (!config) | |
9925 | goto out_config; | |
9926 | ||
9927 | ret = intel_set_config_save_state(dev, config); | |
9928 | if (ret) | |
9929 | goto out_config; | |
9930 | ||
9931 | save_set.crtc = set->crtc; | |
9932 | save_set.mode = &set->crtc->mode; | |
9933 | save_set.x = set->crtc->x; | |
9934 | save_set.y = set->crtc->y; | |
9935 | save_set.fb = set->crtc->fb; | |
9936 | ||
9937 | /* Compute whether we need a full modeset, only an fb base update or no | |
9938 | * change at all. In the future we might also check whether only the | |
9939 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
9940 | * such cases. */ | |
9941 | intel_set_config_compute_mode_changes(set, config); | |
9942 | ||
9a935856 | 9943 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
9944 | if (ret) |
9945 | goto fail; | |
9946 | ||
5e2b584e | 9947 | if (config->mode_changed) { |
c0c36b94 CW |
9948 | ret = intel_set_mode(set->crtc, set->mode, |
9949 | set->x, set->y, set->fb); | |
5e2b584e | 9950 | } else if (config->fb_changed) { |
4878cae2 VS |
9951 | intel_crtc_wait_for_pending_flips(set->crtc); |
9952 | ||
4f660f49 | 9953 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 9954 | set->x, set->y, set->fb); |
50f56119 DV |
9955 | } |
9956 | ||
2d05eae1 | 9957 | if (ret) { |
bf67dfeb DV |
9958 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9959 | set->crtc->base.id, ret); | |
50f56119 | 9960 | fail: |
2d05eae1 | 9961 | intel_set_config_restore_state(dev, config); |
50f56119 | 9962 | |
2d05eae1 CW |
9963 | /* Try to restore the config */ |
9964 | if (config->mode_changed && | |
9965 | intel_set_mode(save_set.crtc, save_set.mode, | |
9966 | save_set.x, save_set.y, save_set.fb)) | |
9967 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
9968 | } | |
50f56119 | 9969 | |
d9e55608 DV |
9970 | out_config: |
9971 | intel_set_config_free(config); | |
50f56119 DV |
9972 | return ret; |
9973 | } | |
f6e5b160 CW |
9974 | |
9975 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
9976 | .cursor_set = intel_crtc_cursor_set, |
9977 | .cursor_move = intel_crtc_cursor_move, | |
9978 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 9979 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
9980 | .destroy = intel_crtc_destroy, |
9981 | .page_flip = intel_crtc_page_flip, | |
9982 | }; | |
9983 | ||
79f689aa PZ |
9984 | static void intel_cpu_pll_init(struct drm_device *dev) |
9985 | { | |
affa9354 | 9986 | if (HAS_DDI(dev)) |
79f689aa PZ |
9987 | intel_ddi_pll_init(dev); |
9988 | } | |
9989 | ||
5358901f DV |
9990 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9991 | struct intel_shared_dpll *pll, | |
9992 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 9993 | { |
5358901f | 9994 | uint32_t val; |
ee7b9f93 | 9995 | |
5358901f | 9996 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
9997 | hw_state->dpll = val; |
9998 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
9999 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10000 | |
10001 | return val & DPLL_VCO_ENABLE; | |
10002 | } | |
10003 | ||
15bdd4cf DV |
10004 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10005 | struct intel_shared_dpll *pll) | |
10006 | { | |
10007 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10008 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10009 | } | |
10010 | ||
e7b903d2 DV |
10011 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10012 | struct intel_shared_dpll *pll) | |
10013 | { | |
e7b903d2 DV |
10014 | /* PCH refclock must be enabled first */ |
10015 | assert_pch_refclk_enabled(dev_priv); | |
10016 | ||
15bdd4cf DV |
10017 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10018 | ||
10019 | /* Wait for the clocks to stabilize. */ | |
10020 | POSTING_READ(PCH_DPLL(pll->id)); | |
10021 | udelay(150); | |
10022 | ||
10023 | /* The pixel multiplier can only be updated once the | |
10024 | * DPLL is enabled and the clocks are stable. | |
10025 | * | |
10026 | * So write it again. | |
10027 | */ | |
10028 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10029 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10030 | udelay(200); |
10031 | } | |
10032 | ||
10033 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10034 | struct intel_shared_dpll *pll) | |
10035 | { | |
10036 | struct drm_device *dev = dev_priv->dev; | |
10037 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10038 | |
10039 | /* Make sure no transcoder isn't still depending on us. */ | |
10040 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10041 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10042 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10043 | } |
10044 | ||
15bdd4cf DV |
10045 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10046 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10047 | udelay(200); |
10048 | } | |
10049 | ||
46edb027 DV |
10050 | static char *ibx_pch_dpll_names[] = { |
10051 | "PCH DPLL A", | |
10052 | "PCH DPLL B", | |
10053 | }; | |
10054 | ||
7c74ade1 | 10055 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10056 | { |
e7b903d2 | 10057 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10058 | int i; |
10059 | ||
7c74ade1 | 10060 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10061 | |
e72f9fbf | 10062 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10063 | dev_priv->shared_dplls[i].id = i; |
10064 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10065 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10066 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10067 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10068 | dev_priv->shared_dplls[i].get_hw_state = |
10069 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10070 | } |
10071 | } | |
10072 | ||
7c74ade1 DV |
10073 | static void intel_shared_dpll_init(struct drm_device *dev) |
10074 | { | |
e7b903d2 | 10075 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10076 | |
10077 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10078 | ibx_pch_dpll_init(dev); | |
10079 | else | |
10080 | dev_priv->num_shared_dpll = 0; | |
10081 | ||
10082 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
10083 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", | |
10084 | dev_priv->num_shared_dpll); | |
10085 | } | |
10086 | ||
b358d0a6 | 10087 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10088 | { |
22fd0fab | 10089 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10090 | struct intel_crtc *intel_crtc; |
10091 | int i; | |
10092 | ||
955382f3 | 10093 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10094 | if (intel_crtc == NULL) |
10095 | return; | |
10096 | ||
10097 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10098 | ||
10099 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10100 | for (i = 0; i < 256; i++) { |
10101 | intel_crtc->lut_r[i] = i; | |
10102 | intel_crtc->lut_g[i] = i; | |
10103 | intel_crtc->lut_b[i] = i; | |
10104 | } | |
10105 | ||
80824003 JB |
10106 | /* Swap pipes & planes for FBC on pre-965 */ |
10107 | intel_crtc->pipe = pipe; | |
10108 | intel_crtc->plane = pipe; | |
e2e767ab | 10109 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 10110 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10111 | intel_crtc->plane = !pipe; |
80824003 JB |
10112 | } |
10113 | ||
22fd0fab JB |
10114 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10115 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10116 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10117 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10118 | ||
79e53945 | 10119 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10120 | } |
10121 | ||
752aa88a JB |
10122 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10123 | { | |
10124 | struct drm_encoder *encoder = connector->base.encoder; | |
10125 | ||
10126 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10127 | ||
10128 | if (!encoder) | |
10129 | return INVALID_PIPE; | |
10130 | ||
10131 | return to_intel_crtc(encoder->crtc)->pipe; | |
10132 | } | |
10133 | ||
08d7b3d1 | 10134 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10135 | struct drm_file *file) |
08d7b3d1 | 10136 | { |
08d7b3d1 | 10137 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10138 | struct drm_mode_object *drmmode_obj; |
10139 | struct intel_crtc *crtc; | |
08d7b3d1 | 10140 | |
1cff8f6b DV |
10141 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10142 | return -ENODEV; | |
08d7b3d1 | 10143 | |
c05422d5 DV |
10144 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10145 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10146 | |
c05422d5 | 10147 | if (!drmmode_obj) { |
08d7b3d1 | 10148 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10149 | return -ENOENT; |
08d7b3d1 CW |
10150 | } |
10151 | ||
c05422d5 DV |
10152 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10153 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10154 | |
c05422d5 | 10155 | return 0; |
08d7b3d1 CW |
10156 | } |
10157 | ||
66a9278e | 10158 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10159 | { |
66a9278e DV |
10160 | struct drm_device *dev = encoder->base.dev; |
10161 | struct intel_encoder *source_encoder; | |
79e53945 | 10162 | int index_mask = 0; |
79e53945 JB |
10163 | int entry = 0; |
10164 | ||
66a9278e DV |
10165 | list_for_each_entry(source_encoder, |
10166 | &dev->mode_config.encoder_list, base.head) { | |
10167 | ||
10168 | if (encoder == source_encoder) | |
79e53945 | 10169 | index_mask |= (1 << entry); |
66a9278e DV |
10170 | |
10171 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10172 | if (encoder->cloneable && source_encoder->cloneable) | |
10173 | index_mask |= (1 << entry); | |
10174 | ||
79e53945 JB |
10175 | entry++; |
10176 | } | |
4ef69c7a | 10177 | |
79e53945 JB |
10178 | return index_mask; |
10179 | } | |
10180 | ||
4d302442 CW |
10181 | static bool has_edp_a(struct drm_device *dev) |
10182 | { | |
10183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10184 | ||
10185 | if (!IS_MOBILE(dev)) | |
10186 | return false; | |
10187 | ||
10188 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10189 | return false; | |
10190 | ||
10191 | if (IS_GEN5(dev) && | |
10192 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
10193 | return false; | |
10194 | ||
10195 | return true; | |
10196 | } | |
10197 | ||
79e53945 JB |
10198 | static void intel_setup_outputs(struct drm_device *dev) |
10199 | { | |
725e30ad | 10200 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10201 | struct intel_encoder *encoder; |
cb0953d7 | 10202 | bool dpd_is_edp = false; |
79e53945 | 10203 | |
c9093354 | 10204 | intel_lvds_init(dev); |
79e53945 | 10205 | |
c40c0f5b | 10206 | if (!IS_ULT(dev)) |
79935fca | 10207 | intel_crt_init(dev); |
cb0953d7 | 10208 | |
affa9354 | 10209 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10210 | int found; |
10211 | ||
10212 | /* Haswell uses DDI functions to detect digital outputs */ | |
10213 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10214 | /* DDI A only supports eDP */ | |
10215 | if (found) | |
10216 | intel_ddi_init(dev, PORT_A); | |
10217 | ||
10218 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10219 | * register */ | |
10220 | found = I915_READ(SFUSE_STRAP); | |
10221 | ||
10222 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10223 | intel_ddi_init(dev, PORT_B); | |
10224 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10225 | intel_ddi_init(dev, PORT_C); | |
10226 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10227 | intel_ddi_init(dev, PORT_D); | |
10228 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10229 | int found; |
270b3042 DV |
10230 | dpd_is_edp = intel_dpd_is_edp(dev); |
10231 | ||
10232 | if (has_edp_a(dev)) | |
10233 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10234 | |
dc0fa718 | 10235 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10236 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10237 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10238 | if (!found) |
e2debe91 | 10239 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10240 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10241 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10242 | } |
10243 | ||
dc0fa718 | 10244 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10245 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10246 | |
dc0fa718 | 10247 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10248 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10249 | |
5eb08b69 | 10250 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10251 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10252 | |
270b3042 | 10253 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10254 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10255 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10256 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10257 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10258 | PORT_B); | |
10259 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10260 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10261 | } | |
10262 | ||
6f6005a5 JB |
10263 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10264 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10265 | PORT_C); | |
10266 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
10267 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | |
10268 | PORT_C); | |
10269 | } | |
19c03924 | 10270 | |
3cfca973 | 10271 | intel_dsi_init(dev); |
103a196f | 10272 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10273 | bool found = false; |
7d57382e | 10274 | |
e2debe91 | 10275 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10276 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10277 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10278 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10279 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10280 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10281 | } |
27185ae1 | 10282 | |
e7281eab | 10283 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10284 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10285 | } |
13520b05 KH |
10286 | |
10287 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10288 | |
e2debe91 | 10289 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10290 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10291 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10292 | } |
27185ae1 | 10293 | |
e2debe91 | 10294 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10295 | |
b01f2c3a JB |
10296 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10297 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10298 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10299 | } |
e7281eab | 10300 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10301 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10302 | } |
27185ae1 | 10303 | |
b01f2c3a | 10304 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10305 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10306 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10307 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10308 | intel_dvo_init(dev); |
10309 | ||
103a196f | 10310 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10311 | intel_tv_init(dev); |
10312 | ||
4ef69c7a CW |
10313 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10314 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10315 | encoder->base.possible_clones = | |
66a9278e | 10316 | intel_encoder_clones(encoder); |
79e53945 | 10317 | } |
47356eb6 | 10318 | |
dde86e2d | 10319 | intel_init_pch_refclk(dev); |
270b3042 DV |
10320 | |
10321 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10322 | } |
10323 | ||
ddfe1567 CW |
10324 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
10325 | { | |
10326 | drm_framebuffer_cleanup(&fb->base); | |
80075d49 | 10327 | WARN_ON(!fb->obj->framebuffer_references--); |
ddfe1567 CW |
10328 | drm_gem_object_unreference_unlocked(&fb->obj->base); |
10329 | } | |
10330 | ||
79e53945 JB |
10331 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
10332 | { | |
10333 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10334 | |
ddfe1567 | 10335 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
10336 | kfree(intel_fb); |
10337 | } | |
10338 | ||
10339 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10340 | struct drm_file *file, |
79e53945 JB |
10341 | unsigned int *handle) |
10342 | { | |
10343 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10344 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10345 | |
05394f39 | 10346 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10347 | } |
10348 | ||
10349 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10350 | .destroy = intel_user_framebuffer_destroy, | |
10351 | .create_handle = intel_user_framebuffer_create_handle, | |
10352 | }; | |
10353 | ||
38651674 DA |
10354 | int intel_framebuffer_init(struct drm_device *dev, |
10355 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 10356 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 10357 | struct drm_i915_gem_object *obj) |
79e53945 | 10358 | { |
53155c0a | 10359 | int aligned_height, tile_height; |
a35cdaa0 | 10360 | int pitch_limit; |
79e53945 JB |
10361 | int ret; |
10362 | ||
dd4916c5 DV |
10363 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10364 | ||
c16ed4be CW |
10365 | if (obj->tiling_mode == I915_TILING_Y) { |
10366 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10367 | return -EINVAL; |
c16ed4be | 10368 | } |
57cd6508 | 10369 | |
c16ed4be CW |
10370 | if (mode_cmd->pitches[0] & 63) { |
10371 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10372 | mode_cmd->pitches[0]); | |
57cd6508 | 10373 | return -EINVAL; |
c16ed4be | 10374 | } |
57cd6508 | 10375 | |
a35cdaa0 CW |
10376 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10377 | pitch_limit = 32*1024; | |
10378 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10379 | if (obj->tiling_mode) | |
10380 | pitch_limit = 16*1024; | |
10381 | else | |
10382 | pitch_limit = 32*1024; | |
10383 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10384 | if (obj->tiling_mode) | |
10385 | pitch_limit = 8*1024; | |
10386 | else | |
10387 | pitch_limit = 16*1024; | |
10388 | } else | |
10389 | /* XXX DSPC is limited to 4k tiled */ | |
10390 | pitch_limit = 8*1024; | |
10391 | ||
10392 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10393 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10394 | obj->tiling_mode ? "tiled" : "linear", | |
10395 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10396 | return -EINVAL; |
c16ed4be | 10397 | } |
5d7bd705 VS |
10398 | |
10399 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10400 | mode_cmd->pitches[0] != obj->stride) { |
10401 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10402 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10403 | return -EINVAL; |
c16ed4be | 10404 | } |
5d7bd705 | 10405 | |
57779d06 | 10406 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10407 | switch (mode_cmd->pixel_format) { |
57779d06 | 10408 | case DRM_FORMAT_C8: |
04b3924d VS |
10409 | case DRM_FORMAT_RGB565: |
10410 | case DRM_FORMAT_XRGB8888: | |
10411 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10412 | break; |
10413 | case DRM_FORMAT_XRGB1555: | |
10414 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10415 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10416 | DRM_DEBUG("unsupported pixel format: %s\n", |
10417 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10418 | return -EINVAL; |
c16ed4be | 10419 | } |
57779d06 VS |
10420 | break; |
10421 | case DRM_FORMAT_XBGR8888: | |
10422 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10423 | case DRM_FORMAT_XRGB2101010: |
10424 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10425 | case DRM_FORMAT_XBGR2101010: |
10426 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10427 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10428 | DRM_DEBUG("unsupported pixel format: %s\n", |
10429 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10430 | return -EINVAL; |
c16ed4be | 10431 | } |
b5626747 | 10432 | break; |
04b3924d VS |
10433 | case DRM_FORMAT_YUYV: |
10434 | case DRM_FORMAT_UYVY: | |
10435 | case DRM_FORMAT_YVYU: | |
10436 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10437 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10438 | DRM_DEBUG("unsupported pixel format: %s\n", |
10439 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10440 | return -EINVAL; |
c16ed4be | 10441 | } |
57cd6508 CW |
10442 | break; |
10443 | default: | |
4ee62c76 VS |
10444 | DRM_DEBUG("unsupported pixel format: %s\n", |
10445 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10446 | return -EINVAL; |
10447 | } | |
10448 | ||
90f9a336 VS |
10449 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10450 | if (mode_cmd->offsets[0] != 0) | |
10451 | return -EINVAL; | |
10452 | ||
53155c0a DV |
10453 | tile_height = IS_GEN2(dev) ? 16 : 8; |
10454 | aligned_height = ALIGN(mode_cmd->height, | |
10455 | obj->tiling_mode ? tile_height : 1); | |
10456 | /* FIXME drm helper for size checks (especially planar formats)? */ | |
10457 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10458 | return -EINVAL; | |
10459 | ||
c7d73f6a DV |
10460 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10461 | intel_fb->obj = obj; | |
80075d49 | 10462 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10463 | |
79e53945 JB |
10464 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10465 | if (ret) { | |
10466 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10467 | return ret; | |
10468 | } | |
10469 | ||
79e53945 JB |
10470 | return 0; |
10471 | } | |
10472 | ||
79e53945 JB |
10473 | static struct drm_framebuffer * |
10474 | intel_user_framebuffer_create(struct drm_device *dev, | |
10475 | struct drm_file *filp, | |
308e5bcb | 10476 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10477 | { |
05394f39 | 10478 | struct drm_i915_gem_object *obj; |
79e53945 | 10479 | |
308e5bcb JB |
10480 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10481 | mode_cmd->handles[0])); | |
c8725226 | 10482 | if (&obj->base == NULL) |
cce13ff7 | 10483 | return ERR_PTR(-ENOENT); |
79e53945 | 10484 | |
d2dff872 | 10485 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10486 | } |
10487 | ||
4520f53a | 10488 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10489 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10490 | { |
10491 | } | |
10492 | #endif | |
10493 | ||
79e53945 | 10494 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10495 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10496 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10497 | }; |
10498 | ||
e70236a8 JB |
10499 | /* Set up chip specific display functions */ |
10500 | static void intel_init_display(struct drm_device *dev) | |
10501 | { | |
10502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10503 | ||
ee9300bb DV |
10504 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10505 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10506 | else if (IS_VALLEYVIEW(dev)) | |
10507 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10508 | else if (IS_PINEVIEW(dev)) | |
10509 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10510 | else | |
10511 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10512 | ||
affa9354 | 10513 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10514 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10515 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10516 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10517 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10518 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10519 | dev_priv->display.update_plane = ironlake_update_plane; |
10520 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10521 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10522 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10523 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10524 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10525 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10526 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10527 | } else if (IS_VALLEYVIEW(dev)) { |
10528 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10529 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10530 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10531 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10532 | dev_priv->display.off = i9xx_crtc_off; | |
10533 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10534 | } else { |
0e8ffe1b | 10535 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10536 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10537 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10538 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10539 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10540 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10541 | } |
e70236a8 | 10542 | |
e70236a8 | 10543 | /* Returns the core display clock speed */ |
25eb05fc JB |
10544 | if (IS_VALLEYVIEW(dev)) |
10545 | dev_priv->display.get_display_clock_speed = | |
10546 | valleyview_get_display_clock_speed; | |
10547 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10548 | dev_priv->display.get_display_clock_speed = |
10549 | i945_get_display_clock_speed; | |
10550 | else if (IS_I915G(dev)) | |
10551 | dev_priv->display.get_display_clock_speed = | |
10552 | i915_get_display_clock_speed; | |
257a7ffc | 10553 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10554 | dev_priv->display.get_display_clock_speed = |
10555 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10556 | else if (IS_PINEVIEW(dev)) |
10557 | dev_priv->display.get_display_clock_speed = | |
10558 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10559 | else if (IS_I915GM(dev)) |
10560 | dev_priv->display.get_display_clock_speed = | |
10561 | i915gm_get_display_clock_speed; | |
10562 | else if (IS_I865G(dev)) | |
10563 | dev_priv->display.get_display_clock_speed = | |
10564 | i865_get_display_clock_speed; | |
f0f8a9ce | 10565 | else if (IS_I85X(dev)) |
e70236a8 JB |
10566 | dev_priv->display.get_display_clock_speed = |
10567 | i855_get_display_clock_speed; | |
10568 | else /* 852, 830 */ | |
10569 | dev_priv->display.get_display_clock_speed = | |
10570 | i830_get_display_clock_speed; | |
10571 | ||
7f8a8569 | 10572 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10573 | if (IS_GEN5(dev)) { |
674cf967 | 10574 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10575 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10576 | } else if (IS_GEN6(dev)) { |
674cf967 | 10577 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10578 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10579 | } else if (IS_IVYBRIDGE(dev)) { |
10580 | /* FIXME: detect B0+ stepping and use auto training */ | |
10581 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10582 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10583 | dev_priv->display.modeset_global_resources = |
10584 | ivb_modeset_global_resources; | |
4e0bbc31 | 10585 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10586 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10587 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10588 | dev_priv->display.modeset_global_resources = |
10589 | haswell_modeset_global_resources; | |
a0e63c22 | 10590 | } |
6067aaea | 10591 | } else if (IS_G4X(dev)) { |
e0dac65e | 10592 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10593 | } else if (IS_VALLEYVIEW(dev)) { |
10594 | dev_priv->display.modeset_global_resources = | |
10595 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10596 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10597 | } |
8c9f3aaf JB |
10598 | |
10599 | /* Default just returns -ENODEV to indicate unsupported */ | |
10600 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10601 | ||
10602 | switch (INTEL_INFO(dev)->gen) { | |
10603 | case 2: | |
10604 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10605 | break; | |
10606 | ||
10607 | case 3: | |
10608 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10609 | break; | |
10610 | ||
10611 | case 4: | |
10612 | case 5: | |
10613 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10614 | break; | |
10615 | ||
10616 | case 6: | |
10617 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10618 | break; | |
7c9017e5 | 10619 | case 7: |
4e0bbc31 | 10620 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10621 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10622 | break; | |
8c9f3aaf | 10623 | } |
7bd688cd JN |
10624 | |
10625 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10626 | } |
10627 | ||
b690e96c JB |
10628 | /* |
10629 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10630 | * resume, or other times. This quirk makes sure that's the case for | |
10631 | * affected systems. | |
10632 | */ | |
0206e353 | 10633 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10634 | { |
10635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10636 | ||
10637 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10638 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10639 | } |
10640 | ||
435793df KP |
10641 | /* |
10642 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10643 | */ | |
10644 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10645 | { | |
10646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10647 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10648 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10649 | } |
10650 | ||
4dca20ef | 10651 | /* |
5a15ab5b CE |
10652 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10653 | * brightness value | |
4dca20ef CE |
10654 | */ |
10655 | static void quirk_invert_brightness(struct drm_device *dev) | |
10656 | { | |
10657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10658 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10659 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10660 | } |
10661 | ||
b690e96c JB |
10662 | struct intel_quirk { |
10663 | int device; | |
10664 | int subsystem_vendor; | |
10665 | int subsystem_device; | |
10666 | void (*hook)(struct drm_device *dev); | |
10667 | }; | |
10668 | ||
5f85f176 EE |
10669 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10670 | struct intel_dmi_quirk { | |
10671 | void (*hook)(struct drm_device *dev); | |
10672 | const struct dmi_system_id (*dmi_id_list)[]; | |
10673 | }; | |
10674 | ||
10675 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10676 | { | |
10677 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10678 | return 1; | |
10679 | } | |
10680 | ||
10681 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10682 | { | |
10683 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10684 | { | |
10685 | .callback = intel_dmi_reverse_brightness, | |
10686 | .ident = "NCR Corporation", | |
10687 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10688 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10689 | }, | |
10690 | }, | |
10691 | { } /* terminating entry */ | |
10692 | }, | |
10693 | .hook = quirk_invert_brightness, | |
10694 | }, | |
10695 | }; | |
10696 | ||
c43b5634 | 10697 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10698 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10699 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10700 | |
b690e96c JB |
10701 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10702 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10703 | ||
b690e96c JB |
10704 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10705 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10706 | ||
a4945f95 | 10707 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10708 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10709 | |
10710 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10711 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10712 | |
10713 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10714 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10715 | |
ee1452d7 JN |
10716 | /* |
10717 | * All GM45 Acer (and its brands eMachines and Packard Bell) laptops | |
10718 | * seem to use inverted backlight PWM. | |
10719 | */ | |
10720 | { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, | |
b690e96c JB |
10721 | }; |
10722 | ||
10723 | static void intel_init_quirks(struct drm_device *dev) | |
10724 | { | |
10725 | struct pci_dev *d = dev->pdev; | |
10726 | int i; | |
10727 | ||
10728 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10729 | struct intel_quirk *q = &intel_quirks[i]; | |
10730 | ||
10731 | if (d->device == q->device && | |
10732 | (d->subsystem_vendor == q->subsystem_vendor || | |
10733 | q->subsystem_vendor == PCI_ANY_ID) && | |
10734 | (d->subsystem_device == q->subsystem_device || | |
10735 | q->subsystem_device == PCI_ANY_ID)) | |
10736 | q->hook(dev); | |
10737 | } | |
5f85f176 EE |
10738 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10739 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10740 | intel_dmi_quirks[i].hook(dev); | |
10741 | } | |
b690e96c JB |
10742 | } |
10743 | ||
9cce37f4 JB |
10744 | /* Disable the VGA plane that we never use */ |
10745 | static void i915_disable_vga(struct drm_device *dev) | |
10746 | { | |
10747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10748 | u8 sr1; | |
766aa1c4 | 10749 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
10750 | |
10751 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 10752 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10753 | sr1 = inb(VGA_SR_DATA); |
10754 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10755 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10756 | udelay(300); | |
10757 | ||
10758 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10759 | POSTING_READ(vga_reg); | |
10760 | } | |
10761 | ||
f817586c DV |
10762 | void intel_modeset_init_hw(struct drm_device *dev) |
10763 | { | |
f6071166 JB |
10764 | struct drm_i915_private *dev_priv = dev->dev_private; |
10765 | ||
a8f78b58 ED |
10766 | intel_prepare_ddi(dev); |
10767 | ||
f817586c DV |
10768 | intel_init_clock_gating(dev); |
10769 | ||
f6071166 JB |
10770 | /* Enable the CRI clock source so we can get at the display */ |
10771 | if (IS_VALLEYVIEW(dev)) | |
10772 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
10773 | DPLL_INTEGRATED_CRI_CLK_VLV); | |
10774 | ||
40e9cf64 JB |
10775 | intel_init_dpio(dev); |
10776 | ||
79f5b2c7 | 10777 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10778 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10779 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10780 | } |
10781 | ||
7d708ee4 ID |
10782 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10783 | { | |
10784 | intel_suspend_hw(dev); | |
10785 | } | |
10786 | ||
79e53945 JB |
10787 | void intel_modeset_init(struct drm_device *dev) |
10788 | { | |
652c393a | 10789 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 10790 | int i, j, ret; |
79e53945 JB |
10791 | |
10792 | drm_mode_config_init(dev); | |
10793 | ||
10794 | dev->mode_config.min_width = 0; | |
10795 | dev->mode_config.min_height = 0; | |
10796 | ||
019d96cb DA |
10797 | dev->mode_config.preferred_depth = 24; |
10798 | dev->mode_config.prefer_shadow = 1; | |
10799 | ||
e6ecefaa | 10800 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 10801 | |
b690e96c JB |
10802 | intel_init_quirks(dev); |
10803 | ||
1fa61106 ED |
10804 | intel_init_pm(dev); |
10805 | ||
e3c74757 BW |
10806 | if (INTEL_INFO(dev)->num_pipes == 0) |
10807 | return; | |
10808 | ||
e70236a8 JB |
10809 | intel_init_display(dev); |
10810 | ||
a6c45cf0 CW |
10811 | if (IS_GEN2(dev)) { |
10812 | dev->mode_config.max_width = 2048; | |
10813 | dev->mode_config.max_height = 2048; | |
10814 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
10815 | dev->mode_config.max_width = 4096; |
10816 | dev->mode_config.max_height = 4096; | |
79e53945 | 10817 | } else { |
a6c45cf0 CW |
10818 | dev->mode_config.max_width = 8192; |
10819 | dev->mode_config.max_height = 8192; | |
79e53945 | 10820 | } |
5d4545ae | 10821 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 10822 | |
28c97730 | 10823 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
10824 | INTEL_INFO(dev)->num_pipes, |
10825 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 10826 | |
08e2a7de | 10827 | for_each_pipe(i) { |
79e53945 | 10828 | intel_crtc_init(dev, i); |
7f1f3851 JB |
10829 | for (j = 0; j < dev_priv->num_plane; j++) { |
10830 | ret = intel_plane_init(dev, i, j); | |
10831 | if (ret) | |
06da8da2 VS |
10832 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10833 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 10834 | } |
79e53945 JB |
10835 | } |
10836 | ||
79f689aa | 10837 | intel_cpu_pll_init(dev); |
e72f9fbf | 10838 | intel_shared_dpll_init(dev); |
ee7b9f93 | 10839 | |
9cce37f4 JB |
10840 | /* Just disable it once at startup */ |
10841 | i915_disable_vga(dev); | |
79e53945 | 10842 | intel_setup_outputs(dev); |
11be49eb CW |
10843 | |
10844 | /* Just in case the BIOS is doing something questionable. */ | |
10845 | intel_disable_fbc(dev); | |
2c7111db CW |
10846 | } |
10847 | ||
24929352 DV |
10848 | static void |
10849 | intel_connector_break_all_links(struct intel_connector *connector) | |
10850 | { | |
10851 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10852 | connector->base.encoder = NULL; | |
10853 | connector->encoder->connectors_active = false; | |
10854 | connector->encoder->base.crtc = NULL; | |
10855 | } | |
10856 | ||
7fad798e DV |
10857 | static void intel_enable_pipe_a(struct drm_device *dev) |
10858 | { | |
10859 | struct intel_connector *connector; | |
10860 | struct drm_connector *crt = NULL; | |
10861 | struct intel_load_detect_pipe load_detect_temp; | |
10862 | ||
10863 | /* We can't just switch on the pipe A, we need to set things up with a | |
10864 | * proper mode and output configuration. As a gross hack, enable pipe A | |
10865 | * by enabling the load detect pipe once. */ | |
10866 | list_for_each_entry(connector, | |
10867 | &dev->mode_config.connector_list, | |
10868 | base.head) { | |
10869 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
10870 | crt = &connector->base; | |
10871 | break; | |
10872 | } | |
10873 | } | |
10874 | ||
10875 | if (!crt) | |
10876 | return; | |
10877 | ||
10878 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
10879 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
10880 | ||
652c393a | 10881 | |
7fad798e DV |
10882 | } |
10883 | ||
fa555837 DV |
10884 | static bool |
10885 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
10886 | { | |
7eb552ae BW |
10887 | struct drm_device *dev = crtc->base.dev; |
10888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
10889 | u32 reg, val; |
10890 | ||
7eb552ae | 10891 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
10892 | return true; |
10893 | ||
10894 | reg = DSPCNTR(!crtc->plane); | |
10895 | val = I915_READ(reg); | |
10896 | ||
10897 | if ((val & DISPLAY_PLANE_ENABLE) && | |
10898 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
10899 | return false; | |
10900 | ||
10901 | return true; | |
10902 | } | |
10903 | ||
24929352 DV |
10904 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10905 | { | |
10906 | struct drm_device *dev = crtc->base.dev; | |
10907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 10908 | u32 reg; |
24929352 | 10909 | |
24929352 | 10910 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 10911 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
10912 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10913 | ||
10914 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
10915 | * disable the crtc (and hence change the state) if it is wrong. Note |
10916 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
10917 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
10918 | struct intel_connector *connector; |
10919 | bool plane; | |
10920 | ||
24929352 DV |
10921 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10922 | crtc->base.base.id); | |
10923 | ||
10924 | /* Pipe has the wrong plane attached and the plane is active. | |
10925 | * Temporarily change the plane mapping and disable everything | |
10926 | * ... */ | |
10927 | plane = crtc->plane; | |
10928 | crtc->plane = !plane; | |
10929 | dev_priv->display.crtc_disable(&crtc->base); | |
10930 | crtc->plane = plane; | |
10931 | ||
10932 | /* ... and break all links. */ | |
10933 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10934 | base.head) { | |
10935 | if (connector->encoder->base.crtc != &crtc->base) | |
10936 | continue; | |
10937 | ||
10938 | intel_connector_break_all_links(connector); | |
10939 | } | |
10940 | ||
10941 | WARN_ON(crtc->active); | |
10942 | crtc->base.enabled = false; | |
10943 | } | |
24929352 | 10944 | |
7fad798e DV |
10945 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10946 | crtc->pipe == PIPE_A && !crtc->active) { | |
10947 | /* BIOS forgot to enable pipe A, this mostly happens after | |
10948 | * resume. Force-enable the pipe to fix this, the update_dpms | |
10949 | * call below we restore the pipe to the right state, but leave | |
10950 | * the required bits on. */ | |
10951 | intel_enable_pipe_a(dev); | |
10952 | } | |
10953 | ||
24929352 DV |
10954 | /* Adjust the state of the output pipe according to whether we |
10955 | * have active connectors/encoders. */ | |
10956 | intel_crtc_update_dpms(&crtc->base); | |
10957 | ||
10958 | if (crtc->active != crtc->base.enabled) { | |
10959 | struct intel_encoder *encoder; | |
10960 | ||
10961 | /* This can happen either due to bugs in the get_hw_state | |
10962 | * functions or because the pipe is force-enabled due to the | |
10963 | * pipe A quirk. */ | |
10964 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
10965 | crtc->base.base.id, | |
10966 | crtc->base.enabled ? "enabled" : "disabled", | |
10967 | crtc->active ? "enabled" : "disabled"); | |
10968 | ||
10969 | crtc->base.enabled = crtc->active; | |
10970 | ||
10971 | /* Because we only establish the connector -> encoder -> | |
10972 | * crtc links if something is active, this means the | |
10973 | * crtc is now deactivated. Break the links. connector | |
10974 | * -> encoder links are only establish when things are | |
10975 | * actually up, hence no need to break them. */ | |
10976 | WARN_ON(crtc->active); | |
10977 | ||
10978 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
10979 | WARN_ON(encoder->connectors_active); | |
10980 | encoder->base.crtc = NULL; | |
10981 | } | |
10982 | } | |
10983 | } | |
10984 | ||
10985 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
10986 | { | |
10987 | struct intel_connector *connector; | |
10988 | struct drm_device *dev = encoder->base.dev; | |
10989 | ||
10990 | /* We need to check both for a crtc link (meaning that the | |
10991 | * encoder is active and trying to read from a pipe) and the | |
10992 | * pipe itself being active. */ | |
10993 | bool has_active_crtc = encoder->base.crtc && | |
10994 | to_intel_crtc(encoder->base.crtc)->active; | |
10995 | ||
10996 | if (encoder->connectors_active && !has_active_crtc) { | |
10997 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
10998 | encoder->base.base.id, | |
10999 | drm_get_encoder_name(&encoder->base)); | |
11000 | ||
11001 | /* Connector is active, but has no active pipe. This is | |
11002 | * fallout from our resume register restoring. Disable | |
11003 | * the encoder manually again. */ | |
11004 | if (encoder->base.crtc) { | |
11005 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11006 | encoder->base.base.id, | |
11007 | drm_get_encoder_name(&encoder->base)); | |
11008 | encoder->disable(encoder); | |
11009 | } | |
11010 | ||
11011 | /* Inconsistent output/port/pipe state happens presumably due to | |
11012 | * a bug in one of the get_hw_state functions. Or someplace else | |
11013 | * in our code, like the register restore mess on resume. Clamp | |
11014 | * things to off as a safer default. */ | |
11015 | list_for_each_entry(connector, | |
11016 | &dev->mode_config.connector_list, | |
11017 | base.head) { | |
11018 | if (connector->encoder != encoder) | |
11019 | continue; | |
11020 | ||
11021 | intel_connector_break_all_links(connector); | |
11022 | } | |
11023 | } | |
11024 | /* Enabled encoders without active connectors will be fixed in | |
11025 | * the crtc fixup. */ | |
11026 | } | |
11027 | ||
44cec740 | 11028 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
11029 | { |
11030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11031 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11032 | |
8dc8a27c PZ |
11033 | /* This function can be called both from intel_modeset_setup_hw_state or |
11034 | * at a very early point in our resume sequence, where the power well | |
11035 | * structures are not yet restored. Since this function is at a very | |
11036 | * paranoid "someone might have enabled VGA while we were not looking" | |
11037 | * level, just check if the power well is enabled instead of trying to | |
11038 | * follow the "don't touch the power well if we don't need it" policy | |
11039 | * the rest of the driver uses. */ | |
f9e711e9 | 11040 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
6aedd1f5 | 11041 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
11042 | return; |
11043 | ||
e1553faa | 11044 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
0fde901f | 11045 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
209d5211 | 11046 | i915_disable_vga(dev); |
0fde901f KM |
11047 | } |
11048 | } | |
11049 | ||
30e984df | 11050 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11051 | { |
11052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11053 | enum pipe pipe; | |
24929352 DV |
11054 | struct intel_crtc *crtc; |
11055 | struct intel_encoder *encoder; | |
11056 | struct intel_connector *connector; | |
5358901f | 11057 | int i; |
24929352 | 11058 | |
0e8ffe1b DV |
11059 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11060 | base.head) { | |
88adfff1 | 11061 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11062 | |
0e8ffe1b DV |
11063 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11064 | &crtc->config); | |
24929352 DV |
11065 | |
11066 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11067 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11068 | |
11069 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11070 | crtc->base.base.id, | |
11071 | crtc->active ? "enabled" : "disabled"); | |
11072 | } | |
11073 | ||
5358901f | 11074 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11075 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11076 | intel_ddi_setup_hw_pll_state(dev); |
11077 | ||
5358901f DV |
11078 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11079 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11080 | ||
11081 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11082 | pll->active = 0; | |
11083 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11084 | base.head) { | |
11085 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11086 | pll->active++; | |
11087 | } | |
11088 | pll->refcount = pll->active; | |
11089 | ||
35c95375 DV |
11090 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11091 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11092 | } |
11093 | ||
24929352 DV |
11094 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11095 | base.head) { | |
11096 | pipe = 0; | |
11097 | ||
11098 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11099 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11100 | encoder->base.crtc = &crtc->base; | |
510d5f2f | 11101 | if (encoder->get_config) |
045ac3b5 | 11102 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11103 | } else { |
11104 | encoder->base.crtc = NULL; | |
11105 | } | |
11106 | ||
11107 | encoder->connectors_active = false; | |
6f2bcceb | 11108 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11109 | encoder->base.base.id, |
11110 | drm_get_encoder_name(&encoder->base), | |
11111 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11112 | pipe_name(pipe)); |
24929352 DV |
11113 | } |
11114 | ||
11115 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11116 | base.head) { | |
11117 | if (connector->get_hw_state(connector)) { | |
11118 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11119 | connector->encoder->connectors_active = true; | |
11120 | connector->base.encoder = &connector->encoder->base; | |
11121 | } else { | |
11122 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11123 | connector->base.encoder = NULL; | |
11124 | } | |
11125 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11126 | connector->base.base.id, | |
11127 | drm_get_connector_name(&connector->base), | |
11128 | connector->base.encoder ? "enabled" : "disabled"); | |
11129 | } | |
30e984df DV |
11130 | } |
11131 | ||
11132 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11133 | * and i915 state tracking structures. */ | |
11134 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11135 | bool force_restore) | |
11136 | { | |
11137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11138 | enum pipe pipe; | |
30e984df DV |
11139 | struct intel_crtc *crtc; |
11140 | struct intel_encoder *encoder; | |
35c95375 | 11141 | int i; |
30e984df DV |
11142 | |
11143 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11144 | |
babea61d JB |
11145 | /* |
11146 | * Now that we have the config, copy it to each CRTC struct | |
11147 | * Note that this could go away if we move to using crtc_config | |
11148 | * checking everywhere. | |
11149 | */ | |
11150 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11151 | base.head) { | |
11152 | if (crtc->active && i915_fastboot) { | |
11153 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); | |
11154 | ||
11155 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
11156 | crtc->base.base.id); | |
11157 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11158 | } | |
11159 | } | |
11160 | ||
24929352 DV |
11161 | /* HW state is read out, now we need to sanitize this mess. */ |
11162 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11163 | base.head) { | |
11164 | intel_sanitize_encoder(encoder); | |
11165 | } | |
11166 | ||
11167 | for_each_pipe(pipe) { | |
11168 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11169 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11170 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11171 | } |
9a935856 | 11172 | |
35c95375 DV |
11173 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11174 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11175 | ||
11176 | if (!pll->on || pll->active) | |
11177 | continue; | |
11178 | ||
11179 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11180 | ||
11181 | pll->disable(dev_priv, pll); | |
11182 | pll->on = false; | |
11183 | } | |
11184 | ||
243e6a44 VS |
11185 | if (IS_HASWELL(dev)) |
11186 | ilk_wm_get_hw_state(dev); | |
11187 | ||
45e2b5f6 | 11188 | if (force_restore) { |
7d0bc1ea VS |
11189 | i915_redisable_vga(dev); |
11190 | ||
f30da187 DV |
11191 | /* |
11192 | * We need to use raw interfaces for restoring state to avoid | |
11193 | * checking (bogus) intermediate states. | |
11194 | */ | |
45e2b5f6 | 11195 | for_each_pipe(pipe) { |
b5644d05 JB |
11196 | struct drm_crtc *crtc = |
11197 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11198 | |
11199 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11200 | crtc->fb); | |
45e2b5f6 DV |
11201 | } |
11202 | } else { | |
11203 | intel_modeset_update_staged_output_state(dev); | |
11204 | } | |
8af6cf88 DV |
11205 | |
11206 | intel_modeset_check_state(dev); | |
2e938892 DV |
11207 | |
11208 | drm_mode_config_reset(dev); | |
2c7111db CW |
11209 | } |
11210 | ||
11211 | void intel_modeset_gem_init(struct drm_device *dev) | |
11212 | { | |
1833b134 | 11213 | intel_modeset_init_hw(dev); |
02e792fb DV |
11214 | |
11215 | intel_setup_overlay(dev); | |
24929352 | 11216 | |
45e2b5f6 | 11217 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
11218 | } |
11219 | ||
11220 | void intel_modeset_cleanup(struct drm_device *dev) | |
11221 | { | |
652c393a JB |
11222 | struct drm_i915_private *dev_priv = dev->dev_private; |
11223 | struct drm_crtc *crtc; | |
d9255d57 | 11224 | struct drm_connector *connector; |
652c393a | 11225 | |
fd0c0642 DV |
11226 | /* |
11227 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11228 | * Too much stuff here (turning of rps, connectors, ...) would | |
11229 | * experience fancy races otherwise. | |
11230 | */ | |
11231 | drm_irq_uninstall(dev); | |
11232 | cancel_work_sync(&dev_priv->hotplug_work); | |
11233 | /* | |
11234 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11235 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11236 | */ | |
f87ea761 | 11237 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11238 | |
652c393a JB |
11239 | mutex_lock(&dev->struct_mutex); |
11240 | ||
723bfd70 JB |
11241 | intel_unregister_dsm_handler(); |
11242 | ||
652c393a JB |
11243 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11244 | /* Skip inactive CRTCs */ | |
11245 | if (!crtc->fb) | |
11246 | continue; | |
11247 | ||
3dec0095 | 11248 | intel_increase_pllclock(crtc); |
652c393a JB |
11249 | } |
11250 | ||
973d04f9 | 11251 | intel_disable_fbc(dev); |
e70236a8 | 11252 | |
8090c6b9 | 11253 | intel_disable_gt_powersave(dev); |
0cdab21f | 11254 | |
930ebb46 DV |
11255 | ironlake_teardown_rc6(dev); |
11256 | ||
69341a5e KH |
11257 | mutex_unlock(&dev->struct_mutex); |
11258 | ||
1630fe75 CW |
11259 | /* flush any delayed tasks or pending work */ |
11260 | flush_scheduled_work(); | |
11261 | ||
db31af1d JN |
11262 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11263 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11264 | intel_panel_destroy_backlight(connector); | |
d9255d57 | 11265 | drm_sysfs_connector_remove(connector); |
db31af1d | 11266 | } |
d9255d57 | 11267 | |
79e53945 | 11268 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11269 | |
11270 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11271 | } |
11272 | ||
f1c79df3 ZW |
11273 | /* |
11274 | * Return which encoder is currently attached for connector. | |
11275 | */ | |
df0e9248 | 11276 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11277 | { |
df0e9248 CW |
11278 | return &intel_attached_encoder(connector)->base; |
11279 | } | |
f1c79df3 | 11280 | |
df0e9248 CW |
11281 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11282 | struct intel_encoder *encoder) | |
11283 | { | |
11284 | connector->encoder = encoder; | |
11285 | drm_mode_connector_attach_encoder(&connector->base, | |
11286 | &encoder->base); | |
79e53945 | 11287 | } |
28d52043 DA |
11288 | |
11289 | /* | |
11290 | * set vga decode state - true == enable VGA decode | |
11291 | */ | |
11292 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11293 | { | |
11294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11295 | u16 gmch_ctrl; | |
11296 | ||
11297 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
11298 | if (state) | |
11299 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11300 | else | |
11301 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
11302 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
11303 | return 0; | |
11304 | } | |
c4a1d9e4 | 11305 | |
c4a1d9e4 | 11306 | struct intel_display_error_state { |
ff57f1b0 PZ |
11307 | |
11308 | u32 power_well_driver; | |
11309 | ||
63b66e5b CW |
11310 | int num_transcoders; |
11311 | ||
c4a1d9e4 CW |
11312 | struct intel_cursor_error_state { |
11313 | u32 control; | |
11314 | u32 position; | |
11315 | u32 base; | |
11316 | u32 size; | |
52331309 | 11317 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11318 | |
11319 | struct intel_pipe_error_state { | |
c4a1d9e4 | 11320 | u32 source; |
52331309 | 11321 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11322 | |
11323 | struct intel_plane_error_state { | |
11324 | u32 control; | |
11325 | u32 stride; | |
11326 | u32 size; | |
11327 | u32 pos; | |
11328 | u32 addr; | |
11329 | u32 surface; | |
11330 | u32 tile_offset; | |
52331309 | 11331 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11332 | |
11333 | struct intel_transcoder_error_state { | |
11334 | enum transcoder cpu_transcoder; | |
11335 | ||
11336 | u32 conf; | |
11337 | ||
11338 | u32 htotal; | |
11339 | u32 hblank; | |
11340 | u32 hsync; | |
11341 | u32 vtotal; | |
11342 | u32 vblank; | |
11343 | u32 vsync; | |
11344 | } transcoder[4]; | |
c4a1d9e4 CW |
11345 | }; |
11346 | ||
11347 | struct intel_display_error_state * | |
11348 | intel_display_capture_error_state(struct drm_device *dev) | |
11349 | { | |
0206e353 | 11350 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11351 | struct intel_display_error_state *error; |
63b66e5b CW |
11352 | int transcoders[] = { |
11353 | TRANSCODER_A, | |
11354 | TRANSCODER_B, | |
11355 | TRANSCODER_C, | |
11356 | TRANSCODER_EDP, | |
11357 | }; | |
c4a1d9e4 CW |
11358 | int i; |
11359 | ||
63b66e5b CW |
11360 | if (INTEL_INFO(dev)->num_pipes == 0) |
11361 | return NULL; | |
11362 | ||
9d1cb914 | 11363 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11364 | if (error == NULL) |
11365 | return NULL; | |
11366 | ||
190be112 | 11367 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11368 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11369 | ||
52331309 | 11370 | for_each_pipe(i) { |
9d1cb914 PZ |
11371 | if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i))) |
11372 | continue; | |
11373 | ||
a18c4c3d PZ |
11374 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11375 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11376 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11377 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11378 | } else { | |
11379 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11380 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11381 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11382 | } | |
c4a1d9e4 CW |
11383 | |
11384 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11385 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11386 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11387 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11388 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11389 | } | |
ca291363 PZ |
11390 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11391 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11392 | if (INTEL_INFO(dev)->gen >= 4) { |
11393 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11394 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11395 | } | |
11396 | ||
c4a1d9e4 | 11397 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11398 | } |
11399 | ||
11400 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11401 | if (HAS_DDI(dev_priv->dev)) | |
11402 | error->num_transcoders++; /* Account for eDP. */ | |
11403 | ||
11404 | for (i = 0; i < error->num_transcoders; i++) { | |
11405 | enum transcoder cpu_transcoder = transcoders[i]; | |
11406 | ||
9d1cb914 PZ |
11407 | if (!intel_display_power_enabled(dev, |
11408 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) | |
11409 | continue; | |
11410 | ||
63b66e5b CW |
11411 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11412 | ||
11413 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11414 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11415 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11416 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11417 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11418 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11419 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11420 | } |
11421 | ||
11422 | return error; | |
11423 | } | |
11424 | ||
edc3d884 MK |
11425 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11426 | ||
c4a1d9e4 | 11427 | void |
edc3d884 | 11428 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11429 | struct drm_device *dev, |
11430 | struct intel_display_error_state *error) | |
11431 | { | |
11432 | int i; | |
11433 | ||
63b66e5b CW |
11434 | if (!error) |
11435 | return; | |
11436 | ||
edc3d884 | 11437 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11438 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11439 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11440 | error->power_well_driver); |
52331309 | 11441 | for_each_pipe(i) { |
edc3d884 | 11442 | err_printf(m, "Pipe [%d]:\n", i); |
edc3d884 | 11443 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11444 | |
11445 | err_printf(m, "Plane [%d]:\n", i); | |
11446 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11447 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11448 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11449 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11450 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11451 | } |
4b71a570 | 11452 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11453 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11454 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11455 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11456 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11457 | } |
11458 | ||
edc3d884 MK |
11459 | err_printf(m, "Cursor [%d]:\n", i); |
11460 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11461 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11462 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11463 | } |
63b66e5b CW |
11464 | |
11465 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11466 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b CW |
11467 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
11468 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); | |
11469 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11470 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11471 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11472 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11473 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11474 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11475 | } | |
c4a1d9e4 | 11476 | } |