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Revert and fix "drm/i915/dp: remove DPMS mode tracking from DP"
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB		 27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
JB		 33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
JB		 39
40#include "drm_crtc_helper.h"
41
32f9d658
ZW		 42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
ML		 71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
79e53945
JB		 73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
d4906093
ML		 75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
79e53945 78
2377b741
JB		 79/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
d4906093
ML		 82static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
79e53945 88
a4fc5ed6
KP		 89static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 92static bool
f2b115e6
AJ		 93intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 95
021357ac
CW		 96static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
8b99e68c
CW		 99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
021357ac
CW		 104}
105
e4b36699 106static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
d4906093 117 .find_pll = intel_find_best_PLL,
e4b36699
KP		 118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
d4906093 131 .find_pll = intel_find_best_PLL,
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
d4906093 145 .find_pll = intel_find_best_PLL,
e4b36699
KP		 146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
d4906093 159 .find_pll = intel_find_best_PLL,
e4b36699
KP		 160};
161
273e27ca 162
e4b36699 163static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
044c7c41 175 },
d4906093 176 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
d4906093 190 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
044c7c41 204 },
d4906093 205 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
044c7c41 219 },
d4906093 220 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 234 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 235};
236
f2b115e6 237static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
6115707b 250 .find_pll = intel_find_best_PLL,
e4b36699
KP		 251};
252
f2b115e6 253static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
6115707b 264 .find_pll = intel_find_best_PLL,
e4b36699
KP		 265};
266
273e27ca
EA		 267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
b91ad0ec 272static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
4547668a 283 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 284};
285
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 311 .find_pll = intel_g4x_find_best_PLL,
312};
313
273e27ca 314/* LVDS 100mhz refclk limits. */
b91ad0ec 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
4547668a 354 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 355};
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec
ZW		 360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 362 const intel_limit_t *limit;
b91ad0ec
ZW		 363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
1b894b59 373 if (refclk == 100000)
b91ad0ec
ZW		 374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
2c07245f 381 else
b91ad0ec 382 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 383
384 return limit;
385}
386
044c7c41
ML		 387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
e4b36699 397 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 398 else
399 /* LVDS with dual channel */
e4b36699 400 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 403 limit = &intel_limits_g4x_hdmi;
044c7c41 404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 405 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 407 limit = &intel_limits_g4x_display_port;
044c7c41 408 } else /* The option is for other outputs */
e4b36699 409 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 410
411 return limit;
412}
413
1b894b59 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
bad720ff 419 if (HAS_PCH_SPLIT(dev))
1b894b59 420 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 421 else if (IS_G4X(dev)) {
044c7c41 422 limit = intel_g4x_limit(crtc);
f2b115e6 423 } else if (IS_PINEVIEW(dev)) {
2177832f 424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 425 limit = &intel_limits_pineview_lvds;
2177832f 426 else
f2b115e6 427 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 435 limit = &intel_limits_i8xx_lvds;
79e53945 436 else
e4b36699 437 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 438 }
439 return limit;
440}
441
f2b115e6
AJ		 442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 444{
2177832f
SL		 445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
f2b115e6
AJ		 453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
2177832f
SL		 455 return;
456 }
79e53945
JB		 457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
79e53945
JB		 463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
4ef69c7a 466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 467{
4ef69c7a
CW		 468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
79e53945
JB		 477}
478
7c04d1d9 479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
1b894b59
CW		 485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
79e53945 488{
79e53945
JB		 489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
f2b115e6 497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
d4906093
ML		 514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
79e53945
JB		 518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
79e53945
JB		 522 int err = target;
523
bc5e5718 524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 525 (I915_READ(LVDS)) != 0) {
79e53945
JB		 526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
42158660
ZY		 546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 557 int this_err;
558
2177832f 559 intel_clock(dev, refclk, &clock);
1b894b59
CW		 560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
79e53945
JB		 562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
d4906093
ML		 577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
6ba770dc
AJ		 586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 591 int lvds_reg;
592
c619eed4 593 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
f77f13e2 611 /* based on hardware requirement, prefer smaller n to precision */
d4906093 612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 613 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
2177832f 622 intel_clock(dev, refclk, &clock);
1b894b59
CW		 623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
d4906093 625 continue;
1b894b59
CW		 626
627 this_err = abs(clock.dot - target);
d4906093
ML		 628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
2c07245f
ZW		 638 return found;
639}
640
5eb08b69 641static bool
f2b115e6
AJ		 642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
4547668a 647
5eb08b69
ZW		 648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
a4fc5ed6
KP		 666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
5eddb70b
CW		 671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
a4fc5ed6
KP		 691}
692
9d0498a2
JB		 693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 702{
9d0498a2 703 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 704 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 705
300387c0
CW		 706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
9d0498a2 722 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
9d0498a2
JB		 726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
ab7ad7f6
KP		 729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
ab7ad7f6
KP		 738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
58e10eb9 744 *
9d0498a2 745 */
58e10eb9 746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 749
750 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 751 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 752
753 /* Wait for the Pipe State to go off */
58e10eb9
CW		 754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
ab7ad7f6
KP		 756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
58e10eb9 759 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
58e10eb9 764 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 765 mdelay(5);
58e10eb9 766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
79e53945
JB		 771}
772
b24e7179
JB		 773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
040484af
JB		 796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
ea0760cf
JB		 874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 900 pipe_name(pipe));
ea0760cf
JB		 901}
902
63d7bbe9
JB		 903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
b24e7179
JB		 905{
906 int reg;
907 u32 val;
63d7bbe9 908 bool cur_state;
b24e7179
JB		 909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
63d7bbe9
JB		 912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 915 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 916}
63d7bbe9
JB		 917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 930 plane_name(plane));
b24e7179
JB		 931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
19ec1358
JB		 940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
b24e7179
JB		 944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
b24e7179
JB		 953 }
954}
955
92f2584a
JB		 956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
92f2584a
JB		 980}
981
f0575e92
KP		 982static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
983 int reg, u32 port_sel, u32 val)
984{
985 if ((val & DP_PORT_EN) == 0)
986 return false;
987
988 if (HAS_PCH_CPT(dev_priv->dev)) {
989 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
990 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
991 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
992 return false;
993 } else {
994 if ((val & DP_PIPE_MASK) != (pipe << 30))
995 return false;
996 }
997 return true;
998}
999
291906f1 1000static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1001 enum pipe pipe, int reg, u32 port_sel)
291906f1 1002{
47a05eca 1003 u32 val = I915_READ(reg);
f0575e92 1004 WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
291906f1 1005 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1006 reg, pipe_name(pipe));
291906f1
JB		 1007}
1008
1009static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, int reg)
1011{
47a05eca
JB		 1012 u32 val = I915_READ(reg);
1013 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 reg, pipe_name(pipe));
291906f1
JB		 1016}
1017
1018static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe)
1020{
1021 int reg;
1022 u32 val;
291906f1 1023
f0575e92
KP		 1024 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1025 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1026 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1027
1028 reg = PCH_ADPA;
1029 val = I915_READ(reg);
47a05eca 1030 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1031 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1032 pipe_name(pipe));
291906f1
JB		 1033
1034 reg = PCH_LVDS;
1035 val = I915_READ(reg);
47a05eca 1036 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1037 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1038 pipe_name(pipe));
291906f1
JB		 1039
1040 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1041 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1042 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1043}
1044
63d7bbe9
JB		 1045/**
1046 * intel_enable_pll - enable a PLL
1047 * @dev_priv: i915 private structure
1048 * @pipe: pipe PLL to enable
1049 *
1050 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1051 * make sure the PLL reg is writable first though, since the panel write
1052 * protect mechanism may be enabled.
1053 *
1054 * Note! This is for pre-ILK only.
1055 */
1056static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1057{
1058 int reg;
1059 u32 val;
1060
1061 /* No really, not for ILK+ */
1062 BUG_ON(dev_priv->info->gen >= 5);
1063
1064 /* PLL is protected by panel, make sure we can write it */
1065 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1066 assert_panel_unlocked(dev_priv, pipe);
1067
1068 reg = DPLL(pipe);
1069 val = I915_READ(reg);
1070 val |= DPLL_VCO_ENABLE;
1071
1072 /* We do this three times for luck */
1073 I915_WRITE(reg, val);
1074 POSTING_READ(reg);
1075 udelay(150); /* wait for warmup */
1076 I915_WRITE(reg, val);
1077 POSTING_READ(reg);
1078 udelay(150); /* wait for warmup */
1079 I915_WRITE(reg, val);
1080 POSTING_READ(reg);
1081 udelay(150); /* wait for warmup */
1082}
1083
1084/**
1085 * intel_disable_pll - disable a PLL
1086 * @dev_priv: i915 private structure
1087 * @pipe: pipe PLL to disable
1088 *
1089 * Disable the PLL for @pipe, making sure the pipe is off first.
1090 *
1091 * Note! This is for pre-ILK only.
1092 */
1093static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1094{
1095 int reg;
1096 u32 val;
1097
1098 /* Don't disable pipe A or pipe A PLLs if needed */
1099 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1100 return;
1101
1102 /* Make sure the pipe isn't still relying on us */
1103 assert_pipe_disabled(dev_priv, pipe);
1104
1105 reg = DPLL(pipe);
1106 val = I915_READ(reg);
1107 val &= ~DPLL_VCO_ENABLE;
1108 I915_WRITE(reg, val);
1109 POSTING_READ(reg);
1110}
1111
92f2584a
JB		 1112/**
1113 * intel_enable_pch_pll - enable PCH PLL
1114 * @dev_priv: i915 private structure
1115 * @pipe: pipe PLL to enable
1116 *
1117 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1118 * drives the transcoder clock.
1119 */
1120static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe)
1122{
1123 int reg;
1124 u32 val;
1125
1126 /* PCH only available on ILK+ */
1127 BUG_ON(dev_priv->info->gen < 5);
1128
1129 /* PCH refclock must be enabled first */
1130 assert_pch_refclk_enabled(dev_priv);
1131
1132 reg = PCH_DPLL(pipe);
1133 val = I915_READ(reg);
1134 val |= DPLL_VCO_ENABLE;
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(200);
1138}
1139
1140static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* PCH only available on ILK+ */
1147 BUG_ON(dev_priv->info->gen < 5);
1148
1149 /* Make sure transcoder isn't still depending on us */
1150 assert_transcoder_disabled(dev_priv, pipe);
1151
1152 reg = PCH_DPLL(pipe);
1153 val = I915_READ(reg);
1154 val &= ~DPLL_VCO_ENABLE;
1155 I915_WRITE(reg, val);
1156 POSTING_READ(reg);
1157 udelay(200);
1158}
1159
040484af
JB		 1160static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162{
1163 int reg;
1164 u32 val;
1165
1166 /* PCH only available on ILK+ */
1167 BUG_ON(dev_priv->info->gen < 5);
1168
1169 /* Make sure PCH DPLL is enabled */
1170 assert_pch_pll_enabled(dev_priv, pipe);
1171
1172 /* FDI must be feeding us bits for PCH ports */
1173 assert_fdi_tx_enabled(dev_priv, pipe);
1174 assert_fdi_rx_enabled(dev_priv, pipe);
1175
1176 reg = TRANSCONF(pipe);
1177 val = I915_READ(reg);
1178 /*
1179 * make the BPC in transcoder be consistent with
1180 * that in pipeconf reg.
1181 */
1182 val &= ~PIPE_BPC_MASK;
1183 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1184 I915_WRITE(reg, val | TRANS_ENABLE);
1185 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1186 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1187}
1188
1189static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191{
1192 int reg;
1193 u32 val;
1194
1195 /* FDI relies on the transcoder */
1196 assert_fdi_tx_disabled(dev_priv, pipe);
1197 assert_fdi_rx_disabled(dev_priv, pipe);
1198
291906f1
JB		 1199 /* Ports must be off as well */
1200 assert_pch_ports_disabled(dev_priv, pipe);
1201
040484af
JB		 1202 reg = TRANSCONF(pipe);
1203 val = I915_READ(reg);
1204 val &= ~TRANS_ENABLE;
1205 I915_WRITE(reg, val);
1206 /* wait for PCH transcoder off, transcoder state */
1207 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1208 DRM_ERROR("failed to disable transcoder\n");
1209}
1210
b24e7179 1211/**
309cfea8 1212 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1213 * @dev_priv: i915 private structure
1214 * @pipe: pipe to enable
040484af 1215 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1216 *
1217 * Enable @pipe, making sure that various hardware specific requirements
1218 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1219 *
1220 * @pipe should be %PIPE_A or %PIPE_B.
1221 *
1222 * Will wait until the pipe is actually running (i.e. first vblank) before
1223 * returning.
1224 */
040484af
JB		 1225static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1226 bool pch_port)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
1230
1231 /*
1232 * A pipe without a PLL won't actually be able to drive bits from
1233 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1234 * need the check.
1235 */
1236 if (!HAS_PCH_SPLIT(dev_priv->dev))
1237 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1238 else {
1239 if (pch_port) {
1240 /* if driving the PCH, we need FDI enabled */
1241 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1242 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1243 }
1244 /* FIXME: assert CPU port conditions for SNB+ */
1245 }
b24e7179
JB		 1246
1247 reg = PIPECONF(pipe);
1248 val = I915_READ(reg);
00d70b15
CW		 1249 if (val & PIPECONF_ENABLE)
1250 return;
1251
1252 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1253 intel_wait_for_vblank(dev_priv->dev, pipe);
1254}
1255
1256/**
309cfea8 1257 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1258 * @dev_priv: i915 private structure
1259 * @pipe: pipe to disable
1260 *
1261 * Disable @pipe, making sure that various hardware specific requirements
1262 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1263 *
1264 * @pipe should be %PIPE_A or %PIPE_B.
1265 *
1266 * Will wait until the pipe has shut down before returning.
1267 */
1268static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1269 enum pipe pipe)
1270{
1271 int reg;
1272 u32 val;
1273
1274 /*
1275 * Make sure planes won't keep trying to pump pixels to us,
1276 * or we might hang the display.
1277 */
1278 assert_planes_disabled(dev_priv, pipe);
1279
1280 /* Don't disable pipe A or pipe A PLLs if needed */
1281 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1282 return;
1283
1284 reg = PIPECONF(pipe);
1285 val = I915_READ(reg);
00d70b15
CW		 1286 if ((val & PIPECONF_ENABLE) == 0)
1287 return;
1288
1289 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1290 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1291}
1292
1293/**
1294 * intel_enable_plane - enable a display plane on a given pipe
1295 * @dev_priv: i915 private structure
1296 * @plane: plane to enable
1297 * @pipe: pipe being fed
1298 *
1299 * Enable @plane on @pipe, making sure that @pipe is running first.
1300 */
1301static void intel_enable_plane(struct drm_i915_private *dev_priv,
1302 enum plane plane, enum pipe pipe)
1303{
1304 int reg;
1305 u32 val;
1306
1307 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1308 assert_pipe_enabled(dev_priv, pipe);
1309
1310 reg = DSPCNTR(plane);
1311 val = I915_READ(reg);
00d70b15
CW		 1312 if (val & DISPLAY_PLANE_ENABLE)
1313 return;
1314
1315 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1316 intel_wait_for_vblank(dev_priv->dev, pipe);
1317}
1318
1319/*
1320 * Plane regs are double buffered, going from enabled->disabled needs a
1321 * trigger in order to latch. The display address reg provides this.
1322 */
1323static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1324 enum plane plane)
1325{
1326 u32 reg = DSPADDR(plane);
1327 I915_WRITE(reg, I915_READ(reg));
1328}
1329
1330/**
1331 * intel_disable_plane - disable a display plane
1332 * @dev_priv: i915 private structure
1333 * @plane: plane to disable
1334 * @pipe: pipe consuming the data
1335 *
1336 * Disable @plane; should be an independent operation.
1337 */
1338static void intel_disable_plane(struct drm_i915_private *dev_priv,
1339 enum plane plane, enum pipe pipe)
1340{
1341 int reg;
1342 u32 val;
1343
1344 reg = DSPCNTR(plane);
1345 val = I915_READ(reg);
00d70b15
CW		 1346 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1347 return;
1348
1349 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1350 intel_flush_display_plane(dev_priv, plane);
1351 intel_wait_for_vblank(dev_priv->dev, pipe);
1352}
1353
47a05eca 1354static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1355 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1356{
1357 u32 val = I915_READ(reg);
f0575e92
KP		 1358 if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1359 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1360 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1361 }
47a05eca
JB		 1362}
1363
1364static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1365 enum pipe pipe, int reg)
1366{
1367 u32 val = I915_READ(reg);
f0575e92
KP		 1368 if (HDMI_PIPE_ENABLED(val, pipe)) {
1369 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1370 reg, pipe);
47a05eca 1371 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1372 }
47a05eca
JB		 1373}
1374
1375/* Disable any ports connected to this transcoder */
1376static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378{
1379 u32 reg, val;
1380
1381 val = I915_READ(PCH_PP_CONTROL);
1382 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1383
f0575e92
KP		 1384 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1385 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1386 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1387
1388 reg = PCH_ADPA;
1389 val = I915_READ(reg);
1390 if (ADPA_PIPE_ENABLED(val, pipe))
1391 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1392
1393 reg = PCH_LVDS;
1394 val = I915_READ(reg);
1395 if (LVDS_PIPE_ENABLED(val, pipe)) {
1396 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1397 POSTING_READ(reg);
1398 udelay(100);
1399 }
1400
1401 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1402 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1403 disable_pch_hdmi(dev_priv, pipe, HDMID);
1404}
1405
80824003
JB		 1406static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1407{
1408 struct drm_device *dev = crtc->dev;
1409 struct drm_i915_private *dev_priv = dev->dev_private;
1410 struct drm_framebuffer *fb = crtc->fb;
1411 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1412 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1414 int plane, i;
1415 u32 fbc_ctl, fbc_ctl2;
1416
bed4a673 1417 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1418 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1419 intel_crtc->plane == dev_priv->cfb_plane &&
1420 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1421 return;
1422
1423 i8xx_disable_fbc(dev);
1424
80824003
JB		 1425 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1426
1427 if (fb->pitch < dev_priv->cfb_pitch)
1428 dev_priv->cfb_pitch = fb->pitch;
1429
1430 /* FBC_CTL wants 64B units */
1431 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1432 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1433 dev_priv->cfb_plane = intel_crtc->plane;
1434 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1435
1436 /* Clear old tags */
1437 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1438 I915_WRITE(FBC_TAG + (i * 4), 0);
1439
1440 /* Set it up... */
1441 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1442 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1443 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1444 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1445 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1446
1447 /* enable it... */
1448 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1449 if (IS_I945GM(dev))
49677901 1450 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1451 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1452 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1453 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1454 fbc_ctl |= dev_priv->cfb_fence;
1455 I915_WRITE(FBC_CONTROL, fbc_ctl);
1456
28c97730 1457 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1458 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1459}
1460
1461void i8xx_disable_fbc(struct drm_device *dev)
1462{
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 u32 fbc_ctl;
1465
1466 /* Disable compression */
1467 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1468 if ((fbc_ctl & FBC_CTL_EN) == 0)
1469 return;
1470
80824003
JB		 1471 fbc_ctl &= ~FBC_CTL_EN;
1472 I915_WRITE(FBC_CONTROL, fbc_ctl);
1473
1474 /* Wait for compressing bit to clear */
481b6af3 1475 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1476 DRM_DEBUG_KMS("FBC idle timed out\n");
1477 return;
9517a92f 1478 }
80824003 1479
28c97730 1480 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1481}
1482
ee5382ae 1483static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1484{
80824003
JB		 1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486
1487 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1488}
1489
74dff282
JB		 1490static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1491{
1492 struct drm_device *dev = crtc->dev;
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494 struct drm_framebuffer *fb = crtc->fb;
1495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1496 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1498 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1499 unsigned long stall_watermark = 200;
1500 u32 dpfc_ctl;
1501
bed4a673
CW		 1502 dpfc_ctl = I915_READ(DPFC_CONTROL);
1503 if (dpfc_ctl & DPFC_CTL_EN) {
1504 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1505 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1506 dev_priv->cfb_plane == intel_crtc->plane &&
1507 dev_priv->cfb_y == crtc->y)
1508 return;
1509
1510 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1511 intel_wait_for_vblank(dev, intel_crtc->pipe);
1512 }
1513
74dff282 1514 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1515 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1516 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1517 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1518
1519 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1520 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1521 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1522 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1523 } else {
1524 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1525 }
1526
74dff282
JB		 1527 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1528 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1529 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1530 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1531
1532 /* enable it... */
1533 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1534
28c97730 1535 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1536}
1537
1538void g4x_disable_fbc(struct drm_device *dev)
1539{
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541 u32 dpfc_ctl;
1542
1543 /* Disable compression */
1544 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1545 if (dpfc_ctl & DPFC_CTL_EN) {
1546 dpfc_ctl &= ~DPFC_CTL_EN;
1547 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1548
bed4a673
CW		 1549 DRM_DEBUG_KMS("disabled FBC\n");
1550 }
74dff282
JB		 1551}
1552
ee5382ae 1553static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1554{
74dff282
JB		 1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556
1557 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1558}
1559
4efe0708
JB		 1560static void sandybridge_blit_fbc_update(struct drm_device *dev)
1561{
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 u32 blt_ecoskpd;
1564
1565 /* Make sure blitter notifies FBC of writes */
fcca7926 1566 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1567 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1568 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1569 GEN6_BLITTER_LOCK_SHIFT;
1570 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1571 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1572 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1573 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1574 GEN6_BLITTER_LOCK_SHIFT);
1575 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1576 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1577 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1578}
1579
b52eb4dc
ZY		 1580static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1581{
1582 struct drm_device *dev = crtc->dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 struct drm_framebuffer *fb = crtc->fb;
1585 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1586 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1588 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1589 unsigned long stall_watermark = 200;
1590 u32 dpfc_ctl;
1591
bed4a673
CW		 1592 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1593 if (dpfc_ctl & DPFC_CTL_EN) {
1594 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1595 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1596 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1597 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1598 dev_priv->cfb_y == crtc->y)
1599 return;
1600
1601 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1602 intel_wait_for_vblank(dev, intel_crtc->pipe);
1603 }
1604
b52eb4dc 1605 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1606 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1607 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1608 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1609 dev_priv->cfb_y = crtc->y;
b52eb4dc 1610
b52eb4dc
ZY		 1611 dpfc_ctl &= DPFC_RESERVED;
1612 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1613 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1614 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1615 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1616 } else {
1617 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1618 }
1619
b52eb4dc
ZY		 1620 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1624 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1625 /* enable it... */
bed4a673 1626 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1627
9c04f015
YL		 1628 if (IS_GEN6(dev)) {
1629 I915_WRITE(SNB_DPFC_CTL_SA,
1630 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1631 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1632 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1633 }
1634
b52eb4dc
ZY		 1635 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636}
1637
1638void ironlake_disable_fbc(struct drm_device *dev)
1639{
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 u32 dpfc_ctl;
1642
1643 /* Disable compression */
1644 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1645 if (dpfc_ctl & DPFC_CTL_EN) {
1646 dpfc_ctl &= ~DPFC_CTL_EN;
1647 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1648
bed4a673
CW		 1649 DRM_DEBUG_KMS("disabled FBC\n");
1650 }
b52eb4dc
ZY		 1651}
1652
1653static bool ironlake_fbc_enabled(struct drm_device *dev)
1654{
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658}
1659
ee5382ae
AJ		 1660bool intel_fbc_enabled(struct drm_device *dev)
1661{
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664 if (!dev_priv->display.fbc_enabled)
1665 return false;
1666
1667 return dev_priv->display.fbc_enabled(dev);
1668}
1669
1670void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671{
1672 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1673
1674 if (!dev_priv->display.enable_fbc)
1675 return;
1676
1677 dev_priv->display.enable_fbc(crtc, interval);
1678}
1679
1680void intel_disable_fbc(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.disable_fbc)
1685 return;
1686
1687 dev_priv->display.disable_fbc(dev);
1688}
1689
80824003
JB		 1690/**
1691 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1692 * @dev: the drm_device
80824003
JB		 1693 *
1694 * Set up the framebuffer compression hardware at mode set time. We
1695 * enable it if possible:
1696 * - plane A only (on pre-965)
1697 * - no pixel mulitply/line duplication
1698 * - no alpha buffer discard
1699 * - no dual wide
1700 * - framebuffer <= 2048 in width, 1536 in height
1701 *
1702 * We can't assume that any compression will take place (worst case),
1703 * so the compressed buffer has to be the same size as the uncompressed
1704 * one. It also must reside (along with the line length buffer) in
1705 * stolen memory.
1706 *
1707 * We need to enable/disable FBC on a global basis.
1708 */
bed4a673 1709static void intel_update_fbc(struct drm_device *dev)
80824003 1710{
80824003 1711 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1712 struct drm_crtc *crtc = NULL, *tmp_crtc;
1713 struct intel_crtc *intel_crtc;
1714 struct drm_framebuffer *fb;
80824003 1715 struct intel_framebuffer *intel_fb;
05394f39 1716 struct drm_i915_gem_object *obj;
9c928d16
JB		 1717
1718 DRM_DEBUG_KMS("\n");
80824003
JB		 1719
1720 if (!i915_powersave)
1721 return;
1722
ee5382ae 1723 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1724 return;
1725
80824003
JB		 1726 /*
1727 * If FBC is already on, we just have to verify that we can
1728 * keep it that way...
1729 * Need to disable if:
9c928d16 1730 * - more than one pipe is active
80824003
JB		 1731 * - changing FBC params (stride, fence, mode)
1732 * - new fb is too large to fit in compressed buffer
1733 * - going to an unsupported config (interlace, pixel multiply, etc.)
1734 */
9c928d16 1735 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1736 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1737 if (crtc) {
1738 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1739 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1740 goto out_disable;
1741 }
1742 crtc = tmp_crtc;
1743 }
9c928d16 1744 }
bed4a673
CW		 1745
1746 if (!crtc || crtc->fb == NULL) {
1747 DRM_DEBUG_KMS("no output, disabling\n");
1748 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1749 goto out_disable;
1750 }
bed4a673
CW		 1751
1752 intel_crtc = to_intel_crtc(crtc);
1753 fb = crtc->fb;
1754 intel_fb = to_intel_framebuffer(fb);
05394f39 1755 obj = intel_fb->obj;
bed4a673 1756
c1a9f047
JB		 1757 if (!i915_enable_fbc) {
1758 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1759 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1760 goto out_disable;
1761 }
05394f39 1762 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1763 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1764 "compression\n");
b5e50c3f 1765 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1766 goto out_disable;
1767 }
bed4a673
CW		 1768 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1769 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1770 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1771 "disabling\n");
b5e50c3f 1772 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1773 goto out_disable;
1774 }
bed4a673
CW		 1775 if ((crtc->mode.hdisplay > 2048) ||
1776 (crtc->mode.vdisplay > 1536)) {
28c97730 1777 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1778 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1779 goto out_disable;
1780 }
bed4a673 1781 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1782 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1783 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1784 goto out_disable;
1785 }
05394f39 1786 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1787 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1788 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1789 goto out_disable;
1790 }
1791
c924b934
JW		 1792 /* If the kernel debugger is active, always disable compression */
1793 if (in_dbg_master())
1794 goto out_disable;
1795
bed4a673 1796 intel_enable_fbc(crtc, 500);
80824003
JB		 1797 return;
1798
1799out_disable:
80824003 1800 /* Multiple disables should be harmless */
a939406f
CW		 1801 if (intel_fbc_enabled(dev)) {
1802 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1803 intel_disable_fbc(dev);
a939406f 1804 }
80824003
JB		 1805}
1806
127bd2ac 1807int
48b956c5 1808intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1809 struct drm_i915_gem_object *obj,
919926ae 1810 struct intel_ring_buffer *pipelined)
6b95a207 1811{
ce453d81 1812 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1813 u32 alignment;
1814 int ret;
1815
05394f39 1816 switch (obj->tiling_mode) {
6b95a207 1817 case I915_TILING_NONE:
534843da
CW		 1818 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1819 alignment = 128 * 1024;
a6c45cf0 1820 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1821 alignment = 4 * 1024;
1822 else
1823 alignment = 64 * 1024;
6b95a207
KH		 1824 break;
1825 case I915_TILING_X:
1826 /* pin() will align the object as required by fence */
1827 alignment = 0;
1828 break;
1829 case I915_TILING_Y:
1830 /* FIXME: Is this true? */
1831 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1832 return -EINVAL;
1833 default:
1834 BUG();
1835 }
1836
ce453d81 1837 dev_priv->mm.interruptible = false;
75e9e915 1838 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1839 if (ret)
ce453d81 1840 goto err_interruptible;
6b95a207 1841
48b956c5
CW		 1842 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1843 if (ret)
1844 goto err_unpin;
7213342d 1845
6b95a207
KH		 1846 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1847 * fence, whereas 965+ only requires a fence if using
1848 * framebuffer compression. For simplicity, we always install
1849 * a fence as the cost is not that onerous.
1850 */
05394f39 1851 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1852 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1853 if (ret)
1854 goto err_unpin;
6b95a207
KH		 1855 }
1856
ce453d81 1857 dev_priv->mm.interruptible = true;
6b95a207 1858 return 0;
48b956c5
CW		 1859
1860err_unpin:
1861 i915_gem_object_unpin(obj);
ce453d81
CW		 1862err_interruptible:
1863 dev_priv->mm.interruptible = true;
48b956c5 1864 return ret;
6b95a207
KH		 1865}
1866
81255565
JB		 1867/* Assume fb object is pinned & idle & fenced and just update base pointers */
1868static int
1869intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1870 int x, int y, enum mode_set_atomic state)
81255565
JB		 1871{
1872 struct drm_device *dev = crtc->dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1875 struct intel_framebuffer *intel_fb;
05394f39 1876 struct drm_i915_gem_object *obj;
81255565
JB		 1877 int plane = intel_crtc->plane;
1878 unsigned long Start, Offset;
81255565 1879 u32 dspcntr;
5eddb70b 1880 u32 reg;
81255565
JB		 1881
1882 switch (plane) {
1883 case 0:
1884 case 1:
1885 break;
1886 default:
1887 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1888 return -EINVAL;
1889 }
1890
1891 intel_fb = to_intel_framebuffer(fb);
1892 obj = intel_fb->obj;
81255565 1893
5eddb70b
CW		 1894 reg = DSPCNTR(plane);
1895 dspcntr = I915_READ(reg);
81255565
JB		 1896 /* Mask out pixel format bits in case we change it */
1897 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1898 switch (fb->bits_per_pixel) {
1899 case 8:
1900 dspcntr |= DISPPLANE_8BPP;
1901 break;
1902 case 16:
1903 if (fb->depth == 15)
1904 dspcntr |= DISPPLANE_15_16BPP;
1905 else
1906 dspcntr |= DISPPLANE_16BPP;
1907 break;
1908 case 24:
1909 case 32:
1910 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1911 break;
1912 default:
1913 DRM_ERROR("Unknown color depth\n");
1914 return -EINVAL;
1915 }
a6c45cf0 1916 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1917 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1918 dspcntr |= DISPPLANE_TILED;
1919 else
1920 dspcntr &= ~DISPPLANE_TILED;
1921 }
1922
4e6cfefc 1923 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1924 /* must disable */
1925 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1926
5eddb70b 1927 I915_WRITE(reg, dspcntr);
81255565 1928
05394f39 1929 Start = obj->gtt_offset;
81255565
JB		 1930 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1931
4e6cfefc
CW		 1932 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1933 Start, Offset, x, y, fb->pitch);
5eddb70b 1934 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1935 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1936 I915_WRITE(DSPSURF(plane), Start);
1937 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1938 I915_WRITE(DSPADDR(plane), Offset);
1939 } else
1940 I915_WRITE(DSPADDR(plane), Start + Offset);
1941 POSTING_READ(reg);
81255565 1942
bed4a673 1943 intel_update_fbc(dev);
3dec0095 1944 intel_increase_pllclock(crtc);
81255565
JB		 1945
1946 return 0;
1947}
1948
5c3b82e2 1949static int
3c4fdcfb
KH		 1950intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1951 struct drm_framebuffer *old_fb)
79e53945
JB		 1952{
1953 struct drm_device *dev = crtc->dev;
79e53945
JB		 1954 struct drm_i915_master_private *master_priv;
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1956 int ret;
79e53945
JB		 1957
1958 /* no fb bound */
1959 if (!crtc->fb) {
28c97730 1960 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1961 return 0;
1962 }
1963
265db958 1964 switch (intel_crtc->plane) {
5c3b82e2
CW		 1965 case 0:
1966 case 1:
1967 break;
1968 default:
5c3b82e2 1969 return -EINVAL;
79e53945
JB		 1970 }
1971
5c3b82e2 1972 mutex_lock(&dev->struct_mutex);
265db958
CW		 1973 ret = intel_pin_and_fence_fb_obj(dev,
1974 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1975 NULL);
5c3b82e2
CW		 1976 if (ret != 0) {
1977 mutex_unlock(&dev->struct_mutex);
1978 return ret;
1979 }
79e53945 1980
265db958 1981 if (old_fb) {
e6c3a2a6 1982 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1983 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1984
e6c3a2a6 1985 wait_event(dev_priv->pending_flip_queue,
01eec727 1986 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1987 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1988
1989 /* Big Hammer, we also need to ensure that any pending
1990 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1991 * current scanout is retired before unpinning the old
1992 * framebuffer.
01eec727
CW		 1993 *
1994 * This should only fail upon a hung GPU, in which case we
1995 * can safely continue.
85345517 1996 */
ce453d81 1997 ret = i915_gem_object_flush_gpu(obj);
01eec727 1998 (void) ret;
265db958
CW		 1999 }
2000
21c74a8e
JW		 2001 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2002 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2003 if (ret) {
265db958 2004 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2005 mutex_unlock(&dev->struct_mutex);
4e6cfefc 2006 return ret;
79e53945 2007 }
3c4fdcfb 2008
b7f1de28
CW		 2009 if (old_fb) {
2010 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2011 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2012 }
652c393a 2013
5c3b82e2 2014 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2015
2016 if (!dev->primary->master)
5c3b82e2 2017 return 0;
79e53945
JB		 2018
2019 master_priv = dev->primary->master->driver_priv;
2020 if (!master_priv->sarea_priv)
5c3b82e2 2021 return 0;
79e53945 2022
265db958 2023 if (intel_crtc->pipe) {
79e53945
JB		 2024 master_priv->sarea_priv->pipeB_x = x;
2025 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2026 } else {
2027 master_priv->sarea_priv->pipeA_x = x;
2028 master_priv->sarea_priv->pipeA_y = y;
79e53945 2029 }
5c3b82e2
CW		 2030
2031 return 0;
79e53945
JB		 2032}
2033
5eddb70b 2034static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2035{
2036 struct drm_device *dev = crtc->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 u32 dpa_ctl;
2039
28c97730 2040 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2041 dpa_ctl = I915_READ(DP_A);
2042 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2043
2044 if (clock < 200000) {
2045 u32 temp;
2046 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2047 /* workaround for 160Mhz:
2048 1) program 0x4600c bits 15:0 = 0x8124
2049 2) program 0x46010 bit 0 = 1
2050 3) program 0x46034 bit 24 = 1
2051 4) program 0x64000 bit 14 = 1
2052 */
2053 temp = I915_READ(0x4600c);
2054 temp &= 0xffff0000;
2055 I915_WRITE(0x4600c, temp | 0x8124);
2056
2057 temp = I915_READ(0x46010);
2058 I915_WRITE(0x46010, temp | 1);
2059
2060 temp = I915_READ(0x46034);
2061 I915_WRITE(0x46034, temp | (1 << 24));
2062 } else {
2063 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2064 }
2065 I915_WRITE(DP_A, dpa_ctl);
2066
5eddb70b 2067 POSTING_READ(DP_A);
32f9d658
ZW		 2068 udelay(500);
2069}
2070
5e84e1a4
ZW		 2071static void intel_fdi_normal_train(struct drm_crtc *crtc)
2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2076 int pipe = intel_crtc->pipe;
2077 u32 reg, temp;
2078
2079 /* enable normal train */
2080 reg = FDI_TX_CTL(pipe);
2081 temp = I915_READ(reg);
61e499bf 2082 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2083 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2084 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2085 } else {
2086 temp &= ~FDI_LINK_TRAIN_NONE;
2087 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2088 }
5e84e1a4
ZW		 2089 I915_WRITE(reg, temp);
2090
2091 reg = FDI_RX_CTL(pipe);
2092 temp = I915_READ(reg);
2093 if (HAS_PCH_CPT(dev)) {
2094 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2095 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2096 } else {
2097 temp &= ~FDI_LINK_TRAIN_NONE;
2098 temp |= FDI_LINK_TRAIN_NONE;
2099 }
2100 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2101
2102 /* wait one idle pattern time */
2103 POSTING_READ(reg);
2104 udelay(1000);
357555c0
JB		 2105
2106 /* IVB wants error correction enabled */
2107 if (IS_IVYBRIDGE(dev))
2108 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2109 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2110}
2111
8db9d77b
ZW		 2112/* The FDI link training functions for ILK/Ibexpeak. */
2113static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2114{
2115 struct drm_device *dev = crtc->dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2118 int pipe = intel_crtc->pipe;
0fc932b8 2119 int plane = intel_crtc->plane;
5eddb70b 2120 u32 reg, temp, tries;
8db9d77b 2121
0fc932b8
JB		 2122 /* FDI needs bits from pipe & plane first */
2123 assert_pipe_enabled(dev_priv, pipe);
2124 assert_plane_enabled(dev_priv, plane);
2125
e1a44743
AJ		 2126 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2127 for train result */
5eddb70b
CW		 2128 reg = FDI_RX_IMR(pipe);
2129 temp = I915_READ(reg);
e1a44743
AJ		 2130 temp &= ~FDI_RX_SYMBOL_LOCK;
2131 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2132 I915_WRITE(reg, temp);
2133 I915_READ(reg);
e1a44743
AJ		 2134 udelay(150);
2135
8db9d77b 2136 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2137 reg = FDI_TX_CTL(pipe);
2138 temp = I915_READ(reg);
77ffb597
AJ		 2139 temp &= ~(7 << 19);
2140 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2141 temp &= ~FDI_LINK_TRAIN_NONE;
2142 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2143 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2144
5eddb70b
CW		 2145 reg = FDI_RX_CTL(pipe);
2146 temp = I915_READ(reg);
8db9d77b
ZW		 2147 temp &= ~FDI_LINK_TRAIN_NONE;
2148 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2149 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2150
2151 POSTING_READ(reg);
8db9d77b
ZW		 2152 udelay(150);
2153
5b2adf89 2154 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2155 if (HAS_PCH_IBX(dev)) {
2156 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2157 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2158 FDI_RX_PHASE_SYNC_POINTER_EN);
2159 }
5b2adf89 2160
5eddb70b 2161 reg = FDI_RX_IIR(pipe);
e1a44743 2162 for (tries = 0; tries < 5; tries++) {
5eddb70b 2163 temp = I915_READ(reg);
8db9d77b
ZW		 2164 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2165
2166 if ((temp & FDI_RX_BIT_LOCK)) {
2167 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2168 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2169 break;
2170 }
8db9d77b 2171 }
e1a44743 2172 if (tries == 5)
5eddb70b 2173 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2174
2175 /* Train 2 */
5eddb70b
CW		 2176 reg = FDI_TX_CTL(pipe);
2177 temp = I915_READ(reg);
8db9d77b
ZW		 2178 temp &= ~FDI_LINK_TRAIN_NONE;
2179 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2180 I915_WRITE(reg, temp);
8db9d77b 2181
5eddb70b
CW		 2182 reg = FDI_RX_CTL(pipe);
2183 temp = I915_READ(reg);
8db9d77b
ZW		 2184 temp &= ~FDI_LINK_TRAIN_NONE;
2185 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2186 I915_WRITE(reg, temp);
8db9d77b 2187
5eddb70b
CW		 2188 POSTING_READ(reg);
2189 udelay(150);
8db9d77b 2190
5eddb70b 2191 reg = FDI_RX_IIR(pipe);
e1a44743 2192 for (tries = 0; tries < 5; tries++) {
5eddb70b 2193 temp = I915_READ(reg);
8db9d77b
ZW		 2194 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2195
2196 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2197 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2198 DRM_DEBUG_KMS("FDI train 2 done.\n");
2199 break;
2200 }
8db9d77b 2201 }
e1a44743 2202 if (tries == 5)
5eddb70b 2203 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2204
2205 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2206
8db9d77b
ZW		 2207}
2208
311bd68e 2209static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2210 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2211 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2212 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2213 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2214};
2215
2216/* The FDI link training functions for SNB/Cougarpoint. */
2217static void gen6_fdi_link_train(struct drm_crtc *crtc)
2218{
2219 struct drm_device *dev = crtc->dev;
2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2222 int pipe = intel_crtc->pipe;
5eddb70b 2223 u32 reg, temp, i;
8db9d77b 2224
e1a44743
AJ		 2225 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2226 for train result */
5eddb70b
CW		 2227 reg = FDI_RX_IMR(pipe);
2228 temp = I915_READ(reg);
e1a44743
AJ		 2229 temp &= ~FDI_RX_SYMBOL_LOCK;
2230 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2231 I915_WRITE(reg, temp);
2232
2233 POSTING_READ(reg);
e1a44743
AJ		 2234 udelay(150);
2235
8db9d77b 2236 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2237 reg = FDI_TX_CTL(pipe);
2238 temp = I915_READ(reg);
77ffb597
AJ		 2239 temp &= ~(7 << 19);
2240 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2241 temp &= ~FDI_LINK_TRAIN_NONE;
2242 temp |= FDI_LINK_TRAIN_PATTERN_1;
2243 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2244 /* SNB-B */
2245 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2246 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2247
5eddb70b
CW		 2248 reg = FDI_RX_CTL(pipe);
2249 temp = I915_READ(reg);
8db9d77b
ZW		 2250 if (HAS_PCH_CPT(dev)) {
2251 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2252 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2253 } else {
2254 temp &= ~FDI_LINK_TRAIN_NONE;
2255 temp |= FDI_LINK_TRAIN_PATTERN_1;
2256 }
5eddb70b
CW		 2257 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2258
2259 POSTING_READ(reg);
8db9d77b
ZW		 2260 udelay(150);
2261
8db9d77b 2262 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2263 reg = FDI_TX_CTL(pipe);
2264 temp = I915_READ(reg);
8db9d77b
ZW		 2265 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2266 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2267 I915_WRITE(reg, temp);
2268
2269 POSTING_READ(reg);
8db9d77b
ZW		 2270 udelay(500);
2271
5eddb70b
CW		 2272 reg = FDI_RX_IIR(pipe);
2273 temp = I915_READ(reg);
8db9d77b
ZW		 2274 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2275
2276 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2277 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2278 DRM_DEBUG_KMS("FDI train 1 done.\n");
2279 break;
2280 }
2281 }
2282 if (i == 4)
5eddb70b 2283 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2284
2285 /* Train 2 */
5eddb70b
CW		 2286 reg = FDI_TX_CTL(pipe);
2287 temp = I915_READ(reg);
8db9d77b
ZW		 2288 temp &= ~FDI_LINK_TRAIN_NONE;
2289 temp |= FDI_LINK_TRAIN_PATTERN_2;
2290 if (IS_GEN6(dev)) {
2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 /* SNB-B */
2293 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2294 }
5eddb70b 2295 I915_WRITE(reg, temp);
8db9d77b 2296
5eddb70b
CW		 2297 reg = FDI_RX_CTL(pipe);
2298 temp = I915_READ(reg);
8db9d77b
ZW		 2299 if (HAS_PCH_CPT(dev)) {
2300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2301 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2302 } else {
2303 temp &= ~FDI_LINK_TRAIN_NONE;
2304 temp |= FDI_LINK_TRAIN_PATTERN_2;
2305 }
5eddb70b
CW		 2306 I915_WRITE(reg, temp);
2307
2308 POSTING_READ(reg);
8db9d77b
ZW		 2309 udelay(150);
2310
2311 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2312 reg = FDI_TX_CTL(pipe);
2313 temp = I915_READ(reg);
8db9d77b
ZW		 2314 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2315 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2316 I915_WRITE(reg, temp);
2317
2318 POSTING_READ(reg);
8db9d77b
ZW		 2319 udelay(500);
2320
5eddb70b
CW		 2321 reg = FDI_RX_IIR(pipe);
2322 temp = I915_READ(reg);
8db9d77b
ZW		 2323 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2324
2325 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2326 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2327 DRM_DEBUG_KMS("FDI train 2 done.\n");
2328 break;
2329 }
2330 }
2331 if (i == 4)
5eddb70b 2332 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2333
2334 DRM_DEBUG_KMS("FDI train done.\n");
2335}
2336
357555c0
JB		 2337/* Manual link training for Ivy Bridge A0 parts */
2338static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2339{
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343 int pipe = intel_crtc->pipe;
2344 u32 reg, temp, i;
2345
2346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2347 for train result */
2348 reg = FDI_RX_IMR(pipe);
2349 temp = I915_READ(reg);
2350 temp &= ~FDI_RX_SYMBOL_LOCK;
2351 temp &= ~FDI_RX_BIT_LOCK;
2352 I915_WRITE(reg, temp);
2353
2354 POSTING_READ(reg);
2355 udelay(150);
2356
2357 /* enable CPU FDI TX and PCH FDI RX */
2358 reg = FDI_TX_CTL(pipe);
2359 temp = I915_READ(reg);
2360 temp &= ~(7 << 19);
2361 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2362 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2363 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2364 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2365 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2366 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2367
2368 reg = FDI_RX_CTL(pipe);
2369 temp = I915_READ(reg);
2370 temp &= ~FDI_LINK_TRAIN_AUTO;
2371 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2372 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2373 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2374
2375 POSTING_READ(reg);
2376 udelay(150);
2377
2378 for (i = 0; i < 4; i++ ) {
2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
2381 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2382 temp |= snb_b_fdi_train_param[i];
2383 I915_WRITE(reg, temp);
2384
2385 POSTING_READ(reg);
2386 udelay(500);
2387
2388 reg = FDI_RX_IIR(pipe);
2389 temp = I915_READ(reg);
2390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392 if (temp & FDI_RX_BIT_LOCK ||
2393 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2394 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2395 DRM_DEBUG_KMS("FDI train 1 done.\n");
2396 break;
2397 }
2398 }
2399 if (i == 4)
2400 DRM_ERROR("FDI train 1 fail!\n");
2401
2402 /* Train 2 */
2403 reg = FDI_TX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2406 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2407 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2408 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2409 I915_WRITE(reg, temp);
2410
2411 reg = FDI_RX_CTL(pipe);
2412 temp = I915_READ(reg);
2413 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2415 I915_WRITE(reg, temp);
2416
2417 POSTING_READ(reg);
2418 udelay(150);
2419
2420 for (i = 0; i < 4; i++ ) {
2421 reg = FDI_TX_CTL(pipe);
2422 temp = I915_READ(reg);
2423 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2424 temp |= snb_b_fdi_train_param[i];
2425 I915_WRITE(reg, temp);
2426
2427 POSTING_READ(reg);
2428 udelay(500);
2429
2430 reg = FDI_RX_IIR(pipe);
2431 temp = I915_READ(reg);
2432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434 if (temp & FDI_RX_SYMBOL_LOCK) {
2435 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2436 DRM_DEBUG_KMS("FDI train 2 done.\n");
2437 break;
2438 }
2439 }
2440 if (i == 4)
2441 DRM_ERROR("FDI train 2 fail!\n");
2442
2443 DRM_DEBUG_KMS("FDI train done.\n");
2444}
2445
2446static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2447{
2448 struct drm_device *dev = crtc->dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 int pipe = intel_crtc->pipe;
5eddb70b 2452 u32 reg, temp;
79e53945 2453
c64e311e 2454 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2455 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2456 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2457
c98e9dcf 2458 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2459 reg = FDI_RX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2462 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2463 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2464 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2465
2466 POSTING_READ(reg);
c98e9dcf
JB		 2467 udelay(200);
2468
2469 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2470 temp = I915_READ(reg);
2471 I915_WRITE(reg, temp | FDI_PCDCLK);
2472
2473 POSTING_READ(reg);
c98e9dcf
JB		 2474 udelay(200);
2475
2476 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2477 reg = FDI_TX_CTL(pipe);
2478 temp = I915_READ(reg);
c98e9dcf 2479 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2480 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2481
2482 POSTING_READ(reg);
c98e9dcf 2483 udelay(100);
6be4a607 2484 }
0e23b99d
JB		 2485}
2486
0fc932b8
JB		 2487static void ironlake_fdi_disable(struct drm_crtc *crtc)
2488{
2489 struct drm_device *dev = crtc->dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2492 int pipe = intel_crtc->pipe;
2493 u32 reg, temp;
2494
2495 /* disable CPU FDI tx and PCH FDI rx */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2499 POSTING_READ(reg);
2500
2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
2503 temp &= ~(0x7 << 16);
2504 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2505 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
2508 udelay(100);
2509
2510 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2511 if (HAS_PCH_IBX(dev)) {
2512 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2513 I915_WRITE(FDI_RX_CHICKEN(pipe),
2514 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2515 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2516 }
0fc932b8
JB		 2517
2518 /* still set train pattern 1 */
2519 reg = FDI_TX_CTL(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~FDI_LINK_TRAIN_NONE;
2522 temp |= FDI_LINK_TRAIN_PATTERN_1;
2523 I915_WRITE(reg, temp);
2524
2525 reg = FDI_RX_CTL(pipe);
2526 temp = I915_READ(reg);
2527 if (HAS_PCH_CPT(dev)) {
2528 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2529 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2530 } else {
2531 temp &= ~FDI_LINK_TRAIN_NONE;
2532 temp |= FDI_LINK_TRAIN_PATTERN_1;
2533 }
2534 /* BPC in FDI rx is consistent with that in PIPECONF */
2535 temp &= ~(0x07 << 16);
2536 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2537 I915_WRITE(reg, temp);
2538
2539 POSTING_READ(reg);
2540 udelay(100);
2541}
2542
6b383a7f
CW		 2543/*
2544 * When we disable a pipe, we need to clear any pending scanline wait events
2545 * to avoid hanging the ring, which we assume we are waiting on.
2546 */
2547static void intel_clear_scanline_wait(struct drm_device *dev)
2548{
2549 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2550 struct intel_ring_buffer *ring;
6b383a7f
CW		 2551 u32 tmp;
2552
2553 if (IS_GEN2(dev))
2554 /* Can't break the hang on i8xx */
2555 return;
2556
1ec14ad3 2557 ring = LP_RING(dev_priv);
8168bd48
CW		 2558 tmp = I915_READ_CTL(ring);
2559 if (tmp & RING_WAIT)
2560 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2561}
2562
e6c3a2a6
CW		 2563static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2564{
05394f39 2565 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2566 struct drm_i915_private *dev_priv;
2567
2568 if (crtc->fb == NULL)
2569 return;
2570
05394f39 2571 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2572 dev_priv = crtc->dev->dev_private;
2573 wait_event(dev_priv->pending_flip_queue,
05394f39 2574 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2575}
2576
040484af
JB		 2577static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2578{
2579 struct drm_device *dev = crtc->dev;
2580 struct drm_mode_config *mode_config = &dev->mode_config;
2581 struct intel_encoder *encoder;
2582
2583 /*
2584 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2585 * must be driven by its own crtc; no sharing is possible.
2586 */
2587 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2588 if (encoder->base.crtc != crtc)
2589 continue;
2590
2591 switch (encoder->type) {
2592 case INTEL_OUTPUT_EDP:
2593 if (!intel_encoder_is_pch_edp(&encoder->base))
2594 return false;
2595 continue;
2596 }
2597 }
2598
2599 return true;
2600}
2601
f67a559d
JB		 2602/*
2603 * Enable PCH resources required for PCH ports:
2604 * - PCH PLLs
2605 * - FDI training & RX/TX
2606 * - update transcoder timings
2607 * - DP transcoding bits
2608 * - transcoder
2609 */
2610static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2611{
2612 struct drm_device *dev = crtc->dev;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615 int pipe = intel_crtc->pipe;
5eddb70b 2616 u32 reg, temp;
2c07245f 2617
c98e9dcf 2618 /* For PCH output, training FDI link */
674cf967 2619 dev_priv->display.fdi_link_train(crtc);
2c07245f 2620
92f2584a 2621 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2622
c98e9dcf
JB		 2623 if (HAS_PCH_CPT(dev)) {
2624 /* Be sure PCH DPLL SEL is set */
2625 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2626 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2627 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2628 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2629 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2630 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2631 }
5eddb70b 2632
d9b6cb56
JB		 2633 /* set transcoder timing, panel must allow it */
2634 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2635 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2636 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2637 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2638
5eddb70b
CW		 2639 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2640 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2641 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2642
5e84e1a4
ZW		 2643 intel_fdi_normal_train(crtc);
2644
c98e9dcf
JB		 2645 /* For PCH DP, enable TRANS_DP_CTL */
2646 if (HAS_PCH_CPT(dev) &&
2647 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2648 reg = TRANS_DP_CTL(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2651 TRANS_DP_SYNC_MASK |
2652 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2653 temp |= (TRANS_DP_OUTPUT_ENABLE |
2654 TRANS_DP_ENH_FRAMING);
220cad3c 2655 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2656
2657 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2658 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2659 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2660 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2661
2662 switch (intel_trans_dp_port_sel(crtc)) {
2663 case PCH_DP_B:
5eddb70b 2664 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2665 break;
2666 case PCH_DP_C:
5eddb70b 2667 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2668 break;
2669 case PCH_DP_D:
5eddb70b 2670 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2671 break;
2672 default:
2673 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2674 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2675 break;
32f9d658 2676 }
2c07245f 2677
5eddb70b 2678 I915_WRITE(reg, temp);
6be4a607 2679 }
b52eb4dc 2680
040484af 2681 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2682}
2683
2684static void ironlake_crtc_enable(struct drm_crtc *crtc)
2685{
2686 struct drm_device *dev = crtc->dev;
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2689 int pipe = intel_crtc->pipe;
2690 int plane = intel_crtc->plane;
2691 u32 temp;
2692 bool is_pch_port;
2693
2694 if (intel_crtc->active)
2695 return;
2696
2697 intel_crtc->active = true;
2698 intel_update_watermarks(dev);
2699
2700 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2701 temp = I915_READ(PCH_LVDS);
2702 if ((temp & LVDS_PORT_EN) == 0)
2703 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2704 }
2705
2706 is_pch_port = intel_crtc_driving_pch(crtc);
2707
2708 if (is_pch_port)
357555c0 2709 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2710 else
2711 ironlake_fdi_disable(crtc);
2712
2713 /* Enable panel fitting for LVDS */
2714 if (dev_priv->pch_pf_size &&
2715 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2716 /* Force use of hard-coded filter coefficients
2717 * as some pre-programmed values are broken,
2718 * e.g. x201.
2719 */
9db4a9c7
JB		 2720 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2721 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2722 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2723 }
2724
9c54c0dd
JB		 2725 /*
2726 * On ILK+ LUT must be loaded before the pipe is running but with
2727 * clocks enabled
2728 */
2729 intel_crtc_load_lut(crtc);
2730
f67a559d
JB		 2731 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2732 intel_enable_plane(dev_priv, plane, pipe);
2733
2734 if (is_pch_port)
2735 ironlake_pch_enable(crtc);
c98e9dcf 2736
d1ebd816 2737 mutex_lock(&dev->struct_mutex);
bed4a673 2738 intel_update_fbc(dev);
d1ebd816
BW		 2739 mutex_unlock(&dev->struct_mutex);
2740
6b383a7f 2741 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2742}
2743
2744static void ironlake_crtc_disable(struct drm_crtc *crtc)
2745{
2746 struct drm_device *dev = crtc->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2749 int pipe = intel_crtc->pipe;
2750 int plane = intel_crtc->plane;
5eddb70b 2751 u32 reg, temp;
b52eb4dc 2752
f7abfe8b
CW		 2753 if (!intel_crtc->active)
2754 return;
2755
e6c3a2a6 2756 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2757 drm_vblank_off(dev, pipe);
6b383a7f 2758 intel_crtc_update_cursor(crtc, false);
5eddb70b 2759
b24e7179 2760 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2761
6be4a607
JB		 2762 if (dev_priv->cfb_plane == plane &&
2763 dev_priv->display.disable_fbc)
2764 dev_priv->display.disable_fbc(dev);
2c07245f 2765
b24e7179 2766 intel_disable_pipe(dev_priv, pipe);
32f9d658 2767
6be4a607 2768 /* Disable PF */
9db4a9c7
JB		 2769 I915_WRITE(PF_CTL(pipe), 0);
2770 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2771
0fc932b8 2772 ironlake_fdi_disable(crtc);
2c07245f 2773
47a05eca
JB		 2774 /* This is a horrible layering violation; we should be doing this in
2775 * the connector/encoder ->prepare instead, but we don't always have
2776 * enough information there about the config to know whether it will
2777 * actually be necessary or just cause undesired flicker.
2778 */
2779 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2780
040484af 2781 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2782
6be4a607
JB		 2783 if (HAS_PCH_CPT(dev)) {
2784 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2785 reg = TRANS_DP_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2788 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2789 I915_WRITE(reg, temp);
6be4a607
JB		 2790
2791 /* disable DPLL_SEL */
2792 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2793 switch (pipe) {
2794 case 0:
2795 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2796 break;
2797 case 1:
6be4a607 2798 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2799 break;
2800 case 2:
2801 /* FIXME: manage transcoder PLLs? */
2802 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2803 break;
2804 default:
2805 BUG(); /* wtf */
2806 }
6be4a607 2807 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2808 }
e3421a18 2809
6be4a607 2810 /* disable PCH DPLL */
92f2584a 2811 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2812
6be4a607 2813 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2817
6be4a607 2818 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
6be4a607 2824 udelay(100);
8db9d77b 2825
5eddb70b
CW		 2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2829
6be4a607 2830 /* Wait for the clocks to turn off. */
5eddb70b 2831 POSTING_READ(reg);
6be4a607 2832 udelay(100);
6b383a7f 2833
f7abfe8b 2834 intel_crtc->active = false;
6b383a7f 2835 intel_update_watermarks(dev);
d1ebd816
BW		 2836
2837 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2838 intel_update_fbc(dev);
2839 intel_clear_scanline_wait(dev);
d1ebd816 2840 mutex_unlock(&dev->struct_mutex);
6be4a607 2841}
1b3c7a47 2842
6be4a607
JB		 2843static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2844{
2845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2846 int pipe = intel_crtc->pipe;
2847 int plane = intel_crtc->plane;
8db9d77b 2848
6be4a607
JB		 2849 /* XXX: When our outputs are all unaware of DPMS modes other than off
2850 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2851 */
2852 switch (mode) {
2853 case DRM_MODE_DPMS_ON:
2854 case DRM_MODE_DPMS_STANDBY:
2855 case DRM_MODE_DPMS_SUSPEND:
2856 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2857 ironlake_crtc_enable(crtc);
2858 break;
1b3c7a47 2859
6be4a607
JB		 2860 case DRM_MODE_DPMS_OFF:
2861 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2862 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2863 break;
2864 }
2865}
2866
02e792fb
DV		 2867static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2868{
02e792fb 2869 if (!enable && intel_crtc->overlay) {
23f09ce3 2870 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2871 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2872
23f09ce3 2873 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2874 dev_priv->mm.interruptible = false;
2875 (void) intel_overlay_switch_off(intel_crtc->overlay);
2876 dev_priv->mm.interruptible = true;
23f09ce3 2877 mutex_unlock(&dev->struct_mutex);
02e792fb 2878 }
02e792fb 2879
5dcdbcb0
CW		 2880 /* Let userspace switch the overlay on again. In most cases userspace
2881 * has to recompute where to put it anyway.
2882 */
02e792fb
DV		 2883}
2884
0b8765c6 2885static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2886{
2887 struct drm_device *dev = crtc->dev;
79e53945
JB		 2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890 int pipe = intel_crtc->pipe;
80824003 2891 int plane = intel_crtc->plane;
79e53945 2892
f7abfe8b
CW		 2893 if (intel_crtc->active)
2894 return;
2895
2896 intel_crtc->active = true;
6b383a7f
CW		 2897 intel_update_watermarks(dev);
2898
63d7bbe9 2899 intel_enable_pll(dev_priv, pipe);
040484af 2900 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2901 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2902
0b8765c6 2903 intel_crtc_load_lut(crtc);
bed4a673 2904 intel_update_fbc(dev);
79e53945 2905
0b8765c6
JB		 2906 /* Give the overlay scaler a chance to enable if it's on this pipe */
2907 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2908 intel_crtc_update_cursor(crtc, true);
0b8765c6 2909}
79e53945 2910
0b8765c6
JB		 2911static void i9xx_crtc_disable(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2916 int pipe = intel_crtc->pipe;
2917 int plane = intel_crtc->plane;
b690e96c 2918
f7abfe8b
CW		 2919 if (!intel_crtc->active)
2920 return;
2921
0b8765c6 2922 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2923 intel_crtc_wait_for_pending_flips(crtc);
2924 drm_vblank_off(dev, pipe);
0b8765c6 2925 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2926 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2927
2928 if (dev_priv->cfb_plane == plane &&
2929 dev_priv->display.disable_fbc)
2930 dev_priv->display.disable_fbc(dev);
79e53945 2931
b24e7179 2932 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2933 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2934 intel_disable_pll(dev_priv, pipe);
0b8765c6 2935
f7abfe8b 2936 intel_crtc->active = false;
6b383a7f
CW		 2937 intel_update_fbc(dev);
2938 intel_update_watermarks(dev);
2939 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2940}
2941
2942static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2943{
2944 /* XXX: When our outputs are all unaware of DPMS modes other than off
2945 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2946 */
2947 switch (mode) {
2948 case DRM_MODE_DPMS_ON:
2949 case DRM_MODE_DPMS_STANDBY:
2950 case DRM_MODE_DPMS_SUSPEND:
2951 i9xx_crtc_enable(crtc);
2952 break;
2953 case DRM_MODE_DPMS_OFF:
2954 i9xx_crtc_disable(crtc);
79e53945
JB		 2955 break;
2956 }
2c07245f
ZW		 2957}
2958
2959/**
2960 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2961 */
2962static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2963{
2964 struct drm_device *dev = crtc->dev;
e70236a8 2965 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2966 struct drm_i915_master_private *master_priv;
2967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2968 int pipe = intel_crtc->pipe;
2969 bool enabled;
2970
032d2a0d
CW		 2971 if (intel_crtc->dpms_mode == mode)
2972 return;
2973
65655d4a 2974 intel_crtc->dpms_mode = mode;
debcaddc 2975
e70236a8 2976 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2977
2978 if (!dev->primary->master)
2979 return;
2980
2981 master_priv = dev->primary->master->driver_priv;
2982 if (!master_priv->sarea_priv)
2983 return;
2984
2985 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2986
2987 switch (pipe) {
2988 case 0:
2989 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2990 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2991 break;
2992 case 1:
2993 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2994 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2995 break;
2996 default:
9db4a9c7 2997 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2998 break;
2999 }
79e53945
JB		 3000}
3001
cdd59983
CW		 3002static void intel_crtc_disable(struct drm_crtc *crtc)
3003{
3004 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3005 struct drm_device *dev = crtc->dev;
3006
3007 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3008
3009 if (crtc->fb) {
3010 mutex_lock(&dev->struct_mutex);
3011 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3012 mutex_unlock(&dev->struct_mutex);
3013 }
3014}
3015
7e7d76c3
JB		 3016/* Prepare for a mode set.
3017 *
3018 * Note we could be a lot smarter here. We need to figure out which outputs
3019 * will be enabled, which disabled (in short, how the config will changes)
3020 * and perform the minimum necessary steps to accomplish that, e.g. updating
3021 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3022 * panel fitting is in the proper state, etc.
3023 */
3024static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3025{
7e7d76c3 3026 i9xx_crtc_disable(crtc);
79e53945
JB		 3027}
3028
7e7d76c3 3029static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3030{
7e7d76c3 3031 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3032}
3033
3034static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3035{
7e7d76c3 3036 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3037}
3038
3039static void ironlake_crtc_commit(struct drm_crtc *crtc)
3040{
7e7d76c3 3041 ironlake_crtc_enable(crtc);
79e53945
JB		 3042}
3043
3044void intel_encoder_prepare (struct drm_encoder *encoder)
3045{
3046 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3047 /* lvds has its own version of prepare see intel_lvds_prepare */
3048 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3049}
3050
3051void intel_encoder_commit (struct drm_encoder *encoder)
3052{
3053 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3054 /* lvds has its own version of commit see intel_lvds_commit */
3055 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3056}
3057
ea5b213a
CW		 3058void intel_encoder_destroy(struct drm_encoder *encoder)
3059{
4ef69c7a 3060 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3061
ea5b213a
CW		 3062 drm_encoder_cleanup(encoder);
3063 kfree(intel_encoder);
3064}
3065
79e53945
JB		 3066static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3067 struct drm_display_mode *mode,
3068 struct drm_display_mode *adjusted_mode)
3069{
2c07245f 3070 struct drm_device *dev = crtc->dev;
89749350 3071
bad720ff 3072 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3073 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3074 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3075 return false;
2c07245f 3076 }
89749350
CW		 3077
3078 /* XXX some encoders set the crtcinfo, others don't.
3079 * Obviously we need some form of conflict resolution here...
3080 */
3081 if (adjusted_mode->crtc_htotal == 0)
3082 drm_mode_set_crtcinfo(adjusted_mode, 0);
3083
79e53945
JB		 3084 return true;
3085}
3086
e70236a8
JB		 3087static int i945_get_display_clock_speed(struct drm_device *dev)
3088{
3089 return 400000;
3090}
79e53945 3091
e70236a8 3092static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3093{
e70236a8
JB		 3094 return 333000;
3095}
79e53945 3096
e70236a8
JB		 3097static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3098{
3099 return 200000;
3100}
79e53945 3101
e70236a8
JB		 3102static int i915gm_get_display_clock_speed(struct drm_device *dev)
3103{
3104 u16 gcfgc = 0;
79e53945 3105
e70236a8
JB		 3106 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3107
3108 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3109 return 133000;
3110 else {
3111 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3112 case GC_DISPLAY_CLOCK_333_MHZ:
3113 return 333000;
3114 default:
3115 case GC_DISPLAY_CLOCK_190_200_MHZ:
3116 return 190000;
79e53945 3117 }
e70236a8
JB		 3118 }
3119}
3120
3121static int i865_get_display_clock_speed(struct drm_device *dev)
3122{
3123 return 266000;
3124}
3125
3126static int i855_get_display_clock_speed(struct drm_device *dev)
3127{
3128 u16 hpllcc = 0;
3129 /* Assume that the hardware is in the high speed state. This
3130 * should be the default.
3131 */
3132 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3133 case GC_CLOCK_133_200:
3134 case GC_CLOCK_100_200:
3135 return 200000;
3136 case GC_CLOCK_166_250:
3137 return 250000;
3138 case GC_CLOCK_100_133:
79e53945 3139 return 133000;
e70236a8 3140 }
79e53945 3141
e70236a8
JB		 3142 /* Shouldn't happen */
3143 return 0;
3144}
79e53945 3145
e70236a8
JB		 3146static int i830_get_display_clock_speed(struct drm_device *dev)
3147{
3148 return 133000;
79e53945
JB		 3149}
3150
2c07245f
ZW		 3151struct fdi_m_n {
3152 u32 tu;
3153 u32 gmch_m;
3154 u32 gmch_n;
3155 u32 link_m;
3156 u32 link_n;
3157};
3158
3159static void
3160fdi_reduce_ratio(u32 *num, u32 *den)
3161{
3162 while (*num > 0xffffff || *den > 0xffffff) {
3163 *num >>= 1;
3164 *den >>= 1;
3165 }
3166}
3167
2c07245f 3168static void
f2b115e6
AJ		 3169ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3170 int link_clock, struct fdi_m_n *m_n)
2c07245f 3171{
2c07245f
ZW		 3172 m_n->tu = 64; /* default size */
3173
22ed1113
CW		 3174 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3175 m_n->gmch_m = bits_per_pixel * pixel_clock;
3176 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3177 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3178
22ed1113
CW		 3179 m_n->link_m = pixel_clock;
3180 m_n->link_n = link_clock;
2c07245f
ZW		 3181 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3182}
3183
3184
7662c8bd
SL		 3185struct intel_watermark_params {
3186 unsigned long fifo_size;
3187 unsigned long max_wm;
3188 unsigned long default_wm;
3189 unsigned long guard_size;
3190 unsigned long cacheline_size;
3191};
3192
f2b115e6 3193/* Pineview has different values for various configs */
d210246a 3194static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3195 PINEVIEW_DISPLAY_FIFO,
3196 PINEVIEW_MAX_WM,
3197 PINEVIEW_DFT_WM,
3198 PINEVIEW_GUARD_WM,
3199 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3200};
d210246a 3201static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3202 PINEVIEW_DISPLAY_FIFO,
3203 PINEVIEW_MAX_WM,
3204 PINEVIEW_DFT_HPLLOFF_WM,
3205 PINEVIEW_GUARD_WM,
3206 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3207};
d210246a 3208static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3209 PINEVIEW_CURSOR_FIFO,
3210 PINEVIEW_CURSOR_MAX_WM,
3211 PINEVIEW_CURSOR_DFT_WM,
3212 PINEVIEW_CURSOR_GUARD_WM,
3213 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3214};
d210246a 3215static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3216 PINEVIEW_CURSOR_FIFO,
3217 PINEVIEW_CURSOR_MAX_WM,
3218 PINEVIEW_CURSOR_DFT_WM,
3219 PINEVIEW_CURSOR_GUARD_WM,
3220 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3221};
d210246a 3222static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3223 G4X_FIFO_SIZE,
3224 G4X_MAX_WM,
3225 G4X_MAX_WM,
3226 2,
3227 G4X_FIFO_LINE_SIZE,
3228};
d210246a 3229static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3230 I965_CURSOR_FIFO,
3231 I965_CURSOR_MAX_WM,
3232 I965_CURSOR_DFT_WM,
3233 2,
3234 G4X_FIFO_LINE_SIZE,
3235};
d210246a 3236static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3237 I965_CURSOR_FIFO,
3238 I965_CURSOR_MAX_WM,
3239 I965_CURSOR_DFT_WM,
3240 2,
3241 I915_FIFO_LINE_SIZE,
3242};
d210246a 3243static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3244 I945_FIFO_SIZE,
7662c8bd
SL		 3245 I915_MAX_WM,
3246 1,
dff33cfc
JB		 3247 2,
3248 I915_FIFO_LINE_SIZE
7662c8bd 3249};
d210246a 3250static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3251 I915_FIFO_SIZE,
7662c8bd
SL		 3252 I915_MAX_WM,
3253 1,
dff33cfc 3254 2,
7662c8bd
SL		 3255 I915_FIFO_LINE_SIZE
3256};
d210246a 3257static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3258 I855GM_FIFO_SIZE,
3259 I915_MAX_WM,
3260 1,
dff33cfc 3261 2,
7662c8bd
SL		 3262 I830_FIFO_LINE_SIZE
3263};
d210246a 3264static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3265 I830_FIFO_SIZE,
3266 I915_MAX_WM,
3267 1,
dff33cfc 3268 2,
7662c8bd
SL		 3269 I830_FIFO_LINE_SIZE
3270};
3271
d210246a 3272static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3273 ILK_DISPLAY_FIFO,
3274 ILK_DISPLAY_MAXWM,
3275 ILK_DISPLAY_DFTWM,
3276 2,
3277 ILK_FIFO_LINE_SIZE
3278};
d210246a 3279static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3280 ILK_CURSOR_FIFO,
3281 ILK_CURSOR_MAXWM,
3282 ILK_CURSOR_DFTWM,
3283 2,
3284 ILK_FIFO_LINE_SIZE
3285};
d210246a 3286static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3287 ILK_DISPLAY_SR_FIFO,
3288 ILK_DISPLAY_MAX_SRWM,
3289 ILK_DISPLAY_DFT_SRWM,
3290 2,
3291 ILK_FIFO_LINE_SIZE
3292};
d210246a 3293static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3294 ILK_CURSOR_SR_FIFO,
3295 ILK_CURSOR_MAX_SRWM,
3296 ILK_CURSOR_DFT_SRWM,
3297 2,
3298 ILK_FIFO_LINE_SIZE
3299};
3300
d210246a 3301static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3302 SNB_DISPLAY_FIFO,
3303 SNB_DISPLAY_MAXWM,
3304 SNB_DISPLAY_DFTWM,
3305 2,
3306 SNB_FIFO_LINE_SIZE
3307};
d210246a 3308static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3309 SNB_CURSOR_FIFO,
3310 SNB_CURSOR_MAXWM,
3311 SNB_CURSOR_DFTWM,
3312 2,
3313 SNB_FIFO_LINE_SIZE
3314};
d210246a 3315static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3316 SNB_DISPLAY_SR_FIFO,
3317 SNB_DISPLAY_MAX_SRWM,
3318 SNB_DISPLAY_DFT_SRWM,
3319 2,
3320 SNB_FIFO_LINE_SIZE
3321};
d210246a 3322static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3323 SNB_CURSOR_SR_FIFO,
3324 SNB_CURSOR_MAX_SRWM,
3325 SNB_CURSOR_DFT_SRWM,
3326 2,
3327 SNB_FIFO_LINE_SIZE
3328};
3329
3330
dff33cfc
JB		 3331/**
3332 * intel_calculate_wm - calculate watermark level
3333 * @clock_in_khz: pixel clock
3334 * @wm: chip FIFO params
3335 * @pixel_size: display pixel size
3336 * @latency_ns: memory latency for the platform
3337 *
3338 * Calculate the watermark level (the level at which the display plane will
3339 * start fetching from memory again). Each chip has a different display
3340 * FIFO size and allocation, so the caller needs to figure that out and pass
3341 * in the correct intel_watermark_params structure.
3342 *
3343 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3344 * on the pixel size. When it reaches the watermark level, it'll start
3345 * fetching FIFO line sized based chunks from memory until the FIFO fills
3346 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3347 * will occur, and a display engine hang could result.
3348 */
7662c8bd 3349static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3350 const struct intel_watermark_params *wm,
3351 int fifo_size,
7662c8bd
SL		 3352 int pixel_size,
3353 unsigned long latency_ns)
3354{
390c4dd4 3355 long entries_required, wm_size;
dff33cfc 3356
d660467c
JB		 3357 /*
3358 * Note: we need to make sure we don't overflow for various clock &
3359 * latency values.
3360 * clocks go from a few thousand to several hundred thousand.
3361 * latency is usually a few thousand
3362 */
3363 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3364 1000;
8de9b311 3365 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3366
bbb0aef5 3367 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3368
d210246a 3369 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3370
bbb0aef5 3371 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3372
390c4dd4
JB		 3373 /* Don't promote wm_size to unsigned... */
3374 if (wm_size > (long)wm->max_wm)
7662c8bd 3375 wm_size = wm->max_wm;
c3add4b6 3376 if (wm_size <= 0)
7662c8bd
SL		 3377 wm_size = wm->default_wm;
3378 return wm_size;
3379}
3380
3381struct cxsr_latency {
3382 int is_desktop;
95534263 3383 int is_ddr3;
7662c8bd
SL		 3384 unsigned long fsb_freq;
3385 unsigned long mem_freq;
3386 unsigned long display_sr;
3387 unsigned long display_hpll_disable;
3388 unsigned long cursor_sr;
3389 unsigned long cursor_hpll_disable;
3390};
3391
403c89ff 3392static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3393 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3394 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3395 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3396 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3397 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3398
3399 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3400 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3401 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3402 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3403 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3404
3405 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3406 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3407 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3408 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3409 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3410
3411 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3412 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3413 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3414 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3415 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3416
3417 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3418 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3419 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3420 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3421 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3422
3423 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3424 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3425 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3426 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3427 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3428};
3429
403c89ff
CW		 3430static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3431 int is_ddr3,
3432 int fsb,
3433 int mem)
7662c8bd 3434{
403c89ff 3435 const struct cxsr_latency *latency;
7662c8bd 3436 int i;
7662c8bd
SL		 3437
3438 if (fsb == 0 || mem == 0)
3439 return NULL;
3440
3441 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3442 latency = &cxsr_latency_table[i];
3443 if (is_desktop == latency->is_desktop &&
95534263 3444 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3445 fsb == latency->fsb_freq && mem == latency->mem_freq)
3446 return latency;
7662c8bd 3447 }
decbbcda 3448
28c97730 3449 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3450
3451 return NULL;
7662c8bd
SL		 3452}
3453
f2b115e6 3454static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3455{
3456 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3457
3458 /* deactivate cxsr */
3e33d94d 3459 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3460}
3461
bcc24fb4
JB		 3462/*
3463 * Latency for FIFO fetches is dependent on several factors:
3464 * - memory configuration (speed, channels)
3465 * - chipset
3466 * - current MCH state
3467 * It can be fairly high in some situations, so here we assume a fairly
3468 * pessimal value. It's a tradeoff between extra memory fetches (if we
3469 * set this value too high, the FIFO will fetch frequently to stay full)
3470 * and power consumption (set it too low to save power and we might see
3471 * FIFO underruns and display "flicker").
3472 *
3473 * A value of 5us seems to be a good balance; safe for very low end
3474 * platforms but not overly aggressive on lower latency configs.
3475 */
69e302a9 3476static const int latency_ns = 5000;
7662c8bd 3477
e70236a8 3478static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3479{
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 uint32_t dsparb = I915_READ(DSPARB);
3482 int size;
3483
8de9b311
CW		 3484 size = dsparb & 0x7f;
3485 if (plane)
3486 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3487
28c97730 3488 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3489 plane ? "B" : "A", size);
dff33cfc
JB		 3490
3491 return size;
3492}
7662c8bd 3493
e70236a8
JB		 3494static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3495{
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 uint32_t dsparb = I915_READ(DSPARB);
3498 int size;
3499
8de9b311
CW		 3500 size = dsparb & 0x1ff;
3501 if (plane)
3502 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3503 size >>= 1; /* Convert to cachelines */
dff33cfc 3504
28c97730 3505 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3506 plane ? "B" : "A", size);
dff33cfc
JB		 3507
3508 return size;
3509}
7662c8bd 3510
e70236a8
JB		 3511static int i845_get_fifo_size(struct drm_device *dev, int plane)
3512{
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 uint32_t dsparb = I915_READ(DSPARB);
3515 int size;
3516
3517 size = dsparb & 0x7f;
3518 size >>= 2; /* Convert to cachelines */
3519
28c97730 3520 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3521 plane ? "B" : "A",
3522 size);
e70236a8
JB		 3523
3524 return size;
3525}
3526
3527static int i830_get_fifo_size(struct drm_device *dev, int plane)
3528{
3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 uint32_t dsparb = I915_READ(DSPARB);
3531 int size;
3532
3533 size = dsparb & 0x7f;
3534 size >>= 1; /* Convert to cachelines */
3535
28c97730 3536 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3537 plane ? "B" : "A", size);
e70236a8
JB		 3538
3539 return size;
3540}
3541
d210246a
CW		 3542static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3543{
3544 struct drm_crtc *crtc, *enabled = NULL;
3545
3546 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3547 if (crtc->enabled && crtc->fb) {
3548 if (enabled)
3549 return NULL;
3550 enabled = crtc;
3551 }
3552 }
3553
3554 return enabled;
3555}
3556
3557static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3558{
3559 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3560 struct drm_crtc *crtc;
403c89ff 3561 const struct cxsr_latency *latency;
d4294342
ZY		 3562 u32 reg;
3563 unsigned long wm;
d4294342 3564
403c89ff 3565 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3566 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3567 if (!latency) {
3568 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3569 pineview_disable_cxsr(dev);
3570 return;
3571 }
3572
d210246a
CW		 3573 crtc = single_enabled_crtc(dev);
3574 if (crtc) {
3575 int clock = crtc->mode.clock;
3576 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3577
3578 /* Display SR */
d210246a
CW		 3579 wm = intel_calculate_wm(clock, &pineview_display_wm,
3580 pineview_display_wm.fifo_size,
d4294342
ZY		 3581 pixel_size, latency->display_sr);
3582 reg = I915_READ(DSPFW1);
3583 reg &= ~DSPFW_SR_MASK;
3584 reg |= wm << DSPFW_SR_SHIFT;
3585 I915_WRITE(DSPFW1, reg);
3586 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3587
3588 /* cursor SR */
d210246a
CW		 3589 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3590 pineview_display_wm.fifo_size,
d4294342
ZY		 3591 pixel_size, latency->cursor_sr);
3592 reg = I915_READ(DSPFW3);
3593 reg &= ~DSPFW_CURSOR_SR_MASK;
3594 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3595 I915_WRITE(DSPFW3, reg);
3596
3597 /* Display HPLL off SR */
d210246a
CW		 3598 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3599 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3600 pixel_size, latency->display_hpll_disable);
3601 reg = I915_READ(DSPFW3);
3602 reg &= ~DSPFW_HPLL_SR_MASK;
3603 reg |= wm & DSPFW_HPLL_SR_MASK;
3604 I915_WRITE(DSPFW3, reg);
3605
3606 /* cursor HPLL off SR */
d210246a
CW		 3607 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3608 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3609 pixel_size, latency->cursor_hpll_disable);
3610 reg = I915_READ(DSPFW3);
3611 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3612 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3613 I915_WRITE(DSPFW3, reg);
3614 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3615
3616 /* activate cxsr */
3e33d94d
CW		 3617 I915_WRITE(DSPFW3,
3618 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3619 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3620 } else {
3621 pineview_disable_cxsr(dev);
3622 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3623 }
3624}
3625
417ae147
CW		 3626static bool g4x_compute_wm0(struct drm_device *dev,
3627 int plane,
3628 const struct intel_watermark_params *display,
3629 int display_latency_ns,
3630 const struct intel_watermark_params *cursor,
3631 int cursor_latency_ns,
3632 int *plane_wm,
3633 int *cursor_wm)
3634{
3635 struct drm_crtc *crtc;
3636 int htotal, hdisplay, clock, pixel_size;
3637 int line_time_us, line_count;
3638 int entries, tlb_miss;
3639
3640 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3641 if (crtc->fb == NULL || !crtc->enabled) {
3642 *cursor_wm = cursor->guard_size;
3643 *plane_wm = display->guard_size;
417ae147 3644 return false;
5c72d064 3645 }
417ae147
CW		 3646
3647 htotal = crtc->mode.htotal;
3648 hdisplay = crtc->mode.hdisplay;
3649 clock = crtc->mode.clock;
3650 pixel_size = crtc->fb->bits_per_pixel / 8;
3651
3652 /* Use the small buffer method to calculate plane watermark */
3653 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3654 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3655 if (tlb_miss > 0)
3656 entries += tlb_miss;
3657 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3658 *plane_wm = entries + display->guard_size;
3659 if (*plane_wm > (int)display->max_wm)
3660 *plane_wm = display->max_wm;
3661
3662 /* Use the large buffer method to calculate cursor watermark */
3663 line_time_us = ((htotal * 1000) / clock);
3664 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3665 entries = line_count * 64 * pixel_size;
3666 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3667 if (tlb_miss > 0)
3668 entries += tlb_miss;
3669 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3670 *cursor_wm = entries + cursor->guard_size;
3671 if (*cursor_wm > (int)cursor->max_wm)
3672 *cursor_wm = (int)cursor->max_wm;
3673
3674 return true;
3675}
3676
3677/*
3678 * Check the wm result.
3679 *
3680 * If any calculated watermark values is larger than the maximum value that
3681 * can be programmed into the associated watermark register, that watermark
3682 * must be disabled.
3683 */
3684static bool g4x_check_srwm(struct drm_device *dev,
3685 int display_wm, int cursor_wm,
3686 const struct intel_watermark_params *display,
3687 const struct intel_watermark_params *cursor)
652c393a 3688{
417ae147
CW		 3689 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3690 display_wm, cursor_wm);
652c393a 3691
417ae147 3692 if (display_wm > display->max_wm) {
bbb0aef5 3693 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3694 display_wm, display->max_wm);
3695 return false;
3696 }
0e442c60 3697
417ae147 3698 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3699 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3700 cursor_wm, cursor->max_wm);
3701 return false;
3702 }
0e442c60 3703
417ae147
CW		 3704 if (!(display_wm || cursor_wm)) {
3705 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3706 return false;
3707 }
0e442c60 3708
417ae147
CW		 3709 return true;
3710}
0e442c60 3711
417ae147 3712static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3713 int plane,
3714 int latency_ns,
417ae147
CW		 3715 const struct intel_watermark_params *display,
3716 const struct intel_watermark_params *cursor,
3717 int *display_wm, int *cursor_wm)
3718{
d210246a
CW		 3719 struct drm_crtc *crtc;
3720 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3721 unsigned long line_time_us;
3722 int line_count, line_size;
3723 int small, large;
3724 int entries;
0e442c60 3725
417ae147
CW		 3726 if (!latency_ns) {
3727 *display_wm = *cursor_wm = 0;
3728 return false;
3729 }
0e442c60 3730
d210246a
CW		 3731 crtc = intel_get_crtc_for_plane(dev, plane);
3732 hdisplay = crtc->mode.hdisplay;
3733 htotal = crtc->mode.htotal;
3734 clock = crtc->mode.clock;
3735 pixel_size = crtc->fb->bits_per_pixel / 8;
3736
417ae147
CW		 3737 line_time_us = (htotal * 1000) / clock;
3738 line_count = (latency_ns / line_time_us + 1000) / 1000;
3739 line_size = hdisplay * pixel_size;
0e442c60 3740
417ae147
CW		 3741 /* Use the minimum of the small and large buffer method for primary */
3742 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3743 large = line_count * line_size;
0e442c60 3744
417ae147
CW		 3745 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3746 *display_wm = entries + display->guard_size;
4fe5e611 3747
417ae147
CW		 3748 /* calculate the self-refresh watermark for display cursor */
3749 entries = line_count * pixel_size * 64;
3750 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3751 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3752
417ae147
CW		 3753 return g4x_check_srwm(dev,
3754 *display_wm, *cursor_wm,
3755 display, cursor);
3756}
4fe5e611 3757
7ccb4a53 3758#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3759
3760static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3761{
3762 static const int sr_latency_ns = 12000;
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3765 int plane_sr, cursor_sr;
3766 unsigned int enabled = 0;
417ae147
CW		 3767
3768 if (g4x_compute_wm0(dev, 0,
3769 &g4x_wm_info, latency_ns,
3770 &g4x_cursor_wm_info, latency_ns,
3771 &planea_wm, &cursora_wm))
d210246a 3772 enabled |= 1;
417ae147
CW		 3773
3774 if (g4x_compute_wm0(dev, 1,
3775 &g4x_wm_info, latency_ns,
3776 &g4x_cursor_wm_info, latency_ns,
3777 &planeb_wm, &cursorb_wm))
d210246a 3778 enabled |= 2;
417ae147
CW		 3779
3780 plane_sr = cursor_sr = 0;
d210246a
CW		 3781 if (single_plane_enabled(enabled) &&
3782 g4x_compute_srwm(dev, ffs(enabled) - 1,
3783 sr_latency_ns,
417ae147
CW		 3784 &g4x_wm_info,
3785 &g4x_cursor_wm_info,
3786 &plane_sr, &cursor_sr))
0e442c60 3787 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3788 else
3789 I915_WRITE(FW_BLC_SELF,
3790 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3791
308977ac
CW		 3792 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3793 planea_wm, cursora_wm,
3794 planeb_wm, cursorb_wm,
3795 plane_sr, cursor_sr);
0e442c60 3796
417ae147
CW		 3797 I915_WRITE(DSPFW1,
3798 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3799 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3800 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3801 planea_wm);
3802 I915_WRITE(DSPFW2,
3803 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3804 (cursora_wm << DSPFW_CURSORA_SHIFT));
3805 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3806 I915_WRITE(DSPFW3,
3807 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3808 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3809}
3810
d210246a 3811static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3812{
3813 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3814 struct drm_crtc *crtc;
3815 int srwm = 1;
4fe5e611 3816 int cursor_sr = 16;
1dc7546d
JB		 3817
3818 /* Calc sr entries for one plane configs */
d210246a
CW		 3819 crtc = single_enabled_crtc(dev);
3820 if (crtc) {
1dc7546d 3821 /* self-refresh has much higher latency */
69e302a9 3822 static const int sr_latency_ns = 12000;
d210246a
CW		 3823 int clock = crtc->mode.clock;
3824 int htotal = crtc->mode.htotal;
3825 int hdisplay = crtc->mode.hdisplay;
3826 int pixel_size = crtc->fb->bits_per_pixel / 8;
3827 unsigned long line_time_us;
3828 int entries;
1dc7546d 3829
d210246a 3830 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3831
3832 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3833 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3834 pixel_size * hdisplay;
3835 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3836 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3837 if (srwm < 0)
3838 srwm = 1;
1b07e04e 3839 srwm &= 0x1ff;
308977ac
CW		 3840 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3841 entries, srwm);
4fe5e611 3842
d210246a 3843 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3844 pixel_size * 64;
d210246a 3845 entries = DIV_ROUND_UP(entries,
8de9b311 3846 i965_cursor_wm_info.cacheline_size);
4fe5e611 3847 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3848 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3849
3850 if (cursor_sr > i965_cursor_wm_info.max_wm)
3851 cursor_sr = i965_cursor_wm_info.max_wm;
3852
3853 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3854 "cursor %d\n", srwm, cursor_sr);
3855
a6c45cf0 3856 if (IS_CRESTLINE(dev))
adcdbc66 3857 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3858 } else {
3859 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3860 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3861 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3862 & ~FW_BLC_SELF_EN);
1dc7546d 3863 }
7662c8bd 3864
1dc7546d
JB		 3865 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3866 srwm);
7662c8bd
SL		 3867
3868 /* 965 has limitations... */
417ae147
CW		 3869 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3870 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3871 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3872 /* update cursor SR watermark */
3873 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3874}
3875
d210246a 3876static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3877{
3878 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3879 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3880 uint32_t fwater_lo;
3881 uint32_t fwater_hi;
d210246a
CW		 3882 int cwm, srwm = 1;
3883 int fifo_size;
dff33cfc 3884 int planea_wm, planeb_wm;
d210246a 3885 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3886
72557b4f 3887 if (IS_I945GM(dev))
d210246a 3888 wm_info = &i945_wm_info;
a6c45cf0 3889 else if (!IS_GEN2(dev))
d210246a 3890 wm_info = &i915_wm_info;
7662c8bd 3891 else
d210246a
CW		 3892 wm_info = &i855_wm_info;
3893
3894 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3895 crtc = intel_get_crtc_for_plane(dev, 0);
3896 if (crtc->enabled && crtc->fb) {
3897 planea_wm = intel_calculate_wm(crtc->mode.clock,
3898 wm_info, fifo_size,
3899 crtc->fb->bits_per_pixel / 8,
3900 latency_ns);
3901 enabled = crtc;
3902 } else
3903 planea_wm = fifo_size - wm_info->guard_size;
3904
3905 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3906 crtc = intel_get_crtc_for_plane(dev, 1);
3907 if (crtc->enabled && crtc->fb) {
3908 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3909 wm_info, fifo_size,
3910 crtc->fb->bits_per_pixel / 8,
3911 latency_ns);
3912 if (enabled == NULL)
3913 enabled = crtc;
3914 else
3915 enabled = NULL;
3916 } else
3917 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3918
28c97730 3919 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3920
3921 /*
3922 * Overlay gets an aggressive default since video jitter is bad.
3923 */
3924 cwm = 2;
3925
18b2190c
AL		 3926 /* Play safe and disable self-refresh before adjusting watermarks. */
3927 if (IS_I945G(dev) || IS_I945GM(dev))
3928 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3929 else if (IS_I915GM(dev))
3930 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3931
dff33cfc 3932 /* Calc sr entries for one plane configs */
d210246a 3933 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3934 /* self-refresh has much higher latency */
69e302a9 3935 static const int sr_latency_ns = 6000;
d210246a
CW		 3936 int clock = enabled->mode.clock;
3937 int htotal = enabled->mode.htotal;
3938 int hdisplay = enabled->mode.hdisplay;
3939 int pixel_size = enabled->fb->bits_per_pixel / 8;
3940 unsigned long line_time_us;
3941 int entries;
dff33cfc 3942
d210246a 3943 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3944
3945 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3946 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3947 pixel_size * hdisplay;
3948 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3949 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3950 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3951 if (srwm < 0)
3952 srwm = 1;
ee980b80
LP		 3953
3954 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3955 I915_WRITE(FW_BLC_SELF,
3956 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3957 else if (IS_I915GM(dev))
ee980b80 3958 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3959 }
3960
28c97730 3961 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3962 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3963
dff33cfc
JB		 3964 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3965 fwater_hi = (cwm & 0x1f);
3966
3967 /* Set request length to 8 cachelines per fetch */
3968 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3969 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3970
3971 I915_WRITE(FW_BLC, fwater_lo);
3972 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3973
d210246a
CW		 3974 if (HAS_FW_BLC(dev)) {
3975 if (enabled) {
3976 if (IS_I945G(dev) || IS_I945GM(dev))
3977 I915_WRITE(FW_BLC_SELF,
3978 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3979 else if (IS_I915GM(dev))
3980 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3981 DRM_DEBUG_KMS("memory self refresh enabled\n");
3982 } else
3983 DRM_DEBUG_KMS("memory self refresh disabled\n");
3984 }
7662c8bd
SL		 3985}
3986
d210246a 3987static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3988{
3989 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3990 struct drm_crtc *crtc;
3991 uint32_t fwater_lo;
dff33cfc 3992 int planea_wm;
7662c8bd 3993
d210246a
CW		 3994 crtc = single_enabled_crtc(dev);
3995 if (crtc == NULL)
3996 return;
7662c8bd 3997
d210246a
CW		 3998 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3999 dev_priv->display.get_fifo_size(dev, 0),
4000 crtc->fb->bits_per_pixel / 8,
4001 latency_ns);
4002 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4003 fwater_lo |= (3<<8) | planea_wm;
4004
28c97730 4005 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4006
4007 I915_WRITE(FW_BLC, fwater_lo);
4008}
4009
7f8a8569 4010#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4011#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4012
1398261a
YL		 4013/*
4014 * Check the wm result.
4015 *
4016 * If any calculated watermark values is larger than the maximum value that
4017 * can be programmed into the associated watermark register, that watermark
4018 * must be disabled.
1398261a 4019 */
b79d4990
JB		 4020static bool ironlake_check_srwm(struct drm_device *dev, int level,
4021 int fbc_wm, int display_wm, int cursor_wm,
4022 const struct intel_watermark_params *display,
4023 const struct intel_watermark_params *cursor)
1398261a
YL		 4024{
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026
4027 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4028 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4029
4030 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4031 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4032 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4033
4034 /* fbc has it's own way to disable FBC WM */
4035 I915_WRITE(DISP_ARB_CTL,
4036 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4037 return false;
4038 }
4039
b79d4990 4040 if (display_wm > display->max_wm) {
1398261a 4041 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4042 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4043 return false;
4044 }
4045
b79d4990 4046 if (cursor_wm > cursor->max_wm) {
1398261a 4047 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4048 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4049 return false;
4050 }
4051
4052 if (!(fbc_wm || display_wm || cursor_wm)) {
4053 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4054 return false;
4055 }
4056
4057 return true;
4058}
4059
4060/*
4061 * Compute watermark values of WM[1-3],
4062 */
d210246a
CW		 4063static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4064 int latency_ns,
b79d4990
JB		 4065 const struct intel_watermark_params *display,
4066 const struct intel_watermark_params *cursor,
4067 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4068{
d210246a 4069 struct drm_crtc *crtc;
1398261a 4070 unsigned long line_time_us;
d210246a 4071 int hdisplay, htotal, pixel_size, clock;
b79d4990 4072 int line_count, line_size;
1398261a
YL		 4073 int small, large;
4074 int entries;
1398261a
YL		 4075
4076 if (!latency_ns) {
4077 *fbc_wm = *display_wm = *cursor_wm = 0;
4078 return false;
4079 }
4080
d210246a
CW		 4081 crtc = intel_get_crtc_for_plane(dev, plane);
4082 hdisplay = crtc->mode.hdisplay;
4083 htotal = crtc->mode.htotal;
4084 clock = crtc->mode.clock;
4085 pixel_size = crtc->fb->bits_per_pixel / 8;
4086
1398261a
YL		 4087 line_time_us = (htotal * 1000) / clock;
4088 line_count = (latency_ns / line_time_us + 1000) / 1000;
4089 line_size = hdisplay * pixel_size;
4090
4091 /* Use the minimum of the small and large buffer method for primary */
4092 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4093 large = line_count * line_size;
4094
b79d4990
JB		 4095 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4096 *display_wm = entries + display->guard_size;
1398261a
YL		 4097
4098 /*
b79d4990 4099 * Spec says:
1398261a
YL		 4100 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4101 */
4102 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4103
4104 /* calculate the self-refresh watermark for display cursor */
4105 entries = line_count * pixel_size * 64;
b79d4990
JB		 4106 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4107 *cursor_wm = entries + cursor->guard_size;
1398261a 4108
b79d4990
JB		 4109 return ironlake_check_srwm(dev, level,
4110 *fbc_wm, *display_wm, *cursor_wm,
4111 display, cursor);
4112}
4113
d210246a 4114static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4115{
4116 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4117 int fbc_wm, plane_wm, cursor_wm;
4118 unsigned int enabled;
b79d4990
JB		 4119
4120 enabled = 0;
9f405100
CW		 4121 if (g4x_compute_wm0(dev, 0,
4122 &ironlake_display_wm_info,
4123 ILK_LP0_PLANE_LATENCY,
4124 &ironlake_cursor_wm_info,
4125 ILK_LP0_CURSOR_LATENCY,
4126 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4127 I915_WRITE(WM0_PIPEA_ILK,
4128 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4129 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4130 " plane %d, " "cursor: %d\n",
4131 plane_wm, cursor_wm);
d210246a 4132 enabled |= 1;
b79d4990
JB		 4133 }
4134
9f405100
CW		 4135 if (g4x_compute_wm0(dev, 1,
4136 &ironlake_display_wm_info,
4137 ILK_LP0_PLANE_LATENCY,
4138 &ironlake_cursor_wm_info,
4139 ILK_LP0_CURSOR_LATENCY,
4140 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4141 I915_WRITE(WM0_PIPEB_ILK,
4142 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4143 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4144 " plane %d, cursor: %d\n",
4145 plane_wm, cursor_wm);
d210246a 4146 enabled |= 2;
b79d4990
JB		 4147 }
4148
4149 /*
4150 * Calculate and update the self-refresh watermark only when one
4151 * display plane is used.
4152 */
4153 I915_WRITE(WM3_LP_ILK, 0);
4154 I915_WRITE(WM2_LP_ILK, 0);
4155 I915_WRITE(WM1_LP_ILK, 0);
4156
d210246a 4157 if (!single_plane_enabled(enabled))
b79d4990 4158 return;
d210246a 4159 enabled = ffs(enabled) - 1;
b79d4990
JB		 4160
4161 /* WM1 */
d210246a
CW		 4162 if (!ironlake_compute_srwm(dev, 1, enabled,
4163 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4164 &ironlake_display_srwm_info,
4165 &ironlake_cursor_srwm_info,
4166 &fbc_wm, &plane_wm, &cursor_wm))
4167 return;
4168
4169 I915_WRITE(WM1_LP_ILK,
4170 WM1_LP_SR_EN |
4171 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4172 (fbc_wm << WM1_LP_FBC_SHIFT) |
4173 (plane_wm << WM1_LP_SR_SHIFT) |
4174 cursor_wm);
4175
4176 /* WM2 */
d210246a
CW		 4177 if (!ironlake_compute_srwm(dev, 2, enabled,
4178 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4179 &ironlake_display_srwm_info,
4180 &ironlake_cursor_srwm_info,
4181 &fbc_wm, &plane_wm, &cursor_wm))
4182 return;
4183
4184 I915_WRITE(WM2_LP_ILK,
4185 WM2_LP_EN |
4186 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4187 (fbc_wm << WM1_LP_FBC_SHIFT) |
4188 (plane_wm << WM1_LP_SR_SHIFT) |
4189 cursor_wm);
4190
4191 /*
4192 * WM3 is unsupported on ILK, probably because we don't have latency
4193 * data for that power state
4194 */
1398261a
YL		 4195}
4196
d210246a 4197static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4198{
4199 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4200 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4201 int fbc_wm, plane_wm, cursor_wm;
4202 unsigned int enabled;
1398261a
YL		 4203
4204 enabled = 0;
9f405100
CW		 4205 if (g4x_compute_wm0(dev, 0,
4206 &sandybridge_display_wm_info, latency,
4207 &sandybridge_cursor_wm_info, latency,
4208 &plane_wm, &cursor_wm)) {
1398261a
YL		 4209 I915_WRITE(WM0_PIPEA_ILK,
4210 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4211 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4212 " plane %d, " "cursor: %d\n",
4213 plane_wm, cursor_wm);
d210246a 4214 enabled |= 1;
1398261a
YL		 4215 }
4216
9f405100
CW		 4217 if (g4x_compute_wm0(dev, 1,
4218 &sandybridge_display_wm_info, latency,
4219 &sandybridge_cursor_wm_info, latency,
4220 &plane_wm, &cursor_wm)) {
1398261a
YL		 4221 I915_WRITE(WM0_PIPEB_ILK,
4222 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4223 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4224 " plane %d, cursor: %d\n",
4225 plane_wm, cursor_wm);
d210246a 4226 enabled |= 2;
1398261a
YL		 4227 }
4228
4229 /*
4230 * Calculate and update the self-refresh watermark only when one
4231 * display plane is used.
4232 *
4233 * SNB support 3 levels of watermark.
4234 *
4235 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4236 * and disabled in the descending order
4237 *
4238 */
4239 I915_WRITE(WM3_LP_ILK, 0);
4240 I915_WRITE(WM2_LP_ILK, 0);
4241 I915_WRITE(WM1_LP_ILK, 0);
4242
d210246a 4243 if (!single_plane_enabled(enabled))
1398261a 4244 return;
d210246a 4245 enabled = ffs(enabled) - 1;
1398261a
YL		 4246
4247 /* WM1 */
d210246a
CW		 4248 if (!ironlake_compute_srwm(dev, 1, enabled,
4249 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4250 &sandybridge_display_srwm_info,
4251 &sandybridge_cursor_srwm_info,
4252 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4253 return;
4254
4255 I915_WRITE(WM1_LP_ILK,
4256 WM1_LP_SR_EN |
4257 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4258 (fbc_wm << WM1_LP_FBC_SHIFT) |
4259 (plane_wm << WM1_LP_SR_SHIFT) |
4260 cursor_wm);
4261
4262 /* WM2 */
d210246a
CW		 4263 if (!ironlake_compute_srwm(dev, 2, enabled,
4264 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4265 &sandybridge_display_srwm_info,
4266 &sandybridge_cursor_srwm_info,
4267 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4268 return;
4269
4270 I915_WRITE(WM2_LP_ILK,
4271 WM2_LP_EN |
4272 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4273 (fbc_wm << WM1_LP_FBC_SHIFT) |
4274 (plane_wm << WM1_LP_SR_SHIFT) |
4275 cursor_wm);
4276
4277 /* WM3 */
d210246a
CW		 4278 if (!ironlake_compute_srwm(dev, 3, enabled,
4279 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4280 &sandybridge_display_srwm_info,
4281 &sandybridge_cursor_srwm_info,
4282 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4283 return;
4284
4285 I915_WRITE(WM3_LP_ILK,
4286 WM3_LP_EN |
4287 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4288 (fbc_wm << WM1_LP_FBC_SHIFT) |
4289 (plane_wm << WM1_LP_SR_SHIFT) |
4290 cursor_wm);
4291}
4292
7662c8bd
SL		 4293/**
4294 * intel_update_watermarks - update FIFO watermark values based on current modes
4295 *
4296 * Calculate watermark values for the various WM regs based on current mode
4297 * and plane configuration.
4298 *
4299 * There are several cases to deal with here:
4300 * - normal (i.e. non-self-refresh)
4301 * - self-refresh (SR) mode
4302 * - lines are large relative to FIFO size (buffer can hold up to 2)
4303 * - lines are small relative to FIFO size (buffer can hold more than 2
4304 * lines), so need to account for TLB latency
4305 *
4306 * The normal calculation is:
4307 * watermark = dotclock * bytes per pixel * latency
4308 * where latency is platform & configuration dependent (we assume pessimal
4309 * values here).
4310 *
4311 * The SR calculation is:
4312 * watermark = (trunc(latency/line time)+1) * surface width *
4313 * bytes per pixel
4314 * where
4315 * line time = htotal / dotclock
fa143215 4316 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4317 * and latency is assumed to be high, as above.
4318 *
4319 * The final value programmed to the register should always be rounded up,
4320 * and include an extra 2 entries to account for clock crossings.
4321 *
4322 * We don't use the sprite, so we can ignore that. And on Crestline we have
4323 * to set the non-SR watermarks to 8.
5eddb70b 4324 */
7662c8bd
SL		 4325static void intel_update_watermarks(struct drm_device *dev)
4326{
e70236a8 4327 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4328
d210246a
CW		 4329 if (dev_priv->display.update_wm)
4330 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4331}
4332
a7615030
CW		 4333static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4334{
435793df
KP		 4335 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4336 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4337}
4338
f564048e
EA		 4339static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4340 struct drm_display_mode *mode,
4341 struct drm_display_mode *adjusted_mode,
4342 int x, int y,
4343 struct drm_framebuffer *old_fb)
79e53945
JB		 4344{
4345 struct drm_device *dev = crtc->dev;
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348 int pipe = intel_crtc->pipe;
80824003 4349 int plane = intel_crtc->plane;
c751ce4f 4350 int refclk, num_connectors = 0;
652c393a 4351 intel_clock_t clock, reduced_clock;
5eddb70b 4352 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4353 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4354 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4355 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4356 struct intel_encoder *encoder;
d4906093 4357 const intel_limit_t *limit;
5c3b82e2 4358 int ret;
fae14981 4359 u32 temp;
aa9b500d 4360 u32 lvds_sync = 0;
79e53945 4361
5eddb70b
CW		 4362 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4363 if (encoder->base.crtc != crtc)
79e53945
JB		 4364 continue;
4365
5eddb70b 4366 switch (encoder->type) {
79e53945
JB		 4367 case INTEL_OUTPUT_LVDS:
4368 is_lvds = true;
4369 break;
4370 case INTEL_OUTPUT_SDVO:
7d57382e 4371 case INTEL_OUTPUT_HDMI:
79e53945 4372 is_sdvo = true;
5eddb70b 4373 if (encoder->needs_tv_clock)
e2f0ba97 4374 is_tv = true;
79e53945
JB		 4375 break;
4376 case INTEL_OUTPUT_DVO:
4377 is_dvo = true;
4378 break;
4379 case INTEL_OUTPUT_TVOUT:
4380 is_tv = true;
4381 break;
4382 case INTEL_OUTPUT_ANALOG:
4383 is_crt = true;
4384 break;
a4fc5ed6
KP		 4385 case INTEL_OUTPUT_DISPLAYPORT:
4386 is_dp = true;
4387 break;
79e53945 4388 }
43565a06 4389
c751ce4f 4390 num_connectors++;
79e53945
JB		 4391 }
4392
a7615030 4393 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4394 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4395 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4396 refclk / 1000);
a6c45cf0 4397 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4398 refclk = 96000;
4399 } else {
4400 refclk = 48000;
4401 }
4402
d4906093
ML		 4403 /*
4404 * Returns a set of divisors for the desired target clock with the given
4405 * refclk, or FALSE. The returned values represent the clock equation:
4406 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4407 */
1b894b59 4408 limit = intel_limit(crtc, refclk);
d4906093 4409 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4410 if (!ok) {
4411 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4412 return -EINVAL;
79e53945
JB		 4413 }
4414
cda4b7d3 4415 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4416 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4417
ddc9003c
ZY		 4418 if (is_lvds && dev_priv->lvds_downclock_avail) {
4419 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4420 dev_priv->lvds_downclock,
4421 refclk,
4422 &reduced_clock);
18f9ed12
ZY		 4423 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4424 /*
4425 * If the different P is found, it means that we can't
4426 * switch the display clock by using the FP0/FP1.
4427 * In such case we will disable the LVDS downclock
4428 * feature.
4429 */
4430 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4431 "LVDS clock/downclock\n");
18f9ed12
ZY		 4432 has_reduced_clock = 0;
4433 }
652c393a 4434 }
7026d4ac
ZW		 4435 /* SDVO TV has fixed PLL values depend on its clock range,
4436 this mirrors vbios setting. */
4437 if (is_sdvo && is_tv) {
4438 if (adjusted_mode->clock >= 100000
5eddb70b 4439 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4440 clock.p1 = 2;
4441 clock.p2 = 10;
4442 clock.n = 3;
4443 clock.m1 = 16;
4444 clock.m2 = 8;
4445 } else if (adjusted_mode->clock >= 140500
5eddb70b 4446 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4447 clock.p1 = 1;
4448 clock.p2 = 10;
4449 clock.n = 6;
4450 clock.m1 = 12;
4451 clock.m2 = 8;
4452 }
4453 }
4454
f2b115e6 4455 if (IS_PINEVIEW(dev)) {
2177832f 4456 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4457 if (has_reduced_clock)
4458 fp2 = (1 << reduced_clock.n) << 16 |
4459 reduced_clock.m1 << 8 | reduced_clock.m2;
4460 } else {
2177832f 4461 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4462 if (has_reduced_clock)
4463 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4464 reduced_clock.m2;
4465 }
79e53945 4466
929c77fb 4467 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4468
a6c45cf0 4469 if (!IS_GEN2(dev)) {
79e53945
JB		 4470 if (is_lvds)
4471 dpll |= DPLLB_MODE_LVDS;
4472 else
4473 dpll |= DPLLB_MODE_DAC_SERIAL;
4474 if (is_sdvo) {
6c9547ff
CW		 4475 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4476 if (pixel_multiplier > 1) {
4477 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4478 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4479 }
79e53945 4480 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4481 }
929c77fb 4482 if (is_dp)
a4fc5ed6 4483 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4484
4485 /* compute bitmask from p1 value */
f2b115e6
AJ		 4486 if (IS_PINEVIEW(dev))
4487 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4488 else {
2177832f 4489 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4490 if (IS_G4X(dev) && has_reduced_clock)
4491 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4492 }
79e53945
JB		 4493 switch (clock.p2) {
4494 case 5:
4495 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4496 break;
4497 case 7:
4498 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4499 break;
4500 case 10:
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4502 break;
4503 case 14:
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4505 break;
4506 }
929c77fb 4507 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4508 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4509 } else {
4510 if (is_lvds) {
4511 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 } else {
4513 if (clock.p1 == 2)
4514 dpll |= PLL_P1_DIVIDE_BY_TWO;
4515 else
4516 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4517 if (clock.p2 == 4)
4518 dpll |= PLL_P2_DIVIDE_BY_4;
4519 }
4520 }
4521
43565a06
KH		 4522 if (is_sdvo && is_tv)
4523 dpll |= PLL_REF_INPUT_TVCLKINBC;
4524 else if (is_tv)
79e53945 4525 /* XXX: just matching BIOS for now */
43565a06 4526 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4527 dpll |= 3;
a7615030 4528 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4529 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4530 else
4531 dpll |= PLL_REF_INPUT_DREFCLK;
4532
4533 /* setup pipeconf */
5eddb70b 4534 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4535
4536 /* Set up the display plane register */
4537 dspcntr = DISPPLANE_GAMMA_ENABLE;
4538
f2b115e6 4539 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4540 enable color space conversion */
929c77fb
EA		 4541 if (pipe == 0)
4542 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4543 else
4544 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4545
a6c45cf0 4546 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4547 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4548 * core speed.
4549 *
4550 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4551 * pipe == 0 check?
4552 */
e70236a8
JB		 4553 if (mode->clock >
4554 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4555 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4556 else
5eddb70b 4557 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4558 }
4559
929c77fb 4560 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4561
28c97730 4562 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4563 drm_mode_debug_printmodeline(mode);
4564
fae14981
EA		 4565 I915_WRITE(FP0(pipe), fp);
4566 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4567
fae14981 4568 POSTING_READ(DPLL(pipe));
c713bb08 4569 udelay(150);
8db9d77b 4570
79e53945
JB		 4571 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4572 * This is an exception to the general rule that mode_set doesn't turn
4573 * things on.
4574 */
4575 if (is_lvds) {
fae14981 4576 temp = I915_READ(LVDS);
5eddb70b 4577 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4578 if (pipe == 1) {
929c77fb 4579 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4580 } else {
929c77fb 4581 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4582 }
a3e17eb8 4583 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4584 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4585 /* Set the B0-B3 data pairs corresponding to whether we're going to
4586 * set the DPLLs for dual-channel mode or not.
4587 */
4588 if (clock.p2 == 7)
5eddb70b 4589 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4590 else
5eddb70b 4591 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4592
4593 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4594 * appropriately here, but we need to look more thoroughly into how
4595 * panels behave in the two modes.
4596 */
929c77fb
EA		 4597 /* set the dithering flag on LVDS as needed */
4598 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4599 if (dev_priv->lvds_dither)
5eddb70b 4600 temp |= LVDS_ENABLE_DITHER;
434ed097 4601 else
5eddb70b 4602 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4603 }
aa9b500d
BF		 4604 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4605 lvds_sync |= LVDS_HSYNC_POLARITY;
4606 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4607 lvds_sync |= LVDS_VSYNC_POLARITY;
4608 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4609 != lvds_sync) {
4610 char flags[2] = "-+";
4611 DRM_INFO("Changing LVDS panel from "
4612 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4613 flags[!(temp & LVDS_HSYNC_POLARITY)],
4614 flags[!(temp & LVDS_VSYNC_POLARITY)],
4615 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4616 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4617 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4618 temp |= lvds_sync;
4619 }
fae14981 4620 I915_WRITE(LVDS, temp);
79e53945 4621 }
434ed097 4622
929c77fb 4623 if (is_dp) {
a4fc5ed6 4624 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4625 }
4626
fae14981 4627 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4628
c713bb08 4629 /* Wait for the clocks to stabilize. */
fae14981 4630 POSTING_READ(DPLL(pipe));
c713bb08 4631 udelay(150);
32f9d658 4632
c713bb08
EA		 4633 if (INTEL_INFO(dev)->gen >= 4) {
4634 temp = 0;
4635 if (is_sdvo) {
4636 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4637 if (temp > 1)
4638 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4639 else
4640 temp = 0;
32f9d658 4641 }
c713bb08
EA		 4642 I915_WRITE(DPLL_MD(pipe), temp);
4643 } else {
4644 /* The pixel multiplier can only be updated once the
4645 * DPLL is enabled and the clocks are stable.
4646 *
4647 * So write it again.
4648 */
fae14981 4649 I915_WRITE(DPLL(pipe), dpll);
79e53945 4650 }
79e53945 4651
5eddb70b 4652 intel_crtc->lowfreq_avail = false;
652c393a 4653 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4654 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4655 intel_crtc->lowfreq_avail = true;
4656 if (HAS_PIPE_CXSR(dev)) {
28c97730 4657 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4658 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4659 }
4660 } else {
fae14981 4661 I915_WRITE(FP1(pipe), fp);
652c393a 4662 if (HAS_PIPE_CXSR(dev)) {
28c97730 4663 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4664 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4665 }
4666 }
4667
734b4157
KH		 4668 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4669 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4670 /* the chip adds 2 halflines automatically */
4671 adjusted_mode->crtc_vdisplay -= 1;
4672 adjusted_mode->crtc_vtotal -= 1;
4673 adjusted_mode->crtc_vblank_start -= 1;
4674 adjusted_mode->crtc_vblank_end -= 1;
4675 adjusted_mode->crtc_vsync_end -= 1;
4676 adjusted_mode->crtc_vsync_start -= 1;
4677 } else
4678 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4679
5eddb70b
CW		 4680 I915_WRITE(HTOTAL(pipe),
4681 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4682 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4683 I915_WRITE(HBLANK(pipe),
4684 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4685 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4686 I915_WRITE(HSYNC(pipe),
4687 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4688 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4689
4690 I915_WRITE(VTOTAL(pipe),
4691 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4692 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4693 I915_WRITE(VBLANK(pipe),
4694 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4695 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4696 I915_WRITE(VSYNC(pipe),
4697 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4698 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4699
4700 /* pipesrc and dspsize control the size that is scaled from,
4701 * which should always be the user's requested size.
79e53945 4702 */
929c77fb
EA		 4703 I915_WRITE(DSPSIZE(plane),
4704 ((mode->vdisplay - 1) << 16) |
4705 (mode->hdisplay - 1));
4706 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4707 I915_WRITE(PIPESRC(pipe),
4708 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4709
f564048e
EA		 4710 I915_WRITE(PIPECONF(pipe), pipeconf);
4711 POSTING_READ(PIPECONF(pipe));
929c77fb 4712 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4713
4714 intel_wait_for_vblank(dev, pipe);
4715
f564048e
EA		 4716 I915_WRITE(DSPCNTR(plane), dspcntr);
4717 POSTING_READ(DSPCNTR(plane));
efc2924e 4718 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4719
4720 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4721
4722 intel_update_watermarks(dev);
4723
f564048e
EA		 4724 return ret;
4725}
4726
4727static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4728 struct drm_display_mode *mode,
4729 struct drm_display_mode *adjusted_mode,
4730 int x, int y,
4731 struct drm_framebuffer *old_fb)
79e53945
JB		 4732{
4733 struct drm_device *dev = crtc->dev;
4734 struct drm_i915_private *dev_priv = dev->dev_private;
4735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4736 int pipe = intel_crtc->pipe;
80824003 4737 int plane = intel_crtc->plane;
c751ce4f 4738 int refclk, num_connectors = 0;
652c393a 4739 intel_clock_t clock, reduced_clock;
5eddb70b 4740 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4741 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4742 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4743 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4744 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4745 struct intel_encoder *encoder;
d4906093 4746 const intel_limit_t *limit;
5c3b82e2 4747 int ret;
2c07245f 4748 struct fdi_m_n m_n = {0};
fae14981 4749 u32 temp;
aa9b500d 4750 u32 lvds_sync = 0;
8febb297 4751 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4752
5eddb70b
CW		 4753 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4754 if (encoder->base.crtc != crtc)
79e53945
JB		 4755 continue;
4756
5eddb70b 4757 switch (encoder->type) {
79e53945
JB		 4758 case INTEL_OUTPUT_LVDS:
4759 is_lvds = true;
4760 break;
4761 case INTEL_OUTPUT_SDVO:
7d57382e 4762 case INTEL_OUTPUT_HDMI:
79e53945 4763 is_sdvo = true;
5eddb70b 4764 if (encoder->needs_tv_clock)
e2f0ba97 4765 is_tv = true;
79e53945 4766 break;
79e53945
JB		 4767 case INTEL_OUTPUT_TVOUT:
4768 is_tv = true;
4769 break;
4770 case INTEL_OUTPUT_ANALOG:
4771 is_crt = true;
4772 break;
a4fc5ed6
KP		 4773 case INTEL_OUTPUT_DISPLAYPORT:
4774 is_dp = true;
4775 break;
32f9d658 4776 case INTEL_OUTPUT_EDP:
5eddb70b 4777 has_edp_encoder = encoder;
32f9d658 4778 break;
79e53945 4779 }
43565a06 4780
c751ce4f 4781 num_connectors++;
79e53945
JB		 4782 }
4783
a7615030 4784 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4785 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4786 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4787 refclk / 1000);
a07d6787 4788 } else {
79e53945 4789 refclk = 96000;
8febb297
EA		 4790 if (!has_edp_encoder ||
4791 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4792 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4793 }
4794
d4906093
ML		 4795 /*
4796 * Returns a set of divisors for the desired target clock with the given
4797 * refclk, or FALSE. The returned values represent the clock equation:
4798 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4799 */
1b894b59 4800 limit = intel_limit(crtc, refclk);
d4906093 4801 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4802 if (!ok) {
4803 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4804 return -EINVAL;
79e53945
JB		 4805 }
4806
cda4b7d3 4807 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4808 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4809
ddc9003c
ZY		 4810 if (is_lvds && dev_priv->lvds_downclock_avail) {
4811 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4812 dev_priv->lvds_downclock,
4813 refclk,
4814 &reduced_clock);
18f9ed12
ZY		 4815 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4816 /*
4817 * If the different P is found, it means that we can't
4818 * switch the display clock by using the FP0/FP1.
4819 * In such case we will disable the LVDS downclock
4820 * feature.
4821 */
4822 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4823 "LVDS clock/downclock\n");
18f9ed12
ZY		 4824 has_reduced_clock = 0;
4825 }
652c393a 4826 }
7026d4ac
ZW		 4827 /* SDVO TV has fixed PLL values depend on its clock range,
4828 this mirrors vbios setting. */
4829 if (is_sdvo && is_tv) {
4830 if (adjusted_mode->clock >= 100000
5eddb70b 4831 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4832 clock.p1 = 2;
4833 clock.p2 = 10;
4834 clock.n = 3;
4835 clock.m1 = 16;
4836 clock.m2 = 8;
4837 } else if (adjusted_mode->clock >= 140500
5eddb70b 4838 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4839 clock.p1 = 1;
4840 clock.p2 = 10;
4841 clock.n = 6;
4842 clock.m1 = 12;
4843 clock.m2 = 8;
4844 }
4845 }
4846
2c07245f 4847 /* FDI link */
8febb297
EA		 4848 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4849 lane = 0;
4850 /* CPU eDP doesn't require FDI link, so just set DP M/N
4851 according to current link config */
4852 if (has_edp_encoder &&
4853 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4854 target_clock = mode->clock;
4855 intel_edp_link_config(has_edp_encoder,
4856 &lane, &link_bw);
4857 } else {
4858 /* [e]DP over FDI requires target mode clock
4859 instead of link clock */
4860 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4861 target_clock = mode->clock;
8febb297
EA		 4862 else
4863 target_clock = adjusted_mode->clock;
4864
4865 /* FDI is a binary signal running at ~2.7GHz, encoding
4866 * each output octet as 10 bits. The actual frequency
4867 * is stored as a divider into a 100MHz clock, and the
4868 * mode pixel clock is stored in units of 1KHz.
4869 * Hence the bw of each lane in terms of the mode signal
4870 * is:
4871 */
4872 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4873 }
58a27471 4874
8febb297
EA		 4875 /* determine panel color depth */
4876 temp = I915_READ(PIPECONF(pipe));
4877 temp &= ~PIPE_BPC_MASK;
4878 if (is_lvds) {
4879 /* the BPC will be 6 if it is 18-bit LVDS panel */
4880 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4881 temp |= PIPE_8BPC;
4882 else
4883 temp |= PIPE_6BPC;
4884 } else if (has_edp_encoder) {
4885 switch (dev_priv->edp.bpp/3) {
4886 case 8:
e5a95eb7 4887 temp |= PIPE_8BPC;
58a27471 4888 break;
8febb297
EA		 4889 case 10:
4890 temp |= PIPE_10BPC;
58a27471 4891 break;
8febb297
EA		 4892 case 6:
4893 temp |= PIPE_6BPC;
58a27471 4894 break;
8febb297
EA		 4895 case 12:
4896 temp |= PIPE_12BPC;
58a27471 4897 break;
77ffb597 4898 }
8febb297
EA		 4899 } else
4900 temp |= PIPE_8BPC;
4901 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4902
8febb297
EA		 4903 switch (temp & PIPE_BPC_MASK) {
4904 case PIPE_8BPC:
4905 bpp = 24;
4906 break;
4907 case PIPE_10BPC:
4908 bpp = 30;
4909 break;
4910 case PIPE_6BPC:
4911 bpp = 18;
4912 break;
4913 case PIPE_12BPC:
4914 bpp = 36;
4915 break;
4916 default:
4917 DRM_ERROR("unknown pipe bpc value\n");
4918 bpp = 24;
4919 }
77ffb597 4920
8febb297
EA		 4921 if (!lane) {
4922 /*
4923 * Account for spread spectrum to avoid
4924 * oversubscribing the link. Max center spread
4925 * is 2.5%; use 5% for safety's sake.
4926 */
4927 u32 bps = target_clock * bpp * 21 / 20;
4928 lane = bps / (link_bw * 8) + 1;
5eb08b69 4929 }
2c07245f 4930
8febb297
EA		 4931 intel_crtc->fdi_lanes = lane;
4932
4933 if (pixel_multiplier > 1)
4934 link_bw *= pixel_multiplier;
4935 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4936
c038e51e
ZW		 4937 /* Ironlake: try to setup display ref clock before DPLL
4938 * enabling. This is only under driver's control after
4939 * PCH B stepping, previous chipset stepping should be
4940 * ignoring this setting.
4941 */
8febb297
EA		 4942 temp = I915_READ(PCH_DREF_CONTROL);
4943 /* Always enable nonspread source */
4944 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4945 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4946 temp &= ~DREF_SSC_SOURCE_MASK;
4947 temp |= DREF_SSC_SOURCE_ENABLE;
4948 I915_WRITE(PCH_DREF_CONTROL, temp);
4949
4950 POSTING_READ(PCH_DREF_CONTROL);
4951 udelay(200);
fc9a2228 4952
8febb297
EA		 4953 if (has_edp_encoder) {
4954 if (intel_panel_use_ssc(dev_priv)) {
4955 temp |= DREF_SSC1_ENABLE;
fc9a2228 4956 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4957
fc9a2228
CW		 4958 POSTING_READ(PCH_DREF_CONTROL);
4959 udelay(200);
4960 }
8febb297
EA		 4961 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4962
4963 /* Enable CPU source on CPU attached eDP */
4964 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4965 if (intel_panel_use_ssc(dev_priv))
4966 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4967 else
4968 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4969 } else {
4970 /* Enable SSC on PCH eDP if needed */
4971 if (intel_panel_use_ssc(dev_priv)) {
4972 DRM_ERROR("enabling SSC on PCH\n");
4973 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4974 }
4975 }
4976 I915_WRITE(PCH_DREF_CONTROL, temp);
4977 POSTING_READ(PCH_DREF_CONTROL);
4978 udelay(200);
fc9a2228 4979 }
c038e51e 4980
a07d6787
EA		 4981 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4982 if (has_reduced_clock)
4983 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4984 reduced_clock.m2;
79e53945 4985
c1858123 4986 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4987 factor = 21;
4988 if (is_lvds) {
4989 if ((intel_panel_use_ssc(dev_priv) &&
4990 dev_priv->lvds_ssc_freq == 100) ||
4991 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4992 factor = 25;
4993 } else if (is_sdvo && is_tv)
4994 factor = 20;
c1858123 4995
8febb297
EA		 4996 if (clock.m1 < factor * clock.n)
4997 fp |= FP_CB_TUNE;
2c07245f 4998
5eddb70b 4999 dpll = 0;
2c07245f 5000
a07d6787
EA		 5001 if (is_lvds)
5002 dpll |= DPLLB_MODE_LVDS;
5003 else
5004 dpll |= DPLLB_MODE_DAC_SERIAL;
5005 if (is_sdvo) {
5006 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5007 if (pixel_multiplier > 1) {
5008 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5009 }
a07d6787
EA		 5010 dpll |= DPLL_DVO_HIGH_SPEED;
5011 }
5012 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5013 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5014
a07d6787
EA		 5015 /* compute bitmask from p1 value */
5016 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5017 /* also FPA1 */
5018 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5019
5020 switch (clock.p2) {
5021 case 5:
5022 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5023 break;
5024 case 7:
5025 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5026 break;
5027 case 10:
5028 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5029 break;
5030 case 14:
5031 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5032 break;
79e53945
JB		 5033 }
5034
43565a06
KH		 5035 if (is_sdvo && is_tv)
5036 dpll |= PLL_REF_INPUT_TVCLKINBC;
5037 else if (is_tv)
79e53945 5038 /* XXX: just matching BIOS for now */
43565a06 5039 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5040 dpll |= 3;
a7615030 5041 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5042 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5043 else
5044 dpll |= PLL_REF_INPUT_DREFCLK;
5045
5046 /* setup pipeconf */
5eddb70b 5047 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5048
5049 /* Set up the display plane register */
5050 dspcntr = DISPPLANE_GAMMA_ENABLE;
5051
28c97730 5052 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5053 drm_mode_debug_printmodeline(mode);
5054
5c5313c8
JB		 5055 /* PCH eDP needs FDI, but CPU eDP does not */
5056 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5057 I915_WRITE(PCH_FP0(pipe), fp);
5058 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5059
fae14981 5060 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5061 udelay(150);
5062 }
5063
8db9d77b
ZW		 5064 /* enable transcoder DPLL */
5065 if (HAS_PCH_CPT(dev)) {
5066 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5067 switch (pipe) {
5068 case 0:
5eddb70b 5069 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5070 break;
5071 case 1:
5eddb70b 5072 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5073 break;
5074 case 2:
5075 /* FIXME: manage transcoder PLLs? */
5076 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5077 break;
5078 default:
5079 BUG();
32f9d658 5080 }
8db9d77b 5081 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5082
5083 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5084 udelay(150);
5085 }
5086
79e53945
JB		 5087 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5088 * This is an exception to the general rule that mode_set doesn't turn
5089 * things on.
5090 */
5091 if (is_lvds) {
fae14981 5092 temp = I915_READ(PCH_LVDS);
5eddb70b 5093 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5094 if (pipe == 1) {
5095 if (HAS_PCH_CPT(dev))
5eddb70b 5096 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5097 else
5eddb70b 5098 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5099 } else {
5100 if (HAS_PCH_CPT(dev))
5eddb70b 5101 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5102 else
5eddb70b 5103 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5104 }
a3e17eb8 5105 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5106 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5107 /* Set the B0-B3 data pairs corresponding to whether we're going to
5108 * set the DPLLs for dual-channel mode or not.
5109 */
5110 if (clock.p2 == 7)
5eddb70b 5111 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5112 else
5eddb70b 5113 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5114
5115 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5116 * appropriately here, but we need to look more thoroughly into how
5117 * panels behave in the two modes.
5118 */
aa9b500d
BF		 5119 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5120 lvds_sync |= LVDS_HSYNC_POLARITY;
5121 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5122 lvds_sync |= LVDS_VSYNC_POLARITY;
5123 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5124 != lvds_sync) {
5125 char flags[2] = "-+";
5126 DRM_INFO("Changing LVDS panel from "
5127 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5128 flags[!(temp & LVDS_HSYNC_POLARITY)],
5129 flags[!(temp & LVDS_VSYNC_POLARITY)],
5130 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5131 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5132 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5133 temp |= lvds_sync;
5134 }
fae14981 5135 I915_WRITE(PCH_LVDS, temp);
79e53945 5136 }
434ed097
JB		 5137
5138 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5139 pipeconf &= ~PIPECONF_DITHER_EN;
5140 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5141 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5142 pipeconf |= PIPECONF_DITHER_EN;
5143 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5144 }
5145
5c5313c8 5146 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5147 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5148 } else {
8db9d77b 5149 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5150 I915_WRITE(TRANSDATA_M1(pipe), 0);
5151 I915_WRITE(TRANSDATA_N1(pipe), 0);
5152 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5153 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5154 }
79e53945 5155
8febb297
EA		 5156 if (!has_edp_encoder ||
5157 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5158 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5159
32f9d658 5160 /* Wait for the clocks to stabilize. */
fae14981 5161 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5162 udelay(150);
5163
8febb297
EA		 5164 /* The pixel multiplier can only be updated once the
5165 * DPLL is enabled and the clocks are stable.
5166 *
5167 * So write it again.
5168 */
fae14981 5169 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5170 }
79e53945 5171
5eddb70b 5172 intel_crtc->lowfreq_avail = false;
652c393a 5173 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5174 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5175 intel_crtc->lowfreq_avail = true;
5176 if (HAS_PIPE_CXSR(dev)) {
28c97730 5177 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5178 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5179 }
5180 } else {
fae14981 5181 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5182 if (HAS_PIPE_CXSR(dev)) {
28c97730 5183 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5184 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5185 }
5186 }
5187
734b4157
KH		 5188 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5189 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5190 /* the chip adds 2 halflines automatically */
5191 adjusted_mode->crtc_vdisplay -= 1;
5192 adjusted_mode->crtc_vtotal -= 1;
5193 adjusted_mode->crtc_vblank_start -= 1;
5194 adjusted_mode->crtc_vblank_end -= 1;
5195 adjusted_mode->crtc_vsync_end -= 1;
5196 adjusted_mode->crtc_vsync_start -= 1;
5197 } else
5198 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5199
5eddb70b
CW		 5200 I915_WRITE(HTOTAL(pipe),
5201 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5202 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5203 I915_WRITE(HBLANK(pipe),
5204 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5205 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5206 I915_WRITE(HSYNC(pipe),
5207 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5208 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5209
5210 I915_WRITE(VTOTAL(pipe),
5211 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5212 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5213 I915_WRITE(VBLANK(pipe),
5214 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5215 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5216 I915_WRITE(VSYNC(pipe),
5217 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5218 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5219
8febb297
EA		 5220 /* pipesrc controls the size that is scaled from, which should
5221 * always be the user's requested size.
79e53945 5222 */
5eddb70b
CW		 5223 I915_WRITE(PIPESRC(pipe),
5224 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5225
8febb297
EA		 5226 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5227 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5228 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5229 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5230
8febb297
EA		 5231 if (has_edp_encoder &&
5232 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5233 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5234 }
5235
5eddb70b
CW		 5236 I915_WRITE(PIPECONF(pipe), pipeconf);
5237 POSTING_READ(PIPECONF(pipe));
79e53945 5238
9d0498a2 5239 intel_wait_for_vblank(dev, pipe);
79e53945 5240
f00a3ddf 5241 if (IS_GEN5(dev)) {
553bd149
ZW		 5242 /* enable address swizzle for tiling buffer */
5243 temp = I915_READ(DISP_ARB_CTL);
5244 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5245 }
5246
5eddb70b 5247 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5248 POSTING_READ(DSPCNTR(plane));
79e53945 5249
5c3b82e2 5250 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5251
5252 intel_update_watermarks(dev);
5253
1f803ee5 5254 return ret;
79e53945
JB		 5255}
5256
f564048e
EA		 5257static int intel_crtc_mode_set(struct drm_crtc *crtc,
5258 struct drm_display_mode *mode,
5259 struct drm_display_mode *adjusted_mode,
5260 int x, int y,
5261 struct drm_framebuffer *old_fb)
5262{
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266 int pipe = intel_crtc->pipe;
f564048e
EA		 5267 int ret;
5268
0b701d27 5269 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5270
f564048e
EA		 5271 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5272 x, y, old_fb);
7662c8bd 5273
79e53945 5274 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5275
1f803ee5 5276 return ret;
79e53945
JB		 5277}
5278
5279/** Loads the palette/gamma unit for the CRTC with the prepared values */
5280void intel_crtc_load_lut(struct drm_crtc *crtc)
5281{
5282 struct drm_device *dev = crtc->dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5285 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5286 int i;
5287
5288 /* The clocks have to be on to load the palette. */
5289 if (!crtc->enabled)
5290 return;
5291
f2b115e6 5292 /* use legacy palette for Ironlake */
bad720ff 5293 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5294 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5295
79e53945
JB		 5296 for (i = 0; i < 256; i++) {
5297 I915_WRITE(palreg + 4 * i,
5298 (intel_crtc->lut_r[i] << 16) |
5299 (intel_crtc->lut_g[i] << 8) |
5300 intel_crtc->lut_b[i]);
5301 }
5302}
5303
560b85bb
CW		 5304static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 bool visible = base != 0;
5310 u32 cntl;
5311
5312 if (intel_crtc->cursor_visible == visible)
5313 return;
5314
9db4a9c7 5315 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5316 if (visible) {
5317 /* On these chipsets we can only modify the base whilst
5318 * the cursor is disabled.
5319 */
9db4a9c7 5320 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5321
5322 cntl &= ~(CURSOR_FORMAT_MASK);
5323 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5324 cntl |= CURSOR_ENABLE |
5325 CURSOR_GAMMA_ENABLE |
5326 CURSOR_FORMAT_ARGB;
5327 } else
5328 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5329 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5330
5331 intel_crtc->cursor_visible = visible;
5332}
5333
5334static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5335{
5336 struct drm_device *dev = crtc->dev;
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5339 int pipe = intel_crtc->pipe;
5340 bool visible = base != 0;
5341
5342 if (intel_crtc->cursor_visible != visible) {
548f245b 5343 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5344 if (base) {
5345 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5346 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5347 cntl |= pipe << 28; /* Connect to correct pipe */
5348 } else {
5349 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5350 cntl |= CURSOR_MODE_DISABLE;
5351 }
9db4a9c7 5352 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5353
5354 intel_crtc->cursor_visible = visible;
5355 }
5356 /* and commit changes on next vblank */
9db4a9c7 5357 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5358}
5359
cda4b7d3 5360/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5361static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5362 bool on)
cda4b7d3
CW		 5363{
5364 struct drm_device *dev = crtc->dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5367 int pipe = intel_crtc->pipe;
5368 int x = intel_crtc->cursor_x;
5369 int y = intel_crtc->cursor_y;
560b85bb 5370 u32 base, pos;
cda4b7d3
CW		 5371 bool visible;
5372
5373 pos = 0;
5374
6b383a7f 5375 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5376 base = intel_crtc->cursor_addr;
5377 if (x > (int) crtc->fb->width)
5378 base = 0;
5379
5380 if (y > (int) crtc->fb->height)
5381 base = 0;
5382 } else
5383 base = 0;
5384
5385 if (x < 0) {
5386 if (x + intel_crtc->cursor_width < 0)
5387 base = 0;
5388
5389 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5390 x = -x;
5391 }
5392 pos |= x << CURSOR_X_SHIFT;
5393
5394 if (y < 0) {
5395 if (y + intel_crtc->cursor_height < 0)
5396 base = 0;
5397
5398 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5399 y = -y;
5400 }
5401 pos |= y << CURSOR_Y_SHIFT;
5402
5403 visible = base != 0;
560b85bb 5404 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5405 return;
5406
9db4a9c7 5407 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5408 if (IS_845G(dev) || IS_I865G(dev))
5409 i845_update_cursor(crtc, base);
5410 else
5411 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5412
5413 if (visible)
5414 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5415}
5416
79e53945 5417static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5418 struct drm_file *file,
79e53945
JB		 5419 uint32_t handle,
5420 uint32_t width, uint32_t height)
5421{
5422 struct drm_device *dev = crtc->dev;
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5425 struct drm_i915_gem_object *obj;
cda4b7d3 5426 uint32_t addr;
3f8bc370 5427 int ret;
79e53945 5428
28c97730 5429 DRM_DEBUG_KMS("\n");
79e53945
JB		 5430
5431 /* if we want to turn off the cursor ignore width and height */
5432 if (!handle) {
28c97730 5433 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5434 addr = 0;
05394f39 5435 obj = NULL;
5004417d 5436 mutex_lock(&dev->struct_mutex);
3f8bc370 5437 goto finish;
79e53945
JB		 5438 }
5439
5440 /* Currently we only support 64x64 cursors */
5441 if (width != 64 || height != 64) {
5442 DRM_ERROR("we currently only support 64x64 cursors\n");
5443 return -EINVAL;
5444 }
5445
05394f39 5446 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5447 if (&obj->base == NULL)
79e53945
JB		 5448 return -ENOENT;
5449
05394f39 5450 if (obj->base.size < width * height * 4) {
79e53945 5451 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5452 ret = -ENOMEM;
5453 goto fail;
79e53945
JB		 5454 }
5455
71acb5eb 5456 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5457 mutex_lock(&dev->struct_mutex);
b295d1b6 5458 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5459 if (obj->tiling_mode) {
5460 DRM_ERROR("cursor cannot be tiled\n");
5461 ret = -EINVAL;
5462 goto fail_locked;
5463 }
5464
05394f39 5465 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA		 5466 if (ret) {
5467 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 5468 goto fail_locked;
71acb5eb 5469 }
e7b526bb 5470
05394f39 5471 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW		 5472 if (ret) {
5473 DRM_ERROR("failed to move cursor bo into the GTT\n");
5474 goto fail_unpin;
5475 }
5476
d9e86c0e
CW		 5477 ret = i915_gem_object_put_fence(obj);
5478 if (ret) {
5479 DRM_ERROR("failed to move cursor bo into the GTT\n");
5480 goto fail_unpin;
5481 }
5482
05394f39 5483 addr = obj->gtt_offset;
71acb5eb 5484 } else {
6eeefaf3 5485 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5486 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5487 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5488 align);
71acb5eb
DA		 5489 if (ret) {
5490 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5491 goto fail_locked;
71acb5eb 5492 }
05394f39 5493 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5494 }
5495
a6c45cf0 5496 if (IS_GEN2(dev))
14b60391
JB		 5497 I915_WRITE(CURSIZE, (height << 12) | width);
5498
3f8bc370 5499 finish:
3f8bc370 5500 if (intel_crtc->cursor_bo) {
b295d1b6 5501 if (dev_priv->info->cursor_needs_physical) {
05394f39 5502 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5503 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5504 } else
5505 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5506 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5507 }
80824003 5508
7f9872e0 5509 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5510
5511 intel_crtc->cursor_addr = addr;
05394f39 5512 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5513 intel_crtc->cursor_width = width;
5514 intel_crtc->cursor_height = height;
5515
6b383a7f 5516 intel_crtc_update_cursor(crtc, true);
3f8bc370 5517
79e53945 5518 return 0;
e7b526bb 5519fail_unpin:
05394f39 5520 i915_gem_object_unpin(obj);
7f9872e0 5521fail_locked:
34b8686e 5522 mutex_unlock(&dev->struct_mutex);
bc9025bd 5523fail:
05394f39 5524 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5525 return ret;
79e53945
JB		 5526}
5527
5528static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5529{
79e53945 5530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5531
cda4b7d3
CW		 5532 intel_crtc->cursor_x = x;
5533 intel_crtc->cursor_y = y;
652c393a 5534
6b383a7f 5535 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5536
5537 return 0;
5538}
5539
5540/** Sets the color ramps on behalf of RandR */
5541void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5542 u16 blue, int regno)
5543{
5544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5545
5546 intel_crtc->lut_r[regno] = red >> 8;
5547 intel_crtc->lut_g[regno] = green >> 8;
5548 intel_crtc->lut_b[regno] = blue >> 8;
5549}
5550
b8c00ac5
DA		 5551void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5552 u16 *blue, int regno)
5553{
5554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5555
5556 *red = intel_crtc->lut_r[regno] << 8;
5557 *green = intel_crtc->lut_g[regno] << 8;
5558 *blue = intel_crtc->lut_b[regno] << 8;
5559}
5560
79e53945 5561static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5562 u16 *blue, uint32_t start, uint32_t size)
79e53945 5563{
7203425a 5564 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5566
7203425a 5567 for (i = start; i < end; i++) {
79e53945
JB		 5568 intel_crtc->lut_r[i] = red[i] >> 8;
5569 intel_crtc->lut_g[i] = green[i] >> 8;
5570 intel_crtc->lut_b[i] = blue[i] >> 8;
5571 }
5572
5573 intel_crtc_load_lut(crtc);
5574}
5575
5576/**
5577 * Get a pipe with a simple mode set on it for doing load-based monitor
5578 * detection.
5579 *
5580 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5581 * its requirements. The pipe will be connected to no other encoders.
79e53945 5582 *
c751ce4f 5583 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5584 * configured for it. In the future, it could choose to temporarily disable
5585 * some outputs to free up a pipe for its use.
5586 *
5587 * \return crtc, or NULL if no pipes are available.
5588 */
5589
5590/* VESA 640x480x72Hz mode to set on the pipe */
5591static struct drm_display_mode load_detect_mode = {
5592 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5593 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5594};
5595
d2dff872
CW		 5596static struct drm_framebuffer *
5597intel_framebuffer_create(struct drm_device *dev,
5598 struct drm_mode_fb_cmd *mode_cmd,
5599 struct drm_i915_gem_object *obj)
5600{
5601 struct intel_framebuffer *intel_fb;
5602 int ret;
5603
5604 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5605 if (!intel_fb) {
5606 drm_gem_object_unreference_unlocked(&obj->base);
5607 return ERR_PTR(-ENOMEM);
5608 }
5609
5610 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5611 if (ret) {
5612 drm_gem_object_unreference_unlocked(&obj->base);
5613 kfree(intel_fb);
5614 return ERR_PTR(ret);
5615 }
5616
5617 return &intel_fb->base;
5618}
5619
5620static u32
5621intel_framebuffer_pitch_for_width(int width, int bpp)
5622{
5623 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5624 return ALIGN(pitch, 64);
5625}
5626
5627static u32
5628intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5629{
5630 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5631 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5632}
5633
5634static struct drm_framebuffer *
5635intel_framebuffer_create_for_mode(struct drm_device *dev,
5636 struct drm_display_mode *mode,
5637 int depth, int bpp)
5638{
5639 struct drm_i915_gem_object *obj;
5640 struct drm_mode_fb_cmd mode_cmd;
5641
5642 obj = i915_gem_alloc_object(dev,
5643 intel_framebuffer_size_for_mode(mode, bpp));
5644 if (obj == NULL)
5645 return ERR_PTR(-ENOMEM);
5646
5647 mode_cmd.width = mode->hdisplay;
5648 mode_cmd.height = mode->vdisplay;
5649 mode_cmd.depth = depth;
5650 mode_cmd.bpp = bpp;
5651 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5652
5653 return intel_framebuffer_create(dev, &mode_cmd, obj);
5654}
5655
5656static struct drm_framebuffer *
5657mode_fits_in_fbdev(struct drm_device *dev,
5658 struct drm_display_mode *mode)
5659{
5660 struct drm_i915_private *dev_priv = dev->dev_private;
5661 struct drm_i915_gem_object *obj;
5662 struct drm_framebuffer *fb;
5663
5664 if (dev_priv->fbdev == NULL)
5665 return NULL;
5666
5667 obj = dev_priv->fbdev->ifb.obj;
5668 if (obj == NULL)
5669 return NULL;
5670
5671 fb = &dev_priv->fbdev->ifb.base;
5672 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5673 fb->bits_per_pixel))
5674 return NULL;
5675
5676 if (obj->base.size < mode->vdisplay * fb->pitch)
5677 return NULL;
5678
5679 return fb;
5680}
5681
7173188d
CW		 5682bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5683 struct drm_connector *connector,
5684 struct drm_display_mode *mode,
8261b191 5685 struct intel_load_detect_pipe *old)
79e53945
JB		 5686{
5687 struct intel_crtc *intel_crtc;
5688 struct drm_crtc *possible_crtc;
4ef69c7a 5689 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5690 struct drm_crtc *crtc = NULL;
5691 struct drm_device *dev = encoder->dev;
d2dff872 5692 struct drm_framebuffer *old_fb;
79e53945
JB		 5693 int i = -1;
5694
d2dff872
CW		 5695 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5696 connector->base.id, drm_get_connector_name(connector),
5697 encoder->base.id, drm_get_encoder_name(encoder));
5698
79e53945
JB		 5699 /*
5700 * Algorithm gets a little messy:
7a5e4805 5701 *
79e53945
JB		 5702 * - if the connector already has an assigned crtc, use it (but make
5703 * sure it's on first)
7a5e4805 5704 *
79e53945
JB		 5705 * - try to find the first unused crtc that can drive this connector,
5706 * and use that if we find one
79e53945
JB		 5707 */
5708
5709 /* See if we already have a CRTC for this connector */
5710 if (encoder->crtc) {
5711 crtc = encoder->crtc;
8261b191 5712
79e53945 5713 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5714 old->dpms_mode = intel_crtc->dpms_mode;
5715 old->load_detect_temp = false;
5716
5717 /* Make sure the crtc and connector are running */
79e53945 5718 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5719 struct drm_encoder_helper_funcs *encoder_funcs;
5720 struct drm_crtc_helper_funcs *crtc_funcs;
5721
79e53945
JB		 5722 crtc_funcs = crtc->helper_private;
5723 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5724
5725 encoder_funcs = encoder->helper_private;
79e53945
JB		 5726 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5727 }
8261b191 5728
7173188d 5729 return true;
79e53945
JB		 5730 }
5731
5732 /* Find an unused one (if possible) */
5733 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5734 i++;
5735 if (!(encoder->possible_crtcs & (1 << i)))
5736 continue;
5737 if (!possible_crtc->enabled) {
5738 crtc = possible_crtc;
5739 break;
5740 }
79e53945
JB		 5741 }
5742
5743 /*
5744 * If we didn't find an unused CRTC, don't use any.
5745 */
5746 if (!crtc) {
7173188d
CW		 5747 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5748 return false;
79e53945
JB		 5749 }
5750
5751 encoder->crtc = crtc;
c1c43977 5752 connector->encoder = encoder;
79e53945
JB		 5753
5754 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5755 old->dpms_mode = intel_crtc->dpms_mode;
5756 old->load_detect_temp = true;
d2dff872 5757 old->release_fb = NULL;
79e53945 5758
6492711d
CW		 5759 if (!mode)
5760 mode = &load_detect_mode;
79e53945 5761
d2dff872
CW		 5762 old_fb = crtc->fb;
5763
5764 /* We need a framebuffer large enough to accommodate all accesses
5765 * that the plane may generate whilst we perform load detection.
5766 * We can not rely on the fbcon either being present (we get called
5767 * during its initialisation to detect all boot displays, or it may
5768 * not even exist) or that it is large enough to satisfy the
5769 * requested mode.
5770 */
5771 crtc->fb = mode_fits_in_fbdev(dev, mode);
5772 if (crtc->fb == NULL) {
5773 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5774 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5775 old->release_fb = crtc->fb;
5776 } else
5777 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5778 if (IS_ERR(crtc->fb)) {
5779 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5780 crtc->fb = old_fb;
5781 return false;
79e53945 5782 }
79e53945 5783
d2dff872 5784 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5785 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5786 if (old->release_fb)
5787 old->release_fb->funcs->destroy(old->release_fb);
5788 crtc->fb = old_fb;
6492711d 5789 return false;
79e53945 5790 }
7173188d 5791
79e53945 5792 /* let the connector get through one full cycle before testing */
9d0498a2 5793 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5794
7173188d 5795 return true;
79e53945
JB		 5796}
5797
c1c43977 5798void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5799 struct drm_connector *connector,
5800 struct intel_load_detect_pipe *old)
79e53945 5801{
4ef69c7a 5802 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5803 struct drm_device *dev = encoder->dev;
5804 struct drm_crtc *crtc = encoder->crtc;
5805 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5806 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5807
d2dff872
CW		 5808 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5809 connector->base.id, drm_get_connector_name(connector),
5810 encoder->base.id, drm_get_encoder_name(encoder));
5811
8261b191 5812 if (old->load_detect_temp) {
c1c43977 5813 connector->encoder = NULL;
79e53945 5814 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5815
5816 if (old->release_fb)
5817 old->release_fb->funcs->destroy(old->release_fb);
5818
0622a53c 5819 return;
79e53945
JB		 5820 }
5821
c751ce4f 5822 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5823 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5824 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5825 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5826 }
5827}
5828
5829/* Returns the clock of the currently programmed mode of the given pipe. */
5830static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5831{
5832 struct drm_i915_private *dev_priv = dev->dev_private;
5833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5834 int pipe = intel_crtc->pipe;
548f245b 5835 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5836 u32 fp;
5837 intel_clock_t clock;
5838
5839 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5840 fp = I915_READ(FP0(pipe));
79e53945 5841 else
39adb7a5 5842 fp = I915_READ(FP1(pipe));
79e53945
JB		 5843
5844 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5845 if (IS_PINEVIEW(dev)) {
5846 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5847 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5848 } else {
5849 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5850 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5851 }
5852
a6c45cf0 5853 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5854 if (IS_PINEVIEW(dev))
5855 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5856 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5857 else
5858 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5859 DPLL_FPA01_P1_POST_DIV_SHIFT);
5860
5861 switch (dpll & DPLL_MODE_MASK) {
5862 case DPLLB_MODE_DAC_SERIAL:
5863 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5864 5 : 10;
5865 break;
5866 case DPLLB_MODE_LVDS:
5867 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5868 7 : 14;
5869 break;
5870 default:
28c97730 5871 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5872 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5873 return 0;
5874 }
5875
5876 /* XXX: Handle the 100Mhz refclk */
2177832f 5877 intel_clock(dev, 96000, &clock);
79e53945
JB		 5878 } else {
5879 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5880
5881 if (is_lvds) {
5882 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5883 DPLL_FPA01_P1_POST_DIV_SHIFT);
5884 clock.p2 = 14;
5885
5886 if ((dpll & PLL_REF_INPUT_MASK) ==
5887 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5888 /* XXX: might not be 66MHz */
2177832f 5889 intel_clock(dev, 66000, &clock);
79e53945 5890 } else
2177832f 5891 intel_clock(dev, 48000, &clock);
79e53945
JB		 5892 } else {
5893 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5894 clock.p1 = 2;
5895 else {
5896 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5897 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5898 }
5899 if (dpll & PLL_P2_DIVIDE_BY_4)
5900 clock.p2 = 4;
5901 else
5902 clock.p2 = 2;
5903
2177832f 5904 intel_clock(dev, 48000, &clock);
79e53945
JB		 5905 }
5906 }
5907
5908 /* XXX: It would be nice to validate the clocks, but we can't reuse
5909 * i830PllIsValid() because it relies on the xf86_config connector
5910 * configuration being accurate, which it isn't necessarily.
5911 */
5912
5913 return clock.dot;
5914}
5915
5916/** Returns the currently programmed mode of the given pipe. */
5917struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5918 struct drm_crtc *crtc)
5919{
548f245b 5920 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5922 int pipe = intel_crtc->pipe;
5923 struct drm_display_mode *mode;
548f245b
JB		 5924 int htot = I915_READ(HTOTAL(pipe));
5925 int hsync = I915_READ(HSYNC(pipe));
5926 int vtot = I915_READ(VTOTAL(pipe));
5927 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5928
5929 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5930 if (!mode)
5931 return NULL;
5932
5933 mode->clock = intel_crtc_clock_get(dev, crtc);
5934 mode->hdisplay = (htot & 0xffff) + 1;
5935 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5936 mode->hsync_start = (hsync & 0xffff) + 1;
5937 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5938 mode->vdisplay = (vtot & 0xffff) + 1;
5939 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5940 mode->vsync_start = (vsync & 0xffff) + 1;
5941 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5942
5943 drm_mode_set_name(mode);
5944 drm_mode_set_crtcinfo(mode, 0);
5945
5946 return mode;
5947}
5948
652c393a
JB		 5949#define GPU_IDLE_TIMEOUT 500 /* ms */
5950
5951/* When this timer fires, we've been idle for awhile */
5952static void intel_gpu_idle_timer(unsigned long arg)
5953{
5954 struct drm_device *dev = (struct drm_device *)arg;
5955 drm_i915_private_t *dev_priv = dev->dev_private;
5956
ff7ea4c0
CW		 5957 if (!list_empty(&dev_priv->mm.active_list)) {
5958 /* Still processing requests, so just re-arm the timer. */
5959 mod_timer(&dev_priv->idle_timer, jiffies +
5960 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5961 return;
5962 }
652c393a 5963
ff7ea4c0 5964 dev_priv->busy = false;
01dfba93 5965 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5966}
5967
652c393a
JB		 5968#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5969
5970static void intel_crtc_idle_timer(unsigned long arg)
5971{
5972 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5973 struct drm_crtc *crtc = &intel_crtc->base;
5974 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5975 struct intel_framebuffer *intel_fb;
652c393a 5976
ff7ea4c0
CW		 5977 intel_fb = to_intel_framebuffer(crtc->fb);
5978 if (intel_fb && intel_fb->obj->active) {
5979 /* The framebuffer is still being accessed by the GPU. */
5980 mod_timer(&intel_crtc->idle_timer, jiffies +
5981 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5982 return;
5983 }
652c393a 5984
ff7ea4c0 5985 intel_crtc->busy = false;
01dfba93 5986 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5987}
5988
3dec0095 5989static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5990{
5991 struct drm_device *dev = crtc->dev;
5992 drm_i915_private_t *dev_priv = dev->dev_private;
5993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5995 int dpll_reg = DPLL(pipe);
5996 int dpll;
652c393a 5997
bad720ff 5998 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5999 return;
6000
6001 if (!dev_priv->lvds_downclock_avail)
6002 return;
6003
dbdc6479 6004 dpll = I915_READ(dpll_reg);
652c393a 6005 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6006 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6007
6008 /* Unlock panel regs */
dbdc6479
JB		 6009 I915_WRITE(PP_CONTROL,
6010 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6011
6012 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6013 I915_WRITE(dpll_reg, dpll);
9d0498a2 6014 intel_wait_for_vblank(dev, pipe);
dbdc6479 6015
652c393a
JB		 6016 dpll = I915_READ(dpll_reg);
6017 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6018 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6019
6020 /* ...and lock them again */
6021 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6022 }
6023
6024 /* Schedule downclock */
3dec0095
DV		 6025 mod_timer(&intel_crtc->idle_timer, jiffies +
6026 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6027}
6028
6029static void intel_decrease_pllclock(struct drm_crtc *crtc)
6030{
6031 struct drm_device *dev = crtc->dev;
6032 drm_i915_private_t *dev_priv = dev->dev_private;
6033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6034 int pipe = intel_crtc->pipe;
9db4a9c7 6035 int dpll_reg = DPLL(pipe);
652c393a
JB		 6036 int dpll = I915_READ(dpll_reg);
6037
bad720ff 6038 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6039 return;
6040
6041 if (!dev_priv->lvds_downclock_avail)
6042 return;
6043
6044 /*
6045 * Since this is called by a timer, we should never get here in
6046 * the manual case.
6047 */
6048 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6049 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6050
6051 /* Unlock panel regs */
4a655f04
JB		 6052 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6053 PANEL_UNLOCK_REGS);
652c393a
JB		 6054
6055 dpll |= DISPLAY_RATE_SELECT_FPA1;
6056 I915_WRITE(dpll_reg, dpll);
9d0498a2 6057 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6058 dpll = I915_READ(dpll_reg);
6059 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6060 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6061
6062 /* ...and lock them again */
6063 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6064 }
6065
6066}
6067
6068/**
6069 * intel_idle_update - adjust clocks for idleness
6070 * @work: work struct
6071 *
6072 * Either the GPU or display (or both) went idle. Check the busy status
6073 * here and adjust the CRTC and GPU clocks as necessary.
6074 */
6075static void intel_idle_update(struct work_struct *work)
6076{
6077 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6078 idle_work);
6079 struct drm_device *dev = dev_priv->dev;
6080 struct drm_crtc *crtc;
6081 struct intel_crtc *intel_crtc;
6082
6083 if (!i915_powersave)
6084 return;
6085
6086 mutex_lock(&dev->struct_mutex);
6087
7648fa99
JB		 6088 i915_update_gfx_val(dev_priv);
6089
652c393a
JB		 6090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6091 /* Skip inactive CRTCs */
6092 if (!crtc->fb)
6093 continue;
6094
6095 intel_crtc = to_intel_crtc(crtc);
6096 if (!intel_crtc->busy)
6097 intel_decrease_pllclock(crtc);
6098 }
6099
45ac22c8 6100
652c393a
JB		 6101 mutex_unlock(&dev->struct_mutex);
6102}
6103
6104/**
6105 * intel_mark_busy - mark the GPU and possibly the display busy
6106 * @dev: drm device
6107 * @obj: object we're operating on
6108 *
6109 * Callers can use this function to indicate that the GPU is busy processing
6110 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6111 * buffer), we'll also mark the display as busy, so we know to increase its
6112 * clock frequency.
6113 */
05394f39 6114void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6115{
6116 drm_i915_private_t *dev_priv = dev->dev_private;
6117 struct drm_crtc *crtc = NULL;
6118 struct intel_framebuffer *intel_fb;
6119 struct intel_crtc *intel_crtc;
6120
5e17ee74
ZW		 6121 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6122 return;
6123
18b2190c 6124 if (!dev_priv->busy)
28cf798f 6125 dev_priv->busy = true;
18b2190c 6126 else
28cf798f
CW		 6127 mod_timer(&dev_priv->idle_timer, jiffies +
6128 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6129
6130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6131 if (!crtc->fb)
6132 continue;
6133
6134 intel_crtc = to_intel_crtc(crtc);
6135 intel_fb = to_intel_framebuffer(crtc->fb);
6136 if (intel_fb->obj == obj) {
6137 if (!intel_crtc->busy) {
6138 /* Non-busy -> busy, upclock */
3dec0095 6139 intel_increase_pllclock(crtc);
652c393a
JB		 6140 intel_crtc->busy = true;
6141 } else {
6142 /* Busy -> busy, put off timer */
6143 mod_timer(&intel_crtc->idle_timer, jiffies +
6144 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6145 }
6146 }
6147 }
6148}
6149
79e53945
JB		 6150static void intel_crtc_destroy(struct drm_crtc *crtc)
6151{
6152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6153 struct drm_device *dev = crtc->dev;
6154 struct intel_unpin_work *work;
6155 unsigned long flags;
6156
6157 spin_lock_irqsave(&dev->event_lock, flags);
6158 work = intel_crtc->unpin_work;
6159 intel_crtc->unpin_work = NULL;
6160 spin_unlock_irqrestore(&dev->event_lock, flags);
6161
6162 if (work) {
6163 cancel_work_sync(&work->work);
6164 kfree(work);
6165 }
79e53945
JB		 6166
6167 drm_crtc_cleanup(crtc);
67e77c5a 6168
79e53945
JB		 6169 kfree(intel_crtc);
6170}
6171
6b95a207
KH		 6172static void intel_unpin_work_fn(struct work_struct *__work)
6173{
6174 struct intel_unpin_work *work =
6175 container_of(__work, struct intel_unpin_work, work);
6176
6177 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6178 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6179 drm_gem_object_unreference(&work->pending_flip_obj->base);
6180 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6181
6b95a207
KH		 6182 mutex_unlock(&work->dev->struct_mutex);
6183 kfree(work);
6184}
6185
1afe3e9d 6186static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6187 struct drm_crtc *crtc)
6b95a207
KH		 6188{
6189 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191 struct intel_unpin_work *work;
05394f39 6192 struct drm_i915_gem_object *obj;
6b95a207 6193 struct drm_pending_vblank_event *e;
49b14a5c 6194 struct timeval tnow, tvbl;
6b95a207
KH		 6195 unsigned long flags;
6196
6197 /* Ignore early vblank irqs */
6198 if (intel_crtc == NULL)
6199 return;
6200
49b14a5c
MK		 6201 do_gettimeofday(&tnow);
6202
6b95a207
KH		 6203 spin_lock_irqsave(&dev->event_lock, flags);
6204 work = intel_crtc->unpin_work;
6205 if (work == NULL || !work->pending) {
6206 spin_unlock_irqrestore(&dev->event_lock, flags);
6207 return;
6208 }
6209
6210 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6211
6212 if (work->event) {
6213 e = work->event;
49b14a5c 6214 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6215
6216 /* Called before vblank count and timestamps have
6217 * been updated for the vblank interval of flip
6218 * completion? Need to increment vblank count and
6219 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6220 * to account for this. We assume this happened if we
6221 * get called over 0.9 frame durations after the last
6222 * timestamped vblank.
6223 *
6224 * This calculation can not be used with vrefresh rates
6225 * below 5Hz (10Hz to be on the safe side) without
6226 * promoting to 64 integers.
0af7e4df 6227 */
49b14a5c
MK		 6228 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6229 9 * crtc->framedur_ns) {
0af7e4df 6230 e->event.sequence++;
49b14a5c
MK		 6231 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6232 crtc->framedur_ns);
0af7e4df
MK		 6233 }
6234
49b14a5c
MK		 6235 e->event.tv_sec = tvbl.tv_sec;
6236 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6237
6b95a207
KH		 6238 list_add_tail(&e->base.link,
6239 &e->base.file_priv->event_list);
6240 wake_up_interruptible(&e->base.file_priv->event_wait);
6241 }
6242
0af7e4df
MK		 6243 drm_vblank_put(dev, intel_crtc->pipe);
6244
6b95a207
KH		 6245 spin_unlock_irqrestore(&dev->event_lock, flags);
6246
05394f39 6247 obj = work->old_fb_obj;
d9e86c0e 6248
e59f2bac 6249 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6250 &obj->pending_flip.counter);
6251 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6252 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6253
6b95a207 6254 schedule_work(&work->work);
e5510fac
JB		 6255
6256 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6257}
6258
1afe3e9d
JB		 6259void intel_finish_page_flip(struct drm_device *dev, int pipe)
6260{
6261 drm_i915_private_t *dev_priv = dev->dev_private;
6262 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6263
49b14a5c 6264 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6265}
6266
6267void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6268{
6269 drm_i915_private_t *dev_priv = dev->dev_private;
6270 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6271
49b14a5c 6272 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6273}
6274
6b95a207
KH		 6275void intel_prepare_page_flip(struct drm_device *dev, int plane)
6276{
6277 drm_i915_private_t *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc =
6279 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6280 unsigned long flags;
6281
6282 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6283 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6284 if ((++intel_crtc->unpin_work->pending) > 1)
6285 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6286 } else {
6287 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6288 }
6b95a207
KH		 6289 spin_unlock_irqrestore(&dev->event_lock, flags);
6290}
6291
8c9f3aaf
JB		 6292static int intel_gen2_queue_flip(struct drm_device *dev,
6293 struct drm_crtc *crtc,
6294 struct drm_framebuffer *fb,
6295 struct drm_i915_gem_object *obj)
6296{
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 unsigned long offset;
6300 u32 flip_mask;
6301 int ret;
6302
6303 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6304 if (ret)
6305 goto out;
6306
6307 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6308 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6309
6310 ret = BEGIN_LP_RING(6);
6311 if (ret)
6312 goto out;
6313
6314 /* Can't queue multiple flips, so wait for the previous
6315 * one to finish before executing the next.
6316 */
6317 if (intel_crtc->plane)
6318 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6319 else
6320 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6321 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6322 OUT_RING(MI_NOOP);
6323 OUT_RING(MI_DISPLAY_FLIP |
6324 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6325 OUT_RING(fb->pitch);
6326 OUT_RING(obj->gtt_offset + offset);
6327 OUT_RING(MI_NOOP);
6328 ADVANCE_LP_RING();
6329out:
6330 return ret;
6331}
6332
6333static int intel_gen3_queue_flip(struct drm_device *dev,
6334 struct drm_crtc *crtc,
6335 struct drm_framebuffer *fb,
6336 struct drm_i915_gem_object *obj)
6337{
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6340 unsigned long offset;
6341 u32 flip_mask;
6342 int ret;
6343
6344 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6345 if (ret)
6346 goto out;
6347
6348 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6349 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6350
6351 ret = BEGIN_LP_RING(6);
6352 if (ret)
6353 goto out;
6354
6355 if (intel_crtc->plane)
6356 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6357 else
6358 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6359 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6360 OUT_RING(MI_NOOP);
6361 OUT_RING(MI_DISPLAY_FLIP_I915 |
6362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6363 OUT_RING(fb->pitch);
6364 OUT_RING(obj->gtt_offset + offset);
6365 OUT_RING(MI_NOOP);
6366
6367 ADVANCE_LP_RING();
6368out:
6369 return ret;
6370}
6371
6372static int intel_gen4_queue_flip(struct drm_device *dev,
6373 struct drm_crtc *crtc,
6374 struct drm_framebuffer *fb,
6375 struct drm_i915_gem_object *obj)
6376{
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 uint32_t pf, pipesrc;
6380 int ret;
6381
6382 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6383 if (ret)
6384 goto out;
6385
6386 ret = BEGIN_LP_RING(4);
6387 if (ret)
6388 goto out;
6389
6390 /* i965+ uses the linear or tiled offsets from the
6391 * Display Registers (which do not change across a page-flip)
6392 * so we need only reprogram the base address.
6393 */
6394 OUT_RING(MI_DISPLAY_FLIP |
6395 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6396 OUT_RING(fb->pitch);
6397 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6398
6399 /* XXX Enabling the panel-fitter across page-flip is so far
6400 * untested on non-native modes, so ignore it for now.
6401 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6402 */
6403 pf = 0;
6404 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6405 OUT_RING(pf | pipesrc);
6406 ADVANCE_LP_RING();
6407out:
6408 return ret;
6409}
6410
6411static int intel_gen6_queue_flip(struct drm_device *dev,
6412 struct drm_crtc *crtc,
6413 struct drm_framebuffer *fb,
6414 struct drm_i915_gem_object *obj)
6415{
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418 uint32_t pf, pipesrc;
6419 int ret;
6420
6421 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6422 if (ret)
6423 goto out;
6424
6425 ret = BEGIN_LP_RING(4);
6426 if (ret)
6427 goto out;
6428
6429 OUT_RING(MI_DISPLAY_FLIP |
6430 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6431 OUT_RING(fb->pitch | obj->tiling_mode);
6432 OUT_RING(obj->gtt_offset);
6433
6434 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6435 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6436 OUT_RING(pf | pipesrc);
6437 ADVANCE_LP_RING();
6438out:
6439 return ret;
6440}
6441
7c9017e5
JB		 6442/*
6443 * On gen7 we currently use the blit ring because (in early silicon at least)
6444 * the render ring doesn't give us interrpts for page flip completion, which
6445 * means clients will hang after the first flip is queued. Fortunately the
6446 * blit ring generates interrupts properly, so use it instead.
6447 */
6448static int intel_gen7_queue_flip(struct drm_device *dev,
6449 struct drm_crtc *crtc,
6450 struct drm_framebuffer *fb,
6451 struct drm_i915_gem_object *obj)
6452{
6453 struct drm_i915_private *dev_priv = dev->dev_private;
6454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6456 int ret;
6457
6458 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6459 if (ret)
6460 goto out;
6461
6462 ret = intel_ring_begin(ring, 4);
6463 if (ret)
6464 goto out;
6465
6466 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6467 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6468 intel_ring_emit(ring, (obj->gtt_offset));
6469 intel_ring_emit(ring, (MI_NOOP));
6470 intel_ring_advance(ring);
6471out:
6472 return ret;
6473}
6474
8c9f3aaf
JB		 6475static int intel_default_queue_flip(struct drm_device *dev,
6476 struct drm_crtc *crtc,
6477 struct drm_framebuffer *fb,
6478 struct drm_i915_gem_object *obj)
6479{
6480 return -ENODEV;
6481}
6482
6b95a207
KH		 6483static int intel_crtc_page_flip(struct drm_crtc *crtc,
6484 struct drm_framebuffer *fb,
6485 struct drm_pending_vblank_event *event)
6486{
6487 struct drm_device *dev = crtc->dev;
6488 struct drm_i915_private *dev_priv = dev->dev_private;
6489 struct intel_framebuffer *intel_fb;
05394f39 6490 struct drm_i915_gem_object *obj;
6b95a207
KH		 6491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492 struct intel_unpin_work *work;
8c9f3aaf 6493 unsigned long flags;
52e68630 6494 int ret;
6b95a207
KH		 6495
6496 work = kzalloc(sizeof *work, GFP_KERNEL);
6497 if (work == NULL)
6498 return -ENOMEM;
6499
6b95a207
KH		 6500 work->event = event;
6501 work->dev = crtc->dev;
6502 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6503 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6504 INIT_WORK(&work->work, intel_unpin_work_fn);
6505
6506 /* We borrow the event spin lock for protecting unpin_work */
6507 spin_lock_irqsave(&dev->event_lock, flags);
6508 if (intel_crtc->unpin_work) {
6509 spin_unlock_irqrestore(&dev->event_lock, flags);
6510 kfree(work);
468f0b44
CW		 6511
6512 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6513 return -EBUSY;
6514 }
6515 intel_crtc->unpin_work = work;
6516 spin_unlock_irqrestore(&dev->event_lock, flags);
6517
6518 intel_fb = to_intel_framebuffer(fb);
6519 obj = intel_fb->obj;
6520
468f0b44 6521 mutex_lock(&dev->struct_mutex);
6b95a207 6522
75dfca80 6523 /* Reference the objects for the scheduled work. */
05394f39
CW		 6524 drm_gem_object_reference(&work->old_fb_obj->base);
6525 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6526
6527 crtc->fb = fb;
96b099fd
CW		 6528
6529 ret = drm_vblank_get(dev, intel_crtc->pipe);
6530 if (ret)
6531 goto cleanup_objs;
6532
e1f99ce6 6533 work->pending_flip_obj = obj;
e1f99ce6 6534
4e5359cd
SF		 6535 work->enable_stall_check = true;
6536
e1f99ce6
CW		 6537 /* Block clients from rendering to the new back buffer until
6538 * the flip occurs and the object is no longer visible.
6539 */
05394f39 6540 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6541
8c9f3aaf
JB		 6542 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6543 if (ret)
6544 goto cleanup_pending;
6b95a207
KH		 6545
6546 mutex_unlock(&dev->struct_mutex);
6547
e5510fac
JB		 6548 trace_i915_flip_request(intel_crtc->plane, obj);
6549
6b95a207 6550 return 0;
96b099fd 6551
8c9f3aaf
JB		 6552cleanup_pending:
6553 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6554cleanup_objs:
05394f39
CW		 6555 drm_gem_object_unreference(&work->old_fb_obj->base);
6556 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6557 mutex_unlock(&dev->struct_mutex);
6558
6559 spin_lock_irqsave(&dev->event_lock, flags);
6560 intel_crtc->unpin_work = NULL;
6561 spin_unlock_irqrestore(&dev->event_lock, flags);
6562
6563 kfree(work);
6564
6565 return ret;
6b95a207
KH		 6566}
6567
47f1c6c9
CW		 6568static void intel_sanitize_modesetting(struct drm_device *dev,
6569 int pipe, int plane)
6570{
6571 struct drm_i915_private *dev_priv = dev->dev_private;
6572 u32 reg, val;
6573
6574 if (HAS_PCH_SPLIT(dev))
6575 return;
6576
6577 /* Who knows what state these registers were left in by the BIOS or
6578 * grub?
6579 *
6580 * If we leave the registers in a conflicting state (e.g. with the
6581 * display plane reading from the other pipe than the one we intend
6582 * to use) then when we attempt to teardown the active mode, we will
6583 * not disable the pipes and planes in the correct order -- leaving
6584 * a plane reading from a disabled pipe and possibly leading to
6585 * undefined behaviour.
6586 */
6587
6588 reg = DSPCNTR(plane);
6589 val = I915_READ(reg);
6590
6591 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6592 return;
6593 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6594 return;
6595
6596 /* This display plane is active and attached to the other CPU pipe. */
6597 pipe = !pipe;
6598
6599 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6600 intel_disable_plane(dev_priv, plane, pipe);
6601 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6602}
79e53945 6603
f6e5b160
CW		 6604static void intel_crtc_reset(struct drm_crtc *crtc)
6605{
6606 struct drm_device *dev = crtc->dev;
6607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6608
6609 /* Reset flags back to the 'unknown' status so that they
6610 * will be correctly set on the initial modeset.
6611 */
6612 intel_crtc->dpms_mode = -1;
6613
6614 /* We need to fix up any BIOS configuration that conflicts with
6615 * our expectations.
6616 */
6617 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6618}
6619
6620static struct drm_crtc_helper_funcs intel_helper_funcs = {
6621 .dpms = intel_crtc_dpms,
6622 .mode_fixup = intel_crtc_mode_fixup,
6623 .mode_set = intel_crtc_mode_set,
6624 .mode_set_base = intel_pipe_set_base,
6625 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6626 .load_lut = intel_crtc_load_lut,
6627 .disable = intel_crtc_disable,
6628};
6629
6630static const struct drm_crtc_funcs intel_crtc_funcs = {
6631 .reset = intel_crtc_reset,
6632 .cursor_set = intel_crtc_cursor_set,
6633 .cursor_move = intel_crtc_cursor_move,
6634 .gamma_set = intel_crtc_gamma_set,
6635 .set_config = drm_crtc_helper_set_config,
6636 .destroy = intel_crtc_destroy,
6637 .page_flip = intel_crtc_page_flip,
6638};
6639
b358d0a6 6640static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6641{
22fd0fab 6642 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6643 struct intel_crtc *intel_crtc;
6644 int i;
6645
6646 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6647 if (intel_crtc == NULL)
6648 return;
6649
6650 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6651
6652 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6653 for (i = 0; i < 256; i++) {
6654 intel_crtc->lut_r[i] = i;
6655 intel_crtc->lut_g[i] = i;
6656 intel_crtc->lut_b[i] = i;
6657 }
6658
80824003
JB		 6659 /* Swap pipes & planes for FBC on pre-965 */
6660 intel_crtc->pipe = pipe;
6661 intel_crtc->plane = pipe;
e2e767ab 6662 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6663 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6664 intel_crtc->plane = !pipe;
80824003
JB		 6665 }
6666
22fd0fab
JB		 6667 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6668 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6669 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6670 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6671
5d1d0cc8 6672 intel_crtc_reset(&intel_crtc->base);
04dbff52 6673 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6674
6675 if (HAS_PCH_SPLIT(dev)) {
6676 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6677 intel_helper_funcs.commit = ironlake_crtc_commit;
6678 } else {
6679 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6680 intel_helper_funcs.commit = i9xx_crtc_commit;
6681 }
6682
79e53945
JB		 6683 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6684
652c393a
JB		 6685 intel_crtc->busy = false;
6686
6687 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6688 (unsigned long)intel_crtc);
79e53945
JB		 6689}
6690
08d7b3d1 6691int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6692 struct drm_file *file)
08d7b3d1
CW		 6693{
6694 drm_i915_private_t *dev_priv = dev->dev_private;
6695 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6696 struct drm_mode_object *drmmode_obj;
6697 struct intel_crtc *crtc;
08d7b3d1
CW		 6698
6699 if (!dev_priv) {
6700 DRM_ERROR("called with no initialization\n");
6701 return -EINVAL;
6702 }
6703
c05422d5
DV		 6704 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6705 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6706
c05422d5 6707 if (!drmmode_obj) {
08d7b3d1
CW		 6708 DRM_ERROR("no such CRTC id\n");
6709 return -EINVAL;
6710 }
6711
c05422d5
DV		 6712 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6713 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6714
c05422d5 6715 return 0;
08d7b3d1
CW		 6716}
6717
c5e4df33 6718static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6719{
4ef69c7a 6720 struct intel_encoder *encoder;
79e53945 6721 int index_mask = 0;
79e53945
JB		 6722 int entry = 0;
6723
4ef69c7a
CW		 6724 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6725 if (type_mask & encoder->clone_mask)
79e53945
JB		 6726 index_mask |= (1 << entry);
6727 entry++;
6728 }
4ef69c7a 6729
79e53945
JB		 6730 return index_mask;
6731}
6732
4d302442
CW		 6733static bool has_edp_a(struct drm_device *dev)
6734{
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736
6737 if (!IS_MOBILE(dev))
6738 return false;
6739
6740 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6741 return false;
6742
6743 if (IS_GEN5(dev) &&
6744 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6745 return false;
6746
6747 return true;
6748}
6749
79e53945
JB		 6750static void intel_setup_outputs(struct drm_device *dev)
6751{
725e30ad 6752 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6753 struct intel_encoder *encoder;
cb0953d7 6754 bool dpd_is_edp = false;
c5d1b51d 6755 bool has_lvds = false;
79e53945 6756
541998a1 6757 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6758 has_lvds = intel_lvds_init(dev);
6759 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6760 /* disable the panel fitter on everything but LVDS */
6761 I915_WRITE(PFIT_CONTROL, 0);
6762 }
79e53945 6763
bad720ff 6764 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6765 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6766
4d302442 6767 if (has_edp_a(dev))
32f9d658
ZW		 6768 intel_dp_init(dev, DP_A);
6769
cb0953d7
AJ		 6770 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6771 intel_dp_init(dev, PCH_DP_D);
6772 }
6773
6774 intel_crt_init(dev);
6775
6776 if (HAS_PCH_SPLIT(dev)) {
6777 int found;
6778
30ad48b7 6779 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6780 /* PCH SDVOB multiplex with HDMIB */
6781 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6782 if (!found)
6783 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6784 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6785 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6786 }
6787
6788 if (I915_READ(HDMIC) & PORT_DETECTED)
6789 intel_hdmi_init(dev, HDMIC);
6790
6791 if (I915_READ(HDMID) & PORT_DETECTED)
6792 intel_hdmi_init(dev, HDMID);
6793
5eb08b69
ZW		 6794 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6795 intel_dp_init(dev, PCH_DP_C);
6796
cb0953d7 6797 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6798 intel_dp_init(dev, PCH_DP_D);
6799
103a196f 6800 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6801 bool found = false;
7d57382e 6802
725e30ad 6803 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6804 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6805 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6806 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6807 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6808 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6809 }
27185ae1 6810
b01f2c3a
JB		 6811 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6812 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6813 intel_dp_init(dev, DP_B);
b01f2c3a 6814 }
725e30ad 6815 }
13520b05
KH		 6816
6817 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6818
b01f2c3a
JB		 6819 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6820 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6821 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6822 }
27185ae1
ML		 6823
6824 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6825
b01f2c3a
JB		 6826 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6827 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6828 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6829 }
6830 if (SUPPORTS_INTEGRATED_DP(dev)) {
6831 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6832 intel_dp_init(dev, DP_C);
b01f2c3a 6833 }
725e30ad 6834 }
27185ae1 6835
b01f2c3a
JB		 6836 if (SUPPORTS_INTEGRATED_DP(dev) &&
6837 (I915_READ(DP_D) & DP_DETECTED)) {
6838 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6839 intel_dp_init(dev, DP_D);
b01f2c3a 6840 }
bad720ff 6841 } else if (IS_GEN2(dev))
79e53945
JB		 6842 intel_dvo_init(dev);
6843
103a196f 6844 if (SUPPORTS_TV(dev))
79e53945
JB		 6845 intel_tv_init(dev);
6846
4ef69c7a
CW		 6847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6848 encoder->base.possible_crtcs = encoder->crtc_mask;
6849 encoder->base.possible_clones =
6850 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6851 }
47356eb6
CW		 6852
6853 intel_panel_setup_backlight(dev);
2c7111db
CW		 6854
6855 /* disable all the possible outputs/crtcs before entering KMS mode */
6856 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6857}
6858
6859static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6860{
6861 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6862
6863 drm_framebuffer_cleanup(fb);
05394f39 6864 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6865
6866 kfree(intel_fb);
6867}
6868
6869static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6870 struct drm_file *file,
79e53945
JB		 6871 unsigned int *handle)
6872{
6873 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6874 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6875
05394f39 6876 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6877}
6878
6879static const struct drm_framebuffer_funcs intel_fb_funcs = {
6880 .destroy = intel_user_framebuffer_destroy,
6881 .create_handle = intel_user_framebuffer_create_handle,
6882};
6883
38651674
DA		 6884int intel_framebuffer_init(struct drm_device *dev,
6885 struct intel_framebuffer *intel_fb,
6886 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6887 struct drm_i915_gem_object *obj)
79e53945 6888{
79e53945
JB		 6889 int ret;
6890
05394f39 6891 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6892 return -EINVAL;
6893
6894 if (mode_cmd->pitch & 63)
6895 return -EINVAL;
6896
6897 switch (mode_cmd->bpp) {
6898 case 8:
6899 case 16:
6900 case 24:
6901 case 32:
6902 break;
6903 default:
6904 return -EINVAL;
6905 }
6906
79e53945
JB		 6907 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6908 if (ret) {
6909 DRM_ERROR("framebuffer init failed %d\n", ret);
6910 return ret;
6911 }
6912
6913 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6914 intel_fb->obj = obj;
79e53945
JB		 6915 return 0;
6916}
6917
79e53945
JB		 6918static struct drm_framebuffer *
6919intel_user_framebuffer_create(struct drm_device *dev,
6920 struct drm_file *filp,
6921 struct drm_mode_fb_cmd *mode_cmd)
6922{
05394f39 6923 struct drm_i915_gem_object *obj;
79e53945 6924
05394f39 6925 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6926 if (&obj->base == NULL)
cce13ff7 6927 return ERR_PTR(-ENOENT);
79e53945 6928
d2dff872 6929 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6930}
6931
79e53945 6932static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6933 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6934 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6935};
6936
05394f39 6937static struct drm_i915_gem_object *
aa40d6bb 6938intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6939{
05394f39 6940 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6941 int ret;
6942
2c34b850
BW		 6943 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6944
aa40d6bb
ZN		 6945 ctx = i915_gem_alloc_object(dev, 4096);
6946 if (!ctx) {
9ea8d059
CW		 6947 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6948 return NULL;
6949 }
6950
75e9e915 6951 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6952 if (ret) {
6953 DRM_ERROR("failed to pin power context: %d\n", ret);
6954 goto err_unref;
6955 }
6956
aa40d6bb 6957 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6958 if (ret) {
6959 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6960 goto err_unpin;
6961 }
9ea8d059 6962
aa40d6bb 6963 return ctx;
9ea8d059
CW		 6964
6965err_unpin:
aa40d6bb 6966 i915_gem_object_unpin(ctx);
9ea8d059 6967err_unref:
05394f39 6968 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6969 mutex_unlock(&dev->struct_mutex);
6970 return NULL;
6971}
6972
7648fa99
JB		 6973bool ironlake_set_drps(struct drm_device *dev, u8 val)
6974{
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 u16 rgvswctl;
6977
6978 rgvswctl = I915_READ16(MEMSWCTL);
6979 if (rgvswctl & MEMCTL_CMD_STS) {
6980 DRM_DEBUG("gpu busy, RCS change rejected\n");
6981 return false; /* still busy with another command */
6982 }
6983
6984 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6985 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6986 I915_WRITE16(MEMSWCTL, rgvswctl);
6987 POSTING_READ16(MEMSWCTL);
6988
6989 rgvswctl |= MEMCTL_CMD_STS;
6990 I915_WRITE16(MEMSWCTL, rgvswctl);
6991
6992 return true;
6993}
6994
f97108d1
JB		 6995void ironlake_enable_drps(struct drm_device *dev)
6996{
6997 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6998 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 6999 u8 fmax, fmin, fstart, vstart;
f97108d1 7000
ea056c14
JB		 7001 /* Enable temp reporting */
7002 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7003 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7004
f97108d1
JB		 7005 /* 100ms RC evaluation intervals */
7006 I915_WRITE(RCUPEI, 100000);
7007 I915_WRITE(RCDNEI, 100000);
7008
7009 /* Set max/min thresholds to 90ms and 80ms respectively */
7010 I915_WRITE(RCBMAXAVG, 90000);
7011 I915_WRITE(RCBMINAVG, 80000);
7012
7013 I915_WRITE(MEMIHYST, 1);
7014
7015 /* Set up min, max, and cur for interrupt handling */
7016 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7017 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7018 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7019 MEMMODE_FSTART_SHIFT;
7648fa99 7020
f97108d1
JB		 7021 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7022 PXVFREQ_PX_SHIFT;
7023
80dbf4b7 7024 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7025 dev_priv->fstart = fstart;
7026
80dbf4b7 7027 dev_priv->max_delay = fstart;
f97108d1
JB		 7028 dev_priv->min_delay = fmin;
7029 dev_priv->cur_delay = fstart;
7030
80dbf4b7
JB		 7031 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7032 fmax, fmin, fstart);
7648fa99 7033
f97108d1
JB		 7034 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7035
7036 /*
7037 * Interrupts will be enabled in ironlake_irq_postinstall
7038 */
7039
7040 I915_WRITE(VIDSTART, vstart);
7041 POSTING_READ(VIDSTART);
7042
7043 rgvmodectl |= MEMMODE_SWMODE_EN;
7044 I915_WRITE(MEMMODECTL, rgvmodectl);
7045
481b6af3 7046 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7047 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7048 msleep(1);
7049
7648fa99 7050 ironlake_set_drps(dev, fstart);
f97108d1 7051
7648fa99
JB		 7052 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7053 I915_READ(0x112e0);
7054 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7055 dev_priv->last_count2 = I915_READ(0x112f4);
7056 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7057}
7058
7059void ironlake_disable_drps(struct drm_device *dev)
7060{
7061 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7062 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7063
7064 /* Ack interrupts, disable EFC interrupt */
7065 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7066 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7067 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7068 I915_WRITE(DEIIR, DE_PCU_EVENT);
7069 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7070
7071 /* Go back to the starting frequency */
7648fa99 7072 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7073 msleep(1);
7074 rgvswctl |= MEMCTL_CMD_STS;
7075 I915_WRITE(MEMSWCTL, rgvswctl);
7076 msleep(1);
7077
7078}
7079
3b8d8d91
JB		 7080void gen6_set_rps(struct drm_device *dev, u8 val)
7081{
7082 struct drm_i915_private *dev_priv = dev->dev_private;
7083 u32 swreq;
7084
7085 swreq = (val & 0x3ff) << 25;
7086 I915_WRITE(GEN6_RPNSWREQ, swreq);
7087}
7088
7089void gen6_disable_rps(struct drm_device *dev)
7090{
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092
7093 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7094 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7095 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7096
7097 spin_lock_irq(&dev_priv->rps_lock);
7098 dev_priv->pm_iir = 0;
7099 spin_unlock_irq(&dev_priv->rps_lock);
7100
3b8d8d91
JB		 7101 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7102}
7103
7648fa99
JB		 7104static unsigned long intel_pxfreq(u32 vidfreq)
7105{
7106 unsigned long freq;
7107 int div = (vidfreq & 0x3f0000) >> 16;
7108 int post = (vidfreq & 0x3000) >> 12;
7109 int pre = (vidfreq & 0x7);
7110
7111 if (!pre)
7112 return 0;
7113
7114 freq = ((div * 133333) / ((1<<post) * pre));
7115
7116 return freq;
7117}
7118
7119void intel_init_emon(struct drm_device *dev)
7120{
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122 u32 lcfuse;
7123 u8 pxw[16];
7124 int i;
7125
7126 /* Disable to program */
7127 I915_WRITE(ECR, 0);
7128 POSTING_READ(ECR);
7129
7130 /* Program energy weights for various events */
7131 I915_WRITE(SDEW, 0x15040d00);
7132 I915_WRITE(CSIEW0, 0x007f0000);
7133 I915_WRITE(CSIEW1, 0x1e220004);
7134 I915_WRITE(CSIEW2, 0x04000004);
7135
7136 for (i = 0; i < 5; i++)
7137 I915_WRITE(PEW + (i * 4), 0);
7138 for (i = 0; i < 3; i++)
7139 I915_WRITE(DEW + (i * 4), 0);
7140
7141 /* Program P-state weights to account for frequency power adjustment */
7142 for (i = 0; i < 16; i++) {
7143 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7144 unsigned long freq = intel_pxfreq(pxvidfreq);
7145 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7146 PXVFREQ_PX_SHIFT;
7147 unsigned long val;
7148
7149 val = vid * vid;
7150 val *= (freq / 1000);
7151 val *= 255;
7152 val /= (127*127*900);
7153 if (val > 0xff)
7154 DRM_ERROR("bad pxval: %ld\n", val);
7155 pxw[i] = val;
7156 }
7157 /* Render standby states get 0 weight */
7158 pxw[14] = 0;
7159 pxw[15] = 0;
7160
7161 for (i = 0; i < 4; i++) {
7162 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7163 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7164 I915_WRITE(PXW + (i * 4), val);
7165 }
7166
7167 /* Adjust magic regs to magic values (more experimental results) */
7168 I915_WRITE(OGW0, 0);
7169 I915_WRITE(OGW1, 0);
7170 I915_WRITE(EG0, 0x00007f00);
7171 I915_WRITE(EG1, 0x0000000e);
7172 I915_WRITE(EG2, 0x000e0000);
7173 I915_WRITE(EG3, 0x68000300);
7174 I915_WRITE(EG4, 0x42000000);
7175 I915_WRITE(EG5, 0x00140031);
7176 I915_WRITE(EG6, 0);
7177 I915_WRITE(EG7, 0);
7178
7179 for (i = 0; i < 8; i++)
7180 I915_WRITE(PXWL + (i * 4), 0);
7181
7182 /* Enable PMON + select events */
7183 I915_WRITE(ECR, 0x80000019);
7184
7185 lcfuse = I915_READ(LCFUSE02);
7186
7187 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7188}
7189
3b8d8d91 7190void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7191{
a6044e23
JB		 7192 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7193 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7194 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7195 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7196 int i;
7197
7198 /* Here begins a magic sequence of register writes to enable
7199 * auto-downclocking.
7200 *
7201 * Perhaps there might be some value in exposing these to
7202 * userspace...
7203 */
7204 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7205 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7206 gen6_gt_force_wake_get(dev_priv);
8fd26859 7207
3b8d8d91 7208 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7209 I915_WRITE(GEN6_RC_CONTROL, 0);
7210
7211 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7212 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7213 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7214 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7215 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7216
7217 for (i = 0; i < I915_NUM_RINGS; i++)
7218 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7219
7220 I915_WRITE(GEN6_RC_SLEEP, 0);
7221 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7222 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7223 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7224 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7225
7df8721b
JB		 7226 if (i915_enable_rc6)
7227 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7228 GEN6_RC_CTL_RC6_ENABLE;
7229
8fd26859 7230 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7231 rc6_mask |
9c3d2f7f 7232 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7233 GEN6_RC_CTL_HW_ENABLE);
7234
3b8d8d91 7235 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7236 GEN6_FREQUENCY(10) |
7237 GEN6_OFFSET(0) |
7238 GEN6_AGGRESSIVE_TURBO);
7239 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7240 GEN6_FREQUENCY(12));
7241
7242 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7243 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7244 18 << 24 |
7245 6 << 16);
ccab5c82
JB		 7246 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7247 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7248 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7249 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7250 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7251 I915_WRITE(GEN6_RP_CONTROL,
7252 GEN6_RP_MEDIA_TURBO |
7253 GEN6_RP_USE_NORMAL_FREQ |
7254 GEN6_RP_MEDIA_IS_GFX |
7255 GEN6_RP_ENABLE |
ccab5c82
JB		 7256 GEN6_RP_UP_BUSY_AVG |
7257 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7258
7259 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7260 500))
7261 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7262
7263 I915_WRITE(GEN6_PCODE_DATA, 0);
7264 I915_WRITE(GEN6_PCODE_MAILBOX,
7265 GEN6_PCODE_READY |
7266 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7267 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7268 500))
7269 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7270
a6044e23
JB		 7271 min_freq = (rp_state_cap & 0xff0000) >> 16;
7272 max_freq = rp_state_cap & 0xff;
7273 cur_freq = (gt_perf_status & 0xff00) >> 8;
7274
7275 /* Check for overclock support */
7276 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7277 500))
7278 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7279 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7280 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7281 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7282 500))
7283 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7284 if (pcu_mbox & (1<<31)) { /* OC supported */
7285 max_freq = pcu_mbox & 0xff;
e281fcaa 7286 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7287 }
7288
7289 /* In units of 100MHz */
7290 dev_priv->max_delay = max_freq;
7291 dev_priv->min_delay = min_freq;
7292 dev_priv->cur_delay = cur_freq;
7293
8fd26859
CW		 7294 /* requires MSI enabled */
7295 I915_WRITE(GEN6_PMIER,
7296 GEN6_PM_MBOX_EVENT |
7297 GEN6_PM_THERMAL_EVENT |
7298 GEN6_PM_RP_DOWN_TIMEOUT |
7299 GEN6_PM_RP_UP_THRESHOLD |
7300 GEN6_PM_RP_DOWN_THRESHOLD |
7301 GEN6_PM_RP_UP_EI_EXPIRED |
7302 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7303 spin_lock_irq(&dev_priv->rps_lock);
7304 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7305 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7306 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7307 /* enable all PM interrupts */
7308 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7309
fcca7926 7310 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7311 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7312}
7313
6067aaea
JB		 7314static void ironlake_init_clock_gating(struct drm_device *dev)
7315{
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7318
7319 /* Required for FBC */
7320 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7321 DPFCRUNIT_CLOCK_GATE_DISABLE |
7322 DPFDUNIT_CLOCK_GATE_DISABLE;
7323 /* Required for CxSR */
7324 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7325
7326 I915_WRITE(PCH_3DCGDIS0,
7327 MARIUNIT_CLOCK_GATE_DISABLE |
7328 SVSMUNIT_CLOCK_GATE_DISABLE);
7329 I915_WRITE(PCH_3DCGDIS1,
7330 VFMUNIT_CLOCK_GATE_DISABLE);
7331
7332 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7333
6067aaea
JB		 7334 /*
7335 * According to the spec the following bits should be set in
7336 * order to enable memory self-refresh
7337 * The bit 22/21 of 0x42004
7338 * The bit 5 of 0x42020
7339 * The bit 15 of 0x45000
7340 */
7341 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7342 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7343 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7344 I915_WRITE(ILK_DSPCLK_GATE,
7345 (I915_READ(ILK_DSPCLK_GATE) |
7346 ILK_DPARB_CLK_GATE));
7347 I915_WRITE(DISP_ARB_CTL,
7348 (I915_READ(DISP_ARB_CTL) |
7349 DISP_FBC_WM_DIS));
7350 I915_WRITE(WM3_LP_ILK, 0);
7351 I915_WRITE(WM2_LP_ILK, 0);
7352 I915_WRITE(WM1_LP_ILK, 0);
7353
7354 /*
7355 * Based on the document from hardware guys the following bits
7356 * should be set unconditionally in order to enable FBC.
7357 * The bit 22 of 0x42000
7358 * The bit 22 of 0x42004
7359 * The bit 7,8,9 of 0x42020.
7360 */
7361 if (IS_IRONLAKE_M(dev)) {
7362 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7363 I915_READ(ILK_DISPLAY_CHICKEN1) |
7364 ILK_FBCQ_DIS);
7365 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7366 I915_READ(ILK_DISPLAY_CHICKEN2) |
7367 ILK_DPARB_GATE);
7368 I915_WRITE(ILK_DSPCLK_GATE,
7369 I915_READ(ILK_DSPCLK_GATE) |
7370 ILK_DPFC_DIS1 |
7371 ILK_DPFC_DIS2 |
7372 ILK_CLK_FBC);
7373 }
7374
7375 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7376 I915_READ(ILK_DISPLAY_CHICKEN2) |
7377 ILK_ELPIN_409_SELECT);
7378 I915_WRITE(_3D_CHICKEN2,
7379 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7380 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7381}
7382
6067aaea 7383static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7384{
7385 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7386 int pipe;
6067aaea
JB		 7387 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7388
7389 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7390
6067aaea
JB		 7391 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7392 I915_READ(ILK_DISPLAY_CHICKEN2) |
7393 ILK_ELPIN_409_SELECT);
8956c8bb 7394
6067aaea
JB		 7395 I915_WRITE(WM3_LP_ILK, 0);
7396 I915_WRITE(WM2_LP_ILK, 0);
7397 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7398
7399 /*
6067aaea
JB		 7400 * According to the spec the following bits should be
7401 * set in order to enable memory self-refresh and fbc:
7402 * The bit21 and bit22 of 0x42000
7403 * The bit21 and bit22 of 0x42004
7404 * The bit5 and bit7 of 0x42020
7405 * The bit14 of 0x70180
7406 * The bit14 of 0x71180
652c393a 7407 */
6067aaea
JB		 7408 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7409 I915_READ(ILK_DISPLAY_CHICKEN1) |
7410 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7411 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7412 I915_READ(ILK_DISPLAY_CHICKEN2) |
7413 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7414 I915_WRITE(ILK_DSPCLK_GATE,
7415 I915_READ(ILK_DSPCLK_GATE) |
7416 ILK_DPARB_CLK_GATE |
7417 ILK_DPFD_CLK_GATE);
8956c8bb 7418
6067aaea
JB		 7419 for_each_pipe(pipe)
7420 I915_WRITE(DSPCNTR(pipe),
7421 I915_READ(DSPCNTR(pipe)) |
7422 DISPPLANE_TRICKLE_FEED_DISABLE);
7423}
8956c8bb 7424
28963a3e
JB		 7425static void ivybridge_init_clock_gating(struct drm_device *dev)
7426{
7427 struct drm_i915_private *dev_priv = dev->dev_private;
7428 int pipe;
7429 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7430
28963a3e 7431 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7432
28963a3e
JB		 7433 I915_WRITE(WM3_LP_ILK, 0);
7434 I915_WRITE(WM2_LP_ILK, 0);
7435 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7436
28963a3e 7437 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7438
28963a3e
JB		 7439 for_each_pipe(pipe)
7440 I915_WRITE(DSPCNTR(pipe),
7441 I915_READ(DSPCNTR(pipe)) |
7442 DISPPLANE_TRICKLE_FEED_DISABLE);
7443}
7444
6067aaea
JB		 7445static void g4x_init_clock_gating(struct drm_device *dev)
7446{
7447 struct drm_i915_private *dev_priv = dev->dev_private;
7448 uint32_t dspclk_gate;
8fd26859 7449
6067aaea
JB		 7450 I915_WRITE(RENCLK_GATE_D1, 0);
7451 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7452 GS_UNIT_CLOCK_GATE_DISABLE |
7453 CL_UNIT_CLOCK_GATE_DISABLE);
7454 I915_WRITE(RAMCLK_GATE_D, 0);
7455 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7456 OVRUNIT_CLOCK_GATE_DISABLE |
7457 OVCUNIT_CLOCK_GATE_DISABLE;
7458 if (IS_GM45(dev))
7459 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7460 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7461}
1398261a 7462
6067aaea
JB		 7463static void crestline_init_clock_gating(struct drm_device *dev)
7464{
7465 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7466
6067aaea
JB		 7467 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7468 I915_WRITE(RENCLK_GATE_D2, 0);
7469 I915_WRITE(DSPCLK_GATE_D, 0);
7470 I915_WRITE(RAMCLK_GATE_D, 0);
7471 I915_WRITE16(DEUC, 0);
7472}
652c393a 7473
6067aaea
JB		 7474static void broadwater_init_clock_gating(struct drm_device *dev)
7475{
7476 struct drm_i915_private *dev_priv = dev->dev_private;
7477
7478 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7479 I965_RCC_CLOCK_GATE_DISABLE |
7480 I965_RCPB_CLOCK_GATE_DISABLE |
7481 I965_ISC_CLOCK_GATE_DISABLE |
7482 I965_FBC_CLOCK_GATE_DISABLE);
7483 I915_WRITE(RENCLK_GATE_D2, 0);
7484}
7485
7486static void gen3_init_clock_gating(struct drm_device *dev)
7487{
7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489 u32 dstate = I915_READ(D_STATE);
7490
7491 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7492 DSTATE_DOT_CLOCK_GATING;
7493 I915_WRITE(D_STATE, dstate);
7494}
7495
7496static void i85x_init_clock_gating(struct drm_device *dev)
7497{
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499
7500 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7501}
7502
7503static void i830_init_clock_gating(struct drm_device *dev)
7504{
7505 struct drm_i915_private *dev_priv = dev->dev_private;
7506
7507 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7508}
7509
645c62a5
JB		 7510static void ibx_init_clock_gating(struct drm_device *dev)
7511{
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513
7514 /*
7515 * On Ibex Peak and Cougar Point, we need to disable clock
7516 * gating for the panel power sequencer or it will fail to
7517 * start up when no ports are active.
7518 */
7519 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7520}
7521
7522static void cpt_init_clock_gating(struct drm_device *dev)
7523{
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525
7526 /*
7527 * On Ibex Peak and Cougar Point, we need to disable clock
7528 * gating for the panel power sequencer or it will fail to
7529 * start up when no ports are active.
7530 */
7531 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7532 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7533 DPLS_EDP_PPS_FIX_DIS);
652c393a
JB		 7534}
7535
ac668088 7536static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7537{
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539
7540 if (dev_priv->renderctx) {
ac668088
CW		 7541 i915_gem_object_unpin(dev_priv->renderctx);
7542 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7543 dev_priv->renderctx = NULL;
7544 }
7545
7546 if (dev_priv->pwrctx) {
ac668088
CW		 7547 i915_gem_object_unpin(dev_priv->pwrctx);
7548 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7549 dev_priv->pwrctx = NULL;
7550 }
7551}
7552
7553static void ironlake_disable_rc6(struct drm_device *dev)
7554{
7555 struct drm_i915_private *dev_priv = dev->dev_private;
7556
7557 if (I915_READ(PWRCTXA)) {
7558 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7559 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7560 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7561 50);
0cdab21f
CW		 7562
7563 I915_WRITE(PWRCTXA, 0);
7564 POSTING_READ(PWRCTXA);
7565
ac668088
CW		 7566 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7567 POSTING_READ(RSTDBYCTL);
0cdab21f 7568 }
ac668088 7569
99507307 7570 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7571}
7572
ac668088 7573static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7574{
7575 struct drm_i915_private *dev_priv = dev->dev_private;
7576
ac668088
CW		 7577 if (dev_priv->renderctx == NULL)
7578 dev_priv->renderctx = intel_alloc_context_page(dev);
7579 if (!dev_priv->renderctx)
7580 return -ENOMEM;
7581
7582 if (dev_priv->pwrctx == NULL)
7583 dev_priv->pwrctx = intel_alloc_context_page(dev);
7584 if (!dev_priv->pwrctx) {
7585 ironlake_teardown_rc6(dev);
7586 return -ENOMEM;
7587 }
7588
7589 return 0;
d5bb081b
JB		 7590}
7591
7592void ironlake_enable_rc6(struct drm_device *dev)
7593{
7594 struct drm_i915_private *dev_priv = dev->dev_private;
7595 int ret;
7596
ac668088
CW		 7597 /* rc6 disabled by default due to repeated reports of hanging during
7598 * boot and resume.
7599 */
7600 if (!i915_enable_rc6)
7601 return;
7602
2c34b850 7603 mutex_lock(&dev->struct_mutex);
ac668088 7604 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7605 if (ret) {
7606 mutex_unlock(&dev->struct_mutex);
ac668088 7607 return;
2c34b850 7608 }
ac668088 7609
d5bb081b
JB		 7610 /*
7611 * GPU can automatically power down the render unit if given a page
7612 * to save state.
7613 */
7614 ret = BEGIN_LP_RING(6);
7615 if (ret) {
ac668088 7616 ironlake_teardown_rc6(dev);
2c34b850 7617 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7618 return;
7619 }
ac668088 7620
d5bb081b
JB		 7621 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7622 OUT_RING(MI_SET_CONTEXT);
7623 OUT_RING(dev_priv->renderctx->gtt_offset |
7624 MI_MM_SPACE_GTT |
7625 MI_SAVE_EXT_STATE_EN |
7626 MI_RESTORE_EXT_STATE_EN |
7627 MI_RESTORE_INHIBIT);
7628 OUT_RING(MI_SUSPEND_FLUSH);
7629 OUT_RING(MI_NOOP);
7630 OUT_RING(MI_FLUSH);
7631 ADVANCE_LP_RING();
7632
4a246cfc
BW		 7633 /*
7634 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7635 * does an implicit flush, combined with MI_FLUSH above, it should be
7636 * safe to assume that renderctx is valid
7637 */
7638 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7639 if (ret) {
7640 DRM_ERROR("failed to enable ironlake power power savings\n");
7641 ironlake_teardown_rc6(dev);
7642 mutex_unlock(&dev->struct_mutex);
7643 return;
7644 }
7645
d5bb081b
JB		 7646 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7647 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7648 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7649}
7650
645c62a5
JB		 7651void intel_init_clock_gating(struct drm_device *dev)
7652{
7653 struct drm_i915_private *dev_priv = dev->dev_private;
7654
7655 dev_priv->display.init_clock_gating(dev);
7656
7657 if (dev_priv->display.init_pch_clock_gating)
7658 dev_priv->display.init_pch_clock_gating(dev);
7659}
ac668088 7660
e70236a8
JB		 7661/* Set up chip specific display functions */
7662static void intel_init_display(struct drm_device *dev)
7663{
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665
7666 /* We always want a DPMS function */
f564048e 7667 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7668 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7669 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7670 } else {
e70236a8 7671 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7672 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7673 }
e70236a8 7674
ee5382ae 7675 if (I915_HAS_FBC(dev)) {
9c04f015 7676 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7677 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7678 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7679 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7680 } else if (IS_GM45(dev)) {
74dff282
JB		 7681 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7682 dev_priv->display.enable_fbc = g4x_enable_fbc;
7683 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7684 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7685 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7686 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7687 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7688 }
74dff282 7689 /* 855GM needs testing */
e70236a8
JB		 7690 }
7691
7692 /* Returns the core display clock speed */
f2b115e6 7693 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7694 dev_priv->display.get_display_clock_speed =
7695 i945_get_display_clock_speed;
7696 else if (IS_I915G(dev))
7697 dev_priv->display.get_display_clock_speed =
7698 i915_get_display_clock_speed;
f2b115e6 7699 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7700 dev_priv->display.get_display_clock_speed =
7701 i9xx_misc_get_display_clock_speed;
7702 else if (IS_I915GM(dev))
7703 dev_priv->display.get_display_clock_speed =
7704 i915gm_get_display_clock_speed;
7705 else if (IS_I865G(dev))
7706 dev_priv->display.get_display_clock_speed =
7707 i865_get_display_clock_speed;
f0f8a9ce 7708 else if (IS_I85X(dev))
e70236a8
JB		 7709 dev_priv->display.get_display_clock_speed =
7710 i855_get_display_clock_speed;
7711 else /* 852, 830 */
7712 dev_priv->display.get_display_clock_speed =
7713 i830_get_display_clock_speed;
7714
7715 /* For FIFO watermark updates */
7f8a8569 7716 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7717 if (HAS_PCH_IBX(dev))
7718 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7719 else if (HAS_PCH_CPT(dev))
7720 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7721
f00a3ddf 7722 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7723 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7724 dev_priv->display.update_wm = ironlake_update_wm;
7725 else {
7726 DRM_DEBUG_KMS("Failed to get proper latency. "
7727 "Disable CxSR\n");
7728 dev_priv->display.update_wm = NULL;
1398261a 7729 }
674cf967 7730 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7731 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7732 } else if (IS_GEN6(dev)) {
7733 if (SNB_READ_WM0_LATENCY()) {
7734 dev_priv->display.update_wm = sandybridge_update_wm;
7735 } else {
7736 DRM_DEBUG_KMS("Failed to read display plane latency. "
7737 "Disable CxSR\n");
7738 dev_priv->display.update_wm = NULL;
7f8a8569 7739 }
674cf967 7740 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7741 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7742 } else if (IS_IVYBRIDGE(dev)) {
7743 /* FIXME: detect B0+ stepping and use auto training */
7744 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7745 if (SNB_READ_WM0_LATENCY()) {
7746 dev_priv->display.update_wm = sandybridge_update_wm;
7747 } else {
7748 DRM_DEBUG_KMS("Failed to read display plane latency. "
7749 "Disable CxSR\n");
7750 dev_priv->display.update_wm = NULL;
7751 }
28963a3e 7752 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7753
7f8a8569
ZW		 7754 } else
7755 dev_priv->display.update_wm = NULL;
7756 } else if (IS_PINEVIEW(dev)) {
d4294342 7757 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7758 dev_priv->is_ddr3,
d4294342
ZY		 7759 dev_priv->fsb_freq,
7760 dev_priv->mem_freq)) {
7761 DRM_INFO("failed to find known CxSR latency "
95534263 7762 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7763 "disabling CxSR\n",
95534263 7764 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7765 dev_priv->fsb_freq, dev_priv->mem_freq);
7766 /* Disable CxSR and never update its watermark again */
7767 pineview_disable_cxsr(dev);
7768 dev_priv->display.update_wm = NULL;
7769 } else
7770 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7771 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7772 } else if (IS_G4X(dev)) {
e70236a8 7773 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7774 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7775 } else if (IS_GEN4(dev)) {
e70236a8 7776 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7777 if (IS_CRESTLINE(dev))
7778 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7779 else if (IS_BROADWATER(dev))
7780 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7781 } else if (IS_GEN3(dev)) {
e70236a8
JB		 7782 dev_priv->display.update_wm = i9xx_update_wm;
7783 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 7784 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7785 } else if (IS_I865G(dev)) {
7786 dev_priv->display.update_wm = i830_update_wm;
7787 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7788 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 7789 } else if (IS_I85X(dev)) {
7790 dev_priv->display.update_wm = i9xx_update_wm;
7791 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 7792 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 7793 } else {
8f4695ed 7794 dev_priv->display.update_wm = i830_update_wm;
6067aaea 7795 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 7796 if (IS_845G(dev))
e70236a8
JB		 7797 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7798 else
7799 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 7800 }
8c9f3aaf
JB		 7801
7802 /* Default just returns -ENODEV to indicate unsupported */
7803 dev_priv->display.queue_flip = intel_default_queue_flip;
7804
7805 switch (INTEL_INFO(dev)->gen) {
7806 case 2:
7807 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7808 break;
7809
7810 case 3:
7811 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7812 break;
7813
7814 case 4:
7815 case 5:
7816 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7817 break;
7818
7819 case 6:
7820 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7821 break;
7c9017e5
JB		 7822 case 7:
7823 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7824 break;
8c9f3aaf 7825 }
e70236a8
JB		 7826}
7827
b690e96c
JB		 7828/*
7829 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7830 * resume, or other times. This quirk makes sure that's the case for
7831 * affected systems.
7832 */
7833static void quirk_pipea_force (struct drm_device *dev)
7834{
7835 struct drm_i915_private *dev_priv = dev->dev_private;
7836
7837 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7838 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7839}
7840
435793df
KP		 7841/*
7842 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7843 */
7844static void quirk_ssc_force_disable(struct drm_device *dev)
7845{
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7848}
7849
b690e96c
JB		 7850struct intel_quirk {
7851 int device;
7852 int subsystem_vendor;
7853 int subsystem_device;
7854 void (*hook)(struct drm_device *dev);
7855};
7856
7857struct intel_quirk intel_quirks[] = {
7858 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7859 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7860 /* HP Mini needs pipe A force quirk (LP: #322104) */
7861 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7862
7863 /* Thinkpad R31 needs pipe A force quirk */
7864 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7865 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7866 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7867
7868 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7869 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7870 /* ThinkPad X40 needs pipe A force quirk */
7871
7872 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7873 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7874
7875 /* 855 & before need to leave pipe A & dpll A up */
7876 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7877 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7878
7879 /* Lenovo U160 cannot use SSC on LVDS */
7880 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
b690e96c
JB		 7881};
7882
7883static void intel_init_quirks(struct drm_device *dev)
7884{
7885 struct pci_dev *d = dev->pdev;
7886 int i;
7887
7888 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7889 struct intel_quirk *q = &intel_quirks[i];
7890
7891 if (d->device == q->device &&
7892 (d->subsystem_vendor == q->subsystem_vendor ||
7893 q->subsystem_vendor == PCI_ANY_ID) &&
7894 (d->subsystem_device == q->subsystem_device ||
7895 q->subsystem_device == PCI_ANY_ID))
7896 q->hook(dev);
7897 }
7898}
7899
9cce37f4
JB		 7900/* Disable the VGA plane that we never use */
7901static void i915_disable_vga(struct drm_device *dev)
7902{
7903 struct drm_i915_private *dev_priv = dev->dev_private;
7904 u8 sr1;
7905 u32 vga_reg;
7906
7907 if (HAS_PCH_SPLIT(dev))
7908 vga_reg = CPU_VGACNTRL;
7909 else
7910 vga_reg = VGACNTRL;
7911
7912 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7913 outb(1, VGA_SR_INDEX);
7914 sr1 = inb(VGA_SR_DATA);
7915 outb(sr1 | 1<<5, VGA_SR_DATA);
7916 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7917 udelay(300);
7918
7919 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7920 POSTING_READ(vga_reg);
7921}
7922
79e53945
JB		 7923void intel_modeset_init(struct drm_device *dev)
7924{
652c393a 7925 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7926 int i;
7927
7928 drm_mode_config_init(dev);
7929
7930 dev->mode_config.min_width = 0;
7931 dev->mode_config.min_height = 0;
7932
7933 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7934
b690e96c
JB		 7935 intel_init_quirks(dev);
7936
e70236a8
JB		 7937 intel_init_display(dev);
7938
a6c45cf0
CW		 7939 if (IS_GEN2(dev)) {
7940 dev->mode_config.max_width = 2048;
7941 dev->mode_config.max_height = 2048;
7942 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7943 dev->mode_config.max_width = 4096;
7944 dev->mode_config.max_height = 4096;
79e53945 7945 } else {
a6c45cf0
CW		 7946 dev->mode_config.max_width = 8192;
7947 dev->mode_config.max_height = 8192;
79e53945 7948 }
35c3047a 7949 dev->mode_config.fb_base = dev->agp->base;
79e53945 7950
28c97730 7951 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7952 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7953
a3524f1b 7954 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7955 intel_crtc_init(dev, i);
7956 }
7957
9cce37f4
JB		 7958 /* Just disable it once at startup */
7959 i915_disable_vga(dev);
79e53945 7960 intel_setup_outputs(dev);
652c393a 7961
645c62a5 7962 intel_init_clock_gating(dev);
9cce37f4 7963
7648fa99 7964 if (IS_IRONLAKE_M(dev)) {
f97108d1 7965 ironlake_enable_drps(dev);
7648fa99
JB		 7966 intel_init_emon(dev);
7967 }
f97108d1 7968
3b8d8d91
JB		 7969 if (IS_GEN6(dev))
7970 gen6_enable_rps(dev_priv);
7971
652c393a
JB		 7972 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7973 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7974 (unsigned long)dev);
2c7111db
CW		 7975}
7976
7977void intel_modeset_gem_init(struct drm_device *dev)
7978{
7979 if (IS_IRONLAKE_M(dev))
7980 ironlake_enable_rc6(dev);
02e792fb
DV		 7981
7982 intel_setup_overlay(dev);
79e53945
JB		 7983}
7984
7985void intel_modeset_cleanup(struct drm_device *dev)
7986{
652c393a
JB		 7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 struct drm_crtc *crtc;
7989 struct intel_crtc *intel_crtc;
7990
f87ea761 7991 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7992 mutex_lock(&dev->struct_mutex);
7993
723bfd70
JB		 7994 intel_unregister_dsm_handler();
7995
7996
652c393a
JB		 7997 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7998 /* Skip inactive CRTCs */
7999 if (!crtc->fb)
8000 continue;
8001
8002 intel_crtc = to_intel_crtc(crtc);
3dec0095 8003 intel_increase_pllclock(crtc);
652c393a
JB		 8004 }
8005
e70236a8
JB		 8006 if (dev_priv->display.disable_fbc)
8007 dev_priv->display.disable_fbc(dev);
8008
f97108d1
JB		 8009 if (IS_IRONLAKE_M(dev))
8010 ironlake_disable_drps(dev);
3b8d8d91
JB		 8011 if (IS_GEN6(dev))
8012 gen6_disable_rps(dev);
f97108d1 8013
d5bb081b
JB		 8014 if (IS_IRONLAKE_M(dev))
8015 ironlake_disable_rc6(dev);
0cdab21f 8016
69341a5e
KH		 8017 mutex_unlock(&dev->struct_mutex);
8018
6c0d9350
DV		 8019 /* Disable the irq before mode object teardown, for the irq might
8020 * enqueue unpin/hotplug work. */
8021 drm_irq_uninstall(dev);
8022 cancel_work_sync(&dev_priv->hotplug_work);
8023
3dec0095
DV		 8024 /* Shut off idle work before the crtcs get freed. */
8025 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8026 intel_crtc = to_intel_crtc(crtc);
8027 del_timer_sync(&intel_crtc->idle_timer);
8028 }
8029 del_timer_sync(&dev_priv->idle_timer);
8030 cancel_work_sync(&dev_priv->idle_work);
8031
79e53945
JB		 8032 drm_mode_config_cleanup(dev);
8033}
8034
f1c79df3
ZW		 8035/*
8036 * Return which encoder is currently attached for connector.
8037 */
df0e9248 8038struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8039{
df0e9248
CW		 8040 return &intel_attached_encoder(connector)->base;
8041}
f1c79df3 8042
df0e9248
CW		 8043void intel_connector_attach_encoder(struct intel_connector *connector,
8044 struct intel_encoder *encoder)
8045{
8046 connector->encoder = encoder;
8047 drm_mode_connector_attach_encoder(&connector->base,
8048 &encoder->base);
79e53945 8049}
28d52043
DA		 8050
8051/*
8052 * set vga decode state - true == enable VGA decode
8053 */
8054int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8055{
8056 struct drm_i915_private *dev_priv = dev->dev_private;
8057 u16 gmch_ctrl;
8058
8059 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8060 if (state)
8061 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8062 else
8063 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8064 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8065 return 0;
8066}
c4a1d9e4
CW		 8067
8068#ifdef CONFIG_DEBUG_FS
8069#include <linux/seq_file.h>
8070
8071struct intel_display_error_state {
8072 struct intel_cursor_error_state {
8073 u32 control;
8074 u32 position;
8075 u32 base;
8076 u32 size;
8077 } cursor[2];
8078
8079 struct intel_pipe_error_state {
8080 u32 conf;
8081 u32 source;
8082
8083 u32 htotal;
8084 u32 hblank;
8085 u32 hsync;
8086 u32 vtotal;
8087 u32 vblank;
8088 u32 vsync;
8089 } pipe[2];
8090
8091 struct intel_plane_error_state {
8092 u32 control;
8093 u32 stride;
8094 u32 size;
8095 u32 pos;
8096 u32 addr;
8097 u32 surface;
8098 u32 tile_offset;
8099 } plane[2];
8100};
8101
8102struct intel_display_error_state *
8103intel_display_capture_error_state(struct drm_device *dev)
8104{
8105 drm_i915_private_t *dev_priv = dev->dev_private;
8106 struct intel_display_error_state *error;
8107 int i;
8108
8109 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8110 if (error == NULL)
8111 return NULL;
8112
8113 for (i = 0; i < 2; i++) {
8114 error->cursor[i].control = I915_READ(CURCNTR(i));
8115 error->cursor[i].position = I915_READ(CURPOS(i));
8116 error->cursor[i].base = I915_READ(CURBASE(i));
8117
8118 error->plane[i].control = I915_READ(DSPCNTR(i));
8119 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8120 error->plane[i].size = I915_READ(DSPSIZE(i));
8121 error->plane[i].pos= I915_READ(DSPPOS(i));
8122 error->plane[i].addr = I915_READ(DSPADDR(i));
8123 if (INTEL_INFO(dev)->gen >= 4) {
8124 error->plane[i].surface = I915_READ(DSPSURF(i));
8125 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8126 }
8127
8128 error->pipe[i].conf = I915_READ(PIPECONF(i));
8129 error->pipe[i].source = I915_READ(PIPESRC(i));
8130 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8131 error->pipe[i].hblank = I915_READ(HBLANK(i));
8132 error->pipe[i].hsync = I915_READ(HSYNC(i));
8133 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8134 error->pipe[i].vblank = I915_READ(VBLANK(i));
8135 error->pipe[i].vsync = I915_READ(VSYNC(i));
8136 }
8137
8138 return error;
8139}
8140
8141void
8142intel_display_print_error_state(struct seq_file *m,
8143 struct drm_device *dev,
8144 struct intel_display_error_state *error)
8145{
8146 int i;
8147
8148 for (i = 0; i < 2; i++) {
8149 seq_printf(m, "Pipe [%d]:\n", i);
8150 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8151 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8152 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8153 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8154 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8155 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8156 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8157 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8158
8159 seq_printf(m, "Plane [%d]:\n", i);
8160 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8161 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8162 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8163 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8164 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8165 if (INTEL_INFO(dev)->gen >= 4) {
8166 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8167 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8168 }
8169
8170 seq_printf(m, "Cursor [%d]:\n", i);
8171 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8172 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8173 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8174 }
8175}
8176#endif
Linux kernel - Deliverables
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