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drm/i915: Flush other plane register writes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB		 27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
JB		 33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
JB		 39
40#include "drm_crtc_helper.h"
41
32f9d658
ZW		 42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
ML		 71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
79e53945
JB		 73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
d4906093
ML		 75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
79e53945 78
2377b741
JB		 79/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
d4906093
ML		 82static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
79e53945 88
a4fc5ed6
KP		 89static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 92static bool
f2b115e6
AJ		 93intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 95
021357ac
CW		 96static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
8b99e68c
CW		 99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
021357ac
CW		 104}
105
e4b36699 106static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
d4906093 117 .find_pll = intel_find_best_PLL,
e4b36699
KP		 118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
d4906093 131 .find_pll = intel_find_best_PLL,
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
d4906093 145 .find_pll = intel_find_best_PLL,
e4b36699
KP		 146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
d4906093 159 .find_pll = intel_find_best_PLL,
e4b36699
KP		 160};
161
273e27ca 162
e4b36699 163static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
044c7c41 175 },
d4906093 176 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
d4906093 190 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
044c7c41 204 },
d4906093 205 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
044c7c41 219 },
d4906093 220 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 234 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 235};
236
f2b115e6 237static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
6115707b 250 .find_pll = intel_find_best_PLL,
e4b36699
KP		 251};
252
f2b115e6 253static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
6115707b 264 .find_pll = intel_find_best_PLL,
e4b36699
KP		 265};
266
273e27ca
EA		 267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
b91ad0ec 272static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
4547668a 283 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 284};
285
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 311 .find_pll = intel_g4x_find_best_PLL,
312};
313
273e27ca 314/* LVDS 100mhz refclk limits. */
b91ad0ec 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
4547668a 354 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 355};
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec
ZW		 360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 362 const intel_limit_t *limit;
b91ad0ec
ZW		 363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
1b894b59 373 if (refclk == 100000)
b91ad0ec
ZW		 374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
2c07245f 381 else
b91ad0ec 382 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 383
384 return limit;
385}
386
044c7c41
ML		 387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
e4b36699 397 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 398 else
399 /* LVDS with dual channel */
e4b36699 400 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 403 limit = &intel_limits_g4x_hdmi;
044c7c41 404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 405 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 407 limit = &intel_limits_g4x_display_port;
044c7c41 408 } else /* The option is for other outputs */
e4b36699 409 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 410
411 return limit;
412}
413
1b894b59 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
bad720ff 419 if (HAS_PCH_SPLIT(dev))
1b894b59 420 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 421 else if (IS_G4X(dev)) {
044c7c41 422 limit = intel_g4x_limit(crtc);
f2b115e6 423 } else if (IS_PINEVIEW(dev)) {
2177832f 424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 425 limit = &intel_limits_pineview_lvds;
2177832f 426 else
f2b115e6 427 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 435 limit = &intel_limits_i8xx_lvds;
79e53945 436 else
e4b36699 437 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 438 }
439 return limit;
440}
441
f2b115e6
AJ		 442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 444{
2177832f
SL		 445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
f2b115e6
AJ		 453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
2177832f
SL		 455 return;
456 }
79e53945
JB		 457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
79e53945
JB		 463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
4ef69c7a 466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 467{
4ef69c7a
CW		 468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
79e53945
JB		 477}
478
7c04d1d9 479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
1b894b59
CW		 485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
79e53945 488{
79e53945
JB		 489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
f2b115e6 497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
d4906093
ML		 514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
79e53945
JB		 518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
79e53945
JB		 522 int err = target;
523
bc5e5718 524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 525 (I915_READ(LVDS)) != 0) {
79e53945
JB		 526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
42158660
ZY		 546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 557 int this_err;
558
2177832f 559 intel_clock(dev, refclk, &clock);
1b894b59
CW		 560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
79e53945
JB		 562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
d4906093
ML		 577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
6ba770dc
AJ		 586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 591 int lvds_reg;
592
c619eed4 593 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
f77f13e2 611 /* based on hardware requirement, prefer smaller n to precision */
d4906093 612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 613 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
2177832f 622 intel_clock(dev, refclk, &clock);
1b894b59
CW		 623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
d4906093 625 continue;
1b894b59
CW		 626
627 this_err = abs(clock.dot - target);
d4906093
ML		 628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
2c07245f
ZW		 638 return found;
639}
640
5eb08b69 641static bool
f2b115e6
AJ		 642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
4547668a 647
5eb08b69
ZW		 648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
a4fc5ed6
KP		 666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
5eddb70b
CW		 671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
a4fc5ed6
KP		 691}
692
9d0498a2
JB		 693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 702{
9d0498a2 703 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 704 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 705
300387c0
CW		 706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
9d0498a2 722 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
9d0498a2
JB		 726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
ab7ad7f6
KP		 729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
ab7ad7f6
KP		 738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
58e10eb9 744 *
9d0498a2 745 */
58e10eb9 746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 749
750 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 751 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 752
753 /* Wait for the Pipe State to go off */
58e10eb9
CW		 754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
ab7ad7f6
KP		 756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
58e10eb9 759 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
58e10eb9 764 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 765 mdelay(5);
58e10eb9 766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
79e53945
JB		 771}
772
b24e7179
JB		 773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
040484af
JB		 796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
ea0760cf
JB		 874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 900 pipe_name(pipe));
ea0760cf
JB		 901}
902
63d7bbe9
JB		 903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
b24e7179
JB		 905{
906 int reg;
907 u32 val;
63d7bbe9 908 bool cur_state;
b24e7179
JB		 909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
63d7bbe9
JB		 912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 915 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 916}
63d7bbe9
JB		 917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 930 plane_name(plane));
b24e7179
JB		 931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
19ec1358
JB		 940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
b24e7179
JB		 944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
b24e7179
JB		 953 }
954}
955
92f2584a
JB		 956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
92f2584a
JB		 980}
981
f0575e92
KP		 982static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
983 int reg, u32 port_sel, u32 val)
984{
985 if ((val & DP_PORT_EN) == 0)
986 return false;
987
988 if (HAS_PCH_CPT(dev_priv->dev)) {
989 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
990 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
991 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
992 return false;
993 } else {
994 if ((val & DP_PIPE_MASK) != (pipe << 30))
995 return false;
996 }
997 return true;
998}
999
291906f1 1000static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1001 enum pipe pipe, int reg, u32 port_sel)
291906f1 1002{
47a05eca 1003 u32 val = I915_READ(reg);
f0575e92 1004 WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
291906f1 1005 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1006 reg, pipe_name(pipe));
291906f1
JB		 1007}
1008
1009static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, int reg)
1011{
47a05eca
JB		 1012 u32 val = I915_READ(reg);
1013 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 reg, pipe_name(pipe));
291906f1
JB		 1016}
1017
1018static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe)
1020{
1021 int reg;
1022 u32 val;
291906f1 1023
f0575e92
KP		 1024 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1025 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1026 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1027
1028 reg = PCH_ADPA;
1029 val = I915_READ(reg);
47a05eca 1030 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1031 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1032 pipe_name(pipe));
291906f1
JB		 1033
1034 reg = PCH_LVDS;
1035 val = I915_READ(reg);
47a05eca 1036 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1037 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1038 pipe_name(pipe));
291906f1
JB		 1039
1040 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1041 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1042 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1043}
1044
63d7bbe9
JB		 1045/**
1046 * intel_enable_pll - enable a PLL
1047 * @dev_priv: i915 private structure
1048 * @pipe: pipe PLL to enable
1049 *
1050 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1051 * make sure the PLL reg is writable first though, since the panel write
1052 * protect mechanism may be enabled.
1053 *
1054 * Note! This is for pre-ILK only.
1055 */
1056static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1057{
1058 int reg;
1059 u32 val;
1060
1061 /* No really, not for ILK+ */
1062 BUG_ON(dev_priv->info->gen >= 5);
1063
1064 /* PLL is protected by panel, make sure we can write it */
1065 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1066 assert_panel_unlocked(dev_priv, pipe);
1067
1068 reg = DPLL(pipe);
1069 val = I915_READ(reg);
1070 val |= DPLL_VCO_ENABLE;
1071
1072 /* We do this three times for luck */
1073 I915_WRITE(reg, val);
1074 POSTING_READ(reg);
1075 udelay(150); /* wait for warmup */
1076 I915_WRITE(reg, val);
1077 POSTING_READ(reg);
1078 udelay(150); /* wait for warmup */
1079 I915_WRITE(reg, val);
1080 POSTING_READ(reg);
1081 udelay(150); /* wait for warmup */
1082}
1083
1084/**
1085 * intel_disable_pll - disable a PLL
1086 * @dev_priv: i915 private structure
1087 * @pipe: pipe PLL to disable
1088 *
1089 * Disable the PLL for @pipe, making sure the pipe is off first.
1090 *
1091 * Note! This is for pre-ILK only.
1092 */
1093static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1094{
1095 int reg;
1096 u32 val;
1097
1098 /* Don't disable pipe A or pipe A PLLs if needed */
1099 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1100 return;
1101
1102 /* Make sure the pipe isn't still relying on us */
1103 assert_pipe_disabled(dev_priv, pipe);
1104
1105 reg = DPLL(pipe);
1106 val = I915_READ(reg);
1107 val &= ~DPLL_VCO_ENABLE;
1108 I915_WRITE(reg, val);
1109 POSTING_READ(reg);
1110}
1111
92f2584a
JB		 1112/**
1113 * intel_enable_pch_pll - enable PCH PLL
1114 * @dev_priv: i915 private structure
1115 * @pipe: pipe PLL to enable
1116 *
1117 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1118 * drives the transcoder clock.
1119 */
1120static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe)
1122{
1123 int reg;
1124 u32 val;
1125
1126 /* PCH only available on ILK+ */
1127 BUG_ON(dev_priv->info->gen < 5);
1128
1129 /* PCH refclock must be enabled first */
1130 assert_pch_refclk_enabled(dev_priv);
1131
1132 reg = PCH_DPLL(pipe);
1133 val = I915_READ(reg);
1134 val |= DPLL_VCO_ENABLE;
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(200);
1138}
1139
1140static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* PCH only available on ILK+ */
1147 BUG_ON(dev_priv->info->gen < 5);
1148
1149 /* Make sure transcoder isn't still depending on us */
1150 assert_transcoder_disabled(dev_priv, pipe);
1151
1152 reg = PCH_DPLL(pipe);
1153 val = I915_READ(reg);
1154 val &= ~DPLL_VCO_ENABLE;
1155 I915_WRITE(reg, val);
1156 POSTING_READ(reg);
1157 udelay(200);
1158}
1159
040484af
JB		 1160static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162{
1163 int reg;
1164 u32 val;
1165
1166 /* PCH only available on ILK+ */
1167 BUG_ON(dev_priv->info->gen < 5);
1168
1169 /* Make sure PCH DPLL is enabled */
1170 assert_pch_pll_enabled(dev_priv, pipe);
1171
1172 /* FDI must be feeding us bits for PCH ports */
1173 assert_fdi_tx_enabled(dev_priv, pipe);
1174 assert_fdi_rx_enabled(dev_priv, pipe);
1175
1176 reg = TRANSCONF(pipe);
1177 val = I915_READ(reg);
1178 /*
1179 * make the BPC in transcoder be consistent with
1180 * that in pipeconf reg.
1181 */
1182 val &= ~PIPE_BPC_MASK;
1183 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1184 I915_WRITE(reg, val | TRANS_ENABLE);
1185 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1186 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1187}
1188
1189static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191{
1192 int reg;
1193 u32 val;
1194
1195 /* FDI relies on the transcoder */
1196 assert_fdi_tx_disabled(dev_priv, pipe);
1197 assert_fdi_rx_disabled(dev_priv, pipe);
1198
291906f1
JB		 1199 /* Ports must be off as well */
1200 assert_pch_ports_disabled(dev_priv, pipe);
1201
040484af
JB		 1202 reg = TRANSCONF(pipe);
1203 val = I915_READ(reg);
1204 val &= ~TRANS_ENABLE;
1205 I915_WRITE(reg, val);
1206 /* wait for PCH transcoder off, transcoder state */
1207 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1208 DRM_ERROR("failed to disable transcoder\n");
1209}
1210
b24e7179 1211/**
309cfea8 1212 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1213 * @dev_priv: i915 private structure
1214 * @pipe: pipe to enable
040484af 1215 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1216 *
1217 * Enable @pipe, making sure that various hardware specific requirements
1218 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1219 *
1220 * @pipe should be %PIPE_A or %PIPE_B.
1221 *
1222 * Will wait until the pipe is actually running (i.e. first vblank) before
1223 * returning.
1224 */
040484af
JB		 1225static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1226 bool pch_port)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
1230
1231 /*
1232 * A pipe without a PLL won't actually be able to drive bits from
1233 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1234 * need the check.
1235 */
1236 if (!HAS_PCH_SPLIT(dev_priv->dev))
1237 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1238 else {
1239 if (pch_port) {
1240 /* if driving the PCH, we need FDI enabled */
1241 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1242 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1243 }
1244 /* FIXME: assert CPU port conditions for SNB+ */
1245 }
b24e7179
JB		 1246
1247 reg = PIPECONF(pipe);
1248 val = I915_READ(reg);
00d70b15
CW		 1249 if (val & PIPECONF_ENABLE)
1250 return;
1251
1252 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1253 intel_wait_for_vblank(dev_priv->dev, pipe);
1254}
1255
1256/**
309cfea8 1257 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1258 * @dev_priv: i915 private structure
1259 * @pipe: pipe to disable
1260 *
1261 * Disable @pipe, making sure that various hardware specific requirements
1262 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1263 *
1264 * @pipe should be %PIPE_A or %PIPE_B.
1265 *
1266 * Will wait until the pipe has shut down before returning.
1267 */
1268static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1269 enum pipe pipe)
1270{
1271 int reg;
1272 u32 val;
1273
1274 /*
1275 * Make sure planes won't keep trying to pump pixels to us,
1276 * or we might hang the display.
1277 */
1278 assert_planes_disabled(dev_priv, pipe);
1279
1280 /* Don't disable pipe A or pipe A PLLs if needed */
1281 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1282 return;
1283
1284 reg = PIPECONF(pipe);
1285 val = I915_READ(reg);
00d70b15
CW		 1286 if ((val & PIPECONF_ENABLE) == 0)
1287 return;
1288
1289 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1290 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1291}
1292
d74362c9
KP		 1293/*
1294 * Plane regs are double buffered, going from enabled->disabled needs a
1295 * trigger in order to latch. The display address reg provides this.
1296 */
1297static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1298 enum plane plane)
1299{
1300 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1301 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1302}
1303
b24e7179
JB		 1304/**
1305 * intel_enable_plane - enable a display plane on a given pipe
1306 * @dev_priv: i915 private structure
1307 * @plane: plane to enable
1308 * @pipe: pipe being fed
1309 *
1310 * Enable @plane on @pipe, making sure that @pipe is running first.
1311 */
1312static void intel_enable_plane(struct drm_i915_private *dev_priv,
1313 enum plane plane, enum pipe pipe)
1314{
1315 int reg;
1316 u32 val;
1317
1318 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1319 assert_pipe_enabled(dev_priv, pipe);
1320
1321 reg = DSPCNTR(plane);
1322 val = I915_READ(reg);
00d70b15
CW		 1323 if (val & DISPLAY_PLANE_ENABLE)
1324 return;
1325
1326 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1327 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1328 intel_wait_for_vblank(dev_priv->dev, pipe);
1329}
1330
b24e7179
JB		 1331/**
1332 * intel_disable_plane - disable a display plane
1333 * @dev_priv: i915 private structure
1334 * @plane: plane to disable
1335 * @pipe: pipe consuming the data
1336 *
1337 * Disable @plane; should be an independent operation.
1338 */
1339static void intel_disable_plane(struct drm_i915_private *dev_priv,
1340 enum plane plane, enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 reg = DSPCNTR(plane);
1346 val = I915_READ(reg);
00d70b15
CW		 1347 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1348 return;
1349
1350 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1351 intel_flush_display_plane(dev_priv, plane);
1352 intel_wait_for_vblank(dev_priv->dev, pipe);
1353}
1354
47a05eca 1355static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1356 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1357{
1358 u32 val = I915_READ(reg);
f0575e92
KP		 1359 if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1360 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1361 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1362 }
47a05eca
JB		 1363}
1364
1365static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, int reg)
1367{
1368 u32 val = I915_READ(reg);
f0575e92
KP		 1369 if (HDMI_PIPE_ENABLED(val, pipe)) {
1370 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1371 reg, pipe);
47a05eca 1372 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1373 }
47a05eca
JB		 1374}
1375
1376/* Disable any ports connected to this transcoder */
1377static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1378 enum pipe pipe)
1379{
1380 u32 reg, val;
1381
1382 val = I915_READ(PCH_PP_CONTROL);
1383 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1384
f0575e92
KP		 1385 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1386 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1387 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1388
1389 reg = PCH_ADPA;
1390 val = I915_READ(reg);
1391 if (ADPA_PIPE_ENABLED(val, pipe))
1392 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1393
1394 reg = PCH_LVDS;
1395 val = I915_READ(reg);
1396 if (LVDS_PIPE_ENABLED(val, pipe)) {
1397 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1398 POSTING_READ(reg);
1399 udelay(100);
1400 }
1401
1402 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1403 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1404 disable_pch_hdmi(dev_priv, pipe, HDMID);
1405}
1406
80824003
JB		 1407static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1408{
1409 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 struct drm_framebuffer *fb = crtc->fb;
1412 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1413 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1415 int plane, i;
1416 u32 fbc_ctl, fbc_ctl2;
1417
bed4a673 1418 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1419 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1420 intel_crtc->plane == dev_priv->cfb_plane &&
1421 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1422 return;
1423
1424 i8xx_disable_fbc(dev);
1425
80824003
JB		 1426 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1427
1428 if (fb->pitch < dev_priv->cfb_pitch)
1429 dev_priv->cfb_pitch = fb->pitch;
1430
1431 /* FBC_CTL wants 64B units */
1432 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1433 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1434 dev_priv->cfb_plane = intel_crtc->plane;
1435 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1436
1437 /* Clear old tags */
1438 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1439 I915_WRITE(FBC_TAG + (i * 4), 0);
1440
1441 /* Set it up... */
1442 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1443 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1444 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1445 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1446 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1447
1448 /* enable it... */
1449 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1450 if (IS_I945GM(dev))
49677901 1451 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1452 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1453 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1454 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1455 fbc_ctl |= dev_priv->cfb_fence;
1456 I915_WRITE(FBC_CONTROL, fbc_ctl);
1457
28c97730 1458 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1459 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1460}
1461
1462void i8xx_disable_fbc(struct drm_device *dev)
1463{
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 u32 fbc_ctl;
1466
1467 /* Disable compression */
1468 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1469 if ((fbc_ctl & FBC_CTL_EN) == 0)
1470 return;
1471
80824003
JB		 1472 fbc_ctl &= ~FBC_CTL_EN;
1473 I915_WRITE(FBC_CONTROL, fbc_ctl);
1474
1475 /* Wait for compressing bit to clear */
481b6af3 1476 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1477 DRM_DEBUG_KMS("FBC idle timed out\n");
1478 return;
9517a92f 1479 }
80824003 1480
28c97730 1481 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1482}
1483
ee5382ae 1484static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1485{
80824003
JB		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487
1488 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1489}
1490
74dff282
JB		 1491static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1492{
1493 struct drm_device *dev = crtc->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 struct drm_framebuffer *fb = crtc->fb;
1496 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1497 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1499 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1500 unsigned long stall_watermark = 200;
1501 u32 dpfc_ctl;
1502
bed4a673
CW		 1503 dpfc_ctl = I915_READ(DPFC_CONTROL);
1504 if (dpfc_ctl & DPFC_CTL_EN) {
1505 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1506 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1507 dev_priv->cfb_plane == intel_crtc->plane &&
1508 dev_priv->cfb_y == crtc->y)
1509 return;
1510
1511 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1512 intel_wait_for_vblank(dev, intel_crtc->pipe);
1513 }
1514
74dff282 1515 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1516 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1517 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1518 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1519
1520 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1521 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1522 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1523 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1524 } else {
1525 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1526 }
1527
74dff282
JB		 1528 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1529 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1530 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1531 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1532
1533 /* enable it... */
1534 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1535
28c97730 1536 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1537}
1538
1539void g4x_disable_fbc(struct drm_device *dev)
1540{
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 u32 dpfc_ctl;
1543
1544 /* Disable compression */
1545 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1546 if (dpfc_ctl & DPFC_CTL_EN) {
1547 dpfc_ctl &= ~DPFC_CTL_EN;
1548 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1549
bed4a673
CW		 1550 DRM_DEBUG_KMS("disabled FBC\n");
1551 }
74dff282
JB		 1552}
1553
ee5382ae 1554static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1555{
74dff282
JB		 1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557
1558 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1559}
1560
4efe0708
JB		 1561static void sandybridge_blit_fbc_update(struct drm_device *dev)
1562{
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 u32 blt_ecoskpd;
1565
1566 /* Make sure blitter notifies FBC of writes */
fcca7926 1567 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1568 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1569 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1570 GEN6_BLITTER_LOCK_SHIFT;
1571 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1572 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1573 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1574 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1575 GEN6_BLITTER_LOCK_SHIFT);
1576 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1577 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1578 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1579}
1580
b52eb4dc
ZY		 1581static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1582{
1583 struct drm_device *dev = crtc->dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 struct drm_framebuffer *fb = crtc->fb;
1586 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1587 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1589 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1590 unsigned long stall_watermark = 200;
1591 u32 dpfc_ctl;
1592
bed4a673
CW		 1593 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1594 if (dpfc_ctl & DPFC_CTL_EN) {
1595 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1596 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1597 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1598 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1599 dev_priv->cfb_y == crtc->y)
1600 return;
1601
1602 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1603 intel_wait_for_vblank(dev, intel_crtc->pipe);
1604 }
1605
b52eb4dc 1606 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1607 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1608 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1609 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1610 dev_priv->cfb_y = crtc->y;
b52eb4dc 1611
b52eb4dc
ZY		 1612 dpfc_ctl &= DPFC_RESERVED;
1613 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1614 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1615 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1616 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1617 } else {
1618 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1619 }
1620
b52eb4dc
ZY		 1621 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1622 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1623 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1624 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1625 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1626 /* enable it... */
bed4a673 1627 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1628
9c04f015
YL		 1629 if (IS_GEN6(dev)) {
1630 I915_WRITE(SNB_DPFC_CTL_SA,
1631 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1632 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1633 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1634 }
1635
b52eb4dc
ZY		 1636 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1637}
1638
1639void ironlake_disable_fbc(struct drm_device *dev)
1640{
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 dpfc_ctl;
1643
1644 /* Disable compression */
1645 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1646 if (dpfc_ctl & DPFC_CTL_EN) {
1647 dpfc_ctl &= ~DPFC_CTL_EN;
1648 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1649
bed4a673
CW		 1650 DRM_DEBUG_KMS("disabled FBC\n");
1651 }
b52eb4dc
ZY		 1652}
1653
1654static bool ironlake_fbc_enabled(struct drm_device *dev)
1655{
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1659}
1660
ee5382ae
AJ		 1661bool intel_fbc_enabled(struct drm_device *dev)
1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.fbc_enabled)
1666 return false;
1667
1668 return dev_priv->display.fbc_enabled(dev);
1669}
1670
1671void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1672{
1673 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1674
1675 if (!dev_priv->display.enable_fbc)
1676 return;
1677
1678 dev_priv->display.enable_fbc(crtc, interval);
1679}
1680
1681void intel_disable_fbc(struct drm_device *dev)
1682{
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685 if (!dev_priv->display.disable_fbc)
1686 return;
1687
1688 dev_priv->display.disable_fbc(dev);
1689}
1690
80824003
JB		 1691/**
1692 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1693 * @dev: the drm_device
80824003
JB		 1694 *
1695 * Set up the framebuffer compression hardware at mode set time. We
1696 * enable it if possible:
1697 * - plane A only (on pre-965)
1698 * - no pixel mulitply/line duplication
1699 * - no alpha buffer discard
1700 * - no dual wide
1701 * - framebuffer <= 2048 in width, 1536 in height
1702 *
1703 * We can't assume that any compression will take place (worst case),
1704 * so the compressed buffer has to be the same size as the uncompressed
1705 * one. It also must reside (along with the line length buffer) in
1706 * stolen memory.
1707 *
1708 * We need to enable/disable FBC on a global basis.
1709 */
bed4a673 1710static void intel_update_fbc(struct drm_device *dev)
80824003 1711{
80824003 1712 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1713 struct drm_crtc *crtc = NULL, *tmp_crtc;
1714 struct intel_crtc *intel_crtc;
1715 struct drm_framebuffer *fb;
80824003 1716 struct intel_framebuffer *intel_fb;
05394f39 1717 struct drm_i915_gem_object *obj;
9c928d16
JB		 1718
1719 DRM_DEBUG_KMS("\n");
80824003
JB		 1720
1721 if (!i915_powersave)
1722 return;
1723
ee5382ae 1724 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1725 return;
1726
80824003
JB		 1727 /*
1728 * If FBC is already on, we just have to verify that we can
1729 * keep it that way...
1730 * Need to disable if:
9c928d16 1731 * - more than one pipe is active
80824003
JB		 1732 * - changing FBC params (stride, fence, mode)
1733 * - new fb is too large to fit in compressed buffer
1734 * - going to an unsupported config (interlace, pixel multiply, etc.)
1735 */
9c928d16 1736 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1737 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1738 if (crtc) {
1739 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1740 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1741 goto out_disable;
1742 }
1743 crtc = tmp_crtc;
1744 }
9c928d16 1745 }
bed4a673
CW		 1746
1747 if (!crtc || crtc->fb == NULL) {
1748 DRM_DEBUG_KMS("no output, disabling\n");
1749 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1750 goto out_disable;
1751 }
bed4a673
CW		 1752
1753 intel_crtc = to_intel_crtc(crtc);
1754 fb = crtc->fb;
1755 intel_fb = to_intel_framebuffer(fb);
05394f39 1756 obj = intel_fb->obj;
bed4a673 1757
c1a9f047
JB		 1758 if (!i915_enable_fbc) {
1759 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1760 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1761 goto out_disable;
1762 }
05394f39 1763 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1764 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1765 "compression\n");
b5e50c3f 1766 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1767 goto out_disable;
1768 }
bed4a673
CW		 1769 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1770 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1771 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1772 "disabling\n");
b5e50c3f 1773 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1774 goto out_disable;
1775 }
bed4a673
CW		 1776 if ((crtc->mode.hdisplay > 2048) ||
1777 (crtc->mode.vdisplay > 1536)) {
28c97730 1778 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1779 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1780 goto out_disable;
1781 }
bed4a673 1782 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1783 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1784 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1785 goto out_disable;
1786 }
05394f39 1787 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1788 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1789 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1790 goto out_disable;
1791 }
1792
c924b934
JW		 1793 /* If the kernel debugger is active, always disable compression */
1794 if (in_dbg_master())
1795 goto out_disable;
1796
bed4a673 1797 intel_enable_fbc(crtc, 500);
80824003
JB		 1798 return;
1799
1800out_disable:
80824003 1801 /* Multiple disables should be harmless */
a939406f
CW		 1802 if (intel_fbc_enabled(dev)) {
1803 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1804 intel_disable_fbc(dev);
a939406f 1805 }
80824003
JB		 1806}
1807
127bd2ac 1808int
48b956c5 1809intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1810 struct drm_i915_gem_object *obj,
919926ae 1811 struct intel_ring_buffer *pipelined)
6b95a207 1812{
ce453d81 1813 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1814 u32 alignment;
1815 int ret;
1816
05394f39 1817 switch (obj->tiling_mode) {
6b95a207 1818 case I915_TILING_NONE:
534843da
CW		 1819 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1820 alignment = 128 * 1024;
a6c45cf0 1821 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1822 alignment = 4 * 1024;
1823 else
1824 alignment = 64 * 1024;
6b95a207
KH		 1825 break;
1826 case I915_TILING_X:
1827 /* pin() will align the object as required by fence */
1828 alignment = 0;
1829 break;
1830 case I915_TILING_Y:
1831 /* FIXME: Is this true? */
1832 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1833 return -EINVAL;
1834 default:
1835 BUG();
1836 }
1837
ce453d81 1838 dev_priv->mm.interruptible = false;
75e9e915 1839 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1840 if (ret)
ce453d81 1841 goto err_interruptible;
6b95a207 1842
48b956c5
CW		 1843 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1844 if (ret)
1845 goto err_unpin;
7213342d 1846
6b95a207
KH		 1847 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1848 * fence, whereas 965+ only requires a fence if using
1849 * framebuffer compression. For simplicity, we always install
1850 * a fence as the cost is not that onerous.
1851 */
05394f39 1852 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1853 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1854 if (ret)
1855 goto err_unpin;
6b95a207
KH		 1856 }
1857
ce453d81 1858 dev_priv->mm.interruptible = true;
6b95a207 1859 return 0;
48b956c5
CW		 1860
1861err_unpin:
1862 i915_gem_object_unpin(obj);
ce453d81
CW		 1863err_interruptible:
1864 dev_priv->mm.interruptible = true;
48b956c5 1865 return ret;
6b95a207
KH		 1866}
1867
81255565
JB		 1868/* Assume fb object is pinned & idle & fenced and just update base pointers */
1869static int
1870intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1871 int x, int y, enum mode_set_atomic state)
81255565
JB		 1872{
1873 struct drm_device *dev = crtc->dev;
1874 struct drm_i915_private *dev_priv = dev->dev_private;
1875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1876 struct intel_framebuffer *intel_fb;
05394f39 1877 struct drm_i915_gem_object *obj;
81255565
JB		 1878 int plane = intel_crtc->plane;
1879 unsigned long Start, Offset;
81255565 1880 u32 dspcntr;
5eddb70b 1881 u32 reg;
81255565
JB		 1882
1883 switch (plane) {
1884 case 0:
1885 case 1:
1886 break;
1887 default:
1888 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1889 return -EINVAL;
1890 }
1891
1892 intel_fb = to_intel_framebuffer(fb);
1893 obj = intel_fb->obj;
81255565 1894
5eddb70b
CW		 1895 reg = DSPCNTR(plane);
1896 dspcntr = I915_READ(reg);
81255565
JB		 1897 /* Mask out pixel format bits in case we change it */
1898 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1899 switch (fb->bits_per_pixel) {
1900 case 8:
1901 dspcntr |= DISPPLANE_8BPP;
1902 break;
1903 case 16:
1904 if (fb->depth == 15)
1905 dspcntr |= DISPPLANE_15_16BPP;
1906 else
1907 dspcntr |= DISPPLANE_16BPP;
1908 break;
1909 case 24:
1910 case 32:
1911 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1912 break;
1913 default:
1914 DRM_ERROR("Unknown color depth\n");
1915 return -EINVAL;
1916 }
a6c45cf0 1917 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1918 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1919 dspcntr |= DISPPLANE_TILED;
1920 else
1921 dspcntr &= ~DISPPLANE_TILED;
1922 }
1923
4e6cfefc 1924 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1925 /* must disable */
1926 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1927
5eddb70b 1928 I915_WRITE(reg, dspcntr);
81255565 1929
05394f39 1930 Start = obj->gtt_offset;
81255565
JB		 1931 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1932
4e6cfefc
CW		 1933 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1934 Start, Offset, x, y, fb->pitch);
5eddb70b 1935 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1936 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1937 I915_WRITE(DSPSURF(plane), Start);
1938 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1939 I915_WRITE(DSPADDR(plane), Offset);
1940 } else
1941 I915_WRITE(DSPADDR(plane), Start + Offset);
1942 POSTING_READ(reg);
81255565 1943
bed4a673 1944 intel_update_fbc(dev);
3dec0095 1945 intel_increase_pllclock(crtc);
81255565
JB		 1946
1947 return 0;
1948}
1949
5c3b82e2 1950static int
3c4fdcfb
KH		 1951intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1952 struct drm_framebuffer *old_fb)
79e53945
JB		 1953{
1954 struct drm_device *dev = crtc->dev;
79e53945
JB		 1955 struct drm_i915_master_private *master_priv;
1956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1957 int ret;
79e53945
JB		 1958
1959 /* no fb bound */
1960 if (!crtc->fb) {
28c97730 1961 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1962 return 0;
1963 }
1964
265db958 1965 switch (intel_crtc->plane) {
5c3b82e2
CW		 1966 case 0:
1967 case 1:
1968 break;
1969 default:
5c3b82e2 1970 return -EINVAL;
79e53945
JB		 1971 }
1972
5c3b82e2 1973 mutex_lock(&dev->struct_mutex);
265db958
CW		 1974 ret = intel_pin_and_fence_fb_obj(dev,
1975 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1976 NULL);
5c3b82e2
CW		 1977 if (ret != 0) {
1978 mutex_unlock(&dev->struct_mutex);
1979 return ret;
1980 }
79e53945 1981
265db958 1982 if (old_fb) {
e6c3a2a6 1983 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1984 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1985
e6c3a2a6 1986 wait_event(dev_priv->pending_flip_queue,
01eec727 1987 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1988 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1989
1990 /* Big Hammer, we also need to ensure that any pending
1991 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1992 * current scanout is retired before unpinning the old
1993 * framebuffer.
01eec727
CW		 1994 *
1995 * This should only fail upon a hung GPU, in which case we
1996 * can safely continue.
85345517 1997 */
ce453d81 1998 ret = i915_gem_object_flush_gpu(obj);
01eec727 1999 (void) ret;
265db958
CW		 2000 }
2001
21c74a8e
JW		 2002 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2003 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2004 if (ret) {
265db958 2005 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2006 mutex_unlock(&dev->struct_mutex);
4e6cfefc 2007 return ret;
79e53945 2008 }
3c4fdcfb 2009
b7f1de28
CW		 2010 if (old_fb) {
2011 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2012 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2013 }
652c393a 2014
5c3b82e2 2015 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2016
2017 if (!dev->primary->master)
5c3b82e2 2018 return 0;
79e53945
JB		 2019
2020 master_priv = dev->primary->master->driver_priv;
2021 if (!master_priv->sarea_priv)
5c3b82e2 2022 return 0;
79e53945 2023
265db958 2024 if (intel_crtc->pipe) {
79e53945
JB		 2025 master_priv->sarea_priv->pipeB_x = x;
2026 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2027 } else {
2028 master_priv->sarea_priv->pipeA_x = x;
2029 master_priv->sarea_priv->pipeA_y = y;
79e53945 2030 }
5c3b82e2
CW		 2031
2032 return 0;
79e53945
JB		 2033}
2034
5eddb70b 2035static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2036{
2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 u32 dpa_ctl;
2040
28c97730 2041 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2042 dpa_ctl = I915_READ(DP_A);
2043 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2044
2045 if (clock < 200000) {
2046 u32 temp;
2047 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2048 /* workaround for 160Mhz:
2049 1) program 0x4600c bits 15:0 = 0x8124
2050 2) program 0x46010 bit 0 = 1
2051 3) program 0x46034 bit 24 = 1
2052 4) program 0x64000 bit 14 = 1
2053 */
2054 temp = I915_READ(0x4600c);
2055 temp &= 0xffff0000;
2056 I915_WRITE(0x4600c, temp | 0x8124);
2057
2058 temp = I915_READ(0x46010);
2059 I915_WRITE(0x46010, temp | 1);
2060
2061 temp = I915_READ(0x46034);
2062 I915_WRITE(0x46034, temp | (1 << 24));
2063 } else {
2064 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2065 }
2066 I915_WRITE(DP_A, dpa_ctl);
2067
5eddb70b 2068 POSTING_READ(DP_A);
32f9d658
ZW		 2069 udelay(500);
2070}
2071
5e84e1a4
ZW		 2072static void intel_fdi_normal_train(struct drm_crtc *crtc)
2073{
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 int pipe = intel_crtc->pipe;
2078 u32 reg, temp;
2079
2080 /* enable normal train */
2081 reg = FDI_TX_CTL(pipe);
2082 temp = I915_READ(reg);
61e499bf 2083 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2084 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2085 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2086 } else {
2087 temp &= ~FDI_LINK_TRAIN_NONE;
2088 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2089 }
5e84e1a4
ZW		 2090 I915_WRITE(reg, temp);
2091
2092 reg = FDI_RX_CTL(pipe);
2093 temp = I915_READ(reg);
2094 if (HAS_PCH_CPT(dev)) {
2095 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2096 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2097 } else {
2098 temp &= ~FDI_LINK_TRAIN_NONE;
2099 temp |= FDI_LINK_TRAIN_NONE;
2100 }
2101 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2102
2103 /* wait one idle pattern time */
2104 POSTING_READ(reg);
2105 udelay(1000);
357555c0
JB		 2106
2107 /* IVB wants error correction enabled */
2108 if (IS_IVYBRIDGE(dev))
2109 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2110 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2111}
2112
8db9d77b
ZW		 2113/* The FDI link training functions for ILK/Ibexpeak. */
2114static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2115{
2116 struct drm_device *dev = crtc->dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119 int pipe = intel_crtc->pipe;
0fc932b8 2120 int plane = intel_crtc->plane;
5eddb70b 2121 u32 reg, temp, tries;
8db9d77b 2122
0fc932b8
JB		 2123 /* FDI needs bits from pipe & plane first */
2124 assert_pipe_enabled(dev_priv, pipe);
2125 assert_plane_enabled(dev_priv, plane);
2126
e1a44743
AJ		 2127 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2128 for train result */
5eddb70b
CW		 2129 reg = FDI_RX_IMR(pipe);
2130 temp = I915_READ(reg);
e1a44743
AJ		 2131 temp &= ~FDI_RX_SYMBOL_LOCK;
2132 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2133 I915_WRITE(reg, temp);
2134 I915_READ(reg);
e1a44743
AJ		 2135 udelay(150);
2136
8db9d77b 2137 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2138 reg = FDI_TX_CTL(pipe);
2139 temp = I915_READ(reg);
77ffb597
AJ		 2140 temp &= ~(7 << 19);
2141 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2142 temp &= ~FDI_LINK_TRAIN_NONE;
2143 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2144 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2145
5eddb70b
CW		 2146 reg = FDI_RX_CTL(pipe);
2147 temp = I915_READ(reg);
8db9d77b
ZW		 2148 temp &= ~FDI_LINK_TRAIN_NONE;
2149 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2150 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2151
2152 POSTING_READ(reg);
8db9d77b
ZW		 2153 udelay(150);
2154
5b2adf89 2155 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2156 if (HAS_PCH_IBX(dev)) {
2157 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2158 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2159 FDI_RX_PHASE_SYNC_POINTER_EN);
2160 }
5b2adf89 2161
5eddb70b 2162 reg = FDI_RX_IIR(pipe);
e1a44743 2163 for (tries = 0; tries < 5; tries++) {
5eddb70b 2164 temp = I915_READ(reg);
8db9d77b
ZW		 2165 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2166
2167 if ((temp & FDI_RX_BIT_LOCK)) {
2168 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2169 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2170 break;
2171 }
8db9d77b 2172 }
e1a44743 2173 if (tries == 5)
5eddb70b 2174 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2175
2176 /* Train 2 */
5eddb70b
CW		 2177 reg = FDI_TX_CTL(pipe);
2178 temp = I915_READ(reg);
8db9d77b
ZW		 2179 temp &= ~FDI_LINK_TRAIN_NONE;
2180 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2181 I915_WRITE(reg, temp);
8db9d77b 2182
5eddb70b
CW		 2183 reg = FDI_RX_CTL(pipe);
2184 temp = I915_READ(reg);
8db9d77b
ZW		 2185 temp &= ~FDI_LINK_TRAIN_NONE;
2186 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2187 I915_WRITE(reg, temp);
8db9d77b 2188
5eddb70b
CW		 2189 POSTING_READ(reg);
2190 udelay(150);
8db9d77b 2191
5eddb70b 2192 reg = FDI_RX_IIR(pipe);
e1a44743 2193 for (tries = 0; tries < 5; tries++) {
5eddb70b 2194 temp = I915_READ(reg);
8db9d77b
ZW		 2195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2196
2197 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2198 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2199 DRM_DEBUG_KMS("FDI train 2 done.\n");
2200 break;
2201 }
8db9d77b 2202 }
e1a44743 2203 if (tries == 5)
5eddb70b 2204 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2205
2206 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2207
8db9d77b
ZW		 2208}
2209
311bd68e 2210static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2211 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2212 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2213 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2214 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2215};
2216
2217/* The FDI link training functions for SNB/Cougarpoint. */
2218static void gen6_fdi_link_train(struct drm_crtc *crtc)
2219{
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223 int pipe = intel_crtc->pipe;
5eddb70b 2224 u32 reg, temp, i;
8db9d77b 2225
e1a44743
AJ		 2226 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2227 for train result */
5eddb70b
CW		 2228 reg = FDI_RX_IMR(pipe);
2229 temp = I915_READ(reg);
e1a44743
AJ		 2230 temp &= ~FDI_RX_SYMBOL_LOCK;
2231 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2232 I915_WRITE(reg, temp);
2233
2234 POSTING_READ(reg);
e1a44743
AJ		 2235 udelay(150);
2236
8db9d77b 2237 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2238 reg = FDI_TX_CTL(pipe);
2239 temp = I915_READ(reg);
77ffb597
AJ		 2240 temp &= ~(7 << 19);
2241 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2242 temp &= ~FDI_LINK_TRAIN_NONE;
2243 temp |= FDI_LINK_TRAIN_PATTERN_1;
2244 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2245 /* SNB-B */
2246 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2247 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2248
5eddb70b
CW		 2249 reg = FDI_RX_CTL(pipe);
2250 temp = I915_READ(reg);
8db9d77b
ZW		 2251 if (HAS_PCH_CPT(dev)) {
2252 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2253 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2254 } else {
2255 temp &= ~FDI_LINK_TRAIN_NONE;
2256 temp |= FDI_LINK_TRAIN_PATTERN_1;
2257 }
5eddb70b
CW		 2258 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2259
2260 POSTING_READ(reg);
8db9d77b
ZW		 2261 udelay(150);
2262
8db9d77b 2263 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2264 reg = FDI_TX_CTL(pipe);
2265 temp = I915_READ(reg);
8db9d77b
ZW		 2266 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2267 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2268 I915_WRITE(reg, temp);
2269
2270 POSTING_READ(reg);
8db9d77b
ZW		 2271 udelay(500);
2272
5eddb70b
CW		 2273 reg = FDI_RX_IIR(pipe);
2274 temp = I915_READ(reg);
8db9d77b
ZW		 2275 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2276
2277 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2278 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2279 DRM_DEBUG_KMS("FDI train 1 done.\n");
2280 break;
2281 }
2282 }
2283 if (i == 4)
5eddb70b 2284 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2285
2286 /* Train 2 */
5eddb70b
CW		 2287 reg = FDI_TX_CTL(pipe);
2288 temp = I915_READ(reg);
8db9d77b
ZW		 2289 temp &= ~FDI_LINK_TRAIN_NONE;
2290 temp |= FDI_LINK_TRAIN_PATTERN_2;
2291 if (IS_GEN6(dev)) {
2292 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2293 /* SNB-B */
2294 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2295 }
5eddb70b 2296 I915_WRITE(reg, temp);
8db9d77b 2297
5eddb70b
CW		 2298 reg = FDI_RX_CTL(pipe);
2299 temp = I915_READ(reg);
8db9d77b
ZW		 2300 if (HAS_PCH_CPT(dev)) {
2301 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2302 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2303 } else {
2304 temp &= ~FDI_LINK_TRAIN_NONE;
2305 temp |= FDI_LINK_TRAIN_PATTERN_2;
2306 }
5eddb70b
CW		 2307 I915_WRITE(reg, temp);
2308
2309 POSTING_READ(reg);
8db9d77b
ZW		 2310 udelay(150);
2311
2312 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2313 reg = FDI_TX_CTL(pipe);
2314 temp = I915_READ(reg);
8db9d77b
ZW		 2315 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2316 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2317 I915_WRITE(reg, temp);
2318
2319 POSTING_READ(reg);
8db9d77b
ZW		 2320 udelay(500);
2321
5eddb70b
CW		 2322 reg = FDI_RX_IIR(pipe);
2323 temp = I915_READ(reg);
8db9d77b
ZW		 2324 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2325
2326 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2327 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2328 DRM_DEBUG_KMS("FDI train 2 done.\n");
2329 break;
2330 }
2331 }
2332 if (i == 4)
5eddb70b 2333 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2334
2335 DRM_DEBUG_KMS("FDI train done.\n");
2336}
2337
357555c0
JB		 2338/* Manual link training for Ivy Bridge A0 parts */
2339static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2340{
2341 struct drm_device *dev = crtc->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344 int pipe = intel_crtc->pipe;
2345 u32 reg, temp, i;
2346
2347 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2348 for train result */
2349 reg = FDI_RX_IMR(pipe);
2350 temp = I915_READ(reg);
2351 temp &= ~FDI_RX_SYMBOL_LOCK;
2352 temp &= ~FDI_RX_BIT_LOCK;
2353 I915_WRITE(reg, temp);
2354
2355 POSTING_READ(reg);
2356 udelay(150);
2357
2358 /* enable CPU FDI TX and PCH FDI RX */
2359 reg = FDI_TX_CTL(pipe);
2360 temp = I915_READ(reg);
2361 temp &= ~(7 << 19);
2362 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2363 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2364 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2366 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2367 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2368
2369 reg = FDI_RX_CTL(pipe);
2370 temp = I915_READ(reg);
2371 temp &= ~FDI_LINK_TRAIN_AUTO;
2372 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2373 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2374 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2375
2376 POSTING_READ(reg);
2377 udelay(150);
2378
2379 for (i = 0; i < 4; i++ ) {
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2383 temp |= snb_b_fdi_train_param[i];
2384 I915_WRITE(reg, temp);
2385
2386 POSTING_READ(reg);
2387 udelay(500);
2388
2389 reg = FDI_RX_IIR(pipe);
2390 temp = I915_READ(reg);
2391 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2392
2393 if (temp & FDI_RX_BIT_LOCK ||
2394 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2395 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2396 DRM_DEBUG_KMS("FDI train 1 done.\n");
2397 break;
2398 }
2399 }
2400 if (i == 4)
2401 DRM_ERROR("FDI train 1 fail!\n");
2402
2403 /* Train 2 */
2404 reg = FDI_TX_CTL(pipe);
2405 temp = I915_READ(reg);
2406 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2407 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2408 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2409 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2410 I915_WRITE(reg, temp);
2411
2412 reg = FDI_RX_CTL(pipe);
2413 temp = I915_READ(reg);
2414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2415 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2416 I915_WRITE(reg, temp);
2417
2418 POSTING_READ(reg);
2419 udelay(150);
2420
2421 for (i = 0; i < 4; i++ ) {
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425 temp |= snb_b_fdi_train_param[i];
2426 I915_WRITE(reg, temp);
2427
2428 POSTING_READ(reg);
2429 udelay(500);
2430
2431 reg = FDI_RX_IIR(pipe);
2432 temp = I915_READ(reg);
2433 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2434
2435 if (temp & FDI_RX_SYMBOL_LOCK) {
2436 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2437 DRM_DEBUG_KMS("FDI train 2 done.\n");
2438 break;
2439 }
2440 }
2441 if (i == 4)
2442 DRM_ERROR("FDI train 2 fail!\n");
2443
2444 DRM_DEBUG_KMS("FDI train done.\n");
2445}
2446
2447static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2448{
2449 struct drm_device *dev = crtc->dev;
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2452 int pipe = intel_crtc->pipe;
5eddb70b 2453 u32 reg, temp;
79e53945 2454
c64e311e 2455 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2456 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2457 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2458
c98e9dcf 2459 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2460 reg = FDI_RX_CTL(pipe);
2461 temp = I915_READ(reg);
2462 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2463 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2464 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2465 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2466
2467 POSTING_READ(reg);
c98e9dcf
JB		 2468 udelay(200);
2469
2470 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2471 temp = I915_READ(reg);
2472 I915_WRITE(reg, temp | FDI_PCDCLK);
2473
2474 POSTING_READ(reg);
c98e9dcf
JB		 2475 udelay(200);
2476
2477 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2478 reg = FDI_TX_CTL(pipe);
2479 temp = I915_READ(reg);
c98e9dcf 2480 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2481 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2482
2483 POSTING_READ(reg);
c98e9dcf 2484 udelay(100);
6be4a607 2485 }
0e23b99d
JB		 2486}
2487
0fc932b8
JB		 2488static void ironlake_fdi_disable(struct drm_crtc *crtc)
2489{
2490 struct drm_device *dev = crtc->dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2493 int pipe = intel_crtc->pipe;
2494 u32 reg, temp;
2495
2496 /* disable CPU FDI tx and PCH FDI rx */
2497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
2499 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2500 POSTING_READ(reg);
2501
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 temp &= ~(0x7 << 16);
2505 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2506 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2507
2508 POSTING_READ(reg);
2509 udelay(100);
2510
2511 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2512 if (HAS_PCH_IBX(dev)) {
2513 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2514 I915_WRITE(FDI_RX_CHICKEN(pipe),
2515 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2516 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2517 }
0fc932b8
JB		 2518
2519 /* still set train pattern 1 */
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 I915_WRITE(reg, temp);
2525
2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 if (HAS_PCH_CPT(dev)) {
2529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2531 } else {
2532 temp &= ~FDI_LINK_TRAIN_NONE;
2533 temp |= FDI_LINK_TRAIN_PATTERN_1;
2534 }
2535 /* BPC in FDI rx is consistent with that in PIPECONF */
2536 temp &= ~(0x07 << 16);
2537 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2538 I915_WRITE(reg, temp);
2539
2540 POSTING_READ(reg);
2541 udelay(100);
2542}
2543
6b383a7f
CW		 2544/*
2545 * When we disable a pipe, we need to clear any pending scanline wait events
2546 * to avoid hanging the ring, which we assume we are waiting on.
2547 */
2548static void intel_clear_scanline_wait(struct drm_device *dev)
2549{
2550 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2551 struct intel_ring_buffer *ring;
6b383a7f
CW		 2552 u32 tmp;
2553
2554 if (IS_GEN2(dev))
2555 /* Can't break the hang on i8xx */
2556 return;
2557
1ec14ad3 2558 ring = LP_RING(dev_priv);
8168bd48
CW		 2559 tmp = I915_READ_CTL(ring);
2560 if (tmp & RING_WAIT)
2561 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2562}
2563
e6c3a2a6
CW		 2564static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2565{
05394f39 2566 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2567 struct drm_i915_private *dev_priv;
2568
2569 if (crtc->fb == NULL)
2570 return;
2571
05394f39 2572 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2573 dev_priv = crtc->dev->dev_private;
2574 wait_event(dev_priv->pending_flip_queue,
05394f39 2575 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2576}
2577
040484af
JB		 2578static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2579{
2580 struct drm_device *dev = crtc->dev;
2581 struct drm_mode_config *mode_config = &dev->mode_config;
2582 struct intel_encoder *encoder;
2583
2584 /*
2585 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2586 * must be driven by its own crtc; no sharing is possible.
2587 */
2588 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2589 if (encoder->base.crtc != crtc)
2590 continue;
2591
2592 switch (encoder->type) {
2593 case INTEL_OUTPUT_EDP:
2594 if (!intel_encoder_is_pch_edp(&encoder->base))
2595 return false;
2596 continue;
2597 }
2598 }
2599
2600 return true;
2601}
2602
f67a559d
JB		 2603/*
2604 * Enable PCH resources required for PCH ports:
2605 * - PCH PLLs
2606 * - FDI training & RX/TX
2607 * - update transcoder timings
2608 * - DP transcoding bits
2609 * - transcoder
2610 */
2611static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2612{
2613 struct drm_device *dev = crtc->dev;
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616 int pipe = intel_crtc->pipe;
5eddb70b 2617 u32 reg, temp;
2c07245f 2618
c98e9dcf 2619 /* For PCH output, training FDI link */
674cf967 2620 dev_priv->display.fdi_link_train(crtc);
2c07245f 2621
92f2584a 2622 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2623
c98e9dcf
JB		 2624 if (HAS_PCH_CPT(dev)) {
2625 /* Be sure PCH DPLL SEL is set */
2626 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2627 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2628 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2629 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2630 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2631 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2632 }
5eddb70b 2633
d9b6cb56
JB		 2634 /* set transcoder timing, panel must allow it */
2635 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2636 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2637 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2638 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2639
5eddb70b
CW		 2640 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2641 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2642 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2643
5e84e1a4
ZW		 2644 intel_fdi_normal_train(crtc);
2645
c98e9dcf
JB		 2646 /* For PCH DP, enable TRANS_DP_CTL */
2647 if (HAS_PCH_CPT(dev) &&
2648 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2649 reg = TRANS_DP_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2652 TRANS_DP_SYNC_MASK |
2653 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2654 temp |= (TRANS_DP_OUTPUT_ENABLE |
2655 TRANS_DP_ENH_FRAMING);
220cad3c 2656 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2657
2658 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2659 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2660 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2661 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2662
2663 switch (intel_trans_dp_port_sel(crtc)) {
2664 case PCH_DP_B:
5eddb70b 2665 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2666 break;
2667 case PCH_DP_C:
5eddb70b 2668 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2669 break;
2670 case PCH_DP_D:
5eddb70b 2671 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2672 break;
2673 default:
2674 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2675 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2676 break;
32f9d658 2677 }
2c07245f 2678
5eddb70b 2679 I915_WRITE(reg, temp);
6be4a607 2680 }
b52eb4dc 2681
040484af 2682 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2683}
2684
2685static void ironlake_crtc_enable(struct drm_crtc *crtc)
2686{
2687 struct drm_device *dev = crtc->dev;
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2690 int pipe = intel_crtc->pipe;
2691 int plane = intel_crtc->plane;
2692 u32 temp;
2693 bool is_pch_port;
2694
2695 if (intel_crtc->active)
2696 return;
2697
2698 intel_crtc->active = true;
2699 intel_update_watermarks(dev);
2700
2701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2702 temp = I915_READ(PCH_LVDS);
2703 if ((temp & LVDS_PORT_EN) == 0)
2704 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2705 }
2706
2707 is_pch_port = intel_crtc_driving_pch(crtc);
2708
2709 if (is_pch_port)
357555c0 2710 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2711 else
2712 ironlake_fdi_disable(crtc);
2713
2714 /* Enable panel fitting for LVDS */
2715 if (dev_priv->pch_pf_size &&
2716 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2717 /* Force use of hard-coded filter coefficients
2718 * as some pre-programmed values are broken,
2719 * e.g. x201.
2720 */
9db4a9c7
JB		 2721 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2722 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2723 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2724 }
2725
9c54c0dd
JB		 2726 /*
2727 * On ILK+ LUT must be loaded before the pipe is running but with
2728 * clocks enabled
2729 */
2730 intel_crtc_load_lut(crtc);
2731
f67a559d
JB		 2732 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2733 intel_enable_plane(dev_priv, plane, pipe);
2734
2735 if (is_pch_port)
2736 ironlake_pch_enable(crtc);
c98e9dcf 2737
d1ebd816 2738 mutex_lock(&dev->struct_mutex);
bed4a673 2739 intel_update_fbc(dev);
d1ebd816
BW		 2740 mutex_unlock(&dev->struct_mutex);
2741
6b383a7f 2742 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2743}
2744
2745static void ironlake_crtc_disable(struct drm_crtc *crtc)
2746{
2747 struct drm_device *dev = crtc->dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2750 int pipe = intel_crtc->pipe;
2751 int plane = intel_crtc->plane;
5eddb70b 2752 u32 reg, temp;
b52eb4dc 2753
f7abfe8b
CW		 2754 if (!intel_crtc->active)
2755 return;
2756
e6c3a2a6 2757 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2758 drm_vblank_off(dev, pipe);
6b383a7f 2759 intel_crtc_update_cursor(crtc, false);
5eddb70b 2760
b24e7179 2761 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2762
6be4a607
JB		 2763 if (dev_priv->cfb_plane == plane &&
2764 dev_priv->display.disable_fbc)
2765 dev_priv->display.disable_fbc(dev);
2c07245f 2766
b24e7179 2767 intel_disable_pipe(dev_priv, pipe);
32f9d658 2768
6be4a607 2769 /* Disable PF */
9db4a9c7
JB		 2770 I915_WRITE(PF_CTL(pipe), 0);
2771 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2772
0fc932b8 2773 ironlake_fdi_disable(crtc);
2c07245f 2774
47a05eca
JB		 2775 /* This is a horrible layering violation; we should be doing this in
2776 * the connector/encoder ->prepare instead, but we don't always have
2777 * enough information there about the config to know whether it will
2778 * actually be necessary or just cause undesired flicker.
2779 */
2780 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2781
040484af 2782 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2783
6be4a607
JB		 2784 if (HAS_PCH_CPT(dev)) {
2785 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2786 reg = TRANS_DP_CTL(pipe);
2787 temp = I915_READ(reg);
2788 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2789 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2790 I915_WRITE(reg, temp);
6be4a607
JB		 2791
2792 /* disable DPLL_SEL */
2793 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2794 switch (pipe) {
2795 case 0:
2796 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2797 break;
2798 case 1:
6be4a607 2799 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2800 break;
2801 case 2:
2802 /* FIXME: manage transcoder PLLs? */
2803 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2804 break;
2805 default:
2806 BUG(); /* wtf */
2807 }
6be4a607 2808 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2809 }
e3421a18 2810
6be4a607 2811 /* disable PCH DPLL */
92f2584a 2812 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2813
6be4a607 2814 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2818
6be4a607 2819 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2823
2824 POSTING_READ(reg);
6be4a607 2825 udelay(100);
8db9d77b 2826
5eddb70b
CW		 2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2830
6be4a607 2831 /* Wait for the clocks to turn off. */
5eddb70b 2832 POSTING_READ(reg);
6be4a607 2833 udelay(100);
6b383a7f 2834
f7abfe8b 2835 intel_crtc->active = false;
6b383a7f 2836 intel_update_watermarks(dev);
d1ebd816
BW		 2837
2838 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2839 intel_update_fbc(dev);
2840 intel_clear_scanline_wait(dev);
d1ebd816 2841 mutex_unlock(&dev->struct_mutex);
6be4a607 2842}
1b3c7a47 2843
6be4a607
JB		 2844static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2845{
2846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2847 int pipe = intel_crtc->pipe;
2848 int plane = intel_crtc->plane;
8db9d77b 2849
6be4a607
JB		 2850 /* XXX: When our outputs are all unaware of DPMS modes other than off
2851 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2852 */
2853 switch (mode) {
2854 case DRM_MODE_DPMS_ON:
2855 case DRM_MODE_DPMS_STANDBY:
2856 case DRM_MODE_DPMS_SUSPEND:
2857 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2858 ironlake_crtc_enable(crtc);
2859 break;
1b3c7a47 2860
6be4a607
JB		 2861 case DRM_MODE_DPMS_OFF:
2862 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2863 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2864 break;
2865 }
2866}
2867
02e792fb
DV		 2868static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2869{
02e792fb 2870 if (!enable && intel_crtc->overlay) {
23f09ce3 2871 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2872 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2873
23f09ce3 2874 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2875 dev_priv->mm.interruptible = false;
2876 (void) intel_overlay_switch_off(intel_crtc->overlay);
2877 dev_priv->mm.interruptible = true;
23f09ce3 2878 mutex_unlock(&dev->struct_mutex);
02e792fb 2879 }
02e792fb 2880
5dcdbcb0
CW		 2881 /* Let userspace switch the overlay on again. In most cases userspace
2882 * has to recompute where to put it anyway.
2883 */
02e792fb
DV		 2884}
2885
0b8765c6 2886static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2887{
2888 struct drm_device *dev = crtc->dev;
79e53945
JB		 2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2891 int pipe = intel_crtc->pipe;
80824003 2892 int plane = intel_crtc->plane;
79e53945 2893
f7abfe8b
CW		 2894 if (intel_crtc->active)
2895 return;
2896
2897 intel_crtc->active = true;
6b383a7f
CW		 2898 intel_update_watermarks(dev);
2899
63d7bbe9 2900 intel_enable_pll(dev_priv, pipe);
040484af 2901 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2902 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2903
0b8765c6 2904 intel_crtc_load_lut(crtc);
bed4a673 2905 intel_update_fbc(dev);
79e53945 2906
0b8765c6
JB		 2907 /* Give the overlay scaler a chance to enable if it's on this pipe */
2908 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2909 intel_crtc_update_cursor(crtc, true);
0b8765c6 2910}
79e53945 2911
0b8765c6
JB		 2912static void i9xx_crtc_disable(struct drm_crtc *crtc)
2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
2918 int plane = intel_crtc->plane;
b690e96c 2919
f7abfe8b
CW		 2920 if (!intel_crtc->active)
2921 return;
2922
0b8765c6 2923 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2924 intel_crtc_wait_for_pending_flips(crtc);
2925 drm_vblank_off(dev, pipe);
0b8765c6 2926 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2927 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2928
2929 if (dev_priv->cfb_plane == plane &&
2930 dev_priv->display.disable_fbc)
2931 dev_priv->display.disable_fbc(dev);
79e53945 2932
b24e7179 2933 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2934 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2935 intel_disable_pll(dev_priv, pipe);
0b8765c6 2936
f7abfe8b 2937 intel_crtc->active = false;
6b383a7f
CW		 2938 intel_update_fbc(dev);
2939 intel_update_watermarks(dev);
2940 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2941}
2942
2943static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2944{
2945 /* XXX: When our outputs are all unaware of DPMS modes other than off
2946 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2947 */
2948 switch (mode) {
2949 case DRM_MODE_DPMS_ON:
2950 case DRM_MODE_DPMS_STANDBY:
2951 case DRM_MODE_DPMS_SUSPEND:
2952 i9xx_crtc_enable(crtc);
2953 break;
2954 case DRM_MODE_DPMS_OFF:
2955 i9xx_crtc_disable(crtc);
79e53945
JB		 2956 break;
2957 }
2c07245f
ZW		 2958}
2959
2960/**
2961 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2962 */
2963static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2964{
2965 struct drm_device *dev = crtc->dev;
e70236a8 2966 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2967 struct drm_i915_master_private *master_priv;
2968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969 int pipe = intel_crtc->pipe;
2970 bool enabled;
2971
032d2a0d
CW		 2972 if (intel_crtc->dpms_mode == mode)
2973 return;
2974
65655d4a 2975 intel_crtc->dpms_mode = mode;
debcaddc 2976
e70236a8 2977 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2978
2979 if (!dev->primary->master)
2980 return;
2981
2982 master_priv = dev->primary->master->driver_priv;
2983 if (!master_priv->sarea_priv)
2984 return;
2985
2986 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2987
2988 switch (pipe) {
2989 case 0:
2990 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2991 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2992 break;
2993 case 1:
2994 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2995 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2996 break;
2997 default:
9db4a9c7 2998 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2999 break;
3000 }
79e53945
JB		 3001}
3002
cdd59983
CW		 3003static void intel_crtc_disable(struct drm_crtc *crtc)
3004{
3005 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3006 struct drm_device *dev = crtc->dev;
3007
3008 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3009
3010 if (crtc->fb) {
3011 mutex_lock(&dev->struct_mutex);
3012 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3013 mutex_unlock(&dev->struct_mutex);
3014 }
3015}
3016
7e7d76c3
JB		 3017/* Prepare for a mode set.
3018 *
3019 * Note we could be a lot smarter here. We need to figure out which outputs
3020 * will be enabled, which disabled (in short, how the config will changes)
3021 * and perform the minimum necessary steps to accomplish that, e.g. updating
3022 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3023 * panel fitting is in the proper state, etc.
3024 */
3025static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3026{
7e7d76c3 3027 i9xx_crtc_disable(crtc);
79e53945
JB		 3028}
3029
7e7d76c3 3030static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3031{
7e7d76c3 3032 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3033}
3034
3035static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3036{
7e7d76c3 3037 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3038}
3039
3040static void ironlake_crtc_commit(struct drm_crtc *crtc)
3041{
7e7d76c3 3042 ironlake_crtc_enable(crtc);
79e53945
JB		 3043}
3044
3045void intel_encoder_prepare (struct drm_encoder *encoder)
3046{
3047 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3048 /* lvds has its own version of prepare see intel_lvds_prepare */
3049 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3050}
3051
3052void intel_encoder_commit (struct drm_encoder *encoder)
3053{
3054 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3055 /* lvds has its own version of commit see intel_lvds_commit */
3056 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3057}
3058
ea5b213a
CW		 3059void intel_encoder_destroy(struct drm_encoder *encoder)
3060{
4ef69c7a 3061 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3062
ea5b213a
CW		 3063 drm_encoder_cleanup(encoder);
3064 kfree(intel_encoder);
3065}
3066
79e53945
JB		 3067static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3068 struct drm_display_mode *mode,
3069 struct drm_display_mode *adjusted_mode)
3070{
2c07245f 3071 struct drm_device *dev = crtc->dev;
89749350 3072
bad720ff 3073 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3074 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3075 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3076 return false;
2c07245f 3077 }
89749350
CW		 3078
3079 /* XXX some encoders set the crtcinfo, others don't.
3080 * Obviously we need some form of conflict resolution here...
3081 */
3082 if (adjusted_mode->crtc_htotal == 0)
3083 drm_mode_set_crtcinfo(adjusted_mode, 0);
3084
79e53945
JB		 3085 return true;
3086}
3087
e70236a8
JB		 3088static int i945_get_display_clock_speed(struct drm_device *dev)
3089{
3090 return 400000;
3091}
79e53945 3092
e70236a8 3093static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3094{
e70236a8
JB		 3095 return 333000;
3096}
79e53945 3097
e70236a8
JB		 3098static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3099{
3100 return 200000;
3101}
79e53945 3102
e70236a8
JB		 3103static int i915gm_get_display_clock_speed(struct drm_device *dev)
3104{
3105 u16 gcfgc = 0;
79e53945 3106
e70236a8
JB		 3107 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3108
3109 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3110 return 133000;
3111 else {
3112 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3113 case GC_DISPLAY_CLOCK_333_MHZ:
3114 return 333000;
3115 default:
3116 case GC_DISPLAY_CLOCK_190_200_MHZ:
3117 return 190000;
79e53945 3118 }
e70236a8
JB		 3119 }
3120}
3121
3122static int i865_get_display_clock_speed(struct drm_device *dev)
3123{
3124 return 266000;
3125}
3126
3127static int i855_get_display_clock_speed(struct drm_device *dev)
3128{
3129 u16 hpllcc = 0;
3130 /* Assume that the hardware is in the high speed state. This
3131 * should be the default.
3132 */
3133 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3134 case GC_CLOCK_133_200:
3135 case GC_CLOCK_100_200:
3136 return 200000;
3137 case GC_CLOCK_166_250:
3138 return 250000;
3139 case GC_CLOCK_100_133:
79e53945 3140 return 133000;
e70236a8 3141 }
79e53945 3142
e70236a8
JB		 3143 /* Shouldn't happen */
3144 return 0;
3145}
79e53945 3146
e70236a8
JB		 3147static int i830_get_display_clock_speed(struct drm_device *dev)
3148{
3149 return 133000;
79e53945
JB		 3150}
3151
2c07245f
ZW		 3152struct fdi_m_n {
3153 u32 tu;
3154 u32 gmch_m;
3155 u32 gmch_n;
3156 u32 link_m;
3157 u32 link_n;
3158};
3159
3160static void
3161fdi_reduce_ratio(u32 *num, u32 *den)
3162{
3163 while (*num > 0xffffff || *den > 0xffffff) {
3164 *num >>= 1;
3165 *den >>= 1;
3166 }
3167}
3168
2c07245f 3169static void
f2b115e6
AJ		 3170ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3171 int link_clock, struct fdi_m_n *m_n)
2c07245f 3172{
2c07245f
ZW		 3173 m_n->tu = 64; /* default size */
3174
22ed1113
CW		 3175 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3176 m_n->gmch_m = bits_per_pixel * pixel_clock;
3177 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3178 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3179
22ed1113
CW		 3180 m_n->link_m = pixel_clock;
3181 m_n->link_n = link_clock;
2c07245f
ZW		 3182 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3183}
3184
3185
7662c8bd
SL		 3186struct intel_watermark_params {
3187 unsigned long fifo_size;
3188 unsigned long max_wm;
3189 unsigned long default_wm;
3190 unsigned long guard_size;
3191 unsigned long cacheline_size;
3192};
3193
f2b115e6 3194/* Pineview has different values for various configs */
d210246a 3195static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3196 PINEVIEW_DISPLAY_FIFO,
3197 PINEVIEW_MAX_WM,
3198 PINEVIEW_DFT_WM,
3199 PINEVIEW_GUARD_WM,
3200 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3201};
d210246a 3202static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3203 PINEVIEW_DISPLAY_FIFO,
3204 PINEVIEW_MAX_WM,
3205 PINEVIEW_DFT_HPLLOFF_WM,
3206 PINEVIEW_GUARD_WM,
3207 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3208};
d210246a 3209static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3210 PINEVIEW_CURSOR_FIFO,
3211 PINEVIEW_CURSOR_MAX_WM,
3212 PINEVIEW_CURSOR_DFT_WM,
3213 PINEVIEW_CURSOR_GUARD_WM,
3214 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3215};
d210246a 3216static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3217 PINEVIEW_CURSOR_FIFO,
3218 PINEVIEW_CURSOR_MAX_WM,
3219 PINEVIEW_CURSOR_DFT_WM,
3220 PINEVIEW_CURSOR_GUARD_WM,
3221 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3222};
d210246a 3223static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3224 G4X_FIFO_SIZE,
3225 G4X_MAX_WM,
3226 G4X_MAX_WM,
3227 2,
3228 G4X_FIFO_LINE_SIZE,
3229};
d210246a 3230static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3231 I965_CURSOR_FIFO,
3232 I965_CURSOR_MAX_WM,
3233 I965_CURSOR_DFT_WM,
3234 2,
3235 G4X_FIFO_LINE_SIZE,
3236};
d210246a 3237static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3238 I965_CURSOR_FIFO,
3239 I965_CURSOR_MAX_WM,
3240 I965_CURSOR_DFT_WM,
3241 2,
3242 I915_FIFO_LINE_SIZE,
3243};
d210246a 3244static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3245 I945_FIFO_SIZE,
7662c8bd
SL		 3246 I915_MAX_WM,
3247 1,
dff33cfc
JB		 3248 2,
3249 I915_FIFO_LINE_SIZE
7662c8bd 3250};
d210246a 3251static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3252 I915_FIFO_SIZE,
7662c8bd
SL		 3253 I915_MAX_WM,
3254 1,
dff33cfc 3255 2,
7662c8bd
SL		 3256 I915_FIFO_LINE_SIZE
3257};
d210246a 3258static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3259 I855GM_FIFO_SIZE,
3260 I915_MAX_WM,
3261 1,
dff33cfc 3262 2,
7662c8bd
SL		 3263 I830_FIFO_LINE_SIZE
3264};
d210246a 3265static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3266 I830_FIFO_SIZE,
3267 I915_MAX_WM,
3268 1,
dff33cfc 3269 2,
7662c8bd
SL		 3270 I830_FIFO_LINE_SIZE
3271};
3272
d210246a 3273static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3274 ILK_DISPLAY_FIFO,
3275 ILK_DISPLAY_MAXWM,
3276 ILK_DISPLAY_DFTWM,
3277 2,
3278 ILK_FIFO_LINE_SIZE
3279};
d210246a 3280static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3281 ILK_CURSOR_FIFO,
3282 ILK_CURSOR_MAXWM,
3283 ILK_CURSOR_DFTWM,
3284 2,
3285 ILK_FIFO_LINE_SIZE
3286};
d210246a 3287static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3288 ILK_DISPLAY_SR_FIFO,
3289 ILK_DISPLAY_MAX_SRWM,
3290 ILK_DISPLAY_DFT_SRWM,
3291 2,
3292 ILK_FIFO_LINE_SIZE
3293};
d210246a 3294static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3295 ILK_CURSOR_SR_FIFO,
3296 ILK_CURSOR_MAX_SRWM,
3297 ILK_CURSOR_DFT_SRWM,
3298 2,
3299 ILK_FIFO_LINE_SIZE
3300};
3301
d210246a 3302static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3303 SNB_DISPLAY_FIFO,
3304 SNB_DISPLAY_MAXWM,
3305 SNB_DISPLAY_DFTWM,
3306 2,
3307 SNB_FIFO_LINE_SIZE
3308};
d210246a 3309static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3310 SNB_CURSOR_FIFO,
3311 SNB_CURSOR_MAXWM,
3312 SNB_CURSOR_DFTWM,
3313 2,
3314 SNB_FIFO_LINE_SIZE
3315};
d210246a 3316static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3317 SNB_DISPLAY_SR_FIFO,
3318 SNB_DISPLAY_MAX_SRWM,
3319 SNB_DISPLAY_DFT_SRWM,
3320 2,
3321 SNB_FIFO_LINE_SIZE
3322};
d210246a 3323static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3324 SNB_CURSOR_SR_FIFO,
3325 SNB_CURSOR_MAX_SRWM,
3326 SNB_CURSOR_DFT_SRWM,
3327 2,
3328 SNB_FIFO_LINE_SIZE
3329};
3330
3331
dff33cfc
JB		 3332/**
3333 * intel_calculate_wm - calculate watermark level
3334 * @clock_in_khz: pixel clock
3335 * @wm: chip FIFO params
3336 * @pixel_size: display pixel size
3337 * @latency_ns: memory latency for the platform
3338 *
3339 * Calculate the watermark level (the level at which the display plane will
3340 * start fetching from memory again). Each chip has a different display
3341 * FIFO size and allocation, so the caller needs to figure that out and pass
3342 * in the correct intel_watermark_params structure.
3343 *
3344 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3345 * on the pixel size. When it reaches the watermark level, it'll start
3346 * fetching FIFO line sized based chunks from memory until the FIFO fills
3347 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3348 * will occur, and a display engine hang could result.
3349 */
7662c8bd 3350static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3351 const struct intel_watermark_params *wm,
3352 int fifo_size,
7662c8bd
SL		 3353 int pixel_size,
3354 unsigned long latency_ns)
3355{
390c4dd4 3356 long entries_required, wm_size;
dff33cfc 3357
d660467c
JB		 3358 /*
3359 * Note: we need to make sure we don't overflow for various clock &
3360 * latency values.
3361 * clocks go from a few thousand to several hundred thousand.
3362 * latency is usually a few thousand
3363 */
3364 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3365 1000;
8de9b311 3366 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3367
bbb0aef5 3368 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3369
d210246a 3370 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3371
bbb0aef5 3372 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3373
390c4dd4
JB		 3374 /* Don't promote wm_size to unsigned... */
3375 if (wm_size > (long)wm->max_wm)
7662c8bd 3376 wm_size = wm->max_wm;
c3add4b6 3377 if (wm_size <= 0)
7662c8bd
SL		 3378 wm_size = wm->default_wm;
3379 return wm_size;
3380}
3381
3382struct cxsr_latency {
3383 int is_desktop;
95534263 3384 int is_ddr3;
7662c8bd
SL		 3385 unsigned long fsb_freq;
3386 unsigned long mem_freq;
3387 unsigned long display_sr;
3388 unsigned long display_hpll_disable;
3389 unsigned long cursor_sr;
3390 unsigned long cursor_hpll_disable;
3391};
3392
403c89ff 3393static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3394 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3395 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3396 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3397 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3398 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3399
3400 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3401 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3402 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3403 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3404 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3405
3406 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3407 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3408 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3409 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3410 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3411
3412 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3413 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3414 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3415 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3416 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3417
3418 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3419 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3420 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3421 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3422 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3423
3424 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3425 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3426 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3427 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3428 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3429};
3430
403c89ff
CW		 3431static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3432 int is_ddr3,
3433 int fsb,
3434 int mem)
7662c8bd 3435{
403c89ff 3436 const struct cxsr_latency *latency;
7662c8bd 3437 int i;
7662c8bd
SL		 3438
3439 if (fsb == 0 || mem == 0)
3440 return NULL;
3441
3442 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3443 latency = &cxsr_latency_table[i];
3444 if (is_desktop == latency->is_desktop &&
95534263 3445 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3446 fsb == latency->fsb_freq && mem == latency->mem_freq)
3447 return latency;
7662c8bd 3448 }
decbbcda 3449
28c97730 3450 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3451
3452 return NULL;
7662c8bd
SL		 3453}
3454
f2b115e6 3455static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3456{
3457 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3458
3459 /* deactivate cxsr */
3e33d94d 3460 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3461}
3462
bcc24fb4
JB		 3463/*
3464 * Latency for FIFO fetches is dependent on several factors:
3465 * - memory configuration (speed, channels)
3466 * - chipset
3467 * - current MCH state
3468 * It can be fairly high in some situations, so here we assume a fairly
3469 * pessimal value. It's a tradeoff between extra memory fetches (if we
3470 * set this value too high, the FIFO will fetch frequently to stay full)
3471 * and power consumption (set it too low to save power and we might see
3472 * FIFO underruns and display "flicker").
3473 *
3474 * A value of 5us seems to be a good balance; safe for very low end
3475 * platforms but not overly aggressive on lower latency configs.
3476 */
69e302a9 3477static const int latency_ns = 5000;
7662c8bd 3478
e70236a8 3479static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3480{
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 uint32_t dsparb = I915_READ(DSPARB);
3483 int size;
3484
8de9b311
CW		 3485 size = dsparb & 0x7f;
3486 if (plane)
3487 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3488
28c97730 3489 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3490 plane ? "B" : "A", size);
dff33cfc
JB		 3491
3492 return size;
3493}
7662c8bd 3494
e70236a8
JB		 3495static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3496{
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 uint32_t dsparb = I915_READ(DSPARB);
3499 int size;
3500
8de9b311
CW		 3501 size = dsparb & 0x1ff;
3502 if (plane)
3503 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3504 size >>= 1; /* Convert to cachelines */
dff33cfc 3505
28c97730 3506 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3507 plane ? "B" : "A", size);
dff33cfc
JB		 3508
3509 return size;
3510}
7662c8bd 3511
e70236a8
JB		 3512static int i845_get_fifo_size(struct drm_device *dev, int plane)
3513{
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 uint32_t dsparb = I915_READ(DSPARB);
3516 int size;
3517
3518 size = dsparb & 0x7f;
3519 size >>= 2; /* Convert to cachelines */
3520
28c97730 3521 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3522 plane ? "B" : "A",
3523 size);
e70236a8
JB		 3524
3525 return size;
3526}
3527
3528static int i830_get_fifo_size(struct drm_device *dev, int plane)
3529{
3530 struct drm_i915_private *dev_priv = dev->dev_private;
3531 uint32_t dsparb = I915_READ(DSPARB);
3532 int size;
3533
3534 size = dsparb & 0x7f;
3535 size >>= 1; /* Convert to cachelines */
3536
28c97730 3537 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3538 plane ? "B" : "A", size);
e70236a8
JB		 3539
3540 return size;
3541}
3542
d210246a
CW		 3543static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3544{
3545 struct drm_crtc *crtc, *enabled = NULL;
3546
3547 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3548 if (crtc->enabled && crtc->fb) {
3549 if (enabled)
3550 return NULL;
3551 enabled = crtc;
3552 }
3553 }
3554
3555 return enabled;
3556}
3557
3558static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3559{
3560 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3561 struct drm_crtc *crtc;
403c89ff 3562 const struct cxsr_latency *latency;
d4294342
ZY		 3563 u32 reg;
3564 unsigned long wm;
d4294342 3565
403c89ff 3566 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3567 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3568 if (!latency) {
3569 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3570 pineview_disable_cxsr(dev);
3571 return;
3572 }
3573
d210246a
CW		 3574 crtc = single_enabled_crtc(dev);
3575 if (crtc) {
3576 int clock = crtc->mode.clock;
3577 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3578
3579 /* Display SR */
d210246a
CW		 3580 wm = intel_calculate_wm(clock, &pineview_display_wm,
3581 pineview_display_wm.fifo_size,
d4294342
ZY		 3582 pixel_size, latency->display_sr);
3583 reg = I915_READ(DSPFW1);
3584 reg &= ~DSPFW_SR_MASK;
3585 reg |= wm << DSPFW_SR_SHIFT;
3586 I915_WRITE(DSPFW1, reg);
3587 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3588
3589 /* cursor SR */
d210246a
CW		 3590 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3591 pineview_display_wm.fifo_size,
d4294342
ZY		 3592 pixel_size, latency->cursor_sr);
3593 reg = I915_READ(DSPFW3);
3594 reg &= ~DSPFW_CURSOR_SR_MASK;
3595 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3596 I915_WRITE(DSPFW3, reg);
3597
3598 /* Display HPLL off SR */
d210246a
CW		 3599 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3600 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3601 pixel_size, latency->display_hpll_disable);
3602 reg = I915_READ(DSPFW3);
3603 reg &= ~DSPFW_HPLL_SR_MASK;
3604 reg |= wm & DSPFW_HPLL_SR_MASK;
3605 I915_WRITE(DSPFW3, reg);
3606
3607 /* cursor HPLL off SR */
d210246a
CW		 3608 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3609 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3610 pixel_size, latency->cursor_hpll_disable);
3611 reg = I915_READ(DSPFW3);
3612 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3613 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3614 I915_WRITE(DSPFW3, reg);
3615 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3616
3617 /* activate cxsr */
3e33d94d
CW		 3618 I915_WRITE(DSPFW3,
3619 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3620 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3621 } else {
3622 pineview_disable_cxsr(dev);
3623 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3624 }
3625}
3626
417ae147
CW		 3627static bool g4x_compute_wm0(struct drm_device *dev,
3628 int plane,
3629 const struct intel_watermark_params *display,
3630 int display_latency_ns,
3631 const struct intel_watermark_params *cursor,
3632 int cursor_latency_ns,
3633 int *plane_wm,
3634 int *cursor_wm)
3635{
3636 struct drm_crtc *crtc;
3637 int htotal, hdisplay, clock, pixel_size;
3638 int line_time_us, line_count;
3639 int entries, tlb_miss;
3640
3641 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3642 if (crtc->fb == NULL || !crtc->enabled) {
3643 *cursor_wm = cursor->guard_size;
3644 *plane_wm = display->guard_size;
417ae147 3645 return false;
5c72d064 3646 }
417ae147
CW		 3647
3648 htotal = crtc->mode.htotal;
3649 hdisplay = crtc->mode.hdisplay;
3650 clock = crtc->mode.clock;
3651 pixel_size = crtc->fb->bits_per_pixel / 8;
3652
3653 /* Use the small buffer method to calculate plane watermark */
3654 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3655 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3656 if (tlb_miss > 0)
3657 entries += tlb_miss;
3658 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3659 *plane_wm = entries + display->guard_size;
3660 if (*plane_wm > (int)display->max_wm)
3661 *plane_wm = display->max_wm;
3662
3663 /* Use the large buffer method to calculate cursor watermark */
3664 line_time_us = ((htotal * 1000) / clock);
3665 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3666 entries = line_count * 64 * pixel_size;
3667 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3668 if (tlb_miss > 0)
3669 entries += tlb_miss;
3670 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3671 *cursor_wm = entries + cursor->guard_size;
3672 if (*cursor_wm > (int)cursor->max_wm)
3673 *cursor_wm = (int)cursor->max_wm;
3674
3675 return true;
3676}
3677
3678/*
3679 * Check the wm result.
3680 *
3681 * If any calculated watermark values is larger than the maximum value that
3682 * can be programmed into the associated watermark register, that watermark
3683 * must be disabled.
3684 */
3685static bool g4x_check_srwm(struct drm_device *dev,
3686 int display_wm, int cursor_wm,
3687 const struct intel_watermark_params *display,
3688 const struct intel_watermark_params *cursor)
652c393a 3689{
417ae147
CW		 3690 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3691 display_wm, cursor_wm);
652c393a 3692
417ae147 3693 if (display_wm > display->max_wm) {
bbb0aef5 3694 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3695 display_wm, display->max_wm);
3696 return false;
3697 }
0e442c60 3698
417ae147 3699 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3700 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3701 cursor_wm, cursor->max_wm);
3702 return false;
3703 }
0e442c60 3704
417ae147
CW		 3705 if (!(display_wm || cursor_wm)) {
3706 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3707 return false;
3708 }
0e442c60 3709
417ae147
CW		 3710 return true;
3711}
0e442c60 3712
417ae147 3713static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3714 int plane,
3715 int latency_ns,
417ae147
CW		 3716 const struct intel_watermark_params *display,
3717 const struct intel_watermark_params *cursor,
3718 int *display_wm, int *cursor_wm)
3719{
d210246a
CW		 3720 struct drm_crtc *crtc;
3721 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3722 unsigned long line_time_us;
3723 int line_count, line_size;
3724 int small, large;
3725 int entries;
0e442c60 3726
417ae147
CW		 3727 if (!latency_ns) {
3728 *display_wm = *cursor_wm = 0;
3729 return false;
3730 }
0e442c60 3731
d210246a
CW		 3732 crtc = intel_get_crtc_for_plane(dev, plane);
3733 hdisplay = crtc->mode.hdisplay;
3734 htotal = crtc->mode.htotal;
3735 clock = crtc->mode.clock;
3736 pixel_size = crtc->fb->bits_per_pixel / 8;
3737
417ae147
CW		 3738 line_time_us = (htotal * 1000) / clock;
3739 line_count = (latency_ns / line_time_us + 1000) / 1000;
3740 line_size = hdisplay * pixel_size;
0e442c60 3741
417ae147
CW		 3742 /* Use the minimum of the small and large buffer method for primary */
3743 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3744 large = line_count * line_size;
0e442c60 3745
417ae147
CW		 3746 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3747 *display_wm = entries + display->guard_size;
4fe5e611 3748
417ae147
CW		 3749 /* calculate the self-refresh watermark for display cursor */
3750 entries = line_count * pixel_size * 64;
3751 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3752 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3753
417ae147
CW		 3754 return g4x_check_srwm(dev,
3755 *display_wm, *cursor_wm,
3756 display, cursor);
3757}
4fe5e611 3758
7ccb4a53 3759#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3760
3761static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3762{
3763 static const int sr_latency_ns = 12000;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3766 int plane_sr, cursor_sr;
3767 unsigned int enabled = 0;
417ae147
CW		 3768
3769 if (g4x_compute_wm0(dev, 0,
3770 &g4x_wm_info, latency_ns,
3771 &g4x_cursor_wm_info, latency_ns,
3772 &planea_wm, &cursora_wm))
d210246a 3773 enabled |= 1;
417ae147
CW		 3774
3775 if (g4x_compute_wm0(dev, 1,
3776 &g4x_wm_info, latency_ns,
3777 &g4x_cursor_wm_info, latency_ns,
3778 &planeb_wm, &cursorb_wm))
d210246a 3779 enabled |= 2;
417ae147
CW		 3780
3781 plane_sr = cursor_sr = 0;
d210246a
CW		 3782 if (single_plane_enabled(enabled) &&
3783 g4x_compute_srwm(dev, ffs(enabled) - 1,
3784 sr_latency_ns,
417ae147
CW		 3785 &g4x_wm_info,
3786 &g4x_cursor_wm_info,
3787 &plane_sr, &cursor_sr))
0e442c60 3788 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3789 else
3790 I915_WRITE(FW_BLC_SELF,
3791 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3792
308977ac
CW		 3793 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3794 planea_wm, cursora_wm,
3795 planeb_wm, cursorb_wm,
3796 plane_sr, cursor_sr);
0e442c60 3797
417ae147
CW		 3798 I915_WRITE(DSPFW1,
3799 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3800 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3801 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3802 planea_wm);
3803 I915_WRITE(DSPFW2,
3804 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3805 (cursora_wm << DSPFW_CURSORA_SHIFT));
3806 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3807 I915_WRITE(DSPFW3,
3808 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3809 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3810}
3811
d210246a 3812static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3813{
3814 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3815 struct drm_crtc *crtc;
3816 int srwm = 1;
4fe5e611 3817 int cursor_sr = 16;
1dc7546d
JB		 3818
3819 /* Calc sr entries for one plane configs */
d210246a
CW		 3820 crtc = single_enabled_crtc(dev);
3821 if (crtc) {
1dc7546d 3822 /* self-refresh has much higher latency */
69e302a9 3823 static const int sr_latency_ns = 12000;
d210246a
CW		 3824 int clock = crtc->mode.clock;
3825 int htotal = crtc->mode.htotal;
3826 int hdisplay = crtc->mode.hdisplay;
3827 int pixel_size = crtc->fb->bits_per_pixel / 8;
3828 unsigned long line_time_us;
3829 int entries;
1dc7546d 3830
d210246a 3831 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3832
3833 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3834 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3835 pixel_size * hdisplay;
3836 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3837 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3838 if (srwm < 0)
3839 srwm = 1;
1b07e04e 3840 srwm &= 0x1ff;
308977ac
CW		 3841 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3842 entries, srwm);
4fe5e611 3843
d210246a 3844 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3845 pixel_size * 64;
d210246a 3846 entries = DIV_ROUND_UP(entries,
8de9b311 3847 i965_cursor_wm_info.cacheline_size);
4fe5e611 3848 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3849 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3850
3851 if (cursor_sr > i965_cursor_wm_info.max_wm)
3852 cursor_sr = i965_cursor_wm_info.max_wm;
3853
3854 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3855 "cursor %d\n", srwm, cursor_sr);
3856
a6c45cf0 3857 if (IS_CRESTLINE(dev))
adcdbc66 3858 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3859 } else {
3860 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3861 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3862 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3863 & ~FW_BLC_SELF_EN);
1dc7546d 3864 }
7662c8bd 3865
1dc7546d
JB		 3866 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3867 srwm);
7662c8bd
SL		 3868
3869 /* 965 has limitations... */
417ae147
CW		 3870 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3871 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3872 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3873 /* update cursor SR watermark */
3874 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3875}
3876
d210246a 3877static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3878{
3879 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3880 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3881 uint32_t fwater_lo;
3882 uint32_t fwater_hi;
d210246a
CW		 3883 int cwm, srwm = 1;
3884 int fifo_size;
dff33cfc 3885 int planea_wm, planeb_wm;
d210246a 3886 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3887
72557b4f 3888 if (IS_I945GM(dev))
d210246a 3889 wm_info = &i945_wm_info;
a6c45cf0 3890 else if (!IS_GEN2(dev))
d210246a 3891 wm_info = &i915_wm_info;
7662c8bd 3892 else
d210246a
CW		 3893 wm_info = &i855_wm_info;
3894
3895 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3896 crtc = intel_get_crtc_for_plane(dev, 0);
3897 if (crtc->enabled && crtc->fb) {
3898 planea_wm = intel_calculate_wm(crtc->mode.clock,
3899 wm_info, fifo_size,
3900 crtc->fb->bits_per_pixel / 8,
3901 latency_ns);
3902 enabled = crtc;
3903 } else
3904 planea_wm = fifo_size - wm_info->guard_size;
3905
3906 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3907 crtc = intel_get_crtc_for_plane(dev, 1);
3908 if (crtc->enabled && crtc->fb) {
3909 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3910 wm_info, fifo_size,
3911 crtc->fb->bits_per_pixel / 8,
3912 latency_ns);
3913 if (enabled == NULL)
3914 enabled = crtc;
3915 else
3916 enabled = NULL;
3917 } else
3918 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3919
28c97730 3920 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3921
3922 /*
3923 * Overlay gets an aggressive default since video jitter is bad.
3924 */
3925 cwm = 2;
3926
18b2190c
AL		 3927 /* Play safe and disable self-refresh before adjusting watermarks. */
3928 if (IS_I945G(dev) || IS_I945GM(dev))
3929 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3930 else if (IS_I915GM(dev))
3931 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3932
dff33cfc 3933 /* Calc sr entries for one plane configs */
d210246a 3934 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3935 /* self-refresh has much higher latency */
69e302a9 3936 static const int sr_latency_ns = 6000;
d210246a
CW		 3937 int clock = enabled->mode.clock;
3938 int htotal = enabled->mode.htotal;
3939 int hdisplay = enabled->mode.hdisplay;
3940 int pixel_size = enabled->fb->bits_per_pixel / 8;
3941 unsigned long line_time_us;
3942 int entries;
dff33cfc 3943
d210246a 3944 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3945
3946 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3947 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3948 pixel_size * hdisplay;
3949 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3950 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3951 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3952 if (srwm < 0)
3953 srwm = 1;
ee980b80
LP		 3954
3955 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3956 I915_WRITE(FW_BLC_SELF,
3957 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3958 else if (IS_I915GM(dev))
ee980b80 3959 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3960 }
3961
28c97730 3962 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3963 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3964
dff33cfc
JB		 3965 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3966 fwater_hi = (cwm & 0x1f);
3967
3968 /* Set request length to 8 cachelines per fetch */
3969 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3970 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3971
3972 I915_WRITE(FW_BLC, fwater_lo);
3973 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3974
d210246a
CW		 3975 if (HAS_FW_BLC(dev)) {
3976 if (enabled) {
3977 if (IS_I945G(dev) || IS_I945GM(dev))
3978 I915_WRITE(FW_BLC_SELF,
3979 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3980 else if (IS_I915GM(dev))
3981 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3982 DRM_DEBUG_KMS("memory self refresh enabled\n");
3983 } else
3984 DRM_DEBUG_KMS("memory self refresh disabled\n");
3985 }
7662c8bd
SL		 3986}
3987
d210246a 3988static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3989{
3990 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3991 struct drm_crtc *crtc;
3992 uint32_t fwater_lo;
dff33cfc 3993 int planea_wm;
7662c8bd 3994
d210246a
CW		 3995 crtc = single_enabled_crtc(dev);
3996 if (crtc == NULL)
3997 return;
7662c8bd 3998
d210246a
CW		 3999 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4000 dev_priv->display.get_fifo_size(dev, 0),
4001 crtc->fb->bits_per_pixel / 8,
4002 latency_ns);
4003 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4004 fwater_lo |= (3<<8) | planea_wm;
4005
28c97730 4006 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4007
4008 I915_WRITE(FW_BLC, fwater_lo);
4009}
4010
7f8a8569 4011#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4012#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4013
1398261a
YL		 4014/*
4015 * Check the wm result.
4016 *
4017 * If any calculated watermark values is larger than the maximum value that
4018 * can be programmed into the associated watermark register, that watermark
4019 * must be disabled.
1398261a 4020 */
b79d4990
JB		 4021static bool ironlake_check_srwm(struct drm_device *dev, int level,
4022 int fbc_wm, int display_wm, int cursor_wm,
4023 const struct intel_watermark_params *display,
4024 const struct intel_watermark_params *cursor)
1398261a
YL		 4025{
4026 struct drm_i915_private *dev_priv = dev->dev_private;
4027
4028 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4029 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4030
4031 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4032 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4033 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4034
4035 /* fbc has it's own way to disable FBC WM */
4036 I915_WRITE(DISP_ARB_CTL,
4037 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4038 return false;
4039 }
4040
b79d4990 4041 if (display_wm > display->max_wm) {
1398261a 4042 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4043 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4044 return false;
4045 }
4046
b79d4990 4047 if (cursor_wm > cursor->max_wm) {
1398261a 4048 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4049 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4050 return false;
4051 }
4052
4053 if (!(fbc_wm || display_wm || cursor_wm)) {
4054 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4055 return false;
4056 }
4057
4058 return true;
4059}
4060
4061/*
4062 * Compute watermark values of WM[1-3],
4063 */
d210246a
CW		 4064static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4065 int latency_ns,
b79d4990
JB		 4066 const struct intel_watermark_params *display,
4067 const struct intel_watermark_params *cursor,
4068 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4069{
d210246a 4070 struct drm_crtc *crtc;
1398261a 4071 unsigned long line_time_us;
d210246a 4072 int hdisplay, htotal, pixel_size, clock;
b79d4990 4073 int line_count, line_size;
1398261a
YL		 4074 int small, large;
4075 int entries;
1398261a
YL		 4076
4077 if (!latency_ns) {
4078 *fbc_wm = *display_wm = *cursor_wm = 0;
4079 return false;
4080 }
4081
d210246a
CW		 4082 crtc = intel_get_crtc_for_plane(dev, plane);
4083 hdisplay = crtc->mode.hdisplay;
4084 htotal = crtc->mode.htotal;
4085 clock = crtc->mode.clock;
4086 pixel_size = crtc->fb->bits_per_pixel / 8;
4087
1398261a
YL		 4088 line_time_us = (htotal * 1000) / clock;
4089 line_count = (latency_ns / line_time_us + 1000) / 1000;
4090 line_size = hdisplay * pixel_size;
4091
4092 /* Use the minimum of the small and large buffer method for primary */
4093 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4094 large = line_count * line_size;
4095
b79d4990
JB		 4096 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4097 *display_wm = entries + display->guard_size;
1398261a
YL		 4098
4099 /*
b79d4990 4100 * Spec says:
1398261a
YL		 4101 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4102 */
4103 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4104
4105 /* calculate the self-refresh watermark for display cursor */
4106 entries = line_count * pixel_size * 64;
b79d4990
JB		 4107 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4108 *cursor_wm = entries + cursor->guard_size;
1398261a 4109
b79d4990
JB		 4110 return ironlake_check_srwm(dev, level,
4111 *fbc_wm, *display_wm, *cursor_wm,
4112 display, cursor);
4113}
4114
d210246a 4115static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4116{
4117 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4118 int fbc_wm, plane_wm, cursor_wm;
4119 unsigned int enabled;
b79d4990
JB		 4120
4121 enabled = 0;
9f405100
CW		 4122 if (g4x_compute_wm0(dev, 0,
4123 &ironlake_display_wm_info,
4124 ILK_LP0_PLANE_LATENCY,
4125 &ironlake_cursor_wm_info,
4126 ILK_LP0_CURSOR_LATENCY,
4127 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4128 I915_WRITE(WM0_PIPEA_ILK,
4129 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4130 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4131 " plane %d, " "cursor: %d\n",
4132 plane_wm, cursor_wm);
d210246a 4133 enabled |= 1;
b79d4990
JB		 4134 }
4135
9f405100
CW		 4136 if (g4x_compute_wm0(dev, 1,
4137 &ironlake_display_wm_info,
4138 ILK_LP0_PLANE_LATENCY,
4139 &ironlake_cursor_wm_info,
4140 ILK_LP0_CURSOR_LATENCY,
4141 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4142 I915_WRITE(WM0_PIPEB_ILK,
4143 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4144 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4145 " plane %d, cursor: %d\n",
4146 plane_wm, cursor_wm);
d210246a 4147 enabled |= 2;
b79d4990
JB		 4148 }
4149
4150 /*
4151 * Calculate and update the self-refresh watermark only when one
4152 * display plane is used.
4153 */
4154 I915_WRITE(WM3_LP_ILK, 0);
4155 I915_WRITE(WM2_LP_ILK, 0);
4156 I915_WRITE(WM1_LP_ILK, 0);
4157
d210246a 4158 if (!single_plane_enabled(enabled))
b79d4990 4159 return;
d210246a 4160 enabled = ffs(enabled) - 1;
b79d4990
JB		 4161
4162 /* WM1 */
d210246a
CW		 4163 if (!ironlake_compute_srwm(dev, 1, enabled,
4164 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4165 &ironlake_display_srwm_info,
4166 &ironlake_cursor_srwm_info,
4167 &fbc_wm, &plane_wm, &cursor_wm))
4168 return;
4169
4170 I915_WRITE(WM1_LP_ILK,
4171 WM1_LP_SR_EN |
4172 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4173 (fbc_wm << WM1_LP_FBC_SHIFT) |
4174 (plane_wm << WM1_LP_SR_SHIFT) |
4175 cursor_wm);
4176
4177 /* WM2 */
d210246a
CW		 4178 if (!ironlake_compute_srwm(dev, 2, enabled,
4179 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4180 &ironlake_display_srwm_info,
4181 &ironlake_cursor_srwm_info,
4182 &fbc_wm, &plane_wm, &cursor_wm))
4183 return;
4184
4185 I915_WRITE(WM2_LP_ILK,
4186 WM2_LP_EN |
4187 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4188 (fbc_wm << WM1_LP_FBC_SHIFT) |
4189 (plane_wm << WM1_LP_SR_SHIFT) |
4190 cursor_wm);
4191
4192 /*
4193 * WM3 is unsupported on ILK, probably because we don't have latency
4194 * data for that power state
4195 */
1398261a
YL		 4196}
4197
d210246a 4198static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4199{
4200 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4201 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4202 int fbc_wm, plane_wm, cursor_wm;
4203 unsigned int enabled;
1398261a
YL		 4204
4205 enabled = 0;
9f405100
CW		 4206 if (g4x_compute_wm0(dev, 0,
4207 &sandybridge_display_wm_info, latency,
4208 &sandybridge_cursor_wm_info, latency,
4209 &plane_wm, &cursor_wm)) {
1398261a
YL		 4210 I915_WRITE(WM0_PIPEA_ILK,
4211 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4212 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4213 " plane %d, " "cursor: %d\n",
4214 plane_wm, cursor_wm);
d210246a 4215 enabled |= 1;
1398261a
YL		 4216 }
4217
9f405100
CW		 4218 if (g4x_compute_wm0(dev, 1,
4219 &sandybridge_display_wm_info, latency,
4220 &sandybridge_cursor_wm_info, latency,
4221 &plane_wm, &cursor_wm)) {
1398261a
YL		 4222 I915_WRITE(WM0_PIPEB_ILK,
4223 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4224 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4225 " plane %d, cursor: %d\n",
4226 plane_wm, cursor_wm);
d210246a 4227 enabled |= 2;
1398261a
YL		 4228 }
4229
4230 /*
4231 * Calculate and update the self-refresh watermark only when one
4232 * display plane is used.
4233 *
4234 * SNB support 3 levels of watermark.
4235 *
4236 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4237 * and disabled in the descending order
4238 *
4239 */
4240 I915_WRITE(WM3_LP_ILK, 0);
4241 I915_WRITE(WM2_LP_ILK, 0);
4242 I915_WRITE(WM1_LP_ILK, 0);
4243
d210246a 4244 if (!single_plane_enabled(enabled))
1398261a 4245 return;
d210246a 4246 enabled = ffs(enabled) - 1;
1398261a
YL		 4247
4248 /* WM1 */
d210246a
CW		 4249 if (!ironlake_compute_srwm(dev, 1, enabled,
4250 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4251 &sandybridge_display_srwm_info,
4252 &sandybridge_cursor_srwm_info,
4253 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4254 return;
4255
4256 I915_WRITE(WM1_LP_ILK,
4257 WM1_LP_SR_EN |
4258 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4259 (fbc_wm << WM1_LP_FBC_SHIFT) |
4260 (plane_wm << WM1_LP_SR_SHIFT) |
4261 cursor_wm);
4262
4263 /* WM2 */
d210246a
CW		 4264 if (!ironlake_compute_srwm(dev, 2, enabled,
4265 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4266 &sandybridge_display_srwm_info,
4267 &sandybridge_cursor_srwm_info,
4268 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4269 return;
4270
4271 I915_WRITE(WM2_LP_ILK,
4272 WM2_LP_EN |
4273 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4274 (fbc_wm << WM1_LP_FBC_SHIFT) |
4275 (plane_wm << WM1_LP_SR_SHIFT) |
4276 cursor_wm);
4277
4278 /* WM3 */
d210246a
CW		 4279 if (!ironlake_compute_srwm(dev, 3, enabled,
4280 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4281 &sandybridge_display_srwm_info,
4282 &sandybridge_cursor_srwm_info,
4283 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4284 return;
4285
4286 I915_WRITE(WM3_LP_ILK,
4287 WM3_LP_EN |
4288 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4289 (fbc_wm << WM1_LP_FBC_SHIFT) |
4290 (plane_wm << WM1_LP_SR_SHIFT) |
4291 cursor_wm);
4292}
4293
7662c8bd
SL		 4294/**
4295 * intel_update_watermarks - update FIFO watermark values based on current modes
4296 *
4297 * Calculate watermark values for the various WM regs based on current mode
4298 * and plane configuration.
4299 *
4300 * There are several cases to deal with here:
4301 * - normal (i.e. non-self-refresh)
4302 * - self-refresh (SR) mode
4303 * - lines are large relative to FIFO size (buffer can hold up to 2)
4304 * - lines are small relative to FIFO size (buffer can hold more than 2
4305 * lines), so need to account for TLB latency
4306 *
4307 * The normal calculation is:
4308 * watermark = dotclock * bytes per pixel * latency
4309 * where latency is platform & configuration dependent (we assume pessimal
4310 * values here).
4311 *
4312 * The SR calculation is:
4313 * watermark = (trunc(latency/line time)+1) * surface width *
4314 * bytes per pixel
4315 * where
4316 * line time = htotal / dotclock
fa143215 4317 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4318 * and latency is assumed to be high, as above.
4319 *
4320 * The final value programmed to the register should always be rounded up,
4321 * and include an extra 2 entries to account for clock crossings.
4322 *
4323 * We don't use the sprite, so we can ignore that. And on Crestline we have
4324 * to set the non-SR watermarks to 8.
5eddb70b 4325 */
7662c8bd
SL		 4326static void intel_update_watermarks(struct drm_device *dev)
4327{
e70236a8 4328 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4329
d210246a
CW		 4330 if (dev_priv->display.update_wm)
4331 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4332}
4333
a7615030
CW		 4334static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4335{
435793df
KP		 4336 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4337 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4338}
4339
f564048e
EA		 4340static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4341 struct drm_display_mode *mode,
4342 struct drm_display_mode *adjusted_mode,
4343 int x, int y,
4344 struct drm_framebuffer *old_fb)
79e53945
JB		 4345{
4346 struct drm_device *dev = crtc->dev;
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4349 int pipe = intel_crtc->pipe;
80824003 4350 int plane = intel_crtc->plane;
c751ce4f 4351 int refclk, num_connectors = 0;
652c393a 4352 intel_clock_t clock, reduced_clock;
5eddb70b 4353 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4354 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4355 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4356 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4357 struct intel_encoder *encoder;
d4906093 4358 const intel_limit_t *limit;
5c3b82e2 4359 int ret;
fae14981 4360 u32 temp;
aa9b500d 4361 u32 lvds_sync = 0;
79e53945 4362
5eddb70b
CW		 4363 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4364 if (encoder->base.crtc != crtc)
79e53945
JB		 4365 continue;
4366
5eddb70b 4367 switch (encoder->type) {
79e53945
JB		 4368 case INTEL_OUTPUT_LVDS:
4369 is_lvds = true;
4370 break;
4371 case INTEL_OUTPUT_SDVO:
7d57382e 4372 case INTEL_OUTPUT_HDMI:
79e53945 4373 is_sdvo = true;
5eddb70b 4374 if (encoder->needs_tv_clock)
e2f0ba97 4375 is_tv = true;
79e53945
JB		 4376 break;
4377 case INTEL_OUTPUT_DVO:
4378 is_dvo = true;
4379 break;
4380 case INTEL_OUTPUT_TVOUT:
4381 is_tv = true;
4382 break;
4383 case INTEL_OUTPUT_ANALOG:
4384 is_crt = true;
4385 break;
a4fc5ed6
KP		 4386 case INTEL_OUTPUT_DISPLAYPORT:
4387 is_dp = true;
4388 break;
79e53945 4389 }
43565a06 4390
c751ce4f 4391 num_connectors++;
79e53945
JB		 4392 }
4393
a7615030 4394 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4395 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4396 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4397 refclk / 1000);
a6c45cf0 4398 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4399 refclk = 96000;
4400 } else {
4401 refclk = 48000;
4402 }
4403
d4906093
ML		 4404 /*
4405 * Returns a set of divisors for the desired target clock with the given
4406 * refclk, or FALSE. The returned values represent the clock equation:
4407 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4408 */
1b894b59 4409 limit = intel_limit(crtc, refclk);
d4906093 4410 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4411 if (!ok) {
4412 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4413 return -EINVAL;
79e53945
JB		 4414 }
4415
cda4b7d3 4416 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4417 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4418
ddc9003c
ZY		 4419 if (is_lvds && dev_priv->lvds_downclock_avail) {
4420 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4421 dev_priv->lvds_downclock,
4422 refclk,
4423 &reduced_clock);
18f9ed12
ZY		 4424 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4425 /*
4426 * If the different P is found, it means that we can't
4427 * switch the display clock by using the FP0/FP1.
4428 * In such case we will disable the LVDS downclock
4429 * feature.
4430 */
4431 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4432 "LVDS clock/downclock\n");
18f9ed12
ZY		 4433 has_reduced_clock = 0;
4434 }
652c393a 4435 }
7026d4ac
ZW		 4436 /* SDVO TV has fixed PLL values depend on its clock range,
4437 this mirrors vbios setting. */
4438 if (is_sdvo && is_tv) {
4439 if (adjusted_mode->clock >= 100000
5eddb70b 4440 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4441 clock.p1 = 2;
4442 clock.p2 = 10;
4443 clock.n = 3;
4444 clock.m1 = 16;
4445 clock.m2 = 8;
4446 } else if (adjusted_mode->clock >= 140500
5eddb70b 4447 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4448 clock.p1 = 1;
4449 clock.p2 = 10;
4450 clock.n = 6;
4451 clock.m1 = 12;
4452 clock.m2 = 8;
4453 }
4454 }
4455
f2b115e6 4456 if (IS_PINEVIEW(dev)) {
2177832f 4457 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4458 if (has_reduced_clock)
4459 fp2 = (1 << reduced_clock.n) << 16 |
4460 reduced_clock.m1 << 8 | reduced_clock.m2;
4461 } else {
2177832f 4462 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4463 if (has_reduced_clock)
4464 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4465 reduced_clock.m2;
4466 }
79e53945 4467
929c77fb 4468 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4469
a6c45cf0 4470 if (!IS_GEN2(dev)) {
79e53945
JB		 4471 if (is_lvds)
4472 dpll |= DPLLB_MODE_LVDS;
4473 else
4474 dpll |= DPLLB_MODE_DAC_SERIAL;
4475 if (is_sdvo) {
6c9547ff
CW		 4476 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4477 if (pixel_multiplier > 1) {
4478 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4479 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4480 }
79e53945 4481 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4482 }
929c77fb 4483 if (is_dp)
a4fc5ed6 4484 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4485
4486 /* compute bitmask from p1 value */
f2b115e6
AJ		 4487 if (IS_PINEVIEW(dev))
4488 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4489 else {
2177832f 4490 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4491 if (IS_G4X(dev) && has_reduced_clock)
4492 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4493 }
79e53945
JB		 4494 switch (clock.p2) {
4495 case 5:
4496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4497 break;
4498 case 7:
4499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4500 break;
4501 case 10:
4502 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4503 break;
4504 case 14:
4505 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4506 break;
4507 }
929c77fb 4508 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4509 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4510 } else {
4511 if (is_lvds) {
4512 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4513 } else {
4514 if (clock.p1 == 2)
4515 dpll |= PLL_P1_DIVIDE_BY_TWO;
4516 else
4517 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4518 if (clock.p2 == 4)
4519 dpll |= PLL_P2_DIVIDE_BY_4;
4520 }
4521 }
4522
43565a06
KH		 4523 if (is_sdvo && is_tv)
4524 dpll |= PLL_REF_INPUT_TVCLKINBC;
4525 else if (is_tv)
79e53945 4526 /* XXX: just matching BIOS for now */
43565a06 4527 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4528 dpll |= 3;
a7615030 4529 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4530 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4531 else
4532 dpll |= PLL_REF_INPUT_DREFCLK;
4533
4534 /* setup pipeconf */
5eddb70b 4535 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4536
4537 /* Set up the display plane register */
4538 dspcntr = DISPPLANE_GAMMA_ENABLE;
4539
f2b115e6 4540 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4541 enable color space conversion */
929c77fb
EA		 4542 if (pipe == 0)
4543 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4544 else
4545 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4546
a6c45cf0 4547 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4548 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4549 * core speed.
4550 *
4551 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4552 * pipe == 0 check?
4553 */
e70236a8
JB		 4554 if (mode->clock >
4555 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4556 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4557 else
5eddb70b 4558 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4559 }
4560
929c77fb 4561 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4562
28c97730 4563 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4564 drm_mode_debug_printmodeline(mode);
4565
fae14981
EA		 4566 I915_WRITE(FP0(pipe), fp);
4567 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4568
fae14981 4569 POSTING_READ(DPLL(pipe));
c713bb08 4570 udelay(150);
8db9d77b 4571
79e53945
JB		 4572 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4573 * This is an exception to the general rule that mode_set doesn't turn
4574 * things on.
4575 */
4576 if (is_lvds) {
fae14981 4577 temp = I915_READ(LVDS);
5eddb70b 4578 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4579 if (pipe == 1) {
929c77fb 4580 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4581 } else {
929c77fb 4582 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4583 }
a3e17eb8 4584 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4585 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4586 /* Set the B0-B3 data pairs corresponding to whether we're going to
4587 * set the DPLLs for dual-channel mode or not.
4588 */
4589 if (clock.p2 == 7)
5eddb70b 4590 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4591 else
5eddb70b 4592 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4593
4594 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4595 * appropriately here, but we need to look more thoroughly into how
4596 * panels behave in the two modes.
4597 */
929c77fb
EA		 4598 /* set the dithering flag on LVDS as needed */
4599 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4600 if (dev_priv->lvds_dither)
5eddb70b 4601 temp |= LVDS_ENABLE_DITHER;
434ed097 4602 else
5eddb70b 4603 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4604 }
aa9b500d
BF		 4605 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4606 lvds_sync |= LVDS_HSYNC_POLARITY;
4607 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4608 lvds_sync |= LVDS_VSYNC_POLARITY;
4609 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4610 != lvds_sync) {
4611 char flags[2] = "-+";
4612 DRM_INFO("Changing LVDS panel from "
4613 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4614 flags[!(temp & LVDS_HSYNC_POLARITY)],
4615 flags[!(temp & LVDS_VSYNC_POLARITY)],
4616 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4617 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4618 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4619 temp |= lvds_sync;
4620 }
fae14981 4621 I915_WRITE(LVDS, temp);
79e53945 4622 }
434ed097 4623
929c77fb 4624 if (is_dp) {
a4fc5ed6 4625 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4626 }
4627
fae14981 4628 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4629
c713bb08 4630 /* Wait for the clocks to stabilize. */
fae14981 4631 POSTING_READ(DPLL(pipe));
c713bb08 4632 udelay(150);
32f9d658 4633
c713bb08
EA		 4634 if (INTEL_INFO(dev)->gen >= 4) {
4635 temp = 0;
4636 if (is_sdvo) {
4637 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4638 if (temp > 1)
4639 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4640 else
4641 temp = 0;
32f9d658 4642 }
c713bb08
EA		 4643 I915_WRITE(DPLL_MD(pipe), temp);
4644 } else {
4645 /* The pixel multiplier can only be updated once the
4646 * DPLL is enabled and the clocks are stable.
4647 *
4648 * So write it again.
4649 */
fae14981 4650 I915_WRITE(DPLL(pipe), dpll);
79e53945 4651 }
79e53945 4652
5eddb70b 4653 intel_crtc->lowfreq_avail = false;
652c393a 4654 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4655 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4656 intel_crtc->lowfreq_avail = true;
4657 if (HAS_PIPE_CXSR(dev)) {
28c97730 4658 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4659 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4660 }
4661 } else {
fae14981 4662 I915_WRITE(FP1(pipe), fp);
652c393a 4663 if (HAS_PIPE_CXSR(dev)) {
28c97730 4664 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4665 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4666 }
4667 }
4668
734b4157
KH		 4669 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4670 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4671 /* the chip adds 2 halflines automatically */
4672 adjusted_mode->crtc_vdisplay -= 1;
4673 adjusted_mode->crtc_vtotal -= 1;
4674 adjusted_mode->crtc_vblank_start -= 1;
4675 adjusted_mode->crtc_vblank_end -= 1;
4676 adjusted_mode->crtc_vsync_end -= 1;
4677 adjusted_mode->crtc_vsync_start -= 1;
4678 } else
4679 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4680
5eddb70b
CW		 4681 I915_WRITE(HTOTAL(pipe),
4682 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4683 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4684 I915_WRITE(HBLANK(pipe),
4685 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4686 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4687 I915_WRITE(HSYNC(pipe),
4688 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4689 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4690
4691 I915_WRITE(VTOTAL(pipe),
4692 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4693 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4694 I915_WRITE(VBLANK(pipe),
4695 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4696 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4697 I915_WRITE(VSYNC(pipe),
4698 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4699 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4700
4701 /* pipesrc and dspsize control the size that is scaled from,
4702 * which should always be the user's requested size.
79e53945 4703 */
929c77fb
EA		 4704 I915_WRITE(DSPSIZE(plane),
4705 ((mode->vdisplay - 1) << 16) |
4706 (mode->hdisplay - 1));
4707 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4708 I915_WRITE(PIPESRC(pipe),
4709 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4710
f564048e
EA		 4711 I915_WRITE(PIPECONF(pipe), pipeconf);
4712 POSTING_READ(PIPECONF(pipe));
929c77fb 4713 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4714
4715 intel_wait_for_vblank(dev, pipe);
4716
f564048e
EA		 4717 I915_WRITE(DSPCNTR(plane), dspcntr);
4718 POSTING_READ(DSPCNTR(plane));
efc2924e 4719 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4720
4721 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4722
4723 intel_update_watermarks(dev);
4724
f564048e
EA		 4725 return ret;
4726}
4727
4728static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4729 struct drm_display_mode *mode,
4730 struct drm_display_mode *adjusted_mode,
4731 int x, int y,
4732 struct drm_framebuffer *old_fb)
79e53945
JB		 4733{
4734 struct drm_device *dev = crtc->dev;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4737 int pipe = intel_crtc->pipe;
80824003 4738 int plane = intel_crtc->plane;
c751ce4f 4739 int refclk, num_connectors = 0;
652c393a 4740 intel_clock_t clock, reduced_clock;
5eddb70b 4741 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4742 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4743 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4744 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4745 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4746 struct intel_encoder *encoder;
d4906093 4747 const intel_limit_t *limit;
5c3b82e2 4748 int ret;
2c07245f 4749 struct fdi_m_n m_n = {0};
fae14981 4750 u32 temp;
aa9b500d 4751 u32 lvds_sync = 0;
8febb297 4752 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4753
5eddb70b
CW		 4754 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4755 if (encoder->base.crtc != crtc)
79e53945
JB		 4756 continue;
4757
5eddb70b 4758 switch (encoder->type) {
79e53945
JB		 4759 case INTEL_OUTPUT_LVDS:
4760 is_lvds = true;
4761 break;
4762 case INTEL_OUTPUT_SDVO:
7d57382e 4763 case INTEL_OUTPUT_HDMI:
79e53945 4764 is_sdvo = true;
5eddb70b 4765 if (encoder->needs_tv_clock)
e2f0ba97 4766 is_tv = true;
79e53945 4767 break;
79e53945
JB		 4768 case INTEL_OUTPUT_TVOUT:
4769 is_tv = true;
4770 break;
4771 case INTEL_OUTPUT_ANALOG:
4772 is_crt = true;
4773 break;
a4fc5ed6
KP		 4774 case INTEL_OUTPUT_DISPLAYPORT:
4775 is_dp = true;
4776 break;
32f9d658 4777 case INTEL_OUTPUT_EDP:
5eddb70b 4778 has_edp_encoder = encoder;
32f9d658 4779 break;
79e53945 4780 }
43565a06 4781
c751ce4f 4782 num_connectors++;
79e53945
JB		 4783 }
4784
a7615030 4785 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4786 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4787 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4788 refclk / 1000);
a07d6787 4789 } else {
79e53945 4790 refclk = 96000;
8febb297
EA		 4791 if (!has_edp_encoder ||
4792 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4793 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4794 }
4795
d4906093
ML		 4796 /*
4797 * Returns a set of divisors for the desired target clock with the given
4798 * refclk, or FALSE. The returned values represent the clock equation:
4799 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4800 */
1b894b59 4801 limit = intel_limit(crtc, refclk);
d4906093 4802 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4803 if (!ok) {
4804 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4805 return -EINVAL;
79e53945
JB		 4806 }
4807
cda4b7d3 4808 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4809 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4810
ddc9003c
ZY		 4811 if (is_lvds && dev_priv->lvds_downclock_avail) {
4812 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4813 dev_priv->lvds_downclock,
4814 refclk,
4815 &reduced_clock);
18f9ed12
ZY		 4816 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4817 /*
4818 * If the different P is found, it means that we can't
4819 * switch the display clock by using the FP0/FP1.
4820 * In such case we will disable the LVDS downclock
4821 * feature.
4822 */
4823 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4824 "LVDS clock/downclock\n");
18f9ed12
ZY		 4825 has_reduced_clock = 0;
4826 }
652c393a 4827 }
7026d4ac
ZW		 4828 /* SDVO TV has fixed PLL values depend on its clock range,
4829 this mirrors vbios setting. */
4830 if (is_sdvo && is_tv) {
4831 if (adjusted_mode->clock >= 100000
5eddb70b 4832 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4833 clock.p1 = 2;
4834 clock.p2 = 10;
4835 clock.n = 3;
4836 clock.m1 = 16;
4837 clock.m2 = 8;
4838 } else if (adjusted_mode->clock >= 140500
5eddb70b 4839 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4840 clock.p1 = 1;
4841 clock.p2 = 10;
4842 clock.n = 6;
4843 clock.m1 = 12;
4844 clock.m2 = 8;
4845 }
4846 }
4847
2c07245f 4848 /* FDI link */
8febb297
EA		 4849 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4850 lane = 0;
4851 /* CPU eDP doesn't require FDI link, so just set DP M/N
4852 according to current link config */
4853 if (has_edp_encoder &&
4854 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4855 target_clock = mode->clock;
4856 intel_edp_link_config(has_edp_encoder,
4857 &lane, &link_bw);
4858 } else {
4859 /* [e]DP over FDI requires target mode clock
4860 instead of link clock */
4861 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4862 target_clock = mode->clock;
8febb297
EA		 4863 else
4864 target_clock = adjusted_mode->clock;
4865
4866 /* FDI is a binary signal running at ~2.7GHz, encoding
4867 * each output octet as 10 bits. The actual frequency
4868 * is stored as a divider into a 100MHz clock, and the
4869 * mode pixel clock is stored in units of 1KHz.
4870 * Hence the bw of each lane in terms of the mode signal
4871 * is:
4872 */
4873 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4874 }
58a27471 4875
8febb297
EA		 4876 /* determine panel color depth */
4877 temp = I915_READ(PIPECONF(pipe));
4878 temp &= ~PIPE_BPC_MASK;
4879 if (is_lvds) {
4880 /* the BPC will be 6 if it is 18-bit LVDS panel */
4881 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4882 temp |= PIPE_8BPC;
4883 else
4884 temp |= PIPE_6BPC;
4885 } else if (has_edp_encoder) {
4886 switch (dev_priv->edp.bpp/3) {
4887 case 8:
e5a95eb7 4888 temp |= PIPE_8BPC;
58a27471 4889 break;
8febb297
EA		 4890 case 10:
4891 temp |= PIPE_10BPC;
58a27471 4892 break;
8febb297
EA		 4893 case 6:
4894 temp |= PIPE_6BPC;
58a27471 4895 break;
8febb297
EA		 4896 case 12:
4897 temp |= PIPE_12BPC;
58a27471 4898 break;
77ffb597 4899 }
8febb297
EA		 4900 } else
4901 temp |= PIPE_8BPC;
4902 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4903
8febb297
EA		 4904 switch (temp & PIPE_BPC_MASK) {
4905 case PIPE_8BPC:
4906 bpp = 24;
4907 break;
4908 case PIPE_10BPC:
4909 bpp = 30;
4910 break;
4911 case PIPE_6BPC:
4912 bpp = 18;
4913 break;
4914 case PIPE_12BPC:
4915 bpp = 36;
4916 break;
4917 default:
4918 DRM_ERROR("unknown pipe bpc value\n");
4919 bpp = 24;
4920 }
77ffb597 4921
8febb297
EA		 4922 if (!lane) {
4923 /*
4924 * Account for spread spectrum to avoid
4925 * oversubscribing the link. Max center spread
4926 * is 2.5%; use 5% for safety's sake.
4927 */
4928 u32 bps = target_clock * bpp * 21 / 20;
4929 lane = bps / (link_bw * 8) + 1;
5eb08b69 4930 }
2c07245f 4931
8febb297
EA		 4932 intel_crtc->fdi_lanes = lane;
4933
4934 if (pixel_multiplier > 1)
4935 link_bw *= pixel_multiplier;
4936 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4937
c038e51e
ZW		 4938 /* Ironlake: try to setup display ref clock before DPLL
4939 * enabling. This is only under driver's control after
4940 * PCH B stepping, previous chipset stepping should be
4941 * ignoring this setting.
4942 */
8febb297
EA		 4943 temp = I915_READ(PCH_DREF_CONTROL);
4944 /* Always enable nonspread source */
4945 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4946 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4947 temp &= ~DREF_SSC_SOURCE_MASK;
4948 temp |= DREF_SSC_SOURCE_ENABLE;
4949 I915_WRITE(PCH_DREF_CONTROL, temp);
4950
4951 POSTING_READ(PCH_DREF_CONTROL);
4952 udelay(200);
fc9a2228 4953
8febb297
EA		 4954 if (has_edp_encoder) {
4955 if (intel_panel_use_ssc(dev_priv)) {
4956 temp |= DREF_SSC1_ENABLE;
fc9a2228 4957 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4958
fc9a2228
CW		 4959 POSTING_READ(PCH_DREF_CONTROL);
4960 udelay(200);
4961 }
8febb297
EA		 4962 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4963
4964 /* Enable CPU source on CPU attached eDP */
4965 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4966 if (intel_panel_use_ssc(dev_priv))
4967 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4968 else
4969 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4970 } else {
4971 /* Enable SSC on PCH eDP if needed */
4972 if (intel_panel_use_ssc(dev_priv)) {
4973 DRM_ERROR("enabling SSC on PCH\n");
4974 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4975 }
4976 }
4977 I915_WRITE(PCH_DREF_CONTROL, temp);
4978 POSTING_READ(PCH_DREF_CONTROL);
4979 udelay(200);
fc9a2228 4980 }
c038e51e 4981
a07d6787
EA		 4982 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4983 if (has_reduced_clock)
4984 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4985 reduced_clock.m2;
79e53945 4986
c1858123 4987 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4988 factor = 21;
4989 if (is_lvds) {
4990 if ((intel_panel_use_ssc(dev_priv) &&
4991 dev_priv->lvds_ssc_freq == 100) ||
4992 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4993 factor = 25;
4994 } else if (is_sdvo && is_tv)
4995 factor = 20;
c1858123 4996
8febb297
EA		 4997 if (clock.m1 < factor * clock.n)
4998 fp |= FP_CB_TUNE;
2c07245f 4999
5eddb70b 5000 dpll = 0;
2c07245f 5001
a07d6787
EA		 5002 if (is_lvds)
5003 dpll |= DPLLB_MODE_LVDS;
5004 else
5005 dpll |= DPLLB_MODE_DAC_SERIAL;
5006 if (is_sdvo) {
5007 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5008 if (pixel_multiplier > 1) {
5009 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5010 }
a07d6787
EA		 5011 dpll |= DPLL_DVO_HIGH_SPEED;
5012 }
5013 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5014 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5015
a07d6787
EA		 5016 /* compute bitmask from p1 value */
5017 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5018 /* also FPA1 */
5019 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5020
5021 switch (clock.p2) {
5022 case 5:
5023 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5024 break;
5025 case 7:
5026 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5027 break;
5028 case 10:
5029 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5030 break;
5031 case 14:
5032 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5033 break;
79e53945
JB		 5034 }
5035
43565a06
KH		 5036 if (is_sdvo && is_tv)
5037 dpll |= PLL_REF_INPUT_TVCLKINBC;
5038 else if (is_tv)
79e53945 5039 /* XXX: just matching BIOS for now */
43565a06 5040 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5041 dpll |= 3;
a7615030 5042 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5043 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5044 else
5045 dpll |= PLL_REF_INPUT_DREFCLK;
5046
5047 /* setup pipeconf */
5eddb70b 5048 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5049
5050 /* Set up the display plane register */
5051 dspcntr = DISPPLANE_GAMMA_ENABLE;
5052
28c97730 5053 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5054 drm_mode_debug_printmodeline(mode);
5055
5c5313c8
JB		 5056 /* PCH eDP needs FDI, but CPU eDP does not */
5057 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5058 I915_WRITE(PCH_FP0(pipe), fp);
5059 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5060
fae14981 5061 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5062 udelay(150);
5063 }
5064
8db9d77b
ZW		 5065 /* enable transcoder DPLL */
5066 if (HAS_PCH_CPT(dev)) {
5067 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5068 switch (pipe) {
5069 case 0:
5eddb70b 5070 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5071 break;
5072 case 1:
5eddb70b 5073 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5074 break;
5075 case 2:
5076 /* FIXME: manage transcoder PLLs? */
5077 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5078 break;
5079 default:
5080 BUG();
32f9d658 5081 }
8db9d77b 5082 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5083
5084 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5085 udelay(150);
5086 }
5087
79e53945
JB		 5088 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5089 * This is an exception to the general rule that mode_set doesn't turn
5090 * things on.
5091 */
5092 if (is_lvds) {
fae14981 5093 temp = I915_READ(PCH_LVDS);
5eddb70b 5094 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5095 if (pipe == 1) {
5096 if (HAS_PCH_CPT(dev))
5eddb70b 5097 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5098 else
5eddb70b 5099 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5100 } else {
5101 if (HAS_PCH_CPT(dev))
5eddb70b 5102 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5103 else
5eddb70b 5104 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5105 }
a3e17eb8 5106 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5107 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5108 /* Set the B0-B3 data pairs corresponding to whether we're going to
5109 * set the DPLLs for dual-channel mode or not.
5110 */
5111 if (clock.p2 == 7)
5eddb70b 5112 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5113 else
5eddb70b 5114 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5115
5116 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5117 * appropriately here, but we need to look more thoroughly into how
5118 * panels behave in the two modes.
5119 */
aa9b500d
BF		 5120 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5121 lvds_sync |= LVDS_HSYNC_POLARITY;
5122 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5123 lvds_sync |= LVDS_VSYNC_POLARITY;
5124 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5125 != lvds_sync) {
5126 char flags[2] = "-+";
5127 DRM_INFO("Changing LVDS panel from "
5128 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5129 flags[!(temp & LVDS_HSYNC_POLARITY)],
5130 flags[!(temp & LVDS_VSYNC_POLARITY)],
5131 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5132 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5133 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5134 temp |= lvds_sync;
5135 }
fae14981 5136 I915_WRITE(PCH_LVDS, temp);
79e53945 5137 }
434ed097
JB		 5138
5139 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5140 pipeconf &= ~PIPECONF_DITHER_EN;
5141 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5142 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5143 pipeconf |= PIPECONF_DITHER_EN;
5144 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5145 }
5146
5c5313c8 5147 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5148 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5149 } else {
8db9d77b 5150 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5151 I915_WRITE(TRANSDATA_M1(pipe), 0);
5152 I915_WRITE(TRANSDATA_N1(pipe), 0);
5153 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5154 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5155 }
79e53945 5156
8febb297
EA		 5157 if (!has_edp_encoder ||
5158 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5159 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5160
32f9d658 5161 /* Wait for the clocks to stabilize. */
fae14981 5162 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5163 udelay(150);
5164
8febb297
EA		 5165 /* The pixel multiplier can only be updated once the
5166 * DPLL is enabled and the clocks are stable.
5167 *
5168 * So write it again.
5169 */
fae14981 5170 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5171 }
79e53945 5172
5eddb70b 5173 intel_crtc->lowfreq_avail = false;
652c393a 5174 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5175 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5176 intel_crtc->lowfreq_avail = true;
5177 if (HAS_PIPE_CXSR(dev)) {
28c97730 5178 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5179 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5180 }
5181 } else {
fae14981 5182 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5183 if (HAS_PIPE_CXSR(dev)) {
28c97730 5184 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5185 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5186 }
5187 }
5188
734b4157
KH		 5189 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5190 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5191 /* the chip adds 2 halflines automatically */
5192 adjusted_mode->crtc_vdisplay -= 1;
5193 adjusted_mode->crtc_vtotal -= 1;
5194 adjusted_mode->crtc_vblank_start -= 1;
5195 adjusted_mode->crtc_vblank_end -= 1;
5196 adjusted_mode->crtc_vsync_end -= 1;
5197 adjusted_mode->crtc_vsync_start -= 1;
5198 } else
5199 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5200
5eddb70b
CW		 5201 I915_WRITE(HTOTAL(pipe),
5202 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5203 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5204 I915_WRITE(HBLANK(pipe),
5205 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5206 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5207 I915_WRITE(HSYNC(pipe),
5208 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5209 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5210
5211 I915_WRITE(VTOTAL(pipe),
5212 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5213 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5214 I915_WRITE(VBLANK(pipe),
5215 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5216 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5217 I915_WRITE(VSYNC(pipe),
5218 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5219 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5220
8febb297
EA		 5221 /* pipesrc controls the size that is scaled from, which should
5222 * always be the user's requested size.
79e53945 5223 */
5eddb70b
CW		 5224 I915_WRITE(PIPESRC(pipe),
5225 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5226
8febb297
EA		 5227 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5228 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5229 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5230 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5231
8febb297
EA		 5232 if (has_edp_encoder &&
5233 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5234 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5235 }
5236
5eddb70b
CW		 5237 I915_WRITE(PIPECONF(pipe), pipeconf);
5238 POSTING_READ(PIPECONF(pipe));
79e53945 5239
9d0498a2 5240 intel_wait_for_vblank(dev, pipe);
79e53945 5241
f00a3ddf 5242 if (IS_GEN5(dev)) {
553bd149
ZW		 5243 /* enable address swizzle for tiling buffer */
5244 temp = I915_READ(DISP_ARB_CTL);
5245 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5246 }
5247
5eddb70b 5248 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5249 POSTING_READ(DSPCNTR(plane));
79e53945 5250
5c3b82e2 5251 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5252
5253 intel_update_watermarks(dev);
5254
1f803ee5 5255 return ret;
79e53945
JB		 5256}
5257
f564048e
EA		 5258static int intel_crtc_mode_set(struct drm_crtc *crtc,
5259 struct drm_display_mode *mode,
5260 struct drm_display_mode *adjusted_mode,
5261 int x, int y,
5262 struct drm_framebuffer *old_fb)
5263{
5264 struct drm_device *dev = crtc->dev;
5265 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5267 int pipe = intel_crtc->pipe;
f564048e
EA		 5268 int ret;
5269
0b701d27 5270 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5271
f564048e
EA		 5272 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5273 x, y, old_fb);
7662c8bd 5274
79e53945 5275 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5276
120eced9
KP		 5277 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5278
1f803ee5 5279 return ret;
79e53945
JB		 5280}
5281
5282/** Loads the palette/gamma unit for the CRTC with the prepared values */
5283void intel_crtc_load_lut(struct drm_crtc *crtc)
5284{
5285 struct drm_device *dev = crtc->dev;
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5288 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5289 int i;
5290
5291 /* The clocks have to be on to load the palette. */
5292 if (!crtc->enabled)
5293 return;
5294
f2b115e6 5295 /* use legacy palette for Ironlake */
bad720ff 5296 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5297 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5298
79e53945
JB		 5299 for (i = 0; i < 256; i++) {
5300 I915_WRITE(palreg + 4 * i,
5301 (intel_crtc->lut_r[i] << 16) |
5302 (intel_crtc->lut_g[i] << 8) |
5303 intel_crtc->lut_b[i]);
5304 }
5305}
5306
560b85bb
CW		 5307static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5308{
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312 bool visible = base != 0;
5313 u32 cntl;
5314
5315 if (intel_crtc->cursor_visible == visible)
5316 return;
5317
9db4a9c7 5318 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5319 if (visible) {
5320 /* On these chipsets we can only modify the base whilst
5321 * the cursor is disabled.
5322 */
9db4a9c7 5323 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5324
5325 cntl &= ~(CURSOR_FORMAT_MASK);
5326 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5327 cntl |= CURSOR_ENABLE |
5328 CURSOR_GAMMA_ENABLE |
5329 CURSOR_FORMAT_ARGB;
5330 } else
5331 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5332 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5333
5334 intel_crtc->cursor_visible = visible;
5335}
5336
5337static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5338{
5339 struct drm_device *dev = crtc->dev;
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5342 int pipe = intel_crtc->pipe;
5343 bool visible = base != 0;
5344
5345 if (intel_crtc->cursor_visible != visible) {
548f245b 5346 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5347 if (base) {
5348 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5349 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5350 cntl |= pipe << 28; /* Connect to correct pipe */
5351 } else {
5352 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5353 cntl |= CURSOR_MODE_DISABLE;
5354 }
9db4a9c7 5355 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5356
5357 intel_crtc->cursor_visible = visible;
5358 }
5359 /* and commit changes on next vblank */
9db4a9c7 5360 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5361}
5362
cda4b7d3 5363/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5364static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5365 bool on)
cda4b7d3
CW		 5366{
5367 struct drm_device *dev = crtc->dev;
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5370 int pipe = intel_crtc->pipe;
5371 int x = intel_crtc->cursor_x;
5372 int y = intel_crtc->cursor_y;
560b85bb 5373 u32 base, pos;
cda4b7d3
CW		 5374 bool visible;
5375
5376 pos = 0;
5377
6b383a7f 5378 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5379 base = intel_crtc->cursor_addr;
5380 if (x > (int) crtc->fb->width)
5381 base = 0;
5382
5383 if (y > (int) crtc->fb->height)
5384 base = 0;
5385 } else
5386 base = 0;
5387
5388 if (x < 0) {
5389 if (x + intel_crtc->cursor_width < 0)
5390 base = 0;
5391
5392 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5393 x = -x;
5394 }
5395 pos |= x << CURSOR_X_SHIFT;
5396
5397 if (y < 0) {
5398 if (y + intel_crtc->cursor_height < 0)
5399 base = 0;
5400
5401 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5402 y = -y;
5403 }
5404 pos |= y << CURSOR_Y_SHIFT;
5405
5406 visible = base != 0;
560b85bb 5407 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5408 return;
5409
9db4a9c7 5410 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5411 if (IS_845G(dev) || IS_I865G(dev))
5412 i845_update_cursor(crtc, base);
5413 else
5414 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5415
5416 if (visible)
5417 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5418}
5419
79e53945 5420static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5421 struct drm_file *file,
79e53945
JB		 5422 uint32_t handle,
5423 uint32_t width, uint32_t height)
5424{
5425 struct drm_device *dev = crtc->dev;
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5428 struct drm_i915_gem_object *obj;
cda4b7d3 5429 uint32_t addr;
3f8bc370 5430 int ret;
79e53945 5431
28c97730 5432 DRM_DEBUG_KMS("\n");
79e53945
JB		 5433
5434 /* if we want to turn off the cursor ignore width and height */
5435 if (!handle) {
28c97730 5436 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5437 addr = 0;
05394f39 5438 obj = NULL;
5004417d 5439 mutex_lock(&dev->struct_mutex);
3f8bc370 5440 goto finish;
79e53945
JB		 5441 }
5442
5443 /* Currently we only support 64x64 cursors */
5444 if (width != 64 || height != 64) {
5445 DRM_ERROR("we currently only support 64x64 cursors\n");
5446 return -EINVAL;
5447 }
5448
05394f39 5449 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5450 if (&obj->base == NULL)
79e53945
JB		 5451 return -ENOENT;
5452
05394f39 5453 if (obj->base.size < width * height * 4) {
79e53945 5454 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5455 ret = -ENOMEM;
5456 goto fail;
79e53945
JB		 5457 }
5458
71acb5eb 5459 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5460 mutex_lock(&dev->struct_mutex);
b295d1b6 5461 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5462 if (obj->tiling_mode) {
5463 DRM_ERROR("cursor cannot be tiled\n");
5464 ret = -EINVAL;
5465 goto fail_locked;
5466 }
5467
05394f39 5468 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA		 5469 if (ret) {
5470 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 5471 goto fail_locked;
71acb5eb 5472 }
e7b526bb 5473
05394f39 5474 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW		 5475 if (ret) {
5476 DRM_ERROR("failed to move cursor bo into the GTT\n");
5477 goto fail_unpin;
5478 }
5479
d9e86c0e
CW		 5480 ret = i915_gem_object_put_fence(obj);
5481 if (ret) {
5482 DRM_ERROR("failed to move cursor bo into the GTT\n");
5483 goto fail_unpin;
5484 }
5485
05394f39 5486 addr = obj->gtt_offset;
71acb5eb 5487 } else {
6eeefaf3 5488 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5489 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5490 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5491 align);
71acb5eb
DA		 5492 if (ret) {
5493 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5494 goto fail_locked;
71acb5eb 5495 }
05394f39 5496 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5497 }
5498
a6c45cf0 5499 if (IS_GEN2(dev))
14b60391
JB		 5500 I915_WRITE(CURSIZE, (height << 12) | width);
5501
3f8bc370 5502 finish:
3f8bc370 5503 if (intel_crtc->cursor_bo) {
b295d1b6 5504 if (dev_priv->info->cursor_needs_physical) {
05394f39 5505 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5506 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5507 } else
5508 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5509 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5510 }
80824003 5511
7f9872e0 5512 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5513
5514 intel_crtc->cursor_addr = addr;
05394f39 5515 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5516 intel_crtc->cursor_width = width;
5517 intel_crtc->cursor_height = height;
5518
6b383a7f 5519 intel_crtc_update_cursor(crtc, true);
3f8bc370 5520
79e53945 5521 return 0;
e7b526bb 5522fail_unpin:
05394f39 5523 i915_gem_object_unpin(obj);
7f9872e0 5524fail_locked:
34b8686e 5525 mutex_unlock(&dev->struct_mutex);
bc9025bd 5526fail:
05394f39 5527 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5528 return ret;
79e53945
JB		 5529}
5530
5531static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5532{
79e53945 5533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5534
cda4b7d3
CW		 5535 intel_crtc->cursor_x = x;
5536 intel_crtc->cursor_y = y;
652c393a 5537
6b383a7f 5538 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5539
5540 return 0;
5541}
5542
5543/** Sets the color ramps on behalf of RandR */
5544void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5545 u16 blue, int regno)
5546{
5547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5548
5549 intel_crtc->lut_r[regno] = red >> 8;
5550 intel_crtc->lut_g[regno] = green >> 8;
5551 intel_crtc->lut_b[regno] = blue >> 8;
5552}
5553
b8c00ac5
DA		 5554void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5555 u16 *blue, int regno)
5556{
5557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558
5559 *red = intel_crtc->lut_r[regno] << 8;
5560 *green = intel_crtc->lut_g[regno] << 8;
5561 *blue = intel_crtc->lut_b[regno] << 8;
5562}
5563
79e53945 5564static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5565 u16 *blue, uint32_t start, uint32_t size)
79e53945 5566{
7203425a 5567 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5569
7203425a 5570 for (i = start; i < end; i++) {
79e53945
JB		 5571 intel_crtc->lut_r[i] = red[i] >> 8;
5572 intel_crtc->lut_g[i] = green[i] >> 8;
5573 intel_crtc->lut_b[i] = blue[i] >> 8;
5574 }
5575
5576 intel_crtc_load_lut(crtc);
5577}
5578
5579/**
5580 * Get a pipe with a simple mode set on it for doing load-based monitor
5581 * detection.
5582 *
5583 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5584 * its requirements. The pipe will be connected to no other encoders.
79e53945 5585 *
c751ce4f 5586 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5587 * configured for it. In the future, it could choose to temporarily disable
5588 * some outputs to free up a pipe for its use.
5589 *
5590 * \return crtc, or NULL if no pipes are available.
5591 */
5592
5593/* VESA 640x480x72Hz mode to set on the pipe */
5594static struct drm_display_mode load_detect_mode = {
5595 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5596 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5597};
5598
d2dff872
CW		 5599static struct drm_framebuffer *
5600intel_framebuffer_create(struct drm_device *dev,
5601 struct drm_mode_fb_cmd *mode_cmd,
5602 struct drm_i915_gem_object *obj)
5603{
5604 struct intel_framebuffer *intel_fb;
5605 int ret;
5606
5607 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5608 if (!intel_fb) {
5609 drm_gem_object_unreference_unlocked(&obj->base);
5610 return ERR_PTR(-ENOMEM);
5611 }
5612
5613 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5614 if (ret) {
5615 drm_gem_object_unreference_unlocked(&obj->base);
5616 kfree(intel_fb);
5617 return ERR_PTR(ret);
5618 }
5619
5620 return &intel_fb->base;
5621}
5622
5623static u32
5624intel_framebuffer_pitch_for_width(int width, int bpp)
5625{
5626 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5627 return ALIGN(pitch, 64);
5628}
5629
5630static u32
5631intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5632{
5633 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5634 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5635}
5636
5637static struct drm_framebuffer *
5638intel_framebuffer_create_for_mode(struct drm_device *dev,
5639 struct drm_display_mode *mode,
5640 int depth, int bpp)
5641{
5642 struct drm_i915_gem_object *obj;
5643 struct drm_mode_fb_cmd mode_cmd;
5644
5645 obj = i915_gem_alloc_object(dev,
5646 intel_framebuffer_size_for_mode(mode, bpp));
5647 if (obj == NULL)
5648 return ERR_PTR(-ENOMEM);
5649
5650 mode_cmd.width = mode->hdisplay;
5651 mode_cmd.height = mode->vdisplay;
5652 mode_cmd.depth = depth;
5653 mode_cmd.bpp = bpp;
5654 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5655
5656 return intel_framebuffer_create(dev, &mode_cmd, obj);
5657}
5658
5659static struct drm_framebuffer *
5660mode_fits_in_fbdev(struct drm_device *dev,
5661 struct drm_display_mode *mode)
5662{
5663 struct drm_i915_private *dev_priv = dev->dev_private;
5664 struct drm_i915_gem_object *obj;
5665 struct drm_framebuffer *fb;
5666
5667 if (dev_priv->fbdev == NULL)
5668 return NULL;
5669
5670 obj = dev_priv->fbdev->ifb.obj;
5671 if (obj == NULL)
5672 return NULL;
5673
5674 fb = &dev_priv->fbdev->ifb.base;
5675 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5676 fb->bits_per_pixel))
5677 return NULL;
5678
5679 if (obj->base.size < mode->vdisplay * fb->pitch)
5680 return NULL;
5681
5682 return fb;
5683}
5684
7173188d
CW		 5685bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5686 struct drm_connector *connector,
5687 struct drm_display_mode *mode,
8261b191 5688 struct intel_load_detect_pipe *old)
79e53945
JB		 5689{
5690 struct intel_crtc *intel_crtc;
5691 struct drm_crtc *possible_crtc;
4ef69c7a 5692 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5693 struct drm_crtc *crtc = NULL;
5694 struct drm_device *dev = encoder->dev;
d2dff872 5695 struct drm_framebuffer *old_fb;
79e53945
JB		 5696 int i = -1;
5697
d2dff872
CW		 5698 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5699 connector->base.id, drm_get_connector_name(connector),
5700 encoder->base.id, drm_get_encoder_name(encoder));
5701
79e53945
JB		 5702 /*
5703 * Algorithm gets a little messy:
7a5e4805 5704 *
79e53945
JB		 5705 * - if the connector already has an assigned crtc, use it (but make
5706 * sure it's on first)
7a5e4805 5707 *
79e53945
JB		 5708 * - try to find the first unused crtc that can drive this connector,
5709 * and use that if we find one
79e53945
JB		 5710 */
5711
5712 /* See if we already have a CRTC for this connector */
5713 if (encoder->crtc) {
5714 crtc = encoder->crtc;
8261b191 5715
79e53945 5716 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5717 old->dpms_mode = intel_crtc->dpms_mode;
5718 old->load_detect_temp = false;
5719
5720 /* Make sure the crtc and connector are running */
79e53945 5721 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5722 struct drm_encoder_helper_funcs *encoder_funcs;
5723 struct drm_crtc_helper_funcs *crtc_funcs;
5724
79e53945
JB		 5725 crtc_funcs = crtc->helper_private;
5726 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5727
5728 encoder_funcs = encoder->helper_private;
79e53945
JB		 5729 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5730 }
8261b191 5731
7173188d 5732 return true;
79e53945
JB		 5733 }
5734
5735 /* Find an unused one (if possible) */
5736 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5737 i++;
5738 if (!(encoder->possible_crtcs & (1 << i)))
5739 continue;
5740 if (!possible_crtc->enabled) {
5741 crtc = possible_crtc;
5742 break;
5743 }
79e53945
JB		 5744 }
5745
5746 /*
5747 * If we didn't find an unused CRTC, don't use any.
5748 */
5749 if (!crtc) {
7173188d
CW		 5750 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5751 return false;
79e53945
JB		 5752 }
5753
5754 encoder->crtc = crtc;
c1c43977 5755 connector->encoder = encoder;
79e53945
JB		 5756
5757 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5758 old->dpms_mode = intel_crtc->dpms_mode;
5759 old->load_detect_temp = true;
d2dff872 5760 old->release_fb = NULL;
79e53945 5761
6492711d
CW		 5762 if (!mode)
5763 mode = &load_detect_mode;
79e53945 5764
d2dff872
CW		 5765 old_fb = crtc->fb;
5766
5767 /* We need a framebuffer large enough to accommodate all accesses
5768 * that the plane may generate whilst we perform load detection.
5769 * We can not rely on the fbcon either being present (we get called
5770 * during its initialisation to detect all boot displays, or it may
5771 * not even exist) or that it is large enough to satisfy the
5772 * requested mode.
5773 */
5774 crtc->fb = mode_fits_in_fbdev(dev, mode);
5775 if (crtc->fb == NULL) {
5776 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5777 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5778 old->release_fb = crtc->fb;
5779 } else
5780 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5781 if (IS_ERR(crtc->fb)) {
5782 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5783 crtc->fb = old_fb;
5784 return false;
79e53945 5785 }
79e53945 5786
d2dff872 5787 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5788 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5789 if (old->release_fb)
5790 old->release_fb->funcs->destroy(old->release_fb);
5791 crtc->fb = old_fb;
6492711d 5792 return false;
79e53945 5793 }
7173188d 5794
79e53945 5795 /* let the connector get through one full cycle before testing */
9d0498a2 5796 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5797
7173188d 5798 return true;
79e53945
JB		 5799}
5800
c1c43977 5801void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5802 struct drm_connector *connector,
5803 struct intel_load_detect_pipe *old)
79e53945 5804{
4ef69c7a 5805 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5806 struct drm_device *dev = encoder->dev;
5807 struct drm_crtc *crtc = encoder->crtc;
5808 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5809 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5810
d2dff872
CW		 5811 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5812 connector->base.id, drm_get_connector_name(connector),
5813 encoder->base.id, drm_get_encoder_name(encoder));
5814
8261b191 5815 if (old->load_detect_temp) {
c1c43977 5816 connector->encoder = NULL;
79e53945 5817 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5818
5819 if (old->release_fb)
5820 old->release_fb->funcs->destroy(old->release_fb);
5821
0622a53c 5822 return;
79e53945
JB		 5823 }
5824
c751ce4f 5825 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5826 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5827 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5828 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5829 }
5830}
5831
5832/* Returns the clock of the currently programmed mode of the given pipe. */
5833static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5834{
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837 int pipe = intel_crtc->pipe;
548f245b 5838 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5839 u32 fp;
5840 intel_clock_t clock;
5841
5842 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5843 fp = I915_READ(FP0(pipe));
79e53945 5844 else
39adb7a5 5845 fp = I915_READ(FP1(pipe));
79e53945
JB		 5846
5847 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5848 if (IS_PINEVIEW(dev)) {
5849 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5850 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5851 } else {
5852 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5853 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5854 }
5855
a6c45cf0 5856 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5857 if (IS_PINEVIEW(dev))
5858 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5859 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5860 else
5861 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5862 DPLL_FPA01_P1_POST_DIV_SHIFT);
5863
5864 switch (dpll & DPLL_MODE_MASK) {
5865 case DPLLB_MODE_DAC_SERIAL:
5866 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5867 5 : 10;
5868 break;
5869 case DPLLB_MODE_LVDS:
5870 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5871 7 : 14;
5872 break;
5873 default:
28c97730 5874 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5875 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5876 return 0;
5877 }
5878
5879 /* XXX: Handle the 100Mhz refclk */
2177832f 5880 intel_clock(dev, 96000, &clock);
79e53945
JB		 5881 } else {
5882 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5883
5884 if (is_lvds) {
5885 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5886 DPLL_FPA01_P1_POST_DIV_SHIFT);
5887 clock.p2 = 14;
5888
5889 if ((dpll & PLL_REF_INPUT_MASK) ==
5890 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5891 /* XXX: might not be 66MHz */
2177832f 5892 intel_clock(dev, 66000, &clock);
79e53945 5893 } else
2177832f 5894 intel_clock(dev, 48000, &clock);
79e53945
JB		 5895 } else {
5896 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5897 clock.p1 = 2;
5898 else {
5899 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5900 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5901 }
5902 if (dpll & PLL_P2_DIVIDE_BY_4)
5903 clock.p2 = 4;
5904 else
5905 clock.p2 = 2;
5906
2177832f 5907 intel_clock(dev, 48000, &clock);
79e53945
JB		 5908 }
5909 }
5910
5911 /* XXX: It would be nice to validate the clocks, but we can't reuse
5912 * i830PllIsValid() because it relies on the xf86_config connector
5913 * configuration being accurate, which it isn't necessarily.
5914 */
5915
5916 return clock.dot;
5917}
5918
5919/** Returns the currently programmed mode of the given pipe. */
5920struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5921 struct drm_crtc *crtc)
5922{
548f245b 5923 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925 int pipe = intel_crtc->pipe;
5926 struct drm_display_mode *mode;
548f245b
JB		 5927 int htot = I915_READ(HTOTAL(pipe));
5928 int hsync = I915_READ(HSYNC(pipe));
5929 int vtot = I915_READ(VTOTAL(pipe));
5930 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5931
5932 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5933 if (!mode)
5934 return NULL;
5935
5936 mode->clock = intel_crtc_clock_get(dev, crtc);
5937 mode->hdisplay = (htot & 0xffff) + 1;
5938 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5939 mode->hsync_start = (hsync & 0xffff) + 1;
5940 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5941 mode->vdisplay = (vtot & 0xffff) + 1;
5942 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5943 mode->vsync_start = (vsync & 0xffff) + 1;
5944 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5945
5946 drm_mode_set_name(mode);
5947 drm_mode_set_crtcinfo(mode, 0);
5948
5949 return mode;
5950}
5951
652c393a
JB		 5952#define GPU_IDLE_TIMEOUT 500 /* ms */
5953
5954/* When this timer fires, we've been idle for awhile */
5955static void intel_gpu_idle_timer(unsigned long arg)
5956{
5957 struct drm_device *dev = (struct drm_device *)arg;
5958 drm_i915_private_t *dev_priv = dev->dev_private;
5959
ff7ea4c0
CW		 5960 if (!list_empty(&dev_priv->mm.active_list)) {
5961 /* Still processing requests, so just re-arm the timer. */
5962 mod_timer(&dev_priv->idle_timer, jiffies +
5963 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5964 return;
5965 }
652c393a 5966
ff7ea4c0 5967 dev_priv->busy = false;
01dfba93 5968 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5969}
5970
652c393a
JB		 5971#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5972
5973static void intel_crtc_idle_timer(unsigned long arg)
5974{
5975 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5976 struct drm_crtc *crtc = &intel_crtc->base;
5977 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5978 struct intel_framebuffer *intel_fb;
652c393a 5979
ff7ea4c0
CW		 5980 intel_fb = to_intel_framebuffer(crtc->fb);
5981 if (intel_fb && intel_fb->obj->active) {
5982 /* The framebuffer is still being accessed by the GPU. */
5983 mod_timer(&intel_crtc->idle_timer, jiffies +
5984 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5985 return;
5986 }
652c393a 5987
ff7ea4c0 5988 intel_crtc->busy = false;
01dfba93 5989 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5990}
5991
3dec0095 5992static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5993{
5994 struct drm_device *dev = crtc->dev;
5995 drm_i915_private_t *dev_priv = dev->dev_private;
5996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5997 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5998 int dpll_reg = DPLL(pipe);
5999 int dpll;
652c393a 6000
bad720ff 6001 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6002 return;
6003
6004 if (!dev_priv->lvds_downclock_avail)
6005 return;
6006
dbdc6479 6007 dpll = I915_READ(dpll_reg);
652c393a 6008 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6009 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6010
6011 /* Unlock panel regs */
dbdc6479
JB		 6012 I915_WRITE(PP_CONTROL,
6013 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6014
6015 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6016 I915_WRITE(dpll_reg, dpll);
9d0498a2 6017 intel_wait_for_vblank(dev, pipe);
dbdc6479 6018
652c393a
JB		 6019 dpll = I915_READ(dpll_reg);
6020 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6021 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6022
6023 /* ...and lock them again */
6024 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6025 }
6026
6027 /* Schedule downclock */
3dec0095
DV		 6028 mod_timer(&intel_crtc->idle_timer, jiffies +
6029 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6030}
6031
6032static void intel_decrease_pllclock(struct drm_crtc *crtc)
6033{
6034 struct drm_device *dev = crtc->dev;
6035 drm_i915_private_t *dev_priv = dev->dev_private;
6036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6037 int pipe = intel_crtc->pipe;
9db4a9c7 6038 int dpll_reg = DPLL(pipe);
652c393a
JB		 6039 int dpll = I915_READ(dpll_reg);
6040
bad720ff 6041 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6042 return;
6043
6044 if (!dev_priv->lvds_downclock_avail)
6045 return;
6046
6047 /*
6048 * Since this is called by a timer, we should never get here in
6049 * the manual case.
6050 */
6051 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6052 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6053
6054 /* Unlock panel regs */
4a655f04
JB		 6055 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6056 PANEL_UNLOCK_REGS);
652c393a
JB		 6057
6058 dpll |= DISPLAY_RATE_SELECT_FPA1;
6059 I915_WRITE(dpll_reg, dpll);
9d0498a2 6060 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6061 dpll = I915_READ(dpll_reg);
6062 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6063 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6064
6065 /* ...and lock them again */
6066 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6067 }
6068
6069}
6070
6071/**
6072 * intel_idle_update - adjust clocks for idleness
6073 * @work: work struct
6074 *
6075 * Either the GPU or display (or both) went idle. Check the busy status
6076 * here and adjust the CRTC and GPU clocks as necessary.
6077 */
6078static void intel_idle_update(struct work_struct *work)
6079{
6080 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6081 idle_work);
6082 struct drm_device *dev = dev_priv->dev;
6083 struct drm_crtc *crtc;
6084 struct intel_crtc *intel_crtc;
6085
6086 if (!i915_powersave)
6087 return;
6088
6089 mutex_lock(&dev->struct_mutex);
6090
7648fa99
JB		 6091 i915_update_gfx_val(dev_priv);
6092
652c393a
JB		 6093 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6094 /* Skip inactive CRTCs */
6095 if (!crtc->fb)
6096 continue;
6097
6098 intel_crtc = to_intel_crtc(crtc);
6099 if (!intel_crtc->busy)
6100 intel_decrease_pllclock(crtc);
6101 }
6102
45ac22c8 6103
652c393a
JB		 6104 mutex_unlock(&dev->struct_mutex);
6105}
6106
6107/**
6108 * intel_mark_busy - mark the GPU and possibly the display busy
6109 * @dev: drm device
6110 * @obj: object we're operating on
6111 *
6112 * Callers can use this function to indicate that the GPU is busy processing
6113 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6114 * buffer), we'll also mark the display as busy, so we know to increase its
6115 * clock frequency.
6116 */
05394f39 6117void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6118{
6119 drm_i915_private_t *dev_priv = dev->dev_private;
6120 struct drm_crtc *crtc = NULL;
6121 struct intel_framebuffer *intel_fb;
6122 struct intel_crtc *intel_crtc;
6123
5e17ee74
ZW		 6124 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6125 return;
6126
18b2190c 6127 if (!dev_priv->busy)
28cf798f 6128 dev_priv->busy = true;
18b2190c 6129 else
28cf798f
CW		 6130 mod_timer(&dev_priv->idle_timer, jiffies +
6131 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6132
6133 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6134 if (!crtc->fb)
6135 continue;
6136
6137 intel_crtc = to_intel_crtc(crtc);
6138 intel_fb = to_intel_framebuffer(crtc->fb);
6139 if (intel_fb->obj == obj) {
6140 if (!intel_crtc->busy) {
6141 /* Non-busy -> busy, upclock */
3dec0095 6142 intel_increase_pllclock(crtc);
652c393a
JB		 6143 intel_crtc->busy = true;
6144 } else {
6145 /* Busy -> busy, put off timer */
6146 mod_timer(&intel_crtc->idle_timer, jiffies +
6147 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6148 }
6149 }
6150 }
6151}
6152
79e53945
JB		 6153static void intel_crtc_destroy(struct drm_crtc *crtc)
6154{
6155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6156 struct drm_device *dev = crtc->dev;
6157 struct intel_unpin_work *work;
6158 unsigned long flags;
6159
6160 spin_lock_irqsave(&dev->event_lock, flags);
6161 work = intel_crtc->unpin_work;
6162 intel_crtc->unpin_work = NULL;
6163 spin_unlock_irqrestore(&dev->event_lock, flags);
6164
6165 if (work) {
6166 cancel_work_sync(&work->work);
6167 kfree(work);
6168 }
79e53945
JB		 6169
6170 drm_crtc_cleanup(crtc);
67e77c5a 6171
79e53945
JB		 6172 kfree(intel_crtc);
6173}
6174
6b95a207
KH		 6175static void intel_unpin_work_fn(struct work_struct *__work)
6176{
6177 struct intel_unpin_work *work =
6178 container_of(__work, struct intel_unpin_work, work);
6179
6180 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6181 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6182 drm_gem_object_unreference(&work->pending_flip_obj->base);
6183 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6184
6b95a207
KH		 6185 mutex_unlock(&work->dev->struct_mutex);
6186 kfree(work);
6187}
6188
1afe3e9d 6189static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6190 struct drm_crtc *crtc)
6b95a207
KH		 6191{
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6194 struct intel_unpin_work *work;
05394f39 6195 struct drm_i915_gem_object *obj;
6b95a207 6196 struct drm_pending_vblank_event *e;
49b14a5c 6197 struct timeval tnow, tvbl;
6b95a207
KH		 6198 unsigned long flags;
6199
6200 /* Ignore early vblank irqs */
6201 if (intel_crtc == NULL)
6202 return;
6203
49b14a5c
MK		 6204 do_gettimeofday(&tnow);
6205
6b95a207
KH		 6206 spin_lock_irqsave(&dev->event_lock, flags);
6207 work = intel_crtc->unpin_work;
6208 if (work == NULL || !work->pending) {
6209 spin_unlock_irqrestore(&dev->event_lock, flags);
6210 return;
6211 }
6212
6213 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6214
6215 if (work->event) {
6216 e = work->event;
49b14a5c 6217 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6218
6219 /* Called before vblank count and timestamps have
6220 * been updated for the vblank interval of flip
6221 * completion? Need to increment vblank count and
6222 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6223 * to account for this. We assume this happened if we
6224 * get called over 0.9 frame durations after the last
6225 * timestamped vblank.
6226 *
6227 * This calculation can not be used with vrefresh rates
6228 * below 5Hz (10Hz to be on the safe side) without
6229 * promoting to 64 integers.
0af7e4df 6230 */
49b14a5c
MK		 6231 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6232 9 * crtc->framedur_ns) {
0af7e4df 6233 e->event.sequence++;
49b14a5c
MK		 6234 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6235 crtc->framedur_ns);
0af7e4df
MK		 6236 }
6237
49b14a5c
MK		 6238 e->event.tv_sec = tvbl.tv_sec;
6239 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6240
6b95a207
KH		 6241 list_add_tail(&e->base.link,
6242 &e->base.file_priv->event_list);
6243 wake_up_interruptible(&e->base.file_priv->event_wait);
6244 }
6245
0af7e4df
MK		 6246 drm_vblank_put(dev, intel_crtc->pipe);
6247
6b95a207
KH		 6248 spin_unlock_irqrestore(&dev->event_lock, flags);
6249
05394f39 6250 obj = work->old_fb_obj;
d9e86c0e 6251
e59f2bac 6252 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6253 &obj->pending_flip.counter);
6254 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6255 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6256
6b95a207 6257 schedule_work(&work->work);
e5510fac
JB		 6258
6259 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6260}
6261
1afe3e9d
JB		 6262void intel_finish_page_flip(struct drm_device *dev, int pipe)
6263{
6264 drm_i915_private_t *dev_priv = dev->dev_private;
6265 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6266
49b14a5c 6267 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6268}
6269
6270void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6271{
6272 drm_i915_private_t *dev_priv = dev->dev_private;
6273 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6274
49b14a5c 6275 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6276}
6277
6b95a207
KH		 6278void intel_prepare_page_flip(struct drm_device *dev, int plane)
6279{
6280 drm_i915_private_t *dev_priv = dev->dev_private;
6281 struct intel_crtc *intel_crtc =
6282 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6283 unsigned long flags;
6284
6285 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6286 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6287 if ((++intel_crtc->unpin_work->pending) > 1)
6288 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6289 } else {
6290 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6291 }
6b95a207
KH		 6292 spin_unlock_irqrestore(&dev->event_lock, flags);
6293}
6294
8c9f3aaf
JB		 6295static int intel_gen2_queue_flip(struct drm_device *dev,
6296 struct drm_crtc *crtc,
6297 struct drm_framebuffer *fb,
6298 struct drm_i915_gem_object *obj)
6299{
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6302 unsigned long offset;
6303 u32 flip_mask;
6304 int ret;
6305
6306 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6307 if (ret)
6308 goto out;
6309
6310 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6311 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6312
6313 ret = BEGIN_LP_RING(6);
6314 if (ret)
6315 goto out;
6316
6317 /* Can't queue multiple flips, so wait for the previous
6318 * one to finish before executing the next.
6319 */
6320 if (intel_crtc->plane)
6321 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6322 else
6323 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6324 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6325 OUT_RING(MI_NOOP);
6326 OUT_RING(MI_DISPLAY_FLIP |
6327 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6328 OUT_RING(fb->pitch);
6329 OUT_RING(obj->gtt_offset + offset);
6330 OUT_RING(MI_NOOP);
6331 ADVANCE_LP_RING();
6332out:
6333 return ret;
6334}
6335
6336static int intel_gen3_queue_flip(struct drm_device *dev,
6337 struct drm_crtc *crtc,
6338 struct drm_framebuffer *fb,
6339 struct drm_i915_gem_object *obj)
6340{
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6343 unsigned long offset;
6344 u32 flip_mask;
6345 int ret;
6346
6347 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6348 if (ret)
6349 goto out;
6350
6351 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6352 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6353
6354 ret = BEGIN_LP_RING(6);
6355 if (ret)
6356 goto out;
6357
6358 if (intel_crtc->plane)
6359 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6360 else
6361 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6362 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6363 OUT_RING(MI_NOOP);
6364 OUT_RING(MI_DISPLAY_FLIP_I915 |
6365 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6366 OUT_RING(fb->pitch);
6367 OUT_RING(obj->gtt_offset + offset);
6368 OUT_RING(MI_NOOP);
6369
6370 ADVANCE_LP_RING();
6371out:
6372 return ret;
6373}
6374
6375static int intel_gen4_queue_flip(struct drm_device *dev,
6376 struct drm_crtc *crtc,
6377 struct drm_framebuffer *fb,
6378 struct drm_i915_gem_object *obj)
6379{
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382 uint32_t pf, pipesrc;
6383 int ret;
6384
6385 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6386 if (ret)
6387 goto out;
6388
6389 ret = BEGIN_LP_RING(4);
6390 if (ret)
6391 goto out;
6392
6393 /* i965+ uses the linear or tiled offsets from the
6394 * Display Registers (which do not change across a page-flip)
6395 * so we need only reprogram the base address.
6396 */
6397 OUT_RING(MI_DISPLAY_FLIP |
6398 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6399 OUT_RING(fb->pitch);
6400 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6401
6402 /* XXX Enabling the panel-fitter across page-flip is so far
6403 * untested on non-native modes, so ignore it for now.
6404 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6405 */
6406 pf = 0;
6407 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6408 OUT_RING(pf | pipesrc);
6409 ADVANCE_LP_RING();
6410out:
6411 return ret;
6412}
6413
6414static int intel_gen6_queue_flip(struct drm_device *dev,
6415 struct drm_crtc *crtc,
6416 struct drm_framebuffer *fb,
6417 struct drm_i915_gem_object *obj)
6418{
6419 struct drm_i915_private *dev_priv = dev->dev_private;
6420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6421 uint32_t pf, pipesrc;
6422 int ret;
6423
6424 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6425 if (ret)
6426 goto out;
6427
6428 ret = BEGIN_LP_RING(4);
6429 if (ret)
6430 goto out;
6431
6432 OUT_RING(MI_DISPLAY_FLIP |
6433 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6434 OUT_RING(fb->pitch | obj->tiling_mode);
6435 OUT_RING(obj->gtt_offset);
6436
6437 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6438 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6439 OUT_RING(pf | pipesrc);
6440 ADVANCE_LP_RING();
6441out:
6442 return ret;
6443}
6444
7c9017e5
JB		 6445/*
6446 * On gen7 we currently use the blit ring because (in early silicon at least)
6447 * the render ring doesn't give us interrpts for page flip completion, which
6448 * means clients will hang after the first flip is queued. Fortunately the
6449 * blit ring generates interrupts properly, so use it instead.
6450 */
6451static int intel_gen7_queue_flip(struct drm_device *dev,
6452 struct drm_crtc *crtc,
6453 struct drm_framebuffer *fb,
6454 struct drm_i915_gem_object *obj)
6455{
6456 struct drm_i915_private *dev_priv = dev->dev_private;
6457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6458 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6459 int ret;
6460
6461 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6462 if (ret)
6463 goto out;
6464
6465 ret = intel_ring_begin(ring, 4);
6466 if (ret)
6467 goto out;
6468
6469 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6470 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6471 intel_ring_emit(ring, (obj->gtt_offset));
6472 intel_ring_emit(ring, (MI_NOOP));
6473 intel_ring_advance(ring);
6474out:
6475 return ret;
6476}
6477
8c9f3aaf
JB		 6478static int intel_default_queue_flip(struct drm_device *dev,
6479 struct drm_crtc *crtc,
6480 struct drm_framebuffer *fb,
6481 struct drm_i915_gem_object *obj)
6482{
6483 return -ENODEV;
6484}
6485
6b95a207
KH		 6486static int intel_crtc_page_flip(struct drm_crtc *crtc,
6487 struct drm_framebuffer *fb,
6488 struct drm_pending_vblank_event *event)
6489{
6490 struct drm_device *dev = crtc->dev;
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct intel_framebuffer *intel_fb;
05394f39 6493 struct drm_i915_gem_object *obj;
6b95a207
KH		 6494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6495 struct intel_unpin_work *work;
8c9f3aaf 6496 unsigned long flags;
52e68630 6497 int ret;
6b95a207
KH		 6498
6499 work = kzalloc(sizeof *work, GFP_KERNEL);
6500 if (work == NULL)
6501 return -ENOMEM;
6502
6b95a207
KH		 6503 work->event = event;
6504 work->dev = crtc->dev;
6505 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6506 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6507 INIT_WORK(&work->work, intel_unpin_work_fn);
6508
6509 /* We borrow the event spin lock for protecting unpin_work */
6510 spin_lock_irqsave(&dev->event_lock, flags);
6511 if (intel_crtc->unpin_work) {
6512 spin_unlock_irqrestore(&dev->event_lock, flags);
6513 kfree(work);
468f0b44
CW		 6514
6515 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6516 return -EBUSY;
6517 }
6518 intel_crtc->unpin_work = work;
6519 spin_unlock_irqrestore(&dev->event_lock, flags);
6520
6521 intel_fb = to_intel_framebuffer(fb);
6522 obj = intel_fb->obj;
6523
468f0b44 6524 mutex_lock(&dev->struct_mutex);
6b95a207 6525
75dfca80 6526 /* Reference the objects for the scheduled work. */
05394f39
CW		 6527 drm_gem_object_reference(&work->old_fb_obj->base);
6528 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6529
6530 crtc->fb = fb;
96b099fd
CW		 6531
6532 ret = drm_vblank_get(dev, intel_crtc->pipe);
6533 if (ret)
6534 goto cleanup_objs;
6535
e1f99ce6 6536 work->pending_flip_obj = obj;
e1f99ce6 6537
4e5359cd
SF		 6538 work->enable_stall_check = true;
6539
e1f99ce6
CW		 6540 /* Block clients from rendering to the new back buffer until
6541 * the flip occurs and the object is no longer visible.
6542 */
05394f39 6543 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6544
8c9f3aaf
JB		 6545 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6546 if (ret)
6547 goto cleanup_pending;
6b95a207
KH		 6548
6549 mutex_unlock(&dev->struct_mutex);
6550
e5510fac
JB		 6551 trace_i915_flip_request(intel_crtc->plane, obj);
6552
6b95a207 6553 return 0;
96b099fd 6554
8c9f3aaf
JB		 6555cleanup_pending:
6556 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6557cleanup_objs:
05394f39
CW		 6558 drm_gem_object_unreference(&work->old_fb_obj->base);
6559 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6560 mutex_unlock(&dev->struct_mutex);
6561
6562 spin_lock_irqsave(&dev->event_lock, flags);
6563 intel_crtc->unpin_work = NULL;
6564 spin_unlock_irqrestore(&dev->event_lock, flags);
6565
6566 kfree(work);
6567
6568 return ret;
6b95a207
KH		 6569}
6570
47f1c6c9
CW		 6571static void intel_sanitize_modesetting(struct drm_device *dev,
6572 int pipe, int plane)
6573{
6574 struct drm_i915_private *dev_priv = dev->dev_private;
6575 u32 reg, val;
6576
6577 if (HAS_PCH_SPLIT(dev))
6578 return;
6579
6580 /* Who knows what state these registers were left in by the BIOS or
6581 * grub?
6582 *
6583 * If we leave the registers in a conflicting state (e.g. with the
6584 * display plane reading from the other pipe than the one we intend
6585 * to use) then when we attempt to teardown the active mode, we will
6586 * not disable the pipes and planes in the correct order -- leaving
6587 * a plane reading from a disabled pipe and possibly leading to
6588 * undefined behaviour.
6589 */
6590
6591 reg = DSPCNTR(plane);
6592 val = I915_READ(reg);
6593
6594 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6595 return;
6596 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6597 return;
6598
6599 /* This display plane is active and attached to the other CPU pipe. */
6600 pipe = !pipe;
6601
6602 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6603 intel_disable_plane(dev_priv, plane, pipe);
6604 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6605}
79e53945 6606
f6e5b160
CW		 6607static void intel_crtc_reset(struct drm_crtc *crtc)
6608{
6609 struct drm_device *dev = crtc->dev;
6610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6611
6612 /* Reset flags back to the 'unknown' status so that they
6613 * will be correctly set on the initial modeset.
6614 */
6615 intel_crtc->dpms_mode = -1;
6616
6617 /* We need to fix up any BIOS configuration that conflicts with
6618 * our expectations.
6619 */
6620 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6621}
6622
6623static struct drm_crtc_helper_funcs intel_helper_funcs = {
6624 .dpms = intel_crtc_dpms,
6625 .mode_fixup = intel_crtc_mode_fixup,
6626 .mode_set = intel_crtc_mode_set,
6627 .mode_set_base = intel_pipe_set_base,
6628 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6629 .load_lut = intel_crtc_load_lut,
6630 .disable = intel_crtc_disable,
6631};
6632
6633static const struct drm_crtc_funcs intel_crtc_funcs = {
6634 .reset = intel_crtc_reset,
6635 .cursor_set = intel_crtc_cursor_set,
6636 .cursor_move = intel_crtc_cursor_move,
6637 .gamma_set = intel_crtc_gamma_set,
6638 .set_config = drm_crtc_helper_set_config,
6639 .destroy = intel_crtc_destroy,
6640 .page_flip = intel_crtc_page_flip,
6641};
6642
b358d0a6 6643static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6644{
22fd0fab 6645 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6646 struct intel_crtc *intel_crtc;
6647 int i;
6648
6649 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6650 if (intel_crtc == NULL)
6651 return;
6652
6653 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6654
6655 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6656 for (i = 0; i < 256; i++) {
6657 intel_crtc->lut_r[i] = i;
6658 intel_crtc->lut_g[i] = i;
6659 intel_crtc->lut_b[i] = i;
6660 }
6661
80824003
JB		 6662 /* Swap pipes & planes for FBC on pre-965 */
6663 intel_crtc->pipe = pipe;
6664 intel_crtc->plane = pipe;
e2e767ab 6665 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6666 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6667 intel_crtc->plane = !pipe;
80824003
JB		 6668 }
6669
22fd0fab
JB		 6670 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6671 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6672 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6673 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6674
5d1d0cc8 6675 intel_crtc_reset(&intel_crtc->base);
04dbff52 6676 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6677
6678 if (HAS_PCH_SPLIT(dev)) {
6679 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6680 intel_helper_funcs.commit = ironlake_crtc_commit;
6681 } else {
6682 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6683 intel_helper_funcs.commit = i9xx_crtc_commit;
6684 }
6685
79e53945
JB		 6686 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6687
652c393a
JB		 6688 intel_crtc->busy = false;
6689
6690 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6691 (unsigned long)intel_crtc);
79e53945
JB		 6692}
6693
08d7b3d1 6694int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6695 struct drm_file *file)
08d7b3d1
CW		 6696{
6697 drm_i915_private_t *dev_priv = dev->dev_private;
6698 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6699 struct drm_mode_object *drmmode_obj;
6700 struct intel_crtc *crtc;
08d7b3d1
CW		 6701
6702 if (!dev_priv) {
6703 DRM_ERROR("called with no initialization\n");
6704 return -EINVAL;
6705 }
6706
c05422d5
DV		 6707 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6708 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6709
c05422d5 6710 if (!drmmode_obj) {
08d7b3d1
CW		 6711 DRM_ERROR("no such CRTC id\n");
6712 return -EINVAL;
6713 }
6714
c05422d5
DV		 6715 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6716 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6717
c05422d5 6718 return 0;
08d7b3d1
CW		 6719}
6720
c5e4df33 6721static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6722{
4ef69c7a 6723 struct intel_encoder *encoder;
79e53945 6724 int index_mask = 0;
79e53945
JB		 6725 int entry = 0;
6726
4ef69c7a
CW		 6727 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6728 if (type_mask & encoder->clone_mask)
79e53945
JB		 6729 index_mask |= (1 << entry);
6730 entry++;
6731 }
4ef69c7a 6732
79e53945
JB		 6733 return index_mask;
6734}
6735
4d302442
CW		 6736static bool has_edp_a(struct drm_device *dev)
6737{
6738 struct drm_i915_private *dev_priv = dev->dev_private;
6739
6740 if (!IS_MOBILE(dev))
6741 return false;
6742
6743 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6744 return false;
6745
6746 if (IS_GEN5(dev) &&
6747 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6748 return false;
6749
6750 return true;
6751}
6752
79e53945
JB		 6753static void intel_setup_outputs(struct drm_device *dev)
6754{
725e30ad 6755 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6756 struct intel_encoder *encoder;
cb0953d7 6757 bool dpd_is_edp = false;
c5d1b51d 6758 bool has_lvds = false;
79e53945 6759
541998a1 6760 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6761 has_lvds = intel_lvds_init(dev);
6762 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6763 /* disable the panel fitter on everything but LVDS */
6764 I915_WRITE(PFIT_CONTROL, 0);
6765 }
79e53945 6766
bad720ff 6767 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6768 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6769
4d302442 6770 if (has_edp_a(dev))
32f9d658
ZW		 6771 intel_dp_init(dev, DP_A);
6772
cb0953d7
AJ		 6773 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6774 intel_dp_init(dev, PCH_DP_D);
6775 }
6776
6777 intel_crt_init(dev);
6778
6779 if (HAS_PCH_SPLIT(dev)) {
6780 int found;
6781
30ad48b7 6782 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6783 /* PCH SDVOB multiplex with HDMIB */
6784 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6785 if (!found)
6786 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6787 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6788 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6789 }
6790
6791 if (I915_READ(HDMIC) & PORT_DETECTED)
6792 intel_hdmi_init(dev, HDMIC);
6793
6794 if (I915_READ(HDMID) & PORT_DETECTED)
6795 intel_hdmi_init(dev, HDMID);
6796
5eb08b69
ZW		 6797 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6798 intel_dp_init(dev, PCH_DP_C);
6799
cb0953d7 6800 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6801 intel_dp_init(dev, PCH_DP_D);
6802
103a196f 6803 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6804 bool found = false;
7d57382e 6805
725e30ad 6806 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6807 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6808 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6809 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6810 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6811 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6812 }
27185ae1 6813
b01f2c3a
JB		 6814 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6815 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6816 intel_dp_init(dev, DP_B);
b01f2c3a 6817 }
725e30ad 6818 }
13520b05
KH		 6819
6820 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6821
b01f2c3a
JB		 6822 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6823 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6824 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6825 }
27185ae1
ML		 6826
6827 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6828
b01f2c3a
JB		 6829 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6830 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6831 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6832 }
6833 if (SUPPORTS_INTEGRATED_DP(dev)) {
6834 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6835 intel_dp_init(dev, DP_C);
b01f2c3a 6836 }
725e30ad 6837 }
27185ae1 6838
b01f2c3a
JB		 6839 if (SUPPORTS_INTEGRATED_DP(dev) &&
6840 (I915_READ(DP_D) & DP_DETECTED)) {
6841 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6842 intel_dp_init(dev, DP_D);
b01f2c3a 6843 }
bad720ff 6844 } else if (IS_GEN2(dev))
79e53945
JB		 6845 intel_dvo_init(dev);
6846
103a196f 6847 if (SUPPORTS_TV(dev))
79e53945
JB		 6848 intel_tv_init(dev);
6849
4ef69c7a
CW		 6850 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6851 encoder->base.possible_crtcs = encoder->crtc_mask;
6852 encoder->base.possible_clones =
6853 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6854 }
47356eb6
CW		 6855
6856 intel_panel_setup_backlight(dev);
2c7111db
CW		 6857
6858 /* disable all the possible outputs/crtcs before entering KMS mode */
6859 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6860}
6861
6862static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6863{
6864 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6865
6866 drm_framebuffer_cleanup(fb);
05394f39 6867 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6868
6869 kfree(intel_fb);
6870}
6871
6872static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6873 struct drm_file *file,
79e53945
JB		 6874 unsigned int *handle)
6875{
6876 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6877 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6878
05394f39 6879 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6880}
6881
6882static const struct drm_framebuffer_funcs intel_fb_funcs = {
6883 .destroy = intel_user_framebuffer_destroy,
6884 .create_handle = intel_user_framebuffer_create_handle,
6885};
6886
38651674
DA		 6887int intel_framebuffer_init(struct drm_device *dev,
6888 struct intel_framebuffer *intel_fb,
6889 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6890 struct drm_i915_gem_object *obj)
79e53945 6891{
79e53945
JB		 6892 int ret;
6893
05394f39 6894 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6895 return -EINVAL;
6896
6897 if (mode_cmd->pitch & 63)
6898 return -EINVAL;
6899
6900 switch (mode_cmd->bpp) {
6901 case 8:
6902 case 16:
6903 case 24:
6904 case 32:
6905 break;
6906 default:
6907 return -EINVAL;
6908 }
6909
79e53945
JB		 6910 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6911 if (ret) {
6912 DRM_ERROR("framebuffer init failed %d\n", ret);
6913 return ret;
6914 }
6915
6916 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6917 intel_fb->obj = obj;
79e53945
JB		 6918 return 0;
6919}
6920
79e53945
JB		 6921static struct drm_framebuffer *
6922intel_user_framebuffer_create(struct drm_device *dev,
6923 struct drm_file *filp,
6924 struct drm_mode_fb_cmd *mode_cmd)
6925{
05394f39 6926 struct drm_i915_gem_object *obj;
79e53945 6927
05394f39 6928 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6929 if (&obj->base == NULL)
cce13ff7 6930 return ERR_PTR(-ENOENT);
79e53945 6931
d2dff872 6932 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6933}
6934
79e53945 6935static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6936 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6937 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6938};
6939
05394f39 6940static struct drm_i915_gem_object *
aa40d6bb 6941intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6942{
05394f39 6943 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6944 int ret;
6945
2c34b850
BW		 6946 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6947
aa40d6bb
ZN		 6948 ctx = i915_gem_alloc_object(dev, 4096);
6949 if (!ctx) {
9ea8d059
CW		 6950 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6951 return NULL;
6952 }
6953
75e9e915 6954 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6955 if (ret) {
6956 DRM_ERROR("failed to pin power context: %d\n", ret);
6957 goto err_unref;
6958 }
6959
aa40d6bb 6960 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6961 if (ret) {
6962 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6963 goto err_unpin;
6964 }
9ea8d059 6965
aa40d6bb 6966 return ctx;
9ea8d059
CW		 6967
6968err_unpin:
aa40d6bb 6969 i915_gem_object_unpin(ctx);
9ea8d059 6970err_unref:
05394f39 6971 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6972 mutex_unlock(&dev->struct_mutex);
6973 return NULL;
6974}
6975
7648fa99
JB		 6976bool ironlake_set_drps(struct drm_device *dev, u8 val)
6977{
6978 struct drm_i915_private *dev_priv = dev->dev_private;
6979 u16 rgvswctl;
6980
6981 rgvswctl = I915_READ16(MEMSWCTL);
6982 if (rgvswctl & MEMCTL_CMD_STS) {
6983 DRM_DEBUG("gpu busy, RCS change rejected\n");
6984 return false; /* still busy with another command */
6985 }
6986
6987 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6988 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6989 I915_WRITE16(MEMSWCTL, rgvswctl);
6990 POSTING_READ16(MEMSWCTL);
6991
6992 rgvswctl |= MEMCTL_CMD_STS;
6993 I915_WRITE16(MEMSWCTL, rgvswctl);
6994
6995 return true;
6996}
6997
f97108d1
JB		 6998void ironlake_enable_drps(struct drm_device *dev)
6999{
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7001 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7002 u8 fmax, fmin, fstart, vstart;
f97108d1 7003
ea056c14
JB		 7004 /* Enable temp reporting */
7005 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7006 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7007
f97108d1
JB		 7008 /* 100ms RC evaluation intervals */
7009 I915_WRITE(RCUPEI, 100000);
7010 I915_WRITE(RCDNEI, 100000);
7011
7012 /* Set max/min thresholds to 90ms and 80ms respectively */
7013 I915_WRITE(RCBMAXAVG, 90000);
7014 I915_WRITE(RCBMINAVG, 80000);
7015
7016 I915_WRITE(MEMIHYST, 1);
7017
7018 /* Set up min, max, and cur for interrupt handling */
7019 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7020 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7021 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7022 MEMMODE_FSTART_SHIFT;
7648fa99 7023
f97108d1
JB		 7024 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7025 PXVFREQ_PX_SHIFT;
7026
80dbf4b7 7027 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7028 dev_priv->fstart = fstart;
7029
80dbf4b7 7030 dev_priv->max_delay = fstart;
f97108d1
JB		 7031 dev_priv->min_delay = fmin;
7032 dev_priv->cur_delay = fstart;
7033
80dbf4b7
JB		 7034 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7035 fmax, fmin, fstart);
7648fa99 7036
f97108d1
JB		 7037 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7038
7039 /*
7040 * Interrupts will be enabled in ironlake_irq_postinstall
7041 */
7042
7043 I915_WRITE(VIDSTART, vstart);
7044 POSTING_READ(VIDSTART);
7045
7046 rgvmodectl |= MEMMODE_SWMODE_EN;
7047 I915_WRITE(MEMMODECTL, rgvmodectl);
7048
481b6af3 7049 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7050 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7051 msleep(1);
7052
7648fa99 7053 ironlake_set_drps(dev, fstart);
f97108d1 7054
7648fa99
JB		 7055 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7056 I915_READ(0x112e0);
7057 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7058 dev_priv->last_count2 = I915_READ(0x112f4);
7059 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7060}
7061
7062void ironlake_disable_drps(struct drm_device *dev)
7063{
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7065 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7066
7067 /* Ack interrupts, disable EFC interrupt */
7068 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7069 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7070 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7071 I915_WRITE(DEIIR, DE_PCU_EVENT);
7072 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7073
7074 /* Go back to the starting frequency */
7648fa99 7075 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7076 msleep(1);
7077 rgvswctl |= MEMCTL_CMD_STS;
7078 I915_WRITE(MEMSWCTL, rgvswctl);
7079 msleep(1);
7080
7081}
7082
3b8d8d91
JB		 7083void gen6_set_rps(struct drm_device *dev, u8 val)
7084{
7085 struct drm_i915_private *dev_priv = dev->dev_private;
7086 u32 swreq;
7087
7088 swreq = (val & 0x3ff) << 25;
7089 I915_WRITE(GEN6_RPNSWREQ, swreq);
7090}
7091
7092void gen6_disable_rps(struct drm_device *dev)
7093{
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095
7096 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7097 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7098 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7099
7100 spin_lock_irq(&dev_priv->rps_lock);
7101 dev_priv->pm_iir = 0;
7102 spin_unlock_irq(&dev_priv->rps_lock);
7103
3b8d8d91
JB		 7104 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7105}
7106
7648fa99
JB		 7107static unsigned long intel_pxfreq(u32 vidfreq)
7108{
7109 unsigned long freq;
7110 int div = (vidfreq & 0x3f0000) >> 16;
7111 int post = (vidfreq & 0x3000) >> 12;
7112 int pre = (vidfreq & 0x7);
7113
7114 if (!pre)
7115 return 0;
7116
7117 freq = ((div * 133333) / ((1<<post) * pre));
7118
7119 return freq;
7120}
7121
7122void intel_init_emon(struct drm_device *dev)
7123{
7124 struct drm_i915_private *dev_priv = dev->dev_private;
7125 u32 lcfuse;
7126 u8 pxw[16];
7127 int i;
7128
7129 /* Disable to program */
7130 I915_WRITE(ECR, 0);
7131 POSTING_READ(ECR);
7132
7133 /* Program energy weights for various events */
7134 I915_WRITE(SDEW, 0x15040d00);
7135 I915_WRITE(CSIEW0, 0x007f0000);
7136 I915_WRITE(CSIEW1, 0x1e220004);
7137 I915_WRITE(CSIEW2, 0x04000004);
7138
7139 for (i = 0; i < 5; i++)
7140 I915_WRITE(PEW + (i * 4), 0);
7141 for (i = 0; i < 3; i++)
7142 I915_WRITE(DEW + (i * 4), 0);
7143
7144 /* Program P-state weights to account for frequency power adjustment */
7145 for (i = 0; i < 16; i++) {
7146 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7147 unsigned long freq = intel_pxfreq(pxvidfreq);
7148 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7149 PXVFREQ_PX_SHIFT;
7150 unsigned long val;
7151
7152 val = vid * vid;
7153 val *= (freq / 1000);
7154 val *= 255;
7155 val /= (127*127*900);
7156 if (val > 0xff)
7157 DRM_ERROR("bad pxval: %ld\n", val);
7158 pxw[i] = val;
7159 }
7160 /* Render standby states get 0 weight */
7161 pxw[14] = 0;
7162 pxw[15] = 0;
7163
7164 for (i = 0; i < 4; i++) {
7165 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7166 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7167 I915_WRITE(PXW + (i * 4), val);
7168 }
7169
7170 /* Adjust magic regs to magic values (more experimental results) */
7171 I915_WRITE(OGW0, 0);
7172 I915_WRITE(OGW1, 0);
7173 I915_WRITE(EG0, 0x00007f00);
7174 I915_WRITE(EG1, 0x0000000e);
7175 I915_WRITE(EG2, 0x000e0000);
7176 I915_WRITE(EG3, 0x68000300);
7177 I915_WRITE(EG4, 0x42000000);
7178 I915_WRITE(EG5, 0x00140031);
7179 I915_WRITE(EG6, 0);
7180 I915_WRITE(EG7, 0);
7181
7182 for (i = 0; i < 8; i++)
7183 I915_WRITE(PXWL + (i * 4), 0);
7184
7185 /* Enable PMON + select events */
7186 I915_WRITE(ECR, 0x80000019);
7187
7188 lcfuse = I915_READ(LCFUSE02);
7189
7190 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7191}
7192
3b8d8d91 7193void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7194{
a6044e23
JB		 7195 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7196 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7197 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7198 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7199 int i;
7200
7201 /* Here begins a magic sequence of register writes to enable
7202 * auto-downclocking.
7203 *
7204 * Perhaps there might be some value in exposing these to
7205 * userspace...
7206 */
7207 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7208 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7209 gen6_gt_force_wake_get(dev_priv);
8fd26859 7210
3b8d8d91 7211 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7212 I915_WRITE(GEN6_RC_CONTROL, 0);
7213
7214 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7215 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7216 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7217 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7218 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7219
7220 for (i = 0; i < I915_NUM_RINGS; i++)
7221 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7222
7223 I915_WRITE(GEN6_RC_SLEEP, 0);
7224 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7225 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7226 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7227 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7228
7df8721b
JB		 7229 if (i915_enable_rc6)
7230 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7231 GEN6_RC_CTL_RC6_ENABLE;
7232
8fd26859 7233 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7234 rc6_mask |
9c3d2f7f 7235 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7236 GEN6_RC_CTL_HW_ENABLE);
7237
3b8d8d91 7238 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7239 GEN6_FREQUENCY(10) |
7240 GEN6_OFFSET(0) |
7241 GEN6_AGGRESSIVE_TURBO);
7242 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7243 GEN6_FREQUENCY(12));
7244
7245 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7246 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7247 18 << 24 |
7248 6 << 16);
ccab5c82
JB		 7249 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7250 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7251 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7252 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7253 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7254 I915_WRITE(GEN6_RP_CONTROL,
7255 GEN6_RP_MEDIA_TURBO |
7256 GEN6_RP_USE_NORMAL_FREQ |
7257 GEN6_RP_MEDIA_IS_GFX |
7258 GEN6_RP_ENABLE |
ccab5c82
JB		 7259 GEN6_RP_UP_BUSY_AVG |
7260 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7261
7262 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7263 500))
7264 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7265
7266 I915_WRITE(GEN6_PCODE_DATA, 0);
7267 I915_WRITE(GEN6_PCODE_MAILBOX,
7268 GEN6_PCODE_READY |
7269 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7270 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7271 500))
7272 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7273
a6044e23
JB		 7274 min_freq = (rp_state_cap & 0xff0000) >> 16;
7275 max_freq = rp_state_cap & 0xff;
7276 cur_freq = (gt_perf_status & 0xff00) >> 8;
7277
7278 /* Check for overclock support */
7279 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7280 500))
7281 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7282 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7283 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7284 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7285 500))
7286 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7287 if (pcu_mbox & (1<<31)) { /* OC supported */
7288 max_freq = pcu_mbox & 0xff;
e281fcaa 7289 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7290 }
7291
7292 /* In units of 100MHz */
7293 dev_priv->max_delay = max_freq;
7294 dev_priv->min_delay = min_freq;
7295 dev_priv->cur_delay = cur_freq;
7296
8fd26859
CW		 7297 /* requires MSI enabled */
7298 I915_WRITE(GEN6_PMIER,
7299 GEN6_PM_MBOX_EVENT |
7300 GEN6_PM_THERMAL_EVENT |
7301 GEN6_PM_RP_DOWN_TIMEOUT |
7302 GEN6_PM_RP_UP_THRESHOLD |
7303 GEN6_PM_RP_DOWN_THRESHOLD |
7304 GEN6_PM_RP_UP_EI_EXPIRED |
7305 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7306 spin_lock_irq(&dev_priv->rps_lock);
7307 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7308 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7309 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7310 /* enable all PM interrupts */
7311 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7312
fcca7926 7313 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7314 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7315}
7316
6067aaea
JB		 7317static void ironlake_init_clock_gating(struct drm_device *dev)
7318{
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7320 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7321
7322 /* Required for FBC */
7323 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7324 DPFCRUNIT_CLOCK_GATE_DISABLE |
7325 DPFDUNIT_CLOCK_GATE_DISABLE;
7326 /* Required for CxSR */
7327 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7328
7329 I915_WRITE(PCH_3DCGDIS0,
7330 MARIUNIT_CLOCK_GATE_DISABLE |
7331 SVSMUNIT_CLOCK_GATE_DISABLE);
7332 I915_WRITE(PCH_3DCGDIS1,
7333 VFMUNIT_CLOCK_GATE_DISABLE);
7334
7335 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7336
6067aaea
JB		 7337 /*
7338 * According to the spec the following bits should be set in
7339 * order to enable memory self-refresh
7340 * The bit 22/21 of 0x42004
7341 * The bit 5 of 0x42020
7342 * The bit 15 of 0x45000
7343 */
7344 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7345 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7346 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7347 I915_WRITE(ILK_DSPCLK_GATE,
7348 (I915_READ(ILK_DSPCLK_GATE) |
7349 ILK_DPARB_CLK_GATE));
7350 I915_WRITE(DISP_ARB_CTL,
7351 (I915_READ(DISP_ARB_CTL) |
7352 DISP_FBC_WM_DIS));
7353 I915_WRITE(WM3_LP_ILK, 0);
7354 I915_WRITE(WM2_LP_ILK, 0);
7355 I915_WRITE(WM1_LP_ILK, 0);
7356
7357 /*
7358 * Based on the document from hardware guys the following bits
7359 * should be set unconditionally in order to enable FBC.
7360 * The bit 22 of 0x42000
7361 * The bit 22 of 0x42004
7362 * The bit 7,8,9 of 0x42020.
7363 */
7364 if (IS_IRONLAKE_M(dev)) {
7365 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7366 I915_READ(ILK_DISPLAY_CHICKEN1) |
7367 ILK_FBCQ_DIS);
7368 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7369 I915_READ(ILK_DISPLAY_CHICKEN2) |
7370 ILK_DPARB_GATE);
7371 I915_WRITE(ILK_DSPCLK_GATE,
7372 I915_READ(ILK_DSPCLK_GATE) |
7373 ILK_DPFC_DIS1 |
7374 ILK_DPFC_DIS2 |
7375 ILK_CLK_FBC);
7376 }
7377
7378 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7379 I915_READ(ILK_DISPLAY_CHICKEN2) |
7380 ILK_ELPIN_409_SELECT);
7381 I915_WRITE(_3D_CHICKEN2,
7382 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7383 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7384}
7385
6067aaea 7386static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7387{
7388 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7389 int pipe;
6067aaea
JB		 7390 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7391
7392 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7393
6067aaea
JB		 7394 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7395 I915_READ(ILK_DISPLAY_CHICKEN2) |
7396 ILK_ELPIN_409_SELECT);
8956c8bb 7397
6067aaea
JB		 7398 I915_WRITE(WM3_LP_ILK, 0);
7399 I915_WRITE(WM2_LP_ILK, 0);
7400 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7401
7402 /*
6067aaea
JB		 7403 * According to the spec the following bits should be
7404 * set in order to enable memory self-refresh and fbc:
7405 * The bit21 and bit22 of 0x42000
7406 * The bit21 and bit22 of 0x42004
7407 * The bit5 and bit7 of 0x42020
7408 * The bit14 of 0x70180
7409 * The bit14 of 0x71180
652c393a 7410 */
6067aaea
JB		 7411 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7412 I915_READ(ILK_DISPLAY_CHICKEN1) |
7413 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7414 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7415 I915_READ(ILK_DISPLAY_CHICKEN2) |
7416 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7417 I915_WRITE(ILK_DSPCLK_GATE,
7418 I915_READ(ILK_DSPCLK_GATE) |
7419 ILK_DPARB_CLK_GATE |
7420 ILK_DPFD_CLK_GATE);
8956c8bb 7421
d74362c9 7422 for_each_pipe(pipe) {
6067aaea
JB		 7423 I915_WRITE(DSPCNTR(pipe),
7424 I915_READ(DSPCNTR(pipe)) |
7425 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7426 intel_flush_display_plane(dev_priv, pipe);
7427 }
6067aaea 7428}
8956c8bb 7429
28963a3e
JB		 7430static void ivybridge_init_clock_gating(struct drm_device *dev)
7431{
7432 struct drm_i915_private *dev_priv = dev->dev_private;
7433 int pipe;
7434 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7435
28963a3e 7436 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7437
28963a3e
JB		 7438 I915_WRITE(WM3_LP_ILK, 0);
7439 I915_WRITE(WM2_LP_ILK, 0);
7440 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7441
28963a3e 7442 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7443
d74362c9 7444 for_each_pipe(pipe) {
28963a3e
JB		 7445 I915_WRITE(DSPCNTR(pipe),
7446 I915_READ(DSPCNTR(pipe)) |
7447 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7448 intel_flush_display_plane(dev_priv, pipe);
7449 }
28963a3e
JB		 7450}
7451
6067aaea
JB		 7452static void g4x_init_clock_gating(struct drm_device *dev)
7453{
7454 struct drm_i915_private *dev_priv = dev->dev_private;
7455 uint32_t dspclk_gate;
8fd26859 7456
6067aaea
JB		 7457 I915_WRITE(RENCLK_GATE_D1, 0);
7458 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7459 GS_UNIT_CLOCK_GATE_DISABLE |
7460 CL_UNIT_CLOCK_GATE_DISABLE);
7461 I915_WRITE(RAMCLK_GATE_D, 0);
7462 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7463 OVRUNIT_CLOCK_GATE_DISABLE |
7464 OVCUNIT_CLOCK_GATE_DISABLE;
7465 if (IS_GM45(dev))
7466 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7467 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7468}
1398261a 7469
6067aaea
JB		 7470static void crestline_init_clock_gating(struct drm_device *dev)
7471{
7472 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7473
6067aaea
JB		 7474 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7475 I915_WRITE(RENCLK_GATE_D2, 0);
7476 I915_WRITE(DSPCLK_GATE_D, 0);
7477 I915_WRITE(RAMCLK_GATE_D, 0);
7478 I915_WRITE16(DEUC, 0);
7479}
652c393a 7480
6067aaea
JB		 7481static void broadwater_init_clock_gating(struct drm_device *dev)
7482{
7483 struct drm_i915_private *dev_priv = dev->dev_private;
7484
7485 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7486 I965_RCC_CLOCK_GATE_DISABLE |
7487 I965_RCPB_CLOCK_GATE_DISABLE |
7488 I965_ISC_CLOCK_GATE_DISABLE |
7489 I965_FBC_CLOCK_GATE_DISABLE);
7490 I915_WRITE(RENCLK_GATE_D2, 0);
7491}
7492
7493static void gen3_init_clock_gating(struct drm_device *dev)
7494{
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496 u32 dstate = I915_READ(D_STATE);
7497
7498 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7499 DSTATE_DOT_CLOCK_GATING;
7500 I915_WRITE(D_STATE, dstate);
7501}
7502
7503static void i85x_init_clock_gating(struct drm_device *dev)
7504{
7505 struct drm_i915_private *dev_priv = dev->dev_private;
7506
7507 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7508}
7509
7510static void i830_init_clock_gating(struct drm_device *dev)
7511{
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513
7514 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7515}
7516
645c62a5
JB		 7517static void ibx_init_clock_gating(struct drm_device *dev)
7518{
7519 struct drm_i915_private *dev_priv = dev->dev_private;
7520
7521 /*
7522 * On Ibex Peak and Cougar Point, we need to disable clock
7523 * gating for the panel power sequencer or it will fail to
7524 * start up when no ports are active.
7525 */
7526 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7527}
7528
7529static void cpt_init_clock_gating(struct drm_device *dev)
7530{
7531 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 7532 int pipe;
645c62a5
JB		 7533
7534 /*
7535 * On Ibex Peak and Cougar Point, we need to disable clock
7536 * gating for the panel power sequencer or it will fail to
7537 * start up when no ports are active.
7538 */
7539 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7540 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7541 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 7542 /* Without this, mode sets may fail silently on FDI */
7543 for_each_pipe(pipe)
7544 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 7545}
7546
ac668088 7547static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7548{
7549 struct drm_i915_private *dev_priv = dev->dev_private;
7550
7551 if (dev_priv->renderctx) {
ac668088
CW		 7552 i915_gem_object_unpin(dev_priv->renderctx);
7553 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7554 dev_priv->renderctx = NULL;
7555 }
7556
7557 if (dev_priv->pwrctx) {
ac668088
CW		 7558 i915_gem_object_unpin(dev_priv->pwrctx);
7559 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7560 dev_priv->pwrctx = NULL;
7561 }
7562}
7563
7564static void ironlake_disable_rc6(struct drm_device *dev)
7565{
7566 struct drm_i915_private *dev_priv = dev->dev_private;
7567
7568 if (I915_READ(PWRCTXA)) {
7569 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7570 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7571 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7572 50);
0cdab21f
CW		 7573
7574 I915_WRITE(PWRCTXA, 0);
7575 POSTING_READ(PWRCTXA);
7576
ac668088
CW		 7577 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7578 POSTING_READ(RSTDBYCTL);
0cdab21f 7579 }
ac668088 7580
99507307 7581 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7582}
7583
ac668088 7584static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7585{
7586 struct drm_i915_private *dev_priv = dev->dev_private;
7587
ac668088
CW		 7588 if (dev_priv->renderctx == NULL)
7589 dev_priv->renderctx = intel_alloc_context_page(dev);
7590 if (!dev_priv->renderctx)
7591 return -ENOMEM;
7592
7593 if (dev_priv->pwrctx == NULL)
7594 dev_priv->pwrctx = intel_alloc_context_page(dev);
7595 if (!dev_priv->pwrctx) {
7596 ironlake_teardown_rc6(dev);
7597 return -ENOMEM;
7598 }
7599
7600 return 0;
d5bb081b
JB		 7601}
7602
7603void ironlake_enable_rc6(struct drm_device *dev)
7604{
7605 struct drm_i915_private *dev_priv = dev->dev_private;
7606 int ret;
7607
ac668088
CW		 7608 /* rc6 disabled by default due to repeated reports of hanging during
7609 * boot and resume.
7610 */
7611 if (!i915_enable_rc6)
7612 return;
7613
2c34b850 7614 mutex_lock(&dev->struct_mutex);
ac668088 7615 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7616 if (ret) {
7617 mutex_unlock(&dev->struct_mutex);
ac668088 7618 return;
2c34b850 7619 }
ac668088 7620
d5bb081b
JB		 7621 /*
7622 * GPU can automatically power down the render unit if given a page
7623 * to save state.
7624 */
7625 ret = BEGIN_LP_RING(6);
7626 if (ret) {
ac668088 7627 ironlake_teardown_rc6(dev);
2c34b850 7628 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7629 return;
7630 }
ac668088 7631
d5bb081b
JB		 7632 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7633 OUT_RING(MI_SET_CONTEXT);
7634 OUT_RING(dev_priv->renderctx->gtt_offset |
7635 MI_MM_SPACE_GTT |
7636 MI_SAVE_EXT_STATE_EN |
7637 MI_RESTORE_EXT_STATE_EN |
7638 MI_RESTORE_INHIBIT);
7639 OUT_RING(MI_SUSPEND_FLUSH);
7640 OUT_RING(MI_NOOP);
7641 OUT_RING(MI_FLUSH);
7642 ADVANCE_LP_RING();
7643
4a246cfc
BW		 7644 /*
7645 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7646 * does an implicit flush, combined with MI_FLUSH above, it should be
7647 * safe to assume that renderctx is valid
7648 */
7649 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7650 if (ret) {
7651 DRM_ERROR("failed to enable ironlake power power savings\n");
7652 ironlake_teardown_rc6(dev);
7653 mutex_unlock(&dev->struct_mutex);
7654 return;
7655 }
7656
d5bb081b
JB		 7657 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7658 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7659 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7660}
7661
645c62a5
JB		 7662void intel_init_clock_gating(struct drm_device *dev)
7663{
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665
7666 dev_priv->display.init_clock_gating(dev);
7667
7668 if (dev_priv->display.init_pch_clock_gating)
7669 dev_priv->display.init_pch_clock_gating(dev);
7670}
ac668088 7671
e70236a8
JB		 7672/* Set up chip specific display functions */
7673static void intel_init_display(struct drm_device *dev)
7674{
7675 struct drm_i915_private *dev_priv = dev->dev_private;
7676
7677 /* We always want a DPMS function */
f564048e 7678 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7679 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7680 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7681 } else {
e70236a8 7682 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7683 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7684 }
e70236a8 7685
ee5382ae 7686 if (I915_HAS_FBC(dev)) {
9c04f015 7687 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7688 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7689 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7690 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7691 } else if (IS_GM45(dev)) {
74dff282
JB		 7692 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7693 dev_priv->display.enable_fbc = g4x_enable_fbc;
7694 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7695 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7696 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7697 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7698 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7699 }
74dff282 7700 /* 855GM needs testing */
e70236a8
JB		 7701 }
7702
7703 /* Returns the core display clock speed */
f2b115e6 7704 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7705 dev_priv->display.get_display_clock_speed =
7706 i945_get_display_clock_speed;
7707 else if (IS_I915G(dev))
7708 dev_priv->display.get_display_clock_speed =
7709 i915_get_display_clock_speed;
f2b115e6 7710 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7711 dev_priv->display.get_display_clock_speed =
7712 i9xx_misc_get_display_clock_speed;
7713 else if (IS_I915GM(dev))
7714 dev_priv->display.get_display_clock_speed =
7715 i915gm_get_display_clock_speed;
7716 else if (IS_I865G(dev))
7717 dev_priv->display.get_display_clock_speed =
7718 i865_get_display_clock_speed;
f0f8a9ce 7719 else if (IS_I85X(dev))
e70236a8
JB		 7720 dev_priv->display.get_display_clock_speed =
7721 i855_get_display_clock_speed;
7722 else /* 852, 830 */
7723 dev_priv->display.get_display_clock_speed =
7724 i830_get_display_clock_speed;
7725
7726 /* For FIFO watermark updates */
7f8a8569 7727 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7728 if (HAS_PCH_IBX(dev))
7729 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7730 else if (HAS_PCH_CPT(dev))
7731 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7732
f00a3ddf 7733 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7734 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7735 dev_priv->display.update_wm = ironlake_update_wm;
7736 else {
7737 DRM_DEBUG_KMS("Failed to get proper latency. "
7738 "Disable CxSR\n");
7739 dev_priv->display.update_wm = NULL;
1398261a 7740 }
674cf967 7741 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7742 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7743 } else if (IS_GEN6(dev)) {
7744 if (SNB_READ_WM0_LATENCY()) {
7745 dev_priv->display.update_wm = sandybridge_update_wm;
7746 } else {
7747 DRM_DEBUG_KMS("Failed to read display plane latency. "
7748 "Disable CxSR\n");
7749 dev_priv->display.update_wm = NULL;
7f8a8569 7750 }
674cf967 7751 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7752 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7753 } else if (IS_IVYBRIDGE(dev)) {
7754 /* FIXME: detect B0+ stepping and use auto training */
7755 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7756 if (SNB_READ_WM0_LATENCY()) {
7757 dev_priv->display.update_wm = sandybridge_update_wm;
7758 } else {
7759 DRM_DEBUG_KMS("Failed to read display plane latency. "
7760 "Disable CxSR\n");
7761 dev_priv->display.update_wm = NULL;
7762 }
28963a3e 7763 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7764
7f8a8569
ZW		 7765 } else
7766 dev_priv->display.update_wm = NULL;
7767 } else if (IS_PINEVIEW(dev)) {
d4294342 7768 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7769 dev_priv->is_ddr3,
d4294342
ZY		 7770 dev_priv->fsb_freq,
7771 dev_priv->mem_freq)) {
7772 DRM_INFO("failed to find known CxSR latency "
95534263 7773 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7774 "disabling CxSR\n",
95534263 7775 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7776 dev_priv->fsb_freq, dev_priv->mem_freq);
7777 /* Disable CxSR and never update its watermark again */
7778 pineview_disable_cxsr(dev);
7779 dev_priv->display.update_wm = NULL;
7780 } else
7781 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7782 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7783 } else if (IS_G4X(dev)) {
e70236a8 7784 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7785 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7786 } else if (IS_GEN4(dev)) {
e70236a8 7787 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7788 if (IS_CRESTLINE(dev))
7789 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7790 else if (IS_BROADWATER(dev))
7791 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7792 } else if (IS_GEN3(dev)) {
e70236a8
JB		 7793 dev_priv->display.update_wm = i9xx_update_wm;
7794 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 7795 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7796 } else if (IS_I865G(dev)) {
7797 dev_priv->display.update_wm = i830_update_wm;
7798 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7799 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 7800 } else if (IS_I85X(dev)) {
7801 dev_priv->display.update_wm = i9xx_update_wm;
7802 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 7803 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 7804 } else {
8f4695ed 7805 dev_priv->display.update_wm = i830_update_wm;
6067aaea 7806 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 7807 if (IS_845G(dev))
e70236a8
JB		 7808 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7809 else
7810 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 7811 }
8c9f3aaf
JB		 7812
7813 /* Default just returns -ENODEV to indicate unsupported */
7814 dev_priv->display.queue_flip = intel_default_queue_flip;
7815
7816 switch (INTEL_INFO(dev)->gen) {
7817 case 2:
7818 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7819 break;
7820
7821 case 3:
7822 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7823 break;
7824
7825 case 4:
7826 case 5:
7827 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7828 break;
7829
7830 case 6:
7831 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7832 break;
7c9017e5
JB		 7833 case 7:
7834 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7835 break;
8c9f3aaf 7836 }
e70236a8
JB		 7837}
7838
b690e96c
JB		 7839/*
7840 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7841 * resume, or other times. This quirk makes sure that's the case for
7842 * affected systems.
7843 */
7844static void quirk_pipea_force (struct drm_device *dev)
7845{
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847
7848 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7849 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7850}
7851
435793df
KP		 7852/*
7853 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7854 */
7855static void quirk_ssc_force_disable(struct drm_device *dev)
7856{
7857 struct drm_i915_private *dev_priv = dev->dev_private;
7858 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7859}
7860
b690e96c
JB		 7861struct intel_quirk {
7862 int device;
7863 int subsystem_vendor;
7864 int subsystem_device;
7865 void (*hook)(struct drm_device *dev);
7866};
7867
7868struct intel_quirk intel_quirks[] = {
7869 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7870 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7871 /* HP Mini needs pipe A force quirk (LP: #322104) */
7872 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7873
7874 /* Thinkpad R31 needs pipe A force quirk */
7875 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7876 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7877 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7878
7879 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7880 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7881 /* ThinkPad X40 needs pipe A force quirk */
7882
7883 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7884 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7885
7886 /* 855 & before need to leave pipe A & dpll A up */
7887 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7888 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7889
7890 /* Lenovo U160 cannot use SSC on LVDS */
7891 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
b690e96c
JB		 7892};
7893
7894static void intel_init_quirks(struct drm_device *dev)
7895{
7896 struct pci_dev *d = dev->pdev;
7897 int i;
7898
7899 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7900 struct intel_quirk *q = &intel_quirks[i];
7901
7902 if (d->device == q->device &&
7903 (d->subsystem_vendor == q->subsystem_vendor ||
7904 q->subsystem_vendor == PCI_ANY_ID) &&
7905 (d->subsystem_device == q->subsystem_device ||
7906 q->subsystem_device == PCI_ANY_ID))
7907 q->hook(dev);
7908 }
7909}
7910
9cce37f4
JB		 7911/* Disable the VGA plane that we never use */
7912static void i915_disable_vga(struct drm_device *dev)
7913{
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 u8 sr1;
7916 u32 vga_reg;
7917
7918 if (HAS_PCH_SPLIT(dev))
7919 vga_reg = CPU_VGACNTRL;
7920 else
7921 vga_reg = VGACNTRL;
7922
7923 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7924 outb(1, VGA_SR_INDEX);
7925 sr1 = inb(VGA_SR_DATA);
7926 outb(sr1 | 1<<5, VGA_SR_DATA);
7927 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7928 udelay(300);
7929
7930 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7931 POSTING_READ(vga_reg);
7932}
7933
79e53945
JB		 7934void intel_modeset_init(struct drm_device *dev)
7935{
652c393a 7936 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7937 int i;
7938
7939 drm_mode_config_init(dev);
7940
7941 dev->mode_config.min_width = 0;
7942 dev->mode_config.min_height = 0;
7943
7944 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7945
b690e96c
JB		 7946 intel_init_quirks(dev);
7947
e70236a8
JB		 7948 intel_init_display(dev);
7949
a6c45cf0
CW		 7950 if (IS_GEN2(dev)) {
7951 dev->mode_config.max_width = 2048;
7952 dev->mode_config.max_height = 2048;
7953 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7954 dev->mode_config.max_width = 4096;
7955 dev->mode_config.max_height = 4096;
79e53945 7956 } else {
a6c45cf0
CW		 7957 dev->mode_config.max_width = 8192;
7958 dev->mode_config.max_height = 8192;
79e53945 7959 }
35c3047a 7960 dev->mode_config.fb_base = dev->agp->base;
79e53945 7961
28c97730 7962 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7963 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7964
a3524f1b 7965 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7966 intel_crtc_init(dev, i);
7967 }
7968
9cce37f4
JB		 7969 /* Just disable it once at startup */
7970 i915_disable_vga(dev);
79e53945 7971 intel_setup_outputs(dev);
652c393a 7972
645c62a5 7973 intel_init_clock_gating(dev);
9cce37f4 7974
7648fa99 7975 if (IS_IRONLAKE_M(dev)) {
f97108d1 7976 ironlake_enable_drps(dev);
7648fa99
JB		 7977 intel_init_emon(dev);
7978 }
f97108d1 7979
3b8d8d91
JB		 7980 if (IS_GEN6(dev))
7981 gen6_enable_rps(dev_priv);
7982
652c393a
JB		 7983 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7984 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7985 (unsigned long)dev);
2c7111db
CW		 7986}
7987
7988void intel_modeset_gem_init(struct drm_device *dev)
7989{
7990 if (IS_IRONLAKE_M(dev))
7991 ironlake_enable_rc6(dev);
02e792fb
DV		 7992
7993 intel_setup_overlay(dev);
79e53945
JB		 7994}
7995
7996void intel_modeset_cleanup(struct drm_device *dev)
7997{
652c393a
JB		 7998 struct drm_i915_private *dev_priv = dev->dev_private;
7999 struct drm_crtc *crtc;
8000 struct intel_crtc *intel_crtc;
8001
f87ea761 8002 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8003 mutex_lock(&dev->struct_mutex);
8004
723bfd70
JB		 8005 intel_unregister_dsm_handler();
8006
8007
652c393a
JB		 8008 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8009 /* Skip inactive CRTCs */
8010 if (!crtc->fb)
8011 continue;
8012
8013 intel_crtc = to_intel_crtc(crtc);
3dec0095 8014 intel_increase_pllclock(crtc);
652c393a
JB		 8015 }
8016
e70236a8
JB		 8017 if (dev_priv->display.disable_fbc)
8018 dev_priv->display.disable_fbc(dev);
8019
f97108d1
JB		 8020 if (IS_IRONLAKE_M(dev))
8021 ironlake_disable_drps(dev);
3b8d8d91
JB		 8022 if (IS_GEN6(dev))
8023 gen6_disable_rps(dev);
f97108d1 8024
d5bb081b
JB		 8025 if (IS_IRONLAKE_M(dev))
8026 ironlake_disable_rc6(dev);
0cdab21f 8027
69341a5e
KH		 8028 mutex_unlock(&dev->struct_mutex);
8029
6c0d9350
DV		 8030 /* Disable the irq before mode object teardown, for the irq might
8031 * enqueue unpin/hotplug work. */
8032 drm_irq_uninstall(dev);
8033 cancel_work_sync(&dev_priv->hotplug_work);
8034
3dec0095
DV		 8035 /* Shut off idle work before the crtcs get freed. */
8036 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8037 intel_crtc = to_intel_crtc(crtc);
8038 del_timer_sync(&intel_crtc->idle_timer);
8039 }
8040 del_timer_sync(&dev_priv->idle_timer);
8041 cancel_work_sync(&dev_priv->idle_work);
8042
79e53945
JB		 8043 drm_mode_config_cleanup(dev);
8044}
8045
f1c79df3
ZW		 8046/*
8047 * Return which encoder is currently attached for connector.
8048 */
df0e9248 8049struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8050{
df0e9248
CW		 8051 return &intel_attached_encoder(connector)->base;
8052}
f1c79df3 8053
df0e9248
CW		 8054void intel_connector_attach_encoder(struct intel_connector *connector,
8055 struct intel_encoder *encoder)
8056{
8057 connector->encoder = encoder;
8058 drm_mode_connector_attach_encoder(&connector->base,
8059 &encoder->base);
79e53945 8060}
28d52043
DA		 8061
8062/*
8063 * set vga decode state - true == enable VGA decode
8064 */
8065int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8066{
8067 struct drm_i915_private *dev_priv = dev->dev_private;
8068 u16 gmch_ctrl;
8069
8070 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8071 if (state)
8072 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8073 else
8074 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8075 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8076 return 0;
8077}
c4a1d9e4
CW		 8078
8079#ifdef CONFIG_DEBUG_FS
8080#include <linux/seq_file.h>
8081
8082struct intel_display_error_state {
8083 struct intel_cursor_error_state {
8084 u32 control;
8085 u32 position;
8086 u32 base;
8087 u32 size;
8088 } cursor[2];
8089
8090 struct intel_pipe_error_state {
8091 u32 conf;
8092 u32 source;
8093
8094 u32 htotal;
8095 u32 hblank;
8096 u32 hsync;
8097 u32 vtotal;
8098 u32 vblank;
8099 u32 vsync;
8100 } pipe[2];
8101
8102 struct intel_plane_error_state {
8103 u32 control;
8104 u32 stride;
8105 u32 size;
8106 u32 pos;
8107 u32 addr;
8108 u32 surface;
8109 u32 tile_offset;
8110 } plane[2];
8111};
8112
8113struct intel_display_error_state *
8114intel_display_capture_error_state(struct drm_device *dev)
8115{
8116 drm_i915_private_t *dev_priv = dev->dev_private;
8117 struct intel_display_error_state *error;
8118 int i;
8119
8120 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8121 if (error == NULL)
8122 return NULL;
8123
8124 for (i = 0; i < 2; i++) {
8125 error->cursor[i].control = I915_READ(CURCNTR(i));
8126 error->cursor[i].position = I915_READ(CURPOS(i));
8127 error->cursor[i].base = I915_READ(CURBASE(i));
8128
8129 error->plane[i].control = I915_READ(DSPCNTR(i));
8130 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8131 error->plane[i].size = I915_READ(DSPSIZE(i));
8132 error->plane[i].pos= I915_READ(DSPPOS(i));
8133 error->plane[i].addr = I915_READ(DSPADDR(i));
8134 if (INTEL_INFO(dev)->gen >= 4) {
8135 error->plane[i].surface = I915_READ(DSPSURF(i));
8136 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8137 }
8138
8139 error->pipe[i].conf = I915_READ(PIPECONF(i));
8140 error->pipe[i].source = I915_READ(PIPESRC(i));
8141 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8142 error->pipe[i].hblank = I915_READ(HBLANK(i));
8143 error->pipe[i].hsync = I915_READ(HSYNC(i));
8144 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8145 error->pipe[i].vblank = I915_READ(VBLANK(i));
8146 error->pipe[i].vsync = I915_READ(VSYNC(i));
8147 }
8148
8149 return error;
8150}
8151
8152void
8153intel_display_print_error_state(struct seq_file *m,
8154 struct drm_device *dev,
8155 struct intel_display_error_state *error)
8156{
8157 int i;
8158
8159 for (i = 0; i < 2; i++) {
8160 seq_printf(m, "Pipe [%d]:\n", i);
8161 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8162 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8163 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8164 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8165 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8166 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8167 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8168 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8169
8170 seq_printf(m, "Plane [%d]:\n", i);
8171 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8172 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8173 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8174 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8175 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8176 if (INTEL_INFO(dev)->gen >= 4) {
8177 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8178 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8179 }
8180
8181 seq_printf(m, "Cursor [%d]:\n", i);
8182 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8183 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8184 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8185 }
8186}
8187#endif
Linux kernel - Deliverables
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