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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 47 | |
79e53945 | 48 | typedef struct { |
0206e353 | 49 | int min, max; |
79e53945 JB |
50 | } intel_range_t; |
51 | ||
52 | typedef struct { | |
0206e353 AJ |
53 | int dot_limit; |
54 | int p2_slow, p2_fast; | |
79e53945 JB |
55 | } intel_p2_t; |
56 | ||
57 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
58 | typedef struct intel_limit intel_limit_t; |
59 | struct intel_limit { | |
0206e353 AJ |
60 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
61 | intel_p2_t p2; | |
f4808ab8 VS |
62 | /** |
63 | * find_pll() - Find the best values for the PLL | |
64 | * @limit: limits for the PLL | |
65 | * @crtc: current CRTC | |
66 | * @target: target frequency in kHz | |
67 | * @refclk: reference clock frequency in kHz | |
68 | * @match_clock: if provided, @best_clock P divider must | |
69 | * match the P divider from @match_clock | |
70 | * used for LVDS downclocking | |
71 | * @best_clock: best PLL values found | |
72 | * | |
73 | * Returns true on success, false on failure. | |
74 | */ | |
75 | bool (*find_pll)(const intel_limit_t *limit, | |
76 | struct drm_crtc *crtc, | |
77 | int target, int refclk, | |
78 | intel_clock_t *match_clock, | |
79 | intel_clock_t *best_clock); | |
d4906093 | 80 | }; |
79e53945 | 81 | |
2377b741 JB |
82 | /* FDI */ |
83 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
84 | ||
d2acd215 DV |
85 | int |
86 | intel_pch_rawclk(struct drm_device *dev) | |
87 | { | |
88 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89 | ||
90 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
91 | ||
92 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
93 | } | |
94 | ||
d4906093 ML |
95 | static bool |
96 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
97 | int target, int refclk, intel_clock_t *match_clock, |
98 | intel_clock_t *best_clock); | |
d4906093 ML |
99 | static bool |
100 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
101 | int target, int refclk, intel_clock_t *match_clock, |
102 | intel_clock_t *best_clock); | |
79e53945 | 103 | |
a0c4da24 JB |
104 | static bool |
105 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
106 | int target, int refclk, intel_clock_t *match_clock, | |
107 | intel_clock_t *best_clock); | |
108 | ||
021357ac CW |
109 | static inline u32 /* units of 100MHz */ |
110 | intel_fdi_link_freq(struct drm_device *dev) | |
111 | { | |
8b99e68c CW |
112 | if (IS_GEN5(dev)) { |
113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
114 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
115 | } else | |
116 | return 27; | |
021357ac CW |
117 | } |
118 | ||
e4b36699 | 119 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
120 | .dot = { .min = 25000, .max = 350000 }, |
121 | .vco = { .min = 930000, .max = 1400000 }, | |
122 | .n = { .min = 3, .max = 16 }, | |
123 | .m = { .min = 96, .max = 140 }, | |
124 | .m1 = { .min = 18, .max = 26 }, | |
125 | .m2 = { .min = 6, .max = 16 }, | |
126 | .p = { .min = 4, .max = 128 }, | |
127 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
128 | .p2 = { .dot_limit = 165000, |
129 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 130 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
131 | }; |
132 | ||
133 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
134 | .dot = { .min = 25000, .max = 350000 }, |
135 | .vco = { .min = 930000, .max = 1400000 }, | |
136 | .n = { .min = 3, .max = 16 }, | |
137 | .m = { .min = 96, .max = 140 }, | |
138 | .m1 = { .min = 18, .max = 26 }, | |
139 | .m2 = { .min = 6, .max = 16 }, | |
140 | .p = { .min = 4, .max = 128 }, | |
141 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
142 | .p2 = { .dot_limit = 165000, |
143 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 144 | .find_pll = intel_find_best_PLL, |
e4b36699 | 145 | }; |
273e27ca | 146 | |
e4b36699 | 147 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
148 | .dot = { .min = 20000, .max = 400000 }, |
149 | .vco = { .min = 1400000, .max = 2800000 }, | |
150 | .n = { .min = 1, .max = 6 }, | |
151 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
152 | .m1 = { .min = 8, .max = 18 }, |
153 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
154 | .p = { .min = 5, .max = 80 }, |
155 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
156 | .p2 = { .dot_limit = 200000, |
157 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 158 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
159 | }; |
160 | ||
161 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
162 | .dot = { .min = 20000, .max = 400000 }, |
163 | .vco = { .min = 1400000, .max = 2800000 }, | |
164 | .n = { .min = 1, .max = 6 }, | |
165 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
166 | .m1 = { .min = 8, .max = 18 }, |
167 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
168 | .p = { .min = 7, .max = 98 }, |
169 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
170 | .p2 = { .dot_limit = 112000, |
171 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 172 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
173 | }; |
174 | ||
273e27ca | 175 | |
e4b36699 | 176 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
177 | .dot = { .min = 25000, .max = 270000 }, |
178 | .vco = { .min = 1750000, .max = 3500000}, | |
179 | .n = { .min = 1, .max = 4 }, | |
180 | .m = { .min = 104, .max = 138 }, | |
181 | .m1 = { .min = 17, .max = 23 }, | |
182 | .m2 = { .min = 5, .max = 11 }, | |
183 | .p = { .min = 10, .max = 30 }, | |
184 | .p1 = { .min = 1, .max = 3}, | |
185 | .p2 = { .dot_limit = 270000, | |
186 | .p2_slow = 10, | |
187 | .p2_fast = 10 | |
044c7c41 | 188 | }, |
d4906093 | 189 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
190 | }; |
191 | ||
192 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
193 | .dot = { .min = 22000, .max = 400000 }, |
194 | .vco = { .min = 1750000, .max = 3500000}, | |
195 | .n = { .min = 1, .max = 4 }, | |
196 | .m = { .min = 104, .max = 138 }, | |
197 | .m1 = { .min = 16, .max = 23 }, | |
198 | .m2 = { .min = 5, .max = 11 }, | |
199 | .p = { .min = 5, .max = 80 }, | |
200 | .p1 = { .min = 1, .max = 8}, | |
201 | .p2 = { .dot_limit = 165000, | |
202 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 203 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
204 | }; |
205 | ||
206 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
207 | .dot = { .min = 20000, .max = 115000 }, |
208 | .vco = { .min = 1750000, .max = 3500000 }, | |
209 | .n = { .min = 1, .max = 3 }, | |
210 | .m = { .min = 104, .max = 138 }, | |
211 | .m1 = { .min = 17, .max = 23 }, | |
212 | .m2 = { .min = 5, .max = 11 }, | |
213 | .p = { .min = 28, .max = 112 }, | |
214 | .p1 = { .min = 2, .max = 8 }, | |
215 | .p2 = { .dot_limit = 0, | |
216 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 217 | }, |
d4906093 | 218 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
219 | }; |
220 | ||
221 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
222 | .dot = { .min = 80000, .max = 224000 }, |
223 | .vco = { .min = 1750000, .max = 3500000 }, | |
224 | .n = { .min = 1, .max = 3 }, | |
225 | .m = { .min = 104, .max = 138 }, | |
226 | .m1 = { .min = 17, .max = 23 }, | |
227 | .m2 = { .min = 5, .max = 11 }, | |
228 | .p = { .min = 14, .max = 42 }, | |
229 | .p1 = { .min = 2, .max = 6 }, | |
230 | .p2 = { .dot_limit = 0, | |
231 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 232 | }, |
d4906093 | 233 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
234 | }; |
235 | ||
f2b115e6 | 236 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
237 | .dot = { .min = 20000, .max = 400000}, |
238 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 239 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
240 | .n = { .min = 3, .max = 6 }, |
241 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 242 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
243 | .m1 = { .min = 0, .max = 0 }, |
244 | .m2 = { .min = 0, .max = 254 }, | |
245 | .p = { .min = 5, .max = 80 }, | |
246 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 200000, |
248 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 249 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
250 | }; |
251 | ||
f2b115e6 | 252 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
253 | .dot = { .min = 20000, .max = 400000 }, |
254 | .vco = { .min = 1700000, .max = 3500000 }, | |
255 | .n = { .min = 3, .max = 6 }, | |
256 | .m = { .min = 2, .max = 256 }, | |
257 | .m1 = { .min = 0, .max = 0 }, | |
258 | .m2 = { .min = 0, .max = 254 }, | |
259 | .p = { .min = 7, .max = 112 }, | |
260 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
261 | .p2 = { .dot_limit = 112000, |
262 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 263 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
264 | }; |
265 | ||
273e27ca EA |
266 | /* Ironlake / Sandybridge |
267 | * | |
268 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
269 | * the range value for them is (actual_value - 2). | |
270 | */ | |
b91ad0ec | 271 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
272 | .dot = { .min = 25000, .max = 350000 }, |
273 | .vco = { .min = 1760000, .max = 3510000 }, | |
274 | .n = { .min = 1, .max = 5 }, | |
275 | .m = { .min = 79, .max = 127 }, | |
276 | .m1 = { .min = 12, .max = 22 }, | |
277 | .m2 = { .min = 5, .max = 9 }, | |
278 | .p = { .min = 5, .max = 80 }, | |
279 | .p1 = { .min = 1, .max = 8 }, | |
280 | .p2 = { .dot_limit = 225000, | |
281 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 282 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
283 | }; |
284 | ||
b91ad0ec | 285 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
286 | .dot = { .min = 25000, .max = 350000 }, |
287 | .vco = { .min = 1760000, .max = 3510000 }, | |
288 | .n = { .min = 1, .max = 3 }, | |
289 | .m = { .min = 79, .max = 118 }, | |
290 | .m1 = { .min = 12, .max = 22 }, | |
291 | .m2 = { .min = 5, .max = 9 }, | |
292 | .p = { .min = 28, .max = 112 }, | |
293 | .p1 = { .min = 2, .max = 8 }, | |
294 | .p2 = { .dot_limit = 225000, | |
295 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
296 | .find_pll = intel_g4x_find_best_PLL, |
297 | }; | |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 127 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 56 }, | |
307 | .p1 = { .min = 2, .max = 8 }, | |
308 | .p2 = { .dot_limit = 225000, | |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
310 | .find_pll = intel_g4x_find_best_PLL, |
311 | }; | |
312 | ||
273e27ca | 313 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 314 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
315 | .dot = { .min = 25000, .max = 350000 }, |
316 | .vco = { .min = 1760000, .max = 3510000 }, | |
317 | .n = { .min = 1, .max = 2 }, | |
318 | .m = { .min = 79, .max = 126 }, | |
319 | .m1 = { .min = 12, .max = 22 }, | |
320 | .m2 = { .min = 5, .max = 9 }, | |
321 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 322 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
323 | .p2 = { .dot_limit = 225000, |
324 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
325 | .find_pll = intel_g4x_find_best_PLL, |
326 | }; | |
327 | ||
328 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 350000 }, |
330 | .vco = { .min = 1760000, .max = 3510000 }, | |
331 | .n = { .min = 1, .max = 3 }, | |
332 | .m = { .min = 79, .max = 126 }, | |
333 | .m1 = { .min = 12, .max = 22 }, | |
334 | .m2 = { .min = 5, .max = 9 }, | |
335 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 336 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
337 | .p2 = { .dot_limit = 225000, |
338 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
339 | .find_pll = intel_g4x_find_best_PLL, |
340 | }; | |
341 | ||
a0c4da24 JB |
342 | static const intel_limit_t intel_limits_vlv_dac = { |
343 | .dot = { .min = 25000, .max = 270000 }, | |
344 | .vco = { .min = 4000000, .max = 6000000 }, | |
345 | .n = { .min = 1, .max = 7 }, | |
346 | .m = { .min = 22, .max = 450 }, /* guess */ | |
347 | .m1 = { .min = 2, .max = 3 }, | |
348 | .m2 = { .min = 11, .max = 156 }, | |
349 | .p = { .min = 10, .max = 30 }, | |
75e53986 | 350 | .p1 = { .min = 1, .max = 3 }, |
a0c4da24 JB |
351 | .p2 = { .dot_limit = 270000, |
352 | .p2_slow = 2, .p2_fast = 20 }, | |
353 | .find_pll = intel_vlv_find_best_pll, | |
354 | }; | |
355 | ||
356 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
75e53986 DV |
357 | .dot = { .min = 25000, .max = 270000 }, |
358 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 JB |
359 | .n = { .min = 1, .max = 7 }, |
360 | .m = { .min = 60, .max = 300 }, /* guess */ | |
361 | .m1 = { .min = 2, .max = 3 }, | |
362 | .m2 = { .min = 11, .max = 156 }, | |
363 | .p = { .min = 10, .max = 30 }, | |
364 | .p1 = { .min = 2, .max = 3 }, | |
365 | .p2 = { .dot_limit = 270000, | |
366 | .p2_slow = 2, .p2_fast = 20 }, | |
367 | .find_pll = intel_vlv_find_best_pll, | |
368 | }; | |
369 | ||
370 | static const intel_limit_t intel_limits_vlv_dp = { | |
74a4dd2e VP |
371 | .dot = { .min = 25000, .max = 270000 }, |
372 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 373 | .n = { .min = 1, .max = 7 }, |
74a4dd2e | 374 | .m = { .min = 22, .max = 450 }, |
a0c4da24 JB |
375 | .m1 = { .min = 2, .max = 3 }, |
376 | .m2 = { .min = 11, .max = 156 }, | |
377 | .p = { .min = 10, .max = 30 }, | |
75e53986 | 378 | .p1 = { .min = 1, .max = 3 }, |
a0c4da24 JB |
379 | .p2 = { .dot_limit = 270000, |
380 | .p2_slow = 2, .p2_fast = 20 }, | |
381 | .find_pll = intel_vlv_find_best_pll, | |
382 | }; | |
383 | ||
57f350b6 JB |
384 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
385 | { | |
09153000 | 386 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
57f350b6 | 387 | |
57f350b6 JB |
388 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
389 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 390 | return 0; |
57f350b6 JB |
391 | } |
392 | ||
393 | I915_WRITE(DPIO_REG, reg); | |
394 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
395 | DPIO_BYTE); | |
396 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
397 | DRM_ERROR("DPIO read wait timed out\n"); | |
09153000 | 398 | return 0; |
57f350b6 | 399 | } |
57f350b6 | 400 | |
09153000 | 401 | return I915_READ(DPIO_DATA); |
57f350b6 JB |
402 | } |
403 | ||
e2fa6fba | 404 | void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) |
a0c4da24 | 405 | { |
09153000 | 406 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a0c4da24 | 407 | |
a0c4da24 JB |
408 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
409 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 410 | return; |
a0c4da24 JB |
411 | } |
412 | ||
413 | I915_WRITE(DPIO_DATA, val); | |
414 | I915_WRITE(DPIO_REG, reg); | |
415 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
416 | DPIO_BYTE); | |
417 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
418 | DRM_ERROR("DPIO write wait timed out\n"); | |
a0c4da24 JB |
419 | } |
420 | ||
1b894b59 CW |
421 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
422 | int refclk) | |
2c07245f | 423 | { |
b91ad0ec | 424 | struct drm_device *dev = crtc->dev; |
2c07245f | 425 | const intel_limit_t *limit; |
b91ad0ec ZW |
426 | |
427 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 428 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 429 | if (refclk == 100000) |
b91ad0ec ZW |
430 | limit = &intel_limits_ironlake_dual_lvds_100m; |
431 | else | |
432 | limit = &intel_limits_ironlake_dual_lvds; | |
433 | } else { | |
1b894b59 | 434 | if (refclk == 100000) |
b91ad0ec ZW |
435 | limit = &intel_limits_ironlake_single_lvds_100m; |
436 | else | |
437 | limit = &intel_limits_ironlake_single_lvds; | |
438 | } | |
c6bb3538 | 439 | } else |
b91ad0ec | 440 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
441 | |
442 | return limit; | |
443 | } | |
444 | ||
044c7c41 ML |
445 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
446 | { | |
447 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
448 | const intel_limit_t *limit; |
449 | ||
450 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 451 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 452 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 453 | else |
e4b36699 | 454 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
455 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
456 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 457 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 458 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 459 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 460 | } else /* The option is for other outputs */ |
e4b36699 | 461 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
462 | |
463 | return limit; | |
464 | } | |
465 | ||
1b894b59 | 466 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
467 | { |
468 | struct drm_device *dev = crtc->dev; | |
469 | const intel_limit_t *limit; | |
470 | ||
bad720ff | 471 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 472 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 473 | else if (IS_G4X(dev)) { |
044c7c41 | 474 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 475 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 476 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 477 | limit = &intel_limits_pineview_lvds; |
2177832f | 478 | else |
f2b115e6 | 479 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
480 | } else if (IS_VALLEYVIEW(dev)) { |
481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
482 | limit = &intel_limits_vlv_dac; | |
483 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
484 | limit = &intel_limits_vlv_hdmi; | |
485 | else | |
486 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
487 | } else if (!IS_GEN2(dev)) { |
488 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
489 | limit = &intel_limits_i9xx_lvds; | |
490 | else | |
491 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
492 | } else { |
493 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 494 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 495 | else |
e4b36699 | 496 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
497 | } |
498 | return limit; | |
499 | } | |
500 | ||
f2b115e6 AJ |
501 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
502 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 503 | { |
2177832f SL |
504 | clock->m = clock->m2 + 2; |
505 | clock->p = clock->p1 * clock->p2; | |
506 | clock->vco = refclk * clock->m / clock->n; | |
507 | clock->dot = clock->vco / clock->p; | |
508 | } | |
509 | ||
7429e9d4 DV |
510 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
511 | { | |
512 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
513 | } | |
514 | ||
2177832f SL |
515 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) |
516 | { | |
f2b115e6 AJ |
517 | if (IS_PINEVIEW(dev)) { |
518 | pineview_clock(refclk, clock); | |
2177832f SL |
519 | return; |
520 | } | |
7429e9d4 | 521 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 JB |
522 | clock->p = clock->p1 * clock->p2; |
523 | clock->vco = refclk * clock->m / (clock->n + 2); | |
524 | clock->dot = clock->vco / clock->p; | |
525 | } | |
526 | ||
79e53945 JB |
527 | /** |
528 | * Returns whether any output on the specified pipe is of the specified type | |
529 | */ | |
4ef69c7a | 530 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 531 | { |
4ef69c7a | 532 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
533 | struct intel_encoder *encoder; |
534 | ||
6c2b7c12 DV |
535 | for_each_encoder_on_crtc(dev, crtc, encoder) |
536 | if (encoder->type == type) | |
4ef69c7a CW |
537 | return true; |
538 | ||
539 | return false; | |
79e53945 JB |
540 | } |
541 | ||
7c04d1d9 | 542 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
543 | /** |
544 | * Returns whether the given set of divisors are valid for a given refclk with | |
545 | * the given connectors. | |
546 | */ | |
547 | ||
1b894b59 CW |
548 | static bool intel_PLL_is_valid(struct drm_device *dev, |
549 | const intel_limit_t *limit, | |
550 | const intel_clock_t *clock) | |
79e53945 | 551 | { |
79e53945 | 552 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 553 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 554 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 555 | INTELPllInvalid("p out of range\n"); |
79e53945 | 556 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 557 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 558 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 559 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 560 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 561 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 562 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 563 | INTELPllInvalid("m out of range\n"); |
79e53945 | 564 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 565 | INTELPllInvalid("n out of range\n"); |
79e53945 | 566 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 567 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
568 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
569 | * connector, etc., rather than just a single range. | |
570 | */ | |
571 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 572 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
573 | |
574 | return true; | |
575 | } | |
576 | ||
d4906093 ML |
577 | static bool |
578 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
579 | int target, int refclk, intel_clock_t *match_clock, |
580 | intel_clock_t *best_clock) | |
d4906093 | 581 | |
79e53945 JB |
582 | { |
583 | struct drm_device *dev = crtc->dev; | |
79e53945 | 584 | intel_clock_t clock; |
79e53945 JB |
585 | int err = target; |
586 | ||
a210b028 | 587 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 588 | /* |
a210b028 DV |
589 | * For LVDS just rely on its current settings for dual-channel. |
590 | * We haven't figured out how to reliably set up different | |
591 | * single/dual channel state, if we even can. | |
79e53945 | 592 | */ |
1974cad0 | 593 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
594 | clock.p2 = limit->p2.p2_fast; |
595 | else | |
596 | clock.p2 = limit->p2.p2_slow; | |
597 | } else { | |
598 | if (target < limit->p2.dot_limit) | |
599 | clock.p2 = limit->p2.p2_slow; | |
600 | else | |
601 | clock.p2 = limit->p2.p2_fast; | |
602 | } | |
603 | ||
0206e353 | 604 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 605 | |
42158660 ZY |
606 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
607 | clock.m1++) { | |
608 | for (clock.m2 = limit->m2.min; | |
609 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
610 | /* m1 is always 0 in Pineview */ |
611 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
612 | break; |
613 | for (clock.n = limit->n.min; | |
614 | clock.n <= limit->n.max; clock.n++) { | |
615 | for (clock.p1 = limit->p1.min; | |
616 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
617 | int this_err; |
618 | ||
2177832f | 619 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
620 | if (!intel_PLL_is_valid(dev, limit, |
621 | &clock)) | |
79e53945 | 622 | continue; |
cec2f356 SP |
623 | if (match_clock && |
624 | clock.p != match_clock->p) | |
625 | continue; | |
79e53945 JB |
626 | |
627 | this_err = abs(clock.dot - target); | |
628 | if (this_err < err) { | |
629 | *best_clock = clock; | |
630 | err = this_err; | |
631 | } | |
632 | } | |
633 | } | |
634 | } | |
635 | } | |
636 | ||
637 | return (err != target); | |
638 | } | |
639 | ||
d4906093 ML |
640 | static bool |
641 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
642 | int target, int refclk, intel_clock_t *match_clock, |
643 | intel_clock_t *best_clock) | |
d4906093 ML |
644 | { |
645 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
646 | intel_clock_t clock; |
647 | int max_n; | |
648 | bool found; | |
6ba770dc AJ |
649 | /* approximately equals target * 0.00585 */ |
650 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
651 | found = false; |
652 | ||
653 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
654 | int lvds_reg; |
655 | ||
c619eed4 | 656 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
657 | lvds_reg = PCH_LVDS; |
658 | else | |
659 | lvds_reg = LVDS; | |
1974cad0 | 660 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
661 | clock.p2 = limit->p2.p2_fast; |
662 | else | |
663 | clock.p2 = limit->p2.p2_slow; | |
664 | } else { | |
665 | if (target < limit->p2.dot_limit) | |
666 | clock.p2 = limit->p2.p2_slow; | |
667 | else | |
668 | clock.p2 = limit->p2.p2_fast; | |
669 | } | |
670 | ||
671 | memset(best_clock, 0, sizeof(*best_clock)); | |
672 | max_n = limit->n.max; | |
f77f13e2 | 673 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 674 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 675 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
676 | for (clock.m1 = limit->m1.max; |
677 | clock.m1 >= limit->m1.min; clock.m1--) { | |
678 | for (clock.m2 = limit->m2.max; | |
679 | clock.m2 >= limit->m2.min; clock.m2--) { | |
680 | for (clock.p1 = limit->p1.max; | |
681 | clock.p1 >= limit->p1.min; clock.p1--) { | |
682 | int this_err; | |
683 | ||
2177832f | 684 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
685 | if (!intel_PLL_is_valid(dev, limit, |
686 | &clock)) | |
d4906093 | 687 | continue; |
1b894b59 CW |
688 | |
689 | this_err = abs(clock.dot - target); | |
d4906093 ML |
690 | if (this_err < err_most) { |
691 | *best_clock = clock; | |
692 | err_most = this_err; | |
693 | max_n = clock.n; | |
694 | found = true; | |
695 | } | |
696 | } | |
697 | } | |
698 | } | |
699 | } | |
2c07245f ZW |
700 | return found; |
701 | } | |
702 | ||
a0c4da24 JB |
703 | static bool |
704 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
705 | int target, int refclk, intel_clock_t *match_clock, | |
706 | intel_clock_t *best_clock) | |
707 | { | |
708 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
709 | u32 m, n, fastclk; | |
710 | u32 updrate, minupdate, fracbits, p; | |
711 | unsigned long bestppm, ppm, absppm; | |
712 | int dotclk, flag; | |
713 | ||
af447bd3 | 714 | flag = 0; |
a0c4da24 JB |
715 | dotclk = target * 1000; |
716 | bestppm = 1000000; | |
717 | ppm = absppm = 0; | |
718 | fastclk = dotclk / (2*100); | |
719 | updrate = 0; | |
720 | minupdate = 19200; | |
721 | fracbits = 1; | |
722 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
723 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
724 | ||
725 | /* based on hardware requirement, prefer smaller n to precision */ | |
726 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
727 | updrate = refclk / n; | |
728 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
729 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
730 | if (p2 > 10) | |
731 | p2 = p2 - 1; | |
732 | p = p1 * p2; | |
733 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
734 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
735 | m2 = (((2*(fastclk * p * n / m1 )) + | |
736 | refclk) / (2*refclk)); | |
737 | m = m1 * m2; | |
738 | vco = updrate * m; | |
739 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
740 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
741 | absppm = (ppm > 0) ? ppm : (-ppm); | |
742 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
743 | bestppm = 0; | |
744 | flag = 1; | |
745 | } | |
746 | if (absppm < bestppm - 10) { | |
747 | bestppm = absppm; | |
748 | flag = 1; | |
749 | } | |
750 | if (flag) { | |
751 | bestn = n; | |
752 | bestm1 = m1; | |
753 | bestm2 = m2; | |
754 | bestp1 = p1; | |
755 | bestp2 = p2; | |
756 | flag = 0; | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | } | |
762 | } | |
763 | best_clock->n = bestn; | |
764 | best_clock->m1 = bestm1; | |
765 | best_clock->m2 = bestm2; | |
766 | best_clock->p1 = bestp1; | |
767 | best_clock->p2 = bestp2; | |
768 | ||
769 | return true; | |
770 | } | |
a4fc5ed6 | 771 | |
a5c961d1 PZ |
772 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
773 | enum pipe pipe) | |
774 | { | |
775 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
777 | ||
3b117c8f | 778 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
779 | } |
780 | ||
a928d536 PZ |
781 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
782 | { | |
783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
784 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
785 | ||
786 | frame = I915_READ(frame_reg); | |
787 | ||
788 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
789 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
790 | } | |
791 | ||
9d0498a2 JB |
792 | /** |
793 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
794 | * @dev: drm device | |
795 | * @pipe: pipe to wait for | |
796 | * | |
797 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
798 | * mode setting code. | |
799 | */ | |
800 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 801 | { |
9d0498a2 | 802 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 803 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 804 | |
a928d536 PZ |
805 | if (INTEL_INFO(dev)->gen >= 5) { |
806 | ironlake_wait_for_vblank(dev, pipe); | |
807 | return; | |
808 | } | |
809 | ||
300387c0 CW |
810 | /* Clear existing vblank status. Note this will clear any other |
811 | * sticky status fields as well. | |
812 | * | |
813 | * This races with i915_driver_irq_handler() with the result | |
814 | * that either function could miss a vblank event. Here it is not | |
815 | * fatal, as we will either wait upon the next vblank interrupt or | |
816 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
817 | * called during modeset at which time the GPU should be idle and | |
818 | * should *not* be performing page flips and thus not waiting on | |
819 | * vblanks... | |
820 | * Currently, the result of us stealing a vblank from the irq | |
821 | * handler is that a single frame will be skipped during swapbuffers. | |
822 | */ | |
823 | I915_WRITE(pipestat_reg, | |
824 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
825 | ||
9d0498a2 | 826 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
827 | if (wait_for(I915_READ(pipestat_reg) & |
828 | PIPE_VBLANK_INTERRUPT_STATUS, | |
829 | 50)) | |
9d0498a2 JB |
830 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
831 | } | |
832 | ||
ab7ad7f6 KP |
833 | /* |
834 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
835 | * @dev: drm device |
836 | * @pipe: pipe to wait for | |
837 | * | |
838 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
839 | * spinning on the vblank interrupt status bit, since we won't actually | |
840 | * see an interrupt when the pipe is disabled. | |
841 | * | |
ab7ad7f6 KP |
842 | * On Gen4 and above: |
843 | * wait for the pipe register state bit to turn off | |
844 | * | |
845 | * Otherwise: | |
846 | * wait for the display line value to settle (it usually | |
847 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 848 | * |
9d0498a2 | 849 | */ |
58e10eb9 | 850 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
851 | { |
852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
853 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
854 | pipe); | |
ab7ad7f6 KP |
855 | |
856 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 857 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
858 | |
859 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
860 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
861 | 100)) | |
284637d9 | 862 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 863 | } else { |
837ba00f | 864 | u32 last_line, line_mask; |
58e10eb9 | 865 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
866 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
867 | ||
837ba00f PZ |
868 | if (IS_GEN2(dev)) |
869 | line_mask = DSL_LINEMASK_GEN2; | |
870 | else | |
871 | line_mask = DSL_LINEMASK_GEN3; | |
872 | ||
ab7ad7f6 KP |
873 | /* Wait for the display line to settle */ |
874 | do { | |
837ba00f | 875 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 876 | mdelay(5); |
837ba00f | 877 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
878 | time_after(timeout, jiffies)); |
879 | if (time_after(jiffies, timeout)) | |
284637d9 | 880 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 881 | } |
79e53945 JB |
882 | } |
883 | ||
b0ea7d37 DL |
884 | /* |
885 | * ibx_digital_port_connected - is the specified port connected? | |
886 | * @dev_priv: i915 private structure | |
887 | * @port: the port to test | |
888 | * | |
889 | * Returns true if @port is connected, false otherwise. | |
890 | */ | |
891 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
892 | struct intel_digital_port *port) | |
893 | { | |
894 | u32 bit; | |
895 | ||
c36346e3 DL |
896 | if (HAS_PCH_IBX(dev_priv->dev)) { |
897 | switch(port->port) { | |
898 | case PORT_B: | |
899 | bit = SDE_PORTB_HOTPLUG; | |
900 | break; | |
901 | case PORT_C: | |
902 | bit = SDE_PORTC_HOTPLUG; | |
903 | break; | |
904 | case PORT_D: | |
905 | bit = SDE_PORTD_HOTPLUG; | |
906 | break; | |
907 | default: | |
908 | return true; | |
909 | } | |
910 | } else { | |
911 | switch(port->port) { | |
912 | case PORT_B: | |
913 | bit = SDE_PORTB_HOTPLUG_CPT; | |
914 | break; | |
915 | case PORT_C: | |
916 | bit = SDE_PORTC_HOTPLUG_CPT; | |
917 | break; | |
918 | case PORT_D: | |
919 | bit = SDE_PORTD_HOTPLUG_CPT; | |
920 | break; | |
921 | default: | |
922 | return true; | |
923 | } | |
b0ea7d37 DL |
924 | } |
925 | ||
926 | return I915_READ(SDEISR) & bit; | |
927 | } | |
928 | ||
b24e7179 JB |
929 | static const char *state_string(bool enabled) |
930 | { | |
931 | return enabled ? "on" : "off"; | |
932 | } | |
933 | ||
934 | /* Only for pre-ILK configs */ | |
935 | static void assert_pll(struct drm_i915_private *dev_priv, | |
936 | enum pipe pipe, bool state) | |
937 | { | |
938 | int reg; | |
939 | u32 val; | |
940 | bool cur_state; | |
941 | ||
942 | reg = DPLL(pipe); | |
943 | val = I915_READ(reg); | |
944 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
945 | WARN(cur_state != state, | |
946 | "PLL state assertion failure (expected %s, current %s)\n", | |
947 | state_string(state), state_string(cur_state)); | |
948 | } | |
949 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
950 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
951 | ||
040484af JB |
952 | /* For ILK+ */ |
953 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
954 | struct intel_pch_pll *pll, |
955 | struct intel_crtc *crtc, | |
956 | bool state) | |
040484af | 957 | { |
040484af JB |
958 | u32 val; |
959 | bool cur_state; | |
960 | ||
9d82aa17 ED |
961 | if (HAS_PCH_LPT(dev_priv->dev)) { |
962 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
963 | return; | |
964 | } | |
965 | ||
92b27b08 CW |
966 | if (WARN (!pll, |
967 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 968 | return; |
ee7b9f93 | 969 | |
92b27b08 CW |
970 | val = I915_READ(pll->pll_reg); |
971 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
972 | WARN(cur_state != state, | |
973 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
974 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
975 | ||
976 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
977 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
978 | u32 pch_dpll; |
979 | ||
980 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
981 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
982 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
4bb6f1f3 VS |
983 | "PLL[%d] not attached to this transcoder %c: %08x\n", |
984 | cur_state, pipe_name(crtc->pipe), pch_dpll)) { | |
92b27b08 CW |
985 | cur_state = !!(val >> (4*crtc->pipe + 3)); |
986 | WARN(cur_state != state, | |
4bb6f1f3 | 987 | "PLL[%d] not %s on this transcoder %c: %08x\n", |
92b27b08 CW |
988 | pll->pll_reg == _PCH_DPLL_B, |
989 | state_string(state), | |
4bb6f1f3 | 990 | pipe_name(crtc->pipe), |
92b27b08 CW |
991 | val); |
992 | } | |
d3ccbe86 | 993 | } |
040484af | 994 | } |
92b27b08 CW |
995 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
996 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
997 | |
998 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
999 | enum pipe pipe, bool state) | |
1000 | { | |
1001 | int reg; | |
1002 | u32 val; | |
1003 | bool cur_state; | |
ad80a810 PZ |
1004 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1005 | pipe); | |
040484af | 1006 | |
affa9354 PZ |
1007 | if (HAS_DDI(dev_priv->dev)) { |
1008 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1009 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1010 | val = I915_READ(reg); |
ad80a810 | 1011 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1012 | } else { |
1013 | reg = FDI_TX_CTL(pipe); | |
1014 | val = I915_READ(reg); | |
1015 | cur_state = !!(val & FDI_TX_ENABLE); | |
1016 | } | |
040484af JB |
1017 | WARN(cur_state != state, |
1018 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1019 | state_string(state), state_string(cur_state)); | |
1020 | } | |
1021 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1022 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1023 | ||
1024 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1025 | enum pipe pipe, bool state) | |
1026 | { | |
1027 | int reg; | |
1028 | u32 val; | |
1029 | bool cur_state; | |
1030 | ||
d63fa0dc PZ |
1031 | reg = FDI_RX_CTL(pipe); |
1032 | val = I915_READ(reg); | |
1033 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1034 | WARN(cur_state != state, |
1035 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1036 | state_string(state), state_string(cur_state)); | |
1037 | } | |
1038 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1039 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1040 | ||
1041 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1042 | enum pipe pipe) | |
1043 | { | |
1044 | int reg; | |
1045 | u32 val; | |
1046 | ||
1047 | /* ILK FDI PLL is always enabled */ | |
1048 | if (dev_priv->info->gen == 5) | |
1049 | return; | |
1050 | ||
bf507ef7 | 1051 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1052 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1053 | return; |
1054 | ||
040484af JB |
1055 | reg = FDI_TX_CTL(pipe); |
1056 | val = I915_READ(reg); | |
1057 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1058 | } | |
1059 | ||
1060 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1061 | enum pipe pipe) | |
1062 | { | |
1063 | int reg; | |
1064 | u32 val; | |
1065 | ||
1066 | reg = FDI_RX_CTL(pipe); | |
1067 | val = I915_READ(reg); | |
1068 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1069 | } | |
1070 | ||
ea0760cf JB |
1071 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1072 | enum pipe pipe) | |
1073 | { | |
1074 | int pp_reg, lvds_reg; | |
1075 | u32 val; | |
1076 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1077 | bool locked = true; |
ea0760cf JB |
1078 | |
1079 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1080 | pp_reg = PCH_PP_CONTROL; | |
1081 | lvds_reg = PCH_LVDS; | |
1082 | } else { | |
1083 | pp_reg = PP_CONTROL; | |
1084 | lvds_reg = LVDS; | |
1085 | } | |
1086 | ||
1087 | val = I915_READ(pp_reg); | |
1088 | if (!(val & PANEL_POWER_ON) || | |
1089 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1090 | locked = false; | |
1091 | ||
1092 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1093 | panel_pipe = PIPE_B; | |
1094 | ||
1095 | WARN(panel_pipe == pipe && locked, | |
1096 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1097 | pipe_name(pipe)); |
ea0760cf JB |
1098 | } |
1099 | ||
b840d907 JB |
1100 | void assert_pipe(struct drm_i915_private *dev_priv, |
1101 | enum pipe pipe, bool state) | |
b24e7179 JB |
1102 | { |
1103 | int reg; | |
1104 | u32 val; | |
63d7bbe9 | 1105 | bool cur_state; |
702e7a56 PZ |
1106 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1107 | pipe); | |
b24e7179 | 1108 | |
8e636784 DV |
1109 | /* if we need the pipe A quirk it must be always on */ |
1110 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1111 | state = true; | |
1112 | ||
b97186f0 PZ |
1113 | if (!intel_display_power_enabled(dev_priv->dev, |
1114 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1115 | cur_state = false; |
1116 | } else { | |
1117 | reg = PIPECONF(cpu_transcoder); | |
1118 | val = I915_READ(reg); | |
1119 | cur_state = !!(val & PIPECONF_ENABLE); | |
1120 | } | |
1121 | ||
63d7bbe9 JB |
1122 | WARN(cur_state != state, |
1123 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1124 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1125 | } |
1126 | ||
931872fc CW |
1127 | static void assert_plane(struct drm_i915_private *dev_priv, |
1128 | enum plane plane, bool state) | |
b24e7179 JB |
1129 | { |
1130 | int reg; | |
1131 | u32 val; | |
931872fc | 1132 | bool cur_state; |
b24e7179 JB |
1133 | |
1134 | reg = DSPCNTR(plane); | |
1135 | val = I915_READ(reg); | |
931872fc CW |
1136 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1137 | WARN(cur_state != state, | |
1138 | "plane %c assertion failure (expected %s, current %s)\n", | |
1139 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1140 | } |
1141 | ||
931872fc CW |
1142 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1143 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1144 | ||
b24e7179 JB |
1145 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1146 | enum pipe pipe) | |
1147 | { | |
1148 | int reg, i; | |
1149 | u32 val; | |
1150 | int cur_pipe; | |
1151 | ||
19ec1358 | 1152 | /* Planes are fixed to pipes on ILK+ */ |
da6ecc5d | 1153 | if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { |
28c05794 AJ |
1154 | reg = DSPCNTR(pipe); |
1155 | val = I915_READ(reg); | |
1156 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1157 | "plane %c assertion failure, should be disabled but not\n", | |
1158 | plane_name(pipe)); | |
19ec1358 | 1159 | return; |
28c05794 | 1160 | } |
19ec1358 | 1161 | |
b24e7179 JB |
1162 | /* Need to check both planes against the pipe */ |
1163 | for (i = 0; i < 2; i++) { | |
1164 | reg = DSPCNTR(i); | |
1165 | val = I915_READ(reg); | |
1166 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1167 | DISPPLANE_SEL_PIPE_SHIFT; | |
1168 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1169 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1170 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1171 | } |
1172 | } | |
1173 | ||
19332d7a JB |
1174 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1175 | enum pipe pipe) | |
1176 | { | |
1177 | int reg, i; | |
1178 | u32 val; | |
1179 | ||
1180 | if (!IS_VALLEYVIEW(dev_priv->dev)) | |
1181 | return; | |
1182 | ||
1183 | /* Need to check both planes against the pipe */ | |
1184 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1185 | reg = SPCNTR(pipe, i); | |
1186 | val = I915_READ(reg); | |
1187 | WARN((val & SP_ENABLE), | |
06da8da2 VS |
1188 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1189 | sprite_name(pipe, i), pipe_name(pipe)); | |
19332d7a JB |
1190 | } |
1191 | } | |
1192 | ||
92f2584a JB |
1193 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1194 | { | |
1195 | u32 val; | |
1196 | bool enabled; | |
1197 | ||
9d82aa17 ED |
1198 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1199 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1200 | return; | |
1201 | } | |
1202 | ||
92f2584a JB |
1203 | val = I915_READ(PCH_DREF_CONTROL); |
1204 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1205 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1206 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1207 | } | |
1208 | ||
ab9412ba DV |
1209 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1210 | enum pipe pipe) | |
92f2584a JB |
1211 | { |
1212 | int reg; | |
1213 | u32 val; | |
1214 | bool enabled; | |
1215 | ||
ab9412ba | 1216 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1217 | val = I915_READ(reg); |
1218 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1219 | WARN(enabled, |
1220 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1221 | pipe_name(pipe)); | |
92f2584a JB |
1222 | } |
1223 | ||
4e634389 KP |
1224 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1225 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1226 | { |
1227 | if ((val & DP_PORT_EN) == 0) | |
1228 | return false; | |
1229 | ||
1230 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1231 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1232 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1233 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1234 | return false; | |
1235 | } else { | |
1236 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1237 | return false; | |
1238 | } | |
1239 | return true; | |
1240 | } | |
1241 | ||
1519b995 KP |
1242 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1243 | enum pipe pipe, u32 val) | |
1244 | { | |
dc0fa718 | 1245 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1246 | return false; |
1247 | ||
1248 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1249 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1250 | return false; |
1251 | } else { | |
dc0fa718 | 1252 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1253 | return false; |
1254 | } | |
1255 | return true; | |
1256 | } | |
1257 | ||
1258 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1259 | enum pipe pipe, u32 val) | |
1260 | { | |
1261 | if ((val & LVDS_PORT_EN) == 0) | |
1262 | return false; | |
1263 | ||
1264 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1265 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1266 | return false; | |
1267 | } else { | |
1268 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1269 | return false; | |
1270 | } | |
1271 | return true; | |
1272 | } | |
1273 | ||
1274 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1275 | enum pipe pipe, u32 val) | |
1276 | { | |
1277 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1278 | return false; | |
1279 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1280 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1281 | return false; | |
1282 | } else { | |
1283 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1284 | return false; | |
1285 | } | |
1286 | return true; | |
1287 | } | |
1288 | ||
291906f1 | 1289 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1290 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1291 | { |
47a05eca | 1292 | u32 val = I915_READ(reg); |
4e634389 | 1293 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1294 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1295 | reg, pipe_name(pipe)); |
de9a35ab | 1296 | |
75c5da27 DV |
1297 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1298 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1299 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1300 | } |
1301 | ||
1302 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1303 | enum pipe pipe, int reg) | |
1304 | { | |
47a05eca | 1305 | u32 val = I915_READ(reg); |
b70ad586 | 1306 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1307 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1308 | reg, pipe_name(pipe)); |
de9a35ab | 1309 | |
dc0fa718 | 1310 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1311 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1312 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1313 | } |
1314 | ||
1315 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1316 | enum pipe pipe) | |
1317 | { | |
1318 | int reg; | |
1319 | u32 val; | |
291906f1 | 1320 | |
f0575e92 KP |
1321 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1322 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1323 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1324 | |
1325 | reg = PCH_ADPA; | |
1326 | val = I915_READ(reg); | |
b70ad586 | 1327 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1328 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1329 | pipe_name(pipe)); |
291906f1 JB |
1330 | |
1331 | reg = PCH_LVDS; | |
1332 | val = I915_READ(reg); | |
b70ad586 | 1333 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1334 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1335 | pipe_name(pipe)); |
291906f1 | 1336 | |
e2debe91 PZ |
1337 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1338 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1339 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1340 | } |
1341 | ||
63d7bbe9 JB |
1342 | /** |
1343 | * intel_enable_pll - enable a PLL | |
1344 | * @dev_priv: i915 private structure | |
1345 | * @pipe: pipe PLL to enable | |
1346 | * | |
1347 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1348 | * make sure the PLL reg is writable first though, since the panel write | |
1349 | * protect mechanism may be enabled. | |
1350 | * | |
1351 | * Note! This is for pre-ILK only. | |
7434a255 TR |
1352 | * |
1353 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. | |
63d7bbe9 JB |
1354 | */ |
1355 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1356 | { | |
1357 | int reg; | |
1358 | u32 val; | |
1359 | ||
58c6eaa2 DV |
1360 | assert_pipe_disabled(dev_priv, pipe); |
1361 | ||
63d7bbe9 | 1362 | /* No really, not for ILK+ */ |
a0c4da24 | 1363 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1364 | |
1365 | /* PLL is protected by panel, make sure we can write it */ | |
1366 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1367 | assert_panel_unlocked(dev_priv, pipe); | |
1368 | ||
1369 | reg = DPLL(pipe); | |
1370 | val = I915_READ(reg); | |
1371 | val |= DPLL_VCO_ENABLE; | |
1372 | ||
1373 | /* We do this three times for luck */ | |
1374 | I915_WRITE(reg, val); | |
1375 | POSTING_READ(reg); | |
1376 | udelay(150); /* wait for warmup */ | |
1377 | I915_WRITE(reg, val); | |
1378 | POSTING_READ(reg); | |
1379 | udelay(150); /* wait for warmup */ | |
1380 | I915_WRITE(reg, val); | |
1381 | POSTING_READ(reg); | |
1382 | udelay(150); /* wait for warmup */ | |
1383 | } | |
1384 | ||
1385 | /** | |
1386 | * intel_disable_pll - disable a PLL | |
1387 | * @dev_priv: i915 private structure | |
1388 | * @pipe: pipe PLL to disable | |
1389 | * | |
1390 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1391 | * | |
1392 | * Note! This is for pre-ILK only. | |
1393 | */ | |
1394 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1395 | { | |
1396 | int reg; | |
1397 | u32 val; | |
1398 | ||
1399 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1400 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1401 | return; | |
1402 | ||
1403 | /* Make sure the pipe isn't still relying on us */ | |
1404 | assert_pipe_disabled(dev_priv, pipe); | |
1405 | ||
1406 | reg = DPLL(pipe); | |
1407 | val = I915_READ(reg); | |
1408 | val &= ~DPLL_VCO_ENABLE; | |
1409 | I915_WRITE(reg, val); | |
1410 | POSTING_READ(reg); | |
1411 | } | |
1412 | ||
a416edef ED |
1413 | /* SBI access */ |
1414 | static void | |
988d6ee8 PZ |
1415 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
1416 | enum intel_sbi_destination destination) | |
a416edef | 1417 | { |
988d6ee8 | 1418 | u32 tmp; |
a416edef | 1419 | |
09153000 | 1420 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1421 | |
39fb50f6 | 1422 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1423 | 100)) { |
1424 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1425 | return; |
a416edef ED |
1426 | } |
1427 | ||
988d6ee8 PZ |
1428 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1429 | I915_WRITE(SBI_DATA, value); | |
1430 | ||
1431 | if (destination == SBI_ICLK) | |
1432 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; | |
1433 | else | |
1434 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; | |
1435 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); | |
a416edef | 1436 | |
39fb50f6 | 1437 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1438 | 100)) { |
1439 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
09153000 | 1440 | return; |
a416edef | 1441 | } |
a416edef ED |
1442 | } |
1443 | ||
1444 | static u32 | |
988d6ee8 PZ |
1445 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
1446 | enum intel_sbi_destination destination) | |
a416edef | 1447 | { |
39fb50f6 | 1448 | u32 value = 0; |
09153000 | 1449 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1450 | |
39fb50f6 | 1451 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1452 | 100)) { |
1453 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1454 | return 0; |
a416edef ED |
1455 | } |
1456 | ||
988d6ee8 PZ |
1457 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1458 | ||
1459 | if (destination == SBI_ICLK) | |
1460 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; | |
1461 | else | |
1462 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; | |
1463 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); | |
a416edef | 1464 | |
39fb50f6 | 1465 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1466 | 100)) { |
1467 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
09153000 | 1468 | return 0; |
a416edef ED |
1469 | } |
1470 | ||
09153000 | 1471 | return I915_READ(SBI_DATA); |
a416edef ED |
1472 | } |
1473 | ||
89b667f8 JB |
1474 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1475 | { | |
1476 | u32 port_mask; | |
1477 | ||
1478 | if (!port) | |
1479 | port_mask = DPLL_PORTB_READY_MASK; | |
1480 | else | |
1481 | port_mask = DPLL_PORTC_READY_MASK; | |
1482 | ||
1483 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1484 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
1485 | 'B' + port, I915_READ(DPLL(0))); | |
1486 | } | |
1487 | ||
92f2584a | 1488 | /** |
b6b4e185 | 1489 | * ironlake_enable_pch_pll - enable PCH PLL |
92f2584a JB |
1490 | * @dev_priv: i915 private structure |
1491 | * @pipe: pipe PLL to enable | |
1492 | * | |
1493 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1494 | * drives the transcoder clock. | |
1495 | */ | |
b6b4e185 | 1496 | static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1497 | { |
ee7b9f93 | 1498 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1499 | struct intel_pch_pll *pll; |
92f2584a JB |
1500 | int reg; |
1501 | u32 val; | |
1502 | ||
48da64a8 | 1503 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1504 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1505 | pll = intel_crtc->pch_pll; |
1506 | if (pll == NULL) | |
1507 | return; | |
1508 | ||
1509 | if (WARN_ON(pll->refcount == 0)) | |
1510 | return; | |
ee7b9f93 JB |
1511 | |
1512 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1513 | pll->pll_reg, pll->active, pll->on, | |
1514 | intel_crtc->base.base.id); | |
92f2584a JB |
1515 | |
1516 | /* PCH refclock must be enabled first */ | |
1517 | assert_pch_refclk_enabled(dev_priv); | |
1518 | ||
ee7b9f93 | 1519 | if (pll->active++ && pll->on) { |
92b27b08 | 1520 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1521 | return; |
1522 | } | |
1523 | ||
1524 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1525 | ||
1526 | reg = pll->pll_reg; | |
92f2584a JB |
1527 | val = I915_READ(reg); |
1528 | val |= DPLL_VCO_ENABLE; | |
1529 | I915_WRITE(reg, val); | |
1530 | POSTING_READ(reg); | |
1531 | udelay(200); | |
ee7b9f93 JB |
1532 | |
1533 | pll->on = true; | |
92f2584a JB |
1534 | } |
1535 | ||
ee7b9f93 | 1536 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1537 | { |
ee7b9f93 JB |
1538 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1539 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1540 | int reg; |
ee7b9f93 | 1541 | u32 val; |
4c609cb8 | 1542 | |
92f2584a JB |
1543 | /* PCH only available on ILK+ */ |
1544 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1545 | if (pll == NULL) |
1546 | return; | |
92f2584a | 1547 | |
48da64a8 CW |
1548 | if (WARN_ON(pll->refcount == 0)) |
1549 | return; | |
7a419866 | 1550 | |
ee7b9f93 JB |
1551 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1552 | pll->pll_reg, pll->active, pll->on, | |
1553 | intel_crtc->base.base.id); | |
7a419866 | 1554 | |
48da64a8 | 1555 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1556 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1557 | return; |
1558 | } | |
1559 | ||
ee7b9f93 | 1560 | if (--pll->active) { |
92b27b08 | 1561 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1562 | return; |
ee7b9f93 JB |
1563 | } |
1564 | ||
1565 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1566 | ||
1567 | /* Make sure transcoder isn't still depending on us */ | |
ab9412ba | 1568 | assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe); |
7a419866 | 1569 | |
ee7b9f93 | 1570 | reg = pll->pll_reg; |
92f2584a JB |
1571 | val = I915_READ(reg); |
1572 | val &= ~DPLL_VCO_ENABLE; | |
1573 | I915_WRITE(reg, val); | |
1574 | POSTING_READ(reg); | |
1575 | udelay(200); | |
ee7b9f93 JB |
1576 | |
1577 | pll->on = false; | |
92f2584a JB |
1578 | } |
1579 | ||
b8a4f404 PZ |
1580 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1581 | enum pipe pipe) | |
040484af | 1582 | { |
23670b32 | 1583 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1584 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
23670b32 | 1585 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1586 | |
1587 | /* PCH only available on ILK+ */ | |
1588 | BUG_ON(dev_priv->info->gen < 5); | |
1589 | ||
1590 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1591 | assert_pch_pll_enabled(dev_priv, |
1592 | to_intel_crtc(crtc)->pch_pll, | |
1593 | to_intel_crtc(crtc)); | |
040484af JB |
1594 | |
1595 | /* FDI must be feeding us bits for PCH ports */ | |
1596 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1597 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1598 | ||
23670b32 DV |
1599 | if (HAS_PCH_CPT(dev)) { |
1600 | /* Workaround: Set the timing override bit before enabling the | |
1601 | * pch transcoder. */ | |
1602 | reg = TRANS_CHICKEN2(pipe); | |
1603 | val = I915_READ(reg); | |
1604 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1605 | I915_WRITE(reg, val); | |
59c859d6 | 1606 | } |
23670b32 | 1607 | |
ab9412ba | 1608 | reg = PCH_TRANSCONF(pipe); |
040484af | 1609 | val = I915_READ(reg); |
5f7f726d | 1610 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1611 | |
1612 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1613 | /* | |
1614 | * make the BPC in transcoder be consistent with | |
1615 | * that in pipeconf reg. | |
1616 | */ | |
dfd07d72 DV |
1617 | val &= ~PIPECONF_BPC_MASK; |
1618 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1619 | } |
5f7f726d PZ |
1620 | |
1621 | val &= ~TRANS_INTERLACE_MASK; | |
1622 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1623 | if (HAS_PCH_IBX(dev_priv->dev) && |
1624 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1625 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1626 | else | |
1627 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1628 | else |
1629 | val |= TRANS_PROGRESSIVE; | |
1630 | ||
040484af JB |
1631 | I915_WRITE(reg, val | TRANS_ENABLE); |
1632 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1633 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1634 | } |
1635 | ||
8fb033d7 | 1636 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1637 | enum transcoder cpu_transcoder) |
040484af | 1638 | { |
8fb033d7 | 1639 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1640 | |
1641 | /* PCH only available on ILK+ */ | |
1642 | BUG_ON(dev_priv->info->gen < 5); | |
1643 | ||
8fb033d7 | 1644 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1645 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1646 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1647 | |
223a6fdf PZ |
1648 | /* Workaround: set timing override bit. */ |
1649 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1650 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1651 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1652 | ||
25f3ef11 | 1653 | val = TRANS_ENABLE; |
937bb610 | 1654 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1655 | |
9a76b1c6 PZ |
1656 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1657 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1658 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1659 | else |
1660 | val |= TRANS_PROGRESSIVE; | |
1661 | ||
ab9412ba DV |
1662 | I915_WRITE(LPT_TRANSCONF, val); |
1663 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1664 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1665 | } |
1666 | ||
b8a4f404 PZ |
1667 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1668 | enum pipe pipe) | |
040484af | 1669 | { |
23670b32 DV |
1670 | struct drm_device *dev = dev_priv->dev; |
1671 | uint32_t reg, val; | |
040484af JB |
1672 | |
1673 | /* FDI relies on the transcoder */ | |
1674 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1675 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1676 | ||
291906f1 JB |
1677 | /* Ports must be off as well */ |
1678 | assert_pch_ports_disabled(dev_priv, pipe); | |
1679 | ||
ab9412ba | 1680 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1681 | val = I915_READ(reg); |
1682 | val &= ~TRANS_ENABLE; | |
1683 | I915_WRITE(reg, val); | |
1684 | /* wait for PCH transcoder off, transcoder state */ | |
1685 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1686 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1687 | |
1688 | if (!HAS_PCH_IBX(dev)) { | |
1689 | /* Workaround: Clear the timing override chicken bit again. */ | |
1690 | reg = TRANS_CHICKEN2(pipe); | |
1691 | val = I915_READ(reg); | |
1692 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1693 | I915_WRITE(reg, val); | |
1694 | } | |
040484af JB |
1695 | } |
1696 | ||
ab4d966c | 1697 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1698 | { |
8fb033d7 PZ |
1699 | u32 val; |
1700 | ||
ab9412ba | 1701 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1702 | val &= ~TRANS_ENABLE; |
ab9412ba | 1703 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1704 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1705 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1706 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1707 | |
1708 | /* Workaround: clear timing override bit. */ | |
1709 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1710 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1711 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1712 | } |
1713 | ||
b24e7179 | 1714 | /** |
309cfea8 | 1715 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1716 | * @dev_priv: i915 private structure |
1717 | * @pipe: pipe to enable | |
040484af | 1718 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1719 | * |
1720 | * Enable @pipe, making sure that various hardware specific requirements | |
1721 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1722 | * | |
1723 | * @pipe should be %PIPE_A or %PIPE_B. | |
1724 | * | |
1725 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1726 | * returning. | |
1727 | */ | |
040484af JB |
1728 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1729 | bool pch_port) | |
b24e7179 | 1730 | { |
702e7a56 PZ |
1731 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1732 | pipe); | |
1a240d4d | 1733 | enum pipe pch_transcoder; |
b24e7179 JB |
1734 | int reg; |
1735 | u32 val; | |
1736 | ||
58c6eaa2 DV |
1737 | assert_planes_disabled(dev_priv, pipe); |
1738 | assert_sprites_disabled(dev_priv, pipe); | |
1739 | ||
681e5811 | 1740 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1741 | pch_transcoder = TRANSCODER_A; |
1742 | else | |
1743 | pch_transcoder = pipe; | |
1744 | ||
b24e7179 JB |
1745 | /* |
1746 | * A pipe without a PLL won't actually be able to drive bits from | |
1747 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1748 | * need the check. | |
1749 | */ | |
1750 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1751 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1752 | else { |
1753 | if (pch_port) { | |
1754 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1755 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1756 | assert_fdi_tx_pll_enabled(dev_priv, |
1757 | (enum pipe) cpu_transcoder); | |
040484af JB |
1758 | } |
1759 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1760 | } | |
b24e7179 | 1761 | |
702e7a56 | 1762 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1763 | val = I915_READ(reg); |
00d70b15 CW |
1764 | if (val & PIPECONF_ENABLE) |
1765 | return; | |
1766 | ||
1767 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1768 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1769 | } | |
1770 | ||
1771 | /** | |
309cfea8 | 1772 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1773 | * @dev_priv: i915 private structure |
1774 | * @pipe: pipe to disable | |
1775 | * | |
1776 | * Disable @pipe, making sure that various hardware specific requirements | |
1777 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1778 | * | |
1779 | * @pipe should be %PIPE_A or %PIPE_B. | |
1780 | * | |
1781 | * Will wait until the pipe has shut down before returning. | |
1782 | */ | |
1783 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1784 | enum pipe pipe) | |
1785 | { | |
702e7a56 PZ |
1786 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1787 | pipe); | |
b24e7179 JB |
1788 | int reg; |
1789 | u32 val; | |
1790 | ||
1791 | /* | |
1792 | * Make sure planes won't keep trying to pump pixels to us, | |
1793 | * or we might hang the display. | |
1794 | */ | |
1795 | assert_planes_disabled(dev_priv, pipe); | |
19332d7a | 1796 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1797 | |
1798 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1799 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1800 | return; | |
1801 | ||
702e7a56 | 1802 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1803 | val = I915_READ(reg); |
00d70b15 CW |
1804 | if ((val & PIPECONF_ENABLE) == 0) |
1805 | return; | |
1806 | ||
1807 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1808 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1809 | } | |
1810 | ||
d74362c9 KP |
1811 | /* |
1812 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1813 | * trigger in order to latch. The display address reg provides this. | |
1814 | */ | |
6f1d69b0 | 1815 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1816 | enum plane plane) |
1817 | { | |
14f86147 DL |
1818 | if (dev_priv->info->gen >= 4) |
1819 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1820 | else | |
1821 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1822 | } |
1823 | ||
b24e7179 JB |
1824 | /** |
1825 | * intel_enable_plane - enable a display plane on a given pipe | |
1826 | * @dev_priv: i915 private structure | |
1827 | * @plane: plane to enable | |
1828 | * @pipe: pipe being fed | |
1829 | * | |
1830 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1831 | */ | |
1832 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1833 | enum plane plane, enum pipe pipe) | |
1834 | { | |
1835 | int reg; | |
1836 | u32 val; | |
1837 | ||
1838 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1839 | assert_pipe_enabled(dev_priv, pipe); | |
1840 | ||
1841 | reg = DSPCNTR(plane); | |
1842 | val = I915_READ(reg); | |
00d70b15 CW |
1843 | if (val & DISPLAY_PLANE_ENABLE) |
1844 | return; | |
1845 | ||
1846 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1847 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1848 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1849 | } | |
1850 | ||
b24e7179 JB |
1851 | /** |
1852 | * intel_disable_plane - disable a display plane | |
1853 | * @dev_priv: i915 private structure | |
1854 | * @plane: plane to disable | |
1855 | * @pipe: pipe consuming the data | |
1856 | * | |
1857 | * Disable @plane; should be an independent operation. | |
1858 | */ | |
1859 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1860 | enum plane plane, enum pipe pipe) | |
1861 | { | |
1862 | int reg; | |
1863 | u32 val; | |
1864 | ||
1865 | reg = DSPCNTR(plane); | |
1866 | val = I915_READ(reg); | |
00d70b15 CW |
1867 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1868 | return; | |
1869 | ||
1870 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1871 | intel_flush_display_plane(dev_priv, plane); |
1872 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1873 | } | |
1874 | ||
693db184 CW |
1875 | static bool need_vtd_wa(struct drm_device *dev) |
1876 | { | |
1877 | #ifdef CONFIG_INTEL_IOMMU | |
1878 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1879 | return true; | |
1880 | #endif | |
1881 | return false; | |
1882 | } | |
1883 | ||
127bd2ac | 1884 | int |
48b956c5 | 1885 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1886 | struct drm_i915_gem_object *obj, |
919926ae | 1887 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1888 | { |
ce453d81 | 1889 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1890 | u32 alignment; |
1891 | int ret; | |
1892 | ||
05394f39 | 1893 | switch (obj->tiling_mode) { |
6b95a207 | 1894 | case I915_TILING_NONE: |
534843da CW |
1895 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1896 | alignment = 128 * 1024; | |
a6c45cf0 | 1897 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1898 | alignment = 4 * 1024; |
1899 | else | |
1900 | alignment = 64 * 1024; | |
6b95a207 KH |
1901 | break; |
1902 | case I915_TILING_X: | |
1903 | /* pin() will align the object as required by fence */ | |
1904 | alignment = 0; | |
1905 | break; | |
1906 | case I915_TILING_Y: | |
8bb6e959 DV |
1907 | /* Despite that we check this in framebuffer_init userspace can |
1908 | * screw us over and change the tiling after the fact. Only | |
1909 | * pinned buffers can't change their tiling. */ | |
1910 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); | |
6b95a207 KH |
1911 | return -EINVAL; |
1912 | default: | |
1913 | BUG(); | |
1914 | } | |
1915 | ||
693db184 CW |
1916 | /* Note that the w/a also requires 64 PTE of padding following the |
1917 | * bo. We currently fill all unused PTE with the shadow page and so | |
1918 | * we should always have valid PTE following the scanout preventing | |
1919 | * the VT-d warning. | |
1920 | */ | |
1921 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1922 | alignment = 256 * 1024; | |
1923 | ||
ce453d81 | 1924 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1925 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1926 | if (ret) |
ce453d81 | 1927 | goto err_interruptible; |
6b95a207 KH |
1928 | |
1929 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1930 | * fence, whereas 965+ only requires a fence if using | |
1931 | * framebuffer compression. For simplicity, we always install | |
1932 | * a fence as the cost is not that onerous. | |
1933 | */ | |
06d98131 | 1934 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1935 | if (ret) |
1936 | goto err_unpin; | |
1690e1eb | 1937 | |
9a5a53b3 | 1938 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1939 | |
ce453d81 | 1940 | dev_priv->mm.interruptible = true; |
6b95a207 | 1941 | return 0; |
48b956c5 CW |
1942 | |
1943 | err_unpin: | |
1944 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1945 | err_interruptible: |
1946 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1947 | return ret; |
6b95a207 KH |
1948 | } |
1949 | ||
1690e1eb CW |
1950 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1951 | { | |
1952 | i915_gem_object_unpin_fence(obj); | |
1953 | i915_gem_object_unpin(obj); | |
1954 | } | |
1955 | ||
c2c75131 DV |
1956 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1957 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1958 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1959 | unsigned int tiling_mode, | |
1960 | unsigned int cpp, | |
1961 | unsigned int pitch) | |
c2c75131 | 1962 | { |
bc752862 CW |
1963 | if (tiling_mode != I915_TILING_NONE) { |
1964 | unsigned int tile_rows, tiles; | |
c2c75131 | 1965 | |
bc752862 CW |
1966 | tile_rows = *y / 8; |
1967 | *y %= 8; | |
c2c75131 | 1968 | |
bc752862 CW |
1969 | tiles = *x / (512/cpp); |
1970 | *x %= 512/cpp; | |
1971 | ||
1972 | return tile_rows * pitch * 8 + tiles * 4096; | |
1973 | } else { | |
1974 | unsigned int offset; | |
1975 | ||
1976 | offset = *y * pitch + *x * cpp; | |
1977 | *y = 0; | |
1978 | *x = (offset & 4095) / cpp; | |
1979 | return offset & -4096; | |
1980 | } | |
c2c75131 DV |
1981 | } |
1982 | ||
17638cd6 JB |
1983 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1984 | int x, int y) | |
81255565 JB |
1985 | { |
1986 | struct drm_device *dev = crtc->dev; | |
1987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1988 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1989 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1990 | struct drm_i915_gem_object *obj; |
81255565 | 1991 | int plane = intel_crtc->plane; |
e506a0c6 | 1992 | unsigned long linear_offset; |
81255565 | 1993 | u32 dspcntr; |
5eddb70b | 1994 | u32 reg; |
81255565 JB |
1995 | |
1996 | switch (plane) { | |
1997 | case 0: | |
1998 | case 1: | |
1999 | break; | |
2000 | default: | |
84f44ce7 | 2001 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2002 | return -EINVAL; |
2003 | } | |
2004 | ||
2005 | intel_fb = to_intel_framebuffer(fb); | |
2006 | obj = intel_fb->obj; | |
81255565 | 2007 | |
5eddb70b CW |
2008 | reg = DSPCNTR(plane); |
2009 | dspcntr = I915_READ(reg); | |
81255565 JB |
2010 | /* Mask out pixel format bits in case we change it */ |
2011 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2012 | switch (fb->pixel_format) { |
2013 | case DRM_FORMAT_C8: | |
81255565 JB |
2014 | dspcntr |= DISPPLANE_8BPP; |
2015 | break; | |
57779d06 VS |
2016 | case DRM_FORMAT_XRGB1555: |
2017 | case DRM_FORMAT_ARGB1555: | |
2018 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2019 | break; |
57779d06 VS |
2020 | case DRM_FORMAT_RGB565: |
2021 | dspcntr |= DISPPLANE_BGRX565; | |
2022 | break; | |
2023 | case DRM_FORMAT_XRGB8888: | |
2024 | case DRM_FORMAT_ARGB8888: | |
2025 | dspcntr |= DISPPLANE_BGRX888; | |
2026 | break; | |
2027 | case DRM_FORMAT_XBGR8888: | |
2028 | case DRM_FORMAT_ABGR8888: | |
2029 | dspcntr |= DISPPLANE_RGBX888; | |
2030 | break; | |
2031 | case DRM_FORMAT_XRGB2101010: | |
2032 | case DRM_FORMAT_ARGB2101010: | |
2033 | dspcntr |= DISPPLANE_BGRX101010; | |
2034 | break; | |
2035 | case DRM_FORMAT_XBGR2101010: | |
2036 | case DRM_FORMAT_ABGR2101010: | |
2037 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2038 | break; |
2039 | default: | |
baba133a | 2040 | BUG(); |
81255565 | 2041 | } |
57779d06 | 2042 | |
a6c45cf0 | 2043 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2044 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2045 | dspcntr |= DISPPLANE_TILED; |
2046 | else | |
2047 | dspcntr &= ~DISPPLANE_TILED; | |
2048 | } | |
2049 | ||
5eddb70b | 2050 | I915_WRITE(reg, dspcntr); |
81255565 | 2051 | |
e506a0c6 | 2052 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2053 | |
c2c75131 DV |
2054 | if (INTEL_INFO(dev)->gen >= 4) { |
2055 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2056 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2057 | fb->bits_per_pixel / 8, | |
2058 | fb->pitches[0]); | |
c2c75131 DV |
2059 | linear_offset -= intel_crtc->dspaddr_offset; |
2060 | } else { | |
e506a0c6 | 2061 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2062 | } |
e506a0c6 DV |
2063 | |
2064 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2065 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2066 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2067 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2068 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2069 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2070 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2071 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2072 | } else |
e506a0c6 | 2073 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2074 | POSTING_READ(reg); |
81255565 | 2075 | |
17638cd6 JB |
2076 | return 0; |
2077 | } | |
2078 | ||
2079 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2080 | struct drm_framebuffer *fb, int x, int y) | |
2081 | { | |
2082 | struct drm_device *dev = crtc->dev; | |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2085 | struct intel_framebuffer *intel_fb; | |
2086 | struct drm_i915_gem_object *obj; | |
2087 | int plane = intel_crtc->plane; | |
e506a0c6 | 2088 | unsigned long linear_offset; |
17638cd6 JB |
2089 | u32 dspcntr; |
2090 | u32 reg; | |
2091 | ||
2092 | switch (plane) { | |
2093 | case 0: | |
2094 | case 1: | |
27f8227b | 2095 | case 2: |
17638cd6 JB |
2096 | break; |
2097 | default: | |
84f44ce7 | 2098 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2099 | return -EINVAL; |
2100 | } | |
2101 | ||
2102 | intel_fb = to_intel_framebuffer(fb); | |
2103 | obj = intel_fb->obj; | |
2104 | ||
2105 | reg = DSPCNTR(plane); | |
2106 | dspcntr = I915_READ(reg); | |
2107 | /* Mask out pixel format bits in case we change it */ | |
2108 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2109 | switch (fb->pixel_format) { |
2110 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2111 | dspcntr |= DISPPLANE_8BPP; |
2112 | break; | |
57779d06 VS |
2113 | case DRM_FORMAT_RGB565: |
2114 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2115 | break; |
57779d06 VS |
2116 | case DRM_FORMAT_XRGB8888: |
2117 | case DRM_FORMAT_ARGB8888: | |
2118 | dspcntr |= DISPPLANE_BGRX888; | |
2119 | break; | |
2120 | case DRM_FORMAT_XBGR8888: | |
2121 | case DRM_FORMAT_ABGR8888: | |
2122 | dspcntr |= DISPPLANE_RGBX888; | |
2123 | break; | |
2124 | case DRM_FORMAT_XRGB2101010: | |
2125 | case DRM_FORMAT_ARGB2101010: | |
2126 | dspcntr |= DISPPLANE_BGRX101010; | |
2127 | break; | |
2128 | case DRM_FORMAT_XBGR2101010: | |
2129 | case DRM_FORMAT_ABGR2101010: | |
2130 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2131 | break; |
2132 | default: | |
baba133a | 2133 | BUG(); |
17638cd6 JB |
2134 | } |
2135 | ||
2136 | if (obj->tiling_mode != I915_TILING_NONE) | |
2137 | dspcntr |= DISPPLANE_TILED; | |
2138 | else | |
2139 | dspcntr &= ~DISPPLANE_TILED; | |
2140 | ||
2141 | /* must disable */ | |
2142 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2143 | ||
2144 | I915_WRITE(reg, dspcntr); | |
2145 | ||
e506a0c6 | 2146 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2147 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2148 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2149 | fb->bits_per_pixel / 8, | |
2150 | fb->pitches[0]); | |
c2c75131 | 2151 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2152 | |
e506a0c6 DV |
2153 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2154 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2155 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2156 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2157 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
bc1c91eb DL |
2158 | if (IS_HASWELL(dev)) { |
2159 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2160 | } else { | |
2161 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2162 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2163 | } | |
17638cd6 JB |
2164 | POSTING_READ(reg); |
2165 | ||
2166 | return 0; | |
2167 | } | |
2168 | ||
2169 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2170 | static int | |
2171 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2172 | int x, int y, enum mode_set_atomic state) | |
2173 | { | |
2174 | struct drm_device *dev = crtc->dev; | |
2175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2176 | |
6b8e6ed0 CW |
2177 | if (dev_priv->display.disable_fbc) |
2178 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2179 | intel_increase_pllclock(crtc); |
81255565 | 2180 | |
6b8e6ed0 | 2181 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2182 | } |
2183 | ||
96a02917 VS |
2184 | void intel_display_handle_reset(struct drm_device *dev) |
2185 | { | |
2186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2187 | struct drm_crtc *crtc; | |
2188 | ||
2189 | /* | |
2190 | * Flips in the rings have been nuked by the reset, | |
2191 | * so complete all pending flips so that user space | |
2192 | * will get its events and not get stuck. | |
2193 | * | |
2194 | * Also update the base address of all primary | |
2195 | * planes to the the last fb to make sure we're | |
2196 | * showing the correct fb after a reset. | |
2197 | * | |
2198 | * Need to make two loops over the crtcs so that we | |
2199 | * don't try to grab a crtc mutex before the | |
2200 | * pending_flip_queue really got woken up. | |
2201 | */ | |
2202 | ||
2203 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2205 | enum plane plane = intel_crtc->plane; | |
2206 | ||
2207 | intel_prepare_page_flip(dev, plane); | |
2208 | intel_finish_page_flip_plane(dev, plane); | |
2209 | } | |
2210 | ||
2211 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2213 | ||
2214 | mutex_lock(&crtc->mutex); | |
2215 | if (intel_crtc->active) | |
2216 | dev_priv->display.update_plane(crtc, crtc->fb, | |
2217 | crtc->x, crtc->y); | |
2218 | mutex_unlock(&crtc->mutex); | |
2219 | } | |
2220 | } | |
2221 | ||
14667a4b CW |
2222 | static int |
2223 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2224 | { | |
2225 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2226 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2227 | bool was_interruptible = dev_priv->mm.interruptible; | |
2228 | int ret; | |
2229 | ||
14667a4b CW |
2230 | /* Big Hammer, we also need to ensure that any pending |
2231 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2232 | * current scanout is retired before unpinning the old | |
2233 | * framebuffer. | |
2234 | * | |
2235 | * This should only fail upon a hung GPU, in which case we | |
2236 | * can safely continue. | |
2237 | */ | |
2238 | dev_priv->mm.interruptible = false; | |
2239 | ret = i915_gem_object_finish_gpu(obj); | |
2240 | dev_priv->mm.interruptible = was_interruptible; | |
2241 | ||
2242 | return ret; | |
2243 | } | |
2244 | ||
198598d0 VS |
2245 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2246 | { | |
2247 | struct drm_device *dev = crtc->dev; | |
2248 | struct drm_i915_master_private *master_priv; | |
2249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2250 | ||
2251 | if (!dev->primary->master) | |
2252 | return; | |
2253 | ||
2254 | master_priv = dev->primary->master->driver_priv; | |
2255 | if (!master_priv->sarea_priv) | |
2256 | return; | |
2257 | ||
2258 | switch (intel_crtc->pipe) { | |
2259 | case 0: | |
2260 | master_priv->sarea_priv->pipeA_x = x; | |
2261 | master_priv->sarea_priv->pipeA_y = y; | |
2262 | break; | |
2263 | case 1: | |
2264 | master_priv->sarea_priv->pipeB_x = x; | |
2265 | master_priv->sarea_priv->pipeB_y = y; | |
2266 | break; | |
2267 | default: | |
2268 | break; | |
2269 | } | |
2270 | } | |
2271 | ||
5c3b82e2 | 2272 | static int |
3c4fdcfb | 2273 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2274 | struct drm_framebuffer *fb) |
79e53945 JB |
2275 | { |
2276 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2277 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2279 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2280 | int ret; |
79e53945 JB |
2281 | |
2282 | /* no fb bound */ | |
94352cf9 | 2283 | if (!fb) { |
a5071c2f | 2284 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2285 | return 0; |
2286 | } | |
2287 | ||
7eb552ae | 2288 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2289 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2290 | plane_name(intel_crtc->plane), | |
2291 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2292 | return -EINVAL; |
79e53945 JB |
2293 | } |
2294 | ||
5c3b82e2 | 2295 | mutex_lock(&dev->struct_mutex); |
265db958 | 2296 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2297 | to_intel_framebuffer(fb)->obj, |
919926ae | 2298 | NULL); |
5c3b82e2 CW |
2299 | if (ret != 0) { |
2300 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2301 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2302 | return ret; |
2303 | } | |
79e53945 | 2304 | |
94352cf9 | 2305 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2306 | if (ret) { |
94352cf9 | 2307 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2308 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2309 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2310 | return ret; |
79e53945 | 2311 | } |
3c4fdcfb | 2312 | |
94352cf9 DV |
2313 | old_fb = crtc->fb; |
2314 | crtc->fb = fb; | |
6c4c86f5 DV |
2315 | crtc->x = x; |
2316 | crtc->y = y; | |
94352cf9 | 2317 | |
b7f1de28 CW |
2318 | if (old_fb) { |
2319 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2320 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2321 | } |
652c393a | 2322 | |
6b8e6ed0 | 2323 | intel_update_fbc(dev); |
5c3b82e2 | 2324 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2325 | |
198598d0 | 2326 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2327 | |
2328 | return 0; | |
79e53945 JB |
2329 | } |
2330 | ||
5e84e1a4 ZW |
2331 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2332 | { | |
2333 | struct drm_device *dev = crtc->dev; | |
2334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2336 | int pipe = intel_crtc->pipe; | |
2337 | u32 reg, temp; | |
2338 | ||
2339 | /* enable normal train */ | |
2340 | reg = FDI_TX_CTL(pipe); | |
2341 | temp = I915_READ(reg); | |
61e499bf | 2342 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2343 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2344 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2345 | } else { |
2346 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2347 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2348 | } |
5e84e1a4 ZW |
2349 | I915_WRITE(reg, temp); |
2350 | ||
2351 | reg = FDI_RX_CTL(pipe); | |
2352 | temp = I915_READ(reg); | |
2353 | if (HAS_PCH_CPT(dev)) { | |
2354 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2355 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2356 | } else { | |
2357 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2358 | temp |= FDI_LINK_TRAIN_NONE; | |
2359 | } | |
2360 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2361 | ||
2362 | /* wait one idle pattern time */ | |
2363 | POSTING_READ(reg); | |
2364 | udelay(1000); | |
357555c0 JB |
2365 | |
2366 | /* IVB wants error correction enabled */ | |
2367 | if (IS_IVYBRIDGE(dev)) | |
2368 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2369 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2370 | } |
2371 | ||
1e833f40 DV |
2372 | static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) |
2373 | { | |
2374 | return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; | |
2375 | } | |
2376 | ||
01a415fd DV |
2377 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2378 | { | |
2379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2380 | struct intel_crtc *pipe_B_crtc = | |
2381 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2382 | struct intel_crtc *pipe_C_crtc = | |
2383 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2384 | uint32_t temp; | |
2385 | ||
1e833f40 DV |
2386 | /* |
2387 | * When everything is off disable fdi C so that we could enable fdi B | |
2388 | * with all lanes. Note that we don't care about enabled pipes without | |
2389 | * an enabled pch encoder. | |
2390 | */ | |
2391 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2392 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2393 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2394 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2395 | ||
2396 | temp = I915_READ(SOUTH_CHICKEN1); | |
2397 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2398 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2399 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2400 | } | |
2401 | } | |
2402 | ||
8db9d77b ZW |
2403 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2404 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2405 | { | |
2406 | struct drm_device *dev = crtc->dev; | |
2407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2409 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2410 | int plane = intel_crtc->plane; |
5eddb70b | 2411 | u32 reg, temp, tries; |
8db9d77b | 2412 | |
0fc932b8 JB |
2413 | /* FDI needs bits from pipe & plane first */ |
2414 | assert_pipe_enabled(dev_priv, pipe); | |
2415 | assert_plane_enabled(dev_priv, plane); | |
2416 | ||
e1a44743 AJ |
2417 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2418 | for train result */ | |
5eddb70b CW |
2419 | reg = FDI_RX_IMR(pipe); |
2420 | temp = I915_READ(reg); | |
e1a44743 AJ |
2421 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2422 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2423 | I915_WRITE(reg, temp); |
2424 | I915_READ(reg); | |
e1a44743 AJ |
2425 | udelay(150); |
2426 | ||
8db9d77b | 2427 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2428 | reg = FDI_TX_CTL(pipe); |
2429 | temp = I915_READ(reg); | |
627eb5a3 DV |
2430 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2431 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2432 | temp &= ~FDI_LINK_TRAIN_NONE; |
2433 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2434 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2435 | |
5eddb70b CW |
2436 | reg = FDI_RX_CTL(pipe); |
2437 | temp = I915_READ(reg); | |
8db9d77b ZW |
2438 | temp &= ~FDI_LINK_TRAIN_NONE; |
2439 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2440 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2441 | ||
2442 | POSTING_READ(reg); | |
8db9d77b ZW |
2443 | udelay(150); |
2444 | ||
5b2adf89 | 2445 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2446 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2447 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2448 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2449 | |
5eddb70b | 2450 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2451 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2452 | temp = I915_READ(reg); |
8db9d77b ZW |
2453 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2454 | ||
2455 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2456 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2457 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2458 | break; |
2459 | } | |
8db9d77b | 2460 | } |
e1a44743 | 2461 | if (tries == 5) |
5eddb70b | 2462 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2463 | |
2464 | /* Train 2 */ | |
5eddb70b CW |
2465 | reg = FDI_TX_CTL(pipe); |
2466 | temp = I915_READ(reg); | |
8db9d77b ZW |
2467 | temp &= ~FDI_LINK_TRAIN_NONE; |
2468 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2469 | I915_WRITE(reg, temp); |
8db9d77b | 2470 | |
5eddb70b CW |
2471 | reg = FDI_RX_CTL(pipe); |
2472 | temp = I915_READ(reg); | |
8db9d77b ZW |
2473 | temp &= ~FDI_LINK_TRAIN_NONE; |
2474 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2475 | I915_WRITE(reg, temp); |
8db9d77b | 2476 | |
5eddb70b CW |
2477 | POSTING_READ(reg); |
2478 | udelay(150); | |
8db9d77b | 2479 | |
5eddb70b | 2480 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2481 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2482 | temp = I915_READ(reg); |
8db9d77b ZW |
2483 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2484 | ||
2485 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2486 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2487 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2488 | break; | |
2489 | } | |
8db9d77b | 2490 | } |
e1a44743 | 2491 | if (tries == 5) |
5eddb70b | 2492 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2493 | |
2494 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2495 | |
8db9d77b ZW |
2496 | } |
2497 | ||
0206e353 | 2498 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2499 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2500 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2501 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2502 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2503 | }; | |
2504 | ||
2505 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2506 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2507 | { | |
2508 | struct drm_device *dev = crtc->dev; | |
2509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2511 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2512 | u32 reg, temp, i, retry; |
8db9d77b | 2513 | |
e1a44743 AJ |
2514 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2515 | for train result */ | |
5eddb70b CW |
2516 | reg = FDI_RX_IMR(pipe); |
2517 | temp = I915_READ(reg); | |
e1a44743 AJ |
2518 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2519 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2520 | I915_WRITE(reg, temp); |
2521 | ||
2522 | POSTING_READ(reg); | |
e1a44743 AJ |
2523 | udelay(150); |
2524 | ||
8db9d77b | 2525 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2526 | reg = FDI_TX_CTL(pipe); |
2527 | temp = I915_READ(reg); | |
627eb5a3 DV |
2528 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2529 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2530 | temp &= ~FDI_LINK_TRAIN_NONE; |
2531 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2532 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2533 | /* SNB-B */ | |
2534 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2535 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2536 | |
d74cf324 DV |
2537 | I915_WRITE(FDI_RX_MISC(pipe), |
2538 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2539 | ||
5eddb70b CW |
2540 | reg = FDI_RX_CTL(pipe); |
2541 | temp = I915_READ(reg); | |
8db9d77b ZW |
2542 | if (HAS_PCH_CPT(dev)) { |
2543 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2544 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2545 | } else { | |
2546 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2547 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2548 | } | |
5eddb70b CW |
2549 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2550 | ||
2551 | POSTING_READ(reg); | |
8db9d77b ZW |
2552 | udelay(150); |
2553 | ||
0206e353 | 2554 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2555 | reg = FDI_TX_CTL(pipe); |
2556 | temp = I915_READ(reg); | |
8db9d77b ZW |
2557 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2558 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2559 | I915_WRITE(reg, temp); |
2560 | ||
2561 | POSTING_READ(reg); | |
8db9d77b ZW |
2562 | udelay(500); |
2563 | ||
fa37d39e SP |
2564 | for (retry = 0; retry < 5; retry++) { |
2565 | reg = FDI_RX_IIR(pipe); | |
2566 | temp = I915_READ(reg); | |
2567 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2568 | if (temp & FDI_RX_BIT_LOCK) { | |
2569 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2570 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2571 | break; | |
2572 | } | |
2573 | udelay(50); | |
8db9d77b | 2574 | } |
fa37d39e SP |
2575 | if (retry < 5) |
2576 | break; | |
8db9d77b ZW |
2577 | } |
2578 | if (i == 4) | |
5eddb70b | 2579 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2580 | |
2581 | /* Train 2 */ | |
5eddb70b CW |
2582 | reg = FDI_TX_CTL(pipe); |
2583 | temp = I915_READ(reg); | |
8db9d77b ZW |
2584 | temp &= ~FDI_LINK_TRAIN_NONE; |
2585 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2586 | if (IS_GEN6(dev)) { | |
2587 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2588 | /* SNB-B */ | |
2589 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2590 | } | |
5eddb70b | 2591 | I915_WRITE(reg, temp); |
8db9d77b | 2592 | |
5eddb70b CW |
2593 | reg = FDI_RX_CTL(pipe); |
2594 | temp = I915_READ(reg); | |
8db9d77b ZW |
2595 | if (HAS_PCH_CPT(dev)) { |
2596 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2597 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2598 | } else { | |
2599 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2600 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2601 | } | |
5eddb70b CW |
2602 | I915_WRITE(reg, temp); |
2603 | ||
2604 | POSTING_READ(reg); | |
8db9d77b ZW |
2605 | udelay(150); |
2606 | ||
0206e353 | 2607 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2608 | reg = FDI_TX_CTL(pipe); |
2609 | temp = I915_READ(reg); | |
8db9d77b ZW |
2610 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2611 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2612 | I915_WRITE(reg, temp); |
2613 | ||
2614 | POSTING_READ(reg); | |
8db9d77b ZW |
2615 | udelay(500); |
2616 | ||
fa37d39e SP |
2617 | for (retry = 0; retry < 5; retry++) { |
2618 | reg = FDI_RX_IIR(pipe); | |
2619 | temp = I915_READ(reg); | |
2620 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2621 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2622 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2623 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2624 | break; | |
2625 | } | |
2626 | udelay(50); | |
8db9d77b | 2627 | } |
fa37d39e SP |
2628 | if (retry < 5) |
2629 | break; | |
8db9d77b ZW |
2630 | } |
2631 | if (i == 4) | |
5eddb70b | 2632 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2633 | |
2634 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2635 | } | |
2636 | ||
357555c0 JB |
2637 | /* Manual link training for Ivy Bridge A0 parts */ |
2638 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2639 | { | |
2640 | struct drm_device *dev = crtc->dev; | |
2641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2643 | int pipe = intel_crtc->pipe; | |
2644 | u32 reg, temp, i; | |
2645 | ||
2646 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2647 | for train result */ | |
2648 | reg = FDI_RX_IMR(pipe); | |
2649 | temp = I915_READ(reg); | |
2650 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2651 | temp &= ~FDI_RX_BIT_LOCK; | |
2652 | I915_WRITE(reg, temp); | |
2653 | ||
2654 | POSTING_READ(reg); | |
2655 | udelay(150); | |
2656 | ||
01a415fd DV |
2657 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2658 | I915_READ(FDI_RX_IIR(pipe))); | |
2659 | ||
357555c0 JB |
2660 | /* enable CPU FDI TX and PCH FDI RX */ |
2661 | reg = FDI_TX_CTL(pipe); | |
2662 | temp = I915_READ(reg); | |
627eb5a3 DV |
2663 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2664 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
357555c0 JB |
2665 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); |
2666 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2667 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2668 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2669 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2670 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2671 | ||
d74cf324 DV |
2672 | I915_WRITE(FDI_RX_MISC(pipe), |
2673 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2674 | ||
357555c0 JB |
2675 | reg = FDI_RX_CTL(pipe); |
2676 | temp = I915_READ(reg); | |
2677 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2678 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2679 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2680 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2681 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2682 | ||
2683 | POSTING_READ(reg); | |
2684 | udelay(150); | |
2685 | ||
0206e353 | 2686 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2687 | reg = FDI_TX_CTL(pipe); |
2688 | temp = I915_READ(reg); | |
2689 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2690 | temp |= snb_b_fdi_train_param[i]; | |
2691 | I915_WRITE(reg, temp); | |
2692 | ||
2693 | POSTING_READ(reg); | |
2694 | udelay(500); | |
2695 | ||
2696 | reg = FDI_RX_IIR(pipe); | |
2697 | temp = I915_READ(reg); | |
2698 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2699 | ||
2700 | if (temp & FDI_RX_BIT_LOCK || | |
2701 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2702 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
01a415fd | 2703 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); |
357555c0 JB |
2704 | break; |
2705 | } | |
2706 | } | |
2707 | if (i == 4) | |
2708 | DRM_ERROR("FDI train 1 fail!\n"); | |
2709 | ||
2710 | /* Train 2 */ | |
2711 | reg = FDI_TX_CTL(pipe); | |
2712 | temp = I915_READ(reg); | |
2713 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2714 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2715 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2716 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2717 | I915_WRITE(reg, temp); | |
2718 | ||
2719 | reg = FDI_RX_CTL(pipe); | |
2720 | temp = I915_READ(reg); | |
2721 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2722 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2723 | I915_WRITE(reg, temp); | |
2724 | ||
2725 | POSTING_READ(reg); | |
2726 | udelay(150); | |
2727 | ||
0206e353 | 2728 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2729 | reg = FDI_TX_CTL(pipe); |
2730 | temp = I915_READ(reg); | |
2731 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2732 | temp |= snb_b_fdi_train_param[i]; | |
2733 | I915_WRITE(reg, temp); | |
2734 | ||
2735 | POSTING_READ(reg); | |
2736 | udelay(500); | |
2737 | ||
2738 | reg = FDI_RX_IIR(pipe); | |
2739 | temp = I915_READ(reg); | |
2740 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2741 | ||
2742 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2743 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
01a415fd | 2744 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); |
357555c0 JB |
2745 | break; |
2746 | } | |
2747 | } | |
2748 | if (i == 4) | |
2749 | DRM_ERROR("FDI train 2 fail!\n"); | |
2750 | ||
2751 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2752 | } | |
2753 | ||
88cefb6c | 2754 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2755 | { |
88cefb6c | 2756 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2757 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2758 | int pipe = intel_crtc->pipe; |
5eddb70b | 2759 | u32 reg, temp; |
79e53945 | 2760 | |
c64e311e | 2761 | |
c98e9dcf | 2762 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2763 | reg = FDI_RX_CTL(pipe); |
2764 | temp = I915_READ(reg); | |
627eb5a3 DV |
2765 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2766 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2767 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2768 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2769 | ||
2770 | POSTING_READ(reg); | |
c98e9dcf JB |
2771 | udelay(200); |
2772 | ||
2773 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2774 | temp = I915_READ(reg); |
2775 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2776 | ||
2777 | POSTING_READ(reg); | |
c98e9dcf JB |
2778 | udelay(200); |
2779 | ||
20749730 PZ |
2780 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2781 | reg = FDI_TX_CTL(pipe); | |
2782 | temp = I915_READ(reg); | |
2783 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2784 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2785 | |
20749730 PZ |
2786 | POSTING_READ(reg); |
2787 | udelay(100); | |
6be4a607 | 2788 | } |
0e23b99d JB |
2789 | } |
2790 | ||
88cefb6c DV |
2791 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2792 | { | |
2793 | struct drm_device *dev = intel_crtc->base.dev; | |
2794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2795 | int pipe = intel_crtc->pipe; | |
2796 | u32 reg, temp; | |
2797 | ||
2798 | /* Switch from PCDclk to Rawclk */ | |
2799 | reg = FDI_RX_CTL(pipe); | |
2800 | temp = I915_READ(reg); | |
2801 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2802 | ||
2803 | /* Disable CPU FDI TX PLL */ | |
2804 | reg = FDI_TX_CTL(pipe); | |
2805 | temp = I915_READ(reg); | |
2806 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2807 | ||
2808 | POSTING_READ(reg); | |
2809 | udelay(100); | |
2810 | ||
2811 | reg = FDI_RX_CTL(pipe); | |
2812 | temp = I915_READ(reg); | |
2813 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2814 | ||
2815 | /* Wait for the clocks to turn off. */ | |
2816 | POSTING_READ(reg); | |
2817 | udelay(100); | |
2818 | } | |
2819 | ||
0fc932b8 JB |
2820 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2821 | { | |
2822 | struct drm_device *dev = crtc->dev; | |
2823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2825 | int pipe = intel_crtc->pipe; | |
2826 | u32 reg, temp; | |
2827 | ||
2828 | /* disable CPU FDI tx and PCH FDI rx */ | |
2829 | reg = FDI_TX_CTL(pipe); | |
2830 | temp = I915_READ(reg); | |
2831 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2832 | POSTING_READ(reg); | |
2833 | ||
2834 | reg = FDI_RX_CTL(pipe); | |
2835 | temp = I915_READ(reg); | |
2836 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2837 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2838 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2839 | ||
2840 | POSTING_READ(reg); | |
2841 | udelay(100); | |
2842 | ||
2843 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2844 | if (HAS_PCH_IBX(dev)) { |
2845 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2846 | } |
0fc932b8 JB |
2847 | |
2848 | /* still set train pattern 1 */ | |
2849 | reg = FDI_TX_CTL(pipe); | |
2850 | temp = I915_READ(reg); | |
2851 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2852 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2853 | I915_WRITE(reg, temp); | |
2854 | ||
2855 | reg = FDI_RX_CTL(pipe); | |
2856 | temp = I915_READ(reg); | |
2857 | if (HAS_PCH_CPT(dev)) { | |
2858 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2859 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2860 | } else { | |
2861 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2862 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2863 | } | |
2864 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2865 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2866 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2867 | I915_WRITE(reg, temp); |
2868 | ||
2869 | POSTING_READ(reg); | |
2870 | udelay(100); | |
2871 | } | |
2872 | ||
5bb61643 CW |
2873 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2874 | { | |
2875 | struct drm_device *dev = crtc->dev; | |
2876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2877 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2878 | unsigned long flags; |
2879 | bool pending; | |
2880 | ||
10d83730 VS |
2881 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2882 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2883 | return false; |
2884 | ||
2885 | spin_lock_irqsave(&dev->event_lock, flags); | |
2886 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2887 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2888 | ||
2889 | return pending; | |
2890 | } | |
2891 | ||
e6c3a2a6 CW |
2892 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2893 | { | |
0f91128d | 2894 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2895 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2896 | |
2897 | if (crtc->fb == NULL) | |
2898 | return; | |
2899 | ||
2c10d571 DV |
2900 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2901 | ||
5bb61643 CW |
2902 | wait_event(dev_priv->pending_flip_queue, |
2903 | !intel_crtc_has_pending_flip(crtc)); | |
2904 | ||
0f91128d CW |
2905 | mutex_lock(&dev->struct_mutex); |
2906 | intel_finish_fb(crtc->fb); | |
2907 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2908 | } |
2909 | ||
e615efe4 ED |
2910 | /* Program iCLKIP clock to the desired frequency */ |
2911 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2912 | { | |
2913 | struct drm_device *dev = crtc->dev; | |
2914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2915 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2916 | u32 temp; | |
2917 | ||
09153000 DV |
2918 | mutex_lock(&dev_priv->dpio_lock); |
2919 | ||
e615efe4 ED |
2920 | /* It is necessary to ungate the pixclk gate prior to programming |
2921 | * the divisors, and gate it back when it is done. | |
2922 | */ | |
2923 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2924 | ||
2925 | /* Disable SSCCTL */ | |
2926 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2927 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2928 | SBI_SSCCTL_DISABLE, | |
2929 | SBI_ICLK); | |
e615efe4 ED |
2930 | |
2931 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2932 | if (crtc->mode.clock == 20000) { | |
2933 | auxdiv = 1; | |
2934 | divsel = 0x41; | |
2935 | phaseinc = 0x20; | |
2936 | } else { | |
2937 | /* The iCLK virtual clock root frequency is in MHz, | |
2938 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2939 | * it is necessary to divide one by another, so we | |
2940 | * convert the virtual clock precision to KHz here for higher | |
2941 | * precision. | |
2942 | */ | |
2943 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2944 | u32 iclk_pi_range = 64; | |
2945 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2946 | ||
2947 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2948 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2949 | pi_value = desired_divisor % iclk_pi_range; | |
2950 | ||
2951 | auxdiv = 0; | |
2952 | divsel = msb_divisor_value - 2; | |
2953 | phaseinc = pi_value; | |
2954 | } | |
2955 | ||
2956 | /* This should not happen with any sane values */ | |
2957 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2958 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2959 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2960 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2961 | ||
2962 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2963 | crtc->mode.clock, | |
2964 | auxdiv, | |
2965 | divsel, | |
2966 | phasedir, | |
2967 | phaseinc); | |
2968 | ||
2969 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 2970 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
2971 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2972 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2973 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2974 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2975 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2976 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 2977 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
2978 | |
2979 | /* Program SSCAUXDIV */ | |
988d6ee8 | 2980 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
2981 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2982 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 2983 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
2984 | |
2985 | /* Enable modulator and associated divider */ | |
988d6ee8 | 2986 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 2987 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 2988 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
2989 | |
2990 | /* Wait for initialization time */ | |
2991 | udelay(24); | |
2992 | ||
2993 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
2994 | |
2995 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
2996 | } |
2997 | ||
275f01b2 DV |
2998 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
2999 | enum pipe pch_transcoder) | |
3000 | { | |
3001 | struct drm_device *dev = crtc->base.dev; | |
3002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3003 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3004 | ||
3005 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3006 | I915_READ(HTOTAL(cpu_transcoder))); | |
3007 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3008 | I915_READ(HBLANK(cpu_transcoder))); | |
3009 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3010 | I915_READ(HSYNC(cpu_transcoder))); | |
3011 | ||
3012 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3013 | I915_READ(VTOTAL(cpu_transcoder))); | |
3014 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3015 | I915_READ(VBLANK(cpu_transcoder))); | |
3016 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3017 | I915_READ(VSYNC(cpu_transcoder))); | |
3018 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3019 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3020 | } | |
3021 | ||
f67a559d JB |
3022 | /* |
3023 | * Enable PCH resources required for PCH ports: | |
3024 | * - PCH PLLs | |
3025 | * - FDI training & RX/TX | |
3026 | * - update transcoder timings | |
3027 | * - DP transcoding bits | |
3028 | * - transcoder | |
3029 | */ | |
3030 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3031 | { |
3032 | struct drm_device *dev = crtc->dev; | |
3033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3034 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3035 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3036 | u32 reg, temp; |
2c07245f | 3037 | |
ab9412ba | 3038 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3039 | |
cd986abb DV |
3040 | /* Write the TU size bits before fdi link training, so that error |
3041 | * detection works. */ | |
3042 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3043 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3044 | ||
c98e9dcf | 3045 | /* For PCH output, training FDI link */ |
674cf967 | 3046 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3047 | |
572deb37 DV |
3048 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3049 | * transcoder, and we actually should do this to not upset any PCH | |
3050 | * transcoder that already use the clock when we share it. | |
3051 | * | |
3052 | * Note that enable_pch_pll tries to do the right thing, but get_pch_pll | |
3053 | * unconditionally resets the pll - we need that to have the right LVDS | |
3054 | * enable sequence. */ | |
b6b4e185 | 3055 | ironlake_enable_pch_pll(intel_crtc); |
6f13b7b5 | 3056 | |
303b81e0 | 3057 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3058 | u32 sel; |
4b645f14 | 3059 | |
c98e9dcf | 3060 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
3061 | switch (pipe) { |
3062 | default: | |
3063 | case 0: | |
3064 | temp |= TRANSA_DPLL_ENABLE; | |
3065 | sel = TRANSA_DPLLB_SEL; | |
3066 | break; | |
3067 | case 1: | |
3068 | temp |= TRANSB_DPLL_ENABLE; | |
3069 | sel = TRANSB_DPLLB_SEL; | |
3070 | break; | |
3071 | case 2: | |
3072 | temp |= TRANSC_DPLL_ENABLE; | |
3073 | sel = TRANSC_DPLLB_SEL; | |
3074 | break; | |
d64311ab | 3075 | } |
ee7b9f93 JB |
3076 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3077 | temp |= sel; | |
3078 | else | |
3079 | temp &= ~sel; | |
c98e9dcf | 3080 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3081 | } |
5eddb70b | 3082 | |
d9b6cb56 JB |
3083 | /* set transcoder timing, panel must allow it */ |
3084 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3085 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3086 | |
303b81e0 | 3087 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3088 | |
c98e9dcf JB |
3089 | /* For PCH DP, enable TRANS_DP_CTL */ |
3090 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3091 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3092 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3093 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3094 | reg = TRANS_DP_CTL(pipe); |
3095 | temp = I915_READ(reg); | |
3096 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3097 | TRANS_DP_SYNC_MASK | |
3098 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3099 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3100 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3101 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3102 | |
3103 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3104 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3105 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3106 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3107 | |
3108 | switch (intel_trans_dp_port_sel(crtc)) { | |
3109 | case PCH_DP_B: | |
5eddb70b | 3110 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3111 | break; |
3112 | case PCH_DP_C: | |
5eddb70b | 3113 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3114 | break; |
3115 | case PCH_DP_D: | |
5eddb70b | 3116 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3117 | break; |
3118 | default: | |
e95d41e1 | 3119 | BUG(); |
32f9d658 | 3120 | } |
2c07245f | 3121 | |
5eddb70b | 3122 | I915_WRITE(reg, temp); |
6be4a607 | 3123 | } |
b52eb4dc | 3124 | |
b8a4f404 | 3125 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3126 | } |
3127 | ||
1507e5bd PZ |
3128 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3129 | { | |
3130 | struct drm_device *dev = crtc->dev; | |
3131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3133 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3134 | |
ab9412ba | 3135 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3136 | |
8c52b5e8 | 3137 | lpt_program_iclkip(crtc); |
1507e5bd | 3138 | |
0540e488 | 3139 | /* Set transcoder timing. */ |
275f01b2 | 3140 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3141 | |
937bb610 | 3142 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3143 | } |
3144 | ||
ee7b9f93 JB |
3145 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3146 | { | |
3147 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3148 | ||
3149 | if (pll == NULL) | |
3150 | return; | |
3151 | ||
3152 | if (pll->refcount == 0) { | |
3153 | WARN(1, "bad PCH PLL refcount\n"); | |
3154 | return; | |
3155 | } | |
3156 | ||
3157 | --pll->refcount; | |
3158 | intel_crtc->pch_pll = NULL; | |
3159 | } | |
3160 | ||
3161 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3162 | { | |
3163 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3164 | struct intel_pch_pll *pll; | |
3165 | int i; | |
3166 | ||
3167 | pll = intel_crtc->pch_pll; | |
3168 | if (pll) { | |
3169 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3170 | intel_crtc->base.base.id, pll->pll_reg); | |
3171 | goto prepare; | |
3172 | } | |
3173 | ||
98b6bd99 DV |
3174 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3175 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3176 | i = intel_crtc->pipe; | |
3177 | pll = &dev_priv->pch_plls[i]; | |
3178 | ||
3179 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3180 | intel_crtc->base.base.id, pll->pll_reg); | |
3181 | ||
3182 | goto found; | |
3183 | } | |
3184 | ||
ee7b9f93 JB |
3185 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3186 | pll = &dev_priv->pch_plls[i]; | |
3187 | ||
3188 | /* Only want to check enabled timings first */ | |
3189 | if (pll->refcount == 0) | |
3190 | continue; | |
3191 | ||
3192 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3193 | fp == I915_READ(pll->fp0_reg)) { | |
3194 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3195 | intel_crtc->base.base.id, | |
3196 | pll->pll_reg, pll->refcount, pll->active); | |
3197 | ||
3198 | goto found; | |
3199 | } | |
3200 | } | |
3201 | ||
3202 | /* Ok no matching timings, maybe there's a free one? */ | |
3203 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3204 | pll = &dev_priv->pch_plls[i]; | |
3205 | if (pll->refcount == 0) { | |
3206 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3207 | intel_crtc->base.base.id, pll->pll_reg); | |
3208 | goto found; | |
3209 | } | |
3210 | } | |
3211 | ||
3212 | return NULL; | |
3213 | ||
3214 | found: | |
3215 | intel_crtc->pch_pll = pll; | |
3216 | pll->refcount++; | |
84f44ce7 | 3217 | DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe)); |
ee7b9f93 JB |
3218 | prepare: /* separate function? */ |
3219 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3220 | |
e04c7350 CW |
3221 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3222 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3223 | POSTING_READ(pll->pll_reg); |
3224 | udelay(150); | |
e04c7350 CW |
3225 | |
3226 | I915_WRITE(pll->fp0_reg, fp); | |
3227 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3228 | pll->on = false; |
3229 | return pll; | |
3230 | } | |
3231 | ||
a1520318 | 3232 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3233 | { |
3234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3235 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3236 | u32 temp; |
3237 | ||
3238 | temp = I915_READ(dslreg); | |
3239 | udelay(500); | |
3240 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3241 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3242 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3243 | } |
3244 | } | |
3245 | ||
b074cec8 JB |
3246 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3247 | { | |
3248 | struct drm_device *dev = crtc->base.dev; | |
3249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3250 | int pipe = crtc->pipe; | |
3251 | ||
0ef37f3f | 3252 | if (crtc->config.pch_pfit.size) { |
b074cec8 JB |
3253 | /* Force use of hard-coded filter coefficients |
3254 | * as some pre-programmed values are broken, | |
3255 | * e.g. x201. | |
3256 | */ | |
3257 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3258 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3259 | PF_PIPE_SEL_IVB(pipe)); | |
3260 | else | |
3261 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3262 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3263 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
3264 | } | |
3265 | } | |
3266 | ||
f67a559d JB |
3267 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3268 | { | |
3269 | struct drm_device *dev = crtc->dev; | |
3270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3272 | struct intel_encoder *encoder; |
f67a559d JB |
3273 | int pipe = intel_crtc->pipe; |
3274 | int plane = intel_crtc->plane; | |
3275 | u32 temp; | |
f67a559d | 3276 | |
08a48469 DV |
3277 | WARN_ON(!crtc->enabled); |
3278 | ||
f67a559d JB |
3279 | if (intel_crtc->active) |
3280 | return; | |
3281 | ||
3282 | intel_crtc->active = true; | |
8664281b PZ |
3283 | |
3284 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3285 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3286 | ||
f67a559d JB |
3287 | intel_update_watermarks(dev); |
3288 | ||
3289 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3290 | temp = I915_READ(PCH_LVDS); | |
3291 | if ((temp & LVDS_PORT_EN) == 0) | |
3292 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3293 | } | |
3294 | ||
f67a559d | 3295 | |
5bfe2ac0 | 3296 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3297 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3298 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3299 | * enabling. */ | |
88cefb6c | 3300 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3301 | } else { |
3302 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3303 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3304 | } | |
f67a559d | 3305 | |
bf49ec8c DV |
3306 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3307 | if (encoder->pre_enable) | |
3308 | encoder->pre_enable(encoder); | |
f67a559d JB |
3309 | |
3310 | /* Enable panel fitting for LVDS */ | |
b074cec8 | 3311 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3312 | |
9c54c0dd JB |
3313 | /* |
3314 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3315 | * clocks enabled | |
3316 | */ | |
3317 | intel_crtc_load_lut(crtc); | |
3318 | ||
5bfe2ac0 DV |
3319 | intel_enable_pipe(dev_priv, pipe, |
3320 | intel_crtc->config.has_pch_encoder); | |
f67a559d JB |
3321 | intel_enable_plane(dev_priv, plane, pipe); |
3322 | ||
5bfe2ac0 | 3323 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3324 | ironlake_pch_enable(crtc); |
c98e9dcf | 3325 | |
d1ebd816 | 3326 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3327 | intel_update_fbc(dev); |
d1ebd816 BW |
3328 | mutex_unlock(&dev->struct_mutex); |
3329 | ||
6b383a7f | 3330 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3331 | |
fa5c73b1 DV |
3332 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3333 | encoder->enable(encoder); | |
61b77ddd DV |
3334 | |
3335 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3336 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3337 | |
3338 | /* | |
3339 | * There seems to be a race in PCH platform hw (at least on some | |
3340 | * outputs) where an enabled pipe still completes any pageflip right | |
3341 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3342 | * as the first vblank happend, everything works as expected. Hence just | |
3343 | * wait for one vblank before returning to avoid strange things | |
3344 | * happening. | |
3345 | */ | |
3346 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3347 | } |
3348 | ||
4f771f10 PZ |
3349 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3350 | { | |
3351 | struct drm_device *dev = crtc->dev; | |
3352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3353 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3354 | struct intel_encoder *encoder; | |
3355 | int pipe = intel_crtc->pipe; | |
3356 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3357 | |
3358 | WARN_ON(!crtc->enabled); | |
3359 | ||
3360 | if (intel_crtc->active) | |
3361 | return; | |
3362 | ||
3363 | intel_crtc->active = true; | |
8664281b PZ |
3364 | |
3365 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3366 | if (intel_crtc->config.has_pch_encoder) | |
3367 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3368 | ||
4f771f10 PZ |
3369 | intel_update_watermarks(dev); |
3370 | ||
5bfe2ac0 | 3371 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3372 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3373 | |
3374 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3375 | if (encoder->pre_enable) | |
3376 | encoder->pre_enable(encoder); | |
3377 | ||
1f544388 | 3378 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3379 | |
1f544388 | 3380 | /* Enable panel fitting for eDP */ |
b074cec8 | 3381 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3382 | |
3383 | /* | |
3384 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3385 | * clocks enabled | |
3386 | */ | |
3387 | intel_crtc_load_lut(crtc); | |
3388 | ||
1f544388 | 3389 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3390 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3391 | |
5bfe2ac0 DV |
3392 | intel_enable_pipe(dev_priv, pipe, |
3393 | intel_crtc->config.has_pch_encoder); | |
4f771f10 PZ |
3394 | intel_enable_plane(dev_priv, plane, pipe); |
3395 | ||
5bfe2ac0 | 3396 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3397 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3398 | |
3399 | mutex_lock(&dev->struct_mutex); | |
3400 | intel_update_fbc(dev); | |
3401 | mutex_unlock(&dev->struct_mutex); | |
3402 | ||
3403 | intel_crtc_update_cursor(crtc, true); | |
3404 | ||
3405 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3406 | encoder->enable(encoder); | |
3407 | ||
4f771f10 PZ |
3408 | /* |
3409 | * There seems to be a race in PCH platform hw (at least on some | |
3410 | * outputs) where an enabled pipe still completes any pageflip right | |
3411 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3412 | * as the first vblank happend, everything works as expected. Hence just | |
3413 | * wait for one vblank before returning to avoid strange things | |
3414 | * happening. | |
3415 | */ | |
3416 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3417 | } | |
3418 | ||
6be4a607 JB |
3419 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3420 | { | |
3421 | struct drm_device *dev = crtc->dev; | |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3424 | struct intel_encoder *encoder; |
6be4a607 JB |
3425 | int pipe = intel_crtc->pipe; |
3426 | int plane = intel_crtc->plane; | |
5eddb70b | 3427 | u32 reg, temp; |
b52eb4dc | 3428 | |
ef9c3aee | 3429 | |
f7abfe8b CW |
3430 | if (!intel_crtc->active) |
3431 | return; | |
3432 | ||
ea9d758d DV |
3433 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3434 | encoder->disable(encoder); | |
3435 | ||
e6c3a2a6 | 3436 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3437 | drm_vblank_off(dev, pipe); |
6b383a7f | 3438 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3439 | |
b24e7179 | 3440 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3441 | |
973d04f9 CW |
3442 | if (dev_priv->cfb_plane == plane) |
3443 | intel_disable_fbc(dev); | |
2c07245f | 3444 | |
8664281b | 3445 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 3446 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3447 | |
6be4a607 | 3448 | /* Disable PF */ |
9db4a9c7 JB |
3449 | I915_WRITE(PF_CTL(pipe), 0); |
3450 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3451 | |
bf49ec8c DV |
3452 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3453 | if (encoder->post_disable) | |
3454 | encoder->post_disable(encoder); | |
2c07245f | 3455 | |
0fc932b8 | 3456 | ironlake_fdi_disable(crtc); |
249c0e64 | 3457 | |
b8a4f404 | 3458 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
8664281b | 3459 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); |
913d8d11 | 3460 | |
6be4a607 JB |
3461 | if (HAS_PCH_CPT(dev)) { |
3462 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3463 | reg = TRANS_DP_CTL(pipe); |
3464 | temp = I915_READ(reg); | |
3465 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3466 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3467 | I915_WRITE(reg, temp); |
6be4a607 JB |
3468 | |
3469 | /* disable DPLL_SEL */ | |
3470 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3471 | switch (pipe) { |
3472 | case 0: | |
d64311ab | 3473 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3474 | break; |
3475 | case 1: | |
6be4a607 | 3476 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3477 | break; |
3478 | case 2: | |
4b645f14 | 3479 | /* C shares PLL A or B */ |
d64311ab | 3480 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3481 | break; |
3482 | default: | |
3483 | BUG(); /* wtf */ | |
3484 | } | |
6be4a607 | 3485 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3486 | } |
e3421a18 | 3487 | |
6be4a607 | 3488 | /* disable PCH DPLL */ |
ee7b9f93 | 3489 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3490 | |
88cefb6c | 3491 | ironlake_fdi_pll_disable(intel_crtc); |
6b383a7f | 3492 | |
f7abfe8b | 3493 | intel_crtc->active = false; |
6b383a7f | 3494 | intel_update_watermarks(dev); |
d1ebd816 BW |
3495 | |
3496 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3497 | intel_update_fbc(dev); |
d1ebd816 | 3498 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3499 | } |
1b3c7a47 | 3500 | |
4f771f10 | 3501 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3502 | { |
4f771f10 PZ |
3503 | struct drm_device *dev = crtc->dev; |
3504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3506 | struct intel_encoder *encoder; |
3507 | int pipe = intel_crtc->pipe; | |
3508 | int plane = intel_crtc->plane; | |
3b117c8f | 3509 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3510 | |
4f771f10 PZ |
3511 | if (!intel_crtc->active) |
3512 | return; | |
3513 | ||
3514 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3515 | encoder->disable(encoder); | |
3516 | ||
3517 | intel_crtc_wait_for_pending_flips(crtc); | |
3518 | drm_vblank_off(dev, pipe); | |
3519 | intel_crtc_update_cursor(crtc, false); | |
3520 | ||
3521 | intel_disable_plane(dev_priv, plane, pipe); | |
3522 | ||
3523 | if (dev_priv->cfb_plane == plane) | |
3524 | intel_disable_fbc(dev); | |
3525 | ||
8664281b PZ |
3526 | if (intel_crtc->config.has_pch_encoder) |
3527 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3528 | intel_disable_pipe(dev_priv, pipe); |
3529 | ||
ad80a810 | 3530 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3531 | |
f7708f78 PZ |
3532 | /* XXX: Once we have proper panel fitter state tracking implemented with |
3533 | * hardware state read/check support we should switch to only disable | |
3534 | * the panel fitter when we know it's used. */ | |
b97186f0 PZ |
3535 | if (intel_display_power_enabled(dev, |
3536 | POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) { | |
f7708f78 PZ |
3537 | I915_WRITE(PF_CTL(pipe), 0); |
3538 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3539 | } | |
4f771f10 | 3540 | |
1f544388 | 3541 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3542 | |
3543 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3544 | if (encoder->post_disable) | |
3545 | encoder->post_disable(encoder); | |
3546 | ||
88adfff1 | 3547 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3548 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3549 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3550 | intel_ddi_fdi_disable(crtc); |
83616634 | 3551 | } |
4f771f10 PZ |
3552 | |
3553 | intel_crtc->active = false; | |
3554 | intel_update_watermarks(dev); | |
3555 | ||
3556 | mutex_lock(&dev->struct_mutex); | |
3557 | intel_update_fbc(dev); | |
3558 | mutex_unlock(&dev->struct_mutex); | |
3559 | } | |
3560 | ||
ee7b9f93 JB |
3561 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3562 | { | |
3563 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3564 | intel_put_pch_pll(intel_crtc); | |
3565 | } | |
3566 | ||
6441ab5f PZ |
3567 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3568 | { | |
a5c961d1 PZ |
3569 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3570 | ||
3571 | /* Stop saying we're using TRANSCODER_EDP because some other CRTC might | |
3572 | * start using it. */ | |
3b117c8f | 3573 | intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
a5c961d1 | 3574 | |
6441ab5f PZ |
3575 | intel_ddi_put_crtc_pll(crtc); |
3576 | } | |
3577 | ||
02e792fb DV |
3578 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3579 | { | |
02e792fb | 3580 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3581 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3582 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3583 | |
23f09ce3 | 3584 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3585 | dev_priv->mm.interruptible = false; |
3586 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3587 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3588 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3589 | } |
02e792fb | 3590 | |
5dcdbcb0 CW |
3591 | /* Let userspace switch the overlay on again. In most cases userspace |
3592 | * has to recompute where to put it anyway. | |
3593 | */ | |
02e792fb DV |
3594 | } |
3595 | ||
61bc95c1 EE |
3596 | /** |
3597 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3598 | * cursor plane briefly if not already running after enabling the display | |
3599 | * plane. | |
3600 | * This workaround avoids occasional blank screens when self refresh is | |
3601 | * enabled. | |
3602 | */ | |
3603 | static void | |
3604 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3605 | { | |
3606 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3607 | ||
3608 | if ((cntl & CURSOR_MODE) == 0) { | |
3609 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3610 | ||
3611 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3612 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3613 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3614 | I915_WRITE(CURCNTR(pipe), cntl); | |
3615 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3616 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3617 | } | |
3618 | } | |
3619 | ||
2dd24552 JB |
3620 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3621 | { | |
3622 | struct drm_device *dev = crtc->base.dev; | |
3623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3624 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3625 | ||
3626 | if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
3627 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))) | |
3628 | return; | |
3629 | ||
3630 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); | |
3631 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
3632 | ||
3633 | /* | |
3634 | * Enable automatic panel scaling so that non-native modes | |
3635 | * fill the screen. The panel fitter should only be | |
3636 | * adjusted whilst the pipe is disabled, according to | |
3637 | * register description and PRM. | |
3638 | */ | |
3639 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
b074cec8 JB |
3640 | pipe_config->gmch_pfit.control, |
3641 | pipe_config->gmch_pfit.pgm_ratios); | |
2dd24552 | 3642 | |
b074cec8 JB |
3643 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3644 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3645 | |
3646 | /* Border color in case we don't scale up to the full screen. Black by | |
3647 | * default, change to something else for debugging. */ | |
3648 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3649 | } |
3650 | ||
89b667f8 JB |
3651 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3652 | { | |
3653 | struct drm_device *dev = crtc->dev; | |
3654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3655 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3656 | struct intel_encoder *encoder; | |
3657 | int pipe = intel_crtc->pipe; | |
3658 | int plane = intel_crtc->plane; | |
3659 | ||
3660 | WARN_ON(!crtc->enabled); | |
3661 | ||
3662 | if (intel_crtc->active) | |
3663 | return; | |
3664 | ||
3665 | intel_crtc->active = true; | |
3666 | intel_update_watermarks(dev); | |
3667 | ||
3668 | mutex_lock(&dev_priv->dpio_lock); | |
3669 | ||
3670 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3671 | if (encoder->pre_pll_enable) | |
3672 | encoder->pre_pll_enable(encoder); | |
3673 | ||
3674 | intel_enable_pll(dev_priv, pipe); | |
3675 | ||
3676 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3677 | if (encoder->pre_enable) | |
3678 | encoder->pre_enable(encoder); | |
3679 | ||
3680 | /* VLV wants encoder enabling _before_ the pipe is up. */ | |
3681 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3682 | encoder->enable(encoder); | |
3683 | ||
2dd24552 JB |
3684 | /* Enable panel fitting for eDP */ |
3685 | i9xx_pfit_enable(intel_crtc); | |
3686 | ||
89b667f8 JB |
3687 | intel_enable_pipe(dev_priv, pipe, false); |
3688 | intel_enable_plane(dev_priv, plane, pipe); | |
3689 | ||
3690 | intel_crtc_load_lut(crtc); | |
3691 | intel_update_fbc(dev); | |
3692 | ||
3693 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | |
3694 | intel_crtc_dpms_overlay(intel_crtc, true); | |
3695 | intel_crtc_update_cursor(crtc, true); | |
3696 | ||
3697 | mutex_unlock(&dev_priv->dpio_lock); | |
3698 | } | |
3699 | ||
0b8765c6 | 3700 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3701 | { |
3702 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3703 | struct drm_i915_private *dev_priv = dev->dev_private; |
3704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3705 | struct intel_encoder *encoder; |
79e53945 | 3706 | int pipe = intel_crtc->pipe; |
80824003 | 3707 | int plane = intel_crtc->plane; |
79e53945 | 3708 | |
08a48469 DV |
3709 | WARN_ON(!crtc->enabled); |
3710 | ||
f7abfe8b CW |
3711 | if (intel_crtc->active) |
3712 | return; | |
3713 | ||
3714 | intel_crtc->active = true; | |
6b383a7f CW |
3715 | intel_update_watermarks(dev); |
3716 | ||
63d7bbe9 | 3717 | intel_enable_pll(dev_priv, pipe); |
9d6d9f19 MK |
3718 | |
3719 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3720 | if (encoder->pre_enable) | |
3721 | encoder->pre_enable(encoder); | |
3722 | ||
2dd24552 JB |
3723 | /* Enable panel fitting for LVDS */ |
3724 | i9xx_pfit_enable(intel_crtc); | |
3725 | ||
040484af | 3726 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3727 | intel_enable_plane(dev_priv, plane, pipe); |
61bc95c1 EE |
3728 | if (IS_G4X(dev)) |
3729 | g4x_fixup_plane(dev_priv, pipe); | |
79e53945 | 3730 | |
0b8765c6 | 3731 | intel_crtc_load_lut(crtc); |
bed4a673 | 3732 | intel_update_fbc(dev); |
79e53945 | 3733 | |
0b8765c6 JB |
3734 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3735 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3736 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3737 | |
fa5c73b1 DV |
3738 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3739 | encoder->enable(encoder); | |
0b8765c6 | 3740 | } |
79e53945 | 3741 | |
87476d63 DV |
3742 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3743 | { | |
3744 | struct drm_device *dev = crtc->base.dev; | |
3745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3746 | enum pipe pipe; | |
3747 | uint32_t pctl = I915_READ(PFIT_CONTROL); | |
3748 | ||
3749 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
3750 | ||
3751 | if (INTEL_INFO(dev)->gen >= 4) | |
3752 | pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT; | |
3753 | else | |
3754 | pipe = PIPE_B; | |
3755 | ||
3756 | if (pipe == crtc->pipe) { | |
3757 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl); | |
3758 | I915_WRITE(PFIT_CONTROL, 0); | |
3759 | } | |
3760 | } | |
3761 | ||
0b8765c6 JB |
3762 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3763 | { | |
3764 | struct drm_device *dev = crtc->dev; | |
3765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3767 | struct intel_encoder *encoder; |
0b8765c6 JB |
3768 | int pipe = intel_crtc->pipe; |
3769 | int plane = intel_crtc->plane; | |
ef9c3aee | 3770 | |
f7abfe8b CW |
3771 | if (!intel_crtc->active) |
3772 | return; | |
3773 | ||
ea9d758d DV |
3774 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3775 | encoder->disable(encoder); | |
3776 | ||
0b8765c6 | 3777 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3778 | intel_crtc_wait_for_pending_flips(crtc); |
3779 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3780 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3781 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3782 | |
973d04f9 CW |
3783 | if (dev_priv->cfb_plane == plane) |
3784 | intel_disable_fbc(dev); | |
79e53945 | 3785 | |
b24e7179 | 3786 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3787 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 3788 | |
87476d63 | 3789 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 3790 | |
89b667f8 JB |
3791 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3792 | if (encoder->post_disable) | |
3793 | encoder->post_disable(encoder); | |
3794 | ||
63d7bbe9 | 3795 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3796 | |
f7abfe8b | 3797 | intel_crtc->active = false; |
6b383a7f CW |
3798 | intel_update_fbc(dev); |
3799 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3800 | } |
3801 | ||
ee7b9f93 JB |
3802 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3803 | { | |
3804 | } | |
3805 | ||
976f8a20 DV |
3806 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3807 | bool enabled) | |
2c07245f ZW |
3808 | { |
3809 | struct drm_device *dev = crtc->dev; | |
3810 | struct drm_i915_master_private *master_priv; | |
3811 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3812 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3813 | |
3814 | if (!dev->primary->master) | |
3815 | return; | |
3816 | ||
3817 | master_priv = dev->primary->master->driver_priv; | |
3818 | if (!master_priv->sarea_priv) | |
3819 | return; | |
3820 | ||
79e53945 JB |
3821 | switch (pipe) { |
3822 | case 0: | |
3823 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3824 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3825 | break; | |
3826 | case 1: | |
3827 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3828 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3829 | break; | |
3830 | default: | |
9db4a9c7 | 3831 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3832 | break; |
3833 | } | |
79e53945 JB |
3834 | } |
3835 | ||
976f8a20 DV |
3836 | /** |
3837 | * Sets the power management mode of the pipe and plane. | |
3838 | */ | |
3839 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3840 | { | |
3841 | struct drm_device *dev = crtc->dev; | |
3842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3843 | struct intel_encoder *intel_encoder; | |
3844 | bool enable = false; | |
3845 | ||
3846 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3847 | enable |= intel_encoder->connectors_active; | |
3848 | ||
3849 | if (enable) | |
3850 | dev_priv->display.crtc_enable(crtc); | |
3851 | else | |
3852 | dev_priv->display.crtc_disable(crtc); | |
3853 | ||
3854 | intel_crtc_update_sarea(crtc, enable); | |
3855 | } | |
3856 | ||
cdd59983 CW |
3857 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3858 | { | |
cdd59983 | 3859 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3860 | struct drm_connector *connector; |
ee7b9f93 | 3861 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 3862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 3863 | |
976f8a20 DV |
3864 | /* crtc should still be enabled when we disable it. */ |
3865 | WARN_ON(!crtc->enabled); | |
3866 | ||
3867 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 3868 | intel_crtc->eld_vld = false; |
976f8a20 | 3869 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
3870 | dev_priv->display.off(crtc); |
3871 | ||
931872fc CW |
3872 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3873 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3874 | |
3875 | if (crtc->fb) { | |
3876 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3877 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3878 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3879 | crtc->fb = NULL; |
3880 | } | |
3881 | ||
3882 | /* Update computed state. */ | |
3883 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3884 | if (!connector->encoder || !connector->encoder->crtc) | |
3885 | continue; | |
3886 | ||
3887 | if (connector->encoder->crtc != crtc) | |
3888 | continue; | |
3889 | ||
3890 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3891 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3892 | } |
3893 | } | |
3894 | ||
a261b246 | 3895 | void intel_modeset_disable(struct drm_device *dev) |
79e53945 | 3896 | { |
a261b246 DV |
3897 | struct drm_crtc *crtc; |
3898 | ||
3899 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3900 | if (crtc->enabled) | |
3901 | intel_crtc_disable(crtc); | |
3902 | } | |
79e53945 JB |
3903 | } |
3904 | ||
ea5b213a | 3905 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3906 | { |
4ef69c7a | 3907 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3908 | |
ea5b213a CW |
3909 | drm_encoder_cleanup(encoder); |
3910 | kfree(intel_encoder); | |
7e7d76c3 JB |
3911 | } |
3912 | ||
5ab432ef DV |
3913 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3914 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the | |
3915 | * state of the entire output pipe. */ | |
3916 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) | |
7e7d76c3 | 3917 | { |
5ab432ef DV |
3918 | if (mode == DRM_MODE_DPMS_ON) { |
3919 | encoder->connectors_active = true; | |
3920 | ||
b2cabb0e | 3921 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3922 | } else { |
3923 | encoder->connectors_active = false; | |
3924 | ||
b2cabb0e | 3925 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3926 | } |
79e53945 JB |
3927 | } |
3928 | ||
0a91ca29 DV |
3929 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3930 | * internal consistency). */ | |
b980514c | 3931 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3932 | { |
0a91ca29 DV |
3933 | if (connector->get_hw_state(connector)) { |
3934 | struct intel_encoder *encoder = connector->encoder; | |
3935 | struct drm_crtc *crtc; | |
3936 | bool encoder_enabled; | |
3937 | enum pipe pipe; | |
3938 | ||
3939 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3940 | connector->base.base.id, | |
3941 | drm_get_connector_name(&connector->base)); | |
3942 | ||
3943 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3944 | "wrong connector dpms state\n"); | |
3945 | WARN(connector->base.encoder != &encoder->base, | |
3946 | "active connector not linked to encoder\n"); | |
3947 | WARN(!encoder->connectors_active, | |
3948 | "encoder->connectors_active not set\n"); | |
3949 | ||
3950 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3951 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3952 | if (WARN_ON(!encoder->base.crtc)) | |
3953 | return; | |
3954 | ||
3955 | crtc = encoder->base.crtc; | |
3956 | ||
3957 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3958 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3959 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3960 | "encoder active on the wrong pipe\n"); | |
3961 | } | |
79e53945 JB |
3962 | } |
3963 | ||
5ab432ef DV |
3964 | /* Even simpler default implementation, if there's really no special case to |
3965 | * consider. */ | |
3966 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3967 | { |
5ab432ef | 3968 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3969 | |
5ab432ef DV |
3970 | /* All the simple cases only support two dpms states. */ |
3971 | if (mode != DRM_MODE_DPMS_ON) | |
3972 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 3973 | |
5ab432ef DV |
3974 | if (mode == connector->dpms) |
3975 | return; | |
3976 | ||
3977 | connector->dpms = mode; | |
3978 | ||
3979 | /* Only need to change hw state when actually enabled */ | |
3980 | if (encoder->base.crtc) | |
3981 | intel_encoder_dpms(encoder, mode); | |
3982 | else | |
8af6cf88 | 3983 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 3984 | |
b980514c | 3985 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
3986 | } |
3987 | ||
f0947c37 DV |
3988 | /* Simple connector->get_hw_state implementation for encoders that support only |
3989 | * one connector and no cloning and hence the encoder state determines the state | |
3990 | * of the connector. */ | |
3991 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 3992 | { |
24929352 | 3993 | enum pipe pipe = 0; |
f0947c37 | 3994 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 3995 | |
f0947c37 | 3996 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
3997 | } |
3998 | ||
1857e1da DV |
3999 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4000 | struct intel_crtc_config *pipe_config) | |
4001 | { | |
4002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4003 | struct intel_crtc *pipe_B_crtc = | |
4004 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4005 | ||
4006 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4007 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4008 | if (pipe_config->fdi_lanes > 4) { | |
4009 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4010 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4011 | return false; | |
4012 | } | |
4013 | ||
4014 | if (IS_HASWELL(dev)) { | |
4015 | if (pipe_config->fdi_lanes > 2) { | |
4016 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4017 | pipe_config->fdi_lanes); | |
4018 | return false; | |
4019 | } else { | |
4020 | return true; | |
4021 | } | |
4022 | } | |
4023 | ||
4024 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4025 | return true; | |
4026 | ||
4027 | /* Ivybridge 3 pipe is really complicated */ | |
4028 | switch (pipe) { | |
4029 | case PIPE_A: | |
4030 | return true; | |
4031 | case PIPE_B: | |
4032 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4033 | pipe_config->fdi_lanes > 2) { | |
4034 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4035 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4036 | return false; | |
4037 | } | |
4038 | return true; | |
4039 | case PIPE_C: | |
1e833f40 | 4040 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4041 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4042 | if (pipe_config->fdi_lanes > 2) { | |
4043 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4044 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4045 | return false; | |
4046 | } | |
4047 | } else { | |
4048 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4049 | return false; | |
4050 | } | |
4051 | return true; | |
4052 | default: | |
4053 | BUG(); | |
4054 | } | |
4055 | } | |
4056 | ||
e29c22c0 DV |
4057 | #define RETRY 1 |
4058 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4059 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4060 | { |
1857e1da | 4061 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 DV |
4062 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
4063 | int target_clock, lane, link_bw; | |
e29c22c0 | 4064 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4065 | |
e29c22c0 | 4066 | retry: |
877d48d5 DV |
4067 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4068 | * each output octet as 10 bits. The actual frequency | |
4069 | * is stored as a divider into a 100MHz clock, and the | |
4070 | * mode pixel clock is stored in units of 1KHz. | |
4071 | * Hence the bw of each lane in terms of the mode signal | |
4072 | * is: | |
4073 | */ | |
4074 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4075 | ||
4076 | if (pipe_config->pixel_target_clock) | |
4077 | target_clock = pipe_config->pixel_target_clock; | |
4078 | else | |
4079 | target_clock = adjusted_mode->clock; | |
4080 | ||
4081 | lane = ironlake_get_lanes_required(target_clock, link_bw, | |
4082 | pipe_config->pipe_bpp); | |
4083 | ||
4084 | pipe_config->fdi_lanes = lane; | |
4085 | ||
4086 | if (pipe_config->pixel_multiplier > 1) | |
4087 | link_bw *= pipe_config->pixel_multiplier; | |
4088 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock, | |
4089 | link_bw, &pipe_config->fdi_m_n); | |
1857e1da | 4090 | |
e29c22c0 DV |
4091 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4092 | intel_crtc->pipe, pipe_config); | |
4093 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4094 | pipe_config->pipe_bpp -= 2*3; | |
4095 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4096 | pipe_config->pipe_bpp); | |
4097 | needs_recompute = true; | |
4098 | pipe_config->bw_constrained = true; | |
4099 | ||
4100 | goto retry; | |
4101 | } | |
4102 | ||
4103 | if (needs_recompute) | |
4104 | return RETRY; | |
4105 | ||
4106 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4107 | } |
4108 | ||
e29c22c0 DV |
4109 | static int intel_crtc_compute_config(struct drm_crtc *crtc, |
4110 | struct intel_crtc_config *pipe_config) | |
79e53945 | 4111 | { |
2c07245f | 4112 | struct drm_device *dev = crtc->dev; |
b8cecdf5 | 4113 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4114 | |
bad720ff | 4115 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 4116 | /* FDI link clock is fixed at 2.7G */ |
b8cecdf5 DV |
4117 | if (pipe_config->requested_mode.clock * 3 |
4118 | > IRONLAKE_FDI_FREQ * 4) | |
e29c22c0 | 4119 | return -EINVAL; |
2c07245f | 4120 | } |
89749350 | 4121 | |
f9bef081 DV |
4122 | /* All interlaced capable intel hw wants timings in frames. Note though |
4123 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
4124 | * timings, so we need to be careful not to clobber these.*/ | |
7ae89233 | 4125 | if (!pipe_config->timings_set) |
f9bef081 | 4126 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
89749350 | 4127 | |
8693a824 DL |
4128 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4129 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4130 | */ |
4131 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4132 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4133 | return -EINVAL; |
44f46b42 | 4134 | |
bd080ee5 | 4135 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4136 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4137 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4138 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4139 | * for lvds. */ | |
4140 | pipe_config->pipe_bpp = 8*3; | |
4141 | } | |
4142 | ||
877d48d5 | 4143 | if (pipe_config->has_pch_encoder) |
1857e1da | 4144 | return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config); |
877d48d5 | 4145 | |
e29c22c0 | 4146 | return 0; |
79e53945 JB |
4147 | } |
4148 | ||
25eb05fc JB |
4149 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4150 | { | |
4151 | return 400000; /* FIXME */ | |
4152 | } | |
4153 | ||
e70236a8 JB |
4154 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4155 | { | |
4156 | return 400000; | |
4157 | } | |
79e53945 | 4158 | |
e70236a8 | 4159 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4160 | { |
e70236a8 JB |
4161 | return 333000; |
4162 | } | |
79e53945 | 4163 | |
e70236a8 JB |
4164 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4165 | { | |
4166 | return 200000; | |
4167 | } | |
79e53945 | 4168 | |
e70236a8 JB |
4169 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4170 | { | |
4171 | u16 gcfgc = 0; | |
79e53945 | 4172 | |
e70236a8 JB |
4173 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4174 | ||
4175 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4176 | return 133000; | |
4177 | else { | |
4178 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4179 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4180 | return 333000; | |
4181 | default: | |
4182 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4183 | return 190000; | |
79e53945 | 4184 | } |
e70236a8 JB |
4185 | } |
4186 | } | |
4187 | ||
4188 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4189 | { | |
4190 | return 266000; | |
4191 | } | |
4192 | ||
4193 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4194 | { | |
4195 | u16 hpllcc = 0; | |
4196 | /* Assume that the hardware is in the high speed state. This | |
4197 | * should be the default. | |
4198 | */ | |
4199 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4200 | case GC_CLOCK_133_200: | |
4201 | case GC_CLOCK_100_200: | |
4202 | return 200000; | |
4203 | case GC_CLOCK_166_250: | |
4204 | return 250000; | |
4205 | case GC_CLOCK_100_133: | |
79e53945 | 4206 | return 133000; |
e70236a8 | 4207 | } |
79e53945 | 4208 | |
e70236a8 JB |
4209 | /* Shouldn't happen */ |
4210 | return 0; | |
4211 | } | |
79e53945 | 4212 | |
e70236a8 JB |
4213 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4214 | { | |
4215 | return 133000; | |
79e53945 JB |
4216 | } |
4217 | ||
2c07245f | 4218 | static void |
e69d0bc1 | 4219 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
2c07245f ZW |
4220 | { |
4221 | while (*num > 0xffffff || *den > 0xffffff) { | |
4222 | *num >>= 1; | |
4223 | *den >>= 1; | |
4224 | } | |
4225 | } | |
4226 | ||
e69d0bc1 DV |
4227 | void |
4228 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4229 | int pixel_clock, int link_clock, | |
4230 | struct intel_link_m_n *m_n) | |
2c07245f | 4231 | { |
e69d0bc1 | 4232 | m_n->tu = 64; |
22ed1113 CW |
4233 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
4234 | m_n->gmch_n = link_clock * nlanes * 8; | |
e69d0bc1 | 4235 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
22ed1113 CW |
4236 | m_n->link_m = pixel_clock; |
4237 | m_n->link_n = link_clock; | |
e69d0bc1 | 4238 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2c07245f ZW |
4239 | } |
4240 | ||
a7615030 CW |
4241 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4242 | { | |
72bbe58c KP |
4243 | if (i915_panel_use_ssc >= 0) |
4244 | return i915_panel_use_ssc != 0; | |
4245 | return dev_priv->lvds_use_ssc | |
435793df | 4246 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4247 | } |
4248 | ||
a0c4da24 JB |
4249 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4250 | { | |
4251 | struct drm_device *dev = crtc->dev; | |
4252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4253 | int refclk = 27000; /* for DP & HDMI */ | |
4254 | ||
4255 | return 100000; /* only one validated so far */ | |
4256 | ||
4257 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
4258 | refclk = 96000; | |
4259 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4260 | if (intel_panel_use_ssc(dev_priv)) | |
4261 | refclk = 100000; | |
4262 | else | |
4263 | refclk = 96000; | |
4264 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4265 | refclk = 100000; | |
4266 | } | |
4267 | ||
4268 | return refclk; | |
4269 | } | |
4270 | ||
c65d77d8 JB |
4271 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4272 | { | |
4273 | struct drm_device *dev = crtc->dev; | |
4274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4275 | int refclk; | |
4276 | ||
a0c4da24 JB |
4277 | if (IS_VALLEYVIEW(dev)) { |
4278 | refclk = vlv_get_refclk(crtc); | |
4279 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
4280 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4281 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
4282 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4283 | refclk / 1000); | |
4284 | } else if (!IS_GEN2(dev)) { | |
4285 | refclk = 96000; | |
4286 | } else { | |
4287 | refclk = 48000; | |
4288 | } | |
4289 | ||
4290 | return refclk; | |
4291 | } | |
4292 | ||
f47709a9 | 4293 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc) |
c65d77d8 | 4294 | { |
f47709a9 DV |
4295 | unsigned dotclock = crtc->config.adjusted_mode.clock; |
4296 | struct dpll *clock = &crtc->config.dpll; | |
4297 | ||
c65d77d8 JB |
4298 | /* SDVO TV has fixed PLL values depend on its clock range, |
4299 | this mirrors vbios setting. */ | |
f47709a9 | 4300 | if (dotclock >= 100000 && dotclock < 140500) { |
c65d77d8 JB |
4301 | clock->p1 = 2; |
4302 | clock->p2 = 10; | |
4303 | clock->n = 3; | |
4304 | clock->m1 = 16; | |
4305 | clock->m2 = 8; | |
f47709a9 | 4306 | } else if (dotclock >= 140500 && dotclock <= 200000) { |
c65d77d8 JB |
4307 | clock->p1 = 1; |
4308 | clock->p2 = 10; | |
4309 | clock->n = 6; | |
4310 | clock->m1 = 12; | |
4311 | clock->m2 = 8; | |
4312 | } | |
f47709a9 DV |
4313 | |
4314 | crtc->config.clock_set = true; | |
c65d77d8 JB |
4315 | } |
4316 | ||
7429e9d4 DV |
4317 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
4318 | { | |
4319 | return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2; | |
4320 | } | |
4321 | ||
4322 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) | |
4323 | { | |
4324 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
4325 | } | |
4326 | ||
f47709a9 | 4327 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4328 | intel_clock_t *reduced_clock) |
4329 | { | |
f47709a9 | 4330 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4331 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4332 | int pipe = crtc->pipe; |
a7516a05 JB |
4333 | u32 fp, fp2 = 0; |
4334 | ||
4335 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4336 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4337 | if (reduced_clock) |
7429e9d4 | 4338 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4339 | } else { |
7429e9d4 | 4340 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4341 | if (reduced_clock) |
7429e9d4 | 4342 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4343 | } |
4344 | ||
4345 | I915_WRITE(FP0(pipe), fp); | |
4346 | ||
f47709a9 DV |
4347 | crtc->lowfreq_avail = false; |
4348 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4349 | reduced_clock && i915_powersave) { |
4350 | I915_WRITE(FP1(pipe), fp2); | |
f47709a9 | 4351 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4352 | } else { |
4353 | I915_WRITE(FP1(pipe), fp); | |
4354 | } | |
4355 | } | |
4356 | ||
89b667f8 JB |
4357 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv) |
4358 | { | |
4359 | u32 reg_val; | |
4360 | ||
4361 | /* | |
4362 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4363 | * and set it to a reasonable value instead. | |
4364 | */ | |
4365 | reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1)); | |
4366 | reg_val &= 0xffffff00; | |
4367 | reg_val |= 0x00000030; | |
4368 | intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val); | |
4369 | ||
4370 | reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION); | |
4371 | reg_val &= 0x8cffffff; | |
4372 | reg_val = 0x8c000000; | |
4373 | intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); | |
4374 | ||
4375 | reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1)); | |
4376 | reg_val &= 0xffffff00; | |
4377 | intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val); | |
4378 | ||
4379 | reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION); | |
4380 | reg_val &= 0x00ffffff; | |
4381 | reg_val |= 0xb0000000; | |
4382 | intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val); | |
4383 | } | |
4384 | ||
b551842d DV |
4385 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4386 | struct intel_link_m_n *m_n) | |
4387 | { | |
4388 | struct drm_device *dev = crtc->base.dev; | |
4389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4390 | int pipe = crtc->pipe; | |
4391 | ||
e3b95f1e DV |
4392 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4393 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4394 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4395 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4396 | } |
4397 | ||
4398 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4399 | struct intel_link_m_n *m_n) | |
4400 | { | |
4401 | struct drm_device *dev = crtc->base.dev; | |
4402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4403 | int pipe = crtc->pipe; | |
4404 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4405 | ||
4406 | if (INTEL_INFO(dev)->gen >= 5) { | |
4407 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4408 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4409 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4410 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4411 | } else { | |
e3b95f1e DV |
4412 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4413 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4414 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4415 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4416 | } |
4417 | } | |
4418 | ||
03afc4a2 DV |
4419 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4420 | { | |
4421 | if (crtc->config.has_pch_encoder) | |
4422 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4423 | else | |
4424 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4425 | } | |
4426 | ||
f47709a9 | 4427 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4428 | { |
f47709a9 | 4429 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4430 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4431 | struct drm_display_mode *adjusted_mode = |
4432 | &crtc->config.adjusted_mode; | |
4433 | struct intel_encoder *encoder; | |
f47709a9 | 4434 | int pipe = crtc->pipe; |
89b667f8 | 4435 | u32 dpll, mdiv; |
a0c4da24 | 4436 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
89b667f8 | 4437 | bool is_hdmi; |
198a037f | 4438 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4439 | |
09153000 DV |
4440 | mutex_lock(&dev_priv->dpio_lock); |
4441 | ||
89b667f8 | 4442 | is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); |
a0c4da24 | 4443 | |
f47709a9 DV |
4444 | bestn = crtc->config.dpll.n; |
4445 | bestm1 = crtc->config.dpll.m1; | |
4446 | bestm2 = crtc->config.dpll.m2; | |
4447 | bestp1 = crtc->config.dpll.p1; | |
4448 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4449 | |
89b667f8 JB |
4450 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4451 | ||
4452 | /* PLL B needs special handling */ | |
4453 | if (pipe) | |
4454 | vlv_pllb_recal_opamp(dev_priv); | |
4455 | ||
4456 | /* Set up Tx target for periodic Rcomp update */ | |
4457 | intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f); | |
4458 | ||
4459 | /* Disable target IRef on PLL */ | |
4460 | reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe)); | |
4461 | reg_val &= 0x00ffffff; | |
4462 | intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val); | |
4463 | ||
4464 | /* Disable fast lock */ | |
4465 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610); | |
4466 | ||
4467 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4468 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4469 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4470 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4471 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4472 | |
4473 | /* | |
4474 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4475 | * but we don't support that). | |
4476 | * Note: don't use the DAC post divider as it seems unstable. | |
4477 | */ | |
4478 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
a0c4da24 JB |
4479 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); |
4480 | ||
89b667f8 JB |
4481 | mdiv |= DPIO_ENABLE_CALIBRATION; |
4482 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
a0c4da24 | 4483 | |
89b667f8 JB |
4484 | /* Set HBR and RBR LPF coefficients */ |
4485 | if (adjusted_mode->clock == 162000 || | |
4486 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) | |
4487 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), | |
4488 | 0x005f0021); | |
4489 | else | |
4490 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), | |
4491 | 0x00d0000f); | |
4492 | ||
4493 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4494 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4495 | /* Use SSC source */ | |
4496 | if (!pipe) | |
4497 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), | |
4498 | 0x0df40000); | |
4499 | else | |
4500 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), | |
4501 | 0x0df70000); | |
4502 | } else { /* HDMI or VGA */ | |
4503 | /* Use bend source */ | |
4504 | if (!pipe) | |
4505 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), | |
4506 | 0x0df70000); | |
4507 | else | |
4508 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), | |
4509 | 0x0df40000); | |
4510 | } | |
a0c4da24 | 4511 | |
89b667f8 JB |
4512 | coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe)); |
4513 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; | |
4514 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4515 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4516 | coreclk |= 0x01000000; | |
4517 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk); | |
a0c4da24 | 4518 | |
89b667f8 | 4519 | intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000); |
a0c4da24 | 4520 | |
89b667f8 JB |
4521 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
4522 | if (encoder->pre_pll_enable) | |
4523 | encoder->pre_pll_enable(encoder); | |
2a8f64ca | 4524 | |
89b667f8 JB |
4525 | /* Enable DPIO clock input */ |
4526 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4527 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
4528 | if (pipe) | |
4529 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
2a8f64ca | 4530 | |
89b667f8 | 4531 | dpll |= DPLL_VCO_ENABLE; |
2a8f64ca | 4532 | I915_WRITE(DPLL(pipe), dpll); |
2a8f64ca VP |
4533 | POSTING_READ(DPLL(pipe)); |
4534 | udelay(150); | |
a0c4da24 | 4535 | |
89b667f8 JB |
4536 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
4537 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4538 | ||
198a037f DV |
4539 | dpll_md = 0; |
4540 | if (crtc->config.pixel_multiplier > 1) { | |
4541 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
4542 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
2a8f64ca | 4543 | } |
198a037f DV |
4544 | I915_WRITE(DPLL_MD(pipe), dpll_md); |
4545 | POSTING_READ(DPLL_MD(pipe)); | |
f47709a9 | 4546 | |
89b667f8 JB |
4547 | if (crtc->config.has_dp_encoder) |
4548 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4549 | |
4550 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4551 | } |
4552 | ||
f47709a9 DV |
4553 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4554 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4555 | int num_connectors) |
4556 | { | |
f47709a9 | 4557 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4558 | struct drm_i915_private *dev_priv = dev->dev_private; |
dafd226c | 4559 | struct intel_encoder *encoder; |
f47709a9 | 4560 | int pipe = crtc->pipe; |
eb1cbe48 DV |
4561 | u32 dpll; |
4562 | bool is_sdvo; | |
f47709a9 | 4563 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4564 | |
f47709a9 | 4565 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4566 | |
f47709a9 DV |
4567 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4568 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
4569 | |
4570 | dpll = DPLL_VGA_MODE_DIS; | |
4571 | ||
f47709a9 | 4572 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
4573 | dpll |= DPLLB_MODE_LVDS; |
4574 | else | |
4575 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 4576 | |
198a037f DV |
4577 | if ((crtc->config.pixel_multiplier > 1) && |
4578 | (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) { | |
4579 | dpll |= (crtc->config.pixel_multiplier - 1) | |
4580 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 4581 | } |
198a037f DV |
4582 | |
4583 | if (is_sdvo) | |
4584 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4585 | ||
f47709a9 | 4586 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
eb1cbe48 DV |
4587 | dpll |= DPLL_DVO_HIGH_SPEED; |
4588 | ||
4589 | /* compute bitmask from p1 value */ | |
4590 | if (IS_PINEVIEW(dev)) | |
4591 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4592 | else { | |
4593 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4594 | if (IS_G4X(dev) && reduced_clock) | |
4595 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4596 | } | |
4597 | switch (clock->p2) { | |
4598 | case 5: | |
4599 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4600 | break; | |
4601 | case 7: | |
4602 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4603 | break; | |
4604 | case 10: | |
4605 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4606 | break; | |
4607 | case 14: | |
4608 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4609 | break; | |
4610 | } | |
4611 | if (INTEL_INFO(dev)->gen >= 4) | |
4612 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4613 | ||
f47709a9 | 4614 | if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) |
eb1cbe48 | 4615 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 4616 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT)) |
eb1cbe48 DV |
4617 | /* XXX: just matching BIOS for now */ |
4618 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4619 | dpll |= 3; | |
f47709a9 | 4620 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4621 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4622 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4623 | else | |
4624 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4625 | ||
4626 | dpll |= DPLL_VCO_ENABLE; | |
4627 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4628 | POSTING_READ(DPLL(pipe)); | |
4629 | udelay(150); | |
4630 | ||
f47709a9 | 4631 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
dafd226c DV |
4632 | if (encoder->pre_pll_enable) |
4633 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 | 4634 | |
f47709a9 DV |
4635 | if (crtc->config.has_dp_encoder) |
4636 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
4637 | |
4638 | I915_WRITE(DPLL(pipe), dpll); | |
4639 | ||
4640 | /* Wait for the clocks to stabilize. */ | |
4641 | POSTING_READ(DPLL(pipe)); | |
4642 | udelay(150); | |
4643 | ||
4644 | if (INTEL_INFO(dev)->gen >= 4) { | |
198a037f DV |
4645 | u32 dpll_md = 0; |
4646 | if (crtc->config.pixel_multiplier > 1) { | |
4647 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
4648 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
eb1cbe48 | 4649 | } |
198a037f | 4650 | I915_WRITE(DPLL_MD(pipe), dpll_md); |
eb1cbe48 DV |
4651 | } else { |
4652 | /* The pixel multiplier can only be updated once the | |
4653 | * DPLL is enabled and the clocks are stable. | |
4654 | * | |
4655 | * So write it again. | |
4656 | */ | |
4657 | I915_WRITE(DPLL(pipe), dpll); | |
4658 | } | |
4659 | } | |
4660 | ||
f47709a9 | 4661 | static void i8xx_update_pll(struct intel_crtc *crtc, |
eb1cbe48 | 4662 | struct drm_display_mode *adjusted_mode, |
f47709a9 | 4663 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4664 | int num_connectors) |
4665 | { | |
f47709a9 | 4666 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4667 | struct drm_i915_private *dev_priv = dev->dev_private; |
dafd226c | 4668 | struct intel_encoder *encoder; |
f47709a9 | 4669 | int pipe = crtc->pipe; |
eb1cbe48 | 4670 | u32 dpll; |
f47709a9 | 4671 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4672 | |
f47709a9 | 4673 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4674 | |
eb1cbe48 DV |
4675 | dpll = DPLL_VGA_MODE_DIS; |
4676 | ||
f47709a9 | 4677 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
4678 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4679 | } else { | |
4680 | if (clock->p1 == 2) | |
4681 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4682 | else | |
4683 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4684 | if (clock->p2 == 4) | |
4685 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4686 | } | |
4687 | ||
f47709a9 | 4688 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4689 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4690 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4691 | else | |
4692 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4693 | ||
4694 | dpll |= DPLL_VCO_ENABLE; | |
4695 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4696 | POSTING_READ(DPLL(pipe)); | |
4697 | udelay(150); | |
4698 | ||
f47709a9 | 4699 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
dafd226c DV |
4700 | if (encoder->pre_pll_enable) |
4701 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 | 4702 | |
5b5896e4 DV |
4703 | I915_WRITE(DPLL(pipe), dpll); |
4704 | ||
4705 | /* Wait for the clocks to stabilize. */ | |
4706 | POSTING_READ(DPLL(pipe)); | |
4707 | udelay(150); | |
4708 | ||
eb1cbe48 DV |
4709 | /* The pixel multiplier can only be updated once the |
4710 | * DPLL is enabled and the clocks are stable. | |
4711 | * | |
4712 | * So write it again. | |
4713 | */ | |
4714 | I915_WRITE(DPLL(pipe), dpll); | |
4715 | } | |
4716 | ||
b0e77b9c PZ |
4717 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, |
4718 | struct drm_display_mode *mode, | |
4719 | struct drm_display_mode *adjusted_mode) | |
4720 | { | |
4721 | struct drm_device *dev = intel_crtc->base.dev; | |
4722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4723 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 4724 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
4d8a62ea DV |
4725 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4726 | ||
4727 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
4728 | * the hw state checker will get angry at the mismatch. */ | |
4729 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
4730 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
4731 | |
4732 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4733 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
4734 | crtc_vtotal -= 1; |
4735 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
4736 | vsyncshift = adjusted_mode->crtc_hsync_start |
4737 | - adjusted_mode->crtc_htotal / 2; | |
4738 | } else { | |
4739 | vsyncshift = 0; | |
4740 | } | |
4741 | ||
4742 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4743 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4744 | |
fe2b8f9d | 4745 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4746 | (adjusted_mode->crtc_hdisplay - 1) | |
4747 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4748 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4749 | (adjusted_mode->crtc_hblank_start - 1) | |
4750 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4751 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4752 | (adjusted_mode->crtc_hsync_start - 1) | |
4753 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4754 | ||
fe2b8f9d | 4755 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 4756 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 4757 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 4758 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 4759 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 4760 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 4761 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4762 | (adjusted_mode->crtc_vsync_start - 1) | |
4763 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4764 | ||
b5e508d4 PZ |
4765 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4766 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4767 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4768 | * bits. */ | |
4769 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4770 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4771 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4772 | ||
b0e77b9c PZ |
4773 | /* pipesrc controls the size that is scaled from, which should |
4774 | * always be the user's requested size. | |
4775 | */ | |
4776 | I915_WRITE(PIPESRC(pipe), | |
4777 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
4778 | } | |
4779 | ||
1bd1bd80 DV |
4780 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4781 | struct intel_crtc_config *pipe_config) | |
4782 | { | |
4783 | struct drm_device *dev = crtc->base.dev; | |
4784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4785 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
4786 | uint32_t tmp; | |
4787 | ||
4788 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
4789 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
4790 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
4791 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
4792 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
4793 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4794 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
4795 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
4796 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4797 | ||
4798 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
4799 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
4800 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
4801 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
4802 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
4803 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4804 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
4805 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
4806 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4807 | ||
4808 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
4809 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
4810 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
4811 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
4812 | } | |
4813 | ||
4814 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
4815 | pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1; | |
4816 | pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1; | |
4817 | } | |
4818 | ||
84b046f3 DV |
4819 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4820 | { | |
4821 | struct drm_device *dev = intel_crtc->base.dev; | |
4822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4823 | uint32_t pipeconf; | |
4824 | ||
4825 | pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); | |
4826 | ||
4827 | if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { | |
4828 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
4829 | * core speed. | |
4830 | * | |
4831 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4832 | * pipe == 0 check? | |
4833 | */ | |
4834 | if (intel_crtc->config.requested_mode.clock > | |
4835 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
4836 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
4837 | else | |
4838 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; | |
4839 | } | |
4840 | ||
ff9ce46e DV |
4841 | /* only g4x and later have fancy bpc/dither controls */ |
4842 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
4843 | pipeconf &= ~(PIPECONF_BPC_MASK | | |
4844 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
4845 | ||
4846 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ | |
4847 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
4848 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 4849 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 4850 | |
ff9ce46e DV |
4851 | switch (intel_crtc->config.pipe_bpp) { |
4852 | case 18: | |
4853 | pipeconf |= PIPECONF_6BPC; | |
4854 | break; | |
4855 | case 24: | |
4856 | pipeconf |= PIPECONF_8BPC; | |
4857 | break; | |
4858 | case 30: | |
4859 | pipeconf |= PIPECONF_10BPC; | |
4860 | break; | |
4861 | default: | |
4862 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
4863 | BUG(); | |
84b046f3 DV |
4864 | } |
4865 | } | |
4866 | ||
4867 | if (HAS_PIPE_CXSR(dev)) { | |
4868 | if (intel_crtc->lowfreq_avail) { | |
4869 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
4870 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
4871 | } else { | |
4872 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
4873 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
4874 | } | |
4875 | } | |
4876 | ||
4877 | pipeconf &= ~PIPECONF_INTERLACE_MASK; | |
4878 | if (!IS_GEN2(dev) && | |
4879 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
4880 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4881 | else | |
4882 | pipeconf |= PIPECONF_PROGRESSIVE; | |
4883 | ||
9c8e09b7 VS |
4884 | if (IS_VALLEYVIEW(dev)) { |
4885 | if (intel_crtc->config.limited_color_range) | |
4886 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
4887 | else | |
4888 | pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT; | |
4889 | } | |
4890 | ||
84b046f3 DV |
4891 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4892 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
4893 | } | |
4894 | ||
f564048e | 4895 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 4896 | int x, int y, |
94352cf9 | 4897 | struct drm_framebuffer *fb) |
79e53945 JB |
4898 | { |
4899 | struct drm_device *dev = crtc->dev; | |
4900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 DV |
4902 | struct drm_display_mode *adjusted_mode = |
4903 | &intel_crtc->config.adjusted_mode; | |
4904 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
79e53945 | 4905 | int pipe = intel_crtc->pipe; |
80824003 | 4906 | int plane = intel_crtc->plane; |
c751ce4f | 4907 | int refclk, num_connectors = 0; |
652c393a | 4908 | intel_clock_t clock, reduced_clock; |
84b046f3 | 4909 | u32 dspcntr; |
eb1cbe48 | 4910 | bool ok, has_reduced_clock = false, is_sdvo = false; |
8b47047b | 4911 | bool is_lvds = false, is_tv = false; |
5eddb70b | 4912 | struct intel_encoder *encoder; |
d4906093 | 4913 | const intel_limit_t *limit; |
5c3b82e2 | 4914 | int ret; |
79e53945 | 4915 | |
6c2b7c12 | 4916 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4917 | switch (encoder->type) { |
79e53945 JB |
4918 | case INTEL_OUTPUT_LVDS: |
4919 | is_lvds = true; | |
4920 | break; | |
4921 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4922 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4923 | is_sdvo = true; |
5eddb70b | 4924 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4925 | is_tv = true; |
79e53945 | 4926 | break; |
79e53945 JB |
4927 | case INTEL_OUTPUT_TVOUT: |
4928 | is_tv = true; | |
4929 | break; | |
79e53945 | 4930 | } |
43565a06 | 4931 | |
c751ce4f | 4932 | num_connectors++; |
79e53945 JB |
4933 | } |
4934 | ||
c65d77d8 | 4935 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4936 | |
d4906093 ML |
4937 | /* |
4938 | * Returns a set of divisors for the desired target clock with the given | |
4939 | * refclk, or FALSE. The returned values represent the clock equation: | |
4940 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4941 | */ | |
1b894b59 | 4942 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4943 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4944 | &clock); | |
79e53945 JB |
4945 | if (!ok) { |
4946 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4947 | return -EINVAL; |
79e53945 JB |
4948 | } |
4949 | ||
cda4b7d3 | 4950 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4951 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4952 | |
ddc9003c | 4953 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4954 | /* |
4955 | * Ensure we match the reduced clock's P to the target clock. | |
4956 | * If the clocks don't match, we can't switch the display clock | |
4957 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4958 | * downclock feature. | |
4959 | */ | |
ddc9003c | 4960 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4961 | dev_priv->lvds_downclock, |
4962 | refclk, | |
cec2f356 | 4963 | &clock, |
5eddb70b | 4964 | &reduced_clock); |
7026d4ac | 4965 | } |
f47709a9 DV |
4966 | /* Compat-code for transition, will disappear. */ |
4967 | if (!intel_crtc->config.clock_set) { | |
4968 | intel_crtc->config.dpll.n = clock.n; | |
4969 | intel_crtc->config.dpll.m1 = clock.m1; | |
4970 | intel_crtc->config.dpll.m2 = clock.m2; | |
4971 | intel_crtc->config.dpll.p1 = clock.p1; | |
4972 | intel_crtc->config.dpll.p2 = clock.p2; | |
4973 | } | |
7026d4ac | 4974 | |
c65d77d8 | 4975 | if (is_sdvo && is_tv) |
f47709a9 | 4976 | i9xx_adjust_sdvo_tv_clock(intel_crtc); |
7026d4ac | 4977 | |
eb1cbe48 | 4978 | if (IS_GEN2(dev)) |
f47709a9 | 4979 | i8xx_update_pll(intel_crtc, adjusted_mode, |
2a8f64ca VP |
4980 | has_reduced_clock ? &reduced_clock : NULL, |
4981 | num_connectors); | |
a0c4da24 | 4982 | else if (IS_VALLEYVIEW(dev)) |
f47709a9 | 4983 | vlv_update_pll(intel_crtc); |
79e53945 | 4984 | else |
f47709a9 | 4985 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 4986 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 4987 | num_connectors); |
79e53945 | 4988 | |
79e53945 JB |
4989 | /* Set up the display plane register */ |
4990 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4991 | ||
da6ecc5d JB |
4992 | if (!IS_VALLEYVIEW(dev)) { |
4993 | if (pipe == 0) | |
4994 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4995 | else | |
4996 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4997 | } | |
79e53945 | 4998 | |
2582a850 | 4999 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe)); |
79e53945 JB |
5000 | drm_mode_debug_printmodeline(mode); |
5001 | ||
b0e77b9c | 5002 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b CW |
5003 | |
5004 | /* pipesrc and dspsize control the size that is scaled from, | |
5005 | * which should always be the user's requested size. | |
79e53945 | 5006 | */ |
929c77fb EA |
5007 | I915_WRITE(DSPSIZE(plane), |
5008 | ((mode->vdisplay - 1) << 16) | | |
5009 | (mode->hdisplay - 1)); | |
5010 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 5011 | |
84b046f3 DV |
5012 | i9xx_set_pipeconf(intel_crtc); |
5013 | ||
f564048e EA |
5014 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5015 | POSTING_READ(DSPCNTR(plane)); | |
5016 | ||
94352cf9 | 5017 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
5018 | |
5019 | intel_update_watermarks(dev); | |
5020 | ||
f564048e EA |
5021 | return ret; |
5022 | } | |
5023 | ||
0e8ffe1b DV |
5024 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5025 | struct intel_crtc_config *pipe_config) | |
5026 | { | |
5027 | struct drm_device *dev = crtc->base.dev; | |
5028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5029 | uint32_t tmp; | |
5030 | ||
5031 | tmp = I915_READ(PIPECONF(crtc->pipe)); | |
5032 | if (!(tmp & PIPECONF_ENABLE)) | |
5033 | return false; | |
5034 | ||
1bd1bd80 DV |
5035 | intel_get_pipe_timings(crtc, pipe_config); |
5036 | ||
0e8ffe1b DV |
5037 | return true; |
5038 | } | |
5039 | ||
dde86e2d | 5040 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5041 | { |
5042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5043 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5044 | struct intel_encoder *encoder; |
74cfd7ac | 5045 | u32 val, final; |
13d83a67 | 5046 | bool has_lvds = false; |
199e5d79 KP |
5047 | bool has_cpu_edp = false; |
5048 | bool has_pch_edp = false; | |
5049 | bool has_panel = false; | |
99eb6a01 KP |
5050 | bool has_ck505 = false; |
5051 | bool can_ssc = false; | |
13d83a67 JB |
5052 | |
5053 | /* We need to take the global config into account */ | |
199e5d79 KP |
5054 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5055 | base.head) { | |
5056 | switch (encoder->type) { | |
5057 | case INTEL_OUTPUT_LVDS: | |
5058 | has_panel = true; | |
5059 | has_lvds = true; | |
5060 | break; | |
5061 | case INTEL_OUTPUT_EDP: | |
5062 | has_panel = true; | |
5063 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5064 | has_pch_edp = true; | |
5065 | else | |
5066 | has_cpu_edp = true; | |
5067 | break; | |
13d83a67 JB |
5068 | } |
5069 | } | |
5070 | ||
99eb6a01 KP |
5071 | if (HAS_PCH_IBX(dev)) { |
5072 | has_ck505 = dev_priv->display_clock_mode; | |
5073 | can_ssc = has_ck505; | |
5074 | } else { | |
5075 | has_ck505 = false; | |
5076 | can_ssc = true; | |
5077 | } | |
5078 | ||
5079 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5080 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5081 | has_ck505); | |
13d83a67 JB |
5082 | |
5083 | /* Ironlake: try to setup display ref clock before DPLL | |
5084 | * enabling. This is only under driver's control after | |
5085 | * PCH B stepping, previous chipset stepping should be | |
5086 | * ignoring this setting. | |
5087 | */ | |
74cfd7ac CW |
5088 | val = I915_READ(PCH_DREF_CONTROL); |
5089 | ||
5090 | /* As we must carefully and slowly disable/enable each source in turn, | |
5091 | * compute the final state we want first and check if we need to | |
5092 | * make any changes at all. | |
5093 | */ | |
5094 | final = val; | |
5095 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5096 | if (has_ck505) | |
5097 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5098 | else | |
5099 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5100 | ||
5101 | final &= ~DREF_SSC_SOURCE_MASK; | |
5102 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5103 | final &= ~DREF_SSC1_ENABLE; | |
5104 | ||
5105 | if (has_panel) { | |
5106 | final |= DREF_SSC_SOURCE_ENABLE; | |
5107 | ||
5108 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5109 | final |= DREF_SSC1_ENABLE; | |
5110 | ||
5111 | if (has_cpu_edp) { | |
5112 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5113 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5114 | else | |
5115 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5116 | } else | |
5117 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5118 | } else { | |
5119 | final |= DREF_SSC_SOURCE_DISABLE; | |
5120 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5121 | } | |
5122 | ||
5123 | if (final == val) | |
5124 | return; | |
5125 | ||
13d83a67 | 5126 | /* Always enable nonspread source */ |
74cfd7ac | 5127 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5128 | |
99eb6a01 | 5129 | if (has_ck505) |
74cfd7ac | 5130 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5131 | else |
74cfd7ac | 5132 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5133 | |
199e5d79 | 5134 | if (has_panel) { |
74cfd7ac CW |
5135 | val &= ~DREF_SSC_SOURCE_MASK; |
5136 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5137 | |
199e5d79 | 5138 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5139 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5140 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5141 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5142 | } else |
74cfd7ac | 5143 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5144 | |
5145 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5146 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5147 | POSTING_READ(PCH_DREF_CONTROL); |
5148 | udelay(200); | |
5149 | ||
74cfd7ac | 5150 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5151 | |
5152 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5153 | if (has_cpu_edp) { |
99eb6a01 | 5154 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5155 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5156 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5157 | } |
13d83a67 | 5158 | else |
74cfd7ac | 5159 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5160 | } else |
74cfd7ac | 5161 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5162 | |
74cfd7ac | 5163 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5164 | POSTING_READ(PCH_DREF_CONTROL); |
5165 | udelay(200); | |
5166 | } else { | |
5167 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5168 | ||
74cfd7ac | 5169 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5170 | |
5171 | /* Turn off CPU output */ | |
74cfd7ac | 5172 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5173 | |
74cfd7ac | 5174 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5175 | POSTING_READ(PCH_DREF_CONTROL); |
5176 | udelay(200); | |
5177 | ||
5178 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5179 | val &= ~DREF_SSC_SOURCE_MASK; |
5180 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5181 | |
5182 | /* Turn off SSC1 */ | |
74cfd7ac | 5183 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5184 | |
74cfd7ac | 5185 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5186 | POSTING_READ(PCH_DREF_CONTROL); |
5187 | udelay(200); | |
5188 | } | |
74cfd7ac CW |
5189 | |
5190 | BUG_ON(val != final); | |
13d83a67 JB |
5191 | } |
5192 | ||
dde86e2d PZ |
5193 | /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ |
5194 | static void lpt_init_pch_refclk(struct drm_device *dev) | |
5195 | { | |
5196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5197 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5198 | struct intel_encoder *encoder; | |
5199 | bool has_vga = false; | |
5200 | bool is_sdv = false; | |
5201 | u32 tmp; | |
5202 | ||
5203 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5204 | switch (encoder->type) { | |
5205 | case INTEL_OUTPUT_ANALOG: | |
5206 | has_vga = true; | |
5207 | break; | |
5208 | } | |
5209 | } | |
5210 | ||
5211 | if (!has_vga) | |
5212 | return; | |
5213 | ||
c00db246 DV |
5214 | mutex_lock(&dev_priv->dpio_lock); |
5215 | ||
dde86e2d PZ |
5216 | /* XXX: Rip out SDV support once Haswell ships for real. */ |
5217 | if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00) | |
5218 | is_sdv = true; | |
5219 | ||
5220 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5221 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5222 | tmp |= SBI_SSCCTL_PATHALT; | |
5223 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5224 | ||
5225 | udelay(24); | |
5226 | ||
5227 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5228 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5229 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5230 | ||
5231 | if (!is_sdv) { | |
5232 | tmp = I915_READ(SOUTH_CHICKEN2); | |
5233 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5234 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
5235 | ||
5236 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & | |
5237 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5238 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
5239 | ||
5240 | tmp = I915_READ(SOUTH_CHICKEN2); | |
5241 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5242 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
5243 | ||
5244 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & | |
5245 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, | |
5246 | 100)) | |
5247 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
5248 | } | |
5249 | ||
5250 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5251 | tmp &= ~(0xFF << 24); | |
5252 | tmp |= (0x12 << 24); | |
5253 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5254 | ||
dde86e2d PZ |
5255 | if (is_sdv) { |
5256 | tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY); | |
5257 | tmp |= 0x7FFF; | |
5258 | intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY); | |
5259 | } | |
5260 | ||
5261 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); | |
5262 | tmp |= (1 << 11); | |
5263 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5264 | ||
5265 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5266 | tmp |= (1 << 11); | |
5267 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5268 | ||
5269 | if (is_sdv) { | |
5270 | tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY); | |
5271 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
5272 | intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY); | |
5273 | ||
5274 | tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY); | |
5275 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
5276 | intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY); | |
5277 | ||
5278 | tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY); | |
5279 | tmp |= (0x3F << 8); | |
5280 | intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY); | |
5281 | ||
5282 | tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY); | |
5283 | tmp |= (0x3F << 8); | |
5284 | intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY); | |
5285 | } | |
5286 | ||
5287 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); | |
5288 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5289 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5290 | ||
5291 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5292 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5293 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5294 | ||
5295 | if (!is_sdv) { | |
5296 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); | |
5297 | tmp &= ~(7 << 13); | |
5298 | tmp |= (5 << 13); | |
5299 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
5300 | ||
5301 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); | |
5302 | tmp &= ~(7 << 13); | |
5303 | tmp |= (5 << 13); | |
5304 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
5305 | } | |
5306 | ||
5307 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5308 | tmp &= ~0xFF; | |
5309 | tmp |= 0x1C; | |
5310 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5311 | ||
5312 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5313 | tmp &= ~0xFF; | |
5314 | tmp |= 0x1C; | |
5315 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5316 | ||
5317 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5318 | tmp &= ~(0xFF << 16); | |
5319 | tmp |= (0x1C << 16); | |
5320 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5321 | ||
5322 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5323 | tmp &= ~(0xFF << 16); | |
5324 | tmp |= (0x1C << 16); | |
5325 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5326 | ||
5327 | if (!is_sdv) { | |
5328 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); | |
5329 | tmp |= (1 << 27); | |
5330 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
5331 | ||
5332 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); | |
5333 | tmp |= (1 << 27); | |
5334 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
5335 | ||
5336 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); | |
5337 | tmp &= ~(0xF << 28); | |
5338 | tmp |= (4 << 28); | |
5339 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
5340 | ||
5341 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); | |
5342 | tmp &= ~(0xF << 28); | |
5343 | tmp |= (4 << 28); | |
5344 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
5345 | } | |
5346 | ||
5347 | /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ | |
5348 | tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); | |
5349 | tmp |= SBI_DBUFF0_ENABLE; | |
5350 | intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); | |
c00db246 DV |
5351 | |
5352 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5353 | } |
5354 | ||
5355 | /* | |
5356 | * Initialize reference clocks when the driver loads | |
5357 | */ | |
5358 | void intel_init_pch_refclk(struct drm_device *dev) | |
5359 | { | |
5360 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5361 | ironlake_init_pch_refclk(dev); | |
5362 | else if (HAS_PCH_LPT(dev)) | |
5363 | lpt_init_pch_refclk(dev); | |
5364 | } | |
5365 | ||
d9d444cb JB |
5366 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5367 | { | |
5368 | struct drm_device *dev = crtc->dev; | |
5369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5370 | struct intel_encoder *encoder; | |
d9d444cb JB |
5371 | struct intel_encoder *edp_encoder = NULL; |
5372 | int num_connectors = 0; | |
5373 | bool is_lvds = false; | |
5374 | ||
6c2b7c12 | 5375 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5376 | switch (encoder->type) { |
5377 | case INTEL_OUTPUT_LVDS: | |
5378 | is_lvds = true; | |
5379 | break; | |
5380 | case INTEL_OUTPUT_EDP: | |
5381 | edp_encoder = encoder; | |
5382 | break; | |
5383 | } | |
5384 | num_connectors++; | |
5385 | } | |
5386 | ||
5387 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5388 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5389 | dev_priv->lvds_ssc_freq); | |
5390 | return dev_priv->lvds_ssc_freq * 1000; | |
5391 | } | |
5392 | ||
5393 | return 120000; | |
5394 | } | |
5395 | ||
6ff93609 | 5396 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5397 | { |
c8203565 | 5398 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5400 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5401 | uint32_t val; |
5402 | ||
5403 | val = I915_READ(PIPECONF(pipe)); | |
5404 | ||
dfd07d72 | 5405 | val &= ~PIPECONF_BPC_MASK; |
965e0c48 | 5406 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5407 | case 18: |
dfd07d72 | 5408 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5409 | break; |
5410 | case 24: | |
dfd07d72 | 5411 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5412 | break; |
5413 | case 30: | |
dfd07d72 | 5414 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5415 | break; |
5416 | case 36: | |
dfd07d72 | 5417 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5418 | break; |
5419 | default: | |
cc769b62 PZ |
5420 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5421 | BUG(); | |
c8203565 PZ |
5422 | } |
5423 | ||
5424 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
d8b32247 | 5425 | if (intel_crtc->config.dither) |
c8203565 PZ |
5426 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5427 | ||
5428 | val &= ~PIPECONF_INTERLACE_MASK; | |
6ff93609 | 5429 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5430 | val |= PIPECONF_INTERLACED_ILK; |
5431 | else | |
5432 | val |= PIPECONF_PROGRESSIVE; | |
5433 | ||
50f3b016 | 5434 | if (intel_crtc->config.limited_color_range) |
3685a8f3 VS |
5435 | val |= PIPECONF_COLOR_RANGE_SELECT; |
5436 | else | |
5437 | val &= ~PIPECONF_COLOR_RANGE_SELECT; | |
5438 | ||
c8203565 PZ |
5439 | I915_WRITE(PIPECONF(pipe), val); |
5440 | POSTING_READ(PIPECONF(pipe)); | |
5441 | } | |
5442 | ||
86d3efce VS |
5443 | /* |
5444 | * Set up the pipe CSC unit. | |
5445 | * | |
5446 | * Currently only full range RGB to limited range RGB conversion | |
5447 | * is supported, but eventually this should handle various | |
5448 | * RGB<->YCbCr scenarios as well. | |
5449 | */ | |
50f3b016 | 5450 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5451 | { |
5452 | struct drm_device *dev = crtc->dev; | |
5453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5455 | int pipe = intel_crtc->pipe; | |
5456 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5457 | ||
5458 | /* | |
5459 | * TODO: Check what kind of values actually come out of the pipe | |
5460 | * with these coeff/postoff values and adjust to get the best | |
5461 | * accuracy. Perhaps we even need to take the bpc value into | |
5462 | * consideration. | |
5463 | */ | |
5464 | ||
50f3b016 | 5465 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5466 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5467 | ||
5468 | /* | |
5469 | * GY/GU and RY/RU should be the other way around according | |
5470 | * to BSpec, but reality doesn't agree. Just set them up in | |
5471 | * a way that results in the correct picture. | |
5472 | */ | |
5473 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5474 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5475 | ||
5476 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5477 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5478 | ||
5479 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5480 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5481 | ||
5482 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5483 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5484 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5485 | ||
5486 | if (INTEL_INFO(dev)->gen > 6) { | |
5487 | uint16_t postoff = 0; | |
5488 | ||
50f3b016 | 5489 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5490 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5491 | ||
5492 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
5493 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
5494 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
5495 | ||
5496 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
5497 | } else { | |
5498 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
5499 | ||
50f3b016 | 5500 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5501 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5502 | ||
5503 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
5504 | } | |
5505 | } | |
5506 | ||
6ff93609 | 5507 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 PZ |
5508 | { |
5509 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 5511 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
5512 | uint32_t val; |
5513 | ||
702e7a56 | 5514 | val = I915_READ(PIPECONF(cpu_transcoder)); |
ee2b0b38 PZ |
5515 | |
5516 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
d8b32247 | 5517 | if (intel_crtc->config.dither) |
ee2b0b38 PZ |
5518 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5519 | ||
5520 | val &= ~PIPECONF_INTERLACE_MASK_HSW; | |
6ff93609 | 5521 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
5522 | val |= PIPECONF_INTERLACED_ILK; |
5523 | else | |
5524 | val |= PIPECONF_PROGRESSIVE; | |
5525 | ||
702e7a56 PZ |
5526 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5527 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
ee2b0b38 PZ |
5528 | } |
5529 | ||
6591c6e4 PZ |
5530 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5531 | struct drm_display_mode *adjusted_mode, | |
5532 | intel_clock_t *clock, | |
5533 | bool *has_reduced_clock, | |
5534 | intel_clock_t *reduced_clock) | |
5535 | { | |
5536 | struct drm_device *dev = crtc->dev; | |
5537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5538 | struct intel_encoder *intel_encoder; | |
5539 | int refclk; | |
d4906093 | 5540 | const intel_limit_t *limit; |
6591c6e4 | 5541 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
79e53945 | 5542 | |
6591c6e4 PZ |
5543 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5544 | switch (intel_encoder->type) { | |
79e53945 JB |
5545 | case INTEL_OUTPUT_LVDS: |
5546 | is_lvds = true; | |
5547 | break; | |
5548 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5549 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5550 | is_sdvo = true; |
6591c6e4 | 5551 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5552 | is_tv = true; |
79e53945 | 5553 | break; |
79e53945 JB |
5554 | case INTEL_OUTPUT_TVOUT: |
5555 | is_tv = true; | |
5556 | break; | |
79e53945 JB |
5557 | } |
5558 | } | |
5559 | ||
d9d444cb | 5560 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5561 | |
d4906093 ML |
5562 | /* |
5563 | * Returns a set of divisors for the desired target clock with the given | |
5564 | * refclk, or FALSE. The returned values represent the clock equation: | |
5565 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5566 | */ | |
1b894b59 | 5567 | limit = intel_limit(crtc, refclk); |
6591c6e4 PZ |
5568 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5569 | clock); | |
5570 | if (!ret) | |
5571 | return false; | |
cda4b7d3 | 5572 | |
ddc9003c | 5573 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5574 | /* |
5575 | * Ensure we match the reduced clock's P to the target clock. | |
5576 | * If the clocks don't match, we can't switch the display clock | |
5577 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5578 | * downclock feature. | |
5579 | */ | |
6591c6e4 PZ |
5580 | *has_reduced_clock = limit->find_pll(limit, crtc, |
5581 | dev_priv->lvds_downclock, | |
5582 | refclk, | |
5583 | clock, | |
5584 | reduced_clock); | |
652c393a | 5585 | } |
61e9653f DV |
5586 | |
5587 | if (is_sdvo && is_tv) | |
f47709a9 | 5588 | i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc)); |
6591c6e4 PZ |
5589 | |
5590 | return true; | |
5591 | } | |
5592 | ||
01a415fd DV |
5593 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5594 | { | |
5595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5596 | uint32_t temp; | |
5597 | ||
5598 | temp = I915_READ(SOUTH_CHICKEN1); | |
5599 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5600 | return; | |
5601 | ||
5602 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5603 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5604 | ||
5605 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5606 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5607 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5608 | POSTING_READ(SOUTH_CHICKEN1); | |
5609 | } | |
5610 | ||
ebfd86fd DV |
5611 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
5612 | { | |
5613 | struct drm_device *dev = intel_crtc->base.dev; | |
5614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5615 | ||
5616 | switch (intel_crtc->pipe) { | |
5617 | case PIPE_A: | |
5618 | break; | |
5619 | case PIPE_B: | |
5620 | if (intel_crtc->config.fdi_lanes > 2) | |
5621 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
5622 | else | |
5623 | cpt_enable_fdi_bc_bifurcation(dev); | |
5624 | ||
5625 | break; | |
5626 | case PIPE_C: | |
01a415fd DV |
5627 | cpt_enable_fdi_bc_bifurcation(dev); |
5628 | ||
ebfd86fd | 5629 | break; |
01a415fd DV |
5630 | default: |
5631 | BUG(); | |
5632 | } | |
5633 | } | |
5634 | ||
d4b1931c PZ |
5635 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5636 | { | |
5637 | /* | |
5638 | * Account for spread spectrum to avoid | |
5639 | * oversubscribing the link. Max center spread | |
5640 | * is 2.5%; use 5% for safety's sake. | |
5641 | */ | |
5642 | u32 bps = target_clock * bpp * 21 / 20; | |
5643 | return bps / (link_bw * 8) + 1; | |
5644 | } | |
5645 | ||
7429e9d4 DV |
5646 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
5647 | { | |
5648 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; | |
5649 | } | |
5650 | ||
de13a2e3 | 5651 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 5652 | u32 *fp, |
9a7c7890 | 5653 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 5654 | { |
de13a2e3 | 5655 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5656 | struct drm_device *dev = crtc->dev; |
5657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5658 | struct intel_encoder *intel_encoder; |
5659 | uint32_t dpll; | |
6cc5f341 | 5660 | int factor, num_connectors = 0; |
de13a2e3 | 5661 | bool is_lvds = false, is_sdvo = false, is_tv = false; |
79e53945 | 5662 | |
de13a2e3 PZ |
5663 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5664 | switch (intel_encoder->type) { | |
79e53945 JB |
5665 | case INTEL_OUTPUT_LVDS: |
5666 | is_lvds = true; | |
5667 | break; | |
5668 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5669 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5670 | is_sdvo = true; |
de13a2e3 | 5671 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5672 | is_tv = true; |
79e53945 | 5673 | break; |
79e53945 JB |
5674 | case INTEL_OUTPUT_TVOUT: |
5675 | is_tv = true; | |
5676 | break; | |
79e53945 | 5677 | } |
43565a06 | 5678 | |
c751ce4f | 5679 | num_connectors++; |
79e53945 | 5680 | } |
79e53945 | 5681 | |
c1858123 | 5682 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5683 | factor = 21; |
5684 | if (is_lvds) { | |
5685 | if ((intel_panel_use_ssc(dev_priv) && | |
5686 | dev_priv->lvds_ssc_freq == 100) || | |
f0b44056 | 5687 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 EA |
5688 | factor = 25; |
5689 | } else if (is_sdvo && is_tv) | |
5690 | factor = 20; | |
c1858123 | 5691 | |
7429e9d4 | 5692 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 5693 | *fp |= FP_CB_TUNE; |
2c07245f | 5694 | |
9a7c7890 DV |
5695 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5696 | *fp2 |= FP_CB_TUNE; | |
5697 | ||
5eddb70b | 5698 | dpll = 0; |
2c07245f | 5699 | |
a07d6787 EA |
5700 | if (is_lvds) |
5701 | dpll |= DPLLB_MODE_LVDS; | |
5702 | else | |
5703 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f DV |
5704 | |
5705 | if (intel_crtc->config.pixel_multiplier > 1) { | |
5706 | dpll |= (intel_crtc->config.pixel_multiplier - 1) | |
5707 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
a07d6787 | 5708 | } |
198a037f DV |
5709 | |
5710 | if (is_sdvo) | |
5711 | dpll |= DPLL_DVO_HIGH_SPEED; | |
9566e9af | 5712 | if (intel_crtc->config.has_dp_encoder) |
a07d6787 | 5713 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5714 | |
a07d6787 | 5715 | /* compute bitmask from p1 value */ |
7429e9d4 | 5716 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5717 | /* also FPA1 */ |
7429e9d4 | 5718 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5719 | |
7429e9d4 | 5720 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
5721 | case 5: |
5722 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5723 | break; | |
5724 | case 7: | |
5725 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5726 | break; | |
5727 | case 10: | |
5728 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5729 | break; | |
5730 | case 14: | |
5731 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5732 | break; | |
79e53945 JB |
5733 | } |
5734 | ||
43565a06 KH |
5735 | if (is_sdvo && is_tv) |
5736 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5737 | else if (is_tv) | |
79e53945 | 5738 | /* XXX: just matching BIOS for now */ |
43565a06 | 5739 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5740 | dpll |= 3; |
a7615030 | 5741 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5742 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5743 | else |
5744 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5745 | ||
de13a2e3 PZ |
5746 | return dpll; |
5747 | } | |
5748 | ||
5749 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
5750 | int x, int y, |
5751 | struct drm_framebuffer *fb) | |
5752 | { | |
5753 | struct drm_device *dev = crtc->dev; | |
5754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 DV |
5756 | struct drm_display_mode *adjusted_mode = |
5757 | &intel_crtc->config.adjusted_mode; | |
5758 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
de13a2e3 PZ |
5759 | int pipe = intel_crtc->pipe; |
5760 | int plane = intel_crtc->plane; | |
5761 | int num_connectors = 0; | |
5762 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 5763 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 5764 | bool ok, has_reduced_clock = false; |
8b47047b | 5765 | bool is_lvds = false; |
de13a2e3 | 5766 | struct intel_encoder *encoder; |
de13a2e3 | 5767 | int ret; |
de13a2e3 PZ |
5768 | |
5769 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5770 | switch (encoder->type) { | |
5771 | case INTEL_OUTPUT_LVDS: | |
5772 | is_lvds = true; | |
5773 | break; | |
de13a2e3 PZ |
5774 | } |
5775 | ||
5776 | num_connectors++; | |
a07d6787 | 5777 | } |
79e53945 | 5778 | |
5dc5298b PZ |
5779 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5780 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5781 | |
3b117c8f | 5782 | intel_crtc->config.cpu_transcoder = pipe; |
6cf86a5e | 5783 | |
de13a2e3 PZ |
5784 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
5785 | &has_reduced_clock, &reduced_clock); | |
5786 | if (!ok) { | |
5787 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5788 | return -EINVAL; | |
79e53945 | 5789 | } |
f47709a9 DV |
5790 | /* Compat-code for transition, will disappear. */ |
5791 | if (!intel_crtc->config.clock_set) { | |
5792 | intel_crtc->config.dpll.n = clock.n; | |
5793 | intel_crtc->config.dpll.m1 = clock.m1; | |
5794 | intel_crtc->config.dpll.m2 = clock.m2; | |
5795 | intel_crtc->config.dpll.p1 = clock.p1; | |
5796 | intel_crtc->config.dpll.p2 = clock.p2; | |
5797 | } | |
79e53945 | 5798 | |
de13a2e3 PZ |
5799 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5800 | intel_crtc_update_cursor(crtc, true); | |
5801 | ||
84f44ce7 | 5802 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe)); |
79e53945 JB |
5803 | drm_mode_debug_printmodeline(mode); |
5804 | ||
5dc5298b | 5805 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 5806 | if (intel_crtc->config.has_pch_encoder) { |
ee7b9f93 | 5807 | struct intel_pch_pll *pll; |
4b645f14 | 5808 | |
7429e9d4 | 5809 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 5810 | if (has_reduced_clock) |
7429e9d4 | 5811 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 5812 | |
7429e9d4 | 5813 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
5814 | &fp, &reduced_clock, |
5815 | has_reduced_clock ? &fp2 : NULL); | |
5816 | ||
ee7b9f93 JB |
5817 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
5818 | if (pll == NULL) { | |
84f44ce7 VS |
5819 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5820 | pipe_name(pipe)); | |
4b645f14 JB |
5821 | return -EINVAL; |
5822 | } | |
ee7b9f93 JB |
5823 | } else |
5824 | intel_put_pch_pll(intel_crtc); | |
79e53945 | 5825 | |
03afc4a2 DV |
5826 | if (intel_crtc->config.has_dp_encoder) |
5827 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 5828 | |
dafd226c DV |
5829 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5830 | if (encoder->pre_pll_enable) | |
5831 | encoder->pre_pll_enable(encoder); | |
79e53945 | 5832 | |
ee7b9f93 JB |
5833 | if (intel_crtc->pch_pll) { |
5834 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 5835 | |
32f9d658 | 5836 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 5837 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
5838 | udelay(150); |
5839 | ||
8febb297 EA |
5840 | /* The pixel multiplier can only be updated once the |
5841 | * DPLL is enabled and the clocks are stable. | |
5842 | * | |
5843 | * So write it again. | |
5844 | */ | |
ee7b9f93 | 5845 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 5846 | } |
79e53945 | 5847 | |
5eddb70b | 5848 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 5849 | if (intel_crtc->pch_pll) { |
4b645f14 | 5850 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 5851 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 5852 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 5853 | } else { |
ee7b9f93 | 5854 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
5855 | } |
5856 | } | |
5857 | ||
b0e77b9c | 5858 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b | 5859 | |
ca3a0ff8 | 5860 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
5861 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5862 | &intel_crtc->config.fdi_m_n); | |
5863 | } | |
2c07245f | 5864 | |
ebfd86fd DV |
5865 | if (IS_IVYBRIDGE(dev)) |
5866 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
2c07245f | 5867 | |
6ff93609 | 5868 | ironlake_set_pipeconf(crtc); |
79e53945 | 5869 | |
a1f9e77e PZ |
5870 | /* Set up the display plane register */ |
5871 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5872 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5873 | |
94352cf9 | 5874 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5875 | |
5876 | intel_update_watermarks(dev); | |
5877 | ||
1f8eeabf ED |
5878 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5879 | ||
1857e1da | 5880 | return ret; |
79e53945 JB |
5881 | } |
5882 | ||
72419203 DV |
5883 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5884 | struct intel_crtc_config *pipe_config) | |
5885 | { | |
5886 | struct drm_device *dev = crtc->base.dev; | |
5887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5888 | enum transcoder transcoder = pipe_config->cpu_transcoder; | |
5889 | ||
5890 | pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
5891 | pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
5892 | pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
5893 | & ~TU_SIZE_MASK; | |
5894 | pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
5895 | pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
5896 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
5897 | } | |
5898 | ||
0e8ffe1b DV |
5899 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5900 | struct intel_crtc_config *pipe_config) | |
5901 | { | |
5902 | struct drm_device *dev = crtc->base.dev; | |
5903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5904 | uint32_t tmp; | |
5905 | ||
5906 | tmp = I915_READ(PIPECONF(crtc->pipe)); | |
5907 | if (!(tmp & PIPECONF_ENABLE)) | |
5908 | return false; | |
5909 | ||
ab9412ba | 5910 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
88adfff1 DV |
5911 | pipe_config->has_pch_encoder = true; |
5912 | ||
627eb5a3 DV |
5913 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
5914 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
5915 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
5916 | |
5917 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
5918 | } |
5919 | ||
1bd1bd80 DV |
5920 | intel_get_pipe_timings(crtc, pipe_config); |
5921 | ||
0e8ffe1b DV |
5922 | return true; |
5923 | } | |
5924 | ||
d6dd9eb1 DV |
5925 | static void haswell_modeset_global_resources(struct drm_device *dev) |
5926 | { | |
d6dd9eb1 DV |
5927 | bool enable = false; |
5928 | struct intel_crtc *crtc; | |
5929 | struct intel_encoder *encoder; | |
5930 | ||
5931 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
5932 | if (crtc->pipe != PIPE_A && crtc->base.enabled) | |
5933 | enable = true; | |
5934 | /* XXX: Should check for edp transcoder here, but thanks to init | |
5935 | * sequence that's not yet available. Just in case desktop eDP | |
5936 | * on PORT D is possible on haswell, too. */ | |
b074cec8 | 5937 | /* Even the eDP panel fitter is outside the always-on well. */ |
2b87f3b1 | 5938 | if (crtc->config.pch_pfit.size && crtc->base.enabled) |
b074cec8 | 5939 | enable = true; |
d6dd9eb1 DV |
5940 | } |
5941 | ||
5942 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
5943 | base.head) { | |
5944 | if (encoder->type != INTEL_OUTPUT_EDP && | |
5945 | encoder->connectors_active) | |
5946 | enable = true; | |
5947 | } | |
5948 | ||
d6dd9eb1 DV |
5949 | intel_set_power_well(dev, enable); |
5950 | } | |
5951 | ||
09b4ddf9 | 5952 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
5953 | int x, int y, |
5954 | struct drm_framebuffer *fb) | |
5955 | { | |
5956 | struct drm_device *dev = crtc->dev; | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b8cecdf5 DV |
5959 | struct drm_display_mode *adjusted_mode = |
5960 | &intel_crtc->config.adjusted_mode; | |
5961 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
09b4ddf9 PZ |
5962 | int pipe = intel_crtc->pipe; |
5963 | int plane = intel_crtc->plane; | |
5964 | int num_connectors = 0; | |
8b47047b | 5965 | bool is_cpu_edp = false; |
09b4ddf9 | 5966 | struct intel_encoder *encoder; |
09b4ddf9 | 5967 | int ret; |
09b4ddf9 PZ |
5968 | |
5969 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5970 | switch (encoder->type) { | |
09b4ddf9 | 5971 | case INTEL_OUTPUT_EDP: |
d8e8b582 | 5972 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
09b4ddf9 PZ |
5973 | is_cpu_edp = true; |
5974 | break; | |
5975 | } | |
5976 | ||
5977 | num_connectors++; | |
5978 | } | |
5979 | ||
bba2181c | 5980 | if (is_cpu_edp) |
3b117c8f | 5981 | intel_crtc->config.cpu_transcoder = TRANSCODER_EDP; |
bba2181c | 5982 | else |
3b117c8f | 5983 | intel_crtc->config.cpu_transcoder = pipe; |
bba2181c | 5984 | |
5dc5298b PZ |
5985 | /* We are not sure yet this won't happen. */ |
5986 | WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", | |
5987 | INTEL_PCH_TYPE(dev)); | |
5988 | ||
5989 | WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", | |
5990 | num_connectors, pipe_name(pipe)); | |
5991 | ||
3b117c8f | 5992 | WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) & |
1ce42920 PZ |
5993 | (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); |
5994 | ||
5995 | WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); | |
5996 | ||
6441ab5f PZ |
5997 | if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) |
5998 | return -EINVAL; | |
5999 | ||
09b4ddf9 PZ |
6000 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6001 | intel_crtc_update_cursor(crtc, true); | |
6002 | ||
84f44ce7 | 6003 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe)); |
09b4ddf9 PZ |
6004 | drm_mode_debug_printmodeline(mode); |
6005 | ||
03afc4a2 DV |
6006 | if (intel_crtc->config.has_dp_encoder) |
6007 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6008 | |
6009 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 PZ |
6010 | |
6011 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); | |
6012 | ||
ca3a0ff8 | 6013 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6014 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6015 | &intel_crtc->config.fdi_m_n); | |
6016 | } | |
09b4ddf9 | 6017 | |
6ff93609 | 6018 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6019 | |
50f3b016 | 6020 | intel_set_pipe_csc(crtc); |
86d3efce | 6021 | |
09b4ddf9 | 6022 | /* Set up the display plane register */ |
86d3efce | 6023 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6024 | POSTING_READ(DSPCNTR(plane)); |
6025 | ||
6026 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6027 | ||
6028 | intel_update_watermarks(dev); | |
6029 | ||
6030 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); | |
6031 | ||
1f803ee5 | 6032 | return ret; |
79e53945 JB |
6033 | } |
6034 | ||
0e8ffe1b DV |
6035 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6036 | struct intel_crtc_config *pipe_config) | |
6037 | { | |
6038 | struct drm_device *dev = crtc->base.dev; | |
6039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bfce950 | 6040 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
0e8ffe1b DV |
6041 | uint32_t tmp; |
6042 | ||
b97186f0 PZ |
6043 | if (!intel_display_power_enabled(dev, |
6044 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) | |
2bfce950 PZ |
6045 | return false; |
6046 | ||
6047 | tmp = I915_READ(PIPECONF(cpu_transcoder)); | |
0e8ffe1b DV |
6048 | if (!(tmp & PIPECONF_ENABLE)) |
6049 | return false; | |
6050 | ||
88adfff1 | 6051 | /* |
f196e6be | 6052 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6053 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6054 | * the PCH transcoder is on. | |
6055 | */ | |
f196e6be | 6056 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
88adfff1 | 6057 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6058 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6059 | pipe_config->has_pch_encoder = true; |
6060 | ||
627eb5a3 DV |
6061 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6062 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6063 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6064 | |
6065 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6066 | } |
6067 | ||
1bd1bd80 DV |
6068 | intel_get_pipe_timings(crtc, pipe_config); |
6069 | ||
0e8ffe1b DV |
6070 | return true; |
6071 | } | |
6072 | ||
f564048e | 6073 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6074 | int x, int y, |
94352cf9 | 6075 | struct drm_framebuffer *fb) |
f564048e EA |
6076 | { |
6077 | struct drm_device *dev = crtc->dev; | |
6078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 DV |
6079 | struct drm_encoder_helper_funcs *encoder_funcs; |
6080 | struct intel_encoder *encoder; | |
0b701d27 | 6081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 DV |
6082 | struct drm_display_mode *adjusted_mode = |
6083 | &intel_crtc->config.adjusted_mode; | |
6084 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
0b701d27 | 6085 | int pipe = intel_crtc->pipe; |
f564048e EA |
6086 | int ret; |
6087 | ||
0b701d27 | 6088 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6089 | |
b8cecdf5 DV |
6090 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6091 | ||
79e53945 | 6092 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6093 | |
9256aa19 DV |
6094 | if (ret != 0) |
6095 | return ret; | |
6096 | ||
6097 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6098 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
6099 | encoder->base.base.id, | |
6100 | drm_get_encoder_name(&encoder->base), | |
6101 | mode->base.id, mode->name); | |
6cc5f341 DV |
6102 | if (encoder->mode_set) { |
6103 | encoder->mode_set(encoder); | |
6104 | } else { | |
6105 | encoder_funcs = encoder->base.helper_private; | |
6106 | encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); | |
6107 | } | |
9256aa19 DV |
6108 | } |
6109 | ||
6110 | return 0; | |
79e53945 JB |
6111 | } |
6112 | ||
3a9627f4 WF |
6113 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6114 | int reg_eldv, uint32_t bits_eldv, | |
6115 | int reg_elda, uint32_t bits_elda, | |
6116 | int reg_edid) | |
6117 | { | |
6118 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6119 | uint8_t *eld = connector->eld; | |
6120 | uint32_t i; | |
6121 | ||
6122 | i = I915_READ(reg_eldv); | |
6123 | i &= bits_eldv; | |
6124 | ||
6125 | if (!eld[0]) | |
6126 | return !i; | |
6127 | ||
6128 | if (!i) | |
6129 | return false; | |
6130 | ||
6131 | i = I915_READ(reg_elda); | |
6132 | i &= ~bits_elda; | |
6133 | I915_WRITE(reg_elda, i); | |
6134 | ||
6135 | for (i = 0; i < eld[2]; i++) | |
6136 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6137 | return false; | |
6138 | ||
6139 | return true; | |
6140 | } | |
6141 | ||
e0dac65e WF |
6142 | static void g4x_write_eld(struct drm_connector *connector, |
6143 | struct drm_crtc *crtc) | |
6144 | { | |
6145 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6146 | uint8_t *eld = connector->eld; | |
6147 | uint32_t eldv; | |
6148 | uint32_t len; | |
6149 | uint32_t i; | |
6150 | ||
6151 | i = I915_READ(G4X_AUD_VID_DID); | |
6152 | ||
6153 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6154 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6155 | else | |
6156 | eldv = G4X_ELDV_DEVCTG; | |
6157 | ||
3a9627f4 WF |
6158 | if (intel_eld_uptodate(connector, |
6159 | G4X_AUD_CNTL_ST, eldv, | |
6160 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6161 | G4X_HDMIW_HDMIEDID)) | |
6162 | return; | |
6163 | ||
e0dac65e WF |
6164 | i = I915_READ(G4X_AUD_CNTL_ST); |
6165 | i &= ~(eldv | G4X_ELD_ADDR); | |
6166 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6167 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6168 | ||
6169 | if (!eld[0]) | |
6170 | return; | |
6171 | ||
6172 | len = min_t(uint8_t, eld[2], len); | |
6173 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6174 | for (i = 0; i < len; i++) | |
6175 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6176 | ||
6177 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6178 | i |= eldv; | |
6179 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6180 | } | |
6181 | ||
83358c85 WX |
6182 | static void haswell_write_eld(struct drm_connector *connector, |
6183 | struct drm_crtc *crtc) | |
6184 | { | |
6185 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6186 | uint8_t *eld = connector->eld; | |
6187 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 6188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
6189 | uint32_t eldv; |
6190 | uint32_t i; | |
6191 | int len; | |
6192 | int pipe = to_intel_crtc(crtc)->pipe; | |
6193 | int tmp; | |
6194 | ||
6195 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
6196 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
6197 | int aud_config = HSW_AUD_CFG(pipe); | |
6198 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
6199 | ||
6200 | ||
6201 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
6202 | ||
6203 | /* Audio output enable */ | |
6204 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
6205 | tmp = I915_READ(aud_cntrl_st2); | |
6206 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
6207 | I915_WRITE(aud_cntrl_st2, tmp); | |
6208 | ||
6209 | /* Wait for 1 vertical blank */ | |
6210 | intel_wait_for_vblank(dev, pipe); | |
6211 | ||
6212 | /* Set ELD valid state */ | |
6213 | tmp = I915_READ(aud_cntrl_st2); | |
6214 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); | |
6215 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); | |
6216 | I915_WRITE(aud_cntrl_st2, tmp); | |
6217 | tmp = I915_READ(aud_cntrl_st2); | |
6218 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); | |
6219 | ||
6220 | /* Enable HDMI mode */ | |
6221 | tmp = I915_READ(aud_config); | |
6222 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); | |
6223 | /* clear N_programing_enable and N_value_index */ | |
6224 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
6225 | I915_WRITE(aud_config, tmp); | |
6226 | ||
6227 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
6228 | ||
6229 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 6230 | intel_crtc->eld_vld = true; |
83358c85 WX |
6231 | |
6232 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
6233 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6234 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
6235 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
6236 | } else | |
6237 | I915_WRITE(aud_config, 0); | |
6238 | ||
6239 | if (intel_eld_uptodate(connector, | |
6240 | aud_cntrl_st2, eldv, | |
6241 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6242 | hdmiw_hdmiedid)) | |
6243 | return; | |
6244 | ||
6245 | i = I915_READ(aud_cntrl_st2); | |
6246 | i &= ~eldv; | |
6247 | I915_WRITE(aud_cntrl_st2, i); | |
6248 | ||
6249 | if (!eld[0]) | |
6250 | return; | |
6251 | ||
6252 | i = I915_READ(aud_cntl_st); | |
6253 | i &= ~IBX_ELD_ADDRESS; | |
6254 | I915_WRITE(aud_cntl_st, i); | |
6255 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
6256 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
6257 | ||
6258 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6259 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6260 | for (i = 0; i < len; i++) | |
6261 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6262 | ||
6263 | i = I915_READ(aud_cntrl_st2); | |
6264 | i |= eldv; | |
6265 | I915_WRITE(aud_cntrl_st2, i); | |
6266 | ||
6267 | } | |
6268 | ||
e0dac65e WF |
6269 | static void ironlake_write_eld(struct drm_connector *connector, |
6270 | struct drm_crtc *crtc) | |
6271 | { | |
6272 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6273 | uint8_t *eld = connector->eld; | |
6274 | uint32_t eldv; | |
6275 | uint32_t i; | |
6276 | int len; | |
6277 | int hdmiw_hdmiedid; | |
b6daa025 | 6278 | int aud_config; |
e0dac65e WF |
6279 | int aud_cntl_st; |
6280 | int aud_cntrl_st2; | |
9b138a83 | 6281 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 6282 | |
b3f33cbf | 6283 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
6284 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6285 | aud_config = IBX_AUD_CFG(pipe); | |
6286 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6287 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 6288 | } else { |
9b138a83 WX |
6289 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6290 | aud_config = CPT_AUD_CFG(pipe); | |
6291 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6292 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
6293 | } |
6294 | ||
9b138a83 | 6295 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
6296 | |
6297 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 6298 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
6299 | if (!i) { |
6300 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6301 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6302 | eldv = IBX_ELD_VALIDB; |
6303 | eldv |= IBX_ELD_VALIDB << 4; | |
6304 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 6305 | } else { |
2582a850 | 6306 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 6307 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6308 | } |
6309 | ||
3a9627f4 WF |
6310 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6311 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6312 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6313 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6314 | } else | |
6315 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6316 | |
3a9627f4 WF |
6317 | if (intel_eld_uptodate(connector, |
6318 | aud_cntrl_st2, eldv, | |
6319 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6320 | hdmiw_hdmiedid)) | |
6321 | return; | |
6322 | ||
e0dac65e WF |
6323 | i = I915_READ(aud_cntrl_st2); |
6324 | i &= ~eldv; | |
6325 | I915_WRITE(aud_cntrl_st2, i); | |
6326 | ||
6327 | if (!eld[0]) | |
6328 | return; | |
6329 | ||
e0dac65e | 6330 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6331 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6332 | I915_WRITE(aud_cntl_st, i); |
6333 | ||
6334 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6335 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6336 | for (i = 0; i < len; i++) | |
6337 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6338 | ||
6339 | i = I915_READ(aud_cntrl_st2); | |
6340 | i |= eldv; | |
6341 | I915_WRITE(aud_cntrl_st2, i); | |
6342 | } | |
6343 | ||
6344 | void intel_write_eld(struct drm_encoder *encoder, | |
6345 | struct drm_display_mode *mode) | |
6346 | { | |
6347 | struct drm_crtc *crtc = encoder->crtc; | |
6348 | struct drm_connector *connector; | |
6349 | struct drm_device *dev = encoder->dev; | |
6350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6351 | ||
6352 | connector = drm_select_eld(encoder, mode); | |
6353 | if (!connector) | |
6354 | return; | |
6355 | ||
6356 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6357 | connector->base.id, | |
6358 | drm_get_connector_name(connector), | |
6359 | connector->encoder->base.id, | |
6360 | drm_get_encoder_name(connector->encoder)); | |
6361 | ||
6362 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6363 | ||
6364 | if (dev_priv->display.write_eld) | |
6365 | dev_priv->display.write_eld(connector, crtc); | |
6366 | } | |
6367 | ||
79e53945 JB |
6368 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6369 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6370 | { | |
6371 | struct drm_device *dev = crtc->dev; | |
6372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6374 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6375 | int i; |
6376 | ||
6377 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6378 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6379 | return; |
6380 | ||
f2b115e6 | 6381 | /* use legacy palette for Ironlake */ |
bad720ff | 6382 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6383 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6384 | |
79e53945 JB |
6385 | for (i = 0; i < 256; i++) { |
6386 | I915_WRITE(palreg + 4 * i, | |
6387 | (intel_crtc->lut_r[i] << 16) | | |
6388 | (intel_crtc->lut_g[i] << 8) | | |
6389 | intel_crtc->lut_b[i]); | |
6390 | } | |
6391 | } | |
6392 | ||
560b85bb CW |
6393 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6394 | { | |
6395 | struct drm_device *dev = crtc->dev; | |
6396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6398 | bool visible = base != 0; | |
6399 | u32 cntl; | |
6400 | ||
6401 | if (intel_crtc->cursor_visible == visible) | |
6402 | return; | |
6403 | ||
9db4a9c7 | 6404 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6405 | if (visible) { |
6406 | /* On these chipsets we can only modify the base whilst | |
6407 | * the cursor is disabled. | |
6408 | */ | |
9db4a9c7 | 6409 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6410 | |
6411 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6412 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6413 | cntl |= CURSOR_ENABLE | | |
6414 | CURSOR_GAMMA_ENABLE | | |
6415 | CURSOR_FORMAT_ARGB; | |
6416 | } else | |
6417 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6418 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6419 | |
6420 | intel_crtc->cursor_visible = visible; | |
6421 | } | |
6422 | ||
6423 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6424 | { | |
6425 | struct drm_device *dev = crtc->dev; | |
6426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6427 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6428 | int pipe = intel_crtc->pipe; | |
6429 | bool visible = base != 0; | |
6430 | ||
6431 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6432 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6433 | if (base) { |
6434 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6435 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6436 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6437 | } else { | |
6438 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6439 | cntl |= CURSOR_MODE_DISABLE; | |
6440 | } | |
9db4a9c7 | 6441 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6442 | |
6443 | intel_crtc->cursor_visible = visible; | |
6444 | } | |
6445 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6446 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6447 | } |
6448 | ||
65a21cd6 JB |
6449 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6450 | { | |
6451 | struct drm_device *dev = crtc->dev; | |
6452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6454 | int pipe = intel_crtc->pipe; | |
6455 | bool visible = base != 0; | |
6456 | ||
6457 | if (intel_crtc->cursor_visible != visible) { | |
6458 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6459 | if (base) { | |
6460 | cntl &= ~CURSOR_MODE; | |
6461 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6462 | } else { | |
6463 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6464 | cntl |= CURSOR_MODE_DISABLE; | |
6465 | } | |
86d3efce VS |
6466 | if (IS_HASWELL(dev)) |
6467 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 JB |
6468 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6469 | ||
6470 | intel_crtc->cursor_visible = visible; | |
6471 | } | |
6472 | /* and commit changes on next vblank */ | |
6473 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6474 | } | |
6475 | ||
cda4b7d3 | 6476 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6477 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6478 | bool on) | |
cda4b7d3 CW |
6479 | { |
6480 | struct drm_device *dev = crtc->dev; | |
6481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6483 | int pipe = intel_crtc->pipe; | |
6484 | int x = intel_crtc->cursor_x; | |
6485 | int y = intel_crtc->cursor_y; | |
560b85bb | 6486 | u32 base, pos; |
cda4b7d3 CW |
6487 | bool visible; |
6488 | ||
6489 | pos = 0; | |
6490 | ||
6b383a7f | 6491 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6492 | base = intel_crtc->cursor_addr; |
6493 | if (x > (int) crtc->fb->width) | |
6494 | base = 0; | |
6495 | ||
6496 | if (y > (int) crtc->fb->height) | |
6497 | base = 0; | |
6498 | } else | |
6499 | base = 0; | |
6500 | ||
6501 | if (x < 0) { | |
6502 | if (x + intel_crtc->cursor_width < 0) | |
6503 | base = 0; | |
6504 | ||
6505 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6506 | x = -x; | |
6507 | } | |
6508 | pos |= x << CURSOR_X_SHIFT; | |
6509 | ||
6510 | if (y < 0) { | |
6511 | if (y + intel_crtc->cursor_height < 0) | |
6512 | base = 0; | |
6513 | ||
6514 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6515 | y = -y; | |
6516 | } | |
6517 | pos |= y << CURSOR_Y_SHIFT; | |
6518 | ||
6519 | visible = base != 0; | |
560b85bb | 6520 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6521 | return; |
6522 | ||
0cd83aa9 | 6523 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
6524 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6525 | ivb_update_cursor(crtc, base); | |
6526 | } else { | |
6527 | I915_WRITE(CURPOS(pipe), pos); | |
6528 | if (IS_845G(dev) || IS_I865G(dev)) | |
6529 | i845_update_cursor(crtc, base); | |
6530 | else | |
6531 | i9xx_update_cursor(crtc, base); | |
6532 | } | |
cda4b7d3 CW |
6533 | } |
6534 | ||
79e53945 | 6535 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6536 | struct drm_file *file, |
79e53945 JB |
6537 | uint32_t handle, |
6538 | uint32_t width, uint32_t height) | |
6539 | { | |
6540 | struct drm_device *dev = crtc->dev; | |
6541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6542 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6543 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6544 | uint32_t addr; |
3f8bc370 | 6545 | int ret; |
79e53945 | 6546 | |
79e53945 JB |
6547 | /* if we want to turn off the cursor ignore width and height */ |
6548 | if (!handle) { | |
28c97730 | 6549 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6550 | addr = 0; |
05394f39 | 6551 | obj = NULL; |
5004417d | 6552 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6553 | goto finish; |
79e53945 JB |
6554 | } |
6555 | ||
6556 | /* Currently we only support 64x64 cursors */ | |
6557 | if (width != 64 || height != 64) { | |
6558 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6559 | return -EINVAL; | |
6560 | } | |
6561 | ||
05394f39 | 6562 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6563 | if (&obj->base == NULL) |
79e53945 JB |
6564 | return -ENOENT; |
6565 | ||
05394f39 | 6566 | if (obj->base.size < width * height * 4) { |
79e53945 | 6567 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6568 | ret = -ENOMEM; |
6569 | goto fail; | |
79e53945 JB |
6570 | } |
6571 | ||
71acb5eb | 6572 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6573 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6574 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
6575 | unsigned alignment; |
6576 | ||
d9e86c0e CW |
6577 | if (obj->tiling_mode) { |
6578 | DRM_ERROR("cursor cannot be tiled\n"); | |
6579 | ret = -EINVAL; | |
6580 | goto fail_locked; | |
6581 | } | |
6582 | ||
693db184 CW |
6583 | /* Note that the w/a also requires 2 PTE of padding following |
6584 | * the bo. We currently fill all unused PTE with the shadow | |
6585 | * page and so we should always have valid PTE following the | |
6586 | * cursor preventing the VT-d warning. | |
6587 | */ | |
6588 | alignment = 0; | |
6589 | if (need_vtd_wa(dev)) | |
6590 | alignment = 64*1024; | |
6591 | ||
6592 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
6593 | if (ret) { |
6594 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6595 | goto fail_locked; |
e7b526bb CW |
6596 | } |
6597 | ||
d9e86c0e CW |
6598 | ret = i915_gem_object_put_fence(obj); |
6599 | if (ret) { | |
2da3b9b9 | 6600 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6601 | goto fail_unpin; |
6602 | } | |
6603 | ||
05394f39 | 6604 | addr = obj->gtt_offset; |
71acb5eb | 6605 | } else { |
6eeefaf3 | 6606 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6607 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6608 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6609 | align); | |
71acb5eb DA |
6610 | if (ret) { |
6611 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6612 | goto fail_locked; |
71acb5eb | 6613 | } |
05394f39 | 6614 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6615 | } |
6616 | ||
a6c45cf0 | 6617 | if (IS_GEN2(dev)) |
14b60391 JB |
6618 | I915_WRITE(CURSIZE, (height << 12) | width); |
6619 | ||
3f8bc370 | 6620 | finish: |
3f8bc370 | 6621 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6622 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6623 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6624 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6625 | } else | |
6626 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6627 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6628 | } |
80824003 | 6629 | |
7f9872e0 | 6630 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6631 | |
6632 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6633 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6634 | intel_crtc->cursor_width = width; |
6635 | intel_crtc->cursor_height = height; | |
6636 | ||
6b383a7f | 6637 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6638 | |
79e53945 | 6639 | return 0; |
e7b526bb | 6640 | fail_unpin: |
05394f39 | 6641 | i915_gem_object_unpin(obj); |
7f9872e0 | 6642 | fail_locked: |
34b8686e | 6643 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6644 | fail: |
05394f39 | 6645 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6646 | return ret; |
79e53945 JB |
6647 | } |
6648 | ||
6649 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6650 | { | |
79e53945 | 6651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6652 | |
cda4b7d3 CW |
6653 | intel_crtc->cursor_x = x; |
6654 | intel_crtc->cursor_y = y; | |
652c393a | 6655 | |
6b383a7f | 6656 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6657 | |
6658 | return 0; | |
6659 | } | |
6660 | ||
6661 | /** Sets the color ramps on behalf of RandR */ | |
6662 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6663 | u16 blue, int regno) | |
6664 | { | |
6665 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6666 | ||
6667 | intel_crtc->lut_r[regno] = red >> 8; | |
6668 | intel_crtc->lut_g[regno] = green >> 8; | |
6669 | intel_crtc->lut_b[regno] = blue >> 8; | |
6670 | } | |
6671 | ||
b8c00ac5 DA |
6672 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6673 | u16 *blue, int regno) | |
6674 | { | |
6675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6676 | ||
6677 | *red = intel_crtc->lut_r[regno] << 8; | |
6678 | *green = intel_crtc->lut_g[regno] << 8; | |
6679 | *blue = intel_crtc->lut_b[regno] << 8; | |
6680 | } | |
6681 | ||
79e53945 | 6682 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6683 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6684 | { |
7203425a | 6685 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6686 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6687 | |
7203425a | 6688 | for (i = start; i < end; i++) { |
79e53945 JB |
6689 | intel_crtc->lut_r[i] = red[i] >> 8; |
6690 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6691 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6692 | } | |
6693 | ||
6694 | intel_crtc_load_lut(crtc); | |
6695 | } | |
6696 | ||
79e53945 JB |
6697 | /* VESA 640x480x72Hz mode to set on the pipe */ |
6698 | static struct drm_display_mode load_detect_mode = { | |
6699 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6700 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6701 | }; | |
6702 | ||
d2dff872 CW |
6703 | static struct drm_framebuffer * |
6704 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6705 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6706 | struct drm_i915_gem_object *obj) |
6707 | { | |
6708 | struct intel_framebuffer *intel_fb; | |
6709 | int ret; | |
6710 | ||
6711 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6712 | if (!intel_fb) { | |
6713 | drm_gem_object_unreference_unlocked(&obj->base); | |
6714 | return ERR_PTR(-ENOMEM); | |
6715 | } | |
6716 | ||
6717 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6718 | if (ret) { | |
6719 | drm_gem_object_unreference_unlocked(&obj->base); | |
6720 | kfree(intel_fb); | |
6721 | return ERR_PTR(ret); | |
6722 | } | |
6723 | ||
6724 | return &intel_fb->base; | |
6725 | } | |
6726 | ||
6727 | static u32 | |
6728 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6729 | { | |
6730 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6731 | return ALIGN(pitch, 64); | |
6732 | } | |
6733 | ||
6734 | static u32 | |
6735 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6736 | { | |
6737 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6738 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6739 | } | |
6740 | ||
6741 | static struct drm_framebuffer * | |
6742 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6743 | struct drm_display_mode *mode, | |
6744 | int depth, int bpp) | |
6745 | { | |
6746 | struct drm_i915_gem_object *obj; | |
0fed39bd | 6747 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
6748 | |
6749 | obj = i915_gem_alloc_object(dev, | |
6750 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6751 | if (obj == NULL) | |
6752 | return ERR_PTR(-ENOMEM); | |
6753 | ||
6754 | mode_cmd.width = mode->hdisplay; | |
6755 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6756 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6757 | bpp); | |
5ca0c34a | 6758 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6759 | |
6760 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6761 | } | |
6762 | ||
6763 | static struct drm_framebuffer * | |
6764 | mode_fits_in_fbdev(struct drm_device *dev, | |
6765 | struct drm_display_mode *mode) | |
6766 | { | |
6767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6768 | struct drm_i915_gem_object *obj; | |
6769 | struct drm_framebuffer *fb; | |
6770 | ||
6771 | if (dev_priv->fbdev == NULL) | |
6772 | return NULL; | |
6773 | ||
6774 | obj = dev_priv->fbdev->ifb.obj; | |
6775 | if (obj == NULL) | |
6776 | return NULL; | |
6777 | ||
6778 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6779 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6780 | fb->bits_per_pixel)) | |
d2dff872 CW |
6781 | return NULL; |
6782 | ||
01f2c773 | 6783 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6784 | return NULL; |
6785 | ||
6786 | return fb; | |
6787 | } | |
6788 | ||
d2434ab7 | 6789 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 6790 | struct drm_display_mode *mode, |
8261b191 | 6791 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6792 | { |
6793 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
6794 | struct intel_encoder *intel_encoder = |
6795 | intel_attached_encoder(connector); | |
79e53945 | 6796 | struct drm_crtc *possible_crtc; |
4ef69c7a | 6797 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6798 | struct drm_crtc *crtc = NULL; |
6799 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 6800 | struct drm_framebuffer *fb; |
79e53945 JB |
6801 | int i = -1; |
6802 | ||
d2dff872 CW |
6803 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6804 | connector->base.id, drm_get_connector_name(connector), | |
6805 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6806 | ||
79e53945 JB |
6807 | /* |
6808 | * Algorithm gets a little messy: | |
7a5e4805 | 6809 | * |
79e53945 JB |
6810 | * - if the connector already has an assigned crtc, use it (but make |
6811 | * sure it's on first) | |
7a5e4805 | 6812 | * |
79e53945 JB |
6813 | * - try to find the first unused crtc that can drive this connector, |
6814 | * and use that if we find one | |
79e53945 JB |
6815 | */ |
6816 | ||
6817 | /* See if we already have a CRTC for this connector */ | |
6818 | if (encoder->crtc) { | |
6819 | crtc = encoder->crtc; | |
8261b191 | 6820 | |
7b24056b DV |
6821 | mutex_lock(&crtc->mutex); |
6822 | ||
24218aac | 6823 | old->dpms_mode = connector->dpms; |
8261b191 CW |
6824 | old->load_detect_temp = false; |
6825 | ||
6826 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
6827 | if (connector->dpms != DRM_MODE_DPMS_ON) |
6828 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 6829 | |
7173188d | 6830 | return true; |
79e53945 JB |
6831 | } |
6832 | ||
6833 | /* Find an unused one (if possible) */ | |
6834 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6835 | i++; | |
6836 | if (!(encoder->possible_crtcs & (1 << i))) | |
6837 | continue; | |
6838 | if (!possible_crtc->enabled) { | |
6839 | crtc = possible_crtc; | |
6840 | break; | |
6841 | } | |
79e53945 JB |
6842 | } |
6843 | ||
6844 | /* | |
6845 | * If we didn't find an unused CRTC, don't use any. | |
6846 | */ | |
6847 | if (!crtc) { | |
7173188d CW |
6848 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6849 | return false; | |
79e53945 JB |
6850 | } |
6851 | ||
7b24056b | 6852 | mutex_lock(&crtc->mutex); |
fc303101 DV |
6853 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
6854 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
6855 | |
6856 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 6857 | old->dpms_mode = connector->dpms; |
8261b191 | 6858 | old->load_detect_temp = true; |
d2dff872 | 6859 | old->release_fb = NULL; |
79e53945 | 6860 | |
6492711d CW |
6861 | if (!mode) |
6862 | mode = &load_detect_mode; | |
79e53945 | 6863 | |
d2dff872 CW |
6864 | /* We need a framebuffer large enough to accommodate all accesses |
6865 | * that the plane may generate whilst we perform load detection. | |
6866 | * We can not rely on the fbcon either being present (we get called | |
6867 | * during its initialisation to detect all boot displays, or it may | |
6868 | * not even exist) or that it is large enough to satisfy the | |
6869 | * requested mode. | |
6870 | */ | |
94352cf9 DV |
6871 | fb = mode_fits_in_fbdev(dev, mode); |
6872 | if (fb == NULL) { | |
d2dff872 | 6873 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
6874 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
6875 | old->release_fb = fb; | |
d2dff872 CW |
6876 | } else |
6877 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 6878 | if (IS_ERR(fb)) { |
d2dff872 | 6879 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 6880 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 6881 | return false; |
79e53945 | 6882 | } |
79e53945 | 6883 | |
c0c36b94 | 6884 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 6885 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6886 | if (old->release_fb) |
6887 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 6888 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 6889 | return false; |
79e53945 | 6890 | } |
7173188d | 6891 | |
79e53945 | 6892 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6893 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 6894 | return true; |
79e53945 JB |
6895 | } |
6896 | ||
d2434ab7 | 6897 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 6898 | struct intel_load_detect_pipe *old) |
79e53945 | 6899 | { |
d2434ab7 DV |
6900 | struct intel_encoder *intel_encoder = |
6901 | intel_attached_encoder(connector); | |
4ef69c7a | 6902 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 6903 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 6904 | |
d2dff872 CW |
6905 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6906 | connector->base.id, drm_get_connector_name(connector), | |
6907 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6908 | ||
8261b191 | 6909 | if (old->load_detect_temp) { |
fc303101 DV |
6910 | to_intel_connector(connector)->new_encoder = NULL; |
6911 | intel_encoder->new_crtc = NULL; | |
6912 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 6913 | |
36206361 DV |
6914 | if (old->release_fb) { |
6915 | drm_framebuffer_unregister_private(old->release_fb); | |
6916 | drm_framebuffer_unreference(old->release_fb); | |
6917 | } | |
d2dff872 | 6918 | |
67c96400 | 6919 | mutex_unlock(&crtc->mutex); |
0622a53c | 6920 | return; |
79e53945 JB |
6921 | } |
6922 | ||
c751ce4f | 6923 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
6924 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
6925 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
6926 | |
6927 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
6928 | } |
6929 | ||
6930 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6931 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6932 | { | |
6933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6934 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6935 | int pipe = intel_crtc->pipe; | |
548f245b | 6936 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6937 | u32 fp; |
6938 | intel_clock_t clock; | |
6939 | ||
6940 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6941 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6942 | else |
39adb7a5 | 6943 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6944 | |
6945 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6946 | if (IS_PINEVIEW(dev)) { |
6947 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6948 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6949 | } else { |
6950 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6951 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6952 | } | |
6953 | ||
a6c45cf0 | 6954 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6955 | if (IS_PINEVIEW(dev)) |
6956 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6957 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6958 | else |
6959 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6960 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6961 | ||
6962 | switch (dpll & DPLL_MODE_MASK) { | |
6963 | case DPLLB_MODE_DAC_SERIAL: | |
6964 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6965 | 5 : 10; | |
6966 | break; | |
6967 | case DPLLB_MODE_LVDS: | |
6968 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6969 | 7 : 14; | |
6970 | break; | |
6971 | default: | |
28c97730 | 6972 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6973 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6974 | return 0; | |
6975 | } | |
6976 | ||
6977 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6978 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6979 | } else { |
6980 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6981 | ||
6982 | if (is_lvds) { | |
6983 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6984 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6985 | clock.p2 = 14; | |
6986 | ||
6987 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6988 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6989 | /* XXX: might not be 66MHz */ | |
2177832f | 6990 | intel_clock(dev, 66000, &clock); |
79e53945 | 6991 | } else |
2177832f | 6992 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6993 | } else { |
6994 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6995 | clock.p1 = 2; | |
6996 | else { | |
6997 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6998 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6999 | } | |
7000 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7001 | clock.p2 = 4; | |
7002 | else | |
7003 | clock.p2 = 2; | |
7004 | ||
2177832f | 7005 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
7006 | } |
7007 | } | |
7008 | ||
7009 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
7010 | * i830PllIsValid() because it relies on the xf86_config connector | |
7011 | * configuration being accurate, which it isn't necessarily. | |
7012 | */ | |
7013 | ||
7014 | return clock.dot; | |
7015 | } | |
7016 | ||
7017 | /** Returns the currently programmed mode of the given pipe. */ | |
7018 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7019 | struct drm_crtc *crtc) | |
7020 | { | |
548f245b | 7021 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 7022 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 7023 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 7024 | struct drm_display_mode *mode; |
fe2b8f9d PZ |
7025 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7026 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
7027 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
7028 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
79e53945 JB |
7029 | |
7030 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
7031 | if (!mode) | |
7032 | return NULL; | |
7033 | ||
7034 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
7035 | mode->hdisplay = (htot & 0xffff) + 1; | |
7036 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
7037 | mode->hsync_start = (hsync & 0xffff) + 1; | |
7038 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
7039 | mode->vdisplay = (vtot & 0xffff) + 1; | |
7040 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
7041 | mode->vsync_start = (vsync & 0xffff) + 1; | |
7042 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
7043 | ||
7044 | drm_mode_set_name(mode); | |
79e53945 JB |
7045 | |
7046 | return mode; | |
7047 | } | |
7048 | ||
3dec0095 | 7049 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7050 | { |
7051 | struct drm_device *dev = crtc->dev; | |
7052 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7054 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7055 | int dpll_reg = DPLL(pipe); |
7056 | int dpll; | |
652c393a | 7057 | |
bad720ff | 7058 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7059 | return; |
7060 | ||
7061 | if (!dev_priv->lvds_downclock_avail) | |
7062 | return; | |
7063 | ||
dbdc6479 | 7064 | dpll = I915_READ(dpll_reg); |
652c393a | 7065 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7066 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7067 | |
8ac5a6d5 | 7068 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7069 | |
7070 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7071 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7072 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7073 | |
652c393a JB |
7074 | dpll = I915_READ(dpll_reg); |
7075 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7076 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 7077 | } |
652c393a JB |
7078 | } |
7079 | ||
7080 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7081 | { | |
7082 | struct drm_device *dev = crtc->dev; | |
7083 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7084 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 7085 | |
bad720ff | 7086 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7087 | return; |
7088 | ||
7089 | if (!dev_priv->lvds_downclock_avail) | |
7090 | return; | |
7091 | ||
7092 | /* | |
7093 | * Since this is called by a timer, we should never get here in | |
7094 | * the manual case. | |
7095 | */ | |
7096 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
7097 | int pipe = intel_crtc->pipe; |
7098 | int dpll_reg = DPLL(pipe); | |
7099 | int dpll; | |
f6e5b160 | 7100 | |
44d98a61 | 7101 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7102 | |
8ac5a6d5 | 7103 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 7104 | |
dc257cf1 | 7105 | dpll = I915_READ(dpll_reg); |
652c393a JB |
7106 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7107 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7108 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7109 | dpll = I915_READ(dpll_reg); |
7110 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7111 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7112 | } |
7113 | ||
7114 | } | |
7115 | ||
f047e395 CW |
7116 | void intel_mark_busy(struct drm_device *dev) |
7117 | { | |
f047e395 CW |
7118 | i915_update_gfx_val(dev->dev_private); |
7119 | } | |
7120 | ||
7121 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 7122 | { |
652c393a | 7123 | struct drm_crtc *crtc; |
652c393a JB |
7124 | |
7125 | if (!i915_powersave) | |
7126 | return; | |
7127 | ||
652c393a | 7128 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
7129 | if (!crtc->fb) |
7130 | continue; | |
7131 | ||
725a5b54 | 7132 | intel_decrease_pllclock(crtc); |
652c393a | 7133 | } |
652c393a JB |
7134 | } |
7135 | ||
725a5b54 | 7136 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) |
652c393a | 7137 | { |
f047e395 CW |
7138 | struct drm_device *dev = obj->base.dev; |
7139 | struct drm_crtc *crtc; | |
652c393a | 7140 | |
f047e395 | 7141 | if (!i915_powersave) |
acb87dfb CW |
7142 | return; |
7143 | ||
652c393a JB |
7144 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7145 | if (!crtc->fb) | |
7146 | continue; | |
7147 | ||
f047e395 | 7148 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
725a5b54 | 7149 | intel_increase_pllclock(crtc); |
652c393a JB |
7150 | } |
7151 | } | |
7152 | ||
79e53945 JB |
7153 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7154 | { | |
7155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7156 | struct drm_device *dev = crtc->dev; |
7157 | struct intel_unpin_work *work; | |
7158 | unsigned long flags; | |
7159 | ||
7160 | spin_lock_irqsave(&dev->event_lock, flags); | |
7161 | work = intel_crtc->unpin_work; | |
7162 | intel_crtc->unpin_work = NULL; | |
7163 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7164 | ||
7165 | if (work) { | |
7166 | cancel_work_sync(&work->work); | |
7167 | kfree(work); | |
7168 | } | |
79e53945 JB |
7169 | |
7170 | drm_crtc_cleanup(crtc); | |
67e77c5a | 7171 | |
79e53945 JB |
7172 | kfree(intel_crtc); |
7173 | } | |
7174 | ||
6b95a207 KH |
7175 | static void intel_unpin_work_fn(struct work_struct *__work) |
7176 | { | |
7177 | struct intel_unpin_work *work = | |
7178 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 7179 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 7180 | |
b4a98e57 | 7181 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 7182 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7183 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7184 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7185 | |
b4a98e57 CW |
7186 | intel_update_fbc(dev); |
7187 | mutex_unlock(&dev->struct_mutex); | |
7188 | ||
7189 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
7190 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
7191 | ||
6b95a207 KH |
7192 | kfree(work); |
7193 | } | |
7194 | ||
1afe3e9d | 7195 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7196 | struct drm_crtc *crtc) |
6b95a207 KH |
7197 | { |
7198 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7200 | struct intel_unpin_work *work; | |
6b95a207 KH |
7201 | unsigned long flags; |
7202 | ||
7203 | /* Ignore early vblank irqs */ | |
7204 | if (intel_crtc == NULL) | |
7205 | return; | |
7206 | ||
7207 | spin_lock_irqsave(&dev->event_lock, flags); | |
7208 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
7209 | |
7210 | /* Ensure we don't miss a work->pending update ... */ | |
7211 | smp_rmb(); | |
7212 | ||
7213 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
7214 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7215 | return; | |
7216 | } | |
7217 | ||
e7d841ca CW |
7218 | /* and that the unpin work is consistent wrt ->pending. */ |
7219 | smp_rmb(); | |
7220 | ||
6b95a207 | 7221 | intel_crtc->unpin_work = NULL; |
6b95a207 | 7222 | |
45a066eb RC |
7223 | if (work->event) |
7224 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 7225 | |
0af7e4df MK |
7226 | drm_vblank_put(dev, intel_crtc->pipe); |
7227 | ||
6b95a207 KH |
7228 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7229 | ||
2c10d571 | 7230 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
7231 | |
7232 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
7233 | |
7234 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7235 | } |
7236 | ||
1afe3e9d JB |
7237 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7238 | { | |
7239 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7240 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7241 | ||
49b14a5c | 7242 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7243 | } |
7244 | ||
7245 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7246 | { | |
7247 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7248 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7249 | ||
49b14a5c | 7250 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7251 | } |
7252 | ||
6b95a207 KH |
7253 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7254 | { | |
7255 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7256 | struct intel_crtc *intel_crtc = | |
7257 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7258 | unsigned long flags; | |
7259 | ||
e7d841ca CW |
7260 | /* NB: An MMIO update of the plane base pointer will also |
7261 | * generate a page-flip completion irq, i.e. every modeset | |
7262 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
7263 | */ | |
6b95a207 | 7264 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
7265 | if (intel_crtc->unpin_work) |
7266 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
7267 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7268 | } | |
7269 | ||
e7d841ca CW |
7270 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7271 | { | |
7272 | /* Ensure that the work item is consistent when activating it ... */ | |
7273 | smp_wmb(); | |
7274 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
7275 | /* and that it is marked active as soon as the irq could fire. */ | |
7276 | smp_wmb(); | |
7277 | } | |
7278 | ||
8c9f3aaf JB |
7279 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7280 | struct drm_crtc *crtc, | |
7281 | struct drm_framebuffer *fb, | |
7282 | struct drm_i915_gem_object *obj) | |
7283 | { | |
7284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7286 | u32 flip_mask; |
6d90c952 | 7287 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7288 | int ret; |
7289 | ||
6d90c952 | 7290 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7291 | if (ret) |
83d4092b | 7292 | goto err; |
8c9f3aaf | 7293 | |
6d90c952 | 7294 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7295 | if (ret) |
83d4092b | 7296 | goto err_unpin; |
8c9f3aaf JB |
7297 | |
7298 | /* Can't queue multiple flips, so wait for the previous | |
7299 | * one to finish before executing the next. | |
7300 | */ | |
7301 | if (intel_crtc->plane) | |
7302 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7303 | else | |
7304 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7305 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7306 | intel_ring_emit(ring, MI_NOOP); | |
7307 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
7308 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7309 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 7310 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 | 7311 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
7312 | |
7313 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7314 | intel_ring_advance(ring); |
83d4092b CW |
7315 | return 0; |
7316 | ||
7317 | err_unpin: | |
7318 | intel_unpin_fb_obj(obj); | |
7319 | err: | |
8c9f3aaf JB |
7320 | return ret; |
7321 | } | |
7322 | ||
7323 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7324 | struct drm_crtc *crtc, | |
7325 | struct drm_framebuffer *fb, | |
7326 | struct drm_i915_gem_object *obj) | |
7327 | { | |
7328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7330 | u32 flip_mask; |
6d90c952 | 7331 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7332 | int ret; |
7333 | ||
6d90c952 | 7334 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7335 | if (ret) |
83d4092b | 7336 | goto err; |
8c9f3aaf | 7337 | |
6d90c952 | 7338 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7339 | if (ret) |
83d4092b | 7340 | goto err_unpin; |
8c9f3aaf JB |
7341 | |
7342 | if (intel_crtc->plane) | |
7343 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7344 | else | |
7345 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7346 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7347 | intel_ring_emit(ring, MI_NOOP); | |
7348 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
7349 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7350 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 7351 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
7352 | intel_ring_emit(ring, MI_NOOP); |
7353 | ||
e7d841ca | 7354 | intel_mark_page_flip_active(intel_crtc); |
6d90c952 | 7355 | intel_ring_advance(ring); |
83d4092b CW |
7356 | return 0; |
7357 | ||
7358 | err_unpin: | |
7359 | intel_unpin_fb_obj(obj); | |
7360 | err: | |
8c9f3aaf JB |
7361 | return ret; |
7362 | } | |
7363 | ||
7364 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7365 | struct drm_crtc *crtc, | |
7366 | struct drm_framebuffer *fb, | |
7367 | struct drm_i915_gem_object *obj) | |
7368 | { | |
7369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7370 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7371 | uint32_t pf, pipesrc; | |
6d90c952 | 7372 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7373 | int ret; |
7374 | ||
6d90c952 | 7375 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7376 | if (ret) |
83d4092b | 7377 | goto err; |
8c9f3aaf | 7378 | |
6d90c952 | 7379 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7380 | if (ret) |
83d4092b | 7381 | goto err_unpin; |
8c9f3aaf JB |
7382 | |
7383 | /* i965+ uses the linear or tiled offsets from the | |
7384 | * Display Registers (which do not change across a page-flip) | |
7385 | * so we need only reprogram the base address. | |
7386 | */ | |
6d90c952 DV |
7387 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7388 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7389 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
7390 | intel_ring_emit(ring, |
7391 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
7392 | obj->tiling_mode); | |
8c9f3aaf JB |
7393 | |
7394 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7395 | * untested on non-native modes, so ignore it for now. | |
7396 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7397 | */ | |
7398 | pf = 0; | |
7399 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 7400 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7401 | |
7402 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7403 | intel_ring_advance(ring); |
83d4092b CW |
7404 | return 0; |
7405 | ||
7406 | err_unpin: | |
7407 | intel_unpin_fb_obj(obj); | |
7408 | err: | |
8c9f3aaf JB |
7409 | return ret; |
7410 | } | |
7411 | ||
7412 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7413 | struct drm_crtc *crtc, | |
7414 | struct drm_framebuffer *fb, | |
7415 | struct drm_i915_gem_object *obj) | |
7416 | { | |
7417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7418 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 7419 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7420 | uint32_t pf, pipesrc; |
7421 | int ret; | |
7422 | ||
6d90c952 | 7423 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7424 | if (ret) |
83d4092b | 7425 | goto err; |
8c9f3aaf | 7426 | |
6d90c952 | 7427 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7428 | if (ret) |
83d4092b | 7429 | goto err_unpin; |
8c9f3aaf | 7430 | |
6d90c952 DV |
7431 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7432 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7433 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 7434 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 7435 | |
dc257cf1 DV |
7436 | /* Contrary to the suggestions in the documentation, |
7437 | * "Enable Panel Fitter" does not seem to be required when page | |
7438 | * flipping with a non-native mode, and worse causes a normal | |
7439 | * modeset to fail. | |
7440 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7441 | */ | |
7442 | pf = 0; | |
8c9f3aaf | 7443 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 7444 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7445 | |
7446 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7447 | intel_ring_advance(ring); |
83d4092b CW |
7448 | return 0; |
7449 | ||
7450 | err_unpin: | |
7451 | intel_unpin_fb_obj(obj); | |
7452 | err: | |
8c9f3aaf JB |
7453 | return ret; |
7454 | } | |
7455 | ||
7c9017e5 JB |
7456 | /* |
7457 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7458 | * the render ring doesn't give us interrpts for page flip completion, which | |
7459 | * means clients will hang after the first flip is queued. Fortunately the | |
7460 | * blit ring generates interrupts properly, so use it instead. | |
7461 | */ | |
7462 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7463 | struct drm_crtc *crtc, | |
7464 | struct drm_framebuffer *fb, | |
7465 | struct drm_i915_gem_object *obj) | |
7466 | { | |
7467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7469 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 7470 | uint32_t plane_bit = 0; |
7c9017e5 JB |
7471 | int ret; |
7472 | ||
7473 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7474 | if (ret) | |
83d4092b | 7475 | goto err; |
7c9017e5 | 7476 | |
cb05d8de DV |
7477 | switch(intel_crtc->plane) { |
7478 | case PLANE_A: | |
7479 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
7480 | break; | |
7481 | case PLANE_B: | |
7482 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
7483 | break; | |
7484 | case PLANE_C: | |
7485 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
7486 | break; | |
7487 | default: | |
7488 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
7489 | ret = -ENODEV; | |
ab3951eb | 7490 | goto err_unpin; |
cb05d8de DV |
7491 | } |
7492 | ||
7c9017e5 JB |
7493 | ret = intel_ring_begin(ring, 4); |
7494 | if (ret) | |
83d4092b | 7495 | goto err_unpin; |
7c9017e5 | 7496 | |
cb05d8de | 7497 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 7498 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 7499 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 | 7500 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
7501 | |
7502 | intel_mark_page_flip_active(intel_crtc); | |
7c9017e5 | 7503 | intel_ring_advance(ring); |
83d4092b CW |
7504 | return 0; |
7505 | ||
7506 | err_unpin: | |
7507 | intel_unpin_fb_obj(obj); | |
7508 | err: | |
7c9017e5 JB |
7509 | return ret; |
7510 | } | |
7511 | ||
8c9f3aaf JB |
7512 | static int intel_default_queue_flip(struct drm_device *dev, |
7513 | struct drm_crtc *crtc, | |
7514 | struct drm_framebuffer *fb, | |
7515 | struct drm_i915_gem_object *obj) | |
7516 | { | |
7517 | return -ENODEV; | |
7518 | } | |
7519 | ||
6b95a207 KH |
7520 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7521 | struct drm_framebuffer *fb, | |
7522 | struct drm_pending_vblank_event *event) | |
7523 | { | |
7524 | struct drm_device *dev = crtc->dev; | |
7525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
7526 | struct drm_framebuffer *old_fb = crtc->fb; |
7527 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
7528 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7529 | struct intel_unpin_work *work; | |
8c9f3aaf | 7530 | unsigned long flags; |
52e68630 | 7531 | int ret; |
6b95a207 | 7532 | |
e6a595d2 VS |
7533 | /* Can't change pixel format via MI display flips. */ |
7534 | if (fb->pixel_format != crtc->fb->pixel_format) | |
7535 | return -EINVAL; | |
7536 | ||
7537 | /* | |
7538 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
7539 | * Note that pitch changes could also affect these register. | |
7540 | */ | |
7541 | if (INTEL_INFO(dev)->gen > 3 && | |
7542 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
7543 | fb->pitches[0] != crtc->fb->pitches[0])) | |
7544 | return -EINVAL; | |
7545 | ||
6b95a207 KH |
7546 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7547 | if (work == NULL) | |
7548 | return -ENOMEM; | |
7549 | ||
6b95a207 | 7550 | work->event = event; |
b4a98e57 | 7551 | work->crtc = crtc; |
4a35f83b | 7552 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
7553 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7554 | ||
7317c75e JB |
7555 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7556 | if (ret) | |
7557 | goto free_work; | |
7558 | ||
6b95a207 KH |
7559 | /* We borrow the event spin lock for protecting unpin_work */ |
7560 | spin_lock_irqsave(&dev->event_lock, flags); | |
7561 | if (intel_crtc->unpin_work) { | |
7562 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7563 | kfree(work); | |
7317c75e | 7564 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7565 | |
7566 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7567 | return -EBUSY; |
7568 | } | |
7569 | intel_crtc->unpin_work = work; | |
7570 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7571 | ||
b4a98e57 CW |
7572 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
7573 | flush_workqueue(dev_priv->wq); | |
7574 | ||
79158103 CW |
7575 | ret = i915_mutex_lock_interruptible(dev); |
7576 | if (ret) | |
7577 | goto cleanup; | |
6b95a207 | 7578 | |
75dfca80 | 7579 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7580 | drm_gem_object_reference(&work->old_fb_obj->base); |
7581 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7582 | |
7583 | crtc->fb = fb; | |
96b099fd | 7584 | |
e1f99ce6 | 7585 | work->pending_flip_obj = obj; |
e1f99ce6 | 7586 | |
4e5359cd SF |
7587 | work->enable_stall_check = true; |
7588 | ||
b4a98e57 | 7589 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 7590 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 7591 | |
8c9f3aaf JB |
7592 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7593 | if (ret) | |
7594 | goto cleanup_pending; | |
6b95a207 | 7595 | |
7782de3b | 7596 | intel_disable_fbc(dev); |
f047e395 | 7597 | intel_mark_fb_busy(obj); |
6b95a207 KH |
7598 | mutex_unlock(&dev->struct_mutex); |
7599 | ||
e5510fac JB |
7600 | trace_i915_flip_request(intel_crtc->plane, obj); |
7601 | ||
6b95a207 | 7602 | return 0; |
96b099fd | 7603 | |
8c9f3aaf | 7604 | cleanup_pending: |
b4a98e57 | 7605 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 7606 | crtc->fb = old_fb; |
05394f39 CW |
7607 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7608 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7609 | mutex_unlock(&dev->struct_mutex); |
7610 | ||
79158103 | 7611 | cleanup: |
96b099fd CW |
7612 | spin_lock_irqsave(&dev->event_lock, flags); |
7613 | intel_crtc->unpin_work = NULL; | |
7614 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7615 | ||
7317c75e JB |
7616 | drm_vblank_put(dev, intel_crtc->pipe); |
7617 | free_work: | |
96b099fd CW |
7618 | kfree(work); |
7619 | ||
7620 | return ret; | |
6b95a207 KH |
7621 | } |
7622 | ||
f6e5b160 | 7623 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
7624 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
7625 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
7626 | }; |
7627 | ||
6ed0f796 | 7628 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
47f1c6c9 | 7629 | { |
6ed0f796 DV |
7630 | struct intel_encoder *other_encoder; |
7631 | struct drm_crtc *crtc = &encoder->new_crtc->base; | |
47f1c6c9 | 7632 | |
6ed0f796 DV |
7633 | if (WARN_ON(!crtc)) |
7634 | return false; | |
7635 | ||
7636 | list_for_each_entry(other_encoder, | |
7637 | &crtc->dev->mode_config.encoder_list, | |
7638 | base.head) { | |
7639 | ||
7640 | if (&other_encoder->new_crtc->base != crtc || | |
7641 | encoder == other_encoder) | |
7642 | continue; | |
7643 | else | |
7644 | return true; | |
f47166d2 CW |
7645 | } |
7646 | ||
6ed0f796 DV |
7647 | return false; |
7648 | } | |
47f1c6c9 | 7649 | |
50f56119 DV |
7650 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
7651 | struct drm_crtc *crtc) | |
7652 | { | |
7653 | struct drm_device *dev; | |
7654 | struct drm_crtc *tmp; | |
7655 | int crtc_mask = 1; | |
47f1c6c9 | 7656 | |
50f56119 | 7657 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 7658 | |
50f56119 | 7659 | dev = crtc->dev; |
47f1c6c9 | 7660 | |
50f56119 DV |
7661 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
7662 | if (tmp == crtc) | |
7663 | break; | |
7664 | crtc_mask <<= 1; | |
7665 | } | |
47f1c6c9 | 7666 | |
50f56119 DV |
7667 | if (encoder->possible_crtcs & crtc_mask) |
7668 | return true; | |
7669 | return false; | |
47f1c6c9 | 7670 | } |
79e53945 | 7671 | |
9a935856 DV |
7672 | /** |
7673 | * intel_modeset_update_staged_output_state | |
7674 | * | |
7675 | * Updates the staged output configuration state, e.g. after we've read out the | |
7676 | * current hw state. | |
7677 | */ | |
7678 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 7679 | { |
9a935856 DV |
7680 | struct intel_encoder *encoder; |
7681 | struct intel_connector *connector; | |
f6e5b160 | 7682 | |
9a935856 DV |
7683 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7684 | base.head) { | |
7685 | connector->new_encoder = | |
7686 | to_intel_encoder(connector->base.encoder); | |
7687 | } | |
f6e5b160 | 7688 | |
9a935856 DV |
7689 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7690 | base.head) { | |
7691 | encoder->new_crtc = | |
7692 | to_intel_crtc(encoder->base.crtc); | |
7693 | } | |
f6e5b160 CW |
7694 | } |
7695 | ||
9a935856 DV |
7696 | /** |
7697 | * intel_modeset_commit_output_state | |
7698 | * | |
7699 | * This function copies the stage display pipe configuration to the real one. | |
7700 | */ | |
7701 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
7702 | { | |
7703 | struct intel_encoder *encoder; | |
7704 | struct intel_connector *connector; | |
f6e5b160 | 7705 | |
9a935856 DV |
7706 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7707 | base.head) { | |
7708 | connector->base.encoder = &connector->new_encoder->base; | |
7709 | } | |
f6e5b160 | 7710 | |
9a935856 DV |
7711 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7712 | base.head) { | |
7713 | encoder->base.crtc = &encoder->new_crtc->base; | |
7714 | } | |
7715 | } | |
7716 | ||
4e53c2e0 DV |
7717 | static int |
7718 | pipe_config_set_bpp(struct drm_crtc *crtc, | |
7719 | struct drm_framebuffer *fb, | |
7720 | struct intel_crtc_config *pipe_config) | |
7721 | { | |
7722 | struct drm_device *dev = crtc->dev; | |
7723 | struct drm_connector *connector; | |
7724 | int bpp; | |
7725 | ||
d42264b1 DV |
7726 | switch (fb->pixel_format) { |
7727 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
7728 | bpp = 8*3; /* since we go through a colormap */ |
7729 | break; | |
d42264b1 DV |
7730 | case DRM_FORMAT_XRGB1555: |
7731 | case DRM_FORMAT_ARGB1555: | |
7732 | /* checked in intel_framebuffer_init already */ | |
7733 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
7734 | return -EINVAL; | |
7735 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
7736 | bpp = 6*3; /* min is 18bpp */ |
7737 | break; | |
d42264b1 DV |
7738 | case DRM_FORMAT_XBGR8888: |
7739 | case DRM_FORMAT_ABGR8888: | |
7740 | /* checked in intel_framebuffer_init already */ | |
7741 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
7742 | return -EINVAL; | |
7743 | case DRM_FORMAT_XRGB8888: | |
7744 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
7745 | bpp = 8*3; |
7746 | break; | |
d42264b1 DV |
7747 | case DRM_FORMAT_XRGB2101010: |
7748 | case DRM_FORMAT_ARGB2101010: | |
7749 | case DRM_FORMAT_XBGR2101010: | |
7750 | case DRM_FORMAT_ABGR2101010: | |
7751 | /* checked in intel_framebuffer_init already */ | |
7752 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 7753 | return -EINVAL; |
4e53c2e0 DV |
7754 | bpp = 10*3; |
7755 | break; | |
baba133a | 7756 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
7757 | default: |
7758 | DRM_DEBUG_KMS("unsupported depth\n"); | |
7759 | return -EINVAL; | |
7760 | } | |
7761 | ||
4e53c2e0 DV |
7762 | pipe_config->pipe_bpp = bpp; |
7763 | ||
7764 | /* Clamp display bpp to EDID value */ | |
7765 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7766 | head) { | |
7767 | if (connector->encoder && connector->encoder->crtc != crtc) | |
7768 | continue; | |
7769 | ||
7770 | /* Don't use an invalid EDID bpc value */ | |
7771 | if (connector->display_info.bpc && | |
7772 | connector->display_info.bpc * 3 < bpp) { | |
7773 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
7774 | bpp, connector->display_info.bpc*3); | |
7775 | pipe_config->pipe_bpp = connector->display_info.bpc*3; | |
7776 | } | |
996a2239 DV |
7777 | |
7778 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
7779 | if (connector->display_info.bpc == 0 && bpp > 24) { | |
7780 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
7781 | bpp); | |
7782 | pipe_config->pipe_bpp = 24; | |
7783 | } | |
4e53c2e0 DV |
7784 | } |
7785 | ||
7786 | return bpp; | |
7787 | } | |
7788 | ||
b8cecdf5 DV |
7789 | static struct intel_crtc_config * |
7790 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 7791 | struct drm_framebuffer *fb, |
b8cecdf5 | 7792 | struct drm_display_mode *mode) |
ee7b9f93 | 7793 | { |
7758a113 | 7794 | struct drm_device *dev = crtc->dev; |
7758a113 DV |
7795 | struct drm_encoder_helper_funcs *encoder_funcs; |
7796 | struct intel_encoder *encoder; | |
b8cecdf5 | 7797 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
7798 | int plane_bpp, ret = -EINVAL; |
7799 | bool retry = true; | |
ee7b9f93 | 7800 | |
b8cecdf5 DV |
7801 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
7802 | if (!pipe_config) | |
7758a113 DV |
7803 | return ERR_PTR(-ENOMEM); |
7804 | ||
b8cecdf5 DV |
7805 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
7806 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
7807 | ||
4e53c2e0 DV |
7808 | plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config); |
7809 | if (plane_bpp < 0) | |
7810 | goto fail; | |
7811 | ||
e29c22c0 | 7812 | encoder_retry: |
7758a113 DV |
7813 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
7814 | * adjust it according to limitations or connector properties, and also | |
7815 | * a chance to reject the mode entirely. | |
47f1c6c9 | 7816 | */ |
7758a113 DV |
7817 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7818 | base.head) { | |
47f1c6c9 | 7819 | |
7758a113 DV |
7820 | if (&encoder->new_crtc->base != crtc) |
7821 | continue; | |
7ae89233 DV |
7822 | |
7823 | if (encoder->compute_config) { | |
7824 | if (!(encoder->compute_config(encoder, pipe_config))) { | |
7825 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7826 | goto fail; | |
7827 | } | |
7828 | ||
7829 | continue; | |
7830 | } | |
7831 | ||
7758a113 | 7832 | encoder_funcs = encoder->base.helper_private; |
b8cecdf5 DV |
7833 | if (!(encoder_funcs->mode_fixup(&encoder->base, |
7834 | &pipe_config->requested_mode, | |
7835 | &pipe_config->adjusted_mode))) { | |
7758a113 DV |
7836 | DRM_DEBUG_KMS("Encoder fixup failed\n"); |
7837 | goto fail; | |
7838 | } | |
ee7b9f93 | 7839 | } |
47f1c6c9 | 7840 | |
e29c22c0 DV |
7841 | ret = intel_crtc_compute_config(crtc, pipe_config); |
7842 | if (ret < 0) { | |
7758a113 DV |
7843 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
7844 | goto fail; | |
ee7b9f93 | 7845 | } |
e29c22c0 DV |
7846 | |
7847 | if (ret == RETRY) { | |
7848 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
7849 | ret = -EINVAL; | |
7850 | goto fail; | |
7851 | } | |
7852 | ||
7853 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
7854 | retry = false; | |
7855 | goto encoder_retry; | |
7856 | } | |
7857 | ||
7758a113 | 7858 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
47f1c6c9 | 7859 | |
4e53c2e0 DV |
7860 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
7861 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
7862 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
7863 | ||
b8cecdf5 | 7864 | return pipe_config; |
7758a113 | 7865 | fail: |
b8cecdf5 | 7866 | kfree(pipe_config); |
e29c22c0 | 7867 | return ERR_PTR(ret); |
ee7b9f93 | 7868 | } |
47f1c6c9 | 7869 | |
e2e1ed41 DV |
7870 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
7871 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
7872 | static void | |
7873 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
7874 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
7875 | { |
7876 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
7877 | struct drm_device *dev = crtc->dev; |
7878 | struct intel_encoder *encoder; | |
7879 | struct intel_connector *connector; | |
7880 | struct drm_crtc *tmp_crtc; | |
79e53945 | 7881 | |
e2e1ed41 | 7882 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 7883 | |
e2e1ed41 DV |
7884 | /* Check which crtcs have changed outputs connected to them, these need |
7885 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
7886 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
7887 | * bit set at most. */ | |
7888 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7889 | base.head) { | |
7890 | if (connector->base.encoder == &connector->new_encoder->base) | |
7891 | continue; | |
79e53945 | 7892 | |
e2e1ed41 DV |
7893 | if (connector->base.encoder) { |
7894 | tmp_crtc = connector->base.encoder->crtc; | |
7895 | ||
7896 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7897 | } | |
7898 | ||
7899 | if (connector->new_encoder) | |
7900 | *prepare_pipes |= | |
7901 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
7902 | } |
7903 | ||
e2e1ed41 DV |
7904 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7905 | base.head) { | |
7906 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
7907 | continue; | |
7908 | ||
7909 | if (encoder->base.crtc) { | |
7910 | tmp_crtc = encoder->base.crtc; | |
7911 | ||
7912 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7913 | } | |
7914 | ||
7915 | if (encoder->new_crtc) | |
7916 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
7917 | } |
7918 | ||
e2e1ed41 DV |
7919 | /* Check for any pipes that will be fully disabled ... */ |
7920 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7921 | base.head) { | |
7922 | bool used = false; | |
22fd0fab | 7923 | |
e2e1ed41 DV |
7924 | /* Don't try to disable disabled crtcs. */ |
7925 | if (!intel_crtc->base.enabled) | |
7926 | continue; | |
7e7d76c3 | 7927 | |
e2e1ed41 DV |
7928 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7929 | base.head) { | |
7930 | if (encoder->new_crtc == intel_crtc) | |
7931 | used = true; | |
7932 | } | |
7933 | ||
7934 | if (!used) | |
7935 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
7936 | } |
7937 | ||
e2e1ed41 DV |
7938 | |
7939 | /* set_mode is also used to update properties on life display pipes. */ | |
7940 | intel_crtc = to_intel_crtc(crtc); | |
7941 | if (crtc->enabled) | |
7942 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7943 | ||
b6c5164d DV |
7944 | /* |
7945 | * For simplicity do a full modeset on any pipe where the output routing | |
7946 | * changed. We could be more clever, but that would require us to be | |
7947 | * more careful with calling the relevant encoder->mode_set functions. | |
7948 | */ | |
e2e1ed41 DV |
7949 | if (*prepare_pipes) |
7950 | *modeset_pipes = *prepare_pipes; | |
7951 | ||
7952 | /* ... and mask these out. */ | |
7953 | *modeset_pipes &= ~(*disable_pipes); | |
7954 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
7955 | |
7956 | /* | |
7957 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
7958 | * obies this rule, but the modeset restore mode of | |
7959 | * intel_modeset_setup_hw_state does not. | |
7960 | */ | |
7961 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
7962 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
7963 | |
7964 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
7965 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 7966 | } |
79e53945 | 7967 | |
ea9d758d | 7968 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 7969 | { |
ea9d758d | 7970 | struct drm_encoder *encoder; |
f6e5b160 | 7971 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 7972 | |
ea9d758d DV |
7973 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
7974 | if (encoder->crtc == crtc) | |
7975 | return true; | |
7976 | ||
7977 | return false; | |
7978 | } | |
7979 | ||
7980 | static void | |
7981 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
7982 | { | |
7983 | struct intel_encoder *intel_encoder; | |
7984 | struct intel_crtc *intel_crtc; | |
7985 | struct drm_connector *connector; | |
7986 | ||
7987 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
7988 | base.head) { | |
7989 | if (!intel_encoder->base.crtc) | |
7990 | continue; | |
7991 | ||
7992 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
7993 | ||
7994 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
7995 | intel_encoder->connectors_active = false; | |
7996 | } | |
7997 | ||
7998 | intel_modeset_commit_output_state(dev); | |
7999 | ||
8000 | /* Update computed state. */ | |
8001 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8002 | base.head) { | |
8003 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
8004 | } | |
8005 | ||
8006 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
8007 | if (!connector->encoder || !connector->encoder->crtc) | |
8008 | continue; | |
8009 | ||
8010 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
8011 | ||
8012 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
8013 | struct drm_property *dpms_property = |
8014 | dev->mode_config.dpms_property; | |
8015 | ||
ea9d758d | 8016 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 8017 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
8018 | dpms_property, |
8019 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
8020 | |
8021 | intel_encoder = to_intel_encoder(connector->encoder); | |
8022 | intel_encoder->connectors_active = true; | |
8023 | } | |
8024 | } | |
8025 | ||
8026 | } | |
8027 | ||
25c5b266 DV |
8028 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8029 | list_for_each_entry((intel_crtc), \ | |
8030 | &(dev)->mode_config.crtc_list, \ | |
8031 | base.head) \ | |
0973f18f | 8032 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 8033 | |
0e8ffe1b DV |
8034 | static bool |
8035 | intel_pipe_config_compare(struct intel_crtc_config *current_config, | |
8036 | struct intel_crtc_config *pipe_config) | |
8037 | { | |
08a24034 DV |
8038 | #define PIPE_CONF_CHECK_I(name) \ |
8039 | if (current_config->name != pipe_config->name) { \ | |
8040 | DRM_ERROR("mismatch in " #name " " \ | |
8041 | "(expected %i, found %i)\n", \ | |
8042 | current_config->name, \ | |
8043 | pipe_config->name); \ | |
8044 | return false; \ | |
88adfff1 DV |
8045 | } |
8046 | ||
1bd1bd80 DV |
8047 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8048 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
8049 | DRM_ERROR("mismatch in " #name " " \ | |
8050 | "(expected %i, found %i)\n", \ | |
8051 | current_config->name & (mask), \ | |
8052 | pipe_config->name & (mask)); \ | |
8053 | return false; \ | |
8054 | } | |
8055 | ||
08a24034 DV |
8056 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8057 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
8058 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8059 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
8060 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
8061 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
8062 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 8063 | |
1bd1bd80 DV |
8064 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8065 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
8066 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
8067 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
8068 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
8069 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
8070 | ||
8071 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
8072 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
8073 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
8074 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
8075 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
8076 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
8077 | ||
8078 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8079 | DRM_MODE_FLAG_INTERLACE); | |
8080 | ||
8081 | PIPE_CONF_CHECK_I(requested_mode.hdisplay); | |
8082 | PIPE_CONF_CHECK_I(requested_mode.vdisplay); | |
8083 | ||
08a24034 | 8084 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 8085 | #undef PIPE_CONF_CHECK_FLAGS |
627eb5a3 | 8086 | |
0e8ffe1b DV |
8087 | return true; |
8088 | } | |
8089 | ||
b980514c | 8090 | void |
8af6cf88 DV |
8091 | intel_modeset_check_state(struct drm_device *dev) |
8092 | { | |
0e8ffe1b | 8093 | drm_i915_private_t *dev_priv = dev->dev_private; |
8af6cf88 DV |
8094 | struct intel_crtc *crtc; |
8095 | struct intel_encoder *encoder; | |
8096 | struct intel_connector *connector; | |
0e8ffe1b | 8097 | struct intel_crtc_config pipe_config; |
8af6cf88 DV |
8098 | |
8099 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8100 | base.head) { | |
8101 | /* This also checks the encoder/connector hw state with the | |
8102 | * ->get_hw_state callbacks. */ | |
8103 | intel_connector_check_state(connector); | |
8104 | ||
8105 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
8106 | "connector's staged encoder doesn't match current encoder\n"); | |
8107 | } | |
8108 | ||
8109 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8110 | base.head) { | |
8111 | bool enabled = false; | |
8112 | bool active = false; | |
8113 | enum pipe pipe, tracked_pipe; | |
8114 | ||
8115 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
8116 | encoder->base.base.id, | |
8117 | drm_get_encoder_name(&encoder->base)); | |
8118 | ||
8119 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
8120 | "encoder's stage crtc doesn't match current crtc\n"); | |
8121 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
8122 | "encoder's active_connectors set, but no crtc\n"); | |
8123 | ||
8124 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8125 | base.head) { | |
8126 | if (connector->base.encoder != &encoder->base) | |
8127 | continue; | |
8128 | enabled = true; | |
8129 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
8130 | active = true; | |
8131 | } | |
8132 | WARN(!!encoder->base.crtc != enabled, | |
8133 | "encoder's enabled state mismatch " | |
8134 | "(expected %i, found %i)\n", | |
8135 | !!encoder->base.crtc, enabled); | |
8136 | WARN(active && !encoder->base.crtc, | |
8137 | "active encoder with no crtc\n"); | |
8138 | ||
8139 | WARN(encoder->connectors_active != active, | |
8140 | "encoder's computed active state doesn't match tracked active state " | |
8141 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
8142 | ||
8143 | active = encoder->get_hw_state(encoder, &pipe); | |
8144 | WARN(active != encoder->connectors_active, | |
8145 | "encoder's hw state doesn't match sw tracking " | |
8146 | "(expected %i, found %i)\n", | |
8147 | encoder->connectors_active, active); | |
8148 | ||
8149 | if (!encoder->base.crtc) | |
8150 | continue; | |
8151 | ||
8152 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
8153 | WARN(active && pipe != tracked_pipe, | |
8154 | "active encoder's pipe doesn't match" | |
8155 | "(expected %i, found %i)\n", | |
8156 | tracked_pipe, pipe); | |
8157 | ||
8158 | } | |
8159 | ||
8160 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8161 | base.head) { | |
8162 | bool enabled = false; | |
8163 | bool active = false; | |
8164 | ||
8165 | DRM_DEBUG_KMS("[CRTC:%d]\n", | |
8166 | crtc->base.base.id); | |
8167 | ||
8168 | WARN(crtc->active && !crtc->base.enabled, | |
8169 | "active crtc, but not enabled in sw tracking\n"); | |
8170 | ||
8171 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8172 | base.head) { | |
8173 | if (encoder->base.crtc != &crtc->base) | |
8174 | continue; | |
8175 | enabled = true; | |
8176 | if (encoder->connectors_active) | |
8177 | active = true; | |
8178 | } | |
8179 | WARN(active != crtc->active, | |
8180 | "crtc's computed active state doesn't match tracked active state " | |
8181 | "(expected %i, found %i)\n", active, crtc->active); | |
8182 | WARN(enabled != crtc->base.enabled, | |
8183 | "crtc's computed enabled state doesn't match tracked enabled state " | |
8184 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
8185 | ||
88adfff1 | 8186 | memset(&pipe_config, 0, sizeof(pipe_config)); |
60c4ae10 | 8187 | pipe_config.cpu_transcoder = crtc->config.cpu_transcoder; |
0e8ffe1b DV |
8188 | active = dev_priv->display.get_pipe_config(crtc, |
8189 | &pipe_config); | |
8190 | WARN(crtc->active != active, | |
8191 | "crtc active state doesn't match with hw state " | |
8192 | "(expected %i, found %i)\n", crtc->active, active); | |
8193 | ||
8194 | WARN(active && | |
8195 | !intel_pipe_config_compare(&crtc->config, &pipe_config), | |
8196 | "pipe state doesn't match!\n"); | |
8af6cf88 DV |
8197 | } |
8198 | } | |
8199 | ||
f30da187 DV |
8200 | static int __intel_set_mode(struct drm_crtc *crtc, |
8201 | struct drm_display_mode *mode, | |
8202 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
8203 | { |
8204 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 8205 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
8206 | struct drm_display_mode *saved_mode, *saved_hwmode; |
8207 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
8208 | struct intel_crtc *intel_crtc; |
8209 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 8210 | int ret = 0; |
a6778b3c | 8211 | |
3ac18232 | 8212 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
8213 | if (!saved_mode) |
8214 | return -ENOMEM; | |
3ac18232 | 8215 | saved_hwmode = saved_mode + 1; |
a6778b3c | 8216 | |
e2e1ed41 | 8217 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
8218 | &prepare_pipes, &disable_pipes); |
8219 | ||
3ac18232 TG |
8220 | *saved_hwmode = crtc->hwmode; |
8221 | *saved_mode = crtc->mode; | |
a6778b3c | 8222 | |
25c5b266 DV |
8223 | /* Hack: Because we don't (yet) support global modeset on multiple |
8224 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
8225 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
8226 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
8227 | * changing their mode at the same time. */ | |
25c5b266 | 8228 | if (modeset_pipes) { |
4e53c2e0 | 8229 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
8230 | if (IS_ERR(pipe_config)) { |
8231 | ret = PTR_ERR(pipe_config); | |
8232 | pipe_config = NULL; | |
8233 | ||
3ac18232 | 8234 | goto out; |
25c5b266 | 8235 | } |
25c5b266 | 8236 | } |
a6778b3c | 8237 | |
460da916 DV |
8238 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
8239 | intel_crtc_disable(&intel_crtc->base); | |
8240 | ||
ea9d758d DV |
8241 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
8242 | if (intel_crtc->base.enabled) | |
8243 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
8244 | } | |
a6778b3c | 8245 | |
6c4c86f5 DV |
8246 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
8247 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 8248 | */ |
b8cecdf5 | 8249 | if (modeset_pipes) { |
3b117c8f | 8250 | enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder; |
25c5b266 | 8251 | crtc->mode = *mode; |
b8cecdf5 DV |
8252 | /* mode_set/enable/disable functions rely on a correct pipe |
8253 | * config. */ | |
8254 | to_intel_crtc(crtc)->config = *pipe_config; | |
3b117c8f | 8255 | to_intel_crtc(crtc)->config.cpu_transcoder = tmp; |
b8cecdf5 | 8256 | } |
7758a113 | 8257 | |
ea9d758d DV |
8258 | /* Only after disabling all output pipelines that will be changed can we |
8259 | * update the the output configuration. */ | |
8260 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 8261 | |
47fab737 DV |
8262 | if (dev_priv->display.modeset_global_resources) |
8263 | dev_priv->display.modeset_global_resources(dev); | |
8264 | ||
a6778b3c DV |
8265 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
8266 | * on the DPLL. | |
f6e5b160 | 8267 | */ |
25c5b266 | 8268 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 8269 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
8270 | x, y, fb); |
8271 | if (ret) | |
8272 | goto done; | |
a6778b3c DV |
8273 | } |
8274 | ||
8275 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
8276 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
8277 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 8278 | |
25c5b266 DV |
8279 | if (modeset_pipes) { |
8280 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 8281 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 8282 | |
25c5b266 DV |
8283 | /* Calculate and store various constants which |
8284 | * are later needed by vblank and swap-completion | |
8285 | * timestamping. They are derived from true hwmode. | |
8286 | */ | |
8287 | drm_calc_timestamping_constants(crtc); | |
8288 | } | |
a6778b3c DV |
8289 | |
8290 | /* FIXME: add subpixel order */ | |
8291 | done: | |
c0c36b94 | 8292 | if (ret && crtc->enabled) { |
3ac18232 TG |
8293 | crtc->hwmode = *saved_hwmode; |
8294 | crtc->mode = *saved_mode; | |
a6778b3c DV |
8295 | } |
8296 | ||
3ac18232 | 8297 | out: |
b8cecdf5 | 8298 | kfree(pipe_config); |
3ac18232 | 8299 | kfree(saved_mode); |
a6778b3c | 8300 | return ret; |
f6e5b160 CW |
8301 | } |
8302 | ||
f30da187 DV |
8303 | int intel_set_mode(struct drm_crtc *crtc, |
8304 | struct drm_display_mode *mode, | |
8305 | int x, int y, struct drm_framebuffer *fb) | |
8306 | { | |
8307 | int ret; | |
8308 | ||
8309 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
8310 | ||
8311 | if (ret == 0) | |
8312 | intel_modeset_check_state(crtc->dev); | |
8313 | ||
8314 | return ret; | |
8315 | } | |
8316 | ||
c0c36b94 CW |
8317 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
8318 | { | |
8319 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
8320 | } | |
8321 | ||
25c5b266 DV |
8322 | #undef for_each_intel_crtc_masked |
8323 | ||
d9e55608 DV |
8324 | static void intel_set_config_free(struct intel_set_config *config) |
8325 | { | |
8326 | if (!config) | |
8327 | return; | |
8328 | ||
1aa4b628 DV |
8329 | kfree(config->save_connector_encoders); |
8330 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
8331 | kfree(config); |
8332 | } | |
8333 | ||
85f9eb71 DV |
8334 | static int intel_set_config_save_state(struct drm_device *dev, |
8335 | struct intel_set_config *config) | |
8336 | { | |
85f9eb71 DV |
8337 | struct drm_encoder *encoder; |
8338 | struct drm_connector *connector; | |
8339 | int count; | |
8340 | ||
1aa4b628 DV |
8341 | config->save_encoder_crtcs = |
8342 | kcalloc(dev->mode_config.num_encoder, | |
8343 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
8344 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
8345 | return -ENOMEM; |
8346 | ||
1aa4b628 DV |
8347 | config->save_connector_encoders = |
8348 | kcalloc(dev->mode_config.num_connector, | |
8349 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
8350 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
8351 | return -ENOMEM; |
8352 | ||
8353 | /* Copy data. Note that driver private data is not affected. | |
8354 | * Should anything bad happen only the expected state is | |
8355 | * restored, not the drivers personal bookkeeping. | |
8356 | */ | |
85f9eb71 DV |
8357 | count = 0; |
8358 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 8359 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
8360 | } |
8361 | ||
8362 | count = 0; | |
8363 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 8364 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
8365 | } |
8366 | ||
8367 | return 0; | |
8368 | } | |
8369 | ||
8370 | static void intel_set_config_restore_state(struct drm_device *dev, | |
8371 | struct intel_set_config *config) | |
8372 | { | |
9a935856 DV |
8373 | struct intel_encoder *encoder; |
8374 | struct intel_connector *connector; | |
85f9eb71 DV |
8375 | int count; |
8376 | ||
85f9eb71 | 8377 | count = 0; |
9a935856 DV |
8378 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8379 | encoder->new_crtc = | |
8380 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
8381 | } |
8382 | ||
8383 | count = 0; | |
9a935856 DV |
8384 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
8385 | connector->new_encoder = | |
8386 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
8387 | } |
8388 | } | |
8389 | ||
5e2b584e DV |
8390 | static void |
8391 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
8392 | struct intel_set_config *config) | |
8393 | { | |
8394 | ||
8395 | /* We should be able to check here if the fb has the same properties | |
8396 | * and then just flip_or_move it */ | |
8397 | if (set->crtc->fb != set->fb) { | |
8398 | /* If we have no fb then treat it as a full mode set */ | |
8399 | if (set->crtc->fb == NULL) { | |
8400 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); | |
8401 | config->mode_changed = true; | |
8402 | } else if (set->fb == NULL) { | |
8403 | config->mode_changed = true; | |
72f4901e DV |
8404 | } else if (set->fb->pixel_format != |
8405 | set->crtc->fb->pixel_format) { | |
5e2b584e DV |
8406 | config->mode_changed = true; |
8407 | } else | |
8408 | config->fb_changed = true; | |
8409 | } | |
8410 | ||
835c5873 | 8411 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
8412 | config->fb_changed = true; |
8413 | ||
8414 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
8415 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
8416 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
8417 | drm_mode_debug_printmodeline(set->mode); | |
8418 | config->mode_changed = true; | |
8419 | } | |
8420 | } | |
8421 | ||
2e431051 | 8422 | static int |
9a935856 DV |
8423 | intel_modeset_stage_output_state(struct drm_device *dev, |
8424 | struct drm_mode_set *set, | |
8425 | struct intel_set_config *config) | |
50f56119 | 8426 | { |
85f9eb71 | 8427 | struct drm_crtc *new_crtc; |
9a935856 DV |
8428 | struct intel_connector *connector; |
8429 | struct intel_encoder *encoder; | |
2e431051 | 8430 | int count, ro; |
50f56119 | 8431 | |
9abdda74 | 8432 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
8433 | * of connectors. For paranoia, double-check this. */ |
8434 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
8435 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
8436 | ||
50f56119 | 8437 | count = 0; |
9a935856 DV |
8438 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8439 | base.head) { | |
8440 | /* Otherwise traverse passed in connector list and get encoders | |
8441 | * for them. */ | |
50f56119 | 8442 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
8443 | if (set->connectors[ro] == &connector->base) { |
8444 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
8445 | break; |
8446 | } | |
8447 | } | |
8448 | ||
9a935856 DV |
8449 | /* If we disable the crtc, disable all its connectors. Also, if |
8450 | * the connector is on the changing crtc but not on the new | |
8451 | * connector list, disable it. */ | |
8452 | if ((!set->fb || ro == set->num_connectors) && | |
8453 | connector->base.encoder && | |
8454 | connector->base.encoder->crtc == set->crtc) { | |
8455 | connector->new_encoder = NULL; | |
8456 | ||
8457 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
8458 | connector->base.base.id, | |
8459 | drm_get_connector_name(&connector->base)); | |
8460 | } | |
8461 | ||
8462 | ||
8463 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 8464 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 8465 | config->mode_changed = true; |
50f56119 DV |
8466 | } |
8467 | } | |
9a935856 | 8468 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 8469 | |
9a935856 | 8470 | /* Update crtc of enabled connectors. */ |
50f56119 | 8471 | count = 0; |
9a935856 DV |
8472 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8473 | base.head) { | |
8474 | if (!connector->new_encoder) | |
50f56119 DV |
8475 | continue; |
8476 | ||
9a935856 | 8477 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
8478 | |
8479 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 8480 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
8481 | new_crtc = set->crtc; |
8482 | } | |
8483 | ||
8484 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
8485 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
8486 | new_crtc)) { | |
5e2b584e | 8487 | return -EINVAL; |
50f56119 | 8488 | } |
9a935856 DV |
8489 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
8490 | ||
8491 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
8492 | connector->base.base.id, | |
8493 | drm_get_connector_name(&connector->base), | |
8494 | new_crtc->base.id); | |
8495 | } | |
8496 | ||
8497 | /* Check for any encoders that needs to be disabled. */ | |
8498 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8499 | base.head) { | |
8500 | list_for_each_entry(connector, | |
8501 | &dev->mode_config.connector_list, | |
8502 | base.head) { | |
8503 | if (connector->new_encoder == encoder) { | |
8504 | WARN_ON(!connector->new_encoder->new_crtc); | |
8505 | ||
8506 | goto next_encoder; | |
8507 | } | |
8508 | } | |
8509 | encoder->new_crtc = NULL; | |
8510 | next_encoder: | |
8511 | /* Only now check for crtc changes so we don't miss encoders | |
8512 | * that will be disabled. */ | |
8513 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 8514 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 8515 | config->mode_changed = true; |
50f56119 DV |
8516 | } |
8517 | } | |
9a935856 | 8518 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 8519 | |
2e431051 DV |
8520 | return 0; |
8521 | } | |
8522 | ||
8523 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
8524 | { | |
8525 | struct drm_device *dev; | |
2e431051 DV |
8526 | struct drm_mode_set save_set; |
8527 | struct intel_set_config *config; | |
8528 | int ret; | |
2e431051 | 8529 | |
8d3e375e DV |
8530 | BUG_ON(!set); |
8531 | BUG_ON(!set->crtc); | |
8532 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 8533 | |
7e53f3a4 DV |
8534 | /* Enforce sane interface api - has been abused by the fb helper. */ |
8535 | BUG_ON(!set->mode && set->fb); | |
8536 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 8537 | |
2e431051 DV |
8538 | if (set->fb) { |
8539 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
8540 | set->crtc->base.id, set->fb->base.id, | |
8541 | (int)set->num_connectors, set->x, set->y); | |
8542 | } else { | |
8543 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
8544 | } |
8545 | ||
8546 | dev = set->crtc->dev; | |
8547 | ||
8548 | ret = -ENOMEM; | |
8549 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
8550 | if (!config) | |
8551 | goto out_config; | |
8552 | ||
8553 | ret = intel_set_config_save_state(dev, config); | |
8554 | if (ret) | |
8555 | goto out_config; | |
8556 | ||
8557 | save_set.crtc = set->crtc; | |
8558 | save_set.mode = &set->crtc->mode; | |
8559 | save_set.x = set->crtc->x; | |
8560 | save_set.y = set->crtc->y; | |
8561 | save_set.fb = set->crtc->fb; | |
8562 | ||
8563 | /* Compute whether we need a full modeset, only an fb base update or no | |
8564 | * change at all. In the future we might also check whether only the | |
8565 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
8566 | * such cases. */ | |
8567 | intel_set_config_compute_mode_changes(set, config); | |
8568 | ||
9a935856 | 8569 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
8570 | if (ret) |
8571 | goto fail; | |
8572 | ||
5e2b584e | 8573 | if (config->mode_changed) { |
87f1faa6 | 8574 | if (set->mode) { |
50f56119 DV |
8575 | DRM_DEBUG_KMS("attempting to set mode from" |
8576 | " userspace\n"); | |
8577 | drm_mode_debug_printmodeline(set->mode); | |
87f1faa6 DV |
8578 | } |
8579 | ||
c0c36b94 CW |
8580 | ret = intel_set_mode(set->crtc, set->mode, |
8581 | set->x, set->y, set->fb); | |
8582 | if (ret) { | |
8583 | DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", | |
8584 | set->crtc->base.id, ret); | |
87f1faa6 DV |
8585 | goto fail; |
8586 | } | |
5e2b584e | 8587 | } else if (config->fb_changed) { |
4878cae2 VS |
8588 | intel_crtc_wait_for_pending_flips(set->crtc); |
8589 | ||
4f660f49 | 8590 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 8591 | set->x, set->y, set->fb); |
50f56119 DV |
8592 | } |
8593 | ||
d9e55608 DV |
8594 | intel_set_config_free(config); |
8595 | ||
50f56119 DV |
8596 | return 0; |
8597 | ||
8598 | fail: | |
85f9eb71 | 8599 | intel_set_config_restore_state(dev, config); |
50f56119 DV |
8600 | |
8601 | /* Try to restore the config */ | |
5e2b584e | 8602 | if (config->mode_changed && |
c0c36b94 CW |
8603 | intel_set_mode(save_set.crtc, save_set.mode, |
8604 | save_set.x, save_set.y, save_set.fb)) | |
50f56119 DV |
8605 | DRM_ERROR("failed to restore config after modeset failure\n"); |
8606 | ||
d9e55608 DV |
8607 | out_config: |
8608 | intel_set_config_free(config); | |
50f56119 DV |
8609 | return ret; |
8610 | } | |
f6e5b160 CW |
8611 | |
8612 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
8613 | .cursor_set = intel_crtc_cursor_set, |
8614 | .cursor_move = intel_crtc_cursor_move, | |
8615 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 8616 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
8617 | .destroy = intel_crtc_destroy, |
8618 | .page_flip = intel_crtc_page_flip, | |
8619 | }; | |
8620 | ||
79f689aa PZ |
8621 | static void intel_cpu_pll_init(struct drm_device *dev) |
8622 | { | |
affa9354 | 8623 | if (HAS_DDI(dev)) |
79f689aa PZ |
8624 | intel_ddi_pll_init(dev); |
8625 | } | |
8626 | ||
ee7b9f93 JB |
8627 | static void intel_pch_pll_init(struct drm_device *dev) |
8628 | { | |
8629 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8630 | int i; | |
8631 | ||
8632 | if (dev_priv->num_pch_pll == 0) { | |
8633 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
8634 | return; | |
8635 | } | |
8636 | ||
8637 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
8638 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
8639 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
8640 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
8641 | } | |
8642 | } | |
8643 | ||
b358d0a6 | 8644 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 8645 | { |
22fd0fab | 8646 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
8647 | struct intel_crtc *intel_crtc; |
8648 | int i; | |
8649 | ||
8650 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
8651 | if (intel_crtc == NULL) | |
8652 | return; | |
8653 | ||
8654 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
8655 | ||
8656 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
8657 | for (i = 0; i < 256; i++) { |
8658 | intel_crtc->lut_r[i] = i; | |
8659 | intel_crtc->lut_g[i] = i; | |
8660 | intel_crtc->lut_b[i] = i; | |
8661 | } | |
8662 | ||
80824003 JB |
8663 | /* Swap pipes & planes for FBC on pre-965 */ |
8664 | intel_crtc->pipe = pipe; | |
8665 | intel_crtc->plane = pipe; | |
3b117c8f | 8666 | intel_crtc->config.cpu_transcoder = pipe; |
e2e767ab | 8667 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 8668 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 8669 | intel_crtc->plane = !pipe; |
80824003 JB |
8670 | } |
8671 | ||
22fd0fab JB |
8672 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
8673 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
8674 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
8675 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
8676 | ||
79e53945 | 8677 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
8678 | } |
8679 | ||
08d7b3d1 | 8680 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 8681 | struct drm_file *file) |
08d7b3d1 | 8682 | { |
08d7b3d1 | 8683 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
8684 | struct drm_mode_object *drmmode_obj; |
8685 | struct intel_crtc *crtc; | |
08d7b3d1 | 8686 | |
1cff8f6b DV |
8687 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
8688 | return -ENODEV; | |
08d7b3d1 | 8689 | |
c05422d5 DV |
8690 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
8691 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 8692 | |
c05422d5 | 8693 | if (!drmmode_obj) { |
08d7b3d1 CW |
8694 | DRM_ERROR("no such CRTC id\n"); |
8695 | return -EINVAL; | |
8696 | } | |
8697 | ||
c05422d5 DV |
8698 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
8699 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 8700 | |
c05422d5 | 8701 | return 0; |
08d7b3d1 CW |
8702 | } |
8703 | ||
66a9278e | 8704 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 8705 | { |
66a9278e DV |
8706 | struct drm_device *dev = encoder->base.dev; |
8707 | struct intel_encoder *source_encoder; | |
79e53945 | 8708 | int index_mask = 0; |
79e53945 JB |
8709 | int entry = 0; |
8710 | ||
66a9278e DV |
8711 | list_for_each_entry(source_encoder, |
8712 | &dev->mode_config.encoder_list, base.head) { | |
8713 | ||
8714 | if (encoder == source_encoder) | |
79e53945 | 8715 | index_mask |= (1 << entry); |
66a9278e DV |
8716 | |
8717 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
8718 | if (encoder->cloneable && source_encoder->cloneable) | |
8719 | index_mask |= (1 << entry); | |
8720 | ||
79e53945 JB |
8721 | entry++; |
8722 | } | |
4ef69c7a | 8723 | |
79e53945 JB |
8724 | return index_mask; |
8725 | } | |
8726 | ||
4d302442 CW |
8727 | static bool has_edp_a(struct drm_device *dev) |
8728 | { | |
8729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8730 | ||
8731 | if (!IS_MOBILE(dev)) | |
8732 | return false; | |
8733 | ||
8734 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
8735 | return false; | |
8736 | ||
8737 | if (IS_GEN5(dev) && | |
8738 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
8739 | return false; | |
8740 | ||
8741 | return true; | |
8742 | } | |
8743 | ||
79e53945 JB |
8744 | static void intel_setup_outputs(struct drm_device *dev) |
8745 | { | |
725e30ad | 8746 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 8747 | struct intel_encoder *encoder; |
cb0953d7 | 8748 | bool dpd_is_edp = false; |
f3cfcba6 | 8749 | bool has_lvds; |
79e53945 | 8750 | |
f3cfcba6 | 8751 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
8752 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
8753 | /* disable the panel fitter on everything but LVDS */ | |
8754 | I915_WRITE(PFIT_CONTROL, 0); | |
8755 | } | |
79e53945 | 8756 | |
c40c0f5b | 8757 | if (!IS_ULT(dev)) |
79935fca | 8758 | intel_crt_init(dev); |
cb0953d7 | 8759 | |
affa9354 | 8760 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
8761 | int found; |
8762 | ||
8763 | /* Haswell uses DDI functions to detect digital outputs */ | |
8764 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
8765 | /* DDI A only supports eDP */ | |
8766 | if (found) | |
8767 | intel_ddi_init(dev, PORT_A); | |
8768 | ||
8769 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
8770 | * register */ | |
8771 | found = I915_READ(SFUSE_STRAP); | |
8772 | ||
8773 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
8774 | intel_ddi_init(dev, PORT_B); | |
8775 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
8776 | intel_ddi_init(dev, PORT_C); | |
8777 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
8778 | intel_ddi_init(dev, PORT_D); | |
8779 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 8780 | int found; |
270b3042 DV |
8781 | dpd_is_edp = intel_dpd_is_edp(dev); |
8782 | ||
8783 | if (has_edp_a(dev)) | |
8784 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 8785 | |
dc0fa718 | 8786 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 8787 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 8788 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 8789 | if (!found) |
e2debe91 | 8790 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 8791 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 8792 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
8793 | } |
8794 | ||
dc0fa718 | 8795 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 8796 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 8797 | |
dc0fa718 | 8798 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 8799 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 8800 | |
5eb08b69 | 8801 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 8802 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 8803 | |
270b3042 | 8804 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 8805 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 8806 | } else if (IS_VALLEYVIEW(dev)) { |
19c03924 | 8807 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
67cfc203 VS |
8808 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
8809 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 8810 | |
dc0fa718 | 8811 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
e2debe91 PZ |
8812 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
8813 | PORT_B); | |
67cfc203 VS |
8814 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
8815 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
4a87d65d | 8816 | } |
103a196f | 8817 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 8818 | bool found = false; |
7d57382e | 8819 | |
e2debe91 | 8820 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8821 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 8822 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
8823 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
8824 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 8825 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 8826 | } |
27185ae1 | 8827 | |
b01f2c3a JB |
8828 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
8829 | DRM_DEBUG_KMS("probing DP_B\n"); | |
ab9d7c30 | 8830 | intel_dp_init(dev, DP_B, PORT_B); |
b01f2c3a | 8831 | } |
725e30ad | 8832 | } |
13520b05 KH |
8833 | |
8834 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 8835 | |
e2debe91 | 8836 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8837 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 8838 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 8839 | } |
27185ae1 | 8840 | |
e2debe91 | 8841 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 8842 | |
b01f2c3a JB |
8843 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
8844 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 8845 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a JB |
8846 | } |
8847 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
8848 | DRM_DEBUG_KMS("probing DP_C\n"); | |
ab9d7c30 | 8849 | intel_dp_init(dev, DP_C, PORT_C); |
b01f2c3a | 8850 | } |
725e30ad | 8851 | } |
27185ae1 | 8852 | |
b01f2c3a JB |
8853 | if (SUPPORTS_INTEGRATED_DP(dev) && |
8854 | (I915_READ(DP_D) & DP_DETECTED)) { | |
8855 | DRM_DEBUG_KMS("probing DP_D\n"); | |
ab9d7c30 | 8856 | intel_dp_init(dev, DP_D, PORT_D); |
b01f2c3a | 8857 | } |
bad720ff | 8858 | } else if (IS_GEN2(dev)) |
79e53945 JB |
8859 | intel_dvo_init(dev); |
8860 | ||
103a196f | 8861 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
8862 | intel_tv_init(dev); |
8863 | ||
4ef69c7a CW |
8864 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8865 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
8866 | encoder->base.possible_clones = | |
66a9278e | 8867 | intel_encoder_clones(encoder); |
79e53945 | 8868 | } |
47356eb6 | 8869 | |
dde86e2d | 8870 | intel_init_pch_refclk(dev); |
270b3042 DV |
8871 | |
8872 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
8873 | } |
8874 | ||
8875 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
8876 | { | |
8877 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
8878 | |
8879 | drm_framebuffer_cleanup(fb); | |
05394f39 | 8880 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
8881 | |
8882 | kfree(intel_fb); | |
8883 | } | |
8884 | ||
8885 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 8886 | struct drm_file *file, |
79e53945 JB |
8887 | unsigned int *handle) |
8888 | { | |
8889 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 8890 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 8891 | |
05394f39 | 8892 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
8893 | } |
8894 | ||
8895 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
8896 | .destroy = intel_user_framebuffer_destroy, | |
8897 | .create_handle = intel_user_framebuffer_create_handle, | |
8898 | }; | |
8899 | ||
38651674 DA |
8900 | int intel_framebuffer_init(struct drm_device *dev, |
8901 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 8902 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 8903 | struct drm_i915_gem_object *obj) |
79e53945 | 8904 | { |
79e53945 JB |
8905 | int ret; |
8906 | ||
c16ed4be CW |
8907 | if (obj->tiling_mode == I915_TILING_Y) { |
8908 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 8909 | return -EINVAL; |
c16ed4be | 8910 | } |
57cd6508 | 8911 | |
c16ed4be CW |
8912 | if (mode_cmd->pitches[0] & 63) { |
8913 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
8914 | mode_cmd->pitches[0]); | |
57cd6508 | 8915 | return -EINVAL; |
c16ed4be | 8916 | } |
57cd6508 | 8917 | |
5d7bd705 | 8918 | /* FIXME <= Gen4 stride limits are bit unclear */ |
c16ed4be CW |
8919 | if (mode_cmd->pitches[0] > 32768) { |
8920 | DRM_DEBUG("pitch (%d) must be at less than 32768\n", | |
8921 | mode_cmd->pitches[0]); | |
5d7bd705 | 8922 | return -EINVAL; |
c16ed4be | 8923 | } |
5d7bd705 VS |
8924 | |
8925 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
8926 | mode_cmd->pitches[0] != obj->stride) { |
8927 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
8928 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 8929 | return -EINVAL; |
c16ed4be | 8930 | } |
5d7bd705 | 8931 | |
57779d06 | 8932 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 8933 | switch (mode_cmd->pixel_format) { |
57779d06 | 8934 | case DRM_FORMAT_C8: |
04b3924d VS |
8935 | case DRM_FORMAT_RGB565: |
8936 | case DRM_FORMAT_XRGB8888: | |
8937 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
8938 | break; |
8939 | case DRM_FORMAT_XRGB1555: | |
8940 | case DRM_FORMAT_ARGB1555: | |
c16ed4be CW |
8941 | if (INTEL_INFO(dev)->gen > 3) { |
8942 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8943 | return -EINVAL; |
c16ed4be | 8944 | } |
57779d06 VS |
8945 | break; |
8946 | case DRM_FORMAT_XBGR8888: | |
8947 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
8948 | case DRM_FORMAT_XRGB2101010: |
8949 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
8950 | case DRM_FORMAT_XBGR2101010: |
8951 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be CW |
8952 | if (INTEL_INFO(dev)->gen < 4) { |
8953 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8954 | return -EINVAL; |
c16ed4be | 8955 | } |
b5626747 | 8956 | break; |
04b3924d VS |
8957 | case DRM_FORMAT_YUYV: |
8958 | case DRM_FORMAT_UYVY: | |
8959 | case DRM_FORMAT_YVYU: | |
8960 | case DRM_FORMAT_VYUY: | |
c16ed4be CW |
8961 | if (INTEL_INFO(dev)->gen < 5) { |
8962 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8963 | return -EINVAL; |
c16ed4be | 8964 | } |
57cd6508 CW |
8965 | break; |
8966 | default: | |
c16ed4be | 8967 | DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); |
57cd6508 CW |
8968 | return -EINVAL; |
8969 | } | |
8970 | ||
90f9a336 VS |
8971 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
8972 | if (mode_cmd->offsets[0] != 0) | |
8973 | return -EINVAL; | |
8974 | ||
c7d73f6a DV |
8975 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
8976 | intel_fb->obj = obj; | |
8977 | ||
79e53945 JB |
8978 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
8979 | if (ret) { | |
8980 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
8981 | return ret; | |
8982 | } | |
8983 | ||
79e53945 JB |
8984 | return 0; |
8985 | } | |
8986 | ||
79e53945 JB |
8987 | static struct drm_framebuffer * |
8988 | intel_user_framebuffer_create(struct drm_device *dev, | |
8989 | struct drm_file *filp, | |
308e5bcb | 8990 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 8991 | { |
05394f39 | 8992 | struct drm_i915_gem_object *obj; |
79e53945 | 8993 | |
308e5bcb JB |
8994 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
8995 | mode_cmd->handles[0])); | |
c8725226 | 8996 | if (&obj->base == NULL) |
cce13ff7 | 8997 | return ERR_PTR(-ENOENT); |
79e53945 | 8998 | |
d2dff872 | 8999 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
9000 | } |
9001 | ||
79e53945 | 9002 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 9003 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 9004 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
9005 | }; |
9006 | ||
e70236a8 JB |
9007 | /* Set up chip specific display functions */ |
9008 | static void intel_init_display(struct drm_device *dev) | |
9009 | { | |
9010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9011 | ||
affa9354 | 9012 | if (HAS_DDI(dev)) { |
0e8ffe1b | 9013 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 9014 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
9015 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9016 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 9017 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
9018 | dev_priv->display.update_plane = ironlake_update_plane; |
9019 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 9020 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 9021 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
9022 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9023 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 9024 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 9025 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
9026 | } else if (IS_VALLEYVIEW(dev)) { |
9027 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
9028 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
9029 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
9030 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
9031 | dev_priv->display.off = i9xx_crtc_off; | |
9032 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 9033 | } else { |
0e8ffe1b | 9034 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 9035 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
9036 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
9037 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 9038 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 9039 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 9040 | } |
e70236a8 | 9041 | |
e70236a8 | 9042 | /* Returns the core display clock speed */ |
25eb05fc JB |
9043 | if (IS_VALLEYVIEW(dev)) |
9044 | dev_priv->display.get_display_clock_speed = | |
9045 | valleyview_get_display_clock_speed; | |
9046 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
9047 | dev_priv->display.get_display_clock_speed = |
9048 | i945_get_display_clock_speed; | |
9049 | else if (IS_I915G(dev)) | |
9050 | dev_priv->display.get_display_clock_speed = | |
9051 | i915_get_display_clock_speed; | |
f2b115e6 | 9052 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
9053 | dev_priv->display.get_display_clock_speed = |
9054 | i9xx_misc_get_display_clock_speed; | |
9055 | else if (IS_I915GM(dev)) | |
9056 | dev_priv->display.get_display_clock_speed = | |
9057 | i915gm_get_display_clock_speed; | |
9058 | else if (IS_I865G(dev)) | |
9059 | dev_priv->display.get_display_clock_speed = | |
9060 | i865_get_display_clock_speed; | |
f0f8a9ce | 9061 | else if (IS_I85X(dev)) |
e70236a8 JB |
9062 | dev_priv->display.get_display_clock_speed = |
9063 | i855_get_display_clock_speed; | |
9064 | else /* 852, 830 */ | |
9065 | dev_priv->display.get_display_clock_speed = | |
9066 | i830_get_display_clock_speed; | |
9067 | ||
7f8a8569 | 9068 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 9069 | if (IS_GEN5(dev)) { |
674cf967 | 9070 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 9071 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 9072 | } else if (IS_GEN6(dev)) { |
674cf967 | 9073 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 9074 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
9075 | } else if (IS_IVYBRIDGE(dev)) { |
9076 | /* FIXME: detect B0+ stepping and use auto training */ | |
9077 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 9078 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
9079 | dev_priv->display.modeset_global_resources = |
9080 | ivb_modeset_global_resources; | |
c82e4d26 ED |
9081 | } else if (IS_HASWELL(dev)) { |
9082 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 9083 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
9084 | dev_priv->display.modeset_global_resources = |
9085 | haswell_modeset_global_resources; | |
a0e63c22 | 9086 | } |
6067aaea | 9087 | } else if (IS_G4X(dev)) { |
e0dac65e | 9088 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 9089 | } |
8c9f3aaf JB |
9090 | |
9091 | /* Default just returns -ENODEV to indicate unsupported */ | |
9092 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
9093 | ||
9094 | switch (INTEL_INFO(dev)->gen) { | |
9095 | case 2: | |
9096 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
9097 | break; | |
9098 | ||
9099 | case 3: | |
9100 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
9101 | break; | |
9102 | ||
9103 | case 4: | |
9104 | case 5: | |
9105 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
9106 | break; | |
9107 | ||
9108 | case 6: | |
9109 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
9110 | break; | |
7c9017e5 JB |
9111 | case 7: |
9112 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
9113 | break; | |
8c9f3aaf | 9114 | } |
e70236a8 JB |
9115 | } |
9116 | ||
b690e96c JB |
9117 | /* |
9118 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
9119 | * resume, or other times. This quirk makes sure that's the case for | |
9120 | * affected systems. | |
9121 | */ | |
0206e353 | 9122 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
9123 | { |
9124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9125 | ||
9126 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 9127 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
9128 | } |
9129 | ||
435793df KP |
9130 | /* |
9131 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
9132 | */ | |
9133 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
9134 | { | |
9135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9136 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 9137 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
9138 | } |
9139 | ||
4dca20ef | 9140 | /* |
5a15ab5b CE |
9141 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9142 | * brightness value | |
4dca20ef CE |
9143 | */ |
9144 | static void quirk_invert_brightness(struct drm_device *dev) | |
9145 | { | |
9146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9147 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 9148 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
9149 | } |
9150 | ||
b690e96c JB |
9151 | struct intel_quirk { |
9152 | int device; | |
9153 | int subsystem_vendor; | |
9154 | int subsystem_device; | |
9155 | void (*hook)(struct drm_device *dev); | |
9156 | }; | |
9157 | ||
5f85f176 EE |
9158 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
9159 | struct intel_dmi_quirk { | |
9160 | void (*hook)(struct drm_device *dev); | |
9161 | const struct dmi_system_id (*dmi_id_list)[]; | |
9162 | }; | |
9163 | ||
9164 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
9165 | { | |
9166 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
9167 | return 1; | |
9168 | } | |
9169 | ||
9170 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
9171 | { | |
9172 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
9173 | { | |
9174 | .callback = intel_dmi_reverse_brightness, | |
9175 | .ident = "NCR Corporation", | |
9176 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
9177 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
9178 | }, | |
9179 | }, | |
9180 | { } /* terminating entry */ | |
9181 | }, | |
9182 | .hook = quirk_invert_brightness, | |
9183 | }, | |
9184 | }; | |
9185 | ||
c43b5634 | 9186 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 9187 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 9188 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 9189 | |
b690e96c JB |
9190 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
9191 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
9192 | ||
b690e96c JB |
9193 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
9194 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
9195 | ||
ccd0d36e | 9196 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 9197 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 9198 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
9199 | |
9200 | /* Lenovo U160 cannot use SSC on LVDS */ | |
9201 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
9202 | |
9203 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
9204 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
9205 | |
9206 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
9207 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
1ffff603 JN |
9208 | |
9209 | /* Acer/eMachines G725 */ | |
9210 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
01e3a8fe JN |
9211 | |
9212 | /* Acer/eMachines e725 */ | |
9213 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
5559ecad JN |
9214 | |
9215 | /* Acer/Packard Bell NCL20 */ | |
9216 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
ac4199e0 DV |
9217 | |
9218 | /* Acer Aspire 4736Z */ | |
9219 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
b690e96c JB |
9220 | }; |
9221 | ||
9222 | static void intel_init_quirks(struct drm_device *dev) | |
9223 | { | |
9224 | struct pci_dev *d = dev->pdev; | |
9225 | int i; | |
9226 | ||
9227 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
9228 | struct intel_quirk *q = &intel_quirks[i]; | |
9229 | ||
9230 | if (d->device == q->device && | |
9231 | (d->subsystem_vendor == q->subsystem_vendor || | |
9232 | q->subsystem_vendor == PCI_ANY_ID) && | |
9233 | (d->subsystem_device == q->subsystem_device || | |
9234 | q->subsystem_device == PCI_ANY_ID)) | |
9235 | q->hook(dev); | |
9236 | } | |
5f85f176 EE |
9237 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
9238 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
9239 | intel_dmi_quirks[i].hook(dev); | |
9240 | } | |
b690e96c JB |
9241 | } |
9242 | ||
9cce37f4 JB |
9243 | /* Disable the VGA plane that we never use */ |
9244 | static void i915_disable_vga(struct drm_device *dev) | |
9245 | { | |
9246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9247 | u8 sr1; | |
766aa1c4 | 9248 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
9249 | |
9250 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 9251 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
9252 | sr1 = inb(VGA_SR_DATA); |
9253 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
9254 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9255 | udelay(300); | |
9256 | ||
9257 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
9258 | POSTING_READ(vga_reg); | |
9259 | } | |
9260 | ||
f817586c DV |
9261 | void intel_modeset_init_hw(struct drm_device *dev) |
9262 | { | |
fa42e23c | 9263 | intel_init_power_well(dev); |
0232e927 | 9264 | |
a8f78b58 ED |
9265 | intel_prepare_ddi(dev); |
9266 | ||
f817586c DV |
9267 | intel_init_clock_gating(dev); |
9268 | ||
79f5b2c7 | 9269 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 9270 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 9271 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
9272 | } |
9273 | ||
7d708ee4 ID |
9274 | void intel_modeset_suspend_hw(struct drm_device *dev) |
9275 | { | |
9276 | intel_suspend_hw(dev); | |
9277 | } | |
9278 | ||
79e53945 JB |
9279 | void intel_modeset_init(struct drm_device *dev) |
9280 | { | |
652c393a | 9281 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 9282 | int i, j, ret; |
79e53945 JB |
9283 | |
9284 | drm_mode_config_init(dev); | |
9285 | ||
9286 | dev->mode_config.min_width = 0; | |
9287 | dev->mode_config.min_height = 0; | |
9288 | ||
019d96cb DA |
9289 | dev->mode_config.preferred_depth = 24; |
9290 | dev->mode_config.prefer_shadow = 1; | |
9291 | ||
e6ecefaa | 9292 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 9293 | |
b690e96c JB |
9294 | intel_init_quirks(dev); |
9295 | ||
1fa61106 ED |
9296 | intel_init_pm(dev); |
9297 | ||
e3c74757 BW |
9298 | if (INTEL_INFO(dev)->num_pipes == 0) |
9299 | return; | |
9300 | ||
e70236a8 JB |
9301 | intel_init_display(dev); |
9302 | ||
a6c45cf0 CW |
9303 | if (IS_GEN2(dev)) { |
9304 | dev->mode_config.max_width = 2048; | |
9305 | dev->mode_config.max_height = 2048; | |
9306 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
9307 | dev->mode_config.max_width = 4096; |
9308 | dev->mode_config.max_height = 4096; | |
79e53945 | 9309 | } else { |
a6c45cf0 CW |
9310 | dev->mode_config.max_width = 8192; |
9311 | dev->mode_config.max_height = 8192; | |
79e53945 | 9312 | } |
5d4545ae | 9313 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 9314 | |
28c97730 | 9315 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
9316 | INTEL_INFO(dev)->num_pipes, |
9317 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 9318 | |
7eb552ae | 9319 | for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { |
79e53945 | 9320 | intel_crtc_init(dev, i); |
7f1f3851 JB |
9321 | for (j = 0; j < dev_priv->num_plane; j++) { |
9322 | ret = intel_plane_init(dev, i, j); | |
9323 | if (ret) | |
06da8da2 VS |
9324 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
9325 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 9326 | } |
79e53945 JB |
9327 | } |
9328 | ||
79f689aa | 9329 | intel_cpu_pll_init(dev); |
ee7b9f93 JB |
9330 | intel_pch_pll_init(dev); |
9331 | ||
9cce37f4 JB |
9332 | /* Just disable it once at startup */ |
9333 | i915_disable_vga(dev); | |
79e53945 | 9334 | intel_setup_outputs(dev); |
11be49eb CW |
9335 | |
9336 | /* Just in case the BIOS is doing something questionable. */ | |
9337 | intel_disable_fbc(dev); | |
2c7111db CW |
9338 | } |
9339 | ||
24929352 DV |
9340 | static void |
9341 | intel_connector_break_all_links(struct intel_connector *connector) | |
9342 | { | |
9343 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
9344 | connector->base.encoder = NULL; | |
9345 | connector->encoder->connectors_active = false; | |
9346 | connector->encoder->base.crtc = NULL; | |
9347 | } | |
9348 | ||
7fad798e DV |
9349 | static void intel_enable_pipe_a(struct drm_device *dev) |
9350 | { | |
9351 | struct intel_connector *connector; | |
9352 | struct drm_connector *crt = NULL; | |
9353 | struct intel_load_detect_pipe load_detect_temp; | |
9354 | ||
9355 | /* We can't just switch on the pipe A, we need to set things up with a | |
9356 | * proper mode and output configuration. As a gross hack, enable pipe A | |
9357 | * by enabling the load detect pipe once. */ | |
9358 | list_for_each_entry(connector, | |
9359 | &dev->mode_config.connector_list, | |
9360 | base.head) { | |
9361 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
9362 | crt = &connector->base; | |
9363 | break; | |
9364 | } | |
9365 | } | |
9366 | ||
9367 | if (!crt) | |
9368 | return; | |
9369 | ||
9370 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
9371 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
9372 | ||
652c393a | 9373 | |
7fad798e DV |
9374 | } |
9375 | ||
fa555837 DV |
9376 | static bool |
9377 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
9378 | { | |
7eb552ae BW |
9379 | struct drm_device *dev = crtc->base.dev; |
9380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
9381 | u32 reg, val; |
9382 | ||
7eb552ae | 9383 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
9384 | return true; |
9385 | ||
9386 | reg = DSPCNTR(!crtc->plane); | |
9387 | val = I915_READ(reg); | |
9388 | ||
9389 | if ((val & DISPLAY_PLANE_ENABLE) && | |
9390 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
9391 | return false; | |
9392 | ||
9393 | return true; | |
9394 | } | |
9395 | ||
24929352 DV |
9396 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
9397 | { | |
9398 | struct drm_device *dev = crtc->base.dev; | |
9399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 9400 | u32 reg; |
24929352 | 9401 | |
24929352 | 9402 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 9403 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
9404 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
9405 | ||
9406 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
9407 | * disable the crtc (and hence change the state) if it is wrong. Note |
9408 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
9409 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
9410 | struct intel_connector *connector; |
9411 | bool plane; | |
9412 | ||
24929352 DV |
9413 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
9414 | crtc->base.base.id); | |
9415 | ||
9416 | /* Pipe has the wrong plane attached and the plane is active. | |
9417 | * Temporarily change the plane mapping and disable everything | |
9418 | * ... */ | |
9419 | plane = crtc->plane; | |
9420 | crtc->plane = !plane; | |
9421 | dev_priv->display.crtc_disable(&crtc->base); | |
9422 | crtc->plane = plane; | |
9423 | ||
9424 | /* ... and break all links. */ | |
9425 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9426 | base.head) { | |
9427 | if (connector->encoder->base.crtc != &crtc->base) | |
9428 | continue; | |
9429 | ||
9430 | intel_connector_break_all_links(connector); | |
9431 | } | |
9432 | ||
9433 | WARN_ON(crtc->active); | |
9434 | crtc->base.enabled = false; | |
9435 | } | |
24929352 | 9436 | |
7fad798e DV |
9437 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
9438 | crtc->pipe == PIPE_A && !crtc->active) { | |
9439 | /* BIOS forgot to enable pipe A, this mostly happens after | |
9440 | * resume. Force-enable the pipe to fix this, the update_dpms | |
9441 | * call below we restore the pipe to the right state, but leave | |
9442 | * the required bits on. */ | |
9443 | intel_enable_pipe_a(dev); | |
9444 | } | |
9445 | ||
24929352 DV |
9446 | /* Adjust the state of the output pipe according to whether we |
9447 | * have active connectors/encoders. */ | |
9448 | intel_crtc_update_dpms(&crtc->base); | |
9449 | ||
9450 | if (crtc->active != crtc->base.enabled) { | |
9451 | struct intel_encoder *encoder; | |
9452 | ||
9453 | /* This can happen either due to bugs in the get_hw_state | |
9454 | * functions or because the pipe is force-enabled due to the | |
9455 | * pipe A quirk. */ | |
9456 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
9457 | crtc->base.base.id, | |
9458 | crtc->base.enabled ? "enabled" : "disabled", | |
9459 | crtc->active ? "enabled" : "disabled"); | |
9460 | ||
9461 | crtc->base.enabled = crtc->active; | |
9462 | ||
9463 | /* Because we only establish the connector -> encoder -> | |
9464 | * crtc links if something is active, this means the | |
9465 | * crtc is now deactivated. Break the links. connector | |
9466 | * -> encoder links are only establish when things are | |
9467 | * actually up, hence no need to break them. */ | |
9468 | WARN_ON(crtc->active); | |
9469 | ||
9470 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
9471 | WARN_ON(encoder->connectors_active); | |
9472 | encoder->base.crtc = NULL; | |
9473 | } | |
9474 | } | |
9475 | } | |
9476 | ||
9477 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
9478 | { | |
9479 | struct intel_connector *connector; | |
9480 | struct drm_device *dev = encoder->base.dev; | |
9481 | ||
9482 | /* We need to check both for a crtc link (meaning that the | |
9483 | * encoder is active and trying to read from a pipe) and the | |
9484 | * pipe itself being active. */ | |
9485 | bool has_active_crtc = encoder->base.crtc && | |
9486 | to_intel_crtc(encoder->base.crtc)->active; | |
9487 | ||
9488 | if (encoder->connectors_active && !has_active_crtc) { | |
9489 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
9490 | encoder->base.base.id, | |
9491 | drm_get_encoder_name(&encoder->base)); | |
9492 | ||
9493 | /* Connector is active, but has no active pipe. This is | |
9494 | * fallout from our resume register restoring. Disable | |
9495 | * the encoder manually again. */ | |
9496 | if (encoder->base.crtc) { | |
9497 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
9498 | encoder->base.base.id, | |
9499 | drm_get_encoder_name(&encoder->base)); | |
9500 | encoder->disable(encoder); | |
9501 | } | |
9502 | ||
9503 | /* Inconsistent output/port/pipe state happens presumably due to | |
9504 | * a bug in one of the get_hw_state functions. Or someplace else | |
9505 | * in our code, like the register restore mess on resume. Clamp | |
9506 | * things to off as a safer default. */ | |
9507 | list_for_each_entry(connector, | |
9508 | &dev->mode_config.connector_list, | |
9509 | base.head) { | |
9510 | if (connector->encoder != encoder) | |
9511 | continue; | |
9512 | ||
9513 | intel_connector_break_all_links(connector); | |
9514 | } | |
9515 | } | |
9516 | /* Enabled encoders without active connectors will be fixed in | |
9517 | * the crtc fixup. */ | |
9518 | } | |
9519 | ||
44cec740 | 9520 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
9521 | { |
9522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 9523 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f KM |
9524 | |
9525 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { | |
9526 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
209d5211 | 9527 | i915_disable_vga(dev); |
0fde901f KM |
9528 | } |
9529 | } | |
9530 | ||
24929352 DV |
9531 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
9532 | * and i915 state tracking structures. */ | |
45e2b5f6 DV |
9533 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
9534 | bool force_restore) | |
24929352 DV |
9535 | { |
9536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9537 | enum pipe pipe; | |
9538 | u32 tmp; | |
b5644d05 | 9539 | struct drm_plane *plane; |
24929352 DV |
9540 | struct intel_crtc *crtc; |
9541 | struct intel_encoder *encoder; | |
9542 | struct intel_connector *connector; | |
9543 | ||
affa9354 | 9544 | if (HAS_DDI(dev)) { |
e28d54cb PZ |
9545 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9546 | ||
9547 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9548 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9549 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9550 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9551 | pipe = PIPE_A; | |
9552 | break; | |
9553 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9554 | pipe = PIPE_B; | |
9555 | break; | |
9556 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9557 | pipe = PIPE_C; | |
9558 | break; | |
aaa148ec DL |
9559 | default: |
9560 | /* A bogus value has been programmed, disable | |
9561 | * the transcoder */ | |
9562 | WARN(1, "Bogus eDP source %08x\n", tmp); | |
9563 | intel_ddi_disable_transcoder_func(dev_priv, | |
9564 | TRANSCODER_EDP); | |
9565 | goto setup_pipes; | |
e28d54cb PZ |
9566 | } |
9567 | ||
9568 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
3b117c8f | 9569 | crtc->config.cpu_transcoder = TRANSCODER_EDP; |
e28d54cb PZ |
9570 | |
9571 | DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", | |
9572 | pipe_name(pipe)); | |
9573 | } | |
9574 | } | |
9575 | ||
aaa148ec | 9576 | setup_pipes: |
0e8ffe1b DV |
9577 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
9578 | base.head) { | |
3b117c8f | 9579 | enum transcoder tmp = crtc->config.cpu_transcoder; |
88adfff1 | 9580 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f DV |
9581 | crtc->config.cpu_transcoder = tmp; |
9582 | ||
0e8ffe1b DV |
9583 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
9584 | &crtc->config); | |
24929352 DV |
9585 | |
9586 | crtc->base.enabled = crtc->active; | |
9587 | ||
9588 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
9589 | crtc->base.base.id, | |
9590 | crtc->active ? "enabled" : "disabled"); | |
9591 | } | |
9592 | ||
affa9354 | 9593 | if (HAS_DDI(dev)) |
6441ab5f PZ |
9594 | intel_ddi_setup_hw_pll_state(dev); |
9595 | ||
24929352 DV |
9596 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9597 | base.head) { | |
9598 | pipe = 0; | |
9599 | ||
9600 | if (encoder->get_hw_state(encoder, &pipe)) { | |
9601 | encoder->base.crtc = | |
9602 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
9603 | } else { | |
9604 | encoder->base.crtc = NULL; | |
9605 | } | |
9606 | ||
9607 | encoder->connectors_active = false; | |
9608 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
9609 | encoder->base.base.id, | |
9610 | drm_get_encoder_name(&encoder->base), | |
9611 | encoder->base.crtc ? "enabled" : "disabled", | |
9612 | pipe); | |
9613 | } | |
9614 | ||
9615 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9616 | base.head) { | |
9617 | if (connector->get_hw_state(connector)) { | |
9618 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
9619 | connector->encoder->connectors_active = true; | |
9620 | connector->base.encoder = &connector->encoder->base; | |
9621 | } else { | |
9622 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
9623 | connector->base.encoder = NULL; | |
9624 | } | |
9625 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
9626 | connector->base.base.id, | |
9627 | drm_get_connector_name(&connector->base), | |
9628 | connector->base.encoder ? "enabled" : "disabled"); | |
9629 | } | |
9630 | ||
9631 | /* HW state is read out, now we need to sanitize this mess. */ | |
9632 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9633 | base.head) { | |
9634 | intel_sanitize_encoder(encoder); | |
9635 | } | |
9636 | ||
9637 | for_each_pipe(pipe) { | |
9638 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
9639 | intel_sanitize_crtc(crtc); | |
9640 | } | |
9a935856 | 9641 | |
45e2b5f6 | 9642 | if (force_restore) { |
f30da187 DV |
9643 | /* |
9644 | * We need to use raw interfaces for restoring state to avoid | |
9645 | * checking (bogus) intermediate states. | |
9646 | */ | |
45e2b5f6 | 9647 | for_each_pipe(pipe) { |
b5644d05 JB |
9648 | struct drm_crtc *crtc = |
9649 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
9650 | |
9651 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
9652 | crtc->fb); | |
45e2b5f6 | 9653 | } |
b5644d05 JB |
9654 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
9655 | intel_plane_restore(plane); | |
0fde901f KM |
9656 | |
9657 | i915_redisable_vga(dev); | |
45e2b5f6 DV |
9658 | } else { |
9659 | intel_modeset_update_staged_output_state(dev); | |
9660 | } | |
8af6cf88 DV |
9661 | |
9662 | intel_modeset_check_state(dev); | |
2e938892 DV |
9663 | |
9664 | drm_mode_config_reset(dev); | |
2c7111db CW |
9665 | } |
9666 | ||
9667 | void intel_modeset_gem_init(struct drm_device *dev) | |
9668 | { | |
1833b134 | 9669 | intel_modeset_init_hw(dev); |
02e792fb DV |
9670 | |
9671 | intel_setup_overlay(dev); | |
24929352 | 9672 | |
45e2b5f6 | 9673 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
9674 | } |
9675 | ||
9676 | void intel_modeset_cleanup(struct drm_device *dev) | |
9677 | { | |
652c393a JB |
9678 | struct drm_i915_private *dev_priv = dev->dev_private; |
9679 | struct drm_crtc *crtc; | |
9680 | struct intel_crtc *intel_crtc; | |
9681 | ||
fd0c0642 DV |
9682 | /* |
9683 | * Interrupts and polling as the first thing to avoid creating havoc. | |
9684 | * Too much stuff here (turning of rps, connectors, ...) would | |
9685 | * experience fancy races otherwise. | |
9686 | */ | |
9687 | drm_irq_uninstall(dev); | |
9688 | cancel_work_sync(&dev_priv->hotplug_work); | |
9689 | /* | |
9690 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
9691 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
9692 | */ | |
f87ea761 | 9693 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 9694 | |
652c393a JB |
9695 | mutex_lock(&dev->struct_mutex); |
9696 | ||
723bfd70 JB |
9697 | intel_unregister_dsm_handler(); |
9698 | ||
652c393a JB |
9699 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9700 | /* Skip inactive CRTCs */ | |
9701 | if (!crtc->fb) | |
9702 | continue; | |
9703 | ||
9704 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9705 | intel_increase_pllclock(crtc); |
652c393a JB |
9706 | } |
9707 | ||
973d04f9 | 9708 | intel_disable_fbc(dev); |
e70236a8 | 9709 | |
8090c6b9 | 9710 | intel_disable_gt_powersave(dev); |
0cdab21f | 9711 | |
930ebb46 DV |
9712 | ironlake_teardown_rc6(dev); |
9713 | ||
69341a5e KH |
9714 | mutex_unlock(&dev->struct_mutex); |
9715 | ||
1630fe75 CW |
9716 | /* flush any delayed tasks or pending work */ |
9717 | flush_scheduled_work(); | |
9718 | ||
dc652f90 JN |
9719 | /* destroy backlight, if any, before the connectors */ |
9720 | intel_panel_destroy_backlight(dev); | |
9721 | ||
79e53945 | 9722 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
9723 | |
9724 | intel_cleanup_overlay(dev); | |
79e53945 JB |
9725 | } |
9726 | ||
f1c79df3 ZW |
9727 | /* |
9728 | * Return which encoder is currently attached for connector. | |
9729 | */ | |
df0e9248 | 9730 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9731 | { |
df0e9248 CW |
9732 | return &intel_attached_encoder(connector)->base; |
9733 | } | |
f1c79df3 | 9734 | |
df0e9248 CW |
9735 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9736 | struct intel_encoder *encoder) | |
9737 | { | |
9738 | connector->encoder = encoder; | |
9739 | drm_mode_connector_attach_encoder(&connector->base, | |
9740 | &encoder->base); | |
79e53945 | 9741 | } |
28d52043 DA |
9742 | |
9743 | /* | |
9744 | * set vga decode state - true == enable VGA decode | |
9745 | */ | |
9746 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9747 | { | |
9748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9749 | u16 gmch_ctrl; | |
9750 | ||
9751 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9752 | if (state) | |
9753 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9754 | else | |
9755 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9756 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9757 | return 0; | |
9758 | } | |
c4a1d9e4 CW |
9759 | |
9760 | #ifdef CONFIG_DEBUG_FS | |
9761 | #include <linux/seq_file.h> | |
9762 | ||
9763 | struct intel_display_error_state { | |
ff57f1b0 PZ |
9764 | |
9765 | u32 power_well_driver; | |
9766 | ||
c4a1d9e4 CW |
9767 | struct intel_cursor_error_state { |
9768 | u32 control; | |
9769 | u32 position; | |
9770 | u32 base; | |
9771 | u32 size; | |
52331309 | 9772 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9773 | |
9774 | struct intel_pipe_error_state { | |
ff57f1b0 | 9775 | enum transcoder cpu_transcoder; |
c4a1d9e4 CW |
9776 | u32 conf; |
9777 | u32 source; | |
9778 | ||
9779 | u32 htotal; | |
9780 | u32 hblank; | |
9781 | u32 hsync; | |
9782 | u32 vtotal; | |
9783 | u32 vblank; | |
9784 | u32 vsync; | |
52331309 | 9785 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9786 | |
9787 | struct intel_plane_error_state { | |
9788 | u32 control; | |
9789 | u32 stride; | |
9790 | u32 size; | |
9791 | u32 pos; | |
9792 | u32 addr; | |
9793 | u32 surface; | |
9794 | u32 tile_offset; | |
52331309 | 9795 | } plane[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9796 | }; |
9797 | ||
9798 | struct intel_display_error_state * | |
9799 | intel_display_capture_error_state(struct drm_device *dev) | |
9800 | { | |
0206e353 | 9801 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 9802 | struct intel_display_error_state *error; |
702e7a56 | 9803 | enum transcoder cpu_transcoder; |
c4a1d9e4 CW |
9804 | int i; |
9805 | ||
9806 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9807 | if (error == NULL) | |
9808 | return NULL; | |
9809 | ||
ff57f1b0 PZ |
9810 | if (HAS_POWER_WELL(dev)) |
9811 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | |
9812 | ||
52331309 | 9813 | for_each_pipe(i) { |
702e7a56 | 9814 | cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); |
ff57f1b0 | 9815 | error->pipe[i].cpu_transcoder = cpu_transcoder; |
702e7a56 | 9816 | |
a18c4c3d PZ |
9817 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
9818 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
9819 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9820 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9821 | } else { | |
9822 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
9823 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
9824 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
9825 | } | |
c4a1d9e4 CW |
9826 | |
9827 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9828 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 9829 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 9830 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
9831 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
9832 | } | |
ca291363 PZ |
9833 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
9834 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
9835 | if (INTEL_INFO(dev)->gen >= 4) { |
9836 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9837 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9838 | } | |
9839 | ||
702e7a56 | 9840 | error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
c4a1d9e4 | 9841 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
fe2b8f9d PZ |
9842 | error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
9843 | error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
9844 | error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9845 | error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
9846 | error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
9847 | error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
9848 | } |
9849 | ||
12d217c7 PZ |
9850 | /* In the code above we read the registers without checking if the power |
9851 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to | |
9852 | * prevent the next I915_WRITE from detecting it and printing an error | |
9853 | * message. */ | |
9854 | if (HAS_POWER_WELL(dev)) | |
9855 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
9856 | ||
c4a1d9e4 CW |
9857 | return error; |
9858 | } | |
9859 | ||
9860 | void | |
9861 | intel_display_print_error_state(struct seq_file *m, | |
9862 | struct drm_device *dev, | |
9863 | struct intel_display_error_state *error) | |
9864 | { | |
9865 | int i; | |
9866 | ||
7eb552ae | 9867 | seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
ff57f1b0 PZ |
9868 | if (HAS_POWER_WELL(dev)) |
9869 | seq_printf(m, "PWR_WELL_CTL2: %08x\n", | |
9870 | error->power_well_driver); | |
52331309 | 9871 | for_each_pipe(i) { |
c4a1d9e4 | 9872 | seq_printf(m, "Pipe [%d]:\n", i); |
ff57f1b0 PZ |
9873 | seq_printf(m, " CPU transcoder: %c\n", |
9874 | transcoder_name(error->pipe[i].cpu_transcoder)); | |
c4a1d9e4 CW |
9875 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); |
9876 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9877 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9878 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9879 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9880 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9881 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9882 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9883 | ||
9884 | seq_printf(m, "Plane [%d]:\n", i); | |
9885 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9886 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 9887 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 9888 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); |
80ca378b PZ |
9889 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); |
9890 | } | |
4b71a570 | 9891 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
ca291363 | 9892 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 CW |
9893 | if (INTEL_INFO(dev)->gen >= 4) { |
9894 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9895 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9896 | } | |
9897 | ||
9898 | seq_printf(m, "Cursor [%d]:\n", i); | |
9899 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9900 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9901 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9902 | } | |
9903 | } | |
9904 | #endif |