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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
54 | static int intel_framebuffer_init(struct drm_device *dev, |
55 | struct intel_framebuffer *ifb, | |
56 | struct drm_mode_fb_cmd2 *mode_cmd, | |
57 | struct drm_i915_gem_object *obj); | |
e7457a9a | 58 | |
79e53945 | 59 | typedef struct { |
0206e353 | 60 | int min, max; |
79e53945 JB |
61 | } intel_range_t; |
62 | ||
63 | typedef struct { | |
0206e353 AJ |
64 | int dot_limit; |
65 | int p2_slow, p2_fast; | |
79e53945 JB |
66 | } intel_p2_t; |
67 | ||
d4906093 ML |
68 | typedef struct intel_limit intel_limit_t; |
69 | struct intel_limit { | |
0206e353 AJ |
70 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
71 | intel_p2_t p2; | |
d4906093 | 72 | }; |
79e53945 | 73 | |
d2acd215 DV |
74 | int |
75 | intel_pch_rawclk(struct drm_device *dev) | |
76 | { | |
77 | struct drm_i915_private *dev_priv = dev->dev_private; | |
78 | ||
79 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
80 | ||
81 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
82 | } | |
83 | ||
021357ac CW |
84 | static inline u32 /* units of 100MHz */ |
85 | intel_fdi_link_freq(struct drm_device *dev) | |
86 | { | |
8b99e68c CW |
87 | if (IS_GEN5(dev)) { |
88 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
90 | } else | |
91 | return 27; | |
021357ac CW |
92 | } |
93 | ||
5d536e28 | 94 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 95 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 96 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 97 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
98 | .m = { .min = 96, .max = 140 }, |
99 | .m1 = { .min = 18, .max = 26 }, | |
100 | .m2 = { .min = 6, .max = 16 }, | |
101 | .p = { .min = 4, .max = 128 }, | |
102 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
103 | .p2 = { .dot_limit = 165000, |
104 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
105 | }; |
106 | ||
5d536e28 DV |
107 | static const intel_limit_t intel_limits_i8xx_dvo = { |
108 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 109 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 110 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
111 | .m = { .min = 96, .max = 140 }, |
112 | .m1 = { .min = 18, .max = 26 }, | |
113 | .m2 = { .min = 6, .max = 16 }, | |
114 | .p = { .min = 4, .max = 128 }, | |
115 | .p1 = { .min = 2, .max = 33 }, | |
116 | .p2 = { .dot_limit = 165000, | |
117 | .p2_slow = 4, .p2_fast = 4 }, | |
118 | }; | |
119 | ||
e4b36699 | 120 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 121 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 122 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 123 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
124 | .m = { .min = 96, .max = 140 }, |
125 | .m1 = { .min = 18, .max = 26 }, | |
126 | .m2 = { .min = 6, .max = 16 }, | |
127 | .p = { .min = 4, .max = 128 }, | |
128 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
129 | .p2 = { .dot_limit = 165000, |
130 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 131 | }; |
273e27ca | 132 | |
e4b36699 | 133 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
134 | .dot = { .min = 20000, .max = 400000 }, |
135 | .vco = { .min = 1400000, .max = 2800000 }, | |
136 | .n = { .min = 1, .max = 6 }, | |
137 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
138 | .m1 = { .min = 8, .max = 18 }, |
139 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
140 | .p = { .min = 5, .max = 80 }, |
141 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
142 | .p2 = { .dot_limit = 200000, |
143 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
144 | }; |
145 | ||
146 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
147 | .dot = { .min = 20000, .max = 400000 }, |
148 | .vco = { .min = 1400000, .max = 2800000 }, | |
149 | .n = { .min = 1, .max = 6 }, | |
150 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
151 | .m1 = { .min = 8, .max = 18 }, |
152 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
153 | .p = { .min = 7, .max = 98 }, |
154 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
155 | .p2 = { .dot_limit = 112000, |
156 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
157 | }; |
158 | ||
273e27ca | 159 | |
e4b36699 | 160 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
161 | .dot = { .min = 25000, .max = 270000 }, |
162 | .vco = { .min = 1750000, .max = 3500000}, | |
163 | .n = { .min = 1, .max = 4 }, | |
164 | .m = { .min = 104, .max = 138 }, | |
165 | .m1 = { .min = 17, .max = 23 }, | |
166 | .m2 = { .min = 5, .max = 11 }, | |
167 | .p = { .min = 10, .max = 30 }, | |
168 | .p1 = { .min = 1, .max = 3}, | |
169 | .p2 = { .dot_limit = 270000, | |
170 | .p2_slow = 10, | |
171 | .p2_fast = 10 | |
044c7c41 | 172 | }, |
e4b36699 KP |
173 | }; |
174 | ||
175 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
176 | .dot = { .min = 22000, .max = 400000 }, |
177 | .vco = { .min = 1750000, .max = 3500000}, | |
178 | .n = { .min = 1, .max = 4 }, | |
179 | .m = { .min = 104, .max = 138 }, | |
180 | .m1 = { .min = 16, .max = 23 }, | |
181 | .m2 = { .min = 5, .max = 11 }, | |
182 | .p = { .min = 5, .max = 80 }, | |
183 | .p1 = { .min = 1, .max = 8}, | |
184 | .p2 = { .dot_limit = 165000, | |
185 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
186 | }; |
187 | ||
188 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
189 | .dot = { .min = 20000, .max = 115000 }, |
190 | .vco = { .min = 1750000, .max = 3500000 }, | |
191 | .n = { .min = 1, .max = 3 }, | |
192 | .m = { .min = 104, .max = 138 }, | |
193 | .m1 = { .min = 17, .max = 23 }, | |
194 | .m2 = { .min = 5, .max = 11 }, | |
195 | .p = { .min = 28, .max = 112 }, | |
196 | .p1 = { .min = 2, .max = 8 }, | |
197 | .p2 = { .dot_limit = 0, | |
198 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 199 | }, |
e4b36699 KP |
200 | }; |
201 | ||
202 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
203 | .dot = { .min = 80000, .max = 224000 }, |
204 | .vco = { .min = 1750000, .max = 3500000 }, | |
205 | .n = { .min = 1, .max = 3 }, | |
206 | .m = { .min = 104, .max = 138 }, | |
207 | .m1 = { .min = 17, .max = 23 }, | |
208 | .m2 = { .min = 5, .max = 11 }, | |
209 | .p = { .min = 14, .max = 42 }, | |
210 | .p1 = { .min = 2, .max = 6 }, | |
211 | .p2 = { .dot_limit = 0, | |
212 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 213 | }, |
e4b36699 KP |
214 | }; |
215 | ||
f2b115e6 | 216 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
217 | .dot = { .min = 20000, .max = 400000}, |
218 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 219 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
220 | .n = { .min = 3, .max = 6 }, |
221 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 222 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
223 | .m1 = { .min = 0, .max = 0 }, |
224 | .m2 = { .min = 0, .max = 254 }, | |
225 | .p = { .min = 5, .max = 80 }, | |
226 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
227 | .p2 = { .dot_limit = 200000, |
228 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
229 | }; |
230 | ||
f2b115e6 | 231 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
232 | .dot = { .min = 20000, .max = 400000 }, |
233 | .vco = { .min = 1700000, .max = 3500000 }, | |
234 | .n = { .min = 3, .max = 6 }, | |
235 | .m = { .min = 2, .max = 256 }, | |
236 | .m1 = { .min = 0, .max = 0 }, | |
237 | .m2 = { .min = 0, .max = 254 }, | |
238 | .p = { .min = 7, .max = 112 }, | |
239 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
240 | .p2 = { .dot_limit = 112000, |
241 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
242 | }; |
243 | ||
273e27ca EA |
244 | /* Ironlake / Sandybridge |
245 | * | |
246 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
247 | * the range value for them is (actual_value - 2). | |
248 | */ | |
b91ad0ec | 249 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
250 | .dot = { .min = 25000, .max = 350000 }, |
251 | .vco = { .min = 1760000, .max = 3510000 }, | |
252 | .n = { .min = 1, .max = 5 }, | |
253 | .m = { .min = 79, .max = 127 }, | |
254 | .m1 = { .min = 12, .max = 22 }, | |
255 | .m2 = { .min = 5, .max = 9 }, | |
256 | .p = { .min = 5, .max = 80 }, | |
257 | .p1 = { .min = 1, .max = 8 }, | |
258 | .p2 = { .dot_limit = 225000, | |
259 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
260 | }; |
261 | ||
b91ad0ec | 262 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
263 | .dot = { .min = 25000, .max = 350000 }, |
264 | .vco = { .min = 1760000, .max = 3510000 }, | |
265 | .n = { .min = 1, .max = 3 }, | |
266 | .m = { .min = 79, .max = 118 }, | |
267 | .m1 = { .min = 12, .max = 22 }, | |
268 | .m2 = { .min = 5, .max = 9 }, | |
269 | .p = { .min = 28, .max = 112 }, | |
270 | .p1 = { .min = 2, .max = 8 }, | |
271 | .p2 = { .dot_limit = 225000, | |
272 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
273 | }; |
274 | ||
275 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
276 | .dot = { .min = 25000, .max = 350000 }, |
277 | .vco = { .min = 1760000, .max = 3510000 }, | |
278 | .n = { .min = 1, .max = 3 }, | |
279 | .m = { .min = 79, .max = 127 }, | |
280 | .m1 = { .min = 12, .max = 22 }, | |
281 | .m2 = { .min = 5, .max = 9 }, | |
282 | .p = { .min = 14, .max = 56 }, | |
283 | .p1 = { .min = 2, .max = 8 }, | |
284 | .p2 = { .dot_limit = 225000, | |
285 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
286 | }; |
287 | ||
273e27ca | 288 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 289 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
290 | .dot = { .min = 25000, .max = 350000 }, |
291 | .vco = { .min = 1760000, .max = 3510000 }, | |
292 | .n = { .min = 1, .max = 2 }, | |
293 | .m = { .min = 79, .max = 126 }, | |
294 | .m1 = { .min = 12, .max = 22 }, | |
295 | .m2 = { .min = 5, .max = 9 }, | |
296 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 297 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
298 | .p2 = { .dot_limit = 225000, |
299 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
300 | }; |
301 | ||
302 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 350000 }, |
304 | .vco = { .min = 1760000, .max = 3510000 }, | |
305 | .n = { .min = 1, .max = 3 }, | |
306 | .m = { .min = 79, .max = 126 }, | |
307 | .m1 = { .min = 12, .max = 22 }, | |
308 | .m2 = { .min = 5, .max = 9 }, | |
309 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 310 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
311 | .p2 = { .dot_limit = 225000, |
312 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
313 | }; |
314 | ||
dc730512 | 315 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
316 | /* |
317 | * These are the data rate limits (measured in fast clocks) | |
318 | * since those are the strictest limits we have. The fast | |
319 | * clock and actual rate limits are more relaxed, so checking | |
320 | * them would make no difference. | |
321 | */ | |
322 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 323 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 324 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
325 | .m1 = { .min = 2, .max = 3 }, |
326 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 327 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 328 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
329 | }; |
330 | ||
6b4bf1c4 VS |
331 | static void vlv_clock(int refclk, intel_clock_t *clock) |
332 | { | |
333 | clock->m = clock->m1 * clock->m2; | |
334 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
335 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
336 | return; | |
fb03ac01 VS |
337 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
338 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
339 | } |
340 | ||
e0638cdf PZ |
341 | /** |
342 | * Returns whether any output on the specified pipe is of the specified type | |
343 | */ | |
344 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
345 | { | |
346 | struct drm_device *dev = crtc->dev; | |
347 | struct intel_encoder *encoder; | |
348 | ||
349 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
350 | if (encoder->type == type) | |
351 | return true; | |
352 | ||
353 | return false; | |
354 | } | |
355 | ||
1b894b59 CW |
356 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
357 | int refclk) | |
2c07245f | 358 | { |
b91ad0ec | 359 | struct drm_device *dev = crtc->dev; |
2c07245f | 360 | const intel_limit_t *limit; |
b91ad0ec ZW |
361 | |
362 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 363 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 364 | if (refclk == 100000) |
b91ad0ec ZW |
365 | limit = &intel_limits_ironlake_dual_lvds_100m; |
366 | else | |
367 | limit = &intel_limits_ironlake_dual_lvds; | |
368 | } else { | |
1b894b59 | 369 | if (refclk == 100000) |
b91ad0ec ZW |
370 | limit = &intel_limits_ironlake_single_lvds_100m; |
371 | else | |
372 | limit = &intel_limits_ironlake_single_lvds; | |
373 | } | |
c6bb3538 | 374 | } else |
b91ad0ec | 375 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
376 | |
377 | return limit; | |
378 | } | |
379 | ||
044c7c41 ML |
380 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
381 | { | |
382 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
383 | const intel_limit_t *limit; |
384 | ||
385 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 386 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 387 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 388 | else |
e4b36699 | 389 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
391 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 392 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 393 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 394 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 395 | } else /* The option is for other outputs */ |
e4b36699 | 396 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
397 | |
398 | return limit; | |
399 | } | |
400 | ||
1b894b59 | 401 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
402 | { |
403 | struct drm_device *dev = crtc->dev; | |
404 | const intel_limit_t *limit; | |
405 | ||
bad720ff | 406 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 407 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 408 | else if (IS_G4X(dev)) { |
044c7c41 | 409 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 410 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 411 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 412 | limit = &intel_limits_pineview_lvds; |
2177832f | 413 | else |
f2b115e6 | 414 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 415 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 416 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
417 | } else if (!IS_GEN2(dev)) { |
418 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
419 | limit = &intel_limits_i9xx_lvds; | |
420 | else | |
421 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
422 | } else { |
423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 424 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 425 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 426 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
427 | else |
428 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
429 | } |
430 | return limit; | |
431 | } | |
432 | ||
f2b115e6 AJ |
433 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
434 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 435 | { |
2177832f SL |
436 | clock->m = clock->m2 + 2; |
437 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
438 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
439 | return; | |
fb03ac01 VS |
440 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
441 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
442 | } |
443 | ||
7429e9d4 DV |
444 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
445 | { | |
446 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
447 | } | |
448 | ||
ac58c3f0 | 449 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 450 | { |
7429e9d4 | 451 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 452 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
453 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
454 | return; | |
fb03ac01 VS |
455 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
456 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
457 | } |
458 | ||
7c04d1d9 | 459 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
460 | /** |
461 | * Returns whether the given set of divisors are valid for a given refclk with | |
462 | * the given connectors. | |
463 | */ | |
464 | ||
1b894b59 CW |
465 | static bool intel_PLL_is_valid(struct drm_device *dev, |
466 | const intel_limit_t *limit, | |
467 | const intel_clock_t *clock) | |
79e53945 | 468 | { |
f01b7962 VS |
469 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
470 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 471 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 472 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 473 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 474 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 475 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 476 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
477 | |
478 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
479 | if (clock->m1 <= clock->m2) | |
480 | INTELPllInvalid("m1 <= m2\n"); | |
481 | ||
482 | if (!IS_VALLEYVIEW(dev)) { | |
483 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
484 | INTELPllInvalid("p out of range\n"); | |
485 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
486 | INTELPllInvalid("m out of range\n"); | |
487 | } | |
488 | ||
79e53945 | 489 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 490 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
491 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
492 | * connector, etc., rather than just a single range. | |
493 | */ | |
494 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 495 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
496 | |
497 | return true; | |
498 | } | |
499 | ||
d4906093 | 500 | static bool |
ee9300bb | 501 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
502 | int target, int refclk, intel_clock_t *match_clock, |
503 | intel_clock_t *best_clock) | |
79e53945 JB |
504 | { |
505 | struct drm_device *dev = crtc->dev; | |
79e53945 | 506 | intel_clock_t clock; |
79e53945 JB |
507 | int err = target; |
508 | ||
a210b028 | 509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 510 | /* |
a210b028 DV |
511 | * For LVDS just rely on its current settings for dual-channel. |
512 | * We haven't figured out how to reliably set up different | |
513 | * single/dual channel state, if we even can. | |
79e53945 | 514 | */ |
1974cad0 | 515 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
516 | clock.p2 = limit->p2.p2_fast; |
517 | else | |
518 | clock.p2 = limit->p2.p2_slow; | |
519 | } else { | |
520 | if (target < limit->p2.dot_limit) | |
521 | clock.p2 = limit->p2.p2_slow; | |
522 | else | |
523 | clock.p2 = limit->p2.p2_fast; | |
524 | } | |
525 | ||
0206e353 | 526 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 527 | |
42158660 ZY |
528 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
529 | clock.m1++) { | |
530 | for (clock.m2 = limit->m2.min; | |
531 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 532 | if (clock.m2 >= clock.m1) |
42158660 ZY |
533 | break; |
534 | for (clock.n = limit->n.min; | |
535 | clock.n <= limit->n.max; clock.n++) { | |
536 | for (clock.p1 = limit->p1.min; | |
537 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
538 | int this_err; |
539 | ||
ac58c3f0 DV |
540 | i9xx_clock(refclk, &clock); |
541 | if (!intel_PLL_is_valid(dev, limit, | |
542 | &clock)) | |
543 | continue; | |
544 | if (match_clock && | |
545 | clock.p != match_clock->p) | |
546 | continue; | |
547 | ||
548 | this_err = abs(clock.dot - target); | |
549 | if (this_err < err) { | |
550 | *best_clock = clock; | |
551 | err = this_err; | |
552 | } | |
553 | } | |
554 | } | |
555 | } | |
556 | } | |
557 | ||
558 | return (err != target); | |
559 | } | |
560 | ||
561 | static bool | |
ee9300bb DV |
562 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
563 | int target, int refclk, intel_clock_t *match_clock, | |
564 | intel_clock_t *best_clock) | |
79e53945 JB |
565 | { |
566 | struct drm_device *dev = crtc->dev; | |
79e53945 | 567 | intel_clock_t clock; |
79e53945 JB |
568 | int err = target; |
569 | ||
a210b028 | 570 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 571 | /* |
a210b028 DV |
572 | * For LVDS just rely on its current settings for dual-channel. |
573 | * We haven't figured out how to reliably set up different | |
574 | * single/dual channel state, if we even can. | |
79e53945 | 575 | */ |
1974cad0 | 576 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
577 | clock.p2 = limit->p2.p2_fast; |
578 | else | |
579 | clock.p2 = limit->p2.p2_slow; | |
580 | } else { | |
581 | if (target < limit->p2.dot_limit) | |
582 | clock.p2 = limit->p2.p2_slow; | |
583 | else | |
584 | clock.p2 = limit->p2.p2_fast; | |
585 | } | |
586 | ||
0206e353 | 587 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 588 | |
42158660 ZY |
589 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
590 | clock.m1++) { | |
591 | for (clock.m2 = limit->m2.min; | |
592 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
593 | for (clock.n = limit->n.min; |
594 | clock.n <= limit->n.max; clock.n++) { | |
595 | for (clock.p1 = limit->p1.min; | |
596 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
597 | int this_err; |
598 | ||
ac58c3f0 | 599 | pineview_clock(refclk, &clock); |
1b894b59 CW |
600 | if (!intel_PLL_is_valid(dev, limit, |
601 | &clock)) | |
79e53945 | 602 | continue; |
cec2f356 SP |
603 | if (match_clock && |
604 | clock.p != match_clock->p) | |
605 | continue; | |
79e53945 JB |
606 | |
607 | this_err = abs(clock.dot - target); | |
608 | if (this_err < err) { | |
609 | *best_clock = clock; | |
610 | err = this_err; | |
611 | } | |
612 | } | |
613 | } | |
614 | } | |
615 | } | |
616 | ||
617 | return (err != target); | |
618 | } | |
619 | ||
d4906093 | 620 | static bool |
ee9300bb DV |
621 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
622 | int target, int refclk, intel_clock_t *match_clock, | |
623 | intel_clock_t *best_clock) | |
d4906093 ML |
624 | { |
625 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
626 | intel_clock_t clock; |
627 | int max_n; | |
628 | bool found; | |
6ba770dc AJ |
629 | /* approximately equals target * 0.00585 */ |
630 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
631 | found = false; |
632 | ||
633 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 634 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
635 | clock.p2 = limit->p2.p2_fast; |
636 | else | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | } else { | |
639 | if (target < limit->p2.dot_limit) | |
640 | clock.p2 = limit->p2.p2_slow; | |
641 | else | |
642 | clock.p2 = limit->p2.p2_fast; | |
643 | } | |
644 | ||
645 | memset(best_clock, 0, sizeof(*best_clock)); | |
646 | max_n = limit->n.max; | |
f77f13e2 | 647 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 648 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 649 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
650 | for (clock.m1 = limit->m1.max; |
651 | clock.m1 >= limit->m1.min; clock.m1--) { | |
652 | for (clock.m2 = limit->m2.max; | |
653 | clock.m2 >= limit->m2.min; clock.m2--) { | |
654 | for (clock.p1 = limit->p1.max; | |
655 | clock.p1 >= limit->p1.min; clock.p1--) { | |
656 | int this_err; | |
657 | ||
ac58c3f0 | 658 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
659 | if (!intel_PLL_is_valid(dev, limit, |
660 | &clock)) | |
d4906093 | 661 | continue; |
1b894b59 CW |
662 | |
663 | this_err = abs(clock.dot - target); | |
d4906093 ML |
664 | if (this_err < err_most) { |
665 | *best_clock = clock; | |
666 | err_most = this_err; | |
667 | max_n = clock.n; | |
668 | found = true; | |
669 | } | |
670 | } | |
671 | } | |
672 | } | |
673 | } | |
2c07245f ZW |
674 | return found; |
675 | } | |
676 | ||
a0c4da24 | 677 | static bool |
ee9300bb DV |
678 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
679 | int target, int refclk, intel_clock_t *match_clock, | |
680 | intel_clock_t *best_clock) | |
a0c4da24 | 681 | { |
f01b7962 | 682 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 683 | intel_clock_t clock; |
69e4f900 | 684 | unsigned int bestppm = 1000000; |
27e639bf VS |
685 | /* min update 19.2 MHz */ |
686 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 687 | bool found = false; |
a0c4da24 | 688 | |
6b4bf1c4 VS |
689 | target *= 5; /* fast clock */ |
690 | ||
691 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
692 | |
693 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 694 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 695 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 696 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 697 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 698 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 699 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 700 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
701 | unsigned int ppm, diff; |
702 | ||
6b4bf1c4 VS |
703 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
704 | refclk * clock.m1); | |
705 | ||
706 | vlv_clock(refclk, &clock); | |
43b0ac53 | 707 | |
f01b7962 VS |
708 | if (!intel_PLL_is_valid(dev, limit, |
709 | &clock)) | |
43b0ac53 VS |
710 | continue; |
711 | ||
6b4bf1c4 VS |
712 | diff = abs(clock.dot - target); |
713 | ppm = div_u64(1000000ULL * diff, target); | |
714 | ||
715 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 716 | bestppm = 0; |
6b4bf1c4 | 717 | *best_clock = clock; |
49e497ef | 718 | found = true; |
43b0ac53 | 719 | } |
6b4bf1c4 | 720 | |
c686122c | 721 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 722 | bestppm = ppm; |
6b4bf1c4 | 723 | *best_clock = clock; |
49e497ef | 724 | found = true; |
a0c4da24 JB |
725 | } |
726 | } | |
727 | } | |
728 | } | |
729 | } | |
a0c4da24 | 730 | |
49e497ef | 731 | return found; |
a0c4da24 | 732 | } |
a4fc5ed6 | 733 | |
20ddf665 VS |
734 | bool intel_crtc_active(struct drm_crtc *crtc) |
735 | { | |
736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
737 | ||
738 | /* Be paranoid as we can arrive here with only partial | |
739 | * state retrieved from the hardware during setup. | |
740 | * | |
241bfc38 | 741 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
742 | * as Haswell has gained clock readout/fastboot support. |
743 | * | |
744 | * We can ditch the crtc->fb check as soon as we can | |
745 | * properly reconstruct framebuffers. | |
746 | */ | |
747 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 748 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
749 | } |
750 | ||
a5c961d1 PZ |
751 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
752 | enum pipe pipe) | |
753 | { | |
754 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756 | ||
3b117c8f | 757 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
758 | } |
759 | ||
57e22f4a | 760 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
761 | { |
762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 763 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
764 | |
765 | frame = I915_READ(frame_reg); | |
766 | ||
767 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
768 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
769 | } | |
770 | ||
9d0498a2 JB |
771 | /** |
772 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
773 | * @dev: drm device | |
774 | * @pipe: pipe to wait for | |
775 | * | |
776 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
777 | * mode setting code. | |
778 | */ | |
779 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 780 | { |
9d0498a2 | 781 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 782 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 783 | |
57e22f4a VS |
784 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
785 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
786 | return; |
787 | } | |
788 | ||
300387c0 CW |
789 | /* Clear existing vblank status. Note this will clear any other |
790 | * sticky status fields as well. | |
791 | * | |
792 | * This races with i915_driver_irq_handler() with the result | |
793 | * that either function could miss a vblank event. Here it is not | |
794 | * fatal, as we will either wait upon the next vblank interrupt or | |
795 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
796 | * called during modeset at which time the GPU should be idle and | |
797 | * should *not* be performing page flips and thus not waiting on | |
798 | * vblanks... | |
799 | * Currently, the result of us stealing a vblank from the irq | |
800 | * handler is that a single frame will be skipped during swapbuffers. | |
801 | */ | |
802 | I915_WRITE(pipestat_reg, | |
803 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
804 | ||
9d0498a2 | 805 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
806 | if (wait_for(I915_READ(pipestat_reg) & |
807 | PIPE_VBLANK_INTERRUPT_STATUS, | |
808 | 50)) | |
9d0498a2 JB |
809 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
810 | } | |
811 | ||
fbf49ea2 VS |
812 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
813 | { | |
814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
815 | u32 reg = PIPEDSL(pipe); | |
816 | u32 line1, line2; | |
817 | u32 line_mask; | |
818 | ||
819 | if (IS_GEN2(dev)) | |
820 | line_mask = DSL_LINEMASK_GEN2; | |
821 | else | |
822 | line_mask = DSL_LINEMASK_GEN3; | |
823 | ||
824 | line1 = I915_READ(reg) & line_mask; | |
825 | mdelay(5); | |
826 | line2 = I915_READ(reg) & line_mask; | |
827 | ||
828 | return line1 == line2; | |
829 | } | |
830 | ||
ab7ad7f6 KP |
831 | /* |
832 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
833 | * @dev: drm device |
834 | * @pipe: pipe to wait for | |
835 | * | |
836 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
837 | * spinning on the vblank interrupt status bit, since we won't actually | |
838 | * see an interrupt when the pipe is disabled. | |
839 | * | |
ab7ad7f6 KP |
840 | * On Gen4 and above: |
841 | * wait for the pipe register state bit to turn off | |
842 | * | |
843 | * Otherwise: | |
844 | * wait for the display line value to settle (it usually | |
845 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 846 | * |
9d0498a2 | 847 | */ |
58e10eb9 | 848 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
849 | { |
850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
851 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
852 | pipe); | |
ab7ad7f6 KP |
853 | |
854 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 855 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
856 | |
857 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
858 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
859 | 100)) | |
284637d9 | 860 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 861 | } else { |
ab7ad7f6 | 862 | /* Wait for the display line to settle */ |
fbf49ea2 | 863 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 864 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 865 | } |
79e53945 JB |
866 | } |
867 | ||
b0ea7d37 DL |
868 | /* |
869 | * ibx_digital_port_connected - is the specified port connected? | |
870 | * @dev_priv: i915 private structure | |
871 | * @port: the port to test | |
872 | * | |
873 | * Returns true if @port is connected, false otherwise. | |
874 | */ | |
875 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
876 | struct intel_digital_port *port) | |
877 | { | |
878 | u32 bit; | |
879 | ||
c36346e3 DL |
880 | if (HAS_PCH_IBX(dev_priv->dev)) { |
881 | switch(port->port) { | |
882 | case PORT_B: | |
883 | bit = SDE_PORTB_HOTPLUG; | |
884 | break; | |
885 | case PORT_C: | |
886 | bit = SDE_PORTC_HOTPLUG; | |
887 | break; | |
888 | case PORT_D: | |
889 | bit = SDE_PORTD_HOTPLUG; | |
890 | break; | |
891 | default: | |
892 | return true; | |
893 | } | |
894 | } else { | |
895 | switch(port->port) { | |
896 | case PORT_B: | |
897 | bit = SDE_PORTB_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_C: | |
900 | bit = SDE_PORTC_HOTPLUG_CPT; | |
901 | break; | |
902 | case PORT_D: | |
903 | bit = SDE_PORTD_HOTPLUG_CPT; | |
904 | break; | |
905 | default: | |
906 | return true; | |
907 | } | |
b0ea7d37 DL |
908 | } |
909 | ||
910 | return I915_READ(SDEISR) & bit; | |
911 | } | |
912 | ||
b24e7179 JB |
913 | static const char *state_string(bool enabled) |
914 | { | |
915 | return enabled ? "on" : "off"; | |
916 | } | |
917 | ||
918 | /* Only for pre-ILK configs */ | |
55607e8a DV |
919 | void assert_pll(struct drm_i915_private *dev_priv, |
920 | enum pipe pipe, bool state) | |
b24e7179 JB |
921 | { |
922 | int reg; | |
923 | u32 val; | |
924 | bool cur_state; | |
925 | ||
926 | reg = DPLL(pipe); | |
927 | val = I915_READ(reg); | |
928 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
929 | WARN(cur_state != state, | |
930 | "PLL state assertion failure (expected %s, current %s)\n", | |
931 | state_string(state), state_string(cur_state)); | |
932 | } | |
b24e7179 | 933 | |
23538ef1 JN |
934 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
935 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
936 | { | |
937 | u32 val; | |
938 | bool cur_state; | |
939 | ||
940 | mutex_lock(&dev_priv->dpio_lock); | |
941 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
942 | mutex_unlock(&dev_priv->dpio_lock); | |
943 | ||
944 | cur_state = val & DSI_PLL_VCO_EN; | |
945 | WARN(cur_state != state, | |
946 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
947 | state_string(state), state_string(cur_state)); | |
948 | } | |
949 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
950 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
951 | ||
55607e8a | 952 | struct intel_shared_dpll * |
e2b78267 DV |
953 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
954 | { | |
955 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
956 | ||
a43f6e0f | 957 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
958 | return NULL; |
959 | ||
a43f6e0f | 960 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
961 | } |
962 | ||
040484af | 963 | /* For ILK+ */ |
55607e8a DV |
964 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
965 | struct intel_shared_dpll *pll, | |
966 | bool state) | |
040484af | 967 | { |
040484af | 968 | bool cur_state; |
5358901f | 969 | struct intel_dpll_hw_state hw_state; |
040484af | 970 | |
9d82aa17 ED |
971 | if (HAS_PCH_LPT(dev_priv->dev)) { |
972 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
973 | return; | |
974 | } | |
975 | ||
92b27b08 | 976 | if (WARN (!pll, |
46edb027 | 977 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 978 | return; |
ee7b9f93 | 979 | |
5358901f | 980 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 981 | WARN(cur_state != state, |
5358901f DV |
982 | "%s assertion failure (expected %s, current %s)\n", |
983 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 984 | } |
040484af JB |
985 | |
986 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
987 | enum pipe pipe, bool state) | |
988 | { | |
989 | int reg; | |
990 | u32 val; | |
991 | bool cur_state; | |
ad80a810 PZ |
992 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
993 | pipe); | |
040484af | 994 | |
affa9354 PZ |
995 | if (HAS_DDI(dev_priv->dev)) { |
996 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 997 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 998 | val = I915_READ(reg); |
ad80a810 | 999 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1000 | } else { |
1001 | reg = FDI_TX_CTL(pipe); | |
1002 | val = I915_READ(reg); | |
1003 | cur_state = !!(val & FDI_TX_ENABLE); | |
1004 | } | |
040484af JB |
1005 | WARN(cur_state != state, |
1006 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1007 | state_string(state), state_string(cur_state)); | |
1008 | } | |
1009 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1010 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1011 | ||
1012 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1013 | enum pipe pipe, bool state) | |
1014 | { | |
1015 | int reg; | |
1016 | u32 val; | |
1017 | bool cur_state; | |
1018 | ||
d63fa0dc PZ |
1019 | reg = FDI_RX_CTL(pipe); |
1020 | val = I915_READ(reg); | |
1021 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1022 | WARN(cur_state != state, |
1023 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1024 | state_string(state), state_string(cur_state)); | |
1025 | } | |
1026 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1027 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1028 | ||
1029 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1030 | enum pipe pipe) | |
1031 | { | |
1032 | int reg; | |
1033 | u32 val; | |
1034 | ||
1035 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1036 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1037 | return; |
1038 | ||
bf507ef7 | 1039 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1040 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1041 | return; |
1042 | ||
040484af JB |
1043 | reg = FDI_TX_CTL(pipe); |
1044 | val = I915_READ(reg); | |
1045 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1046 | } | |
1047 | ||
55607e8a DV |
1048 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1049 | enum pipe pipe, bool state) | |
040484af JB |
1050 | { |
1051 | int reg; | |
1052 | u32 val; | |
55607e8a | 1053 | bool cur_state; |
040484af JB |
1054 | |
1055 | reg = FDI_RX_CTL(pipe); | |
1056 | val = I915_READ(reg); | |
55607e8a DV |
1057 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1058 | WARN(cur_state != state, | |
1059 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1060 | state_string(state), state_string(cur_state)); | |
040484af JB |
1061 | } |
1062 | ||
ea0760cf JB |
1063 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe) | |
1065 | { | |
1066 | int pp_reg, lvds_reg; | |
1067 | u32 val; | |
1068 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1069 | bool locked = true; |
ea0760cf JB |
1070 | |
1071 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1072 | pp_reg = PCH_PP_CONTROL; | |
1073 | lvds_reg = PCH_LVDS; | |
1074 | } else { | |
1075 | pp_reg = PP_CONTROL; | |
1076 | lvds_reg = LVDS; | |
1077 | } | |
1078 | ||
1079 | val = I915_READ(pp_reg); | |
1080 | if (!(val & PANEL_POWER_ON) || | |
1081 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1082 | locked = false; | |
1083 | ||
1084 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1085 | panel_pipe = PIPE_B; | |
1086 | ||
1087 | WARN(panel_pipe == pipe && locked, | |
1088 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1089 | pipe_name(pipe)); |
ea0760cf JB |
1090 | } |
1091 | ||
93ce0ba6 JN |
1092 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1093 | enum pipe pipe, bool state) | |
1094 | { | |
1095 | struct drm_device *dev = dev_priv->dev; | |
1096 | bool cur_state; | |
1097 | ||
1098 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1099 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1100 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1101 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1102 | else | |
1103 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1104 | ||
1105 | WARN(cur_state != state, | |
1106 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1107 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1108 | } | |
1109 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1110 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1111 | ||
b840d907 JB |
1112 | void assert_pipe(struct drm_i915_private *dev_priv, |
1113 | enum pipe pipe, bool state) | |
b24e7179 JB |
1114 | { |
1115 | int reg; | |
1116 | u32 val; | |
63d7bbe9 | 1117 | bool cur_state; |
702e7a56 PZ |
1118 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1119 | pipe); | |
b24e7179 | 1120 | |
8e636784 DV |
1121 | /* if we need the pipe A quirk it must be always on */ |
1122 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1123 | state = true; | |
1124 | ||
da7e29bd | 1125 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1126 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1127 | cur_state = false; |
1128 | } else { | |
1129 | reg = PIPECONF(cpu_transcoder); | |
1130 | val = I915_READ(reg); | |
1131 | cur_state = !!(val & PIPECONF_ENABLE); | |
1132 | } | |
1133 | ||
63d7bbe9 JB |
1134 | WARN(cur_state != state, |
1135 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1136 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1137 | } |
1138 | ||
931872fc CW |
1139 | static void assert_plane(struct drm_i915_private *dev_priv, |
1140 | enum plane plane, bool state) | |
b24e7179 JB |
1141 | { |
1142 | int reg; | |
1143 | u32 val; | |
931872fc | 1144 | bool cur_state; |
b24e7179 JB |
1145 | |
1146 | reg = DSPCNTR(plane); | |
1147 | val = I915_READ(reg); | |
931872fc CW |
1148 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1149 | WARN(cur_state != state, | |
1150 | "plane %c assertion failure (expected %s, current %s)\n", | |
1151 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1152 | } |
1153 | ||
931872fc CW |
1154 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1155 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1156 | ||
b24e7179 JB |
1157 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1158 | enum pipe pipe) | |
1159 | { | |
653e1026 | 1160 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1161 | int reg, i; |
1162 | u32 val; | |
1163 | int cur_pipe; | |
1164 | ||
653e1026 VS |
1165 | /* Primary planes are fixed to pipes on gen4+ */ |
1166 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1167 | reg = DSPCNTR(pipe); |
1168 | val = I915_READ(reg); | |
1169 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1170 | "plane %c assertion failure, should be disabled but not\n", | |
1171 | plane_name(pipe)); | |
19ec1358 | 1172 | return; |
28c05794 | 1173 | } |
19ec1358 | 1174 | |
b24e7179 | 1175 | /* Need to check both planes against the pipe */ |
08e2a7de | 1176 | for_each_pipe(i) { |
b24e7179 JB |
1177 | reg = DSPCNTR(i); |
1178 | val = I915_READ(reg); | |
1179 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1180 | DISPPLANE_SEL_PIPE_SHIFT; | |
1181 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1182 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1183 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1184 | } |
1185 | } | |
1186 | ||
19332d7a JB |
1187 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe) | |
1189 | { | |
20674eef | 1190 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1191 | int reg, sprite; |
19332d7a JB |
1192 | u32 val; |
1193 | ||
20674eef | 1194 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1195 | for_each_sprite(pipe, sprite) { |
1196 | reg = SPCNTR(pipe, sprite); | |
20674eef VS |
1197 | val = I915_READ(reg); |
1198 | WARN((val & SP_ENABLE), | |
1199 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1fe47785 | 1200 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1201 | } |
1202 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1203 | reg = SPRCTL(pipe); | |
19332d7a | 1204 | val = I915_READ(reg); |
20674eef | 1205 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1206 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1207 | plane_name(pipe), pipe_name(pipe)); |
1208 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1209 | reg = DVSCNTR(pipe); | |
19332d7a | 1210 | val = I915_READ(reg); |
20674eef | 1211 | WARN((val & DVS_ENABLE), |
06da8da2 | 1212 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1213 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1214 | } |
1215 | } | |
1216 | ||
89eff4be | 1217 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1218 | { |
1219 | u32 val; | |
1220 | bool enabled; | |
1221 | ||
89eff4be | 1222 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1223 | |
92f2584a JB |
1224 | val = I915_READ(PCH_DREF_CONTROL); |
1225 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1226 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1227 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1228 | } | |
1229 | ||
ab9412ba DV |
1230 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe) | |
92f2584a JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
1235 | bool enabled; | |
1236 | ||
ab9412ba | 1237 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1238 | val = I915_READ(reg); |
1239 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1240 | WARN(enabled, |
1241 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1242 | pipe_name(pipe)); | |
92f2584a JB |
1243 | } |
1244 | ||
4e634389 KP |
1245 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1247 | { |
1248 | if ((val & DP_PORT_EN) == 0) | |
1249 | return false; | |
1250 | ||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1252 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1253 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1254 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1255 | return false; | |
1256 | } else { | |
1257 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1258 | return false; | |
1259 | } | |
1260 | return true; | |
1261 | } | |
1262 | ||
1519b995 KP |
1263 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1264 | enum pipe pipe, u32 val) | |
1265 | { | |
dc0fa718 | 1266 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1267 | return false; |
1268 | ||
1269 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } else { | |
dc0fa718 | 1273 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1274 | return false; |
1275 | } | |
1276 | return true; | |
1277 | } | |
1278 | ||
1279 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1280 | enum pipe pipe, u32 val) | |
1281 | { | |
1282 | if ((val & LVDS_PORT_EN) == 0) | |
1283 | return false; | |
1284 | ||
1285 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1286 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1287 | return false; | |
1288 | } else { | |
1289 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1290 | return false; | |
1291 | } | |
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1296 | enum pipe pipe, u32 val) | |
1297 | { | |
1298 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1299 | return false; | |
1300 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1301 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1302 | return false; | |
1303 | } else { | |
1304 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1305 | return false; | |
1306 | } | |
1307 | return true; | |
1308 | } | |
1309 | ||
291906f1 | 1310 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1311 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1312 | { |
47a05eca | 1313 | u32 val = I915_READ(reg); |
4e634389 | 1314 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1315 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1316 | reg, pipe_name(pipe)); |
de9a35ab | 1317 | |
75c5da27 DV |
1318 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1319 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1320 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1321 | } |
1322 | ||
1323 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1324 | enum pipe pipe, int reg) | |
1325 | { | |
47a05eca | 1326 | u32 val = I915_READ(reg); |
b70ad586 | 1327 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1328 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1329 | reg, pipe_name(pipe)); |
de9a35ab | 1330 | |
dc0fa718 | 1331 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1332 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1333 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1334 | } |
1335 | ||
1336 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1337 | enum pipe pipe) | |
1338 | { | |
1339 | int reg; | |
1340 | u32 val; | |
291906f1 | 1341 | |
f0575e92 KP |
1342 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1343 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1344 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1345 | |
1346 | reg = PCH_ADPA; | |
1347 | val = I915_READ(reg); | |
b70ad586 | 1348 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1349 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1350 | pipe_name(pipe)); |
291906f1 JB |
1351 | |
1352 | reg = PCH_LVDS; | |
1353 | val = I915_READ(reg); | |
b70ad586 | 1354 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1355 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1356 | pipe_name(pipe)); |
291906f1 | 1357 | |
e2debe91 PZ |
1358 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1359 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1360 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1361 | } |
1362 | ||
40e9cf64 JB |
1363 | static void intel_init_dpio(struct drm_device *dev) |
1364 | { | |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1366 | ||
1367 | if (!IS_VALLEYVIEW(dev)) | |
1368 | return; | |
1369 | ||
e4607fcf | 1370 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
5382f5f3 JB |
1371 | } |
1372 | ||
1373 | static void intel_reset_dpio(struct drm_device *dev) | |
1374 | { | |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1376 | ||
1377 | if (!IS_VALLEYVIEW(dev)) | |
1378 | return; | |
1379 | ||
e5cbfbfb ID |
1380 | /* |
1381 | * Enable the CRI clock source so we can get at the display and the | |
1382 | * reference clock for VGA hotplug / manual detection. | |
1383 | */ | |
404faabc | 1384 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
e5cbfbfb | 1385 | DPLL_REFA_CLK_ENABLE_VLV | |
404faabc ID |
1386 | DPLL_INTEGRATED_CRI_CLK_VLV); |
1387 | ||
40e9cf64 JB |
1388 | /* |
1389 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1390 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1391 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1392 | * b. The other bits such as sfr settings / modesel may all be set | |
1393 | * to 0. | |
1394 | * | |
1395 | * This should only be done on init and resume from S3 with both | |
1396 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1397 | */ | |
1398 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1399 | } | |
1400 | ||
426115cf | 1401 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1402 | { |
426115cf DV |
1403 | struct drm_device *dev = crtc->base.dev; |
1404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1405 | int reg = DPLL(crtc->pipe); | |
1406 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1407 | |
426115cf | 1408 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1409 | |
1410 | /* No really, not for ILK+ */ | |
1411 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1412 | ||
1413 | /* PLL is protected by panel, make sure we can write it */ | |
1414 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1415 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1416 | |
426115cf DV |
1417 | I915_WRITE(reg, dpll); |
1418 | POSTING_READ(reg); | |
1419 | udelay(150); | |
1420 | ||
1421 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1422 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1423 | ||
1424 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1425 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1426 | |
1427 | /* We do this three times for luck */ | |
426115cf | 1428 | I915_WRITE(reg, dpll); |
87442f73 DV |
1429 | POSTING_READ(reg); |
1430 | udelay(150); /* wait for warmup */ | |
426115cf | 1431 | I915_WRITE(reg, dpll); |
87442f73 DV |
1432 | POSTING_READ(reg); |
1433 | udelay(150); /* wait for warmup */ | |
426115cf | 1434 | I915_WRITE(reg, dpll); |
87442f73 DV |
1435 | POSTING_READ(reg); |
1436 | udelay(150); /* wait for warmup */ | |
1437 | } | |
1438 | ||
66e3d5c0 | 1439 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1440 | { |
66e3d5c0 DV |
1441 | struct drm_device *dev = crtc->base.dev; |
1442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1443 | int reg = DPLL(crtc->pipe); | |
1444 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1445 | |
66e3d5c0 | 1446 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1447 | |
63d7bbe9 | 1448 | /* No really, not for ILK+ */ |
3d13ef2e | 1449 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1450 | |
1451 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1452 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1453 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1454 | |
66e3d5c0 DV |
1455 | I915_WRITE(reg, dpll); |
1456 | ||
1457 | /* Wait for the clocks to stabilize. */ | |
1458 | POSTING_READ(reg); | |
1459 | udelay(150); | |
1460 | ||
1461 | if (INTEL_INFO(dev)->gen >= 4) { | |
1462 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1463 | crtc->config.dpll_hw_state.dpll_md); | |
1464 | } else { | |
1465 | /* The pixel multiplier can only be updated once the | |
1466 | * DPLL is enabled and the clocks are stable. | |
1467 | * | |
1468 | * So write it again. | |
1469 | */ | |
1470 | I915_WRITE(reg, dpll); | |
1471 | } | |
63d7bbe9 JB |
1472 | |
1473 | /* We do this three times for luck */ | |
66e3d5c0 | 1474 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1475 | POSTING_READ(reg); |
1476 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1477 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1478 | POSTING_READ(reg); |
1479 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1480 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1481 | POSTING_READ(reg); |
1482 | udelay(150); /* wait for warmup */ | |
1483 | } | |
1484 | ||
1485 | /** | |
50b44a44 | 1486 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1487 | * @dev_priv: i915 private structure |
1488 | * @pipe: pipe PLL to disable | |
1489 | * | |
1490 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1491 | * | |
1492 | * Note! This is for pre-ILK only. | |
1493 | */ | |
50b44a44 | 1494 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1495 | { |
63d7bbe9 JB |
1496 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1497 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1498 | return; | |
1499 | ||
1500 | /* Make sure the pipe isn't still relying on us */ | |
1501 | assert_pipe_disabled(dev_priv, pipe); | |
1502 | ||
50b44a44 DV |
1503 | I915_WRITE(DPLL(pipe), 0); |
1504 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1505 | } |
1506 | ||
f6071166 JB |
1507 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1508 | { | |
1509 | u32 val = 0; | |
1510 | ||
1511 | /* Make sure the pipe isn't still relying on us */ | |
1512 | assert_pipe_disabled(dev_priv, pipe); | |
1513 | ||
e5cbfbfb ID |
1514 | /* |
1515 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1516 | * The latter is needed for VGA hotplug / manual detection. | |
1517 | */ | |
f6071166 | 1518 | if (pipe == PIPE_B) |
e5cbfbfb | 1519 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1520 | I915_WRITE(DPLL(pipe), val); |
1521 | POSTING_READ(DPLL(pipe)); | |
1522 | } | |
1523 | ||
e4607fcf CML |
1524 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1525 | struct intel_digital_port *dport) | |
89b667f8 JB |
1526 | { |
1527 | u32 port_mask; | |
1528 | ||
e4607fcf CML |
1529 | switch (dport->port) { |
1530 | case PORT_B: | |
89b667f8 | 1531 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1532 | break; |
1533 | case PORT_C: | |
89b667f8 | 1534 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1535 | break; |
1536 | default: | |
1537 | BUG(); | |
1538 | } | |
89b667f8 JB |
1539 | |
1540 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1541 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
be46ffd4 | 1542 | port_name(dport->port), I915_READ(DPLL(0))); |
89b667f8 JB |
1543 | } |
1544 | ||
92f2584a | 1545 | /** |
e72f9fbf | 1546 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1547 | * @dev_priv: i915 private structure |
1548 | * @pipe: pipe PLL to enable | |
1549 | * | |
1550 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1551 | * drives the transcoder clock. | |
1552 | */ | |
e2b78267 | 1553 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1554 | { |
3d13ef2e DL |
1555 | struct drm_device *dev = crtc->base.dev; |
1556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1557 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1558 | |
48da64a8 | 1559 | /* PCH PLLs only available on ILK, SNB and IVB */ |
3d13ef2e | 1560 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1561 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1562 | return; |
1563 | ||
1564 | if (WARN_ON(pll->refcount == 0)) | |
1565 | return; | |
ee7b9f93 | 1566 | |
46edb027 DV |
1567 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1568 | pll->name, pll->active, pll->on, | |
e2b78267 | 1569 | crtc->base.base.id); |
92f2584a | 1570 | |
cdbd2316 DV |
1571 | if (pll->active++) { |
1572 | WARN_ON(!pll->on); | |
e9d6944e | 1573 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1574 | return; |
1575 | } | |
f4a091c7 | 1576 | WARN_ON(pll->on); |
ee7b9f93 | 1577 | |
46edb027 | 1578 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1579 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1580 | pll->on = true; |
92f2584a JB |
1581 | } |
1582 | ||
e2b78267 | 1583 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1584 | { |
3d13ef2e DL |
1585 | struct drm_device *dev = crtc->base.dev; |
1586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1587 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1588 | |
92f2584a | 1589 | /* PCH only available on ILK+ */ |
3d13ef2e | 1590 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1591 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1592 | return; |
92f2584a | 1593 | |
48da64a8 CW |
1594 | if (WARN_ON(pll->refcount == 0)) |
1595 | return; | |
7a419866 | 1596 | |
46edb027 DV |
1597 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1598 | pll->name, pll->active, pll->on, | |
e2b78267 | 1599 | crtc->base.base.id); |
7a419866 | 1600 | |
48da64a8 | 1601 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1602 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1603 | return; |
1604 | } | |
1605 | ||
e9d6944e | 1606 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1607 | WARN_ON(!pll->on); |
cdbd2316 | 1608 | if (--pll->active) |
7a419866 | 1609 | return; |
ee7b9f93 | 1610 | |
46edb027 | 1611 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1612 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1613 | pll->on = false; |
92f2584a JB |
1614 | } |
1615 | ||
b8a4f404 PZ |
1616 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1617 | enum pipe pipe) | |
040484af | 1618 | { |
23670b32 | 1619 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1620 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1622 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1623 | |
1624 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1625 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1626 | |
1627 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1628 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1629 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1630 | |
1631 | /* FDI must be feeding us bits for PCH ports */ | |
1632 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1633 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1634 | ||
23670b32 DV |
1635 | if (HAS_PCH_CPT(dev)) { |
1636 | /* Workaround: Set the timing override bit before enabling the | |
1637 | * pch transcoder. */ | |
1638 | reg = TRANS_CHICKEN2(pipe); | |
1639 | val = I915_READ(reg); | |
1640 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1641 | I915_WRITE(reg, val); | |
59c859d6 | 1642 | } |
23670b32 | 1643 | |
ab9412ba | 1644 | reg = PCH_TRANSCONF(pipe); |
040484af | 1645 | val = I915_READ(reg); |
5f7f726d | 1646 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1647 | |
1648 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1649 | /* | |
1650 | * make the BPC in transcoder be consistent with | |
1651 | * that in pipeconf reg. | |
1652 | */ | |
dfd07d72 DV |
1653 | val &= ~PIPECONF_BPC_MASK; |
1654 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1655 | } |
5f7f726d PZ |
1656 | |
1657 | val &= ~TRANS_INTERLACE_MASK; | |
1658 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1659 | if (HAS_PCH_IBX(dev_priv->dev) && |
1660 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1661 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1662 | else | |
1663 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1664 | else |
1665 | val |= TRANS_PROGRESSIVE; | |
1666 | ||
040484af JB |
1667 | I915_WRITE(reg, val | TRANS_ENABLE); |
1668 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1669 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1670 | } |
1671 | ||
8fb033d7 | 1672 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1673 | enum transcoder cpu_transcoder) |
040484af | 1674 | { |
8fb033d7 | 1675 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1676 | |
1677 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1678 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1679 | |
8fb033d7 | 1680 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1681 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1682 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1683 | |
223a6fdf PZ |
1684 | /* Workaround: set timing override bit. */ |
1685 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1686 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1687 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1688 | ||
25f3ef11 | 1689 | val = TRANS_ENABLE; |
937bb610 | 1690 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1691 | |
9a76b1c6 PZ |
1692 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1693 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1694 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1695 | else |
1696 | val |= TRANS_PROGRESSIVE; | |
1697 | ||
ab9412ba DV |
1698 | I915_WRITE(LPT_TRANSCONF, val); |
1699 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1700 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1701 | } |
1702 | ||
b8a4f404 PZ |
1703 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1704 | enum pipe pipe) | |
040484af | 1705 | { |
23670b32 DV |
1706 | struct drm_device *dev = dev_priv->dev; |
1707 | uint32_t reg, val; | |
040484af JB |
1708 | |
1709 | /* FDI relies on the transcoder */ | |
1710 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1711 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1712 | ||
291906f1 JB |
1713 | /* Ports must be off as well */ |
1714 | assert_pch_ports_disabled(dev_priv, pipe); | |
1715 | ||
ab9412ba | 1716 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1717 | val = I915_READ(reg); |
1718 | val &= ~TRANS_ENABLE; | |
1719 | I915_WRITE(reg, val); | |
1720 | /* wait for PCH transcoder off, transcoder state */ | |
1721 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1722 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1723 | |
1724 | if (!HAS_PCH_IBX(dev)) { | |
1725 | /* Workaround: Clear the timing override chicken bit again. */ | |
1726 | reg = TRANS_CHICKEN2(pipe); | |
1727 | val = I915_READ(reg); | |
1728 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1729 | I915_WRITE(reg, val); | |
1730 | } | |
040484af JB |
1731 | } |
1732 | ||
ab4d966c | 1733 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1734 | { |
8fb033d7 PZ |
1735 | u32 val; |
1736 | ||
ab9412ba | 1737 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1738 | val &= ~TRANS_ENABLE; |
ab9412ba | 1739 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1740 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1741 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1742 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1743 | |
1744 | /* Workaround: clear timing override bit. */ | |
1745 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1746 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1747 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1748 | } |
1749 | ||
b24e7179 | 1750 | /** |
309cfea8 | 1751 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1752 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1753 | * |
0372264a | 1754 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1755 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1756 | */ |
e1fdc473 | 1757 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1758 | { |
0372264a PZ |
1759 | struct drm_device *dev = crtc->base.dev; |
1760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1761 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
1762 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1763 | pipe); | |
1a240d4d | 1764 | enum pipe pch_transcoder; |
b24e7179 JB |
1765 | int reg; |
1766 | u32 val; | |
1767 | ||
58c6eaa2 | 1768 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1769 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1770 | assert_sprites_disabled(dev_priv, pipe); |
1771 | ||
681e5811 | 1772 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1773 | pch_transcoder = TRANSCODER_A; |
1774 | else | |
1775 | pch_transcoder = pipe; | |
1776 | ||
b24e7179 JB |
1777 | /* |
1778 | * A pipe without a PLL won't actually be able to drive bits from | |
1779 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1780 | * need the check. | |
1781 | */ | |
1782 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 1783 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1784 | assert_dsi_pll_enabled(dev_priv); |
1785 | else | |
1786 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1787 | else { |
30421c4f | 1788 | if (crtc->config.has_pch_encoder) { |
040484af | 1789 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1790 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1791 | assert_fdi_tx_pll_enabled(dev_priv, |
1792 | (enum pipe) cpu_transcoder); | |
040484af JB |
1793 | } |
1794 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1795 | } | |
b24e7179 | 1796 | |
702e7a56 | 1797 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1798 | val = I915_READ(reg); |
7ad25d48 PZ |
1799 | if (val & PIPECONF_ENABLE) { |
1800 | WARN_ON(!(pipe == PIPE_A && | |
1801 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 1802 | return; |
7ad25d48 | 1803 | } |
00d70b15 CW |
1804 | |
1805 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1806 | POSTING_READ(reg); |
e1fdc473 PZ |
1807 | |
1808 | /* | |
1809 | * There's no guarantee the pipe will really start running now. It | |
1810 | * depends on the Gen, the output type and the relative order between | |
1811 | * pipe and plane enabling. Avoid waiting on HSW+ since it's not | |
1812 | * necessary. | |
1813 | * TODO: audit the previous gens. | |
1814 | */ | |
1815 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) | |
851855d8 | 1816 | intel_wait_for_vblank(dev_priv->dev, pipe); |
b24e7179 JB |
1817 | } |
1818 | ||
1819 | /** | |
309cfea8 | 1820 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1821 | * @dev_priv: i915 private structure |
1822 | * @pipe: pipe to disable | |
1823 | * | |
1824 | * Disable @pipe, making sure that various hardware specific requirements | |
1825 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1826 | * | |
1827 | * @pipe should be %PIPE_A or %PIPE_B. | |
1828 | * | |
1829 | * Will wait until the pipe has shut down before returning. | |
1830 | */ | |
1831 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1832 | enum pipe pipe) | |
1833 | { | |
702e7a56 PZ |
1834 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1835 | pipe); | |
b24e7179 JB |
1836 | int reg; |
1837 | u32 val; | |
1838 | ||
1839 | /* | |
1840 | * Make sure planes won't keep trying to pump pixels to us, | |
1841 | * or we might hang the display. | |
1842 | */ | |
1843 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1844 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1845 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1846 | |
1847 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1848 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1849 | return; | |
1850 | ||
702e7a56 | 1851 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1852 | val = I915_READ(reg); |
00d70b15 CW |
1853 | if ((val & PIPECONF_ENABLE) == 0) |
1854 | return; | |
1855 | ||
1856 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1857 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1858 | } | |
1859 | ||
d74362c9 KP |
1860 | /* |
1861 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1862 | * trigger in order to latch. The display address reg provides this. | |
1863 | */ | |
1dba99f4 VS |
1864 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1865 | enum plane plane) | |
d74362c9 | 1866 | { |
3d13ef2e DL |
1867 | struct drm_device *dev = dev_priv->dev; |
1868 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
1869 | |
1870 | I915_WRITE(reg, I915_READ(reg)); | |
1871 | POSTING_READ(reg); | |
d74362c9 KP |
1872 | } |
1873 | ||
b24e7179 | 1874 | /** |
d1de00ef | 1875 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1876 | * @dev_priv: i915 private structure |
1877 | * @plane: plane to enable | |
1878 | * @pipe: pipe being fed | |
1879 | * | |
1880 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1881 | */ | |
d1de00ef VS |
1882 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1883 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1884 | { |
939c2fe8 VS |
1885 | struct intel_crtc *intel_crtc = |
1886 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1887 | int reg; |
1888 | u32 val; | |
1889 | ||
1890 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1891 | assert_pipe_enabled(dev_priv, pipe); | |
1892 | ||
4c445e0e | 1893 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1894 | |
4c445e0e | 1895 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1896 | |
b24e7179 JB |
1897 | reg = DSPCNTR(plane); |
1898 | val = I915_READ(reg); | |
00d70b15 CW |
1899 | if (val & DISPLAY_PLANE_ENABLE) |
1900 | return; | |
1901 | ||
1902 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1903 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1904 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1905 | } | |
1906 | ||
b24e7179 | 1907 | /** |
d1de00ef | 1908 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1909 | * @dev_priv: i915 private structure |
1910 | * @plane: plane to disable | |
1911 | * @pipe: pipe consuming the data | |
1912 | * | |
1913 | * Disable @plane; should be an independent operation. | |
1914 | */ | |
d1de00ef VS |
1915 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1916 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1917 | { |
939c2fe8 VS |
1918 | struct intel_crtc *intel_crtc = |
1919 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1920 | int reg; |
1921 | u32 val; | |
1922 | ||
4c445e0e | 1923 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1924 | |
4c445e0e | 1925 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1926 | |
b24e7179 JB |
1927 | reg = DSPCNTR(plane); |
1928 | val = I915_READ(reg); | |
00d70b15 CW |
1929 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1930 | return; | |
1931 | ||
1932 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1933 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1934 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1935 | } | |
1936 | ||
693db184 CW |
1937 | static bool need_vtd_wa(struct drm_device *dev) |
1938 | { | |
1939 | #ifdef CONFIG_INTEL_IOMMU | |
1940 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1941 | return true; | |
1942 | #endif | |
1943 | return false; | |
1944 | } | |
1945 | ||
a57ce0b2 JB |
1946 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
1947 | { | |
1948 | int tile_height; | |
1949 | ||
1950 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
1951 | return ALIGN(height, tile_height); | |
1952 | } | |
1953 | ||
127bd2ac | 1954 | int |
48b956c5 | 1955 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1956 | struct drm_i915_gem_object *obj, |
919926ae | 1957 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1958 | { |
ce453d81 | 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1960 | u32 alignment; |
1961 | int ret; | |
1962 | ||
05394f39 | 1963 | switch (obj->tiling_mode) { |
6b95a207 | 1964 | case I915_TILING_NONE: |
534843da CW |
1965 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1966 | alignment = 128 * 1024; | |
a6c45cf0 | 1967 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1968 | alignment = 4 * 1024; |
1969 | else | |
1970 | alignment = 64 * 1024; | |
6b95a207 KH |
1971 | break; |
1972 | case I915_TILING_X: | |
1973 | /* pin() will align the object as required by fence */ | |
1974 | alignment = 0; | |
1975 | break; | |
1976 | case I915_TILING_Y: | |
80075d49 | 1977 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1978 | return -EINVAL; |
1979 | default: | |
1980 | BUG(); | |
1981 | } | |
1982 | ||
693db184 CW |
1983 | /* Note that the w/a also requires 64 PTE of padding following the |
1984 | * bo. We currently fill all unused PTE with the shadow page and so | |
1985 | * we should always have valid PTE following the scanout preventing | |
1986 | * the VT-d warning. | |
1987 | */ | |
1988 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1989 | alignment = 256 * 1024; | |
1990 | ||
ce453d81 | 1991 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1992 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1993 | if (ret) |
ce453d81 | 1994 | goto err_interruptible; |
6b95a207 KH |
1995 | |
1996 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1997 | * fence, whereas 965+ only requires a fence if using | |
1998 | * framebuffer compression. For simplicity, we always install | |
1999 | * a fence as the cost is not that onerous. | |
2000 | */ | |
06d98131 | 2001 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2002 | if (ret) |
2003 | goto err_unpin; | |
1690e1eb | 2004 | |
9a5a53b3 | 2005 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2006 | |
ce453d81 | 2007 | dev_priv->mm.interruptible = true; |
6b95a207 | 2008 | return 0; |
48b956c5 CW |
2009 | |
2010 | err_unpin: | |
cc98b413 | 2011 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2012 | err_interruptible: |
2013 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2014 | return ret; |
6b95a207 KH |
2015 | } |
2016 | ||
1690e1eb CW |
2017 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2018 | { | |
2019 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2020 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2021 | } |
2022 | ||
c2c75131 DV |
2023 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2024 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2025 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2026 | unsigned int tiling_mode, | |
2027 | unsigned int cpp, | |
2028 | unsigned int pitch) | |
c2c75131 | 2029 | { |
bc752862 CW |
2030 | if (tiling_mode != I915_TILING_NONE) { |
2031 | unsigned int tile_rows, tiles; | |
c2c75131 | 2032 | |
bc752862 CW |
2033 | tile_rows = *y / 8; |
2034 | *y %= 8; | |
c2c75131 | 2035 | |
bc752862 CW |
2036 | tiles = *x / (512/cpp); |
2037 | *x %= 512/cpp; | |
2038 | ||
2039 | return tile_rows * pitch * 8 + tiles * 4096; | |
2040 | } else { | |
2041 | unsigned int offset; | |
2042 | ||
2043 | offset = *y * pitch + *x * cpp; | |
2044 | *y = 0; | |
2045 | *x = (offset & 4095) / cpp; | |
2046 | return offset & -4096; | |
2047 | } | |
c2c75131 DV |
2048 | } |
2049 | ||
46f297fb JB |
2050 | int intel_format_to_fourcc(int format) |
2051 | { | |
2052 | switch (format) { | |
2053 | case DISPPLANE_8BPP: | |
2054 | return DRM_FORMAT_C8; | |
2055 | case DISPPLANE_BGRX555: | |
2056 | return DRM_FORMAT_XRGB1555; | |
2057 | case DISPPLANE_BGRX565: | |
2058 | return DRM_FORMAT_RGB565; | |
2059 | default: | |
2060 | case DISPPLANE_BGRX888: | |
2061 | return DRM_FORMAT_XRGB8888; | |
2062 | case DISPPLANE_RGBX888: | |
2063 | return DRM_FORMAT_XBGR8888; | |
2064 | case DISPPLANE_BGRX101010: | |
2065 | return DRM_FORMAT_XRGB2101010; | |
2066 | case DISPPLANE_RGBX101010: | |
2067 | return DRM_FORMAT_XBGR2101010; | |
2068 | } | |
2069 | } | |
2070 | ||
2071 | static void intel_alloc_plane_obj(struct intel_crtc *crtc, | |
2072 | struct intel_plane_config *plane_config) | |
2073 | { | |
2074 | struct drm_device *dev = crtc->base.dev; | |
2075 | struct drm_i915_gem_object *obj = NULL; | |
2076 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2077 | u32 base = plane_config->base; | |
2078 | ||
2079 | if (!plane_config->fb) | |
2080 | return; | |
2081 | ||
2082 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, | |
2083 | plane_config->size); | |
2084 | if (!obj) | |
2085 | return; | |
2086 | ||
2087 | if (plane_config->tiled) { | |
2088 | obj->tiling_mode = I915_TILING_X; | |
2089 | obj->stride = plane_config->fb->base.pitches[0]; | |
2090 | } | |
2091 | ||
2092 | mode_cmd.pixel_format = plane_config->fb->base.pixel_format; | |
2093 | mode_cmd.width = plane_config->fb->base.width; | |
2094 | mode_cmd.height = plane_config->fb->base.height; | |
2095 | mode_cmd.pitches[0] = plane_config->fb->base.pitches[0]; | |
2096 | ||
2097 | mutex_lock(&dev->struct_mutex); | |
2098 | ||
2099 | if (intel_framebuffer_init(dev, plane_config->fb, &mode_cmd, obj)) { | |
2100 | DRM_DEBUG_KMS("intel fb init failed\n"); | |
2101 | goto out_unref_obj; | |
2102 | } | |
2103 | ||
2104 | mutex_unlock(&dev->struct_mutex); | |
2105 | DRM_DEBUG_KMS("plane fb obj %p\n", plane_config->fb->obj); | |
2106 | return; | |
2107 | ||
2108 | out_unref_obj: | |
2109 | drm_gem_object_unreference(&obj->base); | |
2110 | mutex_unlock(&dev->struct_mutex); | |
46f297fb JB |
2111 | } |
2112 | ||
17638cd6 JB |
2113 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2114 | int x, int y) | |
81255565 JB |
2115 | { |
2116 | struct drm_device *dev = crtc->dev; | |
2117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2119 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2120 | struct drm_i915_gem_object *obj; |
81255565 | 2121 | int plane = intel_crtc->plane; |
e506a0c6 | 2122 | unsigned long linear_offset; |
81255565 | 2123 | u32 dspcntr; |
5eddb70b | 2124 | u32 reg; |
81255565 JB |
2125 | |
2126 | switch (plane) { | |
2127 | case 0: | |
2128 | case 1: | |
2129 | break; | |
2130 | default: | |
84f44ce7 | 2131 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2132 | return -EINVAL; |
2133 | } | |
2134 | ||
2135 | intel_fb = to_intel_framebuffer(fb); | |
2136 | obj = intel_fb->obj; | |
81255565 | 2137 | |
5eddb70b CW |
2138 | reg = DSPCNTR(plane); |
2139 | dspcntr = I915_READ(reg); | |
81255565 JB |
2140 | /* Mask out pixel format bits in case we change it */ |
2141 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2142 | switch (fb->pixel_format) { |
2143 | case DRM_FORMAT_C8: | |
81255565 JB |
2144 | dspcntr |= DISPPLANE_8BPP; |
2145 | break; | |
57779d06 VS |
2146 | case DRM_FORMAT_XRGB1555: |
2147 | case DRM_FORMAT_ARGB1555: | |
2148 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2149 | break; |
57779d06 VS |
2150 | case DRM_FORMAT_RGB565: |
2151 | dspcntr |= DISPPLANE_BGRX565; | |
2152 | break; | |
2153 | case DRM_FORMAT_XRGB8888: | |
2154 | case DRM_FORMAT_ARGB8888: | |
2155 | dspcntr |= DISPPLANE_BGRX888; | |
2156 | break; | |
2157 | case DRM_FORMAT_XBGR8888: | |
2158 | case DRM_FORMAT_ABGR8888: | |
2159 | dspcntr |= DISPPLANE_RGBX888; | |
2160 | break; | |
2161 | case DRM_FORMAT_XRGB2101010: | |
2162 | case DRM_FORMAT_ARGB2101010: | |
2163 | dspcntr |= DISPPLANE_BGRX101010; | |
2164 | break; | |
2165 | case DRM_FORMAT_XBGR2101010: | |
2166 | case DRM_FORMAT_ABGR2101010: | |
2167 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2168 | break; |
2169 | default: | |
baba133a | 2170 | BUG(); |
81255565 | 2171 | } |
57779d06 | 2172 | |
a6c45cf0 | 2173 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2174 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2175 | dspcntr |= DISPPLANE_TILED; |
2176 | else | |
2177 | dspcntr &= ~DISPPLANE_TILED; | |
2178 | } | |
2179 | ||
de1aa629 VS |
2180 | if (IS_G4X(dev)) |
2181 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2182 | ||
5eddb70b | 2183 | I915_WRITE(reg, dspcntr); |
81255565 | 2184 | |
e506a0c6 | 2185 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2186 | |
c2c75131 DV |
2187 | if (INTEL_INFO(dev)->gen >= 4) { |
2188 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2189 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2190 | fb->bits_per_pixel / 8, | |
2191 | fb->pitches[0]); | |
c2c75131 DV |
2192 | linear_offset -= intel_crtc->dspaddr_offset; |
2193 | } else { | |
e506a0c6 | 2194 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2195 | } |
e506a0c6 | 2196 | |
f343c5f6 BW |
2197 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2198 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2199 | fb->pitches[0]); | |
01f2c773 | 2200 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2201 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2202 | I915_WRITE(DSPSURF(plane), |
2203 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2204 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2205 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2206 | } else |
f343c5f6 | 2207 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2208 | POSTING_READ(reg); |
81255565 | 2209 | |
17638cd6 JB |
2210 | return 0; |
2211 | } | |
2212 | ||
2213 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2214 | struct drm_framebuffer *fb, int x, int y) | |
2215 | { | |
2216 | struct drm_device *dev = crtc->dev; | |
2217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2219 | struct intel_framebuffer *intel_fb; | |
2220 | struct drm_i915_gem_object *obj; | |
2221 | int plane = intel_crtc->plane; | |
e506a0c6 | 2222 | unsigned long linear_offset; |
17638cd6 JB |
2223 | u32 dspcntr; |
2224 | u32 reg; | |
2225 | ||
2226 | switch (plane) { | |
2227 | case 0: | |
2228 | case 1: | |
27f8227b | 2229 | case 2: |
17638cd6 JB |
2230 | break; |
2231 | default: | |
84f44ce7 | 2232 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2233 | return -EINVAL; |
2234 | } | |
2235 | ||
2236 | intel_fb = to_intel_framebuffer(fb); | |
2237 | obj = intel_fb->obj; | |
2238 | ||
2239 | reg = DSPCNTR(plane); | |
2240 | dspcntr = I915_READ(reg); | |
2241 | /* Mask out pixel format bits in case we change it */ | |
2242 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2243 | switch (fb->pixel_format) { |
2244 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2245 | dspcntr |= DISPPLANE_8BPP; |
2246 | break; | |
57779d06 VS |
2247 | case DRM_FORMAT_RGB565: |
2248 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2249 | break; |
57779d06 VS |
2250 | case DRM_FORMAT_XRGB8888: |
2251 | case DRM_FORMAT_ARGB8888: | |
2252 | dspcntr |= DISPPLANE_BGRX888; | |
2253 | break; | |
2254 | case DRM_FORMAT_XBGR8888: | |
2255 | case DRM_FORMAT_ABGR8888: | |
2256 | dspcntr |= DISPPLANE_RGBX888; | |
2257 | break; | |
2258 | case DRM_FORMAT_XRGB2101010: | |
2259 | case DRM_FORMAT_ARGB2101010: | |
2260 | dspcntr |= DISPPLANE_BGRX101010; | |
2261 | break; | |
2262 | case DRM_FORMAT_XBGR2101010: | |
2263 | case DRM_FORMAT_ABGR2101010: | |
2264 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2265 | break; |
2266 | default: | |
baba133a | 2267 | BUG(); |
17638cd6 JB |
2268 | } |
2269 | ||
2270 | if (obj->tiling_mode != I915_TILING_NONE) | |
2271 | dspcntr |= DISPPLANE_TILED; | |
2272 | else | |
2273 | dspcntr &= ~DISPPLANE_TILED; | |
2274 | ||
b42c6009 | 2275 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2276 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2277 | else | |
2278 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2279 | |
2280 | I915_WRITE(reg, dspcntr); | |
2281 | ||
e506a0c6 | 2282 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2283 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2284 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2285 | fb->bits_per_pixel / 8, | |
2286 | fb->pitches[0]); | |
c2c75131 | 2287 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2288 | |
f343c5f6 BW |
2289 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2290 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2291 | fb->pitches[0]); | |
01f2c773 | 2292 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2293 | I915_WRITE(DSPSURF(plane), |
2294 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2295 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2296 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2297 | } else { | |
2298 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2299 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2300 | } | |
17638cd6 JB |
2301 | POSTING_READ(reg); |
2302 | ||
2303 | return 0; | |
2304 | } | |
2305 | ||
2306 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2307 | static int | |
2308 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2309 | int x, int y, enum mode_set_atomic state) | |
2310 | { | |
2311 | struct drm_device *dev = crtc->dev; | |
2312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2313 | |
6b8e6ed0 CW |
2314 | if (dev_priv->display.disable_fbc) |
2315 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2316 | intel_increase_pllclock(crtc); |
81255565 | 2317 | |
6b8e6ed0 | 2318 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2319 | } |
2320 | ||
96a02917 VS |
2321 | void intel_display_handle_reset(struct drm_device *dev) |
2322 | { | |
2323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2324 | struct drm_crtc *crtc; | |
2325 | ||
2326 | /* | |
2327 | * Flips in the rings have been nuked by the reset, | |
2328 | * so complete all pending flips so that user space | |
2329 | * will get its events and not get stuck. | |
2330 | * | |
2331 | * Also update the base address of all primary | |
2332 | * planes to the the last fb to make sure we're | |
2333 | * showing the correct fb after a reset. | |
2334 | * | |
2335 | * Need to make two loops over the crtcs so that we | |
2336 | * don't try to grab a crtc mutex before the | |
2337 | * pending_flip_queue really got woken up. | |
2338 | */ | |
2339 | ||
2340 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2342 | enum plane plane = intel_crtc->plane; | |
2343 | ||
2344 | intel_prepare_page_flip(dev, plane); | |
2345 | intel_finish_page_flip_plane(dev, plane); | |
2346 | } | |
2347 | ||
2348 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2350 | ||
2351 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2352 | /* |
2353 | * FIXME: Once we have proper support for primary planes (and | |
2354 | * disabling them without disabling the entire crtc) allow again | |
2355 | * a NULL crtc->fb. | |
2356 | */ | |
2357 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2358 | dev_priv->display.update_plane(crtc, crtc->fb, |
2359 | crtc->x, crtc->y); | |
2360 | mutex_unlock(&crtc->mutex); | |
2361 | } | |
2362 | } | |
2363 | ||
14667a4b CW |
2364 | static int |
2365 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2366 | { | |
2367 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2368 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2369 | bool was_interruptible = dev_priv->mm.interruptible; | |
2370 | int ret; | |
2371 | ||
14667a4b CW |
2372 | /* Big Hammer, we also need to ensure that any pending |
2373 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2374 | * current scanout is retired before unpinning the old | |
2375 | * framebuffer. | |
2376 | * | |
2377 | * This should only fail upon a hung GPU, in which case we | |
2378 | * can safely continue. | |
2379 | */ | |
2380 | dev_priv->mm.interruptible = false; | |
2381 | ret = i915_gem_object_finish_gpu(obj); | |
2382 | dev_priv->mm.interruptible = was_interruptible; | |
2383 | ||
2384 | return ret; | |
2385 | } | |
2386 | ||
7d5e3799 CW |
2387 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2388 | { | |
2389 | struct drm_device *dev = crtc->dev; | |
2390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2392 | unsigned long flags; | |
2393 | bool pending; | |
2394 | ||
2395 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2396 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2397 | return false; | |
2398 | ||
2399 | spin_lock_irqsave(&dev->event_lock, flags); | |
2400 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2401 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2402 | ||
2403 | return pending; | |
2404 | } | |
2405 | ||
5c3b82e2 | 2406 | static int |
3c4fdcfb | 2407 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2408 | struct drm_framebuffer *fb) |
79e53945 JB |
2409 | { |
2410 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2411 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2412 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2413 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2414 | int ret; |
79e53945 | 2415 | |
7d5e3799 CW |
2416 | if (intel_crtc_has_pending_flip(crtc)) { |
2417 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2418 | return -EBUSY; | |
2419 | } | |
2420 | ||
79e53945 | 2421 | /* no fb bound */ |
94352cf9 | 2422 | if (!fb) { |
a5071c2f | 2423 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2424 | return 0; |
2425 | } | |
2426 | ||
7eb552ae | 2427 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2428 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2429 | plane_name(intel_crtc->plane), | |
2430 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2431 | return -EINVAL; |
79e53945 JB |
2432 | } |
2433 | ||
5c3b82e2 | 2434 | mutex_lock(&dev->struct_mutex); |
265db958 | 2435 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2436 | to_intel_framebuffer(fb)->obj, |
919926ae | 2437 | NULL); |
5c3b82e2 CW |
2438 | if (ret != 0) { |
2439 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2440 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2441 | return ret; |
2442 | } | |
79e53945 | 2443 | |
bb2043de DL |
2444 | /* |
2445 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2446 | * that in compute_mode_changes we check the native mode (not the pfit | |
2447 | * mode) to see if we can flip rather than do a full mode set. In the | |
2448 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2449 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2450 | * sized surface. | |
2451 | * | |
2452 | * To fix this properly, we need to hoist the checks up into | |
2453 | * compute_mode_changes (or above), check the actual pfit state and | |
2454 | * whether the platform allows pfit disable with pipe active, and only | |
2455 | * then update the pipesrc and pfit state, even on the flip path. | |
2456 | */ | |
d330a953 | 2457 | if (i915.fastboot) { |
d7bf63f2 DL |
2458 | const struct drm_display_mode *adjusted_mode = |
2459 | &intel_crtc->config.adjusted_mode; | |
2460 | ||
4d6a3e63 | 2461 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2462 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2463 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2464 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2465 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2466 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2467 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2468 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2469 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2470 | } | |
0637d60d JB |
2471 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2472 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2473 | } |
2474 | ||
94352cf9 | 2475 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2476 | if (ret) { |
94352cf9 | 2477 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2478 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2479 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2480 | return ret; |
79e53945 | 2481 | } |
3c4fdcfb | 2482 | |
94352cf9 DV |
2483 | old_fb = crtc->fb; |
2484 | crtc->fb = fb; | |
6c4c86f5 DV |
2485 | crtc->x = x; |
2486 | crtc->y = y; | |
94352cf9 | 2487 | |
b7f1de28 | 2488 | if (old_fb) { |
d7697eea DV |
2489 | if (intel_crtc->active && old_fb != fb) |
2490 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2491 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2492 | } |
652c393a | 2493 | |
6b8e6ed0 | 2494 | intel_update_fbc(dev); |
4906557e | 2495 | intel_edp_psr_update(dev); |
5c3b82e2 | 2496 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2497 | |
5c3b82e2 | 2498 | return 0; |
79e53945 JB |
2499 | } |
2500 | ||
5e84e1a4 ZW |
2501 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2502 | { | |
2503 | struct drm_device *dev = crtc->dev; | |
2504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2506 | int pipe = intel_crtc->pipe; | |
2507 | u32 reg, temp; | |
2508 | ||
2509 | /* enable normal train */ | |
2510 | reg = FDI_TX_CTL(pipe); | |
2511 | temp = I915_READ(reg); | |
61e499bf | 2512 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2513 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2514 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2515 | } else { |
2516 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2517 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2518 | } |
5e84e1a4 ZW |
2519 | I915_WRITE(reg, temp); |
2520 | ||
2521 | reg = FDI_RX_CTL(pipe); | |
2522 | temp = I915_READ(reg); | |
2523 | if (HAS_PCH_CPT(dev)) { | |
2524 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2525 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2526 | } else { | |
2527 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2528 | temp |= FDI_LINK_TRAIN_NONE; | |
2529 | } | |
2530 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2531 | ||
2532 | /* wait one idle pattern time */ | |
2533 | POSTING_READ(reg); | |
2534 | udelay(1000); | |
357555c0 JB |
2535 | |
2536 | /* IVB wants error correction enabled */ | |
2537 | if (IS_IVYBRIDGE(dev)) | |
2538 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2539 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2540 | } |
2541 | ||
1fbc0d78 | 2542 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2543 | { |
1fbc0d78 DV |
2544 | return crtc->base.enabled && crtc->active && |
2545 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2546 | } |
2547 | ||
01a415fd DV |
2548 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2549 | { | |
2550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2551 | struct intel_crtc *pipe_B_crtc = | |
2552 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2553 | struct intel_crtc *pipe_C_crtc = | |
2554 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2555 | uint32_t temp; | |
2556 | ||
1e833f40 DV |
2557 | /* |
2558 | * When everything is off disable fdi C so that we could enable fdi B | |
2559 | * with all lanes. Note that we don't care about enabled pipes without | |
2560 | * an enabled pch encoder. | |
2561 | */ | |
2562 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2563 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2564 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2565 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2566 | ||
2567 | temp = I915_READ(SOUTH_CHICKEN1); | |
2568 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2569 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2570 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2571 | } | |
2572 | } | |
2573 | ||
8db9d77b ZW |
2574 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2575 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2576 | { | |
2577 | struct drm_device *dev = crtc->dev; | |
2578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2580 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2581 | int plane = intel_crtc->plane; |
5eddb70b | 2582 | u32 reg, temp, tries; |
8db9d77b | 2583 | |
0fc932b8 JB |
2584 | /* FDI needs bits from pipe & plane first */ |
2585 | assert_pipe_enabled(dev_priv, pipe); | |
2586 | assert_plane_enabled(dev_priv, plane); | |
2587 | ||
e1a44743 AJ |
2588 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2589 | for train result */ | |
5eddb70b CW |
2590 | reg = FDI_RX_IMR(pipe); |
2591 | temp = I915_READ(reg); | |
e1a44743 AJ |
2592 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2593 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2594 | I915_WRITE(reg, temp); |
2595 | I915_READ(reg); | |
e1a44743 AJ |
2596 | udelay(150); |
2597 | ||
8db9d77b | 2598 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2599 | reg = FDI_TX_CTL(pipe); |
2600 | temp = I915_READ(reg); | |
627eb5a3 DV |
2601 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2602 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2603 | temp &= ~FDI_LINK_TRAIN_NONE; |
2604 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2605 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2606 | |
5eddb70b CW |
2607 | reg = FDI_RX_CTL(pipe); |
2608 | temp = I915_READ(reg); | |
8db9d77b ZW |
2609 | temp &= ~FDI_LINK_TRAIN_NONE; |
2610 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2611 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2612 | ||
2613 | POSTING_READ(reg); | |
8db9d77b ZW |
2614 | udelay(150); |
2615 | ||
5b2adf89 | 2616 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2617 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2618 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2619 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2620 | |
5eddb70b | 2621 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2622 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2623 | temp = I915_READ(reg); |
8db9d77b ZW |
2624 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2625 | ||
2626 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2627 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2628 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2629 | break; |
2630 | } | |
8db9d77b | 2631 | } |
e1a44743 | 2632 | if (tries == 5) |
5eddb70b | 2633 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2634 | |
2635 | /* Train 2 */ | |
5eddb70b CW |
2636 | reg = FDI_TX_CTL(pipe); |
2637 | temp = I915_READ(reg); | |
8db9d77b ZW |
2638 | temp &= ~FDI_LINK_TRAIN_NONE; |
2639 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2640 | I915_WRITE(reg, temp); |
8db9d77b | 2641 | |
5eddb70b CW |
2642 | reg = FDI_RX_CTL(pipe); |
2643 | temp = I915_READ(reg); | |
8db9d77b ZW |
2644 | temp &= ~FDI_LINK_TRAIN_NONE; |
2645 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2646 | I915_WRITE(reg, temp); |
8db9d77b | 2647 | |
5eddb70b CW |
2648 | POSTING_READ(reg); |
2649 | udelay(150); | |
8db9d77b | 2650 | |
5eddb70b | 2651 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2652 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2653 | temp = I915_READ(reg); |
8db9d77b ZW |
2654 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2655 | ||
2656 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2657 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2658 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2659 | break; | |
2660 | } | |
8db9d77b | 2661 | } |
e1a44743 | 2662 | if (tries == 5) |
5eddb70b | 2663 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2664 | |
2665 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2666 | |
8db9d77b ZW |
2667 | } |
2668 | ||
0206e353 | 2669 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2670 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2671 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2672 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2673 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2674 | }; | |
2675 | ||
2676 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2677 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2678 | { | |
2679 | struct drm_device *dev = crtc->dev; | |
2680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2682 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2683 | u32 reg, temp, i, retry; |
8db9d77b | 2684 | |
e1a44743 AJ |
2685 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2686 | for train result */ | |
5eddb70b CW |
2687 | reg = FDI_RX_IMR(pipe); |
2688 | temp = I915_READ(reg); | |
e1a44743 AJ |
2689 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2690 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2691 | I915_WRITE(reg, temp); |
2692 | ||
2693 | POSTING_READ(reg); | |
e1a44743 AJ |
2694 | udelay(150); |
2695 | ||
8db9d77b | 2696 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2697 | reg = FDI_TX_CTL(pipe); |
2698 | temp = I915_READ(reg); | |
627eb5a3 DV |
2699 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2700 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2701 | temp &= ~FDI_LINK_TRAIN_NONE; |
2702 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2703 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2704 | /* SNB-B */ | |
2705 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2706 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2707 | |
d74cf324 DV |
2708 | I915_WRITE(FDI_RX_MISC(pipe), |
2709 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2710 | ||
5eddb70b CW |
2711 | reg = FDI_RX_CTL(pipe); |
2712 | temp = I915_READ(reg); | |
8db9d77b ZW |
2713 | if (HAS_PCH_CPT(dev)) { |
2714 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2715 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2716 | } else { | |
2717 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2718 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2719 | } | |
5eddb70b CW |
2720 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2721 | ||
2722 | POSTING_READ(reg); | |
8db9d77b ZW |
2723 | udelay(150); |
2724 | ||
0206e353 | 2725 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2726 | reg = FDI_TX_CTL(pipe); |
2727 | temp = I915_READ(reg); | |
8db9d77b ZW |
2728 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2729 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2730 | I915_WRITE(reg, temp); |
2731 | ||
2732 | POSTING_READ(reg); | |
8db9d77b ZW |
2733 | udelay(500); |
2734 | ||
fa37d39e SP |
2735 | for (retry = 0; retry < 5; retry++) { |
2736 | reg = FDI_RX_IIR(pipe); | |
2737 | temp = I915_READ(reg); | |
2738 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2739 | if (temp & FDI_RX_BIT_LOCK) { | |
2740 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2741 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2742 | break; | |
2743 | } | |
2744 | udelay(50); | |
8db9d77b | 2745 | } |
fa37d39e SP |
2746 | if (retry < 5) |
2747 | break; | |
8db9d77b ZW |
2748 | } |
2749 | if (i == 4) | |
5eddb70b | 2750 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2751 | |
2752 | /* Train 2 */ | |
5eddb70b CW |
2753 | reg = FDI_TX_CTL(pipe); |
2754 | temp = I915_READ(reg); | |
8db9d77b ZW |
2755 | temp &= ~FDI_LINK_TRAIN_NONE; |
2756 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2757 | if (IS_GEN6(dev)) { | |
2758 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2759 | /* SNB-B */ | |
2760 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2761 | } | |
5eddb70b | 2762 | I915_WRITE(reg, temp); |
8db9d77b | 2763 | |
5eddb70b CW |
2764 | reg = FDI_RX_CTL(pipe); |
2765 | temp = I915_READ(reg); | |
8db9d77b ZW |
2766 | if (HAS_PCH_CPT(dev)) { |
2767 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2768 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2769 | } else { | |
2770 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2771 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2772 | } | |
5eddb70b CW |
2773 | I915_WRITE(reg, temp); |
2774 | ||
2775 | POSTING_READ(reg); | |
8db9d77b ZW |
2776 | udelay(150); |
2777 | ||
0206e353 | 2778 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2779 | reg = FDI_TX_CTL(pipe); |
2780 | temp = I915_READ(reg); | |
8db9d77b ZW |
2781 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2782 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2783 | I915_WRITE(reg, temp); |
2784 | ||
2785 | POSTING_READ(reg); | |
8db9d77b ZW |
2786 | udelay(500); |
2787 | ||
fa37d39e SP |
2788 | for (retry = 0; retry < 5; retry++) { |
2789 | reg = FDI_RX_IIR(pipe); | |
2790 | temp = I915_READ(reg); | |
2791 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2792 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2793 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2794 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2795 | break; | |
2796 | } | |
2797 | udelay(50); | |
8db9d77b | 2798 | } |
fa37d39e SP |
2799 | if (retry < 5) |
2800 | break; | |
8db9d77b ZW |
2801 | } |
2802 | if (i == 4) | |
5eddb70b | 2803 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2804 | |
2805 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2806 | } | |
2807 | ||
357555c0 JB |
2808 | /* Manual link training for Ivy Bridge A0 parts */ |
2809 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2810 | { | |
2811 | struct drm_device *dev = crtc->dev; | |
2812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2814 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2815 | u32 reg, temp, i, j; |
357555c0 JB |
2816 | |
2817 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2818 | for train result */ | |
2819 | reg = FDI_RX_IMR(pipe); | |
2820 | temp = I915_READ(reg); | |
2821 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2822 | temp &= ~FDI_RX_BIT_LOCK; | |
2823 | I915_WRITE(reg, temp); | |
2824 | ||
2825 | POSTING_READ(reg); | |
2826 | udelay(150); | |
2827 | ||
01a415fd DV |
2828 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2829 | I915_READ(FDI_RX_IIR(pipe))); | |
2830 | ||
139ccd3f JB |
2831 | /* Try each vswing and preemphasis setting twice before moving on */ |
2832 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2833 | /* disable first in case we need to retry */ | |
2834 | reg = FDI_TX_CTL(pipe); | |
2835 | temp = I915_READ(reg); | |
2836 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2837 | temp &= ~FDI_TX_ENABLE; | |
2838 | I915_WRITE(reg, temp); | |
357555c0 | 2839 | |
139ccd3f JB |
2840 | reg = FDI_RX_CTL(pipe); |
2841 | temp = I915_READ(reg); | |
2842 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2843 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2844 | temp &= ~FDI_RX_ENABLE; | |
2845 | I915_WRITE(reg, temp); | |
357555c0 | 2846 | |
139ccd3f | 2847 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2848 | reg = FDI_TX_CTL(pipe); |
2849 | temp = I915_READ(reg); | |
139ccd3f JB |
2850 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2851 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2852 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2853 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2854 | temp |= snb_b_fdi_train_param[j/2]; |
2855 | temp |= FDI_COMPOSITE_SYNC; | |
2856 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2857 | |
139ccd3f JB |
2858 | I915_WRITE(FDI_RX_MISC(pipe), |
2859 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2860 | |
139ccd3f | 2861 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2862 | temp = I915_READ(reg); |
139ccd3f JB |
2863 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2864 | temp |= FDI_COMPOSITE_SYNC; | |
2865 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2866 | |
139ccd3f JB |
2867 | POSTING_READ(reg); |
2868 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2869 | |
139ccd3f JB |
2870 | for (i = 0; i < 4; i++) { |
2871 | reg = FDI_RX_IIR(pipe); | |
2872 | temp = I915_READ(reg); | |
2873 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2874 | |
139ccd3f JB |
2875 | if (temp & FDI_RX_BIT_LOCK || |
2876 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2877 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2878 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2879 | i); | |
2880 | break; | |
2881 | } | |
2882 | udelay(1); /* should be 0.5us */ | |
2883 | } | |
2884 | if (i == 4) { | |
2885 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2886 | continue; | |
2887 | } | |
357555c0 | 2888 | |
139ccd3f | 2889 | /* Train 2 */ |
357555c0 JB |
2890 | reg = FDI_TX_CTL(pipe); |
2891 | temp = I915_READ(reg); | |
139ccd3f JB |
2892 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2893 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2894 | I915_WRITE(reg, temp); | |
2895 | ||
2896 | reg = FDI_RX_CTL(pipe); | |
2897 | temp = I915_READ(reg); | |
2898 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2899 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2900 | I915_WRITE(reg, temp); |
2901 | ||
2902 | POSTING_READ(reg); | |
139ccd3f | 2903 | udelay(2); /* should be 1.5us */ |
357555c0 | 2904 | |
139ccd3f JB |
2905 | for (i = 0; i < 4; i++) { |
2906 | reg = FDI_RX_IIR(pipe); | |
2907 | temp = I915_READ(reg); | |
2908 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2909 | |
139ccd3f JB |
2910 | if (temp & FDI_RX_SYMBOL_LOCK || |
2911 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2912 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2913 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2914 | i); | |
2915 | goto train_done; | |
2916 | } | |
2917 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2918 | } |
139ccd3f JB |
2919 | if (i == 4) |
2920 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2921 | } |
357555c0 | 2922 | |
139ccd3f | 2923 | train_done: |
357555c0 JB |
2924 | DRM_DEBUG_KMS("FDI train done.\n"); |
2925 | } | |
2926 | ||
88cefb6c | 2927 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2928 | { |
88cefb6c | 2929 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2930 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2931 | int pipe = intel_crtc->pipe; |
5eddb70b | 2932 | u32 reg, temp; |
79e53945 | 2933 | |
c64e311e | 2934 | |
c98e9dcf | 2935 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2936 | reg = FDI_RX_CTL(pipe); |
2937 | temp = I915_READ(reg); | |
627eb5a3 DV |
2938 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2939 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2940 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2941 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2942 | ||
2943 | POSTING_READ(reg); | |
c98e9dcf JB |
2944 | udelay(200); |
2945 | ||
2946 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2947 | temp = I915_READ(reg); |
2948 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2949 | ||
2950 | POSTING_READ(reg); | |
c98e9dcf JB |
2951 | udelay(200); |
2952 | ||
20749730 PZ |
2953 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2954 | reg = FDI_TX_CTL(pipe); | |
2955 | temp = I915_READ(reg); | |
2956 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2957 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2958 | |
20749730 PZ |
2959 | POSTING_READ(reg); |
2960 | udelay(100); | |
6be4a607 | 2961 | } |
0e23b99d JB |
2962 | } |
2963 | ||
88cefb6c DV |
2964 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2965 | { | |
2966 | struct drm_device *dev = intel_crtc->base.dev; | |
2967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2968 | int pipe = intel_crtc->pipe; | |
2969 | u32 reg, temp; | |
2970 | ||
2971 | /* Switch from PCDclk to Rawclk */ | |
2972 | reg = FDI_RX_CTL(pipe); | |
2973 | temp = I915_READ(reg); | |
2974 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2975 | ||
2976 | /* Disable CPU FDI TX PLL */ | |
2977 | reg = FDI_TX_CTL(pipe); | |
2978 | temp = I915_READ(reg); | |
2979 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2980 | ||
2981 | POSTING_READ(reg); | |
2982 | udelay(100); | |
2983 | ||
2984 | reg = FDI_RX_CTL(pipe); | |
2985 | temp = I915_READ(reg); | |
2986 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2987 | ||
2988 | /* Wait for the clocks to turn off. */ | |
2989 | POSTING_READ(reg); | |
2990 | udelay(100); | |
2991 | } | |
2992 | ||
0fc932b8 JB |
2993 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2994 | { | |
2995 | struct drm_device *dev = crtc->dev; | |
2996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2998 | int pipe = intel_crtc->pipe; | |
2999 | u32 reg, temp; | |
3000 | ||
3001 | /* disable CPU FDI tx and PCH FDI rx */ | |
3002 | reg = FDI_TX_CTL(pipe); | |
3003 | temp = I915_READ(reg); | |
3004 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3005 | POSTING_READ(reg); | |
3006 | ||
3007 | reg = FDI_RX_CTL(pipe); | |
3008 | temp = I915_READ(reg); | |
3009 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3010 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3011 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3012 | ||
3013 | POSTING_READ(reg); | |
3014 | udelay(100); | |
3015 | ||
3016 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
3017 | if (HAS_PCH_IBX(dev)) { |
3018 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 3019 | } |
0fc932b8 JB |
3020 | |
3021 | /* still set train pattern 1 */ | |
3022 | reg = FDI_TX_CTL(pipe); | |
3023 | temp = I915_READ(reg); | |
3024 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3025 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3026 | I915_WRITE(reg, temp); | |
3027 | ||
3028 | reg = FDI_RX_CTL(pipe); | |
3029 | temp = I915_READ(reg); | |
3030 | if (HAS_PCH_CPT(dev)) { | |
3031 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3032 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3033 | } else { | |
3034 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3035 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3036 | } | |
3037 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3038 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3039 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3040 | I915_WRITE(reg, temp); |
3041 | ||
3042 | POSTING_READ(reg); | |
3043 | udelay(100); | |
3044 | } | |
3045 | ||
5dce5b93 CW |
3046 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3047 | { | |
3048 | struct intel_crtc *crtc; | |
3049 | ||
3050 | /* Note that we don't need to be called with mode_config.lock here | |
3051 | * as our list of CRTC objects is static for the lifetime of the | |
3052 | * device and so cannot disappear as we iterate. Similarly, we can | |
3053 | * happily treat the predicates as racy, atomic checks as userspace | |
3054 | * cannot claim and pin a new fb without at least acquring the | |
3055 | * struct_mutex and so serialising with us. | |
3056 | */ | |
3057 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3058 | if (atomic_read(&crtc->unpin_work_count) == 0) | |
3059 | continue; | |
3060 | ||
3061 | if (crtc->unpin_work) | |
3062 | intel_wait_for_vblank(dev, crtc->pipe); | |
3063 | ||
3064 | return true; | |
3065 | } | |
3066 | ||
3067 | return false; | |
3068 | } | |
3069 | ||
e6c3a2a6 CW |
3070 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3071 | { | |
0f91128d | 3072 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3073 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
3074 | |
3075 | if (crtc->fb == NULL) | |
3076 | return; | |
3077 | ||
2c10d571 DV |
3078 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3079 | ||
5bb61643 CW |
3080 | wait_event(dev_priv->pending_flip_queue, |
3081 | !intel_crtc_has_pending_flip(crtc)); | |
3082 | ||
0f91128d CW |
3083 | mutex_lock(&dev->struct_mutex); |
3084 | intel_finish_fb(crtc->fb); | |
3085 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
3086 | } |
3087 | ||
e615efe4 ED |
3088 | /* Program iCLKIP clock to the desired frequency */ |
3089 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3090 | { | |
3091 | struct drm_device *dev = crtc->dev; | |
3092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3093 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3094 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3095 | u32 temp; | |
3096 | ||
09153000 DV |
3097 | mutex_lock(&dev_priv->dpio_lock); |
3098 | ||
e615efe4 ED |
3099 | /* It is necessary to ungate the pixclk gate prior to programming |
3100 | * the divisors, and gate it back when it is done. | |
3101 | */ | |
3102 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3103 | ||
3104 | /* Disable SSCCTL */ | |
3105 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3106 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3107 | SBI_SSCCTL_DISABLE, | |
3108 | SBI_ICLK); | |
e615efe4 ED |
3109 | |
3110 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3111 | if (clock == 20000) { |
e615efe4 ED |
3112 | auxdiv = 1; |
3113 | divsel = 0x41; | |
3114 | phaseinc = 0x20; | |
3115 | } else { | |
3116 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3117 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3118 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3119 | * convert the virtual clock precision to KHz here for higher |
3120 | * precision. | |
3121 | */ | |
3122 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3123 | u32 iclk_pi_range = 64; | |
3124 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3125 | ||
12d7ceed | 3126 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3127 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3128 | pi_value = desired_divisor % iclk_pi_range; | |
3129 | ||
3130 | auxdiv = 0; | |
3131 | divsel = msb_divisor_value - 2; | |
3132 | phaseinc = pi_value; | |
3133 | } | |
3134 | ||
3135 | /* This should not happen with any sane values */ | |
3136 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3137 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3138 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3139 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3140 | ||
3141 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3142 | clock, |
e615efe4 ED |
3143 | auxdiv, |
3144 | divsel, | |
3145 | phasedir, | |
3146 | phaseinc); | |
3147 | ||
3148 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3149 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3150 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3151 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3152 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3153 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3154 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3155 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3156 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3157 | |
3158 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3159 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3160 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3161 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3162 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3163 | |
3164 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3165 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3166 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3167 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3168 | |
3169 | /* Wait for initialization time */ | |
3170 | udelay(24); | |
3171 | ||
3172 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3173 | |
3174 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3175 | } |
3176 | ||
275f01b2 DV |
3177 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3178 | enum pipe pch_transcoder) | |
3179 | { | |
3180 | struct drm_device *dev = crtc->base.dev; | |
3181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3182 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3183 | ||
3184 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3185 | I915_READ(HTOTAL(cpu_transcoder))); | |
3186 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3187 | I915_READ(HBLANK(cpu_transcoder))); | |
3188 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3189 | I915_READ(HSYNC(cpu_transcoder))); | |
3190 | ||
3191 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3192 | I915_READ(VTOTAL(cpu_transcoder))); | |
3193 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3194 | I915_READ(VBLANK(cpu_transcoder))); | |
3195 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3196 | I915_READ(VSYNC(cpu_transcoder))); | |
3197 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3198 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3199 | } | |
3200 | ||
1fbc0d78 DV |
3201 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3202 | { | |
3203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3204 | uint32_t temp; | |
3205 | ||
3206 | temp = I915_READ(SOUTH_CHICKEN1); | |
3207 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3208 | return; | |
3209 | ||
3210 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3211 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3212 | ||
3213 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3214 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3215 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3216 | POSTING_READ(SOUTH_CHICKEN1); | |
3217 | } | |
3218 | ||
3219 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3220 | { | |
3221 | struct drm_device *dev = intel_crtc->base.dev; | |
3222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3223 | ||
3224 | switch (intel_crtc->pipe) { | |
3225 | case PIPE_A: | |
3226 | break; | |
3227 | case PIPE_B: | |
3228 | if (intel_crtc->config.fdi_lanes > 2) | |
3229 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3230 | else | |
3231 | cpt_enable_fdi_bc_bifurcation(dev); | |
3232 | ||
3233 | break; | |
3234 | case PIPE_C: | |
3235 | cpt_enable_fdi_bc_bifurcation(dev); | |
3236 | ||
3237 | break; | |
3238 | default: | |
3239 | BUG(); | |
3240 | } | |
3241 | } | |
3242 | ||
f67a559d JB |
3243 | /* |
3244 | * Enable PCH resources required for PCH ports: | |
3245 | * - PCH PLLs | |
3246 | * - FDI training & RX/TX | |
3247 | * - update transcoder timings | |
3248 | * - DP transcoding bits | |
3249 | * - transcoder | |
3250 | */ | |
3251 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3252 | { |
3253 | struct drm_device *dev = crtc->dev; | |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3255 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3256 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3257 | u32 reg, temp; |
2c07245f | 3258 | |
ab9412ba | 3259 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3260 | |
1fbc0d78 DV |
3261 | if (IS_IVYBRIDGE(dev)) |
3262 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3263 | ||
cd986abb DV |
3264 | /* Write the TU size bits before fdi link training, so that error |
3265 | * detection works. */ | |
3266 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3267 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3268 | ||
c98e9dcf | 3269 | /* For PCH output, training FDI link */ |
674cf967 | 3270 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3271 | |
3ad8a208 DV |
3272 | /* We need to program the right clock selection before writing the pixel |
3273 | * mutliplier into the DPLL. */ | |
303b81e0 | 3274 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3275 | u32 sel; |
4b645f14 | 3276 | |
c98e9dcf | 3277 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3278 | temp |= TRANS_DPLL_ENABLE(pipe); |
3279 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3280 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3281 | temp |= sel; |
3282 | else | |
3283 | temp &= ~sel; | |
c98e9dcf | 3284 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3285 | } |
5eddb70b | 3286 | |
3ad8a208 DV |
3287 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3288 | * transcoder, and we actually should do this to not upset any PCH | |
3289 | * transcoder that already use the clock when we share it. | |
3290 | * | |
3291 | * Note that enable_shared_dpll tries to do the right thing, but | |
3292 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3293 | * the right LVDS enable sequence. */ | |
3294 | ironlake_enable_shared_dpll(intel_crtc); | |
3295 | ||
d9b6cb56 JB |
3296 | /* set transcoder timing, panel must allow it */ |
3297 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3298 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3299 | |
303b81e0 | 3300 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3301 | |
c98e9dcf JB |
3302 | /* For PCH DP, enable TRANS_DP_CTL */ |
3303 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3304 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3305 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3306 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3307 | reg = TRANS_DP_CTL(pipe); |
3308 | temp = I915_READ(reg); | |
3309 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3310 | TRANS_DP_SYNC_MASK | |
3311 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3312 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3313 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3314 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3315 | |
3316 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3317 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3318 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3319 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3320 | |
3321 | switch (intel_trans_dp_port_sel(crtc)) { | |
3322 | case PCH_DP_B: | |
5eddb70b | 3323 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3324 | break; |
3325 | case PCH_DP_C: | |
5eddb70b | 3326 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3327 | break; |
3328 | case PCH_DP_D: | |
5eddb70b | 3329 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3330 | break; |
3331 | default: | |
e95d41e1 | 3332 | BUG(); |
32f9d658 | 3333 | } |
2c07245f | 3334 | |
5eddb70b | 3335 | I915_WRITE(reg, temp); |
6be4a607 | 3336 | } |
b52eb4dc | 3337 | |
b8a4f404 | 3338 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3339 | } |
3340 | ||
1507e5bd PZ |
3341 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3342 | { | |
3343 | struct drm_device *dev = crtc->dev; | |
3344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3346 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3347 | |
ab9412ba | 3348 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3349 | |
8c52b5e8 | 3350 | lpt_program_iclkip(crtc); |
1507e5bd | 3351 | |
0540e488 | 3352 | /* Set transcoder timing. */ |
275f01b2 | 3353 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3354 | |
937bb610 | 3355 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3356 | } |
3357 | ||
e2b78267 | 3358 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3359 | { |
e2b78267 | 3360 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3361 | |
3362 | if (pll == NULL) | |
3363 | return; | |
3364 | ||
3365 | if (pll->refcount == 0) { | |
46edb027 | 3366 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3367 | return; |
3368 | } | |
3369 | ||
f4a091c7 DV |
3370 | if (--pll->refcount == 0) { |
3371 | WARN_ON(pll->on); | |
3372 | WARN_ON(pll->active); | |
3373 | } | |
3374 | ||
a43f6e0f | 3375 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3376 | } |
3377 | ||
b89a1d39 | 3378 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3379 | { |
e2b78267 DV |
3380 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3381 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3382 | enum intel_dpll_id i; | |
ee7b9f93 | 3383 | |
ee7b9f93 | 3384 | if (pll) { |
46edb027 DV |
3385 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3386 | crtc->base.base.id, pll->name); | |
e2b78267 | 3387 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3388 | } |
3389 | ||
98b6bd99 DV |
3390 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3391 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3392 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3393 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3394 | |
46edb027 DV |
3395 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3396 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3397 | |
3398 | goto found; | |
3399 | } | |
3400 | ||
e72f9fbf DV |
3401 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3402 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3403 | |
3404 | /* Only want to check enabled timings first */ | |
3405 | if (pll->refcount == 0) | |
3406 | continue; | |
3407 | ||
b89a1d39 DV |
3408 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3409 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3410 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3411 | crtc->base.base.id, |
46edb027 | 3412 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3413 | |
3414 | goto found; | |
3415 | } | |
3416 | } | |
3417 | ||
3418 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3419 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3420 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3421 | if (pll->refcount == 0) { |
46edb027 DV |
3422 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3423 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3424 | goto found; |
3425 | } | |
3426 | } | |
3427 | ||
3428 | return NULL; | |
3429 | ||
3430 | found: | |
a43f6e0f | 3431 | crtc->config.shared_dpll = i; |
46edb027 DV |
3432 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3433 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3434 | |
cdbd2316 | 3435 | if (pll->active == 0) { |
66e985c0 DV |
3436 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3437 | sizeof(pll->hw_state)); | |
3438 | ||
46edb027 | 3439 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3440 | WARN_ON(pll->on); |
e9d6944e | 3441 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3442 | |
15bdd4cf | 3443 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3444 | } |
3445 | pll->refcount++; | |
e04c7350 | 3446 | |
ee7b9f93 JB |
3447 | return pll; |
3448 | } | |
3449 | ||
a1520318 | 3450 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3451 | { |
3452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3453 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3454 | u32 temp; |
3455 | ||
3456 | temp = I915_READ(dslreg); | |
3457 | udelay(500); | |
3458 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3459 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3460 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3461 | } |
3462 | } | |
3463 | ||
b074cec8 JB |
3464 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3465 | { | |
3466 | struct drm_device *dev = crtc->base.dev; | |
3467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3468 | int pipe = crtc->pipe; | |
3469 | ||
fd4daa9c | 3470 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3471 | /* Force use of hard-coded filter coefficients |
3472 | * as some pre-programmed values are broken, | |
3473 | * e.g. x201. | |
3474 | */ | |
3475 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3476 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3477 | PF_PIPE_SEL_IVB(pipe)); | |
3478 | else | |
3479 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3480 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3481 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3482 | } |
3483 | } | |
3484 | ||
bb53d4ae VS |
3485 | static void intel_enable_planes(struct drm_crtc *crtc) |
3486 | { | |
3487 | struct drm_device *dev = crtc->dev; | |
3488 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3489 | struct intel_plane *intel_plane; | |
3490 | ||
3491 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3492 | if (intel_plane->pipe == pipe) | |
3493 | intel_plane_restore(&intel_plane->base); | |
3494 | } | |
3495 | ||
3496 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3497 | { | |
3498 | struct drm_device *dev = crtc->dev; | |
3499 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3500 | struct intel_plane *intel_plane; | |
3501 | ||
3502 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3503 | if (intel_plane->pipe == pipe) | |
3504 | intel_plane_disable(&intel_plane->base); | |
3505 | } | |
3506 | ||
20bc8673 | 3507 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3508 | { |
3509 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3510 | ||
3511 | if (!crtc->config.ips_enabled) | |
3512 | return; | |
3513 | ||
3514 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3515 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3516 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3517 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3518 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3519 | if (IS_BROADWELL(crtc->base.dev)) { |
3520 | mutex_lock(&dev_priv->rps.hw_lock); | |
3521 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3522 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3523 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3524 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3525 | * mailbox." Moreover, the mailbox may return a bogus state, |
3526 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3527 | */ |
3528 | } else { | |
3529 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3530 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3531 | * is essentially intel_wait_for_vblank. If we don't have this | |
3532 | * and don't wait for vblanks until the end of crtc_enable, then | |
3533 | * the HW state readout code will complain that the expected | |
3534 | * IPS_CTL value is not the one we read. */ | |
3535 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3536 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3537 | } | |
d77e4531 PZ |
3538 | } |
3539 | ||
20bc8673 | 3540 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3541 | { |
3542 | struct drm_device *dev = crtc->base.dev; | |
3543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3544 | ||
3545 | if (!crtc->config.ips_enabled) | |
3546 | return; | |
3547 | ||
3548 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3549 | if (IS_BROADWELL(crtc->base.dev)) { |
3550 | mutex_lock(&dev_priv->rps.hw_lock); | |
3551 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3552 | mutex_unlock(&dev_priv->rps.hw_lock); | |
e59150dc | 3553 | } else { |
2a114cc1 | 3554 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3555 | POSTING_READ(IPS_CTL); |
3556 | } | |
d77e4531 PZ |
3557 | |
3558 | /* We need to wait for a vblank before we can disable the plane. */ | |
3559 | intel_wait_for_vblank(dev, crtc->pipe); | |
3560 | } | |
3561 | ||
3562 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3563 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3564 | { | |
3565 | struct drm_device *dev = crtc->dev; | |
3566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3568 | enum pipe pipe = intel_crtc->pipe; | |
3569 | int palreg = PALETTE(pipe); | |
3570 | int i; | |
3571 | bool reenable_ips = false; | |
3572 | ||
3573 | /* The clocks have to be on to load the palette. */ | |
3574 | if (!crtc->enabled || !intel_crtc->active) | |
3575 | return; | |
3576 | ||
3577 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3578 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3579 | assert_dsi_pll_enabled(dev_priv); | |
3580 | else | |
3581 | assert_pll_enabled(dev_priv, pipe); | |
3582 | } | |
3583 | ||
3584 | /* use legacy palette for Ironlake */ | |
3585 | if (HAS_PCH_SPLIT(dev)) | |
3586 | palreg = LGC_PALETTE(pipe); | |
3587 | ||
3588 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3589 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3590 | */ | |
41e6fc4c | 3591 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3592 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3593 | GAMMA_MODE_MODE_SPLIT)) { | |
3594 | hsw_disable_ips(intel_crtc); | |
3595 | reenable_ips = true; | |
3596 | } | |
3597 | ||
3598 | for (i = 0; i < 256; i++) { | |
3599 | I915_WRITE(palreg + 4 * i, | |
3600 | (intel_crtc->lut_r[i] << 16) | | |
3601 | (intel_crtc->lut_g[i] << 8) | | |
3602 | intel_crtc->lut_b[i]); | |
3603 | } | |
3604 | ||
3605 | if (reenable_ips) | |
3606 | hsw_enable_ips(intel_crtc); | |
3607 | } | |
3608 | ||
f67a559d JB |
3609 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3610 | { | |
3611 | struct drm_device *dev = crtc->dev; | |
3612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3614 | struct intel_encoder *encoder; |
f67a559d JB |
3615 | int pipe = intel_crtc->pipe; |
3616 | int plane = intel_crtc->plane; | |
f67a559d | 3617 | |
08a48469 DV |
3618 | WARN_ON(!crtc->enabled); |
3619 | ||
f67a559d JB |
3620 | if (intel_crtc->active) |
3621 | return; | |
3622 | ||
3623 | intel_crtc->active = true; | |
8664281b PZ |
3624 | |
3625 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3626 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3627 | ||
f6736a1a | 3628 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3629 | if (encoder->pre_enable) |
3630 | encoder->pre_enable(encoder); | |
f67a559d | 3631 | |
5bfe2ac0 | 3632 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3633 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3634 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3635 | * enabling. */ | |
88cefb6c | 3636 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3637 | } else { |
3638 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3639 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3640 | } | |
f67a559d | 3641 | |
b074cec8 | 3642 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3643 | |
9c54c0dd JB |
3644 | /* |
3645 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3646 | * clocks enabled | |
3647 | */ | |
3648 | intel_crtc_load_lut(crtc); | |
3649 | ||
f37fcc2a | 3650 | intel_update_watermarks(crtc); |
e1fdc473 | 3651 | intel_enable_pipe(intel_crtc); |
d1de00ef | 3652 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3653 | intel_enable_planes(crtc); |
5c38d48c | 3654 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3655 | |
5bfe2ac0 | 3656 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3657 | ironlake_pch_enable(crtc); |
c98e9dcf | 3658 | |
d1ebd816 | 3659 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3660 | intel_update_fbc(dev); |
d1ebd816 BW |
3661 | mutex_unlock(&dev->struct_mutex); |
3662 | ||
fa5c73b1 DV |
3663 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3664 | encoder->enable(encoder); | |
61b77ddd DV |
3665 | |
3666 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3667 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3668 | |
3669 | /* | |
3670 | * There seems to be a race in PCH platform hw (at least on some | |
3671 | * outputs) where an enabled pipe still completes any pageflip right | |
3672 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3673 | * as the first vblank happend, everything works as expected. Hence just | |
3674 | * wait for one vblank before returning to avoid strange things | |
3675 | * happening. | |
3676 | */ | |
3677 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3678 | } |
3679 | ||
42db64ef PZ |
3680 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3681 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3682 | { | |
f5adf94e | 3683 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3684 | } |
3685 | ||
dda9a66a VS |
3686 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3687 | { | |
3688 | struct drm_device *dev = crtc->dev; | |
3689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3691 | int pipe = intel_crtc->pipe; | |
3692 | int plane = intel_crtc->plane; | |
3693 | ||
d1de00ef | 3694 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3695 | intel_enable_planes(crtc); |
3696 | intel_crtc_update_cursor(crtc, true); | |
3697 | ||
3698 | hsw_enable_ips(intel_crtc); | |
3699 | ||
3700 | mutex_lock(&dev->struct_mutex); | |
3701 | intel_update_fbc(dev); | |
3702 | mutex_unlock(&dev->struct_mutex); | |
3703 | } | |
3704 | ||
3705 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3706 | { | |
3707 | struct drm_device *dev = crtc->dev; | |
3708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3709 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3710 | int pipe = intel_crtc->pipe; | |
3711 | int plane = intel_crtc->plane; | |
3712 | ||
3713 | intel_crtc_wait_for_pending_flips(crtc); | |
3714 | drm_vblank_off(dev, pipe); | |
3715 | ||
3716 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3717 | if (dev_priv->fbc.plane == plane) | |
3718 | intel_disable_fbc(dev); | |
3719 | ||
3720 | hsw_disable_ips(intel_crtc); | |
3721 | ||
3722 | intel_crtc_update_cursor(crtc, false); | |
3723 | intel_disable_planes(crtc); | |
d1de00ef | 3724 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3725 | } |
3726 | ||
e4916946 PZ |
3727 | /* |
3728 | * This implements the workaround described in the "notes" section of the mode | |
3729 | * set sequence documentation. When going from no pipes or single pipe to | |
3730 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3731 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3732 | */ | |
3733 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3734 | { | |
3735 | struct drm_device *dev = crtc->base.dev; | |
3736 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3737 | ||
3738 | /* We want to get the other_active_crtc only if there's only 1 other | |
3739 | * active crtc. */ | |
3740 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3741 | if (!crtc_it->active || crtc_it == crtc) | |
3742 | continue; | |
3743 | ||
3744 | if (other_active_crtc) | |
3745 | return; | |
3746 | ||
3747 | other_active_crtc = crtc_it; | |
3748 | } | |
3749 | if (!other_active_crtc) | |
3750 | return; | |
3751 | ||
3752 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3753 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3754 | } | |
3755 | ||
4f771f10 PZ |
3756 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3757 | { | |
3758 | struct drm_device *dev = crtc->dev; | |
3759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3761 | struct intel_encoder *encoder; | |
3762 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3763 | |
3764 | WARN_ON(!crtc->enabled); | |
3765 | ||
3766 | if (intel_crtc->active) | |
3767 | return; | |
3768 | ||
3769 | intel_crtc->active = true; | |
8664281b PZ |
3770 | |
3771 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3772 | if (intel_crtc->config.has_pch_encoder) | |
3773 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3774 | ||
5bfe2ac0 | 3775 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3776 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3777 | |
3778 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3779 | if (encoder->pre_enable) | |
3780 | encoder->pre_enable(encoder); | |
3781 | ||
1f544388 | 3782 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3783 | |
b074cec8 | 3784 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3785 | |
3786 | /* | |
3787 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3788 | * clocks enabled | |
3789 | */ | |
3790 | intel_crtc_load_lut(crtc); | |
3791 | ||
1f544388 | 3792 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3793 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3794 | |
f37fcc2a | 3795 | intel_update_watermarks(crtc); |
e1fdc473 | 3796 | intel_enable_pipe(intel_crtc); |
42db64ef | 3797 | |
5bfe2ac0 | 3798 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3799 | lpt_pch_enable(crtc); |
4f771f10 | 3800 | |
8807e55b | 3801 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3802 | encoder->enable(encoder); |
8807e55b JN |
3803 | intel_opregion_notify_encoder(encoder, true); |
3804 | } | |
4f771f10 | 3805 | |
e4916946 PZ |
3806 | /* If we change the relative order between pipe/planes enabling, we need |
3807 | * to change the workaround. */ | |
3808 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a | 3809 | haswell_crtc_enable_planes(crtc); |
4f771f10 PZ |
3810 | } |
3811 | ||
3f8dce3a DV |
3812 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3813 | { | |
3814 | struct drm_device *dev = crtc->base.dev; | |
3815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3816 | int pipe = crtc->pipe; | |
3817 | ||
3818 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3819 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3820 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3821 | I915_WRITE(PF_CTL(pipe), 0); |
3822 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3823 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3824 | } | |
3825 | } | |
3826 | ||
6be4a607 JB |
3827 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3828 | { | |
3829 | struct drm_device *dev = crtc->dev; | |
3830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3832 | struct intel_encoder *encoder; |
6be4a607 JB |
3833 | int pipe = intel_crtc->pipe; |
3834 | int plane = intel_crtc->plane; | |
5eddb70b | 3835 | u32 reg, temp; |
b52eb4dc | 3836 | |
ef9c3aee | 3837 | |
f7abfe8b CW |
3838 | if (!intel_crtc->active) |
3839 | return; | |
3840 | ||
ea9d758d DV |
3841 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3842 | encoder->disable(encoder); | |
3843 | ||
e6c3a2a6 | 3844 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3845 | drm_vblank_off(dev, pipe); |
913d8d11 | 3846 | |
5c3fe8b0 | 3847 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3848 | intel_disable_fbc(dev); |
2c07245f | 3849 | |
0d5b8c61 | 3850 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3851 | intel_disable_planes(crtc); |
d1de00ef | 3852 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3853 | |
d925c59a DV |
3854 | if (intel_crtc->config.has_pch_encoder) |
3855 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3856 | ||
b24e7179 | 3857 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3858 | |
3f8dce3a | 3859 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3860 | |
bf49ec8c DV |
3861 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3862 | if (encoder->post_disable) | |
3863 | encoder->post_disable(encoder); | |
2c07245f | 3864 | |
d925c59a DV |
3865 | if (intel_crtc->config.has_pch_encoder) { |
3866 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3867 | |
d925c59a DV |
3868 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3869 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3870 | |
d925c59a DV |
3871 | if (HAS_PCH_CPT(dev)) { |
3872 | /* disable TRANS_DP_CTL */ | |
3873 | reg = TRANS_DP_CTL(pipe); | |
3874 | temp = I915_READ(reg); | |
3875 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3876 | TRANS_DP_PORT_SEL_MASK); | |
3877 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3878 | I915_WRITE(reg, temp); | |
3879 | ||
3880 | /* disable DPLL_SEL */ | |
3881 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3882 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3883 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3884 | } |
e3421a18 | 3885 | |
d925c59a | 3886 | /* disable PCH DPLL */ |
e72f9fbf | 3887 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3888 | |
d925c59a DV |
3889 | ironlake_fdi_pll_disable(intel_crtc); |
3890 | } | |
6b383a7f | 3891 | |
f7abfe8b | 3892 | intel_crtc->active = false; |
46ba614c | 3893 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3894 | |
3895 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3896 | intel_update_fbc(dev); |
d1ebd816 | 3897 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3898 | } |
1b3c7a47 | 3899 | |
4f771f10 | 3900 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3901 | { |
4f771f10 PZ |
3902 | struct drm_device *dev = crtc->dev; |
3903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3904 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3905 | struct intel_encoder *encoder; |
3906 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3907 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3908 | |
4f771f10 PZ |
3909 | if (!intel_crtc->active) |
3910 | return; | |
3911 | ||
dda9a66a VS |
3912 | haswell_crtc_disable_planes(crtc); |
3913 | ||
8807e55b JN |
3914 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3915 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3916 | encoder->disable(encoder); |
8807e55b | 3917 | } |
4f771f10 | 3918 | |
8664281b PZ |
3919 | if (intel_crtc->config.has_pch_encoder) |
3920 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3921 | intel_disable_pipe(dev_priv, pipe); |
3922 | ||
ad80a810 | 3923 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3924 | |
3f8dce3a | 3925 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3926 | |
1f544388 | 3927 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3928 | |
3929 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3930 | if (encoder->post_disable) | |
3931 | encoder->post_disable(encoder); | |
3932 | ||
88adfff1 | 3933 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3934 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3935 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3936 | intel_ddi_fdi_disable(crtc); |
83616634 | 3937 | } |
4f771f10 PZ |
3938 | |
3939 | intel_crtc->active = false; | |
46ba614c | 3940 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3941 | |
3942 | mutex_lock(&dev->struct_mutex); | |
3943 | intel_update_fbc(dev); | |
3944 | mutex_unlock(&dev->struct_mutex); | |
3945 | } | |
3946 | ||
ee7b9f93 JB |
3947 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3948 | { | |
3949 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3950 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3951 | } |
3952 | ||
6441ab5f PZ |
3953 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3954 | { | |
3955 | intel_ddi_put_crtc_pll(crtc); | |
3956 | } | |
3957 | ||
02e792fb DV |
3958 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3959 | { | |
02e792fb | 3960 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3961 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3962 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3963 | |
23f09ce3 | 3964 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3965 | dev_priv->mm.interruptible = false; |
3966 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3967 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3968 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3969 | } |
02e792fb | 3970 | |
5dcdbcb0 CW |
3971 | /* Let userspace switch the overlay on again. In most cases userspace |
3972 | * has to recompute where to put it anyway. | |
3973 | */ | |
02e792fb DV |
3974 | } |
3975 | ||
61bc95c1 EE |
3976 | /** |
3977 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3978 | * cursor plane briefly if not already running after enabling the display | |
3979 | * plane. | |
3980 | * This workaround avoids occasional blank screens when self refresh is | |
3981 | * enabled. | |
3982 | */ | |
3983 | static void | |
3984 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3985 | { | |
3986 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3987 | ||
3988 | if ((cntl & CURSOR_MODE) == 0) { | |
3989 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3990 | ||
3991 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3992 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3993 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3994 | I915_WRITE(CURCNTR(pipe), cntl); | |
3995 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3996 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3997 | } | |
3998 | } | |
3999 | ||
2dd24552 JB |
4000 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4001 | { | |
4002 | struct drm_device *dev = crtc->base.dev; | |
4003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4004 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4005 | ||
328d8e82 | 4006 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4007 | return; |
4008 | ||
2dd24552 | 4009 | /* |
c0b03411 DV |
4010 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4011 | * according to register description and PRM. | |
2dd24552 | 4012 | */ |
c0b03411 DV |
4013 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4014 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4015 | |
b074cec8 JB |
4016 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4017 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4018 | |
4019 | /* Border color in case we don't scale up to the full screen. Black by | |
4020 | * default, change to something else for debugging. */ | |
4021 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4022 | } |
4023 | ||
77d22dca ID |
4024 | #define for_each_power_domain(domain, mask) \ |
4025 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4026 | if ((1 << (domain)) & (mask)) | |
4027 | ||
319be8ae ID |
4028 | enum intel_display_power_domain |
4029 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4030 | { | |
4031 | struct drm_device *dev = intel_encoder->base.dev; | |
4032 | struct intel_digital_port *intel_dig_port; | |
4033 | ||
4034 | switch (intel_encoder->type) { | |
4035 | case INTEL_OUTPUT_UNKNOWN: | |
4036 | /* Only DDI platforms should ever use this output type */ | |
4037 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4038 | case INTEL_OUTPUT_DISPLAYPORT: | |
4039 | case INTEL_OUTPUT_HDMI: | |
4040 | case INTEL_OUTPUT_EDP: | |
4041 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4042 | switch (intel_dig_port->port) { | |
4043 | case PORT_A: | |
4044 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4045 | case PORT_B: | |
4046 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4047 | case PORT_C: | |
4048 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4049 | case PORT_D: | |
4050 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4051 | default: | |
4052 | WARN_ON_ONCE(1); | |
4053 | return POWER_DOMAIN_PORT_OTHER; | |
4054 | } | |
4055 | case INTEL_OUTPUT_ANALOG: | |
4056 | return POWER_DOMAIN_PORT_CRT; | |
4057 | case INTEL_OUTPUT_DSI: | |
4058 | return POWER_DOMAIN_PORT_DSI; | |
4059 | default: | |
4060 | return POWER_DOMAIN_PORT_OTHER; | |
4061 | } | |
4062 | } | |
4063 | ||
4064 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4065 | { |
319be8ae ID |
4066 | struct drm_device *dev = crtc->dev; |
4067 | struct intel_encoder *intel_encoder; | |
4068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4069 | enum pipe pipe = intel_crtc->pipe; | |
4070 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4071 | unsigned long mask; |
4072 | enum transcoder transcoder; | |
4073 | ||
4074 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4075 | ||
4076 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4077 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4078 | if (pfit_enabled) | |
4079 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4080 | ||
319be8ae ID |
4081 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4082 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4083 | ||
77d22dca ID |
4084 | return mask; |
4085 | } | |
4086 | ||
4087 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4088 | bool enable) | |
4089 | { | |
4090 | if (dev_priv->power_domains.init_power_on == enable) | |
4091 | return; | |
4092 | ||
4093 | if (enable) | |
4094 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4095 | else | |
4096 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4097 | ||
4098 | dev_priv->power_domains.init_power_on = enable; | |
4099 | } | |
4100 | ||
4101 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4102 | { | |
4103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4104 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4105 | struct intel_crtc *crtc; | |
4106 | ||
4107 | /* | |
4108 | * First get all needed power domains, then put all unneeded, to avoid | |
4109 | * any unnecessary toggling of the power wells. | |
4110 | */ | |
4111 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
4112 | enum intel_display_power_domain domain; | |
4113 | ||
4114 | if (!crtc->base.enabled) | |
4115 | continue; | |
4116 | ||
319be8ae | 4117 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4118 | |
4119 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4120 | intel_display_power_get(dev_priv, domain); | |
4121 | } | |
4122 | ||
4123 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
4124 | enum intel_display_power_domain domain; | |
4125 | ||
4126 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4127 | intel_display_power_put(dev_priv, domain); | |
4128 | ||
4129 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4130 | } | |
4131 | ||
4132 | intel_display_set_init_power(dev_priv, false); | |
4133 | } | |
4134 | ||
586f49dc | 4135 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4136 | { |
586f49dc | 4137 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4138 | |
586f49dc JB |
4139 | /* Obtain SKU information */ |
4140 | mutex_lock(&dev_priv->dpio_lock); | |
4141 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4142 | CCK_FUSE_HPLL_FREQ_MASK; | |
4143 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4144 | |
586f49dc | 4145 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4146 | } |
4147 | ||
4148 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4149 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4150 | { | |
4151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4152 | u32 val, cmd; | |
4153 | ||
4154 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
4155 | cmd = 2; | |
4156 | else if (cdclk == 266) | |
4157 | cmd = 1; | |
4158 | else | |
4159 | cmd = 0; | |
4160 | ||
4161 | mutex_lock(&dev_priv->rps.hw_lock); | |
4162 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4163 | val &= ~DSPFREQGUAR_MASK; | |
4164 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4165 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4166 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4167 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4168 | 50)) { | |
4169 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4170 | } | |
4171 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4172 | ||
4173 | if (cdclk == 400) { | |
4174 | u32 divider, vco; | |
4175 | ||
4176 | vco = valleyview_get_vco(dev_priv); | |
4177 | divider = ((vco << 1) / cdclk) - 1; | |
4178 | ||
4179 | mutex_lock(&dev_priv->dpio_lock); | |
4180 | /* adjust cdclk divider */ | |
4181 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4182 | val &= ~0xf; | |
4183 | val |= divider; | |
4184 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4185 | mutex_unlock(&dev_priv->dpio_lock); | |
4186 | } | |
4187 | ||
4188 | mutex_lock(&dev_priv->dpio_lock); | |
4189 | /* adjust self-refresh exit latency value */ | |
4190 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4191 | val &= ~0x7f; | |
4192 | ||
4193 | /* | |
4194 | * For high bandwidth configs, we set a higher latency in the bunit | |
4195 | * so that the core display fetch happens in time to avoid underruns. | |
4196 | */ | |
4197 | if (cdclk == 400) | |
4198 | val |= 4500 / 250; /* 4.5 usec */ | |
4199 | else | |
4200 | val |= 3000 / 250; /* 3.0 usec */ | |
4201 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4202 | mutex_unlock(&dev_priv->dpio_lock); | |
4203 | ||
4204 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4205 | intel_i2c_reset(dev); | |
4206 | } | |
4207 | ||
4208 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4209 | { | |
4210 | int cur_cdclk, vco; | |
4211 | int divider; | |
4212 | ||
4213 | vco = valleyview_get_vco(dev_priv); | |
4214 | ||
4215 | mutex_lock(&dev_priv->dpio_lock); | |
4216 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4217 | mutex_unlock(&dev_priv->dpio_lock); | |
4218 | ||
4219 | divider &= 0xf; | |
4220 | ||
4221 | cur_cdclk = (vco << 1) / (divider + 1); | |
4222 | ||
4223 | return cur_cdclk; | |
4224 | } | |
4225 | ||
4226 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4227 | int max_pixclk) | |
4228 | { | |
4229 | int cur_cdclk; | |
4230 | ||
4231 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4232 | ||
4233 | /* | |
4234 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4235 | * 200MHz | |
4236 | * 267MHz | |
4237 | * 320MHz | |
4238 | * 400MHz | |
4239 | * So we check to see whether we're above 90% of the lower bin and | |
4240 | * adjust if needed. | |
4241 | */ | |
4242 | if (max_pixclk > 288000) { | |
4243 | return 400; | |
4244 | } else if (max_pixclk > 240000) { | |
4245 | return 320; | |
4246 | } else | |
4247 | return 266; | |
4248 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4249 | } | |
4250 | ||
2f2d7aa1 VS |
4251 | /* compute the max pixel clock for new configuration */ |
4252 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4253 | { |
4254 | struct drm_device *dev = dev_priv->dev; | |
4255 | struct intel_crtc *intel_crtc; | |
4256 | int max_pixclk = 0; | |
4257 | ||
4258 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4259 | base.head) { | |
2f2d7aa1 | 4260 | if (intel_crtc->new_enabled) |
30a970c6 | 4261 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4262 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4263 | } |
4264 | ||
4265 | return max_pixclk; | |
4266 | } | |
4267 | ||
4268 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4269 | unsigned *prepare_pipes) |
30a970c6 JB |
4270 | { |
4271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4272 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4273 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4274 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4275 | ||
4276 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4277 | return; | |
4278 | ||
2f2d7aa1 | 4279 | /* disable/enable all currently active pipes while we change cdclk */ |
30a970c6 JB |
4280 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
4281 | base.head) | |
4282 | if (intel_crtc->base.enabled) | |
4283 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4284 | } | |
4285 | ||
4286 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4287 | { | |
4288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4289 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4290 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); |
4291 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4292 | ||
4293 | if (req_cdclk != cur_cdclk) | |
4294 | valleyview_set_cdclk(dev, req_cdclk); | |
77961eb9 | 4295 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4296 | } |
4297 | ||
89b667f8 JB |
4298 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4299 | { | |
4300 | struct drm_device *dev = crtc->dev; | |
4301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4303 | struct intel_encoder *encoder; | |
4304 | int pipe = intel_crtc->pipe; | |
4305 | int plane = intel_crtc->plane; | |
23538ef1 | 4306 | bool is_dsi; |
89b667f8 JB |
4307 | |
4308 | WARN_ON(!crtc->enabled); | |
4309 | ||
4310 | if (intel_crtc->active) | |
4311 | return; | |
4312 | ||
4313 | intel_crtc->active = true; | |
89b667f8 | 4314 | |
89b667f8 JB |
4315 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4316 | if (encoder->pre_pll_enable) | |
4317 | encoder->pre_pll_enable(encoder); | |
4318 | ||
23538ef1 JN |
4319 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4320 | ||
e9fd1c02 JN |
4321 | if (!is_dsi) |
4322 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4323 | |
4324 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4325 | if (encoder->pre_enable) | |
4326 | encoder->pre_enable(encoder); | |
4327 | ||
2dd24552 JB |
4328 | i9xx_pfit_enable(intel_crtc); |
4329 | ||
63cbb074 VS |
4330 | intel_crtc_load_lut(crtc); |
4331 | ||
f37fcc2a | 4332 | intel_update_watermarks(crtc); |
e1fdc473 | 4333 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4334 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4335 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4336 | intel_enable_planes(crtc); |
5c38d48c | 4337 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4338 | |
89b667f8 | 4339 | intel_update_fbc(dev); |
5004945f JN |
4340 | |
4341 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4342 | encoder->enable(encoder); | |
89b667f8 JB |
4343 | } |
4344 | ||
0b8765c6 | 4345 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4346 | { |
4347 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4348 | struct drm_i915_private *dev_priv = dev->dev_private; |
4349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4350 | struct intel_encoder *encoder; |
79e53945 | 4351 | int pipe = intel_crtc->pipe; |
80824003 | 4352 | int plane = intel_crtc->plane; |
79e53945 | 4353 | |
08a48469 DV |
4354 | WARN_ON(!crtc->enabled); |
4355 | ||
f7abfe8b CW |
4356 | if (intel_crtc->active) |
4357 | return; | |
4358 | ||
4359 | intel_crtc->active = true; | |
6b383a7f | 4360 | |
9d6d9f19 MK |
4361 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4362 | if (encoder->pre_enable) | |
4363 | encoder->pre_enable(encoder); | |
4364 | ||
f6736a1a DV |
4365 | i9xx_enable_pll(intel_crtc); |
4366 | ||
2dd24552 JB |
4367 | i9xx_pfit_enable(intel_crtc); |
4368 | ||
63cbb074 VS |
4369 | intel_crtc_load_lut(crtc); |
4370 | ||
f37fcc2a | 4371 | intel_update_watermarks(crtc); |
e1fdc473 | 4372 | intel_enable_pipe(intel_crtc); |
2d9d2b0b | 4373 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
d1de00ef | 4374 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4375 | intel_enable_planes(crtc); |
22e407d7 | 4376 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4377 | if (IS_G4X(dev)) |
4378 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4379 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4380 | |
0b8765c6 JB |
4381 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4382 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4383 | |
f440eb13 | 4384 | intel_update_fbc(dev); |
ef9c3aee | 4385 | |
fa5c73b1 DV |
4386 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4387 | encoder->enable(encoder); | |
0b8765c6 | 4388 | } |
79e53945 | 4389 | |
87476d63 DV |
4390 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4391 | { | |
4392 | struct drm_device *dev = crtc->base.dev; | |
4393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4394 | |
328d8e82 DV |
4395 | if (!crtc->config.gmch_pfit.control) |
4396 | return; | |
87476d63 | 4397 | |
328d8e82 | 4398 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4399 | |
328d8e82 DV |
4400 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4401 | I915_READ(PFIT_CONTROL)); | |
4402 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4403 | } |
4404 | ||
0b8765c6 JB |
4405 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4406 | { | |
4407 | struct drm_device *dev = crtc->dev; | |
4408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4409 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4410 | struct intel_encoder *encoder; |
0b8765c6 JB |
4411 | int pipe = intel_crtc->pipe; |
4412 | int plane = intel_crtc->plane; | |
ef9c3aee | 4413 | |
f7abfe8b CW |
4414 | if (!intel_crtc->active) |
4415 | return; | |
4416 | ||
ea9d758d DV |
4417 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4418 | encoder->disable(encoder); | |
4419 | ||
0b8765c6 | 4420 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4421 | intel_crtc_wait_for_pending_flips(crtc); |
4422 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4423 | |
5c3fe8b0 | 4424 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4425 | intel_disable_fbc(dev); |
79e53945 | 4426 | |
0d5b8c61 VS |
4427 | intel_crtc_dpms_overlay(intel_crtc, false); |
4428 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4429 | intel_disable_planes(crtc); |
d1de00ef | 4430 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4431 | |
2d9d2b0b | 4432 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); |
b24e7179 | 4433 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4434 | |
87476d63 | 4435 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4436 | |
89b667f8 JB |
4437 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4438 | if (encoder->post_disable) | |
4439 | encoder->post_disable(encoder); | |
4440 | ||
f6071166 JB |
4441 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4442 | vlv_disable_pll(dev_priv, pipe); | |
4443 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4444 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4445 | |
f7abfe8b | 4446 | intel_crtc->active = false; |
46ba614c | 4447 | intel_update_watermarks(crtc); |
f37fcc2a | 4448 | |
6b383a7f | 4449 | intel_update_fbc(dev); |
0b8765c6 JB |
4450 | } |
4451 | ||
ee7b9f93 JB |
4452 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4453 | { | |
4454 | } | |
4455 | ||
976f8a20 DV |
4456 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4457 | bool enabled) | |
2c07245f ZW |
4458 | { |
4459 | struct drm_device *dev = crtc->dev; | |
4460 | struct drm_i915_master_private *master_priv; | |
4461 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4462 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4463 | |
4464 | if (!dev->primary->master) | |
4465 | return; | |
4466 | ||
4467 | master_priv = dev->primary->master->driver_priv; | |
4468 | if (!master_priv->sarea_priv) | |
4469 | return; | |
4470 | ||
79e53945 JB |
4471 | switch (pipe) { |
4472 | case 0: | |
4473 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4474 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4475 | break; | |
4476 | case 1: | |
4477 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4478 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4479 | break; | |
4480 | default: | |
9db4a9c7 | 4481 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4482 | break; |
4483 | } | |
79e53945 JB |
4484 | } |
4485 | ||
976f8a20 DV |
4486 | /** |
4487 | * Sets the power management mode of the pipe and plane. | |
4488 | */ | |
4489 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4490 | { | |
4491 | struct drm_device *dev = crtc->dev; | |
4492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4493 | struct intel_encoder *intel_encoder; | |
4494 | bool enable = false; | |
4495 | ||
4496 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4497 | enable |= intel_encoder->connectors_active; | |
4498 | ||
4499 | if (enable) | |
4500 | dev_priv->display.crtc_enable(crtc); | |
4501 | else | |
4502 | dev_priv->display.crtc_disable(crtc); | |
4503 | ||
4504 | intel_crtc_update_sarea(crtc, enable); | |
4505 | } | |
4506 | ||
cdd59983 CW |
4507 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4508 | { | |
cdd59983 | 4509 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4510 | struct drm_connector *connector; |
ee7b9f93 | 4511 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4513 | |
976f8a20 DV |
4514 | /* crtc should still be enabled when we disable it. */ |
4515 | WARN_ON(!crtc->enabled); | |
4516 | ||
4517 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4518 | intel_crtc->eld_vld = false; |
976f8a20 | 4519 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4520 | dev_priv->display.off(crtc); |
4521 | ||
931872fc | 4522 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4523 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4524 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4525 | |
4526 | if (crtc->fb) { | |
4527 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4528 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4529 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4530 | crtc->fb = NULL; |
4531 | } | |
4532 | ||
4533 | /* Update computed state. */ | |
4534 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4535 | if (!connector->encoder || !connector->encoder->crtc) | |
4536 | continue; | |
4537 | ||
4538 | if (connector->encoder->crtc != crtc) | |
4539 | continue; | |
4540 | ||
4541 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4542 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4543 | } |
4544 | } | |
4545 | ||
ea5b213a | 4546 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4547 | { |
4ef69c7a | 4548 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4549 | |
ea5b213a CW |
4550 | drm_encoder_cleanup(encoder); |
4551 | kfree(intel_encoder); | |
7e7d76c3 JB |
4552 | } |
4553 | ||
9237329d | 4554 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4555 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4556 | * state of the entire output pipe. */ | |
9237329d | 4557 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4558 | { |
5ab432ef DV |
4559 | if (mode == DRM_MODE_DPMS_ON) { |
4560 | encoder->connectors_active = true; | |
4561 | ||
b2cabb0e | 4562 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4563 | } else { |
4564 | encoder->connectors_active = false; | |
4565 | ||
b2cabb0e | 4566 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4567 | } |
79e53945 JB |
4568 | } |
4569 | ||
0a91ca29 DV |
4570 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4571 | * internal consistency). */ | |
b980514c | 4572 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4573 | { |
0a91ca29 DV |
4574 | if (connector->get_hw_state(connector)) { |
4575 | struct intel_encoder *encoder = connector->encoder; | |
4576 | struct drm_crtc *crtc; | |
4577 | bool encoder_enabled; | |
4578 | enum pipe pipe; | |
4579 | ||
4580 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4581 | connector->base.base.id, | |
4582 | drm_get_connector_name(&connector->base)); | |
4583 | ||
4584 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4585 | "wrong connector dpms state\n"); | |
4586 | WARN(connector->base.encoder != &encoder->base, | |
4587 | "active connector not linked to encoder\n"); | |
4588 | WARN(!encoder->connectors_active, | |
4589 | "encoder->connectors_active not set\n"); | |
4590 | ||
4591 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4592 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4593 | if (WARN_ON(!encoder->base.crtc)) | |
4594 | return; | |
4595 | ||
4596 | crtc = encoder->base.crtc; | |
4597 | ||
4598 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4599 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4600 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4601 | "encoder active on the wrong pipe\n"); | |
4602 | } | |
79e53945 JB |
4603 | } |
4604 | ||
5ab432ef DV |
4605 | /* Even simpler default implementation, if there's really no special case to |
4606 | * consider. */ | |
4607 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4608 | { |
5ab432ef DV |
4609 | /* All the simple cases only support two dpms states. */ |
4610 | if (mode != DRM_MODE_DPMS_ON) | |
4611 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4612 | |
5ab432ef DV |
4613 | if (mode == connector->dpms) |
4614 | return; | |
4615 | ||
4616 | connector->dpms = mode; | |
4617 | ||
4618 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4619 | if (connector->encoder) |
4620 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4621 | |
b980514c | 4622 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4623 | } |
4624 | ||
f0947c37 DV |
4625 | /* Simple connector->get_hw_state implementation for encoders that support only |
4626 | * one connector and no cloning and hence the encoder state determines the state | |
4627 | * of the connector. */ | |
4628 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4629 | { |
24929352 | 4630 | enum pipe pipe = 0; |
f0947c37 | 4631 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4632 | |
f0947c37 | 4633 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4634 | } |
4635 | ||
1857e1da DV |
4636 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4637 | struct intel_crtc_config *pipe_config) | |
4638 | { | |
4639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4640 | struct intel_crtc *pipe_B_crtc = | |
4641 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4642 | ||
4643 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4644 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4645 | if (pipe_config->fdi_lanes > 4) { | |
4646 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4647 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4648 | return false; | |
4649 | } | |
4650 | ||
bafb6553 | 4651 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4652 | if (pipe_config->fdi_lanes > 2) { |
4653 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4654 | pipe_config->fdi_lanes); | |
4655 | return false; | |
4656 | } else { | |
4657 | return true; | |
4658 | } | |
4659 | } | |
4660 | ||
4661 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4662 | return true; | |
4663 | ||
4664 | /* Ivybridge 3 pipe is really complicated */ | |
4665 | switch (pipe) { | |
4666 | case PIPE_A: | |
4667 | return true; | |
4668 | case PIPE_B: | |
4669 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4670 | pipe_config->fdi_lanes > 2) { | |
4671 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4672 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4673 | return false; | |
4674 | } | |
4675 | return true; | |
4676 | case PIPE_C: | |
1e833f40 | 4677 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4678 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4679 | if (pipe_config->fdi_lanes > 2) { | |
4680 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4681 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4682 | return false; | |
4683 | } | |
4684 | } else { | |
4685 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4686 | return false; | |
4687 | } | |
4688 | return true; | |
4689 | default: | |
4690 | BUG(); | |
4691 | } | |
4692 | } | |
4693 | ||
e29c22c0 DV |
4694 | #define RETRY 1 |
4695 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4696 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4697 | { |
1857e1da | 4698 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4699 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4700 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4701 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4702 | |
e29c22c0 | 4703 | retry: |
877d48d5 DV |
4704 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4705 | * each output octet as 10 bits. The actual frequency | |
4706 | * is stored as a divider into a 100MHz clock, and the | |
4707 | * mode pixel clock is stored in units of 1KHz. | |
4708 | * Hence the bw of each lane in terms of the mode signal | |
4709 | * is: | |
4710 | */ | |
4711 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4712 | ||
241bfc38 | 4713 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4714 | |
2bd89a07 | 4715 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4716 | pipe_config->pipe_bpp); |
4717 | ||
4718 | pipe_config->fdi_lanes = lane; | |
4719 | ||
2bd89a07 | 4720 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4721 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4722 | |
e29c22c0 DV |
4723 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4724 | intel_crtc->pipe, pipe_config); | |
4725 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4726 | pipe_config->pipe_bpp -= 2*3; | |
4727 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4728 | pipe_config->pipe_bpp); | |
4729 | needs_recompute = true; | |
4730 | pipe_config->bw_constrained = true; | |
4731 | ||
4732 | goto retry; | |
4733 | } | |
4734 | ||
4735 | if (needs_recompute) | |
4736 | return RETRY; | |
4737 | ||
4738 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4739 | } |
4740 | ||
42db64ef PZ |
4741 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4742 | struct intel_crtc_config *pipe_config) | |
4743 | { | |
d330a953 | 4744 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 4745 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 4746 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4747 | } |
4748 | ||
a43f6e0f | 4749 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4750 | struct intel_crtc_config *pipe_config) |
79e53945 | 4751 | { |
a43f6e0f | 4752 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4753 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4754 | |
ad3a4479 | 4755 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4756 | if (INTEL_INFO(dev)->gen < 4) { |
4757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4758 | int clock_limit = | |
4759 | dev_priv->display.get_display_clock_speed(dev); | |
4760 | ||
4761 | /* | |
4762 | * Enable pixel doubling when the dot clock | |
4763 | * is > 90% of the (display) core speed. | |
4764 | * | |
b397c96b VS |
4765 | * GDG double wide on either pipe, |
4766 | * otherwise pipe A only. | |
cf532bb2 | 4767 | */ |
b397c96b | 4768 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4769 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4770 | clock_limit *= 2; |
cf532bb2 | 4771 | pipe_config->double_wide = true; |
ad3a4479 VS |
4772 | } |
4773 | ||
241bfc38 | 4774 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4775 | return -EINVAL; |
2c07245f | 4776 | } |
89749350 | 4777 | |
1d1d0e27 VS |
4778 | /* |
4779 | * Pipe horizontal size must be even in: | |
4780 | * - DVO ganged mode | |
4781 | * - LVDS dual channel mode | |
4782 | * - Double wide pipe | |
4783 | */ | |
4784 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4785 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4786 | pipe_config->pipe_src_w &= ~1; | |
4787 | ||
8693a824 DL |
4788 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4789 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4790 | */ |
4791 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4792 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4793 | return -EINVAL; |
44f46b42 | 4794 | |
bd080ee5 | 4795 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4796 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4797 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4798 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4799 | * for lvds. */ | |
4800 | pipe_config->pipe_bpp = 8*3; | |
4801 | } | |
4802 | ||
f5adf94e | 4803 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4804 | hsw_compute_ips_config(crtc, pipe_config); |
4805 | ||
4806 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4807 | * clock survives for now. */ | |
4808 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4809 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4810 | |
877d48d5 | 4811 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4812 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4813 | |
e29c22c0 | 4814 | return 0; |
79e53945 JB |
4815 | } |
4816 | ||
25eb05fc JB |
4817 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4818 | { | |
4819 | return 400000; /* FIXME */ | |
4820 | } | |
4821 | ||
e70236a8 JB |
4822 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4823 | { | |
4824 | return 400000; | |
4825 | } | |
79e53945 | 4826 | |
e70236a8 | 4827 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4828 | { |
e70236a8 JB |
4829 | return 333000; |
4830 | } | |
79e53945 | 4831 | |
e70236a8 JB |
4832 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4833 | { | |
4834 | return 200000; | |
4835 | } | |
79e53945 | 4836 | |
257a7ffc DV |
4837 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4838 | { | |
4839 | u16 gcfgc = 0; | |
4840 | ||
4841 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4842 | ||
4843 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4844 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4845 | return 267000; | |
4846 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4847 | return 333000; | |
4848 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4849 | return 444000; | |
4850 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4851 | return 200000; | |
4852 | default: | |
4853 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4854 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4855 | return 133000; | |
4856 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4857 | return 167000; | |
4858 | } | |
4859 | } | |
4860 | ||
e70236a8 JB |
4861 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4862 | { | |
4863 | u16 gcfgc = 0; | |
79e53945 | 4864 | |
e70236a8 JB |
4865 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4866 | ||
4867 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4868 | return 133000; | |
4869 | else { | |
4870 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4871 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4872 | return 333000; | |
4873 | default: | |
4874 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4875 | return 190000; | |
79e53945 | 4876 | } |
e70236a8 JB |
4877 | } |
4878 | } | |
4879 | ||
4880 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4881 | { | |
4882 | return 266000; | |
4883 | } | |
4884 | ||
4885 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4886 | { | |
4887 | u16 hpllcc = 0; | |
4888 | /* Assume that the hardware is in the high speed state. This | |
4889 | * should be the default. | |
4890 | */ | |
4891 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4892 | case GC_CLOCK_133_200: | |
4893 | case GC_CLOCK_100_200: | |
4894 | return 200000; | |
4895 | case GC_CLOCK_166_250: | |
4896 | return 250000; | |
4897 | case GC_CLOCK_100_133: | |
79e53945 | 4898 | return 133000; |
e70236a8 | 4899 | } |
79e53945 | 4900 | |
e70236a8 JB |
4901 | /* Shouldn't happen */ |
4902 | return 0; | |
4903 | } | |
79e53945 | 4904 | |
e70236a8 JB |
4905 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4906 | { | |
4907 | return 133000; | |
79e53945 JB |
4908 | } |
4909 | ||
2c07245f | 4910 | static void |
a65851af | 4911 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4912 | { |
a65851af VS |
4913 | while (*num > DATA_LINK_M_N_MASK || |
4914 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4915 | *num >>= 1; |
4916 | *den >>= 1; | |
4917 | } | |
4918 | } | |
4919 | ||
a65851af VS |
4920 | static void compute_m_n(unsigned int m, unsigned int n, |
4921 | uint32_t *ret_m, uint32_t *ret_n) | |
4922 | { | |
4923 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4924 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4925 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4926 | } | |
4927 | ||
e69d0bc1 DV |
4928 | void |
4929 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4930 | int pixel_clock, int link_clock, | |
4931 | struct intel_link_m_n *m_n) | |
2c07245f | 4932 | { |
e69d0bc1 | 4933 | m_n->tu = 64; |
a65851af VS |
4934 | |
4935 | compute_m_n(bits_per_pixel * pixel_clock, | |
4936 | link_clock * nlanes * 8, | |
4937 | &m_n->gmch_m, &m_n->gmch_n); | |
4938 | ||
4939 | compute_m_n(pixel_clock, link_clock, | |
4940 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4941 | } |
4942 | ||
a7615030 CW |
4943 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4944 | { | |
d330a953 JN |
4945 | if (i915.panel_use_ssc >= 0) |
4946 | return i915.panel_use_ssc != 0; | |
41aa3448 | 4947 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4948 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4949 | } |
4950 | ||
c65d77d8 JB |
4951 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4952 | { | |
4953 | struct drm_device *dev = crtc->dev; | |
4954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4955 | int refclk; | |
4956 | ||
a0c4da24 | 4957 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4958 | refclk = 100000; |
a0c4da24 | 4959 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4960 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
4961 | refclk = dev_priv->vbt.lvds_ssc_freq; |
4962 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
4963 | } else if (!IS_GEN2(dev)) { |
4964 | refclk = 96000; | |
4965 | } else { | |
4966 | refclk = 48000; | |
4967 | } | |
4968 | ||
4969 | return refclk; | |
4970 | } | |
4971 | ||
7429e9d4 | 4972 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4973 | { |
7df00d7a | 4974 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4975 | } |
f47709a9 | 4976 | |
7429e9d4 DV |
4977 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4978 | { | |
4979 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4980 | } |
4981 | ||
f47709a9 | 4982 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4983 | intel_clock_t *reduced_clock) |
4984 | { | |
f47709a9 | 4985 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4986 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4987 | int pipe = crtc->pipe; |
a7516a05 JB |
4988 | u32 fp, fp2 = 0; |
4989 | ||
4990 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4991 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4992 | if (reduced_clock) |
7429e9d4 | 4993 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4994 | } else { |
7429e9d4 | 4995 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4996 | if (reduced_clock) |
7429e9d4 | 4997 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4998 | } |
4999 | ||
5000 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 5001 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5002 | |
f47709a9 DV |
5003 | crtc->lowfreq_avail = false; |
5004 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5005 | reduced_clock && i915.powersave) { |
a7516a05 | 5006 | I915_WRITE(FP1(pipe), fp2); |
8bcc2795 | 5007 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5008 | crtc->lowfreq_avail = true; |
a7516a05 JB |
5009 | } else { |
5010 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 5011 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5012 | } |
5013 | } | |
5014 | ||
5e69f97f CML |
5015 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5016 | pipe) | |
89b667f8 JB |
5017 | { |
5018 | u32 reg_val; | |
5019 | ||
5020 | /* | |
5021 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5022 | * and set it to a reasonable value instead. | |
5023 | */ | |
ab3c759a | 5024 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5025 | reg_val &= 0xffffff00; |
5026 | reg_val |= 0x00000030; | |
ab3c759a | 5027 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5028 | |
ab3c759a | 5029 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5030 | reg_val &= 0x8cffffff; |
5031 | reg_val = 0x8c000000; | |
ab3c759a | 5032 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5033 | |
ab3c759a | 5034 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5035 | reg_val &= 0xffffff00; |
ab3c759a | 5036 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5037 | |
ab3c759a | 5038 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5039 | reg_val &= 0x00ffffff; |
5040 | reg_val |= 0xb0000000; | |
ab3c759a | 5041 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5042 | } |
5043 | ||
b551842d DV |
5044 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5045 | struct intel_link_m_n *m_n) | |
5046 | { | |
5047 | struct drm_device *dev = crtc->base.dev; | |
5048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5049 | int pipe = crtc->pipe; | |
5050 | ||
e3b95f1e DV |
5051 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5052 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5053 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5054 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5055 | } |
5056 | ||
5057 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5058 | struct intel_link_m_n *m_n) | |
5059 | { | |
5060 | struct drm_device *dev = crtc->base.dev; | |
5061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5062 | int pipe = crtc->pipe; | |
5063 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5064 | ||
5065 | if (INTEL_INFO(dev)->gen >= 5) { | |
5066 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5067 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5068 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5069 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5070 | } else { | |
e3b95f1e DV |
5071 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5072 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5073 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5074 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5075 | } |
5076 | } | |
5077 | ||
03afc4a2 DV |
5078 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5079 | { | |
5080 | if (crtc->config.has_pch_encoder) | |
5081 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5082 | else | |
5083 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5084 | } | |
5085 | ||
f47709a9 | 5086 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 5087 | { |
f47709a9 | 5088 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5089 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5090 | int pipe = crtc->pipe; |
89b667f8 | 5091 | u32 dpll, mdiv; |
a0c4da24 | 5092 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 5093 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 5094 | |
09153000 DV |
5095 | mutex_lock(&dev_priv->dpio_lock); |
5096 | ||
f47709a9 DV |
5097 | bestn = crtc->config.dpll.n; |
5098 | bestm1 = crtc->config.dpll.m1; | |
5099 | bestm2 = crtc->config.dpll.m2; | |
5100 | bestp1 = crtc->config.dpll.p1; | |
5101 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5102 | |
89b667f8 JB |
5103 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5104 | ||
5105 | /* PLL B needs special handling */ | |
5106 | if (pipe) | |
5e69f97f | 5107 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5108 | |
5109 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5110 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5111 | |
5112 | /* Disable target IRef on PLL */ | |
ab3c759a | 5113 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5114 | reg_val &= 0x00ffffff; |
ab3c759a | 5115 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5116 | |
5117 | /* Disable fast lock */ | |
ab3c759a | 5118 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5119 | |
5120 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5121 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5122 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5123 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5124 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5125 | |
5126 | /* | |
5127 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5128 | * but we don't support that). | |
5129 | * Note: don't use the DAC post divider as it seems unstable. | |
5130 | */ | |
5131 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5132 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5133 | |
a0c4da24 | 5134 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5135 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5136 | |
89b667f8 | 5137 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5138 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5139 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5140 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5141 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5142 | 0x009f0003); |
89b667f8 | 5143 | else |
ab3c759a | 5144 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5145 | 0x00d0000f); |
5146 | ||
5147 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5148 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5149 | /* Use SSC source */ | |
5150 | if (!pipe) | |
ab3c759a | 5151 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5152 | 0x0df40000); |
5153 | else | |
ab3c759a | 5154 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5155 | 0x0df70000); |
5156 | } else { /* HDMI or VGA */ | |
5157 | /* Use bend source */ | |
5158 | if (!pipe) | |
ab3c759a | 5159 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5160 | 0x0df70000); |
5161 | else | |
ab3c759a | 5162 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5163 | 0x0df40000); |
5164 | } | |
a0c4da24 | 5165 | |
ab3c759a | 5166 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5167 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5168 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5169 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5170 | coreclk |= 0x01000000; | |
ab3c759a | 5171 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5172 | |
ab3c759a | 5173 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 5174 | |
e5cbfbfb ID |
5175 | /* |
5176 | * Enable DPIO clock input. We should never disable the reference | |
5177 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5178 | * on it. | |
5179 | */ | |
89b667f8 JB |
5180 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
5181 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
5182 | /* We should never disable this, set it here for state tracking */ |
5183 | if (pipe == PIPE_B) | |
89b667f8 | 5184 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 5185 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
5186 | crtc->config.dpll_hw_state.dpll = dpll; |
5187 | ||
ef1b460d DV |
5188 | dpll_md = (crtc->config.pixel_multiplier - 1) |
5189 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
5190 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
5191 | ||
89b667f8 JB |
5192 | if (crtc->config.has_dp_encoder) |
5193 | intel_dp_set_m_n(crtc); | |
09153000 DV |
5194 | |
5195 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
5196 | } |
5197 | ||
f47709a9 DV |
5198 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5199 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5200 | int num_connectors) |
5201 | { | |
f47709a9 | 5202 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5203 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5204 | u32 dpll; |
5205 | bool is_sdvo; | |
f47709a9 | 5206 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5207 | |
f47709a9 | 5208 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5209 | |
f47709a9 DV |
5210 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5211 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5212 | |
5213 | dpll = DPLL_VGA_MODE_DIS; | |
5214 | ||
f47709a9 | 5215 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5216 | dpll |= DPLLB_MODE_LVDS; |
5217 | else | |
5218 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5219 | |
ef1b460d | 5220 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5221 | dpll |= (crtc->config.pixel_multiplier - 1) |
5222 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5223 | } |
198a037f DV |
5224 | |
5225 | if (is_sdvo) | |
4a33e48d | 5226 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5227 | |
f47709a9 | 5228 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5229 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5230 | |
5231 | /* compute bitmask from p1 value */ | |
5232 | if (IS_PINEVIEW(dev)) | |
5233 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5234 | else { | |
5235 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5236 | if (IS_G4X(dev) && reduced_clock) | |
5237 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5238 | } | |
5239 | switch (clock->p2) { | |
5240 | case 5: | |
5241 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5242 | break; | |
5243 | case 7: | |
5244 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5245 | break; | |
5246 | case 10: | |
5247 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5248 | break; | |
5249 | case 14: | |
5250 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5251 | break; | |
5252 | } | |
5253 | if (INTEL_INFO(dev)->gen >= 4) | |
5254 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5255 | ||
09ede541 | 5256 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5257 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5258 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5259 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5260 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5261 | else | |
5262 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5263 | ||
5264 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5265 | crtc->config.dpll_hw_state.dpll = dpll; |
5266 | ||
eb1cbe48 | 5267 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5268 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5269 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5270 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5271 | } |
66e3d5c0 DV |
5272 | |
5273 | if (crtc->config.has_dp_encoder) | |
5274 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5275 | } |
5276 | ||
f47709a9 | 5277 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5278 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5279 | int num_connectors) |
5280 | { | |
f47709a9 | 5281 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5282 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5283 | u32 dpll; |
f47709a9 | 5284 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5285 | |
f47709a9 | 5286 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5287 | |
eb1cbe48 DV |
5288 | dpll = DPLL_VGA_MODE_DIS; |
5289 | ||
f47709a9 | 5290 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5291 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5292 | } else { | |
5293 | if (clock->p1 == 2) | |
5294 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5295 | else | |
5296 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5297 | if (clock->p2 == 4) | |
5298 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5299 | } | |
5300 | ||
4a33e48d DV |
5301 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5302 | dpll |= DPLL_DVO_2X_MODE; | |
5303 | ||
f47709a9 | 5304 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5305 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5306 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5307 | else | |
5308 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5309 | ||
5310 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5311 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5312 | } |
5313 | ||
8a654f3b | 5314 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5315 | { |
5316 | struct drm_device *dev = intel_crtc->base.dev; | |
5317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5318 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5319 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5320 | struct drm_display_mode *adjusted_mode = |
5321 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5322 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5323 | ||
5324 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5325 | * the hw state checker will get angry at the mismatch. */ | |
5326 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5327 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5328 | |
5329 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5330 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5331 | crtc_vtotal -= 1; |
5332 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5333 | vsyncshift = adjusted_mode->crtc_hsync_start |
5334 | - adjusted_mode->crtc_htotal / 2; | |
5335 | } else { | |
5336 | vsyncshift = 0; | |
5337 | } | |
5338 | ||
5339 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5340 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5341 | |
fe2b8f9d | 5342 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5343 | (adjusted_mode->crtc_hdisplay - 1) | |
5344 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5345 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5346 | (adjusted_mode->crtc_hblank_start - 1) | |
5347 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5348 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5349 | (adjusted_mode->crtc_hsync_start - 1) | |
5350 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5351 | ||
fe2b8f9d | 5352 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5353 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5354 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5355 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5356 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5357 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5358 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5359 | (adjusted_mode->crtc_vsync_start - 1) | |
5360 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5361 | ||
b5e508d4 PZ |
5362 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5363 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5364 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5365 | * bits. */ | |
5366 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5367 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5368 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5369 | ||
b0e77b9c PZ |
5370 | /* pipesrc controls the size that is scaled from, which should |
5371 | * always be the user's requested size. | |
5372 | */ | |
5373 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5374 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5375 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5376 | } |
5377 | ||
1bd1bd80 DV |
5378 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5379 | struct intel_crtc_config *pipe_config) | |
5380 | { | |
5381 | struct drm_device *dev = crtc->base.dev; | |
5382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5383 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5384 | uint32_t tmp; | |
5385 | ||
5386 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5387 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5388 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5389 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5390 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5391 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5392 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5393 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5394 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5395 | ||
5396 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5397 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5398 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5399 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5400 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5401 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5402 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5403 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5404 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5405 | ||
5406 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5407 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5408 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5409 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5410 | } | |
5411 | ||
5412 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5413 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5414 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5415 | ||
5416 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5417 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5418 | } |
5419 | ||
f6a83288 DV |
5420 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5421 | struct intel_crtc_config *pipe_config) | |
babea61d | 5422 | { |
f6a83288 DV |
5423 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5424 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5425 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5426 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5427 | |
f6a83288 DV |
5428 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5429 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5430 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5431 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5432 | |
f6a83288 | 5433 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5434 | |
f6a83288 DV |
5435 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5436 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5437 | } |
5438 | ||
84b046f3 DV |
5439 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5440 | { | |
5441 | struct drm_device *dev = intel_crtc->base.dev; | |
5442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5443 | uint32_t pipeconf; | |
5444 | ||
9f11a9e4 | 5445 | pipeconf = 0; |
84b046f3 | 5446 | |
67c72a12 DV |
5447 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5448 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5449 | pipeconf |= PIPECONF_ENABLE; | |
5450 | ||
cf532bb2 VS |
5451 | if (intel_crtc->config.double_wide) |
5452 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5453 | |
ff9ce46e DV |
5454 | /* only g4x and later have fancy bpc/dither controls */ |
5455 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5456 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5457 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5458 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5459 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5460 | |
ff9ce46e DV |
5461 | switch (intel_crtc->config.pipe_bpp) { |
5462 | case 18: | |
5463 | pipeconf |= PIPECONF_6BPC; | |
5464 | break; | |
5465 | case 24: | |
5466 | pipeconf |= PIPECONF_8BPC; | |
5467 | break; | |
5468 | case 30: | |
5469 | pipeconf |= PIPECONF_10BPC; | |
5470 | break; | |
5471 | default: | |
5472 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5473 | BUG(); | |
84b046f3 DV |
5474 | } |
5475 | } | |
5476 | ||
5477 | if (HAS_PIPE_CXSR(dev)) { | |
5478 | if (intel_crtc->lowfreq_avail) { | |
5479 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5480 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5481 | } else { | |
5482 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5483 | } |
5484 | } | |
5485 | ||
84b046f3 DV |
5486 | if (!IS_GEN2(dev) && |
5487 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5488 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5489 | else | |
5490 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5491 | ||
9f11a9e4 DV |
5492 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5493 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5494 | |
84b046f3 DV |
5495 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5496 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5497 | } | |
5498 | ||
f564048e | 5499 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5500 | int x, int y, |
94352cf9 | 5501 | struct drm_framebuffer *fb) |
79e53945 JB |
5502 | { |
5503 | struct drm_device *dev = crtc->dev; | |
5504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5506 | int pipe = intel_crtc->pipe; | |
80824003 | 5507 | int plane = intel_crtc->plane; |
c751ce4f | 5508 | int refclk, num_connectors = 0; |
652c393a | 5509 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5510 | u32 dspcntr; |
a16af721 | 5511 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5512 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5513 | struct intel_encoder *encoder; |
d4906093 | 5514 | const intel_limit_t *limit; |
5c3b82e2 | 5515 | int ret; |
79e53945 | 5516 | |
6c2b7c12 | 5517 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5518 | switch (encoder->type) { |
79e53945 JB |
5519 | case INTEL_OUTPUT_LVDS: |
5520 | is_lvds = true; | |
5521 | break; | |
e9fd1c02 JN |
5522 | case INTEL_OUTPUT_DSI: |
5523 | is_dsi = true; | |
5524 | break; | |
79e53945 | 5525 | } |
43565a06 | 5526 | |
c751ce4f | 5527 | num_connectors++; |
79e53945 JB |
5528 | } |
5529 | ||
f2335330 JN |
5530 | if (is_dsi) |
5531 | goto skip_dpll; | |
5532 | ||
5533 | if (!intel_crtc->config.clock_set) { | |
5534 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5535 | |
e9fd1c02 JN |
5536 | /* |
5537 | * Returns a set of divisors for the desired target clock with | |
5538 | * the given refclk, or FALSE. The returned values represent | |
5539 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5540 | * 2) / p1 / p2. | |
5541 | */ | |
5542 | limit = intel_limit(crtc, refclk); | |
5543 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5544 | intel_crtc->config.port_clock, | |
5545 | refclk, NULL, &clock); | |
f2335330 | 5546 | if (!ok) { |
e9fd1c02 JN |
5547 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5548 | return -EINVAL; | |
5549 | } | |
79e53945 | 5550 | |
f2335330 JN |
5551 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5552 | /* | |
5553 | * Ensure we match the reduced clock's P to the target | |
5554 | * clock. If the clocks don't match, we can't switch | |
5555 | * the display clock by using the FP0/FP1. In such case | |
5556 | * we will disable the LVDS downclock feature. | |
5557 | */ | |
5558 | has_reduced_clock = | |
5559 | dev_priv->display.find_dpll(limit, crtc, | |
5560 | dev_priv->lvds_downclock, | |
5561 | refclk, &clock, | |
5562 | &reduced_clock); | |
5563 | } | |
5564 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5565 | intel_crtc->config.dpll.n = clock.n; |
5566 | intel_crtc->config.dpll.m1 = clock.m1; | |
5567 | intel_crtc->config.dpll.m2 = clock.m2; | |
5568 | intel_crtc->config.dpll.p1 = clock.p1; | |
5569 | intel_crtc->config.dpll.p2 = clock.p2; | |
5570 | } | |
7026d4ac | 5571 | |
e9fd1c02 | 5572 | if (IS_GEN2(dev)) { |
8a654f3b | 5573 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5574 | has_reduced_clock ? &reduced_clock : NULL, |
5575 | num_connectors); | |
e9fd1c02 | 5576 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5577 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5578 | } else { |
f47709a9 | 5579 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5580 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5581 | num_connectors); |
e9fd1c02 | 5582 | } |
79e53945 | 5583 | |
f2335330 | 5584 | skip_dpll: |
79e53945 JB |
5585 | /* Set up the display plane register */ |
5586 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5587 | ||
da6ecc5d JB |
5588 | if (!IS_VALLEYVIEW(dev)) { |
5589 | if (pipe == 0) | |
5590 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5591 | else | |
5592 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5593 | } | |
79e53945 | 5594 | |
8a654f3b | 5595 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5596 | |
5597 | /* pipesrc and dspsize control the size that is scaled from, | |
5598 | * which should always be the user's requested size. | |
79e53945 | 5599 | */ |
929c77fb | 5600 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5601 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5602 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5603 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5604 | |
84b046f3 DV |
5605 | i9xx_set_pipeconf(intel_crtc); |
5606 | ||
f564048e EA |
5607 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5608 | POSTING_READ(DSPCNTR(plane)); | |
5609 | ||
94352cf9 | 5610 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5611 | |
f564048e EA |
5612 | return ret; |
5613 | } | |
5614 | ||
2fa2fe9a DV |
5615 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5616 | struct intel_crtc_config *pipe_config) | |
5617 | { | |
5618 | struct drm_device *dev = crtc->base.dev; | |
5619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5620 | uint32_t tmp; | |
5621 | ||
dc9e7dec VS |
5622 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
5623 | return; | |
5624 | ||
2fa2fe9a | 5625 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
5626 | if (!(tmp & PFIT_ENABLE)) |
5627 | return; | |
2fa2fe9a | 5628 | |
06922821 | 5629 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5630 | if (INTEL_INFO(dev)->gen < 4) { |
5631 | if (crtc->pipe != PIPE_B) | |
5632 | return; | |
2fa2fe9a DV |
5633 | } else { |
5634 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5635 | return; | |
5636 | } | |
5637 | ||
06922821 | 5638 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5639 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5640 | if (INTEL_INFO(dev)->gen < 5) | |
5641 | pipe_config->gmch_pfit.lvds_border_bits = | |
5642 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5643 | } | |
5644 | ||
acbec814 JB |
5645 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5646 | struct intel_crtc_config *pipe_config) | |
5647 | { | |
5648 | struct drm_device *dev = crtc->base.dev; | |
5649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5650 | int pipe = pipe_config->cpu_transcoder; | |
5651 | intel_clock_t clock; | |
5652 | u32 mdiv; | |
662c6ecb | 5653 | int refclk = 100000; |
acbec814 JB |
5654 | |
5655 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5656 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5657 | mutex_unlock(&dev_priv->dpio_lock); |
5658 | ||
5659 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5660 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5661 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5662 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5663 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5664 | ||
f646628b | 5665 | vlv_clock(refclk, &clock); |
acbec814 | 5666 | |
f646628b VS |
5667 | /* clock.dot is the fast clock */ |
5668 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5669 | } |
5670 | ||
1ad292b5 JB |
5671 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
5672 | struct intel_plane_config *plane_config) | |
5673 | { | |
5674 | struct drm_device *dev = crtc->base.dev; | |
5675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5676 | u32 val, base, offset; | |
5677 | int pipe = crtc->pipe, plane = crtc->plane; | |
5678 | int fourcc, pixel_format; | |
5679 | int aligned_height; | |
5680 | ||
5681 | plane_config->fb = kzalloc(sizeof(*plane_config->fb), GFP_KERNEL); | |
5682 | if (!plane_config->fb) { | |
5683 | DRM_DEBUG_KMS("failed to alloc fb\n"); | |
5684 | return; | |
5685 | } | |
5686 | ||
5687 | val = I915_READ(DSPCNTR(plane)); | |
5688 | ||
5689 | if (INTEL_INFO(dev)->gen >= 4) | |
5690 | if (val & DISPPLANE_TILED) | |
5691 | plane_config->tiled = true; | |
5692 | ||
5693 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
5694 | fourcc = intel_format_to_fourcc(pixel_format); | |
5695 | plane_config->fb->base.pixel_format = fourcc; | |
5696 | plane_config->fb->base.bits_per_pixel = | |
5697 | drm_format_plane_cpp(fourcc, 0) * 8; | |
5698 | ||
5699 | if (INTEL_INFO(dev)->gen >= 4) { | |
5700 | if (plane_config->tiled) | |
5701 | offset = I915_READ(DSPTILEOFF(plane)); | |
5702 | else | |
5703 | offset = I915_READ(DSPLINOFF(plane)); | |
5704 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
5705 | } else { | |
5706 | base = I915_READ(DSPADDR(plane)); | |
5707 | } | |
5708 | plane_config->base = base; | |
5709 | ||
5710 | val = I915_READ(PIPESRC(pipe)); | |
5711 | plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1; | |
5712 | plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1; | |
5713 | ||
5714 | val = I915_READ(DSPSTRIDE(pipe)); | |
5715 | plane_config->fb->base.pitches[0] = val & 0xffffff80; | |
5716 | ||
5717 | aligned_height = intel_align_height(dev, plane_config->fb->base.height, | |
5718 | plane_config->tiled); | |
5719 | ||
5720 | plane_config->size = ALIGN(plane_config->fb->base.pitches[0] * | |
5721 | aligned_height, PAGE_SIZE); | |
5722 | ||
5723 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
5724 | pipe, plane, plane_config->fb->base.width, | |
5725 | plane_config->fb->base.height, | |
5726 | plane_config->fb->base.bits_per_pixel, base, | |
5727 | plane_config->fb->base.pitches[0], | |
5728 | plane_config->size); | |
5729 | ||
5730 | } | |
5731 | ||
0e8ffe1b DV |
5732 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5733 | struct intel_crtc_config *pipe_config) | |
5734 | { | |
5735 | struct drm_device *dev = crtc->base.dev; | |
5736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5737 | uint32_t tmp; | |
5738 | ||
b5482bd0 ID |
5739 | if (!intel_display_power_enabled(dev_priv, |
5740 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
5741 | return false; | |
5742 | ||
e143a21c | 5743 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5744 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5745 | |
0e8ffe1b DV |
5746 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5747 | if (!(tmp & PIPECONF_ENABLE)) | |
5748 | return false; | |
5749 | ||
42571aef VS |
5750 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5751 | switch (tmp & PIPECONF_BPC_MASK) { | |
5752 | case PIPECONF_6BPC: | |
5753 | pipe_config->pipe_bpp = 18; | |
5754 | break; | |
5755 | case PIPECONF_8BPC: | |
5756 | pipe_config->pipe_bpp = 24; | |
5757 | break; | |
5758 | case PIPECONF_10BPC: | |
5759 | pipe_config->pipe_bpp = 30; | |
5760 | break; | |
5761 | default: | |
5762 | break; | |
5763 | } | |
5764 | } | |
5765 | ||
282740f7 VS |
5766 | if (INTEL_INFO(dev)->gen < 4) |
5767 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5768 | ||
1bd1bd80 DV |
5769 | intel_get_pipe_timings(crtc, pipe_config); |
5770 | ||
2fa2fe9a DV |
5771 | i9xx_get_pfit_config(crtc, pipe_config); |
5772 | ||
6c49f241 DV |
5773 | if (INTEL_INFO(dev)->gen >= 4) { |
5774 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5775 | pipe_config->pixel_multiplier = | |
5776 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5777 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5778 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5779 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5780 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5781 | pipe_config->pixel_multiplier = | |
5782 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5783 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5784 | } else { | |
5785 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5786 | * port and will be fixed up in the encoder->get_config | |
5787 | * function. */ | |
5788 | pipe_config->pixel_multiplier = 1; | |
5789 | } | |
8bcc2795 DV |
5790 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5791 | if (!IS_VALLEYVIEW(dev)) { | |
5792 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5793 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5794 | } else { |
5795 | /* Mask out read-only status bits. */ | |
5796 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5797 | DPLL_PORTC_READY_MASK | | |
5798 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5799 | } |
6c49f241 | 5800 | |
acbec814 JB |
5801 | if (IS_VALLEYVIEW(dev)) |
5802 | vlv_crtc_clock_get(crtc, pipe_config); | |
5803 | else | |
5804 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5805 | |
0e8ffe1b DV |
5806 | return true; |
5807 | } | |
5808 | ||
dde86e2d | 5809 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5810 | { |
5811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5812 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5813 | struct intel_encoder *encoder; |
74cfd7ac | 5814 | u32 val, final; |
13d83a67 | 5815 | bool has_lvds = false; |
199e5d79 | 5816 | bool has_cpu_edp = false; |
199e5d79 | 5817 | bool has_panel = false; |
99eb6a01 KP |
5818 | bool has_ck505 = false; |
5819 | bool can_ssc = false; | |
13d83a67 JB |
5820 | |
5821 | /* We need to take the global config into account */ | |
199e5d79 KP |
5822 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5823 | base.head) { | |
5824 | switch (encoder->type) { | |
5825 | case INTEL_OUTPUT_LVDS: | |
5826 | has_panel = true; | |
5827 | has_lvds = true; | |
5828 | break; | |
5829 | case INTEL_OUTPUT_EDP: | |
5830 | has_panel = true; | |
2de6905f | 5831 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5832 | has_cpu_edp = true; |
5833 | break; | |
13d83a67 JB |
5834 | } |
5835 | } | |
5836 | ||
99eb6a01 | 5837 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5838 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5839 | can_ssc = has_ck505; |
5840 | } else { | |
5841 | has_ck505 = false; | |
5842 | can_ssc = true; | |
5843 | } | |
5844 | ||
2de6905f ID |
5845 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5846 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5847 | |
5848 | /* Ironlake: try to setup display ref clock before DPLL | |
5849 | * enabling. This is only under driver's control after | |
5850 | * PCH B stepping, previous chipset stepping should be | |
5851 | * ignoring this setting. | |
5852 | */ | |
74cfd7ac CW |
5853 | val = I915_READ(PCH_DREF_CONTROL); |
5854 | ||
5855 | /* As we must carefully and slowly disable/enable each source in turn, | |
5856 | * compute the final state we want first and check if we need to | |
5857 | * make any changes at all. | |
5858 | */ | |
5859 | final = val; | |
5860 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5861 | if (has_ck505) | |
5862 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5863 | else | |
5864 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5865 | ||
5866 | final &= ~DREF_SSC_SOURCE_MASK; | |
5867 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5868 | final &= ~DREF_SSC1_ENABLE; | |
5869 | ||
5870 | if (has_panel) { | |
5871 | final |= DREF_SSC_SOURCE_ENABLE; | |
5872 | ||
5873 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5874 | final |= DREF_SSC1_ENABLE; | |
5875 | ||
5876 | if (has_cpu_edp) { | |
5877 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5878 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5879 | else | |
5880 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5881 | } else | |
5882 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5883 | } else { | |
5884 | final |= DREF_SSC_SOURCE_DISABLE; | |
5885 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5886 | } | |
5887 | ||
5888 | if (final == val) | |
5889 | return; | |
5890 | ||
13d83a67 | 5891 | /* Always enable nonspread source */ |
74cfd7ac | 5892 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5893 | |
99eb6a01 | 5894 | if (has_ck505) |
74cfd7ac | 5895 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5896 | else |
74cfd7ac | 5897 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5898 | |
199e5d79 | 5899 | if (has_panel) { |
74cfd7ac CW |
5900 | val &= ~DREF_SSC_SOURCE_MASK; |
5901 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5902 | |
199e5d79 | 5903 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5904 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5905 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5906 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5907 | } else |
74cfd7ac | 5908 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5909 | |
5910 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5911 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5912 | POSTING_READ(PCH_DREF_CONTROL); |
5913 | udelay(200); | |
5914 | ||
74cfd7ac | 5915 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5916 | |
5917 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5918 | if (has_cpu_edp) { |
99eb6a01 | 5919 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5920 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5921 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5922 | } |
13d83a67 | 5923 | else |
74cfd7ac | 5924 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5925 | } else |
74cfd7ac | 5926 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5927 | |
74cfd7ac | 5928 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5929 | POSTING_READ(PCH_DREF_CONTROL); |
5930 | udelay(200); | |
5931 | } else { | |
5932 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5933 | ||
74cfd7ac | 5934 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5935 | |
5936 | /* Turn off CPU output */ | |
74cfd7ac | 5937 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5938 | |
74cfd7ac | 5939 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5940 | POSTING_READ(PCH_DREF_CONTROL); |
5941 | udelay(200); | |
5942 | ||
5943 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5944 | val &= ~DREF_SSC_SOURCE_MASK; |
5945 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5946 | |
5947 | /* Turn off SSC1 */ | |
74cfd7ac | 5948 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5949 | |
74cfd7ac | 5950 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5951 | POSTING_READ(PCH_DREF_CONTROL); |
5952 | udelay(200); | |
5953 | } | |
74cfd7ac CW |
5954 | |
5955 | BUG_ON(val != final); | |
13d83a67 JB |
5956 | } |
5957 | ||
f31f2d55 | 5958 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5959 | { |
f31f2d55 | 5960 | uint32_t tmp; |
dde86e2d | 5961 | |
0ff066a9 PZ |
5962 | tmp = I915_READ(SOUTH_CHICKEN2); |
5963 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5964 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5965 | |
0ff066a9 PZ |
5966 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5967 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5968 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5969 | |
0ff066a9 PZ |
5970 | tmp = I915_READ(SOUTH_CHICKEN2); |
5971 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5972 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5973 | |
0ff066a9 PZ |
5974 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5975 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5976 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5977 | } |
5978 | ||
5979 | /* WaMPhyProgramming:hsw */ | |
5980 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5981 | { | |
5982 | uint32_t tmp; | |
dde86e2d PZ |
5983 | |
5984 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5985 | tmp &= ~(0xFF << 24); | |
5986 | tmp |= (0x12 << 24); | |
5987 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5988 | ||
dde86e2d PZ |
5989 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5990 | tmp |= (1 << 11); | |
5991 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5992 | ||
5993 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5994 | tmp |= (1 << 11); | |
5995 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5996 | ||
dde86e2d PZ |
5997 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5998 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5999 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6000 | ||
6001 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6002 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6003 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6004 | ||
0ff066a9 PZ |
6005 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6006 | tmp &= ~(7 << 13); | |
6007 | tmp |= (5 << 13); | |
6008 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6009 | |
0ff066a9 PZ |
6010 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6011 | tmp &= ~(7 << 13); | |
6012 | tmp |= (5 << 13); | |
6013 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6014 | |
6015 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6016 | tmp &= ~0xFF; | |
6017 | tmp |= 0x1C; | |
6018 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6019 | ||
6020 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6021 | tmp &= ~0xFF; | |
6022 | tmp |= 0x1C; | |
6023 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6024 | ||
6025 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6026 | tmp &= ~(0xFF << 16); | |
6027 | tmp |= (0x1C << 16); | |
6028 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6029 | ||
6030 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6031 | tmp &= ~(0xFF << 16); | |
6032 | tmp |= (0x1C << 16); | |
6033 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6034 | ||
0ff066a9 PZ |
6035 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6036 | tmp |= (1 << 27); | |
6037 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6038 | |
0ff066a9 PZ |
6039 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6040 | tmp |= (1 << 27); | |
6041 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6042 | |
0ff066a9 PZ |
6043 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6044 | tmp &= ~(0xF << 28); | |
6045 | tmp |= (4 << 28); | |
6046 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6047 | |
0ff066a9 PZ |
6048 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6049 | tmp &= ~(0xF << 28); | |
6050 | tmp |= (4 << 28); | |
6051 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6052 | } |
6053 | ||
2fa86a1f PZ |
6054 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6055 | * Programming" based on the parameters passed: | |
6056 | * - Sequence to enable CLKOUT_DP | |
6057 | * - Sequence to enable CLKOUT_DP without spread | |
6058 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6059 | */ | |
6060 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6061 | bool with_fdi) | |
f31f2d55 PZ |
6062 | { |
6063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6064 | uint32_t reg, tmp; |
6065 | ||
6066 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6067 | with_spread = true; | |
6068 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6069 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6070 | with_fdi = false; | |
f31f2d55 PZ |
6071 | |
6072 | mutex_lock(&dev_priv->dpio_lock); | |
6073 | ||
6074 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6075 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6076 | tmp |= SBI_SSCCTL_PATHALT; | |
6077 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6078 | ||
6079 | udelay(24); | |
6080 | ||
2fa86a1f PZ |
6081 | if (with_spread) { |
6082 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6083 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6084 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6085 | |
2fa86a1f PZ |
6086 | if (with_fdi) { |
6087 | lpt_reset_fdi_mphy(dev_priv); | |
6088 | lpt_program_fdi_mphy(dev_priv); | |
6089 | } | |
6090 | } | |
dde86e2d | 6091 | |
2fa86a1f PZ |
6092 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6093 | SBI_GEN0 : SBI_DBUFF0; | |
6094 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6095 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6096 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6097 | |
6098 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6099 | } |
6100 | ||
47701c3b PZ |
6101 | /* Sequence to disable CLKOUT_DP */ |
6102 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6103 | { | |
6104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6105 | uint32_t reg, tmp; | |
6106 | ||
6107 | mutex_lock(&dev_priv->dpio_lock); | |
6108 | ||
6109 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6110 | SBI_GEN0 : SBI_DBUFF0; | |
6111 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6112 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6113 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6114 | ||
6115 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6116 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6117 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6118 | tmp |= SBI_SSCCTL_PATHALT; | |
6119 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6120 | udelay(32); | |
6121 | } | |
6122 | tmp |= SBI_SSCCTL_DISABLE; | |
6123 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6124 | } | |
6125 | ||
6126 | mutex_unlock(&dev_priv->dpio_lock); | |
6127 | } | |
6128 | ||
bf8fa3d3 PZ |
6129 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6130 | { | |
6131 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6132 | struct intel_encoder *encoder; | |
6133 | bool has_vga = false; | |
6134 | ||
6135 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6136 | switch (encoder->type) { | |
6137 | case INTEL_OUTPUT_ANALOG: | |
6138 | has_vga = true; | |
6139 | break; | |
6140 | } | |
6141 | } | |
6142 | ||
47701c3b PZ |
6143 | if (has_vga) |
6144 | lpt_enable_clkout_dp(dev, true, true); | |
6145 | else | |
6146 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6147 | } |
6148 | ||
dde86e2d PZ |
6149 | /* |
6150 | * Initialize reference clocks when the driver loads | |
6151 | */ | |
6152 | void intel_init_pch_refclk(struct drm_device *dev) | |
6153 | { | |
6154 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6155 | ironlake_init_pch_refclk(dev); | |
6156 | else if (HAS_PCH_LPT(dev)) | |
6157 | lpt_init_pch_refclk(dev); | |
6158 | } | |
6159 | ||
d9d444cb JB |
6160 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6161 | { | |
6162 | struct drm_device *dev = crtc->dev; | |
6163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6164 | struct intel_encoder *encoder; | |
d9d444cb JB |
6165 | int num_connectors = 0; |
6166 | bool is_lvds = false; | |
6167 | ||
6c2b7c12 | 6168 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6169 | switch (encoder->type) { |
6170 | case INTEL_OUTPUT_LVDS: | |
6171 | is_lvds = true; | |
6172 | break; | |
d9d444cb JB |
6173 | } |
6174 | num_connectors++; | |
6175 | } | |
6176 | ||
6177 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6178 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6179 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6180 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6181 | } |
6182 | ||
6183 | return 120000; | |
6184 | } | |
6185 | ||
6ff93609 | 6186 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6187 | { |
c8203565 | 6188 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6190 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6191 | uint32_t val; |
6192 | ||
78114071 | 6193 | val = 0; |
c8203565 | 6194 | |
965e0c48 | 6195 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6196 | case 18: |
dfd07d72 | 6197 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6198 | break; |
6199 | case 24: | |
dfd07d72 | 6200 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6201 | break; |
6202 | case 30: | |
dfd07d72 | 6203 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6204 | break; |
6205 | case 36: | |
dfd07d72 | 6206 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6207 | break; |
6208 | default: | |
cc769b62 PZ |
6209 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6210 | BUG(); | |
c8203565 PZ |
6211 | } |
6212 | ||
d8b32247 | 6213 | if (intel_crtc->config.dither) |
c8203565 PZ |
6214 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6215 | ||
6ff93609 | 6216 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6217 | val |= PIPECONF_INTERLACED_ILK; |
6218 | else | |
6219 | val |= PIPECONF_PROGRESSIVE; | |
6220 | ||
50f3b016 | 6221 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6222 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6223 | |
c8203565 PZ |
6224 | I915_WRITE(PIPECONF(pipe), val); |
6225 | POSTING_READ(PIPECONF(pipe)); | |
6226 | } | |
6227 | ||
86d3efce VS |
6228 | /* |
6229 | * Set up the pipe CSC unit. | |
6230 | * | |
6231 | * Currently only full range RGB to limited range RGB conversion | |
6232 | * is supported, but eventually this should handle various | |
6233 | * RGB<->YCbCr scenarios as well. | |
6234 | */ | |
50f3b016 | 6235 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6236 | { |
6237 | struct drm_device *dev = crtc->dev; | |
6238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6240 | int pipe = intel_crtc->pipe; | |
6241 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6242 | ||
6243 | /* | |
6244 | * TODO: Check what kind of values actually come out of the pipe | |
6245 | * with these coeff/postoff values and adjust to get the best | |
6246 | * accuracy. Perhaps we even need to take the bpc value into | |
6247 | * consideration. | |
6248 | */ | |
6249 | ||
50f3b016 | 6250 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6251 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6252 | ||
6253 | /* | |
6254 | * GY/GU and RY/RU should be the other way around according | |
6255 | * to BSpec, but reality doesn't agree. Just set them up in | |
6256 | * a way that results in the correct picture. | |
6257 | */ | |
6258 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6259 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6260 | ||
6261 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6262 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6263 | ||
6264 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6265 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6266 | ||
6267 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6268 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6269 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6270 | ||
6271 | if (INTEL_INFO(dev)->gen > 6) { | |
6272 | uint16_t postoff = 0; | |
6273 | ||
50f3b016 | 6274 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6275 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6276 | |
6277 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6278 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6279 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6280 | ||
6281 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6282 | } else { | |
6283 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6284 | ||
50f3b016 | 6285 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6286 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6287 | ||
6288 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6289 | } | |
6290 | } | |
6291 | ||
6ff93609 | 6292 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6293 | { |
756f85cf PZ |
6294 | struct drm_device *dev = crtc->dev; |
6295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6297 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6298 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6299 | uint32_t val; |
6300 | ||
3eff4faa | 6301 | val = 0; |
ee2b0b38 | 6302 | |
756f85cf | 6303 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6304 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6305 | ||
6ff93609 | 6306 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6307 | val |= PIPECONF_INTERLACED_ILK; |
6308 | else | |
6309 | val |= PIPECONF_PROGRESSIVE; | |
6310 | ||
702e7a56 PZ |
6311 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6312 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6313 | |
6314 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6315 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6316 | |
6317 | if (IS_BROADWELL(dev)) { | |
6318 | val = 0; | |
6319 | ||
6320 | switch (intel_crtc->config.pipe_bpp) { | |
6321 | case 18: | |
6322 | val |= PIPEMISC_DITHER_6_BPC; | |
6323 | break; | |
6324 | case 24: | |
6325 | val |= PIPEMISC_DITHER_8_BPC; | |
6326 | break; | |
6327 | case 30: | |
6328 | val |= PIPEMISC_DITHER_10_BPC; | |
6329 | break; | |
6330 | case 36: | |
6331 | val |= PIPEMISC_DITHER_12_BPC; | |
6332 | break; | |
6333 | default: | |
6334 | /* Case prevented by pipe_config_set_bpp. */ | |
6335 | BUG(); | |
6336 | } | |
6337 | ||
6338 | if (intel_crtc->config.dither) | |
6339 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6340 | ||
6341 | I915_WRITE(PIPEMISC(pipe), val); | |
6342 | } | |
ee2b0b38 PZ |
6343 | } |
6344 | ||
6591c6e4 | 6345 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6346 | intel_clock_t *clock, |
6347 | bool *has_reduced_clock, | |
6348 | intel_clock_t *reduced_clock) | |
6349 | { | |
6350 | struct drm_device *dev = crtc->dev; | |
6351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6352 | struct intel_encoder *intel_encoder; | |
6353 | int refclk; | |
d4906093 | 6354 | const intel_limit_t *limit; |
a16af721 | 6355 | bool ret, is_lvds = false; |
79e53945 | 6356 | |
6591c6e4 PZ |
6357 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6358 | switch (intel_encoder->type) { | |
79e53945 JB |
6359 | case INTEL_OUTPUT_LVDS: |
6360 | is_lvds = true; | |
6361 | break; | |
79e53945 JB |
6362 | } |
6363 | } | |
6364 | ||
d9d444cb | 6365 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6366 | |
d4906093 ML |
6367 | /* |
6368 | * Returns a set of divisors for the desired target clock with the given | |
6369 | * refclk, or FALSE. The returned values represent the clock equation: | |
6370 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6371 | */ | |
1b894b59 | 6372 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6373 | ret = dev_priv->display.find_dpll(limit, crtc, |
6374 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6375 | refclk, NULL, clock); |
6591c6e4 PZ |
6376 | if (!ret) |
6377 | return false; | |
cda4b7d3 | 6378 | |
ddc9003c | 6379 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6380 | /* |
6381 | * Ensure we match the reduced clock's P to the target clock. | |
6382 | * If the clocks don't match, we can't switch the display clock | |
6383 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6384 | * downclock feature. | |
6385 | */ | |
ee9300bb DV |
6386 | *has_reduced_clock = |
6387 | dev_priv->display.find_dpll(limit, crtc, | |
6388 | dev_priv->lvds_downclock, | |
6389 | refclk, clock, | |
6390 | reduced_clock); | |
652c393a | 6391 | } |
61e9653f | 6392 | |
6591c6e4 PZ |
6393 | return true; |
6394 | } | |
6395 | ||
d4b1931c PZ |
6396 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6397 | { | |
6398 | /* | |
6399 | * Account for spread spectrum to avoid | |
6400 | * oversubscribing the link. Max center spread | |
6401 | * is 2.5%; use 5% for safety's sake. | |
6402 | */ | |
6403 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6404 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6405 | } |
6406 | ||
7429e9d4 | 6407 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6408 | { |
7429e9d4 | 6409 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6410 | } |
6411 | ||
de13a2e3 | 6412 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6413 | u32 *fp, |
9a7c7890 | 6414 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6415 | { |
de13a2e3 | 6416 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6417 | struct drm_device *dev = crtc->dev; |
6418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6419 | struct intel_encoder *intel_encoder; |
6420 | uint32_t dpll; | |
6cc5f341 | 6421 | int factor, num_connectors = 0; |
09ede541 | 6422 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6423 | |
de13a2e3 PZ |
6424 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6425 | switch (intel_encoder->type) { | |
79e53945 JB |
6426 | case INTEL_OUTPUT_LVDS: |
6427 | is_lvds = true; | |
6428 | break; | |
6429 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6430 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6431 | is_sdvo = true; |
79e53945 | 6432 | break; |
79e53945 | 6433 | } |
43565a06 | 6434 | |
c751ce4f | 6435 | num_connectors++; |
79e53945 | 6436 | } |
79e53945 | 6437 | |
c1858123 | 6438 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6439 | factor = 21; |
6440 | if (is_lvds) { | |
6441 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6442 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6443 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6444 | factor = 25; |
09ede541 | 6445 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6446 | factor = 20; |
c1858123 | 6447 | |
7429e9d4 | 6448 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6449 | *fp |= FP_CB_TUNE; |
2c07245f | 6450 | |
9a7c7890 DV |
6451 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6452 | *fp2 |= FP_CB_TUNE; | |
6453 | ||
5eddb70b | 6454 | dpll = 0; |
2c07245f | 6455 | |
a07d6787 EA |
6456 | if (is_lvds) |
6457 | dpll |= DPLLB_MODE_LVDS; | |
6458 | else | |
6459 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6460 | |
ef1b460d DV |
6461 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6462 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6463 | |
6464 | if (is_sdvo) | |
4a33e48d | 6465 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6466 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6467 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6468 | |
a07d6787 | 6469 | /* compute bitmask from p1 value */ |
7429e9d4 | 6470 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6471 | /* also FPA1 */ |
7429e9d4 | 6472 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6473 | |
7429e9d4 | 6474 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6475 | case 5: |
6476 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6477 | break; | |
6478 | case 7: | |
6479 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6480 | break; | |
6481 | case 10: | |
6482 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6483 | break; | |
6484 | case 14: | |
6485 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6486 | break; | |
79e53945 JB |
6487 | } |
6488 | ||
b4c09f3b | 6489 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6490 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6491 | else |
6492 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6493 | ||
959e16d6 | 6494 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6495 | } |
6496 | ||
6497 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6498 | int x, int y, |
6499 | struct drm_framebuffer *fb) | |
6500 | { | |
6501 | struct drm_device *dev = crtc->dev; | |
6502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6504 | int pipe = intel_crtc->pipe; | |
6505 | int plane = intel_crtc->plane; | |
6506 | int num_connectors = 0; | |
6507 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6508 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6509 | bool ok, has_reduced_clock = false; |
8b47047b | 6510 | bool is_lvds = false; |
de13a2e3 | 6511 | struct intel_encoder *encoder; |
e2b78267 | 6512 | struct intel_shared_dpll *pll; |
de13a2e3 | 6513 | int ret; |
de13a2e3 PZ |
6514 | |
6515 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6516 | switch (encoder->type) { | |
6517 | case INTEL_OUTPUT_LVDS: | |
6518 | is_lvds = true; | |
6519 | break; | |
de13a2e3 PZ |
6520 | } |
6521 | ||
6522 | num_connectors++; | |
a07d6787 | 6523 | } |
79e53945 | 6524 | |
5dc5298b PZ |
6525 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6526 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6527 | |
ff9a6750 | 6528 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6529 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6530 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6531 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6532 | return -EINVAL; | |
79e53945 | 6533 | } |
f47709a9 DV |
6534 | /* Compat-code for transition, will disappear. */ |
6535 | if (!intel_crtc->config.clock_set) { | |
6536 | intel_crtc->config.dpll.n = clock.n; | |
6537 | intel_crtc->config.dpll.m1 = clock.m1; | |
6538 | intel_crtc->config.dpll.m2 = clock.m2; | |
6539 | intel_crtc->config.dpll.p1 = clock.p1; | |
6540 | intel_crtc->config.dpll.p2 = clock.p2; | |
6541 | } | |
79e53945 | 6542 | |
5dc5298b | 6543 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6544 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6545 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6546 | if (has_reduced_clock) |
7429e9d4 | 6547 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6548 | |
7429e9d4 | 6549 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6550 | &fp, &reduced_clock, |
6551 | has_reduced_clock ? &fp2 : NULL); | |
6552 | ||
959e16d6 | 6553 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6554 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6555 | if (has_reduced_clock) | |
6556 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6557 | else | |
6558 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6559 | ||
b89a1d39 | 6560 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6561 | if (pll == NULL) { |
84f44ce7 VS |
6562 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6563 | pipe_name(pipe)); | |
4b645f14 JB |
6564 | return -EINVAL; |
6565 | } | |
ee7b9f93 | 6566 | } else |
e72f9fbf | 6567 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6568 | |
03afc4a2 DV |
6569 | if (intel_crtc->config.has_dp_encoder) |
6570 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6571 | |
d330a953 | 6572 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
6573 | intel_crtc->lowfreq_avail = true; |
6574 | else | |
6575 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6576 | |
8a654f3b | 6577 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6578 | |
ca3a0ff8 | 6579 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6580 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6581 | &intel_crtc->config.fdi_m_n); | |
6582 | } | |
2c07245f | 6583 | |
6ff93609 | 6584 | ironlake_set_pipeconf(crtc); |
79e53945 | 6585 | |
a1f9e77e PZ |
6586 | /* Set up the display plane register */ |
6587 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6588 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6589 | |
94352cf9 | 6590 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6591 | |
1857e1da | 6592 | return ret; |
79e53945 JB |
6593 | } |
6594 | ||
eb14cb74 VS |
6595 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6596 | struct intel_link_m_n *m_n) | |
6597 | { | |
6598 | struct drm_device *dev = crtc->base.dev; | |
6599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6600 | enum pipe pipe = crtc->pipe; | |
6601 | ||
6602 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6603 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6604 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6605 | & ~TU_SIZE_MASK; | |
6606 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6607 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6608 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6609 | } | |
6610 | ||
6611 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6612 | enum transcoder transcoder, | |
6613 | struct intel_link_m_n *m_n) | |
72419203 DV |
6614 | { |
6615 | struct drm_device *dev = crtc->base.dev; | |
6616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6617 | enum pipe pipe = crtc->pipe; |
72419203 | 6618 | |
eb14cb74 VS |
6619 | if (INTEL_INFO(dev)->gen >= 5) { |
6620 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6621 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6622 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6623 | & ~TU_SIZE_MASK; | |
6624 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6625 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6626 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6627 | } else { | |
6628 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6629 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6630 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6631 | & ~TU_SIZE_MASK; | |
6632 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6633 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6634 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6635 | } | |
6636 | } | |
6637 | ||
6638 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6639 | struct intel_crtc_config *pipe_config) | |
6640 | { | |
6641 | if (crtc->config.has_pch_encoder) | |
6642 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6643 | else | |
6644 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6645 | &pipe_config->dp_m_n); | |
6646 | } | |
72419203 | 6647 | |
eb14cb74 VS |
6648 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6649 | struct intel_crtc_config *pipe_config) | |
6650 | { | |
6651 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6652 | &pipe_config->fdi_m_n); | |
72419203 DV |
6653 | } |
6654 | ||
2fa2fe9a DV |
6655 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6656 | struct intel_crtc_config *pipe_config) | |
6657 | { | |
6658 | struct drm_device *dev = crtc->base.dev; | |
6659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6660 | uint32_t tmp; | |
6661 | ||
6662 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6663 | ||
6664 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6665 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6666 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6667 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6668 | |
6669 | /* We currently do not free assignements of panel fitters on | |
6670 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6671 | * differentiates them) so just WARN about this case for now. */ | |
6672 | if (IS_GEN7(dev)) { | |
6673 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6674 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6675 | } | |
2fa2fe9a | 6676 | } |
79e53945 JB |
6677 | } |
6678 | ||
4c6baa59 JB |
6679 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
6680 | struct intel_plane_config *plane_config) | |
6681 | { | |
6682 | struct drm_device *dev = crtc->base.dev; | |
6683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6684 | u32 val, base, offset; | |
6685 | int pipe = crtc->pipe, plane = crtc->plane; | |
6686 | int fourcc, pixel_format; | |
6687 | int aligned_height; | |
6688 | ||
6689 | plane_config->fb = kzalloc(sizeof(*plane_config->fb), GFP_KERNEL); | |
6690 | if (!plane_config->fb) { | |
6691 | DRM_DEBUG_KMS("failed to alloc fb\n"); | |
6692 | return; | |
6693 | } | |
6694 | ||
6695 | val = I915_READ(DSPCNTR(plane)); | |
6696 | ||
6697 | if (INTEL_INFO(dev)->gen >= 4) | |
6698 | if (val & DISPPLANE_TILED) | |
6699 | plane_config->tiled = true; | |
6700 | ||
6701 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6702 | fourcc = intel_format_to_fourcc(pixel_format); | |
6703 | plane_config->fb->base.pixel_format = fourcc; | |
6704 | plane_config->fb->base.bits_per_pixel = | |
6705 | drm_format_plane_cpp(fourcc, 0) * 8; | |
6706 | ||
6707 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6708 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
6709 | offset = I915_READ(DSPOFFSET(plane)); | |
6710 | } else { | |
6711 | if (plane_config->tiled) | |
6712 | offset = I915_READ(DSPTILEOFF(plane)); | |
6713 | else | |
6714 | offset = I915_READ(DSPLINOFF(plane)); | |
6715 | } | |
6716 | plane_config->base = base; | |
6717 | ||
6718 | val = I915_READ(PIPESRC(pipe)); | |
6719 | plane_config->fb->base.width = ((val >> 16) & 0xfff) + 1; | |
6720 | plane_config->fb->base.height = ((val >> 0) & 0xfff) + 1; | |
6721 | ||
6722 | val = I915_READ(DSPSTRIDE(pipe)); | |
6723 | plane_config->fb->base.pitches[0] = val & 0xffffff80; | |
6724 | ||
6725 | aligned_height = intel_align_height(dev, plane_config->fb->base.height, | |
6726 | plane_config->tiled); | |
6727 | ||
6728 | plane_config->size = ALIGN(plane_config->fb->base.pitches[0] * | |
6729 | aligned_height, PAGE_SIZE); | |
6730 | ||
6731 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
6732 | pipe, plane, plane_config->fb->base.width, | |
6733 | plane_config->fb->base.height, | |
6734 | plane_config->fb->base.bits_per_pixel, base, | |
6735 | plane_config->fb->base.pitches[0], | |
6736 | plane_config->size); | |
6737 | } | |
6738 | ||
0e8ffe1b DV |
6739 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6740 | struct intel_crtc_config *pipe_config) | |
6741 | { | |
6742 | struct drm_device *dev = crtc->base.dev; | |
6743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6744 | uint32_t tmp; | |
6745 | ||
e143a21c | 6746 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6747 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6748 | |
0e8ffe1b DV |
6749 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6750 | if (!(tmp & PIPECONF_ENABLE)) | |
6751 | return false; | |
6752 | ||
42571aef VS |
6753 | switch (tmp & PIPECONF_BPC_MASK) { |
6754 | case PIPECONF_6BPC: | |
6755 | pipe_config->pipe_bpp = 18; | |
6756 | break; | |
6757 | case PIPECONF_8BPC: | |
6758 | pipe_config->pipe_bpp = 24; | |
6759 | break; | |
6760 | case PIPECONF_10BPC: | |
6761 | pipe_config->pipe_bpp = 30; | |
6762 | break; | |
6763 | case PIPECONF_12BPC: | |
6764 | pipe_config->pipe_bpp = 36; | |
6765 | break; | |
6766 | default: | |
6767 | break; | |
6768 | } | |
6769 | ||
ab9412ba | 6770 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6771 | struct intel_shared_dpll *pll; |
6772 | ||
88adfff1 DV |
6773 | pipe_config->has_pch_encoder = true; |
6774 | ||
627eb5a3 DV |
6775 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6776 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6777 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6778 | |
6779 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6780 | |
c0d43d62 | 6781 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6782 | pipe_config->shared_dpll = |
6783 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6784 | } else { |
6785 | tmp = I915_READ(PCH_DPLL_SEL); | |
6786 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6787 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6788 | else | |
6789 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6790 | } | |
66e985c0 DV |
6791 | |
6792 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6793 | ||
6794 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6795 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6796 | |
6797 | tmp = pipe_config->dpll_hw_state.dpll; | |
6798 | pipe_config->pixel_multiplier = | |
6799 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6800 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6801 | |
6802 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6803 | } else { |
6804 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6805 | } |
6806 | ||
1bd1bd80 DV |
6807 | intel_get_pipe_timings(crtc, pipe_config); |
6808 | ||
2fa2fe9a DV |
6809 | ironlake_get_pfit_config(crtc, pipe_config); |
6810 | ||
0e8ffe1b DV |
6811 | return true; |
6812 | } | |
6813 | ||
be256dc7 PZ |
6814 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6815 | { | |
6816 | struct drm_device *dev = dev_priv->dev; | |
6817 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6818 | struct intel_crtc *crtc; | |
6819 | unsigned long irqflags; | |
bd633a7c | 6820 | uint32_t val; |
be256dc7 PZ |
6821 | |
6822 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
798183c5 | 6823 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
6824 | pipe_name(crtc->pipe)); |
6825 | ||
6826 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6827 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6828 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6829 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6830 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6831 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6832 | "CPU PWM1 enabled\n"); | |
6833 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6834 | "CPU PWM2 enabled\n"); | |
6835 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6836 | "PCH PWM1 enabled\n"); | |
6837 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6838 | "Utility pin enabled\n"); | |
6839 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6840 | ||
6841 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6842 | val = I915_READ(DEIMR); | |
6806e63f | 6843 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
be256dc7 PZ |
6844 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6845 | val = I915_READ(SDEIMR); | |
bd633a7c | 6846 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6847 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6848 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6849 | } | |
6850 | ||
6851 | /* | |
6852 | * This function implements pieces of two sequences from BSpec: | |
6853 | * - Sequence for display software to disable LCPLL | |
6854 | * - Sequence for display software to allow package C8+ | |
6855 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6856 | * register. Callers should take care of disabling all the display engine | |
6857 | * functions, doing the mode unset, fixing interrupts, etc. | |
6858 | */ | |
6ff58d53 PZ |
6859 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6860 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6861 | { |
6862 | uint32_t val; | |
6863 | ||
6864 | assert_can_disable_lcpll(dev_priv); | |
6865 | ||
6866 | val = I915_READ(LCPLL_CTL); | |
6867 | ||
6868 | if (switch_to_fclk) { | |
6869 | val |= LCPLL_CD_SOURCE_FCLK; | |
6870 | I915_WRITE(LCPLL_CTL, val); | |
6871 | ||
6872 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6873 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6874 | DRM_ERROR("Switching to FCLK failed\n"); | |
6875 | ||
6876 | val = I915_READ(LCPLL_CTL); | |
6877 | } | |
6878 | ||
6879 | val |= LCPLL_PLL_DISABLE; | |
6880 | I915_WRITE(LCPLL_CTL, val); | |
6881 | POSTING_READ(LCPLL_CTL); | |
6882 | ||
6883 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6884 | DRM_ERROR("LCPLL still locked\n"); | |
6885 | ||
6886 | val = I915_READ(D_COMP); | |
6887 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6888 | mutex_lock(&dev_priv->rps.hw_lock); |
6889 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6890 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6891 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6892 | POSTING_READ(D_COMP); |
6893 | ndelay(100); | |
6894 | ||
6895 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6896 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6897 | ||
6898 | if (allow_power_down) { | |
6899 | val = I915_READ(LCPLL_CTL); | |
6900 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6901 | I915_WRITE(LCPLL_CTL, val); | |
6902 | POSTING_READ(LCPLL_CTL); | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | /* | |
6907 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6908 | * source. | |
6909 | */ | |
6ff58d53 | 6910 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6911 | { |
6912 | uint32_t val; | |
6913 | ||
6914 | val = I915_READ(LCPLL_CTL); | |
6915 | ||
6916 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6917 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6918 | return; | |
6919 | ||
215733fa PZ |
6920 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6921 | * we'll hang the machine! */ | |
0d9d349d | 6922 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6923 | |
be256dc7 PZ |
6924 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6925 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6926 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6927 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6928 | } |
6929 | ||
6930 | val = I915_READ(D_COMP); | |
6931 | val |= D_COMP_COMP_FORCE; | |
6932 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6933 | mutex_lock(&dev_priv->rps.hw_lock); |
6934 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6935 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6936 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6937 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6938 | |
6939 | val = I915_READ(LCPLL_CTL); | |
6940 | val &= ~LCPLL_PLL_DISABLE; | |
6941 | I915_WRITE(LCPLL_CTL, val); | |
6942 | ||
6943 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6944 | DRM_ERROR("LCPLL not locked yet\n"); | |
6945 | ||
6946 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6947 | val = I915_READ(LCPLL_CTL); | |
6948 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6949 | I915_WRITE(LCPLL_CTL, val); | |
6950 | ||
6951 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6952 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6953 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6954 | } | |
215733fa | 6955 | |
0d9d349d | 6956 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6957 | } |
6958 | ||
c67a470b PZ |
6959 | void hsw_enable_pc8_work(struct work_struct *__work) |
6960 | { | |
6961 | struct drm_i915_private *dev_priv = | |
6962 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6963 | pc8.enable_work); | |
6964 | struct drm_device *dev = dev_priv->dev; | |
6965 | uint32_t val; | |
6966 | ||
7125ecb8 PZ |
6967 | WARN_ON(!HAS_PC8(dev)); |
6968 | ||
c67a470b PZ |
6969 | if (dev_priv->pc8.enabled) |
6970 | return; | |
6971 | ||
6972 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6973 | ||
6974 | dev_priv->pc8.enabled = true; | |
6975 | ||
6976 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6977 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6978 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6979 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6980 | } | |
6981 | ||
6982 | lpt_disable_clkout_dp(dev); | |
6983 | hsw_pc8_disable_interrupts(dev); | |
6984 | hsw_disable_lcpll(dev_priv, true, true); | |
8771a7f8 PZ |
6985 | |
6986 | intel_runtime_pm_put(dev_priv); | |
c67a470b PZ |
6987 | } |
6988 | ||
6989 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6990 | { | |
6991 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6992 | WARN(dev_priv->pc8.disable_count < 1, | |
6993 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6994 | ||
6995 | dev_priv->pc8.disable_count--; | |
6996 | if (dev_priv->pc8.disable_count != 0) | |
6997 | return; | |
6998 | ||
6999 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
d330a953 | 7000 | msecs_to_jiffies(i915.pc8_timeout)); |
c67a470b PZ |
7001 | } |
7002 | ||
7003 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
7004 | { | |
7005 | struct drm_device *dev = dev_priv->dev; | |
7006 | uint32_t val; | |
7007 | ||
7008 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
7009 | WARN(dev_priv->pc8.disable_count < 0, | |
7010 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
7011 | ||
7012 | dev_priv->pc8.disable_count++; | |
7013 | if (dev_priv->pc8.disable_count != 1) | |
7014 | return; | |
7015 | ||
7125ecb8 PZ |
7016 | WARN_ON(!HAS_PC8(dev)); |
7017 | ||
c67a470b PZ |
7018 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
7019 | if (!dev_priv->pc8.enabled) | |
7020 | return; | |
7021 | ||
7022 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
7023 | ||
8771a7f8 PZ |
7024 | intel_runtime_pm_get(dev_priv); |
7025 | ||
c67a470b PZ |
7026 | hsw_restore_lcpll(dev_priv); |
7027 | hsw_pc8_restore_interrupts(dev); | |
7028 | lpt_init_pch_refclk(dev); | |
7029 | ||
7030 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7031 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7032 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7033 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7034 | } | |
7035 | ||
7036 | intel_prepare_ddi(dev); | |
7037 | i915_gem_init_swizzling(dev); | |
7038 | mutex_lock(&dev_priv->rps.hw_lock); | |
7039 | gen6_update_ring_freq(dev); | |
7040 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7041 | dev_priv->pc8.enabled = false; | |
7042 | } | |
7043 | ||
7044 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
7045 | { | |
7c6c2652 CW |
7046 | if (!HAS_PC8(dev_priv->dev)) |
7047 | return; | |
7048 | ||
c67a470b PZ |
7049 | mutex_lock(&dev_priv->pc8.lock); |
7050 | __hsw_enable_package_c8(dev_priv); | |
7051 | mutex_unlock(&dev_priv->pc8.lock); | |
7052 | } | |
7053 | ||
7054 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
7055 | { | |
7c6c2652 CW |
7056 | if (!HAS_PC8(dev_priv->dev)) |
7057 | return; | |
7058 | ||
c67a470b PZ |
7059 | mutex_lock(&dev_priv->pc8.lock); |
7060 | __hsw_disable_package_c8(dev_priv); | |
7061 | mutex_unlock(&dev_priv->pc8.lock); | |
7062 | } | |
7063 | ||
7064 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
7065 | { | |
7066 | struct drm_device *dev = dev_priv->dev; | |
7067 | struct intel_crtc *crtc; | |
7068 | uint32_t val; | |
7069 | ||
7070 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
7071 | if (crtc->base.enabled) | |
7072 | return false; | |
7073 | ||
7074 | /* This case is still possible since we have the i915.disable_power_well | |
7075 | * parameter and also the KVMr or something else might be requesting the | |
7076 | * power well. */ | |
7077 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
7078 | if (val != 0) { | |
7079 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
7080 | return false; | |
7081 | } | |
7082 | ||
7083 | return true; | |
7084 | } | |
7085 | ||
7086 | /* Since we're called from modeset_global_resources there's no way to | |
7087 | * symmetrically increase and decrease the refcount, so we use | |
7088 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
7089 | * or not. | |
7090 | */ | |
7091 | static void hsw_update_package_c8(struct drm_device *dev) | |
7092 | { | |
7093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7094 | bool allow; | |
7095 | ||
7c6c2652 CW |
7096 | if (!HAS_PC8(dev_priv->dev)) |
7097 | return; | |
7098 | ||
d330a953 | 7099 | if (!i915.enable_pc8) |
c67a470b PZ |
7100 | return; |
7101 | ||
7102 | mutex_lock(&dev_priv->pc8.lock); | |
7103 | ||
7104 | allow = hsw_can_enable_package_c8(dev_priv); | |
7105 | ||
7106 | if (allow == dev_priv->pc8.requirements_met) | |
7107 | goto done; | |
7108 | ||
7109 | dev_priv->pc8.requirements_met = allow; | |
7110 | ||
7111 | if (allow) | |
7112 | __hsw_enable_package_c8(dev_priv); | |
7113 | else | |
7114 | __hsw_disable_package_c8(dev_priv); | |
7115 | ||
7116 | done: | |
7117 | mutex_unlock(&dev_priv->pc8.lock); | |
7118 | } | |
7119 | ||
4f074129 ID |
7120 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7121 | { | |
da723569 | 7122 | modeset_update_crtc_power_domains(dev); |
c67a470b | 7123 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
7124 | } |
7125 | ||
09b4ddf9 | 7126 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7127 | int x, int y, |
7128 | struct drm_framebuffer *fb) | |
7129 | { | |
7130 | struct drm_device *dev = crtc->dev; | |
7131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 7133 | int plane = intel_crtc->plane; |
09b4ddf9 | 7134 | int ret; |
09b4ddf9 | 7135 | |
566b734a | 7136 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7137 | return -EINVAL; |
566b734a | 7138 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7139 | |
03afc4a2 DV |
7140 | if (intel_crtc->config.has_dp_encoder) |
7141 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
7142 | |
7143 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 7144 | |
8a654f3b | 7145 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 7146 | |
ca3a0ff8 | 7147 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
7148 | intel_cpu_transcoder_set_m_n(intel_crtc, |
7149 | &intel_crtc->config.fdi_m_n); | |
7150 | } | |
09b4ddf9 | 7151 | |
6ff93609 | 7152 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 7153 | |
50f3b016 | 7154 | intel_set_pipe_csc(crtc); |
86d3efce | 7155 | |
09b4ddf9 | 7156 | /* Set up the display plane register */ |
86d3efce | 7157 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
7158 | POSTING_READ(DSPCNTR(plane)); |
7159 | ||
7160 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
7161 | ||
1f803ee5 | 7162 | return ret; |
79e53945 JB |
7163 | } |
7164 | ||
0e8ffe1b DV |
7165 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7166 | struct intel_crtc_config *pipe_config) | |
7167 | { | |
7168 | struct drm_device *dev = crtc->base.dev; | |
7169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7170 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7171 | uint32_t tmp; |
7172 | ||
b5482bd0 ID |
7173 | if (!intel_display_power_enabled(dev_priv, |
7174 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7175 | return false; | |
7176 | ||
e143a21c | 7177 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7178 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7179 | ||
eccb140b DV |
7180 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7181 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7182 | enum pipe trans_edp_pipe; | |
7183 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7184 | default: | |
7185 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7186 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7187 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7188 | trans_edp_pipe = PIPE_A; | |
7189 | break; | |
7190 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7191 | trans_edp_pipe = PIPE_B; | |
7192 | break; | |
7193 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7194 | trans_edp_pipe = PIPE_C; | |
7195 | break; | |
7196 | } | |
7197 | ||
7198 | if (trans_edp_pipe == crtc->pipe) | |
7199 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7200 | } | |
7201 | ||
da7e29bd | 7202 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7203 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7204 | return false; |
7205 | ||
eccb140b | 7206 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7207 | if (!(tmp & PIPECONF_ENABLE)) |
7208 | return false; | |
7209 | ||
88adfff1 | 7210 | /* |
f196e6be | 7211 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7212 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7213 | * the PCH transcoder is on. | |
7214 | */ | |
eccb140b | 7215 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7216 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7217 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7218 | pipe_config->has_pch_encoder = true; |
7219 | ||
627eb5a3 DV |
7220 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7221 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7222 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7223 | |
7224 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7225 | } |
7226 | ||
1bd1bd80 DV |
7227 | intel_get_pipe_timings(crtc, pipe_config); |
7228 | ||
2fa2fe9a | 7229 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7230 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7231 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7232 | |
e59150dc JB |
7233 | if (IS_HASWELL(dev)) |
7234 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7235 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7236 | |
6c49f241 DV |
7237 | pipe_config->pixel_multiplier = 1; |
7238 | ||
0e8ffe1b DV |
7239 | return true; |
7240 | } | |
7241 | ||
f564048e | 7242 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 7243 | int x, int y, |
94352cf9 | 7244 | struct drm_framebuffer *fb) |
f564048e EA |
7245 | { |
7246 | struct drm_device *dev = crtc->dev; | |
7247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 7248 | struct intel_encoder *encoder; |
0b701d27 | 7249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 7250 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 7251 | int pipe = intel_crtc->pipe; |
f564048e EA |
7252 | int ret; |
7253 | ||
0b701d27 | 7254 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 7255 | |
b8cecdf5 DV |
7256 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7257 | ||
79e53945 | 7258 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 7259 | |
9256aa19 DV |
7260 | if (ret != 0) |
7261 | return ret; | |
7262 | ||
7263 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7264 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
7265 | encoder->base.base.id, | |
7266 | drm_get_encoder_name(&encoder->base), | |
7267 | mode->base.id, mode->name); | |
36f2d1f1 | 7268 | encoder->mode_set(encoder); |
9256aa19 DV |
7269 | } |
7270 | ||
7271 | return 0; | |
79e53945 JB |
7272 | } |
7273 | ||
1a91510d JN |
7274 | static struct { |
7275 | int clock; | |
7276 | u32 config; | |
7277 | } hdmi_audio_clock[] = { | |
7278 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7279 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7280 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7281 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7282 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7283 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7284 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7285 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7286 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7287 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7288 | }; | |
7289 | ||
7290 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7291 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7292 | { | |
7293 | int i; | |
7294 | ||
7295 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7296 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7297 | break; | |
7298 | } | |
7299 | ||
7300 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7301 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7302 | i = 1; | |
7303 | } | |
7304 | ||
7305 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7306 | hdmi_audio_clock[i].clock, | |
7307 | hdmi_audio_clock[i].config); | |
7308 | ||
7309 | return hdmi_audio_clock[i].config; | |
7310 | } | |
7311 | ||
3a9627f4 WF |
7312 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7313 | int reg_eldv, uint32_t bits_eldv, | |
7314 | int reg_elda, uint32_t bits_elda, | |
7315 | int reg_edid) | |
7316 | { | |
7317 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7318 | uint8_t *eld = connector->eld; | |
7319 | uint32_t i; | |
7320 | ||
7321 | i = I915_READ(reg_eldv); | |
7322 | i &= bits_eldv; | |
7323 | ||
7324 | if (!eld[0]) | |
7325 | return !i; | |
7326 | ||
7327 | if (!i) | |
7328 | return false; | |
7329 | ||
7330 | i = I915_READ(reg_elda); | |
7331 | i &= ~bits_elda; | |
7332 | I915_WRITE(reg_elda, i); | |
7333 | ||
7334 | for (i = 0; i < eld[2]; i++) | |
7335 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7336 | return false; | |
7337 | ||
7338 | return true; | |
7339 | } | |
7340 | ||
e0dac65e | 7341 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7342 | struct drm_crtc *crtc, |
7343 | struct drm_display_mode *mode) | |
e0dac65e WF |
7344 | { |
7345 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7346 | uint8_t *eld = connector->eld; | |
7347 | uint32_t eldv; | |
7348 | uint32_t len; | |
7349 | uint32_t i; | |
7350 | ||
7351 | i = I915_READ(G4X_AUD_VID_DID); | |
7352 | ||
7353 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7354 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7355 | else | |
7356 | eldv = G4X_ELDV_DEVCTG; | |
7357 | ||
3a9627f4 WF |
7358 | if (intel_eld_uptodate(connector, |
7359 | G4X_AUD_CNTL_ST, eldv, | |
7360 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7361 | G4X_HDMIW_HDMIEDID)) | |
7362 | return; | |
7363 | ||
e0dac65e WF |
7364 | i = I915_READ(G4X_AUD_CNTL_ST); |
7365 | i &= ~(eldv | G4X_ELD_ADDR); | |
7366 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7367 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7368 | ||
7369 | if (!eld[0]) | |
7370 | return; | |
7371 | ||
7372 | len = min_t(uint8_t, eld[2], len); | |
7373 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7374 | for (i = 0; i < len; i++) | |
7375 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7376 | ||
7377 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7378 | i |= eldv; | |
7379 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7380 | } | |
7381 | ||
83358c85 | 7382 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7383 | struct drm_crtc *crtc, |
7384 | struct drm_display_mode *mode) | |
83358c85 WX |
7385 | { |
7386 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7387 | uint8_t *eld = connector->eld; | |
7388 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7389 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7390 | uint32_t eldv; |
7391 | uint32_t i; | |
7392 | int len; | |
7393 | int pipe = to_intel_crtc(crtc)->pipe; | |
7394 | int tmp; | |
7395 | ||
7396 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7397 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7398 | int aud_config = HSW_AUD_CFG(pipe); | |
7399 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7400 | ||
7401 | ||
7402 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7403 | ||
7404 | /* Audio output enable */ | |
7405 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7406 | tmp = I915_READ(aud_cntrl_st2); | |
7407 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7408 | I915_WRITE(aud_cntrl_st2, tmp); | |
7409 | ||
7410 | /* Wait for 1 vertical blank */ | |
7411 | intel_wait_for_vblank(dev, pipe); | |
7412 | ||
7413 | /* Set ELD valid state */ | |
7414 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7415 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7416 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7417 | I915_WRITE(aud_cntrl_st2, tmp); | |
7418 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7419 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7420 | |
7421 | /* Enable HDMI mode */ | |
7422 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7423 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7424 | /* clear N_programing_enable and N_value_index */ |
7425 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7426 | I915_WRITE(aud_config, tmp); | |
7427 | ||
7428 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7429 | ||
7430 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7431 | intel_crtc->eld_vld = true; |
83358c85 WX |
7432 | |
7433 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7434 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7435 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7436 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7437 | } else { |
7438 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7439 | } | |
83358c85 WX |
7440 | |
7441 | if (intel_eld_uptodate(connector, | |
7442 | aud_cntrl_st2, eldv, | |
7443 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7444 | hdmiw_hdmiedid)) | |
7445 | return; | |
7446 | ||
7447 | i = I915_READ(aud_cntrl_st2); | |
7448 | i &= ~eldv; | |
7449 | I915_WRITE(aud_cntrl_st2, i); | |
7450 | ||
7451 | if (!eld[0]) | |
7452 | return; | |
7453 | ||
7454 | i = I915_READ(aud_cntl_st); | |
7455 | i &= ~IBX_ELD_ADDRESS; | |
7456 | I915_WRITE(aud_cntl_st, i); | |
7457 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7458 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7459 | ||
7460 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7461 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7462 | for (i = 0; i < len; i++) | |
7463 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7464 | ||
7465 | i = I915_READ(aud_cntrl_st2); | |
7466 | i |= eldv; | |
7467 | I915_WRITE(aud_cntrl_st2, i); | |
7468 | ||
7469 | } | |
7470 | ||
e0dac65e | 7471 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7472 | struct drm_crtc *crtc, |
7473 | struct drm_display_mode *mode) | |
e0dac65e WF |
7474 | { |
7475 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7476 | uint8_t *eld = connector->eld; | |
7477 | uint32_t eldv; | |
7478 | uint32_t i; | |
7479 | int len; | |
7480 | int hdmiw_hdmiedid; | |
b6daa025 | 7481 | int aud_config; |
e0dac65e WF |
7482 | int aud_cntl_st; |
7483 | int aud_cntrl_st2; | |
9b138a83 | 7484 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7485 | |
b3f33cbf | 7486 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7487 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7488 | aud_config = IBX_AUD_CFG(pipe); | |
7489 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7490 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7491 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7492 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7493 | aud_config = VLV_AUD_CFG(pipe); | |
7494 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7495 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7496 | } else { |
9b138a83 WX |
7497 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7498 | aud_config = CPT_AUD_CFG(pipe); | |
7499 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7500 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7501 | } |
7502 | ||
9b138a83 | 7503 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7504 | |
9ca2fe73 ML |
7505 | if (IS_VALLEYVIEW(connector->dev)) { |
7506 | struct intel_encoder *intel_encoder; | |
7507 | struct intel_digital_port *intel_dig_port; | |
7508 | ||
7509 | intel_encoder = intel_attached_encoder(connector); | |
7510 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7511 | i = intel_dig_port->port; | |
7512 | } else { | |
7513 | i = I915_READ(aud_cntl_st); | |
7514 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7515 | /* DIP_Port_Select, 0x1 = PortB */ | |
7516 | } | |
7517 | ||
e0dac65e WF |
7518 | if (!i) { |
7519 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7520 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7521 | eldv = IBX_ELD_VALIDB; |
7522 | eldv |= IBX_ELD_VALIDB << 4; | |
7523 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7524 | } else { |
2582a850 | 7525 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7526 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7527 | } |
7528 | ||
3a9627f4 WF |
7529 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7530 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7531 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7532 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7533 | } else { |
7534 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7535 | } | |
e0dac65e | 7536 | |
3a9627f4 WF |
7537 | if (intel_eld_uptodate(connector, |
7538 | aud_cntrl_st2, eldv, | |
7539 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7540 | hdmiw_hdmiedid)) | |
7541 | return; | |
7542 | ||
e0dac65e WF |
7543 | i = I915_READ(aud_cntrl_st2); |
7544 | i &= ~eldv; | |
7545 | I915_WRITE(aud_cntrl_st2, i); | |
7546 | ||
7547 | if (!eld[0]) | |
7548 | return; | |
7549 | ||
e0dac65e | 7550 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7551 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7552 | I915_WRITE(aud_cntl_st, i); |
7553 | ||
7554 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7555 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7556 | for (i = 0; i < len; i++) | |
7557 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7558 | ||
7559 | i = I915_READ(aud_cntrl_st2); | |
7560 | i |= eldv; | |
7561 | I915_WRITE(aud_cntrl_st2, i); | |
7562 | } | |
7563 | ||
7564 | void intel_write_eld(struct drm_encoder *encoder, | |
7565 | struct drm_display_mode *mode) | |
7566 | { | |
7567 | struct drm_crtc *crtc = encoder->crtc; | |
7568 | struct drm_connector *connector; | |
7569 | struct drm_device *dev = encoder->dev; | |
7570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7571 | ||
7572 | connector = drm_select_eld(encoder, mode); | |
7573 | if (!connector) | |
7574 | return; | |
7575 | ||
7576 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7577 | connector->base.id, | |
7578 | drm_get_connector_name(connector), | |
7579 | connector->encoder->base.id, | |
7580 | drm_get_encoder_name(connector->encoder)); | |
7581 | ||
7582 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7583 | ||
7584 | if (dev_priv->display.write_eld) | |
34427052 | 7585 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7586 | } |
7587 | ||
560b85bb CW |
7588 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7589 | { | |
7590 | struct drm_device *dev = crtc->dev; | |
7591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7593 | bool visible = base != 0; | |
7594 | u32 cntl; | |
7595 | ||
7596 | if (intel_crtc->cursor_visible == visible) | |
7597 | return; | |
7598 | ||
9db4a9c7 | 7599 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7600 | if (visible) { |
7601 | /* On these chipsets we can only modify the base whilst | |
7602 | * the cursor is disabled. | |
7603 | */ | |
9db4a9c7 | 7604 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7605 | |
7606 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7607 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7608 | cntl |= CURSOR_ENABLE | | |
7609 | CURSOR_GAMMA_ENABLE | | |
7610 | CURSOR_FORMAT_ARGB; | |
7611 | } else | |
7612 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7613 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7614 | |
7615 | intel_crtc->cursor_visible = visible; | |
7616 | } | |
7617 | ||
7618 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7619 | { | |
7620 | struct drm_device *dev = crtc->dev; | |
7621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7622 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7623 | int pipe = intel_crtc->pipe; | |
7624 | bool visible = base != 0; | |
7625 | ||
7626 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7627 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7628 | if (base) { |
7629 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7630 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7631 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7632 | } else { | |
7633 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7634 | cntl |= CURSOR_MODE_DISABLE; | |
7635 | } | |
9db4a9c7 | 7636 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7637 | |
7638 | intel_crtc->cursor_visible = visible; | |
7639 | } | |
7640 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7641 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7642 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7643 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7644 | } |
7645 | ||
65a21cd6 JB |
7646 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7647 | { | |
7648 | struct drm_device *dev = crtc->dev; | |
7649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7651 | int pipe = intel_crtc->pipe; | |
7652 | bool visible = base != 0; | |
7653 | ||
7654 | if (intel_crtc->cursor_visible != visible) { | |
7655 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7656 | if (base) { | |
7657 | cntl &= ~CURSOR_MODE; | |
7658 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7659 | } else { | |
7660 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7661 | cntl |= CURSOR_MODE_DISABLE; | |
7662 | } | |
6bbfa1c5 | 7663 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7664 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7665 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7666 | } | |
65a21cd6 JB |
7667 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7668 | ||
7669 | intel_crtc->cursor_visible = visible; | |
7670 | } | |
7671 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7672 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7673 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7674 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7675 | } |
7676 | ||
cda4b7d3 | 7677 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7678 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7679 | bool on) | |
cda4b7d3 CW |
7680 | { |
7681 | struct drm_device *dev = crtc->dev; | |
7682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7684 | int pipe = intel_crtc->pipe; | |
7685 | int x = intel_crtc->cursor_x; | |
7686 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7687 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7688 | bool visible; |
7689 | ||
d6e4db15 | 7690 | if (on) |
cda4b7d3 | 7691 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7692 | |
d6e4db15 VS |
7693 | if (x >= intel_crtc->config.pipe_src_w) |
7694 | base = 0; | |
7695 | ||
7696 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7697 | base = 0; |
7698 | ||
7699 | if (x < 0) { | |
efc9064e | 7700 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7701 | base = 0; |
7702 | ||
7703 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7704 | x = -x; | |
7705 | } | |
7706 | pos |= x << CURSOR_X_SHIFT; | |
7707 | ||
7708 | if (y < 0) { | |
efc9064e | 7709 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7710 | base = 0; |
7711 | ||
7712 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7713 | y = -y; | |
7714 | } | |
7715 | pos |= y << CURSOR_Y_SHIFT; | |
7716 | ||
7717 | visible = base != 0; | |
560b85bb | 7718 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7719 | return; |
7720 | ||
b3dc685e | 7721 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7722 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7723 | ivb_update_cursor(crtc, base); | |
7724 | } else { | |
7725 | I915_WRITE(CURPOS(pipe), pos); | |
7726 | if (IS_845G(dev) || IS_I865G(dev)) | |
7727 | i845_update_cursor(crtc, base); | |
7728 | else | |
7729 | i9xx_update_cursor(crtc, base); | |
7730 | } | |
cda4b7d3 CW |
7731 | } |
7732 | ||
79e53945 | 7733 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7734 | struct drm_file *file, |
79e53945 JB |
7735 | uint32_t handle, |
7736 | uint32_t width, uint32_t height) | |
7737 | { | |
7738 | struct drm_device *dev = crtc->dev; | |
7739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7741 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7742 | uint32_t addr; |
3f8bc370 | 7743 | int ret; |
79e53945 | 7744 | |
79e53945 JB |
7745 | /* if we want to turn off the cursor ignore width and height */ |
7746 | if (!handle) { | |
28c97730 | 7747 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7748 | addr = 0; |
05394f39 | 7749 | obj = NULL; |
5004417d | 7750 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7751 | goto finish; |
79e53945 JB |
7752 | } |
7753 | ||
7754 | /* Currently we only support 64x64 cursors */ | |
7755 | if (width != 64 || height != 64) { | |
7756 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7757 | return -EINVAL; | |
7758 | } | |
7759 | ||
05394f39 | 7760 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7761 | if (&obj->base == NULL) |
79e53945 JB |
7762 | return -ENOENT; |
7763 | ||
05394f39 | 7764 | if (obj->base.size < width * height * 4) { |
3b25b31f | 7765 | DRM_DEBUG_KMS("buffer is to small\n"); |
34b8686e DA |
7766 | ret = -ENOMEM; |
7767 | goto fail; | |
79e53945 JB |
7768 | } |
7769 | ||
71acb5eb | 7770 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7771 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 7772 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
7773 | unsigned alignment; |
7774 | ||
d9e86c0e | 7775 | if (obj->tiling_mode) { |
3b25b31f | 7776 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
7777 | ret = -EINVAL; |
7778 | goto fail_locked; | |
7779 | } | |
7780 | ||
693db184 CW |
7781 | /* Note that the w/a also requires 2 PTE of padding following |
7782 | * the bo. We currently fill all unused PTE with the shadow | |
7783 | * page and so we should always have valid PTE following the | |
7784 | * cursor preventing the VT-d warning. | |
7785 | */ | |
7786 | alignment = 0; | |
7787 | if (need_vtd_wa(dev)) | |
7788 | alignment = 64*1024; | |
7789 | ||
7790 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 7791 | if (ret) { |
3b25b31f | 7792 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 7793 | goto fail_locked; |
e7b526bb CW |
7794 | } |
7795 | ||
d9e86c0e CW |
7796 | ret = i915_gem_object_put_fence(obj); |
7797 | if (ret) { | |
3b25b31f | 7798 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
7799 | goto fail_unpin; |
7800 | } | |
7801 | ||
f343c5f6 | 7802 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7803 | } else { |
6eeefaf3 | 7804 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7805 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7806 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7807 | align); | |
71acb5eb | 7808 | if (ret) { |
3b25b31f | 7809 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 7810 | goto fail_locked; |
71acb5eb | 7811 | } |
05394f39 | 7812 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7813 | } |
7814 | ||
a6c45cf0 | 7815 | if (IS_GEN2(dev)) |
14b60391 JB |
7816 | I915_WRITE(CURSIZE, (height << 12) | width); |
7817 | ||
3f8bc370 | 7818 | finish: |
3f8bc370 | 7819 | if (intel_crtc->cursor_bo) { |
3d13ef2e | 7820 | if (INTEL_INFO(dev)->cursor_needs_physical) { |
05394f39 | 7821 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7822 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7823 | } else | |
cc98b413 | 7824 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7825 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7826 | } |
80824003 | 7827 | |
7f9872e0 | 7828 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7829 | |
7830 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7831 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7832 | intel_crtc->cursor_width = width; |
7833 | intel_crtc->cursor_height = height; | |
7834 | ||
f2f5f771 VS |
7835 | if (intel_crtc->active) |
7836 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7837 | |
79e53945 | 7838 | return 0; |
e7b526bb | 7839 | fail_unpin: |
cc98b413 | 7840 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7841 | fail_locked: |
34b8686e | 7842 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7843 | fail: |
05394f39 | 7844 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7845 | return ret; |
79e53945 JB |
7846 | } |
7847 | ||
7848 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7849 | { | |
79e53945 | 7850 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7851 | |
92e76c8c VS |
7852 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7853 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7854 | |
f2f5f771 VS |
7855 | if (intel_crtc->active) |
7856 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7857 | |
7858 | return 0; | |
b8c00ac5 DA |
7859 | } |
7860 | ||
79e53945 | 7861 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7862 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7863 | { |
7203425a | 7864 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7865 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7866 | |
7203425a | 7867 | for (i = start; i < end; i++) { |
79e53945 JB |
7868 | intel_crtc->lut_r[i] = red[i] >> 8; |
7869 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7870 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7871 | } | |
7872 | ||
7873 | intel_crtc_load_lut(crtc); | |
7874 | } | |
7875 | ||
79e53945 JB |
7876 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7877 | static struct drm_display_mode load_detect_mode = { | |
7878 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7879 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7880 | }; | |
7881 | ||
a8bb6818 DV |
7882 | struct drm_framebuffer * |
7883 | __intel_framebuffer_create(struct drm_device *dev, | |
7884 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7885 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
7886 | { |
7887 | struct intel_framebuffer *intel_fb; | |
7888 | int ret; | |
7889 | ||
7890 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7891 | if (!intel_fb) { | |
7892 | drm_gem_object_unreference_unlocked(&obj->base); | |
7893 | return ERR_PTR(-ENOMEM); | |
7894 | } | |
7895 | ||
7896 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
7897 | if (ret) |
7898 | goto err; | |
d2dff872 CW |
7899 | |
7900 | return &intel_fb->base; | |
dd4916c5 DV |
7901 | err: |
7902 | drm_gem_object_unreference_unlocked(&obj->base); | |
7903 | kfree(intel_fb); | |
7904 | ||
7905 | return ERR_PTR(ret); | |
d2dff872 CW |
7906 | } |
7907 | ||
b5ea642a | 7908 | static struct drm_framebuffer * |
a8bb6818 DV |
7909 | intel_framebuffer_create(struct drm_device *dev, |
7910 | struct drm_mode_fb_cmd2 *mode_cmd, | |
7911 | struct drm_i915_gem_object *obj) | |
7912 | { | |
7913 | struct drm_framebuffer *fb; | |
7914 | int ret; | |
7915 | ||
7916 | ret = i915_mutex_lock_interruptible(dev); | |
7917 | if (ret) | |
7918 | return ERR_PTR(ret); | |
7919 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
7920 | mutex_unlock(&dev->struct_mutex); | |
7921 | ||
7922 | return fb; | |
7923 | } | |
7924 | ||
d2dff872 CW |
7925 | static u32 |
7926 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7927 | { | |
7928 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7929 | return ALIGN(pitch, 64); | |
7930 | } | |
7931 | ||
7932 | static u32 | |
7933 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7934 | { | |
7935 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7936 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7937 | } | |
7938 | ||
7939 | static struct drm_framebuffer * | |
7940 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7941 | struct drm_display_mode *mode, | |
7942 | int depth, int bpp) | |
7943 | { | |
7944 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7945 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7946 | |
7947 | obj = i915_gem_alloc_object(dev, | |
7948 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7949 | if (obj == NULL) | |
7950 | return ERR_PTR(-ENOMEM); | |
7951 | ||
7952 | mode_cmd.width = mode->hdisplay; | |
7953 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7954 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7955 | bpp); | |
5ca0c34a | 7956 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7957 | |
7958 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7959 | } | |
7960 | ||
7961 | static struct drm_framebuffer * | |
7962 | mode_fits_in_fbdev(struct drm_device *dev, | |
7963 | struct drm_display_mode *mode) | |
7964 | { | |
4520f53a | 7965 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7966 | struct drm_i915_private *dev_priv = dev->dev_private; |
7967 | struct drm_i915_gem_object *obj; | |
7968 | struct drm_framebuffer *fb; | |
7969 | ||
4c0e5528 | 7970 | if (!dev_priv->fbdev) |
d2dff872 CW |
7971 | return NULL; |
7972 | ||
4c0e5528 | 7973 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
7974 | return NULL; |
7975 | ||
4c0e5528 DV |
7976 | obj = dev_priv->fbdev->fb->obj; |
7977 | BUG_ON(!obj); | |
7978 | ||
8bcd4553 | 7979 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
7980 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7981 | fb->bits_per_pixel)) | |
d2dff872 CW |
7982 | return NULL; |
7983 | ||
01f2c773 | 7984 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7985 | return NULL; |
7986 | ||
7987 | return fb; | |
4520f53a DV |
7988 | #else |
7989 | return NULL; | |
7990 | #endif | |
d2dff872 CW |
7991 | } |
7992 | ||
d2434ab7 | 7993 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7994 | struct drm_display_mode *mode, |
8261b191 | 7995 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7996 | { |
7997 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7998 | struct intel_encoder *intel_encoder = |
7999 | intel_attached_encoder(connector); | |
79e53945 | 8000 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8001 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8002 | struct drm_crtc *crtc = NULL; |
8003 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8004 | struct drm_framebuffer *fb; |
79e53945 JB |
8005 | int i = -1; |
8006 | ||
d2dff872 CW |
8007 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8008 | connector->base.id, drm_get_connector_name(connector), | |
8009 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8010 | ||
79e53945 JB |
8011 | /* |
8012 | * Algorithm gets a little messy: | |
7a5e4805 | 8013 | * |
79e53945 JB |
8014 | * - if the connector already has an assigned crtc, use it (but make |
8015 | * sure it's on first) | |
7a5e4805 | 8016 | * |
79e53945 JB |
8017 | * - try to find the first unused crtc that can drive this connector, |
8018 | * and use that if we find one | |
79e53945 JB |
8019 | */ |
8020 | ||
8021 | /* See if we already have a CRTC for this connector */ | |
8022 | if (encoder->crtc) { | |
8023 | crtc = encoder->crtc; | |
8261b191 | 8024 | |
7b24056b DV |
8025 | mutex_lock(&crtc->mutex); |
8026 | ||
24218aac | 8027 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8028 | old->load_detect_temp = false; |
8029 | ||
8030 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8031 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8032 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8033 | |
7173188d | 8034 | return true; |
79e53945 JB |
8035 | } |
8036 | ||
8037 | /* Find an unused one (if possible) */ | |
8038 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
8039 | i++; | |
8040 | if (!(encoder->possible_crtcs & (1 << i))) | |
8041 | continue; | |
8042 | if (!possible_crtc->enabled) { | |
8043 | crtc = possible_crtc; | |
8044 | break; | |
8045 | } | |
79e53945 JB |
8046 | } |
8047 | ||
8048 | /* | |
8049 | * If we didn't find an unused CRTC, don't use any. | |
8050 | */ | |
8051 | if (!crtc) { | |
7173188d CW |
8052 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
8053 | return false; | |
79e53945 JB |
8054 | } |
8055 | ||
7b24056b | 8056 | mutex_lock(&crtc->mutex); |
fc303101 DV |
8057 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8058 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8059 | |
8060 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8061 | intel_crtc->new_enabled = true; |
8062 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8063 | old->dpms_mode = connector->dpms; |
8261b191 | 8064 | old->load_detect_temp = true; |
d2dff872 | 8065 | old->release_fb = NULL; |
79e53945 | 8066 | |
6492711d CW |
8067 | if (!mode) |
8068 | mode = &load_detect_mode; | |
79e53945 | 8069 | |
d2dff872 CW |
8070 | /* We need a framebuffer large enough to accommodate all accesses |
8071 | * that the plane may generate whilst we perform load detection. | |
8072 | * We can not rely on the fbcon either being present (we get called | |
8073 | * during its initialisation to detect all boot displays, or it may | |
8074 | * not even exist) or that it is large enough to satisfy the | |
8075 | * requested mode. | |
8076 | */ | |
94352cf9 DV |
8077 | fb = mode_fits_in_fbdev(dev, mode); |
8078 | if (fb == NULL) { | |
d2dff872 | 8079 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8080 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8081 | old->release_fb = fb; | |
d2dff872 CW |
8082 | } else |
8083 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8084 | if (IS_ERR(fb)) { |
d2dff872 | 8085 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8086 | goto fail; |
79e53945 | 8087 | } |
79e53945 | 8088 | |
c0c36b94 | 8089 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8090 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8091 | if (old->release_fb) |
8092 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8093 | goto fail; |
79e53945 | 8094 | } |
7173188d | 8095 | |
79e53945 | 8096 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8097 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8098 | return true; |
412b61d8 VS |
8099 | |
8100 | fail: | |
8101 | intel_crtc->new_enabled = crtc->enabled; | |
8102 | if (intel_crtc->new_enabled) | |
8103 | intel_crtc->new_config = &intel_crtc->config; | |
8104 | else | |
8105 | intel_crtc->new_config = NULL; | |
8106 | mutex_unlock(&crtc->mutex); | |
8107 | return false; | |
79e53945 JB |
8108 | } |
8109 | ||
d2434ab7 | 8110 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 8111 | struct intel_load_detect_pipe *old) |
79e53945 | 8112 | { |
d2434ab7 DV |
8113 | struct intel_encoder *intel_encoder = |
8114 | intel_attached_encoder(connector); | |
4ef69c7a | 8115 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8116 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8118 | |
d2dff872 CW |
8119 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
8120 | connector->base.id, drm_get_connector_name(connector), | |
8121 | encoder->base.id, drm_get_encoder_name(encoder)); | |
8122 | ||
8261b191 | 8123 | if (old->load_detect_temp) { |
fc303101 DV |
8124 | to_intel_connector(connector)->new_encoder = NULL; |
8125 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8126 | intel_crtc->new_enabled = false; |
8127 | intel_crtc->new_config = NULL; | |
fc303101 | 8128 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8129 | |
36206361 DV |
8130 | if (old->release_fb) { |
8131 | drm_framebuffer_unregister_private(old->release_fb); | |
8132 | drm_framebuffer_unreference(old->release_fb); | |
8133 | } | |
d2dff872 | 8134 | |
67c96400 | 8135 | mutex_unlock(&crtc->mutex); |
0622a53c | 8136 | return; |
79e53945 JB |
8137 | } |
8138 | ||
c751ce4f | 8139 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8140 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8141 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
8142 | |
8143 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
8144 | } |
8145 | ||
da4a1efa VS |
8146 | static int i9xx_pll_refclk(struct drm_device *dev, |
8147 | const struct intel_crtc_config *pipe_config) | |
8148 | { | |
8149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8150 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8151 | ||
8152 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8153 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8154 | else if (HAS_PCH_SPLIT(dev)) |
8155 | return 120000; | |
8156 | else if (!IS_GEN2(dev)) | |
8157 | return 96000; | |
8158 | else | |
8159 | return 48000; | |
8160 | } | |
8161 | ||
79e53945 | 8162 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8163 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8164 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8165 | { |
f1f644dc | 8166 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8167 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8168 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8169 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8170 | u32 fp; |
8171 | intel_clock_t clock; | |
da4a1efa | 8172 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8173 | |
8174 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8175 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8176 | else |
293623f7 | 8177 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8178 | |
8179 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8180 | if (IS_PINEVIEW(dev)) { |
8181 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8182 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8183 | } else { |
8184 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8185 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8186 | } | |
8187 | ||
a6c45cf0 | 8188 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8189 | if (IS_PINEVIEW(dev)) |
8190 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8191 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8192 | else |
8193 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8194 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8195 | ||
8196 | switch (dpll & DPLL_MODE_MASK) { | |
8197 | case DPLLB_MODE_DAC_SERIAL: | |
8198 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8199 | 5 : 10; | |
8200 | break; | |
8201 | case DPLLB_MODE_LVDS: | |
8202 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8203 | 7 : 14; | |
8204 | break; | |
8205 | default: | |
28c97730 | 8206 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8207 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8208 | return; |
79e53945 JB |
8209 | } |
8210 | ||
ac58c3f0 | 8211 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8212 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8213 | else |
da4a1efa | 8214 | i9xx_clock(refclk, &clock); |
79e53945 | 8215 | } else { |
0fb58223 | 8216 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8217 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8218 | |
8219 | if (is_lvds) { | |
8220 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8221 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8222 | |
8223 | if (lvds & LVDS_CLKB_POWER_UP) | |
8224 | clock.p2 = 7; | |
8225 | else | |
8226 | clock.p2 = 14; | |
79e53945 JB |
8227 | } else { |
8228 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8229 | clock.p1 = 2; | |
8230 | else { | |
8231 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8232 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8233 | } | |
8234 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8235 | clock.p2 = 4; | |
8236 | else | |
8237 | clock.p2 = 2; | |
79e53945 | 8238 | } |
da4a1efa VS |
8239 | |
8240 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8241 | } |
8242 | ||
18442d08 VS |
8243 | /* |
8244 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8245 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8246 | * encoder's get_config() function. |
8247 | */ | |
8248 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8249 | } |
8250 | ||
6878da05 VS |
8251 | int intel_dotclock_calculate(int link_freq, |
8252 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8253 | { |
f1f644dc JB |
8254 | /* |
8255 | * The calculation for the data clock is: | |
1041a02f | 8256 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8257 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8258 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8259 | * |
8260 | * and the link clock is simpler: | |
1041a02f | 8261 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8262 | */ |
8263 | ||
6878da05 VS |
8264 | if (!m_n->link_n) |
8265 | return 0; | |
f1f644dc | 8266 | |
6878da05 VS |
8267 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8268 | } | |
f1f644dc | 8269 | |
18442d08 VS |
8270 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8271 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8272 | { |
8273 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8274 | |
18442d08 VS |
8275 | /* read out port_clock from the DPLL */ |
8276 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8277 | |
f1f644dc | 8278 | /* |
18442d08 | 8279 | * This value does not include pixel_multiplier. |
241bfc38 | 8280 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8281 | * agree once we know their relationship in the encoder's |
8282 | * get_config() function. | |
79e53945 | 8283 | */ |
241bfc38 | 8284 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8285 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8286 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8287 | } |
8288 | ||
8289 | /** Returns the currently programmed mode of the given pipe. */ | |
8290 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8291 | struct drm_crtc *crtc) | |
8292 | { | |
548f245b | 8293 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8295 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8296 | struct drm_display_mode *mode; |
f1f644dc | 8297 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8298 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8299 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8300 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8301 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8302 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8303 | |
8304 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8305 | if (!mode) | |
8306 | return NULL; | |
8307 | ||
f1f644dc JB |
8308 | /* |
8309 | * Construct a pipe_config sufficient for getting the clock info | |
8310 | * back out of crtc_clock_get. | |
8311 | * | |
8312 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8313 | * to use a real value here instead. | |
8314 | */ | |
293623f7 | 8315 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8316 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8317 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8318 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8319 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8320 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8321 | ||
773ae034 | 8322 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8323 | mode->hdisplay = (htot & 0xffff) + 1; |
8324 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8325 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8326 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8327 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8328 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8329 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8330 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8331 | ||
8332 | drm_mode_set_name(mode); | |
79e53945 JB |
8333 | |
8334 | return mode; | |
8335 | } | |
8336 | ||
3dec0095 | 8337 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8338 | { |
8339 | struct drm_device *dev = crtc->dev; | |
8340 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8342 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8343 | int dpll_reg = DPLL(pipe); |
8344 | int dpll; | |
652c393a | 8345 | |
bad720ff | 8346 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8347 | return; |
8348 | ||
8349 | if (!dev_priv->lvds_downclock_avail) | |
8350 | return; | |
8351 | ||
dbdc6479 | 8352 | dpll = I915_READ(dpll_reg); |
652c393a | 8353 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8354 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8355 | |
8ac5a6d5 | 8356 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8357 | |
8358 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8359 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8360 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8361 | |
652c393a JB |
8362 | dpll = I915_READ(dpll_reg); |
8363 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8364 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8365 | } |
652c393a JB |
8366 | } |
8367 | ||
8368 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8369 | { | |
8370 | struct drm_device *dev = crtc->dev; | |
8371 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8373 | |
bad720ff | 8374 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8375 | return; |
8376 | ||
8377 | if (!dev_priv->lvds_downclock_avail) | |
8378 | return; | |
8379 | ||
8380 | /* | |
8381 | * Since this is called by a timer, we should never get here in | |
8382 | * the manual case. | |
8383 | */ | |
8384 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8385 | int pipe = intel_crtc->pipe; |
8386 | int dpll_reg = DPLL(pipe); | |
8387 | int dpll; | |
f6e5b160 | 8388 | |
44d98a61 | 8389 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8390 | |
8ac5a6d5 | 8391 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8392 | |
dc257cf1 | 8393 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8394 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8395 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8396 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8397 | dpll = I915_READ(dpll_reg); |
8398 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8399 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8400 | } |
8401 | ||
8402 | } | |
8403 | ||
f047e395 CW |
8404 | void intel_mark_busy(struct drm_device *dev) |
8405 | { | |
c67a470b PZ |
8406 | struct drm_i915_private *dev_priv = dev->dev_private; |
8407 | ||
f62a0076 CW |
8408 | if (dev_priv->mm.busy) |
8409 | return; | |
8410 | ||
86c4ec0d | 8411 | hsw_disable_package_c8(dev_priv); |
c67a470b | 8412 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8413 | dev_priv->mm.busy = true; |
f047e395 CW |
8414 | } |
8415 | ||
8416 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8417 | { |
c67a470b | 8418 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8419 | struct drm_crtc *crtc; |
652c393a | 8420 | |
f62a0076 CW |
8421 | if (!dev_priv->mm.busy) |
8422 | return; | |
8423 | ||
8424 | dev_priv->mm.busy = false; | |
8425 | ||
d330a953 | 8426 | if (!i915.powersave) |
bb4cdd53 | 8427 | goto out; |
652c393a | 8428 | |
652c393a | 8429 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8430 | if (!crtc->fb) |
8431 | continue; | |
8432 | ||
725a5b54 | 8433 | intel_decrease_pllclock(crtc); |
652c393a | 8434 | } |
b29c19b6 | 8435 | |
3d13ef2e | 8436 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8437 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8438 | |
8439 | out: | |
86c4ec0d | 8440 | hsw_enable_package_c8(dev_priv); |
652c393a JB |
8441 | } |
8442 | ||
c65355bb CW |
8443 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8444 | struct intel_ring_buffer *ring) | |
652c393a | 8445 | { |
f047e395 CW |
8446 | struct drm_device *dev = obj->base.dev; |
8447 | struct drm_crtc *crtc; | |
652c393a | 8448 | |
d330a953 | 8449 | if (!i915.powersave) |
acb87dfb CW |
8450 | return; |
8451 | ||
652c393a JB |
8452 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8453 | if (!crtc->fb) | |
8454 | continue; | |
8455 | ||
c65355bb CW |
8456 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8457 | continue; | |
8458 | ||
8459 | intel_increase_pllclock(crtc); | |
8460 | if (ring && intel_fbc_enabled(dev)) | |
8461 | ring->fbc_dirty = true; | |
652c393a JB |
8462 | } |
8463 | } | |
8464 | ||
79e53945 JB |
8465 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8466 | { | |
8467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8468 | struct drm_device *dev = crtc->dev; |
8469 | struct intel_unpin_work *work; | |
8470 | unsigned long flags; | |
8471 | ||
8472 | spin_lock_irqsave(&dev->event_lock, flags); | |
8473 | work = intel_crtc->unpin_work; | |
8474 | intel_crtc->unpin_work = NULL; | |
8475 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8476 | ||
8477 | if (work) { | |
8478 | cancel_work_sync(&work->work); | |
8479 | kfree(work); | |
8480 | } | |
79e53945 | 8481 | |
40ccc72b MK |
8482 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8483 | ||
79e53945 | 8484 | drm_crtc_cleanup(crtc); |
67e77c5a | 8485 | |
79e53945 JB |
8486 | kfree(intel_crtc); |
8487 | } | |
8488 | ||
6b95a207 KH |
8489 | static void intel_unpin_work_fn(struct work_struct *__work) |
8490 | { | |
8491 | struct intel_unpin_work *work = | |
8492 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8493 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8494 | |
b4a98e57 | 8495 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8496 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8497 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8498 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8499 | |
b4a98e57 CW |
8500 | intel_update_fbc(dev); |
8501 | mutex_unlock(&dev->struct_mutex); | |
8502 | ||
8503 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8504 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8505 | ||
6b95a207 KH |
8506 | kfree(work); |
8507 | } | |
8508 | ||
1afe3e9d | 8509 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8510 | struct drm_crtc *crtc) |
6b95a207 KH |
8511 | { |
8512 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8514 | struct intel_unpin_work *work; | |
6b95a207 KH |
8515 | unsigned long flags; |
8516 | ||
8517 | /* Ignore early vblank irqs */ | |
8518 | if (intel_crtc == NULL) | |
8519 | return; | |
8520 | ||
8521 | spin_lock_irqsave(&dev->event_lock, flags); | |
8522 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8523 | |
8524 | /* Ensure we don't miss a work->pending update ... */ | |
8525 | smp_rmb(); | |
8526 | ||
8527 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8528 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8529 | return; | |
8530 | } | |
8531 | ||
e7d841ca CW |
8532 | /* and that the unpin work is consistent wrt ->pending. */ |
8533 | smp_rmb(); | |
8534 | ||
6b95a207 | 8535 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8536 | |
45a066eb RC |
8537 | if (work->event) |
8538 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8539 | |
0af7e4df MK |
8540 | drm_vblank_put(dev, intel_crtc->pipe); |
8541 | ||
6b95a207 KH |
8542 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8543 | ||
2c10d571 | 8544 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8545 | |
8546 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8547 | |
8548 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8549 | } |
8550 | ||
1afe3e9d JB |
8551 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8552 | { | |
8553 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8554 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8555 | ||
49b14a5c | 8556 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8557 | } |
8558 | ||
8559 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8560 | { | |
8561 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8562 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8563 | ||
49b14a5c | 8564 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8565 | } |
8566 | ||
6b95a207 KH |
8567 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8568 | { | |
8569 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8570 | struct intel_crtc *intel_crtc = | |
8571 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8572 | unsigned long flags; | |
8573 | ||
e7d841ca CW |
8574 | /* NB: An MMIO update of the plane base pointer will also |
8575 | * generate a page-flip completion irq, i.e. every modeset | |
8576 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8577 | */ | |
6b95a207 | 8578 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8579 | if (intel_crtc->unpin_work) |
8580 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8581 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8582 | } | |
8583 | ||
e7d841ca CW |
8584 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8585 | { | |
8586 | /* Ensure that the work item is consistent when activating it ... */ | |
8587 | smp_wmb(); | |
8588 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8589 | /* and that it is marked active as soon as the irq could fire. */ | |
8590 | smp_wmb(); | |
8591 | } | |
8592 | ||
8c9f3aaf JB |
8593 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8594 | struct drm_crtc *crtc, | |
8595 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8596 | struct drm_i915_gem_object *obj, |
8597 | uint32_t flags) | |
8c9f3aaf JB |
8598 | { |
8599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8601 | u32 flip_mask; |
6d90c952 | 8602 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8603 | int ret; |
8604 | ||
6d90c952 | 8605 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8606 | if (ret) |
83d4092b | 8607 | goto err; |
8c9f3aaf | 8608 | |
6d90c952 | 8609 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8610 | if (ret) |
83d4092b | 8611 | goto err_unpin; |
8c9f3aaf JB |
8612 | |
8613 | /* Can't queue multiple flips, so wait for the previous | |
8614 | * one to finish before executing the next. | |
8615 | */ | |
8616 | if (intel_crtc->plane) | |
8617 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8618 | else | |
8619 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8620 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8621 | intel_ring_emit(ring, MI_NOOP); | |
8622 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8623 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8624 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8625 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8626 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8627 | |
8628 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8629 | __intel_ring_advance(ring); |
83d4092b CW |
8630 | return 0; |
8631 | ||
8632 | err_unpin: | |
8633 | intel_unpin_fb_obj(obj); | |
8634 | err: | |
8c9f3aaf JB |
8635 | return ret; |
8636 | } | |
8637 | ||
8638 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8639 | struct drm_crtc *crtc, | |
8640 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8641 | struct drm_i915_gem_object *obj, |
8642 | uint32_t flags) | |
8c9f3aaf JB |
8643 | { |
8644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8646 | u32 flip_mask; |
6d90c952 | 8647 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8648 | int ret; |
8649 | ||
6d90c952 | 8650 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8651 | if (ret) |
83d4092b | 8652 | goto err; |
8c9f3aaf | 8653 | |
6d90c952 | 8654 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8655 | if (ret) |
83d4092b | 8656 | goto err_unpin; |
8c9f3aaf JB |
8657 | |
8658 | if (intel_crtc->plane) | |
8659 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8660 | else | |
8661 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8662 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8663 | intel_ring_emit(ring, MI_NOOP); | |
8664 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8665 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8666 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8667 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8668 | intel_ring_emit(ring, MI_NOOP); |
8669 | ||
e7d841ca | 8670 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8671 | __intel_ring_advance(ring); |
83d4092b CW |
8672 | return 0; |
8673 | ||
8674 | err_unpin: | |
8675 | intel_unpin_fb_obj(obj); | |
8676 | err: | |
8c9f3aaf JB |
8677 | return ret; |
8678 | } | |
8679 | ||
8680 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8681 | struct drm_crtc *crtc, | |
8682 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8683 | struct drm_i915_gem_object *obj, |
8684 | uint32_t flags) | |
8c9f3aaf JB |
8685 | { |
8686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8687 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8688 | uint32_t pf, pipesrc; | |
6d90c952 | 8689 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8690 | int ret; |
8691 | ||
6d90c952 | 8692 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8693 | if (ret) |
83d4092b | 8694 | goto err; |
8c9f3aaf | 8695 | |
6d90c952 | 8696 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8697 | if (ret) |
83d4092b | 8698 | goto err_unpin; |
8c9f3aaf JB |
8699 | |
8700 | /* i965+ uses the linear or tiled offsets from the | |
8701 | * Display Registers (which do not change across a page-flip) | |
8702 | * so we need only reprogram the base address. | |
8703 | */ | |
6d90c952 DV |
8704 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8705 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8706 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8707 | intel_ring_emit(ring, |
f343c5f6 | 8708 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8709 | obj->tiling_mode); |
8c9f3aaf JB |
8710 | |
8711 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8712 | * untested on non-native modes, so ignore it for now. | |
8713 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8714 | */ | |
8715 | pf = 0; | |
8716 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8717 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8718 | |
8719 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8720 | __intel_ring_advance(ring); |
83d4092b CW |
8721 | return 0; |
8722 | ||
8723 | err_unpin: | |
8724 | intel_unpin_fb_obj(obj); | |
8725 | err: | |
8c9f3aaf JB |
8726 | return ret; |
8727 | } | |
8728 | ||
8729 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8730 | struct drm_crtc *crtc, | |
8731 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8732 | struct drm_i915_gem_object *obj, |
8733 | uint32_t flags) | |
8c9f3aaf JB |
8734 | { |
8735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8737 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8738 | uint32_t pf, pipesrc; |
8739 | int ret; | |
8740 | ||
6d90c952 | 8741 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8742 | if (ret) |
83d4092b | 8743 | goto err; |
8c9f3aaf | 8744 | |
6d90c952 | 8745 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8746 | if (ret) |
83d4092b | 8747 | goto err_unpin; |
8c9f3aaf | 8748 | |
6d90c952 DV |
8749 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8750 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8751 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8752 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8753 | |
dc257cf1 DV |
8754 | /* Contrary to the suggestions in the documentation, |
8755 | * "Enable Panel Fitter" does not seem to be required when page | |
8756 | * flipping with a non-native mode, and worse causes a normal | |
8757 | * modeset to fail. | |
8758 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8759 | */ | |
8760 | pf = 0; | |
8c9f3aaf | 8761 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8762 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8763 | |
8764 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8765 | __intel_ring_advance(ring); |
83d4092b CW |
8766 | return 0; |
8767 | ||
8768 | err_unpin: | |
8769 | intel_unpin_fb_obj(obj); | |
8770 | err: | |
8c9f3aaf JB |
8771 | return ret; |
8772 | } | |
8773 | ||
7c9017e5 JB |
8774 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8775 | struct drm_crtc *crtc, | |
8776 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8777 | struct drm_i915_gem_object *obj, |
8778 | uint32_t flags) | |
7c9017e5 JB |
8779 | { |
8780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8782 | struct intel_ring_buffer *ring; |
cb05d8de | 8783 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8784 | int len, ret; |
8785 | ||
8786 | ring = obj->ring; | |
1c5fd085 | 8787 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8788 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8789 | |
8790 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8791 | if (ret) | |
83d4092b | 8792 | goto err; |
7c9017e5 | 8793 | |
cb05d8de DV |
8794 | switch(intel_crtc->plane) { |
8795 | case PLANE_A: | |
8796 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8797 | break; | |
8798 | case PLANE_B: | |
8799 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8800 | break; | |
8801 | case PLANE_C: | |
8802 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8803 | break; | |
8804 | default: | |
8805 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8806 | ret = -ENODEV; | |
ab3951eb | 8807 | goto err_unpin; |
cb05d8de DV |
8808 | } |
8809 | ||
ffe74d75 CW |
8810 | len = 4; |
8811 | if (ring->id == RCS) | |
8812 | len += 6; | |
8813 | ||
8814 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8815 | if (ret) |
83d4092b | 8816 | goto err_unpin; |
7c9017e5 | 8817 | |
ffe74d75 CW |
8818 | /* Unmask the flip-done completion message. Note that the bspec says that |
8819 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8820 | * more than one flip event at any time (or ensure that one flip message | |
8821 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8822 | * Experimentation says that BCS works despite DERRMR masking all | |
8823 | * flip-done completion events and that unmasking all planes at once | |
8824 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8825 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8826 | */ | |
8827 | if (ring->id == RCS) { | |
8828 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8829 | intel_ring_emit(ring, DERRMR); | |
8830 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8831 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8832 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
22613c96 VS |
8833 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8834 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
8835 | intel_ring_emit(ring, DERRMR); |
8836 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8837 | } | |
8838 | ||
cb05d8de | 8839 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8840 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8841 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8842 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8843 | |
8844 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8845 | __intel_ring_advance(ring); |
83d4092b CW |
8846 | return 0; |
8847 | ||
8848 | err_unpin: | |
8849 | intel_unpin_fb_obj(obj); | |
8850 | err: | |
7c9017e5 JB |
8851 | return ret; |
8852 | } | |
8853 | ||
8c9f3aaf JB |
8854 | static int intel_default_queue_flip(struct drm_device *dev, |
8855 | struct drm_crtc *crtc, | |
8856 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8857 | struct drm_i915_gem_object *obj, |
8858 | uint32_t flags) | |
8c9f3aaf JB |
8859 | { |
8860 | return -ENODEV; | |
8861 | } | |
8862 | ||
6b95a207 KH |
8863 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8864 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8865 | struct drm_pending_vblank_event *event, |
8866 | uint32_t page_flip_flags) | |
6b95a207 KH |
8867 | { |
8868 | struct drm_device *dev = crtc->dev; | |
8869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8870 | struct drm_framebuffer *old_fb = crtc->fb; |
8871 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8873 | struct intel_unpin_work *work; | |
8c9f3aaf | 8874 | unsigned long flags; |
52e68630 | 8875 | int ret; |
6b95a207 | 8876 | |
e6a595d2 VS |
8877 | /* Can't change pixel format via MI display flips. */ |
8878 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8879 | return -EINVAL; | |
8880 | ||
8881 | /* | |
8882 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8883 | * Note that pitch changes could also affect these register. | |
8884 | */ | |
8885 | if (INTEL_INFO(dev)->gen > 3 && | |
8886 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8887 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8888 | return -EINVAL; | |
8889 | ||
f900db47 CW |
8890 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
8891 | goto out_hang; | |
8892 | ||
b14c5679 | 8893 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8894 | if (work == NULL) |
8895 | return -ENOMEM; | |
8896 | ||
6b95a207 | 8897 | work->event = event; |
b4a98e57 | 8898 | work->crtc = crtc; |
4a35f83b | 8899 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8900 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8901 | ||
7317c75e JB |
8902 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8903 | if (ret) | |
8904 | goto free_work; | |
8905 | ||
6b95a207 KH |
8906 | /* We borrow the event spin lock for protecting unpin_work */ |
8907 | spin_lock_irqsave(&dev->event_lock, flags); | |
8908 | if (intel_crtc->unpin_work) { | |
8909 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8910 | kfree(work); | |
7317c75e | 8911 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8912 | |
8913 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8914 | return -EBUSY; |
8915 | } | |
8916 | intel_crtc->unpin_work = work; | |
8917 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8918 | ||
b4a98e57 CW |
8919 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8920 | flush_workqueue(dev_priv->wq); | |
8921 | ||
79158103 CW |
8922 | ret = i915_mutex_lock_interruptible(dev); |
8923 | if (ret) | |
8924 | goto cleanup; | |
6b95a207 | 8925 | |
75dfca80 | 8926 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8927 | drm_gem_object_reference(&work->old_fb_obj->base); |
8928 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8929 | |
8930 | crtc->fb = fb; | |
96b099fd | 8931 | |
e1f99ce6 | 8932 | work->pending_flip_obj = obj; |
e1f99ce6 | 8933 | |
4e5359cd SF |
8934 | work->enable_stall_check = true; |
8935 | ||
b4a98e57 | 8936 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8937 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8938 | |
ed8d1975 | 8939 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8940 | if (ret) |
8941 | goto cleanup_pending; | |
6b95a207 | 8942 | |
7782de3b | 8943 | intel_disable_fbc(dev); |
c65355bb | 8944 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8945 | mutex_unlock(&dev->struct_mutex); |
8946 | ||
e5510fac JB |
8947 | trace_i915_flip_request(intel_crtc->plane, obj); |
8948 | ||
6b95a207 | 8949 | return 0; |
96b099fd | 8950 | |
8c9f3aaf | 8951 | cleanup_pending: |
b4a98e57 | 8952 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8953 | crtc->fb = old_fb; |
05394f39 CW |
8954 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8955 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8956 | mutex_unlock(&dev->struct_mutex); |
8957 | ||
79158103 | 8958 | cleanup: |
96b099fd CW |
8959 | spin_lock_irqsave(&dev->event_lock, flags); |
8960 | intel_crtc->unpin_work = NULL; | |
8961 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8962 | ||
7317c75e JB |
8963 | drm_vblank_put(dev, intel_crtc->pipe); |
8964 | free_work: | |
96b099fd CW |
8965 | kfree(work); |
8966 | ||
f900db47 CW |
8967 | if (ret == -EIO) { |
8968 | out_hang: | |
8969 | intel_crtc_wait_for_pending_flips(crtc); | |
8970 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
8971 | if (ret == 0 && event) | |
8972 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
8973 | } | |
96b099fd | 8974 | return ret; |
6b95a207 KH |
8975 | } |
8976 | ||
f6e5b160 | 8977 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8978 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8979 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8980 | }; |
8981 | ||
9a935856 DV |
8982 | /** |
8983 | * intel_modeset_update_staged_output_state | |
8984 | * | |
8985 | * Updates the staged output configuration state, e.g. after we've read out the | |
8986 | * current hw state. | |
8987 | */ | |
8988 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8989 | { |
7668851f | 8990 | struct intel_crtc *crtc; |
9a935856 DV |
8991 | struct intel_encoder *encoder; |
8992 | struct intel_connector *connector; | |
f6e5b160 | 8993 | |
9a935856 DV |
8994 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8995 | base.head) { | |
8996 | connector->new_encoder = | |
8997 | to_intel_encoder(connector->base.encoder); | |
8998 | } | |
f6e5b160 | 8999 | |
9a935856 DV |
9000 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9001 | base.head) { | |
9002 | encoder->new_crtc = | |
9003 | to_intel_crtc(encoder->base.crtc); | |
9004 | } | |
7668851f VS |
9005 | |
9006 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9007 | base.head) { | |
9008 | crtc->new_enabled = crtc->base.enabled; | |
7bd0a8e7 VS |
9009 | |
9010 | if (crtc->new_enabled) | |
9011 | crtc->new_config = &crtc->config; | |
9012 | else | |
9013 | crtc->new_config = NULL; | |
7668851f | 9014 | } |
f6e5b160 CW |
9015 | } |
9016 | ||
9a935856 DV |
9017 | /** |
9018 | * intel_modeset_commit_output_state | |
9019 | * | |
9020 | * This function copies the stage display pipe configuration to the real one. | |
9021 | */ | |
9022 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9023 | { | |
7668851f | 9024 | struct intel_crtc *crtc; |
9a935856 DV |
9025 | struct intel_encoder *encoder; |
9026 | struct intel_connector *connector; | |
f6e5b160 | 9027 | |
9a935856 DV |
9028 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9029 | base.head) { | |
9030 | connector->base.encoder = &connector->new_encoder->base; | |
9031 | } | |
f6e5b160 | 9032 | |
9a935856 DV |
9033 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9034 | base.head) { | |
9035 | encoder->base.crtc = &encoder->new_crtc->base; | |
9036 | } | |
7668851f VS |
9037 | |
9038 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9039 | base.head) { | |
9040 | crtc->base.enabled = crtc->new_enabled; | |
9041 | } | |
9a935856 DV |
9042 | } |
9043 | ||
050f7aeb DV |
9044 | static void |
9045 | connected_sink_compute_bpp(struct intel_connector * connector, | |
9046 | struct intel_crtc_config *pipe_config) | |
9047 | { | |
9048 | int bpp = pipe_config->pipe_bpp; | |
9049 | ||
9050 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9051 | connector->base.base.id, | |
9052 | drm_get_connector_name(&connector->base)); | |
9053 | ||
9054 | /* Don't use an invalid EDID bpc value */ | |
9055 | if (connector->base.display_info.bpc && | |
9056 | connector->base.display_info.bpc * 3 < bpp) { | |
9057 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9058 | bpp, connector->base.display_info.bpc*3); | |
9059 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9060 | } | |
9061 | ||
9062 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9063 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9064 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9065 | bpp); | |
9066 | pipe_config->pipe_bpp = 24; | |
9067 | } | |
9068 | } | |
9069 | ||
4e53c2e0 | 9070 | static int |
050f7aeb DV |
9071 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9072 | struct drm_framebuffer *fb, | |
9073 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9074 | { |
050f7aeb DV |
9075 | struct drm_device *dev = crtc->base.dev; |
9076 | struct intel_connector *connector; | |
4e53c2e0 DV |
9077 | int bpp; |
9078 | ||
d42264b1 DV |
9079 | switch (fb->pixel_format) { |
9080 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9081 | bpp = 8*3; /* since we go through a colormap */ |
9082 | break; | |
d42264b1 DV |
9083 | case DRM_FORMAT_XRGB1555: |
9084 | case DRM_FORMAT_ARGB1555: | |
9085 | /* checked in intel_framebuffer_init already */ | |
9086 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9087 | return -EINVAL; | |
9088 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9089 | bpp = 6*3; /* min is 18bpp */ |
9090 | break; | |
d42264b1 DV |
9091 | case DRM_FORMAT_XBGR8888: |
9092 | case DRM_FORMAT_ABGR8888: | |
9093 | /* checked in intel_framebuffer_init already */ | |
9094 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9095 | return -EINVAL; | |
9096 | case DRM_FORMAT_XRGB8888: | |
9097 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9098 | bpp = 8*3; |
9099 | break; | |
d42264b1 DV |
9100 | case DRM_FORMAT_XRGB2101010: |
9101 | case DRM_FORMAT_ARGB2101010: | |
9102 | case DRM_FORMAT_XBGR2101010: | |
9103 | case DRM_FORMAT_ABGR2101010: | |
9104 | /* checked in intel_framebuffer_init already */ | |
9105 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9106 | return -EINVAL; |
4e53c2e0 DV |
9107 | bpp = 10*3; |
9108 | break; | |
baba133a | 9109 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9110 | default: |
9111 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9112 | return -EINVAL; | |
9113 | } | |
9114 | ||
4e53c2e0 DV |
9115 | pipe_config->pipe_bpp = bpp; |
9116 | ||
9117 | /* Clamp display bpp to EDID value */ | |
9118 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9119 | base.head) { |
1b829e05 DV |
9120 | if (!connector->new_encoder || |
9121 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9122 | continue; |
9123 | ||
050f7aeb | 9124 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9125 | } |
9126 | ||
9127 | return bpp; | |
9128 | } | |
9129 | ||
644db711 DV |
9130 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9131 | { | |
9132 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9133 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9134 | mode->crtc_clock, |
644db711 DV |
9135 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9136 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9137 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9138 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9139 | } | |
9140 | ||
c0b03411 DV |
9141 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9142 | struct intel_crtc_config *pipe_config, | |
9143 | const char *context) | |
9144 | { | |
9145 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9146 | context, pipe_name(crtc->pipe)); | |
9147 | ||
9148 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9149 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9150 | pipe_config->pipe_bpp, pipe_config->dither); | |
9151 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9152 | pipe_config->has_pch_encoder, | |
9153 | pipe_config->fdi_lanes, | |
9154 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9155 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9156 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9157 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9158 | pipe_config->has_dp_encoder, | |
9159 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9160 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9161 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9162 | DRM_DEBUG_KMS("requested mode:\n"); |
9163 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9164 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9165 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9166 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9167 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9168 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9169 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9170 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9171 | pipe_config->gmch_pfit.control, | |
9172 | pipe_config->gmch_pfit.pgm_ratios, | |
9173 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9174 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9175 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9176 | pipe_config->pch_pfit.size, |
9177 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9178 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9179 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9180 | } |
9181 | ||
accfc0c5 DV |
9182 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
9183 | { | |
9184 | int num_encoders = 0; | |
9185 | bool uncloneable_encoders = false; | |
9186 | struct intel_encoder *encoder; | |
9187 | ||
9188 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
9189 | base.head) { | |
9190 | if (&encoder->new_crtc->base != crtc) | |
9191 | continue; | |
9192 | ||
9193 | num_encoders++; | |
9194 | if (!encoder->cloneable) | |
9195 | uncloneable_encoders = true; | |
9196 | } | |
9197 | ||
9198 | return !(num_encoders > 1 && uncloneable_encoders); | |
9199 | } | |
9200 | ||
b8cecdf5 DV |
9201 | static struct intel_crtc_config * |
9202 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9203 | struct drm_framebuffer *fb, |
b8cecdf5 | 9204 | struct drm_display_mode *mode) |
ee7b9f93 | 9205 | { |
7758a113 | 9206 | struct drm_device *dev = crtc->dev; |
7758a113 | 9207 | struct intel_encoder *encoder; |
b8cecdf5 | 9208 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9209 | int plane_bpp, ret = -EINVAL; |
9210 | bool retry = true; | |
ee7b9f93 | 9211 | |
accfc0c5 DV |
9212 | if (!check_encoder_cloning(crtc)) { |
9213 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
9214 | return ERR_PTR(-EINVAL); | |
9215 | } | |
9216 | ||
b8cecdf5 DV |
9217 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9218 | if (!pipe_config) | |
7758a113 DV |
9219 | return ERR_PTR(-ENOMEM); |
9220 | ||
b8cecdf5 DV |
9221 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9222 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9223 | |
e143a21c DV |
9224 | pipe_config->cpu_transcoder = |
9225 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9226 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9227 | |
2960bc9c ID |
9228 | /* |
9229 | * Sanitize sync polarity flags based on requested ones. If neither | |
9230 | * positive or negative polarity is requested, treat this as meaning | |
9231 | * negative polarity. | |
9232 | */ | |
9233 | if (!(pipe_config->adjusted_mode.flags & | |
9234 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9235 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9236 | ||
9237 | if (!(pipe_config->adjusted_mode.flags & | |
9238 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9239 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9240 | ||
050f7aeb DV |
9241 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9242 | * plane pixel format and any sink constraints into account. Returns the | |
9243 | * source plane bpp so that dithering can be selected on mismatches | |
9244 | * after encoders and crtc also have had their say. */ | |
9245 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9246 | fb, pipe_config); | |
4e53c2e0 DV |
9247 | if (plane_bpp < 0) |
9248 | goto fail; | |
9249 | ||
e41a56be VS |
9250 | /* |
9251 | * Determine the real pipe dimensions. Note that stereo modes can | |
9252 | * increase the actual pipe size due to the frame doubling and | |
9253 | * insertion of additional space for blanks between the frame. This | |
9254 | * is stored in the crtc timings. We use the requested mode to do this | |
9255 | * computation to clearly distinguish it from the adjusted mode, which | |
9256 | * can be changed by the connectors in the below retry loop. | |
9257 | */ | |
9258 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9259 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9260 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9261 | ||
e29c22c0 | 9262 | encoder_retry: |
ef1b460d | 9263 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9264 | pipe_config->port_clock = 0; |
ef1b460d | 9265 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9266 | |
135c81b8 | 9267 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9268 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9269 | |
7758a113 DV |
9270 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9271 | * adjust it according to limitations or connector properties, and also | |
9272 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9273 | */ |
7758a113 DV |
9274 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9275 | base.head) { | |
47f1c6c9 | 9276 | |
7758a113 DV |
9277 | if (&encoder->new_crtc->base != crtc) |
9278 | continue; | |
7ae89233 | 9279 | |
efea6e8e DV |
9280 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9281 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9282 | goto fail; |
9283 | } | |
ee7b9f93 | 9284 | } |
47f1c6c9 | 9285 | |
ff9a6750 DV |
9286 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9287 | * done afterwards in case the encoder adjusts the mode. */ | |
9288 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9289 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9290 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9291 | |
a43f6e0f | 9292 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9293 | if (ret < 0) { |
7758a113 DV |
9294 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9295 | goto fail; | |
ee7b9f93 | 9296 | } |
e29c22c0 DV |
9297 | |
9298 | if (ret == RETRY) { | |
9299 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9300 | ret = -EINVAL; | |
9301 | goto fail; | |
9302 | } | |
9303 | ||
9304 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9305 | retry = false; | |
9306 | goto encoder_retry; | |
9307 | } | |
9308 | ||
4e53c2e0 DV |
9309 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9310 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9311 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9312 | ||
b8cecdf5 | 9313 | return pipe_config; |
7758a113 | 9314 | fail: |
b8cecdf5 | 9315 | kfree(pipe_config); |
e29c22c0 | 9316 | return ERR_PTR(ret); |
ee7b9f93 | 9317 | } |
47f1c6c9 | 9318 | |
e2e1ed41 DV |
9319 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9320 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9321 | static void | |
9322 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9323 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9324 | { |
9325 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9326 | struct drm_device *dev = crtc->dev; |
9327 | struct intel_encoder *encoder; | |
9328 | struct intel_connector *connector; | |
9329 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9330 | |
e2e1ed41 | 9331 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9332 | |
e2e1ed41 DV |
9333 | /* Check which crtcs have changed outputs connected to them, these need |
9334 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9335 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9336 | * bit set at most. */ | |
9337 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9338 | base.head) { | |
9339 | if (connector->base.encoder == &connector->new_encoder->base) | |
9340 | continue; | |
79e53945 | 9341 | |
e2e1ed41 DV |
9342 | if (connector->base.encoder) { |
9343 | tmp_crtc = connector->base.encoder->crtc; | |
9344 | ||
9345 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9346 | } | |
9347 | ||
9348 | if (connector->new_encoder) | |
9349 | *prepare_pipes |= | |
9350 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9351 | } |
9352 | ||
e2e1ed41 DV |
9353 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9354 | base.head) { | |
9355 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9356 | continue; | |
9357 | ||
9358 | if (encoder->base.crtc) { | |
9359 | tmp_crtc = encoder->base.crtc; | |
9360 | ||
9361 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9362 | } | |
9363 | ||
9364 | if (encoder->new_crtc) | |
9365 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9366 | } |
9367 | ||
7668851f | 9368 | /* Check for pipes that will be enabled/disabled ... */ |
e2e1ed41 DV |
9369 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9370 | base.head) { | |
7668851f | 9371 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9372 | continue; |
7e7d76c3 | 9373 | |
7668851f | 9374 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9375 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9376 | else |
9377 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9378 | } |
9379 | ||
e2e1ed41 DV |
9380 | |
9381 | /* set_mode is also used to update properties on life display pipes. */ | |
9382 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9383 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9384 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9385 | ||
b6c5164d DV |
9386 | /* |
9387 | * For simplicity do a full modeset on any pipe where the output routing | |
9388 | * changed. We could be more clever, but that would require us to be | |
9389 | * more careful with calling the relevant encoder->mode_set functions. | |
9390 | */ | |
e2e1ed41 DV |
9391 | if (*prepare_pipes) |
9392 | *modeset_pipes = *prepare_pipes; | |
9393 | ||
9394 | /* ... and mask these out. */ | |
9395 | *modeset_pipes &= ~(*disable_pipes); | |
9396 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9397 | |
9398 | /* | |
9399 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9400 | * obies this rule, but the modeset restore mode of | |
9401 | * intel_modeset_setup_hw_state does not. | |
9402 | */ | |
9403 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9404 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9405 | |
9406 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9407 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9408 | } |
79e53945 | 9409 | |
ea9d758d | 9410 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9411 | { |
ea9d758d | 9412 | struct drm_encoder *encoder; |
f6e5b160 | 9413 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9414 | |
ea9d758d DV |
9415 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9416 | if (encoder->crtc == crtc) | |
9417 | return true; | |
9418 | ||
9419 | return false; | |
9420 | } | |
9421 | ||
9422 | static void | |
9423 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9424 | { | |
9425 | struct intel_encoder *intel_encoder; | |
9426 | struct intel_crtc *intel_crtc; | |
9427 | struct drm_connector *connector; | |
9428 | ||
9429 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9430 | base.head) { | |
9431 | if (!intel_encoder->base.crtc) | |
9432 | continue; | |
9433 | ||
9434 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9435 | ||
9436 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9437 | intel_encoder->connectors_active = false; | |
9438 | } | |
9439 | ||
9440 | intel_modeset_commit_output_state(dev); | |
9441 | ||
7668851f | 9442 | /* Double check state. */ |
ea9d758d DV |
9443 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, |
9444 | base.head) { | |
7668851f | 9445 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9446 | WARN_ON(intel_crtc->new_config && |
9447 | intel_crtc->new_config != &intel_crtc->config); | |
9448 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9449 | } |
9450 | ||
9451 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9452 | if (!connector->encoder || !connector->encoder->crtc) | |
9453 | continue; | |
9454 | ||
9455 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9456 | ||
9457 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9458 | struct drm_property *dpms_property = |
9459 | dev->mode_config.dpms_property; | |
9460 | ||
ea9d758d | 9461 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9462 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9463 | dpms_property, |
9464 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9465 | |
9466 | intel_encoder = to_intel_encoder(connector->encoder); | |
9467 | intel_encoder->connectors_active = true; | |
9468 | } | |
9469 | } | |
9470 | ||
9471 | } | |
9472 | ||
3bd26263 | 9473 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9474 | { |
3bd26263 | 9475 | int diff; |
f1f644dc JB |
9476 | |
9477 | if (clock1 == clock2) | |
9478 | return true; | |
9479 | ||
9480 | if (!clock1 || !clock2) | |
9481 | return false; | |
9482 | ||
9483 | diff = abs(clock1 - clock2); | |
9484 | ||
9485 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9486 | return true; | |
9487 | ||
9488 | return false; | |
9489 | } | |
9490 | ||
25c5b266 DV |
9491 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9492 | list_for_each_entry((intel_crtc), \ | |
9493 | &(dev)->mode_config.crtc_list, \ | |
9494 | base.head) \ | |
0973f18f | 9495 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9496 | |
0e8ffe1b | 9497 | static bool |
2fa2fe9a DV |
9498 | intel_pipe_config_compare(struct drm_device *dev, |
9499 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9500 | struct intel_crtc_config *pipe_config) |
9501 | { | |
66e985c0 DV |
9502 | #define PIPE_CONF_CHECK_X(name) \ |
9503 | if (current_config->name != pipe_config->name) { \ | |
9504 | DRM_ERROR("mismatch in " #name " " \ | |
9505 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9506 | current_config->name, \ | |
9507 | pipe_config->name); \ | |
9508 | return false; \ | |
9509 | } | |
9510 | ||
08a24034 DV |
9511 | #define PIPE_CONF_CHECK_I(name) \ |
9512 | if (current_config->name != pipe_config->name) { \ | |
9513 | DRM_ERROR("mismatch in " #name " " \ | |
9514 | "(expected %i, found %i)\n", \ | |
9515 | current_config->name, \ | |
9516 | pipe_config->name); \ | |
9517 | return false; \ | |
88adfff1 DV |
9518 | } |
9519 | ||
1bd1bd80 DV |
9520 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9521 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9522 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9523 | "(expected %i, found %i)\n", \ |
9524 | current_config->name & (mask), \ | |
9525 | pipe_config->name & (mask)); \ | |
9526 | return false; \ | |
9527 | } | |
9528 | ||
5e550656 VS |
9529 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9530 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9531 | DRM_ERROR("mismatch in " #name " " \ | |
9532 | "(expected %i, found %i)\n", \ | |
9533 | current_config->name, \ | |
9534 | pipe_config->name); \ | |
9535 | return false; \ | |
9536 | } | |
9537 | ||
bb760063 DV |
9538 | #define PIPE_CONF_QUIRK(quirk) \ |
9539 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9540 | ||
eccb140b DV |
9541 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9542 | ||
08a24034 DV |
9543 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9544 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9545 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9546 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9547 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9548 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9549 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9550 | |
eb14cb74 VS |
9551 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9552 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9553 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9554 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9555 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9556 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9557 | ||
1bd1bd80 DV |
9558 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9559 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9560 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9561 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9562 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9563 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9564 | ||
9565 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9566 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9567 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9568 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9569 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9570 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9571 | ||
c93f54cf | 9572 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9573 | |
1bd1bd80 DV |
9574 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9575 | DRM_MODE_FLAG_INTERLACE); | |
9576 | ||
bb760063 DV |
9577 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9578 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9579 | DRM_MODE_FLAG_PHSYNC); | |
9580 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9581 | DRM_MODE_FLAG_NHSYNC); | |
9582 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9583 | DRM_MODE_FLAG_PVSYNC); | |
9584 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9585 | DRM_MODE_FLAG_NVSYNC); | |
9586 | } | |
045ac3b5 | 9587 | |
37327abd VS |
9588 | PIPE_CONF_CHECK_I(pipe_src_w); |
9589 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9590 | |
2fa2fe9a DV |
9591 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9592 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9593 | if (INTEL_INFO(dev)->gen < 4) | |
9594 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9595 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9596 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9597 | if (current_config->pch_pfit.enabled) { | |
9598 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9599 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9600 | } | |
2fa2fe9a | 9601 | |
e59150dc JB |
9602 | /* BDW+ don't expose a synchronous way to read the state */ |
9603 | if (IS_HASWELL(dev)) | |
9604 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 9605 | |
282740f7 VS |
9606 | PIPE_CONF_CHECK_I(double_wide); |
9607 | ||
c0d43d62 | 9608 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9609 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9610 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9611 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9612 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9613 | |
42571aef VS |
9614 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9615 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9616 | ||
a9a7e98a JB |
9617 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
9618 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 9619 | |
66e985c0 | 9620 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9621 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9622 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9623 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9624 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9625 | |
0e8ffe1b DV |
9626 | return true; |
9627 | } | |
9628 | ||
91d1b4bd DV |
9629 | static void |
9630 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9631 | { |
8af6cf88 DV |
9632 | struct intel_connector *connector; |
9633 | ||
9634 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9635 | base.head) { | |
9636 | /* This also checks the encoder/connector hw state with the | |
9637 | * ->get_hw_state callbacks. */ | |
9638 | intel_connector_check_state(connector); | |
9639 | ||
9640 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9641 | "connector's staged encoder doesn't match current encoder\n"); | |
9642 | } | |
91d1b4bd DV |
9643 | } |
9644 | ||
9645 | static void | |
9646 | check_encoder_state(struct drm_device *dev) | |
9647 | { | |
9648 | struct intel_encoder *encoder; | |
9649 | struct intel_connector *connector; | |
8af6cf88 DV |
9650 | |
9651 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9652 | base.head) { | |
9653 | bool enabled = false; | |
9654 | bool active = false; | |
9655 | enum pipe pipe, tracked_pipe; | |
9656 | ||
9657 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9658 | encoder->base.base.id, | |
9659 | drm_get_encoder_name(&encoder->base)); | |
9660 | ||
9661 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9662 | "encoder's stage crtc doesn't match current crtc\n"); | |
9663 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9664 | "encoder's active_connectors set, but no crtc\n"); | |
9665 | ||
9666 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9667 | base.head) { | |
9668 | if (connector->base.encoder != &encoder->base) | |
9669 | continue; | |
9670 | enabled = true; | |
9671 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9672 | active = true; | |
9673 | } | |
9674 | WARN(!!encoder->base.crtc != enabled, | |
9675 | "encoder's enabled state mismatch " | |
9676 | "(expected %i, found %i)\n", | |
9677 | !!encoder->base.crtc, enabled); | |
9678 | WARN(active && !encoder->base.crtc, | |
9679 | "active encoder with no crtc\n"); | |
9680 | ||
9681 | WARN(encoder->connectors_active != active, | |
9682 | "encoder's computed active state doesn't match tracked active state " | |
9683 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9684 | ||
9685 | active = encoder->get_hw_state(encoder, &pipe); | |
9686 | WARN(active != encoder->connectors_active, | |
9687 | "encoder's hw state doesn't match sw tracking " | |
9688 | "(expected %i, found %i)\n", | |
9689 | encoder->connectors_active, active); | |
9690 | ||
9691 | if (!encoder->base.crtc) | |
9692 | continue; | |
9693 | ||
9694 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9695 | WARN(active && pipe != tracked_pipe, | |
9696 | "active encoder's pipe doesn't match" | |
9697 | "(expected %i, found %i)\n", | |
9698 | tracked_pipe, pipe); | |
9699 | ||
9700 | } | |
91d1b4bd DV |
9701 | } |
9702 | ||
9703 | static void | |
9704 | check_crtc_state(struct drm_device *dev) | |
9705 | { | |
9706 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9707 | struct intel_crtc *crtc; | |
9708 | struct intel_encoder *encoder; | |
9709 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9710 | |
9711 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9712 | base.head) { | |
9713 | bool enabled = false; | |
9714 | bool active = false; | |
9715 | ||
045ac3b5 JB |
9716 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9717 | ||
8af6cf88 DV |
9718 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9719 | crtc->base.base.id); | |
9720 | ||
9721 | WARN(crtc->active && !crtc->base.enabled, | |
9722 | "active crtc, but not enabled in sw tracking\n"); | |
9723 | ||
9724 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9725 | base.head) { | |
9726 | if (encoder->base.crtc != &crtc->base) | |
9727 | continue; | |
9728 | enabled = true; | |
9729 | if (encoder->connectors_active) | |
9730 | active = true; | |
9731 | } | |
6c49f241 | 9732 | |
8af6cf88 DV |
9733 | WARN(active != crtc->active, |
9734 | "crtc's computed active state doesn't match tracked active state " | |
9735 | "(expected %i, found %i)\n", active, crtc->active); | |
9736 | WARN(enabled != crtc->base.enabled, | |
9737 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9738 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9739 | ||
0e8ffe1b DV |
9740 | active = dev_priv->display.get_pipe_config(crtc, |
9741 | &pipe_config); | |
d62cf62a DV |
9742 | |
9743 | /* hw state is inconsistent with the pipe A quirk */ | |
9744 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9745 | active = crtc->active; | |
9746 | ||
6c49f241 DV |
9747 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9748 | base.head) { | |
3eaba51c | 9749 | enum pipe pipe; |
6c49f241 DV |
9750 | if (encoder->base.crtc != &crtc->base) |
9751 | continue; | |
1d37b689 | 9752 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
9753 | encoder->get_config(encoder, &pipe_config); |
9754 | } | |
9755 | ||
0e8ffe1b DV |
9756 | WARN(crtc->active != active, |
9757 | "crtc active state doesn't match with hw state " | |
9758 | "(expected %i, found %i)\n", crtc->active, active); | |
9759 | ||
c0b03411 DV |
9760 | if (active && |
9761 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9762 | WARN(1, "pipe state doesn't match!\n"); | |
9763 | intel_dump_pipe_config(crtc, &pipe_config, | |
9764 | "[hw state]"); | |
9765 | intel_dump_pipe_config(crtc, &crtc->config, | |
9766 | "[sw state]"); | |
9767 | } | |
8af6cf88 DV |
9768 | } |
9769 | } | |
9770 | ||
91d1b4bd DV |
9771 | static void |
9772 | check_shared_dpll_state(struct drm_device *dev) | |
9773 | { | |
9774 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9775 | struct intel_crtc *crtc; | |
9776 | struct intel_dpll_hw_state dpll_hw_state; | |
9777 | int i; | |
5358901f DV |
9778 | |
9779 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9780 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9781 | int enabled_crtcs = 0, active_crtcs = 0; | |
9782 | bool active; | |
9783 | ||
9784 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9785 | ||
9786 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9787 | ||
9788 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9789 | ||
9790 | WARN(pll->active > pll->refcount, | |
9791 | "more active pll users than references: %i vs %i\n", | |
9792 | pll->active, pll->refcount); | |
9793 | WARN(pll->active && !pll->on, | |
9794 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9795 | WARN(pll->on && !pll->active, |
9796 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9797 | WARN(pll->on != active, |
9798 | "pll on state mismatch (expected %i, found %i)\n", | |
9799 | pll->on, active); | |
9800 | ||
9801 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9802 | base.head) { | |
9803 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9804 | enabled_crtcs++; | |
9805 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9806 | active_crtcs++; | |
9807 | } | |
9808 | WARN(pll->active != active_crtcs, | |
9809 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9810 | pll->active, active_crtcs); | |
9811 | WARN(pll->refcount != enabled_crtcs, | |
9812 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9813 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9814 | |
9815 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9816 | sizeof(dpll_hw_state)), | |
9817 | "pll hw state mismatch\n"); | |
5358901f | 9818 | } |
8af6cf88 DV |
9819 | } |
9820 | ||
91d1b4bd DV |
9821 | void |
9822 | intel_modeset_check_state(struct drm_device *dev) | |
9823 | { | |
9824 | check_connector_state(dev); | |
9825 | check_encoder_state(dev); | |
9826 | check_crtc_state(dev); | |
9827 | check_shared_dpll_state(dev); | |
9828 | } | |
9829 | ||
18442d08 VS |
9830 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9831 | int dotclock) | |
9832 | { | |
9833 | /* | |
9834 | * FDI already provided one idea for the dotclock. | |
9835 | * Yell if the encoder disagrees. | |
9836 | */ | |
241bfc38 | 9837 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9838 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9839 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9840 | } |
9841 | ||
f30da187 DV |
9842 | static int __intel_set_mode(struct drm_crtc *crtc, |
9843 | struct drm_display_mode *mode, | |
9844 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9845 | { |
9846 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9847 | drm_i915_private_t *dev_priv = dev->dev_private; |
4b4b9238 | 9848 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 9849 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
9850 | struct intel_crtc *intel_crtc; |
9851 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9852 | int ret = 0; |
a6778b3c | 9853 | |
4b4b9238 | 9854 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9855 | if (!saved_mode) |
9856 | return -ENOMEM; | |
a6778b3c | 9857 | |
e2e1ed41 | 9858 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9859 | &prepare_pipes, &disable_pipes); |
9860 | ||
3ac18232 | 9861 | *saved_mode = crtc->mode; |
a6778b3c | 9862 | |
25c5b266 DV |
9863 | /* Hack: Because we don't (yet) support global modeset on multiple |
9864 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9865 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9866 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9867 | * changing their mode at the same time. */ | |
25c5b266 | 9868 | if (modeset_pipes) { |
4e53c2e0 | 9869 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9870 | if (IS_ERR(pipe_config)) { |
9871 | ret = PTR_ERR(pipe_config); | |
9872 | pipe_config = NULL; | |
9873 | ||
3ac18232 | 9874 | goto out; |
25c5b266 | 9875 | } |
c0b03411 DV |
9876 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9877 | "[modeset]"); | |
50741abc | 9878 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 9879 | } |
a6778b3c | 9880 | |
30a970c6 JB |
9881 | /* |
9882 | * See if the config requires any additional preparation, e.g. | |
9883 | * to adjust global state with pipes off. We need to do this | |
9884 | * here so we can get the modeset_pipe updated config for the new | |
9885 | * mode set on this crtc. For other crtcs we need to use the | |
9886 | * adjusted_mode bits in the crtc directly. | |
9887 | */ | |
c164f833 | 9888 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 9889 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 9890 | |
c164f833 VS |
9891 | /* may have added more to prepare_pipes than we should */ |
9892 | prepare_pipes &= ~disable_pipes; | |
9893 | } | |
9894 | ||
460da916 DV |
9895 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9896 | intel_crtc_disable(&intel_crtc->base); | |
9897 | ||
ea9d758d DV |
9898 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9899 | if (intel_crtc->base.enabled) | |
9900 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9901 | } | |
a6778b3c | 9902 | |
6c4c86f5 DV |
9903 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9904 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9905 | */ |
b8cecdf5 | 9906 | if (modeset_pipes) { |
25c5b266 | 9907 | crtc->mode = *mode; |
b8cecdf5 DV |
9908 | /* mode_set/enable/disable functions rely on a correct pipe |
9909 | * config. */ | |
9910 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 9911 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
9912 | |
9913 | /* | |
9914 | * Calculate and store various constants which | |
9915 | * are later needed by vblank and swap-completion | |
9916 | * timestamping. They are derived from true hwmode. | |
9917 | */ | |
9918 | drm_calc_timestamping_constants(crtc, | |
9919 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 9920 | } |
7758a113 | 9921 | |
ea9d758d DV |
9922 | /* Only after disabling all output pipelines that will be changed can we |
9923 | * update the the output configuration. */ | |
9924 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9925 | |
47fab737 DV |
9926 | if (dev_priv->display.modeset_global_resources) |
9927 | dev_priv->display.modeset_global_resources(dev); | |
9928 | ||
a6778b3c DV |
9929 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9930 | * on the DPLL. | |
f6e5b160 | 9931 | */ |
25c5b266 | 9932 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9933 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9934 | x, y, fb); |
9935 | if (ret) | |
9936 | goto done; | |
a6778b3c DV |
9937 | } |
9938 | ||
9939 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9940 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9941 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9942 | |
a6778b3c DV |
9943 | /* FIXME: add subpixel order */ |
9944 | done: | |
4b4b9238 | 9945 | if (ret && crtc->enabled) |
3ac18232 | 9946 | crtc->mode = *saved_mode; |
a6778b3c | 9947 | |
3ac18232 | 9948 | out: |
b8cecdf5 | 9949 | kfree(pipe_config); |
3ac18232 | 9950 | kfree(saved_mode); |
a6778b3c | 9951 | return ret; |
f6e5b160 CW |
9952 | } |
9953 | ||
e7457a9a DL |
9954 | static int intel_set_mode(struct drm_crtc *crtc, |
9955 | struct drm_display_mode *mode, | |
9956 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9957 | { |
9958 | int ret; | |
9959 | ||
9960 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9961 | ||
9962 | if (ret == 0) | |
9963 | intel_modeset_check_state(crtc->dev); | |
9964 | ||
9965 | return ret; | |
9966 | } | |
9967 | ||
c0c36b94 CW |
9968 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9969 | { | |
9970 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9971 | } | |
9972 | ||
25c5b266 DV |
9973 | #undef for_each_intel_crtc_masked |
9974 | ||
d9e55608 DV |
9975 | static void intel_set_config_free(struct intel_set_config *config) |
9976 | { | |
9977 | if (!config) | |
9978 | return; | |
9979 | ||
1aa4b628 DV |
9980 | kfree(config->save_connector_encoders); |
9981 | kfree(config->save_encoder_crtcs); | |
7668851f | 9982 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
9983 | kfree(config); |
9984 | } | |
9985 | ||
85f9eb71 DV |
9986 | static int intel_set_config_save_state(struct drm_device *dev, |
9987 | struct intel_set_config *config) | |
9988 | { | |
7668851f | 9989 | struct drm_crtc *crtc; |
85f9eb71 DV |
9990 | struct drm_encoder *encoder; |
9991 | struct drm_connector *connector; | |
9992 | int count; | |
9993 | ||
7668851f VS |
9994 | config->save_crtc_enabled = |
9995 | kcalloc(dev->mode_config.num_crtc, | |
9996 | sizeof(bool), GFP_KERNEL); | |
9997 | if (!config->save_crtc_enabled) | |
9998 | return -ENOMEM; | |
9999 | ||
1aa4b628 DV |
10000 | config->save_encoder_crtcs = |
10001 | kcalloc(dev->mode_config.num_encoder, | |
10002 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10003 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10004 | return -ENOMEM; |
10005 | ||
1aa4b628 DV |
10006 | config->save_connector_encoders = |
10007 | kcalloc(dev->mode_config.num_connector, | |
10008 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10009 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10010 | return -ENOMEM; |
10011 | ||
10012 | /* Copy data. Note that driver private data is not affected. | |
10013 | * Should anything bad happen only the expected state is | |
10014 | * restored, not the drivers personal bookkeeping. | |
10015 | */ | |
7668851f VS |
10016 | count = 0; |
10017 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
10018 | config->save_crtc_enabled[count++] = crtc->enabled; | |
10019 | } | |
10020 | ||
85f9eb71 DV |
10021 | count = 0; |
10022 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10023 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10024 | } |
10025 | ||
10026 | count = 0; | |
10027 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10028 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10029 | } |
10030 | ||
10031 | return 0; | |
10032 | } | |
10033 | ||
10034 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10035 | struct intel_set_config *config) | |
10036 | { | |
7668851f | 10037 | struct intel_crtc *crtc; |
9a935856 DV |
10038 | struct intel_encoder *encoder; |
10039 | struct intel_connector *connector; | |
85f9eb71 DV |
10040 | int count; |
10041 | ||
7668851f VS |
10042 | count = 0; |
10043 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10044 | crtc->new_enabled = config->save_crtc_enabled[count++]; | |
7bd0a8e7 VS |
10045 | |
10046 | if (crtc->new_enabled) | |
10047 | crtc->new_config = &crtc->config; | |
10048 | else | |
10049 | crtc->new_config = NULL; | |
7668851f VS |
10050 | } |
10051 | ||
85f9eb71 | 10052 | count = 0; |
9a935856 DV |
10053 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10054 | encoder->new_crtc = | |
10055 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10056 | } |
10057 | ||
10058 | count = 0; | |
9a935856 DV |
10059 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10060 | connector->new_encoder = | |
10061 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10062 | } |
10063 | } | |
10064 | ||
e3de42b6 | 10065 | static bool |
2e57f47d | 10066 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10067 | { |
10068 | int i; | |
10069 | ||
2e57f47d CW |
10070 | if (set->num_connectors == 0) |
10071 | return false; | |
10072 | ||
10073 | if (WARN_ON(set->connectors == NULL)) | |
10074 | return false; | |
10075 | ||
10076 | for (i = 0; i < set->num_connectors; i++) | |
10077 | if (set->connectors[i]->encoder && | |
10078 | set->connectors[i]->encoder->crtc == set->crtc && | |
10079 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10080 | return true; |
10081 | ||
10082 | return false; | |
10083 | } | |
10084 | ||
5e2b584e DV |
10085 | static void |
10086 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10087 | struct intel_set_config *config) | |
10088 | { | |
10089 | ||
10090 | /* We should be able to check here if the fb has the same properties | |
10091 | * and then just flip_or_move it */ | |
2e57f47d CW |
10092 | if (is_crtc_connector_off(set)) { |
10093 | config->mode_changed = true; | |
e3de42b6 | 10094 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
10095 | /* If we have no fb then treat it as a full mode set */ |
10096 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
10097 | struct intel_crtc *intel_crtc = |
10098 | to_intel_crtc(set->crtc); | |
10099 | ||
d330a953 | 10100 | if (intel_crtc->active && i915.fastboot) { |
319d9827 JB |
10101 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10102 | config->fb_changed = true; | |
10103 | } else { | |
10104 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10105 | config->mode_changed = true; | |
10106 | } | |
5e2b584e DV |
10107 | } else if (set->fb == NULL) { |
10108 | config->mode_changed = true; | |
72f4901e DV |
10109 | } else if (set->fb->pixel_format != |
10110 | set->crtc->fb->pixel_format) { | |
5e2b584e | 10111 | config->mode_changed = true; |
e3de42b6 | 10112 | } else { |
5e2b584e | 10113 | config->fb_changed = true; |
e3de42b6 | 10114 | } |
5e2b584e DV |
10115 | } |
10116 | ||
835c5873 | 10117 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10118 | config->fb_changed = true; |
10119 | ||
10120 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10121 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10122 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10123 | drm_mode_debug_printmodeline(set->mode); | |
10124 | config->mode_changed = true; | |
10125 | } | |
a1d95703 CW |
10126 | |
10127 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10128 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10129 | } |
10130 | ||
2e431051 | 10131 | static int |
9a935856 DV |
10132 | intel_modeset_stage_output_state(struct drm_device *dev, |
10133 | struct drm_mode_set *set, | |
10134 | struct intel_set_config *config) | |
50f56119 | 10135 | { |
9a935856 DV |
10136 | struct intel_connector *connector; |
10137 | struct intel_encoder *encoder; | |
7668851f | 10138 | struct intel_crtc *crtc; |
f3f08572 | 10139 | int ro; |
50f56119 | 10140 | |
9abdda74 | 10141 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10142 | * of connectors. For paranoia, double-check this. */ |
10143 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10144 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
10145 | ||
9a935856 DV |
10146 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10147 | base.head) { | |
10148 | /* Otherwise traverse passed in connector list and get encoders | |
10149 | * for them. */ | |
50f56119 | 10150 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
10151 | if (set->connectors[ro] == &connector->base) { |
10152 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
10153 | break; |
10154 | } | |
10155 | } | |
10156 | ||
9a935856 DV |
10157 | /* If we disable the crtc, disable all its connectors. Also, if |
10158 | * the connector is on the changing crtc but not on the new | |
10159 | * connector list, disable it. */ | |
10160 | if ((!set->fb || ro == set->num_connectors) && | |
10161 | connector->base.encoder && | |
10162 | connector->base.encoder->crtc == set->crtc) { | |
10163 | connector->new_encoder = NULL; | |
10164 | ||
10165 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
10166 | connector->base.base.id, | |
10167 | drm_get_connector_name(&connector->base)); | |
10168 | } | |
10169 | ||
10170 | ||
10171 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 10172 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 10173 | config->mode_changed = true; |
50f56119 DV |
10174 | } |
10175 | } | |
9a935856 | 10176 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 10177 | |
9a935856 | 10178 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
10179 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10180 | base.head) { | |
7668851f VS |
10181 | struct drm_crtc *new_crtc; |
10182 | ||
9a935856 | 10183 | if (!connector->new_encoder) |
50f56119 DV |
10184 | continue; |
10185 | ||
9a935856 | 10186 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10187 | |
10188 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10189 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10190 | new_crtc = set->crtc; |
10191 | } | |
10192 | ||
10193 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10194 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10195 | new_crtc)) { | |
5e2b584e | 10196 | return -EINVAL; |
50f56119 | 10197 | } |
9a935856 DV |
10198 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10199 | ||
10200 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10201 | connector->base.base.id, | |
10202 | drm_get_connector_name(&connector->base), | |
10203 | new_crtc->base.id); | |
10204 | } | |
10205 | ||
10206 | /* Check for any encoders that needs to be disabled. */ | |
10207 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10208 | base.head) { | |
5a65f358 | 10209 | int num_connectors = 0; |
9a935856 DV |
10210 | list_for_each_entry(connector, |
10211 | &dev->mode_config.connector_list, | |
10212 | base.head) { | |
10213 | if (connector->new_encoder == encoder) { | |
10214 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10215 | num_connectors++; |
9a935856 DV |
10216 | } |
10217 | } | |
5a65f358 PZ |
10218 | |
10219 | if (num_connectors == 0) | |
10220 | encoder->new_crtc = NULL; | |
10221 | else if (num_connectors > 1) | |
10222 | return -EINVAL; | |
10223 | ||
9a935856 DV |
10224 | /* Only now check for crtc changes so we don't miss encoders |
10225 | * that will be disabled. */ | |
10226 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10227 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10228 | config->mode_changed = true; |
50f56119 DV |
10229 | } |
10230 | } | |
9a935856 | 10231 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10232 | |
7668851f VS |
10233 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10234 | base.head) { | |
10235 | crtc->new_enabled = false; | |
10236 | ||
10237 | list_for_each_entry(encoder, | |
10238 | &dev->mode_config.encoder_list, | |
10239 | base.head) { | |
10240 | if (encoder->new_crtc == crtc) { | |
10241 | crtc->new_enabled = true; | |
10242 | break; | |
10243 | } | |
10244 | } | |
10245 | ||
10246 | if (crtc->new_enabled != crtc->base.enabled) { | |
10247 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10248 | crtc->new_enabled ? "en" : "dis"); | |
10249 | config->mode_changed = true; | |
10250 | } | |
7bd0a8e7 VS |
10251 | |
10252 | if (crtc->new_enabled) | |
10253 | crtc->new_config = &crtc->config; | |
10254 | else | |
10255 | crtc->new_config = NULL; | |
7668851f VS |
10256 | } |
10257 | ||
2e431051 DV |
10258 | return 0; |
10259 | } | |
10260 | ||
7d00a1f5 VS |
10261 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10262 | { | |
10263 | struct drm_device *dev = crtc->base.dev; | |
10264 | struct intel_encoder *encoder; | |
10265 | struct intel_connector *connector; | |
10266 | ||
10267 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10268 | pipe_name(crtc->pipe)); | |
10269 | ||
10270 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10271 | if (connector->new_encoder && | |
10272 | connector->new_encoder->new_crtc == crtc) | |
10273 | connector->new_encoder = NULL; | |
10274 | } | |
10275 | ||
10276 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10277 | if (encoder->new_crtc == crtc) | |
10278 | encoder->new_crtc = NULL; | |
10279 | } | |
10280 | ||
10281 | crtc->new_enabled = false; | |
7bd0a8e7 | 10282 | crtc->new_config = NULL; |
7d00a1f5 VS |
10283 | } |
10284 | ||
2e431051 DV |
10285 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10286 | { | |
10287 | struct drm_device *dev; | |
2e431051 DV |
10288 | struct drm_mode_set save_set; |
10289 | struct intel_set_config *config; | |
10290 | int ret; | |
2e431051 | 10291 | |
8d3e375e DV |
10292 | BUG_ON(!set); |
10293 | BUG_ON(!set->crtc); | |
10294 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10295 | |
7e53f3a4 DV |
10296 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10297 | BUG_ON(!set->mode && set->fb); | |
10298 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10299 | |
2e431051 DV |
10300 | if (set->fb) { |
10301 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10302 | set->crtc->base.id, set->fb->base.id, | |
10303 | (int)set->num_connectors, set->x, set->y); | |
10304 | } else { | |
10305 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10306 | } |
10307 | ||
10308 | dev = set->crtc->dev; | |
10309 | ||
10310 | ret = -ENOMEM; | |
10311 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10312 | if (!config) | |
10313 | goto out_config; | |
10314 | ||
10315 | ret = intel_set_config_save_state(dev, config); | |
10316 | if (ret) | |
10317 | goto out_config; | |
10318 | ||
10319 | save_set.crtc = set->crtc; | |
10320 | save_set.mode = &set->crtc->mode; | |
10321 | save_set.x = set->crtc->x; | |
10322 | save_set.y = set->crtc->y; | |
10323 | save_set.fb = set->crtc->fb; | |
10324 | ||
10325 | /* Compute whether we need a full modeset, only an fb base update or no | |
10326 | * change at all. In the future we might also check whether only the | |
10327 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10328 | * such cases. */ | |
10329 | intel_set_config_compute_mode_changes(set, config); | |
10330 | ||
9a935856 | 10331 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10332 | if (ret) |
10333 | goto fail; | |
10334 | ||
5e2b584e | 10335 | if (config->mode_changed) { |
c0c36b94 CW |
10336 | ret = intel_set_mode(set->crtc, set->mode, |
10337 | set->x, set->y, set->fb); | |
5e2b584e | 10338 | } else if (config->fb_changed) { |
4878cae2 VS |
10339 | intel_crtc_wait_for_pending_flips(set->crtc); |
10340 | ||
4f660f49 | 10341 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10342 | set->x, set->y, set->fb); |
7ca51a3a JB |
10343 | /* |
10344 | * In the fastboot case this may be our only check of the | |
10345 | * state after boot. It would be better to only do it on | |
10346 | * the first update, but we don't have a nice way of doing that | |
10347 | * (and really, set_config isn't used much for high freq page | |
10348 | * flipping, so increasing its cost here shouldn't be a big | |
10349 | * deal). | |
10350 | */ | |
d330a953 | 10351 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10352 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10353 | } |
10354 | ||
2d05eae1 | 10355 | if (ret) { |
bf67dfeb DV |
10356 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10357 | set->crtc->base.id, ret); | |
50f56119 | 10358 | fail: |
2d05eae1 | 10359 | intel_set_config_restore_state(dev, config); |
50f56119 | 10360 | |
7d00a1f5 VS |
10361 | /* |
10362 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10363 | * force the pipe off to avoid oopsing in the modeset code | |
10364 | * due to fb==NULL. This should only happen during boot since | |
10365 | * we don't yet reconstruct the FB from the hardware state. | |
10366 | */ | |
10367 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10368 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10369 | ||
2d05eae1 CW |
10370 | /* Try to restore the config */ |
10371 | if (config->mode_changed && | |
10372 | intel_set_mode(save_set.crtc, save_set.mode, | |
10373 | save_set.x, save_set.y, save_set.fb)) | |
10374 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10375 | } | |
50f56119 | 10376 | |
d9e55608 DV |
10377 | out_config: |
10378 | intel_set_config_free(config); | |
50f56119 DV |
10379 | return ret; |
10380 | } | |
f6e5b160 CW |
10381 | |
10382 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10383 | .cursor_set = intel_crtc_cursor_set, |
10384 | .cursor_move = intel_crtc_cursor_move, | |
10385 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10386 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10387 | .destroy = intel_crtc_destroy, |
10388 | .page_flip = intel_crtc_page_flip, | |
10389 | }; | |
10390 | ||
79f689aa PZ |
10391 | static void intel_cpu_pll_init(struct drm_device *dev) |
10392 | { | |
affa9354 | 10393 | if (HAS_DDI(dev)) |
79f689aa PZ |
10394 | intel_ddi_pll_init(dev); |
10395 | } | |
10396 | ||
5358901f DV |
10397 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10398 | struct intel_shared_dpll *pll, | |
10399 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10400 | { |
5358901f | 10401 | uint32_t val; |
ee7b9f93 | 10402 | |
5358901f | 10403 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10404 | hw_state->dpll = val; |
10405 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10406 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10407 | |
10408 | return val & DPLL_VCO_ENABLE; | |
10409 | } | |
10410 | ||
15bdd4cf DV |
10411 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10412 | struct intel_shared_dpll *pll) | |
10413 | { | |
10414 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10415 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10416 | } | |
10417 | ||
e7b903d2 DV |
10418 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10419 | struct intel_shared_dpll *pll) | |
10420 | { | |
e7b903d2 | 10421 | /* PCH refclock must be enabled first */ |
89eff4be | 10422 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10423 | |
15bdd4cf DV |
10424 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10425 | ||
10426 | /* Wait for the clocks to stabilize. */ | |
10427 | POSTING_READ(PCH_DPLL(pll->id)); | |
10428 | udelay(150); | |
10429 | ||
10430 | /* The pixel multiplier can only be updated once the | |
10431 | * DPLL is enabled and the clocks are stable. | |
10432 | * | |
10433 | * So write it again. | |
10434 | */ | |
10435 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10436 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10437 | udelay(200); |
10438 | } | |
10439 | ||
10440 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10441 | struct intel_shared_dpll *pll) | |
10442 | { | |
10443 | struct drm_device *dev = dev_priv->dev; | |
10444 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10445 | |
10446 | /* Make sure no transcoder isn't still depending on us. */ | |
10447 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10448 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10449 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10450 | } |
10451 | ||
15bdd4cf DV |
10452 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10453 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10454 | udelay(200); |
10455 | } | |
10456 | ||
46edb027 DV |
10457 | static char *ibx_pch_dpll_names[] = { |
10458 | "PCH DPLL A", | |
10459 | "PCH DPLL B", | |
10460 | }; | |
10461 | ||
7c74ade1 | 10462 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10463 | { |
e7b903d2 | 10464 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10465 | int i; |
10466 | ||
7c74ade1 | 10467 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10468 | |
e72f9fbf | 10469 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10470 | dev_priv->shared_dplls[i].id = i; |
10471 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10472 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10473 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10474 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10475 | dev_priv->shared_dplls[i].get_hw_state = |
10476 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10477 | } |
10478 | } | |
10479 | ||
7c74ade1 DV |
10480 | static void intel_shared_dpll_init(struct drm_device *dev) |
10481 | { | |
e7b903d2 | 10482 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10483 | |
10484 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10485 | ibx_pch_dpll_init(dev); | |
10486 | else | |
10487 | dev_priv->num_shared_dpll = 0; | |
10488 | ||
10489 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
10490 | } |
10491 | ||
b358d0a6 | 10492 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10493 | { |
22fd0fab | 10494 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10495 | struct intel_crtc *intel_crtc; |
10496 | int i; | |
10497 | ||
955382f3 | 10498 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10499 | if (intel_crtc == NULL) |
10500 | return; | |
10501 | ||
10502 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10503 | ||
10504 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10505 | for (i = 0; i < 256; i++) { |
10506 | intel_crtc->lut_r[i] = i; | |
10507 | intel_crtc->lut_g[i] = i; | |
10508 | intel_crtc->lut_b[i] = i; | |
10509 | } | |
10510 | ||
1f1c2e24 VS |
10511 | /* |
10512 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10513 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10514 | */ | |
80824003 JB |
10515 | intel_crtc->pipe = pipe; |
10516 | intel_crtc->plane = pipe; | |
3a77c4c4 | 10517 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10518 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10519 | intel_crtc->plane = !pipe; |
80824003 JB |
10520 | } |
10521 | ||
22fd0fab JB |
10522 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10523 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10524 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10525 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10526 | ||
79e53945 | 10527 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10528 | } |
10529 | ||
752aa88a JB |
10530 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10531 | { | |
10532 | struct drm_encoder *encoder = connector->base.encoder; | |
10533 | ||
10534 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10535 | ||
10536 | if (!encoder) | |
10537 | return INVALID_PIPE; | |
10538 | ||
10539 | return to_intel_crtc(encoder->crtc)->pipe; | |
10540 | } | |
10541 | ||
08d7b3d1 | 10542 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10543 | struct drm_file *file) |
08d7b3d1 | 10544 | { |
08d7b3d1 | 10545 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10546 | struct drm_mode_object *drmmode_obj; |
10547 | struct intel_crtc *crtc; | |
08d7b3d1 | 10548 | |
1cff8f6b DV |
10549 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10550 | return -ENODEV; | |
08d7b3d1 | 10551 | |
c05422d5 DV |
10552 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10553 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10554 | |
c05422d5 | 10555 | if (!drmmode_obj) { |
08d7b3d1 | 10556 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10557 | return -ENOENT; |
08d7b3d1 CW |
10558 | } |
10559 | ||
c05422d5 DV |
10560 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10561 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10562 | |
c05422d5 | 10563 | return 0; |
08d7b3d1 CW |
10564 | } |
10565 | ||
66a9278e | 10566 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10567 | { |
66a9278e DV |
10568 | struct drm_device *dev = encoder->base.dev; |
10569 | struct intel_encoder *source_encoder; | |
79e53945 | 10570 | int index_mask = 0; |
79e53945 JB |
10571 | int entry = 0; |
10572 | ||
66a9278e DV |
10573 | list_for_each_entry(source_encoder, |
10574 | &dev->mode_config.encoder_list, base.head) { | |
10575 | ||
10576 | if (encoder == source_encoder) | |
79e53945 | 10577 | index_mask |= (1 << entry); |
66a9278e DV |
10578 | |
10579 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10580 | if (encoder->cloneable && source_encoder->cloneable) | |
10581 | index_mask |= (1 << entry); | |
10582 | ||
79e53945 JB |
10583 | entry++; |
10584 | } | |
4ef69c7a | 10585 | |
79e53945 JB |
10586 | return index_mask; |
10587 | } | |
10588 | ||
4d302442 CW |
10589 | static bool has_edp_a(struct drm_device *dev) |
10590 | { | |
10591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10592 | ||
10593 | if (!IS_MOBILE(dev)) | |
10594 | return false; | |
10595 | ||
10596 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10597 | return false; | |
10598 | ||
e3589908 | 10599 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
10600 | return false; |
10601 | ||
10602 | return true; | |
10603 | } | |
10604 | ||
ba0fbca4 DL |
10605 | const char *intel_output_name(int output) |
10606 | { | |
10607 | static const char *names[] = { | |
10608 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
10609 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
10610 | [INTEL_OUTPUT_DVO] = "DVO", | |
10611 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
10612 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
10613 | [INTEL_OUTPUT_TVOUT] = "TV", | |
10614 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
10615 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
10616 | [INTEL_OUTPUT_EDP] = "eDP", | |
10617 | [INTEL_OUTPUT_DSI] = "DSI", | |
10618 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
10619 | }; | |
10620 | ||
10621 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
10622 | return "Invalid"; | |
10623 | ||
10624 | return names[output]; | |
10625 | } | |
10626 | ||
79e53945 JB |
10627 | static void intel_setup_outputs(struct drm_device *dev) |
10628 | { | |
725e30ad | 10629 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10630 | struct intel_encoder *encoder; |
cb0953d7 | 10631 | bool dpd_is_edp = false; |
79e53945 | 10632 | |
c9093354 | 10633 | intel_lvds_init(dev); |
79e53945 | 10634 | |
c40c0f5b | 10635 | if (!IS_ULT(dev)) |
79935fca | 10636 | intel_crt_init(dev); |
cb0953d7 | 10637 | |
affa9354 | 10638 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10639 | int found; |
10640 | ||
10641 | /* Haswell uses DDI functions to detect digital outputs */ | |
10642 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10643 | /* DDI A only supports eDP */ | |
10644 | if (found) | |
10645 | intel_ddi_init(dev, PORT_A); | |
10646 | ||
10647 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10648 | * register */ | |
10649 | found = I915_READ(SFUSE_STRAP); | |
10650 | ||
10651 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10652 | intel_ddi_init(dev, PORT_B); | |
10653 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10654 | intel_ddi_init(dev, PORT_C); | |
10655 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10656 | intel_ddi_init(dev, PORT_D); | |
10657 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10658 | int found; |
5d8a7752 | 10659 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
10660 | |
10661 | if (has_edp_a(dev)) | |
10662 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10663 | |
dc0fa718 | 10664 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10665 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10666 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10667 | if (!found) |
e2debe91 | 10668 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10669 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10670 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10671 | } |
10672 | ||
dc0fa718 | 10673 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10674 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10675 | |
dc0fa718 | 10676 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10677 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10678 | |
5eb08b69 | 10679 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10680 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10681 | |
270b3042 | 10682 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10683 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10684 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10685 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10686 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10687 | PORT_B); | |
10688 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10689 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10690 | } | |
10691 | ||
6f6005a5 JB |
10692 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10693 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10694 | PORT_C); | |
10695 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 10696 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 10697 | } |
19c03924 | 10698 | |
3cfca973 | 10699 | intel_dsi_init(dev); |
103a196f | 10700 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10701 | bool found = false; |
7d57382e | 10702 | |
e2debe91 | 10703 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10704 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10705 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10706 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10707 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10708 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10709 | } |
27185ae1 | 10710 | |
e7281eab | 10711 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10712 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10713 | } |
13520b05 KH |
10714 | |
10715 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10716 | |
e2debe91 | 10717 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10718 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10719 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10720 | } |
27185ae1 | 10721 | |
e2debe91 | 10722 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10723 | |
b01f2c3a JB |
10724 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10725 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10726 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10727 | } |
e7281eab | 10728 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10729 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10730 | } |
27185ae1 | 10731 | |
b01f2c3a | 10732 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10733 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10734 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10735 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10736 | intel_dvo_init(dev); |
10737 | ||
103a196f | 10738 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10739 | intel_tv_init(dev); |
10740 | ||
4ef69c7a CW |
10741 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10742 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10743 | encoder->base.possible_clones = | |
66a9278e | 10744 | intel_encoder_clones(encoder); |
79e53945 | 10745 | } |
47356eb6 | 10746 | |
dde86e2d | 10747 | intel_init_pch_refclk(dev); |
270b3042 DV |
10748 | |
10749 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10750 | } |
10751 | ||
10752 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
10753 | { | |
10754 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10755 | |
ef2d633e DV |
10756 | drm_framebuffer_cleanup(fb); |
10757 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
10758 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
10759 | kfree(intel_fb); |
10760 | } | |
10761 | ||
10762 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10763 | struct drm_file *file, |
79e53945 JB |
10764 | unsigned int *handle) |
10765 | { | |
10766 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10767 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10768 | |
05394f39 | 10769 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10770 | } |
10771 | ||
10772 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10773 | .destroy = intel_user_framebuffer_destroy, | |
10774 | .create_handle = intel_user_framebuffer_create_handle, | |
10775 | }; | |
10776 | ||
b5ea642a DV |
10777 | static int intel_framebuffer_init(struct drm_device *dev, |
10778 | struct intel_framebuffer *intel_fb, | |
10779 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10780 | struct drm_i915_gem_object *obj) | |
79e53945 | 10781 | { |
a57ce0b2 | 10782 | int aligned_height; |
a35cdaa0 | 10783 | int pitch_limit; |
79e53945 JB |
10784 | int ret; |
10785 | ||
dd4916c5 DV |
10786 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10787 | ||
c16ed4be CW |
10788 | if (obj->tiling_mode == I915_TILING_Y) { |
10789 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10790 | return -EINVAL; |
c16ed4be | 10791 | } |
57cd6508 | 10792 | |
c16ed4be CW |
10793 | if (mode_cmd->pitches[0] & 63) { |
10794 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10795 | mode_cmd->pitches[0]); | |
57cd6508 | 10796 | return -EINVAL; |
c16ed4be | 10797 | } |
57cd6508 | 10798 | |
a35cdaa0 CW |
10799 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10800 | pitch_limit = 32*1024; | |
10801 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10802 | if (obj->tiling_mode) | |
10803 | pitch_limit = 16*1024; | |
10804 | else | |
10805 | pitch_limit = 32*1024; | |
10806 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10807 | if (obj->tiling_mode) | |
10808 | pitch_limit = 8*1024; | |
10809 | else | |
10810 | pitch_limit = 16*1024; | |
10811 | } else | |
10812 | /* XXX DSPC is limited to 4k tiled */ | |
10813 | pitch_limit = 8*1024; | |
10814 | ||
10815 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10816 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10817 | obj->tiling_mode ? "tiled" : "linear", | |
10818 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10819 | return -EINVAL; |
c16ed4be | 10820 | } |
5d7bd705 VS |
10821 | |
10822 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10823 | mode_cmd->pitches[0] != obj->stride) { |
10824 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10825 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10826 | return -EINVAL; |
c16ed4be | 10827 | } |
5d7bd705 | 10828 | |
57779d06 | 10829 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10830 | switch (mode_cmd->pixel_format) { |
57779d06 | 10831 | case DRM_FORMAT_C8: |
04b3924d VS |
10832 | case DRM_FORMAT_RGB565: |
10833 | case DRM_FORMAT_XRGB8888: | |
10834 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10835 | break; |
10836 | case DRM_FORMAT_XRGB1555: | |
10837 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10838 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10839 | DRM_DEBUG("unsupported pixel format: %s\n", |
10840 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10841 | return -EINVAL; |
c16ed4be | 10842 | } |
57779d06 VS |
10843 | break; |
10844 | case DRM_FORMAT_XBGR8888: | |
10845 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10846 | case DRM_FORMAT_XRGB2101010: |
10847 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10848 | case DRM_FORMAT_XBGR2101010: |
10849 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10850 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10851 | DRM_DEBUG("unsupported pixel format: %s\n", |
10852 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10853 | return -EINVAL; |
c16ed4be | 10854 | } |
b5626747 | 10855 | break; |
04b3924d VS |
10856 | case DRM_FORMAT_YUYV: |
10857 | case DRM_FORMAT_UYVY: | |
10858 | case DRM_FORMAT_YVYU: | |
10859 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10860 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10861 | DRM_DEBUG("unsupported pixel format: %s\n", |
10862 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10863 | return -EINVAL; |
c16ed4be | 10864 | } |
57cd6508 CW |
10865 | break; |
10866 | default: | |
4ee62c76 VS |
10867 | DRM_DEBUG("unsupported pixel format: %s\n", |
10868 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10869 | return -EINVAL; |
10870 | } | |
10871 | ||
90f9a336 VS |
10872 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10873 | if (mode_cmd->offsets[0] != 0) | |
10874 | return -EINVAL; | |
10875 | ||
a57ce0b2 JB |
10876 | aligned_height = intel_align_height(dev, mode_cmd->height, |
10877 | obj->tiling_mode); | |
53155c0a DV |
10878 | /* FIXME drm helper for size checks (especially planar formats)? */ |
10879 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10880 | return -EINVAL; | |
10881 | ||
c7d73f6a DV |
10882 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10883 | intel_fb->obj = obj; | |
80075d49 | 10884 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10885 | |
79e53945 JB |
10886 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10887 | if (ret) { | |
10888 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10889 | return ret; | |
10890 | } | |
10891 | ||
79e53945 JB |
10892 | return 0; |
10893 | } | |
10894 | ||
79e53945 JB |
10895 | static struct drm_framebuffer * |
10896 | intel_user_framebuffer_create(struct drm_device *dev, | |
10897 | struct drm_file *filp, | |
308e5bcb | 10898 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10899 | { |
05394f39 | 10900 | struct drm_i915_gem_object *obj; |
79e53945 | 10901 | |
308e5bcb JB |
10902 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10903 | mode_cmd->handles[0])); | |
c8725226 | 10904 | if (&obj->base == NULL) |
cce13ff7 | 10905 | return ERR_PTR(-ENOENT); |
79e53945 | 10906 | |
d2dff872 | 10907 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10908 | } |
10909 | ||
4520f53a | 10910 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10911 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10912 | { |
10913 | } | |
10914 | #endif | |
10915 | ||
79e53945 | 10916 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10917 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10918 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10919 | }; |
10920 | ||
e70236a8 JB |
10921 | /* Set up chip specific display functions */ |
10922 | static void intel_init_display(struct drm_device *dev) | |
10923 | { | |
10924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10925 | ||
ee9300bb DV |
10926 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10927 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10928 | else if (IS_VALLEYVIEW(dev)) | |
10929 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10930 | else if (IS_PINEVIEW(dev)) | |
10931 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10932 | else | |
10933 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10934 | ||
affa9354 | 10935 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10936 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 10937 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 10938 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10939 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10940 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10941 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10942 | dev_priv->display.update_plane = ironlake_update_plane; |
10943 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10944 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 10945 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 10946 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10947 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10948 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10949 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10950 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10951 | } else if (IS_VALLEYVIEW(dev)) { |
10952 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 10953 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
10954 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
10955 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10956 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10957 | dev_priv->display.off = i9xx_crtc_off; | |
10958 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10959 | } else { |
0e8ffe1b | 10960 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 10961 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 10962 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10963 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10964 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10965 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10966 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10967 | } |
e70236a8 | 10968 | |
e70236a8 | 10969 | /* Returns the core display clock speed */ |
25eb05fc JB |
10970 | if (IS_VALLEYVIEW(dev)) |
10971 | dev_priv->display.get_display_clock_speed = | |
10972 | valleyview_get_display_clock_speed; | |
10973 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10974 | dev_priv->display.get_display_clock_speed = |
10975 | i945_get_display_clock_speed; | |
10976 | else if (IS_I915G(dev)) | |
10977 | dev_priv->display.get_display_clock_speed = | |
10978 | i915_get_display_clock_speed; | |
257a7ffc | 10979 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10980 | dev_priv->display.get_display_clock_speed = |
10981 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10982 | else if (IS_PINEVIEW(dev)) |
10983 | dev_priv->display.get_display_clock_speed = | |
10984 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10985 | else if (IS_I915GM(dev)) |
10986 | dev_priv->display.get_display_clock_speed = | |
10987 | i915gm_get_display_clock_speed; | |
10988 | else if (IS_I865G(dev)) | |
10989 | dev_priv->display.get_display_clock_speed = | |
10990 | i865_get_display_clock_speed; | |
f0f8a9ce | 10991 | else if (IS_I85X(dev)) |
e70236a8 JB |
10992 | dev_priv->display.get_display_clock_speed = |
10993 | i855_get_display_clock_speed; | |
10994 | else /* 852, 830 */ | |
10995 | dev_priv->display.get_display_clock_speed = | |
10996 | i830_get_display_clock_speed; | |
10997 | ||
7f8a8569 | 10998 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10999 | if (IS_GEN5(dev)) { |
674cf967 | 11000 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 11001 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 11002 | } else if (IS_GEN6(dev)) { |
674cf967 | 11003 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 11004 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
11005 | } else if (IS_IVYBRIDGE(dev)) { |
11006 | /* FIXME: detect B0+ stepping and use auto training */ | |
11007 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 11008 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
11009 | dev_priv->display.modeset_global_resources = |
11010 | ivb_modeset_global_resources; | |
4e0bbc31 | 11011 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 11012 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 11013 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
11014 | dev_priv->display.modeset_global_resources = |
11015 | haswell_modeset_global_resources; | |
a0e63c22 | 11016 | } |
6067aaea | 11017 | } else if (IS_G4X(dev)) { |
e0dac65e | 11018 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
11019 | } else if (IS_VALLEYVIEW(dev)) { |
11020 | dev_priv->display.modeset_global_resources = | |
11021 | valleyview_modeset_global_resources; | |
9ca2fe73 | 11022 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 11023 | } |
8c9f3aaf JB |
11024 | |
11025 | /* Default just returns -ENODEV to indicate unsupported */ | |
11026 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
11027 | ||
11028 | switch (INTEL_INFO(dev)->gen) { | |
11029 | case 2: | |
11030 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
11031 | break; | |
11032 | ||
11033 | case 3: | |
11034 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
11035 | break; | |
11036 | ||
11037 | case 4: | |
11038 | case 5: | |
11039 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
11040 | break; | |
11041 | ||
11042 | case 6: | |
11043 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
11044 | break; | |
7c9017e5 | 11045 | case 7: |
4e0bbc31 | 11046 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
11047 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11048 | break; | |
8c9f3aaf | 11049 | } |
7bd688cd JN |
11050 | |
11051 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
11052 | } |
11053 | ||
b690e96c JB |
11054 | /* |
11055 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
11056 | * resume, or other times. This quirk makes sure that's the case for | |
11057 | * affected systems. | |
11058 | */ | |
0206e353 | 11059 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
11060 | { |
11061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11062 | ||
11063 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 11064 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
11065 | } |
11066 | ||
435793df KP |
11067 | /* |
11068 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
11069 | */ | |
11070 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
11071 | { | |
11072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11073 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 11074 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
11075 | } |
11076 | ||
4dca20ef | 11077 | /* |
5a15ab5b CE |
11078 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11079 | * brightness value | |
4dca20ef CE |
11080 | */ |
11081 | static void quirk_invert_brightness(struct drm_device *dev) | |
11082 | { | |
11083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11084 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 11085 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
11086 | } |
11087 | ||
b690e96c JB |
11088 | struct intel_quirk { |
11089 | int device; | |
11090 | int subsystem_vendor; | |
11091 | int subsystem_device; | |
11092 | void (*hook)(struct drm_device *dev); | |
11093 | }; | |
11094 | ||
5f85f176 EE |
11095 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11096 | struct intel_dmi_quirk { | |
11097 | void (*hook)(struct drm_device *dev); | |
11098 | const struct dmi_system_id (*dmi_id_list)[]; | |
11099 | }; | |
11100 | ||
11101 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
11102 | { | |
11103 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
11104 | return 1; | |
11105 | } | |
11106 | ||
11107 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
11108 | { | |
11109 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
11110 | { | |
11111 | .callback = intel_dmi_reverse_brightness, | |
11112 | .ident = "NCR Corporation", | |
11113 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
11114 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
11115 | }, | |
11116 | }, | |
11117 | { } /* terminating entry */ | |
11118 | }, | |
11119 | .hook = quirk_invert_brightness, | |
11120 | }, | |
11121 | }; | |
11122 | ||
c43b5634 | 11123 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 11124 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 11125 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 11126 | |
b690e96c JB |
11127 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11128 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
11129 | ||
b690e96c JB |
11130 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11131 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
11132 | ||
a4945f95 | 11133 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 11134 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
11135 | |
11136 | /* Lenovo U160 cannot use SSC on LVDS */ | |
11137 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
11138 | |
11139 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
11140 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 11141 | |
be505f64 AH |
11142 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11143 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
11144 | ||
11145 | /* Acer/eMachines G725 */ | |
11146 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
11147 | ||
11148 | /* Acer/eMachines e725 */ | |
11149 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
11150 | ||
11151 | /* Acer/Packard Bell NCL20 */ | |
11152 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
11153 | ||
11154 | /* Acer Aspire 4736Z */ | |
11155 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
11156 | |
11157 | /* Acer Aspire 5336 */ | |
11158 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
11159 | }; |
11160 | ||
11161 | static void intel_init_quirks(struct drm_device *dev) | |
11162 | { | |
11163 | struct pci_dev *d = dev->pdev; | |
11164 | int i; | |
11165 | ||
11166 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
11167 | struct intel_quirk *q = &intel_quirks[i]; | |
11168 | ||
11169 | if (d->device == q->device && | |
11170 | (d->subsystem_vendor == q->subsystem_vendor || | |
11171 | q->subsystem_vendor == PCI_ANY_ID) && | |
11172 | (d->subsystem_device == q->subsystem_device || | |
11173 | q->subsystem_device == PCI_ANY_ID)) | |
11174 | q->hook(dev); | |
11175 | } | |
5f85f176 EE |
11176 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
11177 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
11178 | intel_dmi_quirks[i].hook(dev); | |
11179 | } | |
b690e96c JB |
11180 | } |
11181 | ||
9cce37f4 JB |
11182 | /* Disable the VGA plane that we never use */ |
11183 | static void i915_disable_vga(struct drm_device *dev) | |
11184 | { | |
11185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11186 | u8 sr1; | |
766aa1c4 | 11187 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 11188 | |
2b37c616 | 11189 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 11190 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 11191 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
11192 | sr1 = inb(VGA_SR_DATA); |
11193 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
11194 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
11195 | udelay(300); | |
11196 | ||
11197 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
11198 | POSTING_READ(vga_reg); | |
11199 | } | |
11200 | ||
f817586c DV |
11201 | void intel_modeset_init_hw(struct drm_device *dev) |
11202 | { | |
a8f78b58 ED |
11203 | intel_prepare_ddi(dev); |
11204 | ||
f817586c DV |
11205 | intel_init_clock_gating(dev); |
11206 | ||
5382f5f3 | 11207 | intel_reset_dpio(dev); |
40e9cf64 | 11208 | |
79f5b2c7 | 11209 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 11210 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 11211 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
11212 | } |
11213 | ||
7d708ee4 ID |
11214 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11215 | { | |
11216 | intel_suspend_hw(dev); | |
11217 | } | |
11218 | ||
79e53945 JB |
11219 | void intel_modeset_init(struct drm_device *dev) |
11220 | { | |
652c393a | 11221 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 11222 | int sprite, ret; |
8cc87b75 | 11223 | enum pipe pipe; |
46f297fb | 11224 | struct intel_crtc *crtc; |
79e53945 JB |
11225 | |
11226 | drm_mode_config_init(dev); | |
11227 | ||
11228 | dev->mode_config.min_width = 0; | |
11229 | dev->mode_config.min_height = 0; | |
11230 | ||
019d96cb DA |
11231 | dev->mode_config.preferred_depth = 24; |
11232 | dev->mode_config.prefer_shadow = 1; | |
11233 | ||
e6ecefaa | 11234 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 11235 | |
b690e96c JB |
11236 | intel_init_quirks(dev); |
11237 | ||
1fa61106 ED |
11238 | intel_init_pm(dev); |
11239 | ||
e3c74757 BW |
11240 | if (INTEL_INFO(dev)->num_pipes == 0) |
11241 | return; | |
11242 | ||
e70236a8 JB |
11243 | intel_init_display(dev); |
11244 | ||
a6c45cf0 CW |
11245 | if (IS_GEN2(dev)) { |
11246 | dev->mode_config.max_width = 2048; | |
11247 | dev->mode_config.max_height = 2048; | |
11248 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
11249 | dev->mode_config.max_width = 4096; |
11250 | dev->mode_config.max_height = 4096; | |
79e53945 | 11251 | } else { |
a6c45cf0 CW |
11252 | dev->mode_config.max_width = 8192; |
11253 | dev->mode_config.max_height = 8192; | |
79e53945 | 11254 | } |
5d4545ae | 11255 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 11256 | |
28c97730 | 11257 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
11258 | INTEL_INFO(dev)->num_pipes, |
11259 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 11260 | |
8cc87b75 DL |
11261 | for_each_pipe(pipe) { |
11262 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
11263 | for_each_sprite(pipe, sprite) { |
11264 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 11265 | if (ret) |
06da8da2 | 11266 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 11267 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 11268 | } |
79e53945 JB |
11269 | } |
11270 | ||
f42bb70d | 11271 | intel_init_dpio(dev); |
5382f5f3 | 11272 | intel_reset_dpio(dev); |
f42bb70d | 11273 | |
79f689aa | 11274 | intel_cpu_pll_init(dev); |
e72f9fbf | 11275 | intel_shared_dpll_init(dev); |
ee7b9f93 | 11276 | |
9cce37f4 JB |
11277 | /* Just disable it once at startup */ |
11278 | i915_disable_vga(dev); | |
79e53945 | 11279 | intel_setup_outputs(dev); |
11be49eb CW |
11280 | |
11281 | /* Just in case the BIOS is doing something questionable. */ | |
11282 | intel_disable_fbc(dev); | |
fa9fa083 | 11283 | |
8b687df4 | 11284 | mutex_lock(&dev->mode_config.mutex); |
fa9fa083 | 11285 | intel_modeset_setup_hw_state(dev, false); |
8b687df4 | 11286 | mutex_unlock(&dev->mode_config.mutex); |
46f297fb JB |
11287 | |
11288 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11289 | base.head) { | |
11290 | if (!crtc->active) | |
11291 | continue; | |
11292 | ||
11293 | #if IS_ENABLED(CONFIG_FB) | |
11294 | /* | |
11295 | * We don't have a good way of freeing the buffer w/o the FB | |
11296 | * layer owning it... | |
11297 | * Note that reserving the BIOS fb up front prevents us | |
11298 | * from stuffing other stolen allocations like the ring | |
11299 | * on top. This prevents some ugliness at boot time, and | |
11300 | * can even allow for smooth boot transitions if the BIOS | |
11301 | * fb is large enough for the active pipe configuration. | |
11302 | */ | |
11303 | if (dev_priv->display.get_plane_config) { | |
11304 | dev_priv->display.get_plane_config(crtc, | |
11305 | &crtc->plane_config); | |
11306 | /* | |
11307 | * If the fb is shared between multiple heads, we'll | |
11308 | * just get the first one. | |
11309 | */ | |
11310 | intel_alloc_plane_obj(crtc, &crtc->plane_config); | |
11311 | } | |
11312 | #endif | |
11313 | } | |
2c7111db CW |
11314 | } |
11315 | ||
24929352 DV |
11316 | static void |
11317 | intel_connector_break_all_links(struct intel_connector *connector) | |
11318 | { | |
11319 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11320 | connector->base.encoder = NULL; | |
11321 | connector->encoder->connectors_active = false; | |
11322 | connector->encoder->base.crtc = NULL; | |
11323 | } | |
11324 | ||
7fad798e DV |
11325 | static void intel_enable_pipe_a(struct drm_device *dev) |
11326 | { | |
11327 | struct intel_connector *connector; | |
11328 | struct drm_connector *crt = NULL; | |
11329 | struct intel_load_detect_pipe load_detect_temp; | |
11330 | ||
11331 | /* We can't just switch on the pipe A, we need to set things up with a | |
11332 | * proper mode and output configuration. As a gross hack, enable pipe A | |
11333 | * by enabling the load detect pipe once. */ | |
11334 | list_for_each_entry(connector, | |
11335 | &dev->mode_config.connector_list, | |
11336 | base.head) { | |
11337 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
11338 | crt = &connector->base; | |
11339 | break; | |
11340 | } | |
11341 | } | |
11342 | ||
11343 | if (!crt) | |
11344 | return; | |
11345 | ||
11346 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
11347 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
11348 | ||
652c393a | 11349 | |
7fad798e DV |
11350 | } |
11351 | ||
fa555837 DV |
11352 | static bool |
11353 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
11354 | { | |
7eb552ae BW |
11355 | struct drm_device *dev = crtc->base.dev; |
11356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
11357 | u32 reg, val; |
11358 | ||
7eb552ae | 11359 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
11360 | return true; |
11361 | ||
11362 | reg = DSPCNTR(!crtc->plane); | |
11363 | val = I915_READ(reg); | |
11364 | ||
11365 | if ((val & DISPLAY_PLANE_ENABLE) && | |
11366 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
11367 | return false; | |
11368 | ||
11369 | return true; | |
11370 | } | |
11371 | ||
24929352 DV |
11372 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
11373 | { | |
11374 | struct drm_device *dev = crtc->base.dev; | |
11375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 11376 | u32 reg; |
24929352 | 11377 | |
24929352 | 11378 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 11379 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
11380 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
11381 | ||
11382 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
11383 | * disable the crtc (and hence change the state) if it is wrong. Note |
11384 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
11385 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
11386 | struct intel_connector *connector; |
11387 | bool plane; | |
11388 | ||
24929352 DV |
11389 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
11390 | crtc->base.base.id); | |
11391 | ||
11392 | /* Pipe has the wrong plane attached and the plane is active. | |
11393 | * Temporarily change the plane mapping and disable everything | |
11394 | * ... */ | |
11395 | plane = crtc->plane; | |
11396 | crtc->plane = !plane; | |
11397 | dev_priv->display.crtc_disable(&crtc->base); | |
11398 | crtc->plane = plane; | |
11399 | ||
11400 | /* ... and break all links. */ | |
11401 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11402 | base.head) { | |
11403 | if (connector->encoder->base.crtc != &crtc->base) | |
11404 | continue; | |
11405 | ||
11406 | intel_connector_break_all_links(connector); | |
11407 | } | |
11408 | ||
11409 | WARN_ON(crtc->active); | |
11410 | crtc->base.enabled = false; | |
11411 | } | |
24929352 | 11412 | |
7fad798e DV |
11413 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
11414 | crtc->pipe == PIPE_A && !crtc->active) { | |
11415 | /* BIOS forgot to enable pipe A, this mostly happens after | |
11416 | * resume. Force-enable the pipe to fix this, the update_dpms | |
11417 | * call below we restore the pipe to the right state, but leave | |
11418 | * the required bits on. */ | |
11419 | intel_enable_pipe_a(dev); | |
11420 | } | |
11421 | ||
24929352 DV |
11422 | /* Adjust the state of the output pipe according to whether we |
11423 | * have active connectors/encoders. */ | |
11424 | intel_crtc_update_dpms(&crtc->base); | |
11425 | ||
11426 | if (crtc->active != crtc->base.enabled) { | |
11427 | struct intel_encoder *encoder; | |
11428 | ||
11429 | /* This can happen either due to bugs in the get_hw_state | |
11430 | * functions or because the pipe is force-enabled due to the | |
11431 | * pipe A quirk. */ | |
11432 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11433 | crtc->base.base.id, | |
11434 | crtc->base.enabled ? "enabled" : "disabled", | |
11435 | crtc->active ? "enabled" : "disabled"); | |
11436 | ||
11437 | crtc->base.enabled = crtc->active; | |
11438 | ||
11439 | /* Because we only establish the connector -> encoder -> | |
11440 | * crtc links if something is active, this means the | |
11441 | * crtc is now deactivated. Break the links. connector | |
11442 | * -> encoder links are only establish when things are | |
11443 | * actually up, hence no need to break them. */ | |
11444 | WARN_ON(crtc->active); | |
11445 | ||
11446 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11447 | WARN_ON(encoder->connectors_active); | |
11448 | encoder->base.crtc = NULL; | |
11449 | } | |
11450 | } | |
11451 | } | |
11452 | ||
11453 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11454 | { | |
11455 | struct intel_connector *connector; | |
11456 | struct drm_device *dev = encoder->base.dev; | |
11457 | ||
11458 | /* We need to check both for a crtc link (meaning that the | |
11459 | * encoder is active and trying to read from a pipe) and the | |
11460 | * pipe itself being active. */ | |
11461 | bool has_active_crtc = encoder->base.crtc && | |
11462 | to_intel_crtc(encoder->base.crtc)->active; | |
11463 | ||
11464 | if (encoder->connectors_active && !has_active_crtc) { | |
11465 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11466 | encoder->base.base.id, | |
11467 | drm_get_encoder_name(&encoder->base)); | |
11468 | ||
11469 | /* Connector is active, but has no active pipe. This is | |
11470 | * fallout from our resume register restoring. Disable | |
11471 | * the encoder manually again. */ | |
11472 | if (encoder->base.crtc) { | |
11473 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11474 | encoder->base.base.id, | |
11475 | drm_get_encoder_name(&encoder->base)); | |
11476 | encoder->disable(encoder); | |
11477 | } | |
11478 | ||
11479 | /* Inconsistent output/port/pipe state happens presumably due to | |
11480 | * a bug in one of the get_hw_state functions. Or someplace else | |
11481 | * in our code, like the register restore mess on resume. Clamp | |
11482 | * things to off as a safer default. */ | |
11483 | list_for_each_entry(connector, | |
11484 | &dev->mode_config.connector_list, | |
11485 | base.head) { | |
11486 | if (connector->encoder != encoder) | |
11487 | continue; | |
11488 | ||
11489 | intel_connector_break_all_links(connector); | |
11490 | } | |
11491 | } | |
11492 | /* Enabled encoders without active connectors will be fixed in | |
11493 | * the crtc fixup. */ | |
11494 | } | |
11495 | ||
04098753 | 11496 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
11497 | { |
11498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11499 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11500 | |
04098753 ID |
11501 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
11502 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
11503 | i915_disable_vga(dev); | |
11504 | } | |
11505 | } | |
11506 | ||
11507 | void i915_redisable_vga(struct drm_device *dev) | |
11508 | { | |
11509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11510 | ||
8dc8a27c PZ |
11511 | /* This function can be called both from intel_modeset_setup_hw_state or |
11512 | * at a very early point in our resume sequence, where the power well | |
11513 | * structures are not yet restored. Since this function is at a very | |
11514 | * paranoid "someone might have enabled VGA while we were not looking" | |
11515 | * level, just check if the power well is enabled instead of trying to | |
11516 | * follow the "don't touch the power well if we don't need it" policy | |
11517 | * the rest of the driver uses. */ | |
04098753 | 11518 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
11519 | return; |
11520 | ||
04098753 | 11521 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
11522 | } |
11523 | ||
30e984df | 11524 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11525 | { |
11526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11527 | enum pipe pipe; | |
24929352 DV |
11528 | struct intel_crtc *crtc; |
11529 | struct intel_encoder *encoder; | |
11530 | struct intel_connector *connector; | |
5358901f | 11531 | int i; |
24929352 | 11532 | |
0e8ffe1b DV |
11533 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11534 | base.head) { | |
88adfff1 | 11535 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11536 | |
0e8ffe1b DV |
11537 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11538 | &crtc->config); | |
24929352 DV |
11539 | |
11540 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11541 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11542 | |
11543 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11544 | crtc->base.base.id, | |
11545 | crtc->active ? "enabled" : "disabled"); | |
11546 | } | |
11547 | ||
5358901f | 11548 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11549 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11550 | intel_ddi_setup_hw_pll_state(dev); |
11551 | ||
5358901f DV |
11552 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11553 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11554 | ||
11555 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11556 | pll->active = 0; | |
11557 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11558 | base.head) { | |
11559 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11560 | pll->active++; | |
11561 | } | |
11562 | pll->refcount = pll->active; | |
11563 | ||
35c95375 DV |
11564 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11565 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11566 | } |
11567 | ||
24929352 DV |
11568 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11569 | base.head) { | |
11570 | pipe = 0; | |
11571 | ||
11572 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11573 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11574 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11575 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11576 | } else { |
11577 | encoder->base.crtc = NULL; | |
11578 | } | |
11579 | ||
11580 | encoder->connectors_active = false; | |
6f2bcceb | 11581 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11582 | encoder->base.base.id, |
11583 | drm_get_encoder_name(&encoder->base), | |
11584 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11585 | pipe_name(pipe)); |
24929352 DV |
11586 | } |
11587 | ||
11588 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11589 | base.head) { | |
11590 | if (connector->get_hw_state(connector)) { | |
11591 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11592 | connector->encoder->connectors_active = true; | |
11593 | connector->base.encoder = &connector->encoder->base; | |
11594 | } else { | |
11595 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11596 | connector->base.encoder = NULL; | |
11597 | } | |
11598 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11599 | connector->base.base.id, | |
11600 | drm_get_connector_name(&connector->base), | |
11601 | connector->base.encoder ? "enabled" : "disabled"); | |
11602 | } | |
30e984df DV |
11603 | } |
11604 | ||
11605 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11606 | * and i915 state tracking structures. */ | |
11607 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11608 | bool force_restore) | |
11609 | { | |
11610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11611 | enum pipe pipe; | |
30e984df DV |
11612 | struct intel_crtc *crtc; |
11613 | struct intel_encoder *encoder; | |
35c95375 | 11614 | int i; |
30e984df DV |
11615 | |
11616 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11617 | |
babea61d JB |
11618 | /* |
11619 | * Now that we have the config, copy it to each CRTC struct | |
11620 | * Note that this could go away if we move to using crtc_config | |
11621 | * checking everywhere. | |
11622 | */ | |
11623 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11624 | base.head) { | |
d330a953 | 11625 | if (crtc->active && i915.fastboot) { |
f6a83288 | 11626 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
11627 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
11628 | crtc->base.base.id); | |
11629 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11630 | } | |
11631 | } | |
11632 | ||
24929352 DV |
11633 | /* HW state is read out, now we need to sanitize this mess. */ |
11634 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11635 | base.head) { | |
11636 | intel_sanitize_encoder(encoder); | |
11637 | } | |
11638 | ||
11639 | for_each_pipe(pipe) { | |
11640 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11641 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11642 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11643 | } |
9a935856 | 11644 | |
35c95375 DV |
11645 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11646 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11647 | ||
11648 | if (!pll->on || pll->active) | |
11649 | continue; | |
11650 | ||
11651 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11652 | ||
11653 | pll->disable(dev_priv, pll); | |
11654 | pll->on = false; | |
11655 | } | |
11656 | ||
96f90c54 | 11657 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
11658 | ilk_wm_get_hw_state(dev); |
11659 | ||
45e2b5f6 | 11660 | if (force_restore) { |
7d0bc1ea VS |
11661 | i915_redisable_vga(dev); |
11662 | ||
f30da187 DV |
11663 | /* |
11664 | * We need to use raw interfaces for restoring state to avoid | |
11665 | * checking (bogus) intermediate states. | |
11666 | */ | |
45e2b5f6 | 11667 | for_each_pipe(pipe) { |
b5644d05 JB |
11668 | struct drm_crtc *crtc = |
11669 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11670 | |
11671 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11672 | crtc->fb); | |
45e2b5f6 DV |
11673 | } |
11674 | } else { | |
11675 | intel_modeset_update_staged_output_state(dev); | |
11676 | } | |
8af6cf88 DV |
11677 | |
11678 | intel_modeset_check_state(dev); | |
2c7111db CW |
11679 | } |
11680 | ||
11681 | void intel_modeset_gem_init(struct drm_device *dev) | |
11682 | { | |
1833b134 | 11683 | intel_modeset_init_hw(dev); |
02e792fb DV |
11684 | |
11685 | intel_setup_overlay(dev); | |
79e53945 JB |
11686 | } |
11687 | ||
4932e2c3 ID |
11688 | void intel_connector_unregister(struct intel_connector *intel_connector) |
11689 | { | |
11690 | struct drm_connector *connector = &intel_connector->base; | |
11691 | ||
11692 | intel_panel_destroy_backlight(connector); | |
11693 | drm_sysfs_connector_remove(connector); | |
11694 | } | |
11695 | ||
79e53945 JB |
11696 | void intel_modeset_cleanup(struct drm_device *dev) |
11697 | { | |
652c393a JB |
11698 | struct drm_i915_private *dev_priv = dev->dev_private; |
11699 | struct drm_crtc *crtc; | |
d9255d57 | 11700 | struct drm_connector *connector; |
652c393a | 11701 | |
fd0c0642 DV |
11702 | /* |
11703 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11704 | * Too much stuff here (turning of rps, connectors, ...) would | |
11705 | * experience fancy races otherwise. | |
11706 | */ | |
11707 | drm_irq_uninstall(dev); | |
11708 | cancel_work_sync(&dev_priv->hotplug_work); | |
11709 | /* | |
11710 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11711 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11712 | */ | |
f87ea761 | 11713 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11714 | |
652c393a JB |
11715 | mutex_lock(&dev->struct_mutex); |
11716 | ||
723bfd70 JB |
11717 | intel_unregister_dsm_handler(); |
11718 | ||
652c393a JB |
11719 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11720 | /* Skip inactive CRTCs */ | |
11721 | if (!crtc->fb) | |
11722 | continue; | |
11723 | ||
3dec0095 | 11724 | intel_increase_pllclock(crtc); |
652c393a JB |
11725 | } |
11726 | ||
973d04f9 | 11727 | intel_disable_fbc(dev); |
e70236a8 | 11728 | |
8090c6b9 | 11729 | intel_disable_gt_powersave(dev); |
0cdab21f | 11730 | |
930ebb46 DV |
11731 | ironlake_teardown_rc6(dev); |
11732 | ||
69341a5e KH |
11733 | mutex_unlock(&dev->struct_mutex); |
11734 | ||
1630fe75 CW |
11735 | /* flush any delayed tasks or pending work */ |
11736 | flush_scheduled_work(); | |
11737 | ||
db31af1d JN |
11738 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11739 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
11740 | struct intel_connector *intel_connector; |
11741 | ||
11742 | intel_connector = to_intel_connector(connector); | |
11743 | intel_connector->unregister(intel_connector); | |
db31af1d | 11744 | } |
d9255d57 | 11745 | |
79e53945 | 11746 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11747 | |
11748 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11749 | } |
11750 | ||
f1c79df3 ZW |
11751 | /* |
11752 | * Return which encoder is currently attached for connector. | |
11753 | */ | |
df0e9248 | 11754 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11755 | { |
df0e9248 CW |
11756 | return &intel_attached_encoder(connector)->base; |
11757 | } | |
f1c79df3 | 11758 | |
df0e9248 CW |
11759 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11760 | struct intel_encoder *encoder) | |
11761 | { | |
11762 | connector->encoder = encoder; | |
11763 | drm_mode_connector_attach_encoder(&connector->base, | |
11764 | &encoder->base); | |
79e53945 | 11765 | } |
28d52043 DA |
11766 | |
11767 | /* | |
11768 | * set vga decode state - true == enable VGA decode | |
11769 | */ | |
11770 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11771 | { | |
11772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 11773 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
11774 | u16 gmch_ctrl; |
11775 | ||
75fa041d CW |
11776 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
11777 | DRM_ERROR("failed to read control word\n"); | |
11778 | return -EIO; | |
11779 | } | |
11780 | ||
c0cc8a55 CW |
11781 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
11782 | return 0; | |
11783 | ||
28d52043 DA |
11784 | if (state) |
11785 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11786 | else | |
11787 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
11788 | |
11789 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
11790 | DRM_ERROR("failed to write control word\n"); | |
11791 | return -EIO; | |
11792 | } | |
11793 | ||
28d52043 DA |
11794 | return 0; |
11795 | } | |
c4a1d9e4 | 11796 | |
c4a1d9e4 | 11797 | struct intel_display_error_state { |
ff57f1b0 PZ |
11798 | |
11799 | u32 power_well_driver; | |
11800 | ||
63b66e5b CW |
11801 | int num_transcoders; |
11802 | ||
c4a1d9e4 CW |
11803 | struct intel_cursor_error_state { |
11804 | u32 control; | |
11805 | u32 position; | |
11806 | u32 base; | |
11807 | u32 size; | |
52331309 | 11808 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11809 | |
11810 | struct intel_pipe_error_state { | |
ddf9c536 | 11811 | bool power_domain_on; |
c4a1d9e4 | 11812 | u32 source; |
52331309 | 11813 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11814 | |
11815 | struct intel_plane_error_state { | |
11816 | u32 control; | |
11817 | u32 stride; | |
11818 | u32 size; | |
11819 | u32 pos; | |
11820 | u32 addr; | |
11821 | u32 surface; | |
11822 | u32 tile_offset; | |
52331309 | 11823 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11824 | |
11825 | struct intel_transcoder_error_state { | |
ddf9c536 | 11826 | bool power_domain_on; |
63b66e5b CW |
11827 | enum transcoder cpu_transcoder; |
11828 | ||
11829 | u32 conf; | |
11830 | ||
11831 | u32 htotal; | |
11832 | u32 hblank; | |
11833 | u32 hsync; | |
11834 | u32 vtotal; | |
11835 | u32 vblank; | |
11836 | u32 vsync; | |
11837 | } transcoder[4]; | |
c4a1d9e4 CW |
11838 | }; |
11839 | ||
11840 | struct intel_display_error_state * | |
11841 | intel_display_capture_error_state(struct drm_device *dev) | |
11842 | { | |
0206e353 | 11843 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11844 | struct intel_display_error_state *error; |
63b66e5b CW |
11845 | int transcoders[] = { |
11846 | TRANSCODER_A, | |
11847 | TRANSCODER_B, | |
11848 | TRANSCODER_C, | |
11849 | TRANSCODER_EDP, | |
11850 | }; | |
c4a1d9e4 CW |
11851 | int i; |
11852 | ||
63b66e5b CW |
11853 | if (INTEL_INFO(dev)->num_pipes == 0) |
11854 | return NULL; | |
11855 | ||
9d1cb914 | 11856 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11857 | if (error == NULL) |
11858 | return NULL; | |
11859 | ||
190be112 | 11860 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11861 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11862 | ||
52331309 | 11863 | for_each_pipe(i) { |
ddf9c536 | 11864 | error->pipe[i].power_domain_on = |
da7e29bd ID |
11865 | intel_display_power_enabled_sw(dev_priv, |
11866 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 11867 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
11868 | continue; |
11869 | ||
a18c4c3d PZ |
11870 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11871 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11872 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11873 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11874 | } else { | |
11875 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11876 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11877 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11878 | } | |
c4a1d9e4 CW |
11879 | |
11880 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11881 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11882 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11883 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11884 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11885 | } | |
ca291363 PZ |
11886 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11887 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11888 | if (INTEL_INFO(dev)->gen >= 4) { |
11889 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11890 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11891 | } | |
11892 | ||
c4a1d9e4 | 11893 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11894 | } |
11895 | ||
11896 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11897 | if (HAS_DDI(dev_priv->dev)) | |
11898 | error->num_transcoders++; /* Account for eDP. */ | |
11899 | ||
11900 | for (i = 0; i < error->num_transcoders; i++) { | |
11901 | enum transcoder cpu_transcoder = transcoders[i]; | |
11902 | ||
ddf9c536 | 11903 | error->transcoder[i].power_domain_on = |
da7e29bd | 11904 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 11905 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 11906 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
11907 | continue; |
11908 | ||
63b66e5b CW |
11909 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11910 | ||
11911 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11912 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11913 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11914 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11915 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11916 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11917 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11918 | } |
11919 | ||
11920 | return error; | |
11921 | } | |
11922 | ||
edc3d884 MK |
11923 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11924 | ||
c4a1d9e4 | 11925 | void |
edc3d884 | 11926 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11927 | struct drm_device *dev, |
11928 | struct intel_display_error_state *error) | |
11929 | { | |
11930 | int i; | |
11931 | ||
63b66e5b CW |
11932 | if (!error) |
11933 | return; | |
11934 | ||
edc3d884 | 11935 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11936 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11937 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11938 | error->power_well_driver); |
52331309 | 11939 | for_each_pipe(i) { |
edc3d884 | 11940 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
11941 | err_printf(m, " Power: %s\n", |
11942 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 11943 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11944 | |
11945 | err_printf(m, "Plane [%d]:\n", i); | |
11946 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11947 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11948 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11949 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11950 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11951 | } |
4b71a570 | 11952 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11953 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11954 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11955 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11956 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11957 | } |
11958 | ||
edc3d884 MK |
11959 | err_printf(m, "Cursor [%d]:\n", i); |
11960 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11961 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11962 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11963 | } |
63b66e5b CW |
11964 | |
11965 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11966 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 11967 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
11968 | err_printf(m, " Power: %s\n", |
11969 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
11970 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11971 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11972 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11973 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11974 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11975 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11976 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11977 | } | |
c4a1d9e4 | 11978 | } |