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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
cc36513c DV |
79 | static void intel_increase_pllclock(struct drm_device *dev, |
80 | enum pipe pipe); | |
6b383a7f | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 82 | |
f1f644dc JB |
83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
84 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
86 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 87 | |
e7457a9a DL |
88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
89 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
95 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
96 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab DV |
97 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
98 | struct intel_link_m_n *m_n); | |
99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 103 | |
79e53945 | 104 | typedef struct { |
0206e353 | 105 | int min, max; |
79e53945 JB |
106 | } intel_range_t; |
107 | ||
108 | typedef struct { | |
0206e353 AJ |
109 | int dot_limit; |
110 | int p2_slow, p2_fast; | |
79e53945 JB |
111 | } intel_p2_t; |
112 | ||
d4906093 ML |
113 | typedef struct intel_limit intel_limit_t; |
114 | struct intel_limit { | |
0206e353 AJ |
115 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
116 | intel_p2_t p2; | |
d4906093 | 117 | }; |
79e53945 | 118 | |
d2acd215 DV |
119 | int |
120 | intel_pch_rawclk(struct drm_device *dev) | |
121 | { | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | ||
124 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
125 | ||
126 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
127 | } | |
128 | ||
021357ac CW |
129 | static inline u32 /* units of 100MHz */ |
130 | intel_fdi_link_freq(struct drm_device *dev) | |
131 | { | |
8b99e68c CW |
132 | if (IS_GEN5(dev)) { |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
135 | } else | |
136 | return 27; | |
021357ac CW |
137 | } |
138 | ||
5d536e28 | 139 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 140 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 141 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 142 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
143 | .m = { .min = 96, .max = 140 }, |
144 | .m1 = { .min = 18, .max = 26 }, | |
145 | .m2 = { .min = 6, .max = 16 }, | |
146 | .p = { .min = 4, .max = 128 }, | |
147 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
148 | .p2 = { .dot_limit = 165000, |
149 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
150 | }; |
151 | ||
5d536e28 DV |
152 | static const intel_limit_t intel_limits_i8xx_dvo = { |
153 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 154 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 155 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
156 | .m = { .min = 96, .max = 140 }, |
157 | .m1 = { .min = 18, .max = 26 }, | |
158 | .m2 = { .min = 6, .max = 16 }, | |
159 | .p = { .min = 4, .max = 128 }, | |
160 | .p1 = { .min = 2, .max = 33 }, | |
161 | .p2 = { .dot_limit = 165000, | |
162 | .p2_slow = 4, .p2_fast = 4 }, | |
163 | }; | |
164 | ||
e4b36699 | 165 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 166 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 167 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 168 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
169 | .m = { .min = 96, .max = 140 }, |
170 | .m1 = { .min = 18, .max = 26 }, | |
171 | .m2 = { .min = 6, .max = 16 }, | |
172 | .p = { .min = 4, .max = 128 }, | |
173 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
174 | .p2 = { .dot_limit = 165000, |
175 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 176 | }; |
273e27ca | 177 | |
e4b36699 | 178 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
179 | .dot = { .min = 20000, .max = 400000 }, |
180 | .vco = { .min = 1400000, .max = 2800000 }, | |
181 | .n = { .min = 1, .max = 6 }, | |
182 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
183 | .m1 = { .min = 8, .max = 18 }, |
184 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
185 | .p = { .min = 5, .max = 80 }, |
186 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
187 | .p2 = { .dot_limit = 200000, |
188 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
189 | }; |
190 | ||
191 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
192 | .dot = { .min = 20000, .max = 400000 }, |
193 | .vco = { .min = 1400000, .max = 2800000 }, | |
194 | .n = { .min = 1, .max = 6 }, | |
195 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
196 | .m1 = { .min = 8, .max = 18 }, |
197 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
198 | .p = { .min = 7, .max = 98 }, |
199 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
200 | .p2 = { .dot_limit = 112000, |
201 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
202 | }; |
203 | ||
273e27ca | 204 | |
e4b36699 | 205 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
206 | .dot = { .min = 25000, .max = 270000 }, |
207 | .vco = { .min = 1750000, .max = 3500000}, | |
208 | .n = { .min = 1, .max = 4 }, | |
209 | .m = { .min = 104, .max = 138 }, | |
210 | .m1 = { .min = 17, .max = 23 }, | |
211 | .m2 = { .min = 5, .max = 11 }, | |
212 | .p = { .min = 10, .max = 30 }, | |
213 | .p1 = { .min = 1, .max = 3}, | |
214 | .p2 = { .dot_limit = 270000, | |
215 | .p2_slow = 10, | |
216 | .p2_fast = 10 | |
044c7c41 | 217 | }, |
e4b36699 KP |
218 | }; |
219 | ||
220 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
221 | .dot = { .min = 22000, .max = 400000 }, |
222 | .vco = { .min = 1750000, .max = 3500000}, | |
223 | .n = { .min = 1, .max = 4 }, | |
224 | .m = { .min = 104, .max = 138 }, | |
225 | .m1 = { .min = 16, .max = 23 }, | |
226 | .m2 = { .min = 5, .max = 11 }, | |
227 | .p = { .min = 5, .max = 80 }, | |
228 | .p1 = { .min = 1, .max = 8}, | |
229 | .p2 = { .dot_limit = 165000, | |
230 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
231 | }; |
232 | ||
233 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
234 | .dot = { .min = 20000, .max = 115000 }, |
235 | .vco = { .min = 1750000, .max = 3500000 }, | |
236 | .n = { .min = 1, .max = 3 }, | |
237 | .m = { .min = 104, .max = 138 }, | |
238 | .m1 = { .min = 17, .max = 23 }, | |
239 | .m2 = { .min = 5, .max = 11 }, | |
240 | .p = { .min = 28, .max = 112 }, | |
241 | .p1 = { .min = 2, .max = 8 }, | |
242 | .p2 = { .dot_limit = 0, | |
243 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 244 | }, |
e4b36699 KP |
245 | }; |
246 | ||
247 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
248 | .dot = { .min = 80000, .max = 224000 }, |
249 | .vco = { .min = 1750000, .max = 3500000 }, | |
250 | .n = { .min = 1, .max = 3 }, | |
251 | .m = { .min = 104, .max = 138 }, | |
252 | .m1 = { .min = 17, .max = 23 }, | |
253 | .m2 = { .min = 5, .max = 11 }, | |
254 | .p = { .min = 14, .max = 42 }, | |
255 | .p1 = { .min = 2, .max = 6 }, | |
256 | .p2 = { .dot_limit = 0, | |
257 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 258 | }, |
e4b36699 KP |
259 | }; |
260 | ||
f2b115e6 | 261 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
262 | .dot = { .min = 20000, .max = 400000}, |
263 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 264 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
265 | .n = { .min = 3, .max = 6 }, |
266 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 267 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
268 | .m1 = { .min = 0, .max = 0 }, |
269 | .m2 = { .min = 0, .max = 254 }, | |
270 | .p = { .min = 5, .max = 80 }, | |
271 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 200000, |
273 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
274 | }; |
275 | ||
f2b115e6 | 276 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
277 | .dot = { .min = 20000, .max = 400000 }, |
278 | .vco = { .min = 1700000, .max = 3500000 }, | |
279 | .n = { .min = 3, .max = 6 }, | |
280 | .m = { .min = 2, .max = 256 }, | |
281 | .m1 = { .min = 0, .max = 0 }, | |
282 | .m2 = { .min = 0, .max = 254 }, | |
283 | .p = { .min = 7, .max = 112 }, | |
284 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
285 | .p2 = { .dot_limit = 112000, |
286 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
287 | }; |
288 | ||
273e27ca EA |
289 | /* Ironlake / Sandybridge |
290 | * | |
291 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
292 | * the range value for them is (actual_value - 2). | |
293 | */ | |
b91ad0ec | 294 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
295 | .dot = { .min = 25000, .max = 350000 }, |
296 | .vco = { .min = 1760000, .max = 3510000 }, | |
297 | .n = { .min = 1, .max = 5 }, | |
298 | .m = { .min = 79, .max = 127 }, | |
299 | .m1 = { .min = 12, .max = 22 }, | |
300 | .m2 = { .min = 5, .max = 9 }, | |
301 | .p = { .min = 5, .max = 80 }, | |
302 | .p1 = { .min = 1, .max = 8 }, | |
303 | .p2 = { .dot_limit = 225000, | |
304 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
305 | }; |
306 | ||
b91ad0ec | 307 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, | |
310 | .n = { .min = 1, .max = 3 }, | |
311 | .m = { .min = 79, .max = 118 }, | |
312 | .m1 = { .min = 12, .max = 22 }, | |
313 | .m2 = { .min = 5, .max = 9 }, | |
314 | .p = { .min = 28, .max = 112 }, | |
315 | .p1 = { .min = 2, .max = 8 }, | |
316 | .p2 = { .dot_limit = 225000, | |
317 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
318 | }; |
319 | ||
320 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 3 }, | |
324 | .m = { .min = 79, .max = 127 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 14, .max = 56 }, | |
328 | .p1 = { .min = 2, .max = 8 }, | |
329 | .p2 = { .dot_limit = 225000, | |
330 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
331 | }; |
332 | ||
273e27ca | 333 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 334 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
335 | .dot = { .min = 25000, .max = 350000 }, |
336 | .vco = { .min = 1760000, .max = 3510000 }, | |
337 | .n = { .min = 1, .max = 2 }, | |
338 | .m = { .min = 79, .max = 126 }, | |
339 | .m1 = { .min = 12, .max = 22 }, | |
340 | .m2 = { .min = 5, .max = 9 }, | |
341 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 342 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
343 | .p2 = { .dot_limit = 225000, |
344 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
345 | }; |
346 | ||
347 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 3 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
358 | }; |
359 | ||
dc730512 | 360 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
361 | /* |
362 | * These are the data rate limits (measured in fast clocks) | |
363 | * since those are the strictest limits we have. The fast | |
364 | * clock and actual rate limits are more relaxed, so checking | |
365 | * them would make no difference. | |
366 | */ | |
367 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 368 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 369 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
370 | .m1 = { .min = 2, .max = 3 }, |
371 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 372 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 373 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
374 | }; |
375 | ||
ef9348c8 CML |
376 | static const intel_limit_t intel_limits_chv = { |
377 | /* | |
378 | * These are the data rate limits (measured in fast clocks) | |
379 | * since those are the strictest limits we have. The fast | |
380 | * clock and actual rate limits are more relaxed, so checking | |
381 | * them would make no difference. | |
382 | */ | |
383 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
384 | .vco = { .min = 4860000, .max = 6700000 }, | |
385 | .n = { .min = 1, .max = 1 }, | |
386 | .m1 = { .min = 2, .max = 2 }, | |
387 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
388 | .p1 = { .min = 2, .max = 4 }, | |
389 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
390 | }; | |
391 | ||
6b4bf1c4 VS |
392 | static void vlv_clock(int refclk, intel_clock_t *clock) |
393 | { | |
394 | clock->m = clock->m1 * clock->m2; | |
395 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
396 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
397 | return; | |
fb03ac01 VS |
398 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
399 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
400 | } |
401 | ||
e0638cdf PZ |
402 | /** |
403 | * Returns whether any output on the specified pipe is of the specified type | |
404 | */ | |
405 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
406 | { | |
407 | struct drm_device *dev = crtc->dev; | |
408 | struct intel_encoder *encoder; | |
409 | ||
410 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
411 | if (encoder->type == type) | |
412 | return true; | |
413 | ||
414 | return false; | |
415 | } | |
416 | ||
1b894b59 CW |
417 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
418 | int refclk) | |
2c07245f | 419 | { |
b91ad0ec | 420 | struct drm_device *dev = crtc->dev; |
2c07245f | 421 | const intel_limit_t *limit; |
b91ad0ec ZW |
422 | |
423 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 424 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 425 | if (refclk == 100000) |
b91ad0ec ZW |
426 | limit = &intel_limits_ironlake_dual_lvds_100m; |
427 | else | |
428 | limit = &intel_limits_ironlake_dual_lvds; | |
429 | } else { | |
1b894b59 | 430 | if (refclk == 100000) |
b91ad0ec ZW |
431 | limit = &intel_limits_ironlake_single_lvds_100m; |
432 | else | |
433 | limit = &intel_limits_ironlake_single_lvds; | |
434 | } | |
c6bb3538 | 435 | } else |
b91ad0ec | 436 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
437 | |
438 | return limit; | |
439 | } | |
440 | ||
044c7c41 ML |
441 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
442 | { | |
443 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
444 | const intel_limit_t *limit; |
445 | ||
446 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 447 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 448 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 449 | else |
e4b36699 | 450 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
451 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
452 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 453 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 454 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 455 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 456 | } else /* The option is for other outputs */ |
e4b36699 | 457 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
458 | |
459 | return limit; | |
460 | } | |
461 | ||
1b894b59 | 462 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
463 | { |
464 | struct drm_device *dev = crtc->dev; | |
465 | const intel_limit_t *limit; | |
466 | ||
bad720ff | 467 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 468 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 469 | else if (IS_G4X(dev)) { |
044c7c41 | 470 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 471 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 472 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 473 | limit = &intel_limits_pineview_lvds; |
2177832f | 474 | else |
f2b115e6 | 475 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
476 | } else if (IS_CHERRYVIEW(dev)) { |
477 | limit = &intel_limits_chv; | |
a0c4da24 | 478 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 479 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
480 | } else if (!IS_GEN2(dev)) { |
481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
482 | limit = &intel_limits_i9xx_lvds; | |
483 | else | |
484 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
485 | } else { |
486 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 487 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 488 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 489 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
490 | else |
491 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
492 | } |
493 | return limit; | |
494 | } | |
495 | ||
f2b115e6 AJ |
496 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
497 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 498 | { |
2177832f SL |
499 | clock->m = clock->m2 + 2; |
500 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
501 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
502 | return; | |
fb03ac01 VS |
503 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
504 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
505 | } |
506 | ||
7429e9d4 DV |
507 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
508 | { | |
509 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
510 | } | |
511 | ||
ac58c3f0 | 512 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 513 | { |
7429e9d4 | 514 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 515 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
516 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
517 | return; | |
fb03ac01 VS |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
520 | } |
521 | ||
ef9348c8 CML |
522 | static void chv_clock(int refclk, intel_clock_t *clock) |
523 | { | |
524 | clock->m = clock->m1 * clock->m2; | |
525 | clock->p = clock->p1 * clock->p2; | |
526 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
527 | return; | |
528 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
529 | clock->n << 22); | |
530 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
531 | } | |
532 | ||
7c04d1d9 | 533 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
534 | /** |
535 | * Returns whether the given set of divisors are valid for a given refclk with | |
536 | * the given connectors. | |
537 | */ | |
538 | ||
1b894b59 CW |
539 | static bool intel_PLL_is_valid(struct drm_device *dev, |
540 | const intel_limit_t *limit, | |
541 | const intel_clock_t *clock) | |
79e53945 | 542 | { |
f01b7962 VS |
543 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
544 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 545 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 546 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 547 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 548 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 549 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 550 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
551 | |
552 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
553 | if (clock->m1 <= clock->m2) | |
554 | INTELPllInvalid("m1 <= m2\n"); | |
555 | ||
556 | if (!IS_VALLEYVIEW(dev)) { | |
557 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
558 | INTELPllInvalid("p out of range\n"); | |
559 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
560 | INTELPllInvalid("m out of range\n"); | |
561 | } | |
562 | ||
79e53945 | 563 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 564 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
565 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
566 | * connector, etc., rather than just a single range. | |
567 | */ | |
568 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 569 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
570 | |
571 | return true; | |
572 | } | |
573 | ||
d4906093 | 574 | static bool |
ee9300bb | 575 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
576 | int target, int refclk, intel_clock_t *match_clock, |
577 | intel_clock_t *best_clock) | |
79e53945 JB |
578 | { |
579 | struct drm_device *dev = crtc->dev; | |
79e53945 | 580 | intel_clock_t clock; |
79e53945 JB |
581 | int err = target; |
582 | ||
a210b028 | 583 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 584 | /* |
a210b028 DV |
585 | * For LVDS just rely on its current settings for dual-channel. |
586 | * We haven't figured out how to reliably set up different | |
587 | * single/dual channel state, if we even can. | |
79e53945 | 588 | */ |
1974cad0 | 589 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
590 | clock.p2 = limit->p2.p2_fast; |
591 | else | |
592 | clock.p2 = limit->p2.p2_slow; | |
593 | } else { | |
594 | if (target < limit->p2.dot_limit) | |
595 | clock.p2 = limit->p2.p2_slow; | |
596 | else | |
597 | clock.p2 = limit->p2.p2_fast; | |
598 | } | |
599 | ||
0206e353 | 600 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 601 | |
42158660 ZY |
602 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
603 | clock.m1++) { | |
604 | for (clock.m2 = limit->m2.min; | |
605 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 606 | if (clock.m2 >= clock.m1) |
42158660 ZY |
607 | break; |
608 | for (clock.n = limit->n.min; | |
609 | clock.n <= limit->n.max; clock.n++) { | |
610 | for (clock.p1 = limit->p1.min; | |
611 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
612 | int this_err; |
613 | ||
ac58c3f0 DV |
614 | i9xx_clock(refclk, &clock); |
615 | if (!intel_PLL_is_valid(dev, limit, | |
616 | &clock)) | |
617 | continue; | |
618 | if (match_clock && | |
619 | clock.p != match_clock->p) | |
620 | continue; | |
621 | ||
622 | this_err = abs(clock.dot - target); | |
623 | if (this_err < err) { | |
624 | *best_clock = clock; | |
625 | err = this_err; | |
626 | } | |
627 | } | |
628 | } | |
629 | } | |
630 | } | |
631 | ||
632 | return (err != target); | |
633 | } | |
634 | ||
635 | static bool | |
ee9300bb DV |
636 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
637 | int target, int refclk, intel_clock_t *match_clock, | |
638 | intel_clock_t *best_clock) | |
79e53945 JB |
639 | { |
640 | struct drm_device *dev = crtc->dev; | |
79e53945 | 641 | intel_clock_t clock; |
79e53945 JB |
642 | int err = target; |
643 | ||
a210b028 | 644 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 645 | /* |
a210b028 DV |
646 | * For LVDS just rely on its current settings for dual-channel. |
647 | * We haven't figured out how to reliably set up different | |
648 | * single/dual channel state, if we even can. | |
79e53945 | 649 | */ |
1974cad0 | 650 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
651 | clock.p2 = limit->p2.p2_fast; |
652 | else | |
653 | clock.p2 = limit->p2.p2_slow; | |
654 | } else { | |
655 | if (target < limit->p2.dot_limit) | |
656 | clock.p2 = limit->p2.p2_slow; | |
657 | else | |
658 | clock.p2 = limit->p2.p2_fast; | |
659 | } | |
660 | ||
0206e353 | 661 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 662 | |
42158660 ZY |
663 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
664 | clock.m1++) { | |
665 | for (clock.m2 = limit->m2.min; | |
666 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
667 | for (clock.n = limit->n.min; |
668 | clock.n <= limit->n.max; clock.n++) { | |
669 | for (clock.p1 = limit->p1.min; | |
670 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
671 | int this_err; |
672 | ||
ac58c3f0 | 673 | pineview_clock(refclk, &clock); |
1b894b59 CW |
674 | if (!intel_PLL_is_valid(dev, limit, |
675 | &clock)) | |
79e53945 | 676 | continue; |
cec2f356 SP |
677 | if (match_clock && |
678 | clock.p != match_clock->p) | |
679 | continue; | |
79e53945 JB |
680 | |
681 | this_err = abs(clock.dot - target); | |
682 | if (this_err < err) { | |
683 | *best_clock = clock; | |
684 | err = this_err; | |
685 | } | |
686 | } | |
687 | } | |
688 | } | |
689 | } | |
690 | ||
691 | return (err != target); | |
692 | } | |
693 | ||
d4906093 | 694 | static bool |
ee9300bb DV |
695 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
696 | int target, int refclk, intel_clock_t *match_clock, | |
697 | intel_clock_t *best_clock) | |
d4906093 ML |
698 | { |
699 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
700 | intel_clock_t clock; |
701 | int max_n; | |
702 | bool found; | |
6ba770dc AJ |
703 | /* approximately equals target * 0.00585 */ |
704 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
705 | found = false; |
706 | ||
707 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 708 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
709 | clock.p2 = limit->p2.p2_fast; |
710 | else | |
711 | clock.p2 = limit->p2.p2_slow; | |
712 | } else { | |
713 | if (target < limit->p2.dot_limit) | |
714 | clock.p2 = limit->p2.p2_slow; | |
715 | else | |
716 | clock.p2 = limit->p2.p2_fast; | |
717 | } | |
718 | ||
719 | memset(best_clock, 0, sizeof(*best_clock)); | |
720 | max_n = limit->n.max; | |
f77f13e2 | 721 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 722 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 723 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
724 | for (clock.m1 = limit->m1.max; |
725 | clock.m1 >= limit->m1.min; clock.m1--) { | |
726 | for (clock.m2 = limit->m2.max; | |
727 | clock.m2 >= limit->m2.min; clock.m2--) { | |
728 | for (clock.p1 = limit->p1.max; | |
729 | clock.p1 >= limit->p1.min; clock.p1--) { | |
730 | int this_err; | |
731 | ||
ac58c3f0 | 732 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
733 | if (!intel_PLL_is_valid(dev, limit, |
734 | &clock)) | |
d4906093 | 735 | continue; |
1b894b59 CW |
736 | |
737 | this_err = abs(clock.dot - target); | |
d4906093 ML |
738 | if (this_err < err_most) { |
739 | *best_clock = clock; | |
740 | err_most = this_err; | |
741 | max_n = clock.n; | |
742 | found = true; | |
743 | } | |
744 | } | |
745 | } | |
746 | } | |
747 | } | |
2c07245f ZW |
748 | return found; |
749 | } | |
750 | ||
a0c4da24 | 751 | static bool |
ee9300bb DV |
752 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
753 | int target, int refclk, intel_clock_t *match_clock, | |
754 | intel_clock_t *best_clock) | |
a0c4da24 | 755 | { |
f01b7962 | 756 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 757 | intel_clock_t clock; |
69e4f900 | 758 | unsigned int bestppm = 1000000; |
27e639bf VS |
759 | /* min update 19.2 MHz */ |
760 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 761 | bool found = false; |
a0c4da24 | 762 | |
6b4bf1c4 VS |
763 | target *= 5; /* fast clock */ |
764 | ||
765 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
766 | |
767 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 768 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 769 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 770 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 771 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 772 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 773 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 774 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
775 | unsigned int ppm, diff; |
776 | ||
6b4bf1c4 VS |
777 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
778 | refclk * clock.m1); | |
779 | ||
780 | vlv_clock(refclk, &clock); | |
43b0ac53 | 781 | |
f01b7962 VS |
782 | if (!intel_PLL_is_valid(dev, limit, |
783 | &clock)) | |
43b0ac53 VS |
784 | continue; |
785 | ||
6b4bf1c4 VS |
786 | diff = abs(clock.dot - target); |
787 | ppm = div_u64(1000000ULL * diff, target); | |
788 | ||
789 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 790 | bestppm = 0; |
6b4bf1c4 | 791 | *best_clock = clock; |
49e497ef | 792 | found = true; |
43b0ac53 | 793 | } |
6b4bf1c4 | 794 | |
c686122c | 795 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 796 | bestppm = ppm; |
6b4bf1c4 | 797 | *best_clock = clock; |
49e497ef | 798 | found = true; |
a0c4da24 JB |
799 | } |
800 | } | |
801 | } | |
802 | } | |
803 | } | |
a0c4da24 | 804 | |
49e497ef | 805 | return found; |
a0c4da24 | 806 | } |
a4fc5ed6 | 807 | |
ef9348c8 CML |
808 | static bool |
809 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
810 | int target, int refclk, intel_clock_t *match_clock, | |
811 | intel_clock_t *best_clock) | |
812 | { | |
813 | struct drm_device *dev = crtc->dev; | |
814 | intel_clock_t clock; | |
815 | uint64_t m2; | |
816 | int found = false; | |
817 | ||
818 | memset(best_clock, 0, sizeof(*best_clock)); | |
819 | ||
820 | /* | |
821 | * Based on hardware doc, the n always set to 1, and m1 always | |
822 | * set to 2. If requires to support 200Mhz refclk, we need to | |
823 | * revisit this because n may not 1 anymore. | |
824 | */ | |
825 | clock.n = 1, clock.m1 = 2; | |
826 | target *= 5; /* fast clock */ | |
827 | ||
828 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
829 | for (clock.p2 = limit->p2.p2_fast; | |
830 | clock.p2 >= limit->p2.p2_slow; | |
831 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
832 | ||
833 | clock.p = clock.p1 * clock.p2; | |
834 | ||
835 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
836 | clock.n) << 22, refclk * clock.m1); | |
837 | ||
838 | if (m2 > INT_MAX/clock.m1) | |
839 | continue; | |
840 | ||
841 | clock.m2 = m2; | |
842 | ||
843 | chv_clock(refclk, &clock); | |
844 | ||
845 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
846 | continue; | |
847 | ||
848 | /* based on hardware requirement, prefer bigger p | |
849 | */ | |
850 | if (clock.p > best_clock->p) { | |
851 | *best_clock = clock; | |
852 | found = true; | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | return found; | |
858 | } | |
859 | ||
20ddf665 VS |
860 | bool intel_crtc_active(struct drm_crtc *crtc) |
861 | { | |
862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
863 | ||
864 | /* Be paranoid as we can arrive here with only partial | |
865 | * state retrieved from the hardware during setup. | |
866 | * | |
241bfc38 | 867 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
868 | * as Haswell has gained clock readout/fastboot support. |
869 | * | |
66e514c1 | 870 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
871 | * properly reconstruct framebuffers. |
872 | */ | |
f4510a27 | 873 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 874 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
875 | } |
876 | ||
a5c961d1 PZ |
877 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
878 | enum pipe pipe) | |
879 | { | |
880 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
881 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
882 | ||
3b117c8f | 883 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
884 | } |
885 | ||
57e22f4a | 886 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
887 | { |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 889 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
890 | |
891 | frame = I915_READ(frame_reg); | |
892 | ||
893 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 894 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
895 | } |
896 | ||
9d0498a2 JB |
897 | /** |
898 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
899 | * @dev: drm device | |
900 | * @pipe: pipe to wait for | |
901 | * | |
902 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
903 | * mode setting code. | |
904 | */ | |
905 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 906 | { |
9d0498a2 | 907 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 908 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 909 | |
57e22f4a VS |
910 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
911 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
912 | return; |
913 | } | |
914 | ||
300387c0 CW |
915 | /* Clear existing vblank status. Note this will clear any other |
916 | * sticky status fields as well. | |
917 | * | |
918 | * This races with i915_driver_irq_handler() with the result | |
919 | * that either function could miss a vblank event. Here it is not | |
920 | * fatal, as we will either wait upon the next vblank interrupt or | |
921 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
922 | * called during modeset at which time the GPU should be idle and | |
923 | * should *not* be performing page flips and thus not waiting on | |
924 | * vblanks... | |
925 | * Currently, the result of us stealing a vblank from the irq | |
926 | * handler is that a single frame will be skipped during swapbuffers. | |
927 | */ | |
928 | I915_WRITE(pipestat_reg, | |
929 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
930 | ||
9d0498a2 | 931 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
932 | if (wait_for(I915_READ(pipestat_reg) & |
933 | PIPE_VBLANK_INTERRUPT_STATUS, | |
934 | 50)) | |
9d0498a2 JB |
935 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
936 | } | |
937 | ||
fbf49ea2 VS |
938 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
939 | { | |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
941 | u32 reg = PIPEDSL(pipe); | |
942 | u32 line1, line2; | |
943 | u32 line_mask; | |
944 | ||
945 | if (IS_GEN2(dev)) | |
946 | line_mask = DSL_LINEMASK_GEN2; | |
947 | else | |
948 | line_mask = DSL_LINEMASK_GEN3; | |
949 | ||
950 | line1 = I915_READ(reg) & line_mask; | |
951 | mdelay(5); | |
952 | line2 = I915_READ(reg) & line_mask; | |
953 | ||
954 | return line1 == line2; | |
955 | } | |
956 | ||
ab7ad7f6 KP |
957 | /* |
958 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
959 | * @dev: drm device |
960 | * @pipe: pipe to wait for | |
961 | * | |
962 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
963 | * spinning on the vblank interrupt status bit, since we won't actually | |
964 | * see an interrupt when the pipe is disabled. | |
965 | * | |
ab7ad7f6 KP |
966 | * On Gen4 and above: |
967 | * wait for the pipe register state bit to turn off | |
968 | * | |
969 | * Otherwise: | |
970 | * wait for the display line value to settle (it usually | |
971 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 972 | * |
9d0498a2 | 973 | */ |
58e10eb9 | 974 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
975 | { |
976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
977 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
978 | pipe); | |
ab7ad7f6 KP |
979 | |
980 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 981 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
982 | |
983 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
984 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
985 | 100)) | |
284637d9 | 986 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 987 | } else { |
ab7ad7f6 | 988 | /* Wait for the display line to settle */ |
fbf49ea2 | 989 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 990 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 991 | } |
79e53945 JB |
992 | } |
993 | ||
b0ea7d37 DL |
994 | /* |
995 | * ibx_digital_port_connected - is the specified port connected? | |
996 | * @dev_priv: i915 private structure | |
997 | * @port: the port to test | |
998 | * | |
999 | * Returns true if @port is connected, false otherwise. | |
1000 | */ | |
1001 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1002 | struct intel_digital_port *port) | |
1003 | { | |
1004 | u32 bit; | |
1005 | ||
c36346e3 | 1006 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1007 | switch (port->port) { |
c36346e3 DL |
1008 | case PORT_B: |
1009 | bit = SDE_PORTB_HOTPLUG; | |
1010 | break; | |
1011 | case PORT_C: | |
1012 | bit = SDE_PORTC_HOTPLUG; | |
1013 | break; | |
1014 | case PORT_D: | |
1015 | bit = SDE_PORTD_HOTPLUG; | |
1016 | break; | |
1017 | default: | |
1018 | return true; | |
1019 | } | |
1020 | } else { | |
eba905b2 | 1021 | switch (port->port) { |
c36346e3 DL |
1022 | case PORT_B: |
1023 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1024 | break; | |
1025 | case PORT_C: | |
1026 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1027 | break; | |
1028 | case PORT_D: | |
1029 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1030 | break; | |
1031 | default: | |
1032 | return true; | |
1033 | } | |
b0ea7d37 DL |
1034 | } |
1035 | ||
1036 | return I915_READ(SDEISR) & bit; | |
1037 | } | |
1038 | ||
b24e7179 JB |
1039 | static const char *state_string(bool enabled) |
1040 | { | |
1041 | return enabled ? "on" : "off"; | |
1042 | } | |
1043 | ||
1044 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1045 | void assert_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
b24e7179 JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
1050 | bool cur_state; | |
1051 | ||
1052 | reg = DPLL(pipe); | |
1053 | val = I915_READ(reg); | |
1054 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1055 | WARN(cur_state != state, | |
1056 | "PLL state assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
1058 | } | |
b24e7179 | 1059 | |
23538ef1 JN |
1060 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1061 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1062 | { | |
1063 | u32 val; | |
1064 | bool cur_state; | |
1065 | ||
1066 | mutex_lock(&dev_priv->dpio_lock); | |
1067 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1068 | mutex_unlock(&dev_priv->dpio_lock); | |
1069 | ||
1070 | cur_state = val & DSI_PLL_VCO_EN; | |
1071 | WARN(cur_state != state, | |
1072 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1073 | state_string(state), state_string(cur_state)); | |
1074 | } | |
1075 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1076 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1077 | ||
55607e8a | 1078 | struct intel_shared_dpll * |
e2b78267 DV |
1079 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1080 | { | |
1081 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1082 | ||
a43f6e0f | 1083 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1084 | return NULL; |
1085 | ||
a43f6e0f | 1086 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1087 | } |
1088 | ||
040484af | 1089 | /* For ILK+ */ |
55607e8a DV |
1090 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1091 | struct intel_shared_dpll *pll, | |
1092 | bool state) | |
040484af | 1093 | { |
040484af | 1094 | bool cur_state; |
5358901f | 1095 | struct intel_dpll_hw_state hw_state; |
040484af | 1096 | |
9d82aa17 ED |
1097 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1098 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1099 | return; | |
1100 | } | |
1101 | ||
92b27b08 | 1102 | if (WARN (!pll, |
46edb027 | 1103 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1104 | return; |
ee7b9f93 | 1105 | |
5358901f | 1106 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1107 | WARN(cur_state != state, |
5358901f DV |
1108 | "%s assertion failure (expected %s, current %s)\n", |
1109 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1110 | } |
040484af JB |
1111 | |
1112 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1113 | enum pipe pipe, bool state) | |
1114 | { | |
1115 | int reg; | |
1116 | u32 val; | |
1117 | bool cur_state; | |
ad80a810 PZ |
1118 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1119 | pipe); | |
040484af | 1120 | |
affa9354 PZ |
1121 | if (HAS_DDI(dev_priv->dev)) { |
1122 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1123 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1124 | val = I915_READ(reg); |
ad80a810 | 1125 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1126 | } else { |
1127 | reg = FDI_TX_CTL(pipe); | |
1128 | val = I915_READ(reg); | |
1129 | cur_state = !!(val & FDI_TX_ENABLE); | |
1130 | } | |
040484af JB |
1131 | WARN(cur_state != state, |
1132 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1133 | state_string(state), state_string(cur_state)); | |
1134 | } | |
1135 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1136 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1137 | ||
1138 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1139 | enum pipe pipe, bool state) | |
1140 | { | |
1141 | int reg; | |
1142 | u32 val; | |
1143 | bool cur_state; | |
1144 | ||
d63fa0dc PZ |
1145 | reg = FDI_RX_CTL(pipe); |
1146 | val = I915_READ(reg); | |
1147 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1148 | WARN(cur_state != state, |
1149 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1150 | state_string(state), state_string(cur_state)); | |
1151 | } | |
1152 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1153 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1154 | ||
1155 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1156 | enum pipe pipe) | |
1157 | { | |
1158 | int reg; | |
1159 | u32 val; | |
1160 | ||
1161 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1162 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1163 | return; |
1164 | ||
bf507ef7 | 1165 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1166 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1167 | return; |
1168 | ||
040484af JB |
1169 | reg = FDI_TX_CTL(pipe); |
1170 | val = I915_READ(reg); | |
1171 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1172 | } | |
1173 | ||
55607e8a DV |
1174 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1175 | enum pipe pipe, bool state) | |
040484af JB |
1176 | { |
1177 | int reg; | |
1178 | u32 val; | |
55607e8a | 1179 | bool cur_state; |
040484af JB |
1180 | |
1181 | reg = FDI_RX_CTL(pipe); | |
1182 | val = I915_READ(reg); | |
55607e8a DV |
1183 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1184 | WARN(cur_state != state, | |
1185 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1186 | state_string(state), state_string(cur_state)); | |
040484af JB |
1187 | } |
1188 | ||
ea0760cf JB |
1189 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe) | |
1191 | { | |
1192 | int pp_reg, lvds_reg; | |
1193 | u32 val; | |
1194 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1195 | bool locked = true; |
ea0760cf JB |
1196 | |
1197 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1198 | pp_reg = PCH_PP_CONTROL; | |
1199 | lvds_reg = PCH_LVDS; | |
1200 | } else { | |
1201 | pp_reg = PP_CONTROL; | |
1202 | lvds_reg = LVDS; | |
1203 | } | |
1204 | ||
1205 | val = I915_READ(pp_reg); | |
1206 | if (!(val & PANEL_POWER_ON) || | |
1207 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1208 | locked = false; | |
1209 | ||
1210 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1211 | panel_pipe = PIPE_B; | |
1212 | ||
1213 | WARN(panel_pipe == pipe && locked, | |
1214 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1215 | pipe_name(pipe)); |
ea0760cf JB |
1216 | } |
1217 | ||
93ce0ba6 JN |
1218 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1219 | enum pipe pipe, bool state) | |
1220 | { | |
1221 | struct drm_device *dev = dev_priv->dev; | |
1222 | bool cur_state; | |
1223 | ||
d9d82081 | 1224 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1225 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1226 | else |
5efb3e28 | 1227 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1228 | |
1229 | WARN(cur_state != state, | |
1230 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1231 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1232 | } | |
1233 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1234 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1235 | ||
b840d907 JB |
1236 | void assert_pipe(struct drm_i915_private *dev_priv, |
1237 | enum pipe pipe, bool state) | |
b24e7179 JB |
1238 | { |
1239 | int reg; | |
1240 | u32 val; | |
63d7bbe9 | 1241 | bool cur_state; |
702e7a56 PZ |
1242 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1243 | pipe); | |
b24e7179 | 1244 | |
8e636784 DV |
1245 | /* if we need the pipe A quirk it must be always on */ |
1246 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1247 | state = true; | |
1248 | ||
da7e29bd | 1249 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1250 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1251 | cur_state = false; |
1252 | } else { | |
1253 | reg = PIPECONF(cpu_transcoder); | |
1254 | val = I915_READ(reg); | |
1255 | cur_state = !!(val & PIPECONF_ENABLE); | |
1256 | } | |
1257 | ||
63d7bbe9 JB |
1258 | WARN(cur_state != state, |
1259 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1260 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1261 | } |
1262 | ||
931872fc CW |
1263 | static void assert_plane(struct drm_i915_private *dev_priv, |
1264 | enum plane plane, bool state) | |
b24e7179 JB |
1265 | { |
1266 | int reg; | |
1267 | u32 val; | |
931872fc | 1268 | bool cur_state; |
b24e7179 JB |
1269 | |
1270 | reg = DSPCNTR(plane); | |
1271 | val = I915_READ(reg); | |
931872fc CW |
1272 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1273 | WARN(cur_state != state, | |
1274 | "plane %c assertion failure (expected %s, current %s)\n", | |
1275 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1276 | } |
1277 | ||
931872fc CW |
1278 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1279 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1280 | ||
b24e7179 JB |
1281 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1282 | enum pipe pipe) | |
1283 | { | |
653e1026 | 1284 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1285 | int reg, i; |
1286 | u32 val; | |
1287 | int cur_pipe; | |
1288 | ||
653e1026 VS |
1289 | /* Primary planes are fixed to pipes on gen4+ */ |
1290 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1291 | reg = DSPCNTR(pipe); |
1292 | val = I915_READ(reg); | |
83f26f16 | 1293 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1294 | "plane %c assertion failure, should be disabled but not\n", |
1295 | plane_name(pipe)); | |
19ec1358 | 1296 | return; |
28c05794 | 1297 | } |
19ec1358 | 1298 | |
b24e7179 | 1299 | /* Need to check both planes against the pipe */ |
08e2a7de | 1300 | for_each_pipe(i) { |
b24e7179 JB |
1301 | reg = DSPCNTR(i); |
1302 | val = I915_READ(reg); | |
1303 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1304 | DISPPLANE_SEL_PIPE_SHIFT; | |
1305 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1306 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1307 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1308 | } |
1309 | } | |
1310 | ||
19332d7a JB |
1311 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1312 | enum pipe pipe) | |
1313 | { | |
20674eef | 1314 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1315 | int reg, sprite; |
19332d7a JB |
1316 | u32 val; |
1317 | ||
20674eef | 1318 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1319 | for_each_sprite(pipe, sprite) { |
1320 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1321 | val = I915_READ(reg); |
83f26f16 | 1322 | WARN(val & SP_ENABLE, |
20674eef | 1323 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1324 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1325 | } |
1326 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1327 | reg = SPRCTL(pipe); | |
19332d7a | 1328 | val = I915_READ(reg); |
83f26f16 | 1329 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1330 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1331 | plane_name(pipe), pipe_name(pipe)); |
1332 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1333 | reg = DVSCNTR(pipe); | |
19332d7a | 1334 | val = I915_READ(reg); |
83f26f16 | 1335 | WARN(val & DVS_ENABLE, |
06da8da2 | 1336 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1337 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1338 | } |
1339 | } | |
1340 | ||
89eff4be | 1341 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1342 | { |
1343 | u32 val; | |
1344 | bool enabled; | |
1345 | ||
89eff4be | 1346 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1347 | |
92f2584a JB |
1348 | val = I915_READ(PCH_DREF_CONTROL); |
1349 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1350 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1351 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1352 | } | |
1353 | ||
ab9412ba DV |
1354 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1355 | enum pipe pipe) | |
92f2584a JB |
1356 | { |
1357 | int reg; | |
1358 | u32 val; | |
1359 | bool enabled; | |
1360 | ||
ab9412ba | 1361 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1362 | val = I915_READ(reg); |
1363 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1364 | WARN(enabled, |
1365 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1366 | pipe_name(pipe)); | |
92f2584a JB |
1367 | } |
1368 | ||
4e634389 KP |
1369 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1370 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1371 | { |
1372 | if ((val & DP_PORT_EN) == 0) | |
1373 | return false; | |
1374 | ||
1375 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1376 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1377 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1378 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1379 | return false; | |
44f37d1f CML |
1380 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1381 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1382 | return false; | |
f0575e92 KP |
1383 | } else { |
1384 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1385 | return false; | |
1386 | } | |
1387 | return true; | |
1388 | } | |
1389 | ||
1519b995 KP |
1390 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1391 | enum pipe pipe, u32 val) | |
1392 | { | |
dc0fa718 | 1393 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1394 | return false; |
1395 | ||
1396 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1397 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1398 | return false; |
44f37d1f CML |
1399 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1400 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1401 | return false; | |
1519b995 | 1402 | } else { |
dc0fa718 | 1403 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1404 | return false; |
1405 | } | |
1406 | return true; | |
1407 | } | |
1408 | ||
1409 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1410 | enum pipe pipe, u32 val) | |
1411 | { | |
1412 | if ((val & LVDS_PORT_EN) == 0) | |
1413 | return false; | |
1414 | ||
1415 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1416 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1417 | return false; | |
1418 | } else { | |
1419 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1420 | return false; | |
1421 | } | |
1422 | return true; | |
1423 | } | |
1424 | ||
1425 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1426 | enum pipe pipe, u32 val) | |
1427 | { | |
1428 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1429 | return false; | |
1430 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1431 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1432 | return false; | |
1433 | } else { | |
1434 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1435 | return false; | |
1436 | } | |
1437 | return true; | |
1438 | } | |
1439 | ||
291906f1 | 1440 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1441 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1442 | { |
47a05eca | 1443 | u32 val = I915_READ(reg); |
4e634389 | 1444 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1445 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1446 | reg, pipe_name(pipe)); |
de9a35ab | 1447 | |
75c5da27 DV |
1448 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1449 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1450 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1451 | } |
1452 | ||
1453 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1454 | enum pipe pipe, int reg) | |
1455 | { | |
47a05eca | 1456 | u32 val = I915_READ(reg); |
b70ad586 | 1457 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1458 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1459 | reg, pipe_name(pipe)); |
de9a35ab | 1460 | |
dc0fa718 | 1461 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1462 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1463 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1464 | } |
1465 | ||
1466 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1467 | enum pipe pipe) | |
1468 | { | |
1469 | int reg; | |
1470 | u32 val; | |
291906f1 | 1471 | |
f0575e92 KP |
1472 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1473 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1475 | |
1476 | reg = PCH_ADPA; | |
1477 | val = I915_READ(reg); | |
b70ad586 | 1478 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 JB |
1481 | |
1482 | reg = PCH_LVDS; | |
1483 | val = I915_READ(reg); | |
b70ad586 | 1484 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1485 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1486 | pipe_name(pipe)); |
291906f1 | 1487 | |
e2debe91 PZ |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1490 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1491 | } |
1492 | ||
40e9cf64 JB |
1493 | static void intel_init_dpio(struct drm_device *dev) |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1496 | ||
1497 | if (!IS_VALLEYVIEW(dev)) | |
1498 | return; | |
1499 | ||
a09caddd CML |
1500 | /* |
1501 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1502 | * CHV x1 PHY (DP/HDMI D) | |
1503 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1504 | */ | |
1505 | if (IS_CHERRYVIEW(dev)) { | |
1506 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1507 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1508 | } else { | |
1509 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1510 | } | |
5382f5f3 JB |
1511 | } |
1512 | ||
1513 | static void intel_reset_dpio(struct drm_device *dev) | |
1514 | { | |
1515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1516 | ||
1517 | if (!IS_VALLEYVIEW(dev)) | |
1518 | return; | |
1519 | ||
076ed3b2 CML |
1520 | if (IS_CHERRYVIEW(dev)) { |
1521 | enum dpio_phy phy; | |
1522 | u32 val; | |
1523 | ||
1524 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1525 | /* Poll for phypwrgood signal */ | |
1526 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1527 | PHY_POWERGOOD(phy), 1)) | |
1528 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1529 | ||
1530 | /* | |
1531 | * Deassert common lane reset for PHY. | |
1532 | * | |
1533 | * This should only be done on init and resume from S3 | |
1534 | * with both PLLs disabled, or we risk losing DPIO and | |
1535 | * PLL synchronization. | |
1536 | */ | |
1537 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1538 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1539 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1540 | } | |
1541 | ||
1542 | } else { | |
1543 | /* | |
57021059 JB |
1544 | * If DPIO has already been reset, e.g. by BIOS, just skip all |
1545 | * this. | |
076ed3b2 | 1546 | */ |
57021059 JB |
1547 | if (I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1548 | return; | |
1549 | ||
1550 | /* | |
1551 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1552 | * Need to assert and de-assert PHY SB reset by gating the | |
1553 | * common lane power, then un-gating it. | |
1554 | * Simply ungating isn't enough to reset the PHY enough to get | |
1555 | * ports and lanes running. | |
1556 | */ | |
1557 | __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1558 | false); | |
1559 | __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1560 | true); | |
076ed3b2 | 1561 | } |
40e9cf64 JB |
1562 | } |
1563 | ||
426115cf | 1564 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1565 | { |
426115cf DV |
1566 | struct drm_device *dev = crtc->base.dev; |
1567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1568 | int reg = DPLL(crtc->pipe); | |
1569 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1570 | |
426115cf | 1571 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1572 | |
1573 | /* No really, not for ILK+ */ | |
1574 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1575 | ||
1576 | /* PLL is protected by panel, make sure we can write it */ | |
1577 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1578 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1579 | |
426115cf DV |
1580 | I915_WRITE(reg, dpll); |
1581 | POSTING_READ(reg); | |
1582 | udelay(150); | |
1583 | ||
1584 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1585 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1586 | ||
1587 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1588 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1589 | |
1590 | /* We do this three times for luck */ | |
426115cf | 1591 | I915_WRITE(reg, dpll); |
87442f73 DV |
1592 | POSTING_READ(reg); |
1593 | udelay(150); /* wait for warmup */ | |
426115cf | 1594 | I915_WRITE(reg, dpll); |
87442f73 DV |
1595 | POSTING_READ(reg); |
1596 | udelay(150); /* wait for warmup */ | |
426115cf | 1597 | I915_WRITE(reg, dpll); |
87442f73 DV |
1598 | POSTING_READ(reg); |
1599 | udelay(150); /* wait for warmup */ | |
1600 | } | |
1601 | ||
9d556c99 CML |
1602 | static void chv_enable_pll(struct intel_crtc *crtc) |
1603 | { | |
1604 | struct drm_device *dev = crtc->base.dev; | |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1606 | int pipe = crtc->pipe; | |
1607 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1608 | u32 tmp; |
1609 | ||
1610 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1611 | ||
1612 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1613 | ||
1614 | mutex_lock(&dev_priv->dpio_lock); | |
1615 | ||
1616 | /* Enable back the 10bit clock to display controller */ | |
1617 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1618 | tmp |= DPIO_DCLKP_EN; | |
1619 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1620 | ||
1621 | /* | |
1622 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1623 | */ | |
1624 | udelay(1); | |
1625 | ||
1626 | /* Enable PLL */ | |
a11b0703 | 1627 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1628 | |
1629 | /* Check PLL is locked */ | |
a11b0703 | 1630 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1631 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1632 | ||
a11b0703 VS |
1633 | /* not sure when this should be written */ |
1634 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1635 | POSTING_READ(DPLL_MD(pipe)); | |
1636 | ||
9d556c99 CML |
1637 | mutex_unlock(&dev_priv->dpio_lock); |
1638 | } | |
1639 | ||
66e3d5c0 | 1640 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1641 | { |
66e3d5c0 DV |
1642 | struct drm_device *dev = crtc->base.dev; |
1643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1644 | int reg = DPLL(crtc->pipe); | |
1645 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1646 | |
66e3d5c0 | 1647 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1648 | |
63d7bbe9 | 1649 | /* No really, not for ILK+ */ |
3d13ef2e | 1650 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1651 | |
1652 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1653 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1654 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1655 | |
66e3d5c0 DV |
1656 | I915_WRITE(reg, dpll); |
1657 | ||
1658 | /* Wait for the clocks to stabilize. */ | |
1659 | POSTING_READ(reg); | |
1660 | udelay(150); | |
1661 | ||
1662 | if (INTEL_INFO(dev)->gen >= 4) { | |
1663 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1664 | crtc->config.dpll_hw_state.dpll_md); | |
1665 | } else { | |
1666 | /* The pixel multiplier can only be updated once the | |
1667 | * DPLL is enabled and the clocks are stable. | |
1668 | * | |
1669 | * So write it again. | |
1670 | */ | |
1671 | I915_WRITE(reg, dpll); | |
1672 | } | |
63d7bbe9 JB |
1673 | |
1674 | /* We do this three times for luck */ | |
66e3d5c0 | 1675 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1676 | POSTING_READ(reg); |
1677 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1678 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1679 | POSTING_READ(reg); |
1680 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1681 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1682 | POSTING_READ(reg); |
1683 | udelay(150); /* wait for warmup */ | |
1684 | } | |
1685 | ||
1686 | /** | |
50b44a44 | 1687 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1688 | * @dev_priv: i915 private structure |
1689 | * @pipe: pipe PLL to disable | |
1690 | * | |
1691 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1692 | * | |
1693 | * Note! This is for pre-ILK only. | |
1694 | */ | |
50b44a44 | 1695 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1696 | { |
63d7bbe9 JB |
1697 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1698 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1699 | return; | |
1700 | ||
1701 | /* Make sure the pipe isn't still relying on us */ | |
1702 | assert_pipe_disabled(dev_priv, pipe); | |
1703 | ||
50b44a44 DV |
1704 | I915_WRITE(DPLL(pipe), 0); |
1705 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1706 | } |
1707 | ||
f6071166 JB |
1708 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1709 | { | |
1710 | u32 val = 0; | |
1711 | ||
1712 | /* Make sure the pipe isn't still relying on us */ | |
1713 | assert_pipe_disabled(dev_priv, pipe); | |
1714 | ||
e5cbfbfb ID |
1715 | /* |
1716 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1717 | * The latter is needed for VGA hotplug / manual detection. | |
1718 | */ | |
f6071166 | 1719 | if (pipe == PIPE_B) |
e5cbfbfb | 1720 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1721 | I915_WRITE(DPLL(pipe), val); |
1722 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1723 | |
1724 | } | |
1725 | ||
1726 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1727 | { | |
d752048d | 1728 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1729 | u32 val; |
1730 | ||
a11b0703 VS |
1731 | /* Make sure the pipe isn't still relying on us */ |
1732 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1733 | |
a11b0703 VS |
1734 | /* Set PLL en = 0 */ |
1735 | val = DPLL_SSC_REF_CLOCK_CHV; | |
1736 | if (pipe != PIPE_A) | |
1737 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1738 | I915_WRITE(DPLL(pipe), val); | |
1739 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1740 | |
1741 | mutex_lock(&dev_priv->dpio_lock); | |
1742 | ||
1743 | /* Disable 10bit clock to display controller */ | |
1744 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1745 | val &= ~DPIO_DCLKP_EN; | |
1746 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1747 | ||
61407f6d VS |
1748 | /* disable left/right clock distribution */ |
1749 | if (pipe != PIPE_B) { | |
1750 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1751 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1752 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1753 | } else { | |
1754 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1755 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1756 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1757 | } | |
1758 | ||
d752048d | 1759 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1760 | } |
1761 | ||
e4607fcf CML |
1762 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1763 | struct intel_digital_port *dport) | |
89b667f8 JB |
1764 | { |
1765 | u32 port_mask; | |
00fc31b7 | 1766 | int dpll_reg; |
89b667f8 | 1767 | |
e4607fcf CML |
1768 | switch (dport->port) { |
1769 | case PORT_B: | |
89b667f8 | 1770 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1771 | dpll_reg = DPLL(0); |
e4607fcf CML |
1772 | break; |
1773 | case PORT_C: | |
89b667f8 | 1774 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1775 | dpll_reg = DPLL(0); |
1776 | break; | |
1777 | case PORT_D: | |
1778 | port_mask = DPLL_PORTD_READY_MASK; | |
1779 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1780 | break; |
1781 | default: | |
1782 | BUG(); | |
1783 | } | |
89b667f8 | 1784 | |
00fc31b7 | 1785 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1786 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1787 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1788 | } |
1789 | ||
b14b1055 DV |
1790 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1791 | { | |
1792 | struct drm_device *dev = crtc->base.dev; | |
1793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1794 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1795 | ||
be19f0ff CW |
1796 | if (WARN_ON(pll == NULL)) |
1797 | return; | |
1798 | ||
b14b1055 DV |
1799 | WARN_ON(!pll->refcount); |
1800 | if (pll->active == 0) { | |
1801 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1802 | WARN_ON(pll->on); | |
1803 | assert_shared_dpll_disabled(dev_priv, pll); | |
1804 | ||
1805 | pll->mode_set(dev_priv, pll); | |
1806 | } | |
1807 | } | |
1808 | ||
92f2584a | 1809 | /** |
85b3894f | 1810 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1811 | * @dev_priv: i915 private structure |
1812 | * @pipe: pipe PLL to enable | |
1813 | * | |
1814 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1815 | * drives the transcoder clock. | |
1816 | */ | |
85b3894f | 1817 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1818 | { |
3d13ef2e DL |
1819 | struct drm_device *dev = crtc->base.dev; |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1821 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1822 | |
87a875bb | 1823 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1824 | return; |
1825 | ||
1826 | if (WARN_ON(pll->refcount == 0)) | |
1827 | return; | |
ee7b9f93 | 1828 | |
46edb027 DV |
1829 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1830 | pll->name, pll->active, pll->on, | |
e2b78267 | 1831 | crtc->base.base.id); |
92f2584a | 1832 | |
cdbd2316 DV |
1833 | if (pll->active++) { |
1834 | WARN_ON(!pll->on); | |
e9d6944e | 1835 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1836 | return; |
1837 | } | |
f4a091c7 | 1838 | WARN_ON(pll->on); |
ee7b9f93 | 1839 | |
46edb027 | 1840 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1841 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1842 | pll->on = true; |
92f2584a JB |
1843 | } |
1844 | ||
e2b78267 | 1845 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1846 | { |
3d13ef2e DL |
1847 | struct drm_device *dev = crtc->base.dev; |
1848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1849 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1850 | |
92f2584a | 1851 | /* PCH only available on ILK+ */ |
3d13ef2e | 1852 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1853 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1854 | return; |
92f2584a | 1855 | |
48da64a8 CW |
1856 | if (WARN_ON(pll->refcount == 0)) |
1857 | return; | |
7a419866 | 1858 | |
46edb027 DV |
1859 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1860 | pll->name, pll->active, pll->on, | |
e2b78267 | 1861 | crtc->base.base.id); |
7a419866 | 1862 | |
48da64a8 | 1863 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1864 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1865 | return; |
1866 | } | |
1867 | ||
e9d6944e | 1868 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1869 | WARN_ON(!pll->on); |
cdbd2316 | 1870 | if (--pll->active) |
7a419866 | 1871 | return; |
ee7b9f93 | 1872 | |
46edb027 | 1873 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1874 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1875 | pll->on = false; |
92f2584a JB |
1876 | } |
1877 | ||
b8a4f404 PZ |
1878 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1879 | enum pipe pipe) | |
040484af | 1880 | { |
23670b32 | 1881 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1882 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1883 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1884 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1885 | |
1886 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1887 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1888 | |
1889 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1890 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1891 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1892 | |
1893 | /* FDI must be feeding us bits for PCH ports */ | |
1894 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1895 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1896 | ||
23670b32 DV |
1897 | if (HAS_PCH_CPT(dev)) { |
1898 | /* Workaround: Set the timing override bit before enabling the | |
1899 | * pch transcoder. */ | |
1900 | reg = TRANS_CHICKEN2(pipe); | |
1901 | val = I915_READ(reg); | |
1902 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1903 | I915_WRITE(reg, val); | |
59c859d6 | 1904 | } |
23670b32 | 1905 | |
ab9412ba | 1906 | reg = PCH_TRANSCONF(pipe); |
040484af | 1907 | val = I915_READ(reg); |
5f7f726d | 1908 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1909 | |
1910 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1911 | /* | |
1912 | * make the BPC in transcoder be consistent with | |
1913 | * that in pipeconf reg. | |
1914 | */ | |
dfd07d72 DV |
1915 | val &= ~PIPECONF_BPC_MASK; |
1916 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1917 | } |
5f7f726d PZ |
1918 | |
1919 | val &= ~TRANS_INTERLACE_MASK; | |
1920 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1921 | if (HAS_PCH_IBX(dev_priv->dev) && |
1922 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1923 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1924 | else | |
1925 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1926 | else |
1927 | val |= TRANS_PROGRESSIVE; | |
1928 | ||
040484af JB |
1929 | I915_WRITE(reg, val | TRANS_ENABLE); |
1930 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1931 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1932 | } |
1933 | ||
8fb033d7 | 1934 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1935 | enum transcoder cpu_transcoder) |
040484af | 1936 | { |
8fb033d7 | 1937 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1938 | |
1939 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1940 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1941 | |
8fb033d7 | 1942 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1943 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1944 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1945 | |
223a6fdf PZ |
1946 | /* Workaround: set timing override bit. */ |
1947 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1948 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1949 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1950 | ||
25f3ef11 | 1951 | val = TRANS_ENABLE; |
937bb610 | 1952 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1953 | |
9a76b1c6 PZ |
1954 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1955 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1956 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1957 | else |
1958 | val |= TRANS_PROGRESSIVE; | |
1959 | ||
ab9412ba DV |
1960 | I915_WRITE(LPT_TRANSCONF, val); |
1961 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1962 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1963 | } |
1964 | ||
b8a4f404 PZ |
1965 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1966 | enum pipe pipe) | |
040484af | 1967 | { |
23670b32 DV |
1968 | struct drm_device *dev = dev_priv->dev; |
1969 | uint32_t reg, val; | |
040484af JB |
1970 | |
1971 | /* FDI relies on the transcoder */ | |
1972 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1973 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1974 | ||
291906f1 JB |
1975 | /* Ports must be off as well */ |
1976 | assert_pch_ports_disabled(dev_priv, pipe); | |
1977 | ||
ab9412ba | 1978 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1979 | val = I915_READ(reg); |
1980 | val &= ~TRANS_ENABLE; | |
1981 | I915_WRITE(reg, val); | |
1982 | /* wait for PCH transcoder off, transcoder state */ | |
1983 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1984 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1985 | |
1986 | if (!HAS_PCH_IBX(dev)) { | |
1987 | /* Workaround: Clear the timing override chicken bit again. */ | |
1988 | reg = TRANS_CHICKEN2(pipe); | |
1989 | val = I915_READ(reg); | |
1990 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1991 | I915_WRITE(reg, val); | |
1992 | } | |
040484af JB |
1993 | } |
1994 | ||
ab4d966c | 1995 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1996 | { |
8fb033d7 PZ |
1997 | u32 val; |
1998 | ||
ab9412ba | 1999 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2000 | val &= ~TRANS_ENABLE; |
ab9412ba | 2001 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2002 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2003 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2004 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2005 | |
2006 | /* Workaround: clear timing override bit. */ | |
2007 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2008 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2009 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2010 | } |
2011 | ||
b24e7179 | 2012 | /** |
309cfea8 | 2013 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2014 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2015 | * |
0372264a | 2016 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2017 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2018 | */ |
e1fdc473 | 2019 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2020 | { |
0372264a PZ |
2021 | struct drm_device *dev = crtc->base.dev; |
2022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2023 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2024 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2025 | pipe); | |
1a240d4d | 2026 | enum pipe pch_transcoder; |
b24e7179 JB |
2027 | int reg; |
2028 | u32 val; | |
2029 | ||
58c6eaa2 | 2030 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2031 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2032 | assert_sprites_disabled(dev_priv, pipe); |
2033 | ||
681e5811 | 2034 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2035 | pch_transcoder = TRANSCODER_A; |
2036 | else | |
2037 | pch_transcoder = pipe; | |
2038 | ||
b24e7179 JB |
2039 | /* |
2040 | * A pipe without a PLL won't actually be able to drive bits from | |
2041 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2042 | * need the check. | |
2043 | */ | |
2044 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2045 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2046 | assert_dsi_pll_enabled(dev_priv); |
2047 | else | |
2048 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2049 | else { |
30421c4f | 2050 | if (crtc->config.has_pch_encoder) { |
040484af | 2051 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2052 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2053 | assert_fdi_tx_pll_enabled(dev_priv, |
2054 | (enum pipe) cpu_transcoder); | |
040484af JB |
2055 | } |
2056 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2057 | } | |
b24e7179 | 2058 | |
702e7a56 | 2059 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2060 | val = I915_READ(reg); |
7ad25d48 PZ |
2061 | if (val & PIPECONF_ENABLE) { |
2062 | WARN_ON(!(pipe == PIPE_A && | |
2063 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2064 | return; |
7ad25d48 | 2065 | } |
00d70b15 CW |
2066 | |
2067 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2068 | POSTING_READ(reg); |
b24e7179 JB |
2069 | } |
2070 | ||
2071 | /** | |
309cfea8 | 2072 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2073 | * @dev_priv: i915 private structure |
2074 | * @pipe: pipe to disable | |
2075 | * | |
2076 | * Disable @pipe, making sure that various hardware specific requirements | |
2077 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2078 | * | |
2079 | * @pipe should be %PIPE_A or %PIPE_B. | |
2080 | * | |
2081 | * Will wait until the pipe has shut down before returning. | |
2082 | */ | |
2083 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2084 | enum pipe pipe) | |
2085 | { | |
702e7a56 PZ |
2086 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2087 | pipe); | |
b24e7179 JB |
2088 | int reg; |
2089 | u32 val; | |
2090 | ||
2091 | /* | |
2092 | * Make sure planes won't keep trying to pump pixels to us, | |
2093 | * or we might hang the display. | |
2094 | */ | |
2095 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2096 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2097 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2098 | |
2099 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2100 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2101 | return; | |
2102 | ||
702e7a56 | 2103 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2104 | val = I915_READ(reg); |
00d70b15 CW |
2105 | if ((val & PIPECONF_ENABLE) == 0) |
2106 | return; | |
2107 | ||
2108 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2109 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2110 | } | |
2111 | ||
d74362c9 KP |
2112 | /* |
2113 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2114 | * trigger in order to latch. The display address reg provides this. | |
2115 | */ | |
1dba99f4 VS |
2116 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2117 | enum plane plane) | |
d74362c9 | 2118 | { |
3d13ef2e DL |
2119 | struct drm_device *dev = dev_priv->dev; |
2120 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2121 | |
2122 | I915_WRITE(reg, I915_READ(reg)); | |
2123 | POSTING_READ(reg); | |
d74362c9 KP |
2124 | } |
2125 | ||
b24e7179 | 2126 | /** |
262ca2b0 | 2127 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2128 | * @dev_priv: i915 private structure |
2129 | * @plane: plane to enable | |
2130 | * @pipe: pipe being fed | |
2131 | * | |
2132 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2133 | */ | |
262ca2b0 MR |
2134 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2135 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2136 | { |
33c3b0d1 | 2137 | struct drm_device *dev = dev_priv->dev; |
939c2fe8 VS |
2138 | struct intel_crtc *intel_crtc = |
2139 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2140 | int reg; |
2141 | u32 val; | |
2142 | ||
2143 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2144 | assert_pipe_enabled(dev_priv, pipe); | |
2145 | ||
98ec7739 VS |
2146 | if (intel_crtc->primary_enabled) |
2147 | return; | |
0037f71c | 2148 | |
4c445e0e | 2149 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2150 | |
b24e7179 JB |
2151 | reg = DSPCNTR(plane); |
2152 | val = I915_READ(reg); | |
10efa932 | 2153 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2154 | |
2155 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2156 | intel_flush_primary_plane(dev_priv, plane); |
33c3b0d1 VS |
2157 | |
2158 | /* | |
2159 | * BDW signals flip done immediately if the plane | |
2160 | * is disabled, even if the plane enable is already | |
2161 | * armed to occur at the next vblank :( | |
2162 | */ | |
2163 | if (IS_BROADWELL(dev)) | |
2164 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2165 | } |
2166 | ||
b24e7179 | 2167 | /** |
262ca2b0 | 2168 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2169 | * @dev_priv: i915 private structure |
2170 | * @plane: plane to disable | |
2171 | * @pipe: pipe consuming the data | |
2172 | * | |
2173 | * Disable @plane; should be an independent operation. | |
2174 | */ | |
262ca2b0 MR |
2175 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2176 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2177 | { |
939c2fe8 VS |
2178 | struct intel_crtc *intel_crtc = |
2179 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2180 | int reg; |
2181 | u32 val; | |
2182 | ||
98ec7739 VS |
2183 | if (!intel_crtc->primary_enabled) |
2184 | return; | |
0037f71c | 2185 | |
4c445e0e | 2186 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2187 | |
b24e7179 JB |
2188 | reg = DSPCNTR(plane); |
2189 | val = I915_READ(reg); | |
10efa932 | 2190 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2191 | |
2192 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2193 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2194 | } |
2195 | ||
693db184 CW |
2196 | static bool need_vtd_wa(struct drm_device *dev) |
2197 | { | |
2198 | #ifdef CONFIG_INTEL_IOMMU | |
2199 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2200 | return true; | |
2201 | #endif | |
2202 | return false; | |
2203 | } | |
2204 | ||
a57ce0b2 JB |
2205 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2206 | { | |
2207 | int tile_height; | |
2208 | ||
2209 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2210 | return ALIGN(height, tile_height); | |
2211 | } | |
2212 | ||
127bd2ac | 2213 | int |
48b956c5 | 2214 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2215 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2216 | struct intel_engine_cs *pipelined) |
6b95a207 | 2217 | { |
ce453d81 | 2218 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2219 | u32 alignment; |
2220 | int ret; | |
2221 | ||
05394f39 | 2222 | switch (obj->tiling_mode) { |
6b95a207 | 2223 | case I915_TILING_NONE: |
534843da CW |
2224 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2225 | alignment = 128 * 1024; | |
a6c45cf0 | 2226 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2227 | alignment = 4 * 1024; |
2228 | else | |
2229 | alignment = 64 * 1024; | |
6b95a207 KH |
2230 | break; |
2231 | case I915_TILING_X: | |
2232 | /* pin() will align the object as required by fence */ | |
2233 | alignment = 0; | |
2234 | break; | |
2235 | case I915_TILING_Y: | |
80075d49 | 2236 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2237 | return -EINVAL; |
2238 | default: | |
2239 | BUG(); | |
2240 | } | |
2241 | ||
693db184 CW |
2242 | /* Note that the w/a also requires 64 PTE of padding following the |
2243 | * bo. We currently fill all unused PTE with the shadow page and so | |
2244 | * we should always have valid PTE following the scanout preventing | |
2245 | * the VT-d warning. | |
2246 | */ | |
2247 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2248 | alignment = 256 * 1024; | |
2249 | ||
ce453d81 | 2250 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2251 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2252 | if (ret) |
ce453d81 | 2253 | goto err_interruptible; |
6b95a207 KH |
2254 | |
2255 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2256 | * fence, whereas 965+ only requires a fence if using | |
2257 | * framebuffer compression. For simplicity, we always install | |
2258 | * a fence as the cost is not that onerous. | |
2259 | */ | |
06d98131 | 2260 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2261 | if (ret) |
2262 | goto err_unpin; | |
1690e1eb | 2263 | |
9a5a53b3 | 2264 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2265 | |
ce453d81 | 2266 | dev_priv->mm.interruptible = true; |
6b95a207 | 2267 | return 0; |
48b956c5 CW |
2268 | |
2269 | err_unpin: | |
cc98b413 | 2270 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2271 | err_interruptible: |
2272 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2273 | return ret; |
6b95a207 KH |
2274 | } |
2275 | ||
1690e1eb CW |
2276 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2277 | { | |
2278 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2279 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2280 | } |
2281 | ||
c2c75131 DV |
2282 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2283 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2284 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2285 | unsigned int tiling_mode, | |
2286 | unsigned int cpp, | |
2287 | unsigned int pitch) | |
c2c75131 | 2288 | { |
bc752862 CW |
2289 | if (tiling_mode != I915_TILING_NONE) { |
2290 | unsigned int tile_rows, tiles; | |
c2c75131 | 2291 | |
bc752862 CW |
2292 | tile_rows = *y / 8; |
2293 | *y %= 8; | |
c2c75131 | 2294 | |
bc752862 CW |
2295 | tiles = *x / (512/cpp); |
2296 | *x %= 512/cpp; | |
2297 | ||
2298 | return tile_rows * pitch * 8 + tiles * 4096; | |
2299 | } else { | |
2300 | unsigned int offset; | |
2301 | ||
2302 | offset = *y * pitch + *x * cpp; | |
2303 | *y = 0; | |
2304 | *x = (offset & 4095) / cpp; | |
2305 | return offset & -4096; | |
2306 | } | |
c2c75131 DV |
2307 | } |
2308 | ||
46f297fb JB |
2309 | int intel_format_to_fourcc(int format) |
2310 | { | |
2311 | switch (format) { | |
2312 | case DISPPLANE_8BPP: | |
2313 | return DRM_FORMAT_C8; | |
2314 | case DISPPLANE_BGRX555: | |
2315 | return DRM_FORMAT_XRGB1555; | |
2316 | case DISPPLANE_BGRX565: | |
2317 | return DRM_FORMAT_RGB565; | |
2318 | default: | |
2319 | case DISPPLANE_BGRX888: | |
2320 | return DRM_FORMAT_XRGB8888; | |
2321 | case DISPPLANE_RGBX888: | |
2322 | return DRM_FORMAT_XBGR8888; | |
2323 | case DISPPLANE_BGRX101010: | |
2324 | return DRM_FORMAT_XRGB2101010; | |
2325 | case DISPPLANE_RGBX101010: | |
2326 | return DRM_FORMAT_XBGR2101010; | |
2327 | } | |
2328 | } | |
2329 | ||
484b41dd | 2330 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2331 | struct intel_plane_config *plane_config) |
2332 | { | |
2333 | struct drm_device *dev = crtc->base.dev; | |
2334 | struct drm_i915_gem_object *obj = NULL; | |
2335 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2336 | u32 base = plane_config->base; | |
2337 | ||
ff2652ea CW |
2338 | if (plane_config->size == 0) |
2339 | return false; | |
2340 | ||
46f297fb JB |
2341 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2342 | plane_config->size); | |
2343 | if (!obj) | |
484b41dd | 2344 | return false; |
46f297fb JB |
2345 | |
2346 | if (plane_config->tiled) { | |
2347 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2348 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2349 | } |
2350 | ||
66e514c1 DA |
2351 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2352 | mode_cmd.width = crtc->base.primary->fb->width; | |
2353 | mode_cmd.height = crtc->base.primary->fb->height; | |
2354 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2355 | |
2356 | mutex_lock(&dev->struct_mutex); | |
2357 | ||
66e514c1 | 2358 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2359 | &mode_cmd, obj)) { |
46f297fb JB |
2360 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2361 | goto out_unref_obj; | |
2362 | } | |
2363 | ||
a071fa00 | 2364 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2365 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2366 | |
2367 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2368 | return true; | |
46f297fb JB |
2369 | |
2370 | out_unref_obj: | |
2371 | drm_gem_object_unreference(&obj->base); | |
2372 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2373 | return false; |
2374 | } | |
2375 | ||
2376 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2377 | struct intel_plane_config *plane_config) | |
2378 | { | |
2379 | struct drm_device *dev = intel_crtc->base.dev; | |
2380 | struct drm_crtc *c; | |
2381 | struct intel_crtc *i; | |
2382 | struct intel_framebuffer *fb; | |
2383 | ||
66e514c1 | 2384 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2385 | return; |
2386 | ||
2387 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2388 | return; | |
2389 | ||
66e514c1 DA |
2390 | kfree(intel_crtc->base.primary->fb); |
2391 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2392 | |
2393 | /* | |
2394 | * Failed to alloc the obj, check to see if we should share | |
2395 | * an fb with another CRTC instead | |
2396 | */ | |
70e1e0ec | 2397 | for_each_crtc(dev, c) { |
484b41dd JB |
2398 | i = to_intel_crtc(c); |
2399 | ||
2400 | if (c == &intel_crtc->base) | |
2401 | continue; | |
2402 | ||
66e514c1 | 2403 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2404 | continue; |
2405 | ||
66e514c1 | 2406 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2407 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2408 | drm_framebuffer_reference(c->primary->fb); |
2409 | intel_crtc->base.primary->fb = c->primary->fb; | |
a071fa00 | 2410 | fb->obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2411 | break; |
2412 | } | |
2413 | } | |
46f297fb JB |
2414 | } |
2415 | ||
29b9bde6 DV |
2416 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2417 | struct drm_framebuffer *fb, | |
2418 | int x, int y) | |
81255565 JB |
2419 | { |
2420 | struct drm_device *dev = crtc->dev; | |
2421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2423 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2424 | struct drm_i915_gem_object *obj; |
81255565 | 2425 | int plane = intel_crtc->plane; |
e506a0c6 | 2426 | unsigned long linear_offset; |
81255565 | 2427 | u32 dspcntr; |
5eddb70b | 2428 | u32 reg; |
81255565 | 2429 | |
81255565 JB |
2430 | intel_fb = to_intel_framebuffer(fb); |
2431 | obj = intel_fb->obj; | |
81255565 | 2432 | |
5eddb70b CW |
2433 | reg = DSPCNTR(plane); |
2434 | dspcntr = I915_READ(reg); | |
81255565 JB |
2435 | /* Mask out pixel format bits in case we change it */ |
2436 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2437 | switch (fb->pixel_format) { |
2438 | case DRM_FORMAT_C8: | |
81255565 JB |
2439 | dspcntr |= DISPPLANE_8BPP; |
2440 | break; | |
57779d06 VS |
2441 | case DRM_FORMAT_XRGB1555: |
2442 | case DRM_FORMAT_ARGB1555: | |
2443 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2444 | break; |
57779d06 VS |
2445 | case DRM_FORMAT_RGB565: |
2446 | dspcntr |= DISPPLANE_BGRX565; | |
2447 | break; | |
2448 | case DRM_FORMAT_XRGB8888: | |
2449 | case DRM_FORMAT_ARGB8888: | |
2450 | dspcntr |= DISPPLANE_BGRX888; | |
2451 | break; | |
2452 | case DRM_FORMAT_XBGR8888: | |
2453 | case DRM_FORMAT_ABGR8888: | |
2454 | dspcntr |= DISPPLANE_RGBX888; | |
2455 | break; | |
2456 | case DRM_FORMAT_XRGB2101010: | |
2457 | case DRM_FORMAT_ARGB2101010: | |
2458 | dspcntr |= DISPPLANE_BGRX101010; | |
2459 | break; | |
2460 | case DRM_FORMAT_XBGR2101010: | |
2461 | case DRM_FORMAT_ABGR2101010: | |
2462 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2463 | break; |
2464 | default: | |
baba133a | 2465 | BUG(); |
81255565 | 2466 | } |
57779d06 | 2467 | |
a6c45cf0 | 2468 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2469 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2470 | dspcntr |= DISPPLANE_TILED; |
2471 | else | |
2472 | dspcntr &= ~DISPPLANE_TILED; | |
2473 | } | |
2474 | ||
de1aa629 VS |
2475 | if (IS_G4X(dev)) |
2476 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2477 | ||
5eddb70b | 2478 | I915_WRITE(reg, dspcntr); |
81255565 | 2479 | |
e506a0c6 | 2480 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2481 | |
c2c75131 DV |
2482 | if (INTEL_INFO(dev)->gen >= 4) { |
2483 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2484 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2485 | fb->bits_per_pixel / 8, | |
2486 | fb->pitches[0]); | |
c2c75131 DV |
2487 | linear_offset -= intel_crtc->dspaddr_offset; |
2488 | } else { | |
e506a0c6 | 2489 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2490 | } |
e506a0c6 | 2491 | |
f343c5f6 BW |
2492 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2493 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2494 | fb->pitches[0]); | |
01f2c773 | 2495 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2496 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2497 | I915_WRITE(DSPSURF(plane), |
2498 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2499 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2500 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2501 | } else |
f343c5f6 | 2502 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2503 | POSTING_READ(reg); |
17638cd6 JB |
2504 | } |
2505 | ||
29b9bde6 DV |
2506 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2507 | struct drm_framebuffer *fb, | |
2508 | int x, int y) | |
17638cd6 JB |
2509 | { |
2510 | struct drm_device *dev = crtc->dev; | |
2511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2513 | struct intel_framebuffer *intel_fb; | |
2514 | struct drm_i915_gem_object *obj; | |
2515 | int plane = intel_crtc->plane; | |
e506a0c6 | 2516 | unsigned long linear_offset; |
17638cd6 JB |
2517 | u32 dspcntr; |
2518 | u32 reg; | |
2519 | ||
17638cd6 JB |
2520 | intel_fb = to_intel_framebuffer(fb); |
2521 | obj = intel_fb->obj; | |
2522 | ||
2523 | reg = DSPCNTR(plane); | |
2524 | dspcntr = I915_READ(reg); | |
2525 | /* Mask out pixel format bits in case we change it */ | |
2526 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2527 | switch (fb->pixel_format) { |
2528 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2529 | dspcntr |= DISPPLANE_8BPP; |
2530 | break; | |
57779d06 VS |
2531 | case DRM_FORMAT_RGB565: |
2532 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2533 | break; |
57779d06 VS |
2534 | case DRM_FORMAT_XRGB8888: |
2535 | case DRM_FORMAT_ARGB8888: | |
2536 | dspcntr |= DISPPLANE_BGRX888; | |
2537 | break; | |
2538 | case DRM_FORMAT_XBGR8888: | |
2539 | case DRM_FORMAT_ABGR8888: | |
2540 | dspcntr |= DISPPLANE_RGBX888; | |
2541 | break; | |
2542 | case DRM_FORMAT_XRGB2101010: | |
2543 | case DRM_FORMAT_ARGB2101010: | |
2544 | dspcntr |= DISPPLANE_BGRX101010; | |
2545 | break; | |
2546 | case DRM_FORMAT_XBGR2101010: | |
2547 | case DRM_FORMAT_ABGR2101010: | |
2548 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2549 | break; |
2550 | default: | |
baba133a | 2551 | BUG(); |
17638cd6 JB |
2552 | } |
2553 | ||
2554 | if (obj->tiling_mode != I915_TILING_NONE) | |
2555 | dspcntr |= DISPPLANE_TILED; | |
2556 | else | |
2557 | dspcntr &= ~DISPPLANE_TILED; | |
2558 | ||
b42c6009 | 2559 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2560 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2561 | else | |
2562 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2563 | |
2564 | I915_WRITE(reg, dspcntr); | |
2565 | ||
e506a0c6 | 2566 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2567 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2568 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2569 | fb->bits_per_pixel / 8, | |
2570 | fb->pitches[0]); | |
c2c75131 | 2571 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2572 | |
f343c5f6 BW |
2573 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2574 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2575 | fb->pitches[0]); | |
01f2c773 | 2576 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2577 | I915_WRITE(DSPSURF(plane), |
2578 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2579 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2580 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2581 | } else { | |
2582 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2583 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2584 | } | |
17638cd6 | 2585 | POSTING_READ(reg); |
17638cd6 JB |
2586 | } |
2587 | ||
2588 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2589 | static int | |
2590 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2591 | int x, int y, enum mode_set_atomic state) | |
2592 | { | |
2593 | struct drm_device *dev = crtc->dev; | |
2594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2595 | |
6b8e6ed0 CW |
2596 | if (dev_priv->display.disable_fbc) |
2597 | dev_priv->display.disable_fbc(dev); | |
cc36513c | 2598 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
81255565 | 2599 | |
29b9bde6 DV |
2600 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2601 | ||
2602 | return 0; | |
81255565 JB |
2603 | } |
2604 | ||
96a02917 VS |
2605 | void intel_display_handle_reset(struct drm_device *dev) |
2606 | { | |
2607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2608 | struct drm_crtc *crtc; | |
2609 | ||
2610 | /* | |
2611 | * Flips in the rings have been nuked by the reset, | |
2612 | * so complete all pending flips so that user space | |
2613 | * will get its events and not get stuck. | |
2614 | * | |
2615 | * Also update the base address of all primary | |
2616 | * planes to the the last fb to make sure we're | |
2617 | * showing the correct fb after a reset. | |
2618 | * | |
2619 | * Need to make two loops over the crtcs so that we | |
2620 | * don't try to grab a crtc mutex before the | |
2621 | * pending_flip_queue really got woken up. | |
2622 | */ | |
2623 | ||
70e1e0ec | 2624 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2626 | enum plane plane = intel_crtc->plane; | |
2627 | ||
2628 | intel_prepare_page_flip(dev, plane); | |
2629 | intel_finish_page_flip_plane(dev, plane); | |
2630 | } | |
2631 | ||
70e1e0ec | 2632 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2634 | ||
51fd371b | 2635 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2636 | /* |
2637 | * FIXME: Once we have proper support for primary planes (and | |
2638 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2639 | * a NULL crtc->primary->fb. |
947fdaad | 2640 | */ |
f4510a27 | 2641 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2642 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2643 | crtc->primary->fb, |
262ca2b0 MR |
2644 | crtc->x, |
2645 | crtc->y); | |
51fd371b | 2646 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2647 | } |
2648 | } | |
2649 | ||
14667a4b CW |
2650 | static int |
2651 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2652 | { | |
2653 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2654 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2655 | bool was_interruptible = dev_priv->mm.interruptible; | |
2656 | int ret; | |
2657 | ||
14667a4b CW |
2658 | /* Big Hammer, we also need to ensure that any pending |
2659 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2660 | * current scanout is retired before unpinning the old | |
2661 | * framebuffer. | |
2662 | * | |
2663 | * This should only fail upon a hung GPU, in which case we | |
2664 | * can safely continue. | |
2665 | */ | |
2666 | dev_priv->mm.interruptible = false; | |
2667 | ret = i915_gem_object_finish_gpu(obj); | |
2668 | dev_priv->mm.interruptible = was_interruptible; | |
2669 | ||
2670 | return ret; | |
2671 | } | |
2672 | ||
7d5e3799 CW |
2673 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2674 | { | |
2675 | struct drm_device *dev = crtc->dev; | |
2676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2678 | unsigned long flags; | |
2679 | bool pending; | |
2680 | ||
2681 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2682 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2683 | return false; | |
2684 | ||
2685 | spin_lock_irqsave(&dev->event_lock, flags); | |
2686 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2687 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2688 | ||
2689 | return pending; | |
2690 | } | |
2691 | ||
5c3b82e2 | 2692 | static int |
3c4fdcfb | 2693 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2694 | struct drm_framebuffer *fb) |
79e53945 JB |
2695 | { |
2696 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2697 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2698 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2699 | enum pipe pipe = intel_crtc->pipe; |
94352cf9 | 2700 | struct drm_framebuffer *old_fb; |
a071fa00 | 2701 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
91565c85 | 2702 | struct drm_i915_gem_object *old_obj; |
5c3b82e2 | 2703 | int ret; |
79e53945 | 2704 | |
7d5e3799 CW |
2705 | if (intel_crtc_has_pending_flip(crtc)) { |
2706 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2707 | return -EBUSY; | |
2708 | } | |
2709 | ||
79e53945 | 2710 | /* no fb bound */ |
94352cf9 | 2711 | if (!fb) { |
a5071c2f | 2712 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2713 | return 0; |
2714 | } | |
2715 | ||
7eb552ae | 2716 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2717 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2718 | plane_name(intel_crtc->plane), | |
2719 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2720 | return -EINVAL; |
79e53945 JB |
2721 | } |
2722 | ||
a071fa00 | 2723 | old_fb = crtc->primary->fb; |
91565c85 | 2724 | old_obj = old_fb ? to_intel_framebuffer(old_fb)->obj : NULL; |
a071fa00 | 2725 | |
5c3b82e2 | 2726 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
2727 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
2728 | if (ret == 0) | |
91565c85 | 2729 | i915_gem_track_fb(old_obj, obj, |
a071fa00 | 2730 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2731 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2732 | if (ret != 0) { |
a5071c2f | 2733 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2734 | return ret; |
2735 | } | |
79e53945 | 2736 | |
bb2043de DL |
2737 | /* |
2738 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2739 | * that in compute_mode_changes we check the native mode (not the pfit | |
2740 | * mode) to see if we can flip rather than do a full mode set. In the | |
2741 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2742 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2743 | * sized surface. | |
2744 | * | |
2745 | * To fix this properly, we need to hoist the checks up into | |
2746 | * compute_mode_changes (or above), check the actual pfit state and | |
2747 | * whether the platform allows pfit disable with pipe active, and only | |
2748 | * then update the pipesrc and pfit state, even on the flip path. | |
2749 | */ | |
d330a953 | 2750 | if (i915.fastboot) { |
d7bf63f2 DL |
2751 | const struct drm_display_mode *adjusted_mode = |
2752 | &intel_crtc->config.adjusted_mode; | |
2753 | ||
4d6a3e63 | 2754 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2755 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2756 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2757 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2758 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2759 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2760 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2761 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2762 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2763 | } | |
0637d60d JB |
2764 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2765 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2766 | } |
2767 | ||
29b9bde6 | 2768 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2769 | |
f99d7069 DV |
2770 | if (intel_crtc->active) |
2771 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2772 | ||
f4510a27 | 2773 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2774 | crtc->x = x; |
2775 | crtc->y = y; | |
94352cf9 | 2776 | |
b7f1de28 | 2777 | if (old_fb) { |
d7697eea DV |
2778 | if (intel_crtc->active && old_fb != fb) |
2779 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2780 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2781 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2782 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2783 | } |
652c393a | 2784 | |
8ac36ec1 | 2785 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2786 | intel_update_fbc(dev); |
5c3b82e2 | 2787 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2788 | |
5c3b82e2 | 2789 | return 0; |
79e53945 JB |
2790 | } |
2791 | ||
5e84e1a4 ZW |
2792 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2793 | { | |
2794 | struct drm_device *dev = crtc->dev; | |
2795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2797 | int pipe = intel_crtc->pipe; | |
2798 | u32 reg, temp; | |
2799 | ||
2800 | /* enable normal train */ | |
2801 | reg = FDI_TX_CTL(pipe); | |
2802 | temp = I915_READ(reg); | |
61e499bf | 2803 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2804 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2805 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2806 | } else { |
2807 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2808 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2809 | } |
5e84e1a4 ZW |
2810 | I915_WRITE(reg, temp); |
2811 | ||
2812 | reg = FDI_RX_CTL(pipe); | |
2813 | temp = I915_READ(reg); | |
2814 | if (HAS_PCH_CPT(dev)) { | |
2815 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2816 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2817 | } else { | |
2818 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2819 | temp |= FDI_LINK_TRAIN_NONE; | |
2820 | } | |
2821 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2822 | ||
2823 | /* wait one idle pattern time */ | |
2824 | POSTING_READ(reg); | |
2825 | udelay(1000); | |
357555c0 JB |
2826 | |
2827 | /* IVB wants error correction enabled */ | |
2828 | if (IS_IVYBRIDGE(dev)) | |
2829 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2830 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2831 | } |
2832 | ||
1fbc0d78 | 2833 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2834 | { |
1fbc0d78 DV |
2835 | return crtc->base.enabled && crtc->active && |
2836 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2837 | } |
2838 | ||
01a415fd DV |
2839 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2840 | { | |
2841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2842 | struct intel_crtc *pipe_B_crtc = | |
2843 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2844 | struct intel_crtc *pipe_C_crtc = | |
2845 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2846 | uint32_t temp; | |
2847 | ||
1e833f40 DV |
2848 | /* |
2849 | * When everything is off disable fdi C so that we could enable fdi B | |
2850 | * with all lanes. Note that we don't care about enabled pipes without | |
2851 | * an enabled pch encoder. | |
2852 | */ | |
2853 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2854 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2855 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2856 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2857 | ||
2858 | temp = I915_READ(SOUTH_CHICKEN1); | |
2859 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2860 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2861 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2862 | } | |
2863 | } | |
2864 | ||
8db9d77b ZW |
2865 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2866 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2867 | { | |
2868 | struct drm_device *dev = crtc->dev; | |
2869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2871 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2872 | u32 reg, temp, tries; |
8db9d77b | 2873 | |
1c8562f6 | 2874 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2875 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2876 | |
e1a44743 AJ |
2877 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2878 | for train result */ | |
5eddb70b CW |
2879 | reg = FDI_RX_IMR(pipe); |
2880 | temp = I915_READ(reg); | |
e1a44743 AJ |
2881 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2882 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2883 | I915_WRITE(reg, temp); |
2884 | I915_READ(reg); | |
e1a44743 AJ |
2885 | udelay(150); |
2886 | ||
8db9d77b | 2887 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2888 | reg = FDI_TX_CTL(pipe); |
2889 | temp = I915_READ(reg); | |
627eb5a3 DV |
2890 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2891 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2892 | temp &= ~FDI_LINK_TRAIN_NONE; |
2893 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2894 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2895 | |
5eddb70b CW |
2896 | reg = FDI_RX_CTL(pipe); |
2897 | temp = I915_READ(reg); | |
8db9d77b ZW |
2898 | temp &= ~FDI_LINK_TRAIN_NONE; |
2899 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2900 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2901 | ||
2902 | POSTING_READ(reg); | |
8db9d77b ZW |
2903 | udelay(150); |
2904 | ||
5b2adf89 | 2905 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2906 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2907 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2908 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2909 | |
5eddb70b | 2910 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2911 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2912 | temp = I915_READ(reg); |
8db9d77b ZW |
2913 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2914 | ||
2915 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2916 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2917 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2918 | break; |
2919 | } | |
8db9d77b | 2920 | } |
e1a44743 | 2921 | if (tries == 5) |
5eddb70b | 2922 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2923 | |
2924 | /* Train 2 */ | |
5eddb70b CW |
2925 | reg = FDI_TX_CTL(pipe); |
2926 | temp = I915_READ(reg); | |
8db9d77b ZW |
2927 | temp &= ~FDI_LINK_TRAIN_NONE; |
2928 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2929 | I915_WRITE(reg, temp); |
8db9d77b | 2930 | |
5eddb70b CW |
2931 | reg = FDI_RX_CTL(pipe); |
2932 | temp = I915_READ(reg); | |
8db9d77b ZW |
2933 | temp &= ~FDI_LINK_TRAIN_NONE; |
2934 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2935 | I915_WRITE(reg, temp); |
8db9d77b | 2936 | |
5eddb70b CW |
2937 | POSTING_READ(reg); |
2938 | udelay(150); | |
8db9d77b | 2939 | |
5eddb70b | 2940 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2941 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2942 | temp = I915_READ(reg); |
8db9d77b ZW |
2943 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2944 | ||
2945 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2946 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2947 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2948 | break; | |
2949 | } | |
8db9d77b | 2950 | } |
e1a44743 | 2951 | if (tries == 5) |
5eddb70b | 2952 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2953 | |
2954 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2955 | |
8db9d77b ZW |
2956 | } |
2957 | ||
0206e353 | 2958 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2959 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2960 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2961 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2962 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2963 | }; | |
2964 | ||
2965 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2966 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2967 | { | |
2968 | struct drm_device *dev = crtc->dev; | |
2969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2971 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2972 | u32 reg, temp, i, retry; |
8db9d77b | 2973 | |
e1a44743 AJ |
2974 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2975 | for train result */ | |
5eddb70b CW |
2976 | reg = FDI_RX_IMR(pipe); |
2977 | temp = I915_READ(reg); | |
e1a44743 AJ |
2978 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2979 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2980 | I915_WRITE(reg, temp); |
2981 | ||
2982 | POSTING_READ(reg); | |
e1a44743 AJ |
2983 | udelay(150); |
2984 | ||
8db9d77b | 2985 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2986 | reg = FDI_TX_CTL(pipe); |
2987 | temp = I915_READ(reg); | |
627eb5a3 DV |
2988 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2989 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2990 | temp &= ~FDI_LINK_TRAIN_NONE; |
2991 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2992 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2993 | /* SNB-B */ | |
2994 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2995 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2996 | |
d74cf324 DV |
2997 | I915_WRITE(FDI_RX_MISC(pipe), |
2998 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2999 | ||
5eddb70b CW |
3000 | reg = FDI_RX_CTL(pipe); |
3001 | temp = I915_READ(reg); | |
8db9d77b ZW |
3002 | if (HAS_PCH_CPT(dev)) { |
3003 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3004 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3005 | } else { | |
3006 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3007 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3008 | } | |
5eddb70b CW |
3009 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3010 | ||
3011 | POSTING_READ(reg); | |
8db9d77b ZW |
3012 | udelay(150); |
3013 | ||
0206e353 | 3014 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3015 | reg = FDI_TX_CTL(pipe); |
3016 | temp = I915_READ(reg); | |
8db9d77b ZW |
3017 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3018 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3019 | I915_WRITE(reg, temp); |
3020 | ||
3021 | POSTING_READ(reg); | |
8db9d77b ZW |
3022 | udelay(500); |
3023 | ||
fa37d39e SP |
3024 | for (retry = 0; retry < 5; retry++) { |
3025 | reg = FDI_RX_IIR(pipe); | |
3026 | temp = I915_READ(reg); | |
3027 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3028 | if (temp & FDI_RX_BIT_LOCK) { | |
3029 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3030 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3031 | break; | |
3032 | } | |
3033 | udelay(50); | |
8db9d77b | 3034 | } |
fa37d39e SP |
3035 | if (retry < 5) |
3036 | break; | |
8db9d77b ZW |
3037 | } |
3038 | if (i == 4) | |
5eddb70b | 3039 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3040 | |
3041 | /* Train 2 */ | |
5eddb70b CW |
3042 | reg = FDI_TX_CTL(pipe); |
3043 | temp = I915_READ(reg); | |
8db9d77b ZW |
3044 | temp &= ~FDI_LINK_TRAIN_NONE; |
3045 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3046 | if (IS_GEN6(dev)) { | |
3047 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3048 | /* SNB-B */ | |
3049 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3050 | } | |
5eddb70b | 3051 | I915_WRITE(reg, temp); |
8db9d77b | 3052 | |
5eddb70b CW |
3053 | reg = FDI_RX_CTL(pipe); |
3054 | temp = I915_READ(reg); | |
8db9d77b ZW |
3055 | if (HAS_PCH_CPT(dev)) { |
3056 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3057 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3058 | } else { | |
3059 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3060 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3061 | } | |
5eddb70b CW |
3062 | I915_WRITE(reg, temp); |
3063 | ||
3064 | POSTING_READ(reg); | |
8db9d77b ZW |
3065 | udelay(150); |
3066 | ||
0206e353 | 3067 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3068 | reg = FDI_TX_CTL(pipe); |
3069 | temp = I915_READ(reg); | |
8db9d77b ZW |
3070 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3071 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3072 | I915_WRITE(reg, temp); |
3073 | ||
3074 | POSTING_READ(reg); | |
8db9d77b ZW |
3075 | udelay(500); |
3076 | ||
fa37d39e SP |
3077 | for (retry = 0; retry < 5; retry++) { |
3078 | reg = FDI_RX_IIR(pipe); | |
3079 | temp = I915_READ(reg); | |
3080 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3081 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3082 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3083 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3084 | break; | |
3085 | } | |
3086 | udelay(50); | |
8db9d77b | 3087 | } |
fa37d39e SP |
3088 | if (retry < 5) |
3089 | break; | |
8db9d77b ZW |
3090 | } |
3091 | if (i == 4) | |
5eddb70b | 3092 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3093 | |
3094 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3095 | } | |
3096 | ||
357555c0 JB |
3097 | /* Manual link training for Ivy Bridge A0 parts */ |
3098 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3099 | { | |
3100 | struct drm_device *dev = crtc->dev; | |
3101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3103 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3104 | u32 reg, temp, i, j; |
357555c0 JB |
3105 | |
3106 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3107 | for train result */ | |
3108 | reg = FDI_RX_IMR(pipe); | |
3109 | temp = I915_READ(reg); | |
3110 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3111 | temp &= ~FDI_RX_BIT_LOCK; | |
3112 | I915_WRITE(reg, temp); | |
3113 | ||
3114 | POSTING_READ(reg); | |
3115 | udelay(150); | |
3116 | ||
01a415fd DV |
3117 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3118 | I915_READ(FDI_RX_IIR(pipe))); | |
3119 | ||
139ccd3f JB |
3120 | /* Try each vswing and preemphasis setting twice before moving on */ |
3121 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3122 | /* disable first in case we need to retry */ | |
3123 | reg = FDI_TX_CTL(pipe); | |
3124 | temp = I915_READ(reg); | |
3125 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3126 | temp &= ~FDI_TX_ENABLE; | |
3127 | I915_WRITE(reg, temp); | |
357555c0 | 3128 | |
139ccd3f JB |
3129 | reg = FDI_RX_CTL(pipe); |
3130 | temp = I915_READ(reg); | |
3131 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3132 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3133 | temp &= ~FDI_RX_ENABLE; | |
3134 | I915_WRITE(reg, temp); | |
357555c0 | 3135 | |
139ccd3f | 3136 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3137 | reg = FDI_TX_CTL(pipe); |
3138 | temp = I915_READ(reg); | |
139ccd3f JB |
3139 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3140 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3141 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3142 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3143 | temp |= snb_b_fdi_train_param[j/2]; |
3144 | temp |= FDI_COMPOSITE_SYNC; | |
3145 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3146 | |
139ccd3f JB |
3147 | I915_WRITE(FDI_RX_MISC(pipe), |
3148 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3149 | |
139ccd3f | 3150 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3151 | temp = I915_READ(reg); |
139ccd3f JB |
3152 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3153 | temp |= FDI_COMPOSITE_SYNC; | |
3154 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3155 | |
139ccd3f JB |
3156 | POSTING_READ(reg); |
3157 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3158 | |
139ccd3f JB |
3159 | for (i = 0; i < 4; i++) { |
3160 | reg = FDI_RX_IIR(pipe); | |
3161 | temp = I915_READ(reg); | |
3162 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3163 | |
139ccd3f JB |
3164 | if (temp & FDI_RX_BIT_LOCK || |
3165 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3166 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3167 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3168 | i); | |
3169 | break; | |
3170 | } | |
3171 | udelay(1); /* should be 0.5us */ | |
3172 | } | |
3173 | if (i == 4) { | |
3174 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3175 | continue; | |
3176 | } | |
357555c0 | 3177 | |
139ccd3f | 3178 | /* Train 2 */ |
357555c0 JB |
3179 | reg = FDI_TX_CTL(pipe); |
3180 | temp = I915_READ(reg); | |
139ccd3f JB |
3181 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3182 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3183 | I915_WRITE(reg, temp); | |
3184 | ||
3185 | reg = FDI_RX_CTL(pipe); | |
3186 | temp = I915_READ(reg); | |
3187 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3188 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3189 | I915_WRITE(reg, temp); |
3190 | ||
3191 | POSTING_READ(reg); | |
139ccd3f | 3192 | udelay(2); /* should be 1.5us */ |
357555c0 | 3193 | |
139ccd3f JB |
3194 | for (i = 0; i < 4; i++) { |
3195 | reg = FDI_RX_IIR(pipe); | |
3196 | temp = I915_READ(reg); | |
3197 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3198 | |
139ccd3f JB |
3199 | if (temp & FDI_RX_SYMBOL_LOCK || |
3200 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3201 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3202 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3203 | i); | |
3204 | goto train_done; | |
3205 | } | |
3206 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3207 | } |
139ccd3f JB |
3208 | if (i == 4) |
3209 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3210 | } |
357555c0 | 3211 | |
139ccd3f | 3212 | train_done: |
357555c0 JB |
3213 | DRM_DEBUG_KMS("FDI train done.\n"); |
3214 | } | |
3215 | ||
88cefb6c | 3216 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3217 | { |
88cefb6c | 3218 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3219 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3220 | int pipe = intel_crtc->pipe; |
5eddb70b | 3221 | u32 reg, temp; |
79e53945 | 3222 | |
c64e311e | 3223 | |
c98e9dcf | 3224 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3225 | reg = FDI_RX_CTL(pipe); |
3226 | temp = I915_READ(reg); | |
627eb5a3 DV |
3227 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3228 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3229 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3230 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3231 | ||
3232 | POSTING_READ(reg); | |
c98e9dcf JB |
3233 | udelay(200); |
3234 | ||
3235 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3236 | temp = I915_READ(reg); |
3237 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3238 | ||
3239 | POSTING_READ(reg); | |
c98e9dcf JB |
3240 | udelay(200); |
3241 | ||
20749730 PZ |
3242 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3243 | reg = FDI_TX_CTL(pipe); | |
3244 | temp = I915_READ(reg); | |
3245 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3246 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3247 | |
20749730 PZ |
3248 | POSTING_READ(reg); |
3249 | udelay(100); | |
6be4a607 | 3250 | } |
0e23b99d JB |
3251 | } |
3252 | ||
88cefb6c DV |
3253 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3254 | { | |
3255 | struct drm_device *dev = intel_crtc->base.dev; | |
3256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3257 | int pipe = intel_crtc->pipe; | |
3258 | u32 reg, temp; | |
3259 | ||
3260 | /* Switch from PCDclk to Rawclk */ | |
3261 | reg = FDI_RX_CTL(pipe); | |
3262 | temp = I915_READ(reg); | |
3263 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3264 | ||
3265 | /* Disable CPU FDI TX PLL */ | |
3266 | reg = FDI_TX_CTL(pipe); | |
3267 | temp = I915_READ(reg); | |
3268 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3269 | ||
3270 | POSTING_READ(reg); | |
3271 | udelay(100); | |
3272 | ||
3273 | reg = FDI_RX_CTL(pipe); | |
3274 | temp = I915_READ(reg); | |
3275 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3276 | ||
3277 | /* Wait for the clocks to turn off. */ | |
3278 | POSTING_READ(reg); | |
3279 | udelay(100); | |
3280 | } | |
3281 | ||
0fc932b8 JB |
3282 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3283 | { | |
3284 | struct drm_device *dev = crtc->dev; | |
3285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3286 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3287 | int pipe = intel_crtc->pipe; | |
3288 | u32 reg, temp; | |
3289 | ||
3290 | /* disable CPU FDI tx and PCH FDI rx */ | |
3291 | reg = FDI_TX_CTL(pipe); | |
3292 | temp = I915_READ(reg); | |
3293 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3294 | POSTING_READ(reg); | |
3295 | ||
3296 | reg = FDI_RX_CTL(pipe); | |
3297 | temp = I915_READ(reg); | |
3298 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3299 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3300 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3301 | ||
3302 | POSTING_READ(reg); | |
3303 | udelay(100); | |
3304 | ||
3305 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3306 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3307 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3308 | |
3309 | /* still set train pattern 1 */ | |
3310 | reg = FDI_TX_CTL(pipe); | |
3311 | temp = I915_READ(reg); | |
3312 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3313 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3314 | I915_WRITE(reg, temp); | |
3315 | ||
3316 | reg = FDI_RX_CTL(pipe); | |
3317 | temp = I915_READ(reg); | |
3318 | if (HAS_PCH_CPT(dev)) { | |
3319 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3320 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3321 | } else { | |
3322 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3323 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3324 | } | |
3325 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3326 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3327 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3328 | I915_WRITE(reg, temp); |
3329 | ||
3330 | POSTING_READ(reg); | |
3331 | udelay(100); | |
3332 | } | |
3333 | ||
5dce5b93 CW |
3334 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3335 | { | |
3336 | struct intel_crtc *crtc; | |
3337 | ||
3338 | /* Note that we don't need to be called with mode_config.lock here | |
3339 | * as our list of CRTC objects is static for the lifetime of the | |
3340 | * device and so cannot disappear as we iterate. Similarly, we can | |
3341 | * happily treat the predicates as racy, atomic checks as userspace | |
3342 | * cannot claim and pin a new fb without at least acquring the | |
3343 | * struct_mutex and so serialising with us. | |
3344 | */ | |
d3fcc808 | 3345 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3346 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3347 | continue; | |
3348 | ||
3349 | if (crtc->unpin_work) | |
3350 | intel_wait_for_vblank(dev, crtc->pipe); | |
3351 | ||
3352 | return true; | |
3353 | } | |
3354 | ||
3355 | return false; | |
3356 | } | |
3357 | ||
46a55d30 | 3358 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3359 | { |
0f91128d | 3360 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3361 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3362 | |
f4510a27 | 3363 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3364 | return; |
3365 | ||
2c10d571 DV |
3366 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3367 | ||
eed6d67d DV |
3368 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3369 | !intel_crtc_has_pending_flip(crtc), | |
3370 | 60*HZ) == 0); | |
5bb61643 | 3371 | |
0f91128d | 3372 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3373 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3374 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3375 | } |
3376 | ||
e615efe4 ED |
3377 | /* Program iCLKIP clock to the desired frequency */ |
3378 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3379 | { | |
3380 | struct drm_device *dev = crtc->dev; | |
3381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3382 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3383 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3384 | u32 temp; | |
3385 | ||
09153000 DV |
3386 | mutex_lock(&dev_priv->dpio_lock); |
3387 | ||
e615efe4 ED |
3388 | /* It is necessary to ungate the pixclk gate prior to programming |
3389 | * the divisors, and gate it back when it is done. | |
3390 | */ | |
3391 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3392 | ||
3393 | /* Disable SSCCTL */ | |
3394 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3395 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3396 | SBI_SSCCTL_DISABLE, | |
3397 | SBI_ICLK); | |
e615efe4 ED |
3398 | |
3399 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3400 | if (clock == 20000) { |
e615efe4 ED |
3401 | auxdiv = 1; |
3402 | divsel = 0x41; | |
3403 | phaseinc = 0x20; | |
3404 | } else { | |
3405 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3406 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3407 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3408 | * convert the virtual clock precision to KHz here for higher |
3409 | * precision. | |
3410 | */ | |
3411 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3412 | u32 iclk_pi_range = 64; | |
3413 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3414 | ||
12d7ceed | 3415 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3416 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3417 | pi_value = desired_divisor % iclk_pi_range; | |
3418 | ||
3419 | auxdiv = 0; | |
3420 | divsel = msb_divisor_value - 2; | |
3421 | phaseinc = pi_value; | |
3422 | } | |
3423 | ||
3424 | /* This should not happen with any sane values */ | |
3425 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3426 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3427 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3428 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3429 | ||
3430 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3431 | clock, |
e615efe4 ED |
3432 | auxdiv, |
3433 | divsel, | |
3434 | phasedir, | |
3435 | phaseinc); | |
3436 | ||
3437 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3438 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3439 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3440 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3441 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3442 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3443 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3444 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3445 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3446 | |
3447 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3448 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3449 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3450 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3451 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3452 | |
3453 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3454 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3455 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3456 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3457 | |
3458 | /* Wait for initialization time */ | |
3459 | udelay(24); | |
3460 | ||
3461 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3462 | |
3463 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3464 | } |
3465 | ||
275f01b2 DV |
3466 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3467 | enum pipe pch_transcoder) | |
3468 | { | |
3469 | struct drm_device *dev = crtc->base.dev; | |
3470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3471 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3472 | ||
3473 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3474 | I915_READ(HTOTAL(cpu_transcoder))); | |
3475 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3476 | I915_READ(HBLANK(cpu_transcoder))); | |
3477 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3478 | I915_READ(HSYNC(cpu_transcoder))); | |
3479 | ||
3480 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3481 | I915_READ(VTOTAL(cpu_transcoder))); | |
3482 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3483 | I915_READ(VBLANK(cpu_transcoder))); | |
3484 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3485 | I915_READ(VSYNC(cpu_transcoder))); | |
3486 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3487 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3488 | } | |
3489 | ||
1fbc0d78 DV |
3490 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3491 | { | |
3492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3493 | uint32_t temp; | |
3494 | ||
3495 | temp = I915_READ(SOUTH_CHICKEN1); | |
3496 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3497 | return; | |
3498 | ||
3499 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3500 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3501 | ||
3502 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3503 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3504 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3505 | POSTING_READ(SOUTH_CHICKEN1); | |
3506 | } | |
3507 | ||
3508 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3509 | { | |
3510 | struct drm_device *dev = intel_crtc->base.dev; | |
3511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3512 | ||
3513 | switch (intel_crtc->pipe) { | |
3514 | case PIPE_A: | |
3515 | break; | |
3516 | case PIPE_B: | |
3517 | if (intel_crtc->config.fdi_lanes > 2) | |
3518 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3519 | else | |
3520 | cpt_enable_fdi_bc_bifurcation(dev); | |
3521 | ||
3522 | break; | |
3523 | case PIPE_C: | |
3524 | cpt_enable_fdi_bc_bifurcation(dev); | |
3525 | ||
3526 | break; | |
3527 | default: | |
3528 | BUG(); | |
3529 | } | |
3530 | } | |
3531 | ||
f67a559d JB |
3532 | /* |
3533 | * Enable PCH resources required for PCH ports: | |
3534 | * - PCH PLLs | |
3535 | * - FDI training & RX/TX | |
3536 | * - update transcoder timings | |
3537 | * - DP transcoding bits | |
3538 | * - transcoder | |
3539 | */ | |
3540 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3541 | { |
3542 | struct drm_device *dev = crtc->dev; | |
3543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3544 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3545 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3546 | u32 reg, temp; |
2c07245f | 3547 | |
ab9412ba | 3548 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3549 | |
1fbc0d78 DV |
3550 | if (IS_IVYBRIDGE(dev)) |
3551 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3552 | ||
cd986abb DV |
3553 | /* Write the TU size bits before fdi link training, so that error |
3554 | * detection works. */ | |
3555 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3556 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3557 | ||
c98e9dcf | 3558 | /* For PCH output, training FDI link */ |
674cf967 | 3559 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3560 | |
3ad8a208 DV |
3561 | /* We need to program the right clock selection before writing the pixel |
3562 | * mutliplier into the DPLL. */ | |
303b81e0 | 3563 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3564 | u32 sel; |
4b645f14 | 3565 | |
c98e9dcf | 3566 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3567 | temp |= TRANS_DPLL_ENABLE(pipe); |
3568 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3569 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3570 | temp |= sel; |
3571 | else | |
3572 | temp &= ~sel; | |
c98e9dcf | 3573 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3574 | } |
5eddb70b | 3575 | |
3ad8a208 DV |
3576 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3577 | * transcoder, and we actually should do this to not upset any PCH | |
3578 | * transcoder that already use the clock when we share it. | |
3579 | * | |
3580 | * Note that enable_shared_dpll tries to do the right thing, but | |
3581 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3582 | * the right LVDS enable sequence. */ | |
85b3894f | 3583 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3584 | |
d9b6cb56 JB |
3585 | /* set transcoder timing, panel must allow it */ |
3586 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3587 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3588 | |
303b81e0 | 3589 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3590 | |
c98e9dcf JB |
3591 | /* For PCH DP, enable TRANS_DP_CTL */ |
3592 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3593 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3594 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3595 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3596 | reg = TRANS_DP_CTL(pipe); |
3597 | temp = I915_READ(reg); | |
3598 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3599 | TRANS_DP_SYNC_MASK | |
3600 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3601 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3602 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3603 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3604 | |
3605 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3606 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3607 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3608 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3609 | |
3610 | switch (intel_trans_dp_port_sel(crtc)) { | |
3611 | case PCH_DP_B: | |
5eddb70b | 3612 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3613 | break; |
3614 | case PCH_DP_C: | |
5eddb70b | 3615 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3616 | break; |
3617 | case PCH_DP_D: | |
5eddb70b | 3618 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3619 | break; |
3620 | default: | |
e95d41e1 | 3621 | BUG(); |
32f9d658 | 3622 | } |
2c07245f | 3623 | |
5eddb70b | 3624 | I915_WRITE(reg, temp); |
6be4a607 | 3625 | } |
b52eb4dc | 3626 | |
b8a4f404 | 3627 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3628 | } |
3629 | ||
1507e5bd PZ |
3630 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3631 | { | |
3632 | struct drm_device *dev = crtc->dev; | |
3633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3634 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3635 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3636 | |
ab9412ba | 3637 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3638 | |
8c52b5e8 | 3639 | lpt_program_iclkip(crtc); |
1507e5bd | 3640 | |
0540e488 | 3641 | /* Set transcoder timing. */ |
275f01b2 | 3642 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3643 | |
937bb610 | 3644 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3645 | } |
3646 | ||
e2b78267 | 3647 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3648 | { |
e2b78267 | 3649 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3650 | |
3651 | if (pll == NULL) | |
3652 | return; | |
3653 | ||
3654 | if (pll->refcount == 0) { | |
46edb027 | 3655 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3656 | return; |
3657 | } | |
3658 | ||
f4a091c7 DV |
3659 | if (--pll->refcount == 0) { |
3660 | WARN_ON(pll->on); | |
3661 | WARN_ON(pll->active); | |
3662 | } | |
3663 | ||
a43f6e0f | 3664 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3665 | } |
3666 | ||
b89a1d39 | 3667 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3668 | { |
e2b78267 DV |
3669 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3670 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3671 | enum intel_dpll_id i; | |
ee7b9f93 | 3672 | |
ee7b9f93 | 3673 | if (pll) { |
46edb027 DV |
3674 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3675 | crtc->base.base.id, pll->name); | |
e2b78267 | 3676 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3677 | } |
3678 | ||
98b6bd99 DV |
3679 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3680 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3681 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3682 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3683 | |
46edb027 DV |
3684 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3685 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3686 | |
f2a69f44 DV |
3687 | WARN_ON(pll->refcount); |
3688 | ||
98b6bd99 DV |
3689 | goto found; |
3690 | } | |
3691 | ||
e72f9fbf DV |
3692 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3693 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3694 | |
3695 | /* Only want to check enabled timings first */ | |
3696 | if (pll->refcount == 0) | |
3697 | continue; | |
3698 | ||
b89a1d39 DV |
3699 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3700 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3701 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3702 | crtc->base.base.id, |
46edb027 | 3703 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3704 | |
3705 | goto found; | |
3706 | } | |
3707 | } | |
3708 | ||
3709 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3710 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3711 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3712 | if (pll->refcount == 0) { |
46edb027 DV |
3713 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3714 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3715 | goto found; |
3716 | } | |
3717 | } | |
3718 | ||
3719 | return NULL; | |
3720 | ||
3721 | found: | |
f2a69f44 DV |
3722 | if (pll->refcount == 0) |
3723 | pll->hw_state = crtc->config.dpll_hw_state; | |
3724 | ||
a43f6e0f | 3725 | crtc->config.shared_dpll = i; |
46edb027 DV |
3726 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3727 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3728 | |
cdbd2316 | 3729 | pll->refcount++; |
e04c7350 | 3730 | |
ee7b9f93 JB |
3731 | return pll; |
3732 | } | |
3733 | ||
a1520318 | 3734 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3735 | { |
3736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3737 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3738 | u32 temp; |
3739 | ||
3740 | temp = I915_READ(dslreg); | |
3741 | udelay(500); | |
3742 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3743 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3744 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3745 | } |
3746 | } | |
3747 | ||
b074cec8 JB |
3748 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3749 | { | |
3750 | struct drm_device *dev = crtc->base.dev; | |
3751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3752 | int pipe = crtc->pipe; | |
3753 | ||
fd4daa9c | 3754 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3755 | /* Force use of hard-coded filter coefficients |
3756 | * as some pre-programmed values are broken, | |
3757 | * e.g. x201. | |
3758 | */ | |
3759 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3760 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3761 | PF_PIPE_SEL_IVB(pipe)); | |
3762 | else | |
3763 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3764 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3765 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3766 | } |
3767 | } | |
3768 | ||
bb53d4ae VS |
3769 | static void intel_enable_planes(struct drm_crtc *crtc) |
3770 | { | |
3771 | struct drm_device *dev = crtc->dev; | |
3772 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3773 | struct drm_plane *plane; |
bb53d4ae VS |
3774 | struct intel_plane *intel_plane; |
3775 | ||
af2b653b MR |
3776 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3777 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3778 | if (intel_plane->pipe == pipe) |
3779 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3780 | } |
bb53d4ae VS |
3781 | } |
3782 | ||
3783 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3784 | { | |
3785 | struct drm_device *dev = crtc->dev; | |
3786 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3787 | struct drm_plane *plane; |
bb53d4ae VS |
3788 | struct intel_plane *intel_plane; |
3789 | ||
af2b653b MR |
3790 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3791 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3792 | if (intel_plane->pipe == pipe) |
3793 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3794 | } |
bb53d4ae VS |
3795 | } |
3796 | ||
20bc8673 | 3797 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3798 | { |
cea165c3 VS |
3799 | struct drm_device *dev = crtc->base.dev; |
3800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3801 | |
3802 | if (!crtc->config.ips_enabled) | |
3803 | return; | |
3804 | ||
cea165c3 VS |
3805 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3806 | intel_wait_for_vblank(dev, crtc->pipe); | |
3807 | ||
d77e4531 | 3808 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3809 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3810 | mutex_lock(&dev_priv->rps.hw_lock); |
3811 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3812 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3813 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3814 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3815 | * mailbox." Moreover, the mailbox may return a bogus state, |
3816 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3817 | */ |
3818 | } else { | |
3819 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3820 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3821 | * is essentially intel_wait_for_vblank. If we don't have this | |
3822 | * and don't wait for vblanks until the end of crtc_enable, then | |
3823 | * the HW state readout code will complain that the expected | |
3824 | * IPS_CTL value is not the one we read. */ | |
3825 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3826 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3827 | } | |
d77e4531 PZ |
3828 | } |
3829 | ||
20bc8673 | 3830 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3831 | { |
3832 | struct drm_device *dev = crtc->base.dev; | |
3833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3834 | ||
3835 | if (!crtc->config.ips_enabled) | |
3836 | return; | |
3837 | ||
3838 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3839 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3840 | mutex_lock(&dev_priv->rps.hw_lock); |
3841 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3842 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3843 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3844 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3845 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3846 | } else { |
2a114cc1 | 3847 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3848 | POSTING_READ(IPS_CTL); |
3849 | } | |
d77e4531 PZ |
3850 | |
3851 | /* We need to wait for a vblank before we can disable the plane. */ | |
3852 | intel_wait_for_vblank(dev, crtc->pipe); | |
3853 | } | |
3854 | ||
3855 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3856 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3857 | { | |
3858 | struct drm_device *dev = crtc->dev; | |
3859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3861 | enum pipe pipe = intel_crtc->pipe; | |
3862 | int palreg = PALETTE(pipe); | |
3863 | int i; | |
3864 | bool reenable_ips = false; | |
3865 | ||
3866 | /* The clocks have to be on to load the palette. */ | |
3867 | if (!crtc->enabled || !intel_crtc->active) | |
3868 | return; | |
3869 | ||
3870 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3871 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3872 | assert_dsi_pll_enabled(dev_priv); | |
3873 | else | |
3874 | assert_pll_enabled(dev_priv, pipe); | |
3875 | } | |
3876 | ||
3877 | /* use legacy palette for Ironlake */ | |
3878 | if (HAS_PCH_SPLIT(dev)) | |
3879 | palreg = LGC_PALETTE(pipe); | |
3880 | ||
3881 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3882 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3883 | */ | |
41e6fc4c | 3884 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3885 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3886 | GAMMA_MODE_MODE_SPLIT)) { | |
3887 | hsw_disable_ips(intel_crtc); | |
3888 | reenable_ips = true; | |
3889 | } | |
3890 | ||
3891 | for (i = 0; i < 256; i++) { | |
3892 | I915_WRITE(palreg + 4 * i, | |
3893 | (intel_crtc->lut_r[i] << 16) | | |
3894 | (intel_crtc->lut_g[i] << 8) | | |
3895 | intel_crtc->lut_b[i]); | |
3896 | } | |
3897 | ||
3898 | if (reenable_ips) | |
3899 | hsw_enable_ips(intel_crtc); | |
3900 | } | |
3901 | ||
d3eedb1a VS |
3902 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3903 | { | |
3904 | if (!enable && intel_crtc->overlay) { | |
3905 | struct drm_device *dev = intel_crtc->base.dev; | |
3906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3907 | ||
3908 | mutex_lock(&dev->struct_mutex); | |
3909 | dev_priv->mm.interruptible = false; | |
3910 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3911 | dev_priv->mm.interruptible = true; | |
3912 | mutex_unlock(&dev->struct_mutex); | |
3913 | } | |
3914 | ||
3915 | /* Let userspace switch the overlay on again. In most cases userspace | |
3916 | * has to recompute where to put it anyway. | |
3917 | */ | |
3918 | } | |
3919 | ||
3920 | /** | |
3921 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3922 | * cursor plane briefly if not already running after enabling the display | |
3923 | * plane. | |
3924 | * This workaround avoids occasional blank screens when self refresh is | |
3925 | * enabled. | |
3926 | */ | |
3927 | static void | |
3928 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3929 | { | |
3930 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3931 | ||
3932 | if ((cntl & CURSOR_MODE) == 0) { | |
3933 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3934 | ||
3935 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3936 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3937 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3938 | I915_WRITE(CURCNTR(pipe), cntl); | |
3939 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3940 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3941 | } | |
3942 | } | |
3943 | ||
3944 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
a5c4d7bc VS |
3945 | { |
3946 | struct drm_device *dev = crtc->dev; | |
3947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3949 | int pipe = intel_crtc->pipe; | |
3950 | int plane = intel_crtc->plane; | |
3951 | ||
f98551ae VS |
3952 | drm_vblank_on(dev, pipe); |
3953 | ||
a5c4d7bc VS |
3954 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3955 | intel_enable_planes(crtc); | |
d3eedb1a VS |
3956 | /* The fixup needs to happen before cursor is enabled */ |
3957 | if (IS_G4X(dev)) | |
3958 | g4x_fixup_plane(dev_priv, pipe); | |
a5c4d7bc | 3959 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 3960 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3961 | |
3962 | hsw_enable_ips(intel_crtc); | |
3963 | ||
3964 | mutex_lock(&dev->struct_mutex); | |
3965 | intel_update_fbc(dev); | |
3966 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
3967 | |
3968 | /* | |
3969 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3970 | * to compute the mask of flip planes precisely. For the time being | |
3971 | * consider this a flip from a NULL plane. | |
3972 | */ | |
3973 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
3974 | } |
3975 | ||
d3eedb1a | 3976 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3977 | { |
3978 | struct drm_device *dev = crtc->dev; | |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3980 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3981 | int pipe = intel_crtc->pipe; | |
3982 | int plane = intel_crtc->plane; | |
3983 | ||
3984 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3985 | |
3986 | if (dev_priv->fbc.plane == plane) | |
3987 | intel_disable_fbc(dev); | |
3988 | ||
3989 | hsw_disable_ips(intel_crtc); | |
3990 | ||
d3eedb1a | 3991 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3992 | intel_crtc_update_cursor(crtc, false); |
3993 | intel_disable_planes(crtc); | |
3994 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
f98551ae | 3995 | |
f99d7069 DV |
3996 | /* |
3997 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
3998 | * to compute the mask of flip planes precisely. For the time being | |
3999 | * consider this a flip to a NULL plane. | |
4000 | */ | |
4001 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
4002 | ||
f98551ae | 4003 | drm_vblank_off(dev, pipe); |
a5c4d7bc VS |
4004 | } |
4005 | ||
f67a559d JB |
4006 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4007 | { | |
4008 | struct drm_device *dev = crtc->dev; | |
4009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4011 | struct intel_encoder *encoder; |
f67a559d | 4012 | int pipe = intel_crtc->pipe; |
29407aab | 4013 | enum plane plane = intel_crtc->plane; |
f67a559d | 4014 | |
08a48469 DV |
4015 | WARN_ON(!crtc->enabled); |
4016 | ||
f67a559d JB |
4017 | if (intel_crtc->active) |
4018 | return; | |
4019 | ||
b14b1055 DV |
4020 | if (intel_crtc->config.has_pch_encoder) |
4021 | intel_prepare_shared_dpll(intel_crtc); | |
4022 | ||
29407aab DV |
4023 | if (intel_crtc->config.has_dp_encoder) |
4024 | intel_dp_set_m_n(intel_crtc); | |
4025 | ||
4026 | intel_set_pipe_timings(intel_crtc); | |
4027 | ||
4028 | if (intel_crtc->config.has_pch_encoder) { | |
4029 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4030 | &intel_crtc->config.fdi_m_n); | |
4031 | } | |
4032 | ||
4033 | ironlake_set_pipeconf(crtc); | |
4034 | ||
4035 | /* Set up the display plane register */ | |
4036 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
4037 | POSTING_READ(DSPCNTR(plane)); | |
4038 | ||
4039 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4040 | crtc->x, crtc->y); | |
4041 | ||
f67a559d | 4042 | intel_crtc->active = true; |
8664281b PZ |
4043 | |
4044 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4045 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
4046 | ||
f6736a1a | 4047 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4048 | if (encoder->pre_enable) |
4049 | encoder->pre_enable(encoder); | |
f67a559d | 4050 | |
5bfe2ac0 | 4051 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4052 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4053 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4054 | * enabling. */ | |
88cefb6c | 4055 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4056 | } else { |
4057 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4058 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4059 | } | |
f67a559d | 4060 | |
b074cec8 | 4061 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4062 | |
9c54c0dd JB |
4063 | /* |
4064 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4065 | * clocks enabled | |
4066 | */ | |
4067 | intel_crtc_load_lut(crtc); | |
4068 | ||
f37fcc2a | 4069 | intel_update_watermarks(crtc); |
e1fdc473 | 4070 | intel_enable_pipe(intel_crtc); |
f67a559d | 4071 | |
5bfe2ac0 | 4072 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4073 | ironlake_pch_enable(crtc); |
c98e9dcf | 4074 | |
fa5c73b1 DV |
4075 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4076 | encoder->enable(encoder); | |
61b77ddd DV |
4077 | |
4078 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4079 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4080 | |
d3eedb1a | 4081 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4082 | } |
4083 | ||
42db64ef PZ |
4084 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4085 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4086 | { | |
f5adf94e | 4087 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4088 | } |
4089 | ||
e4916946 PZ |
4090 | /* |
4091 | * This implements the workaround described in the "notes" section of the mode | |
4092 | * set sequence documentation. When going from no pipes or single pipe to | |
4093 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4094 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4095 | */ | |
4096 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4097 | { | |
4098 | struct drm_device *dev = crtc->base.dev; | |
4099 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4100 | ||
4101 | /* We want to get the other_active_crtc only if there's only 1 other | |
4102 | * active crtc. */ | |
d3fcc808 | 4103 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4104 | if (!crtc_it->active || crtc_it == crtc) |
4105 | continue; | |
4106 | ||
4107 | if (other_active_crtc) | |
4108 | return; | |
4109 | ||
4110 | other_active_crtc = crtc_it; | |
4111 | } | |
4112 | if (!other_active_crtc) | |
4113 | return; | |
4114 | ||
4115 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4116 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4117 | } | |
4118 | ||
4f771f10 PZ |
4119 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4120 | { | |
4121 | struct drm_device *dev = crtc->dev; | |
4122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4123 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4124 | struct intel_encoder *encoder; | |
4125 | int pipe = intel_crtc->pipe; | |
229fca97 | 4126 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4127 | |
4128 | WARN_ON(!crtc->enabled); | |
4129 | ||
4130 | if (intel_crtc->active) | |
4131 | return; | |
4132 | ||
229fca97 DV |
4133 | if (intel_crtc->config.has_dp_encoder) |
4134 | intel_dp_set_m_n(intel_crtc); | |
4135 | ||
4136 | intel_set_pipe_timings(intel_crtc); | |
4137 | ||
4138 | if (intel_crtc->config.has_pch_encoder) { | |
4139 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4140 | &intel_crtc->config.fdi_m_n); | |
4141 | } | |
4142 | ||
4143 | haswell_set_pipeconf(crtc); | |
4144 | ||
4145 | intel_set_pipe_csc(crtc); | |
4146 | ||
4147 | /* Set up the display plane register */ | |
4148 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4149 | POSTING_READ(DSPCNTR(plane)); | |
4150 | ||
4151 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4152 | crtc->x, crtc->y); | |
4153 | ||
4f771f10 | 4154 | intel_crtc->active = true; |
8664281b PZ |
4155 | |
4156 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4157 | if (intel_crtc->config.has_pch_encoder) | |
4158 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4159 | ||
5bfe2ac0 | 4160 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4161 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4162 | |
4163 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4164 | if (encoder->pre_enable) | |
4165 | encoder->pre_enable(encoder); | |
4166 | ||
1f544388 | 4167 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4168 | |
b074cec8 | 4169 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4170 | |
4171 | /* | |
4172 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4173 | * clocks enabled | |
4174 | */ | |
4175 | intel_crtc_load_lut(crtc); | |
4176 | ||
1f544388 | 4177 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4178 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4179 | |
f37fcc2a | 4180 | intel_update_watermarks(crtc); |
e1fdc473 | 4181 | intel_enable_pipe(intel_crtc); |
42db64ef | 4182 | |
5bfe2ac0 | 4183 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4184 | lpt_pch_enable(crtc); |
4f771f10 | 4185 | |
8807e55b | 4186 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4187 | encoder->enable(encoder); |
8807e55b JN |
4188 | intel_opregion_notify_encoder(encoder, true); |
4189 | } | |
4f771f10 | 4190 | |
e4916946 PZ |
4191 | /* If we change the relative order between pipe/planes enabling, we need |
4192 | * to change the workaround. */ | |
4193 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4194 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4195 | } |
4196 | ||
3f8dce3a DV |
4197 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4198 | { | |
4199 | struct drm_device *dev = crtc->base.dev; | |
4200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4201 | int pipe = crtc->pipe; | |
4202 | ||
4203 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4204 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4205 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4206 | I915_WRITE(PF_CTL(pipe), 0); |
4207 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4208 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4209 | } | |
4210 | } | |
4211 | ||
6be4a607 JB |
4212 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4213 | { | |
4214 | struct drm_device *dev = crtc->dev; | |
4215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4217 | struct intel_encoder *encoder; |
6be4a607 | 4218 | int pipe = intel_crtc->pipe; |
5eddb70b | 4219 | u32 reg, temp; |
b52eb4dc | 4220 | |
f7abfe8b CW |
4221 | if (!intel_crtc->active) |
4222 | return; | |
4223 | ||
d3eedb1a | 4224 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4225 | |
ea9d758d DV |
4226 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4227 | encoder->disable(encoder); | |
4228 | ||
d925c59a DV |
4229 | if (intel_crtc->config.has_pch_encoder) |
4230 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4231 | ||
b24e7179 | 4232 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4233 | |
3f8dce3a | 4234 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4235 | |
bf49ec8c DV |
4236 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4237 | if (encoder->post_disable) | |
4238 | encoder->post_disable(encoder); | |
2c07245f | 4239 | |
d925c59a DV |
4240 | if (intel_crtc->config.has_pch_encoder) { |
4241 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4242 | |
d925c59a DV |
4243 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4244 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4245 | |
d925c59a DV |
4246 | if (HAS_PCH_CPT(dev)) { |
4247 | /* disable TRANS_DP_CTL */ | |
4248 | reg = TRANS_DP_CTL(pipe); | |
4249 | temp = I915_READ(reg); | |
4250 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4251 | TRANS_DP_PORT_SEL_MASK); | |
4252 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4253 | I915_WRITE(reg, temp); | |
4254 | ||
4255 | /* disable DPLL_SEL */ | |
4256 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4257 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4258 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4259 | } |
e3421a18 | 4260 | |
d925c59a | 4261 | /* disable PCH DPLL */ |
e72f9fbf | 4262 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4263 | |
d925c59a DV |
4264 | ironlake_fdi_pll_disable(intel_crtc); |
4265 | } | |
6b383a7f | 4266 | |
f7abfe8b | 4267 | intel_crtc->active = false; |
46ba614c | 4268 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4269 | |
4270 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4271 | intel_update_fbc(dev); |
d1ebd816 | 4272 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4273 | } |
1b3c7a47 | 4274 | |
4f771f10 | 4275 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4276 | { |
4f771f10 PZ |
4277 | struct drm_device *dev = crtc->dev; |
4278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4280 | struct intel_encoder *encoder; |
4281 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4282 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4283 | |
4f771f10 PZ |
4284 | if (!intel_crtc->active) |
4285 | return; | |
4286 | ||
d3eedb1a | 4287 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4288 | |
8807e55b JN |
4289 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4290 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4291 | encoder->disable(encoder); |
8807e55b | 4292 | } |
4f771f10 | 4293 | |
8664281b PZ |
4294 | if (intel_crtc->config.has_pch_encoder) |
4295 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4296 | intel_disable_pipe(dev_priv, pipe); |
4297 | ||
ad80a810 | 4298 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4299 | |
3f8dce3a | 4300 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4301 | |
1f544388 | 4302 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4303 | |
4304 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4305 | if (encoder->post_disable) | |
4306 | encoder->post_disable(encoder); | |
4307 | ||
88adfff1 | 4308 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4309 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4310 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4311 | intel_ddi_fdi_disable(crtc); |
83616634 | 4312 | } |
4f771f10 PZ |
4313 | |
4314 | intel_crtc->active = false; | |
46ba614c | 4315 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4316 | |
4317 | mutex_lock(&dev->struct_mutex); | |
4318 | intel_update_fbc(dev); | |
4319 | mutex_unlock(&dev->struct_mutex); | |
4320 | } | |
4321 | ||
ee7b9f93 JB |
4322 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4323 | { | |
4324 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4325 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4326 | } |
4327 | ||
6441ab5f PZ |
4328 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4329 | { | |
4330 | intel_ddi_put_crtc_pll(crtc); | |
4331 | } | |
4332 | ||
2dd24552 JB |
4333 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4334 | { | |
4335 | struct drm_device *dev = crtc->base.dev; | |
4336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4337 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4338 | ||
328d8e82 | 4339 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4340 | return; |
4341 | ||
2dd24552 | 4342 | /* |
c0b03411 DV |
4343 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4344 | * according to register description and PRM. | |
2dd24552 | 4345 | */ |
c0b03411 DV |
4346 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4347 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4348 | |
b074cec8 JB |
4349 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4350 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4351 | |
4352 | /* Border color in case we don't scale up to the full screen. Black by | |
4353 | * default, change to something else for debugging. */ | |
4354 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4355 | } |
4356 | ||
77d22dca ID |
4357 | #define for_each_power_domain(domain, mask) \ |
4358 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4359 | if ((1 << (domain)) & (mask)) | |
4360 | ||
319be8ae ID |
4361 | enum intel_display_power_domain |
4362 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4363 | { | |
4364 | struct drm_device *dev = intel_encoder->base.dev; | |
4365 | struct intel_digital_port *intel_dig_port; | |
4366 | ||
4367 | switch (intel_encoder->type) { | |
4368 | case INTEL_OUTPUT_UNKNOWN: | |
4369 | /* Only DDI platforms should ever use this output type */ | |
4370 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4371 | case INTEL_OUTPUT_DISPLAYPORT: | |
4372 | case INTEL_OUTPUT_HDMI: | |
4373 | case INTEL_OUTPUT_EDP: | |
4374 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4375 | switch (intel_dig_port->port) { | |
4376 | case PORT_A: | |
4377 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4378 | case PORT_B: | |
4379 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4380 | case PORT_C: | |
4381 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4382 | case PORT_D: | |
4383 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4384 | default: | |
4385 | WARN_ON_ONCE(1); | |
4386 | return POWER_DOMAIN_PORT_OTHER; | |
4387 | } | |
4388 | case INTEL_OUTPUT_ANALOG: | |
4389 | return POWER_DOMAIN_PORT_CRT; | |
4390 | case INTEL_OUTPUT_DSI: | |
4391 | return POWER_DOMAIN_PORT_DSI; | |
4392 | default: | |
4393 | return POWER_DOMAIN_PORT_OTHER; | |
4394 | } | |
4395 | } | |
4396 | ||
4397 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4398 | { |
319be8ae ID |
4399 | struct drm_device *dev = crtc->dev; |
4400 | struct intel_encoder *intel_encoder; | |
4401 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4402 | enum pipe pipe = intel_crtc->pipe; | |
4403 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4404 | unsigned long mask; |
4405 | enum transcoder transcoder; | |
4406 | ||
4407 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4408 | ||
4409 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4410 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4411 | if (pfit_enabled) | |
4412 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4413 | ||
319be8ae ID |
4414 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4415 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4416 | ||
77d22dca ID |
4417 | return mask; |
4418 | } | |
4419 | ||
4420 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4421 | bool enable) | |
4422 | { | |
4423 | if (dev_priv->power_domains.init_power_on == enable) | |
4424 | return; | |
4425 | ||
4426 | if (enable) | |
4427 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4428 | else | |
4429 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4430 | ||
4431 | dev_priv->power_domains.init_power_on = enable; | |
4432 | } | |
4433 | ||
4434 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4435 | { | |
4436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4437 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4438 | struct intel_crtc *crtc; | |
4439 | ||
4440 | /* | |
4441 | * First get all needed power domains, then put all unneeded, to avoid | |
4442 | * any unnecessary toggling of the power wells. | |
4443 | */ | |
d3fcc808 | 4444 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4445 | enum intel_display_power_domain domain; |
4446 | ||
4447 | if (!crtc->base.enabled) | |
4448 | continue; | |
4449 | ||
319be8ae | 4450 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4451 | |
4452 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4453 | intel_display_power_get(dev_priv, domain); | |
4454 | } | |
4455 | ||
d3fcc808 | 4456 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4457 | enum intel_display_power_domain domain; |
4458 | ||
4459 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4460 | intel_display_power_put(dev_priv, domain); | |
4461 | ||
4462 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4463 | } | |
4464 | ||
4465 | intel_display_set_init_power(dev_priv, false); | |
4466 | } | |
4467 | ||
dfcab17e | 4468 | /* returns HPLL frequency in kHz */ |
586f49dc | 4469 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4470 | { |
586f49dc | 4471 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4472 | |
586f49dc JB |
4473 | /* Obtain SKU information */ |
4474 | mutex_lock(&dev_priv->dpio_lock); | |
4475 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4476 | CCK_FUSE_HPLL_FREQ_MASK; | |
4477 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4478 | |
dfcab17e | 4479 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4480 | } |
4481 | ||
4482 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4483 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4484 | { | |
4485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4486 | u32 val, cmd; | |
4487 | ||
d60c4473 ID |
4488 | WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); |
4489 | dev_priv->vlv_cdclk_freq = cdclk; | |
4490 | ||
dfcab17e | 4491 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4492 | cmd = 2; |
dfcab17e | 4493 | else if (cdclk == 266667) |
30a970c6 JB |
4494 | cmd = 1; |
4495 | else | |
4496 | cmd = 0; | |
4497 | ||
4498 | mutex_lock(&dev_priv->rps.hw_lock); | |
4499 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4500 | val &= ~DSPFREQGUAR_MASK; | |
4501 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4502 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4503 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4504 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4505 | 50)) { | |
4506 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4507 | } | |
4508 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4509 | ||
dfcab17e | 4510 | if (cdclk == 400000) { |
30a970c6 JB |
4511 | u32 divider, vco; |
4512 | ||
4513 | vco = valleyview_get_vco(dev_priv); | |
dfcab17e | 4514 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
30a970c6 JB |
4515 | |
4516 | mutex_lock(&dev_priv->dpio_lock); | |
4517 | /* adjust cdclk divider */ | |
4518 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4519 | val &= ~0xf; | |
4520 | val |= divider; | |
4521 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4522 | mutex_unlock(&dev_priv->dpio_lock); | |
4523 | } | |
4524 | ||
4525 | mutex_lock(&dev_priv->dpio_lock); | |
4526 | /* adjust self-refresh exit latency value */ | |
4527 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4528 | val &= ~0x7f; | |
4529 | ||
4530 | /* | |
4531 | * For high bandwidth configs, we set a higher latency in the bunit | |
4532 | * so that the core display fetch happens in time to avoid underruns. | |
4533 | */ | |
dfcab17e | 4534 | if (cdclk == 400000) |
30a970c6 JB |
4535 | val |= 4500 / 250; /* 4.5 usec */ |
4536 | else | |
4537 | val |= 3000 / 250; /* 3.0 usec */ | |
4538 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4539 | mutex_unlock(&dev_priv->dpio_lock); | |
4540 | ||
4541 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4542 | intel_i2c_reset(dev); | |
4543 | } | |
4544 | ||
d60c4473 | 4545 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
30a970c6 JB |
4546 | { |
4547 | int cur_cdclk, vco; | |
4548 | int divider; | |
4549 | ||
4550 | vco = valleyview_get_vco(dev_priv); | |
4551 | ||
4552 | mutex_lock(&dev_priv->dpio_lock); | |
4553 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4554 | mutex_unlock(&dev_priv->dpio_lock); | |
4555 | ||
4556 | divider &= 0xf; | |
4557 | ||
dfcab17e | 4558 | cur_cdclk = DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
30a970c6 JB |
4559 | |
4560 | return cur_cdclk; | |
4561 | } | |
4562 | ||
4563 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4564 | int max_pixclk) | |
4565 | { | |
30a970c6 JB |
4566 | /* |
4567 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4568 | * 200MHz | |
4569 | * 267MHz | |
4570 | * 320MHz | |
4571 | * 400MHz | |
4572 | * So we check to see whether we're above 90% of the lower bin and | |
4573 | * adjust if needed. | |
4574 | */ | |
dfcab17e VS |
4575 | if (max_pixclk > 320000*9/10) |
4576 | return 400000; | |
4577 | else if (max_pixclk > 266667*9/10) | |
4578 | return 320000; | |
4579 | else | |
4580 | return 266667; | |
30a970c6 JB |
4581 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ |
4582 | } | |
4583 | ||
2f2d7aa1 VS |
4584 | /* compute the max pixel clock for new configuration */ |
4585 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4586 | { |
4587 | struct drm_device *dev = dev_priv->dev; | |
4588 | struct intel_crtc *intel_crtc; | |
4589 | int max_pixclk = 0; | |
4590 | ||
d3fcc808 | 4591 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4592 | if (intel_crtc->new_enabled) |
30a970c6 | 4593 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4594 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4595 | } |
4596 | ||
4597 | return max_pixclk; | |
4598 | } | |
4599 | ||
4600 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4601 | unsigned *prepare_pipes) |
30a970c6 JB |
4602 | { |
4603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4604 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4605 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4606 | |
d60c4473 ID |
4607 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4608 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4609 | return; |
4610 | ||
2f2d7aa1 | 4611 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4612 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4613 | if (intel_crtc->base.enabled) |
4614 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4615 | } | |
4616 | ||
4617 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4618 | { | |
4619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4620 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4621 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4622 | ||
d60c4473 | 4623 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4624 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4625 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4626 | } |
4627 | ||
89b667f8 JB |
4628 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4629 | { | |
4630 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4631 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4633 | struct intel_encoder *encoder; | |
4634 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4635 | int plane = intel_crtc->plane; |
23538ef1 | 4636 | bool is_dsi; |
5b18e57c | 4637 | u32 dspcntr; |
89b667f8 JB |
4638 | |
4639 | WARN_ON(!crtc->enabled); | |
4640 | ||
4641 | if (intel_crtc->active) | |
4642 | return; | |
4643 | ||
8525a235 SK |
4644 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4645 | ||
4646 | if (!is_dsi && !IS_CHERRYVIEW(dev)) | |
4647 | vlv_prepare_pll(intel_crtc); | |
bdd4b6a6 | 4648 | |
5b18e57c DV |
4649 | /* Set up the display plane register */ |
4650 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4651 | ||
4652 | if (intel_crtc->config.has_dp_encoder) | |
4653 | intel_dp_set_m_n(intel_crtc); | |
4654 | ||
4655 | intel_set_pipe_timings(intel_crtc); | |
4656 | ||
4657 | /* pipesrc and dspsize control the size that is scaled from, | |
4658 | * which should always be the user's requested size. | |
4659 | */ | |
4660 | I915_WRITE(DSPSIZE(plane), | |
4661 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4662 | (intel_crtc->config.pipe_src_w - 1)); | |
4663 | I915_WRITE(DSPPOS(plane), 0); | |
4664 | ||
4665 | i9xx_set_pipeconf(intel_crtc); | |
4666 | ||
4667 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4668 | POSTING_READ(DSPCNTR(plane)); | |
4669 | ||
4670 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4671 | crtc->x, crtc->y); | |
4672 | ||
89b667f8 | 4673 | intel_crtc->active = true; |
89b667f8 | 4674 | |
4a3436e8 VS |
4675 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4676 | ||
89b667f8 JB |
4677 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4678 | if (encoder->pre_pll_enable) | |
4679 | encoder->pre_pll_enable(encoder); | |
4680 | ||
9d556c99 CML |
4681 | if (!is_dsi) { |
4682 | if (IS_CHERRYVIEW(dev)) | |
4683 | chv_enable_pll(intel_crtc); | |
4684 | else | |
4685 | vlv_enable_pll(intel_crtc); | |
4686 | } | |
89b667f8 JB |
4687 | |
4688 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4689 | if (encoder->pre_enable) | |
4690 | encoder->pre_enable(encoder); | |
4691 | ||
2dd24552 JB |
4692 | i9xx_pfit_enable(intel_crtc); |
4693 | ||
63cbb074 VS |
4694 | intel_crtc_load_lut(crtc); |
4695 | ||
f37fcc2a | 4696 | intel_update_watermarks(crtc); |
e1fdc473 | 4697 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4698 | |
5004945f JN |
4699 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4700 | encoder->enable(encoder); | |
9ab0460b VS |
4701 | |
4702 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4703 | |
56b80e1f VS |
4704 | /* Underruns don't raise interrupts, so check manually. */ |
4705 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4706 | } |
4707 | ||
f13c2ef3 DV |
4708 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4709 | { | |
4710 | struct drm_device *dev = crtc->base.dev; | |
4711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4712 | ||
4713 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4714 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4715 | } | |
4716 | ||
0b8765c6 | 4717 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4718 | { |
4719 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4720 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4721 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4722 | struct intel_encoder *encoder; |
79e53945 | 4723 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4724 | int plane = intel_crtc->plane; |
4725 | u32 dspcntr; | |
79e53945 | 4726 | |
08a48469 DV |
4727 | WARN_ON(!crtc->enabled); |
4728 | ||
f7abfe8b CW |
4729 | if (intel_crtc->active) |
4730 | return; | |
4731 | ||
f13c2ef3 DV |
4732 | i9xx_set_pll_dividers(intel_crtc); |
4733 | ||
5b18e57c DV |
4734 | /* Set up the display plane register */ |
4735 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4736 | ||
4737 | if (pipe == 0) | |
4738 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4739 | else | |
4740 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4741 | ||
4742 | if (intel_crtc->config.has_dp_encoder) | |
4743 | intel_dp_set_m_n(intel_crtc); | |
4744 | ||
4745 | intel_set_pipe_timings(intel_crtc); | |
4746 | ||
4747 | /* pipesrc and dspsize control the size that is scaled from, | |
4748 | * which should always be the user's requested size. | |
4749 | */ | |
4750 | I915_WRITE(DSPSIZE(plane), | |
4751 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4752 | (intel_crtc->config.pipe_src_w - 1)); | |
4753 | I915_WRITE(DSPPOS(plane), 0); | |
4754 | ||
4755 | i9xx_set_pipeconf(intel_crtc); | |
4756 | ||
4757 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4758 | POSTING_READ(DSPCNTR(plane)); | |
4759 | ||
4760 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4761 | crtc->x, crtc->y); | |
4762 | ||
f7abfe8b | 4763 | intel_crtc->active = true; |
6b383a7f | 4764 | |
4a3436e8 VS |
4765 | if (!IS_GEN2(dev)) |
4766 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4767 | ||
9d6d9f19 MK |
4768 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4769 | if (encoder->pre_enable) | |
4770 | encoder->pre_enable(encoder); | |
4771 | ||
f6736a1a DV |
4772 | i9xx_enable_pll(intel_crtc); |
4773 | ||
2dd24552 JB |
4774 | i9xx_pfit_enable(intel_crtc); |
4775 | ||
63cbb074 VS |
4776 | intel_crtc_load_lut(crtc); |
4777 | ||
f37fcc2a | 4778 | intel_update_watermarks(crtc); |
e1fdc473 | 4779 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4780 | |
fa5c73b1 DV |
4781 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4782 | encoder->enable(encoder); | |
9ab0460b VS |
4783 | |
4784 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4785 | |
4a3436e8 VS |
4786 | /* |
4787 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4788 | * So don't enable underrun reporting before at least some planes | |
4789 | * are enabled. | |
4790 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4791 | * but leave the pipe running. | |
4792 | */ | |
4793 | if (IS_GEN2(dev)) | |
4794 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4795 | ||
56b80e1f VS |
4796 | /* Underruns don't raise interrupts, so check manually. */ |
4797 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4798 | } |
79e53945 | 4799 | |
87476d63 DV |
4800 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4801 | { | |
4802 | struct drm_device *dev = crtc->base.dev; | |
4803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4804 | |
328d8e82 DV |
4805 | if (!crtc->config.gmch_pfit.control) |
4806 | return; | |
87476d63 | 4807 | |
328d8e82 | 4808 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4809 | |
328d8e82 DV |
4810 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4811 | I915_READ(PFIT_CONTROL)); | |
4812 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4813 | } |
4814 | ||
0b8765c6 JB |
4815 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4816 | { | |
4817 | struct drm_device *dev = crtc->dev; | |
4818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4820 | struct intel_encoder *encoder; |
0b8765c6 | 4821 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4822 | |
f7abfe8b CW |
4823 | if (!intel_crtc->active) |
4824 | return; | |
4825 | ||
4a3436e8 VS |
4826 | /* |
4827 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4828 | * So diasble underrun reporting before all the planes get disabled. | |
4829 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4830 | * but leave the pipe running. | |
4831 | */ | |
4832 | if (IS_GEN2(dev)) | |
4833 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4834 | ||
9ab0460b VS |
4835 | intel_crtc_disable_planes(crtc); |
4836 | ||
ea9d758d DV |
4837 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4838 | encoder->disable(encoder); | |
4839 | ||
6304cd91 VS |
4840 | /* |
4841 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4842 | * wait for planes to fully turn off before disabling the pipe. | |
4843 | */ | |
4844 | if (IS_GEN2(dev)) | |
4845 | intel_wait_for_vblank(dev, pipe); | |
4846 | ||
b24e7179 | 4847 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4848 | |
87476d63 | 4849 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4850 | |
89b667f8 JB |
4851 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4852 | if (encoder->post_disable) | |
4853 | encoder->post_disable(encoder); | |
4854 | ||
076ed3b2 CML |
4855 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4856 | if (IS_CHERRYVIEW(dev)) | |
4857 | chv_disable_pll(dev_priv, pipe); | |
4858 | else if (IS_VALLEYVIEW(dev)) | |
4859 | vlv_disable_pll(dev_priv, pipe); | |
4860 | else | |
4861 | i9xx_disable_pll(dev_priv, pipe); | |
4862 | } | |
0b8765c6 | 4863 | |
4a3436e8 VS |
4864 | if (!IS_GEN2(dev)) |
4865 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4866 | ||
f7abfe8b | 4867 | intel_crtc->active = false; |
46ba614c | 4868 | intel_update_watermarks(crtc); |
f37fcc2a | 4869 | |
efa9624e | 4870 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4871 | intel_update_fbc(dev); |
efa9624e | 4872 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4873 | } |
4874 | ||
ee7b9f93 JB |
4875 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4876 | { | |
4877 | } | |
4878 | ||
976f8a20 DV |
4879 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4880 | bool enabled) | |
2c07245f ZW |
4881 | { |
4882 | struct drm_device *dev = crtc->dev; | |
4883 | struct drm_i915_master_private *master_priv; | |
4884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4885 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4886 | |
4887 | if (!dev->primary->master) | |
4888 | return; | |
4889 | ||
4890 | master_priv = dev->primary->master->driver_priv; | |
4891 | if (!master_priv->sarea_priv) | |
4892 | return; | |
4893 | ||
79e53945 JB |
4894 | switch (pipe) { |
4895 | case 0: | |
4896 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4897 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4898 | break; | |
4899 | case 1: | |
4900 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4901 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4902 | break; | |
4903 | default: | |
9db4a9c7 | 4904 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4905 | break; |
4906 | } | |
79e53945 JB |
4907 | } |
4908 | ||
976f8a20 DV |
4909 | /** |
4910 | * Sets the power management mode of the pipe and plane. | |
4911 | */ | |
4912 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4913 | { | |
4914 | struct drm_device *dev = crtc->dev; | |
4915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4916 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
976f8a20 | 4917 | struct intel_encoder *intel_encoder; |
0e572fe7 DV |
4918 | enum intel_display_power_domain domain; |
4919 | unsigned long domains; | |
976f8a20 DV |
4920 | bool enable = false; |
4921 | ||
4922 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4923 | enable |= intel_encoder->connectors_active; | |
4924 | ||
0e572fe7 DV |
4925 | if (enable) { |
4926 | if (!intel_crtc->active) { | |
4927 | /* | |
4928 | * FIXME: DDI plls and relevant code isn't converted | |
4929 | * yet, so do runtime PM for DPMS only for all other | |
4930 | * platforms for now. | |
4931 | */ | |
4932 | if (!HAS_DDI(dev)) { | |
4933 | domains = get_crtc_power_domains(crtc); | |
4934 | for_each_power_domain(domain, domains) | |
4935 | intel_display_power_get(dev_priv, domain); | |
4936 | intel_crtc->enabled_power_domains = domains; | |
4937 | } | |
4938 | ||
4939 | dev_priv->display.crtc_enable(crtc); | |
4940 | } | |
4941 | } else { | |
4942 | if (intel_crtc->active) { | |
4943 | dev_priv->display.crtc_disable(crtc); | |
4944 | ||
4945 | if (!HAS_DDI(dev)) { | |
4946 | domains = intel_crtc->enabled_power_domains; | |
4947 | for_each_power_domain(domain, domains) | |
4948 | intel_display_power_put(dev_priv, domain); | |
4949 | intel_crtc->enabled_power_domains = 0; | |
4950 | } | |
4951 | } | |
4952 | } | |
976f8a20 DV |
4953 | |
4954 | intel_crtc_update_sarea(crtc, enable); | |
4955 | } | |
4956 | ||
cdd59983 CW |
4957 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4958 | { | |
cdd59983 | 4959 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4960 | struct drm_connector *connector; |
ee7b9f93 | 4961 | struct drm_i915_private *dev_priv = dev->dev_private; |
a071fa00 DV |
4962 | struct drm_i915_gem_object *old_obj; |
4963 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
cdd59983 | 4964 | |
976f8a20 DV |
4965 | /* crtc should still be enabled when we disable it. */ |
4966 | WARN_ON(!crtc->enabled); | |
4967 | ||
4968 | dev_priv->display.crtc_disable(crtc); | |
4969 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4970 | dev_priv->display.off(crtc); |
4971 | ||
931872fc | 4972 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
a071fa00 DV |
4973 | assert_cursor_disabled(dev_priv, pipe); |
4974 | assert_pipe_disabled(dev->dev_private, pipe); | |
cdd59983 | 4975 | |
f4510a27 | 4976 | if (crtc->primary->fb) { |
a071fa00 | 4977 | old_obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
cdd59983 | 4978 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
4979 | intel_unpin_fb_obj(old_obj); |
4980 | i915_gem_track_fb(old_obj, NULL, | |
4981 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 4982 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4983 | crtc->primary->fb = NULL; |
976f8a20 DV |
4984 | } |
4985 | ||
4986 | /* Update computed state. */ | |
4987 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4988 | if (!connector->encoder || !connector->encoder->crtc) | |
4989 | continue; | |
4990 | ||
4991 | if (connector->encoder->crtc != crtc) | |
4992 | continue; | |
4993 | ||
4994 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4995 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4996 | } |
4997 | } | |
4998 | ||
ea5b213a | 4999 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5000 | { |
4ef69c7a | 5001 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5002 | |
ea5b213a CW |
5003 | drm_encoder_cleanup(encoder); |
5004 | kfree(intel_encoder); | |
7e7d76c3 JB |
5005 | } |
5006 | ||
9237329d | 5007 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5008 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5009 | * state of the entire output pipe. */ | |
9237329d | 5010 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5011 | { |
5ab432ef DV |
5012 | if (mode == DRM_MODE_DPMS_ON) { |
5013 | encoder->connectors_active = true; | |
5014 | ||
b2cabb0e | 5015 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5016 | } else { |
5017 | encoder->connectors_active = false; | |
5018 | ||
b2cabb0e | 5019 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5020 | } |
79e53945 JB |
5021 | } |
5022 | ||
0a91ca29 DV |
5023 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5024 | * internal consistency). */ | |
b980514c | 5025 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5026 | { |
0a91ca29 DV |
5027 | if (connector->get_hw_state(connector)) { |
5028 | struct intel_encoder *encoder = connector->encoder; | |
5029 | struct drm_crtc *crtc; | |
5030 | bool encoder_enabled; | |
5031 | enum pipe pipe; | |
5032 | ||
5033 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5034 | connector->base.base.id, | |
c23cc417 | 5035 | connector->base.name); |
0a91ca29 DV |
5036 | |
5037 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
5038 | "wrong connector dpms state\n"); | |
5039 | WARN(connector->base.encoder != &encoder->base, | |
5040 | "active connector not linked to encoder\n"); | |
5041 | WARN(!encoder->connectors_active, | |
5042 | "encoder->connectors_active not set\n"); | |
5043 | ||
5044 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5045 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5046 | if (WARN_ON(!encoder->base.crtc)) | |
5047 | return; | |
5048 | ||
5049 | crtc = encoder->base.crtc; | |
5050 | ||
5051 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
5052 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5053 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5054 | "encoder active on the wrong pipe\n"); | |
5055 | } | |
79e53945 JB |
5056 | } |
5057 | ||
5ab432ef DV |
5058 | /* Even simpler default implementation, if there's really no special case to |
5059 | * consider. */ | |
5060 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5061 | { |
5ab432ef DV |
5062 | /* All the simple cases only support two dpms states. */ |
5063 | if (mode != DRM_MODE_DPMS_ON) | |
5064 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5065 | |
5ab432ef DV |
5066 | if (mode == connector->dpms) |
5067 | return; | |
5068 | ||
5069 | connector->dpms = mode; | |
5070 | ||
5071 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5072 | if (connector->encoder) |
5073 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5074 | |
b980514c | 5075 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5076 | } |
5077 | ||
f0947c37 DV |
5078 | /* Simple connector->get_hw_state implementation for encoders that support only |
5079 | * one connector and no cloning and hence the encoder state determines the state | |
5080 | * of the connector. */ | |
5081 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5082 | { |
24929352 | 5083 | enum pipe pipe = 0; |
f0947c37 | 5084 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5085 | |
f0947c37 | 5086 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5087 | } |
5088 | ||
1857e1da DV |
5089 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5090 | struct intel_crtc_config *pipe_config) | |
5091 | { | |
5092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5093 | struct intel_crtc *pipe_B_crtc = | |
5094 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5095 | ||
5096 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5097 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5098 | if (pipe_config->fdi_lanes > 4) { | |
5099 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5100 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5101 | return false; | |
5102 | } | |
5103 | ||
bafb6553 | 5104 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5105 | if (pipe_config->fdi_lanes > 2) { |
5106 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5107 | pipe_config->fdi_lanes); | |
5108 | return false; | |
5109 | } else { | |
5110 | return true; | |
5111 | } | |
5112 | } | |
5113 | ||
5114 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5115 | return true; | |
5116 | ||
5117 | /* Ivybridge 3 pipe is really complicated */ | |
5118 | switch (pipe) { | |
5119 | case PIPE_A: | |
5120 | return true; | |
5121 | case PIPE_B: | |
5122 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5123 | pipe_config->fdi_lanes > 2) { | |
5124 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5125 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5126 | return false; | |
5127 | } | |
5128 | return true; | |
5129 | case PIPE_C: | |
1e833f40 | 5130 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5131 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5132 | if (pipe_config->fdi_lanes > 2) { | |
5133 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5134 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5135 | return false; | |
5136 | } | |
5137 | } else { | |
5138 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5139 | return false; | |
5140 | } | |
5141 | return true; | |
5142 | default: | |
5143 | BUG(); | |
5144 | } | |
5145 | } | |
5146 | ||
e29c22c0 DV |
5147 | #define RETRY 1 |
5148 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5149 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5150 | { |
1857e1da | 5151 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5152 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5153 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5154 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5155 | |
e29c22c0 | 5156 | retry: |
877d48d5 DV |
5157 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5158 | * each output octet as 10 bits. The actual frequency | |
5159 | * is stored as a divider into a 100MHz clock, and the | |
5160 | * mode pixel clock is stored in units of 1KHz. | |
5161 | * Hence the bw of each lane in terms of the mode signal | |
5162 | * is: | |
5163 | */ | |
5164 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5165 | ||
241bfc38 | 5166 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5167 | |
2bd89a07 | 5168 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5169 | pipe_config->pipe_bpp); |
5170 | ||
5171 | pipe_config->fdi_lanes = lane; | |
5172 | ||
2bd89a07 | 5173 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5174 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5175 | |
e29c22c0 DV |
5176 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5177 | intel_crtc->pipe, pipe_config); | |
5178 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5179 | pipe_config->pipe_bpp -= 2*3; | |
5180 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5181 | pipe_config->pipe_bpp); | |
5182 | needs_recompute = true; | |
5183 | pipe_config->bw_constrained = true; | |
5184 | ||
5185 | goto retry; | |
5186 | } | |
5187 | ||
5188 | if (needs_recompute) | |
5189 | return RETRY; | |
5190 | ||
5191 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5192 | } |
5193 | ||
42db64ef PZ |
5194 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5195 | struct intel_crtc_config *pipe_config) | |
5196 | { | |
d330a953 | 5197 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5198 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5199 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5200 | } |
5201 | ||
a43f6e0f | 5202 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5203 | struct intel_crtc_config *pipe_config) |
79e53945 | 5204 | { |
a43f6e0f | 5205 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5206 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5207 | |
ad3a4479 | 5208 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5209 | if (INTEL_INFO(dev)->gen < 4) { |
5210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5211 | int clock_limit = | |
5212 | dev_priv->display.get_display_clock_speed(dev); | |
5213 | ||
5214 | /* | |
5215 | * Enable pixel doubling when the dot clock | |
5216 | * is > 90% of the (display) core speed. | |
5217 | * | |
b397c96b VS |
5218 | * GDG double wide on either pipe, |
5219 | * otherwise pipe A only. | |
cf532bb2 | 5220 | */ |
b397c96b | 5221 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5222 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5223 | clock_limit *= 2; |
cf532bb2 | 5224 | pipe_config->double_wide = true; |
ad3a4479 VS |
5225 | } |
5226 | ||
241bfc38 | 5227 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5228 | return -EINVAL; |
2c07245f | 5229 | } |
89749350 | 5230 | |
1d1d0e27 VS |
5231 | /* |
5232 | * Pipe horizontal size must be even in: | |
5233 | * - DVO ganged mode | |
5234 | * - LVDS dual channel mode | |
5235 | * - Double wide pipe | |
5236 | */ | |
5237 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5238 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5239 | pipe_config->pipe_src_w &= ~1; | |
5240 | ||
8693a824 DL |
5241 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5242 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5243 | */ |
5244 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5245 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5246 | return -EINVAL; |
44f46b42 | 5247 | |
bd080ee5 | 5248 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5249 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5250 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5251 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5252 | * for lvds. */ | |
5253 | pipe_config->pipe_bpp = 8*3; | |
5254 | } | |
5255 | ||
f5adf94e | 5256 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5257 | hsw_compute_ips_config(crtc, pipe_config); |
5258 | ||
5259 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
5260 | * clock survives for now. */ | |
5261 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5262 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 5263 | |
877d48d5 | 5264 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5265 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5266 | |
e29c22c0 | 5267 | return 0; |
79e53945 JB |
5268 | } |
5269 | ||
25eb05fc JB |
5270 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5271 | { | |
5272 | return 400000; /* FIXME */ | |
5273 | } | |
5274 | ||
e70236a8 JB |
5275 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5276 | { | |
5277 | return 400000; | |
5278 | } | |
79e53945 | 5279 | |
e70236a8 | 5280 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5281 | { |
e70236a8 JB |
5282 | return 333000; |
5283 | } | |
79e53945 | 5284 | |
e70236a8 JB |
5285 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5286 | { | |
5287 | return 200000; | |
5288 | } | |
79e53945 | 5289 | |
257a7ffc DV |
5290 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5291 | { | |
5292 | u16 gcfgc = 0; | |
5293 | ||
5294 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5295 | ||
5296 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5297 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5298 | return 267000; | |
5299 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5300 | return 333000; | |
5301 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5302 | return 444000; | |
5303 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5304 | return 200000; | |
5305 | default: | |
5306 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5307 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5308 | return 133000; | |
5309 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5310 | return 167000; | |
5311 | } | |
5312 | } | |
5313 | ||
e70236a8 JB |
5314 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5315 | { | |
5316 | u16 gcfgc = 0; | |
79e53945 | 5317 | |
e70236a8 JB |
5318 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5319 | ||
5320 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5321 | return 133000; | |
5322 | else { | |
5323 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5324 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5325 | return 333000; | |
5326 | default: | |
5327 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5328 | return 190000; | |
79e53945 | 5329 | } |
e70236a8 JB |
5330 | } |
5331 | } | |
5332 | ||
5333 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5334 | { | |
5335 | return 266000; | |
5336 | } | |
5337 | ||
5338 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5339 | { | |
5340 | u16 hpllcc = 0; | |
5341 | /* Assume that the hardware is in the high speed state. This | |
5342 | * should be the default. | |
5343 | */ | |
5344 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5345 | case GC_CLOCK_133_200: | |
5346 | case GC_CLOCK_100_200: | |
5347 | return 200000; | |
5348 | case GC_CLOCK_166_250: | |
5349 | return 250000; | |
5350 | case GC_CLOCK_100_133: | |
79e53945 | 5351 | return 133000; |
e70236a8 | 5352 | } |
79e53945 | 5353 | |
e70236a8 JB |
5354 | /* Shouldn't happen */ |
5355 | return 0; | |
5356 | } | |
79e53945 | 5357 | |
e70236a8 JB |
5358 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5359 | { | |
5360 | return 133000; | |
79e53945 JB |
5361 | } |
5362 | ||
2c07245f | 5363 | static void |
a65851af | 5364 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5365 | { |
a65851af VS |
5366 | while (*num > DATA_LINK_M_N_MASK || |
5367 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5368 | *num >>= 1; |
5369 | *den >>= 1; | |
5370 | } | |
5371 | } | |
5372 | ||
a65851af VS |
5373 | static void compute_m_n(unsigned int m, unsigned int n, |
5374 | uint32_t *ret_m, uint32_t *ret_n) | |
5375 | { | |
5376 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5377 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5378 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5379 | } | |
5380 | ||
e69d0bc1 DV |
5381 | void |
5382 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5383 | int pixel_clock, int link_clock, | |
5384 | struct intel_link_m_n *m_n) | |
2c07245f | 5385 | { |
e69d0bc1 | 5386 | m_n->tu = 64; |
a65851af VS |
5387 | |
5388 | compute_m_n(bits_per_pixel * pixel_clock, | |
5389 | link_clock * nlanes * 8, | |
5390 | &m_n->gmch_m, &m_n->gmch_n); | |
5391 | ||
5392 | compute_m_n(pixel_clock, link_clock, | |
5393 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5394 | } |
5395 | ||
a7615030 CW |
5396 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5397 | { | |
d330a953 JN |
5398 | if (i915.panel_use_ssc >= 0) |
5399 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5400 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5401 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5402 | } |
5403 | ||
c65d77d8 JB |
5404 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5405 | { | |
5406 | struct drm_device *dev = crtc->dev; | |
5407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5408 | int refclk; | |
5409 | ||
a0c4da24 | 5410 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5411 | refclk = 100000; |
a0c4da24 | 5412 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5413 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5414 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5415 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5416 | } else if (!IS_GEN2(dev)) { |
5417 | refclk = 96000; | |
5418 | } else { | |
5419 | refclk = 48000; | |
5420 | } | |
5421 | ||
5422 | return refclk; | |
5423 | } | |
5424 | ||
7429e9d4 | 5425 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5426 | { |
7df00d7a | 5427 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5428 | } |
f47709a9 | 5429 | |
7429e9d4 DV |
5430 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5431 | { | |
5432 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5433 | } |
5434 | ||
f47709a9 | 5435 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5436 | intel_clock_t *reduced_clock) |
5437 | { | |
f47709a9 | 5438 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5439 | u32 fp, fp2 = 0; |
5440 | ||
5441 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5442 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5443 | if (reduced_clock) |
7429e9d4 | 5444 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5445 | } else { |
7429e9d4 | 5446 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5447 | if (reduced_clock) |
7429e9d4 | 5448 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5449 | } |
5450 | ||
8bcc2795 | 5451 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5452 | |
f47709a9 DV |
5453 | crtc->lowfreq_avail = false; |
5454 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5455 | reduced_clock && i915.powersave) { |
8bcc2795 | 5456 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5457 | crtc->lowfreq_avail = true; |
a7516a05 | 5458 | } else { |
8bcc2795 | 5459 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5460 | } |
5461 | } | |
5462 | ||
5e69f97f CML |
5463 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5464 | pipe) | |
89b667f8 JB |
5465 | { |
5466 | u32 reg_val; | |
5467 | ||
5468 | /* | |
5469 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5470 | * and set it to a reasonable value instead. | |
5471 | */ | |
ab3c759a | 5472 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5473 | reg_val &= 0xffffff00; |
5474 | reg_val |= 0x00000030; | |
ab3c759a | 5475 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5476 | |
ab3c759a | 5477 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5478 | reg_val &= 0x8cffffff; |
5479 | reg_val = 0x8c000000; | |
ab3c759a | 5480 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5481 | |
ab3c759a | 5482 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5483 | reg_val &= 0xffffff00; |
ab3c759a | 5484 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5485 | |
ab3c759a | 5486 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5487 | reg_val &= 0x00ffffff; |
5488 | reg_val |= 0xb0000000; | |
ab3c759a | 5489 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5490 | } |
5491 | ||
b551842d DV |
5492 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5493 | struct intel_link_m_n *m_n) | |
5494 | { | |
5495 | struct drm_device *dev = crtc->base.dev; | |
5496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5497 | int pipe = crtc->pipe; | |
5498 | ||
e3b95f1e DV |
5499 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5500 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5501 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5502 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5503 | } |
5504 | ||
5505 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5506 | struct intel_link_m_n *m_n) | |
5507 | { | |
5508 | struct drm_device *dev = crtc->base.dev; | |
5509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5510 | int pipe = crtc->pipe; | |
5511 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5512 | ||
5513 | if (INTEL_INFO(dev)->gen >= 5) { | |
5514 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5515 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5516 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5517 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5518 | } else { | |
e3b95f1e DV |
5519 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5520 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5521 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5522 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5523 | } |
5524 | } | |
5525 | ||
03afc4a2 DV |
5526 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5527 | { | |
5528 | if (crtc->config.has_pch_encoder) | |
5529 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5530 | else | |
5531 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5532 | } | |
5533 | ||
f47709a9 | 5534 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5535 | { |
5536 | u32 dpll, dpll_md; | |
5537 | ||
5538 | /* | |
5539 | * Enable DPIO clock input. We should never disable the reference | |
5540 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5541 | * on it. | |
5542 | */ | |
5543 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5544 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5545 | /* We should never disable this, set it here for state tracking */ | |
5546 | if (crtc->pipe == PIPE_B) | |
5547 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5548 | dpll |= DPLL_VCO_ENABLE; | |
5549 | crtc->config.dpll_hw_state.dpll = dpll; | |
5550 | ||
5551 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5552 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5553 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5554 | } | |
5555 | ||
5556 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5557 | { |
f47709a9 | 5558 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5559 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5560 | int pipe = crtc->pipe; |
bdd4b6a6 | 5561 | u32 mdiv; |
a0c4da24 | 5562 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5563 | u32 coreclk, reg_val; |
a0c4da24 | 5564 | |
09153000 DV |
5565 | mutex_lock(&dev_priv->dpio_lock); |
5566 | ||
f47709a9 DV |
5567 | bestn = crtc->config.dpll.n; |
5568 | bestm1 = crtc->config.dpll.m1; | |
5569 | bestm2 = crtc->config.dpll.m2; | |
5570 | bestp1 = crtc->config.dpll.p1; | |
5571 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5572 | |
89b667f8 JB |
5573 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5574 | ||
5575 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5576 | if (pipe == PIPE_B) |
5e69f97f | 5577 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5578 | |
5579 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5580 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5581 | |
5582 | /* Disable target IRef on PLL */ | |
ab3c759a | 5583 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5584 | reg_val &= 0x00ffffff; |
ab3c759a | 5585 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5586 | |
5587 | /* Disable fast lock */ | |
ab3c759a | 5588 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5589 | |
5590 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5591 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5592 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5593 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5594 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5595 | |
5596 | /* | |
5597 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5598 | * but we don't support that). | |
5599 | * Note: don't use the DAC post divider as it seems unstable. | |
5600 | */ | |
5601 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5602 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5603 | |
a0c4da24 | 5604 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5605 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5606 | |
89b667f8 | 5607 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5608 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5609 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5610 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5611 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5612 | 0x009f0003); |
89b667f8 | 5613 | else |
ab3c759a | 5614 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5615 | 0x00d0000f); |
5616 | ||
5617 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5618 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5619 | /* Use SSC source */ | |
bdd4b6a6 | 5620 | if (pipe == PIPE_A) |
ab3c759a | 5621 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5622 | 0x0df40000); |
5623 | else | |
ab3c759a | 5624 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5625 | 0x0df70000); |
5626 | } else { /* HDMI or VGA */ | |
5627 | /* Use bend source */ | |
bdd4b6a6 | 5628 | if (pipe == PIPE_A) |
ab3c759a | 5629 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5630 | 0x0df70000); |
5631 | else | |
ab3c759a | 5632 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5633 | 0x0df40000); |
5634 | } | |
a0c4da24 | 5635 | |
ab3c759a | 5636 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5637 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5638 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5639 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5640 | coreclk |= 0x01000000; | |
ab3c759a | 5641 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5642 | |
ab3c759a | 5643 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5644 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5645 | } |
5646 | ||
9d556c99 CML |
5647 | static void chv_update_pll(struct intel_crtc *crtc) |
5648 | { | |
5649 | struct drm_device *dev = crtc->base.dev; | |
5650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5651 | int pipe = crtc->pipe; | |
5652 | int dpll_reg = DPLL(crtc->pipe); | |
5653 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5654 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5655 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5656 | int refclk; | |
5657 | ||
a11b0703 VS |
5658 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5659 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5660 | DPLL_VCO_ENABLE; | |
5661 | if (pipe != PIPE_A) | |
5662 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5663 | ||
5664 | crtc->config.dpll_hw_state.dpll_md = | |
5665 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5666 | |
5667 | bestn = crtc->config.dpll.n; | |
5668 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5669 | bestm1 = crtc->config.dpll.m1; | |
5670 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5671 | bestp1 = crtc->config.dpll.p1; | |
5672 | bestp2 = crtc->config.dpll.p2; | |
5673 | ||
5674 | /* | |
5675 | * Enable Refclk and SSC | |
5676 | */ | |
a11b0703 VS |
5677 | I915_WRITE(dpll_reg, |
5678 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5679 | ||
5680 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5681 | |
9d556c99 CML |
5682 | /* p1 and p2 divider */ |
5683 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5684 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5685 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5686 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5687 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5688 | ||
5689 | /* Feedback post-divider - m2 */ | |
5690 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5691 | ||
5692 | /* Feedback refclk divider - n and m1 */ | |
5693 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5694 | DPIO_CHV_M1_DIV_BY_2 | | |
5695 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5696 | ||
5697 | /* M2 fraction division */ | |
5698 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5699 | ||
5700 | /* M2 fraction division enable */ | |
5701 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5702 | DPIO_CHV_FRAC_DIV_EN | | |
5703 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5704 | ||
5705 | /* Loop filter */ | |
5706 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5707 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5708 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5709 | if (refclk == 100000) | |
5710 | intcoeff = 11; | |
5711 | else if (refclk == 38400) | |
5712 | intcoeff = 10; | |
5713 | else | |
5714 | intcoeff = 9; | |
5715 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5716 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5717 | ||
5718 | /* AFC Recal */ | |
5719 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5720 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5721 | DPIO_AFC_RECAL); | |
5722 | ||
5723 | mutex_unlock(&dev_priv->dpio_lock); | |
5724 | } | |
5725 | ||
f47709a9 DV |
5726 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5727 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5728 | int num_connectors) |
5729 | { | |
f47709a9 | 5730 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5731 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5732 | u32 dpll; |
5733 | bool is_sdvo; | |
f47709a9 | 5734 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5735 | |
f47709a9 | 5736 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5737 | |
f47709a9 DV |
5738 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5739 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5740 | |
5741 | dpll = DPLL_VGA_MODE_DIS; | |
5742 | ||
f47709a9 | 5743 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5744 | dpll |= DPLLB_MODE_LVDS; |
5745 | else | |
5746 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5747 | |
ef1b460d | 5748 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5749 | dpll |= (crtc->config.pixel_multiplier - 1) |
5750 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5751 | } |
198a037f DV |
5752 | |
5753 | if (is_sdvo) | |
4a33e48d | 5754 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5755 | |
f47709a9 | 5756 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5757 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5758 | |
5759 | /* compute bitmask from p1 value */ | |
5760 | if (IS_PINEVIEW(dev)) | |
5761 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5762 | else { | |
5763 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5764 | if (IS_G4X(dev) && reduced_clock) | |
5765 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5766 | } | |
5767 | switch (clock->p2) { | |
5768 | case 5: | |
5769 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5770 | break; | |
5771 | case 7: | |
5772 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5773 | break; | |
5774 | case 10: | |
5775 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5776 | break; | |
5777 | case 14: | |
5778 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5779 | break; | |
5780 | } | |
5781 | if (INTEL_INFO(dev)->gen >= 4) | |
5782 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5783 | ||
09ede541 | 5784 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5785 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5786 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5787 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5788 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5789 | else | |
5790 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5791 | ||
5792 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5793 | crtc->config.dpll_hw_state.dpll = dpll; |
5794 | ||
eb1cbe48 | 5795 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5796 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5797 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5798 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5799 | } |
5800 | } | |
5801 | ||
f47709a9 | 5802 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5803 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5804 | int num_connectors) |
5805 | { | |
f47709a9 | 5806 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5807 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5808 | u32 dpll; |
f47709a9 | 5809 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5810 | |
f47709a9 | 5811 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5812 | |
eb1cbe48 DV |
5813 | dpll = DPLL_VGA_MODE_DIS; |
5814 | ||
f47709a9 | 5815 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5816 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5817 | } else { | |
5818 | if (clock->p1 == 2) | |
5819 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5820 | else | |
5821 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5822 | if (clock->p2 == 4) | |
5823 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5824 | } | |
5825 | ||
4a33e48d DV |
5826 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5827 | dpll |= DPLL_DVO_2X_MODE; | |
5828 | ||
f47709a9 | 5829 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5830 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5831 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5832 | else | |
5833 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5834 | ||
5835 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5836 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5837 | } |
5838 | ||
8a654f3b | 5839 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5840 | { |
5841 | struct drm_device *dev = intel_crtc->base.dev; | |
5842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5843 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5844 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5845 | struct drm_display_mode *adjusted_mode = |
5846 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5847 | uint32_t crtc_vtotal, crtc_vblank_end; |
5848 | int vsyncshift = 0; | |
4d8a62ea DV |
5849 | |
5850 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5851 | * the hw state checker will get angry at the mismatch. */ | |
5852 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5853 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5854 | |
609aeaca | 5855 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5856 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5857 | crtc_vtotal -= 1; |
5858 | crtc_vblank_end -= 1; | |
609aeaca VS |
5859 | |
5860 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5861 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5862 | else | |
5863 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5864 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5865 | if (vsyncshift < 0) |
5866 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5867 | } |
5868 | ||
5869 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5870 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5871 | |
fe2b8f9d | 5872 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5873 | (adjusted_mode->crtc_hdisplay - 1) | |
5874 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5875 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5876 | (adjusted_mode->crtc_hblank_start - 1) | |
5877 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5878 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5879 | (adjusted_mode->crtc_hsync_start - 1) | |
5880 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5881 | ||
fe2b8f9d | 5882 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5883 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5884 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5885 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5886 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5887 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5888 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5889 | (adjusted_mode->crtc_vsync_start - 1) | |
5890 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5891 | ||
b5e508d4 PZ |
5892 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5893 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5894 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5895 | * bits. */ | |
5896 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5897 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5898 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5899 | ||
b0e77b9c PZ |
5900 | /* pipesrc controls the size that is scaled from, which should |
5901 | * always be the user's requested size. | |
5902 | */ | |
5903 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5904 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5905 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5906 | } |
5907 | ||
1bd1bd80 DV |
5908 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5909 | struct intel_crtc_config *pipe_config) | |
5910 | { | |
5911 | struct drm_device *dev = crtc->base.dev; | |
5912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5913 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5914 | uint32_t tmp; | |
5915 | ||
5916 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5917 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5918 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5919 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5920 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5921 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5922 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5923 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5924 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5925 | ||
5926 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5927 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5928 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5929 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5930 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5931 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5932 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5933 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5934 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5935 | ||
5936 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5937 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5938 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5939 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5940 | } | |
5941 | ||
5942 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5943 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5944 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5945 | ||
5946 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5947 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5948 | } |
5949 | ||
f6a83288 DV |
5950 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5951 | struct intel_crtc_config *pipe_config) | |
babea61d | 5952 | { |
f6a83288 DV |
5953 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5954 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5955 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5956 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5957 | |
f6a83288 DV |
5958 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5959 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5960 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5961 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5962 | |
f6a83288 | 5963 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5964 | |
f6a83288 DV |
5965 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5966 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5967 | } |
5968 | ||
84b046f3 DV |
5969 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5970 | { | |
5971 | struct drm_device *dev = intel_crtc->base.dev; | |
5972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5973 | uint32_t pipeconf; | |
5974 | ||
9f11a9e4 | 5975 | pipeconf = 0; |
84b046f3 | 5976 | |
67c72a12 DV |
5977 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5978 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5979 | pipeconf |= PIPECONF_ENABLE; | |
5980 | ||
cf532bb2 VS |
5981 | if (intel_crtc->config.double_wide) |
5982 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5983 | |
ff9ce46e DV |
5984 | /* only g4x and later have fancy bpc/dither controls */ |
5985 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5986 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5987 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5988 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5989 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5990 | |
ff9ce46e DV |
5991 | switch (intel_crtc->config.pipe_bpp) { |
5992 | case 18: | |
5993 | pipeconf |= PIPECONF_6BPC; | |
5994 | break; | |
5995 | case 24: | |
5996 | pipeconf |= PIPECONF_8BPC; | |
5997 | break; | |
5998 | case 30: | |
5999 | pipeconf |= PIPECONF_10BPC; | |
6000 | break; | |
6001 | default: | |
6002 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6003 | BUG(); | |
84b046f3 DV |
6004 | } |
6005 | } | |
6006 | ||
6007 | if (HAS_PIPE_CXSR(dev)) { | |
6008 | if (intel_crtc->lowfreq_avail) { | |
6009 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6010 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6011 | } else { | |
6012 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6013 | } |
6014 | } | |
6015 | ||
efc2cfff VS |
6016 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6017 | if (INTEL_INFO(dev)->gen < 4 || | |
6018 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6019 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
6020 | else | |
6021 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6022 | } else | |
84b046f3 DV |
6023 | pipeconf |= PIPECONF_PROGRESSIVE; |
6024 | ||
9f11a9e4 DV |
6025 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6026 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6027 | |
84b046f3 DV |
6028 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6029 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6030 | } | |
6031 | ||
f564048e | 6032 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6033 | int x, int y, |
94352cf9 | 6034 | struct drm_framebuffer *fb) |
79e53945 JB |
6035 | { |
6036 | struct drm_device *dev = crtc->dev; | |
6037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6039 | int refclk, num_connectors = 0; |
652c393a | 6040 | intel_clock_t clock, reduced_clock; |
a16af721 | 6041 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6042 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6043 | struct intel_encoder *encoder; |
d4906093 | 6044 | const intel_limit_t *limit; |
79e53945 | 6045 | |
6c2b7c12 | 6046 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6047 | switch (encoder->type) { |
79e53945 JB |
6048 | case INTEL_OUTPUT_LVDS: |
6049 | is_lvds = true; | |
6050 | break; | |
e9fd1c02 JN |
6051 | case INTEL_OUTPUT_DSI: |
6052 | is_dsi = true; | |
6053 | break; | |
79e53945 | 6054 | } |
43565a06 | 6055 | |
c751ce4f | 6056 | num_connectors++; |
79e53945 JB |
6057 | } |
6058 | ||
f2335330 | 6059 | if (is_dsi) |
5b18e57c | 6060 | return 0; |
f2335330 JN |
6061 | |
6062 | if (!intel_crtc->config.clock_set) { | |
6063 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6064 | |
e9fd1c02 JN |
6065 | /* |
6066 | * Returns a set of divisors for the desired target clock with | |
6067 | * the given refclk, or FALSE. The returned values represent | |
6068 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6069 | * 2) / p1 / p2. | |
6070 | */ | |
6071 | limit = intel_limit(crtc, refclk); | |
6072 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6073 | intel_crtc->config.port_clock, | |
6074 | refclk, NULL, &clock); | |
f2335330 | 6075 | if (!ok) { |
e9fd1c02 JN |
6076 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6077 | return -EINVAL; | |
6078 | } | |
79e53945 | 6079 | |
f2335330 JN |
6080 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6081 | /* | |
6082 | * Ensure we match the reduced clock's P to the target | |
6083 | * clock. If the clocks don't match, we can't switch | |
6084 | * the display clock by using the FP0/FP1. In such case | |
6085 | * we will disable the LVDS downclock feature. | |
6086 | */ | |
6087 | has_reduced_clock = | |
6088 | dev_priv->display.find_dpll(limit, crtc, | |
6089 | dev_priv->lvds_downclock, | |
6090 | refclk, &clock, | |
6091 | &reduced_clock); | |
6092 | } | |
6093 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6094 | intel_crtc->config.dpll.n = clock.n; |
6095 | intel_crtc->config.dpll.m1 = clock.m1; | |
6096 | intel_crtc->config.dpll.m2 = clock.m2; | |
6097 | intel_crtc->config.dpll.p1 = clock.p1; | |
6098 | intel_crtc->config.dpll.p2 = clock.p2; | |
6099 | } | |
7026d4ac | 6100 | |
e9fd1c02 | 6101 | if (IS_GEN2(dev)) { |
8a654f3b | 6102 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6103 | has_reduced_clock ? &reduced_clock : NULL, |
6104 | num_connectors); | |
9d556c99 CML |
6105 | } else if (IS_CHERRYVIEW(dev)) { |
6106 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6107 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6108 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6109 | } else { |
f47709a9 | 6110 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6111 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6112 | num_connectors); |
e9fd1c02 | 6113 | } |
79e53945 | 6114 | |
c8f7a0db | 6115 | return 0; |
f564048e EA |
6116 | } |
6117 | ||
2fa2fe9a DV |
6118 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6119 | struct intel_crtc_config *pipe_config) | |
6120 | { | |
6121 | struct drm_device *dev = crtc->base.dev; | |
6122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6123 | uint32_t tmp; | |
6124 | ||
dc9e7dec VS |
6125 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6126 | return; | |
6127 | ||
2fa2fe9a | 6128 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6129 | if (!(tmp & PFIT_ENABLE)) |
6130 | return; | |
2fa2fe9a | 6131 | |
06922821 | 6132 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6133 | if (INTEL_INFO(dev)->gen < 4) { |
6134 | if (crtc->pipe != PIPE_B) | |
6135 | return; | |
2fa2fe9a DV |
6136 | } else { |
6137 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6138 | return; | |
6139 | } | |
6140 | ||
06922821 | 6141 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6142 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6143 | if (INTEL_INFO(dev)->gen < 5) | |
6144 | pipe_config->gmch_pfit.lvds_border_bits = | |
6145 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6146 | } | |
6147 | ||
acbec814 JB |
6148 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6149 | struct intel_crtc_config *pipe_config) | |
6150 | { | |
6151 | struct drm_device *dev = crtc->base.dev; | |
6152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6153 | int pipe = pipe_config->cpu_transcoder; | |
6154 | intel_clock_t clock; | |
6155 | u32 mdiv; | |
662c6ecb | 6156 | int refclk = 100000; |
acbec814 JB |
6157 | |
6158 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 6159 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6160 | mutex_unlock(&dev_priv->dpio_lock); |
6161 | ||
6162 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6163 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6164 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6165 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6166 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6167 | ||
f646628b | 6168 | vlv_clock(refclk, &clock); |
acbec814 | 6169 | |
f646628b VS |
6170 | /* clock.dot is the fast clock */ |
6171 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6172 | } |
6173 | ||
1ad292b5 JB |
6174 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6175 | struct intel_plane_config *plane_config) | |
6176 | { | |
6177 | struct drm_device *dev = crtc->base.dev; | |
6178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6179 | u32 val, base, offset; | |
6180 | int pipe = crtc->pipe, plane = crtc->plane; | |
6181 | int fourcc, pixel_format; | |
6182 | int aligned_height; | |
6183 | ||
66e514c1 DA |
6184 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6185 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6186 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6187 | return; | |
6188 | } | |
6189 | ||
6190 | val = I915_READ(DSPCNTR(plane)); | |
6191 | ||
6192 | if (INTEL_INFO(dev)->gen >= 4) | |
6193 | if (val & DISPPLANE_TILED) | |
6194 | plane_config->tiled = true; | |
6195 | ||
6196 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6197 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6198 | crtc->base.primary->fb->pixel_format = fourcc; |
6199 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6200 | drm_format_plane_cpp(fourcc, 0) * 8; |
6201 | ||
6202 | if (INTEL_INFO(dev)->gen >= 4) { | |
6203 | if (plane_config->tiled) | |
6204 | offset = I915_READ(DSPTILEOFF(plane)); | |
6205 | else | |
6206 | offset = I915_READ(DSPLINOFF(plane)); | |
6207 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6208 | } else { | |
6209 | base = I915_READ(DSPADDR(plane)); | |
6210 | } | |
6211 | plane_config->base = base; | |
6212 | ||
6213 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6214 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6215 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6216 | |
6217 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 6218 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 6219 | |
66e514c1 | 6220 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6221 | plane_config->tiled); |
6222 | ||
1267a26b FF |
6223 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6224 | aligned_height); | |
1ad292b5 JB |
6225 | |
6226 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6227 | pipe, plane, crtc->base.primary->fb->width, |
6228 | crtc->base.primary->fb->height, | |
6229 | crtc->base.primary->fb->bits_per_pixel, base, | |
6230 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6231 | plane_config->size); |
6232 | ||
6233 | } | |
6234 | ||
70b23a98 VS |
6235 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6236 | struct intel_crtc_config *pipe_config) | |
6237 | { | |
6238 | struct drm_device *dev = crtc->base.dev; | |
6239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6240 | int pipe = pipe_config->cpu_transcoder; | |
6241 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6242 | intel_clock_t clock; | |
6243 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6244 | int refclk = 100000; | |
6245 | ||
6246 | mutex_lock(&dev_priv->dpio_lock); | |
6247 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6248 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6249 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6250 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6251 | mutex_unlock(&dev_priv->dpio_lock); | |
6252 | ||
6253 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6254 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6255 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6256 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6257 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6258 | ||
6259 | chv_clock(refclk, &clock); | |
6260 | ||
6261 | /* clock.dot is the fast clock */ | |
6262 | pipe_config->port_clock = clock.dot / 5; | |
6263 | } | |
6264 | ||
0e8ffe1b DV |
6265 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6266 | struct intel_crtc_config *pipe_config) | |
6267 | { | |
6268 | struct drm_device *dev = crtc->base.dev; | |
6269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6270 | uint32_t tmp; | |
6271 | ||
b5482bd0 ID |
6272 | if (!intel_display_power_enabled(dev_priv, |
6273 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6274 | return false; | |
6275 | ||
e143a21c | 6276 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6277 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6278 | |
0e8ffe1b DV |
6279 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6280 | if (!(tmp & PIPECONF_ENABLE)) | |
6281 | return false; | |
6282 | ||
42571aef VS |
6283 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6284 | switch (tmp & PIPECONF_BPC_MASK) { | |
6285 | case PIPECONF_6BPC: | |
6286 | pipe_config->pipe_bpp = 18; | |
6287 | break; | |
6288 | case PIPECONF_8BPC: | |
6289 | pipe_config->pipe_bpp = 24; | |
6290 | break; | |
6291 | case PIPECONF_10BPC: | |
6292 | pipe_config->pipe_bpp = 30; | |
6293 | break; | |
6294 | default: | |
6295 | break; | |
6296 | } | |
6297 | } | |
6298 | ||
b5a9fa09 DV |
6299 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6300 | pipe_config->limited_color_range = true; | |
6301 | ||
282740f7 VS |
6302 | if (INTEL_INFO(dev)->gen < 4) |
6303 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6304 | ||
1bd1bd80 DV |
6305 | intel_get_pipe_timings(crtc, pipe_config); |
6306 | ||
2fa2fe9a DV |
6307 | i9xx_get_pfit_config(crtc, pipe_config); |
6308 | ||
6c49f241 DV |
6309 | if (INTEL_INFO(dev)->gen >= 4) { |
6310 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6311 | pipe_config->pixel_multiplier = | |
6312 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6313 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6314 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6315 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6316 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6317 | pipe_config->pixel_multiplier = | |
6318 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6319 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6320 | } else { | |
6321 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6322 | * port and will be fixed up in the encoder->get_config | |
6323 | * function. */ | |
6324 | pipe_config->pixel_multiplier = 1; | |
6325 | } | |
8bcc2795 DV |
6326 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6327 | if (!IS_VALLEYVIEW(dev)) { | |
6328 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6329 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6330 | } else { |
6331 | /* Mask out read-only status bits. */ | |
6332 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6333 | DPLL_PORTC_READY_MASK | | |
6334 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6335 | } |
6c49f241 | 6336 | |
70b23a98 VS |
6337 | if (IS_CHERRYVIEW(dev)) |
6338 | chv_crtc_clock_get(crtc, pipe_config); | |
6339 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6340 | vlv_crtc_clock_get(crtc, pipe_config); |
6341 | else | |
6342 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6343 | |
0e8ffe1b DV |
6344 | return true; |
6345 | } | |
6346 | ||
dde86e2d | 6347 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6348 | { |
6349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6350 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6351 | struct intel_encoder *encoder; |
74cfd7ac | 6352 | u32 val, final; |
13d83a67 | 6353 | bool has_lvds = false; |
199e5d79 | 6354 | bool has_cpu_edp = false; |
199e5d79 | 6355 | bool has_panel = false; |
99eb6a01 KP |
6356 | bool has_ck505 = false; |
6357 | bool can_ssc = false; | |
13d83a67 JB |
6358 | |
6359 | /* We need to take the global config into account */ | |
199e5d79 KP |
6360 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6361 | base.head) { | |
6362 | switch (encoder->type) { | |
6363 | case INTEL_OUTPUT_LVDS: | |
6364 | has_panel = true; | |
6365 | has_lvds = true; | |
6366 | break; | |
6367 | case INTEL_OUTPUT_EDP: | |
6368 | has_panel = true; | |
2de6905f | 6369 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6370 | has_cpu_edp = true; |
6371 | break; | |
13d83a67 JB |
6372 | } |
6373 | } | |
6374 | ||
99eb6a01 | 6375 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6376 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6377 | can_ssc = has_ck505; |
6378 | } else { | |
6379 | has_ck505 = false; | |
6380 | can_ssc = true; | |
6381 | } | |
6382 | ||
2de6905f ID |
6383 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6384 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6385 | |
6386 | /* Ironlake: try to setup display ref clock before DPLL | |
6387 | * enabling. This is only under driver's control after | |
6388 | * PCH B stepping, previous chipset stepping should be | |
6389 | * ignoring this setting. | |
6390 | */ | |
74cfd7ac CW |
6391 | val = I915_READ(PCH_DREF_CONTROL); |
6392 | ||
6393 | /* As we must carefully and slowly disable/enable each source in turn, | |
6394 | * compute the final state we want first and check if we need to | |
6395 | * make any changes at all. | |
6396 | */ | |
6397 | final = val; | |
6398 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6399 | if (has_ck505) | |
6400 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6401 | else | |
6402 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6403 | ||
6404 | final &= ~DREF_SSC_SOURCE_MASK; | |
6405 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6406 | final &= ~DREF_SSC1_ENABLE; | |
6407 | ||
6408 | if (has_panel) { | |
6409 | final |= DREF_SSC_SOURCE_ENABLE; | |
6410 | ||
6411 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6412 | final |= DREF_SSC1_ENABLE; | |
6413 | ||
6414 | if (has_cpu_edp) { | |
6415 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6416 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6417 | else | |
6418 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6419 | } else | |
6420 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6421 | } else { | |
6422 | final |= DREF_SSC_SOURCE_DISABLE; | |
6423 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6424 | } | |
6425 | ||
6426 | if (final == val) | |
6427 | return; | |
6428 | ||
13d83a67 | 6429 | /* Always enable nonspread source */ |
74cfd7ac | 6430 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6431 | |
99eb6a01 | 6432 | if (has_ck505) |
74cfd7ac | 6433 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6434 | else |
74cfd7ac | 6435 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6436 | |
199e5d79 | 6437 | if (has_panel) { |
74cfd7ac CW |
6438 | val &= ~DREF_SSC_SOURCE_MASK; |
6439 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6440 | |
199e5d79 | 6441 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6442 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6443 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6444 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6445 | } else |
74cfd7ac | 6446 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6447 | |
6448 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6449 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6450 | POSTING_READ(PCH_DREF_CONTROL); |
6451 | udelay(200); | |
6452 | ||
74cfd7ac | 6453 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6454 | |
6455 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6456 | if (has_cpu_edp) { |
99eb6a01 | 6457 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6458 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6459 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6460 | } else |
74cfd7ac | 6461 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6462 | } else |
74cfd7ac | 6463 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6464 | |
74cfd7ac | 6465 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6466 | POSTING_READ(PCH_DREF_CONTROL); |
6467 | udelay(200); | |
6468 | } else { | |
6469 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6470 | ||
74cfd7ac | 6471 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6472 | |
6473 | /* Turn off CPU output */ | |
74cfd7ac | 6474 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6475 | |
74cfd7ac | 6476 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6477 | POSTING_READ(PCH_DREF_CONTROL); |
6478 | udelay(200); | |
6479 | ||
6480 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6481 | val &= ~DREF_SSC_SOURCE_MASK; |
6482 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6483 | |
6484 | /* Turn off SSC1 */ | |
74cfd7ac | 6485 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6486 | |
74cfd7ac | 6487 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6488 | POSTING_READ(PCH_DREF_CONTROL); |
6489 | udelay(200); | |
6490 | } | |
74cfd7ac CW |
6491 | |
6492 | BUG_ON(val != final); | |
13d83a67 JB |
6493 | } |
6494 | ||
f31f2d55 | 6495 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6496 | { |
f31f2d55 | 6497 | uint32_t tmp; |
dde86e2d | 6498 | |
0ff066a9 PZ |
6499 | tmp = I915_READ(SOUTH_CHICKEN2); |
6500 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6501 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6502 | |
0ff066a9 PZ |
6503 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6504 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6505 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6506 | |
0ff066a9 PZ |
6507 | tmp = I915_READ(SOUTH_CHICKEN2); |
6508 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6509 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6510 | |
0ff066a9 PZ |
6511 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6512 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6513 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6514 | } |
6515 | ||
6516 | /* WaMPhyProgramming:hsw */ | |
6517 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6518 | { | |
6519 | uint32_t tmp; | |
dde86e2d PZ |
6520 | |
6521 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6522 | tmp &= ~(0xFF << 24); | |
6523 | tmp |= (0x12 << 24); | |
6524 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6525 | ||
dde86e2d PZ |
6526 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6527 | tmp |= (1 << 11); | |
6528 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6529 | ||
6530 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6531 | tmp |= (1 << 11); | |
6532 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6533 | ||
dde86e2d PZ |
6534 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6535 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6536 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6537 | ||
6538 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6539 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6540 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6541 | ||
0ff066a9 PZ |
6542 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6543 | tmp &= ~(7 << 13); | |
6544 | tmp |= (5 << 13); | |
6545 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6546 | |
0ff066a9 PZ |
6547 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6548 | tmp &= ~(7 << 13); | |
6549 | tmp |= (5 << 13); | |
6550 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6551 | |
6552 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6553 | tmp &= ~0xFF; | |
6554 | tmp |= 0x1C; | |
6555 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6556 | ||
6557 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6558 | tmp &= ~0xFF; | |
6559 | tmp |= 0x1C; | |
6560 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6561 | ||
6562 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6563 | tmp &= ~(0xFF << 16); | |
6564 | tmp |= (0x1C << 16); | |
6565 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6566 | ||
6567 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6568 | tmp &= ~(0xFF << 16); | |
6569 | tmp |= (0x1C << 16); | |
6570 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6571 | ||
0ff066a9 PZ |
6572 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6573 | tmp |= (1 << 27); | |
6574 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6575 | |
0ff066a9 PZ |
6576 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6577 | tmp |= (1 << 27); | |
6578 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6579 | |
0ff066a9 PZ |
6580 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6581 | tmp &= ~(0xF << 28); | |
6582 | tmp |= (4 << 28); | |
6583 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6584 | |
0ff066a9 PZ |
6585 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6586 | tmp &= ~(0xF << 28); | |
6587 | tmp |= (4 << 28); | |
6588 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6589 | } |
6590 | ||
2fa86a1f PZ |
6591 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6592 | * Programming" based on the parameters passed: | |
6593 | * - Sequence to enable CLKOUT_DP | |
6594 | * - Sequence to enable CLKOUT_DP without spread | |
6595 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6596 | */ | |
6597 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6598 | bool with_fdi) | |
f31f2d55 PZ |
6599 | { |
6600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6601 | uint32_t reg, tmp; |
6602 | ||
6603 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6604 | with_spread = true; | |
6605 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6606 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6607 | with_fdi = false; | |
f31f2d55 PZ |
6608 | |
6609 | mutex_lock(&dev_priv->dpio_lock); | |
6610 | ||
6611 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6612 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6613 | tmp |= SBI_SSCCTL_PATHALT; | |
6614 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6615 | ||
6616 | udelay(24); | |
6617 | ||
2fa86a1f PZ |
6618 | if (with_spread) { |
6619 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6620 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6621 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6622 | |
2fa86a1f PZ |
6623 | if (with_fdi) { |
6624 | lpt_reset_fdi_mphy(dev_priv); | |
6625 | lpt_program_fdi_mphy(dev_priv); | |
6626 | } | |
6627 | } | |
dde86e2d | 6628 | |
2fa86a1f PZ |
6629 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6630 | SBI_GEN0 : SBI_DBUFF0; | |
6631 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6632 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6633 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6634 | |
6635 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6636 | } |
6637 | ||
47701c3b PZ |
6638 | /* Sequence to disable CLKOUT_DP */ |
6639 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6640 | { | |
6641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6642 | uint32_t reg, tmp; | |
6643 | ||
6644 | mutex_lock(&dev_priv->dpio_lock); | |
6645 | ||
6646 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6647 | SBI_GEN0 : SBI_DBUFF0; | |
6648 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6649 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6650 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6651 | ||
6652 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6653 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6654 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6655 | tmp |= SBI_SSCCTL_PATHALT; | |
6656 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6657 | udelay(32); | |
6658 | } | |
6659 | tmp |= SBI_SSCCTL_DISABLE; | |
6660 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6661 | } | |
6662 | ||
6663 | mutex_unlock(&dev_priv->dpio_lock); | |
6664 | } | |
6665 | ||
bf8fa3d3 PZ |
6666 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6667 | { | |
6668 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6669 | struct intel_encoder *encoder; | |
6670 | bool has_vga = false; | |
6671 | ||
6672 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6673 | switch (encoder->type) { | |
6674 | case INTEL_OUTPUT_ANALOG: | |
6675 | has_vga = true; | |
6676 | break; | |
6677 | } | |
6678 | } | |
6679 | ||
47701c3b PZ |
6680 | if (has_vga) |
6681 | lpt_enable_clkout_dp(dev, true, true); | |
6682 | else | |
6683 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6684 | } |
6685 | ||
dde86e2d PZ |
6686 | /* |
6687 | * Initialize reference clocks when the driver loads | |
6688 | */ | |
6689 | void intel_init_pch_refclk(struct drm_device *dev) | |
6690 | { | |
6691 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6692 | ironlake_init_pch_refclk(dev); | |
6693 | else if (HAS_PCH_LPT(dev)) | |
6694 | lpt_init_pch_refclk(dev); | |
6695 | } | |
6696 | ||
d9d444cb JB |
6697 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6698 | { | |
6699 | struct drm_device *dev = crtc->dev; | |
6700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6701 | struct intel_encoder *encoder; | |
d9d444cb JB |
6702 | int num_connectors = 0; |
6703 | bool is_lvds = false; | |
6704 | ||
6c2b7c12 | 6705 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6706 | switch (encoder->type) { |
6707 | case INTEL_OUTPUT_LVDS: | |
6708 | is_lvds = true; | |
6709 | break; | |
d9d444cb JB |
6710 | } |
6711 | num_connectors++; | |
6712 | } | |
6713 | ||
6714 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6715 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6716 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6717 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6718 | } |
6719 | ||
6720 | return 120000; | |
6721 | } | |
6722 | ||
6ff93609 | 6723 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6724 | { |
c8203565 | 6725 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6727 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6728 | uint32_t val; |
6729 | ||
78114071 | 6730 | val = 0; |
c8203565 | 6731 | |
965e0c48 | 6732 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6733 | case 18: |
dfd07d72 | 6734 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6735 | break; |
6736 | case 24: | |
dfd07d72 | 6737 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6738 | break; |
6739 | case 30: | |
dfd07d72 | 6740 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6741 | break; |
6742 | case 36: | |
dfd07d72 | 6743 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6744 | break; |
6745 | default: | |
cc769b62 PZ |
6746 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6747 | BUG(); | |
c8203565 PZ |
6748 | } |
6749 | ||
d8b32247 | 6750 | if (intel_crtc->config.dither) |
c8203565 PZ |
6751 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6752 | ||
6ff93609 | 6753 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6754 | val |= PIPECONF_INTERLACED_ILK; |
6755 | else | |
6756 | val |= PIPECONF_PROGRESSIVE; | |
6757 | ||
50f3b016 | 6758 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6759 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6760 | |
c8203565 PZ |
6761 | I915_WRITE(PIPECONF(pipe), val); |
6762 | POSTING_READ(PIPECONF(pipe)); | |
6763 | } | |
6764 | ||
86d3efce VS |
6765 | /* |
6766 | * Set up the pipe CSC unit. | |
6767 | * | |
6768 | * Currently only full range RGB to limited range RGB conversion | |
6769 | * is supported, but eventually this should handle various | |
6770 | * RGB<->YCbCr scenarios as well. | |
6771 | */ | |
50f3b016 | 6772 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6773 | { |
6774 | struct drm_device *dev = crtc->dev; | |
6775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6777 | int pipe = intel_crtc->pipe; | |
6778 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6779 | ||
6780 | /* | |
6781 | * TODO: Check what kind of values actually come out of the pipe | |
6782 | * with these coeff/postoff values and adjust to get the best | |
6783 | * accuracy. Perhaps we even need to take the bpc value into | |
6784 | * consideration. | |
6785 | */ | |
6786 | ||
50f3b016 | 6787 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6788 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6789 | ||
6790 | /* | |
6791 | * GY/GU and RY/RU should be the other way around according | |
6792 | * to BSpec, but reality doesn't agree. Just set them up in | |
6793 | * a way that results in the correct picture. | |
6794 | */ | |
6795 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6796 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6797 | ||
6798 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6799 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6800 | ||
6801 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6802 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6803 | ||
6804 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6805 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6806 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6807 | ||
6808 | if (INTEL_INFO(dev)->gen > 6) { | |
6809 | uint16_t postoff = 0; | |
6810 | ||
50f3b016 | 6811 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6812 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6813 | |
6814 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6815 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6816 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6817 | ||
6818 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6819 | } else { | |
6820 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6821 | ||
50f3b016 | 6822 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6823 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6824 | ||
6825 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6826 | } | |
6827 | } | |
6828 | ||
6ff93609 | 6829 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6830 | { |
756f85cf PZ |
6831 | struct drm_device *dev = crtc->dev; |
6832 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6833 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6834 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6835 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6836 | uint32_t val; |
6837 | ||
3eff4faa | 6838 | val = 0; |
ee2b0b38 | 6839 | |
756f85cf | 6840 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6841 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6842 | ||
6ff93609 | 6843 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6844 | val |= PIPECONF_INTERLACED_ILK; |
6845 | else | |
6846 | val |= PIPECONF_PROGRESSIVE; | |
6847 | ||
702e7a56 PZ |
6848 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6849 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6850 | |
6851 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6852 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6853 | |
6854 | if (IS_BROADWELL(dev)) { | |
6855 | val = 0; | |
6856 | ||
6857 | switch (intel_crtc->config.pipe_bpp) { | |
6858 | case 18: | |
6859 | val |= PIPEMISC_DITHER_6_BPC; | |
6860 | break; | |
6861 | case 24: | |
6862 | val |= PIPEMISC_DITHER_8_BPC; | |
6863 | break; | |
6864 | case 30: | |
6865 | val |= PIPEMISC_DITHER_10_BPC; | |
6866 | break; | |
6867 | case 36: | |
6868 | val |= PIPEMISC_DITHER_12_BPC; | |
6869 | break; | |
6870 | default: | |
6871 | /* Case prevented by pipe_config_set_bpp. */ | |
6872 | BUG(); | |
6873 | } | |
6874 | ||
6875 | if (intel_crtc->config.dither) | |
6876 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6877 | ||
6878 | I915_WRITE(PIPEMISC(pipe), val); | |
6879 | } | |
ee2b0b38 PZ |
6880 | } |
6881 | ||
6591c6e4 | 6882 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6883 | intel_clock_t *clock, |
6884 | bool *has_reduced_clock, | |
6885 | intel_clock_t *reduced_clock) | |
6886 | { | |
6887 | struct drm_device *dev = crtc->dev; | |
6888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6889 | struct intel_encoder *intel_encoder; | |
6890 | int refclk; | |
d4906093 | 6891 | const intel_limit_t *limit; |
a16af721 | 6892 | bool ret, is_lvds = false; |
79e53945 | 6893 | |
6591c6e4 PZ |
6894 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6895 | switch (intel_encoder->type) { | |
79e53945 JB |
6896 | case INTEL_OUTPUT_LVDS: |
6897 | is_lvds = true; | |
6898 | break; | |
79e53945 JB |
6899 | } |
6900 | } | |
6901 | ||
d9d444cb | 6902 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6903 | |
d4906093 ML |
6904 | /* |
6905 | * Returns a set of divisors for the desired target clock with the given | |
6906 | * refclk, or FALSE. The returned values represent the clock equation: | |
6907 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6908 | */ | |
1b894b59 | 6909 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6910 | ret = dev_priv->display.find_dpll(limit, crtc, |
6911 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6912 | refclk, NULL, clock); |
6591c6e4 PZ |
6913 | if (!ret) |
6914 | return false; | |
cda4b7d3 | 6915 | |
ddc9003c | 6916 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6917 | /* |
6918 | * Ensure we match the reduced clock's P to the target clock. | |
6919 | * If the clocks don't match, we can't switch the display clock | |
6920 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6921 | * downclock feature. | |
6922 | */ | |
ee9300bb DV |
6923 | *has_reduced_clock = |
6924 | dev_priv->display.find_dpll(limit, crtc, | |
6925 | dev_priv->lvds_downclock, | |
6926 | refclk, clock, | |
6927 | reduced_clock); | |
652c393a | 6928 | } |
61e9653f | 6929 | |
6591c6e4 PZ |
6930 | return true; |
6931 | } | |
6932 | ||
d4b1931c PZ |
6933 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6934 | { | |
6935 | /* | |
6936 | * Account for spread spectrum to avoid | |
6937 | * oversubscribing the link. Max center spread | |
6938 | * is 2.5%; use 5% for safety's sake. | |
6939 | */ | |
6940 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6941 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6942 | } |
6943 | ||
7429e9d4 | 6944 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6945 | { |
7429e9d4 | 6946 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6947 | } |
6948 | ||
de13a2e3 | 6949 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6950 | u32 *fp, |
9a7c7890 | 6951 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6952 | { |
de13a2e3 | 6953 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6954 | struct drm_device *dev = crtc->dev; |
6955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6956 | struct intel_encoder *intel_encoder; |
6957 | uint32_t dpll; | |
6cc5f341 | 6958 | int factor, num_connectors = 0; |
09ede541 | 6959 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6960 | |
de13a2e3 PZ |
6961 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6962 | switch (intel_encoder->type) { | |
79e53945 JB |
6963 | case INTEL_OUTPUT_LVDS: |
6964 | is_lvds = true; | |
6965 | break; | |
6966 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6967 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6968 | is_sdvo = true; |
79e53945 | 6969 | break; |
79e53945 | 6970 | } |
43565a06 | 6971 | |
c751ce4f | 6972 | num_connectors++; |
79e53945 | 6973 | } |
79e53945 | 6974 | |
c1858123 | 6975 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6976 | factor = 21; |
6977 | if (is_lvds) { | |
6978 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6979 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6980 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6981 | factor = 25; |
09ede541 | 6982 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6983 | factor = 20; |
c1858123 | 6984 | |
7429e9d4 | 6985 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6986 | *fp |= FP_CB_TUNE; |
2c07245f | 6987 | |
9a7c7890 DV |
6988 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6989 | *fp2 |= FP_CB_TUNE; | |
6990 | ||
5eddb70b | 6991 | dpll = 0; |
2c07245f | 6992 | |
a07d6787 EA |
6993 | if (is_lvds) |
6994 | dpll |= DPLLB_MODE_LVDS; | |
6995 | else | |
6996 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6997 | |
ef1b460d DV |
6998 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6999 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
7000 | |
7001 | if (is_sdvo) | |
4a33e48d | 7002 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 7003 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 7004 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7005 | |
a07d6787 | 7006 | /* compute bitmask from p1 value */ |
7429e9d4 | 7007 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7008 | /* also FPA1 */ |
7429e9d4 | 7009 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7010 | |
7429e9d4 | 7011 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
7012 | case 5: |
7013 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7014 | break; | |
7015 | case 7: | |
7016 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7017 | break; | |
7018 | case 10: | |
7019 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7020 | break; | |
7021 | case 14: | |
7022 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7023 | break; | |
79e53945 JB |
7024 | } |
7025 | ||
b4c09f3b | 7026 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7027 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7028 | else |
7029 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7030 | ||
959e16d6 | 7031 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7032 | } |
7033 | ||
7034 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
7035 | int x, int y, |
7036 | struct drm_framebuffer *fb) | |
7037 | { | |
7038 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7040 | int num_connectors = 0; |
7041 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7042 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7043 | bool ok, has_reduced_clock = false; |
8b47047b | 7044 | bool is_lvds = false; |
de13a2e3 | 7045 | struct intel_encoder *encoder; |
e2b78267 | 7046 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7047 | |
7048 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7049 | switch (encoder->type) { | |
7050 | case INTEL_OUTPUT_LVDS: | |
7051 | is_lvds = true; | |
7052 | break; | |
de13a2e3 PZ |
7053 | } |
7054 | ||
7055 | num_connectors++; | |
a07d6787 | 7056 | } |
79e53945 | 7057 | |
5dc5298b PZ |
7058 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7059 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7060 | |
ff9a6750 | 7061 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7062 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7063 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7064 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7065 | return -EINVAL; | |
79e53945 | 7066 | } |
f47709a9 DV |
7067 | /* Compat-code for transition, will disappear. */ |
7068 | if (!intel_crtc->config.clock_set) { | |
7069 | intel_crtc->config.dpll.n = clock.n; | |
7070 | intel_crtc->config.dpll.m1 = clock.m1; | |
7071 | intel_crtc->config.dpll.m2 = clock.m2; | |
7072 | intel_crtc->config.dpll.p1 = clock.p1; | |
7073 | intel_crtc->config.dpll.p2 = clock.p2; | |
7074 | } | |
79e53945 | 7075 | |
5dc5298b | 7076 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7077 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7078 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7079 | if (has_reduced_clock) |
7429e9d4 | 7080 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7081 | |
7429e9d4 | 7082 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7083 | &fp, &reduced_clock, |
7084 | has_reduced_clock ? &fp2 : NULL); | |
7085 | ||
959e16d6 | 7086 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7087 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7088 | if (has_reduced_clock) | |
7089 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7090 | else | |
7091 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7092 | ||
b89a1d39 | 7093 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7094 | if (pll == NULL) { |
84f44ce7 | 7095 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7096 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7097 | return -EINVAL; |
7098 | } | |
ee7b9f93 | 7099 | } else |
e72f9fbf | 7100 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7101 | |
d330a953 | 7102 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7103 | intel_crtc->lowfreq_avail = true; |
7104 | else | |
7105 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7106 | |
c8f7a0db | 7107 | return 0; |
79e53945 JB |
7108 | } |
7109 | ||
eb14cb74 VS |
7110 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7111 | struct intel_link_m_n *m_n) | |
7112 | { | |
7113 | struct drm_device *dev = crtc->base.dev; | |
7114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7115 | enum pipe pipe = crtc->pipe; | |
7116 | ||
7117 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7118 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7119 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7120 | & ~TU_SIZE_MASK; | |
7121 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7122 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7123 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7124 | } | |
7125 | ||
7126 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7127 | enum transcoder transcoder, | |
7128 | struct intel_link_m_n *m_n) | |
72419203 DV |
7129 | { |
7130 | struct drm_device *dev = crtc->base.dev; | |
7131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7132 | enum pipe pipe = crtc->pipe; |
72419203 | 7133 | |
eb14cb74 VS |
7134 | if (INTEL_INFO(dev)->gen >= 5) { |
7135 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7136 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7137 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7138 | & ~TU_SIZE_MASK; | |
7139 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7140 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7141 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7142 | } else { | |
7143 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7144 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7145 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7146 | & ~TU_SIZE_MASK; | |
7147 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7148 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7149 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7150 | } | |
7151 | } | |
7152 | ||
7153 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7154 | struct intel_crtc_config *pipe_config) | |
7155 | { | |
7156 | if (crtc->config.has_pch_encoder) | |
7157 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7158 | else | |
7159 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7160 | &pipe_config->dp_m_n); | |
7161 | } | |
72419203 | 7162 | |
eb14cb74 VS |
7163 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7164 | struct intel_crtc_config *pipe_config) | |
7165 | { | |
7166 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7167 | &pipe_config->fdi_m_n); | |
72419203 DV |
7168 | } |
7169 | ||
2fa2fe9a DV |
7170 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7171 | struct intel_crtc_config *pipe_config) | |
7172 | { | |
7173 | struct drm_device *dev = crtc->base.dev; | |
7174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7175 | uint32_t tmp; | |
7176 | ||
7177 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7178 | ||
7179 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7180 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7181 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7182 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7183 | |
7184 | /* We currently do not free assignements of panel fitters on | |
7185 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7186 | * differentiates them) so just WARN about this case for now. */ | |
7187 | if (IS_GEN7(dev)) { | |
7188 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7189 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7190 | } | |
2fa2fe9a | 7191 | } |
79e53945 JB |
7192 | } |
7193 | ||
4c6baa59 JB |
7194 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7195 | struct intel_plane_config *plane_config) | |
7196 | { | |
7197 | struct drm_device *dev = crtc->base.dev; | |
7198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7199 | u32 val, base, offset; | |
7200 | int pipe = crtc->pipe, plane = crtc->plane; | |
7201 | int fourcc, pixel_format; | |
7202 | int aligned_height; | |
7203 | ||
66e514c1 DA |
7204 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7205 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7206 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7207 | return; | |
7208 | } | |
7209 | ||
7210 | val = I915_READ(DSPCNTR(plane)); | |
7211 | ||
7212 | if (INTEL_INFO(dev)->gen >= 4) | |
7213 | if (val & DISPPLANE_TILED) | |
7214 | plane_config->tiled = true; | |
7215 | ||
7216 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7217 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7218 | crtc->base.primary->fb->pixel_format = fourcc; |
7219 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7220 | drm_format_plane_cpp(fourcc, 0) * 8; |
7221 | ||
7222 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7223 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7224 | offset = I915_READ(DSPOFFSET(plane)); | |
7225 | } else { | |
7226 | if (plane_config->tiled) | |
7227 | offset = I915_READ(DSPTILEOFF(plane)); | |
7228 | else | |
7229 | offset = I915_READ(DSPLINOFF(plane)); | |
7230 | } | |
7231 | plane_config->base = base; | |
7232 | ||
7233 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7234 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7235 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7236 | |
7237 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7238 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7239 | |
66e514c1 | 7240 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7241 | plane_config->tiled); |
7242 | ||
1267a26b FF |
7243 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7244 | aligned_height); | |
4c6baa59 JB |
7245 | |
7246 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7247 | pipe, plane, crtc->base.primary->fb->width, |
7248 | crtc->base.primary->fb->height, | |
7249 | crtc->base.primary->fb->bits_per_pixel, base, | |
7250 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7251 | plane_config->size); |
7252 | } | |
7253 | ||
0e8ffe1b DV |
7254 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7255 | struct intel_crtc_config *pipe_config) | |
7256 | { | |
7257 | struct drm_device *dev = crtc->base.dev; | |
7258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7259 | uint32_t tmp; | |
7260 | ||
e143a21c | 7261 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7262 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7263 | |
0e8ffe1b DV |
7264 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7265 | if (!(tmp & PIPECONF_ENABLE)) | |
7266 | return false; | |
7267 | ||
42571aef VS |
7268 | switch (tmp & PIPECONF_BPC_MASK) { |
7269 | case PIPECONF_6BPC: | |
7270 | pipe_config->pipe_bpp = 18; | |
7271 | break; | |
7272 | case PIPECONF_8BPC: | |
7273 | pipe_config->pipe_bpp = 24; | |
7274 | break; | |
7275 | case PIPECONF_10BPC: | |
7276 | pipe_config->pipe_bpp = 30; | |
7277 | break; | |
7278 | case PIPECONF_12BPC: | |
7279 | pipe_config->pipe_bpp = 36; | |
7280 | break; | |
7281 | default: | |
7282 | break; | |
7283 | } | |
7284 | ||
b5a9fa09 DV |
7285 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7286 | pipe_config->limited_color_range = true; | |
7287 | ||
ab9412ba | 7288 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7289 | struct intel_shared_dpll *pll; |
7290 | ||
88adfff1 DV |
7291 | pipe_config->has_pch_encoder = true; |
7292 | ||
627eb5a3 DV |
7293 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7294 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7295 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7296 | |
7297 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7298 | |
c0d43d62 | 7299 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7300 | pipe_config->shared_dpll = |
7301 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7302 | } else { |
7303 | tmp = I915_READ(PCH_DPLL_SEL); | |
7304 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7305 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7306 | else | |
7307 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7308 | } | |
66e985c0 DV |
7309 | |
7310 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7311 | ||
7312 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7313 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7314 | |
7315 | tmp = pipe_config->dpll_hw_state.dpll; | |
7316 | pipe_config->pixel_multiplier = | |
7317 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7318 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7319 | |
7320 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7321 | } else { |
7322 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7323 | } |
7324 | ||
1bd1bd80 DV |
7325 | intel_get_pipe_timings(crtc, pipe_config); |
7326 | ||
2fa2fe9a DV |
7327 | ironlake_get_pfit_config(crtc, pipe_config); |
7328 | ||
0e8ffe1b DV |
7329 | return true; |
7330 | } | |
7331 | ||
be256dc7 PZ |
7332 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7333 | { | |
7334 | struct drm_device *dev = dev_priv->dev; | |
7335 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7336 | struct intel_crtc *crtc; | |
be256dc7 | 7337 | |
d3fcc808 | 7338 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7339 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7340 | pipe_name(crtc->pipe)); |
7341 | ||
7342 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7343 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7344 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7345 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7346 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7347 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7348 | "CPU PWM1 enabled\n"); | |
7349 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7350 | "CPU PWM2 enabled\n"); | |
7351 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7352 | "PCH PWM1 enabled\n"); | |
7353 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7354 | "Utility pin enabled\n"); | |
7355 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7356 | ||
9926ada1 PZ |
7357 | /* |
7358 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7359 | * interrupts remain enabled. We used to check for that, but since it's | |
7360 | * gen-specific and since we only disable LCPLL after we fully disable | |
7361 | * the interrupts, the check below should be enough. | |
7362 | */ | |
7363 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7364 | } |
7365 | ||
3c4c9b81 PZ |
7366 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7367 | { | |
7368 | struct drm_device *dev = dev_priv->dev; | |
7369 | ||
7370 | if (IS_HASWELL(dev)) { | |
7371 | mutex_lock(&dev_priv->rps.hw_lock); | |
7372 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7373 | val)) | |
7374 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7375 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7376 | } else { | |
7377 | I915_WRITE(D_COMP, val); | |
7378 | } | |
7379 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7380 | } |
7381 | ||
7382 | /* | |
7383 | * This function implements pieces of two sequences from BSpec: | |
7384 | * - Sequence for display software to disable LCPLL | |
7385 | * - Sequence for display software to allow package C8+ | |
7386 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7387 | * register. Callers should take care of disabling all the display engine | |
7388 | * functions, doing the mode unset, fixing interrupts, etc. | |
7389 | */ | |
6ff58d53 PZ |
7390 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7391 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7392 | { |
7393 | uint32_t val; | |
7394 | ||
7395 | assert_can_disable_lcpll(dev_priv); | |
7396 | ||
7397 | val = I915_READ(LCPLL_CTL); | |
7398 | ||
7399 | if (switch_to_fclk) { | |
7400 | val |= LCPLL_CD_SOURCE_FCLK; | |
7401 | I915_WRITE(LCPLL_CTL, val); | |
7402 | ||
7403 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7404 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7405 | DRM_ERROR("Switching to FCLK failed\n"); | |
7406 | ||
7407 | val = I915_READ(LCPLL_CTL); | |
7408 | } | |
7409 | ||
7410 | val |= LCPLL_PLL_DISABLE; | |
7411 | I915_WRITE(LCPLL_CTL, val); | |
7412 | POSTING_READ(LCPLL_CTL); | |
7413 | ||
7414 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7415 | DRM_ERROR("LCPLL still locked\n"); | |
7416 | ||
7417 | val = I915_READ(D_COMP); | |
7418 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7419 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7420 | ndelay(100); |
7421 | ||
7422 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7423 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7424 | ||
7425 | if (allow_power_down) { | |
7426 | val = I915_READ(LCPLL_CTL); | |
7427 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7428 | I915_WRITE(LCPLL_CTL, val); | |
7429 | POSTING_READ(LCPLL_CTL); | |
7430 | } | |
7431 | } | |
7432 | ||
7433 | /* | |
7434 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7435 | * source. | |
7436 | */ | |
6ff58d53 | 7437 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7438 | { |
7439 | uint32_t val; | |
a8a8bd54 | 7440 | unsigned long irqflags; |
be256dc7 PZ |
7441 | |
7442 | val = I915_READ(LCPLL_CTL); | |
7443 | ||
7444 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7445 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7446 | return; | |
7447 | ||
a8a8bd54 PZ |
7448 | /* |
7449 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7450 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7451 | * | |
7452 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7453 | * the runtime PM resume sequence, so we can't just call | |
7454 | * gen6_gt_force_wake_get() because that function calls | |
7455 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7456 | * while we are on the resume sequence. So to solve this problem we have | |
7457 | * to call special forcewake code that doesn't touch runtime PM and | |
7458 | * doesn't enable the forcewake delayed work. | |
7459 | */ | |
7460 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7461 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7462 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7463 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7464 | |
be256dc7 PZ |
7465 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7466 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7467 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7468 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7469 | } |
7470 | ||
7471 | val = I915_READ(D_COMP); | |
7472 | val |= D_COMP_COMP_FORCE; | |
7473 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7474 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7475 | |
7476 | val = I915_READ(LCPLL_CTL); | |
7477 | val &= ~LCPLL_PLL_DISABLE; | |
7478 | I915_WRITE(LCPLL_CTL, val); | |
7479 | ||
7480 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7481 | DRM_ERROR("LCPLL not locked yet\n"); | |
7482 | ||
7483 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7484 | val = I915_READ(LCPLL_CTL); | |
7485 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7486 | I915_WRITE(LCPLL_CTL, val); | |
7487 | ||
7488 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7489 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7490 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7491 | } | |
215733fa | 7492 | |
a8a8bd54 PZ |
7493 | /* See the big comment above. */ |
7494 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7495 | if (--dev_priv->uncore.forcewake_count == 0) | |
7496 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7497 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7498 | } |
7499 | ||
765dab67 PZ |
7500 | /* |
7501 | * Package states C8 and deeper are really deep PC states that can only be | |
7502 | * reached when all the devices on the system allow it, so even if the graphics | |
7503 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7504 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7505 | * | |
7506 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7507 | * well is disabled and most interrupts are disabled, and these are also | |
7508 | * requirements for runtime PM. When these conditions are met, we manually do | |
7509 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7510 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7511 | * hang the machine. | |
7512 | * | |
7513 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7514 | * the state of some registers, so when we come back from PC8+ we need to | |
7515 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7516 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7517 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7518 | * because of the runtime PM support). | |
7519 | * | |
7520 | * For more, read "Display Sequences for Package C8" on the hardware | |
7521 | * documentation. | |
7522 | */ | |
a14cb6fc | 7523 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7524 | { |
c67a470b PZ |
7525 | struct drm_device *dev = dev_priv->dev; |
7526 | uint32_t val; | |
7527 | ||
c67a470b PZ |
7528 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7529 | ||
c67a470b PZ |
7530 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7531 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7532 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7533 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7534 | } | |
7535 | ||
7536 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7537 | hsw_disable_lcpll(dev_priv, true, true); |
7538 | } | |
7539 | ||
a14cb6fc | 7540 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7541 | { |
7542 | struct drm_device *dev = dev_priv->dev; | |
7543 | uint32_t val; | |
7544 | ||
c67a470b PZ |
7545 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7546 | ||
7547 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7548 | lpt_init_pch_refclk(dev); |
7549 | ||
7550 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7551 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7552 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7553 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7554 | } | |
7555 | ||
7556 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7557 | } |
7558 | ||
9a952a0d PZ |
7559 | static void snb_modeset_global_resources(struct drm_device *dev) |
7560 | { | |
7561 | modeset_update_crtc_power_domains(dev); | |
7562 | } | |
7563 | ||
4f074129 ID |
7564 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7565 | { | |
da723569 | 7566 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7567 | } |
7568 | ||
09b4ddf9 | 7569 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7570 | int x, int y, |
7571 | struct drm_framebuffer *fb) | |
7572 | { | |
09b4ddf9 | 7573 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7574 | |
566b734a | 7575 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7576 | return -EINVAL; |
566b734a | 7577 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7578 | |
644cef34 DV |
7579 | intel_crtc->lowfreq_avail = false; |
7580 | ||
c8f7a0db | 7581 | return 0; |
79e53945 JB |
7582 | } |
7583 | ||
0e8ffe1b DV |
7584 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7585 | struct intel_crtc_config *pipe_config) | |
7586 | { | |
7587 | struct drm_device *dev = crtc->base.dev; | |
7588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7589 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7590 | uint32_t tmp; |
7591 | ||
b5482bd0 ID |
7592 | if (!intel_display_power_enabled(dev_priv, |
7593 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7594 | return false; | |
7595 | ||
e143a21c | 7596 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7597 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7598 | ||
eccb140b DV |
7599 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7600 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7601 | enum pipe trans_edp_pipe; | |
7602 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7603 | default: | |
7604 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7605 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7606 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7607 | trans_edp_pipe = PIPE_A; | |
7608 | break; | |
7609 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7610 | trans_edp_pipe = PIPE_B; | |
7611 | break; | |
7612 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7613 | trans_edp_pipe = PIPE_C; | |
7614 | break; | |
7615 | } | |
7616 | ||
7617 | if (trans_edp_pipe == crtc->pipe) | |
7618 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7619 | } | |
7620 | ||
da7e29bd | 7621 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7622 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7623 | return false; |
7624 | ||
eccb140b | 7625 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7626 | if (!(tmp & PIPECONF_ENABLE)) |
7627 | return false; | |
7628 | ||
88adfff1 | 7629 | /* |
f196e6be | 7630 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7631 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7632 | * the PCH transcoder is on. | |
7633 | */ | |
eccb140b | 7634 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7635 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7636 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7637 | pipe_config->has_pch_encoder = true; |
7638 | ||
627eb5a3 DV |
7639 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7640 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7641 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7642 | |
7643 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7644 | } |
7645 | ||
1bd1bd80 DV |
7646 | intel_get_pipe_timings(crtc, pipe_config); |
7647 | ||
2fa2fe9a | 7648 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7649 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7650 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7651 | |
e59150dc JB |
7652 | if (IS_HASWELL(dev)) |
7653 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7654 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7655 | |
6c49f241 DV |
7656 | pipe_config->pixel_multiplier = 1; |
7657 | ||
0e8ffe1b DV |
7658 | return true; |
7659 | } | |
7660 | ||
1a91510d JN |
7661 | static struct { |
7662 | int clock; | |
7663 | u32 config; | |
7664 | } hdmi_audio_clock[] = { | |
7665 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7666 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7667 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7668 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7669 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7670 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7671 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7672 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7673 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7674 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7675 | }; | |
7676 | ||
7677 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7678 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7679 | { | |
7680 | int i; | |
7681 | ||
7682 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7683 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7684 | break; | |
7685 | } | |
7686 | ||
7687 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7688 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7689 | i = 1; | |
7690 | } | |
7691 | ||
7692 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7693 | hdmi_audio_clock[i].clock, | |
7694 | hdmi_audio_clock[i].config); | |
7695 | ||
7696 | return hdmi_audio_clock[i].config; | |
7697 | } | |
7698 | ||
3a9627f4 WF |
7699 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7700 | int reg_eldv, uint32_t bits_eldv, | |
7701 | int reg_elda, uint32_t bits_elda, | |
7702 | int reg_edid) | |
7703 | { | |
7704 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7705 | uint8_t *eld = connector->eld; | |
7706 | uint32_t i; | |
7707 | ||
7708 | i = I915_READ(reg_eldv); | |
7709 | i &= bits_eldv; | |
7710 | ||
7711 | if (!eld[0]) | |
7712 | return !i; | |
7713 | ||
7714 | if (!i) | |
7715 | return false; | |
7716 | ||
7717 | i = I915_READ(reg_elda); | |
7718 | i &= ~bits_elda; | |
7719 | I915_WRITE(reg_elda, i); | |
7720 | ||
7721 | for (i = 0; i < eld[2]; i++) | |
7722 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7723 | return false; | |
7724 | ||
7725 | return true; | |
7726 | } | |
7727 | ||
e0dac65e | 7728 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7729 | struct drm_crtc *crtc, |
7730 | struct drm_display_mode *mode) | |
e0dac65e WF |
7731 | { |
7732 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7733 | uint8_t *eld = connector->eld; | |
7734 | uint32_t eldv; | |
7735 | uint32_t len; | |
7736 | uint32_t i; | |
7737 | ||
7738 | i = I915_READ(G4X_AUD_VID_DID); | |
7739 | ||
7740 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7741 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7742 | else | |
7743 | eldv = G4X_ELDV_DEVCTG; | |
7744 | ||
3a9627f4 WF |
7745 | if (intel_eld_uptodate(connector, |
7746 | G4X_AUD_CNTL_ST, eldv, | |
7747 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7748 | G4X_HDMIW_HDMIEDID)) | |
7749 | return; | |
7750 | ||
e0dac65e WF |
7751 | i = I915_READ(G4X_AUD_CNTL_ST); |
7752 | i &= ~(eldv | G4X_ELD_ADDR); | |
7753 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7754 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7755 | ||
7756 | if (!eld[0]) | |
7757 | return; | |
7758 | ||
7759 | len = min_t(uint8_t, eld[2], len); | |
7760 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7761 | for (i = 0; i < len; i++) | |
7762 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7763 | ||
7764 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7765 | i |= eldv; | |
7766 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7767 | } | |
7768 | ||
83358c85 | 7769 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7770 | struct drm_crtc *crtc, |
7771 | struct drm_display_mode *mode) | |
83358c85 WX |
7772 | { |
7773 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7774 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7775 | uint32_t eldv; |
7776 | uint32_t i; | |
7777 | int len; | |
7778 | int pipe = to_intel_crtc(crtc)->pipe; | |
7779 | int tmp; | |
7780 | ||
7781 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7782 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7783 | int aud_config = HSW_AUD_CFG(pipe); | |
7784 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7785 | ||
83358c85 WX |
7786 | /* Audio output enable */ |
7787 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7788 | tmp = I915_READ(aud_cntrl_st2); | |
7789 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7790 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7791 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7792 | |
c7905792 | 7793 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7794 | |
7795 | /* Set ELD valid state */ | |
7796 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7797 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7798 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7799 | I915_WRITE(aud_cntrl_st2, tmp); | |
7800 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7801 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7802 | |
7803 | /* Enable HDMI mode */ | |
7804 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7805 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7806 | /* clear N_programing_enable and N_value_index */ |
7807 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7808 | I915_WRITE(aud_config, tmp); | |
7809 | ||
7810 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7811 | ||
7812 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7813 | ||
7814 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7815 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7816 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7817 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7818 | } else { |
7819 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7820 | } | |
83358c85 WX |
7821 | |
7822 | if (intel_eld_uptodate(connector, | |
7823 | aud_cntrl_st2, eldv, | |
7824 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7825 | hdmiw_hdmiedid)) | |
7826 | return; | |
7827 | ||
7828 | i = I915_READ(aud_cntrl_st2); | |
7829 | i &= ~eldv; | |
7830 | I915_WRITE(aud_cntrl_st2, i); | |
7831 | ||
7832 | if (!eld[0]) | |
7833 | return; | |
7834 | ||
7835 | i = I915_READ(aud_cntl_st); | |
7836 | i &= ~IBX_ELD_ADDRESS; | |
7837 | I915_WRITE(aud_cntl_st, i); | |
7838 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7839 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7840 | ||
7841 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7842 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7843 | for (i = 0; i < len; i++) | |
7844 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7845 | ||
7846 | i = I915_READ(aud_cntrl_st2); | |
7847 | i |= eldv; | |
7848 | I915_WRITE(aud_cntrl_st2, i); | |
7849 | ||
7850 | } | |
7851 | ||
e0dac65e | 7852 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7853 | struct drm_crtc *crtc, |
7854 | struct drm_display_mode *mode) | |
e0dac65e WF |
7855 | { |
7856 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7857 | uint8_t *eld = connector->eld; | |
7858 | uint32_t eldv; | |
7859 | uint32_t i; | |
7860 | int len; | |
7861 | int hdmiw_hdmiedid; | |
b6daa025 | 7862 | int aud_config; |
e0dac65e WF |
7863 | int aud_cntl_st; |
7864 | int aud_cntrl_st2; | |
9b138a83 | 7865 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7866 | |
b3f33cbf | 7867 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7868 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7869 | aud_config = IBX_AUD_CFG(pipe); | |
7870 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7871 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7872 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7873 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7874 | aud_config = VLV_AUD_CFG(pipe); | |
7875 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7876 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7877 | } else { |
9b138a83 WX |
7878 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7879 | aud_config = CPT_AUD_CFG(pipe); | |
7880 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7881 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7882 | } |
7883 | ||
9b138a83 | 7884 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7885 | |
9ca2fe73 ML |
7886 | if (IS_VALLEYVIEW(connector->dev)) { |
7887 | struct intel_encoder *intel_encoder; | |
7888 | struct intel_digital_port *intel_dig_port; | |
7889 | ||
7890 | intel_encoder = intel_attached_encoder(connector); | |
7891 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7892 | i = intel_dig_port->port; | |
7893 | } else { | |
7894 | i = I915_READ(aud_cntl_st); | |
7895 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7896 | /* DIP_Port_Select, 0x1 = PortB */ | |
7897 | } | |
7898 | ||
e0dac65e WF |
7899 | if (!i) { |
7900 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7901 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7902 | eldv = IBX_ELD_VALIDB; |
7903 | eldv |= IBX_ELD_VALIDB << 4; | |
7904 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7905 | } else { |
2582a850 | 7906 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7907 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7908 | } |
7909 | ||
3a9627f4 WF |
7910 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7911 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7912 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7913 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7914 | } else { |
7915 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7916 | } | |
e0dac65e | 7917 | |
3a9627f4 WF |
7918 | if (intel_eld_uptodate(connector, |
7919 | aud_cntrl_st2, eldv, | |
7920 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7921 | hdmiw_hdmiedid)) | |
7922 | return; | |
7923 | ||
e0dac65e WF |
7924 | i = I915_READ(aud_cntrl_st2); |
7925 | i &= ~eldv; | |
7926 | I915_WRITE(aud_cntrl_st2, i); | |
7927 | ||
7928 | if (!eld[0]) | |
7929 | return; | |
7930 | ||
e0dac65e | 7931 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7932 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7933 | I915_WRITE(aud_cntl_st, i); |
7934 | ||
7935 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7936 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7937 | for (i = 0; i < len; i++) | |
7938 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7939 | ||
7940 | i = I915_READ(aud_cntrl_st2); | |
7941 | i |= eldv; | |
7942 | I915_WRITE(aud_cntrl_st2, i); | |
7943 | } | |
7944 | ||
7945 | void intel_write_eld(struct drm_encoder *encoder, | |
7946 | struct drm_display_mode *mode) | |
7947 | { | |
7948 | struct drm_crtc *crtc = encoder->crtc; | |
7949 | struct drm_connector *connector; | |
7950 | struct drm_device *dev = encoder->dev; | |
7951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7952 | ||
7953 | connector = drm_select_eld(encoder, mode); | |
7954 | if (!connector) | |
7955 | return; | |
7956 | ||
7957 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7958 | connector->base.id, | |
c23cc417 | 7959 | connector->name, |
e0dac65e | 7960 | connector->encoder->base.id, |
8e329a03 | 7961 | connector->encoder->name); |
e0dac65e WF |
7962 | |
7963 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7964 | ||
7965 | if (dev_priv->display.write_eld) | |
34427052 | 7966 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7967 | } |
7968 | ||
560b85bb CW |
7969 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7970 | { | |
7971 | struct drm_device *dev = crtc->dev; | |
7972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4b0e333e | 7974 | uint32_t cntl; |
560b85bb | 7975 | |
4b0e333e | 7976 | if (base != intel_crtc->cursor_base) { |
560b85bb CW |
7977 | /* On these chipsets we can only modify the base whilst |
7978 | * the cursor is disabled. | |
7979 | */ | |
4b0e333e CW |
7980 | if (intel_crtc->cursor_cntl) { |
7981 | I915_WRITE(_CURACNTR, 0); | |
7982 | POSTING_READ(_CURACNTR); | |
7983 | intel_crtc->cursor_cntl = 0; | |
7984 | } | |
7985 | ||
9db4a9c7 | 7986 | I915_WRITE(_CURABASE, base); |
4b0e333e CW |
7987 | POSTING_READ(_CURABASE); |
7988 | } | |
560b85bb | 7989 | |
4b0e333e CW |
7990 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
7991 | cntl = 0; | |
7992 | if (base) | |
7993 | cntl = (CURSOR_ENABLE | | |
560b85bb | 7994 | CURSOR_GAMMA_ENABLE | |
4b0e333e CW |
7995 | CURSOR_FORMAT_ARGB); |
7996 | if (intel_crtc->cursor_cntl != cntl) { | |
7997 | I915_WRITE(_CURACNTR, cntl); | |
7998 | POSTING_READ(_CURACNTR); | |
7999 | intel_crtc->cursor_cntl = cntl; | |
8000 | } | |
560b85bb CW |
8001 | } |
8002 | ||
8003 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
8004 | { | |
8005 | struct drm_device *dev = crtc->dev; | |
8006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8008 | int pipe = intel_crtc->pipe; | |
4b0e333e | 8009 | uint32_t cntl; |
4726e0b0 | 8010 | |
4b0e333e CW |
8011 | cntl = 0; |
8012 | if (base) { | |
8013 | cntl = MCURSOR_GAMMA_ENABLE; | |
8014 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8015 | case 64: |
8016 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8017 | break; | |
8018 | case 128: | |
8019 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8020 | break; | |
8021 | case 256: | |
8022 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8023 | break; | |
8024 | default: | |
8025 | WARN_ON(1); | |
8026 | return; | |
560b85bb | 8027 | } |
4b0e333e CW |
8028 | cntl |= pipe << 28; /* Connect to correct pipe */ |
8029 | } | |
8030 | if (intel_crtc->cursor_cntl != cntl) { | |
9db4a9c7 | 8031 | I915_WRITE(CURCNTR(pipe), cntl); |
4b0e333e CW |
8032 | POSTING_READ(CURCNTR(pipe)); |
8033 | intel_crtc->cursor_cntl = cntl; | |
560b85bb | 8034 | } |
4b0e333e | 8035 | |
560b85bb | 8036 | /* and commit changes on next vblank */ |
9db4a9c7 | 8037 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 8038 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
8039 | } |
8040 | ||
65a21cd6 JB |
8041 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8042 | { | |
8043 | struct drm_device *dev = crtc->dev; | |
8044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8046 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8047 | uint32_t cntl; |
8048 | ||
8049 | cntl = 0; | |
8050 | if (base) { | |
8051 | cntl = MCURSOR_GAMMA_ENABLE; | |
8052 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8053 | case 64: |
8054 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8055 | break; | |
8056 | case 128: | |
8057 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8058 | break; | |
8059 | case 256: | |
8060 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8061 | break; | |
8062 | default: | |
8063 | WARN_ON(1); | |
8064 | return; | |
65a21cd6 | 8065 | } |
4b0e333e CW |
8066 | } |
8067 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8068 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8069 | |
4b0e333e CW |
8070 | if (intel_crtc->cursor_cntl != cntl) { |
8071 | I915_WRITE(CURCNTR(pipe), cntl); | |
8072 | POSTING_READ(CURCNTR(pipe)); | |
8073 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8074 | } |
4b0e333e | 8075 | |
65a21cd6 | 8076 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8077 | I915_WRITE(CURBASE(pipe), base); |
8078 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8079 | } |
8080 | ||
cda4b7d3 | 8081 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8082 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8083 | bool on) | |
cda4b7d3 CW |
8084 | { |
8085 | struct drm_device *dev = crtc->dev; | |
8086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8088 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8089 | int x = crtc->cursor_x; |
8090 | int y = crtc->cursor_y; | |
d6e4db15 | 8091 | u32 base = 0, pos = 0; |
cda4b7d3 | 8092 | |
d6e4db15 | 8093 | if (on) |
cda4b7d3 | 8094 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8095 | |
d6e4db15 VS |
8096 | if (x >= intel_crtc->config.pipe_src_w) |
8097 | base = 0; | |
8098 | ||
8099 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8100 | base = 0; |
8101 | ||
8102 | if (x < 0) { | |
efc9064e | 8103 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8104 | base = 0; |
8105 | ||
8106 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8107 | x = -x; | |
8108 | } | |
8109 | pos |= x << CURSOR_X_SHIFT; | |
8110 | ||
8111 | if (y < 0) { | |
efc9064e | 8112 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8113 | base = 0; |
8114 | ||
8115 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8116 | y = -y; | |
8117 | } | |
8118 | pos |= y << CURSOR_Y_SHIFT; | |
8119 | ||
4b0e333e | 8120 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8121 | return; |
8122 | ||
5efb3e28 VS |
8123 | I915_WRITE(CURPOS(pipe), pos); |
8124 | ||
8125 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8126 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8127 | else if (IS_845G(dev) || IS_I865G(dev)) |
8128 | i845_update_cursor(crtc, base); | |
8129 | else | |
8130 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8131 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8132 | } |
8133 | ||
e3287951 MR |
8134 | /* |
8135 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8136 | * | |
8137 | * Note that the object's reference will be consumed if the update fails. If | |
8138 | * the update succeeds, the reference of the old object (if any) will be | |
8139 | * consumed. | |
8140 | */ | |
8141 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8142 | struct drm_i915_gem_object *obj, | |
8143 | uint32_t width, uint32_t height) | |
79e53945 JB |
8144 | { |
8145 | struct drm_device *dev = crtc->dev; | |
8146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
a071fa00 | 8148 | enum pipe pipe = intel_crtc->pipe; |
64f962e3 | 8149 | unsigned old_width; |
cda4b7d3 | 8150 | uint32_t addr; |
3f8bc370 | 8151 | int ret; |
79e53945 | 8152 | |
79e53945 | 8153 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8154 | if (!obj) { |
28c97730 | 8155 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8156 | addr = 0; |
05394f39 | 8157 | obj = NULL; |
5004417d | 8158 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8159 | goto finish; |
79e53945 JB |
8160 | } |
8161 | ||
4726e0b0 SK |
8162 | /* Check for which cursor types we support */ |
8163 | if (!((width == 64 && height == 64) || | |
8164 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8165 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8166 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8167 | return -EINVAL; |
8168 | } | |
8169 | ||
05394f39 | 8170 | if (obj->base.size < width * height * 4) { |
e3287951 | 8171 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8172 | ret = -ENOMEM; |
8173 | goto fail; | |
79e53945 JB |
8174 | } |
8175 | ||
71acb5eb | 8176 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8177 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8178 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8179 | unsigned alignment; |
8180 | ||
d9e86c0e | 8181 | if (obj->tiling_mode) { |
3b25b31f | 8182 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8183 | ret = -EINVAL; |
8184 | goto fail_locked; | |
8185 | } | |
8186 | ||
693db184 CW |
8187 | /* Note that the w/a also requires 2 PTE of padding following |
8188 | * the bo. We currently fill all unused PTE with the shadow | |
8189 | * page and so we should always have valid PTE following the | |
8190 | * cursor preventing the VT-d warning. | |
8191 | */ | |
8192 | alignment = 0; | |
8193 | if (need_vtd_wa(dev)) | |
8194 | alignment = 64*1024; | |
8195 | ||
8196 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8197 | if (ret) { |
3b25b31f | 8198 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8199 | goto fail_locked; |
e7b526bb CW |
8200 | } |
8201 | ||
d9e86c0e CW |
8202 | ret = i915_gem_object_put_fence(obj); |
8203 | if (ret) { | |
3b25b31f | 8204 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8205 | goto fail_unpin; |
8206 | } | |
8207 | ||
f343c5f6 | 8208 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8209 | } else { |
6eeefaf3 | 8210 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8211 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8212 | if (ret) { |
3b25b31f | 8213 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8214 | goto fail_locked; |
71acb5eb | 8215 | } |
00731155 | 8216 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8217 | } |
8218 | ||
a6c45cf0 | 8219 | if (IS_GEN2(dev)) |
14b60391 JB |
8220 | I915_WRITE(CURSIZE, (height << 12) | width); |
8221 | ||
3f8bc370 | 8222 | finish: |
3f8bc370 | 8223 | if (intel_crtc->cursor_bo) { |
00731155 | 8224 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8225 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8226 | } |
80824003 | 8227 | |
a071fa00 DV |
8228 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8229 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8230 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8231 | |
64f962e3 CW |
8232 | old_width = intel_crtc->cursor_width; |
8233 | ||
3f8bc370 | 8234 | intel_crtc->cursor_addr = addr; |
05394f39 | 8235 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8236 | intel_crtc->cursor_width = width; |
8237 | intel_crtc->cursor_height = height; | |
8238 | ||
64f962e3 CW |
8239 | if (intel_crtc->active) { |
8240 | if (old_width != width) | |
8241 | intel_update_watermarks(crtc); | |
f2f5f771 | 8242 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8243 | } |
3f8bc370 | 8244 | |
f99d7069 DV |
8245 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8246 | ||
79e53945 | 8247 | return 0; |
e7b526bb | 8248 | fail_unpin: |
cc98b413 | 8249 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8250 | fail_locked: |
34b8686e | 8251 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8252 | fail: |
05394f39 | 8253 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8254 | return ret; |
79e53945 JB |
8255 | } |
8256 | ||
79e53945 | 8257 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8258 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8259 | { |
7203425a | 8260 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8261 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8262 | |
7203425a | 8263 | for (i = start; i < end; i++) { |
79e53945 JB |
8264 | intel_crtc->lut_r[i] = red[i] >> 8; |
8265 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8266 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8267 | } | |
8268 | ||
8269 | intel_crtc_load_lut(crtc); | |
8270 | } | |
8271 | ||
79e53945 JB |
8272 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8273 | static struct drm_display_mode load_detect_mode = { | |
8274 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8275 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8276 | }; | |
8277 | ||
a8bb6818 DV |
8278 | struct drm_framebuffer * |
8279 | __intel_framebuffer_create(struct drm_device *dev, | |
8280 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8281 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8282 | { |
8283 | struct intel_framebuffer *intel_fb; | |
8284 | int ret; | |
8285 | ||
8286 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8287 | if (!intel_fb) { | |
8288 | drm_gem_object_unreference_unlocked(&obj->base); | |
8289 | return ERR_PTR(-ENOMEM); | |
8290 | } | |
8291 | ||
8292 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8293 | if (ret) |
8294 | goto err; | |
d2dff872 CW |
8295 | |
8296 | return &intel_fb->base; | |
dd4916c5 DV |
8297 | err: |
8298 | drm_gem_object_unreference_unlocked(&obj->base); | |
8299 | kfree(intel_fb); | |
8300 | ||
8301 | return ERR_PTR(ret); | |
d2dff872 CW |
8302 | } |
8303 | ||
b5ea642a | 8304 | static struct drm_framebuffer * |
a8bb6818 DV |
8305 | intel_framebuffer_create(struct drm_device *dev, |
8306 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8307 | struct drm_i915_gem_object *obj) | |
8308 | { | |
8309 | struct drm_framebuffer *fb; | |
8310 | int ret; | |
8311 | ||
8312 | ret = i915_mutex_lock_interruptible(dev); | |
8313 | if (ret) | |
8314 | return ERR_PTR(ret); | |
8315 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8316 | mutex_unlock(&dev->struct_mutex); | |
8317 | ||
8318 | return fb; | |
8319 | } | |
8320 | ||
d2dff872 CW |
8321 | static u32 |
8322 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8323 | { | |
8324 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8325 | return ALIGN(pitch, 64); | |
8326 | } | |
8327 | ||
8328 | static u32 | |
8329 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8330 | { | |
8331 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8332 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8333 | } |
8334 | ||
8335 | static struct drm_framebuffer * | |
8336 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8337 | struct drm_display_mode *mode, | |
8338 | int depth, int bpp) | |
8339 | { | |
8340 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8341 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8342 | |
8343 | obj = i915_gem_alloc_object(dev, | |
8344 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8345 | if (obj == NULL) | |
8346 | return ERR_PTR(-ENOMEM); | |
8347 | ||
8348 | mode_cmd.width = mode->hdisplay; | |
8349 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8350 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8351 | bpp); | |
5ca0c34a | 8352 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8353 | |
8354 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8355 | } | |
8356 | ||
8357 | static struct drm_framebuffer * | |
8358 | mode_fits_in_fbdev(struct drm_device *dev, | |
8359 | struct drm_display_mode *mode) | |
8360 | { | |
4520f53a | 8361 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8362 | struct drm_i915_private *dev_priv = dev->dev_private; |
8363 | struct drm_i915_gem_object *obj; | |
8364 | struct drm_framebuffer *fb; | |
8365 | ||
4c0e5528 | 8366 | if (!dev_priv->fbdev) |
d2dff872 CW |
8367 | return NULL; |
8368 | ||
4c0e5528 | 8369 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8370 | return NULL; |
8371 | ||
4c0e5528 DV |
8372 | obj = dev_priv->fbdev->fb->obj; |
8373 | BUG_ON(!obj); | |
8374 | ||
8bcd4553 | 8375 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8376 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8377 | fb->bits_per_pixel)) | |
d2dff872 CW |
8378 | return NULL; |
8379 | ||
01f2c773 | 8380 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8381 | return NULL; |
8382 | ||
8383 | return fb; | |
4520f53a DV |
8384 | #else |
8385 | return NULL; | |
8386 | #endif | |
d2dff872 CW |
8387 | } |
8388 | ||
d2434ab7 | 8389 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8390 | struct drm_display_mode *mode, |
51fd371b RC |
8391 | struct intel_load_detect_pipe *old, |
8392 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8393 | { |
8394 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8395 | struct intel_encoder *intel_encoder = |
8396 | intel_attached_encoder(connector); | |
79e53945 | 8397 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8398 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8399 | struct drm_crtc *crtc = NULL; |
8400 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8401 | struct drm_framebuffer *fb; |
51fd371b RC |
8402 | struct drm_mode_config *config = &dev->mode_config; |
8403 | int ret, i = -1; | |
79e53945 | 8404 | |
d2dff872 | 8405 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8406 | connector->base.id, connector->name, |
8e329a03 | 8407 | encoder->base.id, encoder->name); |
d2dff872 | 8408 | |
51fd371b RC |
8409 | drm_modeset_acquire_init(ctx, 0); |
8410 | ||
8411 | retry: | |
8412 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8413 | if (ret) | |
8414 | goto fail_unlock; | |
6e9f798d | 8415 | |
79e53945 JB |
8416 | /* |
8417 | * Algorithm gets a little messy: | |
7a5e4805 | 8418 | * |
79e53945 JB |
8419 | * - if the connector already has an assigned crtc, use it (but make |
8420 | * sure it's on first) | |
7a5e4805 | 8421 | * |
79e53945 JB |
8422 | * - try to find the first unused crtc that can drive this connector, |
8423 | * and use that if we find one | |
79e53945 JB |
8424 | */ |
8425 | ||
8426 | /* See if we already have a CRTC for this connector */ | |
8427 | if (encoder->crtc) { | |
8428 | crtc = encoder->crtc; | |
8261b191 | 8429 | |
51fd371b RC |
8430 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8431 | if (ret) | |
8432 | goto fail_unlock; | |
7b24056b | 8433 | |
24218aac | 8434 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8435 | old->load_detect_temp = false; |
8436 | ||
8437 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8438 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8439 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8440 | |
7173188d | 8441 | return true; |
79e53945 JB |
8442 | } |
8443 | ||
8444 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8445 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8446 | i++; |
8447 | if (!(encoder->possible_crtcs & (1 << i))) | |
8448 | continue; | |
8449 | if (!possible_crtc->enabled) { | |
8450 | crtc = possible_crtc; | |
8451 | break; | |
8452 | } | |
79e53945 JB |
8453 | } |
8454 | ||
8455 | /* | |
8456 | * If we didn't find an unused CRTC, don't use any. | |
8457 | */ | |
8458 | if (!crtc) { | |
7173188d | 8459 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8460 | goto fail_unlock; |
79e53945 JB |
8461 | } |
8462 | ||
51fd371b RC |
8463 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8464 | if (ret) | |
8465 | goto fail_unlock; | |
fc303101 DV |
8466 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8467 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8468 | |
8469 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8470 | intel_crtc->new_enabled = true; |
8471 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8472 | old->dpms_mode = connector->dpms; |
8261b191 | 8473 | old->load_detect_temp = true; |
d2dff872 | 8474 | old->release_fb = NULL; |
79e53945 | 8475 | |
6492711d CW |
8476 | if (!mode) |
8477 | mode = &load_detect_mode; | |
79e53945 | 8478 | |
d2dff872 CW |
8479 | /* We need a framebuffer large enough to accommodate all accesses |
8480 | * that the plane may generate whilst we perform load detection. | |
8481 | * We can not rely on the fbcon either being present (we get called | |
8482 | * during its initialisation to detect all boot displays, or it may | |
8483 | * not even exist) or that it is large enough to satisfy the | |
8484 | * requested mode. | |
8485 | */ | |
94352cf9 DV |
8486 | fb = mode_fits_in_fbdev(dev, mode); |
8487 | if (fb == NULL) { | |
d2dff872 | 8488 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8489 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8490 | old->release_fb = fb; | |
d2dff872 CW |
8491 | } else |
8492 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8493 | if (IS_ERR(fb)) { |
d2dff872 | 8494 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8495 | goto fail; |
79e53945 | 8496 | } |
79e53945 | 8497 | |
c0c36b94 | 8498 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8499 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8500 | if (old->release_fb) |
8501 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8502 | goto fail; |
79e53945 | 8503 | } |
7173188d | 8504 | |
79e53945 | 8505 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8506 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8507 | return true; |
412b61d8 VS |
8508 | |
8509 | fail: | |
8510 | intel_crtc->new_enabled = crtc->enabled; | |
8511 | if (intel_crtc->new_enabled) | |
8512 | intel_crtc->new_config = &intel_crtc->config; | |
8513 | else | |
8514 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8515 | fail_unlock: |
8516 | if (ret == -EDEADLK) { | |
8517 | drm_modeset_backoff(ctx); | |
8518 | goto retry; | |
8519 | } | |
8520 | ||
8521 | drm_modeset_drop_locks(ctx); | |
8522 | drm_modeset_acquire_fini(ctx); | |
6e9f798d | 8523 | |
412b61d8 | 8524 | return false; |
79e53945 JB |
8525 | } |
8526 | ||
d2434ab7 | 8527 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
51fd371b RC |
8528 | struct intel_load_detect_pipe *old, |
8529 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 8530 | { |
d2434ab7 DV |
8531 | struct intel_encoder *intel_encoder = |
8532 | intel_attached_encoder(connector); | |
4ef69c7a | 8533 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8534 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8535 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8536 | |
d2dff872 | 8537 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8538 | connector->base.id, connector->name, |
8e329a03 | 8539 | encoder->base.id, encoder->name); |
d2dff872 | 8540 | |
8261b191 | 8541 | if (old->load_detect_temp) { |
fc303101 DV |
8542 | to_intel_connector(connector)->new_encoder = NULL; |
8543 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8544 | intel_crtc->new_enabled = false; |
8545 | intel_crtc->new_config = NULL; | |
fc303101 | 8546 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8547 | |
36206361 DV |
8548 | if (old->release_fb) { |
8549 | drm_framebuffer_unregister_private(old->release_fb); | |
8550 | drm_framebuffer_unreference(old->release_fb); | |
8551 | } | |
d2dff872 | 8552 | |
51fd371b | 8553 | goto unlock; |
0622a53c | 8554 | return; |
79e53945 JB |
8555 | } |
8556 | ||
c751ce4f | 8557 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8558 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8559 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b | 8560 | |
51fd371b RC |
8561 | unlock: |
8562 | drm_modeset_drop_locks(ctx); | |
8563 | drm_modeset_acquire_fini(ctx); | |
79e53945 JB |
8564 | } |
8565 | ||
da4a1efa VS |
8566 | static int i9xx_pll_refclk(struct drm_device *dev, |
8567 | const struct intel_crtc_config *pipe_config) | |
8568 | { | |
8569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8570 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8571 | ||
8572 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8573 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8574 | else if (HAS_PCH_SPLIT(dev)) |
8575 | return 120000; | |
8576 | else if (!IS_GEN2(dev)) | |
8577 | return 96000; | |
8578 | else | |
8579 | return 48000; | |
8580 | } | |
8581 | ||
79e53945 | 8582 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8583 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8584 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8585 | { |
f1f644dc | 8586 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8587 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8588 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8589 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8590 | u32 fp; |
8591 | intel_clock_t clock; | |
da4a1efa | 8592 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8593 | |
8594 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8595 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8596 | else |
293623f7 | 8597 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8598 | |
8599 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8600 | if (IS_PINEVIEW(dev)) { |
8601 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8602 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8603 | } else { |
8604 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8605 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8606 | } | |
8607 | ||
a6c45cf0 | 8608 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8609 | if (IS_PINEVIEW(dev)) |
8610 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8611 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8612 | else |
8613 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8614 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8615 | ||
8616 | switch (dpll & DPLL_MODE_MASK) { | |
8617 | case DPLLB_MODE_DAC_SERIAL: | |
8618 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8619 | 5 : 10; | |
8620 | break; | |
8621 | case DPLLB_MODE_LVDS: | |
8622 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8623 | 7 : 14; | |
8624 | break; | |
8625 | default: | |
28c97730 | 8626 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8627 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8628 | return; |
79e53945 JB |
8629 | } |
8630 | ||
ac58c3f0 | 8631 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8632 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8633 | else |
da4a1efa | 8634 | i9xx_clock(refclk, &clock); |
79e53945 | 8635 | } else { |
0fb58223 | 8636 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8637 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8638 | |
8639 | if (is_lvds) { | |
8640 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8641 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8642 | |
8643 | if (lvds & LVDS_CLKB_POWER_UP) | |
8644 | clock.p2 = 7; | |
8645 | else | |
8646 | clock.p2 = 14; | |
79e53945 JB |
8647 | } else { |
8648 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8649 | clock.p1 = 2; | |
8650 | else { | |
8651 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8652 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8653 | } | |
8654 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8655 | clock.p2 = 4; | |
8656 | else | |
8657 | clock.p2 = 2; | |
79e53945 | 8658 | } |
da4a1efa VS |
8659 | |
8660 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8661 | } |
8662 | ||
18442d08 VS |
8663 | /* |
8664 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8665 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8666 | * encoder's get_config() function. |
8667 | */ | |
8668 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8669 | } |
8670 | ||
6878da05 VS |
8671 | int intel_dotclock_calculate(int link_freq, |
8672 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8673 | { |
f1f644dc JB |
8674 | /* |
8675 | * The calculation for the data clock is: | |
1041a02f | 8676 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8677 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8678 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8679 | * |
8680 | * and the link clock is simpler: | |
1041a02f | 8681 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8682 | */ |
8683 | ||
6878da05 VS |
8684 | if (!m_n->link_n) |
8685 | return 0; | |
f1f644dc | 8686 | |
6878da05 VS |
8687 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8688 | } | |
f1f644dc | 8689 | |
18442d08 VS |
8690 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8691 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8692 | { |
8693 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8694 | |
18442d08 VS |
8695 | /* read out port_clock from the DPLL */ |
8696 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8697 | |
f1f644dc | 8698 | /* |
18442d08 | 8699 | * This value does not include pixel_multiplier. |
241bfc38 | 8700 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8701 | * agree once we know their relationship in the encoder's |
8702 | * get_config() function. | |
79e53945 | 8703 | */ |
241bfc38 | 8704 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8705 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8706 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8707 | } |
8708 | ||
8709 | /** Returns the currently programmed mode of the given pipe. */ | |
8710 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8711 | struct drm_crtc *crtc) | |
8712 | { | |
548f245b | 8713 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8714 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8715 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8716 | struct drm_display_mode *mode; |
f1f644dc | 8717 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8718 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8719 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8720 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8721 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8722 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8723 | |
8724 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8725 | if (!mode) | |
8726 | return NULL; | |
8727 | ||
f1f644dc JB |
8728 | /* |
8729 | * Construct a pipe_config sufficient for getting the clock info | |
8730 | * back out of crtc_clock_get. | |
8731 | * | |
8732 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8733 | * to use a real value here instead. | |
8734 | */ | |
293623f7 | 8735 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8736 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8737 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8738 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8739 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8740 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8741 | ||
773ae034 | 8742 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8743 | mode->hdisplay = (htot & 0xffff) + 1; |
8744 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8745 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8746 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8747 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8748 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8749 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8750 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8751 | ||
8752 | drm_mode_set_name(mode); | |
79e53945 JB |
8753 | |
8754 | return mode; | |
8755 | } | |
8756 | ||
cc36513c DV |
8757 | static void intel_increase_pllclock(struct drm_device *dev, |
8758 | enum pipe pipe) | |
652c393a | 8759 | { |
fbee40df | 8760 | struct drm_i915_private *dev_priv = dev->dev_private; |
dbdc6479 JB |
8761 | int dpll_reg = DPLL(pipe); |
8762 | int dpll; | |
652c393a | 8763 | |
bad720ff | 8764 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8765 | return; |
8766 | ||
8767 | if (!dev_priv->lvds_downclock_avail) | |
8768 | return; | |
8769 | ||
dbdc6479 | 8770 | dpll = I915_READ(dpll_reg); |
652c393a | 8771 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8772 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8773 | |
8ac5a6d5 | 8774 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8775 | |
8776 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8777 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8778 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8779 | |
652c393a JB |
8780 | dpll = I915_READ(dpll_reg); |
8781 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8782 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8783 | } |
652c393a JB |
8784 | } |
8785 | ||
8786 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8787 | { | |
8788 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8789 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8791 | |
bad720ff | 8792 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8793 | return; |
8794 | ||
8795 | if (!dev_priv->lvds_downclock_avail) | |
8796 | return; | |
8797 | ||
8798 | /* | |
8799 | * Since this is called by a timer, we should never get here in | |
8800 | * the manual case. | |
8801 | */ | |
8802 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8803 | int pipe = intel_crtc->pipe; |
8804 | int dpll_reg = DPLL(pipe); | |
8805 | int dpll; | |
f6e5b160 | 8806 | |
44d98a61 | 8807 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8808 | |
8ac5a6d5 | 8809 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8810 | |
dc257cf1 | 8811 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8812 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8813 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8814 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8815 | dpll = I915_READ(dpll_reg); |
8816 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8817 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8818 | } |
8819 | ||
8820 | } | |
8821 | ||
f047e395 CW |
8822 | void intel_mark_busy(struct drm_device *dev) |
8823 | { | |
c67a470b PZ |
8824 | struct drm_i915_private *dev_priv = dev->dev_private; |
8825 | ||
f62a0076 CW |
8826 | if (dev_priv->mm.busy) |
8827 | return; | |
8828 | ||
43694d69 | 8829 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8830 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8831 | dev_priv->mm.busy = true; |
f047e395 CW |
8832 | } |
8833 | ||
8834 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8835 | { |
c67a470b | 8836 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8837 | struct drm_crtc *crtc; |
652c393a | 8838 | |
f62a0076 CW |
8839 | if (!dev_priv->mm.busy) |
8840 | return; | |
8841 | ||
8842 | dev_priv->mm.busy = false; | |
8843 | ||
d330a953 | 8844 | if (!i915.powersave) |
bb4cdd53 | 8845 | goto out; |
652c393a | 8846 | |
70e1e0ec | 8847 | for_each_crtc(dev, crtc) { |
f4510a27 | 8848 | if (!crtc->primary->fb) |
652c393a JB |
8849 | continue; |
8850 | ||
725a5b54 | 8851 | intel_decrease_pllclock(crtc); |
652c393a | 8852 | } |
b29c19b6 | 8853 | |
3d13ef2e | 8854 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8855 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8856 | |
8857 | out: | |
43694d69 | 8858 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8859 | } |
8860 | ||
7c8f8a70 | 8861 | |
f99d7069 DV |
8862 | /** |
8863 | * intel_mark_fb_busy - mark given planes as busy | |
8864 | * @dev: DRM device | |
8865 | * @frontbuffer_bits: bits for the affected planes | |
8866 | * @ring: optional ring for asynchronous commands | |
8867 | * | |
8868 | * This function gets called every time the screen contents change. It can be | |
8869 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. | |
8870 | */ | |
8871 | static void intel_mark_fb_busy(struct drm_device *dev, | |
8872 | unsigned frontbuffer_bits, | |
8873 | struct intel_engine_cs *ring) | |
652c393a | 8874 | { |
cc36513c | 8875 | enum pipe pipe; |
652c393a | 8876 | |
d330a953 | 8877 | if (!i915.powersave) |
acb87dfb CW |
8878 | return; |
8879 | ||
cc36513c | 8880 | for_each_pipe(pipe) { |
f99d7069 | 8881 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
c65355bb CW |
8882 | continue; |
8883 | ||
cc36513c | 8884 | intel_increase_pllclock(dev, pipe); |
c65355bb CW |
8885 | if (ring && intel_fbc_enabled(dev)) |
8886 | ring->fbc_dirty = true; | |
652c393a JB |
8887 | } |
8888 | } | |
8889 | ||
f99d7069 DV |
8890 | /** |
8891 | * intel_fb_obj_invalidate - invalidate frontbuffer object | |
8892 | * @obj: GEM object to invalidate | |
8893 | * @ring: set for asynchronous rendering | |
8894 | * | |
8895 | * This function gets called every time rendering on the given object starts and | |
8896 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must | |
8897 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed | |
8898 | * until the rendering completes or a flip on this frontbuffer plane is | |
8899 | * scheduled. | |
8900 | */ | |
8901 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
8902 | struct intel_engine_cs *ring) | |
8903 | { | |
8904 | struct drm_device *dev = obj->base.dev; | |
8905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8906 | ||
8907 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
8908 | ||
8909 | if (!obj->frontbuffer_bits) | |
8910 | return; | |
8911 | ||
8912 | if (ring) { | |
8913 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8914 | dev_priv->fb_tracking.busy_bits | |
8915 | |= obj->frontbuffer_bits; | |
8916 | dev_priv->fb_tracking.flip_bits | |
8917 | &= ~obj->frontbuffer_bits; | |
8918 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8919 | } | |
8920 | ||
8921 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); | |
8922 | ||
8923 | intel_edp_psr_exit(dev); | |
8924 | } | |
8925 | ||
8926 | /** | |
8927 | * intel_frontbuffer_flush - flush frontbuffer | |
8928 | * @dev: DRM device | |
8929 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
8930 | * | |
8931 | * This function gets called every time rendering on the given planes has | |
8932 | * completed and frontbuffer caching can be started again. Flushes will get | |
8933 | * delayed if they're blocked by some oustanding asynchronous rendering. | |
8934 | * | |
8935 | * Can be called without any locks held. | |
8936 | */ | |
8937 | void intel_frontbuffer_flush(struct drm_device *dev, | |
8938 | unsigned frontbuffer_bits) | |
8939 | { | |
8940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8941 | ||
8942 | /* Delay flushing when rings are still busy.*/ | |
8943 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8944 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; | |
8945 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8946 | ||
8947 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); | |
8948 | ||
8949 | intel_edp_psr_exit(dev); | |
8950 | } | |
8951 | ||
8952 | /** | |
8953 | * intel_fb_obj_flush - flush frontbuffer object | |
8954 | * @obj: GEM object to flush | |
8955 | * @retire: set when retiring asynchronous rendering | |
8956 | * | |
8957 | * This function gets called every time rendering on the given object has | |
8958 | * completed and frontbuffer caching can be started again. If @retire is true | |
8959 | * then any delayed flushes will be unblocked. | |
8960 | */ | |
8961 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, | |
8962 | bool retire) | |
8963 | { | |
8964 | struct drm_device *dev = obj->base.dev; | |
8965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8966 | unsigned frontbuffer_bits; | |
8967 | ||
8968 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
8969 | ||
8970 | if (!obj->frontbuffer_bits) | |
8971 | return; | |
8972 | ||
8973 | frontbuffer_bits = obj->frontbuffer_bits; | |
8974 | ||
8975 | if (retire) { | |
8976 | mutex_lock(&dev_priv->fb_tracking.lock); | |
8977 | /* Filter out new bits since rendering started. */ | |
8978 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; | |
8979 | ||
8980 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; | |
8981 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
8982 | } | |
8983 | ||
8984 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
8985 | } | |
8986 | ||
8987 | /** | |
8988 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip | |
8989 | * @dev: DRM device | |
8990 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
8991 | * | |
8992 | * This function gets called after scheduling a flip on @obj. The actual | |
8993 | * frontbuffer flushing will be delayed until completion is signalled with | |
8994 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this | |
8995 | * flush will be cancelled. | |
8996 | * | |
8997 | * Can be called without any locks held. | |
8998 | */ | |
8999 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
9000 | unsigned frontbuffer_bits) | |
9001 | { | |
9002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9003 | ||
9004 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9005 | dev_priv->fb_tracking.flip_bits | |
9006 | |= frontbuffer_bits; | |
9007 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9008 | } | |
9009 | ||
9010 | /** | |
9011 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush | |
9012 | * @dev: DRM device | |
9013 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9014 | * | |
9015 | * This function gets called after the flip has been latched and will complete | |
9016 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. | |
9017 | * | |
9018 | * Can be called without any locks held. | |
9019 | */ | |
9020 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
9021 | unsigned frontbuffer_bits) | |
9022 | { | |
9023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9024 | ||
9025 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9026 | /* Mask any cancelled flips. */ | |
9027 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; | |
9028 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; | |
9029 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9030 | ||
9031 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9032 | } | |
9033 | ||
79e53945 JB |
9034 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9035 | { | |
9036 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9037 | struct drm_device *dev = crtc->dev; |
9038 | struct intel_unpin_work *work; | |
9039 | unsigned long flags; | |
9040 | ||
9041 | spin_lock_irqsave(&dev->event_lock, flags); | |
9042 | work = intel_crtc->unpin_work; | |
9043 | intel_crtc->unpin_work = NULL; | |
9044 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9045 | ||
9046 | if (work) { | |
9047 | cancel_work_sync(&work->work); | |
9048 | kfree(work); | |
9049 | } | |
79e53945 JB |
9050 | |
9051 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9052 | |
79e53945 JB |
9053 | kfree(intel_crtc); |
9054 | } | |
9055 | ||
6b95a207 KH |
9056 | static void intel_unpin_work_fn(struct work_struct *__work) |
9057 | { | |
9058 | struct intel_unpin_work *work = | |
9059 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9060 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9061 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9062 | |
b4a98e57 | 9063 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9064 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9065 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9066 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9067 | |
b4a98e57 CW |
9068 | intel_update_fbc(dev); |
9069 | mutex_unlock(&dev->struct_mutex); | |
9070 | ||
f99d7069 DV |
9071 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9072 | ||
b4a98e57 CW |
9073 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9074 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9075 | ||
6b95a207 KH |
9076 | kfree(work); |
9077 | } | |
9078 | ||
1afe3e9d | 9079 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9080 | struct drm_crtc *crtc) |
6b95a207 | 9081 | { |
fbee40df | 9082 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9084 | struct intel_unpin_work *work; | |
6b95a207 KH |
9085 | unsigned long flags; |
9086 | ||
9087 | /* Ignore early vblank irqs */ | |
9088 | if (intel_crtc == NULL) | |
9089 | return; | |
9090 | ||
9091 | spin_lock_irqsave(&dev->event_lock, flags); | |
9092 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9093 | |
9094 | /* Ensure we don't miss a work->pending update ... */ | |
9095 | smp_rmb(); | |
9096 | ||
9097 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9098 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9099 | return; | |
9100 | } | |
9101 | ||
e7d841ca CW |
9102 | /* and that the unpin work is consistent wrt ->pending. */ |
9103 | smp_rmb(); | |
9104 | ||
6b95a207 | 9105 | intel_crtc->unpin_work = NULL; |
6b95a207 | 9106 | |
45a066eb RC |
9107 | if (work->event) |
9108 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 9109 | |
87b6b101 | 9110 | drm_crtc_vblank_put(crtc); |
0af7e4df | 9111 | |
6b95a207 KH |
9112 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9113 | ||
2c10d571 | 9114 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
9115 | |
9116 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
9117 | |
9118 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
9119 | } |
9120 | ||
1afe3e9d JB |
9121 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9122 | { | |
fbee40df | 9123 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9124 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9125 | ||
49b14a5c | 9126 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9127 | } |
9128 | ||
9129 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9130 | { | |
fbee40df | 9131 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9132 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9133 | ||
49b14a5c | 9134 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9135 | } |
9136 | ||
75f7f3ec VS |
9137 | /* Is 'a' after or equal to 'b'? */ |
9138 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9139 | { | |
9140 | return !((a - b) & 0x80000000); | |
9141 | } | |
9142 | ||
9143 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9144 | { | |
9145 | struct drm_device *dev = crtc->base.dev; | |
9146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9147 | ||
9148 | /* | |
9149 | * The relevant registers doen't exist on pre-ctg. | |
9150 | * As the flip done interrupt doesn't trigger for mmio | |
9151 | * flips on gmch platforms, a flip count check isn't | |
9152 | * really needed there. But since ctg has the registers, | |
9153 | * include it in the check anyway. | |
9154 | */ | |
9155 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9156 | return true; | |
9157 | ||
9158 | /* | |
9159 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9160 | * used the same base address. In that case the mmio flip might | |
9161 | * have completed, but the CS hasn't even executed the flip yet. | |
9162 | * | |
9163 | * A flip count check isn't enough as the CS might have updated | |
9164 | * the base address just after start of vblank, but before we | |
9165 | * managed to process the interrupt. This means we'd complete the | |
9166 | * CS flip too soon. | |
9167 | * | |
9168 | * Combining both checks should get us a good enough result. It may | |
9169 | * still happen that the CS flip has been executed, but has not | |
9170 | * yet actually completed. But in case the base address is the same | |
9171 | * anyway, we don't really care. | |
9172 | */ | |
9173 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9174 | crtc->unpin_work->gtt_offset && | |
9175 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9176 | crtc->unpin_work->flip_count); | |
9177 | } | |
9178 | ||
6b95a207 KH |
9179 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9180 | { | |
fbee40df | 9181 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9182 | struct intel_crtc *intel_crtc = |
9183 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9184 | unsigned long flags; | |
9185 | ||
e7d841ca CW |
9186 | /* NB: An MMIO update of the plane base pointer will also |
9187 | * generate a page-flip completion irq, i.e. every modeset | |
9188 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9189 | */ | |
6b95a207 | 9190 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9191 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9192 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9193 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9194 | } | |
9195 | ||
eba905b2 | 9196 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9197 | { |
9198 | /* Ensure that the work item is consistent when activating it ... */ | |
9199 | smp_wmb(); | |
9200 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9201 | /* and that it is marked active as soon as the irq could fire. */ | |
9202 | smp_wmb(); | |
9203 | } | |
9204 | ||
8c9f3aaf JB |
9205 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9206 | struct drm_crtc *crtc, | |
9207 | struct drm_framebuffer *fb, | |
ed8d1975 | 9208 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9209 | struct intel_engine_cs *ring, |
ed8d1975 | 9210 | uint32_t flags) |
8c9f3aaf | 9211 | { |
8c9f3aaf | 9212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9213 | u32 flip_mask; |
9214 | int ret; | |
9215 | ||
6d90c952 | 9216 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9217 | if (ret) |
4fa62c89 | 9218 | return ret; |
8c9f3aaf JB |
9219 | |
9220 | /* Can't queue multiple flips, so wait for the previous | |
9221 | * one to finish before executing the next. | |
9222 | */ | |
9223 | if (intel_crtc->plane) | |
9224 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9225 | else | |
9226 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9227 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9228 | intel_ring_emit(ring, MI_NOOP); | |
9229 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9230 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9231 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9232 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9233 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9234 | |
9235 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9236 | __intel_ring_advance(ring); |
83d4092b | 9237 | return 0; |
8c9f3aaf JB |
9238 | } |
9239 | ||
9240 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9241 | struct drm_crtc *crtc, | |
9242 | struct drm_framebuffer *fb, | |
ed8d1975 | 9243 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9244 | struct intel_engine_cs *ring, |
ed8d1975 | 9245 | uint32_t flags) |
8c9f3aaf | 9246 | { |
8c9f3aaf | 9247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9248 | u32 flip_mask; |
9249 | int ret; | |
9250 | ||
6d90c952 | 9251 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9252 | if (ret) |
4fa62c89 | 9253 | return ret; |
8c9f3aaf JB |
9254 | |
9255 | if (intel_crtc->plane) | |
9256 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9257 | else | |
9258 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9259 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9260 | intel_ring_emit(ring, MI_NOOP); | |
9261 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9262 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9263 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9264 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9265 | intel_ring_emit(ring, MI_NOOP); |
9266 | ||
e7d841ca | 9267 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9268 | __intel_ring_advance(ring); |
83d4092b | 9269 | return 0; |
8c9f3aaf JB |
9270 | } |
9271 | ||
9272 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9273 | struct drm_crtc *crtc, | |
9274 | struct drm_framebuffer *fb, | |
ed8d1975 | 9275 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9276 | struct intel_engine_cs *ring, |
ed8d1975 | 9277 | uint32_t flags) |
8c9f3aaf JB |
9278 | { |
9279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9281 | uint32_t pf, pipesrc; | |
9282 | int ret; | |
9283 | ||
6d90c952 | 9284 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9285 | if (ret) |
4fa62c89 | 9286 | return ret; |
8c9f3aaf JB |
9287 | |
9288 | /* i965+ uses the linear or tiled offsets from the | |
9289 | * Display Registers (which do not change across a page-flip) | |
9290 | * so we need only reprogram the base address. | |
9291 | */ | |
6d90c952 DV |
9292 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9293 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9294 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9295 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9296 | obj->tiling_mode); |
8c9f3aaf JB |
9297 | |
9298 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9299 | * untested on non-native modes, so ignore it for now. | |
9300 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9301 | */ | |
9302 | pf = 0; | |
9303 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9304 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9305 | |
9306 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9307 | __intel_ring_advance(ring); |
83d4092b | 9308 | return 0; |
8c9f3aaf JB |
9309 | } |
9310 | ||
9311 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9312 | struct drm_crtc *crtc, | |
9313 | struct drm_framebuffer *fb, | |
ed8d1975 | 9314 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9315 | struct intel_engine_cs *ring, |
ed8d1975 | 9316 | uint32_t flags) |
8c9f3aaf JB |
9317 | { |
9318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9319 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9320 | uint32_t pf, pipesrc; | |
9321 | int ret; | |
9322 | ||
6d90c952 | 9323 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9324 | if (ret) |
4fa62c89 | 9325 | return ret; |
8c9f3aaf | 9326 | |
6d90c952 DV |
9327 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9328 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9329 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9330 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9331 | |
dc257cf1 DV |
9332 | /* Contrary to the suggestions in the documentation, |
9333 | * "Enable Panel Fitter" does not seem to be required when page | |
9334 | * flipping with a non-native mode, and worse causes a normal | |
9335 | * modeset to fail. | |
9336 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9337 | */ | |
9338 | pf = 0; | |
8c9f3aaf | 9339 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9340 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9341 | |
9342 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9343 | __intel_ring_advance(ring); |
83d4092b | 9344 | return 0; |
8c9f3aaf JB |
9345 | } |
9346 | ||
7c9017e5 JB |
9347 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9348 | struct drm_crtc *crtc, | |
9349 | struct drm_framebuffer *fb, | |
ed8d1975 | 9350 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9351 | struct intel_engine_cs *ring, |
ed8d1975 | 9352 | uint32_t flags) |
7c9017e5 | 9353 | { |
7c9017e5 | 9354 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9355 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9356 | int len, ret; |
9357 | ||
eba905b2 | 9358 | switch (intel_crtc->plane) { |
cb05d8de DV |
9359 | case PLANE_A: |
9360 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9361 | break; | |
9362 | case PLANE_B: | |
9363 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9364 | break; | |
9365 | case PLANE_C: | |
9366 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9367 | break; | |
9368 | default: | |
9369 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9370 | return -ENODEV; |
cb05d8de DV |
9371 | } |
9372 | ||
ffe74d75 | 9373 | len = 4; |
f476828a | 9374 | if (ring->id == RCS) { |
ffe74d75 | 9375 | len += 6; |
f476828a DL |
9376 | /* |
9377 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9378 | * 48bits addresses, and we need a NOOP for the batch size to | |
9379 | * stay even. | |
9380 | */ | |
9381 | if (IS_GEN8(dev)) | |
9382 | len += 2; | |
9383 | } | |
ffe74d75 | 9384 | |
f66fab8e VS |
9385 | /* |
9386 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9387 | * "The full packet must be contained within the same cache line." | |
9388 | * | |
9389 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9390 | * cacheline, if we ever start emitting more commands before | |
9391 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9392 | * then do the cacheline alignment, and finally emit the | |
9393 | * MI_DISPLAY_FLIP. | |
9394 | */ | |
9395 | ret = intel_ring_cacheline_align(ring); | |
9396 | if (ret) | |
4fa62c89 | 9397 | return ret; |
f66fab8e | 9398 | |
ffe74d75 | 9399 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9400 | if (ret) |
4fa62c89 | 9401 | return ret; |
7c9017e5 | 9402 | |
ffe74d75 CW |
9403 | /* Unmask the flip-done completion message. Note that the bspec says that |
9404 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9405 | * more than one flip event at any time (or ensure that one flip message | |
9406 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9407 | * Experimentation says that BCS works despite DERRMR masking all | |
9408 | * flip-done completion events and that unmasking all planes at once | |
9409 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9410 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9411 | */ | |
9412 | if (ring->id == RCS) { | |
9413 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9414 | intel_ring_emit(ring, DERRMR); | |
9415 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9416 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9417 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9418 | if (IS_GEN8(dev)) |
9419 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9420 | MI_SRM_LRM_GLOBAL_GTT); | |
9421 | else | |
9422 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9423 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9424 | intel_ring_emit(ring, DERRMR); |
9425 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9426 | if (IS_GEN8(dev)) { |
9427 | intel_ring_emit(ring, 0); | |
9428 | intel_ring_emit(ring, MI_NOOP); | |
9429 | } | |
ffe74d75 CW |
9430 | } |
9431 | ||
cb05d8de | 9432 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9433 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9434 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9435 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9436 | |
9437 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9438 | __intel_ring_advance(ring); |
83d4092b | 9439 | return 0; |
7c9017e5 JB |
9440 | } |
9441 | ||
84c33a64 SG |
9442 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9443 | struct drm_i915_gem_object *obj) | |
9444 | { | |
9445 | /* | |
9446 | * This is not being used for older platforms, because | |
9447 | * non-availability of flip done interrupt forces us to use | |
9448 | * CS flips. Older platforms derive flip done using some clever | |
9449 | * tricks involving the flip_pending status bits and vblank irqs. | |
9450 | * So using MMIO flips there would disrupt this mechanism. | |
9451 | */ | |
9452 | ||
9453 | if (INTEL_INFO(ring->dev)->gen < 5) | |
9454 | return false; | |
9455 | ||
9456 | if (i915.use_mmio_flip < 0) | |
9457 | return false; | |
9458 | else if (i915.use_mmio_flip > 0) | |
9459 | return true; | |
9460 | else | |
9461 | return ring != obj->ring; | |
9462 | } | |
9463 | ||
9464 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9465 | { | |
9466 | struct drm_device *dev = intel_crtc->base.dev; | |
9467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9468 | struct intel_framebuffer *intel_fb = | |
9469 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9470 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9471 | u32 dspcntr; | |
9472 | u32 reg; | |
9473 | ||
9474 | intel_mark_page_flip_active(intel_crtc); | |
9475 | ||
9476 | reg = DSPCNTR(intel_crtc->plane); | |
9477 | dspcntr = I915_READ(reg); | |
9478 | ||
9479 | if (INTEL_INFO(dev)->gen >= 4) { | |
9480 | if (obj->tiling_mode != I915_TILING_NONE) | |
9481 | dspcntr |= DISPPLANE_TILED; | |
9482 | else | |
9483 | dspcntr &= ~DISPPLANE_TILED; | |
9484 | } | |
9485 | I915_WRITE(reg, dspcntr); | |
9486 | ||
9487 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9488 | intel_crtc->unpin_work->gtt_offset); | |
9489 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
9490 | } | |
9491 | ||
9492 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) | |
9493 | { | |
9494 | struct intel_engine_cs *ring; | |
9495 | int ret; | |
9496 | ||
9497 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
9498 | ||
9499 | if (!obj->last_write_seqno) | |
9500 | return 0; | |
9501 | ||
9502 | ring = obj->ring; | |
9503 | ||
9504 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
9505 | obj->last_write_seqno)) | |
9506 | return 0; | |
9507 | ||
9508 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); | |
9509 | if (ret) | |
9510 | return ret; | |
9511 | ||
9512 | if (WARN_ON(!ring->irq_get(ring))) | |
9513 | return 0; | |
9514 | ||
9515 | return 1; | |
9516 | } | |
9517 | ||
9518 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) | |
9519 | { | |
9520 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
9521 | struct intel_crtc *intel_crtc; | |
9522 | unsigned long irq_flags; | |
9523 | u32 seqno; | |
9524 | ||
9525 | seqno = ring->get_seqno(ring, false); | |
9526 | ||
9527 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9528 | for_each_intel_crtc(ring->dev, intel_crtc) { | |
9529 | struct intel_mmio_flip *mmio_flip; | |
9530 | ||
9531 | mmio_flip = &intel_crtc->mmio_flip; | |
9532 | if (mmio_flip->seqno == 0) | |
9533 | continue; | |
9534 | ||
9535 | if (ring->id != mmio_flip->ring_id) | |
9536 | continue; | |
9537 | ||
9538 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { | |
9539 | intel_do_mmio_flip(intel_crtc); | |
9540 | mmio_flip->seqno = 0; | |
9541 | ring->irq_put(ring); | |
9542 | } | |
9543 | } | |
9544 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9545 | } | |
9546 | ||
9547 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9548 | struct drm_crtc *crtc, | |
9549 | struct drm_framebuffer *fb, | |
9550 | struct drm_i915_gem_object *obj, | |
9551 | struct intel_engine_cs *ring, | |
9552 | uint32_t flags) | |
9553 | { | |
9554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9556 | unsigned long irq_flags; | |
9557 | int ret; | |
9558 | ||
9559 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) | |
9560 | return -EBUSY; | |
9561 | ||
9562 | ret = intel_postpone_flip(obj); | |
9563 | if (ret < 0) | |
9564 | return ret; | |
9565 | if (ret == 0) { | |
9566 | intel_do_mmio_flip(intel_crtc); | |
9567 | return 0; | |
9568 | } | |
9569 | ||
9570 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9571 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; | |
9572 | intel_crtc->mmio_flip.ring_id = obj->ring->id; | |
9573 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9574 | ||
9575 | /* | |
9576 | * Double check to catch cases where irq fired before | |
9577 | * mmio flip data was ready | |
9578 | */ | |
9579 | intel_notify_mmio_flip(obj->ring); | |
9580 | return 0; | |
9581 | } | |
9582 | ||
8c9f3aaf JB |
9583 | static int intel_default_queue_flip(struct drm_device *dev, |
9584 | struct drm_crtc *crtc, | |
9585 | struct drm_framebuffer *fb, | |
ed8d1975 | 9586 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9587 | struct intel_engine_cs *ring, |
ed8d1975 | 9588 | uint32_t flags) |
8c9f3aaf JB |
9589 | { |
9590 | return -ENODEV; | |
9591 | } | |
9592 | ||
6b95a207 KH |
9593 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9594 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9595 | struct drm_pending_vblank_event *event, |
9596 | uint32_t page_flip_flags) | |
6b95a207 KH |
9597 | { |
9598 | struct drm_device *dev = crtc->dev; | |
9599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9600 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9601 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 | 9602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9603 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9604 | struct intel_unpin_work *work; |
a4872ba6 | 9605 | struct intel_engine_cs *ring; |
8c9f3aaf | 9606 | unsigned long flags; |
52e68630 | 9607 | int ret; |
6b95a207 | 9608 | |
e6a595d2 | 9609 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9610 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9611 | return -EINVAL; |
9612 | ||
9613 | /* | |
9614 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9615 | * Note that pitch changes could also affect these register. | |
9616 | */ | |
9617 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9618 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9619 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9620 | return -EINVAL; |
9621 | ||
f900db47 CW |
9622 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9623 | goto out_hang; | |
9624 | ||
b14c5679 | 9625 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9626 | if (work == NULL) |
9627 | return -ENOMEM; | |
9628 | ||
6b95a207 | 9629 | work->event = event; |
b4a98e57 | 9630 | work->crtc = crtc; |
4a35f83b | 9631 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9632 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9633 | ||
87b6b101 | 9634 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9635 | if (ret) |
9636 | goto free_work; | |
9637 | ||
6b95a207 KH |
9638 | /* We borrow the event spin lock for protecting unpin_work */ |
9639 | spin_lock_irqsave(&dev->event_lock, flags); | |
9640 | if (intel_crtc->unpin_work) { | |
9641 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9642 | kfree(work); | |
87b6b101 | 9643 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9644 | |
9645 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9646 | return -EBUSY; |
9647 | } | |
9648 | intel_crtc->unpin_work = work; | |
9649 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9650 | ||
b4a98e57 CW |
9651 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9652 | flush_workqueue(dev_priv->wq); | |
9653 | ||
79158103 CW |
9654 | ret = i915_mutex_lock_interruptible(dev); |
9655 | if (ret) | |
9656 | goto cleanup; | |
6b95a207 | 9657 | |
75dfca80 | 9658 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9659 | drm_gem_object_reference(&work->old_fb_obj->base); |
9660 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9661 | |
f4510a27 | 9662 | crtc->primary->fb = fb; |
96b099fd | 9663 | |
e1f99ce6 | 9664 | work->pending_flip_obj = obj; |
e1f99ce6 | 9665 | |
4e5359cd SF |
9666 | work->enable_stall_check = true; |
9667 | ||
b4a98e57 | 9668 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9669 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9670 | |
75f7f3ec | 9671 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9672 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9673 | |
4fa62c89 VS |
9674 | if (IS_VALLEYVIEW(dev)) { |
9675 | ring = &dev_priv->ring[BCS]; | |
9676 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
9677 | ring = obj->ring; | |
9678 | if (ring == NULL || ring->id != RCS) | |
9679 | ring = &dev_priv->ring[BCS]; | |
9680 | } else { | |
9681 | ring = &dev_priv->ring[RCS]; | |
9682 | } | |
9683 | ||
9684 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9685 | if (ret) |
9686 | goto cleanup_pending; | |
6b95a207 | 9687 | |
4fa62c89 VS |
9688 | work->gtt_offset = |
9689 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9690 | ||
84c33a64 SG |
9691 | if (use_mmio_flip(ring, obj)) |
9692 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, | |
9693 | page_flip_flags); | |
9694 | else | |
9695 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, | |
9696 | page_flip_flags); | |
4fa62c89 VS |
9697 | if (ret) |
9698 | goto cleanup_unpin; | |
9699 | ||
a071fa00 DV |
9700 | i915_gem_track_fb(work->old_fb_obj, obj, |
9701 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9702 | ||
7782de3b | 9703 | intel_disable_fbc(dev); |
f99d7069 | 9704 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9705 | mutex_unlock(&dev->struct_mutex); |
9706 | ||
e5510fac JB |
9707 | trace_i915_flip_request(intel_crtc->plane, obj); |
9708 | ||
6b95a207 | 9709 | return 0; |
96b099fd | 9710 | |
4fa62c89 VS |
9711 | cleanup_unpin: |
9712 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9713 | cleanup_pending: |
b4a98e57 | 9714 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9715 | crtc->primary->fb = old_fb; |
05394f39 CW |
9716 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9717 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9718 | mutex_unlock(&dev->struct_mutex); |
9719 | ||
79158103 | 9720 | cleanup: |
96b099fd CW |
9721 | spin_lock_irqsave(&dev->event_lock, flags); |
9722 | intel_crtc->unpin_work = NULL; | |
9723 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9724 | ||
87b6b101 | 9725 | drm_crtc_vblank_put(crtc); |
7317c75e | 9726 | free_work: |
96b099fd CW |
9727 | kfree(work); |
9728 | ||
f900db47 CW |
9729 | if (ret == -EIO) { |
9730 | out_hang: | |
9731 | intel_crtc_wait_for_pending_flips(crtc); | |
9732 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9733 | if (ret == 0 && event) | |
a071fa00 | 9734 | drm_send_vblank_event(dev, pipe, event); |
f900db47 | 9735 | } |
96b099fd | 9736 | return ret; |
6b95a207 KH |
9737 | } |
9738 | ||
f6e5b160 | 9739 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9740 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9741 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9742 | }; |
9743 | ||
9a935856 DV |
9744 | /** |
9745 | * intel_modeset_update_staged_output_state | |
9746 | * | |
9747 | * Updates the staged output configuration state, e.g. after we've read out the | |
9748 | * current hw state. | |
9749 | */ | |
9750 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9751 | { |
7668851f | 9752 | struct intel_crtc *crtc; |
9a935856 DV |
9753 | struct intel_encoder *encoder; |
9754 | struct intel_connector *connector; | |
f6e5b160 | 9755 | |
9a935856 DV |
9756 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9757 | base.head) { | |
9758 | connector->new_encoder = | |
9759 | to_intel_encoder(connector->base.encoder); | |
9760 | } | |
f6e5b160 | 9761 | |
9a935856 DV |
9762 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9763 | base.head) { | |
9764 | encoder->new_crtc = | |
9765 | to_intel_crtc(encoder->base.crtc); | |
9766 | } | |
7668851f | 9767 | |
d3fcc808 | 9768 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9769 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9770 | |
9771 | if (crtc->new_enabled) | |
9772 | crtc->new_config = &crtc->config; | |
9773 | else | |
9774 | crtc->new_config = NULL; | |
7668851f | 9775 | } |
f6e5b160 CW |
9776 | } |
9777 | ||
9a935856 DV |
9778 | /** |
9779 | * intel_modeset_commit_output_state | |
9780 | * | |
9781 | * This function copies the stage display pipe configuration to the real one. | |
9782 | */ | |
9783 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9784 | { | |
7668851f | 9785 | struct intel_crtc *crtc; |
9a935856 DV |
9786 | struct intel_encoder *encoder; |
9787 | struct intel_connector *connector; | |
f6e5b160 | 9788 | |
9a935856 DV |
9789 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9790 | base.head) { | |
9791 | connector->base.encoder = &connector->new_encoder->base; | |
9792 | } | |
f6e5b160 | 9793 | |
9a935856 DV |
9794 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9795 | base.head) { | |
9796 | encoder->base.crtc = &encoder->new_crtc->base; | |
9797 | } | |
7668851f | 9798 | |
d3fcc808 | 9799 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9800 | crtc->base.enabled = crtc->new_enabled; |
9801 | } | |
9a935856 DV |
9802 | } |
9803 | ||
050f7aeb | 9804 | static void |
eba905b2 | 9805 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9806 | struct intel_crtc_config *pipe_config) |
9807 | { | |
9808 | int bpp = pipe_config->pipe_bpp; | |
9809 | ||
9810 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9811 | connector->base.base.id, | |
c23cc417 | 9812 | connector->base.name); |
050f7aeb DV |
9813 | |
9814 | /* Don't use an invalid EDID bpc value */ | |
9815 | if (connector->base.display_info.bpc && | |
9816 | connector->base.display_info.bpc * 3 < bpp) { | |
9817 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9818 | bpp, connector->base.display_info.bpc*3); | |
9819 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9820 | } | |
9821 | ||
9822 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9823 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9824 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9825 | bpp); | |
9826 | pipe_config->pipe_bpp = 24; | |
9827 | } | |
9828 | } | |
9829 | ||
4e53c2e0 | 9830 | static int |
050f7aeb DV |
9831 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9832 | struct drm_framebuffer *fb, | |
9833 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9834 | { |
050f7aeb DV |
9835 | struct drm_device *dev = crtc->base.dev; |
9836 | struct intel_connector *connector; | |
4e53c2e0 DV |
9837 | int bpp; |
9838 | ||
d42264b1 DV |
9839 | switch (fb->pixel_format) { |
9840 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9841 | bpp = 8*3; /* since we go through a colormap */ |
9842 | break; | |
d42264b1 DV |
9843 | case DRM_FORMAT_XRGB1555: |
9844 | case DRM_FORMAT_ARGB1555: | |
9845 | /* checked in intel_framebuffer_init already */ | |
9846 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9847 | return -EINVAL; | |
9848 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9849 | bpp = 6*3; /* min is 18bpp */ |
9850 | break; | |
d42264b1 DV |
9851 | case DRM_FORMAT_XBGR8888: |
9852 | case DRM_FORMAT_ABGR8888: | |
9853 | /* checked in intel_framebuffer_init already */ | |
9854 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9855 | return -EINVAL; | |
9856 | case DRM_FORMAT_XRGB8888: | |
9857 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9858 | bpp = 8*3; |
9859 | break; | |
d42264b1 DV |
9860 | case DRM_FORMAT_XRGB2101010: |
9861 | case DRM_FORMAT_ARGB2101010: | |
9862 | case DRM_FORMAT_XBGR2101010: | |
9863 | case DRM_FORMAT_ABGR2101010: | |
9864 | /* checked in intel_framebuffer_init already */ | |
9865 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9866 | return -EINVAL; |
4e53c2e0 DV |
9867 | bpp = 10*3; |
9868 | break; | |
baba133a | 9869 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9870 | default: |
9871 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9872 | return -EINVAL; | |
9873 | } | |
9874 | ||
4e53c2e0 DV |
9875 | pipe_config->pipe_bpp = bpp; |
9876 | ||
9877 | /* Clamp display bpp to EDID value */ | |
9878 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9879 | base.head) { |
1b829e05 DV |
9880 | if (!connector->new_encoder || |
9881 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9882 | continue; |
9883 | ||
050f7aeb | 9884 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9885 | } |
9886 | ||
9887 | return bpp; | |
9888 | } | |
9889 | ||
644db711 DV |
9890 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9891 | { | |
9892 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9893 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9894 | mode->crtc_clock, |
644db711 DV |
9895 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9896 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9897 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9898 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9899 | } | |
9900 | ||
c0b03411 DV |
9901 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9902 | struct intel_crtc_config *pipe_config, | |
9903 | const char *context) | |
9904 | { | |
9905 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9906 | context, pipe_name(crtc->pipe)); | |
9907 | ||
9908 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9909 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9910 | pipe_config->pipe_bpp, pipe_config->dither); | |
9911 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9912 | pipe_config->has_pch_encoder, | |
9913 | pipe_config->fdi_lanes, | |
9914 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9915 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9916 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9917 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9918 | pipe_config->has_dp_encoder, | |
9919 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9920 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9921 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9922 | DRM_DEBUG_KMS("requested mode:\n"); |
9923 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9924 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9925 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9926 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9927 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9928 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9929 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9930 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9931 | pipe_config->gmch_pfit.control, | |
9932 | pipe_config->gmch_pfit.pgm_ratios, | |
9933 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9934 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9935 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9936 | pipe_config->pch_pfit.size, |
9937 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9938 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9939 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9940 | } |
9941 | ||
bc079e8b VS |
9942 | static bool encoders_cloneable(const struct intel_encoder *a, |
9943 | const struct intel_encoder *b) | |
accfc0c5 | 9944 | { |
bc079e8b VS |
9945 | /* masks could be asymmetric, so check both ways */ |
9946 | return a == b || (a->cloneable & (1 << b->type) && | |
9947 | b->cloneable & (1 << a->type)); | |
9948 | } | |
9949 | ||
9950 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9951 | struct intel_encoder *encoder) | |
9952 | { | |
9953 | struct drm_device *dev = crtc->base.dev; | |
9954 | struct intel_encoder *source_encoder; | |
9955 | ||
9956 | list_for_each_entry(source_encoder, | |
9957 | &dev->mode_config.encoder_list, base.head) { | |
9958 | if (source_encoder->new_crtc != crtc) | |
9959 | continue; | |
9960 | ||
9961 | if (!encoders_cloneable(encoder, source_encoder)) | |
9962 | return false; | |
9963 | } | |
9964 | ||
9965 | return true; | |
9966 | } | |
9967 | ||
9968 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9969 | { | |
9970 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9971 | struct intel_encoder *encoder; |
9972 | ||
bc079e8b VS |
9973 | list_for_each_entry(encoder, |
9974 | &dev->mode_config.encoder_list, base.head) { | |
9975 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9976 | continue; |
9977 | ||
bc079e8b VS |
9978 | if (!check_single_encoder_cloning(crtc, encoder)) |
9979 | return false; | |
accfc0c5 DV |
9980 | } |
9981 | ||
bc079e8b | 9982 | return true; |
accfc0c5 DV |
9983 | } |
9984 | ||
b8cecdf5 DV |
9985 | static struct intel_crtc_config * |
9986 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9987 | struct drm_framebuffer *fb, |
b8cecdf5 | 9988 | struct drm_display_mode *mode) |
ee7b9f93 | 9989 | { |
7758a113 | 9990 | struct drm_device *dev = crtc->dev; |
7758a113 | 9991 | struct intel_encoder *encoder; |
b8cecdf5 | 9992 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9993 | int plane_bpp, ret = -EINVAL; |
9994 | bool retry = true; | |
ee7b9f93 | 9995 | |
bc079e8b | 9996 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9997 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9998 | return ERR_PTR(-EINVAL); | |
9999 | } | |
10000 | ||
b8cecdf5 DV |
10001 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10002 | if (!pipe_config) | |
7758a113 DV |
10003 | return ERR_PTR(-ENOMEM); |
10004 | ||
b8cecdf5 DV |
10005 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10006 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10007 | |
e143a21c DV |
10008 | pipe_config->cpu_transcoder = |
10009 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10010 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10011 | |
2960bc9c ID |
10012 | /* |
10013 | * Sanitize sync polarity flags based on requested ones. If neither | |
10014 | * positive or negative polarity is requested, treat this as meaning | |
10015 | * negative polarity. | |
10016 | */ | |
10017 | if (!(pipe_config->adjusted_mode.flags & | |
10018 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10019 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10020 | ||
10021 | if (!(pipe_config->adjusted_mode.flags & | |
10022 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10023 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10024 | ||
050f7aeb DV |
10025 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10026 | * plane pixel format and any sink constraints into account. Returns the | |
10027 | * source plane bpp so that dithering can be selected on mismatches | |
10028 | * after encoders and crtc also have had their say. */ | |
10029 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10030 | fb, pipe_config); | |
4e53c2e0 DV |
10031 | if (plane_bpp < 0) |
10032 | goto fail; | |
10033 | ||
e41a56be VS |
10034 | /* |
10035 | * Determine the real pipe dimensions. Note that stereo modes can | |
10036 | * increase the actual pipe size due to the frame doubling and | |
10037 | * insertion of additional space for blanks between the frame. This | |
10038 | * is stored in the crtc timings. We use the requested mode to do this | |
10039 | * computation to clearly distinguish it from the adjusted mode, which | |
10040 | * can be changed by the connectors in the below retry loop. | |
10041 | */ | |
10042 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10043 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10044 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10045 | ||
e29c22c0 | 10046 | encoder_retry: |
ef1b460d | 10047 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10048 | pipe_config->port_clock = 0; |
ef1b460d | 10049 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10050 | |
135c81b8 | 10051 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10052 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10053 | |
7758a113 DV |
10054 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10055 | * adjust it according to limitations or connector properties, and also | |
10056 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10057 | */ |
7758a113 DV |
10058 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10059 | base.head) { | |
47f1c6c9 | 10060 | |
7758a113 DV |
10061 | if (&encoder->new_crtc->base != crtc) |
10062 | continue; | |
7ae89233 | 10063 | |
efea6e8e DV |
10064 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10065 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10066 | goto fail; |
10067 | } | |
ee7b9f93 | 10068 | } |
47f1c6c9 | 10069 | |
ff9a6750 DV |
10070 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10071 | * done afterwards in case the encoder adjusts the mode. */ | |
10072 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10073 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10074 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10075 | |
a43f6e0f | 10076 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10077 | if (ret < 0) { |
7758a113 DV |
10078 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10079 | goto fail; | |
ee7b9f93 | 10080 | } |
e29c22c0 DV |
10081 | |
10082 | if (ret == RETRY) { | |
10083 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10084 | ret = -EINVAL; | |
10085 | goto fail; | |
10086 | } | |
10087 | ||
10088 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10089 | retry = false; | |
10090 | goto encoder_retry; | |
10091 | } | |
10092 | ||
4e53c2e0 DV |
10093 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10094 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10095 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10096 | ||
b8cecdf5 | 10097 | return pipe_config; |
7758a113 | 10098 | fail: |
b8cecdf5 | 10099 | kfree(pipe_config); |
e29c22c0 | 10100 | return ERR_PTR(ret); |
ee7b9f93 | 10101 | } |
47f1c6c9 | 10102 | |
e2e1ed41 DV |
10103 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10104 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10105 | static void | |
10106 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10107 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10108 | { |
10109 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10110 | struct drm_device *dev = crtc->dev; |
10111 | struct intel_encoder *encoder; | |
10112 | struct intel_connector *connector; | |
10113 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10114 | |
e2e1ed41 | 10115 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10116 | |
e2e1ed41 DV |
10117 | /* Check which crtcs have changed outputs connected to them, these need |
10118 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10119 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10120 | * bit set at most. */ | |
10121 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10122 | base.head) { | |
10123 | if (connector->base.encoder == &connector->new_encoder->base) | |
10124 | continue; | |
79e53945 | 10125 | |
e2e1ed41 DV |
10126 | if (connector->base.encoder) { |
10127 | tmp_crtc = connector->base.encoder->crtc; | |
10128 | ||
10129 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10130 | } | |
10131 | ||
10132 | if (connector->new_encoder) | |
10133 | *prepare_pipes |= | |
10134 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10135 | } |
10136 | ||
e2e1ed41 DV |
10137 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10138 | base.head) { | |
10139 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
10140 | continue; | |
10141 | ||
10142 | if (encoder->base.crtc) { | |
10143 | tmp_crtc = encoder->base.crtc; | |
10144 | ||
10145 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10146 | } | |
10147 | ||
10148 | if (encoder->new_crtc) | |
10149 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10150 | } |
10151 | ||
7668851f | 10152 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10153 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10154 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10155 | continue; |
7e7d76c3 | 10156 | |
7668851f | 10157 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10158 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10159 | else |
10160 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10161 | } |
10162 | ||
e2e1ed41 DV |
10163 | |
10164 | /* set_mode is also used to update properties on life display pipes. */ | |
10165 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10166 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10167 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10168 | ||
b6c5164d DV |
10169 | /* |
10170 | * For simplicity do a full modeset on any pipe where the output routing | |
10171 | * changed. We could be more clever, but that would require us to be | |
10172 | * more careful with calling the relevant encoder->mode_set functions. | |
10173 | */ | |
e2e1ed41 DV |
10174 | if (*prepare_pipes) |
10175 | *modeset_pipes = *prepare_pipes; | |
10176 | ||
10177 | /* ... and mask these out. */ | |
10178 | *modeset_pipes &= ~(*disable_pipes); | |
10179 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10180 | |
10181 | /* | |
10182 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10183 | * obies this rule, but the modeset restore mode of | |
10184 | * intel_modeset_setup_hw_state does not. | |
10185 | */ | |
10186 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10187 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10188 | |
10189 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10190 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10191 | } |
79e53945 | 10192 | |
ea9d758d | 10193 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10194 | { |
ea9d758d | 10195 | struct drm_encoder *encoder; |
f6e5b160 | 10196 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10197 | |
ea9d758d DV |
10198 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10199 | if (encoder->crtc == crtc) | |
10200 | return true; | |
10201 | ||
10202 | return false; | |
10203 | } | |
10204 | ||
10205 | static void | |
10206 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10207 | { | |
10208 | struct intel_encoder *intel_encoder; | |
10209 | struct intel_crtc *intel_crtc; | |
10210 | struct drm_connector *connector; | |
10211 | ||
10212 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
10213 | base.head) { | |
10214 | if (!intel_encoder->base.crtc) | |
10215 | continue; | |
10216 | ||
10217 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10218 | ||
10219 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10220 | intel_encoder->connectors_active = false; | |
10221 | } | |
10222 | ||
10223 | intel_modeset_commit_output_state(dev); | |
10224 | ||
7668851f | 10225 | /* Double check state. */ |
d3fcc808 | 10226 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10227 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10228 | WARN_ON(intel_crtc->new_config && |
10229 | intel_crtc->new_config != &intel_crtc->config); | |
10230 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10231 | } |
10232 | ||
10233 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10234 | if (!connector->encoder || !connector->encoder->crtc) | |
10235 | continue; | |
10236 | ||
10237 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10238 | ||
10239 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10240 | struct drm_property *dpms_property = |
10241 | dev->mode_config.dpms_property; | |
10242 | ||
ea9d758d | 10243 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10244 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10245 | dpms_property, |
10246 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10247 | |
10248 | intel_encoder = to_intel_encoder(connector->encoder); | |
10249 | intel_encoder->connectors_active = true; | |
10250 | } | |
10251 | } | |
10252 | ||
10253 | } | |
10254 | ||
3bd26263 | 10255 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10256 | { |
3bd26263 | 10257 | int diff; |
f1f644dc JB |
10258 | |
10259 | if (clock1 == clock2) | |
10260 | return true; | |
10261 | ||
10262 | if (!clock1 || !clock2) | |
10263 | return false; | |
10264 | ||
10265 | diff = abs(clock1 - clock2); | |
10266 | ||
10267 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10268 | return true; | |
10269 | ||
10270 | return false; | |
10271 | } | |
10272 | ||
25c5b266 DV |
10273 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10274 | list_for_each_entry((intel_crtc), \ | |
10275 | &(dev)->mode_config.crtc_list, \ | |
10276 | base.head) \ | |
0973f18f | 10277 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10278 | |
0e8ffe1b | 10279 | static bool |
2fa2fe9a DV |
10280 | intel_pipe_config_compare(struct drm_device *dev, |
10281 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10282 | struct intel_crtc_config *pipe_config) |
10283 | { | |
66e985c0 DV |
10284 | #define PIPE_CONF_CHECK_X(name) \ |
10285 | if (current_config->name != pipe_config->name) { \ | |
10286 | DRM_ERROR("mismatch in " #name " " \ | |
10287 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10288 | current_config->name, \ | |
10289 | pipe_config->name); \ | |
10290 | return false; \ | |
10291 | } | |
10292 | ||
08a24034 DV |
10293 | #define PIPE_CONF_CHECK_I(name) \ |
10294 | if (current_config->name != pipe_config->name) { \ | |
10295 | DRM_ERROR("mismatch in " #name " " \ | |
10296 | "(expected %i, found %i)\n", \ | |
10297 | current_config->name, \ | |
10298 | pipe_config->name); \ | |
10299 | return false; \ | |
88adfff1 DV |
10300 | } |
10301 | ||
1bd1bd80 DV |
10302 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10303 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10304 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10305 | "(expected %i, found %i)\n", \ |
10306 | current_config->name & (mask), \ | |
10307 | pipe_config->name & (mask)); \ | |
10308 | return false; \ | |
10309 | } | |
10310 | ||
5e550656 VS |
10311 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10312 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10313 | DRM_ERROR("mismatch in " #name " " \ | |
10314 | "(expected %i, found %i)\n", \ | |
10315 | current_config->name, \ | |
10316 | pipe_config->name); \ | |
10317 | return false; \ | |
10318 | } | |
10319 | ||
bb760063 DV |
10320 | #define PIPE_CONF_QUIRK(quirk) \ |
10321 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10322 | ||
eccb140b DV |
10323 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10324 | ||
08a24034 DV |
10325 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10326 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10327 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10328 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10329 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10330 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10331 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10332 | |
eb14cb74 VS |
10333 | PIPE_CONF_CHECK_I(has_dp_encoder); |
10334 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10335 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10336 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10337 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10338 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10339 | ||
1bd1bd80 DV |
10340 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10341 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10342 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10343 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10344 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10345 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10346 | ||
10347 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10348 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10349 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10350 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10351 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10352 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10353 | ||
c93f54cf | 10354 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10355 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10356 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10357 | IS_VALLEYVIEW(dev)) | |
10358 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10359 | |
9ed109a7 DV |
10360 | PIPE_CONF_CHECK_I(has_audio); |
10361 | ||
1bd1bd80 DV |
10362 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10363 | DRM_MODE_FLAG_INTERLACE); | |
10364 | ||
bb760063 DV |
10365 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10366 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10367 | DRM_MODE_FLAG_PHSYNC); | |
10368 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10369 | DRM_MODE_FLAG_NHSYNC); | |
10370 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10371 | DRM_MODE_FLAG_PVSYNC); | |
10372 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10373 | DRM_MODE_FLAG_NVSYNC); | |
10374 | } | |
045ac3b5 | 10375 | |
37327abd VS |
10376 | PIPE_CONF_CHECK_I(pipe_src_w); |
10377 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10378 | |
9953599b DV |
10379 | /* |
10380 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10381 | * screen. Since we don't yet re-compute the pipe config when moving | |
10382 | * just the lvds port away to another pipe the sw tracking won't match. | |
10383 | * | |
10384 | * Proper atomic modesets with recomputed global state will fix this. | |
10385 | * Until then just don't check gmch state for inherited modes. | |
10386 | */ | |
10387 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10388 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10389 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10390 | if (INTEL_INFO(dev)->gen < 4) | |
10391 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10392 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10393 | } | |
10394 | ||
fd4daa9c CW |
10395 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10396 | if (current_config->pch_pfit.enabled) { | |
10397 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10398 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10399 | } | |
2fa2fe9a | 10400 | |
e59150dc JB |
10401 | /* BDW+ don't expose a synchronous way to read the state */ |
10402 | if (IS_HASWELL(dev)) | |
10403 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10404 | |
282740f7 VS |
10405 | PIPE_CONF_CHECK_I(double_wide); |
10406 | ||
c0d43d62 | 10407 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10408 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10409 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10410 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10411 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 10412 | |
42571aef VS |
10413 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10414 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10415 | ||
a9a7e98a JB |
10416 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10417 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10418 | |
66e985c0 | 10419 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10420 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 10421 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10422 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10423 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10424 | |
0e8ffe1b DV |
10425 | return true; |
10426 | } | |
10427 | ||
91d1b4bd DV |
10428 | static void |
10429 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10430 | { |
8af6cf88 DV |
10431 | struct intel_connector *connector; |
10432 | ||
10433 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10434 | base.head) { | |
10435 | /* This also checks the encoder/connector hw state with the | |
10436 | * ->get_hw_state callbacks. */ | |
10437 | intel_connector_check_state(connector); | |
10438 | ||
10439 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10440 | "connector's staged encoder doesn't match current encoder\n"); | |
10441 | } | |
91d1b4bd DV |
10442 | } |
10443 | ||
10444 | static void | |
10445 | check_encoder_state(struct drm_device *dev) | |
10446 | { | |
10447 | struct intel_encoder *encoder; | |
10448 | struct intel_connector *connector; | |
8af6cf88 DV |
10449 | |
10450 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10451 | base.head) { | |
10452 | bool enabled = false; | |
10453 | bool active = false; | |
10454 | enum pipe pipe, tracked_pipe; | |
10455 | ||
10456 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10457 | encoder->base.base.id, | |
8e329a03 | 10458 | encoder->base.name); |
8af6cf88 DV |
10459 | |
10460 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10461 | "encoder's stage crtc doesn't match current crtc\n"); | |
10462 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10463 | "encoder's active_connectors set, but no crtc\n"); | |
10464 | ||
10465 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10466 | base.head) { | |
10467 | if (connector->base.encoder != &encoder->base) | |
10468 | continue; | |
10469 | enabled = true; | |
10470 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10471 | active = true; | |
10472 | } | |
10473 | WARN(!!encoder->base.crtc != enabled, | |
10474 | "encoder's enabled state mismatch " | |
10475 | "(expected %i, found %i)\n", | |
10476 | !!encoder->base.crtc, enabled); | |
10477 | WARN(active && !encoder->base.crtc, | |
10478 | "active encoder with no crtc\n"); | |
10479 | ||
10480 | WARN(encoder->connectors_active != active, | |
10481 | "encoder's computed active state doesn't match tracked active state " | |
10482 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10483 | ||
10484 | active = encoder->get_hw_state(encoder, &pipe); | |
10485 | WARN(active != encoder->connectors_active, | |
10486 | "encoder's hw state doesn't match sw tracking " | |
10487 | "(expected %i, found %i)\n", | |
10488 | encoder->connectors_active, active); | |
10489 | ||
10490 | if (!encoder->base.crtc) | |
10491 | continue; | |
10492 | ||
10493 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10494 | WARN(active && pipe != tracked_pipe, | |
10495 | "active encoder's pipe doesn't match" | |
10496 | "(expected %i, found %i)\n", | |
10497 | tracked_pipe, pipe); | |
10498 | ||
10499 | } | |
91d1b4bd DV |
10500 | } |
10501 | ||
10502 | static void | |
10503 | check_crtc_state(struct drm_device *dev) | |
10504 | { | |
fbee40df | 10505 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10506 | struct intel_crtc *crtc; |
10507 | struct intel_encoder *encoder; | |
10508 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10509 | |
d3fcc808 | 10510 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10511 | bool enabled = false; |
10512 | bool active = false; | |
10513 | ||
045ac3b5 JB |
10514 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10515 | ||
8af6cf88 DV |
10516 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10517 | crtc->base.base.id); | |
10518 | ||
10519 | WARN(crtc->active && !crtc->base.enabled, | |
10520 | "active crtc, but not enabled in sw tracking\n"); | |
10521 | ||
10522 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10523 | base.head) { | |
10524 | if (encoder->base.crtc != &crtc->base) | |
10525 | continue; | |
10526 | enabled = true; | |
10527 | if (encoder->connectors_active) | |
10528 | active = true; | |
10529 | } | |
6c49f241 | 10530 | |
8af6cf88 DV |
10531 | WARN(active != crtc->active, |
10532 | "crtc's computed active state doesn't match tracked active state " | |
10533 | "(expected %i, found %i)\n", active, crtc->active); | |
10534 | WARN(enabled != crtc->base.enabled, | |
10535 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10536 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10537 | ||
0e8ffe1b DV |
10538 | active = dev_priv->display.get_pipe_config(crtc, |
10539 | &pipe_config); | |
d62cf62a DV |
10540 | |
10541 | /* hw state is inconsistent with the pipe A quirk */ | |
10542 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10543 | active = crtc->active; | |
10544 | ||
6c49f241 DV |
10545 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10546 | base.head) { | |
3eaba51c | 10547 | enum pipe pipe; |
6c49f241 DV |
10548 | if (encoder->base.crtc != &crtc->base) |
10549 | continue; | |
1d37b689 | 10550 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10551 | encoder->get_config(encoder, &pipe_config); |
10552 | } | |
10553 | ||
0e8ffe1b DV |
10554 | WARN(crtc->active != active, |
10555 | "crtc active state doesn't match with hw state " | |
10556 | "(expected %i, found %i)\n", crtc->active, active); | |
10557 | ||
c0b03411 DV |
10558 | if (active && |
10559 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10560 | WARN(1, "pipe state doesn't match!\n"); | |
10561 | intel_dump_pipe_config(crtc, &pipe_config, | |
10562 | "[hw state]"); | |
10563 | intel_dump_pipe_config(crtc, &crtc->config, | |
10564 | "[sw state]"); | |
10565 | } | |
8af6cf88 DV |
10566 | } |
10567 | } | |
10568 | ||
91d1b4bd DV |
10569 | static void |
10570 | check_shared_dpll_state(struct drm_device *dev) | |
10571 | { | |
fbee40df | 10572 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10573 | struct intel_crtc *crtc; |
10574 | struct intel_dpll_hw_state dpll_hw_state; | |
10575 | int i; | |
5358901f DV |
10576 | |
10577 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10578 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10579 | int enabled_crtcs = 0, active_crtcs = 0; | |
10580 | bool active; | |
10581 | ||
10582 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10583 | ||
10584 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10585 | ||
10586 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10587 | ||
10588 | WARN(pll->active > pll->refcount, | |
10589 | "more active pll users than references: %i vs %i\n", | |
10590 | pll->active, pll->refcount); | |
10591 | WARN(pll->active && !pll->on, | |
10592 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10593 | WARN(pll->on && !pll->active, |
10594 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10595 | WARN(pll->on != active, |
10596 | "pll on state mismatch (expected %i, found %i)\n", | |
10597 | pll->on, active); | |
10598 | ||
d3fcc808 | 10599 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10600 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10601 | enabled_crtcs++; | |
10602 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10603 | active_crtcs++; | |
10604 | } | |
10605 | WARN(pll->active != active_crtcs, | |
10606 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10607 | pll->active, active_crtcs); | |
10608 | WARN(pll->refcount != enabled_crtcs, | |
10609 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10610 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10611 | |
10612 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10613 | sizeof(dpll_hw_state)), | |
10614 | "pll hw state mismatch\n"); | |
5358901f | 10615 | } |
8af6cf88 DV |
10616 | } |
10617 | ||
91d1b4bd DV |
10618 | void |
10619 | intel_modeset_check_state(struct drm_device *dev) | |
10620 | { | |
10621 | check_connector_state(dev); | |
10622 | check_encoder_state(dev); | |
10623 | check_crtc_state(dev); | |
10624 | check_shared_dpll_state(dev); | |
10625 | } | |
10626 | ||
18442d08 VS |
10627 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10628 | int dotclock) | |
10629 | { | |
10630 | /* | |
10631 | * FDI already provided one idea for the dotclock. | |
10632 | * Yell if the encoder disagrees. | |
10633 | */ | |
241bfc38 | 10634 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10635 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10636 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10637 | } |
10638 | ||
80715b2f VS |
10639 | static void update_scanline_offset(struct intel_crtc *crtc) |
10640 | { | |
10641 | struct drm_device *dev = crtc->base.dev; | |
10642 | ||
10643 | /* | |
10644 | * The scanline counter increments at the leading edge of hsync. | |
10645 | * | |
10646 | * On most platforms it starts counting from vtotal-1 on the | |
10647 | * first active line. That means the scanline counter value is | |
10648 | * always one less than what we would expect. Ie. just after | |
10649 | * start of vblank, which also occurs at start of hsync (on the | |
10650 | * last active line), the scanline counter will read vblank_start-1. | |
10651 | * | |
10652 | * On gen2 the scanline counter starts counting from 1 instead | |
10653 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10654 | * to keep the value positive), instead of adding one. | |
10655 | * | |
10656 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10657 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10658 | * there's an extra 1 line difference. So we need to add two instead of | |
10659 | * one to the value. | |
10660 | */ | |
10661 | if (IS_GEN2(dev)) { | |
10662 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10663 | int vtotal; | |
10664 | ||
10665 | vtotal = mode->crtc_vtotal; | |
10666 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10667 | vtotal /= 2; | |
10668 | ||
10669 | crtc->scanline_offset = vtotal - 1; | |
10670 | } else if (HAS_DDI(dev) && | |
10671 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10672 | crtc->scanline_offset = 2; | |
10673 | } else | |
10674 | crtc->scanline_offset = 1; | |
10675 | } | |
10676 | ||
f30da187 DV |
10677 | static int __intel_set_mode(struct drm_crtc *crtc, |
10678 | struct drm_display_mode *mode, | |
10679 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10680 | { |
10681 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10682 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10683 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10684 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10685 | struct intel_crtc *intel_crtc; |
10686 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10687 | int ret = 0; |
a6778b3c | 10688 | |
4b4b9238 | 10689 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10690 | if (!saved_mode) |
10691 | return -ENOMEM; | |
a6778b3c | 10692 | |
e2e1ed41 | 10693 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10694 | &prepare_pipes, &disable_pipes); |
10695 | ||
3ac18232 | 10696 | *saved_mode = crtc->mode; |
a6778b3c | 10697 | |
25c5b266 DV |
10698 | /* Hack: Because we don't (yet) support global modeset on multiple |
10699 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10700 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10701 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10702 | * changing their mode at the same time. */ | |
25c5b266 | 10703 | if (modeset_pipes) { |
4e53c2e0 | 10704 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10705 | if (IS_ERR(pipe_config)) { |
10706 | ret = PTR_ERR(pipe_config); | |
10707 | pipe_config = NULL; | |
10708 | ||
3ac18232 | 10709 | goto out; |
25c5b266 | 10710 | } |
c0b03411 DV |
10711 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10712 | "[modeset]"); | |
50741abc | 10713 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10714 | } |
a6778b3c | 10715 | |
30a970c6 JB |
10716 | /* |
10717 | * See if the config requires any additional preparation, e.g. | |
10718 | * to adjust global state with pipes off. We need to do this | |
10719 | * here so we can get the modeset_pipe updated config for the new | |
10720 | * mode set on this crtc. For other crtcs we need to use the | |
10721 | * adjusted_mode bits in the crtc directly. | |
10722 | */ | |
c164f833 | 10723 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10724 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10725 | |
c164f833 VS |
10726 | /* may have added more to prepare_pipes than we should */ |
10727 | prepare_pipes &= ~disable_pipes; | |
10728 | } | |
10729 | ||
460da916 DV |
10730 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10731 | intel_crtc_disable(&intel_crtc->base); | |
10732 | ||
ea9d758d DV |
10733 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10734 | if (intel_crtc->base.enabled) | |
10735 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10736 | } | |
a6778b3c | 10737 | |
6c4c86f5 DV |
10738 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10739 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10740 | */ |
b8cecdf5 | 10741 | if (modeset_pipes) { |
25c5b266 | 10742 | crtc->mode = *mode; |
b8cecdf5 DV |
10743 | /* mode_set/enable/disable functions rely on a correct pipe |
10744 | * config. */ | |
10745 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10746 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10747 | |
10748 | /* | |
10749 | * Calculate and store various constants which | |
10750 | * are later needed by vblank and swap-completion | |
10751 | * timestamping. They are derived from true hwmode. | |
10752 | */ | |
10753 | drm_calc_timestamping_constants(crtc, | |
10754 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10755 | } |
7758a113 | 10756 | |
ea9d758d DV |
10757 | /* Only after disabling all output pipelines that will be changed can we |
10758 | * update the the output configuration. */ | |
10759 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10760 | |
47fab737 DV |
10761 | if (dev_priv->display.modeset_global_resources) |
10762 | dev_priv->display.modeset_global_resources(dev); | |
10763 | ||
a6778b3c DV |
10764 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10765 | * on the DPLL. | |
f6e5b160 | 10766 | */ |
25c5b266 | 10767 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4c10794f | 10768 | struct drm_framebuffer *old_fb; |
a071fa00 DV |
10769 | struct drm_i915_gem_object *old_obj = NULL; |
10770 | struct drm_i915_gem_object *obj = | |
10771 | to_intel_framebuffer(fb)->obj; | |
4c10794f DV |
10772 | |
10773 | mutex_lock(&dev->struct_mutex); | |
10774 | ret = intel_pin_and_fence_fb_obj(dev, | |
a071fa00 | 10775 | obj, |
4c10794f DV |
10776 | NULL); |
10777 | if (ret != 0) { | |
10778 | DRM_ERROR("pin & fence failed\n"); | |
10779 | mutex_unlock(&dev->struct_mutex); | |
10780 | goto done; | |
10781 | } | |
10782 | old_fb = crtc->primary->fb; | |
a071fa00 DV |
10783 | if (old_fb) { |
10784 | old_obj = to_intel_framebuffer(old_fb)->obj; | |
10785 | intel_unpin_fb_obj(old_obj); | |
10786 | } | |
10787 | i915_gem_track_fb(old_obj, obj, | |
10788 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
10789 | mutex_unlock(&dev->struct_mutex); |
10790 | ||
10791 | crtc->primary->fb = fb; | |
10792 | crtc->x = x; | |
10793 | crtc->y = y; | |
10794 | ||
4271b753 DV |
10795 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10796 | x, y, fb); | |
c0c36b94 CW |
10797 | if (ret) |
10798 | goto done; | |
a6778b3c DV |
10799 | } |
10800 | ||
10801 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10802 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10803 | update_scanline_offset(intel_crtc); | |
10804 | ||
25c5b266 | 10805 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10806 | } |
a6778b3c | 10807 | |
a6778b3c DV |
10808 | /* FIXME: add subpixel order */ |
10809 | done: | |
4b4b9238 | 10810 | if (ret && crtc->enabled) |
3ac18232 | 10811 | crtc->mode = *saved_mode; |
a6778b3c | 10812 | |
3ac18232 | 10813 | out: |
b8cecdf5 | 10814 | kfree(pipe_config); |
3ac18232 | 10815 | kfree(saved_mode); |
a6778b3c | 10816 | return ret; |
f6e5b160 CW |
10817 | } |
10818 | ||
e7457a9a DL |
10819 | static int intel_set_mode(struct drm_crtc *crtc, |
10820 | struct drm_display_mode *mode, | |
10821 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10822 | { |
10823 | int ret; | |
10824 | ||
10825 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10826 | ||
10827 | if (ret == 0) | |
10828 | intel_modeset_check_state(crtc->dev); | |
10829 | ||
10830 | return ret; | |
10831 | } | |
10832 | ||
c0c36b94 CW |
10833 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10834 | { | |
f4510a27 | 10835 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10836 | } |
10837 | ||
25c5b266 DV |
10838 | #undef for_each_intel_crtc_masked |
10839 | ||
d9e55608 DV |
10840 | static void intel_set_config_free(struct intel_set_config *config) |
10841 | { | |
10842 | if (!config) | |
10843 | return; | |
10844 | ||
1aa4b628 DV |
10845 | kfree(config->save_connector_encoders); |
10846 | kfree(config->save_encoder_crtcs); | |
7668851f | 10847 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10848 | kfree(config); |
10849 | } | |
10850 | ||
85f9eb71 DV |
10851 | static int intel_set_config_save_state(struct drm_device *dev, |
10852 | struct intel_set_config *config) | |
10853 | { | |
7668851f | 10854 | struct drm_crtc *crtc; |
85f9eb71 DV |
10855 | struct drm_encoder *encoder; |
10856 | struct drm_connector *connector; | |
10857 | int count; | |
10858 | ||
7668851f VS |
10859 | config->save_crtc_enabled = |
10860 | kcalloc(dev->mode_config.num_crtc, | |
10861 | sizeof(bool), GFP_KERNEL); | |
10862 | if (!config->save_crtc_enabled) | |
10863 | return -ENOMEM; | |
10864 | ||
1aa4b628 DV |
10865 | config->save_encoder_crtcs = |
10866 | kcalloc(dev->mode_config.num_encoder, | |
10867 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10868 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10869 | return -ENOMEM; |
10870 | ||
1aa4b628 DV |
10871 | config->save_connector_encoders = |
10872 | kcalloc(dev->mode_config.num_connector, | |
10873 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10874 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10875 | return -ENOMEM; |
10876 | ||
10877 | /* Copy data. Note that driver private data is not affected. | |
10878 | * Should anything bad happen only the expected state is | |
10879 | * restored, not the drivers personal bookkeeping. | |
10880 | */ | |
7668851f | 10881 | count = 0; |
70e1e0ec | 10882 | for_each_crtc(dev, crtc) { |
7668851f VS |
10883 | config->save_crtc_enabled[count++] = crtc->enabled; |
10884 | } | |
10885 | ||
85f9eb71 DV |
10886 | count = 0; |
10887 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10888 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10889 | } |
10890 | ||
10891 | count = 0; | |
10892 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10893 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10894 | } |
10895 | ||
10896 | return 0; | |
10897 | } | |
10898 | ||
10899 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10900 | struct intel_set_config *config) | |
10901 | { | |
7668851f | 10902 | struct intel_crtc *crtc; |
9a935856 DV |
10903 | struct intel_encoder *encoder; |
10904 | struct intel_connector *connector; | |
85f9eb71 DV |
10905 | int count; |
10906 | ||
7668851f | 10907 | count = 0; |
d3fcc808 | 10908 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10909 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10910 | |
10911 | if (crtc->new_enabled) | |
10912 | crtc->new_config = &crtc->config; | |
10913 | else | |
10914 | crtc->new_config = NULL; | |
7668851f VS |
10915 | } |
10916 | ||
85f9eb71 | 10917 | count = 0; |
9a935856 DV |
10918 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10919 | encoder->new_crtc = | |
10920 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10921 | } |
10922 | ||
10923 | count = 0; | |
9a935856 DV |
10924 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10925 | connector->new_encoder = | |
10926 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10927 | } |
10928 | } | |
10929 | ||
e3de42b6 | 10930 | static bool |
2e57f47d | 10931 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10932 | { |
10933 | int i; | |
10934 | ||
2e57f47d CW |
10935 | if (set->num_connectors == 0) |
10936 | return false; | |
10937 | ||
10938 | if (WARN_ON(set->connectors == NULL)) | |
10939 | return false; | |
10940 | ||
10941 | for (i = 0; i < set->num_connectors; i++) | |
10942 | if (set->connectors[i]->encoder && | |
10943 | set->connectors[i]->encoder->crtc == set->crtc && | |
10944 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10945 | return true; |
10946 | ||
10947 | return false; | |
10948 | } | |
10949 | ||
5e2b584e DV |
10950 | static void |
10951 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10952 | struct intel_set_config *config) | |
10953 | { | |
10954 | ||
10955 | /* We should be able to check here if the fb has the same properties | |
10956 | * and then just flip_or_move it */ | |
2e57f47d CW |
10957 | if (is_crtc_connector_off(set)) { |
10958 | config->mode_changed = true; | |
f4510a27 | 10959 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
10960 | /* |
10961 | * If we have no fb, we can only flip as long as the crtc is | |
10962 | * active, otherwise we need a full mode set. The crtc may | |
10963 | * be active if we've only disabled the primary plane, or | |
10964 | * in fastboot situations. | |
10965 | */ | |
f4510a27 | 10966 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10967 | struct intel_crtc *intel_crtc = |
10968 | to_intel_crtc(set->crtc); | |
10969 | ||
3b150f08 | 10970 | if (intel_crtc->active) { |
319d9827 JB |
10971 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10972 | config->fb_changed = true; | |
10973 | } else { | |
10974 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10975 | config->mode_changed = true; | |
10976 | } | |
5e2b584e DV |
10977 | } else if (set->fb == NULL) { |
10978 | config->mode_changed = true; | |
72f4901e | 10979 | } else if (set->fb->pixel_format != |
f4510a27 | 10980 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10981 | config->mode_changed = true; |
e3de42b6 | 10982 | } else { |
5e2b584e | 10983 | config->fb_changed = true; |
e3de42b6 | 10984 | } |
5e2b584e DV |
10985 | } |
10986 | ||
835c5873 | 10987 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10988 | config->fb_changed = true; |
10989 | ||
10990 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10991 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10992 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10993 | drm_mode_debug_printmodeline(set->mode); | |
10994 | config->mode_changed = true; | |
10995 | } | |
a1d95703 CW |
10996 | |
10997 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10998 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10999 | } |
11000 | ||
2e431051 | 11001 | static int |
9a935856 DV |
11002 | intel_modeset_stage_output_state(struct drm_device *dev, |
11003 | struct drm_mode_set *set, | |
11004 | struct intel_set_config *config) | |
50f56119 | 11005 | { |
9a935856 DV |
11006 | struct intel_connector *connector; |
11007 | struct intel_encoder *encoder; | |
7668851f | 11008 | struct intel_crtc *crtc; |
f3f08572 | 11009 | int ro; |
50f56119 | 11010 | |
9abdda74 | 11011 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11012 | * of connectors. For paranoia, double-check this. */ |
11013 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11014 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11015 | ||
9a935856 DV |
11016 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11017 | base.head) { | |
11018 | /* Otherwise traverse passed in connector list and get encoders | |
11019 | * for them. */ | |
50f56119 | 11020 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
11021 | if (set->connectors[ro] == &connector->base) { |
11022 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
11023 | break; |
11024 | } | |
11025 | } | |
11026 | ||
9a935856 DV |
11027 | /* If we disable the crtc, disable all its connectors. Also, if |
11028 | * the connector is on the changing crtc but not on the new | |
11029 | * connector list, disable it. */ | |
11030 | if ((!set->fb || ro == set->num_connectors) && | |
11031 | connector->base.encoder && | |
11032 | connector->base.encoder->crtc == set->crtc) { | |
11033 | connector->new_encoder = NULL; | |
11034 | ||
11035 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11036 | connector->base.base.id, | |
c23cc417 | 11037 | connector->base.name); |
9a935856 DV |
11038 | } |
11039 | ||
11040 | ||
11041 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11042 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11043 | config->mode_changed = true; |
50f56119 DV |
11044 | } |
11045 | } | |
9a935856 | 11046 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11047 | |
9a935856 | 11048 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11049 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11050 | base.head) { | |
7668851f VS |
11051 | struct drm_crtc *new_crtc; |
11052 | ||
9a935856 | 11053 | if (!connector->new_encoder) |
50f56119 DV |
11054 | continue; |
11055 | ||
9a935856 | 11056 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11057 | |
11058 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11059 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11060 | new_crtc = set->crtc; |
11061 | } | |
11062 | ||
11063 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11064 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11065 | new_crtc)) { | |
5e2b584e | 11066 | return -EINVAL; |
50f56119 | 11067 | } |
9a935856 DV |
11068 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
11069 | ||
11070 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11071 | connector->base.base.id, | |
c23cc417 | 11072 | connector->base.name, |
9a935856 DV |
11073 | new_crtc->base.id); |
11074 | } | |
11075 | ||
11076 | /* Check for any encoders that needs to be disabled. */ | |
11077 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11078 | base.head) { | |
5a65f358 | 11079 | int num_connectors = 0; |
9a935856 DV |
11080 | list_for_each_entry(connector, |
11081 | &dev->mode_config.connector_list, | |
11082 | base.head) { | |
11083 | if (connector->new_encoder == encoder) { | |
11084 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11085 | num_connectors++; |
9a935856 DV |
11086 | } |
11087 | } | |
5a65f358 PZ |
11088 | |
11089 | if (num_connectors == 0) | |
11090 | encoder->new_crtc = NULL; | |
11091 | else if (num_connectors > 1) | |
11092 | return -EINVAL; | |
11093 | ||
9a935856 DV |
11094 | /* Only now check for crtc changes so we don't miss encoders |
11095 | * that will be disabled. */ | |
11096 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11097 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11098 | config->mode_changed = true; |
50f56119 DV |
11099 | } |
11100 | } | |
9a935856 | 11101 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 11102 | |
d3fcc808 | 11103 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11104 | crtc->new_enabled = false; |
11105 | ||
11106 | list_for_each_entry(encoder, | |
11107 | &dev->mode_config.encoder_list, | |
11108 | base.head) { | |
11109 | if (encoder->new_crtc == crtc) { | |
11110 | crtc->new_enabled = true; | |
11111 | break; | |
11112 | } | |
11113 | } | |
11114 | ||
11115 | if (crtc->new_enabled != crtc->base.enabled) { | |
11116 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11117 | crtc->new_enabled ? "en" : "dis"); | |
11118 | config->mode_changed = true; | |
11119 | } | |
7bd0a8e7 VS |
11120 | |
11121 | if (crtc->new_enabled) | |
11122 | crtc->new_config = &crtc->config; | |
11123 | else | |
11124 | crtc->new_config = NULL; | |
7668851f VS |
11125 | } |
11126 | ||
2e431051 DV |
11127 | return 0; |
11128 | } | |
11129 | ||
7d00a1f5 VS |
11130 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11131 | { | |
11132 | struct drm_device *dev = crtc->base.dev; | |
11133 | struct intel_encoder *encoder; | |
11134 | struct intel_connector *connector; | |
11135 | ||
11136 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11137 | pipe_name(crtc->pipe)); | |
11138 | ||
11139 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11140 | if (connector->new_encoder && | |
11141 | connector->new_encoder->new_crtc == crtc) | |
11142 | connector->new_encoder = NULL; | |
11143 | } | |
11144 | ||
11145 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
11146 | if (encoder->new_crtc == crtc) | |
11147 | encoder->new_crtc = NULL; | |
11148 | } | |
11149 | ||
11150 | crtc->new_enabled = false; | |
7bd0a8e7 | 11151 | crtc->new_config = NULL; |
7d00a1f5 VS |
11152 | } |
11153 | ||
2e431051 DV |
11154 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11155 | { | |
11156 | struct drm_device *dev; | |
2e431051 DV |
11157 | struct drm_mode_set save_set; |
11158 | struct intel_set_config *config; | |
11159 | int ret; | |
2e431051 | 11160 | |
8d3e375e DV |
11161 | BUG_ON(!set); |
11162 | BUG_ON(!set->crtc); | |
11163 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11164 | |
7e53f3a4 DV |
11165 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11166 | BUG_ON(!set->mode && set->fb); | |
11167 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11168 | |
2e431051 DV |
11169 | if (set->fb) { |
11170 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11171 | set->crtc->base.id, set->fb->base.id, | |
11172 | (int)set->num_connectors, set->x, set->y); | |
11173 | } else { | |
11174 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11175 | } |
11176 | ||
11177 | dev = set->crtc->dev; | |
11178 | ||
11179 | ret = -ENOMEM; | |
11180 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11181 | if (!config) | |
11182 | goto out_config; | |
11183 | ||
11184 | ret = intel_set_config_save_state(dev, config); | |
11185 | if (ret) | |
11186 | goto out_config; | |
11187 | ||
11188 | save_set.crtc = set->crtc; | |
11189 | save_set.mode = &set->crtc->mode; | |
11190 | save_set.x = set->crtc->x; | |
11191 | save_set.y = set->crtc->y; | |
f4510a27 | 11192 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11193 | |
11194 | /* Compute whether we need a full modeset, only an fb base update or no | |
11195 | * change at all. In the future we might also check whether only the | |
11196 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11197 | * such cases. */ | |
11198 | intel_set_config_compute_mode_changes(set, config); | |
11199 | ||
9a935856 | 11200 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11201 | if (ret) |
11202 | goto fail; | |
11203 | ||
5e2b584e | 11204 | if (config->mode_changed) { |
c0c36b94 CW |
11205 | ret = intel_set_mode(set->crtc, set->mode, |
11206 | set->x, set->y, set->fb); | |
5e2b584e | 11207 | } else if (config->fb_changed) { |
3b150f08 MR |
11208 | struct drm_i915_private *dev_priv = dev->dev_private; |
11209 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); | |
11210 | ||
4878cae2 VS |
11211 | intel_crtc_wait_for_pending_flips(set->crtc); |
11212 | ||
4f660f49 | 11213 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11214 | set->x, set->y, set->fb); |
3b150f08 MR |
11215 | |
11216 | /* | |
11217 | * We need to make sure the primary plane is re-enabled if it | |
11218 | * has previously been turned off. | |
11219 | */ | |
11220 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11221 | WARN_ON(!intel_crtc->active); | |
11222 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11223 | intel_crtc->pipe); | |
11224 | } | |
11225 | ||
7ca51a3a JB |
11226 | /* |
11227 | * In the fastboot case this may be our only check of the | |
11228 | * state after boot. It would be better to only do it on | |
11229 | * the first update, but we don't have a nice way of doing that | |
11230 | * (and really, set_config isn't used much for high freq page | |
11231 | * flipping, so increasing its cost here shouldn't be a big | |
11232 | * deal). | |
11233 | */ | |
d330a953 | 11234 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11235 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11236 | } |
11237 | ||
2d05eae1 | 11238 | if (ret) { |
bf67dfeb DV |
11239 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11240 | set->crtc->base.id, ret); | |
50f56119 | 11241 | fail: |
2d05eae1 | 11242 | intel_set_config_restore_state(dev, config); |
50f56119 | 11243 | |
7d00a1f5 VS |
11244 | /* |
11245 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11246 | * force the pipe off to avoid oopsing in the modeset code | |
11247 | * due to fb==NULL. This should only happen during boot since | |
11248 | * we don't yet reconstruct the FB from the hardware state. | |
11249 | */ | |
11250 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11251 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11252 | ||
2d05eae1 CW |
11253 | /* Try to restore the config */ |
11254 | if (config->mode_changed && | |
11255 | intel_set_mode(save_set.crtc, save_set.mode, | |
11256 | save_set.x, save_set.y, save_set.fb)) | |
11257 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11258 | } | |
50f56119 | 11259 | |
d9e55608 DV |
11260 | out_config: |
11261 | intel_set_config_free(config); | |
50f56119 DV |
11262 | return ret; |
11263 | } | |
f6e5b160 CW |
11264 | |
11265 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11266 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11267 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11268 | .destroy = intel_crtc_destroy, |
11269 | .page_flip = intel_crtc_page_flip, | |
11270 | }; | |
11271 | ||
79f689aa PZ |
11272 | static void intel_cpu_pll_init(struct drm_device *dev) |
11273 | { | |
affa9354 | 11274 | if (HAS_DDI(dev)) |
79f689aa PZ |
11275 | intel_ddi_pll_init(dev); |
11276 | } | |
11277 | ||
5358901f DV |
11278 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11279 | struct intel_shared_dpll *pll, | |
11280 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11281 | { |
5358901f | 11282 | uint32_t val; |
ee7b9f93 | 11283 | |
5358901f | 11284 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11285 | hw_state->dpll = val; |
11286 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11287 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11288 | |
11289 | return val & DPLL_VCO_ENABLE; | |
11290 | } | |
11291 | ||
15bdd4cf DV |
11292 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11293 | struct intel_shared_dpll *pll) | |
11294 | { | |
11295 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
11296 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
11297 | } | |
11298 | ||
e7b903d2 DV |
11299 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11300 | struct intel_shared_dpll *pll) | |
11301 | { | |
e7b903d2 | 11302 | /* PCH refclock must be enabled first */ |
89eff4be | 11303 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11304 | |
15bdd4cf DV |
11305 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11306 | ||
11307 | /* Wait for the clocks to stabilize. */ | |
11308 | POSTING_READ(PCH_DPLL(pll->id)); | |
11309 | udelay(150); | |
11310 | ||
11311 | /* The pixel multiplier can only be updated once the | |
11312 | * DPLL is enabled and the clocks are stable. | |
11313 | * | |
11314 | * So write it again. | |
11315 | */ | |
11316 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
11317 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11318 | udelay(200); |
11319 | } | |
11320 | ||
11321 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11322 | struct intel_shared_dpll *pll) | |
11323 | { | |
11324 | struct drm_device *dev = dev_priv->dev; | |
11325 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11326 | |
11327 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11328 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11329 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11330 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11331 | } |
11332 | ||
15bdd4cf DV |
11333 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11334 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11335 | udelay(200); |
11336 | } | |
11337 | ||
46edb027 DV |
11338 | static char *ibx_pch_dpll_names[] = { |
11339 | "PCH DPLL A", | |
11340 | "PCH DPLL B", | |
11341 | }; | |
11342 | ||
7c74ade1 | 11343 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11344 | { |
e7b903d2 | 11345 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11346 | int i; |
11347 | ||
7c74ade1 | 11348 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11349 | |
e72f9fbf | 11350 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11351 | dev_priv->shared_dplls[i].id = i; |
11352 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11353 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11354 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11355 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11356 | dev_priv->shared_dplls[i].get_hw_state = |
11357 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11358 | } |
11359 | } | |
11360 | ||
7c74ade1 DV |
11361 | static void intel_shared_dpll_init(struct drm_device *dev) |
11362 | { | |
e7b903d2 | 11363 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
11364 | |
11365 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
11366 | ibx_pch_dpll_init(dev); | |
11367 | else | |
11368 | dev_priv->num_shared_dpll = 0; | |
11369 | ||
11370 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11371 | } |
11372 | ||
465c120c MR |
11373 | static int |
11374 | intel_primary_plane_disable(struct drm_plane *plane) | |
11375 | { | |
11376 | struct drm_device *dev = plane->dev; | |
11377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11378 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11379 | struct intel_crtc *intel_crtc; | |
11380 | ||
11381 | if (!plane->fb) | |
11382 | return 0; | |
11383 | ||
11384 | BUG_ON(!plane->crtc); | |
11385 | ||
11386 | intel_crtc = to_intel_crtc(plane->crtc); | |
11387 | ||
11388 | /* | |
11389 | * Even though we checked plane->fb above, it's still possible that | |
11390 | * the primary plane has been implicitly disabled because the crtc | |
11391 | * coordinates given weren't visible, or because we detected | |
11392 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11393 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11394 | * In either case, we need to unpin the FB and let the fb pointer get | |
11395 | * updated, but otherwise we don't need to touch the hardware. | |
11396 | */ | |
11397 | if (!intel_crtc->primary_enabled) | |
11398 | goto disable_unpin; | |
11399 | ||
11400 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
11401 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, | |
11402 | intel_plane->pipe); | |
465c120c | 11403 | disable_unpin: |
a071fa00 DV |
11404 | i915_gem_track_fb(to_intel_framebuffer(plane->fb)->obj, NULL, |
11405 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11406 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); |
11407 | plane->fb = NULL; | |
11408 | ||
11409 | return 0; | |
11410 | } | |
11411 | ||
11412 | static int | |
11413 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11414 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11415 | unsigned int crtc_w, unsigned int crtc_h, | |
11416 | uint32_t src_x, uint32_t src_y, | |
11417 | uint32_t src_w, uint32_t src_h) | |
11418 | { | |
11419 | struct drm_device *dev = crtc->dev; | |
11420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11422 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
a071fa00 | 11423 | struct drm_i915_gem_object *obj, *old_obj = NULL; |
465c120c MR |
11424 | struct drm_rect dest = { |
11425 | /* integer pixels */ | |
11426 | .x1 = crtc_x, | |
11427 | .y1 = crtc_y, | |
11428 | .x2 = crtc_x + crtc_w, | |
11429 | .y2 = crtc_y + crtc_h, | |
11430 | }; | |
11431 | struct drm_rect src = { | |
11432 | /* 16.16 fixed point */ | |
11433 | .x1 = src_x, | |
11434 | .y1 = src_y, | |
11435 | .x2 = src_x + src_w, | |
11436 | .y2 = src_y + src_h, | |
11437 | }; | |
11438 | const struct drm_rect clip = { | |
11439 | /* integer pixels */ | |
11440 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11441 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11442 | }; | |
11443 | bool visible; | |
11444 | int ret; | |
11445 | ||
11446 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11447 | &src, &dest, &clip, | |
11448 | DRM_PLANE_HELPER_NO_SCALING, | |
11449 | DRM_PLANE_HELPER_NO_SCALING, | |
11450 | false, true, &visible); | |
11451 | ||
11452 | if (ret) | |
11453 | return ret; | |
11454 | ||
a071fa00 DV |
11455 | if (plane->fb) |
11456 | old_obj = to_intel_framebuffer(plane->fb)->obj; | |
11457 | obj = to_intel_framebuffer(fb)->obj; | |
11458 | ||
465c120c MR |
11459 | /* |
11460 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11461 | * updating the fb pointer, and returning without touching the | |
11462 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11463 | * turn on the display with all planes setup as desired. | |
11464 | */ | |
11465 | if (!crtc->enabled) { | |
11466 | /* | |
11467 | * If we already called setplane while the crtc was disabled, | |
11468 | * we may have an fb pinned; unpin it. | |
11469 | */ | |
11470 | if (plane->fb) | |
a071fa00 DV |
11471 | intel_unpin_fb_obj(old_obj); |
11472 | ||
11473 | i915_gem_track_fb(old_obj, obj, | |
11474 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
465c120c MR |
11475 | |
11476 | /* Pin and return without programming hardware */ | |
a071fa00 | 11477 | return intel_pin_and_fence_fb_obj(dev, obj, NULL); |
465c120c MR |
11478 | } |
11479 | ||
11480 | intel_crtc_wait_for_pending_flips(crtc); | |
11481 | ||
11482 | /* | |
11483 | * If clipping results in a non-visible primary plane, we'll disable | |
11484 | * the primary plane. Note that this is a bit different than what | |
11485 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11486 | * because plane->fb still gets set and pinned. | |
11487 | */ | |
11488 | if (!visible) { | |
11489 | /* | |
11490 | * Try to pin the new fb first so that we can bail out if we | |
11491 | * fail. | |
11492 | */ | |
11493 | if (plane->fb != fb) { | |
a071fa00 | 11494 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
465c120c MR |
11495 | if (ret) |
11496 | return ret; | |
11497 | } | |
11498 | ||
a071fa00 DV |
11499 | i915_gem_track_fb(old_obj, obj, |
11500 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
11501 | ||
465c120c MR |
11502 | if (intel_crtc->primary_enabled) |
11503 | intel_disable_primary_hw_plane(dev_priv, | |
11504 | intel_plane->plane, | |
11505 | intel_plane->pipe); | |
11506 | ||
11507 | ||
11508 | if (plane->fb != fb) | |
11509 | if (plane->fb) | |
a071fa00 | 11510 | intel_unpin_fb_obj(old_obj); |
465c120c MR |
11511 | |
11512 | return 0; | |
11513 | } | |
11514 | ||
11515 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); | |
11516 | if (ret) | |
11517 | return ret; | |
11518 | ||
11519 | if (!intel_crtc->primary_enabled) | |
11520 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11521 | intel_crtc->pipe); | |
11522 | ||
11523 | return 0; | |
11524 | } | |
11525 | ||
3d7d6510 MR |
11526 | /* Common destruction function for both primary and cursor planes */ |
11527 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11528 | { |
11529 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11530 | drm_plane_cleanup(plane); | |
11531 | kfree(intel_plane); | |
11532 | } | |
11533 | ||
11534 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11535 | .update_plane = intel_primary_plane_setplane, | |
11536 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11537 | .destroy = intel_plane_destroy, |
465c120c MR |
11538 | }; |
11539 | ||
11540 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11541 | int pipe) | |
11542 | { | |
11543 | struct intel_plane *primary; | |
11544 | const uint32_t *intel_primary_formats; | |
11545 | int num_formats; | |
11546 | ||
11547 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11548 | if (primary == NULL) | |
11549 | return NULL; | |
11550 | ||
11551 | primary->can_scale = false; | |
11552 | primary->max_downscale = 1; | |
11553 | primary->pipe = pipe; | |
11554 | primary->plane = pipe; | |
11555 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) | |
11556 | primary->plane = !pipe; | |
11557 | ||
11558 | if (INTEL_INFO(dev)->gen <= 3) { | |
11559 | intel_primary_formats = intel_primary_formats_gen2; | |
11560 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11561 | } else { | |
11562 | intel_primary_formats = intel_primary_formats_gen4; | |
11563 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11564 | } | |
11565 | ||
11566 | drm_universal_plane_init(dev, &primary->base, 0, | |
11567 | &intel_primary_plane_funcs, | |
11568 | intel_primary_formats, num_formats, | |
11569 | DRM_PLANE_TYPE_PRIMARY); | |
11570 | return &primary->base; | |
11571 | } | |
11572 | ||
3d7d6510 MR |
11573 | static int |
11574 | intel_cursor_plane_disable(struct drm_plane *plane) | |
11575 | { | |
11576 | if (!plane->fb) | |
11577 | return 0; | |
11578 | ||
11579 | BUG_ON(!plane->crtc); | |
11580 | ||
11581 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
11582 | } | |
11583 | ||
11584 | static int | |
11585 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
11586 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11587 | unsigned int crtc_w, unsigned int crtc_h, | |
11588 | uint32_t src_x, uint32_t src_y, | |
11589 | uint32_t src_w, uint32_t src_h) | |
11590 | { | |
11591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11592 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
11593 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11594 | struct drm_rect dest = { | |
11595 | /* integer pixels */ | |
11596 | .x1 = crtc_x, | |
11597 | .y1 = crtc_y, | |
11598 | .x2 = crtc_x + crtc_w, | |
11599 | .y2 = crtc_y + crtc_h, | |
11600 | }; | |
11601 | struct drm_rect src = { | |
11602 | /* 16.16 fixed point */ | |
11603 | .x1 = src_x, | |
11604 | .y1 = src_y, | |
11605 | .x2 = src_x + src_w, | |
11606 | .y2 = src_y + src_h, | |
11607 | }; | |
11608 | const struct drm_rect clip = { | |
11609 | /* integer pixels */ | |
11610 | .x2 = intel_crtc->config.pipe_src_w, | |
11611 | .y2 = intel_crtc->config.pipe_src_h, | |
11612 | }; | |
11613 | bool visible; | |
11614 | int ret; | |
11615 | ||
11616 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11617 | &src, &dest, &clip, | |
11618 | DRM_PLANE_HELPER_NO_SCALING, | |
11619 | DRM_PLANE_HELPER_NO_SCALING, | |
11620 | true, true, &visible); | |
11621 | if (ret) | |
11622 | return ret; | |
11623 | ||
11624 | crtc->cursor_x = crtc_x; | |
11625 | crtc->cursor_y = crtc_y; | |
11626 | if (fb != crtc->cursor->fb) { | |
11627 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); | |
11628 | } else { | |
11629 | intel_crtc_update_cursor(crtc, visible); | |
11630 | return 0; | |
11631 | } | |
11632 | } | |
11633 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
11634 | .update_plane = intel_cursor_plane_update, | |
11635 | .disable_plane = intel_cursor_plane_disable, | |
11636 | .destroy = intel_plane_destroy, | |
11637 | }; | |
11638 | ||
11639 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
11640 | int pipe) | |
11641 | { | |
11642 | struct intel_plane *cursor; | |
11643 | ||
11644 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
11645 | if (cursor == NULL) | |
11646 | return NULL; | |
11647 | ||
11648 | cursor->can_scale = false; | |
11649 | cursor->max_downscale = 1; | |
11650 | cursor->pipe = pipe; | |
11651 | cursor->plane = pipe; | |
11652 | ||
11653 | drm_universal_plane_init(dev, &cursor->base, 0, | |
11654 | &intel_cursor_plane_funcs, | |
11655 | intel_cursor_formats, | |
11656 | ARRAY_SIZE(intel_cursor_formats), | |
11657 | DRM_PLANE_TYPE_CURSOR); | |
11658 | return &cursor->base; | |
11659 | } | |
11660 | ||
b358d0a6 | 11661 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11662 | { |
fbee40df | 11663 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11664 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
11665 | struct drm_plane *primary = NULL; |
11666 | struct drm_plane *cursor = NULL; | |
465c120c | 11667 | int i, ret; |
79e53945 | 11668 | |
955382f3 | 11669 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11670 | if (intel_crtc == NULL) |
11671 | return; | |
11672 | ||
465c120c | 11673 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
11674 | if (!primary) |
11675 | goto fail; | |
11676 | ||
11677 | cursor = intel_cursor_plane_create(dev, pipe); | |
11678 | if (!cursor) | |
11679 | goto fail; | |
11680 | ||
465c120c | 11681 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
11682 | cursor, &intel_crtc_funcs); |
11683 | if (ret) | |
11684 | goto fail; | |
79e53945 JB |
11685 | |
11686 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11687 | for (i = 0; i < 256; i++) { |
11688 | intel_crtc->lut_r[i] = i; | |
11689 | intel_crtc->lut_g[i] = i; | |
11690 | intel_crtc->lut_b[i] = i; | |
11691 | } | |
11692 | ||
1f1c2e24 VS |
11693 | /* |
11694 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 11695 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 11696 | */ |
80824003 JB |
11697 | intel_crtc->pipe = pipe; |
11698 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11699 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11700 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11701 | intel_crtc->plane = !pipe; |
80824003 JB |
11702 | } |
11703 | ||
4b0e333e CW |
11704 | intel_crtc->cursor_base = ~0; |
11705 | intel_crtc->cursor_cntl = ~0; | |
11706 | ||
8d7849db VS |
11707 | init_waitqueue_head(&intel_crtc->vbl_wait); |
11708 | ||
22fd0fab JB |
11709 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11710 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11711 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11712 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11713 | ||
79e53945 | 11714 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11715 | |
11716 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
11717 | return; |
11718 | ||
11719 | fail: | |
11720 | if (primary) | |
11721 | drm_plane_cleanup(primary); | |
11722 | if (cursor) | |
11723 | drm_plane_cleanup(cursor); | |
11724 | kfree(intel_crtc); | |
79e53945 JB |
11725 | } |
11726 | ||
752aa88a JB |
11727 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11728 | { | |
11729 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 11730 | struct drm_device *dev = connector->base.dev; |
752aa88a | 11731 | |
51fd371b | 11732 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
11733 | |
11734 | if (!encoder) | |
11735 | return INVALID_PIPE; | |
11736 | ||
11737 | return to_intel_crtc(encoder->crtc)->pipe; | |
11738 | } | |
11739 | ||
08d7b3d1 | 11740 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 11741 | struct drm_file *file) |
08d7b3d1 | 11742 | { |
08d7b3d1 | 11743 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
11744 | struct drm_mode_object *drmmode_obj; |
11745 | struct intel_crtc *crtc; | |
08d7b3d1 | 11746 | |
1cff8f6b DV |
11747 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11748 | return -ENODEV; | |
08d7b3d1 | 11749 | |
c05422d5 DV |
11750 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
11751 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 11752 | |
c05422d5 | 11753 | if (!drmmode_obj) { |
08d7b3d1 | 11754 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 11755 | return -ENOENT; |
08d7b3d1 CW |
11756 | } |
11757 | ||
c05422d5 DV |
11758 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
11759 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 11760 | |
c05422d5 | 11761 | return 0; |
08d7b3d1 CW |
11762 | } |
11763 | ||
66a9278e | 11764 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 11765 | { |
66a9278e DV |
11766 | struct drm_device *dev = encoder->base.dev; |
11767 | struct intel_encoder *source_encoder; | |
79e53945 | 11768 | int index_mask = 0; |
79e53945 JB |
11769 | int entry = 0; |
11770 | ||
66a9278e DV |
11771 | list_for_each_entry(source_encoder, |
11772 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 11773 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
11774 | index_mask |= (1 << entry); |
11775 | ||
79e53945 JB |
11776 | entry++; |
11777 | } | |
4ef69c7a | 11778 | |
79e53945 JB |
11779 | return index_mask; |
11780 | } | |
11781 | ||
4d302442 CW |
11782 | static bool has_edp_a(struct drm_device *dev) |
11783 | { | |
11784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11785 | ||
11786 | if (!IS_MOBILE(dev)) | |
11787 | return false; | |
11788 | ||
11789 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
11790 | return false; | |
11791 | ||
e3589908 | 11792 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
11793 | return false; |
11794 | ||
11795 | return true; | |
11796 | } | |
11797 | ||
ba0fbca4 DL |
11798 | const char *intel_output_name(int output) |
11799 | { | |
11800 | static const char *names[] = { | |
11801 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
11802 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
11803 | [INTEL_OUTPUT_DVO] = "DVO", | |
11804 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
11805 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
11806 | [INTEL_OUTPUT_TVOUT] = "TV", | |
11807 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
11808 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
11809 | [INTEL_OUTPUT_EDP] = "eDP", | |
11810 | [INTEL_OUTPUT_DSI] = "DSI", | |
11811 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
11812 | }; | |
11813 | ||
11814 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
11815 | return "Invalid"; | |
11816 | ||
11817 | return names[output]; | |
11818 | } | |
11819 | ||
84b4e042 JB |
11820 | static bool intel_crt_present(struct drm_device *dev) |
11821 | { | |
11822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11823 | ||
11824 | if (IS_ULT(dev)) | |
11825 | return false; | |
11826 | ||
11827 | if (IS_CHERRYVIEW(dev)) | |
11828 | return false; | |
11829 | ||
11830 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
11831 | return false; | |
11832 | ||
11833 | return true; | |
11834 | } | |
11835 | ||
79e53945 JB |
11836 | static void intel_setup_outputs(struct drm_device *dev) |
11837 | { | |
725e30ad | 11838 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 11839 | struct intel_encoder *encoder; |
cb0953d7 | 11840 | bool dpd_is_edp = false; |
79e53945 | 11841 | |
c9093354 | 11842 | intel_lvds_init(dev); |
79e53945 | 11843 | |
84b4e042 | 11844 | if (intel_crt_present(dev)) |
79935fca | 11845 | intel_crt_init(dev); |
cb0953d7 | 11846 | |
affa9354 | 11847 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
11848 | int found; |
11849 | ||
11850 | /* Haswell uses DDI functions to detect digital outputs */ | |
11851 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
11852 | /* DDI A only supports eDP */ | |
11853 | if (found) | |
11854 | intel_ddi_init(dev, PORT_A); | |
11855 | ||
11856 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
11857 | * register */ | |
11858 | found = I915_READ(SFUSE_STRAP); | |
11859 | ||
11860 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
11861 | intel_ddi_init(dev, PORT_B); | |
11862 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
11863 | intel_ddi_init(dev, PORT_C); | |
11864 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
11865 | intel_ddi_init(dev, PORT_D); | |
11866 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 11867 | int found; |
5d8a7752 | 11868 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
11869 | |
11870 | if (has_edp_a(dev)) | |
11871 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 11872 | |
dc0fa718 | 11873 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 11874 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 11875 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 11876 | if (!found) |
e2debe91 | 11877 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 11878 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 11879 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
11880 | } |
11881 | ||
dc0fa718 | 11882 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 11883 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 11884 | |
dc0fa718 | 11885 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 11886 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 11887 | |
5eb08b69 | 11888 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 11889 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 11890 | |
270b3042 | 11891 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 11892 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 11893 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
11894 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11895 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
11896 | PORT_B); | |
11897 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
11898 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
11899 | } | |
11900 | ||
6f6005a5 JB |
11901 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11902 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
11903 | PORT_C); | |
11904 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 11905 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 11906 | } |
19c03924 | 11907 | |
9418c1f1 VS |
11908 | if (IS_CHERRYVIEW(dev)) { |
11909 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
11910 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
11911 | PORT_D); | |
11912 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
11913 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
11914 | } | |
11915 | } | |
11916 | ||
3cfca973 | 11917 | intel_dsi_init(dev); |
103a196f | 11918 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 11919 | bool found = false; |
7d57382e | 11920 | |
e2debe91 | 11921 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11922 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 11923 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
11924 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11925 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 11926 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 11927 | } |
27185ae1 | 11928 | |
e7281eab | 11929 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11930 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 11931 | } |
13520b05 KH |
11932 | |
11933 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 11934 | |
e2debe91 | 11935 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11936 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11937 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11938 | } |
27185ae1 | 11939 | |
e2debe91 | 11940 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11941 | |
b01f2c3a JB |
11942 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11943 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11944 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11945 | } |
e7281eab | 11946 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11947 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11948 | } |
27185ae1 | 11949 | |
b01f2c3a | 11950 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11951 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11952 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11953 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11954 | intel_dvo_init(dev); |
11955 | ||
103a196f | 11956 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11957 | intel_tv_init(dev); |
11958 | ||
7c8f8a70 RV |
11959 | intel_edp_psr_init(dev); |
11960 | ||
4ef69c7a CW |
11961 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11962 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11963 | encoder->base.possible_clones = | |
66a9278e | 11964 | intel_encoder_clones(encoder); |
79e53945 | 11965 | } |
47356eb6 | 11966 | |
dde86e2d | 11967 | intel_init_pch_refclk(dev); |
270b3042 DV |
11968 | |
11969 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11970 | } |
11971 | ||
11972 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11973 | { | |
60a5ca01 | 11974 | struct drm_device *dev = fb->dev; |
79e53945 | 11975 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 11976 | |
ef2d633e | 11977 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 11978 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 11979 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
11980 | drm_gem_object_unreference(&intel_fb->obj->base); |
11981 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
11982 | kfree(intel_fb); |
11983 | } | |
11984 | ||
11985 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11986 | struct drm_file *file, |
79e53945 JB |
11987 | unsigned int *handle) |
11988 | { | |
11989 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11990 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11991 | |
05394f39 | 11992 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11993 | } |
11994 | ||
11995 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11996 | .destroy = intel_user_framebuffer_destroy, | |
11997 | .create_handle = intel_user_framebuffer_create_handle, | |
11998 | }; | |
11999 | ||
b5ea642a DV |
12000 | static int intel_framebuffer_init(struct drm_device *dev, |
12001 | struct intel_framebuffer *intel_fb, | |
12002 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12003 | struct drm_i915_gem_object *obj) | |
79e53945 | 12004 | { |
a57ce0b2 | 12005 | int aligned_height; |
a35cdaa0 | 12006 | int pitch_limit; |
79e53945 JB |
12007 | int ret; |
12008 | ||
dd4916c5 DV |
12009 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12010 | ||
c16ed4be CW |
12011 | if (obj->tiling_mode == I915_TILING_Y) { |
12012 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12013 | return -EINVAL; |
c16ed4be | 12014 | } |
57cd6508 | 12015 | |
c16ed4be CW |
12016 | if (mode_cmd->pitches[0] & 63) { |
12017 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12018 | mode_cmd->pitches[0]); | |
57cd6508 | 12019 | return -EINVAL; |
c16ed4be | 12020 | } |
57cd6508 | 12021 | |
a35cdaa0 CW |
12022 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12023 | pitch_limit = 32*1024; | |
12024 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12025 | if (obj->tiling_mode) | |
12026 | pitch_limit = 16*1024; | |
12027 | else | |
12028 | pitch_limit = 32*1024; | |
12029 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12030 | if (obj->tiling_mode) | |
12031 | pitch_limit = 8*1024; | |
12032 | else | |
12033 | pitch_limit = 16*1024; | |
12034 | } else | |
12035 | /* XXX DSPC is limited to 4k tiled */ | |
12036 | pitch_limit = 8*1024; | |
12037 | ||
12038 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12039 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12040 | obj->tiling_mode ? "tiled" : "linear", | |
12041 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12042 | return -EINVAL; |
c16ed4be | 12043 | } |
5d7bd705 VS |
12044 | |
12045 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12046 | mode_cmd->pitches[0] != obj->stride) { |
12047 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12048 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12049 | return -EINVAL; |
c16ed4be | 12050 | } |
5d7bd705 | 12051 | |
57779d06 | 12052 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12053 | switch (mode_cmd->pixel_format) { |
57779d06 | 12054 | case DRM_FORMAT_C8: |
04b3924d VS |
12055 | case DRM_FORMAT_RGB565: |
12056 | case DRM_FORMAT_XRGB8888: | |
12057 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12058 | break; |
12059 | case DRM_FORMAT_XRGB1555: | |
12060 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12061 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12062 | DRM_DEBUG("unsupported pixel format: %s\n", |
12063 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12064 | return -EINVAL; |
c16ed4be | 12065 | } |
57779d06 VS |
12066 | break; |
12067 | case DRM_FORMAT_XBGR8888: | |
12068 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12069 | case DRM_FORMAT_XRGB2101010: |
12070 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12071 | case DRM_FORMAT_XBGR2101010: |
12072 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12073 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12074 | DRM_DEBUG("unsupported pixel format: %s\n", |
12075 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12076 | return -EINVAL; |
c16ed4be | 12077 | } |
b5626747 | 12078 | break; |
04b3924d VS |
12079 | case DRM_FORMAT_YUYV: |
12080 | case DRM_FORMAT_UYVY: | |
12081 | case DRM_FORMAT_YVYU: | |
12082 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12083 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12084 | DRM_DEBUG("unsupported pixel format: %s\n", |
12085 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12086 | return -EINVAL; |
c16ed4be | 12087 | } |
57cd6508 CW |
12088 | break; |
12089 | default: | |
4ee62c76 VS |
12090 | DRM_DEBUG("unsupported pixel format: %s\n", |
12091 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12092 | return -EINVAL; |
12093 | } | |
12094 | ||
90f9a336 VS |
12095 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12096 | if (mode_cmd->offsets[0] != 0) | |
12097 | return -EINVAL; | |
12098 | ||
a57ce0b2 JB |
12099 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12100 | obj->tiling_mode); | |
53155c0a DV |
12101 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12102 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12103 | return -EINVAL; | |
12104 | ||
c7d73f6a DV |
12105 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12106 | intel_fb->obj = obj; | |
80075d49 | 12107 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12108 | |
79e53945 JB |
12109 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12110 | if (ret) { | |
12111 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12112 | return ret; | |
12113 | } | |
12114 | ||
79e53945 JB |
12115 | return 0; |
12116 | } | |
12117 | ||
79e53945 JB |
12118 | static struct drm_framebuffer * |
12119 | intel_user_framebuffer_create(struct drm_device *dev, | |
12120 | struct drm_file *filp, | |
308e5bcb | 12121 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12122 | { |
05394f39 | 12123 | struct drm_i915_gem_object *obj; |
79e53945 | 12124 | |
308e5bcb JB |
12125 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12126 | mode_cmd->handles[0])); | |
c8725226 | 12127 | if (&obj->base == NULL) |
cce13ff7 | 12128 | return ERR_PTR(-ENOENT); |
79e53945 | 12129 | |
d2dff872 | 12130 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12131 | } |
12132 | ||
4520f53a | 12133 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12134 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12135 | { |
12136 | } | |
12137 | #endif | |
12138 | ||
79e53945 | 12139 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12140 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12141 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12142 | }; |
12143 | ||
e70236a8 JB |
12144 | /* Set up chip specific display functions */ |
12145 | static void intel_init_display(struct drm_device *dev) | |
12146 | { | |
12147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12148 | ||
ee9300bb DV |
12149 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12150 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12151 | else if (IS_CHERRYVIEW(dev)) |
12152 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12153 | else if (IS_VALLEYVIEW(dev)) |
12154 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12155 | else if (IS_PINEVIEW(dev)) | |
12156 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12157 | else | |
12158 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12159 | ||
affa9354 | 12160 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12161 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12162 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 12163 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
12164 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12165 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 12166 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
12167 | dev_priv->display.update_primary_plane = |
12168 | ironlake_update_primary_plane; | |
09b4ddf9 | 12169 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12170 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12171 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 12172 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
12173 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12174 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12175 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12176 | dev_priv->display.update_primary_plane = |
12177 | ironlake_update_primary_plane; | |
89b667f8 JB |
12178 | } else if (IS_VALLEYVIEW(dev)) { |
12179 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12180 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
12181 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12182 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
12183 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12184 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12185 | dev_priv->display.update_primary_plane = |
12186 | i9xx_update_primary_plane; | |
f564048e | 12187 | } else { |
0e8ffe1b | 12188 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12189 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 12190 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
12191 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12192 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12193 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12194 | dev_priv->display.update_primary_plane = |
12195 | i9xx_update_primary_plane; | |
f564048e | 12196 | } |
e70236a8 | 12197 | |
e70236a8 | 12198 | /* Returns the core display clock speed */ |
25eb05fc JB |
12199 | if (IS_VALLEYVIEW(dev)) |
12200 | dev_priv->display.get_display_clock_speed = | |
12201 | valleyview_get_display_clock_speed; | |
12202 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12203 | dev_priv->display.get_display_clock_speed = |
12204 | i945_get_display_clock_speed; | |
12205 | else if (IS_I915G(dev)) | |
12206 | dev_priv->display.get_display_clock_speed = | |
12207 | i915_get_display_clock_speed; | |
257a7ffc | 12208 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12209 | dev_priv->display.get_display_clock_speed = |
12210 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12211 | else if (IS_PINEVIEW(dev)) |
12212 | dev_priv->display.get_display_clock_speed = | |
12213 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12214 | else if (IS_I915GM(dev)) |
12215 | dev_priv->display.get_display_clock_speed = | |
12216 | i915gm_get_display_clock_speed; | |
12217 | else if (IS_I865G(dev)) | |
12218 | dev_priv->display.get_display_clock_speed = | |
12219 | i865_get_display_clock_speed; | |
f0f8a9ce | 12220 | else if (IS_I85X(dev)) |
e70236a8 JB |
12221 | dev_priv->display.get_display_clock_speed = |
12222 | i855_get_display_clock_speed; | |
12223 | else /* 852, 830 */ | |
12224 | dev_priv->display.get_display_clock_speed = | |
12225 | i830_get_display_clock_speed; | |
12226 | ||
7f8a8569 | 12227 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 12228 | if (IS_GEN5(dev)) { |
674cf967 | 12229 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 12230 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 12231 | } else if (IS_GEN6(dev)) { |
674cf967 | 12232 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 12233 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
12234 | dev_priv->display.modeset_global_resources = |
12235 | snb_modeset_global_resources; | |
357555c0 JB |
12236 | } else if (IS_IVYBRIDGE(dev)) { |
12237 | /* FIXME: detect B0+ stepping and use auto training */ | |
12238 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 12239 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
12240 | dev_priv->display.modeset_global_resources = |
12241 | ivb_modeset_global_resources; | |
4e0bbc31 | 12242 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 12243 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 12244 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
12245 | dev_priv->display.modeset_global_resources = |
12246 | haswell_modeset_global_resources; | |
a0e63c22 | 12247 | } |
6067aaea | 12248 | } else if (IS_G4X(dev)) { |
e0dac65e | 12249 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
12250 | } else if (IS_VALLEYVIEW(dev)) { |
12251 | dev_priv->display.modeset_global_resources = | |
12252 | valleyview_modeset_global_resources; | |
9ca2fe73 | 12253 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 12254 | } |
8c9f3aaf JB |
12255 | |
12256 | /* Default just returns -ENODEV to indicate unsupported */ | |
12257 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12258 | ||
12259 | switch (INTEL_INFO(dev)->gen) { | |
12260 | case 2: | |
12261 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12262 | break; | |
12263 | ||
12264 | case 3: | |
12265 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12266 | break; | |
12267 | ||
12268 | case 4: | |
12269 | case 5: | |
12270 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12271 | break; | |
12272 | ||
12273 | case 6: | |
12274 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12275 | break; | |
7c9017e5 | 12276 | case 7: |
4e0bbc31 | 12277 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12278 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12279 | break; | |
8c9f3aaf | 12280 | } |
7bd688cd JN |
12281 | |
12282 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
12283 | } |
12284 | ||
b690e96c JB |
12285 | /* |
12286 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12287 | * resume, or other times. This quirk makes sure that's the case for | |
12288 | * affected systems. | |
12289 | */ | |
0206e353 | 12290 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12291 | { |
12292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12293 | ||
12294 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12295 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12296 | } |
12297 | ||
435793df KP |
12298 | /* |
12299 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12300 | */ | |
12301 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12302 | { | |
12303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12304 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12305 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12306 | } |
12307 | ||
4dca20ef | 12308 | /* |
5a15ab5b CE |
12309 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12310 | * brightness value | |
4dca20ef CE |
12311 | */ |
12312 | static void quirk_invert_brightness(struct drm_device *dev) | |
12313 | { | |
12314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12315 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12316 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12317 | } |
12318 | ||
b690e96c JB |
12319 | struct intel_quirk { |
12320 | int device; | |
12321 | int subsystem_vendor; | |
12322 | int subsystem_device; | |
12323 | void (*hook)(struct drm_device *dev); | |
12324 | }; | |
12325 | ||
5f85f176 EE |
12326 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12327 | struct intel_dmi_quirk { | |
12328 | void (*hook)(struct drm_device *dev); | |
12329 | const struct dmi_system_id (*dmi_id_list)[]; | |
12330 | }; | |
12331 | ||
12332 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12333 | { | |
12334 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12335 | return 1; | |
12336 | } | |
12337 | ||
12338 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12339 | { | |
12340 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12341 | { | |
12342 | .callback = intel_dmi_reverse_brightness, | |
12343 | .ident = "NCR Corporation", | |
12344 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12345 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12346 | }, | |
12347 | }, | |
12348 | { } /* terminating entry */ | |
12349 | }, | |
12350 | .hook = quirk_invert_brightness, | |
12351 | }, | |
12352 | }; | |
12353 | ||
c43b5634 | 12354 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12355 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12356 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12357 | |
b690e96c JB |
12358 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12359 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12360 | ||
b690e96c JB |
12361 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12362 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12363 | ||
435793df KP |
12364 | /* Lenovo U160 cannot use SSC on LVDS */ |
12365 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12366 | |
12367 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12368 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12369 | |
be505f64 AH |
12370 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12371 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12372 | ||
12373 | /* Acer/eMachines G725 */ | |
12374 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12375 | ||
12376 | /* Acer/eMachines e725 */ | |
12377 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12378 | ||
12379 | /* Acer/Packard Bell NCL20 */ | |
12380 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12381 | ||
12382 | /* Acer Aspire 4736Z */ | |
12383 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12384 | |
12385 | /* Acer Aspire 5336 */ | |
12386 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
12387 | }; |
12388 | ||
12389 | static void intel_init_quirks(struct drm_device *dev) | |
12390 | { | |
12391 | struct pci_dev *d = dev->pdev; | |
12392 | int i; | |
12393 | ||
12394 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12395 | struct intel_quirk *q = &intel_quirks[i]; | |
12396 | ||
12397 | if (d->device == q->device && | |
12398 | (d->subsystem_vendor == q->subsystem_vendor || | |
12399 | q->subsystem_vendor == PCI_ANY_ID) && | |
12400 | (d->subsystem_device == q->subsystem_device || | |
12401 | q->subsystem_device == PCI_ANY_ID)) | |
12402 | q->hook(dev); | |
12403 | } | |
5f85f176 EE |
12404 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12405 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12406 | intel_dmi_quirks[i].hook(dev); | |
12407 | } | |
b690e96c JB |
12408 | } |
12409 | ||
9cce37f4 JB |
12410 | /* Disable the VGA plane that we never use */ |
12411 | static void i915_disable_vga(struct drm_device *dev) | |
12412 | { | |
12413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12414 | u8 sr1; | |
766aa1c4 | 12415 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12416 | |
2b37c616 | 12417 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12418 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12419 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12420 | sr1 = inb(VGA_SR_DATA); |
12421 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12422 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12423 | udelay(300); | |
12424 | ||
12425 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
12426 | POSTING_READ(vga_reg); | |
12427 | } | |
12428 | ||
f817586c DV |
12429 | void intel_modeset_init_hw(struct drm_device *dev) |
12430 | { | |
a8f78b58 ED |
12431 | intel_prepare_ddi(dev); |
12432 | ||
f817586c DV |
12433 | intel_init_clock_gating(dev); |
12434 | ||
5382f5f3 | 12435 | intel_reset_dpio(dev); |
40e9cf64 | 12436 | |
8090c6b9 | 12437 | intel_enable_gt_powersave(dev); |
f817586c DV |
12438 | } |
12439 | ||
7d708ee4 ID |
12440 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12441 | { | |
12442 | intel_suspend_hw(dev); | |
12443 | } | |
12444 | ||
79e53945 JB |
12445 | void intel_modeset_init(struct drm_device *dev) |
12446 | { | |
652c393a | 12447 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12448 | int sprite, ret; |
8cc87b75 | 12449 | enum pipe pipe; |
46f297fb | 12450 | struct intel_crtc *crtc; |
79e53945 JB |
12451 | |
12452 | drm_mode_config_init(dev); | |
12453 | ||
12454 | dev->mode_config.min_width = 0; | |
12455 | dev->mode_config.min_height = 0; | |
12456 | ||
019d96cb DA |
12457 | dev->mode_config.preferred_depth = 24; |
12458 | dev->mode_config.prefer_shadow = 1; | |
12459 | ||
e6ecefaa | 12460 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12461 | |
b690e96c JB |
12462 | intel_init_quirks(dev); |
12463 | ||
1fa61106 ED |
12464 | intel_init_pm(dev); |
12465 | ||
e3c74757 BW |
12466 | if (INTEL_INFO(dev)->num_pipes == 0) |
12467 | return; | |
12468 | ||
e70236a8 JB |
12469 | intel_init_display(dev); |
12470 | ||
a6c45cf0 CW |
12471 | if (IS_GEN2(dev)) { |
12472 | dev->mode_config.max_width = 2048; | |
12473 | dev->mode_config.max_height = 2048; | |
12474 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12475 | dev->mode_config.max_width = 4096; |
12476 | dev->mode_config.max_height = 4096; | |
79e53945 | 12477 | } else { |
a6c45cf0 CW |
12478 | dev->mode_config.max_width = 8192; |
12479 | dev->mode_config.max_height = 8192; | |
79e53945 | 12480 | } |
068be561 DL |
12481 | |
12482 | if (IS_GEN2(dev)) { | |
12483 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
12484 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12485 | } else { | |
12486 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12487 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12488 | } | |
12489 | ||
5d4545ae | 12490 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12491 | |
28c97730 | 12492 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12493 | INTEL_INFO(dev)->num_pipes, |
12494 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12495 | |
8cc87b75 DL |
12496 | for_each_pipe(pipe) { |
12497 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
12498 | for_each_sprite(pipe, sprite) { |
12499 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12500 | if (ret) |
06da8da2 | 12501 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12502 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12503 | } |
79e53945 JB |
12504 | } |
12505 | ||
f42bb70d | 12506 | intel_init_dpio(dev); |
5382f5f3 | 12507 | intel_reset_dpio(dev); |
f42bb70d | 12508 | |
79f689aa | 12509 | intel_cpu_pll_init(dev); |
e72f9fbf | 12510 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12511 | |
9cce37f4 JB |
12512 | /* Just disable it once at startup */ |
12513 | i915_disable_vga(dev); | |
79e53945 | 12514 | intel_setup_outputs(dev); |
11be49eb CW |
12515 | |
12516 | /* Just in case the BIOS is doing something questionable. */ | |
12517 | intel_disable_fbc(dev); | |
fa9fa083 | 12518 | |
6e9f798d | 12519 | drm_modeset_lock_all(dev); |
fa9fa083 | 12520 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12521 | drm_modeset_unlock_all(dev); |
46f297fb | 12522 | |
d3fcc808 | 12523 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12524 | if (!crtc->active) |
12525 | continue; | |
12526 | ||
46f297fb | 12527 | /* |
46f297fb JB |
12528 | * Note that reserving the BIOS fb up front prevents us |
12529 | * from stuffing other stolen allocations like the ring | |
12530 | * on top. This prevents some ugliness at boot time, and | |
12531 | * can even allow for smooth boot transitions if the BIOS | |
12532 | * fb is large enough for the active pipe configuration. | |
12533 | */ | |
12534 | if (dev_priv->display.get_plane_config) { | |
12535 | dev_priv->display.get_plane_config(crtc, | |
12536 | &crtc->plane_config); | |
12537 | /* | |
12538 | * If the fb is shared between multiple heads, we'll | |
12539 | * just get the first one. | |
12540 | */ | |
484b41dd | 12541 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12542 | } |
46f297fb | 12543 | } |
2c7111db CW |
12544 | } |
12545 | ||
7fad798e DV |
12546 | static void intel_enable_pipe_a(struct drm_device *dev) |
12547 | { | |
12548 | struct intel_connector *connector; | |
12549 | struct drm_connector *crt = NULL; | |
12550 | struct intel_load_detect_pipe load_detect_temp; | |
51fd371b | 12551 | struct drm_modeset_acquire_ctx ctx; |
7fad798e DV |
12552 | |
12553 | /* We can't just switch on the pipe A, we need to set things up with a | |
12554 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12555 | * by enabling the load detect pipe once. */ | |
12556 | list_for_each_entry(connector, | |
12557 | &dev->mode_config.connector_list, | |
12558 | base.head) { | |
12559 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12560 | crt = &connector->base; | |
12561 | break; | |
12562 | } | |
12563 | } | |
12564 | ||
12565 | if (!crt) | |
12566 | return; | |
12567 | ||
51fd371b RC |
12568 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) |
12569 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | |
7fad798e | 12570 | |
652c393a | 12571 | |
7fad798e DV |
12572 | } |
12573 | ||
fa555837 DV |
12574 | static bool |
12575 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12576 | { | |
7eb552ae BW |
12577 | struct drm_device *dev = crtc->base.dev; |
12578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12579 | u32 reg, val; |
12580 | ||
7eb552ae | 12581 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12582 | return true; |
12583 | ||
12584 | reg = DSPCNTR(!crtc->plane); | |
12585 | val = I915_READ(reg); | |
12586 | ||
12587 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12588 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12589 | return false; | |
12590 | ||
12591 | return true; | |
12592 | } | |
12593 | ||
24929352 DV |
12594 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12595 | { | |
12596 | struct drm_device *dev = crtc->base.dev; | |
12597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12598 | u32 reg; |
24929352 | 12599 | |
24929352 | 12600 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12601 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12602 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12603 | ||
d3eaf884 VS |
12604 | /* restore vblank interrupts to correct state */ |
12605 | if (crtc->active) | |
12606 | drm_vblank_on(dev, crtc->pipe); | |
12607 | else | |
12608 | drm_vblank_off(dev, crtc->pipe); | |
12609 | ||
24929352 | 12610 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12611 | * disable the crtc (and hence change the state) if it is wrong. Note |
12612 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12613 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12614 | struct intel_connector *connector; |
12615 | bool plane; | |
12616 | ||
24929352 DV |
12617 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12618 | crtc->base.base.id); | |
12619 | ||
12620 | /* Pipe has the wrong plane attached and the plane is active. | |
12621 | * Temporarily change the plane mapping and disable everything | |
12622 | * ... */ | |
12623 | plane = crtc->plane; | |
12624 | crtc->plane = !plane; | |
12625 | dev_priv->display.crtc_disable(&crtc->base); | |
12626 | crtc->plane = plane; | |
12627 | ||
12628 | /* ... and break all links. */ | |
12629 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12630 | base.head) { | |
12631 | if (connector->encoder->base.crtc != &crtc->base) | |
12632 | continue; | |
12633 | ||
7f1950fb EE |
12634 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12635 | connector->base.encoder = NULL; | |
24929352 | 12636 | } |
7f1950fb EE |
12637 | /* multiple connectors may have the same encoder: |
12638 | * handle them and break crtc link separately */ | |
12639 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12640 | base.head) | |
12641 | if (connector->encoder->base.crtc == &crtc->base) { | |
12642 | connector->encoder->base.crtc = NULL; | |
12643 | connector->encoder->connectors_active = false; | |
12644 | } | |
24929352 DV |
12645 | |
12646 | WARN_ON(crtc->active); | |
12647 | crtc->base.enabled = false; | |
12648 | } | |
24929352 | 12649 | |
7fad798e DV |
12650 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12651 | crtc->pipe == PIPE_A && !crtc->active) { | |
12652 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12653 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12654 | * call below we restore the pipe to the right state, but leave | |
12655 | * the required bits on. */ | |
12656 | intel_enable_pipe_a(dev); | |
12657 | } | |
12658 | ||
24929352 DV |
12659 | /* Adjust the state of the output pipe according to whether we |
12660 | * have active connectors/encoders. */ | |
12661 | intel_crtc_update_dpms(&crtc->base); | |
12662 | ||
12663 | if (crtc->active != crtc->base.enabled) { | |
12664 | struct intel_encoder *encoder; | |
12665 | ||
12666 | /* This can happen either due to bugs in the get_hw_state | |
12667 | * functions or because the pipe is force-enabled due to the | |
12668 | * pipe A quirk. */ | |
12669 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12670 | crtc->base.base.id, | |
12671 | crtc->base.enabled ? "enabled" : "disabled", | |
12672 | crtc->active ? "enabled" : "disabled"); | |
12673 | ||
12674 | crtc->base.enabled = crtc->active; | |
12675 | ||
12676 | /* Because we only establish the connector -> encoder -> | |
12677 | * crtc links if something is active, this means the | |
12678 | * crtc is now deactivated. Break the links. connector | |
12679 | * -> encoder links are only establish when things are | |
12680 | * actually up, hence no need to break them. */ | |
12681 | WARN_ON(crtc->active); | |
12682 | ||
12683 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12684 | WARN_ON(encoder->connectors_active); | |
12685 | encoder->base.crtc = NULL; | |
12686 | } | |
12687 | } | |
c5ab3bc0 DV |
12688 | |
12689 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12690 | /* |
12691 | * We start out with underrun reporting disabled to avoid races. | |
12692 | * For correct bookkeeping mark this on active crtcs. | |
12693 | * | |
c5ab3bc0 DV |
12694 | * Also on gmch platforms we dont have any hardware bits to |
12695 | * disable the underrun reporting. Which means we need to start | |
12696 | * out with underrun reporting disabled also on inactive pipes, | |
12697 | * since otherwise we'll complain about the garbage we read when | |
12698 | * e.g. coming up after runtime pm. | |
12699 | * | |
4cc31489 DV |
12700 | * No protection against concurrent access is required - at |
12701 | * worst a fifo underrun happens which also sets this to false. | |
12702 | */ | |
12703 | crtc->cpu_fifo_underrun_disabled = true; | |
12704 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12705 | |
12706 | update_scanline_offset(crtc); | |
4cc31489 | 12707 | } |
24929352 DV |
12708 | } |
12709 | ||
12710 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
12711 | { | |
12712 | struct intel_connector *connector; | |
12713 | struct drm_device *dev = encoder->base.dev; | |
12714 | ||
12715 | /* We need to check both for a crtc link (meaning that the | |
12716 | * encoder is active and trying to read from a pipe) and the | |
12717 | * pipe itself being active. */ | |
12718 | bool has_active_crtc = encoder->base.crtc && | |
12719 | to_intel_crtc(encoder->base.crtc)->active; | |
12720 | ||
12721 | if (encoder->connectors_active && !has_active_crtc) { | |
12722 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
12723 | encoder->base.base.id, | |
8e329a03 | 12724 | encoder->base.name); |
24929352 DV |
12725 | |
12726 | /* Connector is active, but has no active pipe. This is | |
12727 | * fallout from our resume register restoring. Disable | |
12728 | * the encoder manually again. */ | |
12729 | if (encoder->base.crtc) { | |
12730 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
12731 | encoder->base.base.id, | |
8e329a03 | 12732 | encoder->base.name); |
24929352 DV |
12733 | encoder->disable(encoder); |
12734 | } | |
7f1950fb EE |
12735 | encoder->base.crtc = NULL; |
12736 | encoder->connectors_active = false; | |
24929352 DV |
12737 | |
12738 | /* Inconsistent output/port/pipe state happens presumably due to | |
12739 | * a bug in one of the get_hw_state functions. Or someplace else | |
12740 | * in our code, like the register restore mess on resume. Clamp | |
12741 | * things to off as a safer default. */ | |
12742 | list_for_each_entry(connector, | |
12743 | &dev->mode_config.connector_list, | |
12744 | base.head) { | |
12745 | if (connector->encoder != encoder) | |
12746 | continue; | |
7f1950fb EE |
12747 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12748 | connector->base.encoder = NULL; | |
24929352 DV |
12749 | } |
12750 | } | |
12751 | /* Enabled encoders without active connectors will be fixed in | |
12752 | * the crtc fixup. */ | |
12753 | } | |
12754 | ||
04098753 | 12755 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
12756 | { |
12757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 12758 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 12759 | |
04098753 ID |
12760 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
12761 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
12762 | i915_disable_vga(dev); | |
12763 | } | |
12764 | } | |
12765 | ||
12766 | void i915_redisable_vga(struct drm_device *dev) | |
12767 | { | |
12768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12769 | ||
8dc8a27c PZ |
12770 | /* This function can be called both from intel_modeset_setup_hw_state or |
12771 | * at a very early point in our resume sequence, where the power well | |
12772 | * structures are not yet restored. Since this function is at a very | |
12773 | * paranoid "someone might have enabled VGA while we were not looking" | |
12774 | * level, just check if the power well is enabled instead of trying to | |
12775 | * follow the "don't touch the power well if we don't need it" policy | |
12776 | * the rest of the driver uses. */ | |
04098753 | 12777 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
12778 | return; |
12779 | ||
04098753 | 12780 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
12781 | } |
12782 | ||
98ec7739 VS |
12783 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
12784 | { | |
12785 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
12786 | ||
12787 | if (!crtc->active) | |
12788 | return false; | |
12789 | ||
12790 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
12791 | } | |
12792 | ||
30e984df | 12793 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
12794 | { |
12795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12796 | enum pipe pipe; | |
24929352 DV |
12797 | struct intel_crtc *crtc; |
12798 | struct intel_encoder *encoder; | |
12799 | struct intel_connector *connector; | |
5358901f | 12800 | int i; |
24929352 | 12801 | |
d3fcc808 | 12802 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 12803 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 12804 | |
9953599b DV |
12805 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
12806 | ||
0e8ffe1b DV |
12807 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12808 | &crtc->config); | |
24929352 DV |
12809 | |
12810 | crtc->base.enabled = crtc->active; | |
98ec7739 | 12811 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
12812 | |
12813 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
12814 | crtc->base.base.id, | |
12815 | crtc->active ? "enabled" : "disabled"); | |
12816 | } | |
12817 | ||
5358901f | 12818 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 12819 | if (HAS_DDI(dev)) |
6441ab5f PZ |
12820 | intel_ddi_setup_hw_pll_state(dev); |
12821 | ||
5358901f DV |
12822 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12823 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12824 | ||
12825 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
12826 | pll->active = 0; | |
d3fcc808 | 12827 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
12828 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12829 | pll->active++; | |
12830 | } | |
12831 | pll->refcount = pll->active; | |
12832 | ||
35c95375 DV |
12833 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
12834 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
12835 | } |
12836 | ||
24929352 DV |
12837 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12838 | base.head) { | |
12839 | pipe = 0; | |
12840 | ||
12841 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
12842 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12843 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 12844 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
12845 | } else { |
12846 | encoder->base.crtc = NULL; | |
12847 | } | |
12848 | ||
12849 | encoder->connectors_active = false; | |
6f2bcceb | 12850 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 12851 | encoder->base.base.id, |
8e329a03 | 12852 | encoder->base.name, |
24929352 | 12853 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 12854 | pipe_name(pipe)); |
24929352 DV |
12855 | } |
12856 | ||
12857 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12858 | base.head) { | |
12859 | if (connector->get_hw_state(connector)) { | |
12860 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
12861 | connector->encoder->connectors_active = true; | |
12862 | connector->base.encoder = &connector->encoder->base; | |
12863 | } else { | |
12864 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
12865 | connector->base.encoder = NULL; | |
12866 | } | |
12867 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
12868 | connector->base.base.id, | |
c23cc417 | 12869 | connector->base.name, |
24929352 DV |
12870 | connector->base.encoder ? "enabled" : "disabled"); |
12871 | } | |
30e984df DV |
12872 | } |
12873 | ||
12874 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
12875 | * and i915 state tracking structures. */ | |
12876 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
12877 | bool force_restore) | |
12878 | { | |
12879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12880 | enum pipe pipe; | |
30e984df DV |
12881 | struct intel_crtc *crtc; |
12882 | struct intel_encoder *encoder; | |
35c95375 | 12883 | int i; |
30e984df DV |
12884 | |
12885 | intel_modeset_readout_hw_state(dev); | |
24929352 | 12886 | |
babea61d JB |
12887 | /* |
12888 | * Now that we have the config, copy it to each CRTC struct | |
12889 | * Note that this could go away if we move to using crtc_config | |
12890 | * checking everywhere. | |
12891 | */ | |
d3fcc808 | 12892 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 12893 | if (crtc->active && i915.fastboot) { |
f6a83288 | 12894 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
12895 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12896 | crtc->base.base.id); | |
12897 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
12898 | } | |
12899 | } | |
12900 | ||
24929352 DV |
12901 | /* HW state is read out, now we need to sanitize this mess. */ |
12902 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
12903 | base.head) { | |
12904 | intel_sanitize_encoder(encoder); | |
12905 | } | |
12906 | ||
12907 | for_each_pipe(pipe) { | |
12908 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
12909 | intel_sanitize_crtc(crtc); | |
c0b03411 | 12910 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 12911 | } |
9a935856 | 12912 | |
35c95375 DV |
12913 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12914 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12915 | ||
12916 | if (!pll->on || pll->active) | |
12917 | continue; | |
12918 | ||
12919 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
12920 | ||
12921 | pll->disable(dev_priv, pll); | |
12922 | pll->on = false; | |
12923 | } | |
12924 | ||
96f90c54 | 12925 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
12926 | ilk_wm_get_hw_state(dev); |
12927 | ||
45e2b5f6 | 12928 | if (force_restore) { |
7d0bc1ea VS |
12929 | i915_redisable_vga(dev); |
12930 | ||
f30da187 DV |
12931 | /* |
12932 | * We need to use raw interfaces for restoring state to avoid | |
12933 | * checking (bogus) intermediate states. | |
12934 | */ | |
45e2b5f6 | 12935 | for_each_pipe(pipe) { |
b5644d05 JB |
12936 | struct drm_crtc *crtc = |
12937 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
12938 | |
12939 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 12940 | crtc->primary->fb); |
45e2b5f6 DV |
12941 | } |
12942 | } else { | |
12943 | intel_modeset_update_staged_output_state(dev); | |
12944 | } | |
8af6cf88 DV |
12945 | |
12946 | intel_modeset_check_state(dev); | |
2c7111db CW |
12947 | } |
12948 | ||
12949 | void intel_modeset_gem_init(struct drm_device *dev) | |
12950 | { | |
484b41dd JB |
12951 | struct drm_crtc *c; |
12952 | struct intel_framebuffer *fb; | |
12953 | ||
ae48434c ID |
12954 | mutex_lock(&dev->struct_mutex); |
12955 | intel_init_gt_powersave(dev); | |
12956 | mutex_unlock(&dev->struct_mutex); | |
12957 | ||
1833b134 | 12958 | intel_modeset_init_hw(dev); |
02e792fb DV |
12959 | |
12960 | intel_setup_overlay(dev); | |
484b41dd JB |
12961 | |
12962 | /* | |
12963 | * Make sure any fbs we allocated at startup are properly | |
12964 | * pinned & fenced. When we do the allocation it's too early | |
12965 | * for this. | |
12966 | */ | |
12967 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12968 | for_each_crtc(dev, c) { |
66e514c1 | 12969 | if (!c->primary->fb) |
484b41dd JB |
12970 | continue; |
12971 | ||
66e514c1 | 12972 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12973 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12974 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12975 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12976 | drm_framebuffer_unreference(c->primary->fb); |
12977 | c->primary->fb = NULL; | |
484b41dd JB |
12978 | } |
12979 | } | |
12980 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12981 | } |
12982 | ||
4932e2c3 ID |
12983 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12984 | { | |
12985 | struct drm_connector *connector = &intel_connector->base; | |
12986 | ||
12987 | intel_panel_destroy_backlight(connector); | |
12988 | drm_sysfs_connector_remove(connector); | |
12989 | } | |
12990 | ||
79e53945 JB |
12991 | void intel_modeset_cleanup(struct drm_device *dev) |
12992 | { | |
652c393a | 12993 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 12994 | struct drm_connector *connector; |
652c393a | 12995 | |
fd0c0642 DV |
12996 | /* |
12997 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12998 | * Too much stuff here (turning of rps, connectors, ...) would | |
12999 | * experience fancy races otherwise. | |
13000 | */ | |
13001 | drm_irq_uninstall(dev); | |
13002 | cancel_work_sync(&dev_priv->hotplug_work); | |
13003 | /* | |
13004 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13005 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13006 | */ | |
f87ea761 | 13007 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13008 | |
652c393a JB |
13009 | mutex_lock(&dev->struct_mutex); |
13010 | ||
723bfd70 JB |
13011 | intel_unregister_dsm_handler(); |
13012 | ||
973d04f9 | 13013 | intel_disable_fbc(dev); |
e70236a8 | 13014 | |
8090c6b9 | 13015 | intel_disable_gt_powersave(dev); |
0cdab21f | 13016 | |
930ebb46 DV |
13017 | ironlake_teardown_rc6(dev); |
13018 | ||
69341a5e KH |
13019 | mutex_unlock(&dev->struct_mutex); |
13020 | ||
1630fe75 CW |
13021 | /* flush any delayed tasks or pending work */ |
13022 | flush_scheduled_work(); | |
13023 | ||
db31af1d JN |
13024 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13025 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13026 | struct intel_connector *intel_connector; |
13027 | ||
13028 | intel_connector = to_intel_connector(connector); | |
13029 | intel_connector->unregister(intel_connector); | |
db31af1d | 13030 | } |
d9255d57 | 13031 | |
79e53945 | 13032 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13033 | |
13034 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13035 | |
13036 | mutex_lock(&dev->struct_mutex); | |
13037 | intel_cleanup_gt_powersave(dev); | |
13038 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13039 | } |
13040 | ||
f1c79df3 ZW |
13041 | /* |
13042 | * Return which encoder is currently attached for connector. | |
13043 | */ | |
df0e9248 | 13044 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13045 | { |
df0e9248 CW |
13046 | return &intel_attached_encoder(connector)->base; |
13047 | } | |
f1c79df3 | 13048 | |
df0e9248 CW |
13049 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13050 | struct intel_encoder *encoder) | |
13051 | { | |
13052 | connector->encoder = encoder; | |
13053 | drm_mode_connector_attach_encoder(&connector->base, | |
13054 | &encoder->base); | |
79e53945 | 13055 | } |
28d52043 DA |
13056 | |
13057 | /* | |
13058 | * set vga decode state - true == enable VGA decode | |
13059 | */ | |
13060 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13061 | { | |
13062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13063 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13064 | u16 gmch_ctrl; |
13065 | ||
75fa041d CW |
13066 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13067 | DRM_ERROR("failed to read control word\n"); | |
13068 | return -EIO; | |
13069 | } | |
13070 | ||
c0cc8a55 CW |
13071 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13072 | return 0; | |
13073 | ||
28d52043 DA |
13074 | if (state) |
13075 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13076 | else | |
13077 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13078 | |
13079 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13080 | DRM_ERROR("failed to write control word\n"); | |
13081 | return -EIO; | |
13082 | } | |
13083 | ||
28d52043 DA |
13084 | return 0; |
13085 | } | |
c4a1d9e4 | 13086 | |
c4a1d9e4 | 13087 | struct intel_display_error_state { |
ff57f1b0 PZ |
13088 | |
13089 | u32 power_well_driver; | |
13090 | ||
63b66e5b CW |
13091 | int num_transcoders; |
13092 | ||
c4a1d9e4 CW |
13093 | struct intel_cursor_error_state { |
13094 | u32 control; | |
13095 | u32 position; | |
13096 | u32 base; | |
13097 | u32 size; | |
52331309 | 13098 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13099 | |
13100 | struct intel_pipe_error_state { | |
ddf9c536 | 13101 | bool power_domain_on; |
c4a1d9e4 | 13102 | u32 source; |
f301b1e1 | 13103 | u32 stat; |
52331309 | 13104 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13105 | |
13106 | struct intel_plane_error_state { | |
13107 | u32 control; | |
13108 | u32 stride; | |
13109 | u32 size; | |
13110 | u32 pos; | |
13111 | u32 addr; | |
13112 | u32 surface; | |
13113 | u32 tile_offset; | |
52331309 | 13114 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13115 | |
13116 | struct intel_transcoder_error_state { | |
ddf9c536 | 13117 | bool power_domain_on; |
63b66e5b CW |
13118 | enum transcoder cpu_transcoder; |
13119 | ||
13120 | u32 conf; | |
13121 | ||
13122 | u32 htotal; | |
13123 | u32 hblank; | |
13124 | u32 hsync; | |
13125 | u32 vtotal; | |
13126 | u32 vblank; | |
13127 | u32 vsync; | |
13128 | } transcoder[4]; | |
c4a1d9e4 CW |
13129 | }; |
13130 | ||
13131 | struct intel_display_error_state * | |
13132 | intel_display_capture_error_state(struct drm_device *dev) | |
13133 | { | |
fbee40df | 13134 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13135 | struct intel_display_error_state *error; |
63b66e5b CW |
13136 | int transcoders[] = { |
13137 | TRANSCODER_A, | |
13138 | TRANSCODER_B, | |
13139 | TRANSCODER_C, | |
13140 | TRANSCODER_EDP, | |
13141 | }; | |
c4a1d9e4 CW |
13142 | int i; |
13143 | ||
63b66e5b CW |
13144 | if (INTEL_INFO(dev)->num_pipes == 0) |
13145 | return NULL; | |
13146 | ||
9d1cb914 | 13147 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13148 | if (error == NULL) |
13149 | return NULL; | |
13150 | ||
190be112 | 13151 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13152 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13153 | ||
52331309 | 13154 | for_each_pipe(i) { |
ddf9c536 | 13155 | error->pipe[i].power_domain_on = |
bfafe93a ID |
13156 | intel_display_power_enabled_unlocked(dev_priv, |
13157 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13158 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13159 | continue; |
13160 | ||
5efb3e28 VS |
13161 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13162 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13163 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13164 | |
13165 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13166 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13167 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13168 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13169 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13170 | } | |
ca291363 PZ |
13171 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13172 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13173 | if (INTEL_INFO(dev)->gen >= 4) { |
13174 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13175 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13176 | } | |
13177 | ||
c4a1d9e4 | 13178 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
13179 | |
13180 | if (!HAS_PCH_SPLIT(dev)) | |
13181 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
13182 | } |
13183 | ||
13184 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13185 | if (HAS_DDI(dev_priv->dev)) | |
13186 | error->num_transcoders++; /* Account for eDP. */ | |
13187 | ||
13188 | for (i = 0; i < error->num_transcoders; i++) { | |
13189 | enum transcoder cpu_transcoder = transcoders[i]; | |
13190 | ||
ddf9c536 | 13191 | error->transcoder[i].power_domain_on = |
bfafe93a | 13192 | intel_display_power_enabled_unlocked(dev_priv, |
38cc1daf | 13193 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13194 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13195 | continue; |
13196 | ||
63b66e5b CW |
13197 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13198 | ||
13199 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13200 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13201 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13202 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13203 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13204 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13205 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13206 | } |
13207 | ||
13208 | return error; | |
13209 | } | |
13210 | ||
edc3d884 MK |
13211 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13212 | ||
c4a1d9e4 | 13213 | void |
edc3d884 | 13214 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13215 | struct drm_device *dev, |
13216 | struct intel_display_error_state *error) | |
13217 | { | |
13218 | int i; | |
13219 | ||
63b66e5b CW |
13220 | if (!error) |
13221 | return; | |
13222 | ||
edc3d884 | 13223 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13224 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13225 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13226 | error->power_well_driver); |
52331309 | 13227 | for_each_pipe(i) { |
edc3d884 | 13228 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13229 | err_printf(m, " Power: %s\n", |
13230 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13231 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13232 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13233 | |
13234 | err_printf(m, "Plane [%d]:\n", i); | |
13235 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13236 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13237 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13238 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13239 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13240 | } |
4b71a570 | 13241 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13242 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13243 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13244 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13245 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13246 | } |
13247 | ||
edc3d884 MK |
13248 | err_printf(m, "Cursor [%d]:\n", i); |
13249 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13250 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13251 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13252 | } |
63b66e5b CW |
13253 | |
13254 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13255 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13256 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13257 | err_printf(m, " Power: %s\n", |
13258 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13259 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13260 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13261 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13262 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13263 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13264 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13265 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13266 | } | |
c4a1d9e4 | 13267 | } |