projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: enable Package C8+ by default
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
2377b741
JB		 72/* FDI */
73#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
d2acd215
DV		 75int
76intel_pch_rawclk(struct drm_device *dev)
77{
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83}
84
021357ac
CW		 85static inline u32 /* units of 100MHz */
86intel_fdi_link_freq(struct drm_device *dev)
87{
8b99e68c
CW		 88 if (IS_GEN5(dev)) {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 } else
92 return 27;
021357ac
CW		 93}
94
5d536e28 95static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 106};
107
5d536e28
DV		 108static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
119};
120
e4b36699 121static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 145};
146
147static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 158};
159
273e27ca 160
e4b36699 161static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
171 .p2_slow = 10,
172 .p2_fast = 10
044c7c41 173 },
e4b36699
KP		 174};
175
176static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
044c7c41 200 },
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
044c7c41 214 },
e4b36699
KP		 215};
216
f2b115e6 217static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 220 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
273e27ca 223 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 230};
231
f2b115e6 232static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 243};
244
273e27ca
EA		 245/* Ironlake / Sandybridge
246 *
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
249 */
b91ad0ec 250static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 261};
262
b91ad0ec 263static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 274};
275
276static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 287};
288
273e27ca 289/* LVDS 100mhz refclk limits. */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
0206e353 298 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
0206e353 311 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 314};
315
a0c4da24
JB		 316static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
75e53986 324 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 327};
328
329static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 340};
341
342static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 345 .n = { .min = 1, .max = 7 },
74a4dd2e 346 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 353};
354
1b894b59
CW		 355static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 int refclk)
2c07245f 357{
b91ad0ec 358 struct drm_device *dev = crtc->dev;
2c07245f 359 const intel_limit_t *limit;
b91ad0ec
ZW		 360
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 362 if (intel_is_dual_link_lvds(dev)) {
1b894b59 363 if (refclk == 100000)
b91ad0ec
ZW		 364 limit = &intel_limits_ironlake_dual_lvds_100m;
365 else
366 limit = &intel_limits_ironlake_dual_lvds;
367 } else {
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_single_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_single_lvds;
372 }
c6bb3538 373 } else
b91ad0ec 374 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 375
376 return limit;
377}
378
044c7c41
ML		 379static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
380{
381 struct drm_device *dev = crtc->dev;
044c7c41
ML		 382 const intel_limit_t *limit;
383
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 385 if (intel_is_dual_link_lvds(dev))
e4b36699 386 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 387 else
e4b36699 388 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 391 limit = &intel_limits_g4x_hdmi;
044c7c41 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 393 limit = &intel_limits_g4x_sdvo;
044c7c41 394 } else /* The option is for other outputs */
e4b36699 395 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 396
397 return limit;
398}
399
1b894b59 400static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 401{
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
404
bad720ff 405 if (HAS_PCH_SPLIT(dev))
1b894b59 406 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 407 else if (IS_G4X(dev)) {
044c7c41 408 limit = intel_g4x_limit(crtc);
f2b115e6 409 } else if (IS_PINEVIEW(dev)) {
2177832f 410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 411 limit = &intel_limits_pineview_lvds;
2177832f 412 else
f2b115e6 413 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
419 else
420 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 428 limit = &intel_limits_i8xx_lvds;
5d536e28 429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 430 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 431 else
432 limit = &intel_limits_i8xx_dac;
79e53945
JB		 433 }
434 return limit;
435}
436
f2b115e6
AJ		 437/* m1 is reserved as 0 in Pineview, n is a ring counter */
438static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 439{
2177832f
SL		 440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444}
445
7429e9d4
DV		 446static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447{
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449}
450
ac58c3f0 451static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 452{
7429e9d4 453 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457}
458
79e53945
JB		 459/**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
4ef69c7a 462bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 463{
4ef69c7a 464 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 465 struct intel_encoder *encoder;
466
6c2b7c12
DV		 467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
4ef69c7a
CW		 469 return true;
470
471 return false;
79e53945
JB		 472}
473
7c04d1d9 474#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 475/**
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
478 */
479
1b894b59
CW		 480static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
79e53945 483{
79e53945 484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 485 INTELPllInvalid("p1 out of range\n");
79e53945 486 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 487 INTELPllInvalid("p out of range\n");
79e53945 488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 489 INTELPllInvalid("m2 out of range\n");
79e53945 490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 491 INTELPllInvalid("m1 out of range\n");
f2b115e6 492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 493 INTELPllInvalid("m1 <= m2\n");
79e53945 494 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 495 INTELPllInvalid("m out of range\n");
79e53945 496 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 497 INTELPllInvalid("n out of range\n");
79e53945 498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 499 INTELPllInvalid("vco out of range\n");
79e53945
JB		 500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
502 */
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 504 INTELPllInvalid("dot out of range\n");
79e53945
JB		 505
506 return true;
507}
508
d4906093 509static bool
ee9300bb 510i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
79e53945
JB		 513{
514 struct drm_device *dev = crtc->dev;
79e53945 515 intel_clock_t clock;
79e53945
JB		 516 int err = target;
517
a210b028 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 519 /*
a210b028
DV		 520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
79e53945 523 */
1974cad0 524 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 525 clock.p2 = limit->p2.p2_fast;
526 else
527 clock.p2 = limit->p2.p2_slow;
528 } else {
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
531 else
532 clock.p2 = limit->p2.p2_fast;
533 }
534
0206e353 535 memset(best_clock, 0, sizeof(*best_clock));
79e53945 536
42158660
ZY		 537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
538 clock.m1++) {
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 541 if (clock.m2 >= clock.m1)
42158660
ZY		 542 break;
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 547 int this_err;
548
ac58c3f0
DV		 549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
551 &clock))
552 continue;
553 if (match_clock &&
554 clock.p != match_clock->p)
555 continue;
556
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
559 *best_clock = clock;
560 err = this_err;
561 }
562 }
563 }
564 }
565 }
566
567 return (err != target);
568}
569
570static bool
ee9300bb
DV		 571pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
79e53945
JB		 574{
575 struct drm_device *dev = crtc->dev;
79e53945 576 intel_clock_t clock;
79e53945
JB		 577 int err = target;
578
a210b028 579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 580 /*
a210b028
DV		 581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
79e53945 584 */
1974cad0 585 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 586 clock.p2 = limit->p2.p2_fast;
587 else
588 clock.p2 = limit->p2.p2_slow;
589 } else {
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
592 else
593 clock.p2 = limit->p2.p2_fast;
594 }
595
0206e353 596 memset(best_clock, 0, sizeof(*best_clock));
79e53945 597
42158660
ZY		 598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
599 clock.m1++) {
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 606 int this_err;
607
ac58c3f0 608 pineview_clock(refclk, &clock);
1b894b59
CW		 609 if (!intel_PLL_is_valid(dev, limit,
610 &clock))
79e53945 611 continue;
cec2f356
SP		 612 if (match_clock &&
613 clock.p != match_clock->p)
614 continue;
79e53945
JB		 615
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
618 *best_clock = clock;
619 err = this_err;
620 }
621 }
622 }
623 }
624 }
625
626 return (err != target);
627}
628
d4906093 629static bool
ee9300bb
DV		 630g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
d4906093
ML		 633{
634 struct drm_device *dev = crtc->dev;
d4906093
ML		 635 intel_clock_t clock;
636 int max_n;
637 bool found;
6ba770dc
AJ		 638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 640 found = false;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 643 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 644 clock.p2 = limit->p2.p2_fast;
645 else
646 clock.p2 = limit->p2.p2_slow;
647 } else {
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
650 else
651 clock.p2 = limit->p2.p2_fast;
652 }
653
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
f77f13e2 656 /* based on hardware requirement, prefer smaller n to precision */
d4906093 657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 658 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
665 int this_err;
666
ac58c3f0 667 i9xx_clock(refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
d4906093 670 continue;
1b894b59
CW		 671
672 this_err = abs(clock.dot - target);
d4906093
ML		 673 if (this_err < err_most) {
674 *best_clock = clock;
675 err_most = this_err;
676 max_n = clock.n;
677 found = true;
678 }
679 }
680 }
681 }
682 }
2c07245f
ZW		 683 return found;
684}
685
a0c4da24 686static bool
ee9300bb
DV		 687vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
a0c4da24
JB		 690{
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
692 u32 m, n, fastclk;
f3f08572 693 u32 updrate, minupdate, p;
a0c4da24
JB		 694 unsigned long bestppm, ppm, absppm;
695 int dotclk, flag;
696
af447bd3 697 flag = 0;
a0c4da24
JB		 698 dotclk = target * 1000;
699 bestppm = 1000000;
700 ppm = absppm = 0;
701 fastclk = dotclk / (2*100);
702 updrate = 0;
703 minupdate = 19200;
a0c4da24
JB		 704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
706
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
712 if (p2 > 10)
713 p2 = p2 - 1;
714 p = p1 * p2;
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
719 m = m1 * m2;
720 vco = updrate * m;
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
725 bestppm = 0;
726 flag = 1;
727 }
728 if (absppm < bestppm - 10) {
729 bestppm = absppm;
730 flag = 1;
731 }
732 if (flag) {
733 bestn = n;
734 bestm1 = m1;
735 bestm2 = m2;
736 bestp1 = p1;
737 bestp2 = p2;
738 flag = 0;
739 }
740 }
741 }
742 }
743 }
744 }
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
750
751 return true;
752}
a4fc5ed6 753
a5c961d1
PZ		 754enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756{
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
3b117c8f 760 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 761}
762
a928d536
PZ		 763static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772}
773
9d0498a2
JB		 774/**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 783{
9d0498a2 784 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 785 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 786
a928d536
PZ		 787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
300387c0
CW		 792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
9d0498a2 808 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
9d0498a2
JB		 812 DRM_DEBUG_KMS("vblank wait timed out\n");
813}
814
ab7ad7f6
KP		 815/*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
ab7ad7f6
KP		 824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
58e10eb9 830 *
9d0498a2 831 */
58e10eb9 832void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
ab7ad7f6
KP		 837
838 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 839 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 840
841 /* Wait for the Pipe State to go off */
58e10eb9
CW		 842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 } else {
837ba00f 846 u32 last_line, line_mask;
58e10eb9 847 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
837ba00f
PZ		 850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
ab7ad7f6
KP		 855 /* Wait for the display line to settle */
856 do {
837ba00f 857 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 858 mdelay(5);
837ba00f 859 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 }
79e53945
JB		 864}
865
b0ea7d37
DL		 866/*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875{
876 u32 bit;
877
c36346e3
DL		 878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
b0ea7d37
DL		 906 }
907
908 return I915_READ(SDEISR) & bit;
909}
910
b24e7179
JB		 911static const char *state_string(bool enabled)
912{
913 return enabled ? "on" : "off";
914}
915
916/* Only for pre-ILK configs */
55607e8a
DV		 917void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
b24e7179
JB		 919{
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930}
b24e7179 931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
b840d907
JB		 1072void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
b24e7179
JB		 1074{
1075 int reg;
1076 u32 val;
63d7bbe9 1077 bool cur_state;
702e7a56
PZ		 1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 pipe);
b24e7179 1080
8e636784
DV		 1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083 state = true;
1084
b97186f0
PZ		 1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1087 cur_state = false;
1088 } else {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1092 }
1093
63d7bbe9
JB		 1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1096 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1097}
1098
931872fc
CW		 1099static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
b24e7179
JB		 1101{
1102 int reg;
1103 u32 val;
931872fc 1104 bool cur_state;
b24e7179
JB		 1105
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
931872fc
CW		 1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1112}
1113
931872fc
CW		 1114#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
b24e7179
JB		 1117static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118 enum pipe pipe)
1119{
653e1026 1120 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1121 int reg, i;
1122 u32 val;
1123 int cur_pipe;
1124
653e1026
VS		 1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1131 plane_name(pipe));
19ec1358 1132 return;
28c05794 1133 }
19ec1358 1134
b24e7179 1135 /* Need to check both planes against the pipe */
08e2a7de 1136 for_each_pipe(i) {
b24e7179
JB		 1137 reg = DSPCNTR(i);
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1144 }
1145}
1146
19332d7a
JB		 1147static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148 enum pipe pipe)
1149{
20674eef 1150 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1151 int reg, i;
1152 u32 val;
1153
20674eef
VS		 1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1161 }
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1163 reg = SPRCTL(pipe);
19332d7a 1164 val = I915_READ(reg);
20674eef 1165 WARN((val & SPRITE_ENABLE),
06da8da2 1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
19332d7a 1170 val = I915_READ(reg);
20674eef 1171 WARN((val & DVS_ENABLE),
06da8da2 1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1173 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1174 }
1175}
1176
92f2584a
JB		 1177static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178{
1179 u32 val;
1180 bool enabled;
1181
9d82aa17
ED		 1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184 return;
1185 }
1186
92f2584a
JB		 1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191}
1192
ab9412ba
DV		 1193static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
92f2584a
JB		 1195{
1196 int reg;
1197 u32 val;
1198 bool enabled;
1199
ab9412ba 1200 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1203 WARN(enabled,
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205 pipe_name(pipe));
92f2584a
JB		 1206}
1207
4e634389
KP		 1208static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1210{
1211 if ((val & DP_PORT_EN) == 0)
1212 return false;
1213
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218 return false;
1219 } else {
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221 return false;
1222 }
1223 return true;
1224}
1225
1519b995
KP		 1226static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1228{
dc0fa718 1229 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1234 return false;
1235 } else {
dc0fa718 1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1237 return false;
1238 }
1239 return true;
1240}
1241
1242static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
1245 if ((val & LVDS_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250 return false;
1251 } else {
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1262 return false;
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265 return false;
1266 } else {
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268 return false;
1269 }
1270 return true;
1271}
1272
291906f1 1273static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1274 enum pipe pipe, int reg, u32 port_sel)
291906f1 1275{
47a05eca 1276 u32 val = I915_READ(reg);
4e634389 1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1279 reg, pipe_name(pipe));
de9a35ab 1280
75c5da27
DV		 1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
de9a35ab 1283 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1284}
1285
1286static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1288{
47a05eca 1289 u32 val = I915_READ(reg);
b70ad586 1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 reg, pipe_name(pipe));
de9a35ab 1293
dc0fa718 1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1295 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1296 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1297}
1298
1299static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301{
1302 int reg;
1303 u32 val;
291906f1 1304
f0575e92
KP		 1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1308
1309 reg = PCH_ADPA;
1310 val = I915_READ(reg);
b70ad586 1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1313 pipe_name(pipe));
291906f1
JB		 1314
1315 reg = PCH_LVDS;
1316 val = I915_READ(reg);
b70ad586 1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1319 pipe_name(pipe));
291906f1 1320
e2debe91
PZ		 1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1324}
1325
426115cf 1326static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1327{
426115cf
DV		 1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1332
426115cf 1333 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1334
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1340 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1341
426115cf
DV		 1342 I915_WRITE(reg, dpll);
1343 POSTING_READ(reg);
1344 udelay(150);
1345
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1351
1352 /* We do this three times for luck */
426115cf 1353 I915_WRITE(reg, dpll);
87442f73
DV		 1354 POSTING_READ(reg);
1355 udelay(150); /* wait for warmup */
426115cf 1356 I915_WRITE(reg, dpll);
87442f73
DV		 1357 POSTING_READ(reg);
1358 udelay(150); /* wait for warmup */
426115cf 1359 I915_WRITE(reg, dpll);
87442f73
DV		 1360 POSTING_READ(reg);
1361 udelay(150); /* wait for warmup */
1362}
1363
66e3d5c0 1364static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1365{
66e3d5c0
DV		 1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1370
66e3d5c0 1371 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1372
63d7bbe9 1373 /* No really, not for ILK+ */
87442f73 1374 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1375
1376 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1379
66e3d5c0
DV		 1380 I915_WRITE(reg, dpll);
1381
1382 /* Wait for the clocks to stabilize. */
1383 POSTING_READ(reg);
1384 udelay(150);
1385
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1389 } else {
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1392 *
1393 * So write it again.
1394 */
1395 I915_WRITE(reg, dpll);
1396 }
63d7bbe9
JB		 1397
1398 /* We do this three times for luck */
66e3d5c0 1399 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
66e3d5c0 1402 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
66e3d5c0 1405 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408}
1409
1410/**
50b44a44 1411 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1414 *
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1416 *
1417 * Note! This is for pre-ILK only.
1418 */
50b44a44 1419static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1420{
63d7bbe9
JB		 1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423 return;
1424
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1427
50b44a44
DV		 1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1430}
1431
89b667f8
JB		 1432void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1433{
1434 u32 port_mask;
1435
1436 if (!port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1438 else
1439 port_mask = DPLL_PORTC_READY_MASK;
1440
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1444}
1445
92f2584a 1446/**
e72f9fbf 1447 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1450 *
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1453 */
e2b78267 1454static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1455{
e2b78267
DV		 1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1458
48da64a8 1459 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1460 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1461 if (WARN_ON(pll == NULL))
48da64a8
CW		 1462 return;
1463
1464 if (WARN_ON(pll->refcount == 0))
1465 return;
ee7b9f93 1466
46edb027
DV		 1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
e2b78267 1469 crtc->base.base.id);
92f2584a 1470
cdbd2316
DV		 1471 if (pll->active++) {
1472 WARN_ON(!pll->on);
e9d6944e 1473 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1474 return;
1475 }
f4a091c7 1476 WARN_ON(pll->on);
ee7b9f93 1477
46edb027 1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1479 pll->enable(dev_priv, pll);
ee7b9f93 1480 pll->on = true;
92f2584a
JB		 1481}
1482
e2b78267 1483static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1484{
e2b78267
DV		 1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1487
92f2584a
JB		 1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1490 if (WARN_ON(pll == NULL))
ee7b9f93 1491 return;
92f2584a 1492
48da64a8
CW		 1493 if (WARN_ON(pll->refcount == 0))
1494 return;
7a419866 1495
46edb027
DV		 1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
e2b78267 1498 crtc->base.base.id);
7a419866 1499
48da64a8 1500 if (WARN_ON(pll->active == 0)) {
e9d6944e 1501 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1502 return;
1503 }
1504
e9d6944e 1505 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1506 WARN_ON(!pll->on);
cdbd2316 1507 if (--pll->active)
7a419866 1508 return;
ee7b9f93 1509
46edb027 1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1511 pll->disable(dev_priv, pll);
ee7b9f93 1512 pll->on = false;
92f2584a
JB		 1513}
1514
b8a4f404
PZ		 1515static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1516 enum pipe pipe)
040484af 1517{
23670b32 1518 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1521 uint32_t reg, val, pipeconf_val;
040484af
JB		 1522
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1525
1526 /* Make sure PCH DPLL is enabled */
e72f9fbf 1527 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1528 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1529
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1533
23670b32
DV		 1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
59c859d6 1541 }
23670b32 1542
ab9412ba 1543 reg = PCH_TRANSCONF(pipe);
040484af 1544 val = I915_READ(reg);
5f7f726d 1545 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1546
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1548 /*
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1551 */
dfd07d72
DV		 1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1554 }
5f7f726d
PZ		 1555
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1561 else
1562 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1563 else
1564 val |= TRANS_PROGRESSIVE;
1565
040484af
JB		 1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1569}
1570
8fb033d7 1571static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1572 enum transcoder cpu_transcoder)
040484af 1573{
8fb033d7 1574 u32 val, pipeconf_val;
8fb033d7
PZ		 1575
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1578
8fb033d7 1579 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1582
223a6fdf
PZ		 1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1587
25f3ef11 1588 val = TRANS_ENABLE;
937bb610 1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1590
9a76b1c6
PZ		 1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
a35f2679 1593 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1594 else
1595 val |= TRANS_PROGRESSIVE;
1596
ab9412ba
DV		 1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1599 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1600}
1601
b8a4f404
PZ		 1602static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1603 enum pipe pipe)
040484af 1604{
23670b32
DV		 1605 struct drm_device *dev = dev_priv->dev;
1606 uint32_t reg, val;
040484af
JB		 1607
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1611
291906f1
JB		 1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1614
ab9412ba 1615 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1622
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1629 }
040484af
JB		 1630}
1631
ab4d966c 1632static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1633{
8fb033d7
PZ		 1634 u32 val;
1635
ab9412ba 1636 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1637 val &= ~TRANS_ENABLE;
ab9412ba 1638 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1639 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1641 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1642
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1646 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1647}
1648
b24e7179 1649/**
309cfea8 1650 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
040484af 1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1654 *
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1657 *
1658 * @pipe should be %PIPE_A or %PIPE_B.
1659 *
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1661 * returning.
1662 */
040484af
JB		 1663static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1664 bool pch_port)
b24e7179 1665{
702e7a56
PZ		 1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1667 pipe);
1a240d4d 1668 enum pipe pch_transcoder;
b24e7179
JB		 1669 int reg;
1670 u32 val;
1671
58c6eaa2
DV		 1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1674
681e5811 1675 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1676 pch_transcoder = TRANSCODER_A;
1677 else
1678 pch_transcoder = pipe;
1679
b24e7179
JB		 1680 /*
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1683 * need the check.
1684 */
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
1686 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1687 else {
1688 if (pch_port) {
1689 /* if driving the PCH, we need FDI enabled */
cc391bbb 1690 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1691 assert_fdi_tx_pll_enabled(dev_priv,
1692 (enum pipe) cpu_transcoder);
040484af
JB		 1693 }
1694 /* FIXME: assert CPU port conditions for SNB+ */
1695 }
b24e7179 1696
702e7a56 1697 reg = PIPECONF(cpu_transcoder);
b24e7179 1698 val = I915_READ(reg);
00d70b15
CW		 1699 if (val & PIPECONF_ENABLE)
1700 return;
1701
1702 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1703 intel_wait_for_vblank(dev_priv->dev, pipe);
1704}
1705
1706/**
309cfea8 1707 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1708 * @dev_priv: i915 private structure
1709 * @pipe: pipe to disable
1710 *
1711 * Disable @pipe, making sure that various hardware specific requirements
1712 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1713 *
1714 * @pipe should be %PIPE_A or %PIPE_B.
1715 *
1716 * Will wait until the pipe has shut down before returning.
1717 */
1718static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1719 enum pipe pipe)
1720{
702e7a56
PZ		 1721 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1722 pipe);
b24e7179
JB		 1723 int reg;
1724 u32 val;
1725
1726 /*
1727 * Make sure planes won't keep trying to pump pixels to us,
1728 * or we might hang the display.
1729 */
1730 assert_planes_disabled(dev_priv, pipe);
19332d7a 1731 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1732
1733 /* Don't disable pipe A or pipe A PLLs if needed */
1734 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1735 return;
1736
702e7a56 1737 reg = PIPECONF(cpu_transcoder);
b24e7179 1738 val = I915_READ(reg);
00d70b15
CW		 1739 if ((val & PIPECONF_ENABLE) == 0)
1740 return;
1741
1742 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1743 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1744}
1745
d74362c9
KP		 1746/*
1747 * Plane regs are double buffered, going from enabled->disabled needs a
1748 * trigger in order to latch. The display address reg provides this.
1749 */
6f1d69b0 1750void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1751 enum plane plane)
1752{
14f86147
DL		 1753 if (dev_priv->info->gen >= 4)
1754 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1755 else
1756 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1757}
1758
b24e7179
JB		 1759/**
1760 * intel_enable_plane - enable a display plane on a given pipe
1761 * @dev_priv: i915 private structure
1762 * @plane: plane to enable
1763 * @pipe: pipe being fed
1764 *
1765 * Enable @plane on @pipe, making sure that @pipe is running first.
1766 */
1767static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768 enum plane plane, enum pipe pipe)
1769{
1770 int reg;
1771 u32 val;
1772
1773 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774 assert_pipe_enabled(dev_priv, pipe);
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if (val & DISPLAY_PLANE_ENABLE)
1779 return;
1780
1781 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1782 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
b24e7179
JB		 1786/**
1787 * intel_disable_plane - disable a display plane
1788 * @dev_priv: i915 private structure
1789 * @plane: plane to disable
1790 * @pipe: pipe consuming the data
1791 *
1792 * Disable @plane; should be an independent operation.
1793 */
1794static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795 enum plane plane, enum pipe pipe)
1796{
1797 int reg;
1798 u32 val;
1799
1800 reg = DSPCNTR(plane);
1801 val = I915_READ(reg);
00d70b15
CW		 1802 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1803 return;
1804
1805 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1806 intel_flush_display_plane(dev_priv, plane);
1807 intel_wait_for_vblank(dev_priv->dev, pipe);
1808}
1809
693db184
CW		 1810static bool need_vtd_wa(struct drm_device *dev)
1811{
1812#ifdef CONFIG_INTEL_IOMMU
1813 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1814 return true;
1815#endif
1816 return false;
1817}
1818
127bd2ac 1819int
48b956c5 1820intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1821 struct drm_i915_gem_object *obj,
919926ae 1822 struct intel_ring_buffer *pipelined)
6b95a207 1823{
ce453d81 1824 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1825 u32 alignment;
1826 int ret;
1827
05394f39 1828 switch (obj->tiling_mode) {
6b95a207 1829 case I915_TILING_NONE:
534843da
CW		 1830 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831 alignment = 128 * 1024;
a6c45cf0 1832 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1833 alignment = 4 * 1024;
1834 else
1835 alignment = 64 * 1024;
6b95a207
KH		 1836 break;
1837 case I915_TILING_X:
1838 /* pin() will align the object as required by fence */
1839 alignment = 0;
1840 break;
1841 case I915_TILING_Y:
8bb6e959
DV		 1842 /* Despite that we check this in framebuffer_init userspace can
1843 * screw us over and change the tiling after the fact. Only
1844 * pinned buffers can't change their tiling. */
1845 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1846 return -EINVAL;
1847 default:
1848 BUG();
1849 }
1850
693db184
CW		 1851 /* Note that the w/a also requires 64 PTE of padding following the
1852 * bo. We currently fill all unused PTE with the shadow page and so
1853 * we should always have valid PTE following the scanout preventing
1854 * the VT-d warning.
1855 */
1856 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857 alignment = 256 * 1024;
1858
ce453d81 1859 dev_priv->mm.interruptible = false;
2da3b9b9 1860 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1861 if (ret)
ce453d81 1862 goto err_interruptible;
6b95a207
KH		 1863
1864 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865 * fence, whereas 965+ only requires a fence if using
1866 * framebuffer compression. For simplicity, we always install
1867 * a fence as the cost is not that onerous.
1868 */
06d98131 1869 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1870 if (ret)
1871 goto err_unpin;
1690e1eb 1872
9a5a53b3 1873 i915_gem_object_pin_fence(obj);
6b95a207 1874
ce453d81 1875 dev_priv->mm.interruptible = true;
6b95a207 1876 return 0;
48b956c5
CW		 1877
1878err_unpin:
cc98b413 1879 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1880err_interruptible:
1881 dev_priv->mm.interruptible = true;
48b956c5 1882 return ret;
6b95a207
KH		 1883}
1884
1690e1eb
CW		 1885void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1886{
1887 i915_gem_object_unpin_fence(obj);
cc98b413 1888 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1889}
1890
c2c75131
DV		 1891/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892 * is assumed to be a power-of-two. */
bc752862
CW		 1893unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894 unsigned int tiling_mode,
1895 unsigned int cpp,
1896 unsigned int pitch)
c2c75131 1897{
bc752862
CW		 1898 if (tiling_mode != I915_TILING_NONE) {
1899 unsigned int tile_rows, tiles;
c2c75131 1900
bc752862
CW		 1901 tile_rows = *y / 8;
1902 *y %= 8;
c2c75131 1903
bc752862
CW		 1904 tiles = *x / (512/cpp);
1905 *x %= 512/cpp;
1906
1907 return tile_rows * pitch * 8 + tiles * 4096;
1908 } else {
1909 unsigned int offset;
1910
1911 offset = *y * pitch + *x * cpp;
1912 *y = 0;
1913 *x = (offset & 4095) / cpp;
1914 return offset & -4096;
1915 }
c2c75131
DV		 1916}
1917
17638cd6
JB		 1918static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1919 int x, int y)
81255565
JB		 1920{
1921 struct drm_device *dev = crtc->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924 struct intel_framebuffer *intel_fb;
05394f39 1925 struct drm_i915_gem_object *obj;
81255565 1926 int plane = intel_crtc->plane;
e506a0c6 1927 unsigned long linear_offset;
81255565 1928 u32 dspcntr;
5eddb70b 1929 u32 reg;
81255565
JB		 1930
1931 switch (plane) {
1932 case 0:
1933 case 1:
1934 break;
1935 default:
84f44ce7 1936 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1937 return -EINVAL;
1938 }
1939
1940 intel_fb = to_intel_framebuffer(fb);
1941 obj = intel_fb->obj;
81255565 1942
5eddb70b
CW		 1943 reg = DSPCNTR(plane);
1944 dspcntr = I915_READ(reg);
81255565
JB		 1945 /* Mask out pixel format bits in case we change it */
1946 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1947 switch (fb->pixel_format) {
1948 case DRM_FORMAT_C8:
81255565
JB		 1949 dspcntr |= DISPPLANE_8BPP;
1950 break;
57779d06
VS		 1951 case DRM_FORMAT_XRGB1555:
1952 case DRM_FORMAT_ARGB1555:
1953 dspcntr |= DISPPLANE_BGRX555;
81255565 1954 break;
57779d06
VS		 1955 case DRM_FORMAT_RGB565:
1956 dspcntr |= DISPPLANE_BGRX565;
1957 break;
1958 case DRM_FORMAT_XRGB8888:
1959 case DRM_FORMAT_ARGB8888:
1960 dspcntr |= DISPPLANE_BGRX888;
1961 break;
1962 case DRM_FORMAT_XBGR8888:
1963 case DRM_FORMAT_ABGR8888:
1964 dspcntr |= DISPPLANE_RGBX888;
1965 break;
1966 case DRM_FORMAT_XRGB2101010:
1967 case DRM_FORMAT_ARGB2101010:
1968 dspcntr |= DISPPLANE_BGRX101010;
1969 break;
1970 case DRM_FORMAT_XBGR2101010:
1971 case DRM_FORMAT_ABGR2101010:
1972 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1973 break;
1974 default:
baba133a 1975 BUG();
81255565 1976 }
57779d06 1977
a6c45cf0 1978 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1979 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1980 dspcntr |= DISPPLANE_TILED;
1981 else
1982 dspcntr &= ~DISPPLANE_TILED;
1983 }
1984
de1aa629
VS		 1985 if (IS_G4X(dev))
1986 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1987
5eddb70b 1988 I915_WRITE(reg, dspcntr);
81255565 1989
e506a0c6 1990 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1991
c2c75131
DV		 1992 if (INTEL_INFO(dev)->gen >= 4) {
1993 intel_crtc->dspaddr_offset =
bc752862
CW		 1994 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995 fb->bits_per_pixel / 8,
1996 fb->pitches[0]);
c2c75131
DV		 1997 linear_offset -= intel_crtc->dspaddr_offset;
1998 } else {
e506a0c6 1999 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2000 }
e506a0c6 2001
f343c5f6
BW		 2002 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2004 fb->pitches[0]);
01f2c773 2005 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2006 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2007 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2008 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2009 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2010 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2011 } else
f343c5f6 2012 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2013 POSTING_READ(reg);
81255565 2014
17638cd6
JB		 2015 return 0;
2016}
2017
2018static int ironlake_update_plane(struct drm_crtc *crtc,
2019 struct drm_framebuffer *fb, int x, int y)
2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
17638cd6
JB		 2028 u32 dspcntr;
2029 u32 reg;
2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
27f8227b 2034 case 2:
17638cd6
JB		 2035 break;
2036 default:
84f44ce7 2037 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2043
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2048 switch (fb->pixel_format) {
2049 case DRM_FORMAT_C8:
17638cd6
JB		 2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
57779d06
VS		 2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2058 break;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2062 break;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2066 break;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2070 break;
2071 default:
baba133a 2072 BUG();
17638cd6
JB		 2073 }
2074
2075 if (obj->tiling_mode != I915_TILING_NONE)
2076 dspcntr |= DISPPLANE_TILED;
2077 else
2078 dspcntr &= ~DISPPLANE_TILED;
2079
2080 /* must disable */
2081 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2082
2083 I915_WRITE(reg, dspcntr);
2084
e506a0c6 2085 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2086 intel_crtc->dspaddr_offset =
bc752862
CW		 2087 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2088 fb->bits_per_pixel / 8,
2089 fb->pitches[0]);
c2c75131 2090 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2091
f343c5f6
BW		 2092 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2093 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2094 fb->pitches[0]);
01f2c773 2095 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2096 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2097 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2098 if (IS_HASWELL(dev)) {
2099 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2100 } else {
2101 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2102 I915_WRITE(DSPLINOFF(plane), linear_offset);
2103 }
17638cd6
JB		 2104 POSTING_READ(reg);
2105
2106 return 0;
2107}
2108
2109/* Assume fb object is pinned & idle & fenced and just update base pointers */
2110static int
2111intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2113{
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2116
6b8e6ed0
CW		 2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
3dec0095 2119 intel_increase_pllclock(crtc);
81255565 2120
6b8e6ed0 2121 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2122}
2123
96a02917
VS		 2124void intel_display_handle_reset(struct drm_device *dev)
2125{
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 struct drm_crtc *crtc;
2128
2129 /*
2130 * Flips in the rings have been nuked by the reset,
2131 * so complete all pending flips so that user space
2132 * will get its events and not get stuck.
2133 *
2134 * Also update the base address of all primary
2135 * planes to the the last fb to make sure we're
2136 * showing the correct fb after a reset.
2137 *
2138 * Need to make two loops over the crtcs so that we
2139 * don't try to grab a crtc mutex before the
2140 * pending_flip_queue really got woken up.
2141 */
2142
2143 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145 enum plane plane = intel_crtc->plane;
2146
2147 intel_prepare_page_flip(dev, plane);
2148 intel_finish_page_flip_plane(dev, plane);
2149 }
2150
2151 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2153
2154 mutex_lock(&crtc->mutex);
2155 if (intel_crtc->active)
2156 dev_priv->display.update_plane(crtc, crtc->fb,
2157 crtc->x, crtc->y);
2158 mutex_unlock(&crtc->mutex);
2159 }
2160}
2161
14667a4b
CW		 2162static int
2163intel_finish_fb(struct drm_framebuffer *old_fb)
2164{
2165 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2166 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2167 bool was_interruptible = dev_priv->mm.interruptible;
2168 int ret;
2169
14667a4b
CW		 2170 /* Big Hammer, we also need to ensure that any pending
2171 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2172 * current scanout is retired before unpinning the old
2173 * framebuffer.
2174 *
2175 * This should only fail upon a hung GPU, in which case we
2176 * can safely continue.
2177 */
2178 dev_priv->mm.interruptible = false;
2179 ret = i915_gem_object_finish_gpu(obj);
2180 dev_priv->mm.interruptible = was_interruptible;
2181
2182 return ret;
2183}
2184
198598d0
VS		 2185static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2186{
2187 struct drm_device *dev = crtc->dev;
2188 struct drm_i915_master_private *master_priv;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190
2191 if (!dev->primary->master)
2192 return;
2193
2194 master_priv = dev->primary->master->driver_priv;
2195 if (!master_priv->sarea_priv)
2196 return;
2197
2198 switch (intel_crtc->pipe) {
2199 case 0:
2200 master_priv->sarea_priv->pipeA_x = x;
2201 master_priv->sarea_priv->pipeA_y = y;
2202 break;
2203 case 1:
2204 master_priv->sarea_priv->pipeB_x = x;
2205 master_priv->sarea_priv->pipeB_y = y;
2206 break;
2207 default:
2208 break;
2209 }
2210}
2211
5c3b82e2 2212static int
3c4fdcfb 2213intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2214 struct drm_framebuffer *fb)
79e53945
JB		 2215{
2216 struct drm_device *dev = crtc->dev;
6b8e6ed0 2217 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2219 struct drm_framebuffer *old_fb;
5c3b82e2 2220 int ret;
79e53945
JB		 2221
2222 /* no fb bound */
94352cf9 2223 if (!fb) {
a5071c2f 2224 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2225 return 0;
2226 }
2227
7eb552ae 2228 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2229 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2230 plane_name(intel_crtc->plane),
2231 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2232 return -EINVAL;
79e53945
JB		 2233 }
2234
5c3b82e2 2235 mutex_lock(&dev->struct_mutex);
265db958 2236 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2237 to_intel_framebuffer(fb)->obj,
919926ae 2238 NULL);
5c3b82e2
CW		 2239 if (ret != 0) {
2240 mutex_unlock(&dev->struct_mutex);
a5071c2f 2241 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2242 return ret;
2243 }
79e53945 2244
4d6a3e63
JB		 2245 /* Update pipe size and adjust fitter if needed */
2246 if (i915_fastboot) {
2247 I915_WRITE(PIPESRC(intel_crtc->pipe),
2248 ((crtc->mode.hdisplay - 1) << 16) |
2249 (crtc->mode.vdisplay - 1));
2250 if (!intel_crtc->config.pch_pfit.size &&
2251 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2252 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2253 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2254 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2255 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2256 }
2257 }
2258
94352cf9 2259 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2260 if (ret) {
94352cf9 2261 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2262 mutex_unlock(&dev->struct_mutex);
a5071c2f 2263 DRM_ERROR("failed to update base address\n");
4e6cfefc 2264 return ret;
79e53945 2265 }
3c4fdcfb 2266
94352cf9
DV		 2267 old_fb = crtc->fb;
2268 crtc->fb = fb;
6c4c86f5
DV		 2269 crtc->x = x;
2270 crtc->y = y;
94352cf9 2271
b7f1de28 2272 if (old_fb) {
d7697eea
DV		 2273 if (intel_crtc->active && old_fb != fb)
2274 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2275 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2276 }
652c393a 2277
6b8e6ed0 2278 intel_update_fbc(dev);
4906557e 2279 intel_edp_psr_update(dev);
5c3b82e2 2280 mutex_unlock(&dev->struct_mutex);
79e53945 2281
198598d0 2282 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2283
2284 return 0;
79e53945
JB		 2285}
2286
5e84e1a4
ZW		 2287static void intel_fdi_normal_train(struct drm_crtc *crtc)
2288{
2289 struct drm_device *dev = crtc->dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
2293 u32 reg, temp;
2294
2295 /* enable normal train */
2296 reg = FDI_TX_CTL(pipe);
2297 temp = I915_READ(reg);
61e499bf 2298 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2299 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2300 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2301 } else {
2302 temp &= ~FDI_LINK_TRAIN_NONE;
2303 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2304 }
5e84e1a4
ZW		 2305 I915_WRITE(reg, temp);
2306
2307 reg = FDI_RX_CTL(pipe);
2308 temp = I915_READ(reg);
2309 if (HAS_PCH_CPT(dev)) {
2310 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2311 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2312 } else {
2313 temp &= ~FDI_LINK_TRAIN_NONE;
2314 temp |= FDI_LINK_TRAIN_NONE;
2315 }
2316 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2317
2318 /* wait one idle pattern time */
2319 POSTING_READ(reg);
2320 udelay(1000);
357555c0
JB		 2321
2322 /* IVB wants error correction enabled */
2323 if (IS_IVYBRIDGE(dev))
2324 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2325 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2326}
2327
1e833f40
DV		 2328static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2329{
2330 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2331}
2332
01a415fd
DV		 2333static void ivb_modeset_global_resources(struct drm_device *dev)
2334{
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *pipe_B_crtc =
2337 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2338 struct intel_crtc *pipe_C_crtc =
2339 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2340 uint32_t temp;
2341
1e833f40
DV		 2342 /*
2343 * When everything is off disable fdi C so that we could enable fdi B
2344 * with all lanes. Note that we don't care about enabled pipes without
2345 * an enabled pch encoder.
2346 */
2347 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2348 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2349 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2350 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2351
2352 temp = I915_READ(SOUTH_CHICKEN1);
2353 temp &= ~FDI_BC_BIFURCATION_SELECT;
2354 DRM_DEBUG_KMS("disabling fdi C rx\n");
2355 I915_WRITE(SOUTH_CHICKEN1, temp);
2356 }
2357}
2358
8db9d77b
ZW		 2359/* The FDI link training functions for ILK/Ibexpeak. */
2360static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2361{
2362 struct drm_device *dev = crtc->dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365 int pipe = intel_crtc->pipe;
0fc932b8 2366 int plane = intel_crtc->plane;
5eddb70b 2367 u32 reg, temp, tries;
8db9d77b 2368
0fc932b8
JB		 2369 /* FDI needs bits from pipe & plane first */
2370 assert_pipe_enabled(dev_priv, pipe);
2371 assert_plane_enabled(dev_priv, plane);
2372
e1a44743
AJ		 2373 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2374 for train result */
5eddb70b
CW		 2375 reg = FDI_RX_IMR(pipe);
2376 temp = I915_READ(reg);
e1a44743
AJ		 2377 temp &= ~FDI_RX_SYMBOL_LOCK;
2378 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2379 I915_WRITE(reg, temp);
2380 I915_READ(reg);
e1a44743
AJ		 2381 udelay(150);
2382
8db9d77b 2383 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
627eb5a3
DV		 2386 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2387 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2390 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2391
5eddb70b
CW		 2392 reg = FDI_RX_CTL(pipe);
2393 temp = I915_READ(reg);
8db9d77b
ZW		 2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2396 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2397
2398 POSTING_READ(reg);
8db9d77b
ZW		 2399 udelay(150);
2400
5b2adf89 2401 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2402 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2403 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2404 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2405
5eddb70b 2406 reg = FDI_RX_IIR(pipe);
e1a44743 2407 for (tries = 0; tries < 5; tries++) {
5eddb70b 2408 temp = I915_READ(reg);
8db9d77b
ZW		 2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411 if ((temp & FDI_RX_BIT_LOCK)) {
2412 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2413 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2414 break;
2415 }
8db9d77b 2416 }
e1a44743 2417 if (tries == 5)
5eddb70b 2418 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2419
2420 /* Train 2 */
5eddb70b
CW		 2421 reg = FDI_TX_CTL(pipe);
2422 temp = I915_READ(reg);
8db9d77b
ZW		 2423 temp &= ~FDI_LINK_TRAIN_NONE;
2424 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2425 I915_WRITE(reg, temp);
8db9d77b 2426
5eddb70b
CW		 2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
8db9d77b
ZW		 2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2431 I915_WRITE(reg, temp);
8db9d77b 2432
5eddb70b
CW		 2433 POSTING_READ(reg);
2434 udelay(150);
8db9d77b 2435
5eddb70b 2436 reg = FDI_RX_IIR(pipe);
e1a44743 2437 for (tries = 0; tries < 5; tries++) {
5eddb70b 2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2440
2441 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2442 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2443 DRM_DEBUG_KMS("FDI train 2 done.\n");
2444 break;
2445 }
8db9d77b 2446 }
e1a44743 2447 if (tries == 5)
5eddb70b 2448 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2449
2450 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2451
8db9d77b
ZW		 2452}
2453
0206e353 2454static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2455 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2456 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2457 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2458 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2459};
2460
2461/* The FDI link training functions for SNB/Cougarpoint. */
2462static void gen6_fdi_link_train(struct drm_crtc *crtc)
2463{
2464 struct drm_device *dev = crtc->dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2467 int pipe = intel_crtc->pipe;
fa37d39e 2468 u32 reg, temp, i, retry;
8db9d77b 2469
e1a44743
AJ		 2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
5eddb70b
CW		 2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
e1a44743
AJ		 2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2476 I915_WRITE(reg, temp);
2477
2478 POSTING_READ(reg);
e1a44743
AJ		 2479 udelay(150);
2480
8db9d77b 2481 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
627eb5a3
DV		 2484 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2485 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2486 temp &= ~FDI_LINK_TRAIN_NONE;
2487 temp |= FDI_LINK_TRAIN_PATTERN_1;
2488 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2489 /* SNB-B */
2490 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2491 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2492
d74cf324
DV		 2493 I915_WRITE(FDI_RX_MISC(pipe),
2494 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2495
5eddb70b
CW		 2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
8db9d77b
ZW		 2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501 } else {
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 }
5eddb70b
CW		 2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
8db9d77b
ZW		 2508 udelay(150);
2509
0206e353 2510 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2511 reg = FDI_TX_CTL(pipe);
2512 temp = I915_READ(reg);
8db9d77b
ZW		 2513 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2515 I915_WRITE(reg, temp);
2516
2517 POSTING_READ(reg);
8db9d77b
ZW		 2518 udelay(500);
2519
fa37d39e
SP		 2520 for (retry = 0; retry < 5; retry++) {
2521 reg = FDI_RX_IIR(pipe);
2522 temp = I915_READ(reg);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524 if (temp & FDI_RX_BIT_LOCK) {
2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
2527 break;
2528 }
2529 udelay(50);
8db9d77b 2530 }
fa37d39e
SP		 2531 if (retry < 5)
2532 break;
8db9d77b
ZW		 2533 }
2534 if (i == 4)
5eddb70b 2535 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2536
2537 /* Train 2 */
5eddb70b
CW		 2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
8db9d77b
ZW		 2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2542 if (IS_GEN6(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2544 /* SNB-B */
2545 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2546 }
5eddb70b 2547 I915_WRITE(reg, temp);
8db9d77b 2548
5eddb70b
CW		 2549 reg = FDI_RX_CTL(pipe);
2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 if (HAS_PCH_CPT(dev)) {
2552 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2554 } else {
2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
2557 }
5eddb70b
CW		 2558 I915_WRITE(reg, temp);
2559
2560 POSTING_READ(reg);
8db9d77b
ZW		 2561 udelay(150);
2562
0206e353 2563 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
8db9d77b
ZW		 2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
8db9d77b
ZW		 2571 udelay(500);
2572
fa37d39e
SP		 2573 for (retry = 0; retry < 5; retry++) {
2574 reg = FDI_RX_IIR(pipe);
2575 temp = I915_READ(reg);
2576 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2577 if (temp & FDI_RX_SYMBOL_LOCK) {
2578 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2579 DRM_DEBUG_KMS("FDI train 2 done.\n");
2580 break;
2581 }
2582 udelay(50);
8db9d77b 2583 }
fa37d39e
SP		 2584 if (retry < 5)
2585 break;
8db9d77b
ZW		 2586 }
2587 if (i == 4)
5eddb70b 2588 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2589
2590 DRM_DEBUG_KMS("FDI train done.\n");
2591}
2592
357555c0
JB		 2593/* Manual link training for Ivy Bridge A0 parts */
2594static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2595{
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
139ccd3f 2600 u32 reg, temp, i, j;
357555c0
JB		 2601
2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
2611 udelay(150);
2612
01a415fd
DV		 2613 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2614 I915_READ(FDI_RX_IIR(pipe)));
2615
139ccd3f
JB		 2616 /* Try each vswing and preemphasis setting twice before moving on */
2617 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2618 /* disable first in case we need to retry */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2622 temp &= ~FDI_TX_ENABLE;
2623 I915_WRITE(reg, temp);
357555c0 2624
139ccd3f
JB		 2625 reg = FDI_RX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~FDI_LINK_TRAIN_AUTO;
2628 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2629 temp &= ~FDI_RX_ENABLE;
2630 I915_WRITE(reg, temp);
357555c0 2631
139ccd3f 2632 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
139ccd3f
JB		 2635 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2636 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2637 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2639 temp |= snb_b_fdi_train_param[j/2];
2640 temp |= FDI_COMPOSITE_SYNC;
2641 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2642
139ccd3f
JB		 2643 I915_WRITE(FDI_RX_MISC(pipe),
2644 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2645
139ccd3f 2646 reg = FDI_RX_CTL(pipe);
357555c0 2647 temp = I915_READ(reg);
139ccd3f
JB		 2648 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2649 temp |= FDI_COMPOSITE_SYNC;
2650 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2651
139ccd3f
JB		 2652 POSTING_READ(reg);
2653 udelay(1); /* should be 0.5us */
357555c0 2654
139ccd3f
JB		 2655 for (i = 0; i < 4; i++) {
2656 reg = FDI_RX_IIR(pipe);
2657 temp = I915_READ(reg);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2659
139ccd3f
JB		 2660 if (temp & FDI_RX_BIT_LOCK ||
2661 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2662 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2663 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2664 i);
2665 break;
2666 }
2667 udelay(1); /* should be 0.5us */
2668 }
2669 if (i == 4) {
2670 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2671 continue;
2672 }
357555c0 2673
139ccd3f 2674 /* Train 2 */
357555c0
JB		 2675 reg = FDI_TX_CTL(pipe);
2676 temp = I915_READ(reg);
139ccd3f
JB		 2677 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2678 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2679 I915_WRITE(reg, temp);
2680
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
139ccd3f 2688 udelay(2); /* should be 1.5us */
357555c0 2689
139ccd3f
JB		 2690 for (i = 0; i < 4; i++) {
2691 reg = FDI_RX_IIR(pipe);
2692 temp = I915_READ(reg);
2693 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2694
139ccd3f
JB		 2695 if (temp & FDI_RX_SYMBOL_LOCK ||
2696 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2697 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2698 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2699 i);
2700 goto train_done;
2701 }
2702 udelay(2); /* should be 1.5us */
357555c0 2703 }
139ccd3f
JB		 2704 if (i == 4)
2705 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2706 }
357555c0 2707
139ccd3f 2708train_done:
357555c0
JB		 2709 DRM_DEBUG_KMS("FDI train done.\n");
2710}
2711
88cefb6c 2712static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2713{
88cefb6c 2714 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2715 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2716 int pipe = intel_crtc->pipe;
5eddb70b 2717 u32 reg, temp;
79e53945 2718
c64e311e 2719
c98e9dcf 2720 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2721 reg = FDI_RX_CTL(pipe);
2722 temp = I915_READ(reg);
627eb5a3
DV		 2723 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2724 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2725 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2726 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
c98e9dcf
JB		 2729 udelay(200);
2730
2731 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp | FDI_PCDCLK);
2734
2735 POSTING_READ(reg);
c98e9dcf
JB		 2736 udelay(200);
2737
20749730
PZ		 2738 /* Enable CPU FDI TX PLL, always on for Ironlake */
2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2742 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2743
20749730
PZ		 2744 POSTING_READ(reg);
2745 udelay(100);
6be4a607 2746 }
0e23b99d
JB		 2747}
2748
88cefb6c
DV		 2749static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2750{
2751 struct drm_device *dev = intel_crtc->base.dev;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 int pipe = intel_crtc->pipe;
2754 u32 reg, temp;
2755
2756 /* Switch from PCDclk to Rawclk */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2760
2761 /* Disable CPU FDI TX PLL */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2765
2766 POSTING_READ(reg);
2767 udelay(100);
2768
2769 reg = FDI_RX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2772
2773 /* Wait for the clocks to turn off. */
2774 POSTING_READ(reg);
2775 udelay(100);
2776}
2777
0fc932b8
JB		 2778static void ironlake_fdi_disable(struct drm_crtc *crtc)
2779{
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783 int pipe = intel_crtc->pipe;
2784 u32 reg, temp;
2785
2786 /* disable CPU FDI tx and PCH FDI rx */
2787 reg = FDI_TX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2790 POSTING_READ(reg);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~(0x7 << 16);
dfd07d72 2795 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2796 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2797
2798 POSTING_READ(reg);
2799 udelay(100);
2800
2801 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2802 if (HAS_PCH_IBX(dev)) {
2803 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2804 }
0fc932b8
JB		 2805
2806 /* still set train pattern 1 */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_NONE;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1;
2811 I915_WRITE(reg, temp);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 if (HAS_PCH_CPT(dev)) {
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2818 } else {
2819 temp &= ~FDI_LINK_TRAIN_NONE;
2820 temp |= FDI_LINK_TRAIN_PATTERN_1;
2821 }
2822 /* BPC in FDI rx is consistent with that in PIPECONF */
2823 temp &= ~(0x07 << 16);
dfd07d72 2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2825 I915_WRITE(reg, temp);
2826
2827 POSTING_READ(reg);
2828 udelay(100);
2829}
2830
5bb61643
CW		 2831static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2832{
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2836 unsigned long flags;
2837 bool pending;
2838
10d83730
VS		 2839 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2840 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2841 return false;
2842
2843 spin_lock_irqsave(&dev->event_lock, flags);
2844 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2845 spin_unlock_irqrestore(&dev->event_lock, flags);
2846
2847 return pending;
2848}
2849
e6c3a2a6
CW		 2850static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2851{
0f91128d 2852 struct drm_device *dev = crtc->dev;
5bb61643 2853 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2854
2855 if (crtc->fb == NULL)
2856 return;
2857
2c10d571
DV		 2858 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2859
5bb61643
CW		 2860 wait_event(dev_priv->pending_flip_queue,
2861 !intel_crtc_has_pending_flip(crtc));
2862
0f91128d
CW		 2863 mutex_lock(&dev->struct_mutex);
2864 intel_finish_fb(crtc->fb);
2865 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2866}
2867
e615efe4
ED		 2868/* Program iCLKIP clock to the desired frequency */
2869static void lpt_program_iclkip(struct drm_crtc *crtc)
2870{
2871 struct drm_device *dev = crtc->dev;
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2874 u32 temp;
2875
09153000
DV		 2876 mutex_lock(&dev_priv->dpio_lock);
2877
e615efe4
ED		 2878 /* It is necessary to ungate the pixclk gate prior to programming
2879 * the divisors, and gate it back when it is done.
2880 */
2881 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2882
2883 /* Disable SSCCTL */
2884 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2885 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2886 SBI_SSCCTL_DISABLE,
2887 SBI_ICLK);
e615efe4
ED		 2888
2889 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2890 if (crtc->mode.clock == 20000) {
2891 auxdiv = 1;
2892 divsel = 0x41;
2893 phaseinc = 0x20;
2894 } else {
2895 /* The iCLK virtual clock root frequency is in MHz,
2896 * but the crtc->mode.clock in in KHz. To get the divisors,
2897 * it is necessary to divide one by another, so we
2898 * convert the virtual clock precision to KHz here for higher
2899 * precision.
2900 */
2901 u32 iclk_virtual_root_freq = 172800 * 1000;
2902 u32 iclk_pi_range = 64;
2903 u32 desired_divisor, msb_divisor_value, pi_value;
2904
2905 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2906 msb_divisor_value = desired_divisor / iclk_pi_range;
2907 pi_value = desired_divisor % iclk_pi_range;
2908
2909 auxdiv = 0;
2910 divsel = msb_divisor_value - 2;
2911 phaseinc = pi_value;
2912 }
2913
2914 /* This should not happen with any sane values */
2915 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2916 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2917 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2918 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2919
2920 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2921 crtc->mode.clock,
2922 auxdiv,
2923 divsel,
2924 phasedir,
2925 phaseinc);
2926
2927 /* Program SSCDIVINTPHASE6 */
988d6ee8 2928 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2929 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2930 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2931 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2932 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2933 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2934 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2935 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2936
2937 /* Program SSCAUXDIV */
988d6ee8 2938 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2939 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2940 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2941 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2942
2943 /* Enable modulator and associated divider */
988d6ee8 2944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2945 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2947
2948 /* Wait for initialization time */
2949 udelay(24);
2950
2951 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2952
2953 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2954}
2955
275f01b2
DV		 2956static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2957 enum pipe pch_transcoder)
2958{
2959 struct drm_device *dev = crtc->base.dev;
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2962
2963 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2964 I915_READ(HTOTAL(cpu_transcoder)));
2965 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2966 I915_READ(HBLANK(cpu_transcoder)));
2967 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2968 I915_READ(HSYNC(cpu_transcoder)));
2969
2970 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2971 I915_READ(VTOTAL(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2973 I915_READ(VBLANK(cpu_transcoder)));
2974 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2975 I915_READ(VSYNC(cpu_transcoder)));
2976 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2977 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2978}
2979
f67a559d
JB		 2980/*
2981 * Enable PCH resources required for PCH ports:
2982 * - PCH PLLs
2983 * - FDI training & RX/TX
2984 * - update transcoder timings
2985 * - DP transcoding bits
2986 * - transcoder
2987 */
2988static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2989{
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2993 int pipe = intel_crtc->pipe;
ee7b9f93 2994 u32 reg, temp;
2c07245f 2995
ab9412ba 2996 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2997
cd986abb
DV		 2998 /* Write the TU size bits before fdi link training, so that error
2999 * detection works. */
3000 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3001 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3002
c98e9dcf 3003 /* For PCH output, training FDI link */
674cf967 3004 dev_priv->display.fdi_link_train(crtc);
2c07245f 3005
3ad8a208
DV		 3006 /* We need to program the right clock selection before writing the pixel
3007 * mutliplier into the DPLL. */
303b81e0 3008 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3009 u32 sel;
4b645f14 3010
c98e9dcf 3011 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3012 temp |= TRANS_DPLL_ENABLE(pipe);
3013 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3014 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3015 temp |= sel;
3016 else
3017 temp &= ~sel;
c98e9dcf 3018 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3019 }
5eddb70b 3020
3ad8a208
DV		 3021 /* XXX: pch pll's can be enabled any time before we enable the PCH
3022 * transcoder, and we actually should do this to not upset any PCH
3023 * transcoder that already use the clock when we share it.
3024 *
3025 * Note that enable_shared_dpll tries to do the right thing, but
3026 * get_shared_dpll unconditionally resets the pll - we need that to have
3027 * the right LVDS enable sequence. */
3028 ironlake_enable_shared_dpll(intel_crtc);
3029
d9b6cb56
JB		 3030 /* set transcoder timing, panel must allow it */
3031 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3032 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3033
303b81e0 3034 intel_fdi_normal_train(crtc);
5e84e1a4 3035
c98e9dcf
JB		 3036 /* For PCH DP, enable TRANS_DP_CTL */
3037 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3038 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3039 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3040 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3041 reg = TRANS_DP_CTL(pipe);
3042 temp = I915_READ(reg);
3043 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3044 TRANS_DP_SYNC_MASK |
3045 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3046 temp |= (TRANS_DP_OUTPUT_ENABLE |
3047 TRANS_DP_ENH_FRAMING);
9325c9f0 3048 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3049
3050 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3051 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3052 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3053 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3054
3055 switch (intel_trans_dp_port_sel(crtc)) {
3056 case PCH_DP_B:
5eddb70b 3057 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3058 break;
3059 case PCH_DP_C:
5eddb70b 3060 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3061 break;
3062 case PCH_DP_D:
5eddb70b 3063 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3064 break;
3065 default:
e95d41e1 3066 BUG();
32f9d658 3067 }
2c07245f 3068
5eddb70b 3069 I915_WRITE(reg, temp);
6be4a607 3070 }
b52eb4dc 3071
b8a4f404 3072 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3073}
3074
1507e5bd
PZ		 3075static void lpt_pch_enable(struct drm_crtc *crtc)
3076{
3077 struct drm_device *dev = crtc->dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3080 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3081
ab9412ba 3082 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3083
8c52b5e8 3084 lpt_program_iclkip(crtc);
1507e5bd 3085
0540e488 3086 /* Set transcoder timing. */
275f01b2 3087 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3088
937bb610 3089 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3090}
3091
e2b78267 3092static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3093{
e2b78267 3094 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3095
3096 if (pll == NULL)
3097 return;
3098
3099 if (pll->refcount == 0) {
46edb027 3100 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3101 return;
3102 }
3103
f4a091c7
DV		 3104 if (--pll->refcount == 0) {
3105 WARN_ON(pll->on);
3106 WARN_ON(pll->active);
3107 }
3108
a43f6e0f 3109 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3110}
3111
b89a1d39 3112static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3113{
e2b78267
DV		 3114 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3115 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3116 enum intel_dpll_id i;
ee7b9f93 3117
ee7b9f93 3118 if (pll) {
46edb027
DV		 3119 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3120 crtc->base.base.id, pll->name);
e2b78267 3121 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3122 }
3123
98b6bd99
DV		 3124 if (HAS_PCH_IBX(dev_priv->dev)) {
3125 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3126 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3127 pll = &dev_priv->shared_dplls[i];
98b6bd99 3128
46edb027
DV		 3129 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3130 crtc->base.base.id, pll->name);
98b6bd99
DV		 3131
3132 goto found;
3133 }
3134
e72f9fbf
DV		 3135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3136 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3137
3138 /* Only want to check enabled timings first */
3139 if (pll->refcount == 0)
3140 continue;
3141
b89a1d39
DV		 3142 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3143 sizeof(pll->hw_state)) == 0) {
46edb027 3144 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3145 crtc->base.base.id,
46edb027 3146 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3147
3148 goto found;
3149 }
3150 }
3151
3152 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3153 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3154 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3155 if (pll->refcount == 0) {
46edb027
DV		 3156 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3157 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3158 goto found;
3159 }
3160 }
3161
3162 return NULL;
3163
3164found:
a43f6e0f 3165 crtc->config.shared_dpll = i;
46edb027
DV		 3166 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3167 pipe_name(crtc->pipe));
ee7b9f93 3168
cdbd2316 3169 if (pll->active == 0) {
66e985c0
DV		 3170 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3171 sizeof(pll->hw_state));
3172
46edb027 3173 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3174 WARN_ON(pll->on);
e9d6944e 3175 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3176
15bdd4cf 3177 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3178 }
3179 pll->refcount++;
e04c7350 3180
ee7b9f93
JB		 3181 return pll;
3182}
3183
a1520318 3184static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3185{
3186 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3187 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3188 u32 temp;
3189
3190 temp = I915_READ(dslreg);
3191 udelay(500);
3192 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3193 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3194 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3195 }
3196}
3197
b074cec8
JB		 3198static void ironlake_pfit_enable(struct intel_crtc *crtc)
3199{
3200 struct drm_device *dev = crtc->base.dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 int pipe = crtc->pipe;
3203
0ef37f3f 3204 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3205 /* Force use of hard-coded filter coefficients
3206 * as some pre-programmed values are broken,
3207 * e.g. x201.
3208 */
3209 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3210 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3211 PF_PIPE_SEL_IVB(pipe));
3212 else
3213 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3214 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3215 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3216 }
3217}
3218
bb53d4ae
VS		 3219static void intel_enable_planes(struct drm_crtc *crtc)
3220{
3221 struct drm_device *dev = crtc->dev;
3222 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3223 struct intel_plane *intel_plane;
3224
3225 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3226 if (intel_plane->pipe == pipe)
3227 intel_plane_restore(&intel_plane->base);
3228}
3229
3230static void intel_disable_planes(struct drm_crtc *crtc)
3231{
3232 struct drm_device *dev = crtc->dev;
3233 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3234 struct intel_plane *intel_plane;
3235
3236 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3237 if (intel_plane->pipe == pipe)
3238 intel_plane_disable(&intel_plane->base);
3239}
3240
f67a559d
JB		 3241static void ironlake_crtc_enable(struct drm_crtc *crtc)
3242{
3243 struct drm_device *dev = crtc->dev;
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3246 struct intel_encoder *encoder;
f67a559d
JB		 3247 int pipe = intel_crtc->pipe;
3248 int plane = intel_crtc->plane;
f67a559d 3249
08a48469
DV		 3250 WARN_ON(!crtc->enabled);
3251
f67a559d
JB		 3252 if (intel_crtc->active)
3253 return;
3254
3255 intel_crtc->active = true;
8664281b
PZ		 3256
3257 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3258 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3259
f67a559d
JB		 3260 intel_update_watermarks(dev);
3261
f6736a1a 3262 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3263 if (encoder->pre_enable)
3264 encoder->pre_enable(encoder);
f67a559d 3265
5bfe2ac0 3266 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3267 /* Note: FDI PLL enabling _must_ be done before we enable the
3268 * cpu pipes, hence this is separate from all the other fdi/pch
3269 * enabling. */
88cefb6c 3270 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3271 } else {
3272 assert_fdi_tx_disabled(dev_priv, pipe);
3273 assert_fdi_rx_disabled(dev_priv, pipe);
3274 }
f67a559d 3275
b074cec8 3276 ironlake_pfit_enable(intel_crtc);
f67a559d 3277
9c54c0dd
JB		 3278 /*
3279 * On ILK+ LUT must be loaded before the pipe is running but with
3280 * clocks enabled
3281 */
3282 intel_crtc_load_lut(crtc);
3283
5bfe2ac0
DV		 3284 intel_enable_pipe(dev_priv, pipe,
3285 intel_crtc->config.has_pch_encoder);
f67a559d 3286 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3287 intel_enable_planes(crtc);
5c38d48c 3288 intel_crtc_update_cursor(crtc, true);
f67a559d 3289
5bfe2ac0 3290 if (intel_crtc->config.has_pch_encoder)
f67a559d 3291 ironlake_pch_enable(crtc);
c98e9dcf 3292
d1ebd816 3293 mutex_lock(&dev->struct_mutex);
bed4a673 3294 intel_update_fbc(dev);
d1ebd816
BW		 3295 mutex_unlock(&dev->struct_mutex);
3296
fa5c73b1
DV		 3297 for_each_encoder_on_crtc(dev, crtc, encoder)
3298 encoder->enable(encoder);
61b77ddd
DV		 3299
3300 if (HAS_PCH_CPT(dev))
a1520318 3301 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3302
3303 /*
3304 * There seems to be a race in PCH platform hw (at least on some
3305 * outputs) where an enabled pipe still completes any pageflip right
3306 * away (as if the pipe is off) instead of waiting for vblank. As soon
3307 * as the first vblank happend, everything works as expected. Hence just
3308 * wait for one vblank before returning to avoid strange things
3309 * happening.
3310 */
3311 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3312}
3313
42db64ef
PZ		 3314/* IPS only exists on ULT machines and is tied to pipe A. */
3315static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3316{
f5adf94e 3317 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3318}
3319
3320static void hsw_enable_ips(struct intel_crtc *crtc)
3321{
3322 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3323
3324 if (!crtc->config.ips_enabled)
3325 return;
3326
3327 /* We can only enable IPS after we enable a plane and wait for a vblank.
3328 * We guarantee that the plane is enabled by calling intel_enable_ips
3329 * only after intel_enable_plane. And intel_enable_plane already waits
3330 * for a vblank, so all we need to do here is to enable the IPS bit. */
3331 assert_plane_enabled(dev_priv, crtc->plane);
3332 I915_WRITE(IPS_CTL, IPS_ENABLE);
3333}
3334
3335static void hsw_disable_ips(struct intel_crtc *crtc)
3336{
3337 struct drm_device *dev = crtc->base.dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339
3340 if (!crtc->config.ips_enabled)
3341 return;
3342
3343 assert_plane_enabled(dev_priv, crtc->plane);
3344 I915_WRITE(IPS_CTL, 0);
3345
3346 /* We need to wait for a vblank before we can disable the plane. */
3347 intel_wait_for_vblank(dev, crtc->pipe);
3348}
3349
4f771f10
PZ		 3350static void haswell_crtc_enable(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 struct intel_encoder *encoder;
3356 int pipe = intel_crtc->pipe;
3357 int plane = intel_crtc->plane;
4f771f10
PZ		 3358
3359 WARN_ON(!crtc->enabled);
3360
3361 if (intel_crtc->active)
3362 return;
3363
3364 intel_crtc->active = true;
8664281b
PZ		 3365
3366 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3367 if (intel_crtc->config.has_pch_encoder)
3368 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3369
4f771f10
PZ		 3370 intel_update_watermarks(dev);
3371
5bfe2ac0 3372 if (intel_crtc->config.has_pch_encoder)
04945641 3373 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3374
3375 for_each_encoder_on_crtc(dev, crtc, encoder)
3376 if (encoder->pre_enable)
3377 encoder->pre_enable(encoder);
3378
1f544388 3379 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3380
b074cec8 3381 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3382
3383 /*
3384 * On ILK+ LUT must be loaded before the pipe is running but with
3385 * clocks enabled
3386 */
3387 intel_crtc_load_lut(crtc);
3388
1f544388 3389 intel_ddi_set_pipe_settings(crtc);
8228c251 3390 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3391
5bfe2ac0
DV		 3392 intel_enable_pipe(dev_priv, pipe,
3393 intel_crtc->config.has_pch_encoder);
4f771f10 3394 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3395 intel_enable_planes(crtc);
5c38d48c 3396 intel_crtc_update_cursor(crtc, true);
4f771f10 3397
42db64ef
PZ		 3398 hsw_enable_ips(intel_crtc);
3399
5bfe2ac0 3400 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3401 lpt_pch_enable(crtc);
4f771f10
PZ		 3402
3403 mutex_lock(&dev->struct_mutex);
3404 intel_update_fbc(dev);
3405 mutex_unlock(&dev->struct_mutex);
3406
4f771f10
PZ		 3407 for_each_encoder_on_crtc(dev, crtc, encoder)
3408 encoder->enable(encoder);
3409
4f771f10
PZ		 3410 /*
3411 * There seems to be a race in PCH platform hw (at least on some
3412 * outputs) where an enabled pipe still completes any pageflip right
3413 * away (as if the pipe is off) instead of waiting for vblank. As soon
3414 * as the first vblank happend, everything works as expected. Hence just
3415 * wait for one vblank before returning to avoid strange things
3416 * happening.
3417 */
3418 intel_wait_for_vblank(dev, intel_crtc->pipe);
3419}
3420
3f8dce3a
DV		 3421static void ironlake_pfit_disable(struct intel_crtc *crtc)
3422{
3423 struct drm_device *dev = crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = crtc->pipe;
3426
3427 /* To avoid upsetting the power well on haswell only disable the pfit if
3428 * it's in use. The hw state code will make sure we get this right. */
3429 if (crtc->config.pch_pfit.size) {
3430 I915_WRITE(PF_CTL(pipe), 0);
3431 I915_WRITE(PF_WIN_POS(pipe), 0);
3432 I915_WRITE(PF_WIN_SZ(pipe), 0);
3433 }
3434}
3435
6be4a607
JB		 3436static void ironlake_crtc_disable(struct drm_crtc *crtc)
3437{
3438 struct drm_device *dev = crtc->dev;
3439 struct drm_i915_private *dev_priv = dev->dev_private;
3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3441 struct intel_encoder *encoder;
6be4a607
JB		 3442 int pipe = intel_crtc->pipe;
3443 int plane = intel_crtc->plane;
5eddb70b 3444 u32 reg, temp;
b52eb4dc 3445
ef9c3aee 3446
f7abfe8b
CW		 3447 if (!intel_crtc->active)
3448 return;
3449
ea9d758d
DV		 3450 for_each_encoder_on_crtc(dev, crtc, encoder)
3451 encoder->disable(encoder);
3452
e6c3a2a6 3453 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3454 drm_vblank_off(dev, pipe);
913d8d11 3455
5c3fe8b0 3456 if (dev_priv->fbc.plane == plane)
973d04f9 3457 intel_disable_fbc(dev);
2c07245f 3458
0d5b8c61 3459 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3460 intel_disable_planes(crtc);
0d5b8c61
VS		 3461 intel_disable_plane(dev_priv, plane, pipe);
3462
d925c59a
DV		 3463 if (intel_crtc->config.has_pch_encoder)
3464 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3465
b24e7179 3466 intel_disable_pipe(dev_priv, pipe);
32f9d658 3467
3f8dce3a 3468 ironlake_pfit_disable(intel_crtc);
2c07245f 3469
bf49ec8c
DV		 3470 for_each_encoder_on_crtc(dev, crtc, encoder)
3471 if (encoder->post_disable)
3472 encoder->post_disable(encoder);
2c07245f 3473
d925c59a
DV		 3474 if (intel_crtc->config.has_pch_encoder) {
3475 ironlake_fdi_disable(crtc);
913d8d11 3476
d925c59a
DV		 3477 ironlake_disable_pch_transcoder(dev_priv, pipe);
3478 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3479
d925c59a
DV		 3480 if (HAS_PCH_CPT(dev)) {
3481 /* disable TRANS_DP_CTL */
3482 reg = TRANS_DP_CTL(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3485 TRANS_DP_PORT_SEL_MASK);
3486 temp |= TRANS_DP_PORT_SEL_NONE;
3487 I915_WRITE(reg, temp);
3488
3489 /* disable DPLL_SEL */
3490 temp = I915_READ(PCH_DPLL_SEL);
11887397 3491 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3492 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3493 }
e3421a18 3494
d925c59a 3495 /* disable PCH DPLL */
e72f9fbf 3496 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3497
d925c59a
DV		 3498 ironlake_fdi_pll_disable(intel_crtc);
3499 }
6b383a7f 3500
f7abfe8b 3501 intel_crtc->active = false;
6b383a7f 3502 intel_update_watermarks(dev);
d1ebd816
BW		 3503
3504 mutex_lock(&dev->struct_mutex);
6b383a7f 3505 intel_update_fbc(dev);
d1ebd816 3506 mutex_unlock(&dev->struct_mutex);
6be4a607 3507}
1b3c7a47 3508
4f771f10 3509static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3510{
4f771f10
PZ		 3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3b117c8f 3517 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3518
4f771f10
PZ		 3519 if (!intel_crtc->active)
3520 return;
3521
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3524
3525 intel_crtc_wait_for_pending_flips(crtc);
3526 drm_vblank_off(dev, pipe);
4f771f10 3527
891348b2 3528 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3529 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3530 intel_disable_fbc(dev);
3531
42db64ef
PZ		 3532 hsw_disable_ips(intel_crtc);
3533
0d5b8c61 3534 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3535 intel_disable_planes(crtc);
891348b2
RV		 3536 intel_disable_plane(dev_priv, plane, pipe);
3537
8664281b
PZ		 3538 if (intel_crtc->config.has_pch_encoder)
3539 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3540 intel_disable_pipe(dev_priv, pipe);
3541
ad80a810 3542 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3543
3f8dce3a 3544 ironlake_pfit_disable(intel_crtc);
4f771f10 3545
1f544388 3546 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3547
3548 for_each_encoder_on_crtc(dev, crtc, encoder)
3549 if (encoder->post_disable)
3550 encoder->post_disable(encoder);
3551
88adfff1 3552 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3553 lpt_disable_pch_transcoder(dev_priv);
8664281b 3554 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3555 intel_ddi_fdi_disable(crtc);
83616634 3556 }
4f771f10
PZ		 3557
3558 intel_crtc->active = false;
3559 intel_update_watermarks(dev);
3560
3561 mutex_lock(&dev->struct_mutex);
3562 intel_update_fbc(dev);
3563 mutex_unlock(&dev->struct_mutex);
3564}
3565
ee7b9f93
JB		 3566static void ironlake_crtc_off(struct drm_crtc *crtc)
3567{
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3569 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3570}
3571
6441ab5f
PZ		 3572static void haswell_crtc_off(struct drm_crtc *crtc)
3573{
3574 intel_ddi_put_crtc_pll(crtc);
3575}
3576
02e792fb
DV		 3577static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3578{
02e792fb 3579 if (!enable && intel_crtc->overlay) {
23f09ce3 3580 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3581 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3582
23f09ce3 3583 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3584 dev_priv->mm.interruptible = false;
3585 (void) intel_overlay_switch_off(intel_crtc->overlay);
3586 dev_priv->mm.interruptible = true;
23f09ce3 3587 mutex_unlock(&dev->struct_mutex);
02e792fb 3588 }
02e792fb 3589
5dcdbcb0
CW		 3590 /* Let userspace switch the overlay on again. In most cases userspace
3591 * has to recompute where to put it anyway.
3592 */
02e792fb
DV		 3593}
3594
61bc95c1
EE		 3595/**
3596 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3597 * cursor plane briefly if not already running after enabling the display
3598 * plane.
3599 * This workaround avoids occasional blank screens when self refresh is
3600 * enabled.
3601 */
3602static void
3603g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3604{
3605 u32 cntl = I915_READ(CURCNTR(pipe));
3606
3607 if ((cntl & CURSOR_MODE) == 0) {
3608 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3609
3610 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3611 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3612 intel_wait_for_vblank(dev_priv->dev, pipe);
3613 I915_WRITE(CURCNTR(pipe), cntl);
3614 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3615 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3616 }
3617}
3618
2dd24552
JB		 3619static void i9xx_pfit_enable(struct intel_crtc *crtc)
3620{
3621 struct drm_device *dev = crtc->base.dev;
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 struct intel_crtc_config *pipe_config = &crtc->config;
3624
328d8e82 3625 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3626 return;
3627
2dd24552 3628 /*
c0b03411
DV		 3629 * The panel fitter should only be adjusted whilst the pipe is disabled,
3630 * according to register description and PRM.
2dd24552 3631 */
c0b03411
DV		 3632 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3633 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3634
b074cec8
JB		 3635 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3636 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3637
3638 /* Border color in case we don't scale up to the full screen. Black by
3639 * default, change to something else for debugging. */
3640 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3641}
3642
89b667f8
JB		 3643static void valleyview_crtc_enable(struct drm_crtc *crtc)
3644{
3645 struct drm_device *dev = crtc->dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648 struct intel_encoder *encoder;
3649 int pipe = intel_crtc->pipe;
3650 int plane = intel_crtc->plane;
3651
3652 WARN_ON(!crtc->enabled);
3653
3654 if (intel_crtc->active)
3655 return;
3656
3657 intel_crtc->active = true;
3658 intel_update_watermarks(dev);
3659
89b667f8
JB		 3660 for_each_encoder_on_crtc(dev, crtc, encoder)
3661 if (encoder->pre_pll_enable)
3662 encoder->pre_pll_enable(encoder);
3663
426115cf 3664 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3665
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->pre_enable)
3668 encoder->pre_enable(encoder);
3669
2dd24552
JB		 3670 i9xx_pfit_enable(intel_crtc);
3671
63cbb074
VS		 3672 intel_crtc_load_lut(crtc);
3673
89b667f8
JB		 3674 intel_enable_pipe(dev_priv, pipe, false);
3675 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3676 intel_enable_planes(crtc);
5c38d48c 3677 intel_crtc_update_cursor(crtc, true);
89b667f8 3678
89b667f8 3679 intel_update_fbc(dev);
5004945f
JN		 3680
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
89b667f8
JB		 3683}
3684
0b8765c6 3685static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3686{
3687 struct drm_device *dev = crtc->dev;
79e53945
JB		 3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3690 struct intel_encoder *encoder;
79e53945 3691 int pipe = intel_crtc->pipe;
80824003 3692 int plane = intel_crtc->plane;
79e53945 3693
08a48469
DV		 3694 WARN_ON(!crtc->enabled);
3695
f7abfe8b
CW		 3696 if (intel_crtc->active)
3697 return;
3698
3699 intel_crtc->active = true;
6b383a7f
CW		 3700 intel_update_watermarks(dev);
3701
9d6d9f19
MK		 3702 for_each_encoder_on_crtc(dev, crtc, encoder)
3703 if (encoder->pre_enable)
3704 encoder->pre_enable(encoder);
3705
f6736a1a
DV		 3706 i9xx_enable_pll(intel_crtc);
3707
2dd24552
JB		 3708 i9xx_pfit_enable(intel_crtc);
3709
63cbb074
VS		 3710 intel_crtc_load_lut(crtc);
3711
040484af 3712 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3713 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3714 intel_enable_planes(crtc);
22e407d7 3715 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3716 if (IS_G4X(dev))
3717 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3718 intel_crtc_update_cursor(crtc, true);
79e53945 3719
0b8765c6
JB		 3720 /* Give the overlay scaler a chance to enable if it's on this pipe */
3721 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3722
f440eb13 3723 intel_update_fbc(dev);
ef9c3aee 3724
fa5c73b1
DV		 3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
0b8765c6 3727}
79e53945 3728
87476d63
DV		 3729static void i9xx_pfit_disable(struct intel_crtc *crtc)
3730{
3731 struct drm_device *dev = crtc->base.dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3733
328d8e82
DV		 3734 if (!crtc->config.gmch_pfit.control)
3735 return;
87476d63 3736
328d8e82 3737 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3738
328d8e82
DV		 3739 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3740 I915_READ(PFIT_CONTROL));
3741 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3742}
3743
0b8765c6
JB		 3744static void i9xx_crtc_disable(struct drm_crtc *crtc)
3745{
3746 struct drm_device *dev = crtc->dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3749 struct intel_encoder *encoder;
0b8765c6
JB		 3750 int pipe = intel_crtc->pipe;
3751 int plane = intel_crtc->plane;
ef9c3aee 3752
f7abfe8b
CW		 3753 if (!intel_crtc->active)
3754 return;
3755
ea9d758d
DV		 3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 encoder->disable(encoder);
3758
0b8765c6 3759 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3760 intel_crtc_wait_for_pending_flips(crtc);
3761 drm_vblank_off(dev, pipe);
0b8765c6 3762
5c3fe8b0 3763 if (dev_priv->fbc.plane == plane)
973d04f9 3764 intel_disable_fbc(dev);
79e53945 3765
0d5b8c61
VS		 3766 intel_crtc_dpms_overlay(intel_crtc, false);
3767 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3768 intel_disable_planes(crtc);
b24e7179 3769 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3770
b24e7179 3771 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3772
87476d63 3773 i9xx_pfit_disable(intel_crtc);
24a1f16d 3774
89b667f8
JB		 3775 for_each_encoder_on_crtc(dev, crtc, encoder)
3776 if (encoder->post_disable)
3777 encoder->post_disable(encoder);
3778
50b44a44 3779 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3780
f7abfe8b 3781 intel_crtc->active = false;
6b383a7f
CW		 3782 intel_update_fbc(dev);
3783 intel_update_watermarks(dev);
0b8765c6
JB		 3784}
3785
ee7b9f93
JB		 3786static void i9xx_crtc_off(struct drm_crtc *crtc)
3787{
3788}
3789
976f8a20
DV		 3790static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3791 bool enabled)
2c07245f
ZW		 3792{
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_master_private *master_priv;
3795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3796 int pipe = intel_crtc->pipe;
79e53945
JB		 3797
3798 if (!dev->primary->master)
3799 return;
3800
3801 master_priv = dev->primary->master->driver_priv;
3802 if (!master_priv->sarea_priv)
3803 return;
3804
79e53945
JB		 3805 switch (pipe) {
3806 case 0:
3807 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3808 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3809 break;
3810 case 1:
3811 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3812 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3813 break;
3814 default:
9db4a9c7 3815 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3816 break;
3817 }
79e53945
JB		 3818}
3819
976f8a20
DV		 3820/**
3821 * Sets the power management mode of the pipe and plane.
3822 */
3823void intel_crtc_update_dpms(struct drm_crtc *crtc)
3824{
3825 struct drm_device *dev = crtc->dev;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 struct intel_encoder *intel_encoder;
3828 bool enable = false;
3829
3830 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3831 enable |= intel_encoder->connectors_active;
3832
3833 if (enable)
3834 dev_priv->display.crtc_enable(crtc);
3835 else
3836 dev_priv->display.crtc_disable(crtc);
3837
3838 intel_crtc_update_sarea(crtc, enable);
3839}
3840
cdd59983
CW		 3841static void intel_crtc_disable(struct drm_crtc *crtc)
3842{
cdd59983 3843 struct drm_device *dev = crtc->dev;
976f8a20 3844 struct drm_connector *connector;
ee7b9f93 3845 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3847
976f8a20
DV		 3848 /* crtc should still be enabled when we disable it. */
3849 WARN_ON(!crtc->enabled);
3850
3851 dev_priv->display.crtc_disable(crtc);
c77bf565 3852 intel_crtc->eld_vld = false;
976f8a20 3853 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3854 dev_priv->display.off(crtc);
3855
931872fc
CW		 3856 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3857 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3858
3859 if (crtc->fb) {
3860 mutex_lock(&dev->struct_mutex);
1690e1eb 3861 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3862 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3863 crtc->fb = NULL;
3864 }
3865
3866 /* Update computed state. */
3867 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3868 if (!connector->encoder || !connector->encoder->crtc)
3869 continue;
3870
3871 if (connector->encoder->crtc != crtc)
3872 continue;
3873
3874 connector->dpms = DRM_MODE_DPMS_OFF;
3875 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3876 }
3877}
3878
ea5b213a 3879void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3880{
4ef69c7a 3881 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3882
ea5b213a
CW		 3883 drm_encoder_cleanup(encoder);
3884 kfree(intel_encoder);
7e7d76c3
JB		 3885}
3886
9237329d 3887/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3888 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3889 * state of the entire output pipe. */
9237329d 3890static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3891{
5ab432ef
DV		 3892 if (mode == DRM_MODE_DPMS_ON) {
3893 encoder->connectors_active = true;
3894
b2cabb0e 3895 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3896 } else {
3897 encoder->connectors_active = false;
3898
b2cabb0e 3899 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3900 }
79e53945
JB		 3901}
3902
0a91ca29
DV		 3903/* Cross check the actual hw state with our own modeset state tracking (and it's
3904 * internal consistency). */
b980514c 3905static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3906{
0a91ca29
DV		 3907 if (connector->get_hw_state(connector)) {
3908 struct intel_encoder *encoder = connector->encoder;
3909 struct drm_crtc *crtc;
3910 bool encoder_enabled;
3911 enum pipe pipe;
3912
3913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3914 connector->base.base.id,
3915 drm_get_connector_name(&connector->base));
3916
3917 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3918 "wrong connector dpms state\n");
3919 WARN(connector->base.encoder != &encoder->base,
3920 "active connector not linked to encoder\n");
3921 WARN(!encoder->connectors_active,
3922 "encoder->connectors_active not set\n");
3923
3924 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3925 WARN(!encoder_enabled, "encoder not enabled\n");
3926 if (WARN_ON(!encoder->base.crtc))
3927 return;
3928
3929 crtc = encoder->base.crtc;
3930
3931 WARN(!crtc->enabled, "crtc not enabled\n");
3932 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3933 WARN(pipe != to_intel_crtc(crtc)->pipe,
3934 "encoder active on the wrong pipe\n");
3935 }
79e53945
JB		 3936}
3937
5ab432ef
DV		 3938/* Even simpler default implementation, if there's really no special case to
3939 * consider. */
3940void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3941{
5ab432ef 3942 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3943
5ab432ef
DV		 3944 /* All the simple cases only support two dpms states. */
3945 if (mode != DRM_MODE_DPMS_ON)
3946 mode = DRM_MODE_DPMS_OFF;
d4270e57 3947
5ab432ef
DV		 3948 if (mode == connector->dpms)
3949 return;
3950
3951 connector->dpms = mode;
3952
3953 /* Only need to change hw state when actually enabled */
3954 if (encoder->base.crtc)
3955 intel_encoder_dpms(encoder, mode);
3956 else
8af6cf88 3957 WARN_ON(encoder->connectors_active != false);
0a91ca29 3958
b980514c 3959 intel_modeset_check_state(connector->dev);
79e53945
JB		 3960}
3961
f0947c37
DV		 3962/* Simple connector->get_hw_state implementation for encoders that support only
3963 * one connector and no cloning and hence the encoder state determines the state
3964 * of the connector. */
3965bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3966{
24929352 3967 enum pipe pipe = 0;
f0947c37 3968 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3969
f0947c37 3970 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3971}
3972
1857e1da
DV		 3973static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3974 struct intel_crtc_config *pipe_config)
3975{
3976 struct drm_i915_private *dev_priv = dev->dev_private;
3977 struct intel_crtc *pipe_B_crtc =
3978 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3979
3980 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3982 if (pipe_config->fdi_lanes > 4) {
3983 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3984 pipe_name(pipe), pipe_config->fdi_lanes);
3985 return false;
3986 }
3987
3988 if (IS_HASWELL(dev)) {
3989 if (pipe_config->fdi_lanes > 2) {
3990 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3991 pipe_config->fdi_lanes);
3992 return false;
3993 } else {
3994 return true;
3995 }
3996 }
3997
3998 if (INTEL_INFO(dev)->num_pipes == 2)
3999 return true;
4000
4001 /* Ivybridge 3 pipe is really complicated */
4002 switch (pipe) {
4003 case PIPE_A:
4004 return true;
4005 case PIPE_B:
4006 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4007 pipe_config->fdi_lanes > 2) {
4008 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4009 pipe_name(pipe), pipe_config->fdi_lanes);
4010 return false;
4011 }
4012 return true;
4013 case PIPE_C:
1e833f40 4014 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4015 pipe_B_crtc->config.fdi_lanes <= 2) {
4016 if (pipe_config->fdi_lanes > 2) {
4017 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4018 pipe_name(pipe), pipe_config->fdi_lanes);
4019 return false;
4020 }
4021 } else {
4022 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4023 return false;
4024 }
4025 return true;
4026 default:
4027 BUG();
4028 }
4029}
4030
e29c22c0
DV		 4031#define RETRY 1
4032static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4033 struct intel_crtc_config *pipe_config)
877d48d5 4034{
1857e1da 4035 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4036 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4037 int lane, link_bw, fdi_dotclock;
e29c22c0 4038 bool setup_ok, needs_recompute = false;
877d48d5 4039
e29c22c0 4040retry:
877d48d5
DV		 4041 /* FDI is a binary signal running at ~2.7GHz, encoding
4042 * each output octet as 10 bits. The actual frequency
4043 * is stored as a divider into a 100MHz clock, and the
4044 * mode pixel clock is stored in units of 1KHz.
4045 * Hence the bw of each lane in terms of the mode signal
4046 * is:
4047 */
4048 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4049
ff9a6750 4050 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4051 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4052
2bd89a07 4053 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4054 pipe_config->pipe_bpp);
4055
4056 pipe_config->fdi_lanes = lane;
4057
2bd89a07 4058 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4059 link_bw, &pipe_config->fdi_m_n);
1857e1da 4060
e29c22c0
DV		 4061 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4062 intel_crtc->pipe, pipe_config);
4063 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4064 pipe_config->pipe_bpp -= 2*3;
4065 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4066 pipe_config->pipe_bpp);
4067 needs_recompute = true;
4068 pipe_config->bw_constrained = true;
4069
4070 goto retry;
4071 }
4072
4073 if (needs_recompute)
4074 return RETRY;
4075
4076 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4077}
4078
42db64ef
PZ		 4079static void hsw_compute_ips_config(struct intel_crtc *crtc,
4080 struct intel_crtc_config *pipe_config)
4081{
3c4ca58c
PZ		 4082 pipe_config->ips_enabled = i915_enable_ips &&
4083 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4084 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4085}
4086
a43f6e0f 4087static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4088 struct intel_crtc_config *pipe_config)
79e53945 4089{
a43f6e0f 4090 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4091 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4092
bad720ff 4093 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4094 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4095 if (pipe_config->requested_mode.clock * 3
4096 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4097 return -EINVAL;
2c07245f 4098 }
89749350 4099
8693a824
DL		 4100 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4101 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4102 */
4103 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4104 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4105 return -EINVAL;
44f46b42 4106
bd080ee5 4107 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4108 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4109 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4110 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4111 * for lvds. */
4112 pipe_config->pipe_bpp = 8*3;
4113 }
4114
f5adf94e 4115 if (HAS_IPS(dev))
a43f6e0f
DV		 4116 hsw_compute_ips_config(crtc, pipe_config);
4117
4118 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4119 * clock survives for now. */
4120 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4121 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4122
877d48d5 4123 if (pipe_config->has_pch_encoder)
a43f6e0f 4124 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4125
e29c22c0 4126 return 0;
79e53945
JB		 4127}
4128
25eb05fc
JB		 4129static int valleyview_get_display_clock_speed(struct drm_device *dev)
4130{
4131 return 400000; /* FIXME */
4132}
4133
e70236a8
JB		 4134static int i945_get_display_clock_speed(struct drm_device *dev)
4135{
4136 return 400000;
4137}
79e53945 4138
e70236a8 4139static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4140{
e70236a8
JB		 4141 return 333000;
4142}
79e53945 4143
e70236a8
JB		 4144static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 200000;
4147}
79e53945 4148
257a7ffc
DV		 4149static int pnv_get_display_clock_speed(struct drm_device *dev)
4150{
4151 u16 gcfgc = 0;
4152
4153 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4154
4155 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4156 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4157 return 267000;
4158 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4159 return 333000;
4160 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4161 return 444000;
4162 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4163 return 200000;
4164 default:
4165 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4166 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4167 return 133000;
4168 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4169 return 167000;
4170 }
4171}
4172
e70236a8
JB		 4173static int i915gm_get_display_clock_speed(struct drm_device *dev)
4174{
4175 u16 gcfgc = 0;
79e53945 4176
e70236a8
JB		 4177 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4178
4179 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4180 return 133000;
4181 else {
4182 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4183 case GC_DISPLAY_CLOCK_333_MHZ:
4184 return 333000;
4185 default:
4186 case GC_DISPLAY_CLOCK_190_200_MHZ:
4187 return 190000;
79e53945 4188 }
e70236a8
JB		 4189 }
4190}
4191
4192static int i865_get_display_clock_speed(struct drm_device *dev)
4193{
4194 return 266000;
4195}
4196
4197static int i855_get_display_clock_speed(struct drm_device *dev)
4198{
4199 u16 hpllcc = 0;
4200 /* Assume that the hardware is in the high speed state. This
4201 * should be the default.
4202 */
4203 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4204 case GC_CLOCK_133_200:
4205 case GC_CLOCK_100_200:
4206 return 200000;
4207 case GC_CLOCK_166_250:
4208 return 250000;
4209 case GC_CLOCK_100_133:
79e53945 4210 return 133000;
e70236a8 4211 }
79e53945 4212
e70236a8
JB		 4213 /* Shouldn't happen */
4214 return 0;
4215}
79e53945 4216
e70236a8
JB		 4217static int i830_get_display_clock_speed(struct drm_device *dev)
4218{
4219 return 133000;
79e53945
JB		 4220}
4221
2c07245f 4222static void
a65851af 4223intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4224{
a65851af
VS		 4225 while (*num > DATA_LINK_M_N_MASK ||
4226 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4227 *num >>= 1;
4228 *den >>= 1;
4229 }
4230}
4231
a65851af
VS		 4232static void compute_m_n(unsigned int m, unsigned int n,
4233 uint32_t *ret_m, uint32_t *ret_n)
4234{
4235 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4236 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4237 intel_reduce_m_n_ratio(ret_m, ret_n);
4238}
4239
e69d0bc1
DV		 4240void
4241intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4242 int pixel_clock, int link_clock,
4243 struct intel_link_m_n *m_n)
2c07245f 4244{
e69d0bc1 4245 m_n->tu = 64;
a65851af
VS		 4246
4247 compute_m_n(bits_per_pixel * pixel_clock,
4248 link_clock * nlanes * 8,
4249 &m_n->gmch_m, &m_n->gmch_n);
4250
4251 compute_m_n(pixel_clock, link_clock,
4252 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4253}
4254
a7615030
CW		 4255static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4256{
72bbe58c
KP		 4257 if (i915_panel_use_ssc >= 0)
4258 return i915_panel_use_ssc != 0;
41aa3448 4259 return dev_priv->vbt.lvds_use_ssc
435793df 4260 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4261}
4262
a0c4da24
JB		 4263static int vlv_get_refclk(struct drm_crtc *crtc)
4264{
4265 struct drm_device *dev = crtc->dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 int refclk = 27000; /* for DP & HDMI */
4268
4269 return 100000; /* only one validated so far */
4270
4271 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4272 refclk = 96000;
4273 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4274 if (intel_panel_use_ssc(dev_priv))
4275 refclk = 100000;
4276 else
4277 refclk = 96000;
4278 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4279 refclk = 100000;
4280 }
4281
4282 return refclk;
4283}
4284
c65d77d8
JB		 4285static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4286{
4287 struct drm_device *dev = crtc->dev;
4288 struct drm_i915_private *dev_priv = dev->dev_private;
4289 int refclk;
4290
a0c4da24
JB		 4291 if (IS_VALLEYVIEW(dev)) {
4292 refclk = vlv_get_refclk(crtc);
4293 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4294 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4295 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4296 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4297 refclk / 1000);
4298 } else if (!IS_GEN2(dev)) {
4299 refclk = 96000;
4300 } else {
4301 refclk = 48000;
4302 }
4303
4304 return refclk;
4305}
4306
7429e9d4 4307static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4308{
7df00d7a 4309 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4310}
f47709a9 4311
7429e9d4
DV		 4312static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4313{
4314 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4315}
4316
f47709a9 4317static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4318 intel_clock_t *reduced_clock)
4319{
f47709a9 4320 struct drm_device *dev = crtc->base.dev;
a7516a05 4321 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4322 int pipe = crtc->pipe;
a7516a05
JB		 4323 u32 fp, fp2 = 0;
4324
4325 if (IS_PINEVIEW(dev)) {
7429e9d4 4326 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4327 if (reduced_clock)
7429e9d4 4328 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4329 } else {
7429e9d4 4330 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4331 if (reduced_clock)
7429e9d4 4332 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4333 }
4334
4335 I915_WRITE(FP0(pipe), fp);
8bcc2795 4336 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4337
f47709a9
DV		 4338 crtc->lowfreq_avail = false;
4339 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4340 reduced_clock && i915_powersave) {
4341 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4342 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4343 crtc->lowfreq_avail = true;
a7516a05
JB		 4344 } else {
4345 I915_WRITE(FP1(pipe), fp);
8bcc2795 4346 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4347 }
4348}
4349
89b667f8
JB		 4350static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4351{
4352 u32 reg_val;
4353
4354 /*
4355 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4356 * and set it to a reasonable value instead.
4357 */
ae99258f 4358 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4359 reg_val &= 0xffffff00;
4360 reg_val |= 0x00000030;
ae99258f 4361 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4362
ae99258f 4363 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4364 reg_val &= 0x8cffffff;
4365 reg_val = 0x8c000000;
ae99258f 4366 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4367
ae99258f 4368 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4369 reg_val &= 0xffffff00;
ae99258f 4370 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4371
ae99258f 4372 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4373 reg_val &= 0x00ffffff;
4374 reg_val |= 0xb0000000;
ae99258f 4375 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4376}
4377
b551842d
DV		 4378static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4379 struct intel_link_m_n *m_n)
4380{
4381 struct drm_device *dev = crtc->base.dev;
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 int pipe = crtc->pipe;
4384
e3b95f1e
DV		 4385 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4386 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4387 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4388 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4389}
4390
4391static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4392 struct intel_link_m_n *m_n)
4393{
4394 struct drm_device *dev = crtc->base.dev;
4395 struct drm_i915_private *dev_priv = dev->dev_private;
4396 int pipe = crtc->pipe;
4397 enum transcoder transcoder = crtc->config.cpu_transcoder;
4398
4399 if (INTEL_INFO(dev)->gen >= 5) {
4400 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4401 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4402 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4403 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4404 } else {
e3b95f1e
DV		 4405 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4406 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4407 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4408 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4409 }
4410}
4411
03afc4a2
DV		 4412static void intel_dp_set_m_n(struct intel_crtc *crtc)
4413{
4414 if (crtc->config.has_pch_encoder)
4415 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4416 else
4417 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4418}
4419
f47709a9 4420static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4421{
f47709a9 4422 struct drm_device *dev = crtc->base.dev;
a0c4da24 4423 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4424 int pipe = crtc->pipe;
89b667f8 4425 u32 dpll, mdiv;
a0c4da24 4426 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4427 u32 coreclk, reg_val, dpll_md;
a0c4da24 4428
09153000
DV		 4429 mutex_lock(&dev_priv->dpio_lock);
4430
f47709a9
DV		 4431 bestn = crtc->config.dpll.n;
4432 bestm1 = crtc->config.dpll.m1;
4433 bestm2 = crtc->config.dpll.m2;
4434 bestp1 = crtc->config.dpll.p1;
4435 bestp2 = crtc->config.dpll.p2;
a0c4da24 4436
89b667f8
JB		 4437 /* See eDP HDMI DPIO driver vbios notes doc */
4438
4439 /* PLL B needs special handling */
4440 if (pipe)
4441 vlv_pllb_recal_opamp(dev_priv);
4442
4443 /* Set up Tx target for periodic Rcomp update */
ae99258f 4444 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4445
4446 /* Disable target IRef on PLL */
ae99258f 4447 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4448 reg_val &= 0x00ffffff;
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4450
4451 /* Disable fast lock */
ae99258f 4452 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4453
4454 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4455 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4456 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4457 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4458 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4459
4460 /*
4461 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4462 * but we don't support that).
4463 * Note: don't use the DAC post divider as it seems unstable.
4464 */
4465 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4466 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4467
a0c4da24 4468 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4469 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4470
89b667f8 4471 /* Set HBR and RBR LPF coefficients */
ff9a6750 4472 if (crtc->config.port_clock == 162000 ||
99750bd4 4473 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4474 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4475 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4476 0x009f0003);
89b667f8 4477 else
4abb2c39 4478 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4479 0x00d0000f);
4480
4481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4482 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4483 /* Use SSC source */
4484 if (!pipe)
ae99258f 4485 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4486 0x0df40000);
4487 else
ae99258f 4488 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4489 0x0df70000);
4490 } else { /* HDMI or VGA */
4491 /* Use bend source */
4492 if (!pipe)
ae99258f 4493 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4494 0x0df70000);
4495 else
ae99258f 4496 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4497 0x0df40000);
4498 }
a0c4da24 4499
ae99258f 4500 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4501 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4502 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4503 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4504 coreclk |= 0x01000000;
ae99258f 4505 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4506
ae99258f 4507 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4508
89b667f8
JB		 4509 /* Enable DPIO clock input */
4510 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4511 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4512 if (pipe)
4513 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4514
4515 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4516 crtc->config.dpll_hw_state.dpll = dpll;
4517
ef1b460d
DV		 4518 dpll_md = (crtc->config.pixel_multiplier - 1)
4519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4520 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4521
89b667f8
JB		 4522 if (crtc->config.has_dp_encoder)
4523 intel_dp_set_m_n(crtc);
09153000
DV		 4524
4525 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4526}
4527
f47709a9
DV		 4528static void i9xx_update_pll(struct intel_crtc *crtc,
4529 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4530 int num_connectors)
4531{
f47709a9 4532 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4533 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4534 u32 dpll;
4535 bool is_sdvo;
f47709a9 4536 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4537
f47709a9 4538 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4539
f47709a9
DV		 4540 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4541 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4542
4543 dpll = DPLL_VGA_MODE_DIS;
4544
f47709a9 4545 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4546 dpll |= DPLLB_MODE_LVDS;
4547 else
4548 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4549
ef1b460d 4550 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4551 dpll |= (crtc->config.pixel_multiplier - 1)
4552 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4553 }
198a037f
DV		 4554
4555 if (is_sdvo)
4a33e48d 4556 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4557
f47709a9 4558 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4559 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4560
4561 /* compute bitmask from p1 value */
4562 if (IS_PINEVIEW(dev))
4563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4564 else {
4565 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4566 if (IS_G4X(dev) && reduced_clock)
4567 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4568 }
4569 switch (clock->p2) {
4570 case 5:
4571 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4572 break;
4573 case 7:
4574 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4575 break;
4576 case 10:
4577 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4578 break;
4579 case 14:
4580 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4581 break;
4582 }
4583 if (INTEL_INFO(dev)->gen >= 4)
4584 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4585
09ede541 4586 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4587 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4588 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4591 else
4592 dpll |= PLL_REF_INPUT_DREFCLK;
4593
4594 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4595 crtc->config.dpll_hw_state.dpll = dpll;
4596
eb1cbe48 4597 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4598 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4599 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4600 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4601 }
66e3d5c0
DV		 4602
4603 if (crtc->config.has_dp_encoder)
4604 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4605}
4606
f47709a9 4607static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4608 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4609 int num_connectors)
4610{
f47709a9 4611 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4612 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4613 u32 dpll;
f47709a9 4614 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4615
f47709a9 4616 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4617
eb1cbe48
DV		 4618 dpll = DPLL_VGA_MODE_DIS;
4619
f47709a9 4620 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4621 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4622 } else {
4623 if (clock->p1 == 2)
4624 dpll |= PLL_P1_DIVIDE_BY_TWO;
4625 else
4626 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4627 if (clock->p2 == 4)
4628 dpll |= PLL_P2_DIVIDE_BY_4;
4629 }
4630
4a33e48d
DV		 4631 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4632 dpll |= DPLL_DVO_2X_MODE;
4633
f47709a9 4634 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4635 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4636 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4637 else
4638 dpll |= PLL_REF_INPUT_DREFCLK;
4639
4640 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4641 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4642}
4643
8a654f3b 4644static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4645{
4646 struct drm_device *dev = intel_crtc->base.dev;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4649 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4650 struct drm_display_mode *adjusted_mode =
4651 &intel_crtc->config.adjusted_mode;
4652 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4653 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4654
4655 /* We need to be careful not to changed the adjusted mode, for otherwise
4656 * the hw state checker will get angry at the mismatch. */
4657 crtc_vtotal = adjusted_mode->crtc_vtotal;
4658 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4659
4660 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4661 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4662 crtc_vtotal -= 1;
4663 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4664 vsyncshift = adjusted_mode->crtc_hsync_start
4665 - adjusted_mode->crtc_htotal / 2;
4666 } else {
4667 vsyncshift = 0;
4668 }
4669
4670 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4671 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4672
fe2b8f9d 4673 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4674 (adjusted_mode->crtc_hdisplay - 1) |
4675 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4676 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4677 (adjusted_mode->crtc_hblank_start - 1) |
4678 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4679 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4680 (adjusted_mode->crtc_hsync_start - 1) |
4681 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4682
fe2b8f9d 4683 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4684 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4685 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4686 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4687 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4688 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4689 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4690 (adjusted_mode->crtc_vsync_start - 1) |
4691 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4692
b5e508d4
PZ		 4693 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4694 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4695 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4696 * bits. */
4697 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4698 (pipe == PIPE_B || pipe == PIPE_C))
4699 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4700
b0e77b9c
PZ		 4701 /* pipesrc controls the size that is scaled from, which should
4702 * always be the user's requested size.
4703 */
4704 I915_WRITE(PIPESRC(pipe),
4705 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4706}
4707
1bd1bd80
DV		 4708static void intel_get_pipe_timings(struct intel_crtc *crtc,
4709 struct intel_crtc_config *pipe_config)
4710{
4711 struct drm_device *dev = crtc->base.dev;
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4714 uint32_t tmp;
4715
4716 tmp = I915_READ(HTOTAL(cpu_transcoder));
4717 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4718 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4719 tmp = I915_READ(HBLANK(cpu_transcoder));
4720 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4721 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4722 tmp = I915_READ(HSYNC(cpu_transcoder));
4723 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4724 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4725
4726 tmp = I915_READ(VTOTAL(cpu_transcoder));
4727 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4728 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4729 tmp = I915_READ(VBLANK(cpu_transcoder));
4730 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4731 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4732 tmp = I915_READ(VSYNC(cpu_transcoder));
4733 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4734 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4735
4736 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4737 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4738 pipe_config->adjusted_mode.crtc_vtotal += 1;
4739 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4740 }
4741
4742 tmp = I915_READ(PIPESRC(crtc->pipe));
4743 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4744 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4745}
4746
babea61d
JB		 4747static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4748 struct intel_crtc_config *pipe_config)
4749{
4750 struct drm_crtc *crtc = &intel_crtc->base;
4751
4752 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4753 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4754 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4755 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4756
4757 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4758 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4759 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4760 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4761
4762 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4763
4764 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4765 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4766}
4767
84b046f3
DV		 4768static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4769{
4770 struct drm_device *dev = intel_crtc->base.dev;
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4772 uint32_t pipeconf;
4773
9f11a9e4 4774 pipeconf = 0;
84b046f3
DV		 4775
4776 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4777 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4778 * core speed.
4779 *
4780 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4781 * pipe == 0 check?
4782 */
4783 if (intel_crtc->config.requested_mode.clock >
4784 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4785 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4786 }
4787
ff9ce46e
DV		 4788 /* only g4x and later have fancy bpc/dither controls */
4789 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4790 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4791 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4792 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4793 PIPECONF_DITHER_TYPE_SP;
84b046f3 4794
ff9ce46e
DV		 4795 switch (intel_crtc->config.pipe_bpp) {
4796 case 18:
4797 pipeconf |= PIPECONF_6BPC;
4798 break;
4799 case 24:
4800 pipeconf |= PIPECONF_8BPC;
4801 break;
4802 case 30:
4803 pipeconf |= PIPECONF_10BPC;
4804 break;
4805 default:
4806 /* Case prevented by intel_choose_pipe_bpp_dither. */
4807 BUG();
84b046f3
DV		 4808 }
4809 }
4810
4811 if (HAS_PIPE_CXSR(dev)) {
4812 if (intel_crtc->lowfreq_avail) {
4813 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4814 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4815 } else {
4816 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4817 }
4818 }
4819
84b046f3
DV		 4820 if (!IS_GEN2(dev) &&
4821 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4822 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4823 else
4824 pipeconf |= PIPECONF_PROGRESSIVE;
4825
9f11a9e4
DV		 4826 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4827 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4828
84b046f3
DV		 4829 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4830 POSTING_READ(PIPECONF(intel_crtc->pipe));
4831}
4832
f564048e 4833static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4834 int x, int y,
94352cf9 4835 struct drm_framebuffer *fb)
79e53945
JB		 4836{
4837 struct drm_device *dev = crtc->dev;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4840 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4841 int pipe = intel_crtc->pipe;
80824003 4842 int plane = intel_crtc->plane;
c751ce4f 4843 int refclk, num_connectors = 0;
652c393a 4844 intel_clock_t clock, reduced_clock;
84b046f3 4845 u32 dspcntr;
a16af721
DV		 4846 bool ok, has_reduced_clock = false;
4847 bool is_lvds = false;
5eddb70b 4848 struct intel_encoder *encoder;
d4906093 4849 const intel_limit_t *limit;
5c3b82e2 4850 int ret;
79e53945 4851
6c2b7c12 4852 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4853 switch (encoder->type) {
79e53945
JB		 4854 case INTEL_OUTPUT_LVDS:
4855 is_lvds = true;
4856 break;
79e53945 4857 }
43565a06 4858
c751ce4f 4859 num_connectors++;
79e53945
JB		 4860 }
4861
c65d77d8 4862 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4863
d4906093
ML		 4864 /*
4865 * Returns a set of divisors for the desired target clock with the given
4866 * refclk, or FALSE. The returned values represent the clock equation:
4867 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4868 */
1b894b59 4869 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4870 ok = dev_priv->display.find_dpll(limit, crtc,
4871 intel_crtc->config.port_clock,
ee9300bb
DV		 4872 refclk, NULL, &clock);
4873 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4874 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4875 return -EINVAL;
79e53945
JB		 4876 }
4877
cda4b7d3 4878 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4879 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4880
ddc9003c 4881 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4882 /*
4883 * Ensure we match the reduced clock's P to the target clock.
4884 * If the clocks don't match, we can't switch the display clock
4885 * by using the FP0/FP1. In such case we will disable the LVDS
4886 * downclock feature.
4887 */
ee9300bb
DV		 4888 has_reduced_clock =
4889 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4890 dev_priv->lvds_downclock,
ee9300bb 4891 refclk, &clock,
5eddb70b 4892 &reduced_clock);
7026d4ac 4893 }
f47709a9
DV		 4894 /* Compat-code for transition, will disappear. */
4895 if (!intel_crtc->config.clock_set) {
4896 intel_crtc->config.dpll.n = clock.n;
4897 intel_crtc->config.dpll.m1 = clock.m1;
4898 intel_crtc->config.dpll.m2 = clock.m2;
4899 intel_crtc->config.dpll.p1 = clock.p1;
4900 intel_crtc->config.dpll.p2 = clock.p2;
4901 }
7026d4ac 4902
eb1cbe48 4903 if (IS_GEN2(dev))
8a654f3b 4904 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4905 has_reduced_clock ? &reduced_clock : NULL,
4906 num_connectors);
a0c4da24 4907 else if (IS_VALLEYVIEW(dev))
f47709a9 4908 vlv_update_pll(intel_crtc);
79e53945 4909 else
f47709a9 4910 i9xx_update_pll(intel_crtc,
eb1cbe48 4911 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4912 num_connectors);
79e53945 4913
79e53945
JB		 4914 /* Set up the display plane register */
4915 dspcntr = DISPPLANE_GAMMA_ENABLE;
4916
da6ecc5d
JB		 4917 if (!IS_VALLEYVIEW(dev)) {
4918 if (pipe == 0)
4919 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4920 else
4921 dspcntr |= DISPPLANE_SEL_PIPE_B;
4922 }
79e53945 4923
8a654f3b 4924 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4925
4926 /* pipesrc and dspsize control the size that is scaled from,
4927 * which should always be the user's requested size.
79e53945 4928 */
929c77fb
EA		 4929 I915_WRITE(DSPSIZE(plane),
4930 ((mode->vdisplay - 1) << 16) |
4931 (mode->hdisplay - 1));
4932 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4933
84b046f3
DV		 4934 i9xx_set_pipeconf(intel_crtc);
4935
f564048e
EA		 4936 I915_WRITE(DSPCNTR(plane), dspcntr);
4937 POSTING_READ(DSPCNTR(plane));
4938
94352cf9 4939 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4940
4941 intel_update_watermarks(dev);
4942
f564048e
EA		 4943 return ret;
4944}
4945
2fa2fe9a
DV		 4946static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4947 struct intel_crtc_config *pipe_config)
4948{
4949 struct drm_device *dev = crtc->base.dev;
4950 struct drm_i915_private *dev_priv = dev->dev_private;
4951 uint32_t tmp;
4952
4953 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4954 if (!(tmp & PFIT_ENABLE))
4955 return;
2fa2fe9a 4956
06922821 4957 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4958 if (INTEL_INFO(dev)->gen < 4) {
4959 if (crtc->pipe != PIPE_B)
4960 return;
2fa2fe9a
DV		 4961 } else {
4962 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4963 return;
4964 }
4965
06922821 4966 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 4967 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4968 if (INTEL_INFO(dev)->gen < 5)
4969 pipe_config->gmch_pfit.lvds_border_bits =
4970 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4971}
4972
0e8ffe1b
DV		 4973static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4974 struct intel_crtc_config *pipe_config)
4975{
4976 struct drm_device *dev = crtc->base.dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 uint32_t tmp;
4979
e143a21c 4980 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4981 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4982
0e8ffe1b
DV		 4983 tmp = I915_READ(PIPECONF(crtc->pipe));
4984 if (!(tmp & PIPECONF_ENABLE))
4985 return false;
4986
1bd1bd80
DV		 4987 intel_get_pipe_timings(crtc, pipe_config);
4988
2fa2fe9a
DV		 4989 i9xx_get_pfit_config(crtc, pipe_config);
4990
6c49f241
DV		 4991 if (INTEL_INFO(dev)->gen >= 4) {
4992 tmp = I915_READ(DPLL_MD(crtc->pipe));
4993 pipe_config->pixel_multiplier =
4994 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4995 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4996 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4997 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4998 tmp = I915_READ(DPLL(crtc->pipe));
4999 pipe_config->pixel_multiplier =
5000 ((tmp & SDVO_MULTIPLIER_MASK)
5001 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5002 } else {
5003 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5004 * port and will be fixed up in the encoder->get_config
5005 * function. */
5006 pipe_config->pixel_multiplier = 1;
5007 }
8bcc2795
DV		 5008 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5009 if (!IS_VALLEYVIEW(dev)) {
5010 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5011 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5012 } else {
5013 /* Mask out read-only status bits. */
5014 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5015 DPLL_PORTC_READY_MASK |
5016 DPLL_PORTB_READY_MASK);
8bcc2795 5017 }
6c49f241 5018
0e8ffe1b
DV		 5019 return true;
5020}
5021
dde86e2d 5022static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5023{
5024 struct drm_i915_private *dev_priv = dev->dev_private;
5025 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5026 struct intel_encoder *encoder;
74cfd7ac 5027 u32 val, final;
13d83a67 5028 bool has_lvds = false;
199e5d79 5029 bool has_cpu_edp = false;
199e5d79 5030 bool has_panel = false;
99eb6a01
KP		 5031 bool has_ck505 = false;
5032 bool can_ssc = false;
13d83a67
JB		 5033
5034 /* We need to take the global config into account */
199e5d79
KP		 5035 list_for_each_entry(encoder, &mode_config->encoder_list,
5036 base.head) {
5037 switch (encoder->type) {
5038 case INTEL_OUTPUT_LVDS:
5039 has_panel = true;
5040 has_lvds = true;
5041 break;
5042 case INTEL_OUTPUT_EDP:
5043 has_panel = true;
2de6905f 5044 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5045 has_cpu_edp = true;
5046 break;
13d83a67
JB		 5047 }
5048 }
5049
99eb6a01 5050 if (HAS_PCH_IBX(dev)) {
41aa3448 5051 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5052 can_ssc = has_ck505;
5053 } else {
5054 has_ck505 = false;
5055 can_ssc = true;
5056 }
5057
2de6905f
ID		 5058 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5059 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5060
5061 /* Ironlake: try to setup display ref clock before DPLL
5062 * enabling. This is only under driver's control after
5063 * PCH B stepping, previous chipset stepping should be
5064 * ignoring this setting.
5065 */
74cfd7ac
CW		 5066 val = I915_READ(PCH_DREF_CONTROL);
5067
5068 /* As we must carefully and slowly disable/enable each source in turn,
5069 * compute the final state we want first and check if we need to
5070 * make any changes at all.
5071 */
5072 final = val;
5073 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5074 if (has_ck505)
5075 final |= DREF_NONSPREAD_CK505_ENABLE;
5076 else
5077 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5078
5079 final &= ~DREF_SSC_SOURCE_MASK;
5080 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5081 final &= ~DREF_SSC1_ENABLE;
5082
5083 if (has_panel) {
5084 final |= DREF_SSC_SOURCE_ENABLE;
5085
5086 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5087 final |= DREF_SSC1_ENABLE;
5088
5089 if (has_cpu_edp) {
5090 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5091 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5092 else
5093 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5094 } else
5095 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5096 } else {
5097 final |= DREF_SSC_SOURCE_DISABLE;
5098 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5099 }
5100
5101 if (final == val)
5102 return;
5103
13d83a67 5104 /* Always enable nonspread source */
74cfd7ac 5105 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5106
99eb6a01 5107 if (has_ck505)
74cfd7ac 5108 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5109 else
74cfd7ac 5110 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5111
199e5d79 5112 if (has_panel) {
74cfd7ac
CW		 5113 val &= ~DREF_SSC_SOURCE_MASK;
5114 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5115
199e5d79 5116 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5117 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5118 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5119 val |= DREF_SSC1_ENABLE;
e77166b5 5120 } else
74cfd7ac 5121 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5122
5123 /* Get SSC going before enabling the outputs */
74cfd7ac 5124 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5125 POSTING_READ(PCH_DREF_CONTROL);
5126 udelay(200);
5127
74cfd7ac 5128 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5129
5130 /* Enable CPU source on CPU attached eDP */
199e5d79 5131 if (has_cpu_edp) {
99eb6a01 5132 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5133 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5134 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5135 }
13d83a67 5136 else
74cfd7ac 5137 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5138 } else
74cfd7ac 5139 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5140
74cfd7ac 5141 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5142 POSTING_READ(PCH_DREF_CONTROL);
5143 udelay(200);
5144 } else {
5145 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5146
74cfd7ac 5147 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5148
5149 /* Turn off CPU output */
74cfd7ac 5150 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5151
74cfd7ac 5152 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5153 POSTING_READ(PCH_DREF_CONTROL);
5154 udelay(200);
5155
5156 /* Turn off the SSC source */
74cfd7ac
CW		 5157 val &= ~DREF_SSC_SOURCE_MASK;
5158 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5159
5160 /* Turn off SSC1 */
74cfd7ac 5161 val &= ~DREF_SSC1_ENABLE;
199e5d79 5162
74cfd7ac 5163 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5164 POSTING_READ(PCH_DREF_CONTROL);
5165 udelay(200);
5166 }
74cfd7ac
CW		 5167
5168 BUG_ON(val != final);
13d83a67
JB		 5169}
5170
f31f2d55 5171static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5172{
f31f2d55 5173 uint32_t tmp;
dde86e2d 5174
0ff066a9
PZ		 5175 tmp = I915_READ(SOUTH_CHICKEN2);
5176 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5177 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5178
0ff066a9
PZ		 5179 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5180 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5181 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5182
0ff066a9
PZ		 5183 tmp = I915_READ(SOUTH_CHICKEN2);
5184 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5185 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5186
0ff066a9
PZ		 5187 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5188 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5189 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5190}
5191
5192/* WaMPhyProgramming:hsw */
5193static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5194{
5195 uint32_t tmp;
dde86e2d
PZ		 5196
5197 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5198 tmp &= ~(0xFF << 24);
5199 tmp |= (0x12 << 24);
5200 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5201
dde86e2d
PZ		 5202 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5203 tmp |= (1 << 11);
5204 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5205
5206 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5207 tmp |= (1 << 11);
5208 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5209
dde86e2d
PZ		 5210 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5211 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5212 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5213
5214 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5215 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5216 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5217
0ff066a9
PZ		 5218 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5219 tmp &= ~(7 << 13);
5220 tmp |= (5 << 13);
5221 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5222
0ff066a9
PZ		 5223 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5224 tmp &= ~(7 << 13);
5225 tmp |= (5 << 13);
5226 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5227
5228 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5229 tmp &= ~0xFF;
5230 tmp |= 0x1C;
5231 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5234 tmp &= ~0xFF;
5235 tmp |= 0x1C;
5236 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5237
5238 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5239 tmp &= ~(0xFF << 16);
5240 tmp |= (0x1C << 16);
5241 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5242
5243 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5244 tmp &= ~(0xFF << 16);
5245 tmp |= (0x1C << 16);
5246 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5247
0ff066a9
PZ		 5248 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5249 tmp |= (1 << 27);
5250 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5251
0ff066a9
PZ		 5252 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5253 tmp |= (1 << 27);
5254 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5255
0ff066a9
PZ		 5256 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5257 tmp &= ~(0xF << 28);
5258 tmp |= (4 << 28);
5259 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5260
0ff066a9
PZ		 5261 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5262 tmp &= ~(0xF << 28);
5263 tmp |= (4 << 28);
5264 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5265}
5266
2fa86a1f
PZ		 5267/* Implements 3 different sequences from BSpec chapter "Display iCLK
5268 * Programming" based on the parameters passed:
5269 * - Sequence to enable CLKOUT_DP
5270 * - Sequence to enable CLKOUT_DP without spread
5271 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5272 */
5273static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5274 bool with_fdi)
f31f2d55
PZ		 5275{
5276 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5277 uint32_t reg, tmp;
5278
5279 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5280 with_spread = true;
5281 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5282 with_fdi, "LP PCH doesn't have FDI\n"))
5283 with_fdi = false;
f31f2d55
PZ		 5284
5285 mutex_lock(&dev_priv->dpio_lock);
5286
5287 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5288 tmp &= ~SBI_SSCCTL_DISABLE;
5289 tmp |= SBI_SSCCTL_PATHALT;
5290 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5291
5292 udelay(24);
5293
2fa86a1f
PZ		 5294 if (with_spread) {
5295 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5296 tmp &= ~SBI_SSCCTL_PATHALT;
5297 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5298
2fa86a1f
PZ		 5299 if (with_fdi) {
5300 lpt_reset_fdi_mphy(dev_priv);
5301 lpt_program_fdi_mphy(dev_priv);
5302 }
5303 }
dde86e2d 5304
2fa86a1f
PZ		 5305 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5306 SBI_GEN0 : SBI_DBUFF0;
5307 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5308 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5309 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5310
5311 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5312}
5313
47701c3b
PZ		 5314/* Sequence to disable CLKOUT_DP */
5315static void lpt_disable_clkout_dp(struct drm_device *dev)
5316{
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318 uint32_t reg, tmp;
5319
5320 mutex_lock(&dev_priv->dpio_lock);
5321
5322 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5323 SBI_GEN0 : SBI_DBUFF0;
5324 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5325 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5326 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5327
5328 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5329 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5330 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5331 tmp |= SBI_SSCCTL_PATHALT;
5332 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5333 udelay(32);
5334 }
5335 tmp |= SBI_SSCCTL_DISABLE;
5336 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5337 }
5338
5339 mutex_unlock(&dev_priv->dpio_lock);
5340}
5341
bf8fa3d3
PZ		 5342static void lpt_init_pch_refclk(struct drm_device *dev)
5343{
5344 struct drm_mode_config *mode_config = &dev->mode_config;
5345 struct intel_encoder *encoder;
5346 bool has_vga = false;
5347
5348 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5349 switch (encoder->type) {
5350 case INTEL_OUTPUT_ANALOG:
5351 has_vga = true;
5352 break;
5353 }
5354 }
5355
47701c3b
PZ		 5356 if (has_vga)
5357 lpt_enable_clkout_dp(dev, true, true);
5358 else
5359 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5360}
5361
dde86e2d
PZ		 5362/*
5363 * Initialize reference clocks when the driver loads
5364 */
5365void intel_init_pch_refclk(struct drm_device *dev)
5366{
5367 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5368 ironlake_init_pch_refclk(dev);
5369 else if (HAS_PCH_LPT(dev))
5370 lpt_init_pch_refclk(dev);
5371}
5372
d9d444cb
JB		 5373static int ironlake_get_refclk(struct drm_crtc *crtc)
5374{
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_encoder *encoder;
d9d444cb
JB		 5378 int num_connectors = 0;
5379 bool is_lvds = false;
5380
6c2b7c12 5381 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5382 switch (encoder->type) {
5383 case INTEL_OUTPUT_LVDS:
5384 is_lvds = true;
5385 break;
d9d444cb
JB		 5386 }
5387 num_connectors++;
5388 }
5389
5390 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5391 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5392 dev_priv->vbt.lvds_ssc_freq);
5393 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5394 }
5395
5396 return 120000;
5397}
5398
6ff93609 5399static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5400{
c8203565 5401 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5403 int pipe = intel_crtc->pipe;
c8203565
PZ		 5404 uint32_t val;
5405
78114071 5406 val = 0;
c8203565 5407
965e0c48 5408 switch (intel_crtc->config.pipe_bpp) {
c8203565 5409 case 18:
dfd07d72 5410 val |= PIPECONF_6BPC;
c8203565
PZ		 5411 break;
5412 case 24:
dfd07d72 5413 val |= PIPECONF_8BPC;
c8203565
PZ		 5414 break;
5415 case 30:
dfd07d72 5416 val |= PIPECONF_10BPC;
c8203565
PZ		 5417 break;
5418 case 36:
dfd07d72 5419 val |= PIPECONF_12BPC;
c8203565
PZ		 5420 break;
5421 default:
cc769b62
PZ		 5422 /* Case prevented by intel_choose_pipe_bpp_dither. */
5423 BUG();
c8203565
PZ		 5424 }
5425
d8b32247 5426 if (intel_crtc->config.dither)
c8203565
PZ		 5427 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5428
6ff93609 5429 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5430 val |= PIPECONF_INTERLACED_ILK;
5431 else
5432 val |= PIPECONF_PROGRESSIVE;
5433
50f3b016 5434 if (intel_crtc->config.limited_color_range)
3685a8f3 5435 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5436
c8203565
PZ		 5437 I915_WRITE(PIPECONF(pipe), val);
5438 POSTING_READ(PIPECONF(pipe));
5439}
5440
86d3efce
VS		 5441/*
5442 * Set up the pipe CSC unit.
5443 *
5444 * Currently only full range RGB to limited range RGB conversion
5445 * is supported, but eventually this should handle various
5446 * RGB<->YCbCr scenarios as well.
5447 */
50f3b016 5448static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5449{
5450 struct drm_device *dev = crtc->dev;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453 int pipe = intel_crtc->pipe;
5454 uint16_t coeff = 0x7800; /* 1.0 */
5455
5456 /*
5457 * TODO: Check what kind of values actually come out of the pipe
5458 * with these coeff/postoff values and adjust to get the best
5459 * accuracy. Perhaps we even need to take the bpc value into
5460 * consideration.
5461 */
5462
50f3b016 5463 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5464 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5465
5466 /*
5467 * GY/GU and RY/RU should be the other way around according
5468 * to BSpec, but reality doesn't agree. Just set them up in
5469 * a way that results in the correct picture.
5470 */
5471 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5472 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5473
5474 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5475 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5476
5477 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5478 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5479
5480 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5481 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5482 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5483
5484 if (INTEL_INFO(dev)->gen > 6) {
5485 uint16_t postoff = 0;
5486
50f3b016 5487 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5488 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5489
5490 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5491 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5492 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5493
5494 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5495 } else {
5496 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5497
50f3b016 5498 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5499 mode |= CSC_BLACK_SCREEN_OFFSET;
5500
5501 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5502 }
5503}
5504
6ff93609 5505static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5506{
5507 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5509 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5510 uint32_t val;
5511
3eff4faa 5512 val = 0;
ee2b0b38 5513
d8b32247 5514 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5515 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5516
6ff93609 5517 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5518 val |= PIPECONF_INTERLACED_ILK;
5519 else
5520 val |= PIPECONF_PROGRESSIVE;
5521
702e7a56
PZ		 5522 I915_WRITE(PIPECONF(cpu_transcoder), val);
5523 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5524
5525 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5526 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5527}
5528
6591c6e4 5529static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5530 intel_clock_t *clock,
5531 bool *has_reduced_clock,
5532 intel_clock_t *reduced_clock)
5533{
5534 struct drm_device *dev = crtc->dev;
5535 struct drm_i915_private *dev_priv = dev->dev_private;
5536 struct intel_encoder *intel_encoder;
5537 int refclk;
d4906093 5538 const intel_limit_t *limit;
a16af721 5539 bool ret, is_lvds = false;
79e53945 5540
6591c6e4
PZ		 5541 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5542 switch (intel_encoder->type) {
79e53945
JB		 5543 case INTEL_OUTPUT_LVDS:
5544 is_lvds = true;
5545 break;
79e53945
JB		 5546 }
5547 }
5548
d9d444cb 5549 refclk = ironlake_get_refclk(crtc);
79e53945 5550
d4906093
ML		 5551 /*
5552 * Returns a set of divisors for the desired target clock with the given
5553 * refclk, or FALSE. The returned values represent the clock equation:
5554 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5555 */
1b894b59 5556 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5557 ret = dev_priv->display.find_dpll(limit, crtc,
5558 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5559 refclk, NULL, clock);
6591c6e4
PZ		 5560 if (!ret)
5561 return false;
cda4b7d3 5562
ddc9003c 5563 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5564 /*
5565 * Ensure we match the reduced clock's P to the target clock.
5566 * If the clocks don't match, we can't switch the display clock
5567 * by using the FP0/FP1. In such case we will disable the LVDS
5568 * downclock feature.
5569 */
ee9300bb
DV		 5570 *has_reduced_clock =
5571 dev_priv->display.find_dpll(limit, crtc,
5572 dev_priv->lvds_downclock,
5573 refclk, clock,
5574 reduced_clock);
652c393a 5575 }
61e9653f 5576
6591c6e4
PZ		 5577 return true;
5578}
5579
01a415fd
DV		 5580static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5581{
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5583 uint32_t temp;
5584
5585 temp = I915_READ(SOUTH_CHICKEN1);
5586 if (temp & FDI_BC_BIFURCATION_SELECT)
5587 return;
5588
5589 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5590 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5591
5592 temp |= FDI_BC_BIFURCATION_SELECT;
5593 DRM_DEBUG_KMS("enabling fdi C rx\n");
5594 I915_WRITE(SOUTH_CHICKEN1, temp);
5595 POSTING_READ(SOUTH_CHICKEN1);
5596}
5597
ebfd86fd 5598static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5599{
5600 struct drm_device *dev = intel_crtc->base.dev;
5601 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5602
5603 switch (intel_crtc->pipe) {
5604 case PIPE_A:
ebfd86fd 5605 break;
01a415fd 5606 case PIPE_B:
ebfd86fd 5607 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5608 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5609 else
5610 cpt_enable_fdi_bc_bifurcation(dev);
5611
ebfd86fd 5612 break;
01a415fd 5613 case PIPE_C:
01a415fd
DV		 5614 cpt_enable_fdi_bc_bifurcation(dev);
5615
ebfd86fd 5616 break;
01a415fd
DV		 5617 default:
5618 BUG();
5619 }
5620}
5621
d4b1931c
PZ		 5622int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5623{
5624 /*
5625 * Account for spread spectrum to avoid
5626 * oversubscribing the link. Max center spread
5627 * is 2.5%; use 5% for safety's sake.
5628 */
5629 u32 bps = target_clock * bpp * 21 / 20;
5630 return bps / (link_bw * 8) + 1;
5631}
5632
7429e9d4 5633static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5634{
7429e9d4 5635 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5636}
5637
de13a2e3 5638static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5639 u32 *fp,
9a7c7890 5640 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5641{
de13a2e3 5642 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5643 struct drm_device *dev = crtc->dev;
5644 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5645 struct intel_encoder *intel_encoder;
5646 uint32_t dpll;
6cc5f341 5647 int factor, num_connectors = 0;
09ede541 5648 bool is_lvds = false, is_sdvo = false;
79e53945 5649
de13a2e3
PZ		 5650 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5651 switch (intel_encoder->type) {
79e53945
JB		 5652 case INTEL_OUTPUT_LVDS:
5653 is_lvds = true;
5654 break;
5655 case INTEL_OUTPUT_SDVO:
7d57382e 5656 case INTEL_OUTPUT_HDMI:
79e53945 5657 is_sdvo = true;
79e53945 5658 break;
79e53945 5659 }
43565a06 5660
c751ce4f 5661 num_connectors++;
79e53945 5662 }
79e53945 5663
c1858123 5664 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5665 factor = 21;
5666 if (is_lvds) {
5667 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5668 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5669 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5670 factor = 25;
09ede541 5671 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5672 factor = 20;
c1858123 5673
7429e9d4 5674 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5675 *fp |= FP_CB_TUNE;
2c07245f 5676
9a7c7890
DV		 5677 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5678 *fp2 |= FP_CB_TUNE;
5679
5eddb70b 5680 dpll = 0;
2c07245f 5681
a07d6787
EA		 5682 if (is_lvds)
5683 dpll |= DPLLB_MODE_LVDS;
5684 else
5685 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5686
ef1b460d
DV		 5687 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5688 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5689
5690 if (is_sdvo)
4a33e48d 5691 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5692 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5693 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5694
a07d6787 5695 /* compute bitmask from p1 value */
7429e9d4 5696 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5697 /* also FPA1 */
7429e9d4 5698 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5699
7429e9d4 5700 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5701 case 5:
5702 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5703 break;
5704 case 7:
5705 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5706 break;
5707 case 10:
5708 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5709 break;
5710 case 14:
5711 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5712 break;
79e53945
JB		 5713 }
5714
b4c09f3b 5715 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5716 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5717 else
5718 dpll |= PLL_REF_INPUT_DREFCLK;
5719
959e16d6 5720 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5721}
5722
5723static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5724 int x, int y,
5725 struct drm_framebuffer *fb)
5726{
5727 struct drm_device *dev = crtc->dev;
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5730 int pipe = intel_crtc->pipe;
5731 int plane = intel_crtc->plane;
5732 int num_connectors = 0;
5733 intel_clock_t clock, reduced_clock;
cbbab5bd 5734 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5735 bool ok, has_reduced_clock = false;
8b47047b 5736 bool is_lvds = false;
de13a2e3 5737 struct intel_encoder *encoder;
e2b78267 5738 struct intel_shared_dpll *pll;
de13a2e3 5739 int ret;
de13a2e3
PZ		 5740
5741 for_each_encoder_on_crtc(dev, crtc, encoder) {
5742 switch (encoder->type) {
5743 case INTEL_OUTPUT_LVDS:
5744 is_lvds = true;
5745 break;
de13a2e3
PZ		 5746 }
5747
5748 num_connectors++;
a07d6787 5749 }
79e53945 5750
5dc5298b
PZ		 5751 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5752 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5753
ff9a6750 5754 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5755 &has_reduced_clock, &reduced_clock);
ee9300bb 5756 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5757 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5758 return -EINVAL;
79e53945 5759 }
f47709a9
DV		 5760 /* Compat-code for transition, will disappear. */
5761 if (!intel_crtc->config.clock_set) {
5762 intel_crtc->config.dpll.n = clock.n;
5763 intel_crtc->config.dpll.m1 = clock.m1;
5764 intel_crtc->config.dpll.m2 = clock.m2;
5765 intel_crtc->config.dpll.p1 = clock.p1;
5766 intel_crtc->config.dpll.p2 = clock.p2;
5767 }
79e53945 5768
de13a2e3
PZ		 5769 /* Ensure that the cursor is valid for the new mode before changing... */
5770 intel_crtc_update_cursor(crtc, true);
5771
5dc5298b 5772 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5773 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5774 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5775 if (has_reduced_clock)
7429e9d4 5776 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5777
7429e9d4 5778 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5779 &fp, &reduced_clock,
5780 has_reduced_clock ? &fp2 : NULL);
5781
959e16d6 5782 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5783 intel_crtc->config.dpll_hw_state.fp0 = fp;
5784 if (has_reduced_clock)
5785 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5786 else
5787 intel_crtc->config.dpll_hw_state.fp1 = fp;
5788
b89a1d39 5789 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5790 if (pll == NULL) {
84f44ce7
VS		 5791 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5792 pipe_name(pipe));
4b645f14
JB		 5793 return -EINVAL;
5794 }
ee7b9f93 5795 } else
e72f9fbf 5796 intel_put_shared_dpll(intel_crtc);
79e53945 5797
03afc4a2
DV		 5798 if (intel_crtc->config.has_dp_encoder)
5799 intel_dp_set_m_n(intel_crtc);
79e53945 5800
bcd644e0
DV		 5801 if (is_lvds && has_reduced_clock && i915_powersave)
5802 intel_crtc->lowfreq_avail = true;
5803 else
5804 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5805
5806 if (intel_crtc->config.has_pch_encoder) {
5807 pll = intel_crtc_to_shared_dpll(intel_crtc);
5808
652c393a
JB		 5809 }
5810
8a654f3b 5811 intel_set_pipe_timings(intel_crtc);
5eddb70b 5812
ca3a0ff8 5813 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5814 intel_cpu_transcoder_set_m_n(intel_crtc,
5815 &intel_crtc->config.fdi_m_n);
5816 }
2c07245f 5817
ebfd86fd
DV		 5818 if (IS_IVYBRIDGE(dev))
5819 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5820
6ff93609 5821 ironlake_set_pipeconf(crtc);
79e53945 5822
a1f9e77e
PZ		 5823 /* Set up the display plane register */
5824 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5825 POSTING_READ(DSPCNTR(plane));
79e53945 5826
94352cf9 5827 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5828
5829 intel_update_watermarks(dev);
5830
1857e1da 5831 return ret;
79e53945
JB		 5832}
5833
72419203
DV		 5834static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5835 struct intel_crtc_config *pipe_config)
5836{
5837 struct drm_device *dev = crtc->base.dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 enum transcoder transcoder = pipe_config->cpu_transcoder;
5840
5841 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5842 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5843 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5844 & ~TU_SIZE_MASK;
5845 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5846 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5847 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5848}
5849
2fa2fe9a
DV		 5850static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5851 struct intel_crtc_config *pipe_config)
5852{
5853 struct drm_device *dev = crtc->base.dev;
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 uint32_t tmp;
5856
5857 tmp = I915_READ(PF_CTL(crtc->pipe));
5858
5859 if (tmp & PF_ENABLE) {
5860 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5861 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5862
5863 /* We currently do not free assignements of panel fitters on
5864 * ivb/hsw (since we don't use the higher upscaling modes which
5865 * differentiates them) so just WARN about this case for now. */
5866 if (IS_GEN7(dev)) {
5867 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5868 PF_PIPE_SEL_IVB(crtc->pipe));
5869 }
2fa2fe9a 5870 }
79e53945
JB		 5871}
5872
0e8ffe1b
DV		 5873static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5874 struct intel_crtc_config *pipe_config)
5875{
5876 struct drm_device *dev = crtc->base.dev;
5877 struct drm_i915_private *dev_priv = dev->dev_private;
5878 uint32_t tmp;
5879
e143a21c 5880 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5881 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5882
0e8ffe1b
DV		 5883 tmp = I915_READ(PIPECONF(crtc->pipe));
5884 if (!(tmp & PIPECONF_ENABLE))
5885 return false;
5886
ab9412ba 5887 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5888 struct intel_shared_dpll *pll;
5889
88adfff1
DV		 5890 pipe_config->has_pch_encoder = true;
5891
627eb5a3
DV		 5892 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5893 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5894 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5895
5896 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5897
c0d43d62 5898 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5899 pipe_config->shared_dpll =
5900 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5901 } else {
5902 tmp = I915_READ(PCH_DPLL_SEL);
5903 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5905 else
5906 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5907 }
66e985c0
DV		 5908
5909 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5910
5911 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5912 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5913
5914 tmp = pipe_config->dpll_hw_state.dpll;
5915 pipe_config->pixel_multiplier =
5916 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5917 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5918 } else {
5919 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5920 }
5921
1bd1bd80
DV		 5922 intel_get_pipe_timings(crtc, pipe_config);
5923
2fa2fe9a
DV		 5924 ironlake_get_pfit_config(crtc, pipe_config);
5925
0e8ffe1b
DV		 5926 return true;
5927}
5928
be256dc7
PZ		 5929static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5930{
5931 struct drm_device *dev = dev_priv->dev;
5932 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5933 struct intel_crtc *crtc;
5934 unsigned long irqflags;
bd633a7c 5935 uint32_t val;
be256dc7
PZ		 5936
5937 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5938 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5939 pipe_name(crtc->pipe));
5940
5941 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5942 WARN(plls->spll_refcount, "SPLL enabled\n");
5943 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5944 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5945 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5946 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5947 "CPU PWM1 enabled\n");
5948 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5949 "CPU PWM2 enabled\n");
5950 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5951 "PCH PWM1 enabled\n");
5952 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5953 "Utility pin enabled\n");
5954 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5955
5956 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5957 val = I915_READ(DEIMR);
5958 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5959 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5960 val = I915_READ(SDEIMR);
bd633a7c 5961 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 5962 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5963 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5964}
5965
5966/*
5967 * This function implements pieces of two sequences from BSpec:
5968 * - Sequence for display software to disable LCPLL
5969 * - Sequence for display software to allow package C8+
5970 * The steps implemented here are just the steps that actually touch the LCPLL
5971 * register. Callers should take care of disabling all the display engine
5972 * functions, doing the mode unset, fixing interrupts, etc.
5973 */
5974void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5975 bool switch_to_fclk, bool allow_power_down)
5976{
5977 uint32_t val;
5978
5979 assert_can_disable_lcpll(dev_priv);
5980
5981 val = I915_READ(LCPLL_CTL);
5982
5983 if (switch_to_fclk) {
5984 val |= LCPLL_CD_SOURCE_FCLK;
5985 I915_WRITE(LCPLL_CTL, val);
5986
5987 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5988 LCPLL_CD_SOURCE_FCLK_DONE, 1))
5989 DRM_ERROR("Switching to FCLK failed\n");
5990
5991 val = I915_READ(LCPLL_CTL);
5992 }
5993
5994 val |= LCPLL_PLL_DISABLE;
5995 I915_WRITE(LCPLL_CTL, val);
5996 POSTING_READ(LCPLL_CTL);
5997
5998 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
5999 DRM_ERROR("LCPLL still locked\n");
6000
6001 val = I915_READ(D_COMP);
6002 val |= D_COMP_COMP_DISABLE;
6003 I915_WRITE(D_COMP, val);
6004 POSTING_READ(D_COMP);
6005 ndelay(100);
6006
6007 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6008 DRM_ERROR("D_COMP RCOMP still in progress\n");
6009
6010 if (allow_power_down) {
6011 val = I915_READ(LCPLL_CTL);
6012 val |= LCPLL_POWER_DOWN_ALLOW;
6013 I915_WRITE(LCPLL_CTL, val);
6014 POSTING_READ(LCPLL_CTL);
6015 }
6016}
6017
6018/*
6019 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6020 * source.
6021 */
6022void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6023{
6024 uint32_t val;
6025
6026 val = I915_READ(LCPLL_CTL);
6027
6028 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6029 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6030 return;
6031
215733fa
PZ		 6032 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6033 * we'll hang the machine! */
6034 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6035
be256dc7
PZ		 6036 if (val & LCPLL_POWER_DOWN_ALLOW) {
6037 val &= ~LCPLL_POWER_DOWN_ALLOW;
6038 I915_WRITE(LCPLL_CTL, val);
6039 }
6040
6041 val = I915_READ(D_COMP);
6042 val |= D_COMP_COMP_FORCE;
6043 val &= ~D_COMP_COMP_DISABLE;
6044 I915_WRITE(D_COMP, val);
6045 I915_READ(D_COMP);
6046
6047 val = I915_READ(LCPLL_CTL);
6048 val &= ~LCPLL_PLL_DISABLE;
6049 I915_WRITE(LCPLL_CTL, val);
6050
6051 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6052 DRM_ERROR("LCPLL not locked yet\n");
6053
6054 if (val & LCPLL_CD_SOURCE_FCLK) {
6055 val = I915_READ(LCPLL_CTL);
6056 val &= ~LCPLL_CD_SOURCE_FCLK;
6057 I915_WRITE(LCPLL_CTL, val);
6058
6059 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6060 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6061 DRM_ERROR("Switching back to LCPLL failed\n");
6062 }
215733fa
PZ		 6063
6064 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6065}
6066
c67a470b
PZ		 6067void hsw_enable_pc8_work(struct work_struct *__work)
6068{
6069 struct drm_i915_private *dev_priv =
6070 container_of(to_delayed_work(__work), struct drm_i915_private,
6071 pc8.enable_work);
6072 struct drm_device *dev = dev_priv->dev;
6073 uint32_t val;
6074
6075 if (dev_priv->pc8.enabled)
6076 return;
6077
6078 DRM_DEBUG_KMS("Enabling package C8+\n");
6079
6080 dev_priv->pc8.enabled = true;
6081
6082 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6083 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6084 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6085 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6086 }
6087
6088 lpt_disable_clkout_dp(dev);
6089 hsw_pc8_disable_interrupts(dev);
6090 hsw_disable_lcpll(dev_priv, true, true);
6091}
6092
6093static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6094{
6095 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6096 WARN(dev_priv->pc8.disable_count < 1,
6097 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6098
6099 dev_priv->pc8.disable_count--;
6100 if (dev_priv->pc8.disable_count != 0)
6101 return;
6102
6103 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6104 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6105}
6106
6107static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6108{
6109 struct drm_device *dev = dev_priv->dev;
6110 uint32_t val;
6111
6112 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6113 WARN(dev_priv->pc8.disable_count < 0,
6114 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6115
6116 dev_priv->pc8.disable_count++;
6117 if (dev_priv->pc8.disable_count != 1)
6118 return;
6119
6120 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6121 if (!dev_priv->pc8.enabled)
6122 return;
6123
6124 DRM_DEBUG_KMS("Disabling package C8+\n");
6125
6126 hsw_restore_lcpll(dev_priv);
6127 hsw_pc8_restore_interrupts(dev);
6128 lpt_init_pch_refclk(dev);
6129
6130 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6131 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6132 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6133 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6134 }
6135
6136 intel_prepare_ddi(dev);
6137 i915_gem_init_swizzling(dev);
6138 mutex_lock(&dev_priv->rps.hw_lock);
6139 gen6_update_ring_freq(dev);
6140 mutex_unlock(&dev_priv->rps.hw_lock);
6141 dev_priv->pc8.enabled = false;
6142}
6143
6144void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6145{
6146 mutex_lock(&dev_priv->pc8.lock);
6147 __hsw_enable_package_c8(dev_priv);
6148 mutex_unlock(&dev_priv->pc8.lock);
6149}
6150
6151void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6152{
6153 mutex_lock(&dev_priv->pc8.lock);
6154 __hsw_disable_package_c8(dev_priv);
6155 mutex_unlock(&dev_priv->pc8.lock);
6156}
6157
6158static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6159{
6160 struct drm_device *dev = dev_priv->dev;
6161 struct intel_crtc *crtc;
6162 uint32_t val;
6163
6164 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6165 if (crtc->base.enabled)
6166 return false;
6167
6168 /* This case is still possible since we have the i915.disable_power_well
6169 * parameter and also the KVMr or something else might be requesting the
6170 * power well. */
6171 val = I915_READ(HSW_PWR_WELL_DRIVER);
6172 if (val != 0) {
6173 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6174 return false;
6175 }
6176
6177 return true;
6178}
6179
6180/* Since we're called from modeset_global_resources there's no way to
6181 * symmetrically increase and decrease the refcount, so we use
6182 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6183 * or not.
6184 */
6185static void hsw_update_package_c8(struct drm_device *dev)
6186{
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188 bool allow;
6189
6190 if (!i915_enable_pc8)
6191 return;
6192
6193 mutex_lock(&dev_priv->pc8.lock);
6194
6195 allow = hsw_can_enable_package_c8(dev_priv);
6196
6197 if (allow == dev_priv->pc8.requirements_met)
6198 goto done;
6199
6200 dev_priv->pc8.requirements_met = allow;
6201
6202 if (allow)
6203 __hsw_enable_package_c8(dev_priv);
6204 else
6205 __hsw_disable_package_c8(dev_priv);
6206
6207done:
6208 mutex_unlock(&dev_priv->pc8.lock);
6209}
6210
6211static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6212{
6213 if (!dev_priv->pc8.gpu_idle) {
6214 dev_priv->pc8.gpu_idle = true;
6215 hsw_enable_package_c8(dev_priv);
6216 }
6217}
6218
6219static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6220{
6221 if (dev_priv->pc8.gpu_idle) {
6222 dev_priv->pc8.gpu_idle = false;
6223 hsw_disable_package_c8(dev_priv);
6224 }
6225}
6226
d6dd9eb1
DV		 6227static void haswell_modeset_global_resources(struct drm_device *dev)
6228{
d6dd9eb1
DV		 6229 bool enable = false;
6230 struct intel_crtc *crtc;
d6dd9eb1
DV		 6231
6232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6233 if (!crtc->base.enabled)
6234 continue;
d6dd9eb1 6235
e7a639c4
DV		 6236 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6237 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6238 enable = true;
6239 }
6240
d6dd9eb1 6241 intel_set_power_well(dev, enable);
c67a470b
PZ		 6242
6243 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6244}
6245
09b4ddf9 6246static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6247 int x, int y,
6248 struct drm_framebuffer *fb)
6249{
6250 struct drm_device *dev = crtc->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6253 int plane = intel_crtc->plane;
09b4ddf9 6254 int ret;
09b4ddf9 6255
ff9a6750 6256 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6257 return -EINVAL;
6258
09b4ddf9
PZ		 6259 /* Ensure that the cursor is valid for the new mode before changing... */
6260 intel_crtc_update_cursor(crtc, true);
6261
03afc4a2
DV		 6262 if (intel_crtc->config.has_dp_encoder)
6263 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6264
6265 intel_crtc->lowfreq_avail = false;
09b4ddf9 6266
8a654f3b 6267 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6268
ca3a0ff8 6269 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6270 intel_cpu_transcoder_set_m_n(intel_crtc,
6271 &intel_crtc->config.fdi_m_n);
6272 }
09b4ddf9 6273
6ff93609 6274 haswell_set_pipeconf(crtc);
09b4ddf9 6275
50f3b016 6276 intel_set_pipe_csc(crtc);
86d3efce 6277
09b4ddf9 6278 /* Set up the display plane register */
86d3efce 6279 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6280 POSTING_READ(DSPCNTR(plane));
6281
6282 ret = intel_pipe_set_base(crtc, x, y, fb);
6283
6284 intel_update_watermarks(dev);
6285
1f803ee5 6286 return ret;
79e53945
JB		 6287}
6288
0e8ffe1b
DV		 6289static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6290 struct intel_crtc_config *pipe_config)
6291{
6292 struct drm_device *dev = crtc->base.dev;
6293 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6294 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6295 uint32_t tmp;
6296
e143a21c 6297 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6298 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6299
eccb140b
DV		 6300 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6301 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6302 enum pipe trans_edp_pipe;
6303 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6304 default:
6305 WARN(1, "unknown pipe linked to edp transcoder\n");
6306 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6307 case TRANS_DDI_EDP_INPUT_A_ON:
6308 trans_edp_pipe = PIPE_A;
6309 break;
6310 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6311 trans_edp_pipe = PIPE_B;
6312 break;
6313 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6314 trans_edp_pipe = PIPE_C;
6315 break;
6316 }
6317
6318 if (trans_edp_pipe == crtc->pipe)
6319 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6320 }
6321
b97186f0 6322 if (!intel_display_power_enabled(dev,
eccb140b 6323 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6324 return false;
6325
eccb140b 6326 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6327 if (!(tmp & PIPECONF_ENABLE))
6328 return false;
6329
88adfff1 6330 /*
f196e6be 6331 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6332 * DDI E. So just check whether this pipe is wired to DDI E and whether
6333 * the PCH transcoder is on.
6334 */
eccb140b 6335 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6336 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6337 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6338 pipe_config->has_pch_encoder = true;
6339
627eb5a3
DV		 6340 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6341 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6342 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6343
6344 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6345 }
6346
1bd1bd80
DV		 6347 intel_get_pipe_timings(crtc, pipe_config);
6348
2fa2fe9a
DV		 6349 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6350 if (intel_display_power_enabled(dev, pfit_domain))
6351 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6352
42db64ef
PZ		 6353 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6354 (I915_READ(IPS_CTL) & IPS_ENABLE);
6355
6c49f241
DV		 6356 pipe_config->pixel_multiplier = 1;
6357
0e8ffe1b
DV		 6358 return true;
6359}
6360
f564048e 6361static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6362 int x, int y,
94352cf9 6363 struct drm_framebuffer *fb)
f564048e
EA		 6364{
6365 struct drm_device *dev = crtc->dev;
6366 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6367 struct intel_encoder *encoder;
0b701d27 6368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6369 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6370 int pipe = intel_crtc->pipe;
f564048e
EA		 6371 int ret;
6372
0b701d27 6373 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6374
b8cecdf5
DV		 6375 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6376
79e53945 6377 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6378
9256aa19
DV		 6379 if (ret != 0)
6380 return ret;
6381
6382 for_each_encoder_on_crtc(dev, crtc, encoder) {
6383 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6384 encoder->base.base.id,
6385 drm_get_encoder_name(&encoder->base),
6386 mode->base.id, mode->name);
36f2d1f1 6387 encoder->mode_set(encoder);
9256aa19
DV		 6388 }
6389
6390 return 0;
79e53945
JB		 6391}
6392
3a9627f4
WF		 6393static bool intel_eld_uptodate(struct drm_connector *connector,
6394 int reg_eldv, uint32_t bits_eldv,
6395 int reg_elda, uint32_t bits_elda,
6396 int reg_edid)
6397{
6398 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6399 uint8_t *eld = connector->eld;
6400 uint32_t i;
6401
6402 i = I915_READ(reg_eldv);
6403 i &= bits_eldv;
6404
6405 if (!eld[0])
6406 return !i;
6407
6408 if (!i)
6409 return false;
6410
6411 i = I915_READ(reg_elda);
6412 i &= ~bits_elda;
6413 I915_WRITE(reg_elda, i);
6414
6415 for (i = 0; i < eld[2]; i++)
6416 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6417 return false;
6418
6419 return true;
6420}
6421
e0dac65e
WF		 6422static void g4x_write_eld(struct drm_connector *connector,
6423 struct drm_crtc *crtc)
6424{
6425 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6426 uint8_t *eld = connector->eld;
6427 uint32_t eldv;
6428 uint32_t len;
6429 uint32_t i;
6430
6431 i = I915_READ(G4X_AUD_VID_DID);
6432
6433 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6434 eldv = G4X_ELDV_DEVCL_DEVBLC;
6435 else
6436 eldv = G4X_ELDV_DEVCTG;
6437
3a9627f4
WF		 6438 if (intel_eld_uptodate(connector,
6439 G4X_AUD_CNTL_ST, eldv,
6440 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6441 G4X_HDMIW_HDMIEDID))
6442 return;
6443
e0dac65e
WF		 6444 i = I915_READ(G4X_AUD_CNTL_ST);
6445 i &= ~(eldv | G4X_ELD_ADDR);
6446 len = (i >> 9) & 0x1f; /* ELD buffer size */
6447 I915_WRITE(G4X_AUD_CNTL_ST, i);
6448
6449 if (!eld[0])
6450 return;
6451
6452 len = min_t(uint8_t, eld[2], len);
6453 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6454 for (i = 0; i < len; i++)
6455 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6456
6457 i = I915_READ(G4X_AUD_CNTL_ST);
6458 i |= eldv;
6459 I915_WRITE(G4X_AUD_CNTL_ST, i);
6460}
6461
83358c85
WX		 6462static void haswell_write_eld(struct drm_connector *connector,
6463 struct drm_crtc *crtc)
6464{
6465 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6466 uint8_t *eld = connector->eld;
6467 struct drm_device *dev = crtc->dev;
7b9f35a6 6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6469 uint32_t eldv;
6470 uint32_t i;
6471 int len;
6472 int pipe = to_intel_crtc(crtc)->pipe;
6473 int tmp;
6474
6475 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6476 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6477 int aud_config = HSW_AUD_CFG(pipe);
6478 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6479
6480
6481 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6482
6483 /* Audio output enable */
6484 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6485 tmp = I915_READ(aud_cntrl_st2);
6486 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6487 I915_WRITE(aud_cntrl_st2, tmp);
6488
6489 /* Wait for 1 vertical blank */
6490 intel_wait_for_vblank(dev, pipe);
6491
6492 /* Set ELD valid state */
6493 tmp = I915_READ(aud_cntrl_st2);
6494 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6495 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6496 I915_WRITE(aud_cntrl_st2, tmp);
6497 tmp = I915_READ(aud_cntrl_st2);
6498 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6499
6500 /* Enable HDMI mode */
6501 tmp = I915_READ(aud_config);
6502 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6503 /* clear N_programing_enable and N_value_index */
6504 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6505 I915_WRITE(aud_config, tmp);
6506
6507 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6508
6509 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6510 intel_crtc->eld_vld = true;
83358c85
WX		 6511
6512 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6513 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6514 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6515 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6516 } else
6517 I915_WRITE(aud_config, 0);
6518
6519 if (intel_eld_uptodate(connector,
6520 aud_cntrl_st2, eldv,
6521 aud_cntl_st, IBX_ELD_ADDRESS,
6522 hdmiw_hdmiedid))
6523 return;
6524
6525 i = I915_READ(aud_cntrl_st2);
6526 i &= ~eldv;
6527 I915_WRITE(aud_cntrl_st2, i);
6528
6529 if (!eld[0])
6530 return;
6531
6532 i = I915_READ(aud_cntl_st);
6533 i &= ~IBX_ELD_ADDRESS;
6534 I915_WRITE(aud_cntl_st, i);
6535 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6536 DRM_DEBUG_DRIVER("port num:%d\n", i);
6537
6538 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6539 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6540 for (i = 0; i < len; i++)
6541 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6542
6543 i = I915_READ(aud_cntrl_st2);
6544 i |= eldv;
6545 I915_WRITE(aud_cntrl_st2, i);
6546
6547}
6548
e0dac65e
WF		 6549static void ironlake_write_eld(struct drm_connector *connector,
6550 struct drm_crtc *crtc)
6551{
6552 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6553 uint8_t *eld = connector->eld;
6554 uint32_t eldv;
6555 uint32_t i;
6556 int len;
6557 int hdmiw_hdmiedid;
b6daa025 6558 int aud_config;
e0dac65e
WF		 6559 int aud_cntl_st;
6560 int aud_cntrl_st2;
9b138a83 6561 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6562
b3f33cbf 6563 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6564 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6565 aud_config = IBX_AUD_CFG(pipe);
6566 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6567 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6568 } else {
9b138a83
WX		 6569 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6570 aud_config = CPT_AUD_CFG(pipe);
6571 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6572 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6573 }
6574
9b138a83 6575 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6576
6577 i = I915_READ(aud_cntl_st);
9b138a83 6578 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6579 if (!i) {
6580 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6581 /* operate blindly on all ports */
1202b4c6
WF		 6582 eldv = IBX_ELD_VALIDB;
6583 eldv |= IBX_ELD_VALIDB << 4;
6584 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6585 } else {
2582a850 6586 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6587 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6588 }
6589
3a9627f4
WF		 6590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6591 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6592 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6593 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6594 } else
6595 I915_WRITE(aud_config, 0);
e0dac65e 6596
3a9627f4
WF		 6597 if (intel_eld_uptodate(connector,
6598 aud_cntrl_st2, eldv,
6599 aud_cntl_st, IBX_ELD_ADDRESS,
6600 hdmiw_hdmiedid))
6601 return;
6602
e0dac65e
WF		 6603 i = I915_READ(aud_cntrl_st2);
6604 i &= ~eldv;
6605 I915_WRITE(aud_cntrl_st2, i);
6606
6607 if (!eld[0])
6608 return;
6609
e0dac65e 6610 i = I915_READ(aud_cntl_st);
1202b4c6 6611 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6612 I915_WRITE(aud_cntl_st, i);
6613
6614 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6615 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6616 for (i = 0; i < len; i++)
6617 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6618
6619 i = I915_READ(aud_cntrl_st2);
6620 i |= eldv;
6621 I915_WRITE(aud_cntrl_st2, i);
6622}
6623
6624void intel_write_eld(struct drm_encoder *encoder,
6625 struct drm_display_mode *mode)
6626{
6627 struct drm_crtc *crtc = encoder->crtc;
6628 struct drm_connector *connector;
6629 struct drm_device *dev = encoder->dev;
6630 struct drm_i915_private *dev_priv = dev->dev_private;
6631
6632 connector = drm_select_eld(encoder, mode);
6633 if (!connector)
6634 return;
6635
6636 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6637 connector->base.id,
6638 drm_get_connector_name(connector),
6639 connector->encoder->base.id,
6640 drm_get_encoder_name(connector->encoder));
6641
6642 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6643
6644 if (dev_priv->display.write_eld)
6645 dev_priv->display.write_eld(connector, crtc);
6646}
6647
79e53945
JB		 6648/** Loads the palette/gamma unit for the CRTC with the prepared values */
6649void intel_crtc_load_lut(struct drm_crtc *crtc)
6650{
6651 struct drm_device *dev = crtc->dev;
6652 struct drm_i915_private *dev_priv = dev->dev_private;
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6654 enum pipe pipe = intel_crtc->pipe;
6655 int palreg = PALETTE(pipe);
79e53945 6656 int i;
42db64ef 6657 bool reenable_ips = false;
79e53945
JB		 6658
6659 /* The clocks have to be on to load the palette. */
aed3f09d 6660 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6661 return;
6662
14420bd0
VS		 6663 if (!HAS_PCH_SPLIT(dev_priv->dev))
6664 assert_pll_enabled(dev_priv, pipe);
6665
f2b115e6 6666 /* use legacy palette for Ironlake */
bad720ff 6667 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6668 palreg = LGC_PALETTE(pipe);
6669
6670 /* Workaround : Do not read or write the pipe palette/gamma data while
6671 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6672 */
6673 if (intel_crtc->config.ips_enabled &&
6674 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6675 GAMMA_MODE_MODE_SPLIT)) {
6676 hsw_disable_ips(intel_crtc);
6677 reenable_ips = true;
6678 }
2c07245f 6679
79e53945
JB		 6680 for (i = 0; i < 256; i++) {
6681 I915_WRITE(palreg + 4 * i,
6682 (intel_crtc->lut_r[i] << 16) |
6683 (intel_crtc->lut_g[i] << 8) |
6684 intel_crtc->lut_b[i]);
6685 }
42db64ef
PZ		 6686
6687 if (reenable_ips)
6688 hsw_enable_ips(intel_crtc);
79e53945
JB		 6689}
6690
560b85bb
CW		 6691static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6692{
6693 struct drm_device *dev = crtc->dev;
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6696 bool visible = base != 0;
6697 u32 cntl;
6698
6699 if (intel_crtc->cursor_visible == visible)
6700 return;
6701
9db4a9c7 6702 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6703 if (visible) {
6704 /* On these chipsets we can only modify the base whilst
6705 * the cursor is disabled.
6706 */
9db4a9c7 6707 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6708
6709 cntl &= ~(CURSOR_FORMAT_MASK);
6710 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6711 cntl |= CURSOR_ENABLE |
6712 CURSOR_GAMMA_ENABLE |
6713 CURSOR_FORMAT_ARGB;
6714 } else
6715 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6716 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6717
6718 intel_crtc->cursor_visible = visible;
6719}
6720
6721static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6722{
6723 struct drm_device *dev = crtc->dev;
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6726 int pipe = intel_crtc->pipe;
6727 bool visible = base != 0;
6728
6729 if (intel_crtc->cursor_visible != visible) {
548f245b 6730 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6731 if (base) {
6732 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6733 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6734 cntl |= pipe << 28; /* Connect to correct pipe */
6735 } else {
6736 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6737 cntl |= CURSOR_MODE_DISABLE;
6738 }
9db4a9c7 6739 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6740
6741 intel_crtc->cursor_visible = visible;
6742 }
6743 /* and commit changes on next vblank */
9db4a9c7 6744 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6745}
6746
65a21cd6
JB		 6747static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6748{
6749 struct drm_device *dev = crtc->dev;
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6752 int pipe = intel_crtc->pipe;
6753 bool visible = base != 0;
6754
6755 if (intel_crtc->cursor_visible != visible) {
6756 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6757 if (base) {
6758 cntl &= ~CURSOR_MODE;
6759 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6760 } else {
6761 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6762 cntl |= CURSOR_MODE_DISABLE;
6763 }
86d3efce
VS		 6764 if (IS_HASWELL(dev))
6765 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6766 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6767
6768 intel_crtc->cursor_visible = visible;
6769 }
6770 /* and commit changes on next vblank */
6771 I915_WRITE(CURBASE_IVB(pipe), base);
6772}
6773
cda4b7d3 6774/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6775static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6776 bool on)
cda4b7d3
CW		 6777{
6778 struct drm_device *dev = crtc->dev;
6779 struct drm_i915_private *dev_priv = dev->dev_private;
6780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6781 int pipe = intel_crtc->pipe;
6782 int x = intel_crtc->cursor_x;
6783 int y = intel_crtc->cursor_y;
560b85bb 6784 u32 base, pos;
cda4b7d3
CW		 6785 bool visible;
6786
6787 pos = 0;
6788
6b383a7f 6789 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6790 base = intel_crtc->cursor_addr;
6791 if (x > (int) crtc->fb->width)
6792 base = 0;
6793
6794 if (y > (int) crtc->fb->height)
6795 base = 0;
6796 } else
6797 base = 0;
6798
6799 if (x < 0) {
6800 if (x + intel_crtc->cursor_width < 0)
6801 base = 0;
6802
6803 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6804 x = -x;
6805 }
6806 pos |= x << CURSOR_X_SHIFT;
6807
6808 if (y < 0) {
6809 if (y + intel_crtc->cursor_height < 0)
6810 base = 0;
6811
6812 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6813 y = -y;
6814 }
6815 pos |= y << CURSOR_Y_SHIFT;
6816
6817 visible = base != 0;
560b85bb 6818 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6819 return;
6820
0cd83aa9 6821 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6822 I915_WRITE(CURPOS_IVB(pipe), pos);
6823 ivb_update_cursor(crtc, base);
6824 } else {
6825 I915_WRITE(CURPOS(pipe), pos);
6826 if (IS_845G(dev) || IS_I865G(dev))
6827 i845_update_cursor(crtc, base);
6828 else
6829 i9xx_update_cursor(crtc, base);
6830 }
cda4b7d3
CW		 6831}
6832
79e53945 6833static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6834 struct drm_file *file,
79e53945
JB		 6835 uint32_t handle,
6836 uint32_t width, uint32_t height)
6837{
6838 struct drm_device *dev = crtc->dev;
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6841 struct drm_i915_gem_object *obj;
cda4b7d3 6842 uint32_t addr;
3f8bc370 6843 int ret;
79e53945 6844
79e53945
JB		 6845 /* if we want to turn off the cursor ignore width and height */
6846 if (!handle) {
28c97730 6847 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6848 addr = 0;
05394f39 6849 obj = NULL;
5004417d 6850 mutex_lock(&dev->struct_mutex);
3f8bc370 6851 goto finish;
79e53945
JB		 6852 }
6853
6854 /* Currently we only support 64x64 cursors */
6855 if (width != 64 || height != 64) {
6856 DRM_ERROR("we currently only support 64x64 cursors\n");
6857 return -EINVAL;
6858 }
6859
05394f39 6860 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6861 if (&obj->base == NULL)
79e53945
JB		 6862 return -ENOENT;
6863
05394f39 6864 if (obj->base.size < width * height * 4) {
79e53945 6865 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6866 ret = -ENOMEM;
6867 goto fail;
79e53945
JB		 6868 }
6869
71acb5eb 6870 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6871 mutex_lock(&dev->struct_mutex);
b295d1b6 6872 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6873 unsigned alignment;
6874
d9e86c0e
CW		 6875 if (obj->tiling_mode) {
6876 DRM_ERROR("cursor cannot be tiled\n");
6877 ret = -EINVAL;
6878 goto fail_locked;
6879 }
6880
693db184
CW		 6881 /* Note that the w/a also requires 2 PTE of padding following
6882 * the bo. We currently fill all unused PTE with the shadow
6883 * page and so we should always have valid PTE following the
6884 * cursor preventing the VT-d warning.
6885 */
6886 alignment = 0;
6887 if (need_vtd_wa(dev))
6888 alignment = 64*1024;
6889
6890 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6891 if (ret) {
6892 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6893 goto fail_locked;
e7b526bb
CW		 6894 }
6895
d9e86c0e
CW		 6896 ret = i915_gem_object_put_fence(obj);
6897 if (ret) {
2da3b9b9 6898 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6899 goto fail_unpin;
6900 }
6901
f343c5f6 6902 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6903 } else {
6eeefaf3 6904 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6905 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6906 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6907 align);
71acb5eb
DA		 6908 if (ret) {
6909 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6910 goto fail_locked;
71acb5eb 6911 }
05394f39 6912 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6913 }
6914
a6c45cf0 6915 if (IS_GEN2(dev))
14b60391
JB		 6916 I915_WRITE(CURSIZE, (height << 12) | width);
6917
3f8bc370 6918 finish:
3f8bc370 6919 if (intel_crtc->cursor_bo) {
b295d1b6 6920 if (dev_priv->info->cursor_needs_physical) {
05394f39 6921 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6922 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6923 } else
cc98b413 6924 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6925 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6926 }
80824003 6927
7f9872e0 6928 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6929
6930 intel_crtc->cursor_addr = addr;
05394f39 6931 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6932 intel_crtc->cursor_width = width;
6933 intel_crtc->cursor_height = height;
6934
40ccc72b 6935 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6936
79e53945 6937 return 0;
e7b526bb 6938fail_unpin:
cc98b413 6939 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6940fail_locked:
34b8686e 6941 mutex_unlock(&dev->struct_mutex);
bc9025bd 6942fail:
05394f39 6943 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6944 return ret;
79e53945
JB		 6945}
6946
6947static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6948{
79e53945 6949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6950
cda4b7d3
CW		 6951 intel_crtc->cursor_x = x;
6952 intel_crtc->cursor_y = y;
652c393a 6953
40ccc72b 6954 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6955
6956 return 0;
6957}
6958
6959/** Sets the color ramps on behalf of RandR */
6960void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6961 u16 blue, int regno)
6962{
6963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6964
6965 intel_crtc->lut_r[regno] = red >> 8;
6966 intel_crtc->lut_g[regno] = green >> 8;
6967 intel_crtc->lut_b[regno] = blue >> 8;
6968}
6969
b8c00ac5
DA		 6970void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6971 u16 *blue, int regno)
6972{
6973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6974
6975 *red = intel_crtc->lut_r[regno] << 8;
6976 *green = intel_crtc->lut_g[regno] << 8;
6977 *blue = intel_crtc->lut_b[regno] << 8;
6978}
6979
79e53945 6980static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6981 u16 *blue, uint32_t start, uint32_t size)
79e53945 6982{
7203425a 6983 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6985
7203425a 6986 for (i = start; i < end; i++) {
79e53945
JB		 6987 intel_crtc->lut_r[i] = red[i] >> 8;
6988 intel_crtc->lut_g[i] = green[i] >> 8;
6989 intel_crtc->lut_b[i] = blue[i] >> 8;
6990 }
6991
6992 intel_crtc_load_lut(crtc);
6993}
6994
79e53945
JB		 6995/* VESA 640x480x72Hz mode to set on the pipe */
6996static struct drm_display_mode load_detect_mode = {
6997 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6998 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6999};
7000
d2dff872
CW		 7001static struct drm_framebuffer *
7002intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7003 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7004 struct drm_i915_gem_object *obj)
7005{
7006 struct intel_framebuffer *intel_fb;
7007 int ret;
7008
7009 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7010 if (!intel_fb) {
7011 drm_gem_object_unreference_unlocked(&obj->base);
7012 return ERR_PTR(-ENOMEM);
7013 }
7014
7015 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7016 if (ret) {
7017 drm_gem_object_unreference_unlocked(&obj->base);
7018 kfree(intel_fb);
7019 return ERR_PTR(ret);
7020 }
7021
7022 return &intel_fb->base;
7023}
7024
7025static u32
7026intel_framebuffer_pitch_for_width(int width, int bpp)
7027{
7028 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7029 return ALIGN(pitch, 64);
7030}
7031
7032static u32
7033intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7034{
7035 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7036 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7037}
7038
7039static struct drm_framebuffer *
7040intel_framebuffer_create_for_mode(struct drm_device *dev,
7041 struct drm_display_mode *mode,
7042 int depth, int bpp)
7043{
7044 struct drm_i915_gem_object *obj;
0fed39bd 7045 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7046
7047 obj = i915_gem_alloc_object(dev,
7048 intel_framebuffer_size_for_mode(mode, bpp));
7049 if (obj == NULL)
7050 return ERR_PTR(-ENOMEM);
7051
7052 mode_cmd.width = mode->hdisplay;
7053 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7054 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7055 bpp);
5ca0c34a 7056 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7057
7058 return intel_framebuffer_create(dev, &mode_cmd, obj);
7059}
7060
7061static struct drm_framebuffer *
7062mode_fits_in_fbdev(struct drm_device *dev,
7063 struct drm_display_mode *mode)
7064{
7065 struct drm_i915_private *dev_priv = dev->dev_private;
7066 struct drm_i915_gem_object *obj;
7067 struct drm_framebuffer *fb;
7068
7069 if (dev_priv->fbdev == NULL)
7070 return NULL;
7071
7072 obj = dev_priv->fbdev->ifb.obj;
7073 if (obj == NULL)
7074 return NULL;
7075
7076 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7077 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7078 fb->bits_per_pixel))
d2dff872
CW		 7079 return NULL;
7080
01f2c773 7081 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7082 return NULL;
7083
7084 return fb;
7085}
7086
d2434ab7 7087bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7088 struct drm_display_mode *mode,
8261b191 7089 struct intel_load_detect_pipe *old)
79e53945
JB		 7090{
7091 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7092 struct intel_encoder *intel_encoder =
7093 intel_attached_encoder(connector);
79e53945 7094 struct drm_crtc *possible_crtc;
4ef69c7a 7095 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7096 struct drm_crtc *crtc = NULL;
7097 struct drm_device *dev = encoder->dev;
94352cf9 7098 struct drm_framebuffer *fb;
79e53945
JB		 7099 int i = -1;
7100
d2dff872
CW		 7101 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7102 connector->base.id, drm_get_connector_name(connector),
7103 encoder->base.id, drm_get_encoder_name(encoder));
7104
79e53945
JB		 7105 /*
7106 * Algorithm gets a little messy:
7a5e4805 7107 *
79e53945
JB		 7108 * - if the connector already has an assigned crtc, use it (but make
7109 * sure it's on first)
7a5e4805 7110 *
79e53945
JB		 7111 * - try to find the first unused crtc that can drive this connector,
7112 * and use that if we find one
79e53945
JB		 7113 */
7114
7115 /* See if we already have a CRTC for this connector */
7116 if (encoder->crtc) {
7117 crtc = encoder->crtc;
8261b191 7118
7b24056b
DV		 7119 mutex_lock(&crtc->mutex);
7120
24218aac 7121 old->dpms_mode = connector->dpms;
8261b191
CW		 7122 old->load_detect_temp = false;
7123
7124 /* Make sure the crtc and connector are running */
24218aac
DV		 7125 if (connector->dpms != DRM_MODE_DPMS_ON)
7126 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7127
7173188d 7128 return true;
79e53945
JB		 7129 }
7130
7131 /* Find an unused one (if possible) */
7132 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7133 i++;
7134 if (!(encoder->possible_crtcs & (1 << i)))
7135 continue;
7136 if (!possible_crtc->enabled) {
7137 crtc = possible_crtc;
7138 break;
7139 }
79e53945
JB		 7140 }
7141
7142 /*
7143 * If we didn't find an unused CRTC, don't use any.
7144 */
7145 if (!crtc) {
7173188d
CW		 7146 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7147 return false;
79e53945
JB		 7148 }
7149
7b24056b 7150 mutex_lock(&crtc->mutex);
fc303101
DV		 7151 intel_encoder->new_crtc = to_intel_crtc(crtc);
7152 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7153
7154 intel_crtc = to_intel_crtc(crtc);
24218aac 7155 old->dpms_mode = connector->dpms;
8261b191 7156 old->load_detect_temp = true;
d2dff872 7157 old->release_fb = NULL;
79e53945 7158
6492711d
CW		 7159 if (!mode)
7160 mode = &load_detect_mode;
79e53945 7161
d2dff872
CW		 7162 /* We need a framebuffer large enough to accommodate all accesses
7163 * that the plane may generate whilst we perform load detection.
7164 * We can not rely on the fbcon either being present (we get called
7165 * during its initialisation to detect all boot displays, or it may
7166 * not even exist) or that it is large enough to satisfy the
7167 * requested mode.
7168 */
94352cf9
DV		 7169 fb = mode_fits_in_fbdev(dev, mode);
7170 if (fb == NULL) {
d2dff872 7171 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7172 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7173 old->release_fb = fb;
d2dff872
CW		 7174 } else
7175 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7176 if (IS_ERR(fb)) {
d2dff872 7177 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7178 mutex_unlock(&crtc->mutex);
0e8b3d3e 7179 return false;
79e53945 7180 }
79e53945 7181
c0c36b94 7182 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7183 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7184 if (old->release_fb)
7185 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7186 mutex_unlock(&crtc->mutex);
0e8b3d3e 7187 return false;
79e53945 7188 }
7173188d 7189
79e53945 7190 /* let the connector get through one full cycle before testing */
9d0498a2 7191 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7192 return true;
79e53945
JB		 7193}
7194
d2434ab7 7195void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7196 struct intel_load_detect_pipe *old)
79e53945 7197{
d2434ab7
DV		 7198 struct intel_encoder *intel_encoder =
7199 intel_attached_encoder(connector);
4ef69c7a 7200 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7201 struct drm_crtc *crtc = encoder->crtc;
79e53945 7202
d2dff872
CW		 7203 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7204 connector->base.id, drm_get_connector_name(connector),
7205 encoder->base.id, drm_get_encoder_name(encoder));
7206
8261b191 7207 if (old->load_detect_temp) {
fc303101
DV		 7208 to_intel_connector(connector)->new_encoder = NULL;
7209 intel_encoder->new_crtc = NULL;
7210 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7211
36206361
DV		 7212 if (old->release_fb) {
7213 drm_framebuffer_unregister_private(old->release_fb);
7214 drm_framebuffer_unreference(old->release_fb);
7215 }
d2dff872 7216
67c96400 7217 mutex_unlock(&crtc->mutex);
0622a53c 7218 return;
79e53945
JB		 7219 }
7220
c751ce4f 7221 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7222 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7223 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7224
7225 mutex_unlock(&crtc->mutex);
79e53945
JB		 7226}
7227
7228/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7229static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7230 struct intel_crtc_config *pipe_config)
79e53945 7231{
f1f644dc 7232 struct drm_device *dev = crtc->base.dev;
79e53945 7233 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7234 int pipe = pipe_config->cpu_transcoder;
548f245b 7235 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7236 u32 fp;
7237 intel_clock_t clock;
7238
7239 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7240 fp = I915_READ(FP0(pipe));
79e53945 7241 else
39adb7a5 7242 fp = I915_READ(FP1(pipe));
79e53945
JB		 7243
7244 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7245 if (IS_PINEVIEW(dev)) {
7246 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7247 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7248 } else {
7249 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7250 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7251 }
7252
a6c45cf0 7253 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7254 if (IS_PINEVIEW(dev))
7255 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7256 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7257 else
7258 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7259 DPLL_FPA01_P1_POST_DIV_SHIFT);
7260
7261 switch (dpll & DPLL_MODE_MASK) {
7262 case DPLLB_MODE_DAC_SERIAL:
7263 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7264 5 : 10;
7265 break;
7266 case DPLLB_MODE_LVDS:
7267 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7268 7 : 14;
7269 break;
7270 default:
28c97730 7271 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7272 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7273 pipe_config->adjusted_mode.clock = 0;
7274 return;
79e53945
JB		 7275 }
7276
ac58c3f0
DV		 7277 if (IS_PINEVIEW(dev))
7278 pineview_clock(96000, &clock);
7279 else
7280 i9xx_clock(96000, &clock);
79e53945
JB		 7281 } else {
7282 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7283
7284 if (is_lvds) {
7285 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7286 DPLL_FPA01_P1_POST_DIV_SHIFT);
7287 clock.p2 = 14;
7288
7289 if ((dpll & PLL_REF_INPUT_MASK) ==
7290 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7291 /* XXX: might not be 66MHz */
ac58c3f0 7292 i9xx_clock(66000, &clock);
79e53945 7293 } else
ac58c3f0 7294 i9xx_clock(48000, &clock);
79e53945
JB		 7295 } else {
7296 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7297 clock.p1 = 2;
7298 else {
7299 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7300 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7301 }
7302 if (dpll & PLL_P2_DIVIDE_BY_4)
7303 clock.p2 = 4;
7304 else
7305 clock.p2 = 2;
7306
ac58c3f0 7307 i9xx_clock(48000, &clock);
79e53945
JB		 7308 }
7309 }
7310
f1f644dc
JB		 7311 pipe_config->adjusted_mode.clock = clock.dot *
7312 pipe_config->pixel_multiplier;
7313}
7314
7315static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7316 struct intel_crtc_config *pipe_config)
7317{
7318 struct drm_device *dev = crtc->base.dev;
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7320 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7321 int link_freq, repeat;
7322 u64 clock;
7323 u32 link_m, link_n;
7324
7325 repeat = pipe_config->pixel_multiplier;
7326
7327 /*
7328 * The calculation for the data clock is:
7329 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7330 * But we want to avoid losing precison if possible, so:
7331 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7332 *
7333 * and the link clock is simpler:
7334 * link_clock = (m * link_clock * repeat) / n
7335 */
7336
7337 /*
7338 * We need to get the FDI or DP link clock here to derive
7339 * the M/N dividers.
7340 *
7341 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7342 * For DP, it's either 1.62GHz or 2.7GHz.
7343 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7344 */
f1f644dc
JB		 7345 if (pipe_config->has_pch_encoder)
7346 link_freq = intel_fdi_link_freq(dev) * 10000;
7347 else
7348 link_freq = pipe_config->port_clock;
7349
7350 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7351 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7352
7353 if (!link_m || !link_n)
7354 return;
79e53945 7355
f1f644dc
JB		 7356 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7357 do_div(clock, link_n);
7358
7359 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7360}
7361
7362/** Returns the currently programmed mode of the given pipe. */
7363struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7364 struct drm_crtc *crtc)
7365{
548f245b 7366 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7368 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7369 struct drm_display_mode *mode;
f1f644dc 7370 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7371 int htot = I915_READ(HTOTAL(cpu_transcoder));
7372 int hsync = I915_READ(HSYNC(cpu_transcoder));
7373 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7374 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7375
7376 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7377 if (!mode)
7378 return NULL;
7379
f1f644dc
JB		 7380 /*
7381 * Construct a pipe_config sufficient for getting the clock info
7382 * back out of crtc_clock_get.
7383 *
7384 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7385 * to use a real value here instead.
7386 */
e143a21c 7387 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7388 pipe_config.pixel_multiplier = 1;
7389 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7390
7391 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7392 mode->hdisplay = (htot & 0xffff) + 1;
7393 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7394 mode->hsync_start = (hsync & 0xffff) + 1;
7395 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7396 mode->vdisplay = (vtot & 0xffff) + 1;
7397 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7398 mode->vsync_start = (vsync & 0xffff) + 1;
7399 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7400
7401 drm_mode_set_name(mode);
79e53945
JB		 7402
7403 return mode;
7404}
7405
3dec0095 7406static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7407{
7408 struct drm_device *dev = crtc->dev;
7409 drm_i915_private_t *dev_priv = dev->dev_private;
7410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7411 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7412 int dpll_reg = DPLL(pipe);
7413 int dpll;
652c393a 7414
bad720ff 7415 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7416 return;
7417
7418 if (!dev_priv->lvds_downclock_avail)
7419 return;
7420
dbdc6479 7421 dpll = I915_READ(dpll_reg);
652c393a 7422 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7423 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7424
8ac5a6d5 7425 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7426
7427 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7428 I915_WRITE(dpll_reg, dpll);
9d0498a2 7429 intel_wait_for_vblank(dev, pipe);
dbdc6479 7430
652c393a
JB		 7431 dpll = I915_READ(dpll_reg);
7432 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7433 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7434 }
652c393a
JB		 7435}
7436
7437static void intel_decrease_pllclock(struct drm_crtc *crtc)
7438{
7439 struct drm_device *dev = crtc->dev;
7440 drm_i915_private_t *dev_priv = dev->dev_private;
7441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7442
bad720ff 7443 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7444 return;
7445
7446 if (!dev_priv->lvds_downclock_avail)
7447 return;
7448
7449 /*
7450 * Since this is called by a timer, we should never get here in
7451 * the manual case.
7452 */
7453 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7454 int pipe = intel_crtc->pipe;
7455 int dpll_reg = DPLL(pipe);
7456 int dpll;
f6e5b160 7457
44d98a61 7458 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7459
8ac5a6d5 7460 assert_panel_unlocked(dev_priv, pipe);
652c393a 7461
dc257cf1 7462 dpll = I915_READ(dpll_reg);
652c393a
JB		 7463 dpll |= DISPLAY_RATE_SELECT_FPA1;
7464 I915_WRITE(dpll_reg, dpll);
9d0498a2 7465 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7466 dpll = I915_READ(dpll_reg);
7467 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7468 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7469 }
7470
7471}
7472
f047e395
CW		 7473void intel_mark_busy(struct drm_device *dev)
7474{
c67a470b
PZ		 7475 struct drm_i915_private *dev_priv = dev->dev_private;
7476
7477 hsw_package_c8_gpu_busy(dev_priv);
7478 i915_update_gfx_val(dev_priv);
f047e395
CW		 7479}
7480
7481void intel_mark_idle(struct drm_device *dev)
652c393a 7482{
c67a470b 7483 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7484 struct drm_crtc *crtc;
652c393a 7485
c67a470b
PZ		 7486 hsw_package_c8_gpu_idle(dev_priv);
7487
652c393a
JB		 7488 if (!i915_powersave)
7489 return;
7490
652c393a 7491 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7492 if (!crtc->fb)
7493 continue;
7494
725a5b54 7495 intel_decrease_pllclock(crtc);
652c393a 7496 }
652c393a
JB		 7497}
7498
c65355bb
CW		 7499void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7500 struct intel_ring_buffer *ring)
652c393a 7501{
f047e395
CW		 7502 struct drm_device *dev = obj->base.dev;
7503 struct drm_crtc *crtc;
652c393a 7504
f047e395 7505 if (!i915_powersave)
acb87dfb
CW		 7506 return;
7507
652c393a
JB		 7508 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7509 if (!crtc->fb)
7510 continue;
7511
c65355bb
CW		 7512 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7513 continue;
7514
7515 intel_increase_pllclock(crtc);
7516 if (ring && intel_fbc_enabled(dev))
7517 ring->fbc_dirty = true;
652c393a
JB		 7518 }
7519}
7520
79e53945
JB		 7521static void intel_crtc_destroy(struct drm_crtc *crtc)
7522{
7523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7524 struct drm_device *dev = crtc->dev;
7525 struct intel_unpin_work *work;
7526 unsigned long flags;
7527
7528 spin_lock_irqsave(&dev->event_lock, flags);
7529 work = intel_crtc->unpin_work;
7530 intel_crtc->unpin_work = NULL;
7531 spin_unlock_irqrestore(&dev->event_lock, flags);
7532
7533 if (work) {
7534 cancel_work_sync(&work->work);
7535 kfree(work);
7536 }
79e53945 7537
40ccc72b
MK		 7538 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7539
79e53945 7540 drm_crtc_cleanup(crtc);
67e77c5a 7541
79e53945
JB		 7542 kfree(intel_crtc);
7543}
7544
6b95a207
KH		 7545static void intel_unpin_work_fn(struct work_struct *__work)
7546{
7547 struct intel_unpin_work *work =
7548 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7549 struct drm_device *dev = work->crtc->dev;
6b95a207 7550
b4a98e57 7551 mutex_lock(&dev->struct_mutex);
1690e1eb 7552 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7553 drm_gem_object_unreference(&work->pending_flip_obj->base);
7554 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7555
b4a98e57
CW		 7556 intel_update_fbc(dev);
7557 mutex_unlock(&dev->struct_mutex);
7558
7559 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7560 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7561
6b95a207
KH		 7562 kfree(work);
7563}
7564
1afe3e9d 7565static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7566 struct drm_crtc *crtc)
6b95a207
KH		 7567{
7568 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7570 struct intel_unpin_work *work;
6b95a207
KH		 7571 unsigned long flags;
7572
7573 /* Ignore early vblank irqs */
7574 if (intel_crtc == NULL)
7575 return;
7576
7577 spin_lock_irqsave(&dev->event_lock, flags);
7578 work = intel_crtc->unpin_work;
e7d841ca
CW		 7579
7580 /* Ensure we don't miss a work->pending update ... */
7581 smp_rmb();
7582
7583 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7584 spin_unlock_irqrestore(&dev->event_lock, flags);
7585 return;
7586 }
7587
e7d841ca
CW		 7588 /* and that the unpin work is consistent wrt ->pending. */
7589 smp_rmb();
7590
6b95a207 7591 intel_crtc->unpin_work = NULL;
6b95a207 7592
45a066eb
RC		 7593 if (work->event)
7594 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7595
0af7e4df
MK		 7596 drm_vblank_put(dev, intel_crtc->pipe);
7597
6b95a207
KH		 7598 spin_unlock_irqrestore(&dev->event_lock, flags);
7599
2c10d571 7600 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7601
7602 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7603
7604 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7605}
7606
1afe3e9d
JB		 7607void intel_finish_page_flip(struct drm_device *dev, int pipe)
7608{
7609 drm_i915_private_t *dev_priv = dev->dev_private;
7610 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7611
49b14a5c 7612 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7613}
7614
7615void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7616{
7617 drm_i915_private_t *dev_priv = dev->dev_private;
7618 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7619
49b14a5c 7620 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7621}
7622
6b95a207
KH		 7623void intel_prepare_page_flip(struct drm_device *dev, int plane)
7624{
7625 drm_i915_private_t *dev_priv = dev->dev_private;
7626 struct intel_crtc *intel_crtc =
7627 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7628 unsigned long flags;
7629
e7d841ca
CW		 7630 /* NB: An MMIO update of the plane base pointer will also
7631 * generate a page-flip completion irq, i.e. every modeset
7632 * is also accompanied by a spurious intel_prepare_page_flip().
7633 */
6b95a207 7634 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7635 if (intel_crtc->unpin_work)
7636 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7637 spin_unlock_irqrestore(&dev->event_lock, flags);
7638}
7639
e7d841ca
CW		 7640inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7641{
7642 /* Ensure that the work item is consistent when activating it ... */
7643 smp_wmb();
7644 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7645 /* and that it is marked active as soon as the irq could fire. */
7646 smp_wmb();
7647}
7648
8c9f3aaf
JB		 7649static int intel_gen2_queue_flip(struct drm_device *dev,
7650 struct drm_crtc *crtc,
7651 struct drm_framebuffer *fb,
7652 struct drm_i915_gem_object *obj)
7653{
7654 struct drm_i915_private *dev_priv = dev->dev_private;
7655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7656 u32 flip_mask;
6d90c952 7657 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7658 int ret;
7659
6d90c952 7660 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7661 if (ret)
83d4092b 7662 goto err;
8c9f3aaf 7663
6d90c952 7664 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7665 if (ret)
83d4092b 7666 goto err_unpin;
8c9f3aaf
JB		 7667
7668 /* Can't queue multiple flips, so wait for the previous
7669 * one to finish before executing the next.
7670 */
7671 if (intel_crtc->plane)
7672 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7673 else
7674 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7675 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7676 intel_ring_emit(ring, MI_NOOP);
7677 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7678 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7679 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7680 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7681 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7682
7683 intel_mark_page_flip_active(intel_crtc);
6d90c952 7684 intel_ring_advance(ring);
83d4092b
CW		 7685 return 0;
7686
7687err_unpin:
7688 intel_unpin_fb_obj(obj);
7689err:
8c9f3aaf
JB		 7690 return ret;
7691}
7692
7693static int intel_gen3_queue_flip(struct drm_device *dev,
7694 struct drm_crtc *crtc,
7695 struct drm_framebuffer *fb,
7696 struct drm_i915_gem_object *obj)
7697{
7698 struct drm_i915_private *dev_priv = dev->dev_private;
7699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7700 u32 flip_mask;
6d90c952 7701 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7702 int ret;
7703
6d90c952 7704 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7705 if (ret)
83d4092b 7706 goto err;
8c9f3aaf 7707
6d90c952 7708 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7709 if (ret)
83d4092b 7710 goto err_unpin;
8c9f3aaf
JB		 7711
7712 if (intel_crtc->plane)
7713 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7714 else
7715 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7716 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7717 intel_ring_emit(ring, MI_NOOP);
7718 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7719 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7720 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7721 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7722 intel_ring_emit(ring, MI_NOOP);
7723
e7d841ca 7724 intel_mark_page_flip_active(intel_crtc);
6d90c952 7725 intel_ring_advance(ring);
83d4092b
CW		 7726 return 0;
7727
7728err_unpin:
7729 intel_unpin_fb_obj(obj);
7730err:
8c9f3aaf
JB		 7731 return ret;
7732}
7733
7734static int intel_gen4_queue_flip(struct drm_device *dev,
7735 struct drm_crtc *crtc,
7736 struct drm_framebuffer *fb,
7737 struct drm_i915_gem_object *obj)
7738{
7739 struct drm_i915_private *dev_priv = dev->dev_private;
7740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7741 uint32_t pf, pipesrc;
6d90c952 7742 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7743 int ret;
7744
6d90c952 7745 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7746 if (ret)
83d4092b 7747 goto err;
8c9f3aaf 7748
6d90c952 7749 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7750 if (ret)
83d4092b 7751 goto err_unpin;
8c9f3aaf
JB		 7752
7753 /* i965+ uses the linear or tiled offsets from the
7754 * Display Registers (which do not change across a page-flip)
7755 * so we need only reprogram the base address.
7756 */
6d90c952
DV		 7757 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7758 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7759 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7760 intel_ring_emit(ring,
f343c5f6 7761 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7762 obj->tiling_mode);
8c9f3aaf
JB		 7763
7764 /* XXX Enabling the panel-fitter across page-flip is so far
7765 * untested on non-native modes, so ignore it for now.
7766 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7767 */
7768 pf = 0;
7769 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7770 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7771
7772 intel_mark_page_flip_active(intel_crtc);
6d90c952 7773 intel_ring_advance(ring);
83d4092b
CW		 7774 return 0;
7775
7776err_unpin:
7777 intel_unpin_fb_obj(obj);
7778err:
8c9f3aaf
JB		 7779 return ret;
7780}
7781
7782static int intel_gen6_queue_flip(struct drm_device *dev,
7783 struct drm_crtc *crtc,
7784 struct drm_framebuffer *fb,
7785 struct drm_i915_gem_object *obj)
7786{
7787 struct drm_i915_private *dev_priv = dev->dev_private;
7788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7789 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7790 uint32_t pf, pipesrc;
7791 int ret;
7792
6d90c952 7793 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7794 if (ret)
83d4092b 7795 goto err;
8c9f3aaf 7796
6d90c952 7797 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7798 if (ret)
83d4092b 7799 goto err_unpin;
8c9f3aaf 7800
6d90c952
DV		 7801 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7802 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7803 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7804 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7805
dc257cf1
DV		 7806 /* Contrary to the suggestions in the documentation,
7807 * "Enable Panel Fitter" does not seem to be required when page
7808 * flipping with a non-native mode, and worse causes a normal
7809 * modeset to fail.
7810 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7811 */
7812 pf = 0;
8c9f3aaf 7813 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7814 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7815
7816 intel_mark_page_flip_active(intel_crtc);
6d90c952 7817 intel_ring_advance(ring);
83d4092b
CW		 7818 return 0;
7819
7820err_unpin:
7821 intel_unpin_fb_obj(obj);
7822err:
8c9f3aaf
JB		 7823 return ret;
7824}
7825
7c9017e5
JB		 7826/*
7827 * On gen7 we currently use the blit ring because (in early silicon at least)
7828 * the render ring doesn't give us interrpts for page flip completion, which
7829 * means clients will hang after the first flip is queued. Fortunately the
7830 * blit ring generates interrupts properly, so use it instead.
7831 */
7832static int intel_gen7_queue_flip(struct drm_device *dev,
7833 struct drm_crtc *crtc,
7834 struct drm_framebuffer *fb,
7835 struct drm_i915_gem_object *obj)
7836{
7837 struct drm_i915_private *dev_priv = dev->dev_private;
7838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7839 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7840 uint32_t plane_bit = 0;
7c9017e5
JB		 7841 int ret;
7842
7843 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7844 if (ret)
83d4092b 7845 goto err;
7c9017e5 7846
cb05d8de
DV		 7847 switch(intel_crtc->plane) {
7848 case PLANE_A:
7849 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7850 break;
7851 case PLANE_B:
7852 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7853 break;
7854 case PLANE_C:
7855 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7856 break;
7857 default:
7858 WARN_ONCE(1, "unknown plane in flip command\n");
7859 ret = -ENODEV;
ab3951eb 7860 goto err_unpin;
cb05d8de
DV		 7861 }
7862
7c9017e5
JB		 7863 ret = intel_ring_begin(ring, 4);
7864 if (ret)
83d4092b 7865 goto err_unpin;
7c9017e5 7866
cb05d8de 7867 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7868 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7869 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7870 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7871
7872 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7873 intel_ring_advance(ring);
83d4092b
CW		 7874 return 0;
7875
7876err_unpin:
7877 intel_unpin_fb_obj(obj);
7878err:
7c9017e5
JB		 7879 return ret;
7880}
7881
8c9f3aaf
JB		 7882static int intel_default_queue_flip(struct drm_device *dev,
7883 struct drm_crtc *crtc,
7884 struct drm_framebuffer *fb,
7885 struct drm_i915_gem_object *obj)
7886{
7887 return -ENODEV;
7888}
7889
6b95a207
KH		 7890static int intel_crtc_page_flip(struct drm_crtc *crtc,
7891 struct drm_framebuffer *fb,
7892 struct drm_pending_vblank_event *event)
7893{
7894 struct drm_device *dev = crtc->dev;
7895 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7896 struct drm_framebuffer *old_fb = crtc->fb;
7897 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7899 struct intel_unpin_work *work;
8c9f3aaf 7900 unsigned long flags;
52e68630 7901 int ret;
6b95a207 7902
e6a595d2
VS		 7903 /* Can't change pixel format via MI display flips. */
7904 if (fb->pixel_format != crtc->fb->pixel_format)
7905 return -EINVAL;
7906
7907 /*
7908 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7909 * Note that pitch changes could also affect these register.
7910 */
7911 if (INTEL_INFO(dev)->gen > 3 &&
7912 (fb->offsets[0] != crtc->fb->offsets[0] ||
7913 fb->pitches[0] != crtc->fb->pitches[0]))
7914 return -EINVAL;
7915
6b95a207
KH		 7916 work = kzalloc(sizeof *work, GFP_KERNEL);
7917 if (work == NULL)
7918 return -ENOMEM;
7919
6b95a207 7920 work->event = event;
b4a98e57 7921 work->crtc = crtc;
4a35f83b 7922 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7923 INIT_WORK(&work->work, intel_unpin_work_fn);
7924
7317c75e
JB		 7925 ret = drm_vblank_get(dev, intel_crtc->pipe);
7926 if (ret)
7927 goto free_work;
7928
6b95a207
KH		 7929 /* We borrow the event spin lock for protecting unpin_work */
7930 spin_lock_irqsave(&dev->event_lock, flags);
7931 if (intel_crtc->unpin_work) {
7932 spin_unlock_irqrestore(&dev->event_lock, flags);
7933 kfree(work);
7317c75e 7934 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7935
7936 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7937 return -EBUSY;
7938 }
7939 intel_crtc->unpin_work = work;
7940 spin_unlock_irqrestore(&dev->event_lock, flags);
7941
b4a98e57
CW		 7942 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7943 flush_workqueue(dev_priv->wq);
7944
79158103
CW		 7945 ret = i915_mutex_lock_interruptible(dev);
7946 if (ret)
7947 goto cleanup;
6b95a207 7948
75dfca80 7949 /* Reference the objects for the scheduled work. */
05394f39
CW		 7950 drm_gem_object_reference(&work->old_fb_obj->base);
7951 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7952
7953 crtc->fb = fb;
96b099fd 7954
e1f99ce6 7955 work->pending_flip_obj = obj;
e1f99ce6 7956
4e5359cd
SF		 7957 work->enable_stall_check = true;
7958
b4a98e57 7959 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7960 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7961
8c9f3aaf
JB		 7962 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7963 if (ret)
7964 goto cleanup_pending;
6b95a207 7965
7782de3b 7966 intel_disable_fbc(dev);
c65355bb 7967 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7968 mutex_unlock(&dev->struct_mutex);
7969
e5510fac
JB		 7970 trace_i915_flip_request(intel_crtc->plane, obj);
7971
6b95a207 7972 return 0;
96b099fd 7973
8c9f3aaf 7974cleanup_pending:
b4a98e57 7975 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7976 crtc->fb = old_fb;
05394f39
CW		 7977 drm_gem_object_unreference(&work->old_fb_obj->base);
7978 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7979 mutex_unlock(&dev->struct_mutex);
7980
79158103 7981cleanup:
96b099fd
CW		 7982 spin_lock_irqsave(&dev->event_lock, flags);
7983 intel_crtc->unpin_work = NULL;
7984 spin_unlock_irqrestore(&dev->event_lock, flags);
7985
7317c75e
JB		 7986 drm_vblank_put(dev, intel_crtc->pipe);
7987free_work:
96b099fd
CW		 7988 kfree(work);
7989
7990 return ret;
6b95a207
KH		 7991}
7992
f6e5b160 7993static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7994 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7995 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7996};
7997
50f56119
DV		 7998static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7999 struct drm_crtc *crtc)
8000{
8001 struct drm_device *dev;
8002 struct drm_crtc *tmp;
8003 int crtc_mask = 1;
47f1c6c9 8004
50f56119 8005 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8006
50f56119 8007 dev = crtc->dev;
47f1c6c9 8008
50f56119
DV		 8009 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8010 if (tmp == crtc)
8011 break;
8012 crtc_mask <<= 1;
8013 }
47f1c6c9 8014
50f56119
DV		 8015 if (encoder->possible_crtcs & crtc_mask)
8016 return true;
8017 return false;
47f1c6c9 8018}
79e53945 8019
9a935856
DV		 8020/**
8021 * intel_modeset_update_staged_output_state
8022 *
8023 * Updates the staged output configuration state, e.g. after we've read out the
8024 * current hw state.
8025 */
8026static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8027{
9a935856
DV		 8028 struct intel_encoder *encoder;
8029 struct intel_connector *connector;
f6e5b160 8030
9a935856
DV		 8031 list_for_each_entry(connector, &dev->mode_config.connector_list,
8032 base.head) {
8033 connector->new_encoder =
8034 to_intel_encoder(connector->base.encoder);
8035 }
f6e5b160 8036
9a935856
DV		 8037 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8038 base.head) {
8039 encoder->new_crtc =
8040 to_intel_crtc(encoder->base.crtc);
8041 }
f6e5b160
CW		 8042}
8043
9a935856
DV		 8044/**
8045 * intel_modeset_commit_output_state
8046 *
8047 * This function copies the stage display pipe configuration to the real one.
8048 */
8049static void intel_modeset_commit_output_state(struct drm_device *dev)
8050{
8051 struct intel_encoder *encoder;
8052 struct intel_connector *connector;
f6e5b160 8053
9a935856
DV		 8054 list_for_each_entry(connector, &dev->mode_config.connector_list,
8055 base.head) {
8056 connector->base.encoder = &connector->new_encoder->base;
8057 }
f6e5b160 8058
9a935856
DV		 8059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8060 base.head) {
8061 encoder->base.crtc = &encoder->new_crtc->base;
8062 }
8063}
8064
050f7aeb
DV		 8065static void
8066connected_sink_compute_bpp(struct intel_connector * connector,
8067 struct intel_crtc_config *pipe_config)
8068{
8069 int bpp = pipe_config->pipe_bpp;
8070
8071 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8072 connector->base.base.id,
8073 drm_get_connector_name(&connector->base));
8074
8075 /* Don't use an invalid EDID bpc value */
8076 if (connector->base.display_info.bpc &&
8077 connector->base.display_info.bpc * 3 < bpp) {
8078 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8079 bpp, connector->base.display_info.bpc*3);
8080 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8081 }
8082
8083 /* Clamp bpp to 8 on screens without EDID 1.4 */
8084 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8085 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8086 bpp);
8087 pipe_config->pipe_bpp = 24;
8088 }
8089}
8090
4e53c2e0 8091static int
050f7aeb
DV		 8092compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8093 struct drm_framebuffer *fb,
8094 struct intel_crtc_config *pipe_config)
4e53c2e0 8095{
050f7aeb
DV		 8096 struct drm_device *dev = crtc->base.dev;
8097 struct intel_connector *connector;
4e53c2e0
DV		 8098 int bpp;
8099
d42264b1
DV		 8100 switch (fb->pixel_format) {
8101 case DRM_FORMAT_C8:
4e53c2e0
DV		 8102 bpp = 8*3; /* since we go through a colormap */
8103 break;
d42264b1
DV		 8104 case DRM_FORMAT_XRGB1555:
8105 case DRM_FORMAT_ARGB1555:
8106 /* checked in intel_framebuffer_init already */
8107 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8108 return -EINVAL;
8109 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8110 bpp = 6*3; /* min is 18bpp */
8111 break;
d42264b1
DV		 8112 case DRM_FORMAT_XBGR8888:
8113 case DRM_FORMAT_ABGR8888:
8114 /* checked in intel_framebuffer_init already */
8115 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8116 return -EINVAL;
8117 case DRM_FORMAT_XRGB8888:
8118 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8119 bpp = 8*3;
8120 break;
d42264b1
DV		 8121 case DRM_FORMAT_XRGB2101010:
8122 case DRM_FORMAT_ARGB2101010:
8123 case DRM_FORMAT_XBGR2101010:
8124 case DRM_FORMAT_ABGR2101010:
8125 /* checked in intel_framebuffer_init already */
8126 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8127 return -EINVAL;
4e53c2e0
DV		 8128 bpp = 10*3;
8129 break;
baba133a 8130 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8131 default:
8132 DRM_DEBUG_KMS("unsupported depth\n");
8133 return -EINVAL;
8134 }
8135
4e53c2e0
DV		 8136 pipe_config->pipe_bpp = bpp;
8137
8138 /* Clamp display bpp to EDID value */
8139 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8140 base.head) {
1b829e05
DV		 8141 if (!connector->new_encoder ||
8142 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8143 continue;
8144
050f7aeb 8145 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8146 }
8147
8148 return bpp;
8149}
8150
c0b03411
DV		 8151static void intel_dump_pipe_config(struct intel_crtc *crtc,
8152 struct intel_crtc_config *pipe_config,
8153 const char *context)
8154{
8155 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8156 context, pipe_name(crtc->pipe));
8157
8158 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8159 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8160 pipe_config->pipe_bpp, pipe_config->dither);
8161 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8162 pipe_config->has_pch_encoder,
8163 pipe_config->fdi_lanes,
8164 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8165 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8166 pipe_config->fdi_m_n.tu);
8167 DRM_DEBUG_KMS("requested mode:\n");
8168 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8169 DRM_DEBUG_KMS("adjusted mode:\n");
8170 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8171 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8172 pipe_config->gmch_pfit.control,
8173 pipe_config->gmch_pfit.pgm_ratios,
8174 pipe_config->gmch_pfit.lvds_border_bits);
8175 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8176 pipe_config->pch_pfit.pos,
8177 pipe_config->pch_pfit.size);
42db64ef 8178 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8179}
8180
accfc0c5
DV		 8181static bool check_encoder_cloning(struct drm_crtc *crtc)
8182{
8183 int num_encoders = 0;
8184 bool uncloneable_encoders = false;
8185 struct intel_encoder *encoder;
8186
8187 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8188 base.head) {
8189 if (&encoder->new_crtc->base != crtc)
8190 continue;
8191
8192 num_encoders++;
8193 if (!encoder->cloneable)
8194 uncloneable_encoders = true;
8195 }
8196
8197 return !(num_encoders > 1 && uncloneable_encoders);
8198}
8199
b8cecdf5
DV		 8200static struct intel_crtc_config *
8201intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8202 struct drm_framebuffer *fb,
b8cecdf5 8203 struct drm_display_mode *mode)
ee7b9f93 8204{
7758a113 8205 struct drm_device *dev = crtc->dev;
7758a113 8206 struct intel_encoder *encoder;
b8cecdf5 8207 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8208 int plane_bpp, ret = -EINVAL;
8209 bool retry = true;
ee7b9f93 8210
accfc0c5
DV		 8211 if (!check_encoder_cloning(crtc)) {
8212 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8213 return ERR_PTR(-EINVAL);
8214 }
8215
b8cecdf5
DV		 8216 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8217 if (!pipe_config)
7758a113
DV		 8218 return ERR_PTR(-ENOMEM);
8219
b8cecdf5
DV		 8220 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8221 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8222 pipe_config->cpu_transcoder =
8223 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8224 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8225
2960bc9c
ID		 8226 /*
8227 * Sanitize sync polarity flags based on requested ones. If neither
8228 * positive or negative polarity is requested, treat this as meaning
8229 * negative polarity.
8230 */
8231 if (!(pipe_config->adjusted_mode.flags &
8232 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8233 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8234
8235 if (!(pipe_config->adjusted_mode.flags &
8236 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8237 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8238
050f7aeb
DV		 8239 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8240 * plane pixel format and any sink constraints into account. Returns the
8241 * source plane bpp so that dithering can be selected on mismatches
8242 * after encoders and crtc also have had their say. */
8243 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8244 fb, pipe_config);
4e53c2e0
DV		 8245 if (plane_bpp < 0)
8246 goto fail;
8247
e29c22c0 8248encoder_retry:
ef1b460d 8249 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8250 pipe_config->port_clock = 0;
ef1b460d 8251 pipe_config->pixel_multiplier = 1;
ff9a6750 8252
135c81b8
DV		 8253 /* Fill in default crtc timings, allow encoders to overwrite them. */
8254 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8255
7758a113
DV		 8256 /* Pass our mode to the connectors and the CRTC to give them a chance to
8257 * adjust it according to limitations or connector properties, and also
8258 * a chance to reject the mode entirely.
47f1c6c9 8259 */
7758a113
DV		 8260 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8261 base.head) {
47f1c6c9 8262
7758a113
DV		 8263 if (&encoder->new_crtc->base != crtc)
8264 continue;
7ae89233 8265
efea6e8e
DV		 8266 if (!(encoder->compute_config(encoder, pipe_config))) {
8267 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8268 goto fail;
8269 }
ee7b9f93 8270 }
47f1c6c9 8271
ff9a6750
DV		 8272 /* Set default port clock if not overwritten by the encoder. Needs to be
8273 * done afterwards in case the encoder adjusts the mode. */
8274 if (!pipe_config->port_clock)
8275 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8276
a43f6e0f 8277 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8278 if (ret < 0) {
7758a113
DV		 8279 DRM_DEBUG_KMS("CRTC fixup failed\n");
8280 goto fail;
ee7b9f93 8281 }
e29c22c0
DV		 8282
8283 if (ret == RETRY) {
8284 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8285 ret = -EINVAL;
8286 goto fail;
8287 }
8288
8289 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8290 retry = false;
8291 goto encoder_retry;
8292 }
8293
4e53c2e0
DV		 8294 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8295 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8296 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8297
b8cecdf5 8298 return pipe_config;
7758a113 8299fail:
b8cecdf5 8300 kfree(pipe_config);
e29c22c0 8301 return ERR_PTR(ret);
ee7b9f93 8302}
47f1c6c9 8303
e2e1ed41
DV		 8304/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8305 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8306static void
8307intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8308 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8309{
8310 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8311 struct drm_device *dev = crtc->dev;
8312 struct intel_encoder *encoder;
8313 struct intel_connector *connector;
8314 struct drm_crtc *tmp_crtc;
79e53945 8315
e2e1ed41 8316 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8317
e2e1ed41
DV		 8318 /* Check which crtcs have changed outputs connected to them, these need
8319 * to be part of the prepare_pipes mask. We don't (yet) support global
8320 * modeset across multiple crtcs, so modeset_pipes will only have one
8321 * bit set at most. */
8322 list_for_each_entry(connector, &dev->mode_config.connector_list,
8323 base.head) {
8324 if (connector->base.encoder == &connector->new_encoder->base)
8325 continue;
79e53945 8326
e2e1ed41
DV		 8327 if (connector->base.encoder) {
8328 tmp_crtc = connector->base.encoder->crtc;
8329
8330 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8331 }
8332
8333 if (connector->new_encoder)
8334 *prepare_pipes |=
8335 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8336 }
8337
e2e1ed41
DV		 8338 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8339 base.head) {
8340 if (encoder->base.crtc == &encoder->new_crtc->base)
8341 continue;
8342
8343 if (encoder->base.crtc) {
8344 tmp_crtc = encoder->base.crtc;
8345
8346 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8347 }
8348
8349 if (encoder->new_crtc)
8350 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8351 }
8352
e2e1ed41
DV		 8353 /* Check for any pipes that will be fully disabled ... */
8354 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8355 base.head) {
8356 bool used = false;
22fd0fab 8357
e2e1ed41
DV		 8358 /* Don't try to disable disabled crtcs. */
8359 if (!intel_crtc->base.enabled)
8360 continue;
7e7d76c3 8361
e2e1ed41
DV		 8362 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8363 base.head) {
8364 if (encoder->new_crtc == intel_crtc)
8365 used = true;
8366 }
8367
8368 if (!used)
8369 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8370 }
8371
e2e1ed41
DV		 8372
8373 /* set_mode is also used to update properties on life display pipes. */
8374 intel_crtc = to_intel_crtc(crtc);
8375 if (crtc->enabled)
8376 *prepare_pipes |= 1 << intel_crtc->pipe;
8377
b6c5164d
DV		 8378 /*
8379 * For simplicity do a full modeset on any pipe where the output routing
8380 * changed. We could be more clever, but that would require us to be
8381 * more careful with calling the relevant encoder->mode_set functions.
8382 */
e2e1ed41
DV		 8383 if (*prepare_pipes)
8384 *modeset_pipes = *prepare_pipes;
8385
8386 /* ... and mask these out. */
8387 *modeset_pipes &= ~(*disable_pipes);
8388 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8389
8390 /*
8391 * HACK: We don't (yet) fully support global modesets. intel_set_config
8392 * obies this rule, but the modeset restore mode of
8393 * intel_modeset_setup_hw_state does not.
8394 */
8395 *modeset_pipes &= 1 << intel_crtc->pipe;
8396 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8397
8398 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8399 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8400}
79e53945 8401
ea9d758d 8402static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8403{
ea9d758d 8404 struct drm_encoder *encoder;
f6e5b160 8405 struct drm_device *dev = crtc->dev;
f6e5b160 8406
ea9d758d
DV		 8407 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8408 if (encoder->crtc == crtc)
8409 return true;
8410
8411 return false;
8412}
8413
8414static void
8415intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8416{
8417 struct intel_encoder *intel_encoder;
8418 struct intel_crtc *intel_crtc;
8419 struct drm_connector *connector;
8420
8421 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8422 base.head) {
8423 if (!intel_encoder->base.crtc)
8424 continue;
8425
8426 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8427
8428 if (prepare_pipes & (1 << intel_crtc->pipe))
8429 intel_encoder->connectors_active = false;
8430 }
8431
8432 intel_modeset_commit_output_state(dev);
8433
8434 /* Update computed state. */
8435 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8436 base.head) {
8437 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8438 }
8439
8440 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8441 if (!connector->encoder || !connector->encoder->crtc)
8442 continue;
8443
8444 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8445
8446 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8447 struct drm_property *dpms_property =
8448 dev->mode_config.dpms_property;
8449
ea9d758d 8450 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8451 drm_object_property_set_value(&connector->base,
68d34720
DV		 8452 dpms_property,
8453 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8454
8455 intel_encoder = to_intel_encoder(connector->encoder);
8456 intel_encoder->connectors_active = true;
8457 }
8458 }
8459
8460}
8461
f1f644dc
JB		 8462static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8463 struct intel_crtc_config *new)
8464{
8465 int clock1, clock2, diff;
8466
8467 clock1 = cur->adjusted_mode.clock;
8468 clock2 = new->adjusted_mode.clock;
8469
8470 if (clock1 == clock2)
8471 return true;
8472
8473 if (!clock1 || !clock2)
8474 return false;
8475
8476 diff = abs(clock1 - clock2);
8477
8478 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8479 return true;
8480
8481 return false;
8482}
8483
25c5b266
DV		 8484#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8485 list_for_each_entry((intel_crtc), \
8486 &(dev)->mode_config.crtc_list, \
8487 base.head) \
0973f18f 8488 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8489
0e8ffe1b 8490static bool
2fa2fe9a
DV		 8491intel_pipe_config_compare(struct drm_device *dev,
8492 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8493 struct intel_crtc_config *pipe_config)
8494{
66e985c0
DV		 8495#define PIPE_CONF_CHECK_X(name) \
8496 if (current_config->name != pipe_config->name) { \
8497 DRM_ERROR("mismatch in " #name " " \
8498 "(expected 0x%08x, found 0x%08x)\n", \
8499 current_config->name, \
8500 pipe_config->name); \
8501 return false; \
8502 }
8503
08a24034
DV		 8504#define PIPE_CONF_CHECK_I(name) \
8505 if (current_config->name != pipe_config->name) { \
8506 DRM_ERROR("mismatch in " #name " " \
8507 "(expected %i, found %i)\n", \
8508 current_config->name, \
8509 pipe_config->name); \
8510 return false; \
88adfff1
DV		 8511 }
8512
1bd1bd80
DV		 8513#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8514 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8515 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8516 "(expected %i, found %i)\n", \
8517 current_config->name & (mask), \
8518 pipe_config->name & (mask)); \
8519 return false; \
8520 }
8521
bb760063
DV		 8522#define PIPE_CONF_QUIRK(quirk) \
8523 ((current_config->quirks | pipe_config->quirks) & (quirk))
8524
eccb140b
DV		 8525 PIPE_CONF_CHECK_I(cpu_transcoder);
8526
08a24034
DV		 8527 PIPE_CONF_CHECK_I(has_pch_encoder);
8528 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8529 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8530 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8531 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8532 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8533 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8534
1bd1bd80
DV		 8535 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8536 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8537 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8538 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8539 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8540 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8541
8542 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8543 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8544 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8545 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8546 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8547 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8548
c93f54cf 8549 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8550
1bd1bd80
DV		 8551 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8552 DRM_MODE_FLAG_INTERLACE);
8553
bb760063
DV		 8554 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8555 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8556 DRM_MODE_FLAG_PHSYNC);
8557 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8558 DRM_MODE_FLAG_NHSYNC);
8559 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8560 DRM_MODE_FLAG_PVSYNC);
8561 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8562 DRM_MODE_FLAG_NVSYNC);
8563 }
045ac3b5 8564
1bd1bd80
DV		 8565 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8566 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8567
2fa2fe9a
DV		 8568 PIPE_CONF_CHECK_I(gmch_pfit.control);
8569 /* pfit ratios are autocomputed by the hw on gen4+ */
8570 if (INTEL_INFO(dev)->gen < 4)
8571 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8572 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8573 PIPE_CONF_CHECK_I(pch_pfit.pos);
8574 PIPE_CONF_CHECK_I(pch_pfit.size);
8575
42db64ef
PZ		 8576 PIPE_CONF_CHECK_I(ips_enabled);
8577
c0d43d62 8578 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8579 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8580 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8581 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8582 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8583
66e985c0 8584#undef PIPE_CONF_CHECK_X
08a24034 8585#undef PIPE_CONF_CHECK_I
1bd1bd80 8586#undef PIPE_CONF_CHECK_FLAGS
bb760063 8587#undef PIPE_CONF_QUIRK
88adfff1 8588
f1f644dc
JB		 8589 if (!IS_HASWELL(dev)) {
8590 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8591 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8592 current_config->adjusted_mode.clock,
8593 pipe_config->adjusted_mode.clock);
8594 return false;
8595 }
8596 }
8597
0e8ffe1b
DV		 8598 return true;
8599}
8600
91d1b4bd
DV		 8601static void
8602check_connector_state(struct drm_device *dev)
8af6cf88 8603{
8af6cf88
DV		 8604 struct intel_connector *connector;
8605
8606 list_for_each_entry(connector, &dev->mode_config.connector_list,
8607 base.head) {
8608 /* This also checks the encoder/connector hw state with the
8609 * ->get_hw_state callbacks. */
8610 intel_connector_check_state(connector);
8611
8612 WARN(&connector->new_encoder->base != connector->base.encoder,
8613 "connector's staged encoder doesn't match current encoder\n");
8614 }
91d1b4bd
DV		 8615}
8616
8617static void
8618check_encoder_state(struct drm_device *dev)
8619{
8620 struct intel_encoder *encoder;
8621 struct intel_connector *connector;
8af6cf88
DV		 8622
8623 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8624 base.head) {
8625 bool enabled = false;
8626 bool active = false;
8627 enum pipe pipe, tracked_pipe;
8628
8629 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8630 encoder->base.base.id,
8631 drm_get_encoder_name(&encoder->base));
8632
8633 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8634 "encoder's stage crtc doesn't match current crtc\n");
8635 WARN(encoder->connectors_active && !encoder->base.crtc,
8636 "encoder's active_connectors set, but no crtc\n");
8637
8638 list_for_each_entry(connector, &dev->mode_config.connector_list,
8639 base.head) {
8640 if (connector->base.encoder != &encoder->base)
8641 continue;
8642 enabled = true;
8643 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8644 active = true;
8645 }
8646 WARN(!!encoder->base.crtc != enabled,
8647 "encoder's enabled state mismatch "
8648 "(expected %i, found %i)\n",
8649 !!encoder->base.crtc, enabled);
8650 WARN(active && !encoder->base.crtc,
8651 "active encoder with no crtc\n");
8652
8653 WARN(encoder->connectors_active != active,
8654 "encoder's computed active state doesn't match tracked active state "
8655 "(expected %i, found %i)\n", active, encoder->connectors_active);
8656
8657 active = encoder->get_hw_state(encoder, &pipe);
8658 WARN(active != encoder->connectors_active,
8659 "encoder's hw state doesn't match sw tracking "
8660 "(expected %i, found %i)\n",
8661 encoder->connectors_active, active);
8662
8663 if (!encoder->base.crtc)
8664 continue;
8665
8666 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8667 WARN(active && pipe != tracked_pipe,
8668 "active encoder's pipe doesn't match"
8669 "(expected %i, found %i)\n",
8670 tracked_pipe, pipe);
8671
8672 }
91d1b4bd
DV		 8673}
8674
8675static void
8676check_crtc_state(struct drm_device *dev)
8677{
8678 drm_i915_private_t *dev_priv = dev->dev_private;
8679 struct intel_crtc *crtc;
8680 struct intel_encoder *encoder;
8681 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8682
8683 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8684 base.head) {
8685 bool enabled = false;
8686 bool active = false;
8687
045ac3b5
JB		 8688 memset(&pipe_config, 0, sizeof(pipe_config));
8689
8af6cf88
DV		 8690 DRM_DEBUG_KMS("[CRTC:%d]\n",
8691 crtc->base.base.id);
8692
8693 WARN(crtc->active && !crtc->base.enabled,
8694 "active crtc, but not enabled in sw tracking\n");
8695
8696 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8697 base.head) {
8698 if (encoder->base.crtc != &crtc->base)
8699 continue;
8700 enabled = true;
8701 if (encoder->connectors_active)
8702 active = true;
8703 }
6c49f241 8704
8af6cf88
DV		 8705 WARN(active != crtc->active,
8706 "crtc's computed active state doesn't match tracked active state "
8707 "(expected %i, found %i)\n", active, crtc->active);
8708 WARN(enabled != crtc->base.enabled,
8709 "crtc's computed enabled state doesn't match tracked enabled state "
8710 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8711
0e8ffe1b
DV		 8712 active = dev_priv->display.get_pipe_config(crtc,
8713 &pipe_config);
d62cf62a
DV		 8714
8715 /* hw state is inconsistent with the pipe A quirk */
8716 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8717 active = crtc->active;
8718
6c49f241
DV		 8719 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8720 base.head) {
8721 if (encoder->base.crtc != &crtc->base)
8722 continue;
510d5f2f 8723 if (encoder->get_config)
6c49f241
DV		 8724 encoder->get_config(encoder, &pipe_config);
8725 }
8726
510d5f2f
JB		 8727 if (dev_priv->display.get_clock)
8728 dev_priv->display.get_clock(crtc, &pipe_config);
8729
0e8ffe1b
DV		 8730 WARN(crtc->active != active,
8731 "crtc active state doesn't match with hw state "
8732 "(expected %i, found %i)\n", crtc->active, active);
8733
c0b03411
DV		 8734 if (active &&
8735 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8736 WARN(1, "pipe state doesn't match!\n");
8737 intel_dump_pipe_config(crtc, &pipe_config,
8738 "[hw state]");
8739 intel_dump_pipe_config(crtc, &crtc->config,
8740 "[sw state]");
8741 }
8af6cf88
DV		 8742 }
8743}
8744
91d1b4bd
DV		 8745static void
8746check_shared_dpll_state(struct drm_device *dev)
8747{
8748 drm_i915_private_t *dev_priv = dev->dev_private;
8749 struct intel_crtc *crtc;
8750 struct intel_dpll_hw_state dpll_hw_state;
8751 int i;
5358901f
DV		 8752
8753 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8754 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8755 int enabled_crtcs = 0, active_crtcs = 0;
8756 bool active;
8757
8758 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8759
8760 DRM_DEBUG_KMS("%s\n", pll->name);
8761
8762 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8763
8764 WARN(pll->active > pll->refcount,
8765 "more active pll users than references: %i vs %i\n",
8766 pll->active, pll->refcount);
8767 WARN(pll->active && !pll->on,
8768 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8769 WARN(pll->on && !pll->active,
8770 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8771 WARN(pll->on != active,
8772 "pll on state mismatch (expected %i, found %i)\n",
8773 pll->on, active);
8774
8775 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8776 base.head) {
8777 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8778 enabled_crtcs++;
8779 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8780 active_crtcs++;
8781 }
8782 WARN(pll->active != active_crtcs,
8783 "pll active crtcs mismatch (expected %i, found %i)\n",
8784 pll->active, active_crtcs);
8785 WARN(pll->refcount != enabled_crtcs,
8786 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8787 pll->refcount, enabled_crtcs);
66e985c0
DV		 8788
8789 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8790 sizeof(dpll_hw_state)),
8791 "pll hw state mismatch\n");
5358901f 8792 }
8af6cf88
DV		 8793}
8794
91d1b4bd
DV		 8795void
8796intel_modeset_check_state(struct drm_device *dev)
8797{
8798 check_connector_state(dev);
8799 check_encoder_state(dev);
8800 check_crtc_state(dev);
8801 check_shared_dpll_state(dev);
8802}
8803
f30da187
DV		 8804static int __intel_set_mode(struct drm_crtc *crtc,
8805 struct drm_display_mode *mode,
8806 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8807{
8808 struct drm_device *dev = crtc->dev;
dbf2b54e 8809 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8810 struct drm_display_mode *saved_mode, *saved_hwmode;
8811 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8812 struct intel_crtc *intel_crtc;
8813 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8814 int ret = 0;
a6778b3c 8815
3ac18232 8816 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8817 if (!saved_mode)
8818 return -ENOMEM;
3ac18232 8819 saved_hwmode = saved_mode + 1;
a6778b3c 8820
e2e1ed41 8821 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8822 &prepare_pipes, &disable_pipes);
8823
3ac18232
TG		 8824 *saved_hwmode = crtc->hwmode;
8825 *saved_mode = crtc->mode;
a6778b3c 8826
25c5b266
DV		 8827 /* Hack: Because we don't (yet) support global modeset on multiple
8828 * crtcs, we don't keep track of the new mode for more than one crtc.
8829 * Hence simply check whether any bit is set in modeset_pipes in all the
8830 * pieces of code that are not yet converted to deal with mutliple crtcs
8831 * changing their mode at the same time. */
25c5b266 8832 if (modeset_pipes) {
4e53c2e0 8833 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8834 if (IS_ERR(pipe_config)) {
8835 ret = PTR_ERR(pipe_config);
8836 pipe_config = NULL;
8837
3ac18232 8838 goto out;
25c5b266 8839 }
c0b03411
DV		 8840 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8841 "[modeset]");
25c5b266 8842 }
a6778b3c 8843
460da916
DV		 8844 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8845 intel_crtc_disable(&intel_crtc->base);
8846
ea9d758d
DV		 8847 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8848 if (intel_crtc->base.enabled)
8849 dev_priv->display.crtc_disable(&intel_crtc->base);
8850 }
a6778b3c 8851
6c4c86f5
DV		 8852 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8853 * to set it here already despite that we pass it down the callchain.
f6e5b160 8854 */
b8cecdf5 8855 if (modeset_pipes) {
25c5b266 8856 crtc->mode = *mode;
b8cecdf5
DV		 8857 /* mode_set/enable/disable functions rely on a correct pipe
8858 * config. */
8859 to_intel_crtc(crtc)->config = *pipe_config;
8860 }
7758a113 8861
ea9d758d
DV		 8862 /* Only after disabling all output pipelines that will be changed can we
8863 * update the the output configuration. */
8864 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8865
47fab737
DV		 8866 if (dev_priv->display.modeset_global_resources)
8867 dev_priv->display.modeset_global_resources(dev);
8868
a6778b3c
DV		 8869 /* Set up the DPLL and any encoders state that needs to adjust or depend
8870 * on the DPLL.
f6e5b160 8871 */
25c5b266 8872 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8873 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8874 x, y, fb);
8875 if (ret)
8876 goto done;
a6778b3c
DV		 8877 }
8878
8879 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8880 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8881 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8882
25c5b266
DV		 8883 if (modeset_pipes) {
8884 /* Store real post-adjustment hardware mode. */
b8cecdf5 8885 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8886
25c5b266
DV		 8887 /* Calculate and store various constants which
8888 * are later needed by vblank and swap-completion
8889 * timestamping. They are derived from true hwmode.
8890 */
8891 drm_calc_timestamping_constants(crtc);
8892 }
a6778b3c
DV		 8893
8894 /* FIXME: add subpixel order */
8895done:
c0c36b94 8896 if (ret && crtc->enabled) {
3ac18232
TG		 8897 crtc->hwmode = *saved_hwmode;
8898 crtc->mode = *saved_mode;
a6778b3c
DV		 8899 }
8900
3ac18232 8901out:
b8cecdf5 8902 kfree(pipe_config);
3ac18232 8903 kfree(saved_mode);
a6778b3c 8904 return ret;
f6e5b160
CW		 8905}
8906
e7457a9a
DL		 8907static int intel_set_mode(struct drm_crtc *crtc,
8908 struct drm_display_mode *mode,
8909 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 8910{
8911 int ret;
8912
8913 ret = __intel_set_mode(crtc, mode, x, y, fb);
8914
8915 if (ret == 0)
8916 intel_modeset_check_state(crtc->dev);
8917
8918 return ret;
8919}
8920
c0c36b94
CW		 8921void intel_crtc_restore_mode(struct drm_crtc *crtc)
8922{
8923 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8924}
8925
25c5b266
DV		 8926#undef for_each_intel_crtc_masked
8927
d9e55608
DV		 8928static void intel_set_config_free(struct intel_set_config *config)
8929{
8930 if (!config)
8931 return;
8932
1aa4b628
DV		 8933 kfree(config->save_connector_encoders);
8934 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8935 kfree(config);
8936}
8937
85f9eb71
DV		 8938static int intel_set_config_save_state(struct drm_device *dev,
8939 struct intel_set_config *config)
8940{
85f9eb71
DV		 8941 struct drm_encoder *encoder;
8942 struct drm_connector *connector;
8943 int count;
8944
1aa4b628
DV		 8945 config->save_encoder_crtcs =
8946 kcalloc(dev->mode_config.num_encoder,
8947 sizeof(struct drm_crtc *), GFP_KERNEL);
8948 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8949 return -ENOMEM;
8950
1aa4b628
DV		 8951 config->save_connector_encoders =
8952 kcalloc(dev->mode_config.num_connector,
8953 sizeof(struct drm_encoder *), GFP_KERNEL);
8954 if (!config->save_connector_encoders)
85f9eb71
DV		 8955 return -ENOMEM;
8956
8957 /* Copy data. Note that driver private data is not affected.
8958 * Should anything bad happen only the expected state is
8959 * restored, not the drivers personal bookkeeping.
8960 */
85f9eb71
DV		 8961 count = 0;
8962 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8963 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8964 }
8965
8966 count = 0;
8967 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8968 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8969 }
8970
8971 return 0;
8972}
8973
8974static void intel_set_config_restore_state(struct drm_device *dev,
8975 struct intel_set_config *config)
8976{
9a935856
DV		 8977 struct intel_encoder *encoder;
8978 struct intel_connector *connector;
85f9eb71
DV		 8979 int count;
8980
85f9eb71 8981 count = 0;
9a935856
DV		 8982 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8983 encoder->new_crtc =
8984 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8985 }
8986
8987 count = 0;
9a935856
DV		 8988 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8989 connector->new_encoder =
8990 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8991 }
8992}
8993
e3de42b6 8994static bool
2e57f47d 8995is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 8996{
8997 int i;
8998
2e57f47d
CW		 8999 if (set->num_connectors == 0)
9000 return false;
9001
9002 if (WARN_ON(set->connectors == NULL))
9003 return false;
9004
9005 for (i = 0; i < set->num_connectors; i++)
9006 if (set->connectors[i]->encoder &&
9007 set->connectors[i]->encoder->crtc == set->crtc &&
9008 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9009 return true;
9010
9011 return false;
9012}
9013
5e2b584e
DV		 9014static void
9015intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9016 struct intel_set_config *config)
9017{
9018
9019 /* We should be able to check here if the fb has the same properties
9020 * and then just flip_or_move it */
2e57f47d
CW		 9021 if (is_crtc_connector_off(set)) {
9022 config->mode_changed = true;
e3de42b6 9023 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9024 /* If we have no fb then treat it as a full mode set */
9025 if (set->crtc->fb == NULL) {
319d9827
JB		 9026 struct intel_crtc *intel_crtc =
9027 to_intel_crtc(set->crtc);
9028
9029 if (intel_crtc->active && i915_fastboot) {
9030 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9031 config->fb_changed = true;
9032 } else {
9033 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9034 config->mode_changed = true;
9035 }
5e2b584e
DV		 9036 } else if (set->fb == NULL) {
9037 config->mode_changed = true;
72f4901e
DV		 9038 } else if (set->fb->pixel_format !=
9039 set->crtc->fb->pixel_format) {
5e2b584e 9040 config->mode_changed = true;
e3de42b6 9041 } else {
5e2b584e 9042 config->fb_changed = true;
e3de42b6 9043 }
5e2b584e
DV		 9044 }
9045
835c5873 9046 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9047 config->fb_changed = true;
9048
9049 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9050 DRM_DEBUG_KMS("modes are different, full mode set\n");
9051 drm_mode_debug_printmodeline(&set->crtc->mode);
9052 drm_mode_debug_printmodeline(set->mode);
9053 config->mode_changed = true;
9054 }
a1d95703
CW		 9055
9056 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9057 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9058}
9059
2e431051 9060static int
9a935856
DV		 9061intel_modeset_stage_output_state(struct drm_device *dev,
9062 struct drm_mode_set *set,
9063 struct intel_set_config *config)
50f56119 9064{
85f9eb71 9065 struct drm_crtc *new_crtc;
9a935856
DV		 9066 struct intel_connector *connector;
9067 struct intel_encoder *encoder;
f3f08572 9068 int ro;
50f56119 9069
9abdda74 9070 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9071 * of connectors. For paranoia, double-check this. */
9072 WARN_ON(!set->fb && (set->num_connectors != 0));
9073 WARN_ON(set->fb && (set->num_connectors == 0));
9074
9a935856
DV		 9075 list_for_each_entry(connector, &dev->mode_config.connector_list,
9076 base.head) {
9077 /* Otherwise traverse passed in connector list and get encoders
9078 * for them. */
50f56119 9079 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9080 if (set->connectors[ro] == &connector->base) {
9081 connector->new_encoder = connector->encoder;
50f56119
DV		 9082 break;
9083 }
9084 }
9085
9a935856
DV		 9086 /* If we disable the crtc, disable all its connectors. Also, if
9087 * the connector is on the changing crtc but not on the new
9088 * connector list, disable it. */
9089 if ((!set->fb || ro == set->num_connectors) &&
9090 connector->base.encoder &&
9091 connector->base.encoder->crtc == set->crtc) {
9092 connector->new_encoder = NULL;
9093
9094 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9095 connector->base.base.id,
9096 drm_get_connector_name(&connector->base));
9097 }
9098
9099
9100 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9101 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9102 config->mode_changed = true;
50f56119
DV		 9103 }
9104 }
9a935856 9105 /* connector->new_encoder is now updated for all connectors. */
50f56119 9106
9a935856 9107 /* Update crtc of enabled connectors. */
9a935856
DV		 9108 list_for_each_entry(connector, &dev->mode_config.connector_list,
9109 base.head) {
9110 if (!connector->new_encoder)
50f56119
DV		 9111 continue;
9112
9a935856 9113 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9114
9115 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9116 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9117 new_crtc = set->crtc;
9118 }
9119
9120 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9121 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9122 new_crtc)) {
5e2b584e 9123 return -EINVAL;
50f56119 9124 }
9a935856
DV		 9125 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9126
9127 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9128 connector->base.base.id,
9129 drm_get_connector_name(&connector->base),
9130 new_crtc->base.id);
9131 }
9132
9133 /* Check for any encoders that needs to be disabled. */
9134 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9135 base.head) {
9136 list_for_each_entry(connector,
9137 &dev->mode_config.connector_list,
9138 base.head) {
9139 if (connector->new_encoder == encoder) {
9140 WARN_ON(!connector->new_encoder->new_crtc);
9141
9142 goto next_encoder;
9143 }
9144 }
9145 encoder->new_crtc = NULL;
9146next_encoder:
9147 /* Only now check for crtc changes so we don't miss encoders
9148 * that will be disabled. */
9149 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9150 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9151 config->mode_changed = true;
50f56119
DV		 9152 }
9153 }
9a935856 9154 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9155
2e431051
DV		 9156 return 0;
9157}
9158
9159static int intel_crtc_set_config(struct drm_mode_set *set)
9160{
9161 struct drm_device *dev;
2e431051
DV		 9162 struct drm_mode_set save_set;
9163 struct intel_set_config *config;
9164 int ret;
2e431051 9165
8d3e375e
DV		 9166 BUG_ON(!set);
9167 BUG_ON(!set->crtc);
9168 BUG_ON(!set->crtc->helper_private);
2e431051 9169
7e53f3a4
DV		 9170 /* Enforce sane interface api - has been abused by the fb helper. */
9171 BUG_ON(!set->mode && set->fb);
9172 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9173
2e431051
DV		 9174 if (set->fb) {
9175 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9176 set->crtc->base.id, set->fb->base.id,
9177 (int)set->num_connectors, set->x, set->y);
9178 } else {
9179 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9180 }
9181
9182 dev = set->crtc->dev;
9183
9184 ret = -ENOMEM;
9185 config = kzalloc(sizeof(*config), GFP_KERNEL);
9186 if (!config)
9187 goto out_config;
9188
9189 ret = intel_set_config_save_state(dev, config);
9190 if (ret)
9191 goto out_config;
9192
9193 save_set.crtc = set->crtc;
9194 save_set.mode = &set->crtc->mode;
9195 save_set.x = set->crtc->x;
9196 save_set.y = set->crtc->y;
9197 save_set.fb = set->crtc->fb;
9198
9199 /* Compute whether we need a full modeset, only an fb base update or no
9200 * change at all. In the future we might also check whether only the
9201 * mode changed, e.g. for LVDS where we only change the panel fitter in
9202 * such cases. */
9203 intel_set_config_compute_mode_changes(set, config);
9204
9a935856 9205 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9206 if (ret)
9207 goto fail;
9208
5e2b584e 9209 if (config->mode_changed) {
c0c36b94
CW		 9210 ret = intel_set_mode(set->crtc, set->mode,
9211 set->x, set->y, set->fb);
5e2b584e 9212 } else if (config->fb_changed) {
4878cae2
VS		 9213 intel_crtc_wait_for_pending_flips(set->crtc);
9214
4f660f49 9215 ret = intel_pipe_set_base(set->crtc,
94352cf9 9216 set->x, set->y, set->fb);
50f56119
DV		 9217 }
9218
2d05eae1 9219 if (ret) {
bf67dfeb
DV		 9220 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9221 set->crtc->base.id, ret);
50f56119 9222fail:
2d05eae1 9223 intel_set_config_restore_state(dev, config);
50f56119 9224
2d05eae1
CW		 9225 /* Try to restore the config */
9226 if (config->mode_changed &&
9227 intel_set_mode(save_set.crtc, save_set.mode,
9228 save_set.x, save_set.y, save_set.fb))
9229 DRM_ERROR("failed to restore config after modeset failure\n");
9230 }
50f56119 9231
d9e55608
DV		 9232out_config:
9233 intel_set_config_free(config);
50f56119
DV		 9234 return ret;
9235}
f6e5b160
CW		 9236
9237static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9238 .cursor_set = intel_crtc_cursor_set,
9239 .cursor_move = intel_crtc_cursor_move,
9240 .gamma_set = intel_crtc_gamma_set,
50f56119 9241 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9242 .destroy = intel_crtc_destroy,
9243 .page_flip = intel_crtc_page_flip,
9244};
9245
79f689aa
PZ		 9246static void intel_cpu_pll_init(struct drm_device *dev)
9247{
affa9354 9248 if (HAS_DDI(dev))
79f689aa
PZ		 9249 intel_ddi_pll_init(dev);
9250}
9251
5358901f
DV		 9252static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9253 struct intel_shared_dpll *pll,
9254 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9255{
5358901f 9256 uint32_t val;
ee7b9f93 9257
5358901f 9258 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9259 hw_state->dpll = val;
9260 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9261 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9262
9263 return val & DPLL_VCO_ENABLE;
9264}
9265
15bdd4cf
DV		 9266static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9267 struct intel_shared_dpll *pll)
9268{
9269 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9270 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9271}
9272
e7b903d2
DV		 9273static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9274 struct intel_shared_dpll *pll)
9275{
e7b903d2
DV		 9276 /* PCH refclock must be enabled first */
9277 assert_pch_refclk_enabled(dev_priv);
9278
15bdd4cf
DV		 9279 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9280
9281 /* Wait for the clocks to stabilize. */
9282 POSTING_READ(PCH_DPLL(pll->id));
9283 udelay(150);
9284
9285 /* The pixel multiplier can only be updated once the
9286 * DPLL is enabled and the clocks are stable.
9287 *
9288 * So write it again.
9289 */
9290 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9291 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9292 udelay(200);
9293}
9294
9295static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9296 struct intel_shared_dpll *pll)
9297{
9298 struct drm_device *dev = dev_priv->dev;
9299 struct intel_crtc *crtc;
e7b903d2
DV		 9300
9301 /* Make sure no transcoder isn't still depending on us. */
9302 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9303 if (intel_crtc_to_shared_dpll(crtc) == pll)
9304 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9305 }
9306
15bdd4cf
DV		 9307 I915_WRITE(PCH_DPLL(pll->id), 0);
9308 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9309 udelay(200);
9310}
9311
46edb027
DV		 9312static char *ibx_pch_dpll_names[] = {
9313 "PCH DPLL A",
9314 "PCH DPLL B",
9315};
9316
7c74ade1 9317static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9318{
e7b903d2 9319 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9320 int i;
9321
7c74ade1 9322 dev_priv->num_shared_dpll = 2;
ee7b9f93 9323
e72f9fbf 9324 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9325 dev_priv->shared_dplls[i].id = i;
9326 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9327 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9328 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9329 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9330 dev_priv->shared_dplls[i].get_hw_state =
9331 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9332 }
9333}
9334
7c74ade1
DV		 9335static void intel_shared_dpll_init(struct drm_device *dev)
9336{
e7b903d2 9337 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9338
9339 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9340 ibx_pch_dpll_init(dev);
9341 else
9342 dev_priv->num_shared_dpll = 0;
9343
9344 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9345 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9346 dev_priv->num_shared_dpll);
9347}
9348
b358d0a6 9349static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9350{
22fd0fab 9351 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9352 struct intel_crtc *intel_crtc;
9353 int i;
9354
9355 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9356 if (intel_crtc == NULL)
9357 return;
9358
9359 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9360
9361 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9362 for (i = 0; i < 256; i++) {
9363 intel_crtc->lut_r[i] = i;
9364 intel_crtc->lut_g[i] = i;
9365 intel_crtc->lut_b[i] = i;
9366 }
9367
80824003
JB		 9368 /* Swap pipes & planes for FBC on pre-965 */
9369 intel_crtc->pipe = pipe;
9370 intel_crtc->plane = pipe;
e2e767ab 9371 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9372 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9373 intel_crtc->plane = !pipe;
80824003
JB		 9374 }
9375
22fd0fab
JB		 9376 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9377 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9378 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9379 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9380
79e53945 9381 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9382}
9383
08d7b3d1 9384int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9385 struct drm_file *file)
08d7b3d1 9386{
08d7b3d1 9387 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9388 struct drm_mode_object *drmmode_obj;
9389 struct intel_crtc *crtc;
08d7b3d1 9390
1cff8f6b
DV		 9391 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9392 return -ENODEV;
08d7b3d1 9393
c05422d5
DV		 9394 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9395 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9396
c05422d5 9397 if (!drmmode_obj) {
08d7b3d1
CW		 9398 DRM_ERROR("no such CRTC id\n");
9399 return -EINVAL;
9400 }
9401
c05422d5
DV		 9402 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9403 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9404
c05422d5 9405 return 0;
08d7b3d1
CW		 9406}
9407
66a9278e 9408static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9409{
66a9278e
DV		 9410 struct drm_device *dev = encoder->base.dev;
9411 struct intel_encoder *source_encoder;
79e53945 9412 int index_mask = 0;
79e53945
JB		 9413 int entry = 0;
9414
66a9278e
DV		 9415 list_for_each_entry(source_encoder,
9416 &dev->mode_config.encoder_list, base.head) {
9417
9418 if (encoder == source_encoder)
79e53945 9419 index_mask |= (1 << entry);
66a9278e
DV		 9420
9421 /* Intel hw has only one MUX where enocoders could be cloned. */
9422 if (encoder->cloneable && source_encoder->cloneable)
9423 index_mask |= (1 << entry);
9424
79e53945
JB		 9425 entry++;
9426 }
4ef69c7a 9427
79e53945
JB		 9428 return index_mask;
9429}
9430
4d302442
CW		 9431static bool has_edp_a(struct drm_device *dev)
9432{
9433 struct drm_i915_private *dev_priv = dev->dev_private;
9434
9435 if (!IS_MOBILE(dev))
9436 return false;
9437
9438 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9439 return false;
9440
9441 if (IS_GEN5(dev) &&
9442 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9443 return false;
9444
9445 return true;
9446}
9447
79e53945
JB		 9448static void intel_setup_outputs(struct drm_device *dev)
9449{
725e30ad 9450 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9451 struct intel_encoder *encoder;
cb0953d7 9452 bool dpd_is_edp = false;
79e53945 9453
c9093354 9454 intel_lvds_init(dev);
79e53945 9455
c40c0f5b 9456 if (!IS_ULT(dev))
79935fca 9457 intel_crt_init(dev);
cb0953d7 9458
affa9354 9459 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9460 int found;
9461
9462 /* Haswell uses DDI functions to detect digital outputs */
9463 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9464 /* DDI A only supports eDP */
9465 if (found)
9466 intel_ddi_init(dev, PORT_A);
9467
9468 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9469 * register */
9470 found = I915_READ(SFUSE_STRAP);
9471
9472 if (found & SFUSE_STRAP_DDIB_DETECTED)
9473 intel_ddi_init(dev, PORT_B);
9474 if (found & SFUSE_STRAP_DDIC_DETECTED)
9475 intel_ddi_init(dev, PORT_C);
9476 if (found & SFUSE_STRAP_DDID_DETECTED)
9477 intel_ddi_init(dev, PORT_D);
9478 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9479 int found;
270b3042
DV		 9480 dpd_is_edp = intel_dpd_is_edp(dev);
9481
9482 if (has_edp_a(dev))
9483 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9484
dc0fa718 9485 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9486 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9487 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9488 if (!found)
e2debe91 9489 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9490 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9491 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9492 }
9493
dc0fa718 9494 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9495 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9496
dc0fa718 9497 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9498 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9499
5eb08b69 9500 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9501 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9502
270b3042 9503 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9504 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9505 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9506 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9507 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9508 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9509 PORT_C);
9510 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9511 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9512 PORT_C);
9513 }
19c03924 9514
dc0fa718 9515 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9516 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9517 PORT_B);
67cfc203
VS		 9518 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9519 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9520 }
103a196f 9521 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9522 bool found = false;
7d57382e 9523
e2debe91 9524 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9525 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9526 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9527 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9528 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9529 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9530 }
27185ae1 9531
e7281eab 9532 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9533 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9534 }
13520b05
KH		 9535
9536 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9537
e2debe91 9538 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9539 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9540 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9541 }
27185ae1 9542
e2debe91 9543 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9544
b01f2c3a
JB		 9545 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9546 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9547 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9548 }
e7281eab 9549 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9550 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9551 }
27185ae1 9552
b01f2c3a 9553 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9554 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9555 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9556 } else if (IS_GEN2(dev))
79e53945
JB		 9557 intel_dvo_init(dev);
9558
103a196f 9559 if (SUPPORTS_TV(dev))
79e53945
JB		 9560 intel_tv_init(dev);
9561
4ef69c7a
CW		 9562 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9563 encoder->base.possible_crtcs = encoder->crtc_mask;
9564 encoder->base.possible_clones =
66a9278e 9565 intel_encoder_clones(encoder);
79e53945 9566 }
47356eb6 9567
dde86e2d 9568 intel_init_pch_refclk(dev);
270b3042
DV		 9569
9570 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9571}
9572
ddfe1567
CW		 9573void intel_framebuffer_fini(struct intel_framebuffer *fb)
9574{
9575 drm_framebuffer_cleanup(&fb->base);
9576 drm_gem_object_unreference_unlocked(&fb->obj->base);
9577}
9578
79e53945
JB		 9579static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9580{
9581 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9582
ddfe1567 9583 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9584 kfree(intel_fb);
9585}
9586
9587static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9588 struct drm_file *file,
79e53945
JB		 9589 unsigned int *handle)
9590{
9591 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9592 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9593
05394f39 9594 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9595}
9596
9597static const struct drm_framebuffer_funcs intel_fb_funcs = {
9598 .destroy = intel_user_framebuffer_destroy,
9599 .create_handle = intel_user_framebuffer_create_handle,
9600};
9601
38651674
DA		 9602int intel_framebuffer_init(struct drm_device *dev,
9603 struct intel_framebuffer *intel_fb,
308e5bcb 9604 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9605 struct drm_i915_gem_object *obj)
79e53945 9606{
a35cdaa0 9607 int pitch_limit;
79e53945
JB		 9608 int ret;
9609
c16ed4be
CW		 9610 if (obj->tiling_mode == I915_TILING_Y) {
9611 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9612 return -EINVAL;
c16ed4be 9613 }
57cd6508 9614
c16ed4be
CW		 9615 if (mode_cmd->pitches[0] & 63) {
9616 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9617 mode_cmd->pitches[0]);
57cd6508 9618 return -EINVAL;
c16ed4be 9619 }
57cd6508 9620
a35cdaa0
CW		 9621 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9622 pitch_limit = 32*1024;
9623 } else if (INTEL_INFO(dev)->gen >= 4) {
9624 if (obj->tiling_mode)
9625 pitch_limit = 16*1024;
9626 else
9627 pitch_limit = 32*1024;
9628 } else if (INTEL_INFO(dev)->gen >= 3) {
9629 if (obj->tiling_mode)
9630 pitch_limit = 8*1024;
9631 else
9632 pitch_limit = 16*1024;
9633 } else
9634 /* XXX DSPC is limited to 4k tiled */
9635 pitch_limit = 8*1024;
9636
9637 if (mode_cmd->pitches[0] > pitch_limit) {
9638 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9639 obj->tiling_mode ? "tiled" : "linear",
9640 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9641 return -EINVAL;
c16ed4be 9642 }
5d7bd705
VS		 9643
9644 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9645 mode_cmd->pitches[0] != obj->stride) {
9646 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9647 mode_cmd->pitches[0], obj->stride);
5d7bd705 9648 return -EINVAL;
c16ed4be 9649 }
5d7bd705 9650
57779d06 9651 /* Reject formats not supported by any plane early. */
308e5bcb 9652 switch (mode_cmd->pixel_format) {
57779d06 9653 case DRM_FORMAT_C8:
04b3924d
VS		 9654 case DRM_FORMAT_RGB565:
9655 case DRM_FORMAT_XRGB8888:
9656 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9657 break;
9658 case DRM_FORMAT_XRGB1555:
9659 case DRM_FORMAT_ARGB1555:
c16ed4be 9660 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9661 DRM_DEBUG("unsupported pixel format: %s\n",
9662 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9663 return -EINVAL;
c16ed4be 9664 }
57779d06
VS		 9665 break;
9666 case DRM_FORMAT_XBGR8888:
9667 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9668 case DRM_FORMAT_XRGB2101010:
9669 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9670 case DRM_FORMAT_XBGR2101010:
9671 case DRM_FORMAT_ABGR2101010:
c16ed4be 9672 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9673 DRM_DEBUG("unsupported pixel format: %s\n",
9674 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9675 return -EINVAL;
c16ed4be 9676 }
b5626747 9677 break;
04b3924d
VS		 9678 case DRM_FORMAT_YUYV:
9679 case DRM_FORMAT_UYVY:
9680 case DRM_FORMAT_YVYU:
9681 case DRM_FORMAT_VYUY:
c16ed4be 9682 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9683 DRM_DEBUG("unsupported pixel format: %s\n",
9684 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9685 return -EINVAL;
c16ed4be 9686 }
57cd6508
CW		 9687 break;
9688 default:
4ee62c76
VS		 9689 DRM_DEBUG("unsupported pixel format: %s\n",
9690 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9691 return -EINVAL;
9692 }
9693
90f9a336
VS		 9694 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9695 if (mode_cmd->offsets[0] != 0)
9696 return -EINVAL;
9697
c7d73f6a
DV		 9698 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9699 intel_fb->obj = obj;
9700
79e53945
JB		 9701 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9702 if (ret) {
9703 DRM_ERROR("framebuffer init failed %d\n", ret);
9704 return ret;
9705 }
9706
79e53945
JB		 9707 return 0;
9708}
9709
79e53945
JB		 9710static struct drm_framebuffer *
9711intel_user_framebuffer_create(struct drm_device *dev,
9712 struct drm_file *filp,
308e5bcb 9713 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9714{
05394f39 9715 struct drm_i915_gem_object *obj;
79e53945 9716
308e5bcb
JB		 9717 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9718 mode_cmd->handles[0]));
c8725226 9719 if (&obj->base == NULL)
cce13ff7 9720 return ERR_PTR(-ENOENT);
79e53945 9721
d2dff872 9722 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9723}
9724
79e53945 9725static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9726 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9727 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9728};
9729
e70236a8
JB		 9730/* Set up chip specific display functions */
9731static void intel_init_display(struct drm_device *dev)
9732{
9733 struct drm_i915_private *dev_priv = dev->dev_private;
9734
ee9300bb
DV		 9735 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9736 dev_priv->display.find_dpll = g4x_find_best_dpll;
9737 else if (IS_VALLEYVIEW(dev))
9738 dev_priv->display.find_dpll = vlv_find_best_dpll;
9739 else if (IS_PINEVIEW(dev))
9740 dev_priv->display.find_dpll = pnv_find_best_dpll;
9741 else
9742 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9743
affa9354 9744 if (HAS_DDI(dev)) {
0e8ffe1b 9745 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9746 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9747 dev_priv->display.crtc_enable = haswell_crtc_enable;
9748 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9749 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9750 dev_priv->display.update_plane = ironlake_update_plane;
9751 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9752 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9753 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9754 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9755 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9756 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9757 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9758 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9759 } else if (IS_VALLEYVIEW(dev)) {
9760 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9761 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9762 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9763 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9764 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9765 dev_priv->display.off = i9xx_crtc_off;
9766 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9767 } else {
0e8ffe1b 9768 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9769 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9770 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9771 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9772 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9773 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9774 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9775 }
e70236a8 9776
e70236a8 9777 /* Returns the core display clock speed */
25eb05fc
JB		 9778 if (IS_VALLEYVIEW(dev))
9779 dev_priv->display.get_display_clock_speed =
9780 valleyview_get_display_clock_speed;
9781 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9782 dev_priv->display.get_display_clock_speed =
9783 i945_get_display_clock_speed;
9784 else if (IS_I915G(dev))
9785 dev_priv->display.get_display_clock_speed =
9786 i915_get_display_clock_speed;
257a7ffc 9787 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9788 dev_priv->display.get_display_clock_speed =
9789 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9790 else if (IS_PINEVIEW(dev))
9791 dev_priv->display.get_display_clock_speed =
9792 pnv_get_display_clock_speed;
e70236a8
JB		 9793 else if (IS_I915GM(dev))
9794 dev_priv->display.get_display_clock_speed =
9795 i915gm_get_display_clock_speed;
9796 else if (IS_I865G(dev))
9797 dev_priv->display.get_display_clock_speed =
9798 i865_get_display_clock_speed;
f0f8a9ce 9799 else if (IS_I85X(dev))
e70236a8
JB		 9800 dev_priv->display.get_display_clock_speed =
9801 i855_get_display_clock_speed;
9802 else /* 852, 830 */
9803 dev_priv->display.get_display_clock_speed =
9804 i830_get_display_clock_speed;
9805
7f8a8569 9806 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9807 if (IS_GEN5(dev)) {
674cf967 9808 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9809 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9810 } else if (IS_GEN6(dev)) {
674cf967 9811 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9812 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9813 } else if (IS_IVYBRIDGE(dev)) {
9814 /* FIXME: detect B0+ stepping and use auto training */
9815 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9816 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9817 dev_priv->display.modeset_global_resources =
9818 ivb_modeset_global_resources;
c82e4d26
ED		 9819 } else if (IS_HASWELL(dev)) {
9820 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9821 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9822 dev_priv->display.modeset_global_resources =
9823 haswell_modeset_global_resources;
a0e63c22 9824 }
6067aaea 9825 } else if (IS_G4X(dev)) {
e0dac65e 9826 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9827 }
8c9f3aaf
JB		 9828
9829 /* Default just returns -ENODEV to indicate unsupported */
9830 dev_priv->display.queue_flip = intel_default_queue_flip;
9831
9832 switch (INTEL_INFO(dev)->gen) {
9833 case 2:
9834 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9835 break;
9836
9837 case 3:
9838 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9839 break;
9840
9841 case 4:
9842 case 5:
9843 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9844 break;
9845
9846 case 6:
9847 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9848 break;
7c9017e5
JB		 9849 case 7:
9850 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9851 break;
8c9f3aaf 9852 }
e70236a8
JB		 9853}
9854
b690e96c
JB		 9855/*
9856 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9857 * resume, or other times. This quirk makes sure that's the case for
9858 * affected systems.
9859 */
0206e353 9860static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9861{
9862 struct drm_i915_private *dev_priv = dev->dev_private;
9863
9864 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9865 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9866}
9867
435793df
KP		 9868/*
9869 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9870 */
9871static void quirk_ssc_force_disable(struct drm_device *dev)
9872{
9873 struct drm_i915_private *dev_priv = dev->dev_private;
9874 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9875 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9876}
9877
4dca20ef 9878/*
5a15ab5b
CE		 9879 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9880 * brightness value
4dca20ef
CE		 9881 */
9882static void quirk_invert_brightness(struct drm_device *dev)
9883{
9884 struct drm_i915_private *dev_priv = dev->dev_private;
9885 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9886 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9887}
9888
e85843be
KM		 9889/*
9890 * Some machines (Dell XPS13) suffer broken backlight controls if
9891 * BLM_PCH_PWM_ENABLE is set.
9892 */
9893static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9894{
9895 struct drm_i915_private *dev_priv = dev->dev_private;
9896 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9897 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9898}
9899
b690e96c
JB		 9900struct intel_quirk {
9901 int device;
9902 int subsystem_vendor;
9903 int subsystem_device;
9904 void (*hook)(struct drm_device *dev);
9905};
9906
5f85f176
EE		 9907/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9908struct intel_dmi_quirk {
9909 void (*hook)(struct drm_device *dev);
9910 const struct dmi_system_id (*dmi_id_list)[];
9911};
9912
9913static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9914{
9915 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9916 return 1;
9917}
9918
9919static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9920 {
9921 .dmi_id_list = &(const struct dmi_system_id[]) {
9922 {
9923 .callback = intel_dmi_reverse_brightness,
9924 .ident = "NCR Corporation",
9925 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9926 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9927 },
9928 },
9929 { } /* terminating entry */
9930 },
9931 .hook = quirk_invert_brightness,
9932 },
9933};
9934
c43b5634 9935static struct intel_quirk intel_quirks[] = {
b690e96c 9936 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9937 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9938
b690e96c
JB		 9939 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9940 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9941
b690e96c
JB		 9942 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9943 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9944
ccd0d36e 9945 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9946 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9947 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9948
9949 /* Lenovo U160 cannot use SSC on LVDS */
9950 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9951
9952 /* Sony Vaio Y cannot use SSC on LVDS */
9953 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9954
9955 /* Acer Aspire 5734Z must invert backlight brightness */
9956 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9957
9958 /* Acer/eMachines G725 */
9959 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9960
9961 /* Acer/eMachines e725 */
9962 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9963
9964 /* Acer/Packard Bell NCL20 */
9965 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9966
9967 /* Acer Aspire 4736Z */
9968 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 9969
9970 /* Dell XPS13 HD Sandy Bridge */
9971 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9972 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9973 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 9974};
9975
9976static void intel_init_quirks(struct drm_device *dev)
9977{
9978 struct pci_dev *d = dev->pdev;
9979 int i;
9980
9981 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9982 struct intel_quirk *q = &intel_quirks[i];
9983
9984 if (d->device == q->device &&
9985 (d->subsystem_vendor == q->subsystem_vendor ||
9986 q->subsystem_vendor == PCI_ANY_ID) &&
9987 (d->subsystem_device == q->subsystem_device ||
9988 q->subsystem_device == PCI_ANY_ID))
9989 q->hook(dev);
9990 }
5f85f176
EE		 9991 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9992 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9993 intel_dmi_quirks[i].hook(dev);
9994 }
b690e96c
JB		 9995}
9996
9cce37f4
JB		 9997/* Disable the VGA plane that we never use */
9998static void i915_disable_vga(struct drm_device *dev)
9999{
10000 struct drm_i915_private *dev_priv = dev->dev_private;
10001 u8 sr1;
766aa1c4 10002 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10003
10004 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10005 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10006 sr1 = inb(VGA_SR_DATA);
10007 outb(sr1 | 1<<5, VGA_SR_DATA);
10008 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10009 udelay(300);
10010
10011 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10012 POSTING_READ(vga_reg);
10013}
10014
f817586c
DV		 10015void intel_modeset_init_hw(struct drm_device *dev)
10016{
fa42e23c 10017 intel_init_power_well(dev);
0232e927 10018
a8f78b58
ED		 10019 intel_prepare_ddi(dev);
10020
f817586c
DV		 10021 intel_init_clock_gating(dev);
10022
79f5b2c7 10023 mutex_lock(&dev->struct_mutex);
8090c6b9 10024 intel_enable_gt_powersave(dev);
79f5b2c7 10025 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10026}
10027
7d708ee4
ID		 10028void intel_modeset_suspend_hw(struct drm_device *dev)
10029{
10030 intel_suspend_hw(dev);
10031}
10032
79e53945
JB		 10033void intel_modeset_init(struct drm_device *dev)
10034{
652c393a 10035 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10036 int i, j, ret;
79e53945
JB		 10037
10038 drm_mode_config_init(dev);
10039
10040 dev->mode_config.min_width = 0;
10041 dev->mode_config.min_height = 0;
10042
019d96cb
DA		 10043 dev->mode_config.preferred_depth = 24;
10044 dev->mode_config.prefer_shadow = 1;
10045
e6ecefaa 10046 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10047
b690e96c
JB		 10048 intel_init_quirks(dev);
10049
1fa61106
ED		 10050 intel_init_pm(dev);
10051
e3c74757
BW		 10052 if (INTEL_INFO(dev)->num_pipes == 0)
10053 return;
10054
e70236a8
JB		 10055 intel_init_display(dev);
10056
a6c45cf0
CW		 10057 if (IS_GEN2(dev)) {
10058 dev->mode_config.max_width = 2048;
10059 dev->mode_config.max_height = 2048;
10060 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10061 dev->mode_config.max_width = 4096;
10062 dev->mode_config.max_height = 4096;
79e53945 10063 } else {
a6c45cf0
CW		 10064 dev->mode_config.max_width = 8192;
10065 dev->mode_config.max_height = 8192;
79e53945 10066 }
5d4545ae 10067 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10068
28c97730 10069 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10070 INTEL_INFO(dev)->num_pipes,
10071 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10072
08e2a7de 10073 for_each_pipe(i) {
79e53945 10074 intel_crtc_init(dev, i);
7f1f3851
JB		 10075 for (j = 0; j < dev_priv->num_plane; j++) {
10076 ret = intel_plane_init(dev, i, j);
10077 if (ret)
06da8da2
VS		 10078 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10079 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10080 }
79e53945
JB		 10081 }
10082
79f689aa 10083 intel_cpu_pll_init(dev);
e72f9fbf 10084 intel_shared_dpll_init(dev);
ee7b9f93 10085
9cce37f4
JB		 10086 /* Just disable it once at startup */
10087 i915_disable_vga(dev);
79e53945 10088 intel_setup_outputs(dev);
11be49eb
CW		 10089
10090 /* Just in case the BIOS is doing something questionable. */
10091 intel_disable_fbc(dev);
2c7111db
CW		 10092}
10093
24929352
DV		 10094static void
10095intel_connector_break_all_links(struct intel_connector *connector)
10096{
10097 connector->base.dpms = DRM_MODE_DPMS_OFF;
10098 connector->base.encoder = NULL;
10099 connector->encoder->connectors_active = false;
10100 connector->encoder->base.crtc = NULL;
10101}
10102
7fad798e
DV		 10103static void intel_enable_pipe_a(struct drm_device *dev)
10104{
10105 struct intel_connector *connector;
10106 struct drm_connector *crt = NULL;
10107 struct intel_load_detect_pipe load_detect_temp;
10108
10109 /* We can't just switch on the pipe A, we need to set things up with a
10110 * proper mode and output configuration. As a gross hack, enable pipe A
10111 * by enabling the load detect pipe once. */
10112 list_for_each_entry(connector,
10113 &dev->mode_config.connector_list,
10114 base.head) {
10115 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10116 crt = &connector->base;
10117 break;
10118 }
10119 }
10120
10121 if (!crt)
10122 return;
10123
10124 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10125 intel_release_load_detect_pipe(crt, &load_detect_temp);
10126
652c393a 10127
7fad798e
DV		 10128}
10129
fa555837
DV		 10130static bool
10131intel_check_plane_mapping(struct intel_crtc *crtc)
10132{
7eb552ae
BW		 10133 struct drm_device *dev = crtc->base.dev;
10134 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10135 u32 reg, val;
10136
7eb552ae 10137 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10138 return true;
10139
10140 reg = DSPCNTR(!crtc->plane);
10141 val = I915_READ(reg);
10142
10143 if ((val & DISPLAY_PLANE_ENABLE) &&
10144 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10145 return false;
10146
10147 return true;
10148}
10149
24929352
DV		 10150static void intel_sanitize_crtc(struct intel_crtc *crtc)
10151{
10152 struct drm_device *dev = crtc->base.dev;
10153 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10154 u32 reg;
24929352 10155
24929352 10156 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10157 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10158 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10159
10160 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10161 * disable the crtc (and hence change the state) if it is wrong. Note
10162 * that gen4+ has a fixed plane -> pipe mapping. */
10163 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10164 struct intel_connector *connector;
10165 bool plane;
10166
24929352
DV		 10167 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10168 crtc->base.base.id);
10169
10170 /* Pipe has the wrong plane attached and the plane is active.
10171 * Temporarily change the plane mapping and disable everything
10172 * ... */
10173 plane = crtc->plane;
10174 crtc->plane = !plane;
10175 dev_priv->display.crtc_disable(&crtc->base);
10176 crtc->plane = plane;
10177
10178 /* ... and break all links. */
10179 list_for_each_entry(connector, &dev->mode_config.connector_list,
10180 base.head) {
10181 if (connector->encoder->base.crtc != &crtc->base)
10182 continue;
10183
10184 intel_connector_break_all_links(connector);
10185 }
10186
10187 WARN_ON(crtc->active);
10188 crtc->base.enabled = false;
10189 }
24929352 10190
7fad798e
DV		 10191 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10192 crtc->pipe == PIPE_A && !crtc->active) {
10193 /* BIOS forgot to enable pipe A, this mostly happens after
10194 * resume. Force-enable the pipe to fix this, the update_dpms
10195 * call below we restore the pipe to the right state, but leave
10196 * the required bits on. */
10197 intel_enable_pipe_a(dev);
10198 }
10199
24929352
DV		 10200 /* Adjust the state of the output pipe according to whether we
10201 * have active connectors/encoders. */
10202 intel_crtc_update_dpms(&crtc->base);
10203
10204 if (crtc->active != crtc->base.enabled) {
10205 struct intel_encoder *encoder;
10206
10207 /* This can happen either due to bugs in the get_hw_state
10208 * functions or because the pipe is force-enabled due to the
10209 * pipe A quirk. */
10210 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10211 crtc->base.base.id,
10212 crtc->base.enabled ? "enabled" : "disabled",
10213 crtc->active ? "enabled" : "disabled");
10214
10215 crtc->base.enabled = crtc->active;
10216
10217 /* Because we only establish the connector -> encoder ->
10218 * crtc links if something is active, this means the
10219 * crtc is now deactivated. Break the links. connector
10220 * -> encoder links are only establish when things are
10221 * actually up, hence no need to break them. */
10222 WARN_ON(crtc->active);
10223
10224 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10225 WARN_ON(encoder->connectors_active);
10226 encoder->base.crtc = NULL;
10227 }
10228 }
10229}
10230
10231static void intel_sanitize_encoder(struct intel_encoder *encoder)
10232{
10233 struct intel_connector *connector;
10234 struct drm_device *dev = encoder->base.dev;
10235
10236 /* We need to check both for a crtc link (meaning that the
10237 * encoder is active and trying to read from a pipe) and the
10238 * pipe itself being active. */
10239 bool has_active_crtc = encoder->base.crtc &&
10240 to_intel_crtc(encoder->base.crtc)->active;
10241
10242 if (encoder->connectors_active && !has_active_crtc) {
10243 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10244 encoder->base.base.id,
10245 drm_get_encoder_name(&encoder->base));
10246
10247 /* Connector is active, but has no active pipe. This is
10248 * fallout from our resume register restoring. Disable
10249 * the encoder manually again. */
10250 if (encoder->base.crtc) {
10251 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10252 encoder->base.base.id,
10253 drm_get_encoder_name(&encoder->base));
10254 encoder->disable(encoder);
10255 }
10256
10257 /* Inconsistent output/port/pipe state happens presumably due to
10258 * a bug in one of the get_hw_state functions. Or someplace else
10259 * in our code, like the register restore mess on resume. Clamp
10260 * things to off as a safer default. */
10261 list_for_each_entry(connector,
10262 &dev->mode_config.connector_list,
10263 base.head) {
10264 if (connector->encoder != encoder)
10265 continue;
10266
10267 intel_connector_break_all_links(connector);
10268 }
10269 }
10270 /* Enabled encoders without active connectors will be fixed in
10271 * the crtc fixup. */
10272}
10273
44cec740 10274void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10275{
10276 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10277 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10278
8dc8a27c
PZ		 10279 /* This function can be called both from intel_modeset_setup_hw_state or
10280 * at a very early point in our resume sequence, where the power well
10281 * structures are not yet restored. Since this function is at a very
10282 * paranoid "someone might have enabled VGA while we were not looking"
10283 * level, just check if the power well is enabled instead of trying to
10284 * follow the "don't touch the power well if we don't need it" policy
10285 * the rest of the driver uses. */
10286 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10287 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10288 return;
10289
0fde901f
KM		 10290 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10291 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10292 i915_disable_vga(dev);
0fde901f
KM		 10293 }
10294}
10295
30e984df 10296static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10297{
10298 struct drm_i915_private *dev_priv = dev->dev_private;
10299 enum pipe pipe;
24929352
DV		 10300 struct intel_crtc *crtc;
10301 struct intel_encoder *encoder;
10302 struct intel_connector *connector;
5358901f 10303 int i;
24929352 10304
0e8ffe1b
DV		 10305 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10306 base.head) {
88adfff1 10307 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10308
0e8ffe1b
DV		 10309 crtc->active = dev_priv->display.get_pipe_config(crtc,
10310 &crtc->config);
24929352
DV		 10311
10312 crtc->base.enabled = crtc->active;
10313
10314 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10315 crtc->base.base.id,
10316 crtc->active ? "enabled" : "disabled");
10317 }
10318
5358901f 10319 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10320 if (HAS_DDI(dev))
6441ab5f
PZ		 10321 intel_ddi_setup_hw_pll_state(dev);
10322
5358901f
DV		 10323 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10324 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10325
10326 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10327 pll->active = 0;
10328 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10329 base.head) {
10330 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10331 pll->active++;
10332 }
10333 pll->refcount = pll->active;
10334
35c95375
DV		 10335 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10336 pll->name, pll->refcount, pll->on);
5358901f
DV		 10337 }
10338
24929352
DV		 10339 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10340 base.head) {
10341 pipe = 0;
10342
10343 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10344 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10345 encoder->base.crtc = &crtc->base;
510d5f2f 10346 if (encoder->get_config)
045ac3b5 10347 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10348 } else {
10349 encoder->base.crtc = NULL;
10350 }
10351
10352 encoder->connectors_active = false;
10353 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10354 encoder->base.base.id,
10355 drm_get_encoder_name(&encoder->base),
10356 encoder->base.crtc ? "enabled" : "disabled",
10357 pipe);
10358 }
10359
510d5f2f
JB		 10360 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10361 base.head) {
10362 if (!crtc->active)
10363 continue;
10364 if (dev_priv->display.get_clock)
10365 dev_priv->display.get_clock(crtc,
10366 &crtc->config);
10367 }
10368
24929352
DV		 10369 list_for_each_entry(connector, &dev->mode_config.connector_list,
10370 base.head) {
10371 if (connector->get_hw_state(connector)) {
10372 connector->base.dpms = DRM_MODE_DPMS_ON;
10373 connector->encoder->connectors_active = true;
10374 connector->base.encoder = &connector->encoder->base;
10375 } else {
10376 connector->base.dpms = DRM_MODE_DPMS_OFF;
10377 connector->base.encoder = NULL;
10378 }
10379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10380 connector->base.base.id,
10381 drm_get_connector_name(&connector->base),
10382 connector->base.encoder ? "enabled" : "disabled");
10383 }
30e984df
DV		 10384}
10385
10386/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10387 * and i915 state tracking structures. */
10388void intel_modeset_setup_hw_state(struct drm_device *dev,
10389 bool force_restore)
10390{
10391 struct drm_i915_private *dev_priv = dev->dev_private;
10392 enum pipe pipe;
10393 struct drm_plane *plane;
10394 struct intel_crtc *crtc;
10395 struct intel_encoder *encoder;
35c95375 10396 int i;
30e984df
DV		 10397
10398 intel_modeset_readout_hw_state(dev);
24929352 10399
babea61d
JB		 10400 /*
10401 * Now that we have the config, copy it to each CRTC struct
10402 * Note that this could go away if we move to using crtc_config
10403 * checking everywhere.
10404 */
10405 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10406 base.head) {
10407 if (crtc->active && i915_fastboot) {
10408 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10409
10410 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10411 crtc->base.base.id);
10412 drm_mode_debug_printmodeline(&crtc->base.mode);
10413 }
10414 }
10415
24929352
DV		 10416 /* HW state is read out, now we need to sanitize this mess. */
10417 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10418 base.head) {
10419 intel_sanitize_encoder(encoder);
10420 }
10421
10422 for_each_pipe(pipe) {
10423 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10424 intel_sanitize_crtc(crtc);
c0b03411 10425 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10426 }
9a935856 10427
35c95375
DV		 10428 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10429 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10430
10431 if (!pll->on || pll->active)
10432 continue;
10433
10434 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10435
10436 pll->disable(dev_priv, pll);
10437 pll->on = false;
10438 }
10439
45e2b5f6 10440 if (force_restore) {
f30da187
DV		 10441 /*
10442 * We need to use raw interfaces for restoring state to avoid
10443 * checking (bogus) intermediate states.
10444 */
45e2b5f6 10445 for_each_pipe(pipe) {
b5644d05
JB		 10446 struct drm_crtc *crtc =
10447 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10448
10449 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10450 crtc->fb);
45e2b5f6 10451 }
b5644d05
JB		 10452 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10453 intel_plane_restore(plane);
0fde901f
KM		 10454
10455 i915_redisable_vga(dev);
45e2b5f6
DV		 10456 } else {
10457 intel_modeset_update_staged_output_state(dev);
10458 }
8af6cf88
DV		 10459
10460 intel_modeset_check_state(dev);
2e938892
DV		 10461
10462 drm_mode_config_reset(dev);
2c7111db
CW		 10463}
10464
10465void intel_modeset_gem_init(struct drm_device *dev)
10466{
1833b134 10467 intel_modeset_init_hw(dev);
02e792fb
DV		 10468
10469 intel_setup_overlay(dev);
24929352 10470
45e2b5f6 10471 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10472}
10473
10474void intel_modeset_cleanup(struct drm_device *dev)
10475{
652c393a
JB		 10476 struct drm_i915_private *dev_priv = dev->dev_private;
10477 struct drm_crtc *crtc;
652c393a 10478
fd0c0642
DV		 10479 /*
10480 * Interrupts and polling as the first thing to avoid creating havoc.
10481 * Too much stuff here (turning of rps, connectors, ...) would
10482 * experience fancy races otherwise.
10483 */
10484 drm_irq_uninstall(dev);
10485 cancel_work_sync(&dev_priv->hotplug_work);
10486 /*
10487 * Due to the hpd irq storm handling the hotplug work can re-arm the
10488 * poll handlers. Hence disable polling after hpd handling is shut down.
10489 */
f87ea761 10490 drm_kms_helper_poll_fini(dev);
fd0c0642 10491
652c393a
JB		 10492 mutex_lock(&dev->struct_mutex);
10493
723bfd70
JB		 10494 intel_unregister_dsm_handler();
10495
652c393a
JB		 10496 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10497 /* Skip inactive CRTCs */
10498 if (!crtc->fb)
10499 continue;
10500
3dec0095 10501 intel_increase_pllclock(crtc);
652c393a
JB		 10502 }
10503
973d04f9 10504 intel_disable_fbc(dev);
e70236a8 10505
8090c6b9 10506 intel_disable_gt_powersave(dev);
0cdab21f 10507
930ebb46
DV		 10508 ironlake_teardown_rc6(dev);
10509
69341a5e
KH		 10510 mutex_unlock(&dev->struct_mutex);
10511
1630fe75
CW		 10512 /* flush any delayed tasks or pending work */
10513 flush_scheduled_work();
10514
dc652f90
JN		 10515 /* destroy backlight, if any, before the connectors */
10516 intel_panel_destroy_backlight(dev);
10517
79e53945 10518 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10519
10520 intel_cleanup_overlay(dev);
79e53945
JB		 10521}
10522
f1c79df3
ZW		 10523/*
10524 * Return which encoder is currently attached for connector.
10525 */
df0e9248 10526struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10527{
df0e9248
CW		 10528 return &intel_attached_encoder(connector)->base;
10529}
f1c79df3 10530
df0e9248
CW		 10531void intel_connector_attach_encoder(struct intel_connector *connector,
10532 struct intel_encoder *encoder)
10533{
10534 connector->encoder = encoder;
10535 drm_mode_connector_attach_encoder(&connector->base,
10536 &encoder->base);
79e53945 10537}
28d52043
DA		 10538
10539/*
10540 * set vga decode state - true == enable VGA decode
10541 */
10542int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10543{
10544 struct drm_i915_private *dev_priv = dev->dev_private;
10545 u16 gmch_ctrl;
10546
10547 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10548 if (state)
10549 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10550 else
10551 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10552 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10553 return 0;
10554}
c4a1d9e4 10555
c4a1d9e4 10556struct intel_display_error_state {
ff57f1b0
PZ		 10557
10558 u32 power_well_driver;
10559
c4a1d9e4
CW		 10560 struct intel_cursor_error_state {
10561 u32 control;
10562 u32 position;
10563 u32 base;
10564 u32 size;
52331309 10565 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10566
10567 struct intel_pipe_error_state {
ff57f1b0 10568 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10569 u32 conf;
10570 u32 source;
10571
10572 u32 htotal;
10573 u32 hblank;
10574 u32 hsync;
10575 u32 vtotal;
10576 u32 vblank;
10577 u32 vsync;
52331309 10578 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10579
10580 struct intel_plane_error_state {
10581 u32 control;
10582 u32 stride;
10583 u32 size;
10584 u32 pos;
10585 u32 addr;
10586 u32 surface;
10587 u32 tile_offset;
52331309 10588 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10589};
10590
10591struct intel_display_error_state *
10592intel_display_capture_error_state(struct drm_device *dev)
10593{
0206e353 10594 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10595 struct intel_display_error_state *error;
702e7a56 10596 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10597 int i;
10598
10599 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10600 if (error == NULL)
10601 return NULL;
10602
ff57f1b0
PZ		 10603 if (HAS_POWER_WELL(dev))
10604 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10605
52331309 10606 for_each_pipe(i) {
702e7a56 10607 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10608 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10609
a18c4c3d
PZ		 10610 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10611 error->cursor[i].control = I915_READ(CURCNTR(i));
10612 error->cursor[i].position = I915_READ(CURPOS(i));
10613 error->cursor[i].base = I915_READ(CURBASE(i));
10614 } else {
10615 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10616 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10617 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10618 }
c4a1d9e4
CW		 10619
10620 error->plane[i].control = I915_READ(DSPCNTR(i));
10621 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10622 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10623 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10624 error->plane[i].pos = I915_READ(DSPPOS(i));
10625 }
ca291363
PZ		 10626 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10627 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10628 if (INTEL_INFO(dev)->gen >= 4) {
10629 error->plane[i].surface = I915_READ(DSPSURF(i));
10630 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10631 }
10632
702e7a56 10633 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10634 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10635 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10636 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10637 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10638 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10639 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10640 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10641 }
10642
12d217c7
PZ		 10643 /* In the code above we read the registers without checking if the power
10644 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10645 * prevent the next I915_WRITE from detecting it and printing an error
10646 * message. */
907b28c5 10647 intel_uncore_clear_errors(dev);
12d217c7 10648
c4a1d9e4
CW		 10649 return error;
10650}
10651
edc3d884
MK		 10652#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10653
c4a1d9e4 10654void
edc3d884 10655intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10656 struct drm_device *dev,
10657 struct intel_display_error_state *error)
10658{
10659 int i;
10660
edc3d884 10661 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10662 if (HAS_POWER_WELL(dev))
edc3d884 10663 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10664 error->power_well_driver);
52331309 10665 for_each_pipe(i) {
edc3d884
MK		 10666 err_printf(m, "Pipe [%d]:\n", i);
10667 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10668 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10669 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10670 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10671 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10672 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10673 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10674 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10675 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10676 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10677
10678 err_printf(m, "Plane [%d]:\n", i);
10679 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10680 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10681 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10682 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10683 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10684 }
4b71a570 10685 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10686 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10687 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10688 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10689 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10690 }
10691
edc3d884
MK		 10692 err_printf(m, "Cursor [%d]:\n", i);
10693 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10694 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10695 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10696 }
10697}
Linux kernel - Deliverables
This page took 2.276237 seconds and 5 git commands to generate.