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drm/i915: Make intel_dp_source_supports_hbr2() take an intel_dp pointer
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179 1159{
b24e7179
JB		 1160 u32 val;
1161 bool cur_state;
1162
649636ef 1163 val = I915_READ(DPLL(pipe));
b24e7179 1164 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1165 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168}
b24e7179 1169
23538ef1
JN		 1170/* XXX: the dsi pll is shared between MIPI DSI ports */
1171static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172{
1173 u32 val;
1174 bool cur_state;
1175
a580516d 1176 mutex_lock(&dev_priv->sb_lock);
23538ef1 1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1178 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1179
1180 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1181 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184}
1185#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
55607e8a 1188struct intel_shared_dpll *
e2b78267
DV		 1189intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190{
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
6e3c9717 1193 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1194 return NULL;
1195
6e3c9717 1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1197}
1198
040484af 1199/* For ILK+ */
55607e8a
DV		 1200void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
040484af 1203{
040484af 1204 bool cur_state;
5358901f 1205 struct intel_dpll_hw_state hw_state;
040484af 1206
92b27b08 1207 if (WARN (!pll,
46edb027 1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1209 return;
ee7b9f93 1210
5358901f 1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1212 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
040484af 1215}
040484af
JB		 1216
1217static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219{
040484af 1220 bool cur_state;
ad80a810
PZ		 1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
040484af 1223
affa9354
PZ		 1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
649636ef 1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1228 } else {
649636ef 1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED		 1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
e2c719b7 1232 I915_STATE_WARN(cur_state != state,
040484af
JB		 1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235}
1236#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241{
040484af
JB		 1242 u32 val;
1243 bool cur_state;
1244
649636ef 1245 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1246 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1247 I915_STATE_WARN(cur_state != state,
040484af
JB		 1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250}
1251#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
040484af
JB		 1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
3d13ef2e 1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1261 return;
1262
bf507ef7 1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1264 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1265 return;
1266
649636ef 1267 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1269}
1270
55607e8a
DV		 1271void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
040484af 1273{
040484af 1274 u32 val;
55607e8a 1275 bool cur_state;
040484af 1276
649636ef 1277 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1279 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
040484af
JB		 1282}
1283
b680c37a
DV		 1284void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
ea0760cf 1286{
bedd4dba
JN		 1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
ea0760cf
JB		 1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
0de3b485 1291 bool locked = true;
ea0760cf 1292
bedd4dba
JN		 1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
ea0760cf 1299 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
ea0760cf
JB		 1310 } else {
1311 pp_reg = PP_CONTROL;
bedd4dba
JN		 1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
ea0760cf
JB		 1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1319 locked = false;
1320
e2c719b7 1321 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1322 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1323 pipe_name(pipe));
ea0760cf
JB		 1324}
1325
93ce0ba6
JN		 1326static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328{
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
d9d82081 1332 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1334 else
5efb3e28 1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340}
1341#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
b840d907
JB		 1344void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
b24e7179 1346{
63d7bbe9 1347 bool cur_state;
702e7a56
PZ		 1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
b24e7179 1350
b6b5d049
VS		 1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1354 state = true;
1355
f458ebbc 1356 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1358 cur_state = false;
1359 } else {
649636ef 1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161
PZ		 1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
63d7bbe9 1365 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1366 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
b24e7179 1371{
b24e7179 1372 u32 val;
931872fc 1373 bool cur_state;
b24e7179 1374
649636ef 1375 val = I915_READ(DSPCNTR(plane));
931872fc 1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1377 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1380}
1381
931872fc
CW		 1382#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
b24e7179
JB		 1385static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387{
653e1026 1388 struct drm_device *dev = dev_priv->dev;
649636ef 1389 int i;
b24e7179 1390
653e1026
VS		 1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1393 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
19ec1358 1397 return;
28c05794 1398 }
19ec1358 1399
b24e7179 1400 /* Need to check both planes against the pipe */
055e393f 1401 for_each_pipe(dev_priv, i) {
649636ef
VS		 1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1404 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1408 }
1409}
1410
19332d7a
JB		 1411static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
20674eef 1414 struct drm_device *dev = dev_priv->dev;
649636ef 1415 int sprite;
19332d7a 1416
7feb8b88 1417 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1425 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1427 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1429 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1432 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1433 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1437 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1438 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1440 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1441 }
1442}
1443
08c71e5e
VS		 1444static void assert_vblank_disabled(struct drm_crtc *crtc)
1445{
e2c719b7 1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1447 drm_crtc_vblank_put(crtc);
1448}
1449
89eff4be 1450static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1451{
1452 u32 val;
1453 bool enabled;
1454
e2c719b7 1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1456
92f2584a
JB		 1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1461}
1462
ab9412ba
DV		 1463static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
92f2584a 1465{
92f2584a
JB		 1466 u32 val;
1467 bool enabled;
1468
649636ef 1469 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1470 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1471 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
92f2584a
JB		 1474}
1475
4e634389
KP		 1476static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1478{
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
44f37d1f
CML		 1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
f0575e92
KP		 1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495}
1496
1519b995
KP		 1497static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
dc0fa718 1500 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1505 return false;
44f37d1f
CML		 1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1519b995 1509 } else {
dc0fa718 1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1511 return false;
1512 }
1513 return true;
1514}
1515
1516static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518{
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
1532static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534{
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545}
1546
291906f1 1547static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1548 enum pipe pipe, int reg, u32 port_sel)
291906f1 1549{
47a05eca 1550 u32 val = I915_READ(reg);
e2c719b7 1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1553 reg, pipe_name(pipe));
de9a35ab 1554
e2c719b7 1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1556 && (val & DP_PIPEB_SELECT),
de9a35ab 1557 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1558}
1559
1560static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562{
47a05eca 1563 u32 val = I915_READ(reg);
e2c719b7 1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1566 reg, pipe_name(pipe));
de9a35ab 1567
e2c719b7 1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1569 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1570 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1571}
1572
1573static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575{
291906f1 1576 u32 val;
291906f1 1577
f0575e92
KP		 1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1581
649636ef 1582 val = I915_READ(PCH_ADPA);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
649636ef 1587 val = I915_READ(PCH_LVDS);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
b8afb911 1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
b8afb911 1783 u32 val;
f6071166
JB		 1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
b8afb911 1792 val = DPLL_VGA_MODE_DIS;
f6071166 1793 if (pipe == PIPE_B)
60bfe44f 1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1797
1798}
1799
1800static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801{
d752048d 1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1803 u32 val;
1804
a11b0703
VS		 1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1807
a11b0703 1808 /* Set PLL en = 0 */
60bfe44f
VS		 1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
d752048d 1815
a580516d 1816 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
a580516d 1823 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1824}
1825
e4607fcf 1826void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
89b667f8
JB		 1829{
1830 u32 port_mask;
00fc31b7 1831 int dpll_reg;
89b667f8 1832
e4607fcf
CML		 1833 switch (dport->port) {
1834 case PORT_B:
89b667f8 1835 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1836 dpll_reg = DPLL(0);
e4607fcf
CML		 1837 break;
1838 case PORT_C:
89b667f8 1839 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1840 dpll_reg = DPLL(0);
9b6de0a1 1841 expected_mask <<= 4;
00fc31b7
CML		 1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1846 break;
1847 default:
1848 BUG();
1849 }
89b667f8 1850
9b6de0a1
VS		 1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1854}
1855
b14b1055
DV		 1856static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857{
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
be19f0ff
CW		 1862 if (WARN_ON(pll == NULL))
1863 return;
1864
3e369b76 1865 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873}
1874
92f2584a 1875/**
85b3894f 1876 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
85b3894f 1883static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1884{
3d13ef2e
DL		 1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1888
87a875bb 1889 if (WARN_ON(pll == NULL))
48da64a8
CW		 1890 return;
1891
3e369b76 1892 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1893 return;
ee7b9f93 1894
74dd6928 1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1896 pll->name, pll->active, pll->on,
e2b78267 1897 crtc->base.base.id);
92f2584a 1898
cdbd2316
DV		 1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
e9d6944e 1901 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1902 return;
1903 }
f4a091c7 1904 WARN_ON(pll->on);
ee7b9f93 1905
bd2bb1b9
PZ		 1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
46edb027 1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1909 pll->enable(dev_priv, pll);
ee7b9f93 1910 pll->on = true;
92f2584a
JB		 1911}
1912
f6daaec2 1913static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1918
92f2584a 1919 /* PCH only available on ILK+ */
80aa9312
JB		 1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
eddfcbcd
ML		 1923 if (pll == NULL)
1924 return;
92f2584a 1925
eddfcbcd 1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1927 return;
7a419866 1928
46edb027
DV		 1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
e2b78267 1931 crtc->base.base.id);
7a419866 1932
48da64a8 1933 if (WARN_ON(pll->active == 0)) {
e9d6944e 1934 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1935 return;
1936 }
1937
e9d6944e 1938 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1939 WARN_ON(!pll->on);
cdbd2316 1940 if (--pll->active)
7a419866 1941 return;
ee7b9f93 1942
46edb027 1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1944 pll->disable(dev_priv, pll);
ee7b9f93 1945 pll->on = false;
bd2bb1b9
PZ		 1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1948}
1949
b8a4f404
PZ		 1950static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
040484af 1952{
23670b32 1953 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1956 uint32_t reg, val, pipeconf_val;
040484af
JB		 1957
1958 /* PCH only available on ILK+ */
55522f37 1959 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1960
1961 /* Make sure PCH DPLL is enabled */
e72f9fbf 1962 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1963 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
23670b32
DV		 1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
59c859d6 1976 }
23670b32 1977
ab9412ba 1978 reg = PCH_TRANSCONF(pipe);
040484af 1979 val = I915_READ(reg);
5f7f726d 1980 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
c5de7c6f
VS		 1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
e9bcff5c 1987 */
dfd07d72 1988 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1993 }
5f7f726d
PZ		 1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1997 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
040484af
JB		 2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2008}
2009
8fb033d7 2010static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2011 enum transcoder cpu_transcoder)
040484af 2012{
8fb033d7 2013 u32 val, pipeconf_val;
8fb033d7
PZ		 2014
2015 /* PCH only available on ILK+ */
55522f37 2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2017
8fb033d7 2018 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2021
223a6fdf 2022 /* Workaround: set timing override bit. */
36c0d0cf 2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2026
25f3ef11 2027 val = TRANS_ENABLE;
937bb610 2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2029
9a76b1c6
PZ		 2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
a35f2679 2032 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
ab9412ba
DV		 2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2038 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2039}
2040
b8a4f404
PZ		 2041static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
040484af 2043{
23670b32
DV		 2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
040484af
JB		 2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
291906f1
JB		 2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
ab9412ba 2054 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2061
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
040484af
JB		 2069}
2070
ab4d966c 2071static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2072{
8fb033d7
PZ		 2073 u32 val;
2074
ab9412ba 2075 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2076 val &= ~TRANS_ENABLE;
ab9412ba 2077 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2078 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2080 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2081
2082 /* Workaround: clear timing override bit. */
36c0d0cf 2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2086}
2087
b24e7179 2088/**
309cfea8 2089 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2090 * @crtc: crtc responsible for the pipe
b24e7179 2091 *
0372264a 2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2094 */
e1fdc473 2095static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2096{
0372264a
PZ		 2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2101 pipe);
1a240d4d 2102 enum pipe pch_transcoder;
b24e7179
JB		 2103 int reg;
2104 u32 val;
2105
9e2ee2dd
VS		 2106 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2107
58c6eaa2 2108 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2109 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2110 assert_sprites_disabled(dev_priv, pipe);
2111
681e5811 2112 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2113 pch_transcoder = TRANSCODER_A;
2114 else
2115 pch_transcoder = pipe;
2116
b24e7179
JB		 2117 /*
2118 * A pipe without a PLL won't actually be able to drive bits from
2119 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2120 * need the check.
2121 */
50360403 2122 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2124 assert_dsi_pll_enabled(dev_priv);
2125 else
2126 assert_pll_enabled(dev_priv, pipe);
040484af 2127 else {
6e3c9717 2128 if (crtc->config->has_pch_encoder) {
040484af 2129 /* if driving the PCH, we need FDI enabled */
cc391bbb 2130 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2131 assert_fdi_tx_pll_enabled(dev_priv,
2132 (enum pipe) cpu_transcoder);
040484af
JB		 2133 }
2134 /* FIXME: assert CPU port conditions for SNB+ */
2135 }
b24e7179 2136
702e7a56 2137 reg = PIPECONF(cpu_transcoder);
b24e7179 2138 val = I915_READ(reg);
7ad25d48 2139 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2140 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2142 return;
7ad25d48 2143 }
00d70b15
CW		 2144
2145 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2146 POSTING_READ(reg);
b24e7179
JB		 2147}
2148
2149/**
309cfea8 2150 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2151 * @crtc: crtc whose pipes is to be disabled
b24e7179 2152 *
575f7ab7
VS		 2153 * Disable the pipe of @crtc, making sure that various hardware
2154 * specific requirements are met, if applicable, e.g. plane
2155 * disabled, panel fitter off, etc.
b24e7179
JB		 2156 *
2157 * Will wait until the pipe has shut down before returning.
2158 */
575f7ab7 2159static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2160{
575f7ab7 2161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2162 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2163 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2164 int reg;
2165 u32 val;
2166
9e2ee2dd
VS		 2167 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2168
b24e7179
JB		 2169 /*
2170 * Make sure planes won't keep trying to pump pixels to us,
2171 * or we might hang the display.
2172 */
2173 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2174 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2175 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2176
702e7a56 2177 reg = PIPECONF(cpu_transcoder);
b24e7179 2178 val = I915_READ(reg);
00d70b15
CW		 2179 if ((val & PIPECONF_ENABLE) == 0)
2180 return;
2181
67adc644
VS		 2182 /*
2183 * Double wide has implications for planes
2184 * so best keep it disabled when not needed.
2185 */
6e3c9717 2186 if (crtc->config->double_wide)
67adc644
VS		 2187 val &= ~PIPECONF_DOUBLE_WIDE;
2188
2189 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2190 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2192 val &= ~PIPECONF_ENABLE;
2193
2194 I915_WRITE(reg, val);
2195 if ((val & PIPECONF_ENABLE) == 0)
2196 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2197}
2198
693db184
CW		 2199static bool need_vtd_wa(struct drm_device *dev)
2200{
2201#ifdef CONFIG_INTEL_IOMMU
2202 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2203 return true;
2204#endif
2205 return false;
2206}
2207
50470bb0 2208unsigned int
6761dd31 2209intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2210 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2211{
6761dd31
TU		 2212 unsigned int tile_height;
2213 uint32_t pixel_bytes;
a57ce0b2 2214
b5d0e9bf
DL		 2215 switch (fb_format_modifier) {
2216 case DRM_FORMAT_MOD_NONE:
2217 tile_height = 1;
2218 break;
2219 case I915_FORMAT_MOD_X_TILED:
2220 tile_height = IS_GEN2(dev) ? 16 : 8;
2221 break;
2222 case I915_FORMAT_MOD_Y_TILED:
2223 tile_height = 32;
2224 break;
2225 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2226 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2227 switch (pixel_bytes) {
b5d0e9bf 2228 default:
6761dd31 2229 case 1:
b5d0e9bf
DL		 2230 tile_height = 64;
2231 break;
6761dd31
TU		 2232 case 2:
2233 case 4:
b5d0e9bf
DL		 2234 tile_height = 32;
2235 break;
6761dd31 2236 case 8:
b5d0e9bf
DL		 2237 tile_height = 16;
2238 break;
6761dd31 2239 case 16:
b5d0e9bf
DL		 2240 WARN_ONCE(1,
2241 "128-bit pixels are not supported for display!");
2242 tile_height = 16;
2243 break;
2244 }
2245 break;
2246 default:
2247 MISSING_CASE(fb_format_modifier);
2248 tile_height = 1;
2249 break;
2250 }
091df6cb 2251
6761dd31
TU		 2252 return tile_height;
2253}
2254
2255unsigned int
2256intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257 uint32_t pixel_format, uint64_t fb_format_modifier)
2258{
2259 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2260 fb_format_modifier, 0));
a57ce0b2
JB		 2261}
2262
f64b98cd
TU		 2263static int
2264intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265 const struct drm_plane_state *plane_state)
2266{
50470bb0 2267 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2268 unsigned int tile_height, tile_pitch;
50470bb0 2269
f64b98cd
TU		 2270 *view = i915_ggtt_view_normal;
2271
50470bb0
TU		 2272 if (!plane_state)
2273 return 0;
2274
121920fa 2275 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2276 return 0;
2277
9abc4648 2278 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2279
2280 info->height = fb->height;
2281 info->pixel_format = fb->pixel_format;
2282 info->pitch = fb->pitches[0];
89e3e142 2283 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2284 info->fb_modifier = fb->modifier[0];
2285
84fe03f7 2286 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2287 fb->modifier[0], 0);
84fe03f7
TU		 2288 tile_pitch = PAGE_SIZE / tile_height;
2289 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2292
89e3e142
TU		 2293 if (info->pixel_format == DRM_FORMAT_NV12) {
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 1);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2299 tile_height);
2300 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2301 PAGE_SIZE;
2302 }
2303
f64b98cd
TU		 2304 return 0;
2305}
2306
4e9a86b6
VS		 2307static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2308{
2309 if (INTEL_INFO(dev_priv)->gen >= 9)
2310 return 256 * 1024;
985b8bb4
VS		 2311 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2313 return 128 * 1024;
2314 else if (INTEL_INFO(dev_priv)->gen >= 4)
2315 return 4 * 1024;
2316 else
44c5905e 2317 return 0;
4e9a86b6
VS		 2318}
2319
127bd2ac 2320int
850c4cdc
TU		 2321intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322 struct drm_framebuffer *fb,
7580d774 2323 const struct drm_plane_state *plane_state)
6b95a207 2324{
850c4cdc 2325 struct drm_device *dev = fb->dev;
ce453d81 2326 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2327 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2328 struct i915_ggtt_view view;
6b95a207
KH		 2329 u32 alignment;
2330 int ret;
2331
ebcdd39e
MR		 2332 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2333
7b911adc
TU		 2334 switch (fb->modifier[0]) {
2335 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2336 alignment = intel_linear_alignment(dev_priv);
6b95a207 2337 break;
7b911adc 2338 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2339 if (INTEL_INFO(dev)->gen >= 9)
2340 alignment = 256 * 1024;
2341 else {
2342 /* pin() will align the object as required by fence */
2343 alignment = 0;
2344 }
6b95a207 2345 break;
7b911adc 2346 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2347 case I915_FORMAT_MOD_Yf_TILED:
2348 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2349 "Y tiling bo slipped through, driver bug!\n"))
2350 return -EINVAL;
2351 alignment = 1 * 1024 * 1024;
2352 break;
6b95a207 2353 default:
7b911adc
TU		 2354 MISSING_CASE(fb->modifier[0]);
2355 return -EINVAL;
6b95a207
KH		 2356 }
2357
f64b98cd
TU		 2358 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2359 if (ret)
2360 return ret;
2361
693db184
CW		 2362 /* Note that the w/a also requires 64 PTE of padding following the
2363 * bo. We currently fill all unused PTE with the shadow page and so
2364 * we should always have valid PTE following the scanout preventing
2365 * the VT-d warning.
2366 */
2367 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2368 alignment = 256 * 1024;
2369
d6dd6843
PZ		 2370 /*
2371 * Global gtt pte registers are special registers which actually forward
2372 * writes to a chunk of system memory. Which means that there is no risk
2373 * that the register values disappear as soon as we call
2374 * intel_runtime_pm_put(), so it is correct to wrap only the
2375 * pin/unpin/fence and not more.
2376 */
2377 intel_runtime_pm_get(dev_priv);
2378
7580d774
ML		 2379 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2380 &view);
48b956c5 2381 if (ret)
b26a6b35 2382 goto err_pm;
6b95a207
KH		 2383
2384 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2385 * fence, whereas 965+ only requires a fence if using
2386 * framebuffer compression. For simplicity, we always install
2387 * a fence as the cost is not that onerous.
2388 */
06d98131 2389 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2390 if (ret == -EDEADLK) {
2391 /*
2392 * -EDEADLK means there are no free fences
2393 * no pending flips.
2394 *
2395 * This is propagated to atomic, but it uses
2396 * -EDEADLK to force a locking recovery, so
2397 * change the returned error to -EBUSY.
2398 */
2399 ret = -EBUSY;
2400 goto err_unpin;
2401 } else if (ret)
9a5a53b3 2402 goto err_unpin;
1690e1eb 2403
9a5a53b3 2404 i915_gem_object_pin_fence(obj);
6b95a207 2405
d6dd6843 2406 intel_runtime_pm_put(dev_priv);
6b95a207 2407 return 0;
48b956c5
CW		 2408
2409err_unpin:
f64b98cd 2410 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2411err_pm:
d6dd6843 2412 intel_runtime_pm_put(dev_priv);
48b956c5 2413 return ret;
6b95a207
KH		 2414}
2415
82bc3b2d
TU		 2416static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2417 const struct drm_plane_state *plane_state)
1690e1eb 2418{
82bc3b2d 2419 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2420 struct i915_ggtt_view view;
2421 int ret;
82bc3b2d 2422
ebcdd39e
MR		 2423 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2424
f64b98cd
TU		 2425 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2426 WARN_ONCE(ret, "Couldn't get view from plane state!");
2427
1690e1eb 2428 i915_gem_object_unpin_fence(obj);
f64b98cd 2429 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2430}
2431
c2c75131
DV		 2432/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2433 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2434unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2435 int *x, int *y,
bc752862
CW		 2436 unsigned int tiling_mode,
2437 unsigned int cpp,
2438 unsigned int pitch)
c2c75131 2439{
bc752862
CW		 2440 if (tiling_mode != I915_TILING_NONE) {
2441 unsigned int tile_rows, tiles;
c2c75131 2442
bc752862
CW		 2443 tile_rows = *y / 8;
2444 *y %= 8;
c2c75131 2445
bc752862
CW		 2446 tiles = *x / (512/cpp);
2447 *x %= 512/cpp;
2448
2449 return tile_rows * pitch * 8 + tiles * 4096;
2450 } else {
4e9a86b6 2451 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2452 unsigned int offset;
2453
2454 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2455 *y = (offset & alignment) / pitch;
2456 *x = ((offset & alignment) - *y * pitch) / cpp;
2457 return offset & ~alignment;
bc752862 2458 }
c2c75131
DV		 2459}
2460
b35d63fa 2461static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2462{
2463 switch (format) {
2464 case DISPPLANE_8BPP:
2465 return DRM_FORMAT_C8;
2466 case DISPPLANE_BGRX555:
2467 return DRM_FORMAT_XRGB1555;
2468 case DISPPLANE_BGRX565:
2469 return DRM_FORMAT_RGB565;
2470 default:
2471 case DISPPLANE_BGRX888:
2472 return DRM_FORMAT_XRGB8888;
2473 case DISPPLANE_RGBX888:
2474 return DRM_FORMAT_XBGR8888;
2475 case DISPPLANE_BGRX101010:
2476 return DRM_FORMAT_XRGB2101010;
2477 case DISPPLANE_RGBX101010:
2478 return DRM_FORMAT_XBGR2101010;
2479 }
2480}
2481
bc8d7dff
DL		 2482static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2483{
2484 switch (format) {
2485 case PLANE_CTL_FORMAT_RGB_565:
2486 return DRM_FORMAT_RGB565;
2487 default:
2488 case PLANE_CTL_FORMAT_XRGB_8888:
2489 if (rgb_order) {
2490 if (alpha)
2491 return DRM_FORMAT_ABGR8888;
2492 else
2493 return DRM_FORMAT_XBGR8888;
2494 } else {
2495 if (alpha)
2496 return DRM_FORMAT_ARGB8888;
2497 else
2498 return DRM_FORMAT_XRGB8888;
2499 }
2500 case PLANE_CTL_FORMAT_XRGB_2101010:
2501 if (rgb_order)
2502 return DRM_FORMAT_XBGR2101010;
2503 else
2504 return DRM_FORMAT_XRGB2101010;
2505 }
2506}
2507
5724dbd1 2508static bool
f6936e29
DV		 2509intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2510 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2511{
2512 struct drm_device *dev = crtc->base.dev;
3badb49f 2513 struct drm_i915_private *dev_priv = to_i915(dev);
46f297fb
JB		 2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
3badb49f
PZ		 2526 /* If the FB is too big, just don't use it since fbdev is not very
2527 * important and we should probably use that space with FBC or other
2528 * features. */
2529 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2530 return false;
2531
f37b5c2b
DV		 2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
46f297fb 2536 if (!obj)
484b41dd 2537 return false;
46f297fb 2538
49af449b
DL		 2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2541 obj->stride = fb->pitches[0];
46f297fb 2542
6bf129df
DL		 2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2549
2550 mutex_lock(&dev->struct_mutex);
6bf129df 2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2552 &mode_cmd, obj)) {
46f297fb
JB		 2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
46f297fb 2556 mutex_unlock(&dev->struct_mutex);
484b41dd 2557
f6936e29 2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2559 return true;
46f297fb
JB		 2560
2561out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2564 return false;
2565}
2566
afd65eb4
MR		 2567/* Update plane->state->fb to match plane->fb after driver-internal updates */
2568static void
2569update_state_fb(struct drm_plane *plane)
2570{
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579}
2580
5724dbd1 2581static void
f6936e29
DV		 2582intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2584{
2585 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2586 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2ff8fde1 2589 struct drm_i915_gem_object *obj;
88595ac9 2590 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2591 struct drm_plane_state *plane_state = primary->state;
88595ac9 2592 struct drm_framebuffer *fb;
484b41dd 2593
2d14030b 2594 if (!plane_config->fb)
484b41dd
JB		 2595 return;
2596
f6936e29 2597 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2598 fb = &plane_config->fb->base;
2599 goto valid_fb;
f55548b5 2600 }
484b41dd 2601
2d14030b 2602 kfree(plane_config->fb);
484b41dd
JB		 2603
2604 /*
2605 * Failed to alloc the obj, check to see if we should share
2606 * an fb with another CRTC instead
2607 */
70e1e0ec 2608 for_each_crtc(dev, c) {
484b41dd
JB		 2609 i = to_intel_crtc(c);
2610
2611 if (c == &intel_crtc->base)
2612 continue;
2613
2ff8fde1
MR		 2614 if (!i->active)
2615 continue;
2616
88595ac9
DV		 2617 fb = c->primary->fb;
2618 if (!fb)
484b41dd
JB		 2619 continue;
2620
88595ac9 2621 obj = intel_fb_obj(fb);
2ff8fde1 2622 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2623 drm_framebuffer_reference(fb);
2624 goto valid_fb;
484b41dd
JB		 2625 }
2626 }
88595ac9
DV		 2627
2628 return;
2629
2630valid_fb:
be5651f2
ML		 2631 plane_state->src_x = plane_state->src_y = 0;
2632 plane_state->src_w = fb->width << 16;
2633 plane_state->src_h = fb->height << 16;
2634
2635 plane_state->crtc_x = plane_state->src_y = 0;
2636 plane_state->crtc_w = fb->width;
2637 plane_state->crtc_h = fb->height;
2638
88595ac9
DV		 2639 obj = intel_fb_obj(fb);
2640 if (obj->tiling_mode != I915_TILING_NONE)
2641 dev_priv->preserve_bios_swizzle = true;
2642
be5651f2
ML		 2643 drm_framebuffer_reference(fb);
2644 primary->fb = primary->state->fb = fb;
36750f28 2645 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2646 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2647 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2648}
2649
29b9bde6
DV		 2650static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2651 struct drm_framebuffer *fb,
2652 int x, int y)
81255565
JB		 2653{
2654 struct drm_device *dev = crtc->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2657 struct drm_plane *primary = crtc->primary;
2658 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2659 struct drm_i915_gem_object *obj;
81255565 2660 int plane = intel_crtc->plane;
e506a0c6 2661 unsigned long linear_offset;
81255565 2662 u32 dspcntr;
f45651ba 2663 u32 reg = DSPCNTR(plane);
48404c1e 2664 int pixel_size;
f45651ba 2665
b70709a6 2666 if (!visible || !fb) {
fdd508a6
VS		 2667 I915_WRITE(reg, 0);
2668 if (INTEL_INFO(dev)->gen >= 4)
2669 I915_WRITE(DSPSURF(plane), 0);
2670 else
2671 I915_WRITE(DSPADDR(plane), 0);
2672 POSTING_READ(reg);
2673 return;
2674 }
2675
c9ba6fad
VS		 2676 obj = intel_fb_obj(fb);
2677 if (WARN_ON(obj == NULL))
2678 return;
2679
2680 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2681
f45651ba
VS		 2682 dspcntr = DISPPLANE_GAMMA_ENABLE;
2683
fdd508a6 2684 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2685
2686 if (INTEL_INFO(dev)->gen < 4) {
2687 if (intel_crtc->pipe == PIPE_B)
2688 dspcntr |= DISPPLANE_SEL_PIPE_B;
2689
2690 /* pipesrc and dspsize control the size that is scaled from,
2691 * which should always be the user's requested size.
2692 */
2693 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2696 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2697 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2698 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2701 I915_WRITE(PRIMPOS(plane), 0);
2702 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2703 }
81255565 2704
57779d06
VS		 2705 switch (fb->pixel_format) {
2706 case DRM_FORMAT_C8:
81255565
JB		 2707 dspcntr |= DISPPLANE_8BPP;
2708 break;
57779d06 2709 case DRM_FORMAT_XRGB1555:
57779d06 2710 dspcntr |= DISPPLANE_BGRX555;
81255565 2711 break;
57779d06
VS		 2712 case DRM_FORMAT_RGB565:
2713 dspcntr |= DISPPLANE_BGRX565;
2714 break;
2715 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2716 dspcntr |= DISPPLANE_BGRX888;
2717 break;
2718 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2722 dspcntr |= DISPPLANE_BGRX101010;
2723 break;
2724 case DRM_FORMAT_XBGR2101010:
57779d06 2725 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2726 break;
2727 default:
baba133a 2728 BUG();
81255565 2729 }
57779d06 2730
f45651ba
VS		 2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
81255565 2734
de1aa629
VS		 2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
b9897127 2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2739
c2c75131
DV		 2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2742 intel_gen4_compute_page_offset(dev_priv,
2743 &x, &y, obj->tiling_mode,
b9897127 2744 pixel_size,
bc752862 2745 fb->pitches[0]);
c2c75131
DV		 2746 linear_offset -= intel_crtc->dspaddr_offset;
2747 } else {
e506a0c6 2748 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2749 }
e506a0c6 2750
8e7d688b 2751 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2752 dspcntr |= DISPPLANE_ROTATE_180;
2753
6e3c9717
ACO		 2754 x += (intel_crtc->config->pipe_src_w - 1);
2755 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2756
2757 /* Finding the last pixel of the last line of the display
2758 data and adding to linear_offset*/
2759 linear_offset +=
6e3c9717
ACO		 2760 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2761 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2762 }
2763
2db3366b
PZ		 2764 intel_crtc->adjusted_x = x;
2765 intel_crtc->adjusted_y = y;
2766
48404c1e
SJ		 2767 I915_WRITE(reg, dspcntr);
2768
01f2c773 2769 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2770 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2771 I915_WRITE(DSPSURF(plane),
2772 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2773 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2774 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2775 } else
f343c5f6 2776 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2777 POSTING_READ(reg);
17638cd6
JB		 2778}
2779
29b9bde6
DV		 2780static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2781 struct drm_framebuffer *fb,
2782 int x, int y)
17638cd6
JB		 2783{
2784 struct drm_device *dev = crtc->dev;
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2787 struct drm_plane *primary = crtc->primary;
2788 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2789 struct drm_i915_gem_object *obj;
17638cd6 2790 int plane = intel_crtc->plane;
e506a0c6 2791 unsigned long linear_offset;
17638cd6 2792 u32 dspcntr;
f45651ba 2793 u32 reg = DSPCNTR(plane);
48404c1e 2794 int pixel_size;
f45651ba 2795
b70709a6 2796 if (!visible || !fb) {
fdd508a6
VS		 2797 I915_WRITE(reg, 0);
2798 I915_WRITE(DSPSURF(plane), 0);
2799 POSTING_READ(reg);
2800 return;
2801 }
2802
c9ba6fad
VS		 2803 obj = intel_fb_obj(fb);
2804 if (WARN_ON(obj == NULL))
2805 return;
2806
2807 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2808
f45651ba
VS		 2809 dspcntr = DISPPLANE_GAMMA_ENABLE;
2810
fdd508a6 2811 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2812
2813 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2814 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2815
57779d06
VS		 2816 switch (fb->pixel_format) {
2817 case DRM_FORMAT_C8:
17638cd6
JB		 2818 dspcntr |= DISPPLANE_8BPP;
2819 break;
57779d06
VS		 2820 case DRM_FORMAT_RGB565:
2821 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2822 break;
57779d06 2823 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2824 dspcntr |= DISPPLANE_BGRX888;
2825 break;
2826 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2827 dspcntr |= DISPPLANE_RGBX888;
2828 break;
2829 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2830 dspcntr |= DISPPLANE_BGRX101010;
2831 break;
2832 case DRM_FORMAT_XBGR2101010:
57779d06 2833 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2834 break;
2835 default:
baba133a 2836 BUG();
17638cd6
JB		 2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
17638cd6 2841
f45651ba 2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2844
b9897127 2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2846 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2847 intel_gen4_compute_page_offset(dev_priv,
2848 &x, &y, obj->tiling_mode,
b9897127 2849 pixel_size,
bc752862 2850 fb->pitches[0]);
c2c75131 2851 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2852 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2853 dspcntr |= DISPPLANE_ROTATE_180;
2854
2855 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2856 x += (intel_crtc->config->pipe_src_w - 1);
2857 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2858
2859 /* Finding the last pixel of the last line of the display
2860 data and adding to linear_offset*/
2861 linear_offset +=
6e3c9717
ACO		 2862 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2863 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2864 }
2865 }
2866
2db3366b
PZ		 2867 intel_crtc->adjusted_x = x;
2868 intel_crtc->adjusted_y = y;
2869
48404c1e 2870 I915_WRITE(reg, dspcntr);
17638cd6 2871
01f2c773 2872 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2873 I915_WRITE(DSPSURF(plane),
2874 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2875 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2876 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2877 } else {
2878 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2879 I915_WRITE(DSPLINOFF(plane), linear_offset);
2880 }
17638cd6 2881 POSTING_READ(reg);
17638cd6
JB		 2882}
2883
b321803d
DL		 2884u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2885 uint32_t pixel_format)
2886{
2887 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2888
2889 /*
2890 * The stride is either expressed as a multiple of 64 bytes
2891 * chunks for linear buffers or in number of tiles for tiled
2892 * buffers.
2893 */
2894 switch (fb_modifier) {
2895 case DRM_FORMAT_MOD_NONE:
2896 return 64;
2897 case I915_FORMAT_MOD_X_TILED:
2898 if (INTEL_INFO(dev)->gen == 2)
2899 return 128;
2900 return 512;
2901 case I915_FORMAT_MOD_Y_TILED:
2902 /* No need to check for old gens and Y tiling since this is
2903 * about the display engine and those will be blocked before
2904 * we get here.
2905 */
2906 return 128;
2907 case I915_FORMAT_MOD_Yf_TILED:
2908 if (bits_per_pixel == 8)
2909 return 64;
2910 else
2911 return 128;
2912 default:
2913 MISSING_CASE(fb_modifier);
2914 return 64;
2915 }
2916}
2917
121920fa 2918unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
dedf278c
TU		 2919 struct drm_i915_gem_object *obj,
2920 unsigned int plane)
121920fa 2921{
9abc4648 2922 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c
TU		 2923 struct i915_vma *vma;
2924 unsigned char *offset;
121920fa
TU		 2925
2926 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2927 view = &i915_ggtt_view_rotated;
121920fa 2928
dedf278c
TU		 2929 vma = i915_gem_obj_to_ggtt_view(obj, view);
2930 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2931 view->type))
2932 return -1;
2933
2934 offset = (unsigned char *)vma->node.start;
2935
2936 if (plane == 1) {
2937 offset += vma->ggtt_view.rotation_info.uv_start_page *
2938 PAGE_SIZE;
2939 }
2940
2941 return (unsigned long)offset;
121920fa
TU		 2942}
2943
e435d6e5
ML		 2944static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2945{
2946 struct drm_device *dev = intel_crtc->base.dev;
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948
2949 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2950 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2951 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2952}
2953
a1b2278e
CK		 2954/*
2955 * This function detaches (aka. unbinds) unused scalers in hardware
2956 */
0583236e 2957static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2958{
a1b2278e
CK		 2959 struct intel_crtc_scaler_state *scaler_state;
2960 int i;
2961
a1b2278e
CK		 2962 scaler_state = &intel_crtc->config->scaler_state;
2963
2964 /* loop through and disable scalers that aren't in use */
2965 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2966 if (!scaler_state->scalers[i].in_use)
2967 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2968 }
2969}
2970
6156a456 2971u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2972{
6156a456 2973 switch (pixel_format) {
d161cf7a 2974 case DRM_FORMAT_C8:
c34ce3d1 2975 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2976 case DRM_FORMAT_RGB565:
c34ce3d1 2977 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2978 case DRM_FORMAT_XBGR8888:
c34ce3d1 2979 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2980 case DRM_FORMAT_XRGB8888:
c34ce3d1 2981 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2982 /*
2983 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2984 * to be already pre-multiplied. We need to add a knob (or a different
2985 * DRM_FORMAT) for user-space to configure that.
2986 */
f75fb42a 2987 case DRM_FORMAT_ABGR8888:
c34ce3d1 2988 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2989 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2990 case DRM_FORMAT_ARGB8888:
c34ce3d1 2991 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2992 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2993 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2994 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2995 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2996 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2997 case DRM_FORMAT_YUYV:
c34ce3d1 2998 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2999 case DRM_FORMAT_YVYU:
c34ce3d1 3000 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3001 case DRM_FORMAT_UYVY:
c34ce3d1 3002 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3003 case DRM_FORMAT_VYUY:
c34ce3d1 3004 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3005 default:
4249eeef 3006 MISSING_CASE(pixel_format);
70d21f0e 3007 }
8cfcba41 3008
c34ce3d1 3009 return 0;
6156a456 3010}
70d21f0e 3011
6156a456
CK		 3012u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3013{
6156a456 3014 switch (fb_modifier) {
30af77c4 3015 case DRM_FORMAT_MOD_NONE:
70d21f0e 3016 break;
30af77c4 3017 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3018 return PLANE_CTL_TILED_X;
b321803d 3019 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3020 return PLANE_CTL_TILED_Y;
b321803d 3021 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3022 return PLANE_CTL_TILED_YF;
70d21f0e 3023 default:
6156a456 3024 MISSING_CASE(fb_modifier);
70d21f0e 3025 }
8cfcba41 3026
c34ce3d1 3027 return 0;
6156a456 3028}
70d21f0e 3029
6156a456
CK		 3030u32 skl_plane_ctl_rotation(unsigned int rotation)
3031{
3b7a5119 3032 switch (rotation) {
6156a456
CK		 3033 case BIT(DRM_ROTATE_0):
3034 break;
1e8df167
SJ		 3035 /*
3036 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3037 * while i915 HW rotation is clockwise, thats why this swapping.
3038 */
3b7a5119 3039 case BIT(DRM_ROTATE_90):
1e8df167 3040 return PLANE_CTL_ROTATE_270;
3b7a5119 3041 case BIT(DRM_ROTATE_180):
c34ce3d1 3042 return PLANE_CTL_ROTATE_180;
3b7a5119 3043 case BIT(DRM_ROTATE_270):
1e8df167 3044 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3045 default:
3046 MISSING_CASE(rotation);
3047 }
3048
c34ce3d1 3049 return 0;
6156a456
CK		 3050}
3051
3052static void skylake_update_primary_plane(struct drm_crtc *crtc,
3053 struct drm_framebuffer *fb,
3054 int x, int y)
3055{
3056 struct drm_device *dev = crtc->dev;
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3059 struct drm_plane *plane = crtc->primary;
3060 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3061 struct drm_i915_gem_object *obj;
3062 int pipe = intel_crtc->pipe;
3063 u32 plane_ctl, stride_div, stride;
3064 u32 tile_height, plane_offset, plane_size;
3065 unsigned int rotation;
3066 int x_offset, y_offset;
3067 unsigned long surf_addr;
6156a456
CK		 3068 struct intel_crtc_state *crtc_state = intel_crtc->config;
3069 struct intel_plane_state *plane_state;
3070 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3071 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3072 int scaler_id = -1;
3073
6156a456
CK		 3074 plane_state = to_intel_plane_state(plane->state);
3075
b70709a6 3076 if (!visible || !fb) {
6156a456
CK		 3077 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3078 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3079 POSTING_READ(PLANE_CTL(pipe, 0));
3080 return;
3b7a5119 3081 }
70d21f0e 3082
6156a456
CK		 3083 plane_ctl = PLANE_CTL_ENABLE |
3084 PLANE_CTL_PIPE_GAMMA_ENABLE |
3085 PLANE_CTL_PIPE_CSC_ENABLE;
3086
3087 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3088 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3089 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3090
3091 rotation = plane->state->rotation;
3092 plane_ctl |= skl_plane_ctl_rotation(rotation);
3093
b321803d
DL		 3094 obj = intel_fb_obj(fb);
3095 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3096 fb->pixel_format);
dedf278c 3097 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3098
a42e5a23
PZ		 3099 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3100
3101 scaler_id = plane_state->scaler_id;
3102 src_x = plane_state->src.x1 >> 16;
3103 src_y = plane_state->src.y1 >> 16;
3104 src_w = drm_rect_width(&plane_state->src) >> 16;
3105 src_h = drm_rect_height(&plane_state->src) >> 16;
3106 dst_x = plane_state->dst.x1;
3107 dst_y = plane_state->dst.y1;
3108 dst_w = drm_rect_width(&plane_state->dst);
3109 dst_h = drm_rect_height(&plane_state->dst);
3110
3111 WARN_ON(x != src_x || y != src_y);
6156a456 3112
3b7a5119
SJ		 3113 if (intel_rotation_90_or_270(rotation)) {
3114 /* stride = Surface height in tiles */
2614f17d 3115 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3116 fb->modifier[0], 0);
3b7a5119 3117 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3118 x_offset = stride * tile_height - y - src_h;
3b7a5119 3119 y_offset = x;
6156a456 3120 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3121 } else {
3122 stride = fb->pitches[0] / stride_div;
3123 x_offset = x;
3124 y_offset = y;
6156a456 3125 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3126 }
3127 plane_offset = y_offset << 16 | x_offset;
b321803d 3128
2db3366b
PZ		 3129 intel_crtc->adjusted_x = x_offset;
3130 intel_crtc->adjusted_y = y_offset;
3131
70d21f0e 3132 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3133 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3134 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3135 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3136
3137 if (scaler_id >= 0) {
3138 uint32_t ps_ctrl = 0;
3139
3140 WARN_ON(!dst_w || !dst_h);
3141 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3142 crtc_state->scaler_state.scalers[scaler_id].mode;
3143 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3144 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3145 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3146 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3147 I915_WRITE(PLANE_POS(pipe, 0), 0);
3148 } else {
3149 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3150 }
3151
121920fa 3152 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3153
3154 POSTING_READ(PLANE_SURF(pipe, 0));
3155}
3156
17638cd6
JB		 3157/* Assume fb object is pinned & idle & fenced and just update base pointers */
3158static int
3159intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3160 int x, int y, enum mode_set_atomic state)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3164
ff2a3117 3165 if (dev_priv->fbc.disable_fbc)
7733b49b 3166 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3167
29b9bde6
DV		 3168 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3169
3170 return 0;
81255565
JB		 3171}
3172
7514747d 3173static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3174{
96a02917
VS		 3175 struct drm_crtc *crtc;
3176
70e1e0ec 3177 for_each_crtc(dev, crtc) {
96a02917
VS		 3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179 enum plane plane = intel_crtc->plane;
3180
3181 intel_prepare_page_flip(dev, plane);
3182 intel_finish_page_flip_plane(dev, plane);
3183 }
7514747d
VS		 3184}
3185
3186static void intel_update_primary_planes(struct drm_device *dev)
3187{
7514747d 3188 struct drm_crtc *crtc;
96a02917 3189
70e1e0ec 3190 for_each_crtc(dev, crtc) {
11c22da6
ML		 3191 struct intel_plane *plane = to_intel_plane(crtc->primary);
3192 struct intel_plane_state *plane_state;
96a02917 3193
11c22da6 3194 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML		 3195 plane_state = to_intel_plane_state(plane->base.state);
3196
f029ee82 3197 if (crtc->state->active && plane_state->base.fb)
11c22da6
ML		 3198 plane->commit_plane(&plane->base, plane_state);
3199
3200 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3201 }
3202}
3203
7514747d
VS		 3204void intel_prepare_reset(struct drm_device *dev)
3205{
3206 /* no reset support for gen2 */
3207 if (IS_GEN2(dev))
3208 return;
3209
3210 /* reset doesn't touch the display */
3211 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3212 return;
3213
3214 drm_modeset_lock_all(dev);
f98ce92f
VS		 3215 /*
3216 * Disabling the crtcs gracefully seems nicer. Also the
3217 * g33 docs say we should at least disable all the planes.
3218 */
6b72d486 3219 intel_display_suspend(dev);
7514747d
VS		 3220}
3221
3222void intel_finish_reset(struct drm_device *dev)
3223{
3224 struct drm_i915_private *dev_priv = to_i915(dev);
3225
3226 /*
3227 * Flips in the rings will be nuked by the reset,
3228 * so complete all pending flips so that user space
3229 * will get its events and not get stuck.
3230 */
3231 intel_complete_page_flips(dev);
3232
3233 /* no reset support for gen2 */
3234 if (IS_GEN2(dev))
3235 return;
3236
3237 /* reset doesn't touch the display */
3238 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3239 /*
3240 * Flips in the rings have been nuked by the reset,
3241 * so update the base address of all primary
3242 * planes to the the last fb to make sure we're
3243 * showing the correct fb after a reset.
11c22da6
ML		 3244 *
3245 * FIXME: Atomic will make this obsolete since we won't schedule
3246 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3247 */
3248 intel_update_primary_planes(dev);
3249 return;
3250 }
3251
3252 /*
3253 * The display has been reset as well,
3254 * so need a full re-initialization.
3255 */
3256 intel_runtime_pm_disable_interrupts(dev_priv);
3257 intel_runtime_pm_enable_interrupts(dev_priv);
3258
3259 intel_modeset_init_hw(dev);
3260
3261 spin_lock_irq(&dev_priv->irq_lock);
3262 if (dev_priv->display.hpd_irq_setup)
3263 dev_priv->display.hpd_irq_setup(dev);
3264 spin_unlock_irq(&dev_priv->irq_lock);
3265
043e9bda 3266 intel_display_resume(dev);
7514747d
VS		 3267
3268 intel_hpd_init(dev_priv);
3269
3270 drm_modeset_unlock_all(dev);
3271}
3272
7d5e3799
CW		 3273static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3274{
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3278 bool pending;
3279
3280 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3281 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3282 return false;
3283
5e2d7afc 3284 spin_lock_irq(&dev->event_lock);
7d5e3799 3285 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3286 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3287
3288 return pending;
3289}
3290
bfd16b2a
ML		 3291static void intel_update_pipe_config(struct intel_crtc *crtc,
3292 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3293{
3294 struct drm_device *dev = crtc->base.dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3296 struct intel_crtc_state *pipe_config =
3297 to_intel_crtc_state(crtc->base.state);
e30e8f75 3298
bfd16b2a
ML		 3299 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3300 crtc->base.mode = crtc->base.state->mode;
3301
3302 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3303 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3304 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3305
44522d85
ML		 3306 if (HAS_DDI(dev))
3307 intel_set_pipe_csc(&crtc->base);
3308
e30e8f75
GP		 3309 /*
3310 * Update pipe size and adjust fitter if needed: the reason for this is
3311 * that in compute_mode_changes we check the native mode (not the pfit
3312 * mode) to see if we can flip rather than do a full mode set. In the
3313 * fastboot case, we'll flip, but if we don't update the pipesrc and
3314 * pfit state, we'll end up with a big fb scanned out into the wrong
3315 * sized surface.
e30e8f75
GP		 3316 */
3317
e30e8f75 3318 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3319 ((pipe_config->pipe_src_w - 1) << 16) |
3320 (pipe_config->pipe_src_h - 1));
3321
3322 /* on skylake this is done by detaching scalers */
3323 if (INTEL_INFO(dev)->gen >= 9) {
3324 skl_detach_scalers(crtc);
3325
3326 if (pipe_config->pch_pfit.enabled)
3327 skylake_pfit_enable(crtc);
3328 } else if (HAS_PCH_SPLIT(dev)) {
3329 if (pipe_config->pch_pfit.enabled)
3330 ironlake_pfit_enable(crtc);
3331 else if (old_crtc_state->pch_pfit.enabled)
3332 ironlake_pfit_disable(crtc, true);
e30e8f75 3333 }
e30e8f75
GP		 3334}
3335
5e84e1a4
ZW		 3336static void intel_fdi_normal_train(struct drm_crtc *crtc)
3337{
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 int pipe = intel_crtc->pipe;
3342 u32 reg, temp;
3343
3344 /* enable normal train */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
61e499bf 3347 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3350 } else {
3351 temp &= ~FDI_LINK_TRAIN_NONE;
3352 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3353 }
5e84e1a4
ZW		 3354 I915_WRITE(reg, temp);
3355
3356 reg = FDI_RX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (HAS_PCH_CPT(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3361 } else {
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE;
3364 }
3365 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3366
3367 /* wait one idle pattern time */
3368 POSTING_READ(reg);
3369 udelay(1000);
357555c0
JB		 3370
3371 /* IVB wants error correction enabled */
3372 if (IS_IVYBRIDGE(dev))
3373 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3374 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3375}
3376
8db9d77b
ZW		 3377/* The FDI link training functions for ILK/Ibexpeak. */
3378static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
5eddb70b 3384 u32 reg, temp, tries;
8db9d77b 3385
1c8562f6 3386 /* FDI needs bits from pipe first */
0fc932b8 3387 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3388
e1a44743
AJ		 3389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3390 for train result */
5eddb70b
CW		 3391 reg = FDI_RX_IMR(pipe);
3392 temp = I915_READ(reg);
e1a44743
AJ		 3393 temp &= ~FDI_RX_SYMBOL_LOCK;
3394 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3395 I915_WRITE(reg, temp);
3396 I915_READ(reg);
e1a44743
AJ		 3397 udelay(150);
3398
8db9d77b 3399 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
627eb5a3 3402 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3403 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3407
5eddb70b
CW		 3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
8db9d77b
ZW		 3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3412 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3413
3414 POSTING_READ(reg);
8db9d77b
ZW		 3415 udelay(150);
3416
5b2adf89 3417 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3420 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3421
5eddb70b 3422 reg = FDI_RX_IIR(pipe);
e1a44743 3423 for (tries = 0; tries < 5; tries++) {
5eddb70b 3424 temp = I915_READ(reg);
8db9d77b
ZW		 3425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3426
3427 if ((temp & FDI_RX_BIT_LOCK)) {
3428 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3429 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3430 break;
3431 }
8db9d77b 3432 }
e1a44743 3433 if (tries == 5)
5eddb70b 3434 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3435
3436 /* Train 2 */
5eddb70b
CW		 3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3441 I915_WRITE(reg, temp);
8db9d77b 3442
5eddb70b
CW		 3443 reg = FDI_RX_CTL(pipe);
3444 temp = I915_READ(reg);
8db9d77b
ZW		 3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3447 I915_WRITE(reg, temp);
8db9d77b 3448
5eddb70b
CW		 3449 POSTING_READ(reg);
3450 udelay(150);
8db9d77b 3451
5eddb70b 3452 reg = FDI_RX_IIR(pipe);
e1a44743 3453 for (tries = 0; tries < 5; tries++) {
5eddb70b 3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3456
3457 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3458 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3459 DRM_DEBUG_KMS("FDI train 2 done.\n");
3460 break;
3461 }
8db9d77b 3462 }
e1a44743 3463 if (tries == 5)
5eddb70b 3464 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3465
3466 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3467
8db9d77b
ZW		 3468}
3469
0206e353 3470static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3471 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3472 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3473 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3474 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3475};
3476
3477/* The FDI link training functions for SNB/Cougarpoint. */
3478static void gen6_fdi_link_train(struct drm_crtc *crtc)
3479{
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 int pipe = intel_crtc->pipe;
fa37d39e 3484 u32 reg, temp, i, retry;
8db9d77b 3485
e1a44743
AJ		 3486 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3487 for train result */
5eddb70b
CW		 3488 reg = FDI_RX_IMR(pipe);
3489 temp = I915_READ(reg);
e1a44743
AJ		 3490 temp &= ~FDI_RX_SYMBOL_LOCK;
3491 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3492 I915_WRITE(reg, temp);
3493
3494 POSTING_READ(reg);
e1a44743
AJ		 3495 udelay(150);
3496
8db9d77b 3497 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3498 reg = FDI_TX_CTL(pipe);
3499 temp = I915_READ(reg);
627eb5a3 3500 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3501 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_1;
3504 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3505 /* SNB-B */
3506 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3507 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3508
d74cf324
DV		 3509 I915_WRITE(FDI_RX_MISC(pipe),
3510 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3511
5eddb70b
CW		 3512 reg = FDI_RX_CTL(pipe);
3513 temp = I915_READ(reg);
8db9d77b
ZW		 3514 if (HAS_PCH_CPT(dev)) {
3515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3517 } else {
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 }
5eddb70b
CW		 3521 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3522
3523 POSTING_READ(reg);
8db9d77b
ZW		 3524 udelay(150);
3525
0206e353 3526 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3527 reg = FDI_TX_CTL(pipe);
3528 temp = I915_READ(reg);
8db9d77b
ZW		 3529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3531 I915_WRITE(reg, temp);
3532
3533 POSTING_READ(reg);
8db9d77b
ZW		 3534 udelay(500);
3535
fa37d39e
SP		 3536 for (retry = 0; retry < 5; retry++) {
3537 reg = FDI_RX_IIR(pipe);
3538 temp = I915_READ(reg);
3539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540 if (temp & FDI_RX_BIT_LOCK) {
3541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542 DRM_DEBUG_KMS("FDI train 1 done.\n");
3543 break;
3544 }
3545 udelay(50);
8db9d77b 3546 }
fa37d39e
SP		 3547 if (retry < 5)
3548 break;
8db9d77b
ZW		 3549 }
3550 if (i == 4)
5eddb70b 3551 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3552
3553 /* Train 2 */
5eddb70b
CW		 3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
8db9d77b
ZW		 3556 temp &= ~FDI_LINK_TRAIN_NONE;
3557 temp |= FDI_LINK_TRAIN_PATTERN_2;
3558 if (IS_GEN6(dev)) {
3559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560 /* SNB-B */
3561 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3562 }
5eddb70b 3563 I915_WRITE(reg, temp);
8db9d77b 3564
5eddb70b
CW		 3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
8db9d77b
ZW		 3567 if (HAS_PCH_CPT(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3570 } else {
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573 }
5eddb70b
CW		 3574 I915_WRITE(reg, temp);
3575
3576 POSTING_READ(reg);
8db9d77b
ZW		 3577 udelay(150);
3578
0206e353 3579 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
8db9d77b
ZW		 3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
8db9d77b
ZW		 3587 udelay(500);
3588
fa37d39e
SP		 3589 for (retry = 0; retry < 5; retry++) {
3590 reg = FDI_RX_IIR(pipe);
3591 temp = I915_READ(reg);
3592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593 if (temp & FDI_RX_SYMBOL_LOCK) {
3594 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595 DRM_DEBUG_KMS("FDI train 2 done.\n");
3596 break;
3597 }
3598 udelay(50);
8db9d77b 3599 }
fa37d39e
SP		 3600 if (retry < 5)
3601 break;
8db9d77b
ZW		 3602 }
3603 if (i == 4)
5eddb70b 3604 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3605
3606 DRM_DEBUG_KMS("FDI train done.\n");
3607}
3608
357555c0
JB		 3609/* Manual link training for Ivy Bridge A0 parts */
3610static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 int pipe = intel_crtc->pipe;
139ccd3f 3616 u32 reg, temp, i, j;
357555c0
JB		 3617
3618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3619 for train result */
3620 reg = FDI_RX_IMR(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_RX_SYMBOL_LOCK;
3623 temp &= ~FDI_RX_BIT_LOCK;
3624 I915_WRITE(reg, temp);
3625
3626 POSTING_READ(reg);
3627 udelay(150);
3628
01a415fd
DV		 3629 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3630 I915_READ(FDI_RX_IIR(pipe)));
3631
139ccd3f
JB		 3632 /* Try each vswing and preemphasis setting twice before moving on */
3633 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3634 /* disable first in case we need to retry */
3635 reg = FDI_TX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3638 temp &= ~FDI_TX_ENABLE;
3639 I915_WRITE(reg, temp);
357555c0 3640
139ccd3f
JB		 3641 reg = FDI_RX_CTL(pipe);
3642 temp = I915_READ(reg);
3643 temp &= ~FDI_LINK_TRAIN_AUTO;
3644 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3645 temp &= ~FDI_RX_ENABLE;
3646 I915_WRITE(reg, temp);
357555c0 3647
139ccd3f 3648 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
139ccd3f 3651 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3652 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3653 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3655 temp |= snb_b_fdi_train_param[j/2];
3656 temp |= FDI_COMPOSITE_SYNC;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3658
139ccd3f
JB		 3659 I915_WRITE(FDI_RX_MISC(pipe),
3660 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3661
139ccd3f 3662 reg = FDI_RX_CTL(pipe);
357555c0 3663 temp = I915_READ(reg);
139ccd3f
JB		 3664 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3665 temp |= FDI_COMPOSITE_SYNC;
3666 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3667
139ccd3f
JB		 3668 POSTING_READ(reg);
3669 udelay(1); /* should be 0.5us */
357555c0 3670
139ccd3f
JB		 3671 for (i = 0; i < 4; i++) {
3672 reg = FDI_RX_IIR(pipe);
3673 temp = I915_READ(reg);
3674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3675
139ccd3f
JB		 3676 if (temp & FDI_RX_BIT_LOCK ||
3677 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3678 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3679 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3680 i);
3681 break;
3682 }
3683 udelay(1); /* should be 0.5us */
3684 }
3685 if (i == 4) {
3686 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3687 continue;
3688 }
357555c0 3689
139ccd3f 3690 /* Train 2 */
357555c0
JB		 3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
139ccd3f
JB		 3693 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3695 I915_WRITE(reg, temp);
3696
3697 reg = FDI_RX_CTL(pipe);
3698 temp = I915_READ(reg);
3699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3701 I915_WRITE(reg, temp);
3702
3703 POSTING_READ(reg);
139ccd3f 3704 udelay(2); /* should be 1.5us */
357555c0 3705
139ccd3f
JB		 3706 for (i = 0; i < 4; i++) {
3707 reg = FDI_RX_IIR(pipe);
3708 temp = I915_READ(reg);
3709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3710
139ccd3f
JB		 3711 if (temp & FDI_RX_SYMBOL_LOCK ||
3712 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3714 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3715 i);
3716 goto train_done;
3717 }
3718 udelay(2); /* should be 1.5us */
357555c0 3719 }
139ccd3f
JB		 3720 if (i == 4)
3721 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3722 }
357555c0 3723
139ccd3f 3724train_done:
357555c0
JB		 3725 DRM_DEBUG_KMS("FDI train done.\n");
3726}
3727
88cefb6c 3728static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3729{
88cefb6c 3730 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3731 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3732 int pipe = intel_crtc->pipe;
5eddb70b 3733 u32 reg, temp;
79e53945 3734
c64e311e 3735
c98e9dcf 3736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
627eb5a3 3739 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3740 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3741 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3743
3744 POSTING_READ(reg);
c98e9dcf
JB		 3745 udelay(200);
3746
3747 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp | FDI_PCDCLK);
3750
3751 POSTING_READ(reg);
c98e9dcf
JB		 3752 udelay(200);
3753
20749730
PZ		 3754 /* Enable CPU FDI TX PLL, always on for Ironlake */
3755 reg = FDI_TX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3758 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3759
20749730
PZ		 3760 POSTING_READ(reg);
3761 udelay(100);
6be4a607 3762 }
0e23b99d
JB		 3763}
3764
88cefb6c
DV		 3765static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3766{
3767 struct drm_device *dev = intel_crtc->base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 int pipe = intel_crtc->pipe;
3770 u32 reg, temp;
3771
3772 /* Switch from PCDclk to Rawclk */
3773 reg = FDI_RX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3776
3777 /* Disable CPU FDI TX PLL */
3778 reg = FDI_TX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3781
3782 POSTING_READ(reg);
3783 udelay(100);
3784
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3788
3789 /* Wait for the clocks to turn off. */
3790 POSTING_READ(reg);
3791 udelay(100);
3792}
3793
0fc932b8
JB		 3794static void ironlake_fdi_disable(struct drm_crtc *crtc)
3795{
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3800 u32 reg, temp;
3801
3802 /* disable CPU FDI tx and PCH FDI rx */
3803 reg = FDI_TX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3806 POSTING_READ(reg);
3807
3808 reg = FDI_RX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 temp &= ~(0x7 << 16);
dfd07d72 3811 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3812 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3813
3814 POSTING_READ(reg);
3815 udelay(100);
3816
3817 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3818 if (HAS_PCH_IBX(dev))
6f06ce18 3819 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3820
3821 /* still set train pattern 1 */
3822 reg = FDI_TX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~FDI_LINK_TRAIN_NONE;
3825 temp |= FDI_LINK_TRAIN_PATTERN_1;
3826 I915_WRITE(reg, temp);
3827
3828 reg = FDI_RX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 if (HAS_PCH_CPT(dev)) {
3831 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3833 } else {
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 }
3837 /* BPC in FDI rx is consistent with that in PIPECONF */
3838 temp &= ~(0x07 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844}
3845
5dce5b93
CW		 3846bool intel_has_pending_fb_unpin(struct drm_device *dev)
3847{
3848 struct intel_crtc *crtc;
3849
3850 /* Note that we don't need to be called with mode_config.lock here
3851 * as our list of CRTC objects is static for the lifetime of the
3852 * device and so cannot disappear as we iterate. Similarly, we can
3853 * happily treat the predicates as racy, atomic checks as userspace
3854 * cannot claim and pin a new fb without at least acquring the
3855 * struct_mutex and so serialising with us.
3856 */
d3fcc808 3857 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3858 if (atomic_read(&crtc->unpin_work_count) == 0)
3859 continue;
3860
3861 if (crtc->unpin_work)
3862 intel_wait_for_vblank(dev, crtc->pipe);
3863
3864 return true;
3865 }
3866
3867 return false;
3868}
3869
d6bbafa1
CW		 3870static void page_flip_completed(struct intel_crtc *intel_crtc)
3871{
3872 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3873 struct intel_unpin_work *work = intel_crtc->unpin_work;
3874
3875 /* ensure that the unpin work is consistent wrt ->pending. */
3876 smp_rmb();
3877 intel_crtc->unpin_work = NULL;
3878
3879 if (work->event)
3880 drm_send_vblank_event(intel_crtc->base.dev,
3881 intel_crtc->pipe,
3882 work->event);
3883
3884 drm_crtc_vblank_put(&intel_crtc->base);
3885
3886 wake_up_all(&dev_priv->pending_flip_queue);
3887 queue_work(dev_priv->wq, &work->work);
3888
3889 trace_i915_flip_complete(intel_crtc->plane,
3890 work->pending_flip_obj);
3891}
3892
5008e874 3893static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3894{
0f91128d 3895 struct drm_device *dev = crtc->dev;
5bb61643 3896 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3897 long ret;
e6c3a2a6 3898
2c10d571 3899 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML		 3900
3901 ret = wait_event_interruptible_timeout(
3902 dev_priv->pending_flip_queue,
3903 !intel_crtc_has_pending_flip(crtc),
3904 60*HZ);
3905
3906 if (ret < 0)
3907 return ret;
3908
3909 if (ret == 0) {
9c787942 3910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3911
5e2d7afc 3912 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3913 if (intel_crtc->unpin_work) {
3914 WARN_ONCE(1, "Removing stuck page flip\n");
3915 page_flip_completed(intel_crtc);
3916 }
5e2d7afc 3917 spin_unlock_irq(&dev->event_lock);
9c787942 3918 }
5bb61643 3919
5008e874 3920 return 0;
e6c3a2a6
CW		 3921}
3922
e615efe4
ED		 3923/* Program iCLKIP clock to the desired frequency */
3924static void lpt_program_iclkip(struct drm_crtc *crtc)
3925{
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3928 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3929 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3930 u32 temp;
3931
a580516d 3932 mutex_lock(&dev_priv->sb_lock);
09153000 3933
e615efe4
ED		 3934 /* It is necessary to ungate the pixclk gate prior to programming
3935 * the divisors, and gate it back when it is done.
3936 */
3937 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3938
3939 /* Disable SSCCTL */
3940 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3941 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3942 SBI_SSCCTL_DISABLE,
3943 SBI_ICLK);
e615efe4
ED		 3944
3945 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3946 if (clock == 20000) {
e615efe4
ED		 3947 auxdiv = 1;
3948 divsel = 0x41;
3949 phaseinc = 0x20;
3950 } else {
3951 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3952 * but the adjusted_mode->crtc_clock in in KHz. To get the
3953 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3954 * convert the virtual clock precision to KHz here for higher
3955 * precision.
3956 */
3957 u32 iclk_virtual_root_freq = 172800 * 1000;
3958 u32 iclk_pi_range = 64;
3959 u32 desired_divisor, msb_divisor_value, pi_value;
3960
12d7ceed 3961 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3962 msb_divisor_value = desired_divisor / iclk_pi_range;
3963 pi_value = desired_divisor % iclk_pi_range;
3964
3965 auxdiv = 0;
3966 divsel = msb_divisor_value - 2;
3967 phaseinc = pi_value;
3968 }
3969
3970 /* This should not happen with any sane values */
3971 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3972 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3973 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3974 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3975
3976 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3977 clock,
e615efe4
ED		 3978 auxdiv,
3979 divsel,
3980 phasedir,
3981 phaseinc);
3982
3983 /* Program SSCDIVINTPHASE6 */
988d6ee8 3984 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3985 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3986 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3987 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3988 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3989 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3990 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3991 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3992
3993 /* Program SSCAUXDIV */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3996 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3997 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3998
3999 /* Enable modulator and associated divider */
988d6ee8 4000 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4001 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4002 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4003
4004 /* Wait for initialization time */
4005 udelay(24);
4006
4007 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4008
a580516d 4009 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4010}
4011
275f01b2
DV		 4012static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4013 enum pipe pch_transcoder)
4014{
4015 struct drm_device *dev = crtc->base.dev;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4017 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4018
4019 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4020 I915_READ(HTOTAL(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4022 I915_READ(HBLANK(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4024 I915_READ(HSYNC(cpu_transcoder)));
4025
4026 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4027 I915_READ(VTOTAL(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4029 I915_READ(VBLANK(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4031 I915_READ(VSYNC(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4033 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4034}
4035
003632d9 4036static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4037{
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039 uint32_t temp;
4040
4041 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4042 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4043 return;
4044
4045 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4046 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4047
003632d9
ACO		 4048 temp &= ~FDI_BC_BIFURCATION_SELECT;
4049 if (enable)
4050 temp |= FDI_BC_BIFURCATION_SELECT;
4051
4052 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4053 I915_WRITE(SOUTH_CHICKEN1, temp);
4054 POSTING_READ(SOUTH_CHICKEN1);
4055}
4056
4057static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4058{
4059 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4060
4061 switch (intel_crtc->pipe) {
4062 case PIPE_A:
4063 break;
4064 case PIPE_B:
6e3c9717 4065 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4066 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4067 else
003632d9 4068 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4069
4070 break;
4071 case PIPE_C:
003632d9 4072 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4073
4074 break;
4075 default:
4076 BUG();
4077 }
4078}
4079
f67a559d
JB		 4080/*
4081 * Enable PCH resources required for PCH ports:
4082 * - PCH PLLs
4083 * - FDI training & RX/TX
4084 * - update transcoder timings
4085 * - DP transcoding bits
4086 * - transcoder
4087 */
4088static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4089{
4090 struct drm_device *dev = crtc->dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 int pipe = intel_crtc->pipe;
ee7b9f93 4094 u32 reg, temp;
2c07245f 4095
ab9412ba 4096 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4097
1fbc0d78
DV		 4098 if (IS_IVYBRIDGE(dev))
4099 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4100
cd986abb
DV		 4101 /* Write the TU size bits before fdi link training, so that error
4102 * detection works. */
4103 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4104 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4105
c98e9dcf 4106 /* For PCH output, training FDI link */
674cf967 4107 dev_priv->display.fdi_link_train(crtc);
2c07245f 4108
3ad8a208
DV		 4109 /* We need to program the right clock selection before writing the pixel
4110 * mutliplier into the DPLL. */
303b81e0 4111 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4112 u32 sel;
4b645f14 4113
c98e9dcf 4114 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4115 temp |= TRANS_DPLL_ENABLE(pipe);
4116 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4117 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4118 temp |= sel;
4119 else
4120 temp &= ~sel;
c98e9dcf 4121 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4122 }
5eddb70b 4123
3ad8a208
DV		 4124 /* XXX: pch pll's can be enabled any time before we enable the PCH
4125 * transcoder, and we actually should do this to not upset any PCH
4126 * transcoder that already use the clock when we share it.
4127 *
4128 * Note that enable_shared_dpll tries to do the right thing, but
4129 * get_shared_dpll unconditionally resets the pll - we need that to have
4130 * the right LVDS enable sequence. */
85b3894f 4131 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4132
d9b6cb56
JB		 4133 /* set transcoder timing, panel must allow it */
4134 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4135 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4136
303b81e0 4137 intel_fdi_normal_train(crtc);
5e84e1a4 4138
c98e9dcf 4139 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4140 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4142 reg = TRANS_DP_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4145 TRANS_DP_SYNC_MASK |
4146 TRANS_DP_BPC_MASK);
e3ef4479 4147 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4148 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4149
4150 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4151 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4152 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4153 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4154
4155 switch (intel_trans_dp_port_sel(crtc)) {
4156 case PCH_DP_B:
5eddb70b 4157 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4158 break;
4159 case PCH_DP_C:
5eddb70b 4160 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4161 break;
4162 case PCH_DP_D:
5eddb70b 4163 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4164 break;
4165 default:
e95d41e1 4166 BUG();
32f9d658 4167 }
2c07245f 4168
5eddb70b 4169 I915_WRITE(reg, temp);
6be4a607 4170 }
b52eb4dc 4171
b8a4f404 4172 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4173}
4174
1507e5bd
PZ		 4175static void lpt_pch_enable(struct drm_crtc *crtc)
4176{
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4181
ab9412ba 4182 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4183
8c52b5e8 4184 lpt_program_iclkip(crtc);
1507e5bd 4185
0540e488 4186 /* Set transcoder timing. */
275f01b2 4187 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4188
937bb610 4189 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4190}
4191
190f68c5
ACO		 4192struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4193 struct intel_crtc_state *crtc_state)
ee7b9f93 4194{
e2b78267 4195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4196 struct intel_shared_dpll *pll;
de419ab6 4197 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4198 enum intel_dpll_id i;
ee7b9f93 4199
de419ab6
ML		 4200 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4201
98b6bd99
DV		 4202 if (HAS_PCH_IBX(dev_priv->dev)) {
4203 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4204 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4205 pll = &dev_priv->shared_dplls[i];
98b6bd99 4206
46edb027
DV		 4207 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4208 crtc->base.base.id, pll->name);
98b6bd99 4209
de419ab6 4210 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4211
98b6bd99
DV		 4212 goto found;
4213 }
4214
bcddf610
S		 4215 if (IS_BROXTON(dev_priv->dev)) {
4216 /* PLL is attached to port in bxt */
4217 struct intel_encoder *encoder;
4218 struct intel_digital_port *intel_dig_port;
4219
4220 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4221 if (WARN_ON(!encoder))
4222 return NULL;
4223
4224 intel_dig_port = enc_to_dig_port(&encoder->base);
4225 /* 1:1 mapping between ports and PLLs */
4226 i = (enum intel_dpll_id)intel_dig_port->port;
4227 pll = &dev_priv->shared_dplls[i];
4228 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4229 crtc->base.base.id, pll->name);
de419ab6 4230 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4231
4232 goto found;
4233 }
4234
e72f9fbf
DV		 4235 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4236 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4237
4238 /* Only want to check enabled timings first */
de419ab6 4239 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4240 continue;
4241
190f68c5 4242 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4243 &shared_dpll[i].hw_state,
4244 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4245 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4246 crtc->base.base.id, pll->name,
de419ab6 4247 shared_dpll[i].crtc_mask,
8bd31e67 4248 pll->active);
ee7b9f93
JB		 4249 goto found;
4250 }
4251 }
4252
4253 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4254 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4255 pll = &dev_priv->shared_dplls[i];
de419ab6 4256 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4257 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4258 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4259 goto found;
4260 }
4261 }
4262
4263 return NULL;
4264
4265found:
de419ab6
ML		 4266 if (shared_dpll[i].crtc_mask == 0)
4267 shared_dpll[i].hw_state =
4268 crtc_state->dpll_hw_state;
f2a69f44 4269
190f68c5 4270 crtc_state->shared_dpll = i;
46edb027
DV		 4271 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4272 pipe_name(crtc->pipe));
ee7b9f93 4273
de419ab6 4274 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4275
ee7b9f93
JB		 4276 return pll;
4277}
4278
de419ab6 4279static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4280{
de419ab6
ML		 4281 struct drm_i915_private *dev_priv = to_i915(state->dev);
4282 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4283 struct intel_shared_dpll *pll;
4284 enum intel_dpll_id i;
4285
de419ab6
ML		 4286 if (!to_intel_atomic_state(state)->dpll_set)
4287 return;
8bd31e67 4288
de419ab6 4289 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4290 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4291 pll = &dev_priv->shared_dplls[i];
de419ab6 4292 pll->config = shared_dpll[i];
8bd31e67
ACO		 4293 }
4294}
4295
a1520318 4296static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4297{
4298 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4299 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4300 u32 temp;
4301
4302 temp = I915_READ(dslreg);
4303 udelay(500);
4304 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4305 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4306 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4307 }
4308}
4309
86adf9d7
ML		 4310static int
4311skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4312 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4313 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4314{
86adf9d7
ML		 4315 struct intel_crtc_scaler_state *scaler_state =
4316 &crtc_state->scaler_state;
4317 struct intel_crtc *intel_crtc =
4318 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4319 int need_scaling;
6156a456
CK		 4320
4321 need_scaling = intel_rotation_90_or_270(rotation) ?
4322 (src_h != dst_w || src_w != dst_h):
4323 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4324
4325 /*
4326 * if plane is being disabled or scaler is no more required or force detach
4327 * - free scaler binded to this plane/crtc
4328 * - in order to do this, update crtc->scaler_usage
4329 *
4330 * Here scaler state in crtc_state is set free so that
4331 * scaler can be assigned to other user. Actual register
4332 * update to free the scaler is done in plane/panel-fit programming.
4333 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4334 */
86adf9d7 4335 if (force_detach || !need_scaling) {
a1b2278e 4336 if (*scaler_id >= 0) {
86adf9d7 4337 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4338 scaler_state->scalers[*scaler_id].in_use = 0;
4339
86adf9d7
ML		 4340 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4341 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4342 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4343 scaler_state->scaler_users);
4344 *scaler_id = -1;
4345 }
4346 return 0;
4347 }
4348
4349 /* range checks */
4350 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4351 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4352
4353 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4354 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4355 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4356 "size is out of scaler range\n",
86adf9d7 4357 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4358 return -EINVAL;
4359 }
4360
86adf9d7
ML		 4361 /* mark this plane as a scaler user in crtc_state */
4362 scaler_state->scaler_users |= (1 << scaler_user);
4363 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4364 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4365 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4366 scaler_state->scaler_users);
4367
4368 return 0;
4369}
4370
4371/**
4372 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4373 *
4374 * @state: crtc's scaler state
86adf9d7
ML		 4375 *
4376 * Return
4377 * 0 - scaler_usage updated successfully
4378 * error - requested scaling cannot be supported or other error condition
4379 */
e435d6e5 4380int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4381{
4382 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4383 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4384
4385 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4386 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4387
e435d6e5 4388 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4389 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4390 state->pipe_src_w, state->pipe_src_h,
aad941d5 4391 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4392}
4393
4394/**
4395 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4396 *
4397 * @state: crtc's scaler state
86adf9d7
ML		 4398 * @plane_state: atomic plane state to update
4399 *
4400 * Return
4401 * 0 - scaler_usage updated successfully
4402 * error - requested scaling cannot be supported or other error condition
4403 */
da20eabd
ML		 4404static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4405 struct intel_plane_state *plane_state)
86adf9d7
ML		 4406{
4407
4408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4409 struct intel_plane *intel_plane =
4410 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4411 struct drm_framebuffer *fb = plane_state->base.fb;
4412 int ret;
4413
4414 bool force_detach = !fb || !plane_state->visible;
4415
4416 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4417 intel_plane->base.base.id, intel_crtc->pipe,
4418 drm_plane_index(&intel_plane->base));
4419
4420 ret = skl_update_scaler(crtc_state, force_detach,
4421 drm_plane_index(&intel_plane->base),
4422 &plane_state->scaler_id,
4423 plane_state->base.rotation,
4424 drm_rect_width(&plane_state->src) >> 16,
4425 drm_rect_height(&plane_state->src) >> 16,
4426 drm_rect_width(&plane_state->dst),
4427 drm_rect_height(&plane_state->dst));
4428
4429 if (ret || plane_state->scaler_id < 0)
4430 return ret;
4431
a1b2278e 4432 /* check colorkey */
818ed961 4433 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4434 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4435 intel_plane->base.base.id);
a1b2278e
CK		 4436 return -EINVAL;
4437 }
4438
4439 /* Check src format */
86adf9d7
ML		 4440 switch (fb->pixel_format) {
4441 case DRM_FORMAT_RGB565:
4442 case DRM_FORMAT_XBGR8888:
4443 case DRM_FORMAT_XRGB8888:
4444 case DRM_FORMAT_ABGR8888:
4445 case DRM_FORMAT_ARGB8888:
4446 case DRM_FORMAT_XRGB2101010:
4447 case DRM_FORMAT_XBGR2101010:
4448 case DRM_FORMAT_YUYV:
4449 case DRM_FORMAT_YVYU:
4450 case DRM_FORMAT_UYVY:
4451 case DRM_FORMAT_VYUY:
4452 break;
4453 default:
4454 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4455 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4456 return -EINVAL;
a1b2278e
CK		 4457 }
4458
a1b2278e
CK		 4459 return 0;
4460}
4461
e435d6e5
ML		 4462static void skylake_scaler_disable(struct intel_crtc *crtc)
4463{
4464 int i;
4465
4466 for (i = 0; i < crtc->num_scalers; i++)
4467 skl_detach_scaler(crtc, i);
4468}
4469
4470static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4471{
4472 struct drm_device *dev = crtc->base.dev;
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474 int pipe = crtc->pipe;
a1b2278e
CK		 4475 struct intel_crtc_scaler_state *scaler_state =
4476 &crtc->config->scaler_state;
4477
4478 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4479
6e3c9717 4480 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4481 int id;
4482
4483 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4484 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4485 return;
4486 }
4487
4488 id = scaler_state->scaler_id;
4489 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4490 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4491 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4492 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4493
4494 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4495 }
4496}
4497
b074cec8
JB		 4498static void ironlake_pfit_enable(struct intel_crtc *crtc)
4499{
4500 struct drm_device *dev = crtc->base.dev;
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 int pipe = crtc->pipe;
4503
6e3c9717 4504 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4505 /* Force use of hard-coded filter coefficients
4506 * as some pre-programmed values are broken,
4507 * e.g. x201.
4508 */
4509 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4510 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4511 PF_PIPE_SEL_IVB(pipe));
4512 else
4513 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4514 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4515 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4516 }
4517}
4518
20bc8673 4519void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4520{
cea165c3
VS		 4521 struct drm_device *dev = crtc->base.dev;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4523
6e3c9717 4524 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4525 return;
4526
cea165c3
VS		 4527 /* We can only enable IPS after we enable a plane and wait for a vblank */
4528 intel_wait_for_vblank(dev, crtc->pipe);
4529
d77e4531 4530 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4531 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4532 mutex_lock(&dev_priv->rps.hw_lock);
4533 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4534 mutex_unlock(&dev_priv->rps.hw_lock);
4535 /* Quoting Art Runyan: "its not safe to expect any particular
4536 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4537 * mailbox." Moreover, the mailbox may return a bogus state,
4538 * so we need to just enable it and continue on.
2a114cc1
BW		 4539 */
4540 } else {
4541 I915_WRITE(IPS_CTL, IPS_ENABLE);
4542 /* The bit only becomes 1 in the next vblank, so this wait here
4543 * is essentially intel_wait_for_vblank. If we don't have this
4544 * and don't wait for vblanks until the end of crtc_enable, then
4545 * the HW state readout code will complain that the expected
4546 * IPS_CTL value is not the one we read. */
4547 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4548 DRM_ERROR("Timed out waiting for IPS enable\n");
4549 }
d77e4531
PZ		 4550}
4551
20bc8673 4552void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4553{
4554 struct drm_device *dev = crtc->base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556
6e3c9717 4557 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4558 return;
4559
4560 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4561 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4562 mutex_lock(&dev_priv->rps.hw_lock);
4563 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4564 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4565 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4566 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4567 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4568 } else {
2a114cc1 4569 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4570 POSTING_READ(IPS_CTL);
4571 }
d77e4531
PZ		 4572
4573 /* We need to wait for a vblank before we can disable the plane. */
4574 intel_wait_for_vblank(dev, crtc->pipe);
4575}
4576
4577/** Loads the palette/gamma unit for the CRTC with the prepared values */
4578static void intel_crtc_load_lut(struct drm_crtc *crtc)
4579{
4580 struct drm_device *dev = crtc->dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4583 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4584 int i;
4585 bool reenable_ips = false;
4586
4587 /* The clocks have to be on to load the palette. */
53d9f4e9 4588 if (!crtc->state->active)
d77e4531
PZ		 4589 return;
4590
50360403 4591 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4592 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4593 assert_dsi_pll_enabled(dev_priv);
4594 else
4595 assert_pll_enabled(dev_priv, pipe);
4596 }
4597
d77e4531
PZ		 4598 /* Workaround : Do not read or write the pipe palette/gamma data while
4599 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4600 */
6e3c9717 4601 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4602 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4603 GAMMA_MODE_MODE_SPLIT)) {
4604 hsw_disable_ips(intel_crtc);
4605 reenable_ips = true;
4606 }
4607
4608 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4609 u32 palreg;
4610
4611 if (HAS_GMCH_DISPLAY(dev))
4612 palreg = PALETTE(pipe, i);
4613 else
4614 palreg = LGC_PALETTE(pipe, i);
4615
4616 I915_WRITE(palreg,
d77e4531
PZ		 4617 (intel_crtc->lut_r[i] << 16) |
4618 (intel_crtc->lut_g[i] << 8) |
4619 intel_crtc->lut_b[i]);
4620 }
4621
4622 if (reenable_ips)
4623 hsw_enable_ips(intel_crtc);
4624}
4625
7cac945f 4626static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4627{
7cac945f 4628 if (intel_crtc->overlay) {
d3eedb1a
VS		 4629 struct drm_device *dev = intel_crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631
4632 mutex_lock(&dev->struct_mutex);
4633 dev_priv->mm.interruptible = false;
4634 (void) intel_overlay_switch_off(intel_crtc->overlay);
4635 dev_priv->mm.interruptible = true;
4636 mutex_unlock(&dev->struct_mutex);
4637 }
4638
4639 /* Let userspace switch the overlay on again. In most cases userspace
4640 * has to recompute where to put it anyway.
4641 */
4642}
4643
87d4300a
ML		 4644/**
4645 * intel_post_enable_primary - Perform operations after enabling primary plane
4646 * @crtc: the CRTC whose primary plane was just enabled
4647 *
4648 * Performs potentially sleeping operations that must be done after the primary
4649 * plane is enabled, such as updating FBC and IPS. Note that this may be
4650 * called due to an explicit primary plane update, or due to an implicit
4651 * re-enable that is caused when a sprite plane is updated to no longer
4652 * completely hide the primary plane.
4653 */
4654static void
4655intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4656{
4657 struct drm_device *dev = crtc->dev;
87d4300a 4658 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4660 int pipe = intel_crtc->pipe;
a5c4d7bc 4661
87d4300a
ML		 4662 /*
4663 * BDW signals flip done immediately if the plane
4664 * is disabled, even if the plane enable is already
4665 * armed to occur at the next vblank :(
4666 */
4667 if (IS_BROADWELL(dev))
4668 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4669
87d4300a
ML		 4670 /*
4671 * FIXME IPS should be fine as long as one plane is
4672 * enabled, but in practice it seems to have problems
4673 * when going from primary only to sprite only and vice
4674 * versa.
4675 */
a5c4d7bc
VS		 4676 hsw_enable_ips(intel_crtc);
4677
f99d7069 4678 /*
87d4300a
ML		 4679 * Gen2 reports pipe underruns whenever all planes are disabled.
4680 * So don't enable underrun reporting before at least some planes
4681 * are enabled.
4682 * FIXME: Need to fix the logic to work when we turn off all planes
4683 * but leave the pipe running.
f99d7069 4684 */
87d4300a
ML		 4685 if (IS_GEN2(dev))
4686 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4687
4688 /* Underruns don't raise interrupts, so check manually. */
4689 if (HAS_GMCH_DISPLAY(dev))
4690 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4691}
4692
87d4300a
ML		 4693/**
4694 * intel_pre_disable_primary - Perform operations before disabling primary plane
4695 * @crtc: the CRTC whose primary plane is to be disabled
4696 *
4697 * Performs potentially sleeping operations that must be done before the
4698 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4699 * be called due to an explicit primary plane update, or due to an implicit
4700 * disable that is caused when a sprite plane completely hides the primary
4701 * plane.
4702 */
4703static void
4704intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4705{
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 int pipe = intel_crtc->pipe;
a5c4d7bc 4710
87d4300a
ML		 4711 /*
4712 * Gen2 reports pipe underruns whenever all planes are disabled.
4713 * So diasble underrun reporting before all the planes get disabled.
4714 * FIXME: Need to fix the logic to work when we turn off all planes
4715 * but leave the pipe running.
4716 */
4717 if (IS_GEN2(dev))
4718 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4719
87d4300a
ML		 4720 /*
4721 * Vblank time updates from the shadow to live plane control register
4722 * are blocked if the memory self-refresh mode is active at that
4723 * moment. So to make sure the plane gets truly disabled, disable
4724 * first the self-refresh mode. The self-refresh enable bit in turn
4725 * will be checked/applied by the HW only at the next frame start
4726 * event which is after the vblank start event, so we need to have a
4727 * wait-for-vblank between disabling the plane and the pipe.
4728 */
262cd2e1 4729 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4730 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4731 dev_priv->wm.vlv.cxsr = false;
4732 intel_wait_for_vblank(dev, pipe);
4733 }
87d4300a 4734
87d4300a
ML		 4735 /*
4736 * FIXME IPS should be fine as long as one plane is
4737 * enabled, but in practice it seems to have problems
4738 * when going from primary only to sprite only and vice
4739 * versa.
4740 */
a5c4d7bc 4741 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4742}
4743
ac21b225
ML		 4744static void intel_post_plane_update(struct intel_crtc *crtc)
4745{
4746 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4747 struct drm_device *dev = crtc->base.dev;
7733b49b 4748 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4749
4750 if (atomic->wait_vblank)
4751 intel_wait_for_vblank(dev, crtc->pipe);
4752
4753 intel_frontbuffer_flip(dev, atomic->fb_bits);
4754
852eb00d
VS		 4755 if (atomic->disable_cxsr)
4756 crtc->wm.cxsr_allowed = true;
4757
f015c551
VS		 4758 if (crtc->atomic.update_wm_post)
4759 intel_update_watermarks(&crtc->base);
4760
c80ac854 4761 if (atomic->update_fbc)
7733b49b 4762 intel_fbc_update(dev_priv);
ac21b225
ML		 4763
4764 if (atomic->post_enable_primary)
4765 intel_post_enable_primary(&crtc->base);
4766
ac21b225
ML		 4767 memset(atomic, 0, sizeof(*atomic));
4768}
4769
4770static void intel_pre_plane_update(struct intel_crtc *crtc)
4771{
4772 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4773 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225 4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
ac21b225 4775
c80ac854 4776 if (atomic->disable_fbc)
25ad93fd 4777 intel_fbc_disable_crtc(crtc);
ac21b225 4778
066cf55b
RV		 4779 if (crtc->atomic.disable_ips)
4780 hsw_disable_ips(crtc);
4781
ac21b225
ML		 4782 if (atomic->pre_disable_primary)
4783 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4784
4785 if (atomic->disable_cxsr) {
4786 crtc->wm.cxsr_allowed = false;
4787 intel_set_memory_cxsr(dev_priv, false);
4788 }
ac21b225
ML		 4789}
4790
d032ffa0 4791static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4792{
4793 struct drm_device *dev = crtc->dev;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4795 struct drm_plane *p;
87d4300a
ML		 4796 int pipe = intel_crtc->pipe;
4797
7cac945f 4798 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4799
d032ffa0
ML		 4800 drm_for_each_plane_mask(p, dev, plane_mask)
4801 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4802
f99d7069
DV		 4803 /*
4804 * FIXME: Once we grow proper nuclear flip support out of this we need
4805 * to compute the mask of flip planes precisely. For the time being
4806 * consider this a flip to a NULL plane.
4807 */
4808 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4809}
4810
f67a559d
JB		 4811static void ironlake_crtc_enable(struct drm_crtc *crtc)
4812{
4813 struct drm_device *dev = crtc->dev;
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4816 struct intel_encoder *encoder;
f67a559d 4817 int pipe = intel_crtc->pipe;
f67a559d 4818
53d9f4e9 4819 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4820 return;
4821
6e3c9717 4822 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4823 intel_prepare_shared_dpll(intel_crtc);
4824
6e3c9717 4825 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4826 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4827
4828 intel_set_pipe_timings(intel_crtc);
4829
6e3c9717 4830 if (intel_crtc->config->has_pch_encoder) {
29407aab 4831 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4832 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4833 }
4834
4835 ironlake_set_pipeconf(crtc);
4836
f67a559d 4837 intel_crtc->active = true;
8664281b 4838
a72e4c9f
DV		 4839 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4840 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4841
f6736a1a 4842 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4843 if (encoder->pre_enable)
4844 encoder->pre_enable(encoder);
f67a559d 4845
6e3c9717 4846 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4847 /* Note: FDI PLL enabling _must_ be done before we enable the
4848 * cpu pipes, hence this is separate from all the other fdi/pch
4849 * enabling. */
88cefb6c 4850 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4851 } else {
4852 assert_fdi_tx_disabled(dev_priv, pipe);
4853 assert_fdi_rx_disabled(dev_priv, pipe);
4854 }
f67a559d 4855
b074cec8 4856 ironlake_pfit_enable(intel_crtc);
f67a559d 4857
9c54c0dd
JB		 4858 /*
4859 * On ILK+ LUT must be loaded before the pipe is running but with
4860 * clocks enabled
4861 */
4862 intel_crtc_load_lut(crtc);
4863
f37fcc2a 4864 intel_update_watermarks(crtc);
e1fdc473 4865 intel_enable_pipe(intel_crtc);
f67a559d 4866
6e3c9717 4867 if (intel_crtc->config->has_pch_encoder)
f67a559d 4868 ironlake_pch_enable(crtc);
c98e9dcf 4869
f9b61ff6
DV		 4870 assert_vblank_disabled(crtc);
4871 drm_crtc_vblank_on(crtc);
4872
fa5c73b1
DV		 4873 for_each_encoder_on_crtc(dev, crtc, encoder)
4874 encoder->enable(encoder);
61b77ddd
DV		 4875
4876 if (HAS_PCH_CPT(dev))
a1520318 4877 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4878}
4879
42db64ef
PZ		 4880/* IPS only exists on ULT machines and is tied to pipe A. */
4881static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4882{
f5adf94e 4883 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4884}
4885
4f771f10
PZ		 4886static void haswell_crtc_enable(struct drm_crtc *crtc)
4887{
4888 struct drm_device *dev = crtc->dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891 struct intel_encoder *encoder;
99d736a2
ML		 4892 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4893 struct intel_crtc_state *pipe_config =
4894 to_intel_crtc_state(crtc->state);
7d4aefd0 4895 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4f771f10 4896
53d9f4e9 4897 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4898 return;
4899
df8ad70c
DV		 4900 if (intel_crtc_to_shared_dpll(intel_crtc))
4901 intel_enable_shared_dpll(intel_crtc);
4902
6e3c9717 4903 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4904 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4905
4906 intel_set_pipe_timings(intel_crtc);
4907
6e3c9717
ACO		 4908 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4909 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4910 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4911 }
4912
6e3c9717 4913 if (intel_crtc->config->has_pch_encoder) {
229fca97 4914 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4915 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4916 }
4917
4918 haswell_set_pipeconf(crtc);
4919
4920 intel_set_pipe_csc(crtc);
4921
4f771f10 4922 intel_crtc->active = true;
8664281b 4923
a72e4c9f 4924 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7d4aefd0
SS		 4925 for_each_encoder_on_crtc(dev, crtc, encoder) {
4926 if (encoder->pre_pll_enable)
4927 encoder->pre_pll_enable(encoder);
4f771f10
PZ		 4928 if (encoder->pre_enable)
4929 encoder->pre_enable(encoder);
7d4aefd0 4930 }
4f771f10 4931
6e3c9717 4932 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4933 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4934 true);
4fe9467d
ID		 4935 dev_priv->display.fdi_link_train(crtc);
4936 }
4937
7d4aefd0
SS		 4938 if (!is_dsi)
4939 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4940
1c132b44 4941 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4942 skylake_pfit_enable(intel_crtc);
ff6d9f55 4943 else
1c132b44 4944 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4945
4946 /*
4947 * On ILK+ LUT must be loaded before the pipe is running but with
4948 * clocks enabled
4949 */
4950 intel_crtc_load_lut(crtc);
4951
1f544388 4952 intel_ddi_set_pipe_settings(crtc);
7d4aefd0
SS		 4953 if (!is_dsi)
4954 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4955
f37fcc2a 4956 intel_update_watermarks(crtc);
e1fdc473 4957 intel_enable_pipe(intel_crtc);
42db64ef 4958
6e3c9717 4959 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4960 lpt_pch_enable(crtc);
4f771f10 4961
7d4aefd0 4962 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
0e32b39c
DA		 4963 intel_ddi_set_vc_payload_alloc(crtc, true);
4964
f9b61ff6
DV		 4965 assert_vblank_disabled(crtc);
4966 drm_crtc_vblank_on(crtc);
4967
8807e55b 4968 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4969 encoder->enable(encoder);
8807e55b
JN		 4970 intel_opregion_notify_encoder(encoder, true);
4971 }
4f771f10 4972
e4916946
PZ		 4973 /* If we change the relative order between pipe/planes enabling, we need
4974 * to change the workaround. */
99d736a2
ML		 4975 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4976 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4977 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4978 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4979 }
4f771f10
PZ		 4980}
4981
bfd16b2a 4982static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4983{
4984 struct drm_device *dev = crtc->base.dev;
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 int pipe = crtc->pipe;
4987
4988 /* To avoid upsetting the power well on haswell only disable the pfit if
4989 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4990 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4991 I915_WRITE(PF_CTL(pipe), 0);
4992 I915_WRITE(PF_WIN_POS(pipe), 0);
4993 I915_WRITE(PF_WIN_SZ(pipe), 0);
4994 }
4995}
4996
6be4a607
JB		 4997static void ironlake_crtc_disable(struct drm_crtc *crtc)
4998{
4999 struct drm_device *dev = crtc->dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5002 struct intel_encoder *encoder;
6be4a607 5003 int pipe = intel_crtc->pipe;
5eddb70b 5004 u32 reg, temp;
b52eb4dc 5005
ea9d758d
DV		 5006 for_each_encoder_on_crtc(dev, crtc, encoder)
5007 encoder->disable(encoder);
5008
f9b61ff6
DV		 5009 drm_crtc_vblank_off(crtc);
5010 assert_vblank_disabled(crtc);
5011
6e3c9717 5012 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5013 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5014
575f7ab7 5015 intel_disable_pipe(intel_crtc);
32f9d658 5016
bfd16b2a 5017 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5018
5a74f70a
VS		 5019 if (intel_crtc->config->has_pch_encoder)
5020 ironlake_fdi_disable(crtc);
5021
bf49ec8c
DV		 5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->post_disable)
5024 encoder->post_disable(encoder);
2c07245f 5025
6e3c9717 5026 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5027 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5028
d925c59a
DV		 5029 if (HAS_PCH_CPT(dev)) {
5030 /* disable TRANS_DP_CTL */
5031 reg = TRANS_DP_CTL(pipe);
5032 temp = I915_READ(reg);
5033 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5034 TRANS_DP_PORT_SEL_MASK);
5035 temp |= TRANS_DP_PORT_SEL_NONE;
5036 I915_WRITE(reg, temp);
5037
5038 /* disable DPLL_SEL */
5039 temp = I915_READ(PCH_DPLL_SEL);
11887397 5040 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5041 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5042 }
e3421a18 5043
d925c59a
DV		 5044 ironlake_fdi_pll_disable(intel_crtc);
5045 }
6be4a607 5046}
1b3c7a47 5047
4f771f10 5048static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5049{
4f771f10
PZ		 5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5053 struct intel_encoder *encoder;
6e3c9717 5054 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7d4aefd0 5055 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
ee7b9f93 5056
8807e55b
JN		 5057 for_each_encoder_on_crtc(dev, crtc, encoder) {
5058 intel_opregion_notify_encoder(encoder, false);
4f771f10 5059 encoder->disable(encoder);
8807e55b 5060 }
4f771f10 5061
f9b61ff6
DV		 5062 drm_crtc_vblank_off(crtc);
5063 assert_vblank_disabled(crtc);
5064
6e3c9717 5065 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5066 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5067 false);
575f7ab7 5068 intel_disable_pipe(intel_crtc);
4f771f10 5069
6e3c9717 5070 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5071 intel_ddi_set_vc_payload_alloc(crtc, false);
5072
7d4aefd0
SS		 5073 if (!is_dsi)
5074 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5075
1c132b44 5076 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5077 skylake_scaler_disable(intel_crtc);
ff6d9f55 5078 else
bfd16b2a 5079 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5080
7d4aefd0
SS		 5081 if (!is_dsi)
5082 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5083
6e3c9717 5084 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5085 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5086 intel_ddi_fdi_disable(crtc);
83616634 5087 }
4f771f10 5088
97b040aa
ID		 5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 if (encoder->post_disable)
5091 encoder->post_disable(encoder);
4f771f10
PZ		 5092}
5093
2dd24552
JB		 5094static void i9xx_pfit_enable(struct intel_crtc *crtc)
5095{
5096 struct drm_device *dev = crtc->base.dev;
5097 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5098 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5099
681a8504 5100 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5101 return;
5102
2dd24552 5103 /*
c0b03411
DV		 5104 * The panel fitter should only be adjusted whilst the pipe is disabled,
5105 * according to register description and PRM.
2dd24552 5106 */
c0b03411
DV		 5107 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5108 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5109
b074cec8
JB		 5110 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5111 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5112
5113 /* Border color in case we don't scale up to the full screen. Black by
5114 * default, change to something else for debugging. */
5115 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5116}
5117
d05410f9
DA		 5118static enum intel_display_power_domain port_to_power_domain(enum port port)
5119{
5120 switch (port) {
5121 case PORT_A:
5122 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5123 case PORT_B:
5124 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5125 case PORT_C:
5126 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5127 case PORT_D:
5128 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5129 case PORT_E:
5130 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5131 default:
5132 WARN_ON_ONCE(1);
5133 return POWER_DOMAIN_PORT_OTHER;
5134 }
5135}
5136
77d22dca
ID		 5137#define for_each_power_domain(domain, mask) \
5138 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5139 if ((1 << (domain)) & (mask))
5140
319be8ae
ID		 5141enum intel_display_power_domain
5142intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5143{
5144 struct drm_device *dev = intel_encoder->base.dev;
5145 struct intel_digital_port *intel_dig_port;
5146
5147 switch (intel_encoder->type) {
5148 case INTEL_OUTPUT_UNKNOWN:
5149 /* Only DDI platforms should ever use this output type */
5150 WARN_ON_ONCE(!HAS_DDI(dev));
5151 case INTEL_OUTPUT_DISPLAYPORT:
5152 case INTEL_OUTPUT_HDMI:
5153 case INTEL_OUTPUT_EDP:
5154 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5155 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5156 case INTEL_OUTPUT_DP_MST:
5157 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5158 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5159 case INTEL_OUTPUT_ANALOG:
5160 return POWER_DOMAIN_PORT_CRT;
5161 case INTEL_OUTPUT_DSI:
5162 return POWER_DOMAIN_PORT_DSI;
5163 default:
5164 return POWER_DOMAIN_PORT_OTHER;
5165 }
5166}
5167
5168static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5169{
319be8ae
ID		 5170 struct drm_device *dev = crtc->dev;
5171 struct intel_encoder *intel_encoder;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5174 unsigned long mask;
5175 enum transcoder transcoder;
5176
292b990e
ML		 5177 if (!crtc->state->active)
5178 return 0;
5179
77d22dca
ID		 5180 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5181
5182 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5183 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5184 if (intel_crtc->config->pch_pfit.enabled ||
5185 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5186 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5187
319be8ae
ID		 5188 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5189 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5190
77d22dca
ID		 5191 return mask;
5192}
5193
292b990e 5194static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5195{
292b990e
ML		 5196 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198 enum intel_display_power_domain domain;
5199 unsigned long domains, new_domains, old_domains;
77d22dca 5200
292b990e
ML		 5201 old_domains = intel_crtc->enabled_power_domains;
5202 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5203
292b990e
ML		 5204 domains = new_domains & ~old_domains;
5205
5206 for_each_power_domain(domain, domains)
5207 intel_display_power_get(dev_priv, domain);
5208
5209 return old_domains & ~new_domains;
5210}
5211
5212static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5213 unsigned long domains)
5214{
5215 enum intel_display_power_domain domain;
5216
5217 for_each_power_domain(domain, domains)
5218 intel_display_power_put(dev_priv, domain);
5219}
77d22dca 5220
292b990e
ML		 5221static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5222{
5223 struct drm_device *dev = state->dev;
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5225 unsigned long put_domains[I915_MAX_PIPES] = {};
5226 struct drm_crtc_state *crtc_state;
5227 struct drm_crtc *crtc;
5228 int i;
77d22dca 5229
292b990e
ML		 5230 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5231 if (needs_modeset(crtc->state))
5232 put_domains[to_intel_crtc(crtc)->pipe] =
5233 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5234 }
5235
27c329ed
ML		 5236 if (dev_priv->display.modeset_commit_cdclk) {
5237 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5238
5239 if (cdclk != dev_priv->cdclk_freq &&
5240 !WARN_ON(!state->allow_modeset))
5241 dev_priv->display.modeset_commit_cdclk(state);
5242 }
50f6e502 5243
292b990e
ML		 5244 for (i = 0; i < I915_MAX_PIPES; i++)
5245 if (put_domains[i])
5246 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5247}
5248
adafdc6f
MK		 5249static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5250{
5251 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5252
5253 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5254 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5255 return max_cdclk_freq;
5256 else if (IS_CHERRYVIEW(dev_priv))
5257 return max_cdclk_freq*95/100;
5258 else if (INTEL_INFO(dev_priv)->gen < 4)
5259 return 2*max_cdclk_freq*90/100;
5260 else
5261 return max_cdclk_freq*90/100;
5262}
5263
560a7ae4
DL		 5264static void intel_update_max_cdclk(struct drm_device *dev)
5265{
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267
ef11bdb3 5268 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4
DL		 5269 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5270
5271 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5272 dev_priv->max_cdclk_freq = 675000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5274 dev_priv->max_cdclk_freq = 540000;
5275 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5276 dev_priv->max_cdclk_freq = 450000;
5277 else
5278 dev_priv->max_cdclk_freq = 337500;
5279 } else if (IS_BROADWELL(dev)) {
5280 /*
5281 * FIXME with extra cooling we can allow
5282 * 540 MHz for ULX and 675 Mhz for ULT.
5283 * How can we know if extra cooling is
5284 * available? PCI ID, VTB, something else?
5285 */
5286 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULX(dev))
5289 dev_priv->max_cdclk_freq = 450000;
5290 else if (IS_BDW_ULT(dev))
5291 dev_priv->max_cdclk_freq = 540000;
5292 else
5293 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5294 } else if (IS_CHERRYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5296 } else if (IS_VALLEYVIEW(dev)) {
5297 dev_priv->max_cdclk_freq = 400000;
5298 } else {
5299 /* otherwise assume cdclk is fixed */
5300 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5301 }
5302
adafdc6f
MK		 5303 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5304
560a7ae4
DL		 5305 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5306 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5307
5308 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5309 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5310}
5311
5312static void intel_update_cdclk(struct drm_device *dev)
5313{
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315
5316 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5317 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5318 dev_priv->cdclk_freq);
5319
5320 /*
5321 * Program the gmbus_freq based on the cdclk frequency.
5322 * BSpec erroneously claims we should aim for 4MHz, but
5323 * in fact 1MHz is the correct frequency.
5324 */
5325 if (IS_VALLEYVIEW(dev)) {
5326 /*
5327 * Program the gmbus_freq based on the cdclk frequency.
5328 * BSpec erroneously claims we should aim for 4MHz, but
5329 * in fact 1MHz is the correct frequency.
5330 */
5331 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5332 }
5333
5334 if (dev_priv->max_cdclk_freq == 0)
5335 intel_update_max_cdclk(dev);
5336}
5337
70d0c574 5338static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5339{
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 uint32_t divider;
5342 uint32_t ratio;
5343 uint32_t current_freq;
5344 int ret;
5345
5346 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5347 switch (frequency) {
5348 case 144000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5350 ratio = BXT_DE_PLL_RATIO(60);
5351 break;
5352 case 288000:
5353 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5354 ratio = BXT_DE_PLL_RATIO(60);
5355 break;
5356 case 384000:
5357 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5358 ratio = BXT_DE_PLL_RATIO(60);
5359 break;
5360 case 576000:
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5362 ratio = BXT_DE_PLL_RATIO(60);
5363 break;
5364 case 624000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5366 ratio = BXT_DE_PLL_RATIO(65);
5367 break;
5368 case 19200:
5369 /*
5370 * Bypass frequency with DE PLL disabled. Init ratio, divider
5371 * to suppress GCC warning.
5372 */
5373 ratio = 0;
5374 divider = 0;
5375 break;
5376 default:
5377 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5378
5379 return;
5380 }
5381
5382 mutex_lock(&dev_priv->rps.hw_lock);
5383 /* Inform power controller of upcoming frequency change */
5384 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5385 0x80000000);
5386 mutex_unlock(&dev_priv->rps.hw_lock);
5387
5388 if (ret) {
5389 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5390 ret, frequency);
5391 return;
5392 }
5393
5394 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5395 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5396 current_freq = current_freq * 500 + 1000;
5397
5398 /*
5399 * DE PLL has to be disabled when
5400 * - setting to 19.2MHz (bypass, PLL isn't used)
5401 * - before setting to 624MHz (PLL needs toggling)
5402 * - before setting to any frequency from 624MHz (PLL needs toggling)
5403 */
5404 if (frequency == 19200 || frequency == 624000 ||
5405 current_freq == 624000) {
5406 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5407 /* Timeout 200us */
5408 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5409 1))
5410 DRM_ERROR("timout waiting for DE PLL unlock\n");
5411 }
5412
5413 if (frequency != 19200) {
5414 uint32_t val;
5415
5416 val = I915_READ(BXT_DE_PLL_CTL);
5417 val &= ~BXT_DE_PLL_RATIO_MASK;
5418 val |= ratio;
5419 I915_WRITE(BXT_DE_PLL_CTL, val);
5420
5421 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5424 DRM_ERROR("timeout waiting for DE PLL lock\n");
5425
5426 val = I915_READ(CDCLK_CTL);
5427 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5428 val |= divider;
5429 /*
5430 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5431 * enable otherwise.
5432 */
5433 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5434 if (frequency >= 500000)
5435 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436
5437 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5438 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5439 val |= (frequency - 1000) / 500;
5440 I915_WRITE(CDCLK_CTL, val);
5441 }
5442
5443 mutex_lock(&dev_priv->rps.hw_lock);
5444 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445 DIV_ROUND_UP(frequency, 25000));
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448 if (ret) {
5449 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5450 ret, frequency);
5451 return;
5452 }
5453
a47871bd 5454 intel_update_cdclk(dev);
f8437dd1
VK		 5455}
5456
5457void broxton_init_cdclk(struct drm_device *dev)
5458{
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 uint32_t val;
5461
5462 /*
5463 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5464 * or else the reset will hang because there is no PCH to respond.
5465 * Move the handshake programming to initialization sequence.
5466 * Previously was left up to BIOS.
5467 */
5468 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5469 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5470 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5471
5472 /* Enable PG1 for cdclk */
5473 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5474
5475 /* check if cd clock is enabled */
5476 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5477 DRM_DEBUG_KMS("Display already initialized\n");
5478 return;
5479 }
5480
5481 /*
5482 * FIXME:
5483 * - The initial CDCLK needs to be read from VBT.
5484 * Need to make this change after VBT has changes for BXT.
5485 * - check if setting the max (or any) cdclk freq is really necessary
5486 * here, it belongs to modeset time
5487 */
5488 broxton_set_cdclk(dev, 624000);
5489
5490 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5491 POSTING_READ(DBUF_CTL);
5492
f8437dd1
VK		 5493 udelay(10);
5494
5495 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5496 DRM_ERROR("DBuf power enable timeout!\n");
5497}
5498
5499void broxton_uninit_cdclk(struct drm_device *dev)
5500{
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5504 POSTING_READ(DBUF_CTL);
5505
f8437dd1
VK		 5506 udelay(10);
5507
5508 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5509 DRM_ERROR("DBuf power disable timeout!\n");
5510
5511 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5512 broxton_set_cdclk(dev, 19200);
5513
5514 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5515}
5516
5d96d8af
DL		 5517static const struct skl_cdclk_entry {
5518 unsigned int freq;
5519 unsigned int vco;
5520} skl_cdclk_frequencies[] = {
5521 { .freq = 308570, .vco = 8640 },
5522 { .freq = 337500, .vco = 8100 },
5523 { .freq = 432000, .vco = 8640 },
5524 { .freq = 450000, .vco = 8100 },
5525 { .freq = 540000, .vco = 8100 },
5526 { .freq = 617140, .vco = 8640 },
5527 { .freq = 675000, .vco = 8100 },
5528};
5529
5530static unsigned int skl_cdclk_decimal(unsigned int freq)
5531{
5532 return (freq - 1000) / 500;
5533}
5534
5535static unsigned int skl_cdclk_get_vco(unsigned int freq)
5536{
5537 unsigned int i;
5538
5539 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5540 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5541
5542 if (e->freq == freq)
5543 return e->vco;
5544 }
5545
5546 return 8100;
5547}
5548
5549static void
5550skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5551{
5552 unsigned int min_freq;
5553 u32 val;
5554
5555 /* select the minimum CDCLK before enabling DPLL 0 */
5556 val = I915_READ(CDCLK_CTL);
5557 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5558 val |= CDCLK_FREQ_337_308;
5559
5560 if (required_vco == 8640)
5561 min_freq = 308570;
5562 else
5563 min_freq = 337500;
5564
5565 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5566
5567 I915_WRITE(CDCLK_CTL, val);
5568 POSTING_READ(CDCLK_CTL);
5569
5570 /*
5571 * We always enable DPLL0 with the lowest link rate possible, but still
5572 * taking into account the VCO required to operate the eDP panel at the
5573 * desired frequency. The usual DP link rates operate with a VCO of
5574 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5575 * The modeset code is responsible for the selection of the exact link
5576 * rate later on, with the constraint of choosing a frequency that
5577 * works with required_vco.
5578 */
5579 val = I915_READ(DPLL_CTRL1);
5580
5581 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5582 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5583 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5584 if (required_vco == 8640)
5585 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5586 SKL_DPLL0);
5587 else
5588 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5589 SKL_DPLL0);
5590
5591 I915_WRITE(DPLL_CTRL1, val);
5592 POSTING_READ(DPLL_CTRL1);
5593
5594 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5595
5596 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5597 DRM_ERROR("DPLL0 not locked\n");
5598}
5599
5600static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5601{
5602 int ret;
5603 u32 val;
5604
5605 /* inform PCU we want to change CDCLK */
5606 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5607 mutex_lock(&dev_priv->rps.hw_lock);
5608 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5609 mutex_unlock(&dev_priv->rps.hw_lock);
5610
5611 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5612}
5613
5614static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5615{
5616 unsigned int i;
5617
5618 for (i = 0; i < 15; i++) {
5619 if (skl_cdclk_pcu_ready(dev_priv))
5620 return true;
5621 udelay(10);
5622 }
5623
5624 return false;
5625}
5626
5627static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5628{
560a7ae4 5629 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5630 u32 freq_select, pcu_ack;
5631
5632 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5633
5634 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5635 DRM_ERROR("failed to inform PCU about cdclk change\n");
5636 return;
5637 }
5638
5639 /* set CDCLK_CTL */
5640 switch(freq) {
5641 case 450000:
5642 case 432000:
5643 freq_select = CDCLK_FREQ_450_432;
5644 pcu_ack = 1;
5645 break;
5646 case 540000:
5647 freq_select = CDCLK_FREQ_540;
5648 pcu_ack = 2;
5649 break;
5650 case 308570:
5651 case 337500:
5652 default:
5653 freq_select = CDCLK_FREQ_337_308;
5654 pcu_ack = 0;
5655 break;
5656 case 617140:
5657 case 675000:
5658 freq_select = CDCLK_FREQ_675_617;
5659 pcu_ack = 3;
5660 break;
5661 }
5662
5663 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5664 POSTING_READ(CDCLK_CTL);
5665
5666 /* inform PCU of the change */
5667 mutex_lock(&dev_priv->rps.hw_lock);
5668 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5669 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5670
5671 intel_update_cdclk(dev);
5d96d8af
DL		 5672}
5673
5674void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5675{
5676 /* disable DBUF power */
5677 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5678 POSTING_READ(DBUF_CTL);
5679
5680 udelay(10);
5681
5682 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5683 DRM_ERROR("DBuf power disable timeout\n");
5684
4e961e42
AM		 5685 /*
5686 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5687 */
5688 if (dev_priv->csr.dmc_payload) {
5689 /* disable DPLL0 */
5690 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5691 ~LCPLL_PLL_ENABLE);
5692 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5693 DRM_ERROR("Couldn't disable DPLL0\n");
5694 }
5d96d8af
DL		 5695
5696 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5697}
5698
5699void skl_init_cdclk(struct drm_i915_private *dev_priv)
5700{
5701 u32 val;
5702 unsigned int required_vco;
5703
5704 /* enable PCH reset handshake */
5705 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5706 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5707
5708 /* enable PG1 and Misc I/O */
5709 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5710
39d9b85a
GW		 5711 /* DPLL0 not enabled (happens on early BIOS versions) */
5712 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5713 /* enable DPLL0 */
5714 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5715 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5716 }
5717
5d96d8af
DL		 5718 /* set CDCLK to the frequency the BIOS chose */
5719 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5720
5721 /* enable DBUF power */
5722 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5723 POSTING_READ(DBUF_CTL);
5724
5725 udelay(10);
5726
5727 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5728 DRM_ERROR("DBuf power enable timeout\n");
5729}
5730
c73666f3
SK		 5731int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5732{
5733 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5734 uint32_t cdctl = I915_READ(CDCLK_CTL);
5735 int freq = dev_priv->skl_boot_cdclk;
5736
f1b391a5
SK		 5737 /*
5738 * check if the pre-os intialized the display
5739 * There is SWF18 scratchpad register defined which is set by the
5740 * pre-os which can be used by the OS drivers to check the status
5741 */
5742 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5743 goto sanitize;
5744
c73666f3
SK		 5745 /* Is PLL enabled and locked ? */
5746 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5747 goto sanitize;
5748
5749 /* DPLL okay; verify the cdclock
5750 *
5751 * Noticed in some instances that the freq selection is correct but
5752 * decimal part is programmed wrong from BIOS where pre-os does not
5753 * enable display. Verify the same as well.
5754 */
5755 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5756 /* All well; nothing to sanitize */
5757 return false;
5758sanitize:
5759 /*
5760 * As of now initialize with max cdclk till
5761 * we get dynamic cdclk support
5762 * */
5763 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5764 skl_init_cdclk(dev_priv);
5765
5766 /* we did have to sanitize */
5767 return true;
5768}
5769
30a970c6
JB		 5770/* Adjust CDclk dividers to allow high res or save power if possible */
5771static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5772{
5773 struct drm_i915_private *dev_priv = dev->dev_private;
5774 u32 val, cmd;
5775
164dfd28
VK		 5776 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5777 != dev_priv->cdclk_freq);
d60c4473 5778
dfcab17e 5779 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5780 cmd = 2;
dfcab17e 5781 else if (cdclk == 266667)
30a970c6
JB		 5782 cmd = 1;
5783 else
5784 cmd = 0;
5785
5786 mutex_lock(&dev_priv->rps.hw_lock);
5787 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5788 val &= ~DSPFREQGUAR_MASK;
5789 val |= (cmd << DSPFREQGUAR_SHIFT);
5790 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5791 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5792 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5793 50)) {
5794 DRM_ERROR("timed out waiting for CDclk change\n");
5795 }
5796 mutex_unlock(&dev_priv->rps.hw_lock);
5797
54433e91
VS		 5798 mutex_lock(&dev_priv->sb_lock);
5799
dfcab17e 5800 if (cdclk == 400000) {
6bcda4f0 5801 u32 divider;
30a970c6 5802
6bcda4f0 5803 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5804
30a970c6
JB		 5805 /* adjust cdclk divider */
5806 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5807 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5808 val |= divider;
5809 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5810
5811 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5812 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5813 50))
5814 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5815 }
5816
30a970c6
JB		 5817 /* adjust self-refresh exit latency value */
5818 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5819 val &= ~0x7f;
5820
5821 /*
5822 * For high bandwidth configs, we set a higher latency in the bunit
5823 * so that the core display fetch happens in time to avoid underruns.
5824 */
dfcab17e 5825 if (cdclk == 400000)
30a970c6
JB		 5826 val |= 4500 / 250; /* 4.5 usec */
5827 else
5828 val |= 3000 / 250; /* 3.0 usec */
5829 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5830
a580516d 5831 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5832
b6283055 5833 intel_update_cdclk(dev);
30a970c6
JB		 5834}
5835
383c5a6a
VS		 5836static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5837{
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 u32 val, cmd;
5840
164dfd28
VK		 5841 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5842 != dev_priv->cdclk_freq);
383c5a6a
VS		 5843
5844 switch (cdclk) {
383c5a6a
VS		 5845 case 333333:
5846 case 320000:
383c5a6a 5847 case 266667:
383c5a6a 5848 case 200000:
383c5a6a
VS		 5849 break;
5850 default:
5f77eeb0 5851 MISSING_CASE(cdclk);
383c5a6a
VS		 5852 return;
5853 }
5854
9d0d3fda
VS		 5855 /*
5856 * Specs are full of misinformation, but testing on actual
5857 * hardware has shown that we just need to write the desired
5858 * CCK divider into the Punit register.
5859 */
5860 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5861
383c5a6a
VS		 5862 mutex_lock(&dev_priv->rps.hw_lock);
5863 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5864 val &= ~DSPFREQGUAR_MASK_CHV;
5865 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5866 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5867 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5868 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5869 50)) {
5870 DRM_ERROR("timed out waiting for CDclk change\n");
5871 }
5872 mutex_unlock(&dev_priv->rps.hw_lock);
5873
b6283055 5874 intel_update_cdclk(dev);
383c5a6a
VS		 5875}
5876
30a970c6
JB		 5877static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5878 int max_pixclk)
5879{
6bcda4f0 5880 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5881 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5882
30a970c6
JB		 5883 /*
5884 * Really only a few cases to deal with, as only 4 CDclks are supported:
5885 * 200MHz
5886 * 267MHz
29dc7ef3 5887 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5888 * 400MHz (VLV only)
5889 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5890 * of the lower bin and adjust if needed.
e37c67a1
VS		 5891 *
5892 * We seem to get an unstable or solid color picture at 200MHz.
5893 * Not sure what's wrong. For now use 200MHz only when all pipes
5894 * are off.
30a970c6 5895 */
6cca3195
VS		 5896 if (!IS_CHERRYVIEW(dev_priv) &&
5897 max_pixclk > freq_320*limit/100)
dfcab17e 5898 return 400000;
6cca3195 5899 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5900 return freq_320;
e37c67a1 5901 else if (max_pixclk > 0)
dfcab17e 5902 return 266667;
e37c67a1
VS		 5903 else
5904 return 200000;
30a970c6
JB		 5905}
5906
f8437dd1
VK		 5907static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5908 int max_pixclk)
5909{
5910 /*
5911 * FIXME:
5912 * - remove the guardband, it's not needed on BXT
5913 * - set 19.2MHz bypass frequency if there are no active pipes
5914 */
5915 if (max_pixclk > 576000*9/10)
5916 return 624000;
5917 else if (max_pixclk > 384000*9/10)
5918 return 576000;
5919 else if (max_pixclk > 288000*9/10)
5920 return 384000;
5921 else if (max_pixclk > 144000*9/10)
5922 return 288000;
5923 else
5924 return 144000;
5925}
5926
a821fc46
ACO		 5927/* Compute the max pixel clock for new configuration. Uses atomic state if
5928 * that's non-NULL, look at current state otherwise. */
5929static int intel_mode_max_pixclk(struct drm_device *dev,
5930 struct drm_atomic_state *state)
30a970c6 5931{
30a970c6 5932 struct intel_crtc *intel_crtc;
304603f4 5933 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5934 int max_pixclk = 0;
5935
d3fcc808 5936 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5937 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5938 if (IS_ERR(crtc_state))
5939 return PTR_ERR(crtc_state);
5940
5941 if (!crtc_state->base.enable)
5942 continue;
5943
5944 max_pixclk = max(max_pixclk,
5945 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5946 }
5947
5948 return max_pixclk;
5949}
5950
27c329ed 5951static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5952{
27c329ed
ML		 5953 struct drm_device *dev = state->dev;
5954 struct drm_i915_private *dev_priv = dev->dev_private;
5955 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5956
304603f4
ACO		 5957 if (max_pixclk < 0)
5958 return max_pixclk;
30a970c6 5959
27c329ed
ML		 5960 to_intel_atomic_state(state)->cdclk =
5961 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5962
27c329ed
ML		 5963 return 0;
5964}
304603f4 5965
27c329ed
ML		 5966static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5967{
5968 struct drm_device *dev = state->dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5970 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5971
27c329ed
ML		 5972 if (max_pixclk < 0)
5973 return max_pixclk;
85a96e7a 5974
27c329ed
ML		 5975 to_intel_atomic_state(state)->cdclk =
5976 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5977
27c329ed 5978 return 0;
30a970c6
JB		 5979}
5980
1e69cd74
VS		 5981static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5982{
5983 unsigned int credits, default_credits;
5984
5985 if (IS_CHERRYVIEW(dev_priv))
5986 default_credits = PFI_CREDIT(12);
5987 else
5988 default_credits = PFI_CREDIT(8);
5989
bfa7df01 5990 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 5991 /* CHV suggested value is 31 or 63 */
5992 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5993 credits = PFI_CREDIT_63;
1e69cd74
VS		 5994 else
5995 credits = PFI_CREDIT(15);
5996 } else {
5997 credits = default_credits;
5998 }
5999
6000 /*
6001 * WA - write default credits before re-programming
6002 * FIXME: should we also set the resend bit here?
6003 */
6004 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6005 default_credits);
6006
6007 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6008 credits | PFI_CREDIT_RESEND);
6009
6010 /*
6011 * FIXME is this guaranteed to clear
6012 * immediately or should we poll for it?
6013 */
6014 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6015}
6016
27c329ed 6017static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6018{
a821fc46 6019 struct drm_device *dev = old_state->dev;
27c329ed 6020 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6021 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6022
27c329ed
ML		 6023 /*
6024 * FIXME: We can end up here with all power domains off, yet
6025 * with a CDCLK frequency other than the minimum. To account
6026 * for this take the PIPE-A power domain, which covers the HW
6027 * blocks needed for the following programming. This can be
6028 * removed once it's guaranteed that we get here either with
6029 * the minimum CDCLK set, or the required power domains
6030 * enabled.
6031 */
6032 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6033
27c329ed
ML		 6034 if (IS_CHERRYVIEW(dev))
6035 cherryview_set_cdclk(dev, req_cdclk);
6036 else
6037 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6038
27c329ed 6039 vlv_program_pfi_credits(dev_priv);
1e69cd74 6040
27c329ed 6041 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6042}
6043
89b667f8
JB		 6044static void valleyview_crtc_enable(struct drm_crtc *crtc)
6045{
6046 struct drm_device *dev = crtc->dev;
a72e4c9f 6047 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6049 struct intel_encoder *encoder;
6050 int pipe = intel_crtc->pipe;
23538ef1 6051 bool is_dsi;
89b667f8 6052
53d9f4e9 6053 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6054 return;
6055
409ee761 6056 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6057
6e3c9717 6058 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6059 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6060
6061 intel_set_pipe_timings(intel_crtc);
6062
c14b0485
VS		 6063 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6064 struct drm_i915_private *dev_priv = dev->dev_private;
6065
6066 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6067 I915_WRITE(CHV_CANVAS(pipe), 0);
6068 }
6069
5b18e57c
DV		 6070 i9xx_set_pipeconf(intel_crtc);
6071
89b667f8 6072 intel_crtc->active = true;
89b667f8 6073
a72e4c9f 6074 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6075
89b667f8
JB		 6076 for_each_encoder_on_crtc(dev, crtc, encoder)
6077 if (encoder->pre_pll_enable)
6078 encoder->pre_pll_enable(encoder);
6079
9d556c99 6080 if (!is_dsi) {
c0b4c660
VS		 6081 if (IS_CHERRYVIEW(dev)) {
6082 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6083 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6084 } else {
6085 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6086 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6087 }
9d556c99 6088 }
89b667f8
JB		 6089
6090 for_each_encoder_on_crtc(dev, crtc, encoder)
6091 if (encoder->pre_enable)
6092 encoder->pre_enable(encoder);
6093
2dd24552
JB		 6094 i9xx_pfit_enable(intel_crtc);
6095
63cbb074
VS		 6096 intel_crtc_load_lut(crtc);
6097
e1fdc473 6098 intel_enable_pipe(intel_crtc);
be6a6f8e 6099
4b3a9526
VS		 6100 assert_vblank_disabled(crtc);
6101 drm_crtc_vblank_on(crtc);
6102
f9b61ff6
DV		 6103 for_each_encoder_on_crtc(dev, crtc, encoder)
6104 encoder->enable(encoder);
89b667f8
JB		 6105}
6106
f13c2ef3
DV		 6107static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6108{
6109 struct drm_device *dev = crtc->base.dev;
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111
6e3c9717
ACO		 6112 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6113 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6114}
6115
0b8765c6 6116static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6117{
6118 struct drm_device *dev = crtc->dev;
a72e4c9f 6119 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6121 struct intel_encoder *encoder;
79e53945 6122 int pipe = intel_crtc->pipe;
79e53945 6123
53d9f4e9 6124 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6125 return;
6126
f13c2ef3
DV		 6127 i9xx_set_pll_dividers(intel_crtc);
6128
6e3c9717 6129 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6130 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6131
6132 intel_set_pipe_timings(intel_crtc);
6133
5b18e57c
DV		 6134 i9xx_set_pipeconf(intel_crtc);
6135
f7abfe8b 6136 intel_crtc->active = true;
6b383a7f 6137
4a3436e8 6138 if (!IS_GEN2(dev))
a72e4c9f 6139 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6140
9d6d9f19
MK		 6141 for_each_encoder_on_crtc(dev, crtc, encoder)
6142 if (encoder->pre_enable)
6143 encoder->pre_enable(encoder);
6144
f6736a1a
DV		 6145 i9xx_enable_pll(intel_crtc);
6146
2dd24552
JB		 6147 i9xx_pfit_enable(intel_crtc);
6148
63cbb074
VS		 6149 intel_crtc_load_lut(crtc);
6150
f37fcc2a 6151 intel_update_watermarks(crtc);
e1fdc473 6152 intel_enable_pipe(intel_crtc);
be6a6f8e 6153
4b3a9526
VS		 6154 assert_vblank_disabled(crtc);
6155 drm_crtc_vblank_on(crtc);
6156
f9b61ff6
DV		 6157 for_each_encoder_on_crtc(dev, crtc, encoder)
6158 encoder->enable(encoder);
0b8765c6 6159}
79e53945 6160
87476d63
DV		 6161static void i9xx_pfit_disable(struct intel_crtc *crtc)
6162{
6163 struct drm_device *dev = crtc->base.dev;
6164 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6165
6e3c9717 6166 if (!crtc->config->gmch_pfit.control)
328d8e82 6167 return;
87476d63 6168
328d8e82 6169 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6170
328d8e82
DV		 6171 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6172 I915_READ(PFIT_CONTROL));
6173 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6174}
6175
0b8765c6
JB		 6176static void i9xx_crtc_disable(struct drm_crtc *crtc)
6177{
6178 struct drm_device *dev = crtc->dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6181 struct intel_encoder *encoder;
0b8765c6 6182 int pipe = intel_crtc->pipe;
ef9c3aee 6183
6304cd91
VS		 6184 /*
6185 * On gen2 planes are double buffered but the pipe isn't, so we must
6186 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6187 * We also need to wait on all gmch platforms because of the
6188 * self-refresh mode constraint explained above.
6304cd91 6189 */
564ed191 6190 intel_wait_for_vblank(dev, pipe);
6304cd91 6191
4b3a9526
VS		 6192 for_each_encoder_on_crtc(dev, crtc, encoder)
6193 encoder->disable(encoder);
6194
f9b61ff6
DV		 6195 drm_crtc_vblank_off(crtc);
6196 assert_vblank_disabled(crtc);
6197
575f7ab7 6198 intel_disable_pipe(intel_crtc);
24a1f16d 6199
87476d63 6200 i9xx_pfit_disable(intel_crtc);
24a1f16d 6201
89b667f8
JB		 6202 for_each_encoder_on_crtc(dev, crtc, encoder)
6203 if (encoder->post_disable)
6204 encoder->post_disable(encoder);
6205
409ee761 6206 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6207 if (IS_CHERRYVIEW(dev))
6208 chv_disable_pll(dev_priv, pipe);
6209 else if (IS_VALLEYVIEW(dev))
6210 vlv_disable_pll(dev_priv, pipe);
6211 else
1c4e0274 6212 i9xx_disable_pll(intel_crtc);
076ed3b2 6213 }
0b8765c6 6214
d6db995f
VS		 6215 for_each_encoder_on_crtc(dev, crtc, encoder)
6216 if (encoder->post_pll_disable)
6217 encoder->post_pll_disable(encoder);
6218
4a3436e8 6219 if (!IS_GEN2(dev))
a72e4c9f 6220 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6221}
6222
b17d48e2
ML		 6223static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6224{
6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6227 enum intel_display_power_domain domain;
6228 unsigned long domains;
6229
6230 if (!intel_crtc->active)
6231 return;
6232
a539205a 6233 if (to_intel_plane_state(crtc->primary->state)->visible) {
fc32b1fd
ML		 6234 WARN_ON(intel_crtc->unpin_work);
6235
a539205a
ML		 6236 intel_pre_disable_primary(crtc);
6237 }
6238
d032ffa0 6239 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6240 dev_priv->display.crtc_disable(crtc);
37d9078b
MR		 6241 intel_crtc->active = false;
6242 intel_update_watermarks(crtc);
1f7457b1 6243 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6244
6245 domains = intel_crtc->enabled_power_domains;
6246 for_each_power_domain(domain, domains)
6247 intel_display_power_put(dev_priv, domain);
6248 intel_crtc->enabled_power_domains = 0;
6249}
6250
6b72d486
ML		 6251/*
6252 * turn all crtc's off, but do not adjust state
6253 * This has to be paired with a call to intel_modeset_setup_hw_state.
6254 */
70e0bd74 6255int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6256{
70e0bd74
ML		 6257 struct drm_mode_config *config = &dev->mode_config;
6258 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6259 struct drm_atomic_state *state;
6b72d486 6260 struct drm_crtc *crtc;
70e0bd74
ML		 6261 unsigned crtc_mask = 0;
6262 int ret = 0;
6263
6264 if (WARN_ON(!ctx))
6265 return 0;
6266
6267 lockdep_assert_held(&ctx->ww_ctx);
6268 state = drm_atomic_state_alloc(dev);
6269 if (WARN_ON(!state))
6270 return -ENOMEM;
6271
6272 state->acquire_ctx = ctx;
6273 state->allow_modeset = true;
6274
6275 for_each_crtc(dev, crtc) {
6276 struct drm_crtc_state *crtc_state =
6277 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6278
70e0bd74
ML		 6279 ret = PTR_ERR_OR_ZERO(crtc_state);
6280 if (ret)
6281 goto free;
6282
6283 if (!crtc_state->active)
6284 continue;
6285
6286 crtc_state->active = false;
6287 crtc_mask |= 1 << drm_crtc_index(crtc);
6288 }
6289
6290 if (crtc_mask) {
74c090b1 6291 ret = drm_atomic_commit(state);
70e0bd74
ML		 6292
6293 if (!ret) {
6294 for_each_crtc(dev, crtc)
6295 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6296 crtc->state->active = true;
6297
6298 return ret;
6299 }
6300 }
6301
6302free:
6303 if (ret)
6304 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6305 drm_atomic_state_free(state);
6306 return ret;
ee7b9f93
JB		 6307}
6308
ea5b213a 6309void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6310{
4ef69c7a 6311 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6312
ea5b213a
CW		 6313 drm_encoder_cleanup(encoder);
6314 kfree(intel_encoder);
7e7d76c3
JB		 6315}
6316
0a91ca29
DV		 6317/* Cross check the actual hw state with our own modeset state tracking (and it's
6318 * internal consistency). */
b980514c 6319static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6320{
35dd3c64
ML		 6321 struct drm_crtc *crtc = connector->base.state->crtc;
6322
6323 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6324 connector->base.base.id,
6325 connector->base.name);
6326
0a91ca29 6327 if (connector->get_hw_state(connector)) {
e85376cb 6328 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6329 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6330
35dd3c64
ML		 6331 I915_STATE_WARN(!crtc,
6332 "connector enabled without attached crtc\n");
0a91ca29 6333
35dd3c64
ML		 6334 if (!crtc)
6335 return;
6336
6337 I915_STATE_WARN(!crtc->state->active,
6338 "connector is active, but attached crtc isn't\n");
6339
e85376cb 6340 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6341 return;
6342
e85376cb 6343 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6344 "atomic encoder doesn't match attached encoder\n");
6345
e85376cb 6346 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6347 "attached encoder crtc differs from connector crtc\n");
6348 } else {
4d688a2a
ML		 6349 I915_STATE_WARN(crtc && crtc->state->active,
6350 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6351 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6352 "best encoder set without crtc!\n");
0a91ca29 6353 }
79e53945
JB		 6354}
6355
08d9bc92
ACO		 6356int intel_connector_init(struct intel_connector *connector)
6357{
6358 struct drm_connector_state *connector_state;
6359
6360 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6361 if (!connector_state)
6362 return -ENOMEM;
6363
6364 connector->base.state = connector_state;
6365 return 0;
6366}
6367
6368struct intel_connector *intel_connector_alloc(void)
6369{
6370 struct intel_connector *connector;
6371
6372 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6373 if (!connector)
6374 return NULL;
6375
6376 if (intel_connector_init(connector) < 0) {
6377 kfree(connector);
6378 return NULL;
6379 }
6380
6381 return connector;
6382}
6383
f0947c37
DV		 6384/* Simple connector->get_hw_state implementation for encoders that support only
6385 * one connector and no cloning and hence the encoder state determines the state
6386 * of the connector. */
6387bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6388{
24929352 6389 enum pipe pipe = 0;
f0947c37 6390 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6391
f0947c37 6392 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6393}
6394
6d293983 6395static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6396{
6d293983
ACO		 6397 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6398 return crtc_state->fdi_lanes;
d272ddfa
VS		 6399
6400 return 0;
6401}
6402
6d293983 6403static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6404 struct intel_crtc_state *pipe_config)
1857e1da 6405{
6d293983
ACO		 6406 struct drm_atomic_state *state = pipe_config->base.state;
6407 struct intel_crtc *other_crtc;
6408 struct intel_crtc_state *other_crtc_state;
6409
1857e1da
DV		 6410 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6411 pipe_name(pipe), pipe_config->fdi_lanes);
6412 if (pipe_config->fdi_lanes > 4) {
6413 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6415 return -EINVAL;
1857e1da
DV		 6416 }
6417
bafb6553 6418 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6419 if (pipe_config->fdi_lanes > 2) {
6420 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6421 pipe_config->fdi_lanes);
6d293983 6422 return -EINVAL;
1857e1da 6423 } else {
6d293983 6424 return 0;
1857e1da
DV		 6425 }
6426 }
6427
6428 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6429 return 0;
1857e1da
DV		 6430
6431 /* Ivybridge 3 pipe is really complicated */
6432 switch (pipe) {
6433 case PIPE_A:
6d293983 6434 return 0;
1857e1da 6435 case PIPE_B:
6d293983
ACO		 6436 if (pipe_config->fdi_lanes <= 2)
6437 return 0;
6438
6439 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6440 other_crtc_state =
6441 intel_atomic_get_crtc_state(state, other_crtc);
6442 if (IS_ERR(other_crtc_state))
6443 return PTR_ERR(other_crtc_state);
6444
6445 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6446 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6447 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6448 return -EINVAL;
1857e1da 6449 }
6d293983 6450 return 0;
1857e1da 6451 case PIPE_C:
251cc67c
VS		 6452 if (pipe_config->fdi_lanes > 2) {
6453 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6454 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6455 return -EINVAL;
251cc67c 6456 }
6d293983
ACO		 6457
6458 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6459 other_crtc_state =
6460 intel_atomic_get_crtc_state(state, other_crtc);
6461 if (IS_ERR(other_crtc_state))
6462 return PTR_ERR(other_crtc_state);
6463
6464 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6465 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6466 return -EINVAL;
1857e1da 6467 }
6d293983 6468 return 0;
1857e1da
DV		 6469 default:
6470 BUG();
6471 }
6472}
6473
e29c22c0
DV		 6474#define RETRY 1
6475static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6476 struct intel_crtc_state *pipe_config)
877d48d5 6477{
1857e1da 6478 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6479 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6480 int lane, link_bw, fdi_dotclock, ret;
6481 bool needs_recompute = false;
877d48d5 6482
e29c22c0 6483retry:
877d48d5
DV		 6484 /* FDI is a binary signal running at ~2.7GHz, encoding
6485 * each output octet as 10 bits. The actual frequency
6486 * is stored as a divider into a 100MHz clock, and the
6487 * mode pixel clock is stored in units of 1KHz.
6488 * Hence the bw of each lane in terms of the mode signal
6489 * is:
6490 */
6491 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6492
241bfc38 6493 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6494
2bd89a07 6495 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6496 pipe_config->pipe_bpp);
6497
6498 pipe_config->fdi_lanes = lane;
6499
2bd89a07 6500 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6501 link_bw, &pipe_config->fdi_m_n);
1857e1da 6502
6d293983
ACO		 6503 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6504 intel_crtc->pipe, pipe_config);
6505 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6506 pipe_config->pipe_bpp -= 2*3;
6507 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6508 pipe_config->pipe_bpp);
6509 needs_recompute = true;
6510 pipe_config->bw_constrained = true;
6511
6512 goto retry;
6513 }
6514
6515 if (needs_recompute)
6516 return RETRY;
6517
6d293983 6518 return ret;
877d48d5
DV		 6519}
6520
8cfb3407
VS		 6521static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6522 struct intel_crtc_state *pipe_config)
6523{
6524 if (pipe_config->pipe_bpp > 24)
6525 return false;
6526
6527 /* HSW can handle pixel rate up to cdclk? */
6528 if (IS_HASWELL(dev_priv->dev))
6529 return true;
6530
6531 /*
b432e5cf
VS		 6532 * We compare against max which means we must take
6533 * the increased cdclk requirement into account when
6534 * calculating the new cdclk.
6535 *
6536 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6537 */
6538 return ilk_pipe_pixel_rate(pipe_config) <=
6539 dev_priv->max_cdclk_freq * 95 / 100;
6540}
6541
42db64ef 6542static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6543 struct intel_crtc_state *pipe_config)
42db64ef 6544{
8cfb3407
VS		 6545 struct drm_device *dev = crtc->base.dev;
6546 struct drm_i915_private *dev_priv = dev->dev_private;
6547
d330a953 6548 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6549 hsw_crtc_supports_ips(crtc) &&
6550 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6551}
6552
a43f6e0f 6553static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6554 struct intel_crtc_state *pipe_config)
79e53945 6555{
a43f6e0f 6556 struct drm_device *dev = crtc->base.dev;
8bd31e67 6557 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6558 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6559
ad3a4479 6560 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6561 if (INTEL_INFO(dev)->gen < 4) {
44913155 6562 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6563
6564 /*
6565 * Enable pixel doubling when the dot clock
6566 * is > 90% of the (display) core speed.
6567 *
b397c96b
VS		 6568 * GDG double wide on either pipe,
6569 * otherwise pipe A only.
cf532bb2 6570 */
b397c96b 6571 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6572 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6573 clock_limit *= 2;
cf532bb2 6574 pipe_config->double_wide = true;
ad3a4479
VS		 6575 }
6576
241bfc38 6577 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6578 return -EINVAL;
2c07245f 6579 }
89749350 6580
1d1d0e27
VS		 6581 /*
6582 * Pipe horizontal size must be even in:
6583 * - DVO ganged mode
6584 * - LVDS dual channel mode
6585 * - Double wide pipe
6586 */
a93e255f 6587 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6588 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6589 pipe_config->pipe_src_w &= ~1;
6590
8693a824
DL		 6591 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6592 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6593 */
6594 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6595 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6596 return -EINVAL;
44f46b42 6597
f5adf94e 6598 if (HAS_IPS(dev))
a43f6e0f
DV		 6599 hsw_compute_ips_config(crtc, pipe_config);
6600
877d48d5 6601 if (pipe_config->has_pch_encoder)
a43f6e0f 6602 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6603
cf5a15be 6604 return 0;
79e53945
JB		 6605}
6606
1652d19e
VS		 6607static int skylake_get_display_clock_speed(struct drm_device *dev)
6608{
6609 struct drm_i915_private *dev_priv = to_i915(dev);
6610 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6611 uint32_t cdctl = I915_READ(CDCLK_CTL);
6612 uint32_t linkrate;
6613
414355a7 6614 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6615 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6616
6617 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6618 return 540000;
6619
6620 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6621 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6622
71cd8423
DL		 6623 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6624 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6625 /* vco 8640 */
6626 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6627 case CDCLK_FREQ_450_432:
6628 return 432000;
6629 case CDCLK_FREQ_337_308:
6630 return 308570;
6631 case CDCLK_FREQ_675_617:
6632 return 617140;
6633 default:
6634 WARN(1, "Unknown cd freq selection\n");
6635 }
6636 } else {
6637 /* vco 8100 */
6638 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6639 case CDCLK_FREQ_450_432:
6640 return 450000;
6641 case CDCLK_FREQ_337_308:
6642 return 337500;
6643 case CDCLK_FREQ_675_617:
6644 return 675000;
6645 default:
6646 WARN(1, "Unknown cd freq selection\n");
6647 }
6648 }
6649
6650 /* error case, do as if DPLL0 isn't enabled */
6651 return 24000;
6652}
6653
acd3f3d3
BP		 6654static int broxton_get_display_clock_speed(struct drm_device *dev)
6655{
6656 struct drm_i915_private *dev_priv = to_i915(dev);
6657 uint32_t cdctl = I915_READ(CDCLK_CTL);
6658 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6659 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6660 int cdclk;
6661
6662 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6663 return 19200;
6664
6665 cdclk = 19200 * pll_ratio / 2;
6666
6667 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6668 case BXT_CDCLK_CD2X_DIV_SEL_1:
6669 return cdclk; /* 576MHz or 624MHz */
6670 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6671 return cdclk * 2 / 3; /* 384MHz */
6672 case BXT_CDCLK_CD2X_DIV_SEL_2:
6673 return cdclk / 2; /* 288MHz */
6674 case BXT_CDCLK_CD2X_DIV_SEL_4:
6675 return cdclk / 4; /* 144MHz */
6676 }
6677
6678 /* error case, do as if DE PLL isn't enabled */
6679 return 19200;
6680}
6681
1652d19e
VS		 6682static int broadwell_get_display_clock_speed(struct drm_device *dev)
6683{
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6685 uint32_t lcpll = I915_READ(LCPLL_CTL);
6686 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6687
6688 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6689 return 800000;
6690 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6691 return 450000;
6692 else if (freq == LCPLL_CLK_FREQ_450)
6693 return 450000;
6694 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6695 return 540000;
6696 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6697 return 337500;
6698 else
6699 return 675000;
6700}
6701
6702static int haswell_get_display_clock_speed(struct drm_device *dev)
6703{
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 uint32_t lcpll = I915_READ(LCPLL_CTL);
6706 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6707
6708 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6709 return 800000;
6710 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6711 return 450000;
6712 else if (freq == LCPLL_CLK_FREQ_450)
6713 return 450000;
6714 else if (IS_HSW_ULT(dev))
6715 return 337500;
6716 else
6717 return 540000;
79e53945
JB		 6718}
6719
25eb05fc
JB		 6720static int valleyview_get_display_clock_speed(struct drm_device *dev)
6721{
bfa7df01
VS		 6722 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6723 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6724}
6725
b37a6434
VS		 6726static int ilk_get_display_clock_speed(struct drm_device *dev)
6727{
6728 return 450000;
6729}
6730
e70236a8
JB		 6731static int i945_get_display_clock_speed(struct drm_device *dev)
6732{
6733 return 400000;
6734}
79e53945 6735
e70236a8 6736static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6737{
e907f170 6738 return 333333;
e70236a8 6739}
79e53945 6740
e70236a8
JB		 6741static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6742{
6743 return 200000;
6744}
79e53945 6745
257a7ffc
DV		 6746static int pnv_get_display_clock_speed(struct drm_device *dev)
6747{
6748 u16 gcfgc = 0;
6749
6750 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6751
6752 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6753 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6754 return 266667;
257a7ffc 6755 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6756 return 333333;
257a7ffc 6757 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6758 return 444444;
257a7ffc
DV		 6759 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6760 return 200000;
6761 default:
6762 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6763 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6764 return 133333;
257a7ffc 6765 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6766 return 166667;
257a7ffc
DV		 6767 }
6768}
6769
e70236a8
JB		 6770static int i915gm_get_display_clock_speed(struct drm_device *dev)
6771{
6772 u16 gcfgc = 0;
79e53945 6773
e70236a8
JB		 6774 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6775
6776 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6777 return 133333;
e70236a8
JB		 6778 else {
6779 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6780 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6781 return 333333;
e70236a8
JB		 6782 default:
6783 case GC_DISPLAY_CLOCK_190_200_MHZ:
6784 return 190000;
79e53945 6785 }
e70236a8
JB		 6786 }
6787}
6788
6789static int i865_get_display_clock_speed(struct drm_device *dev)
6790{
e907f170 6791 return 266667;
e70236a8
JB		 6792}
6793
1b1d2716 6794static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6795{
6796 u16 hpllcc = 0;
1b1d2716 6797
65cd2b3f
VS		 6798 /*
6799 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6800 * encoding is different :(
6801 * FIXME is this the right way to detect 852GM/852GMV?
6802 */
6803 if (dev->pdev->revision == 0x1)
6804 return 133333;
6805
1b1d2716
VS		 6806 pci_bus_read_config_word(dev->pdev->bus,
6807 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6808
e70236a8
JB		 6809 /* Assume that the hardware is in the high speed state. This
6810 * should be the default.
6811 */
6812 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6813 case GC_CLOCK_133_200:
1b1d2716 6814 case GC_CLOCK_133_200_2:
e70236a8
JB		 6815 case GC_CLOCK_100_200:
6816 return 200000;
6817 case GC_CLOCK_166_250:
6818 return 250000;
6819 case GC_CLOCK_100_133:
e907f170 6820 return 133333;
1b1d2716
VS		 6821 case GC_CLOCK_133_266:
6822 case GC_CLOCK_133_266_2:
6823 case GC_CLOCK_166_266:
6824 return 266667;
e70236a8 6825 }
79e53945 6826
e70236a8
JB		 6827 /* Shouldn't happen */
6828 return 0;
6829}
79e53945 6830
e70236a8
JB		 6831static int i830_get_display_clock_speed(struct drm_device *dev)
6832{
e907f170 6833 return 133333;
79e53945
JB		 6834}
6835
34edce2f
VS		 6836static unsigned int intel_hpll_vco(struct drm_device *dev)
6837{
6838 struct drm_i915_private *dev_priv = dev->dev_private;
6839 static const unsigned int blb_vco[8] = {
6840 [0] = 3200000,
6841 [1] = 4000000,
6842 [2] = 5333333,
6843 [3] = 4800000,
6844 [4] = 6400000,
6845 };
6846 static const unsigned int pnv_vco[8] = {
6847 [0] = 3200000,
6848 [1] = 4000000,
6849 [2] = 5333333,
6850 [3] = 4800000,
6851 [4] = 2666667,
6852 };
6853 static const unsigned int cl_vco[8] = {
6854 [0] = 3200000,
6855 [1] = 4000000,
6856 [2] = 5333333,
6857 [3] = 6400000,
6858 [4] = 3333333,
6859 [5] = 3566667,
6860 [6] = 4266667,
6861 };
6862 static const unsigned int elk_vco[8] = {
6863 [0] = 3200000,
6864 [1] = 4000000,
6865 [2] = 5333333,
6866 [3] = 4800000,
6867 };
6868 static const unsigned int ctg_vco[8] = {
6869 [0] = 3200000,
6870 [1] = 4000000,
6871 [2] = 5333333,
6872 [3] = 6400000,
6873 [4] = 2666667,
6874 [5] = 4266667,
6875 };
6876 const unsigned int *vco_table;
6877 unsigned int vco;
6878 uint8_t tmp = 0;
6879
6880 /* FIXME other chipsets? */
6881 if (IS_GM45(dev))
6882 vco_table = ctg_vco;
6883 else if (IS_G4X(dev))
6884 vco_table = elk_vco;
6885 else if (IS_CRESTLINE(dev))
6886 vco_table = cl_vco;
6887 else if (IS_PINEVIEW(dev))
6888 vco_table = pnv_vco;
6889 else if (IS_G33(dev))
6890 vco_table = blb_vco;
6891 else
6892 return 0;
6893
6894 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6895
6896 vco = vco_table[tmp & 0x7];
6897 if (vco == 0)
6898 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6899 else
6900 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6901
6902 return vco;
6903}
6904
6905static int gm45_get_display_clock_speed(struct drm_device *dev)
6906{
6907 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6908 uint16_t tmp = 0;
6909
6910 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6911
6912 cdclk_sel = (tmp >> 12) & 0x1;
6913
6914 switch (vco) {
6915 case 2666667:
6916 case 4000000:
6917 case 5333333:
6918 return cdclk_sel ? 333333 : 222222;
6919 case 3200000:
6920 return cdclk_sel ? 320000 : 228571;
6921 default:
6922 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6923 return 222222;
6924 }
6925}
6926
6927static int i965gm_get_display_clock_speed(struct drm_device *dev)
6928{
6929 static const uint8_t div_3200[] = { 16, 10, 8 };
6930 static const uint8_t div_4000[] = { 20, 12, 10 };
6931 static const uint8_t div_5333[] = { 24, 16, 14 };
6932 const uint8_t *div_table;
6933 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6934 uint16_t tmp = 0;
6935
6936 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6937
6938 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6939
6940 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6941 goto fail;
6942
6943 switch (vco) {
6944 case 3200000:
6945 div_table = div_3200;
6946 break;
6947 case 4000000:
6948 div_table = div_4000;
6949 break;
6950 case 5333333:
6951 div_table = div_5333;
6952 break;
6953 default:
6954 goto fail;
6955 }
6956
6957 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6958
caf4e252 6959fail:
34edce2f
VS		 6960 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6961 return 200000;
6962}
6963
6964static int g33_get_display_clock_speed(struct drm_device *dev)
6965{
6966 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6967 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6968 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6969 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6970 const uint8_t *div_table;
6971 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6972 uint16_t tmp = 0;
6973
6974 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6975
6976 cdclk_sel = (tmp >> 4) & 0x7;
6977
6978 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6979 goto fail;
6980
6981 switch (vco) {
6982 case 3200000:
6983 div_table = div_3200;
6984 break;
6985 case 4000000:
6986 div_table = div_4000;
6987 break;
6988 case 4800000:
6989 div_table = div_4800;
6990 break;
6991 case 5333333:
6992 div_table = div_5333;
6993 break;
6994 default:
6995 goto fail;
6996 }
6997
6998 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6999
caf4e252 7000fail:
34edce2f
VS		 7001 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7002 return 190476;
7003}
7004
2c07245f 7005static void
a65851af 7006intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7007{
a65851af
VS		 7008 while (*num > DATA_LINK_M_N_MASK ||
7009 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7010 *num >>= 1;
7011 *den >>= 1;
7012 }
7013}
7014
a65851af
VS		 7015static void compute_m_n(unsigned int m, unsigned int n,
7016 uint32_t *ret_m, uint32_t *ret_n)
7017{
7018 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7019 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7020 intel_reduce_m_n_ratio(ret_m, ret_n);
7021}
7022
e69d0bc1
DV		 7023void
7024intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7025 int pixel_clock, int link_clock,
7026 struct intel_link_m_n *m_n)
2c07245f 7027{
e69d0bc1 7028 m_n->tu = 64;
a65851af
VS		 7029
7030 compute_m_n(bits_per_pixel * pixel_clock,
7031 link_clock * nlanes * 8,
7032 &m_n->gmch_m, &m_n->gmch_n);
7033
7034 compute_m_n(pixel_clock, link_clock,
7035 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7036}
7037
a7615030
CW		 7038static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7039{
d330a953
JN		 7040 if (i915.panel_use_ssc >= 0)
7041 return i915.panel_use_ssc != 0;
41aa3448 7042 return dev_priv->vbt.lvds_use_ssc
435793df 7043 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7044}
7045
a93e255f
ACO		 7046static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7047 int num_connectors)
c65d77d8 7048{
a93e255f 7049 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7050 struct drm_i915_private *dev_priv = dev->dev_private;
7051 int refclk;
7052
a93e255f
ACO		 7053 WARN_ON(!crtc_state->base.state);
7054
5ab7b0b7 7055 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7056 refclk = 100000;
a93e255f 7057 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7058 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7059 refclk = dev_priv->vbt.lvds_ssc_freq;
7060 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7061 } else if (!IS_GEN2(dev)) {
7062 refclk = 96000;
7063 } else {
7064 refclk = 48000;
7065 }
7066
7067 return refclk;
7068}
7069
7429e9d4 7070static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7071{
7df00d7a 7072 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7073}
f47709a9 7074
7429e9d4
DV		 7075static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7076{
7077 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7078}
7079
f47709a9 7080static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7081 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7082 intel_clock_t *reduced_clock)
7083{
f47709a9 7084 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7085 u32 fp, fp2 = 0;
7086
7087 if (IS_PINEVIEW(dev)) {
190f68c5 7088 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7089 if (reduced_clock)
7429e9d4 7090 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7091 } else {
190f68c5 7092 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7093 if (reduced_clock)
7429e9d4 7094 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7095 }
7096
190f68c5 7097 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7098
f47709a9 7099 crtc->lowfreq_avail = false;
a93e255f 7100 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7101 reduced_clock) {
190f68c5 7102 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7103 crtc->lowfreq_avail = true;
a7516a05 7104 } else {
190f68c5 7105 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7106 }
7107}
7108
5e69f97f
CML		 7109static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7110 pipe)
89b667f8
JB		 7111{
7112 u32 reg_val;
7113
7114 /*
7115 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7116 * and set it to a reasonable value instead.
7117 */
ab3c759a 7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7119 reg_val &= 0xffffff00;
7120 reg_val |= 0x00000030;
ab3c759a 7121 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7122
ab3c759a 7123 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7124 reg_val &= 0x8cffffff;
7125 reg_val = 0x8c000000;
ab3c759a 7126 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7127
ab3c759a 7128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7129 reg_val &= 0xffffff00;
ab3c759a 7130 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7131
ab3c759a 7132 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7133 reg_val &= 0x00ffffff;
7134 reg_val |= 0xb0000000;
ab3c759a 7135 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7136}
7137
b551842d
DV		 7138static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7139 struct intel_link_m_n *m_n)
7140{
7141 struct drm_device *dev = crtc->base.dev;
7142 struct drm_i915_private *dev_priv = dev->dev_private;
7143 int pipe = crtc->pipe;
7144
e3b95f1e
DV		 7145 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7146 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7147 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7148 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7149}
7150
7151static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7152 struct intel_link_m_n *m_n,
7153 struct intel_link_m_n *m2_n2)
b551842d
DV		 7154{
7155 struct drm_device *dev = crtc->base.dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 int pipe = crtc->pipe;
6e3c9717 7158 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7159
7160 if (INTEL_INFO(dev)->gen >= 5) {
7161 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7162 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7163 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7164 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7165 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7166 * for gen < 8) and if DRRS is supported (to make sure the
7167 * registers are not unnecessarily accessed).
7168 */
44395bfe 7169 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7170 crtc->config->has_drrs) {
f769cd24
VK		 7171 I915_WRITE(PIPE_DATA_M2(transcoder),
7172 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7173 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7174 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7175 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7176 }
b551842d 7177 } else {
e3b95f1e
DV		 7178 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7179 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7180 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7181 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7182 }
7183}
7184
fe3cd48d 7185void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7186{
fe3cd48d
R		 7187 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7188
7189 if (m_n == M1_N1) {
7190 dp_m_n = &crtc->config->dp_m_n;
7191 dp_m2_n2 = &crtc->config->dp_m2_n2;
7192 } else if (m_n == M2_N2) {
7193
7194 /*
7195 * M2_N2 registers are not supported. Hence m2_n2 divider value
7196 * needs to be programmed into M1_N1.
7197 */
7198 dp_m_n = &crtc->config->dp_m2_n2;
7199 } else {
7200 DRM_ERROR("Unsupported divider value\n");
7201 return;
7202 }
7203
6e3c9717
ACO		 7204 if (crtc->config->has_pch_encoder)
7205 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7206 else
fe3cd48d 7207 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7208}
7209
251ac862
DV		 7210static void vlv_compute_dpll(struct intel_crtc *crtc,
7211 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7212{
7213 u32 dpll, dpll_md;
7214
7215 /*
7216 * Enable DPIO clock input. We should never disable the reference
7217 * clock for pipe B, since VGA hotplug / manual detection depends
7218 * on it.
7219 */
60bfe44f
VS		 7220 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7221 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7222 /* We should never disable this, set it here for state tracking */
7223 if (crtc->pipe == PIPE_B)
7224 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7225 dpll |= DPLL_VCO_ENABLE;
d288f65f 7226 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7227
d288f65f 7228 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7229 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7230 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7231}
7232
d288f65f 7233static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7234 const struct intel_crtc_state *pipe_config)
a0c4da24 7235{
f47709a9 7236 struct drm_device *dev = crtc->base.dev;
a0c4da24 7237 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7238 int pipe = crtc->pipe;
bdd4b6a6 7239 u32 mdiv;
a0c4da24 7240 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7241 u32 coreclk, reg_val;
a0c4da24 7242
a580516d 7243 mutex_lock(&dev_priv->sb_lock);
09153000 7244
d288f65f
VS		 7245 bestn = pipe_config->dpll.n;
7246 bestm1 = pipe_config->dpll.m1;
7247 bestm2 = pipe_config->dpll.m2;
7248 bestp1 = pipe_config->dpll.p1;
7249 bestp2 = pipe_config->dpll.p2;
a0c4da24 7250
89b667f8
JB		 7251 /* See eDP HDMI DPIO driver vbios notes doc */
7252
7253 /* PLL B needs special handling */
bdd4b6a6 7254 if (pipe == PIPE_B)
5e69f97f 7255 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7256
7257 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7258 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7259
7260 /* Disable target IRef on PLL */
ab3c759a 7261 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7262 reg_val &= 0x00ffffff;
ab3c759a 7263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7264
7265 /* Disable fast lock */
ab3c759a 7266 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7267
7268 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7269 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7270 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7271 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7272 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7273
7274 /*
7275 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7276 * but we don't support that).
7277 * Note: don't use the DAC post divider as it seems unstable.
7278 */
7279 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7280 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7281
a0c4da24 7282 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7284
89b667f8 7285 /* Set HBR and RBR LPF coefficients */
d288f65f 7286 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7287 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7288 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7290 0x009f0003);
89b667f8 7291 else
ab3c759a 7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7293 0x00d0000f);
7294
681a8504 7295 if (pipe_config->has_dp_encoder) {
89b667f8 7296 /* Use SSC source */
bdd4b6a6 7297 if (pipe == PIPE_A)
ab3c759a 7298 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7299 0x0df40000);
7300 else
ab3c759a 7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7302 0x0df70000);
7303 } else { /* HDMI or VGA */
7304 /* Use bend source */
bdd4b6a6 7305 if (pipe == PIPE_A)
ab3c759a 7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7307 0x0df70000);
7308 else
ab3c759a 7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7310 0x0df40000);
7311 }
a0c4da24 7312
ab3c759a 7313 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7314 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7315 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7316 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7317 coreclk |= 0x01000000;
ab3c759a 7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7319
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7321 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7322}
7323
251ac862
DV		 7324static void chv_compute_dpll(struct intel_crtc *crtc,
7325 struct intel_crtc_state *pipe_config)
1ae0d137 7326{
60bfe44f
VS		 7327 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7328 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7329 DPLL_VCO_ENABLE;
7330 if (crtc->pipe != PIPE_A)
d288f65f 7331 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7332
d288f65f
VS		 7333 pipe_config->dpll_hw_state.dpll_md =
7334 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7335}
7336
d288f65f 7337static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7338 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7339{
7340 struct drm_device *dev = crtc->base.dev;
7341 struct drm_i915_private *dev_priv = dev->dev_private;
7342 int pipe = crtc->pipe;
7343 int dpll_reg = DPLL(crtc->pipe);
7344 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7345 u32 loopfilter, tribuf_calcntr;
9d556c99 7346 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7347 u32 dpio_val;
9cbe40c1 7348 int vco;
9d556c99 7349
d288f65f
VS		 7350 bestn = pipe_config->dpll.n;
7351 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7352 bestm1 = pipe_config->dpll.m1;
7353 bestm2 = pipe_config->dpll.m2 >> 22;
7354 bestp1 = pipe_config->dpll.p1;
7355 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7356 vco = pipe_config->dpll.vco;
a945ce7e 7357 dpio_val = 0;
9cbe40c1 7358 loopfilter = 0;
9d556c99
CML		 7359
7360 /*
7361 * Enable Refclk and SSC
7362 */
a11b0703 7363 I915_WRITE(dpll_reg,
d288f65f 7364 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7365
a580516d 7366 mutex_lock(&dev_priv->sb_lock);
9d556c99 7367
9d556c99
CML		 7368 /* p1 and p2 divider */
7369 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7370 5 << DPIO_CHV_S1_DIV_SHIFT |
7371 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7372 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7373 1 << DPIO_CHV_K_DIV_SHIFT);
7374
7375 /* Feedback post-divider - m2 */
7376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7377
7378 /* Feedback refclk divider - n and m1 */
7379 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7380 DPIO_CHV_M1_DIV_BY_2 |
7381 1 << DPIO_CHV_N_DIV_SHIFT);
7382
7383 /* M2 fraction division */
25a25dfc 7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7385
7386 /* M2 fraction division enable */
a945ce7e
VP		 7387 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7388 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7389 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7390 if (bestm2_frac)
7391 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7392 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7393
de3a0fde
VP		 7394 /* Program digital lock detect threshold */
7395 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7396 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7397 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7398 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7399 if (!bestm2_frac)
7400 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7401 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7402
9d556c99 7403 /* Loop filter */
9cbe40c1
VP		 7404 if (vco == 5400000) {
7405 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7406 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7407 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7408 tribuf_calcntr = 0x9;
7409 } else if (vco <= 6200000) {
7410 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7411 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7412 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7413 tribuf_calcntr = 0x9;
7414 } else if (vco <= 6480000) {
7415 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7416 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7417 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7418 tribuf_calcntr = 0x8;
7419 } else {
7420 /* Not supported. Apply the same limits as in the max case */
7421 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7422 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7423 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424 tribuf_calcntr = 0;
7425 }
9d556c99
CML		 7426 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7427
968040b2 7428 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7429 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7430 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7431 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7432
9d556c99
CML		 7433 /* AFC Recal */
7434 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7435 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7436 DPIO_AFC_RECAL);
7437
a580516d 7438 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7439}
7440
d288f65f
VS		 7441/**
7442 * vlv_force_pll_on - forcibly enable just the PLL
7443 * @dev_priv: i915 private structure
7444 * @pipe: pipe PLL to enable
7445 * @dpll: PLL configuration
7446 *
7447 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7448 * in cases where we need the PLL enabled even when @pipe is not going to
7449 * be enabled.
7450 */
7451void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7452 const struct dpll *dpll)
7453{
7454 struct intel_crtc *crtc =
7455 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7456 struct intel_crtc_state pipe_config = {
a93e255f 7457 .base.crtc = &crtc->base,
d288f65f
VS		 7458 .pixel_multiplier = 1,
7459 .dpll = *dpll,
7460 };
7461
7462 if (IS_CHERRYVIEW(dev)) {
251ac862 7463 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7464 chv_prepare_pll(crtc, &pipe_config);
7465 chv_enable_pll(crtc, &pipe_config);
7466 } else {
251ac862 7467 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7468 vlv_prepare_pll(crtc, &pipe_config);
7469 vlv_enable_pll(crtc, &pipe_config);
7470 }
7471}
7472
7473/**
7474 * vlv_force_pll_off - forcibly disable just the PLL
7475 * @dev_priv: i915 private structure
7476 * @pipe: pipe PLL to disable
7477 *
7478 * Disable the PLL for @pipe. To be used in cases where we need
7479 * the PLL enabled even when @pipe is not going to be enabled.
7480 */
7481void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7482{
7483 if (IS_CHERRYVIEW(dev))
7484 chv_disable_pll(to_i915(dev), pipe);
7485 else
7486 vlv_disable_pll(to_i915(dev), pipe);
7487}
7488
251ac862
DV		 7489static void i9xx_compute_dpll(struct intel_crtc *crtc,
7490 struct intel_crtc_state *crtc_state,
7491 intel_clock_t *reduced_clock,
7492 int num_connectors)
eb1cbe48 7493{
f47709a9 7494 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7495 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7496 u32 dpll;
7497 bool is_sdvo;
190f68c5 7498 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7499
190f68c5 7500 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7501
a93e255f
ACO		 7502 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7503 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7504
7505 dpll = DPLL_VGA_MODE_DIS;
7506
a93e255f 7507 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7508 dpll |= DPLLB_MODE_LVDS;
7509 else
7510 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7511
ef1b460d 7512 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7513 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7514 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7515 }
198a037f
DV		 7516
7517 if (is_sdvo)
4a33e48d 7518 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7519
190f68c5 7520 if (crtc_state->has_dp_encoder)
4a33e48d 7521 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7522
7523 /* compute bitmask from p1 value */
7524 if (IS_PINEVIEW(dev))
7525 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7526 else {
7527 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7528 if (IS_G4X(dev) && reduced_clock)
7529 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7530 }
7531 switch (clock->p2) {
7532 case 5:
7533 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7534 break;
7535 case 7:
7536 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7537 break;
7538 case 10:
7539 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7540 break;
7541 case 14:
7542 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7543 break;
7544 }
7545 if (INTEL_INFO(dev)->gen >= 4)
7546 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7547
190f68c5 7548 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7549 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7550 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7551 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7552 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7553 else
7554 dpll |= PLL_REF_INPUT_DREFCLK;
7555
7556 dpll |= DPLL_VCO_ENABLE;
190f68c5 7557 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7558
eb1cbe48 7559 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7560 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7561 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7562 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7563 }
7564}
7565
251ac862
DV		 7566static void i8xx_compute_dpll(struct intel_crtc *crtc,
7567 struct intel_crtc_state *crtc_state,
7568 intel_clock_t *reduced_clock,
7569 int num_connectors)
eb1cbe48 7570{
f47709a9 7571 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7572 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7573 u32 dpll;
190f68c5 7574 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7575
190f68c5 7576 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7577
eb1cbe48
DV		 7578 dpll = DPLL_VGA_MODE_DIS;
7579
a93e255f 7580 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7581 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7582 } else {
7583 if (clock->p1 == 2)
7584 dpll |= PLL_P1_DIVIDE_BY_TWO;
7585 else
7586 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7587 if (clock->p2 == 4)
7588 dpll |= PLL_P2_DIVIDE_BY_4;
7589 }
7590
a93e255f 7591 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7592 dpll |= DPLL_DVO_2X_MODE;
7593
a93e255f 7594 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7595 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7596 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7597 else
7598 dpll |= PLL_REF_INPUT_DREFCLK;
7599
7600 dpll |= DPLL_VCO_ENABLE;
190f68c5 7601 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7602}
7603
8a654f3b 7604static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7605{
7606 struct drm_device *dev = intel_crtc->base.dev;
7607 struct drm_i915_private *dev_priv = dev->dev_private;
7608 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7609 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7610 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7611 uint32_t crtc_vtotal, crtc_vblank_end;
7612 int vsyncshift = 0;
4d8a62ea
DV		 7613
7614 /* We need to be careful not to changed the adjusted mode, for otherwise
7615 * the hw state checker will get angry at the mismatch. */
7616 crtc_vtotal = adjusted_mode->crtc_vtotal;
7617 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7618
609aeaca 7619 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7620 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7621 crtc_vtotal -= 1;
7622 crtc_vblank_end -= 1;
609aeaca 7623
409ee761 7624 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7625 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7626 else
7627 vsyncshift = adjusted_mode->crtc_hsync_start -
7628 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7629 if (vsyncshift < 0)
7630 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7631 }
7632
7633 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7634 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7635
fe2b8f9d 7636 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7637 (adjusted_mode->crtc_hdisplay - 1) |
7638 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7639 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7640 (adjusted_mode->crtc_hblank_start - 1) |
7641 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7642 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7643 (adjusted_mode->crtc_hsync_start - 1) |
7644 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7645
fe2b8f9d 7646 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7647 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7648 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7649 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7650 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7651 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7652 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7653 (adjusted_mode->crtc_vsync_start - 1) |
7654 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7655
b5e508d4
PZ		 7656 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7657 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7658 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7659 * bits. */
7660 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7661 (pipe == PIPE_B || pipe == PIPE_C))
7662 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7663
b0e77b9c
PZ		 7664 /* pipesrc controls the size that is scaled from, which should
7665 * always be the user's requested size.
7666 */
7667 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7668 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7669 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7670}
7671
1bd1bd80 7672static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7673 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7674{
7675 struct drm_device *dev = crtc->base.dev;
7676 struct drm_i915_private *dev_priv = dev->dev_private;
7677 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7678 uint32_t tmp;
7679
7680 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7681 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7682 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7683 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7684 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7685 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7686 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7687 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7688 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7689
7690 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7691 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7693 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7694 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7696 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7697 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7698 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7699
7700 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7701 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7702 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7703 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7704 }
7705
7706 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7707 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7708 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7709
2d112de7
ACO		 7710 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7711 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7712}
7713
f6a83288 7714void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7715 struct intel_crtc_state *pipe_config)
babea61d 7716{
2d112de7
ACO		 7717 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7718 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7719 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7720 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7721
2d112de7
ACO		 7722 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7723 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7724 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7725 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7726
2d112de7 7727 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7728 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7729
2d112de7
ACO		 7730 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7731 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7732
7733 mode->hsync = drm_mode_hsync(mode);
7734 mode->vrefresh = drm_mode_vrefresh(mode);
7735 drm_mode_set_name(mode);
babea61d
JB		 7736}
7737
84b046f3
DV		 7738static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7739{
7740 struct drm_device *dev = intel_crtc->base.dev;
7741 struct drm_i915_private *dev_priv = dev->dev_private;
7742 uint32_t pipeconf;
7743
9f11a9e4 7744 pipeconf = 0;
84b046f3 7745
b6b5d049
VS		 7746 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7747 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7748 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7749
6e3c9717 7750 if (intel_crtc->config->double_wide)
cf532bb2 7751 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7752
ff9ce46e
DV		 7753 /* only g4x and later have fancy bpc/dither controls */
7754 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7755 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7756 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7757 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7758 PIPECONF_DITHER_TYPE_SP;
84b046f3 7759
6e3c9717 7760 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7761 case 18:
7762 pipeconf |= PIPECONF_6BPC;
7763 break;
7764 case 24:
7765 pipeconf |= PIPECONF_8BPC;
7766 break;
7767 case 30:
7768 pipeconf |= PIPECONF_10BPC;
7769 break;
7770 default:
7771 /* Case prevented by intel_choose_pipe_bpp_dither. */
7772 BUG();
84b046f3
DV		 7773 }
7774 }
7775
7776 if (HAS_PIPE_CXSR(dev)) {
7777 if (intel_crtc->lowfreq_avail) {
7778 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7779 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7780 } else {
7781 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7782 }
7783 }
7784
6e3c9717 7785 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7786 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7787 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7788 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7789 else
7790 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7791 } else
84b046f3
DV		 7792 pipeconf |= PIPECONF_PROGRESSIVE;
7793
6e3c9717 7794 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7795 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7796
84b046f3
DV		 7797 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7798 POSTING_READ(PIPECONF(intel_crtc->pipe));
7799}
7800
190f68c5
ACO		 7801static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7802 struct intel_crtc_state *crtc_state)
79e53945 7803{
c7653199 7804 struct drm_device *dev = crtc->base.dev;
79e53945 7805 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7806 int refclk, num_connectors = 0;
c329a4ec
DV		 7807 intel_clock_t clock;
7808 bool ok;
7809 bool is_dsi = false;
5eddb70b 7810 struct intel_encoder *encoder;
d4906093 7811 const intel_limit_t *limit;
55bb9992 7812 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7813 struct drm_connector *connector;
55bb9992
ACO		 7814 struct drm_connector_state *connector_state;
7815 int i;
79e53945 7816
dd3cd74a
ACO		 7817 memset(&crtc_state->dpll_hw_state, 0,
7818 sizeof(crtc_state->dpll_hw_state));
7819
da3ced29 7820 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7821 if (connector_state->crtc != &crtc->base)
7822 continue;
7823
7824 encoder = to_intel_encoder(connector_state->best_encoder);
7825
5eddb70b 7826 switch (encoder->type) {
e9fd1c02
JN		 7827 case INTEL_OUTPUT_DSI:
7828 is_dsi = true;
7829 break;
6847d71b
PZ		 7830 default:
7831 break;
79e53945 7832 }
43565a06 7833
c751ce4f 7834 num_connectors++;
79e53945
JB		 7835 }
7836
f2335330 7837 if (is_dsi)
5b18e57c 7838 return 0;
f2335330 7839
190f68c5 7840 if (!crtc_state->clock_set) {
a93e255f 7841 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7842
e9fd1c02
JN		 7843 /*
7844 * Returns a set of divisors for the desired target clock with
7845 * the given refclk, or FALSE. The returned values represent
7846 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7847 * 2) / p1 / p2.
7848 */
a93e255f
ACO		 7849 limit = intel_limit(crtc_state, refclk);
7850 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7851 crtc_state->port_clock,
e9fd1c02 7852 refclk, NULL, &clock);
f2335330 7853 if (!ok) {
e9fd1c02
JN		 7854 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7855 return -EINVAL;
7856 }
79e53945 7857
f2335330 7858 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7859 crtc_state->dpll.n = clock.n;
7860 crtc_state->dpll.m1 = clock.m1;
7861 crtc_state->dpll.m2 = clock.m2;
7862 crtc_state->dpll.p1 = clock.p1;
7863 crtc_state->dpll.p2 = clock.p2;
f47709a9 7864 }
7026d4ac 7865
e9fd1c02 7866 if (IS_GEN2(dev)) {
c329a4ec 7867 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7868 num_connectors);
9d556c99 7869 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7870 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7871 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7872 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7873 } else {
c329a4ec 7874 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7875 num_connectors);
e9fd1c02 7876 }
79e53945 7877
c8f7a0db 7878 return 0;
f564048e
EA		 7879}
7880
2fa2fe9a 7881static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7882 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7883{
7884 struct drm_device *dev = crtc->base.dev;
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 uint32_t tmp;
7887
dc9e7dec
VS		 7888 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7889 return;
7890
2fa2fe9a 7891 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7892 if (!(tmp & PFIT_ENABLE))
7893 return;
2fa2fe9a 7894
06922821 7895 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7896 if (INTEL_INFO(dev)->gen < 4) {
7897 if (crtc->pipe != PIPE_B)
7898 return;
2fa2fe9a
DV		 7899 } else {
7900 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7901 return;
7902 }
7903
06922821 7904 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7905 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7906 if (INTEL_INFO(dev)->gen < 5)
7907 pipe_config->gmch_pfit.lvds_border_bits =
7908 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7909}
7910
acbec814 7911static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7912 struct intel_crtc_state *pipe_config)
acbec814
JB		 7913{
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916 int pipe = pipe_config->cpu_transcoder;
7917 intel_clock_t clock;
7918 u32 mdiv;
662c6ecb 7919 int refclk = 100000;
acbec814 7920
f573de5a
SK		 7921 /* In case of MIPI DPLL will not even be used */
7922 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7923 return;
7924
a580516d 7925 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7926 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7927 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7928
7929 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7930 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7931 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7932 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7933 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7934
dccbea3b 7935 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7936}
7937
5724dbd1
DL		 7938static void
7939i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7940 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7941{
7942 struct drm_device *dev = crtc->base.dev;
7943 struct drm_i915_private *dev_priv = dev->dev_private;
7944 u32 val, base, offset;
7945 int pipe = crtc->pipe, plane = crtc->plane;
7946 int fourcc, pixel_format;
6761dd31 7947 unsigned int aligned_height;
b113d5ee 7948 struct drm_framebuffer *fb;
1b842c89 7949 struct intel_framebuffer *intel_fb;
1ad292b5 7950
42a7b088
DL		 7951 val = I915_READ(DSPCNTR(plane));
7952 if (!(val & DISPLAY_PLANE_ENABLE))
7953 return;
7954
d9806c9f 7955 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7956 if (!intel_fb) {
1ad292b5
JB		 7957 DRM_DEBUG_KMS("failed to alloc fb\n");
7958 return;
7959 }
7960
1b842c89
DL		 7961 fb = &intel_fb->base;
7962
18c5247e
DV		 7963 if (INTEL_INFO(dev)->gen >= 4) {
7964 if (val & DISPPLANE_TILED) {
49af449b 7965 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7966 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7967 }
7968 }
1ad292b5
JB		 7969
7970 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7971 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7972 fb->pixel_format = fourcc;
7973 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7974
7975 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7976 if (plane_config->tiling)
1ad292b5
JB		 7977 offset = I915_READ(DSPTILEOFF(plane));
7978 else
7979 offset = I915_READ(DSPLINOFF(plane));
7980 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7981 } else {
7982 base = I915_READ(DSPADDR(plane));
7983 }
7984 plane_config->base = base;
7985
7986 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7987 fb->width = ((val >> 16) & 0xfff) + 1;
7988 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7989
7990 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7991 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7992
b113d5ee 7993 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7994 fb->pixel_format,
7995 fb->modifier[0]);
1ad292b5 7996
f37b5c2b 7997 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7998
2844a921
DL		 7999 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8000 pipe_name(pipe), plane, fb->width, fb->height,
8001 fb->bits_per_pixel, base, fb->pitches[0],
8002 plane_config->size);
1ad292b5 8003
2d14030b 8004 plane_config->fb = intel_fb;
1ad292b5
JB		 8005}
8006
70b23a98 8007static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8008 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8009{
8010 struct drm_device *dev = crtc->base.dev;
8011 struct drm_i915_private *dev_priv = dev->dev_private;
8012 int pipe = pipe_config->cpu_transcoder;
8013 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8014 intel_clock_t clock;
0d7b6b11 8015 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8016 int refclk = 100000;
8017
a580516d 8018 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8019 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8020 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8021 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8022 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8023 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8024 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8025
8026 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8027 clock.m2 = (pll_dw0 & 0xff) << 22;
8028 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8029 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8030 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8031 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8032 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8033
dccbea3b 8034 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8035}
8036
0e8ffe1b 8037static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8038 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8039{
8040 struct drm_device *dev = crtc->base.dev;
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042 uint32_t tmp;
8043
f458ebbc
DV		 8044 if (!intel_display_power_is_enabled(dev_priv,
8045 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8046 return false;
8047
e143a21c 8048 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8049 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8050
0e8ffe1b
DV		 8051 tmp = I915_READ(PIPECONF(crtc->pipe));
8052 if (!(tmp & PIPECONF_ENABLE))
8053 return false;
8054
42571aef
VS		 8055 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8056 switch (tmp & PIPECONF_BPC_MASK) {
8057 case PIPECONF_6BPC:
8058 pipe_config->pipe_bpp = 18;
8059 break;
8060 case PIPECONF_8BPC:
8061 pipe_config->pipe_bpp = 24;
8062 break;
8063 case PIPECONF_10BPC:
8064 pipe_config->pipe_bpp = 30;
8065 break;
8066 default:
8067 break;
8068 }
8069 }
8070
b5a9fa09
DV		 8071 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8072 pipe_config->limited_color_range = true;
8073
282740f7
VS		 8074 if (INTEL_INFO(dev)->gen < 4)
8075 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8076
1bd1bd80
DV		 8077 intel_get_pipe_timings(crtc, pipe_config);
8078
2fa2fe9a
DV		 8079 i9xx_get_pfit_config(crtc, pipe_config);
8080
6c49f241
DV		 8081 if (INTEL_INFO(dev)->gen >= 4) {
8082 tmp = I915_READ(DPLL_MD(crtc->pipe));
8083 pipe_config->pixel_multiplier =
8084 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8085 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8086 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8087 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8088 tmp = I915_READ(DPLL(crtc->pipe));
8089 pipe_config->pixel_multiplier =
8090 ((tmp & SDVO_MULTIPLIER_MASK)
8091 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8092 } else {
8093 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8094 * port and will be fixed up in the encoder->get_config
8095 * function. */
8096 pipe_config->pixel_multiplier = 1;
8097 }
8bcc2795
DV		 8098 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8099 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8100 /*
8101 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8102 * on 830. Filter it out here so that we don't
8103 * report errors due to that.
8104 */
8105 if (IS_I830(dev))
8106 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8107
8bcc2795
DV		 8108 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8109 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8110 } else {
8111 /* Mask out read-only status bits. */
8112 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8113 DPLL_PORTC_READY_MASK |
8114 DPLL_PORTB_READY_MASK);
8bcc2795 8115 }
6c49f241 8116
70b23a98
VS		 8117 if (IS_CHERRYVIEW(dev))
8118 chv_crtc_clock_get(crtc, pipe_config);
8119 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8120 vlv_crtc_clock_get(crtc, pipe_config);
8121 else
8122 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8123
0f64614d
VS		 8124 /*
8125 * Normally the dotclock is filled in by the encoder .get_config()
8126 * but in case the pipe is enabled w/o any ports we need a sane
8127 * default.
8128 */
8129 pipe_config->base.adjusted_mode.crtc_clock =
8130 pipe_config->port_clock / pipe_config->pixel_multiplier;
8131
0e8ffe1b
DV		 8132 return true;
8133}
8134
dde86e2d 8135static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8136{
8137 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8138 struct intel_encoder *encoder;
74cfd7ac 8139 u32 val, final;
13d83a67 8140 bool has_lvds = false;
199e5d79 8141 bool has_cpu_edp = false;
199e5d79 8142 bool has_panel = false;
99eb6a01
KP		 8143 bool has_ck505 = false;
8144 bool can_ssc = false;
13d83a67
JB		 8145
8146 /* We need to take the global config into account */
b2784e15 8147 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8148 switch (encoder->type) {
8149 case INTEL_OUTPUT_LVDS:
8150 has_panel = true;
8151 has_lvds = true;
8152 break;
8153 case INTEL_OUTPUT_EDP:
8154 has_panel = true;
2de6905f 8155 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8156 has_cpu_edp = true;
8157 break;
6847d71b
PZ		 8158 default:
8159 break;
13d83a67
JB		 8160 }
8161 }
8162
99eb6a01 8163 if (HAS_PCH_IBX(dev)) {
41aa3448 8164 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8165 can_ssc = has_ck505;
8166 } else {
8167 has_ck505 = false;
8168 can_ssc = true;
8169 }
8170
2de6905f
ID		 8171 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8172 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8173
8174 /* Ironlake: try to setup display ref clock before DPLL
8175 * enabling. This is only under driver's control after
8176 * PCH B stepping, previous chipset stepping should be
8177 * ignoring this setting.
8178 */
74cfd7ac
CW		 8179 val = I915_READ(PCH_DREF_CONTROL);
8180
8181 /* As we must carefully and slowly disable/enable each source in turn,
8182 * compute the final state we want first and check if we need to
8183 * make any changes at all.
8184 */
8185 final = val;
8186 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8187 if (has_ck505)
8188 final |= DREF_NONSPREAD_CK505_ENABLE;
8189 else
8190 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8191
8192 final &= ~DREF_SSC_SOURCE_MASK;
8193 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8194 final &= ~DREF_SSC1_ENABLE;
8195
8196 if (has_panel) {
8197 final |= DREF_SSC_SOURCE_ENABLE;
8198
8199 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8200 final |= DREF_SSC1_ENABLE;
8201
8202 if (has_cpu_edp) {
8203 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8204 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8205 else
8206 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8207 } else
8208 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8209 } else {
8210 final |= DREF_SSC_SOURCE_DISABLE;
8211 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8212 }
8213
8214 if (final == val)
8215 return;
8216
13d83a67 8217 /* Always enable nonspread source */
74cfd7ac 8218 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8219
99eb6a01 8220 if (has_ck505)
74cfd7ac 8221 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8222 else
74cfd7ac 8223 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8224
199e5d79 8225 if (has_panel) {
74cfd7ac
CW		 8226 val &= ~DREF_SSC_SOURCE_MASK;
8227 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8228
199e5d79 8229 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8230 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8231 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8232 val |= DREF_SSC1_ENABLE;
e77166b5 8233 } else
74cfd7ac 8234 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8235
8236 /* Get SSC going before enabling the outputs */
74cfd7ac 8237 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8238 POSTING_READ(PCH_DREF_CONTROL);
8239 udelay(200);
8240
74cfd7ac 8241 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8242
8243 /* Enable CPU source on CPU attached eDP */
199e5d79 8244 if (has_cpu_edp) {
99eb6a01 8245 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8246 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8247 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8248 } else
74cfd7ac 8249 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8250 } else
74cfd7ac 8251 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8252
74cfd7ac 8253 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8254 POSTING_READ(PCH_DREF_CONTROL);
8255 udelay(200);
8256 } else {
8257 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8258
74cfd7ac 8259 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8260
8261 /* Turn off CPU output */
74cfd7ac 8262 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8263
74cfd7ac 8264 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8265 POSTING_READ(PCH_DREF_CONTROL);
8266 udelay(200);
8267
8268 /* Turn off the SSC source */
74cfd7ac
CW		 8269 val &= ~DREF_SSC_SOURCE_MASK;
8270 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8271
8272 /* Turn off SSC1 */
74cfd7ac 8273 val &= ~DREF_SSC1_ENABLE;
199e5d79 8274
74cfd7ac 8275 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8276 POSTING_READ(PCH_DREF_CONTROL);
8277 udelay(200);
8278 }
74cfd7ac
CW		 8279
8280 BUG_ON(val != final);
13d83a67
JB		 8281}
8282
f31f2d55 8283static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8284{
f31f2d55 8285 uint32_t tmp;
dde86e2d 8286
0ff066a9
PZ		 8287 tmp = I915_READ(SOUTH_CHICKEN2);
8288 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8289 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8290
0ff066a9
PZ		 8291 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8292 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8293 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8294
0ff066a9
PZ		 8295 tmp = I915_READ(SOUTH_CHICKEN2);
8296 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8297 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8298
0ff066a9
PZ		 8299 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8300 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8301 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8302}
8303
8304/* WaMPhyProgramming:hsw */
8305static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8306{
8307 uint32_t tmp;
dde86e2d
PZ		 8308
8309 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8310 tmp &= ~(0xFF << 24);
8311 tmp |= (0x12 << 24);
8312 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8313
dde86e2d
PZ		 8314 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8315 tmp |= (1 << 11);
8316 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8319 tmp |= (1 << 11);
8320 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8321
dde86e2d
PZ		 8322 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8323 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8324 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8325
8326 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8327 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8328 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8329
0ff066a9
PZ		 8330 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8331 tmp &= ~(7 << 13);
8332 tmp |= (5 << 13);
8333 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8334
0ff066a9
PZ		 8335 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8336 tmp &= ~(7 << 13);
8337 tmp |= (5 << 13);
8338 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8339
8340 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8341 tmp &= ~0xFF;
8342 tmp |= 0x1C;
8343 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8344
8345 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8346 tmp &= ~0xFF;
8347 tmp |= 0x1C;
8348 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8349
8350 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8351 tmp &= ~(0xFF << 16);
8352 tmp |= (0x1C << 16);
8353 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8354
8355 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8356 tmp &= ~(0xFF << 16);
8357 tmp |= (0x1C << 16);
8358 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8359
0ff066a9
PZ		 8360 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8361 tmp |= (1 << 27);
8362 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8363
0ff066a9
PZ		 8364 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8365 tmp |= (1 << 27);
8366 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8367
0ff066a9
PZ		 8368 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8369 tmp &= ~(0xF << 28);
8370 tmp |= (4 << 28);
8371 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8372
0ff066a9
PZ		 8373 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8374 tmp &= ~(0xF << 28);
8375 tmp |= (4 << 28);
8376 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8377}
8378
2fa86a1f
PZ		 8379/* Implements 3 different sequences from BSpec chapter "Display iCLK
8380 * Programming" based on the parameters passed:
8381 * - Sequence to enable CLKOUT_DP
8382 * - Sequence to enable CLKOUT_DP without spread
8383 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8384 */
8385static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8386 bool with_fdi)
f31f2d55
PZ		 8387{
8388 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8389 uint32_t reg, tmp;
8390
8391 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8392 with_spread = true;
c2699524 8393 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8394 with_fdi = false;
f31f2d55 8395
a580516d 8396 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8397
8398 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8399 tmp &= ~SBI_SSCCTL_DISABLE;
8400 tmp |= SBI_SSCCTL_PATHALT;
8401 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8402
8403 udelay(24);
8404
2fa86a1f
PZ		 8405 if (with_spread) {
8406 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8407 tmp &= ~SBI_SSCCTL_PATHALT;
8408 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8409
2fa86a1f
PZ		 8410 if (with_fdi) {
8411 lpt_reset_fdi_mphy(dev_priv);
8412 lpt_program_fdi_mphy(dev_priv);
8413 }
8414 }
dde86e2d 8415
c2699524 8416 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8417 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8418 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8419 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8420
a580516d 8421 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8422}
8423
47701c3b
PZ		 8424/* Sequence to disable CLKOUT_DP */
8425static void lpt_disable_clkout_dp(struct drm_device *dev)
8426{
8427 struct drm_i915_private *dev_priv = dev->dev_private;
8428 uint32_t reg, tmp;
8429
a580516d 8430 mutex_lock(&dev_priv->sb_lock);
47701c3b 8431
c2699524 8432 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8433 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8434 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8435 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8436
8437 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8438 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8439 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8440 tmp |= SBI_SSCCTL_PATHALT;
8441 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8442 udelay(32);
8443 }
8444 tmp |= SBI_SSCCTL_DISABLE;
8445 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8446 }
8447
a580516d 8448 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8449}
8450
bf8fa3d3
PZ		 8451static void lpt_init_pch_refclk(struct drm_device *dev)
8452{
bf8fa3d3
PZ		 8453 struct intel_encoder *encoder;
8454 bool has_vga = false;
8455
b2784e15 8456 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8457 switch (encoder->type) {
8458 case INTEL_OUTPUT_ANALOG:
8459 has_vga = true;
8460 break;
6847d71b
PZ		 8461 default:
8462 break;
bf8fa3d3
PZ		 8463 }
8464 }
8465
47701c3b
PZ		 8466 if (has_vga)
8467 lpt_enable_clkout_dp(dev, true, true);
8468 else
8469 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8470}
8471
dde86e2d
PZ		 8472/*
8473 * Initialize reference clocks when the driver loads
8474 */
8475void intel_init_pch_refclk(struct drm_device *dev)
8476{
8477 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8478 ironlake_init_pch_refclk(dev);
8479 else if (HAS_PCH_LPT(dev))
8480 lpt_init_pch_refclk(dev);
8481}
8482
55bb9992 8483static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8484{
55bb9992 8485 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8486 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8487 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8488 struct drm_connector *connector;
55bb9992 8489 struct drm_connector_state *connector_state;
d9d444cb 8490 struct intel_encoder *encoder;
55bb9992 8491 int num_connectors = 0, i;
d9d444cb
JB		 8492 bool is_lvds = false;
8493
da3ced29 8494 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8495 if (connector_state->crtc != crtc_state->base.crtc)
8496 continue;
8497
8498 encoder = to_intel_encoder(connector_state->best_encoder);
8499
d9d444cb
JB		 8500 switch (encoder->type) {
8501 case INTEL_OUTPUT_LVDS:
8502 is_lvds = true;
8503 break;
6847d71b
PZ		 8504 default:
8505 break;
d9d444cb
JB		 8506 }
8507 num_connectors++;
8508 }
8509
8510 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8511 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8512 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8513 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8514 }
8515
8516 return 120000;
8517}
8518
6ff93609 8519static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8520{
c8203565 8521 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8523 int pipe = intel_crtc->pipe;
c8203565
PZ		 8524 uint32_t val;
8525
78114071 8526 val = 0;
c8203565 8527
6e3c9717 8528 switch (intel_crtc->config->pipe_bpp) {
c8203565 8529 case 18:
dfd07d72 8530 val |= PIPECONF_6BPC;
c8203565
PZ		 8531 break;
8532 case 24:
dfd07d72 8533 val |= PIPECONF_8BPC;
c8203565
PZ		 8534 break;
8535 case 30:
dfd07d72 8536 val |= PIPECONF_10BPC;
c8203565
PZ		 8537 break;
8538 case 36:
dfd07d72 8539 val |= PIPECONF_12BPC;
c8203565
PZ		 8540 break;
8541 default:
cc769b62
PZ		 8542 /* Case prevented by intel_choose_pipe_bpp_dither. */
8543 BUG();
c8203565
PZ		 8544 }
8545
6e3c9717 8546 if (intel_crtc->config->dither)
c8203565
PZ		 8547 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8548
6e3c9717 8549 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8550 val |= PIPECONF_INTERLACED_ILK;
8551 else
8552 val |= PIPECONF_PROGRESSIVE;
8553
6e3c9717 8554 if (intel_crtc->config->limited_color_range)
3685a8f3 8555 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8556
c8203565
PZ		 8557 I915_WRITE(PIPECONF(pipe), val);
8558 POSTING_READ(PIPECONF(pipe));
8559}
8560
86d3efce
VS		 8561/*
8562 * Set up the pipe CSC unit.
8563 *
8564 * Currently only full range RGB to limited range RGB conversion
8565 * is supported, but eventually this should handle various
8566 * RGB<->YCbCr scenarios as well.
8567 */
50f3b016 8568static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8569{
8570 struct drm_device *dev = crtc->dev;
8571 struct drm_i915_private *dev_priv = dev->dev_private;
8572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8573 int pipe = intel_crtc->pipe;
8574 uint16_t coeff = 0x7800; /* 1.0 */
8575
8576 /*
8577 * TODO: Check what kind of values actually come out of the pipe
8578 * with these coeff/postoff values and adjust to get the best
8579 * accuracy. Perhaps we even need to take the bpc value into
8580 * consideration.
8581 */
8582
6e3c9717 8583 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8584 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8585
8586 /*
8587 * GY/GU and RY/RU should be the other way around according
8588 * to BSpec, but reality doesn't agree. Just set them up in
8589 * a way that results in the correct picture.
8590 */
8591 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8592 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8593
8594 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8595 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8596
8597 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8598 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8599
8600 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8601 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8602 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8603
8604 if (INTEL_INFO(dev)->gen > 6) {
8605 uint16_t postoff = 0;
8606
6e3c9717 8607 if (intel_crtc->config->limited_color_range)
32cf0cb0 8608 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8609
8610 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8611 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8612 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8613
8614 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8615 } else {
8616 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8617
6e3c9717 8618 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8619 mode |= CSC_BLACK_SCREEN_OFFSET;
8620
8621 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8622 }
8623}
8624
6ff93609 8625static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8626{
756f85cf
PZ		 8627 struct drm_device *dev = crtc->dev;
8628 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8630 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8631 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8632 uint32_t val;
8633
3eff4faa 8634 val = 0;
ee2b0b38 8635
6e3c9717 8636 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8637 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8638
6e3c9717 8639 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8640 val |= PIPECONF_INTERLACED_ILK;
8641 else
8642 val |= PIPECONF_PROGRESSIVE;
8643
702e7a56
PZ		 8644 I915_WRITE(PIPECONF(cpu_transcoder), val);
8645 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8646
8647 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8648 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8649
3cdf122c 8650 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8651 val = 0;
8652
6e3c9717 8653 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8654 case 18:
8655 val |= PIPEMISC_DITHER_6_BPC;
8656 break;
8657 case 24:
8658 val |= PIPEMISC_DITHER_8_BPC;
8659 break;
8660 case 30:
8661 val |= PIPEMISC_DITHER_10_BPC;
8662 break;
8663 case 36:
8664 val |= PIPEMISC_DITHER_12_BPC;
8665 break;
8666 default:
8667 /* Case prevented by pipe_config_set_bpp. */
8668 BUG();
8669 }
8670
6e3c9717 8671 if (intel_crtc->config->dither)
756f85cf
PZ		 8672 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8673
8674 I915_WRITE(PIPEMISC(pipe), val);
8675 }
ee2b0b38
PZ		 8676}
8677
6591c6e4 8678static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8679 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8680 intel_clock_t *clock,
8681 bool *has_reduced_clock,
8682 intel_clock_t *reduced_clock)
8683{
8684 struct drm_device *dev = crtc->dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8686 int refclk;
d4906093 8687 const intel_limit_t *limit;
c329a4ec 8688 bool ret;
79e53945 8689
55bb9992 8690 refclk = ironlake_get_refclk(crtc_state);
79e53945 8691
d4906093
ML		 8692 /*
8693 * Returns a set of divisors for the desired target clock with the given
8694 * refclk, or FALSE. The returned values represent the clock equation:
8695 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8696 */
a93e255f
ACO		 8697 limit = intel_limit(crtc_state, refclk);
8698 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8699 crtc_state->port_clock,
ee9300bb 8700 refclk, NULL, clock);
6591c6e4
PZ		 8701 if (!ret)
8702 return false;
cda4b7d3 8703
6591c6e4
PZ		 8704 return true;
8705}
8706
d4b1931c
PZ		 8707int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8708{
8709 /*
8710 * Account for spread spectrum to avoid
8711 * oversubscribing the link. Max center spread
8712 * is 2.5%; use 5% for safety's sake.
8713 */
8714 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8715 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8716}
8717
7429e9d4 8718static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8719{
7429e9d4 8720 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8721}
8722
de13a2e3 8723static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8724 struct intel_crtc_state *crtc_state,
7429e9d4 8725 u32 *fp,
9a7c7890 8726 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8727{
de13a2e3 8728 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8729 struct drm_device *dev = crtc->dev;
8730 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8731 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8732 struct drm_connector *connector;
55bb9992
ACO		 8733 struct drm_connector_state *connector_state;
8734 struct intel_encoder *encoder;
de13a2e3 8735 uint32_t dpll;
55bb9992 8736 int factor, num_connectors = 0, i;
09ede541 8737 bool is_lvds = false, is_sdvo = false;
79e53945 8738
da3ced29 8739 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8740 if (connector_state->crtc != crtc_state->base.crtc)
8741 continue;
8742
8743 encoder = to_intel_encoder(connector_state->best_encoder);
8744
8745 switch (encoder->type) {
79e53945
JB		 8746 case INTEL_OUTPUT_LVDS:
8747 is_lvds = true;
8748 break;
8749 case INTEL_OUTPUT_SDVO:
7d57382e 8750 case INTEL_OUTPUT_HDMI:
79e53945 8751 is_sdvo = true;
79e53945 8752 break;
6847d71b
PZ		 8753 default:
8754 break;
79e53945 8755 }
43565a06 8756
c751ce4f 8757 num_connectors++;
79e53945 8758 }
79e53945 8759
c1858123 8760 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8761 factor = 21;
8762 if (is_lvds) {
8763 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8764 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8765 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8766 factor = 25;
190f68c5 8767 } else if (crtc_state->sdvo_tv_clock)
8febb297 8768 factor = 20;
c1858123 8769
190f68c5 8770 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8771 *fp |= FP_CB_TUNE;
2c07245f 8772
9a7c7890
DV		 8773 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8774 *fp2 |= FP_CB_TUNE;
8775
5eddb70b 8776 dpll = 0;
2c07245f 8777
a07d6787
EA		 8778 if (is_lvds)
8779 dpll |= DPLLB_MODE_LVDS;
8780 else
8781 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8782
190f68c5 8783 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8784 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8785
8786 if (is_sdvo)
4a33e48d 8787 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8788 if (crtc_state->has_dp_encoder)
4a33e48d 8789 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8790
a07d6787 8791 /* compute bitmask from p1 value */
190f68c5 8792 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8793 /* also FPA1 */
190f68c5 8794 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8795
190f68c5 8796 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8797 case 5:
8798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8799 break;
8800 case 7:
8801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8802 break;
8803 case 10:
8804 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8805 break;
8806 case 14:
8807 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8808 break;
79e53945
JB		 8809 }
8810
b4c09f3b 8811 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8812 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8813 else
8814 dpll |= PLL_REF_INPUT_DREFCLK;
8815
959e16d6 8816 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8817}
8818
190f68c5
ACO		 8819static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8820 struct intel_crtc_state *crtc_state)
de13a2e3 8821{
c7653199 8822 struct drm_device *dev = crtc->base.dev;
de13a2e3 8823 intel_clock_t clock, reduced_clock;
cbbab5bd 8824 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8825 bool ok, has_reduced_clock = false;
8b47047b 8826 bool is_lvds = false;
e2b78267 8827 struct intel_shared_dpll *pll;
de13a2e3 8828
dd3cd74a
ACO		 8829 memset(&crtc_state->dpll_hw_state, 0,
8830 sizeof(crtc_state->dpll_hw_state));
8831
409ee761 8832 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8833
5dc5298b
PZ		 8834 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8835 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8836
190f68c5 8837 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8838 &has_reduced_clock, &reduced_clock);
190f68c5 8839 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8840 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8841 return -EINVAL;
79e53945 8842 }
f47709a9 8843 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8844 if (!crtc_state->clock_set) {
8845 crtc_state->dpll.n = clock.n;
8846 crtc_state->dpll.m1 = clock.m1;
8847 crtc_state->dpll.m2 = clock.m2;
8848 crtc_state->dpll.p1 = clock.p1;
8849 crtc_state->dpll.p2 = clock.p2;
f47709a9 8850 }
79e53945 8851
5dc5298b 8852 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8853 if (crtc_state->has_pch_encoder) {
8854 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8855 if (has_reduced_clock)
7429e9d4 8856 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8857
190f68c5 8858 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8859 &fp, &reduced_clock,
8860 has_reduced_clock ? &fp2 : NULL);
8861
190f68c5
ACO		 8862 crtc_state->dpll_hw_state.dpll = dpll;
8863 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8864 if (has_reduced_clock)
190f68c5 8865 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8866 else
190f68c5 8867 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8868
190f68c5 8869 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8870 if (pll == NULL) {
84f44ce7 8871 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8872 pipe_name(crtc->pipe));
4b645f14
JB		 8873 return -EINVAL;
8874 }
3fb37703 8875 }
79e53945 8876
ab585dea 8877 if (is_lvds && has_reduced_clock)
c7653199 8878 crtc->lowfreq_avail = true;
bcd644e0 8879 else
c7653199 8880 crtc->lowfreq_avail = false;
e2b78267 8881
c8f7a0db 8882 return 0;
79e53945
JB		 8883}
8884
eb14cb74
VS		 8885static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8886 struct intel_link_m_n *m_n)
8887{
8888 struct drm_device *dev = crtc->base.dev;
8889 struct drm_i915_private *dev_priv = dev->dev_private;
8890 enum pipe pipe = crtc->pipe;
8891
8892 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8893 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8894 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8895 & ~TU_SIZE_MASK;
8896 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8897 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8898 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8899}
8900
8901static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8902 enum transcoder transcoder,
b95af8be
VK		 8903 struct intel_link_m_n *m_n,
8904 struct intel_link_m_n *m2_n2)
72419203
DV		 8905{
8906 struct drm_device *dev = crtc->base.dev;
8907 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8908 enum pipe pipe = crtc->pipe;
72419203 8909
eb14cb74
VS		 8910 if (INTEL_INFO(dev)->gen >= 5) {
8911 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8912 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8913 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8914 & ~TU_SIZE_MASK;
8915 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8916 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8917 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8918 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8919 * gen < 8) and if DRRS is supported (to make sure the
8920 * registers are not unnecessarily read).
8921 */
8922 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8923 crtc->config->has_drrs) {
b95af8be
VK		 8924 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8925 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8926 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8927 & ~TU_SIZE_MASK;
8928 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8929 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8930 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8931 }
eb14cb74
VS		 8932 } else {
8933 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8934 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8935 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8936 & ~TU_SIZE_MASK;
8937 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8938 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8939 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8940 }
8941}
8942
8943void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8944 struct intel_crtc_state *pipe_config)
eb14cb74 8945{
681a8504 8946 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8947 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8948 else
8949 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8950 &pipe_config->dp_m_n,
8951 &pipe_config->dp_m2_n2);
eb14cb74 8952}
72419203 8953
eb14cb74 8954static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8955 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8956{
8957 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8958 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8959}
8960
bd2e244f 8961static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8962 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8963{
8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8966 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8967 uint32_t ps_ctrl = 0;
8968 int id = -1;
8969 int i;
bd2e244f 8970
a1b2278e
CK		 8971 /* find scaler attached to this pipe */
8972 for (i = 0; i < crtc->num_scalers; i++) {
8973 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8974 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8975 id = i;
8976 pipe_config->pch_pfit.enabled = true;
8977 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8978 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8979 break;
8980 }
8981 }
bd2e244f 8982
a1b2278e
CK		 8983 scaler_state->scaler_id = id;
8984 if (id >= 0) {
8985 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8986 } else {
8987 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8988 }
8989}
8990
5724dbd1
DL		 8991static void
8992skylake_get_initial_plane_config(struct intel_crtc *crtc,
8993 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8994{
8995 struct drm_device *dev = crtc->base.dev;
8996 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8997 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8998 int pipe = crtc->pipe;
8999 int fourcc, pixel_format;
6761dd31 9000 unsigned int aligned_height;
bc8d7dff 9001 struct drm_framebuffer *fb;
1b842c89 9002 struct intel_framebuffer *intel_fb;
bc8d7dff 9003
d9806c9f 9004 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9005 if (!intel_fb) {
bc8d7dff
DL		 9006 DRM_DEBUG_KMS("failed to alloc fb\n");
9007 return;
9008 }
9009
1b842c89
DL		 9010 fb = &intel_fb->base;
9011
bc8d7dff 9012 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9013 if (!(val & PLANE_CTL_ENABLE))
9014 goto error;
9015
bc8d7dff
DL		 9016 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9017 fourcc = skl_format_to_fourcc(pixel_format,
9018 val & PLANE_CTL_ORDER_RGBX,
9019 val & PLANE_CTL_ALPHA_MASK);
9020 fb->pixel_format = fourcc;
9021 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9022
40f46283
DL		 9023 tiling = val & PLANE_CTL_TILED_MASK;
9024 switch (tiling) {
9025 case PLANE_CTL_TILED_LINEAR:
9026 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9027 break;
9028 case PLANE_CTL_TILED_X:
9029 plane_config->tiling = I915_TILING_X;
9030 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9031 break;
9032 case PLANE_CTL_TILED_Y:
9033 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9034 break;
9035 case PLANE_CTL_TILED_YF:
9036 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9037 break;
9038 default:
9039 MISSING_CASE(tiling);
9040 goto error;
9041 }
9042
bc8d7dff
DL		 9043 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9044 plane_config->base = base;
9045
9046 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9047
9048 val = I915_READ(PLANE_SIZE(pipe, 0));
9049 fb->height = ((val >> 16) & 0xfff) + 1;
9050 fb->width = ((val >> 0) & 0x1fff) + 1;
9051
9052 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9053 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9054 fb->pixel_format);
bc8d7dff
DL		 9055 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9056
9057 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9058 fb->pixel_format,
9059 fb->modifier[0]);
bc8d7dff 9060
f37b5c2b 9061 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9062
9063 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9064 pipe_name(pipe), fb->width, fb->height,
9065 fb->bits_per_pixel, base, fb->pitches[0],
9066 plane_config->size);
9067
2d14030b 9068 plane_config->fb = intel_fb;
bc8d7dff
DL		 9069 return;
9070
9071error:
9072 kfree(fb);
9073}
9074
2fa2fe9a 9075static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9076 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9077{
9078 struct drm_device *dev = crtc->base.dev;
9079 struct drm_i915_private *dev_priv = dev->dev_private;
9080 uint32_t tmp;
9081
9082 tmp = I915_READ(PF_CTL(crtc->pipe));
9083
9084 if (tmp & PF_ENABLE) {
fd4daa9c 9085 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9086 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9087 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9088
9089 /* We currently do not free assignements of panel fitters on
9090 * ivb/hsw (since we don't use the higher upscaling modes which
9091 * differentiates them) so just WARN about this case for now. */
9092 if (IS_GEN7(dev)) {
9093 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9094 PF_PIPE_SEL_IVB(crtc->pipe));
9095 }
2fa2fe9a 9096 }
79e53945
JB		 9097}
9098
5724dbd1
DL		 9099static void
9100ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9101 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9102{
9103 struct drm_device *dev = crtc->base.dev;
9104 struct drm_i915_private *dev_priv = dev->dev_private;
9105 u32 val, base, offset;
aeee5a49 9106 int pipe = crtc->pipe;
4c6baa59 9107 int fourcc, pixel_format;
6761dd31 9108 unsigned int aligned_height;
b113d5ee 9109 struct drm_framebuffer *fb;
1b842c89 9110 struct intel_framebuffer *intel_fb;
4c6baa59 9111
42a7b088
DL		 9112 val = I915_READ(DSPCNTR(pipe));
9113 if (!(val & DISPLAY_PLANE_ENABLE))
9114 return;
9115
d9806c9f 9116 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9117 if (!intel_fb) {
4c6baa59
JB		 9118 DRM_DEBUG_KMS("failed to alloc fb\n");
9119 return;
9120 }
9121
1b842c89
DL		 9122 fb = &intel_fb->base;
9123
18c5247e
DV		 9124 if (INTEL_INFO(dev)->gen >= 4) {
9125 if (val & DISPPLANE_TILED) {
49af449b 9126 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9127 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9128 }
9129 }
4c6baa59
JB		 9130
9131 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9132 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9133 fb->pixel_format = fourcc;
9134 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9135
aeee5a49 9136 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9137 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9138 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9139 } else {
49af449b 9140 if (plane_config->tiling)
aeee5a49 9141 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9142 else
aeee5a49 9143 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9144 }
9145 plane_config->base = base;
9146
9147 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9148 fb->width = ((val >> 16) & 0xfff) + 1;
9149 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9150
9151 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9152 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9153
b113d5ee 9154 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9155 fb->pixel_format,
9156 fb->modifier[0]);
4c6baa59 9157
f37b5c2b 9158 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9159
2844a921
DL		 9160 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9161 pipe_name(pipe), fb->width, fb->height,
9162 fb->bits_per_pixel, base, fb->pitches[0],
9163 plane_config->size);
b113d5ee 9164
2d14030b 9165 plane_config->fb = intel_fb;
4c6baa59
JB		 9166}
9167
0e8ffe1b 9168static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9169 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9170{
9171 struct drm_device *dev = crtc->base.dev;
9172 struct drm_i915_private *dev_priv = dev->dev_private;
9173 uint32_t tmp;
9174
f458ebbc
DV		 9175 if (!intel_display_power_is_enabled(dev_priv,
9176 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9177 return false;
9178
e143a21c 9179 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9180 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9181
0e8ffe1b
DV		 9182 tmp = I915_READ(PIPECONF(crtc->pipe));
9183 if (!(tmp & PIPECONF_ENABLE))
9184 return false;
9185
42571aef
VS		 9186 switch (tmp & PIPECONF_BPC_MASK) {
9187 case PIPECONF_6BPC:
9188 pipe_config->pipe_bpp = 18;
9189 break;
9190 case PIPECONF_8BPC:
9191 pipe_config->pipe_bpp = 24;
9192 break;
9193 case PIPECONF_10BPC:
9194 pipe_config->pipe_bpp = 30;
9195 break;
9196 case PIPECONF_12BPC:
9197 pipe_config->pipe_bpp = 36;
9198 break;
9199 default:
9200 break;
9201 }
9202
b5a9fa09
DV		 9203 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9204 pipe_config->limited_color_range = true;
9205
ab9412ba 9206 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9207 struct intel_shared_dpll *pll;
9208
88adfff1
DV		 9209 pipe_config->has_pch_encoder = true;
9210
627eb5a3
DV		 9211 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9212 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9213 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9214
9215 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9216
c0d43d62 9217 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9218 pipe_config->shared_dpll =
9219 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9220 } else {
9221 tmp = I915_READ(PCH_DPLL_SEL);
9222 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9223 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9224 else
9225 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9226 }
66e985c0
DV		 9227
9228 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9229
9230 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9231 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9232
9233 tmp = pipe_config->dpll_hw_state.dpll;
9234 pipe_config->pixel_multiplier =
9235 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9236 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9237
9238 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9239 } else {
9240 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9241 }
9242
1bd1bd80
DV		 9243 intel_get_pipe_timings(crtc, pipe_config);
9244
2fa2fe9a
DV		 9245 ironlake_get_pfit_config(crtc, pipe_config);
9246
0e8ffe1b
DV		 9247 return true;
9248}
9249
be256dc7
PZ		 9250static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9251{
9252 struct drm_device *dev = dev_priv->dev;
be256dc7 9253 struct intel_crtc *crtc;
be256dc7 9254
d3fcc808 9255 for_each_intel_crtc(dev, crtc)
e2c719b7 9256 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9257 pipe_name(crtc->pipe));
9258
e2c719b7
RC		 9259 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9260 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS		 9261 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9262 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC		 9263 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9264 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9265 "CPU PWM1 enabled\n");
c5107b87 9266 if (IS_HASWELL(dev))
e2c719b7 9267 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9268 "CPU PWM2 enabled\n");
e2c719b7 9269 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9270 "PCH PWM1 enabled\n");
e2c719b7 9271 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9272 "Utility pin enabled\n");
e2c719b7 9273 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9274
9926ada1
PZ		 9275 /*
9276 * In theory we can still leave IRQs enabled, as long as only the HPD
9277 * interrupts remain enabled. We used to check for that, but since it's
9278 * gen-specific and since we only disable LCPLL after we fully disable
9279 * the interrupts, the check below should be enough.
9280 */
e2c719b7 9281 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9282}
9283
9ccd5aeb
PZ		 9284static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9285{
9286 struct drm_device *dev = dev_priv->dev;
9287
9288 if (IS_HASWELL(dev))
9289 return I915_READ(D_COMP_HSW);
9290 else
9291 return I915_READ(D_COMP_BDW);
9292}
9293
3c4c9b81
PZ		 9294static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9295{
9296 struct drm_device *dev = dev_priv->dev;
9297
9298 if (IS_HASWELL(dev)) {
9299 mutex_lock(&dev_priv->rps.hw_lock);
9300 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9301 val))
f475dadf 9302 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9303 mutex_unlock(&dev_priv->rps.hw_lock);
9304 } else {
9ccd5aeb
PZ		 9305 I915_WRITE(D_COMP_BDW, val);
9306 POSTING_READ(D_COMP_BDW);
3c4c9b81 9307 }
be256dc7
PZ		 9308}
9309
9310/*
9311 * This function implements pieces of two sequences from BSpec:
9312 * - Sequence for display software to disable LCPLL
9313 * - Sequence for display software to allow package C8+
9314 * The steps implemented here are just the steps that actually touch the LCPLL
9315 * register. Callers should take care of disabling all the display engine
9316 * functions, doing the mode unset, fixing interrupts, etc.
9317 */
6ff58d53
PZ		 9318static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9319 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9320{
9321 uint32_t val;
9322
9323 assert_can_disable_lcpll(dev_priv);
9324
9325 val = I915_READ(LCPLL_CTL);
9326
9327 if (switch_to_fclk) {
9328 val |= LCPLL_CD_SOURCE_FCLK;
9329 I915_WRITE(LCPLL_CTL, val);
9330
9331 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9332 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9333 DRM_ERROR("Switching to FCLK failed\n");
9334
9335 val = I915_READ(LCPLL_CTL);
9336 }
9337
9338 val |= LCPLL_PLL_DISABLE;
9339 I915_WRITE(LCPLL_CTL, val);
9340 POSTING_READ(LCPLL_CTL);
9341
9342 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9343 DRM_ERROR("LCPLL still locked\n");
9344
9ccd5aeb 9345 val = hsw_read_dcomp(dev_priv);
be256dc7 9346 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9347 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9348 ndelay(100);
9349
9ccd5aeb
PZ		 9350 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9351 1))
be256dc7
PZ		 9352 DRM_ERROR("D_COMP RCOMP still in progress\n");
9353
9354 if (allow_power_down) {
9355 val = I915_READ(LCPLL_CTL);
9356 val |= LCPLL_POWER_DOWN_ALLOW;
9357 I915_WRITE(LCPLL_CTL, val);
9358 POSTING_READ(LCPLL_CTL);
9359 }
9360}
9361
9362/*
9363 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9364 * source.
9365 */
6ff58d53 9366static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9367{
9368 uint32_t val;
9369
9370 val = I915_READ(LCPLL_CTL);
9371
9372 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9373 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9374 return;
9375
a8a8bd54
PZ		 9376 /*
9377 * Make sure we're not on PC8 state before disabling PC8, otherwise
9378 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9379 */
59bad947 9380 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9381
be256dc7
PZ		 9382 if (val & LCPLL_POWER_DOWN_ALLOW) {
9383 val &= ~LCPLL_POWER_DOWN_ALLOW;
9384 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9385 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9386 }
9387
9ccd5aeb 9388 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9389 val |= D_COMP_COMP_FORCE;
9390 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9391 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9392
9393 val = I915_READ(LCPLL_CTL);
9394 val &= ~LCPLL_PLL_DISABLE;
9395 I915_WRITE(LCPLL_CTL, val);
9396
9397 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9398 DRM_ERROR("LCPLL not locked yet\n");
9399
9400 if (val & LCPLL_CD_SOURCE_FCLK) {
9401 val = I915_READ(LCPLL_CTL);
9402 val &= ~LCPLL_CD_SOURCE_FCLK;
9403 I915_WRITE(LCPLL_CTL, val);
9404
9405 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9406 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9407 DRM_ERROR("Switching back to LCPLL failed\n");
9408 }
215733fa 9409
59bad947 9410 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9411 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9412}
9413
765dab67
PZ		 9414/*
9415 * Package states C8 and deeper are really deep PC states that can only be
9416 * reached when all the devices on the system allow it, so even if the graphics
9417 * device allows PC8+, it doesn't mean the system will actually get to these
9418 * states. Our driver only allows PC8+ when going into runtime PM.
9419 *
9420 * The requirements for PC8+ are that all the outputs are disabled, the power
9421 * well is disabled and most interrupts are disabled, and these are also
9422 * requirements for runtime PM. When these conditions are met, we manually do
9423 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9424 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9425 * hang the machine.
9426 *
9427 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9428 * the state of some registers, so when we come back from PC8+ we need to
9429 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9430 * need to take care of the registers kept by RC6. Notice that this happens even
9431 * if we don't put the device in PCI D3 state (which is what currently happens
9432 * because of the runtime PM support).
9433 *
9434 * For more, read "Display Sequences for Package C8" on the hardware
9435 * documentation.
9436 */
a14cb6fc 9437void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9438{
c67a470b
PZ		 9439 struct drm_device *dev = dev_priv->dev;
9440 uint32_t val;
9441
c67a470b
PZ		 9442 DRM_DEBUG_KMS("Enabling package C8+\n");
9443
c2699524 9444 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9445 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9446 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9447 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9448 }
9449
9450 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9451 hsw_disable_lcpll(dev_priv, true, true);
9452}
9453
a14cb6fc 9454void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9455{
9456 struct drm_device *dev = dev_priv->dev;
9457 uint32_t val;
9458
c67a470b
PZ		 9459 DRM_DEBUG_KMS("Disabling package C8+\n");
9460
9461 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9462 lpt_init_pch_refclk(dev);
9463
c2699524 9464 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9465 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9466 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9467 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9468 }
9469
9470 intel_prepare_ddi(dev);
c67a470b
PZ		 9471}
9472
27c329ed 9473static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9474{
a821fc46 9475 struct drm_device *dev = old_state->dev;
27c329ed 9476 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9477
27c329ed 9478 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9479}
9480
b432e5cf 9481/* compute the max rate for new configuration */
27c329ed 9482static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9483{
b432e5cf 9484 struct intel_crtc *intel_crtc;
27c329ed 9485 struct intel_crtc_state *crtc_state;
b432e5cf 9486 int max_pixel_rate = 0;
b432e5cf 9487
27c329ed
ML		 9488 for_each_intel_crtc(state->dev, intel_crtc) {
9489 int pixel_rate;
9490
9491 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9492 if (IS_ERR(crtc_state))
9493 return PTR_ERR(crtc_state);
9494
9495 if (!crtc_state->base.enable)
b432e5cf
VS		 9496 continue;
9497
27c329ed 9498 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9499
9500 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9501 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9502 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9503
9504 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9505 }
9506
9507 return max_pixel_rate;
9508}
9509
9510static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9511{
9512 struct drm_i915_private *dev_priv = dev->dev_private;
9513 uint32_t val, data;
9514 int ret;
9515
9516 if (WARN((I915_READ(LCPLL_CTL) &
9517 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9518 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9519 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9520 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9521 "trying to change cdclk frequency with cdclk not enabled\n"))
9522 return;
9523
9524 mutex_lock(&dev_priv->rps.hw_lock);
9525 ret = sandybridge_pcode_write(dev_priv,
9526 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9527 mutex_unlock(&dev_priv->rps.hw_lock);
9528 if (ret) {
9529 DRM_ERROR("failed to inform pcode about cdclk change\n");
9530 return;
9531 }
9532
9533 val = I915_READ(LCPLL_CTL);
9534 val |= LCPLL_CD_SOURCE_FCLK;
9535 I915_WRITE(LCPLL_CTL, val);
9536
9537 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9538 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9539 DRM_ERROR("Switching to FCLK failed\n");
9540
9541 val = I915_READ(LCPLL_CTL);
9542 val &= ~LCPLL_CLK_FREQ_MASK;
9543
9544 switch (cdclk) {
9545 case 450000:
9546 val |= LCPLL_CLK_FREQ_450;
9547 data = 0;
9548 break;
9549 case 540000:
9550 val |= LCPLL_CLK_FREQ_54O_BDW;
9551 data = 1;
9552 break;
9553 case 337500:
9554 val |= LCPLL_CLK_FREQ_337_5_BDW;
9555 data = 2;
9556 break;
9557 case 675000:
9558 val |= LCPLL_CLK_FREQ_675_BDW;
9559 data = 3;
9560 break;
9561 default:
9562 WARN(1, "invalid cdclk frequency\n");
9563 return;
9564 }
9565
9566 I915_WRITE(LCPLL_CTL, val);
9567
9568 val = I915_READ(LCPLL_CTL);
9569 val &= ~LCPLL_CD_SOURCE_FCLK;
9570 I915_WRITE(LCPLL_CTL, val);
9571
9572 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9573 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9574 DRM_ERROR("Switching back to LCPLL failed\n");
9575
9576 mutex_lock(&dev_priv->rps.hw_lock);
9577 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9578 mutex_unlock(&dev_priv->rps.hw_lock);
9579
9580 intel_update_cdclk(dev);
9581
9582 WARN(cdclk != dev_priv->cdclk_freq,
9583 "cdclk requested %d kHz but got %d kHz\n",
9584 cdclk, dev_priv->cdclk_freq);
9585}
9586
27c329ed 9587static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9588{
27c329ed
ML		 9589 struct drm_i915_private *dev_priv = to_i915(state->dev);
9590 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9591 int cdclk;
9592
9593 /*
9594 * FIXME should also account for plane ratio
9595 * once 64bpp pixel formats are supported.
9596 */
27c329ed 9597 if (max_pixclk > 540000)
b432e5cf 9598 cdclk = 675000;
27c329ed 9599 else if (max_pixclk > 450000)
b432e5cf 9600 cdclk = 540000;
27c329ed 9601 else if (max_pixclk > 337500)
b432e5cf
VS		 9602 cdclk = 450000;
9603 else
9604 cdclk = 337500;
9605
9606 /*
9607 * FIXME move the cdclk caclulation to
9608 * compute_config() so we can fail gracegully.
9609 */
9610 if (cdclk > dev_priv->max_cdclk_freq) {
9611 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9612 cdclk, dev_priv->max_cdclk_freq);
9613 cdclk = dev_priv->max_cdclk_freq;
9614 }
9615
27c329ed 9616 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9617
9618 return 0;
9619}
9620
27c329ed 9621static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9622{
27c329ed
ML		 9623 struct drm_device *dev = old_state->dev;
9624 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9625
27c329ed 9626 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9627}
9628
190f68c5
ACO		 9629static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9630 struct intel_crtc_state *crtc_state)
09b4ddf9 9631{
190f68c5 9632 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9633 return -EINVAL;
716c2e55 9634
c7653199 9635 crtc->lowfreq_avail = false;
644cef34 9636
c8f7a0db 9637 return 0;
79e53945
JB		 9638}
9639
3760b59c
S		 9640static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9641 enum port port,
9642 struct intel_crtc_state *pipe_config)
9643{
9644 switch (port) {
9645 case PORT_A:
9646 pipe_config->ddi_pll_sel = SKL_DPLL0;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9648 break;
9649 case PORT_B:
9650 pipe_config->ddi_pll_sel = SKL_DPLL1;
9651 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9652 break;
9653 case PORT_C:
9654 pipe_config->ddi_pll_sel = SKL_DPLL2;
9655 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9656 break;
9657 default:
9658 DRM_ERROR("Incorrect port type\n");
9659 }
9660}
9661
96b7dfb7
S		 9662static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9663 enum port port,
5cec258b 9664 struct intel_crtc_state *pipe_config)
96b7dfb7 9665{
3148ade7 9666 u32 temp, dpll_ctl1;
96b7dfb7
S		 9667
9668 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9669 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9670
9671 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9672 case SKL_DPLL0:
9673 /*
9674 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9675 * of the shared DPLL framework and thus needs to be read out
9676 * separately
9677 */
9678 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9679 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9680 break;
96b7dfb7
S		 9681 case SKL_DPLL1:
9682 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9683 break;
9684 case SKL_DPLL2:
9685 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9686 break;
9687 case SKL_DPLL3:
9688 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9689 break;
96b7dfb7
S		 9690 }
9691}
9692
7d2c8175
DL		 9693static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9694 enum port port,
5cec258b 9695 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9696{
9697 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9698
9699 switch (pipe_config->ddi_pll_sel) {
9700 case PORT_CLK_SEL_WRPLL1:
9701 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9702 break;
9703 case PORT_CLK_SEL_WRPLL2:
9704 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9705 break;
9706 }
9707}
9708
26804afd 9709static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9710 struct intel_crtc_state *pipe_config)
26804afd
DV		 9711{
9712 struct drm_device *dev = crtc->base.dev;
9713 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9714 struct intel_shared_dpll *pll;
26804afd
DV		 9715 enum port port;
9716 uint32_t tmp;
9717
9718 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9719
9720 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9721
ef11bdb3 9722 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 9723 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9724 else if (IS_BROXTON(dev))
9725 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9726 else
9727 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9728
d452c5b6
DV		 9729 if (pipe_config->shared_dpll >= 0) {
9730 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9731
9732 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9733 &pipe_config->dpll_hw_state));
9734 }
9735
26804afd
DV		 9736 /*
9737 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9738 * DDI E. So just check whether this pipe is wired to DDI E and whether
9739 * the PCH transcoder is on.
9740 */
ca370455
DL		 9741 if (INTEL_INFO(dev)->gen < 9 &&
9742 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9743 pipe_config->has_pch_encoder = true;
9744
9745 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9746 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9747 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9748
9749 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9750 }
9751}
9752
0e8ffe1b 9753static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9754 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9755{
9756 struct drm_device *dev = crtc->base.dev;
9757 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9758 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9759 uint32_t tmp;
9760
f458ebbc 9761 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9762 POWER_DOMAIN_PIPE(crtc->pipe)))
9763 return false;
9764
e143a21c 9765 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9766 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9767
eccb140b
DV		 9768 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9769 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9770 enum pipe trans_edp_pipe;
9771 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9772 default:
9773 WARN(1, "unknown pipe linked to edp transcoder\n");
9774 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9775 case TRANS_DDI_EDP_INPUT_A_ON:
9776 trans_edp_pipe = PIPE_A;
9777 break;
9778 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9779 trans_edp_pipe = PIPE_B;
9780 break;
9781 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9782 trans_edp_pipe = PIPE_C;
9783 break;
9784 }
9785
9786 if (trans_edp_pipe == crtc->pipe)
9787 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9788 }
9789
f458ebbc 9790 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9791 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9792 return false;
9793
eccb140b 9794 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9795 if (!(tmp & PIPECONF_ENABLE))
9796 return false;
9797
26804afd 9798 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9799
1bd1bd80
DV		 9800 intel_get_pipe_timings(crtc, pipe_config);
9801
a1b2278e
CK		 9802 if (INTEL_INFO(dev)->gen >= 9) {
9803 skl_init_scalers(dev, crtc, pipe_config);
9804 }
9805
2fa2fe9a 9806 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9807
9808 if (INTEL_INFO(dev)->gen >= 9) {
9809 pipe_config->scaler_state.scaler_id = -1;
9810 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9811 }
9812
bd2e244f 9813 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9814 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9815 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9816 else
1c132b44 9817 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9818 }
88adfff1 9819
e59150dc
JB		 9820 if (IS_HASWELL(dev))
9821 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9822 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9823
ebb69c95
CT		 9824 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9825 pipe_config->pixel_multiplier =
9826 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9827 } else {
9828 pipe_config->pixel_multiplier = 1;
9829 }
6c49f241 9830
0e8ffe1b
DV		 9831 return true;
9832}
9833
560b85bb
CW		 9834static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9835{
9836 struct drm_device *dev = crtc->dev;
9837 struct drm_i915_private *dev_priv = dev->dev_private;
9838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9839 uint32_t cntl = 0, size = 0;
560b85bb 9840
dc41c154 9841 if (base) {
3dd512fb
MR		 9842 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9843 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9844 unsigned int stride = roundup_pow_of_two(width) * 4;
9845
9846 switch (stride) {
9847 default:
9848 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9849 width, stride);
9850 stride = 256;
9851 /* fallthrough */
9852 case 256:
9853 case 512:
9854 case 1024:
9855 case 2048:
9856 break;
4b0e333e
CW		 9857 }
9858
dc41c154
VS		 9859 cntl |= CURSOR_ENABLE |
9860 CURSOR_GAMMA_ENABLE |
9861 CURSOR_FORMAT_ARGB |
9862 CURSOR_STRIDE(stride);
9863
9864 size = (height << 12) | width;
4b0e333e 9865 }
560b85bb 9866
dc41c154
VS		 9867 if (intel_crtc->cursor_cntl != 0 &&
9868 (intel_crtc->cursor_base != base ||
9869 intel_crtc->cursor_size != size ||
9870 intel_crtc->cursor_cntl != cntl)) {
9871 /* On these chipsets we can only modify the base/size/stride
9872 * whilst the cursor is disabled.
9873 */
0b87c24e
VS		 9874 I915_WRITE(CURCNTR(PIPE_A), 0);
9875 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9876 intel_crtc->cursor_cntl = 0;
4b0e333e 9877 }
560b85bb 9878
99d1f387 9879 if (intel_crtc->cursor_base != base) {
0b87c24e 9880 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9881 intel_crtc->cursor_base = base;
9882 }
4726e0b0 9883
dc41c154
VS		 9884 if (intel_crtc->cursor_size != size) {
9885 I915_WRITE(CURSIZE, size);
9886 intel_crtc->cursor_size = size;
4b0e333e 9887 }
560b85bb 9888
4b0e333e 9889 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9890 I915_WRITE(CURCNTR(PIPE_A), cntl);
9891 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9892 intel_crtc->cursor_cntl = cntl;
560b85bb 9893 }
560b85bb
CW		 9894}
9895
560b85bb 9896static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9897{
9898 struct drm_device *dev = crtc->dev;
9899 struct drm_i915_private *dev_priv = dev->dev_private;
9900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9901 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9902 uint32_t cntl;
9903
9904 cntl = 0;
9905 if (base) {
9906 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9907 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9908 case 64:
9909 cntl |= CURSOR_MODE_64_ARGB_AX;
9910 break;
9911 case 128:
9912 cntl |= CURSOR_MODE_128_ARGB_AX;
9913 break;
9914 case 256:
9915 cntl |= CURSOR_MODE_256_ARGB_AX;
9916 break;
9917 default:
3dd512fb 9918 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9919 return;
65a21cd6 9920 }
4b0e333e 9921 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 9922
fc6f93bc 9923 if (HAS_DDI(dev))
47bf17a7 9924 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9925 }
65a21cd6 9926
8e7d688b 9927 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9928 cntl |= CURSOR_ROTATE_180;
9929
4b0e333e
CW		 9930 if (intel_crtc->cursor_cntl != cntl) {
9931 I915_WRITE(CURCNTR(pipe), cntl);
9932 POSTING_READ(CURCNTR(pipe));
9933 intel_crtc->cursor_cntl = cntl;
65a21cd6 9934 }
4b0e333e 9935
65a21cd6 9936 /* and commit changes on next vblank */
5efb3e28
VS		 9937 I915_WRITE(CURBASE(pipe), base);
9938 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9939
9940 intel_crtc->cursor_base = base;
65a21cd6
JB		 9941}
9942
cda4b7d3 9943/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9944static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9945 bool on)
cda4b7d3
CW		 9946{
9947 struct drm_device *dev = crtc->dev;
9948 struct drm_i915_private *dev_priv = dev->dev_private;
9949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9950 int pipe = intel_crtc->pipe;
9b4101be
ML		 9951 struct drm_plane_state *cursor_state = crtc->cursor->state;
9952 int x = cursor_state->crtc_x;
9953 int y = cursor_state->crtc_y;
d6e4db15 9954 u32 base = 0, pos = 0;
cda4b7d3 9955
d6e4db15 9956 if (on)
cda4b7d3 9957 base = intel_crtc->cursor_addr;
cda4b7d3 9958
6e3c9717 9959 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9960 base = 0;
9961
6e3c9717 9962 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9963 base = 0;
9964
9965 if (x < 0) {
9b4101be 9966 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9967 base = 0;
9968
9969 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9970 x = -x;
9971 }
9972 pos |= x << CURSOR_X_SHIFT;
9973
9974 if (y < 0) {
9b4101be 9975 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9976 base = 0;
9977
9978 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9979 y = -y;
9980 }
9981 pos |= y << CURSOR_Y_SHIFT;
9982
4b0e333e 9983 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9984 return;
9985
5efb3e28
VS		 9986 I915_WRITE(CURPOS(pipe), pos);
9987
4398ad45
VS		 9988 /* ILK+ do this automagically */
9989 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9990 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 9991 base += (cursor_state->crtc_h *
9992 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 9993 }
9994
8ac54669 9995 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9996 i845_update_cursor(crtc, base);
9997 else
9998 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9999}
10000
dc41c154
VS		 10001static bool cursor_size_ok(struct drm_device *dev,
10002 uint32_t width, uint32_t height)
10003{
10004 if (width == 0 || height == 0)
10005 return false;
10006
10007 /*
10008 * 845g/865g are special in that they are only limited by
10009 * the width of their cursors, the height is arbitrary up to
10010 * the precision of the register. Everything else requires
10011 * square cursors, limited to a few power-of-two sizes.
10012 */
10013 if (IS_845G(dev) || IS_I865G(dev)) {
10014 if ((width & 63) != 0)
10015 return false;
10016
10017 if (width > (IS_845G(dev) ? 64 : 512))
10018 return false;
10019
10020 if (height > 1023)
10021 return false;
10022 } else {
10023 switch (width | height) {
10024 case 256:
10025 case 128:
10026 if (IS_GEN2(dev))
10027 return false;
10028 case 64:
10029 break;
10030 default:
10031 return false;
10032 }
10033 }
10034
10035 return true;
10036}
10037
79e53945 10038static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10039 u16 *blue, uint32_t start, uint32_t size)
79e53945 10040{
7203425a 10041 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10043
7203425a 10044 for (i = start; i < end; i++) {
79e53945
JB		 10045 intel_crtc->lut_r[i] = red[i] >> 8;
10046 intel_crtc->lut_g[i] = green[i] >> 8;
10047 intel_crtc->lut_b[i] = blue[i] >> 8;
10048 }
10049
10050 intel_crtc_load_lut(crtc);
10051}
10052
79e53945
JB		 10053/* VESA 640x480x72Hz mode to set on the pipe */
10054static struct drm_display_mode load_detect_mode = {
10055 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10056 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10057};
10058
a8bb6818
DV		 10059struct drm_framebuffer *
10060__intel_framebuffer_create(struct drm_device *dev,
10061 struct drm_mode_fb_cmd2 *mode_cmd,
10062 struct drm_i915_gem_object *obj)
d2dff872
CW		 10063{
10064 struct intel_framebuffer *intel_fb;
10065 int ret;
10066
10067 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10068 if (!intel_fb) {
6ccb81f2 10069 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10070 return ERR_PTR(-ENOMEM);
10071 }
10072
10073 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10074 if (ret)
10075 goto err;
d2dff872
CW		 10076
10077 return &intel_fb->base;
dd4916c5 10078err:
6ccb81f2 10079 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10080 kfree(intel_fb);
10081
10082 return ERR_PTR(ret);
d2dff872
CW		 10083}
10084
b5ea642a 10085static struct drm_framebuffer *
a8bb6818
DV		 10086intel_framebuffer_create(struct drm_device *dev,
10087 struct drm_mode_fb_cmd2 *mode_cmd,
10088 struct drm_i915_gem_object *obj)
10089{
10090 struct drm_framebuffer *fb;
10091 int ret;
10092
10093 ret = i915_mutex_lock_interruptible(dev);
10094 if (ret)
10095 return ERR_PTR(ret);
10096 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10097 mutex_unlock(&dev->struct_mutex);
10098
10099 return fb;
10100}
10101
d2dff872
CW		 10102static u32
10103intel_framebuffer_pitch_for_width(int width, int bpp)
10104{
10105 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10106 return ALIGN(pitch, 64);
10107}
10108
10109static u32
10110intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10111{
10112 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10113 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10114}
10115
10116static struct drm_framebuffer *
10117intel_framebuffer_create_for_mode(struct drm_device *dev,
10118 struct drm_display_mode *mode,
10119 int depth, int bpp)
10120{
10121 struct drm_i915_gem_object *obj;
0fed39bd 10122 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10123
10124 obj = i915_gem_alloc_object(dev,
10125 intel_framebuffer_size_for_mode(mode, bpp));
10126 if (obj == NULL)
10127 return ERR_PTR(-ENOMEM);
10128
10129 mode_cmd.width = mode->hdisplay;
10130 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10131 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10132 bpp);
5ca0c34a 10133 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10134
10135 return intel_framebuffer_create(dev, &mode_cmd, obj);
10136}
10137
10138static struct drm_framebuffer *
10139mode_fits_in_fbdev(struct drm_device *dev,
10140 struct drm_display_mode *mode)
10141{
0695726e 10142#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10143 struct drm_i915_private *dev_priv = dev->dev_private;
10144 struct drm_i915_gem_object *obj;
10145 struct drm_framebuffer *fb;
10146
4c0e5528 10147 if (!dev_priv->fbdev)
d2dff872
CW		 10148 return NULL;
10149
4c0e5528 10150 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10151 return NULL;
10152
4c0e5528
DV		 10153 obj = dev_priv->fbdev->fb->obj;
10154 BUG_ON(!obj);
10155
8bcd4553 10156 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10157 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10158 fb->bits_per_pixel))
d2dff872
CW		 10159 return NULL;
10160
01f2c773 10161 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10162 return NULL;
10163
10164 return fb;
4520f53a
DV		 10165#else
10166 return NULL;
10167#endif
d2dff872
CW		 10168}
10169
d3a40d1b
ACO		 10170static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10171 struct drm_crtc *crtc,
10172 struct drm_display_mode *mode,
10173 struct drm_framebuffer *fb,
10174 int x, int y)
10175{
10176 struct drm_plane_state *plane_state;
10177 int hdisplay, vdisplay;
10178 int ret;
10179
10180 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10181 if (IS_ERR(plane_state))
10182 return PTR_ERR(plane_state);
10183
10184 if (mode)
10185 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10186 else
10187 hdisplay = vdisplay = 0;
10188
10189 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10190 if (ret)
10191 return ret;
10192 drm_atomic_set_fb_for_plane(plane_state, fb);
10193 plane_state->crtc_x = 0;
10194 plane_state->crtc_y = 0;
10195 plane_state->crtc_w = hdisplay;
10196 plane_state->crtc_h = vdisplay;
10197 plane_state->src_x = x << 16;
10198 plane_state->src_y = y << 16;
10199 plane_state->src_w = hdisplay << 16;
10200 plane_state->src_h = vdisplay << 16;
10201
10202 return 0;
10203}
10204
d2434ab7 10205bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10206 struct drm_display_mode *mode,
51fd371b
RC		 10207 struct intel_load_detect_pipe *old,
10208 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10209{
10210 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10211 struct intel_encoder *intel_encoder =
10212 intel_attached_encoder(connector);
79e53945 10213 struct drm_crtc *possible_crtc;
4ef69c7a 10214 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10215 struct drm_crtc *crtc = NULL;
10216 struct drm_device *dev = encoder->dev;
94352cf9 10217 struct drm_framebuffer *fb;
51fd371b 10218 struct drm_mode_config *config = &dev->mode_config;
83a57153 10219 struct drm_atomic_state *state = NULL;
944b0c76 10220 struct drm_connector_state *connector_state;
4be07317 10221 struct intel_crtc_state *crtc_state;
51fd371b 10222 int ret, i = -1;
79e53945 10223
d2dff872 10224 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10225 connector->base.id, connector->name,
8e329a03 10226 encoder->base.id, encoder->name);
d2dff872 10227
51fd371b
RC		 10228retry:
10229 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10230 if (ret)
ad3c558f 10231 goto fail;
6e9f798d 10232
79e53945
JB		 10233 /*
10234 * Algorithm gets a little messy:
7a5e4805 10235 *
79e53945
JB		 10236 * - if the connector already has an assigned crtc, use it (but make
10237 * sure it's on first)
7a5e4805 10238 *
79e53945
JB		 10239 * - try to find the first unused crtc that can drive this connector,
10240 * and use that if we find one
79e53945
JB		 10241 */
10242
10243 /* See if we already have a CRTC for this connector */
10244 if (encoder->crtc) {
10245 crtc = encoder->crtc;
8261b191 10246
51fd371b 10247 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10248 if (ret)
ad3c558f 10249 goto fail;
4d02e2de 10250 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10251 if (ret)
ad3c558f 10252 goto fail;
7b24056b 10253
24218aac 10254 old->dpms_mode = connector->dpms;
8261b191
CW		 10255 old->load_detect_temp = false;
10256
10257 /* Make sure the crtc and connector are running */
24218aac
DV		 10258 if (connector->dpms != DRM_MODE_DPMS_ON)
10259 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10260
7173188d 10261 return true;
79e53945
JB		 10262 }
10263
10264 /* Find an unused one (if possible) */
70e1e0ec 10265 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10266 i++;
10267 if (!(encoder->possible_crtcs & (1 << i)))
10268 continue;
83d65738 10269 if (possible_crtc->state->enable)
a459249c 10270 continue;
a459249c
VS		 10271
10272 crtc = possible_crtc;
10273 break;
79e53945
JB		 10274 }
10275
10276 /*
10277 * If we didn't find an unused CRTC, don't use any.
10278 */
10279 if (!crtc) {
7173188d 10280 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10281 goto fail;
79e53945
JB		 10282 }
10283
51fd371b
RC		 10284 ret = drm_modeset_lock(&crtc->mutex, ctx);
10285 if (ret)
ad3c558f 10286 goto fail;
4d02e2de
DV		 10287 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10288 if (ret)
ad3c558f 10289 goto fail;
79e53945
JB		 10290
10291 intel_crtc = to_intel_crtc(crtc);
24218aac 10292 old->dpms_mode = connector->dpms;
8261b191 10293 old->load_detect_temp = true;
d2dff872 10294 old->release_fb = NULL;
79e53945 10295
83a57153
ACO		 10296 state = drm_atomic_state_alloc(dev);
10297 if (!state)
10298 return false;
10299
10300 state->acquire_ctx = ctx;
10301
944b0c76
ACO		 10302 connector_state = drm_atomic_get_connector_state(state, connector);
10303 if (IS_ERR(connector_state)) {
10304 ret = PTR_ERR(connector_state);
10305 goto fail;
10306 }
10307
10308 connector_state->crtc = crtc;
10309 connector_state->best_encoder = &intel_encoder->base;
10310
4be07317
ACO		 10311 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10312 if (IS_ERR(crtc_state)) {
10313 ret = PTR_ERR(crtc_state);
10314 goto fail;
10315 }
10316
49d6fa21 10317 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10318
6492711d
CW		 10319 if (!mode)
10320 mode = &load_detect_mode;
79e53945 10321
d2dff872
CW		 10322 /* We need a framebuffer large enough to accommodate all accesses
10323 * that the plane may generate whilst we perform load detection.
10324 * We can not rely on the fbcon either being present (we get called
10325 * during its initialisation to detect all boot displays, or it may
10326 * not even exist) or that it is large enough to satisfy the
10327 * requested mode.
10328 */
94352cf9
DV		 10329 fb = mode_fits_in_fbdev(dev, mode);
10330 if (fb == NULL) {
d2dff872 10331 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10332 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10333 old->release_fb = fb;
d2dff872
CW		 10334 } else
10335 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10336 if (IS_ERR(fb)) {
d2dff872 10337 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10338 goto fail;
79e53945 10339 }
79e53945 10340
d3a40d1b
ACO		 10341 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10342 if (ret)
10343 goto fail;
10344
8c7b5ccb
ACO		 10345 drm_mode_copy(&crtc_state->base.mode, mode);
10346
74c090b1 10347 if (drm_atomic_commit(state)) {
6492711d 10348 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10349 if (old->release_fb)
10350 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10351 goto fail;
79e53945 10352 }
9128b040 10353 crtc->primary->crtc = crtc;
7173188d 10354
79e53945 10355 /* let the connector get through one full cycle before testing */
9d0498a2 10356 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10357 return true;
412b61d8 10358
ad3c558f 10359fail:
e5d958ef
ACO		 10360 drm_atomic_state_free(state);
10361 state = NULL;
83a57153 10362
51fd371b
RC		 10363 if (ret == -EDEADLK) {
10364 drm_modeset_backoff(ctx);
10365 goto retry;
10366 }
10367
412b61d8 10368 return false;
79e53945
JB		 10369}
10370
d2434ab7 10371void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10372 struct intel_load_detect_pipe *old,
10373 struct drm_modeset_acquire_ctx *ctx)
79e53945 10374{
83a57153 10375 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10376 struct intel_encoder *intel_encoder =
10377 intel_attached_encoder(connector);
4ef69c7a 10378 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10379 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10381 struct drm_atomic_state *state;
944b0c76 10382 struct drm_connector_state *connector_state;
4be07317 10383 struct intel_crtc_state *crtc_state;
d3a40d1b 10384 int ret;
79e53945 10385
d2dff872 10386 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10387 connector->base.id, connector->name,
8e329a03 10388 encoder->base.id, encoder->name);
d2dff872 10389
8261b191 10390 if (old->load_detect_temp) {
83a57153 10391 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10392 if (!state)
10393 goto fail;
83a57153
ACO		 10394
10395 state->acquire_ctx = ctx;
10396
944b0c76
ACO		 10397 connector_state = drm_atomic_get_connector_state(state, connector);
10398 if (IS_ERR(connector_state))
10399 goto fail;
10400
4be07317
ACO		 10401 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10402 if (IS_ERR(crtc_state))
10403 goto fail;
10404
944b0c76
ACO		 10405 connector_state->best_encoder = NULL;
10406 connector_state->crtc = NULL;
10407
49d6fa21 10408 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10409
d3a40d1b
ACO		 10410 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10411 0, 0);
10412 if (ret)
10413 goto fail;
10414
74c090b1 10415 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10416 if (ret)
10417 goto fail;
d2dff872 10418
36206361
DV		 10419 if (old->release_fb) {
10420 drm_framebuffer_unregister_private(old->release_fb);
10421 drm_framebuffer_unreference(old->release_fb);
10422 }
d2dff872 10423
0622a53c 10424 return;
79e53945
JB		 10425 }
10426
c751ce4f 10427 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10428 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10429 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10430
10431 return;
10432fail:
10433 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10434 drm_atomic_state_free(state);
79e53945
JB		 10435}
10436
da4a1efa 10437static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10438 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10439{
10440 struct drm_i915_private *dev_priv = dev->dev_private;
10441 u32 dpll = pipe_config->dpll_hw_state.dpll;
10442
10443 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10444 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10445 else if (HAS_PCH_SPLIT(dev))
10446 return 120000;
10447 else if (!IS_GEN2(dev))
10448 return 96000;
10449 else
10450 return 48000;
10451}
10452
79e53945 10453/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10454static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10455 struct intel_crtc_state *pipe_config)
79e53945 10456{
f1f644dc 10457 struct drm_device *dev = crtc->base.dev;
79e53945 10458 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10459 int pipe = pipe_config->cpu_transcoder;
293623f7 10460 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10461 u32 fp;
10462 intel_clock_t clock;
dccbea3b 10463 int port_clock;
da4a1efa 10464 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10465
10466 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10467 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10468 else
293623f7 10469 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10470
10471 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10472 if (IS_PINEVIEW(dev)) {
10473 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10474 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10475 } else {
10476 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10477 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10478 }
10479
a6c45cf0 10480 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10481 if (IS_PINEVIEW(dev))
10482 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10483 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10484 else
10485 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10486 DPLL_FPA01_P1_POST_DIV_SHIFT);
10487
10488 switch (dpll & DPLL_MODE_MASK) {
10489 case DPLLB_MODE_DAC_SERIAL:
10490 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10491 5 : 10;
10492 break;
10493 case DPLLB_MODE_LVDS:
10494 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10495 7 : 14;
10496 break;
10497 default:
28c97730 10498 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10499 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10500 return;
79e53945
JB		 10501 }
10502
ac58c3f0 10503 if (IS_PINEVIEW(dev))
dccbea3b 10504 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10505 else
dccbea3b 10506 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10507 } else {
0fb58223 10508 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10509 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10510
10511 if (is_lvds) {
10512 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10513 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10514
10515 if (lvds & LVDS_CLKB_POWER_UP)
10516 clock.p2 = 7;
10517 else
10518 clock.p2 = 14;
79e53945
JB		 10519 } else {
10520 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10521 clock.p1 = 2;
10522 else {
10523 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10524 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10525 }
10526 if (dpll & PLL_P2_DIVIDE_BY_4)
10527 clock.p2 = 4;
10528 else
10529 clock.p2 = 2;
79e53945 10530 }
da4a1efa 10531
dccbea3b 10532 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10533 }
10534
18442d08
VS		 10535 /*
10536 * This value includes pixel_multiplier. We will use
241bfc38 10537 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10538 * encoder's get_config() function.
10539 */
dccbea3b 10540 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10541}
10542
6878da05
VS		 10543int intel_dotclock_calculate(int link_freq,
10544 const struct intel_link_m_n *m_n)
f1f644dc 10545{
f1f644dc
JB		 10546 /*
10547 * The calculation for the data clock is:
1041a02f 10548 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10549 * But we want to avoid losing precison if possible, so:
1041a02f 10550 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10551 *
10552 * and the link clock is simpler:
1041a02f 10553 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10554 */
10555
6878da05
VS		 10556 if (!m_n->link_n)
10557 return 0;
f1f644dc 10558
6878da05
VS		 10559 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10560}
f1f644dc 10561
18442d08 10562static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10563 struct intel_crtc_state *pipe_config)
6878da05
VS		 10564{
10565 struct drm_device *dev = crtc->base.dev;
79e53945 10566
18442d08
VS		 10567 /* read out port_clock from the DPLL */
10568 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10569
f1f644dc 10570 /*
18442d08 10571 * This value does not include pixel_multiplier.
241bfc38 10572 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10573 * agree once we know their relationship in the encoder's
10574 * get_config() function.
79e53945 10575 */
2d112de7 10576 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10577 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10578 &pipe_config->fdi_m_n);
79e53945
JB		 10579}
10580
10581/** Returns the currently programmed mode of the given pipe. */
10582struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10583 struct drm_crtc *crtc)
10584{
548f245b 10585 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10587 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10588 struct drm_display_mode *mode;
5cec258b 10589 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10590 int htot = I915_READ(HTOTAL(cpu_transcoder));
10591 int hsync = I915_READ(HSYNC(cpu_transcoder));
10592 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10593 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10594 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10595
10596 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10597 if (!mode)
10598 return NULL;
10599
f1f644dc
JB		 10600 /*
10601 * Construct a pipe_config sufficient for getting the clock info
10602 * back out of crtc_clock_get.
10603 *
10604 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10605 * to use a real value here instead.
10606 */
293623f7 10607 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10608 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10609 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10610 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10611 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10612 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10613
773ae034 10614 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10615 mode->hdisplay = (htot & 0xffff) + 1;
10616 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10617 mode->hsync_start = (hsync & 0xffff) + 1;
10618 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10619 mode->vdisplay = (vtot & 0xffff) + 1;
10620 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10621 mode->vsync_start = (vsync & 0xffff) + 1;
10622 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10623
10624 drm_mode_set_name(mode);
79e53945
JB		 10625
10626 return mode;
10627}
10628
f047e395
CW		 10629void intel_mark_busy(struct drm_device *dev)
10630{
c67a470b
PZ		 10631 struct drm_i915_private *dev_priv = dev->dev_private;
10632
f62a0076
CW		 10633 if (dev_priv->mm.busy)
10634 return;
10635
43694d69 10636 intel_runtime_pm_get(dev_priv);
c67a470b 10637 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10638 if (INTEL_INFO(dev)->gen >= 6)
10639 gen6_rps_busy(dev_priv);
f62a0076 10640 dev_priv->mm.busy = true;
f047e395
CW		 10641}
10642
10643void intel_mark_idle(struct drm_device *dev)
652c393a 10644{
c67a470b 10645 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10646
f62a0076
CW		 10647 if (!dev_priv->mm.busy)
10648 return;
10649
10650 dev_priv->mm.busy = false;
10651
3d13ef2e 10652 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10653 gen6_rps_idle(dev->dev_private);
bb4cdd53 10654
43694d69 10655 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10656}
10657
79e53945
JB		 10658static void intel_crtc_destroy(struct drm_crtc *crtc)
10659{
10660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10661 struct drm_device *dev = crtc->dev;
10662 struct intel_unpin_work *work;
67e77c5a 10663
5e2d7afc 10664 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10665 work = intel_crtc->unpin_work;
10666 intel_crtc->unpin_work = NULL;
5e2d7afc 10667 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10668
10669 if (work) {
10670 cancel_work_sync(&work->work);
10671 kfree(work);
10672 }
79e53945
JB		 10673
10674 drm_crtc_cleanup(crtc);
67e77c5a 10675
79e53945
JB		 10676 kfree(intel_crtc);
10677}
10678
6b95a207
KH		 10679static void intel_unpin_work_fn(struct work_struct *__work)
10680{
10681 struct intel_unpin_work *work =
10682 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10683 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10684 struct drm_device *dev = crtc->base.dev;
10685 struct drm_plane *primary = crtc->base.primary;
6b95a207 10686
b4a98e57 10687 mutex_lock(&dev->struct_mutex);
a9ff8714 10688 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10689 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10690
f06cc1b9 10691 if (work->flip_queued_req)
146d84f0 10692 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10693 mutex_unlock(&dev->struct_mutex);
10694
a9ff8714 10695 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10696 drm_framebuffer_unreference(work->old_fb);
f99d7069 10697
a9ff8714
VS		 10698 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10699 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10700
6b95a207
KH		 10701 kfree(work);
10702}
10703
1afe3e9d 10704static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10705 struct drm_crtc *crtc)
6b95a207 10706{
6b95a207
KH		 10707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10708 struct intel_unpin_work *work;
6b95a207
KH		 10709 unsigned long flags;
10710
10711 /* Ignore early vblank irqs */
10712 if (intel_crtc == NULL)
10713 return;
10714
f326038a
DV		 10715 /*
10716 * This is called both by irq handlers and the reset code (to complete
10717 * lost pageflips) so needs the full irqsave spinlocks.
10718 */
6b95a207
KH		 10719 spin_lock_irqsave(&dev->event_lock, flags);
10720 work = intel_crtc->unpin_work;
e7d841ca
CW		 10721
10722 /* Ensure we don't miss a work->pending update ... */
10723 smp_rmb();
10724
10725 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10726 spin_unlock_irqrestore(&dev->event_lock, flags);
10727 return;
10728 }
10729
d6bbafa1 10730 page_flip_completed(intel_crtc);
0af7e4df 10731
6b95a207 10732 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10733}
10734
1afe3e9d
JB		 10735void intel_finish_page_flip(struct drm_device *dev, int pipe)
10736{
fbee40df 10737 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10738 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10739
49b14a5c 10740 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10741}
10742
10743void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10744{
fbee40df 10745 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10746 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10747
49b14a5c 10748 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10749}
10750
75f7f3ec
VS		 10751/* Is 'a' after or equal to 'b'? */
10752static bool g4x_flip_count_after_eq(u32 a, u32 b)
10753{
10754 return !((a - b) & 0x80000000);
10755}
10756
10757static bool page_flip_finished(struct intel_crtc *crtc)
10758{
10759 struct drm_device *dev = crtc->base.dev;
10760 struct drm_i915_private *dev_priv = dev->dev_private;
10761
bdfa7542
VS		 10762 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10763 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10764 return true;
10765
75f7f3ec
VS		 10766 /*
10767 * The relevant registers doen't exist on pre-ctg.
10768 * As the flip done interrupt doesn't trigger for mmio
10769 * flips on gmch platforms, a flip count check isn't
10770 * really needed there. But since ctg has the registers,
10771 * include it in the check anyway.
10772 */
10773 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10774 return true;
10775
10776 /*
10777 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10778 * used the same base address. In that case the mmio flip might
10779 * have completed, but the CS hasn't even executed the flip yet.
10780 *
10781 * A flip count check isn't enough as the CS might have updated
10782 * the base address just after start of vblank, but before we
10783 * managed to process the interrupt. This means we'd complete the
10784 * CS flip too soon.
10785 *
10786 * Combining both checks should get us a good enough result. It may
10787 * still happen that the CS flip has been executed, but has not
10788 * yet actually completed. But in case the base address is the same
10789 * anyway, we don't really care.
10790 */
10791 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10792 crtc->unpin_work->gtt_offset &&
fd8f507c 10793 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
75f7f3ec
VS		 10794 crtc->unpin_work->flip_count);
10795}
10796
6b95a207
KH		 10797void intel_prepare_page_flip(struct drm_device *dev, int plane)
10798{
fbee40df 10799 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10800 struct intel_crtc *intel_crtc =
10801 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10802 unsigned long flags;
10803
f326038a
DV		 10804
10805 /*
10806 * This is called both by irq handlers and the reset code (to complete
10807 * lost pageflips) so needs the full irqsave spinlocks.
10808 *
10809 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10810 * generate a page-flip completion irq, i.e. every modeset
10811 * is also accompanied by a spurious intel_prepare_page_flip().
10812 */
6b95a207 10813 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10814 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10815 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10816 spin_unlock_irqrestore(&dev->event_lock, flags);
10817}
10818
6042639c 10819static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
e7d841ca
CW		 10820{
10821 /* Ensure that the work item is consistent when activating it ... */
10822 smp_wmb();
6042639c 10823 atomic_set(&work->pending, INTEL_FLIP_PENDING);
e7d841ca
CW		 10824 /* and that it is marked active as soon as the irq could fire. */
10825 smp_wmb();
10826}
10827
8c9f3aaf
JB		 10828static int intel_gen2_queue_flip(struct drm_device *dev,
10829 struct drm_crtc *crtc,
10830 struct drm_framebuffer *fb,
ed8d1975 10831 struct drm_i915_gem_object *obj,
6258fbe2 10832 struct drm_i915_gem_request *req,
ed8d1975 10833 uint32_t flags)
8c9f3aaf 10834{
6258fbe2 10835 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10837 u32 flip_mask;
10838 int ret;
10839
5fb9de1a 10840 ret = intel_ring_begin(req, 6);
8c9f3aaf 10841 if (ret)
4fa62c89 10842 return ret;
8c9f3aaf
JB		 10843
10844 /* Can't queue multiple flips, so wait for the previous
10845 * one to finish before executing the next.
10846 */
10847 if (intel_crtc->plane)
10848 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10849 else
10850 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10851 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10852 intel_ring_emit(ring, MI_NOOP);
10853 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10854 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10855 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10856 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10857 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca 10858
6042639c 10859 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10860 return 0;
8c9f3aaf
JB		 10861}
10862
10863static int intel_gen3_queue_flip(struct drm_device *dev,
10864 struct drm_crtc *crtc,
10865 struct drm_framebuffer *fb,
ed8d1975 10866 struct drm_i915_gem_object *obj,
6258fbe2 10867 struct drm_i915_gem_request *req,
ed8d1975 10868 uint32_t flags)
8c9f3aaf 10869{
6258fbe2 10870 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10872 u32 flip_mask;
10873 int ret;
10874
5fb9de1a 10875 ret = intel_ring_begin(req, 6);
8c9f3aaf 10876 if (ret)
4fa62c89 10877 return ret;
8c9f3aaf
JB		 10878
10879 if (intel_crtc->plane)
10880 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10881 else
10882 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10883 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10884 intel_ring_emit(ring, MI_NOOP);
10885 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10886 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10887 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10888 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10889 intel_ring_emit(ring, MI_NOOP);
10890
6042639c 10891 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10892 return 0;
8c9f3aaf
JB		 10893}
10894
10895static int intel_gen4_queue_flip(struct drm_device *dev,
10896 struct drm_crtc *crtc,
10897 struct drm_framebuffer *fb,
ed8d1975 10898 struct drm_i915_gem_object *obj,
6258fbe2 10899 struct drm_i915_gem_request *req,
ed8d1975 10900 uint32_t flags)
8c9f3aaf 10901{
6258fbe2 10902 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10903 struct drm_i915_private *dev_priv = dev->dev_private;
10904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10905 uint32_t pf, pipesrc;
10906 int ret;
10907
5fb9de1a 10908 ret = intel_ring_begin(req, 4);
8c9f3aaf 10909 if (ret)
4fa62c89 10910 return ret;
8c9f3aaf
JB		 10911
10912 /* i965+ uses the linear or tiled offsets from the
10913 * Display Registers (which do not change across a page-flip)
10914 * so we need only reprogram the base address.
10915 */
6d90c952
DV		 10916 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10917 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10918 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10919 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10920 obj->tiling_mode);
8c9f3aaf
JB		 10921
10922 /* XXX Enabling the panel-fitter across page-flip is so far
10923 * untested on non-native modes, so ignore it for now.
10924 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10925 */
10926 pf = 0;
10927 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10928 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10929
6042639c 10930 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10931 return 0;
8c9f3aaf
JB		 10932}
10933
10934static int intel_gen6_queue_flip(struct drm_device *dev,
10935 struct drm_crtc *crtc,
10936 struct drm_framebuffer *fb,
ed8d1975 10937 struct drm_i915_gem_object *obj,
6258fbe2 10938 struct drm_i915_gem_request *req,
ed8d1975 10939 uint32_t flags)
8c9f3aaf 10940{
6258fbe2 10941 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10942 struct drm_i915_private *dev_priv = dev->dev_private;
10943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10944 uint32_t pf, pipesrc;
10945 int ret;
10946
5fb9de1a 10947 ret = intel_ring_begin(req, 4);
8c9f3aaf 10948 if (ret)
4fa62c89 10949 return ret;
8c9f3aaf 10950
6d90c952
DV		 10951 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10952 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10953 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10954 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10955
dc257cf1
DV		 10956 /* Contrary to the suggestions in the documentation,
10957 * "Enable Panel Fitter" does not seem to be required when page
10958 * flipping with a non-native mode, and worse causes a normal
10959 * modeset to fail.
10960 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10961 */
10962 pf = 0;
8c9f3aaf 10963 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10964 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10965
6042639c 10966 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10967 return 0;
8c9f3aaf
JB		 10968}
10969
7c9017e5
JB		 10970static int intel_gen7_queue_flip(struct drm_device *dev,
10971 struct drm_crtc *crtc,
10972 struct drm_framebuffer *fb,
ed8d1975 10973 struct drm_i915_gem_object *obj,
6258fbe2 10974 struct drm_i915_gem_request *req,
ed8d1975 10975 uint32_t flags)
7c9017e5 10976{
6258fbe2 10977 struct intel_engine_cs *ring = req->ring;
7c9017e5 10978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10979 uint32_t plane_bit = 0;
ffe74d75
CW		 10980 int len, ret;
10981
eba905b2 10982 switch (intel_crtc->plane) {
cb05d8de
DV		 10983 case PLANE_A:
10984 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10985 break;
10986 case PLANE_B:
10987 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10988 break;
10989 case PLANE_C:
10990 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10991 break;
10992 default:
10993 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10994 return -ENODEV;
cb05d8de
DV		 10995 }
10996
ffe74d75 10997 len = 4;
f476828a 10998 if (ring->id == RCS) {
ffe74d75 10999 len += 6;
f476828a
DL		 11000 /*
11001 * On Gen 8, SRM is now taking an extra dword to accommodate
11002 * 48bits addresses, and we need a NOOP for the batch size to
11003 * stay even.
11004 */
11005 if (IS_GEN8(dev))
11006 len += 2;
11007 }
ffe74d75 11008
f66fab8e
VS		 11009 /*
11010 * BSpec MI_DISPLAY_FLIP for IVB:
11011 * "The full packet must be contained within the same cache line."
11012 *
11013 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11014 * cacheline, if we ever start emitting more commands before
11015 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11016 * then do the cacheline alignment, and finally emit the
11017 * MI_DISPLAY_FLIP.
11018 */
bba09b12 11019 ret = intel_ring_cacheline_align(req);
f66fab8e 11020 if (ret)
4fa62c89 11021 return ret;
f66fab8e 11022
5fb9de1a 11023 ret = intel_ring_begin(req, len);
7c9017e5 11024 if (ret)
4fa62c89 11025 return ret;
7c9017e5 11026
ffe74d75
CW		 11027 /* Unmask the flip-done completion message. Note that the bspec says that
11028 * we should do this for both the BCS and RCS, and that we must not unmask
11029 * more than one flip event at any time (or ensure that one flip message
11030 * can be sent by waiting for flip-done prior to queueing new flips).
11031 * Experimentation says that BCS works despite DERRMR masking all
11032 * flip-done completion events and that unmasking all planes at once
11033 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11034 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11035 */
11036 if (ring->id == RCS) {
11037 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11038 intel_ring_emit(ring, DERRMR);
11039 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11040 DERRMR_PIPEB_PRI_FLIP_DONE |
11041 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11042 if (IS_GEN8(dev))
f1afe24f 11043 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11044 MI_SRM_LRM_GLOBAL_GTT);
11045 else
f1afe24f 11046 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11047 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11048 intel_ring_emit(ring, DERRMR);
11049 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11050 if (IS_GEN8(dev)) {
11051 intel_ring_emit(ring, 0);
11052 intel_ring_emit(ring, MI_NOOP);
11053 }
ffe74d75
CW		 11054 }
11055
cb05d8de 11056 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11057 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11058 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11059 intel_ring_emit(ring, (MI_NOOP));
e7d841ca 11060
6042639c 11061 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11062 return 0;
7c9017e5
JB		 11063}
11064
84c33a64
SG		 11065static bool use_mmio_flip(struct intel_engine_cs *ring,
11066 struct drm_i915_gem_object *obj)
11067{
11068 /*
11069 * This is not being used for older platforms, because
11070 * non-availability of flip done interrupt forces us to use
11071 * CS flips. Older platforms derive flip done using some clever
11072 * tricks involving the flip_pending status bits and vblank irqs.
11073 * So using MMIO flips there would disrupt this mechanism.
11074 */
11075
8e09bf83
CW		 11076 if (ring == NULL)
11077 return true;
11078
84c33a64
SG		 11079 if (INTEL_INFO(ring->dev)->gen < 5)
11080 return false;
11081
11082 if (i915.use_mmio_flip < 0)
11083 return false;
11084 else if (i915.use_mmio_flip > 0)
11085 return true;
14bf993e
OM		 11086 else if (i915.enable_execlists)
11087 return true;
84c33a64 11088 else
b4716185 11089 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11090}
11091
6042639c 11092static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
86efe24a 11093 unsigned int rotation,
6042639c 11094 struct intel_unpin_work *work)
ff944564
DL		 11095{
11096 struct drm_device *dev = intel_crtc->base.dev;
11097 struct drm_i915_private *dev_priv = dev->dev_private;
11098 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564 11099 const enum pipe pipe = intel_crtc->pipe;
86efe24a 11100 u32 ctl, stride, tile_height;
ff944564
DL		 11101
11102 ctl = I915_READ(PLANE_CTL(pipe, 0));
11103 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11104 switch (fb->modifier[0]) {
11105 case DRM_FORMAT_MOD_NONE:
11106 break;
11107 case I915_FORMAT_MOD_X_TILED:
ff944564 11108 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11109 break;
11110 case I915_FORMAT_MOD_Y_TILED:
11111 ctl |= PLANE_CTL_TILED_Y;
11112 break;
11113 case I915_FORMAT_MOD_Yf_TILED:
11114 ctl |= PLANE_CTL_TILED_YF;
11115 break;
11116 default:
11117 MISSING_CASE(fb->modifier[0]);
11118 }
ff944564
DL		 11119
11120 /*
11121 * The stride is either expressed as a multiple of 64 bytes chunks for
11122 * linear buffers or in number of tiles for tiled buffers.
11123 */
86efe24a
TU		 11124 if (intel_rotation_90_or_270(rotation)) {
11125 /* stride = Surface height in tiles */
11126 tile_height = intel_tile_height(dev, fb->pixel_format,
11127 fb->modifier[0], 0);
11128 stride = DIV_ROUND_UP(fb->height, tile_height);
11129 } else {
11130 stride = fb->pitches[0] /
11131 intel_fb_stride_alignment(dev, fb->modifier[0],
11132 fb->pixel_format);
11133 }
ff944564
DL		 11134
11135 /*
11136 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11137 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11138 */
11139 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11140 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11141
6042639c 11142 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
ff944564
DL		 11143 POSTING_READ(PLANE_SURF(pipe, 0));
11144}
11145
6042639c
CW		 11146static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11147 struct intel_unpin_work *work)
84c33a64
SG		 11148{
11149 struct drm_device *dev = intel_crtc->base.dev;
11150 struct drm_i915_private *dev_priv = dev->dev_private;
11151 struct intel_framebuffer *intel_fb =
11152 to_intel_framebuffer(intel_crtc->base.primary->fb);
11153 struct drm_i915_gem_object *obj = intel_fb->obj;
11154 u32 dspcntr;
11155 u32 reg;
11156
84c33a64
SG		 11157 reg = DSPCNTR(intel_crtc->plane);
11158 dspcntr = I915_READ(reg);
11159
c5d97472
DL		 11160 if (obj->tiling_mode != I915_TILING_NONE)
11161 dspcntr |= DISPPLANE_TILED;
11162 else
11163 dspcntr &= ~DISPPLANE_TILED;
11164
84c33a64
SG		 11165 I915_WRITE(reg, dspcntr);
11166
6042639c 11167 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
84c33a64 11168 POSTING_READ(DSPSURF(intel_crtc->plane));
ff944564
DL		 11169}
11170
11171/*
11172 * XXX: This is the temporary way to update the plane registers until we get
11173 * around to using the usual plane update functions for MMIO flips
11174 */
6042639c 11175static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
ff944564 11176{
6042639c
CW		 11177 struct intel_crtc *crtc = mmio_flip->crtc;
11178 struct intel_unpin_work *work;
11179
11180 spin_lock_irq(&crtc->base.dev->event_lock);
11181 work = crtc->unpin_work;
11182 spin_unlock_irq(&crtc->base.dev->event_lock);
11183 if (work == NULL)
11184 return;
ff944564 11185
6042639c 11186 intel_mark_page_flip_active(work);
ff944564 11187
6042639c 11188 intel_pipe_update_start(crtc);
ff944564 11189
6042639c 11190 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
86efe24a 11191 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
ff944564
DL		 11192 else
11193 /* use_mmio_flip() retricts MMIO flips to ilk+ */
6042639c 11194 ilk_do_mmio_flip(crtc, work);
ff944564 11195
6042639c 11196 intel_pipe_update_end(crtc);
84c33a64
SG		 11197}
11198
9362c7c5 11199static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11200{
b2cfe0ab
CW		 11201 struct intel_mmio_flip *mmio_flip =
11202 container_of(work, struct intel_mmio_flip, work);
84c33a64 11203
6042639c 11204 if (mmio_flip->req) {
eed29a5b 11205 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11206 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11207 false, NULL,
11208 &mmio_flip->i915->rps.mmioflips));
6042639c
CW		 11209 i915_gem_request_unreference__unlocked(mmio_flip->req);
11210 }
84c33a64 11211
6042639c 11212 intel_do_mmio_flip(mmio_flip);
b2cfe0ab 11213 kfree(mmio_flip);
84c33a64
SG		 11214}
11215
11216static int intel_queue_mmio_flip(struct drm_device *dev,
11217 struct drm_crtc *crtc,
86efe24a 11218 struct drm_i915_gem_object *obj)
84c33a64 11219{
b2cfe0ab
CW		 11220 struct intel_mmio_flip *mmio_flip;
11221
11222 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11223 if (mmio_flip == NULL)
11224 return -ENOMEM;
84c33a64 11225
bcafc4e3 11226 mmio_flip->i915 = to_i915(dev);
eed29a5b 11227 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11228 mmio_flip->crtc = to_intel_crtc(crtc);
86efe24a 11229 mmio_flip->rotation = crtc->primary->state->rotation;
536f5b5e 11230
b2cfe0ab
CW		 11231 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11232 schedule_work(&mmio_flip->work);
84c33a64 11233
84c33a64
SG		 11234 return 0;
11235}
11236
8c9f3aaf
JB		 11237static int intel_default_queue_flip(struct drm_device *dev,
11238 struct drm_crtc *crtc,
11239 struct drm_framebuffer *fb,
ed8d1975 11240 struct drm_i915_gem_object *obj,
6258fbe2 11241 struct drm_i915_gem_request *req,
ed8d1975 11242 uint32_t flags)
8c9f3aaf
JB		 11243{
11244 return -ENODEV;
11245}
11246
d6bbafa1
CW		 11247static bool __intel_pageflip_stall_check(struct drm_device *dev,
11248 struct drm_crtc *crtc)
11249{
11250 struct drm_i915_private *dev_priv = dev->dev_private;
11251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11252 struct intel_unpin_work *work = intel_crtc->unpin_work;
11253 u32 addr;
11254
11255 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11256 return true;
11257
908565c2
CW		 11258 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11259 return false;
11260
d6bbafa1
CW		 11261 if (!work->enable_stall_check)
11262 return false;
11263
11264 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11265 if (work->flip_queued_req &&
11266 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11267 return false;
11268
1e3feefd 11269 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11270 }
11271
1e3feefd 11272 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11273 return false;
11274
11275 /* Potential stall - if we see that the flip has happened,
11276 * assume a missed interrupt. */
11277 if (INTEL_INFO(dev)->gen >= 4)
11278 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11279 else
11280 addr = I915_READ(DSPADDR(intel_crtc->plane));
11281
11282 /* There is a potential issue here with a false positive after a flip
11283 * to the same address. We could address this by checking for a
11284 * non-incrementing frame counter.
11285 */
11286 return addr == work->gtt_offset;
11287}
11288
11289void intel_check_page_flip(struct drm_device *dev, int pipe)
11290{
11291 struct drm_i915_private *dev_priv = dev->dev_private;
11292 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11294 struct intel_unpin_work *work;
f326038a 11295
6c51d46f 11296 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11297
11298 if (crtc == NULL)
11299 return;
11300
f326038a 11301 spin_lock(&dev->event_lock);
6ad790c0
CW		 11302 work = intel_crtc->unpin_work;
11303 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11304 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11305 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11306 page_flip_completed(intel_crtc);
6ad790c0 11307 work = NULL;
d6bbafa1 11308 }
6ad790c0
CW		 11309 if (work != NULL &&
11310 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11311 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11312 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11313}
11314
6b95a207
KH		 11315static int intel_crtc_page_flip(struct drm_crtc *crtc,
11316 struct drm_framebuffer *fb,
ed8d1975
KP		 11317 struct drm_pending_vblank_event *event,
11318 uint32_t page_flip_flags)
6b95a207
KH		 11319{
11320 struct drm_device *dev = crtc->dev;
11321 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11322 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11323 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11325 struct drm_plane *primary = crtc->primary;
a071fa00 11326 enum pipe pipe = intel_crtc->pipe;
6b95a207 11327 struct intel_unpin_work *work;
a4872ba6 11328 struct intel_engine_cs *ring;
cf5d8a46 11329 bool mmio_flip;
91af127f 11330 struct drm_i915_gem_request *request = NULL;
52e68630 11331 int ret;
6b95a207 11332
2ff8fde1
MR		 11333 /*
11334 * drm_mode_page_flip_ioctl() should already catch this, but double
11335 * check to be safe. In the future we may enable pageflipping from
11336 * a disabled primary plane.
11337 */
11338 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11339 return -EBUSY;
11340
e6a595d2 11341 /* Can't change pixel format via MI display flips. */
f4510a27 11342 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11343 return -EINVAL;
11344
11345 /*
11346 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11347 * Note that pitch changes could also affect these register.
11348 */
11349 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11350 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11351 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11352 return -EINVAL;
11353
f900db47
CW		 11354 if (i915_terminally_wedged(&dev_priv->gpu_error))
11355 goto out_hang;
11356
b14c5679 11357 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11358 if (work == NULL)
11359 return -ENOMEM;
11360
6b95a207 11361 work->event = event;
b4a98e57 11362 work->crtc = crtc;
ab8d6675 11363 work->old_fb = old_fb;
6b95a207
KH		 11364 INIT_WORK(&work->work, intel_unpin_work_fn);
11365
87b6b101 11366 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11367 if (ret)
11368 goto free_work;
11369
6b95a207 11370 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11371 spin_lock_irq(&dev->event_lock);
6b95a207 11372 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11373 /* Before declaring the flip queue wedged, check if
11374 * the hardware completed the operation behind our backs.
11375 */
11376 if (__intel_pageflip_stall_check(dev, crtc)) {
11377 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11378 page_flip_completed(intel_crtc);
11379 } else {
11380 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11381 spin_unlock_irq(&dev->event_lock);
468f0b44 11382
d6bbafa1
CW		 11383 drm_crtc_vblank_put(crtc);
11384 kfree(work);
11385 return -EBUSY;
11386 }
6b95a207
KH		 11387 }
11388 intel_crtc->unpin_work = work;
5e2d7afc 11389 spin_unlock_irq(&dev->event_lock);
6b95a207 11390
b4a98e57
CW		 11391 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11392 flush_workqueue(dev_priv->wq);
11393
75dfca80 11394 /* Reference the objects for the scheduled work. */
ab8d6675 11395 drm_framebuffer_reference(work->old_fb);
05394f39 11396 drm_gem_object_reference(&obj->base);
6b95a207 11397
f4510a27 11398 crtc->primary->fb = fb;
afd65eb4 11399 update_state_fb(crtc->primary);
1ed1f968 11400
e1f99ce6 11401 work->pending_flip_obj = obj;
e1f99ce6 11402
89ed88ba
CW		 11403 ret = i915_mutex_lock_interruptible(dev);
11404 if (ret)
11405 goto cleanup;
11406
b4a98e57 11407 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11408 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11409
75f7f3ec 11410 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
fd8f507c 11411 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
75f7f3ec 11412
4fa62c89
VS		 11413 if (IS_VALLEYVIEW(dev)) {
11414 ring = &dev_priv->ring[BCS];
ab8d6675 11415 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11416 /* vlv: DISPLAY_FLIP fails to change tiling */
11417 ring = NULL;
48bf5b2d 11418 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11419 ring = &dev_priv->ring[BCS];
4fa62c89 11420 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11421 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11422 if (ring == NULL || ring->id != RCS)
11423 ring = &dev_priv->ring[BCS];
11424 } else {
11425 ring = &dev_priv->ring[RCS];
11426 }
11427
cf5d8a46
CW		 11428 mmio_flip = use_mmio_flip(ring, obj);
11429
11430 /* When using CS flips, we want to emit semaphores between rings.
11431 * However, when using mmio flips we will create a task to do the
11432 * synchronisation, so all we want here is to pin the framebuffer
11433 * into the display plane and skip any waits.
11434 */
7580d774
ML		 11435 if (!mmio_flip) {
11436 ret = i915_gem_object_sync(obj, ring, &request);
11437 if (ret)
11438 goto cleanup_pending;
11439 }
11440
82bc3b2d 11441 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
7580d774 11442 crtc->primary->state);
8c9f3aaf
JB		 11443 if (ret)
11444 goto cleanup_pending;
6b95a207 11445
dedf278c
TU		 11446 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11447 obj, 0);
11448 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11449
cf5d8a46 11450 if (mmio_flip) {
86efe24a 11451 ret = intel_queue_mmio_flip(dev, crtc, obj);
d6bbafa1
CW		 11452 if (ret)
11453 goto cleanup_unpin;
11454
f06cc1b9
JH		 11455 i915_gem_request_assign(&work->flip_queued_req,
11456 obj->last_write_req);
d6bbafa1 11457 } else {
6258fbe2
JH		 11458 if (!request) {
11459 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11460 if (ret)
11461 goto cleanup_unpin;
11462 }
11463
11464 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11465 page_flip_flags);
11466 if (ret)
11467 goto cleanup_unpin;
11468
6258fbe2 11469 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11470 }
11471
91af127f 11472 if (request)
75289874 11473 i915_add_request_no_flush(request);
91af127f 11474
1e3feefd 11475 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11476 work->enable_stall_check = true;
4fa62c89 11477
ab8d6675 11478 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11479 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11480 mutex_unlock(&dev->struct_mutex);
a071fa00 11481
4e1e26f1 11482 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11483 intel_frontbuffer_flip_prepare(dev,
11484 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11485
e5510fac
JB		 11486 trace_i915_flip_request(intel_crtc->plane, obj);
11487
6b95a207 11488 return 0;
96b099fd 11489
4fa62c89 11490cleanup_unpin:
82bc3b2d 11491 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11492cleanup_pending:
91af127f
JH		 11493 if (request)
11494 i915_gem_request_cancel(request);
b4a98e57 11495 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11496 mutex_unlock(&dev->struct_mutex);
11497cleanup:
f4510a27 11498 crtc->primary->fb = old_fb;
afd65eb4 11499 update_state_fb(crtc->primary);
89ed88ba
CW		 11500
11501 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11502 drm_framebuffer_unreference(work->old_fb);
96b099fd 11503
5e2d7afc 11504 spin_lock_irq(&dev->event_lock);
96b099fd 11505 intel_crtc->unpin_work = NULL;
5e2d7afc 11506 spin_unlock_irq(&dev->event_lock);
96b099fd 11507
87b6b101 11508 drm_crtc_vblank_put(crtc);
7317c75e 11509free_work:
96b099fd
CW		 11510 kfree(work);
11511
f900db47 11512 if (ret == -EIO) {
02e0efb5
ML		 11513 struct drm_atomic_state *state;
11514 struct drm_plane_state *plane_state;
11515
f900db47 11516out_hang:
02e0efb5
ML		 11517 state = drm_atomic_state_alloc(dev);
11518 if (!state)
11519 return -ENOMEM;
11520 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11521
11522retry:
11523 plane_state = drm_atomic_get_plane_state(state, primary);
11524 ret = PTR_ERR_OR_ZERO(plane_state);
11525 if (!ret) {
11526 drm_atomic_set_fb_for_plane(plane_state, fb);
11527
11528 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11529 if (!ret)
11530 ret = drm_atomic_commit(state);
11531 }
11532
11533 if (ret == -EDEADLK) {
11534 drm_modeset_backoff(state->acquire_ctx);
11535 drm_atomic_state_clear(state);
11536 goto retry;
11537 }
11538
11539 if (ret)
11540 drm_atomic_state_free(state);
11541
f0d3dad3 11542 if (ret == 0 && event) {
5e2d7afc 11543 spin_lock_irq(&dev->event_lock);
a071fa00 11544 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11545 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11546 }
f900db47 11547 }
96b099fd 11548 return ret;
6b95a207
KH		 11549}
11550
da20eabd
ML		 11551
11552/**
11553 * intel_wm_need_update - Check whether watermarks need updating
11554 * @plane: drm plane
11555 * @state: new plane state
11556 *
11557 * Check current plane state versus the new one to determine whether
11558 * watermarks need to be recalculated.
11559 *
11560 * Returns true or false.
11561 */
11562static bool intel_wm_need_update(struct drm_plane *plane,
11563 struct drm_plane_state *state)
11564{
d21fbe87
MR		 11565 struct intel_plane_state *new = to_intel_plane_state(state);
11566 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11567
11568 /* Update watermarks on tiling or size changes. */
da20eabd
ML		 11569 if (!plane->state->fb || !state->fb ||
11570 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
d21fbe87
MR		 11571 plane->state->rotation != state->rotation ||
11572 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11573 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11574 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11575 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
2791a16c 11576 return true;
7809e5ae 11577
2791a16c 11578 return false;
7809e5ae
MR		 11579}
11580
d21fbe87
MR		 11581static bool needs_scaling(struct intel_plane_state *state)
11582{
11583 int src_w = drm_rect_width(&state->src) >> 16;
11584 int src_h = drm_rect_height(&state->src) >> 16;
11585 int dst_w = drm_rect_width(&state->dst);
11586 int dst_h = drm_rect_height(&state->dst);
11587
11588 return (src_w != dst_w || src_h != dst_h);
11589}
11590
da20eabd
ML		 11591int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11592 struct drm_plane_state *plane_state)
11593{
11594 struct drm_crtc *crtc = crtc_state->crtc;
11595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11596 struct drm_plane *plane = plane_state->plane;
11597 struct drm_device *dev = crtc->dev;
11598 struct drm_i915_private *dev_priv = dev->dev_private;
11599 struct intel_plane_state *old_plane_state =
11600 to_intel_plane_state(plane->state);
11601 int idx = intel_crtc->base.base.id, ret;
11602 int i = drm_plane_index(plane);
11603 bool mode_changed = needs_modeset(crtc_state);
11604 bool was_crtc_enabled = crtc->state->active;
11605 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11606 bool turn_off, turn_on, visible, was_visible;
11607 struct drm_framebuffer *fb = plane_state->fb;
11608
11609 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11610 plane->type != DRM_PLANE_TYPE_CURSOR) {
11611 ret = skl_update_scaler_plane(
11612 to_intel_crtc_state(crtc_state),
11613 to_intel_plane_state(plane_state));
11614 if (ret)
11615 return ret;
11616 }
11617
da20eabd
ML		 11618 was_visible = old_plane_state->visible;
11619 visible = to_intel_plane_state(plane_state)->visible;
11620
11621 if (!was_crtc_enabled && WARN_ON(was_visible))
11622 was_visible = false;
11623
11624 if (!is_crtc_enabled && WARN_ON(visible))
11625 visible = false;
11626
11627 if (!was_visible && !visible)
11628 return 0;
11629
11630 turn_off = was_visible && (!visible || mode_changed);
11631 turn_on = visible && (!was_visible || mode_changed);
11632
11633 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11634 plane->base.id, fb ? fb->base.id : -1);
11635
11636 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11637 plane->base.id, was_visible, visible,
11638 turn_off, turn_on, mode_changed);
11639
852eb00d 11640 if (turn_on) {
f015c551 11641 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11642 /* must disable cxsr around plane enable/disable */
11643 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11644 intel_crtc->atomic.disable_cxsr = true;
11645 /* to potentially re-enable cxsr */
11646 intel_crtc->atomic.wait_vblank = true;
11647 intel_crtc->atomic.update_wm_post = true;
11648 }
11649 } else if (turn_off) {
f015c551 11650 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11651 /* must disable cxsr around plane enable/disable */
11652 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11653 if (is_crtc_enabled)
11654 intel_crtc->atomic.wait_vblank = true;
11655 intel_crtc->atomic.disable_cxsr = true;
11656 }
11657 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11658 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11659 }
da20eabd 11660
8be6ca85 11661 if (visible || was_visible)
a9ff8714
VS		 11662 intel_crtc->atomic.fb_bits |=
11663 to_intel_plane(plane)->frontbuffer_bit;
11664
da20eabd
ML		 11665 switch (plane->type) {
11666 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11667 intel_crtc->atomic.pre_disable_primary = turn_off;
11668 intel_crtc->atomic.post_enable_primary = turn_on;
11669
066cf55b
RV		 11670 if (turn_off) {
11671 /*
11672 * FIXME: Actually if we will still have any other
11673 * plane enabled on the pipe we could let IPS enabled
11674 * still, but for now lets consider that when we make
11675 * primary invisible by setting DSPCNTR to 0 on
11676 * update_primary_plane function IPS needs to be
11677 * disable.
11678 */
11679 intel_crtc->atomic.disable_ips = true;
11680
da20eabd 11681 intel_crtc->atomic.disable_fbc = true;
066cf55b 11682 }
da20eabd
ML		 11683
11684 /*
11685 * FBC does not work on some platforms for rotated
11686 * planes, so disable it when rotation is not 0 and
11687 * update it when rotation is set back to 0.
11688 *
11689 * FIXME: This is redundant with the fbc update done in
11690 * the primary plane enable function except that that
11691 * one is done too late. We eventually need to unify
11692 * this.
11693 */
11694
11695 if (visible &&
11696 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11697 dev_priv->fbc.crtc == intel_crtc &&
11698 plane_state->rotation != BIT(DRM_ROTATE_0))
11699 intel_crtc->atomic.disable_fbc = true;
11700
11701 /*
11702 * BDW signals flip done immediately if the plane
11703 * is disabled, even if the plane enable is already
11704 * armed to occur at the next vblank :(
11705 */
11706 if (turn_on && IS_BROADWELL(dev))
11707 intel_crtc->atomic.wait_vblank = true;
11708
11709 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11710 break;
11711 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11712 break;
11713 case DRM_PLANE_TYPE_OVERLAY:
d21fbe87
MR		 11714 /*
11715 * WaCxSRDisabledForSpriteScaling:ivb
11716 *
11717 * cstate->update_wm was already set above, so this flag will
11718 * take effect when we commit and program watermarks.
11719 */
11720 if (IS_IVYBRIDGE(dev) &&
11721 needs_scaling(to_intel_plane_state(plane_state)) &&
11722 !needs_scaling(old_plane_state)) {
11723 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11724 } else if (turn_off && !mode_changed) {
da20eabd
ML		 11725 intel_crtc->atomic.wait_vblank = true;
11726 intel_crtc->atomic.update_sprite_watermarks |=
11727 1 << i;
11728 }
d21fbe87
MR		 11729
11730 break;
da20eabd
ML		 11731 }
11732 return 0;
11733}
11734
6d3a1ce7
ML		 11735static bool encoders_cloneable(const struct intel_encoder *a,
11736 const struct intel_encoder *b)
11737{
11738 /* masks could be asymmetric, so check both ways */
11739 return a == b || (a->cloneable & (1 << b->type) &&
11740 b->cloneable & (1 << a->type));
11741}
11742
11743static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11744 struct intel_crtc *crtc,
11745 struct intel_encoder *encoder)
11746{
11747 struct intel_encoder *source_encoder;
11748 struct drm_connector *connector;
11749 struct drm_connector_state *connector_state;
11750 int i;
11751
11752 for_each_connector_in_state(state, connector, connector_state, i) {
11753 if (connector_state->crtc != &crtc->base)
11754 continue;
11755
11756 source_encoder =
11757 to_intel_encoder(connector_state->best_encoder);
11758 if (!encoders_cloneable(encoder, source_encoder))
11759 return false;
11760 }
11761
11762 return true;
11763}
11764
11765static bool check_encoder_cloning(struct drm_atomic_state *state,
11766 struct intel_crtc *crtc)
11767{
11768 struct intel_encoder *encoder;
11769 struct drm_connector *connector;
11770 struct drm_connector_state *connector_state;
11771 int i;
11772
11773 for_each_connector_in_state(state, connector, connector_state, i) {
11774 if (connector_state->crtc != &crtc->base)
11775 continue;
11776
11777 encoder = to_intel_encoder(connector_state->best_encoder);
11778 if (!check_single_encoder_cloning(state, crtc, encoder))
11779 return false;
11780 }
11781
11782 return true;
11783}
11784
11785static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11786 struct drm_crtc_state *crtc_state)
11787{
cf5a15be 11788 struct drm_device *dev = crtc->dev;
ad421372 11789 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11791 struct intel_crtc_state *pipe_config =
11792 to_intel_crtc_state(crtc_state);
6d3a1ce7 11793 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11794 int ret;
6d3a1ce7
ML		 11795 bool mode_changed = needs_modeset(crtc_state);
11796
11797 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11798 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11799 return -EINVAL;
11800 }
11801
852eb00d
VS		 11802 if (mode_changed && !crtc_state->active)
11803 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11804
ad421372
ML		 11805 if (mode_changed && crtc_state->enable &&
11806 dev_priv->display.crtc_compute_clock &&
11807 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11808 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11809 pipe_config);
11810 if (ret)
11811 return ret;
11812 }
11813
e435d6e5 11814 ret = 0;
86c8bbbe
MR		 11815 if (dev_priv->display.compute_pipe_wm) {
11816 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11817 if (ret)
11818 return ret;
11819 }
11820
e435d6e5
ML		 11821 if (INTEL_INFO(dev)->gen >= 9) {
11822 if (mode_changed)
11823 ret = skl_update_scaler_crtc(pipe_config);
11824
11825 if (!ret)
11826 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11827 pipe_config);
11828 }
11829
11830 return ret;
6d3a1ce7
ML		 11831}
11832
65b38e0d 11833static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11834 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11835 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11836 .atomic_begin = intel_begin_crtc_commit,
11837 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11838 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11839};
11840
d29b2f9d
ACO		 11841static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11842{
11843 struct intel_connector *connector;
11844
11845 for_each_intel_connector(dev, connector) {
11846 if (connector->base.encoder) {
11847 connector->base.state->best_encoder =
11848 connector->base.encoder;
11849 connector->base.state->crtc =
11850 connector->base.encoder->crtc;
11851 } else {
11852 connector->base.state->best_encoder = NULL;
11853 connector->base.state->crtc = NULL;
11854 }
11855 }
11856}
11857
050f7aeb 11858static void
eba905b2 11859connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11860 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11861{
11862 int bpp = pipe_config->pipe_bpp;
11863
11864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11865 connector->base.base.id,
c23cc417 11866 connector->base.name);
050f7aeb
DV		 11867
11868 /* Don't use an invalid EDID bpc value */
11869 if (connector->base.display_info.bpc &&
11870 connector->base.display_info.bpc * 3 < bpp) {
11871 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11872 bpp, connector->base.display_info.bpc*3);
11873 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11874 }
11875
11876 /* Clamp bpp to 8 on screens without EDID 1.4 */
11877 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11878 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11879 bpp);
11880 pipe_config->pipe_bpp = 24;
11881 }
11882}
11883
4e53c2e0 11884static int
050f7aeb 11885compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11886 struct intel_crtc_state *pipe_config)
4e53c2e0 11887{
050f7aeb 11888 struct drm_device *dev = crtc->base.dev;
1486017f 11889 struct drm_atomic_state *state;
da3ced29
ACO		 11890 struct drm_connector *connector;
11891 struct drm_connector_state *connector_state;
1486017f 11892 int bpp, i;
4e53c2e0 11893
d328c9d7 11894 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11895 bpp = 10*3;
d328c9d7
DV		 11896 else if (INTEL_INFO(dev)->gen >= 5)
11897 bpp = 12*3;
11898 else
11899 bpp = 8*3;
11900
4e53c2e0 11901
4e53c2e0
DV		 11902 pipe_config->pipe_bpp = bpp;
11903
1486017f
ACO		 11904 state = pipe_config->base.state;
11905
4e53c2e0 11906 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11907 for_each_connector_in_state(state, connector, connector_state, i) {
11908 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11909 continue;
11910
da3ced29
ACO		 11911 connected_sink_compute_bpp(to_intel_connector(connector),
11912 pipe_config);
4e53c2e0
DV		 11913 }
11914
11915 return bpp;
11916}
11917
644db711
DV		 11918static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11919{
11920 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11921 "type: 0x%x flags: 0x%x\n",
1342830c 11922 mode->crtc_clock,
644db711
DV		 11923 mode->crtc_hdisplay, mode->crtc_hsync_start,
11924 mode->crtc_hsync_end, mode->crtc_htotal,
11925 mode->crtc_vdisplay, mode->crtc_vsync_start,
11926 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11927}
11928
c0b03411 11929static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11930 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11931 const char *context)
11932{
6a60cd87
CK		 11933 struct drm_device *dev = crtc->base.dev;
11934 struct drm_plane *plane;
11935 struct intel_plane *intel_plane;
11936 struct intel_plane_state *state;
11937 struct drm_framebuffer *fb;
11938
11939 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11940 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11941
11942 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11943 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11944 pipe_config->pipe_bpp, pipe_config->dither);
11945 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11946 pipe_config->has_pch_encoder,
11947 pipe_config->fdi_lanes,
11948 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11949 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11950 pipe_config->fdi_m_n.tu);
90a6b7b0 11951 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11952 pipe_config->has_dp_encoder,
90a6b7b0 11953 pipe_config->lane_count,
eb14cb74
VS		 11954 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11955 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11956 pipe_config->dp_m_n.tu);
b95af8be 11957
90a6b7b0 11958 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11959 pipe_config->has_dp_encoder,
90a6b7b0 11960 pipe_config->lane_count,
b95af8be
VK		 11961 pipe_config->dp_m2_n2.gmch_m,
11962 pipe_config->dp_m2_n2.gmch_n,
11963 pipe_config->dp_m2_n2.link_m,
11964 pipe_config->dp_m2_n2.link_n,
11965 pipe_config->dp_m2_n2.tu);
11966
55072d19
DV		 11967 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11968 pipe_config->has_audio,
11969 pipe_config->has_infoframe);
11970
c0b03411 11971 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11972 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11973 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11974 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11975 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11976 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11977 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11978 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11979 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11980 crtc->num_scalers,
11981 pipe_config->scaler_state.scaler_users,
11982 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11983 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11984 pipe_config->gmch_pfit.control,
11985 pipe_config->gmch_pfit.pgm_ratios,
11986 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11987 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11988 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11989 pipe_config->pch_pfit.size,
11990 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11991 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11992 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11993
415ff0f6 11994 if (IS_BROXTON(dev)) {
05712c15 11995 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11996 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11997 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11998 pipe_config->ddi_pll_sel,
11999 pipe_config->dpll_hw_state.ebb0,
05712c15 12000 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12001 pipe_config->dpll_hw_state.pll0,
12002 pipe_config->dpll_hw_state.pll1,
12003 pipe_config->dpll_hw_state.pll2,
12004 pipe_config->dpll_hw_state.pll3,
12005 pipe_config->dpll_hw_state.pll6,
12006 pipe_config->dpll_hw_state.pll8,
05712c15 12007 pipe_config->dpll_hw_state.pll9,
c8453338 12008 pipe_config->dpll_hw_state.pll10,
415ff0f6 12009 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 12010 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU		 12011 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12012 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12013 pipe_config->ddi_pll_sel,
12014 pipe_config->dpll_hw_state.ctrl1,
12015 pipe_config->dpll_hw_state.cfgcr1,
12016 pipe_config->dpll_hw_state.cfgcr2);
12017 } else if (HAS_DDI(dev)) {
12018 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12019 pipe_config->ddi_pll_sel,
12020 pipe_config->dpll_hw_state.wrpll);
12021 } else {
12022 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12023 "fp0: 0x%x, fp1: 0x%x\n",
12024 pipe_config->dpll_hw_state.dpll,
12025 pipe_config->dpll_hw_state.dpll_md,
12026 pipe_config->dpll_hw_state.fp0,
12027 pipe_config->dpll_hw_state.fp1);
12028 }
12029
6a60cd87
CK		 12030 DRM_DEBUG_KMS("planes on this crtc\n");
12031 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12032 intel_plane = to_intel_plane(plane);
12033 if (intel_plane->pipe != crtc->pipe)
12034 continue;
12035
12036 state = to_intel_plane_state(plane->state);
12037 fb = state->base.fb;
12038 if (!fb) {
12039 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12040 "disabled, scaler_id = %d\n",
12041 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12042 plane->base.id, intel_plane->pipe,
12043 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12044 drm_plane_index(plane), state->scaler_id);
12045 continue;
12046 }
12047
12048 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12049 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12050 plane->base.id, intel_plane->pipe,
12051 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12052 drm_plane_index(plane));
12053 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12054 fb->base.id, fb->width, fb->height, fb->pixel_format);
12055 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12056 state->scaler_id,
12057 state->src.x1 >> 16, state->src.y1 >> 16,
12058 drm_rect_width(&state->src) >> 16,
12059 drm_rect_height(&state->src) >> 16,
12060 state->dst.x1, state->dst.y1,
12061 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12062 }
c0b03411
DV		 12063}
12064
5448a00d 12065static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12066{
5448a00d
ACO		 12067 struct drm_device *dev = state->dev;
12068 struct intel_encoder *encoder;
da3ced29 12069 struct drm_connector *connector;
5448a00d 12070 struct drm_connector_state *connector_state;
00f0b378 12071 unsigned int used_ports = 0;
5448a00d 12072 int i;
00f0b378
VS		 12073
12074 /*
12075 * Walk the connector list instead of the encoder
12076 * list to detect the problem on ddi platforms
12077 * where there's just one encoder per digital port.
12078 */
da3ced29 12079 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12080 if (!connector_state->best_encoder)
00f0b378
VS		 12081 continue;
12082
5448a00d
ACO		 12083 encoder = to_intel_encoder(connector_state->best_encoder);
12084
12085 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12086
12087 switch (encoder->type) {
12088 unsigned int port_mask;
12089 case INTEL_OUTPUT_UNKNOWN:
12090 if (WARN_ON(!HAS_DDI(dev)))
12091 break;
12092 case INTEL_OUTPUT_DISPLAYPORT:
12093 case INTEL_OUTPUT_HDMI:
12094 case INTEL_OUTPUT_EDP:
12095 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12096
12097 /* the same port mustn't appear more than once */
12098 if (used_ports & port_mask)
12099 return false;
12100
12101 used_ports |= port_mask;
12102 default:
12103 break;
12104 }
12105 }
12106
12107 return true;
12108}
12109
83a57153
ACO		 12110static void
12111clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12112{
12113 struct drm_crtc_state tmp_state;
663a3640 12114 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12115 struct intel_dpll_hw_state dpll_hw_state;
12116 enum intel_dpll_id shared_dpll;
8504c74c 12117 uint32_t ddi_pll_sel;
c4e2d043 12118 bool force_thru;
83a57153 12119
7546a384
ACO		 12120 /* FIXME: before the switch to atomic started, a new pipe_config was
12121 * kzalloc'd. Code that depends on any field being zero should be
12122 * fixed, so that the crtc_state can be safely duplicated. For now,
12123 * only fields that are know to not cause problems are preserved. */
12124
83a57153 12125 tmp_state = crtc_state->base;
663a3640 12126 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12127 shared_dpll = crtc_state->shared_dpll;
12128 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12129 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12130 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12131
83a57153 12132 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12133
83a57153 12134 crtc_state->base = tmp_state;
663a3640 12135 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12136 crtc_state->shared_dpll = shared_dpll;
12137 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12138 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12139 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12140}
12141
548ee15b 12142static int
b8cecdf5 12143intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12144 struct intel_crtc_state *pipe_config)
ee7b9f93 12145{
b359283a 12146 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12147 struct intel_encoder *encoder;
da3ced29 12148 struct drm_connector *connector;
0b901879 12149 struct drm_connector_state *connector_state;
d328c9d7 12150 int base_bpp, ret = -EINVAL;
0b901879 12151 int i;
e29c22c0 12152 bool retry = true;
ee7b9f93 12153
83a57153 12154 clear_intel_crtc_state(pipe_config);
7758a113 12155
e143a21c
DV		 12156 pipe_config->cpu_transcoder =
12157 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12158
2960bc9c
ID		 12159 /*
12160 * Sanitize sync polarity flags based on requested ones. If neither
12161 * positive or negative polarity is requested, treat this as meaning
12162 * negative polarity.
12163 */
2d112de7 12164 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12165 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12166 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12167
2d112de7 12168 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12169 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12170 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12171
d328c9d7
DV		 12172 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12173 pipe_config);
12174 if (base_bpp < 0)
4e53c2e0
DV		 12175 goto fail;
12176
e41a56be
VS		 12177 /*
12178 * Determine the real pipe dimensions. Note that stereo modes can
12179 * increase the actual pipe size due to the frame doubling and
12180 * insertion of additional space for blanks between the frame. This
12181 * is stored in the crtc timings. We use the requested mode to do this
12182 * computation to clearly distinguish it from the adjusted mode, which
12183 * can be changed by the connectors in the below retry loop.
12184 */
2d112de7 12185 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12186 &pipe_config->pipe_src_w,
12187 &pipe_config->pipe_src_h);
e41a56be 12188
e29c22c0 12189encoder_retry:
ef1b460d 12190 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12191 pipe_config->port_clock = 0;
ef1b460d 12192 pipe_config->pixel_multiplier = 1;
ff9a6750 12193
135c81b8 12194 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12195 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12196 CRTC_STEREO_DOUBLE);
135c81b8 12197
7758a113
DV		 12198 /* Pass our mode to the connectors and the CRTC to give them a chance to
12199 * adjust it according to limitations or connector properties, and also
12200 * a chance to reject the mode entirely.
47f1c6c9 12201 */
da3ced29 12202 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12203 if (connector_state->crtc != crtc)
7758a113 12204 continue;
7ae89233 12205
0b901879
ACO		 12206 encoder = to_intel_encoder(connector_state->best_encoder);
12207
efea6e8e
DV		 12208 if (!(encoder->compute_config(encoder, pipe_config))) {
12209 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12210 goto fail;
12211 }
ee7b9f93 12212 }
47f1c6c9 12213
ff9a6750
DV		 12214 /* Set default port clock if not overwritten by the encoder. Needs to be
12215 * done afterwards in case the encoder adjusts the mode. */
12216 if (!pipe_config->port_clock)
2d112de7 12217 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12218 * pipe_config->pixel_multiplier;
ff9a6750 12219
a43f6e0f 12220 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12221 if (ret < 0) {
7758a113
DV		 12222 DRM_DEBUG_KMS("CRTC fixup failed\n");
12223 goto fail;
ee7b9f93 12224 }
e29c22c0
DV		 12225
12226 if (ret == RETRY) {
12227 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12228 ret = -EINVAL;
12229 goto fail;
12230 }
12231
12232 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12233 retry = false;
12234 goto encoder_retry;
12235 }
12236
e8fa4270
DV		 12237 /* Dithering seems to not pass-through bits correctly when it should, so
12238 * only enable it on 6bpc panels. */
12239 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12240 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12241 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12242
7758a113 12243fail:
548ee15b 12244 return ret;
ee7b9f93 12245}
47f1c6c9 12246
ea9d758d 12247static void
4740b0f2 12248intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12249{
0a9ab303
ACO		 12250 struct drm_crtc *crtc;
12251 struct drm_crtc_state *crtc_state;
8a75d157 12252 int i;
ea9d758d 12253
7668851f 12254 /* Double check state. */
8a75d157 12255 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12256 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12257
12258 /* Update hwmode for vblank functions */
12259 if (crtc->state->active)
12260 crtc->hwmode = crtc->state->adjusted_mode;
12261 else
12262 crtc->hwmode.crtc_clock = 0;
61067a5e
ML		 12263
12264 /*
12265 * Update legacy state to satisfy fbc code. This can
12266 * be removed when fbc uses the atomic state.
12267 */
12268 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12269 struct drm_plane_state *plane_state = crtc->primary->state;
12270
12271 crtc->primary->fb = plane_state->fb;
12272 crtc->x = plane_state->src_x >> 16;
12273 crtc->y = plane_state->src_y >> 16;
12274 }
ea9d758d 12275 }
ea9d758d
DV		 12276}
12277
3bd26263 12278static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12279{
3bd26263 12280 int diff;
f1f644dc
JB		 12281
12282 if (clock1 == clock2)
12283 return true;
12284
12285 if (!clock1 || !clock2)
12286 return false;
12287
12288 diff = abs(clock1 - clock2);
12289
12290 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12291 return true;
12292
12293 return false;
12294}
12295
25c5b266
DV		 12296#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12297 list_for_each_entry((intel_crtc), \
12298 &(dev)->mode_config.crtc_list, \
12299 base.head) \
0973f18f 12300 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12301
cfb23ed6
ML		 12302static bool
12303intel_compare_m_n(unsigned int m, unsigned int n,
12304 unsigned int m2, unsigned int n2,
12305 bool exact)
12306{
12307 if (m == m2 && n == n2)
12308 return true;
12309
12310 if (exact || !m || !n || !m2 || !n2)
12311 return false;
12312
12313 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12314
12315 if (m > m2) {
12316 while (m > m2) {
12317 m2 <<= 1;
12318 n2 <<= 1;
12319 }
12320 } else if (m < m2) {
12321 while (m < m2) {
12322 m <<= 1;
12323 n <<= 1;
12324 }
12325 }
12326
12327 return m == m2 && n == n2;
12328}
12329
12330static bool
12331intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12332 struct intel_link_m_n *m2_n2,
12333 bool adjust)
12334{
12335 if (m_n->tu == m2_n2->tu &&
12336 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12337 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12338 intel_compare_m_n(m_n->link_m, m_n->link_n,
12339 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12340 if (adjust)
12341 *m2_n2 = *m_n;
12342
12343 return true;
12344 }
12345
12346 return false;
12347}
12348
0e8ffe1b 12349static bool
2fa2fe9a 12350intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12351 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12352 struct intel_crtc_state *pipe_config,
12353 bool adjust)
0e8ffe1b 12354{
cfb23ed6
ML		 12355 bool ret = true;
12356
12357#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12358 do { \
12359 if (!adjust) \
12360 DRM_ERROR(fmt, ##__VA_ARGS__); \
12361 else \
12362 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12363 } while (0)
12364
66e985c0
DV		 12365#define PIPE_CONF_CHECK_X(name) \
12366 if (current_config->name != pipe_config->name) { \
cfb23ed6 12367 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12368 "(expected 0x%08x, found 0x%08x)\n", \
12369 current_config->name, \
12370 pipe_config->name); \
cfb23ed6 12371 ret = false; \
66e985c0
DV		 12372 }
12373
08a24034
DV		 12374#define PIPE_CONF_CHECK_I(name) \
12375 if (current_config->name != pipe_config->name) { \
cfb23ed6 12376 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12377 "(expected %i, found %i)\n", \
12378 current_config->name, \
12379 pipe_config->name); \
cfb23ed6
ML		 12380 ret = false; \
12381 }
12382
12383#define PIPE_CONF_CHECK_M_N(name) \
12384 if (!intel_compare_link_m_n(&current_config->name, \
12385 &pipe_config->name,\
12386 adjust)) { \
12387 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12388 "(expected tu %i gmch %i/%i link %i/%i, " \
12389 "found tu %i, gmch %i/%i link %i/%i)\n", \
12390 current_config->name.tu, \
12391 current_config->name.gmch_m, \
12392 current_config->name.gmch_n, \
12393 current_config->name.link_m, \
12394 current_config->name.link_n, \
12395 pipe_config->name.tu, \
12396 pipe_config->name.gmch_m, \
12397 pipe_config->name.gmch_n, \
12398 pipe_config->name.link_m, \
12399 pipe_config->name.link_n); \
12400 ret = false; \
12401 }
12402
12403#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12404 if (!intel_compare_link_m_n(&current_config->name, \
12405 &pipe_config->name, adjust) && \
12406 !intel_compare_link_m_n(&current_config->alt_name, \
12407 &pipe_config->name, adjust)) { \
12408 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12409 "(expected tu %i gmch %i/%i link %i/%i, " \
12410 "or tu %i gmch %i/%i link %i/%i, " \
12411 "found tu %i, gmch %i/%i link %i/%i)\n", \
12412 current_config->name.tu, \
12413 current_config->name.gmch_m, \
12414 current_config->name.gmch_n, \
12415 current_config->name.link_m, \
12416 current_config->name.link_n, \
12417 current_config->alt_name.tu, \
12418 current_config->alt_name.gmch_m, \
12419 current_config->alt_name.gmch_n, \
12420 current_config->alt_name.link_m, \
12421 current_config->alt_name.link_n, \
12422 pipe_config->name.tu, \
12423 pipe_config->name.gmch_m, \
12424 pipe_config->name.gmch_n, \
12425 pipe_config->name.link_m, \
12426 pipe_config->name.link_n); \
12427 ret = false; \
88adfff1
DV		 12428 }
12429
b95af8be
VK		 12430/* This is required for BDW+ where there is only one set of registers for
12431 * switching between high and low RR.
12432 * This macro can be used whenever a comparison has to be made between one
12433 * hw state and multiple sw state variables.
12434 */
12435#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12436 if ((current_config->name != pipe_config->name) && \
12437 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12438 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12439 "(expected %i or %i, found %i)\n", \
12440 current_config->name, \
12441 current_config->alt_name, \
12442 pipe_config->name); \
cfb23ed6 12443 ret = false; \
b95af8be
VK		 12444 }
12445
1bd1bd80
DV		 12446#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12447 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12448 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12449 "(expected %i, found %i)\n", \
12450 current_config->name & (mask), \
12451 pipe_config->name & (mask)); \
cfb23ed6 12452 ret = false; \
1bd1bd80
DV		 12453 }
12454
5e550656
VS		 12455#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12456 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12457 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12458 "(expected %i, found %i)\n", \
12459 current_config->name, \
12460 pipe_config->name); \
cfb23ed6 12461 ret = false; \
5e550656
VS		 12462 }
12463
bb760063
DV		 12464#define PIPE_CONF_QUIRK(quirk) \
12465 ((current_config->quirks | pipe_config->quirks) & (quirk))
12466
eccb140b
DV		 12467 PIPE_CONF_CHECK_I(cpu_transcoder);
12468
08a24034
DV		 12469 PIPE_CONF_CHECK_I(has_pch_encoder);
12470 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12471 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12472
eb14cb74 12473 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12474 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12475
12476 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12477 PIPE_CONF_CHECK_M_N(dp_m_n);
12478
12479 PIPE_CONF_CHECK_I(has_drrs);
12480 if (current_config->has_drrs)
12481 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12482 } else
12483 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12484
2d112de7
ACO		 12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12491
2d112de7
ACO		 12492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12495 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12496 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12497 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12498
c93f54cf 12499 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12500 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12501 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12502 IS_VALLEYVIEW(dev))
12503 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12504 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12505
9ed109a7
DV		 12506 PIPE_CONF_CHECK_I(has_audio);
12507
2d112de7 12508 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12509 DRM_MODE_FLAG_INTERLACE);
12510
bb760063 12511 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12512 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12513 DRM_MODE_FLAG_PHSYNC);
2d112de7 12514 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12515 DRM_MODE_FLAG_NHSYNC);
2d112de7 12516 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12517 DRM_MODE_FLAG_PVSYNC);
2d112de7 12518 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12519 DRM_MODE_FLAG_NVSYNC);
12520 }
045ac3b5 12521
333b8ca8 12522 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12523 /* pfit ratios are autocomputed by the hw on gen4+ */
12524 if (INTEL_INFO(dev)->gen < 4)
12525 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12526 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12527
bfd16b2a
ML		 12528 if (!adjust) {
12529 PIPE_CONF_CHECK_I(pipe_src_w);
12530 PIPE_CONF_CHECK_I(pipe_src_h);
12531
12532 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12533 if (current_config->pch_pfit.enabled) {
12534 PIPE_CONF_CHECK_X(pch_pfit.pos);
12535 PIPE_CONF_CHECK_X(pch_pfit.size);
12536 }
2fa2fe9a 12537
7aefe2b5
ML		 12538 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12539 }
a1b2278e 12540
e59150dc
JB		 12541 /* BDW+ don't expose a synchronous way to read the state */
12542 if (IS_HASWELL(dev))
12543 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12544
282740f7
VS		 12545 PIPE_CONF_CHECK_I(double_wide);
12546
26804afd
DV		 12547 PIPE_CONF_CHECK_X(ddi_pll_sel);
12548
c0d43d62 12549 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12550 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12551 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12552 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12553 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12554 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12555 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12556 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12557 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12558
42571aef
VS		 12559 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12560 PIPE_CONF_CHECK_I(pipe_bpp);
12561
2d112de7 12562 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12563 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12564
66e985c0 12565#undef PIPE_CONF_CHECK_X
08a24034 12566#undef PIPE_CONF_CHECK_I
b95af8be 12567#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12568#undef PIPE_CONF_CHECK_FLAGS
5e550656 12569#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12570#undef PIPE_CONF_QUIRK
cfb23ed6 12571#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12572
cfb23ed6 12573 return ret;
0e8ffe1b
DV		 12574}
12575
08db6652
DL		 12576static void check_wm_state(struct drm_device *dev)
12577{
12578 struct drm_i915_private *dev_priv = dev->dev_private;
12579 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12580 struct intel_crtc *intel_crtc;
12581 int plane;
12582
12583 if (INTEL_INFO(dev)->gen < 9)
12584 return;
12585
12586 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12587 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12588
12589 for_each_intel_crtc(dev, intel_crtc) {
12590 struct skl_ddb_entry *hw_entry, *sw_entry;
12591 const enum pipe pipe = intel_crtc->pipe;
12592
12593 if (!intel_crtc->active)
12594 continue;
12595
12596 /* planes */
dd740780 12597 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12598 hw_entry = &hw_ddb.plane[pipe][plane];
12599 sw_entry = &sw_ddb->plane[pipe][plane];
12600
12601 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12602 continue;
12603
12604 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12605 "(expected (%u,%u), found (%u,%u))\n",
12606 pipe_name(pipe), plane + 1,
12607 sw_entry->start, sw_entry->end,
12608 hw_entry->start, hw_entry->end);
12609 }
12610
12611 /* cursor */
4969d33e
MR		 12612 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12613 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12614
12615 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12616 continue;
12617
12618 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12619 "(expected (%u,%u), found (%u,%u))\n",
12620 pipe_name(pipe),
12621 sw_entry->start, sw_entry->end,
12622 hw_entry->start, hw_entry->end);
12623 }
12624}
12625
91d1b4bd 12626static void
35dd3c64
ML		 12627check_connector_state(struct drm_device *dev,
12628 struct drm_atomic_state *old_state)
8af6cf88 12629{
35dd3c64
ML		 12630 struct drm_connector_state *old_conn_state;
12631 struct drm_connector *connector;
12632 int i;
8af6cf88 12633
35dd3c64
ML		 12634 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12635 struct drm_encoder *encoder = connector->encoder;
12636 struct drm_connector_state *state = connector->state;
ad3c558f 12637
8af6cf88
DV		 12638 /* This also checks the encoder/connector hw state with the
12639 * ->get_hw_state callbacks. */
35dd3c64 12640 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12641
ad3c558f 12642 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12643 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12644 }
91d1b4bd
DV		 12645}
12646
12647static void
12648check_encoder_state(struct drm_device *dev)
12649{
12650 struct intel_encoder *encoder;
12651 struct intel_connector *connector;
8af6cf88 12652
b2784e15 12653 for_each_intel_encoder(dev, encoder) {
8af6cf88 12654 bool enabled = false;
4d20cd86 12655 enum pipe pipe;
8af6cf88
DV		 12656
12657 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12658 encoder->base.base.id,
8e329a03 12659 encoder->base.name);
8af6cf88 12660
3a3371ff 12661 for_each_intel_connector(dev, connector) {
4d20cd86 12662 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12663 continue;
12664 enabled = true;
ad3c558f
ML		 12665
12666 I915_STATE_WARN(connector->base.state->crtc !=
12667 encoder->base.crtc,
12668 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12669 }
0e32b39c 12670
e2c719b7 12671 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12672 "encoder's enabled state mismatch "
12673 "(expected %i, found %i)\n",
12674 !!encoder->base.crtc, enabled);
7c60d198
ML		 12675
12676 if (!encoder->base.crtc) {
4d20cd86 12677 bool active;
7c60d198 12678
4d20cd86
ML		 12679 active = encoder->get_hw_state(encoder, &pipe);
12680 I915_STATE_WARN(active,
12681 "encoder detached but still enabled on pipe %c.\n",
12682 pipe_name(pipe));
7c60d198 12683 }
8af6cf88 12684 }
91d1b4bd
DV		 12685}
12686
12687static void
4d20cd86 12688check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12689{
fbee40df 12690 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12691 struct intel_encoder *encoder;
4d20cd86
ML		 12692 struct drm_crtc_state *old_crtc_state;
12693 struct drm_crtc *crtc;
12694 int i;
8af6cf88 12695
4d20cd86
ML		 12696 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12698 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12699 bool active;
8af6cf88 12700
bfd16b2a
ML		 12701 if (!needs_modeset(crtc->state) &&
12702 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12703 continue;
045ac3b5 12704
4d20cd86
ML		 12705 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12706 pipe_config = to_intel_crtc_state(old_crtc_state);
12707 memset(pipe_config, 0, sizeof(*pipe_config));
12708 pipe_config->base.crtc = crtc;
12709 pipe_config->base.state = old_state;
8af6cf88 12710
4d20cd86
ML		 12711 DRM_DEBUG_KMS("[CRTC:%d]\n",
12712 crtc->base.id);
8af6cf88 12713
4d20cd86
ML		 12714 active = dev_priv->display.get_pipe_config(intel_crtc,
12715 pipe_config);
d62cf62a 12716
b6b5d049 12717 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12718 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12719 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12720 active = crtc->state->active;
6c49f241 12721
4d20cd86 12722 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12723 "crtc active state doesn't match with hw state "
4d20cd86 12724 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12725
4d20cd86 12726 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12727 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12728 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12729
12730 for_each_encoder_on_crtc(dev, crtc, encoder) {
12731 enum pipe pipe;
12732
12733 active = encoder->get_hw_state(encoder, &pipe);
12734 I915_STATE_WARN(active != crtc->state->active,
12735 "[ENCODER:%i] active %i with crtc active %i\n",
12736 encoder->base.base.id, active, crtc->state->active);
12737
12738 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12739 "Encoder connected to wrong pipe %c\n",
12740 pipe_name(pipe));
12741
12742 if (active)
12743 encoder->get_config(encoder, pipe_config);
12744 }
53d9f4e9 12745
4d20cd86 12746 if (!crtc->state->active)
cfb23ed6
ML		 12747 continue;
12748
4d20cd86
ML		 12749 sw_config = to_intel_crtc_state(crtc->state);
12750 if (!intel_pipe_config_compare(dev, sw_config,
12751 pipe_config, false)) {
e2c719b7 12752 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12753 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12754 "[hw state]");
4d20cd86 12755 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12756 "[sw state]");
12757 }
8af6cf88
DV		 12758 }
12759}
12760
91d1b4bd
DV		 12761static void
12762check_shared_dpll_state(struct drm_device *dev)
12763{
fbee40df 12764 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12765 struct intel_crtc *crtc;
12766 struct intel_dpll_hw_state dpll_hw_state;
12767 int i;
5358901f
DV		 12768
12769 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12770 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12771 int enabled_crtcs = 0, active_crtcs = 0;
12772 bool active;
12773
12774 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12775
12776 DRM_DEBUG_KMS("%s\n", pll->name);
12777
12778 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12779
e2c719b7 12780 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12781 "more active pll users than references: %i vs %i\n",
3e369b76 12782 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12783 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12784 "pll in active use but not on in sw tracking\n");
e2c719b7 12785 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12786 "pll in on but not on in use in sw tracking\n");
e2c719b7 12787 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12788 "pll on state mismatch (expected %i, found %i)\n",
12789 pll->on, active);
12790
d3fcc808 12791 for_each_intel_crtc(dev, crtc) {
83d65738 12792 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12793 enabled_crtcs++;
12794 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12795 active_crtcs++;
12796 }
e2c719b7 12797 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12798 "pll active crtcs mismatch (expected %i, found %i)\n",
12799 pll->active, active_crtcs);
e2c719b7 12800 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12801 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12802 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12803
e2c719b7 12804 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12805 sizeof(dpll_hw_state)),
12806 "pll hw state mismatch\n");
5358901f 12807 }
8af6cf88
DV		 12808}
12809
ee165b1a
ML		 12810static void
12811intel_modeset_check_state(struct drm_device *dev,
12812 struct drm_atomic_state *old_state)
91d1b4bd 12813{
08db6652 12814 check_wm_state(dev);
35dd3c64 12815 check_connector_state(dev, old_state);
91d1b4bd 12816 check_encoder_state(dev);
4d20cd86 12817 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12818 check_shared_dpll_state(dev);
12819}
12820
5cec258b 12821void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12822 int dotclock)
12823{
12824 /*
12825 * FDI already provided one idea for the dotclock.
12826 * Yell if the encoder disagrees.
12827 */
2d112de7 12828 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12829 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12830 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12831}
12832
80715b2f
VS		 12833static void update_scanline_offset(struct intel_crtc *crtc)
12834{
12835 struct drm_device *dev = crtc->base.dev;
12836
12837 /*
12838 * The scanline counter increments at the leading edge of hsync.
12839 *
12840 * On most platforms it starts counting from vtotal-1 on the
12841 * first active line. That means the scanline counter value is
12842 * always one less than what we would expect. Ie. just after
12843 * start of vblank, which also occurs at start of hsync (on the
12844 * last active line), the scanline counter will read vblank_start-1.
12845 *
12846 * On gen2 the scanline counter starts counting from 1 instead
12847 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12848 * to keep the value positive), instead of adding one.
12849 *
12850 * On HSW+ the behaviour of the scanline counter depends on the output
12851 * type. For DP ports it behaves like most other platforms, but on HDMI
12852 * there's an extra 1 line difference. So we need to add two instead of
12853 * one to the value.
12854 */
12855 if (IS_GEN2(dev)) {
124abe07 12856 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12857 int vtotal;
12858
124abe07
VS		 12859 vtotal = adjusted_mode->crtc_vtotal;
12860 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12861 vtotal /= 2;
12862
12863 crtc->scanline_offset = vtotal - 1;
12864 } else if (HAS_DDI(dev) &&
409ee761 12865 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12866 crtc->scanline_offset = 2;
12867 } else
12868 crtc->scanline_offset = 1;
12869}
12870
ad421372 12871static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12872{
225da59b 12873 struct drm_device *dev = state->dev;
ed6739ef 12874 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12875 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12876 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12877 struct intel_crtc_state *intel_crtc_state;
12878 struct drm_crtc *crtc;
12879 struct drm_crtc_state *crtc_state;
0a9ab303 12880 int i;
ed6739ef
ACO		 12881
12882 if (!dev_priv->display.crtc_compute_clock)
ad421372 12883 return;
ed6739ef 12884
0a9ab303 12885 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12886 int dpll;
12887
0a9ab303 12888 intel_crtc = to_intel_crtc(crtc);
4978cc93 12889 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12890 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12891
ad421372 12892 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12893 continue;
12894
ad421372 12895 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12896
ad421372
ML		 12897 if (!shared_dpll)
12898 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12899
ad421372
ML		 12900 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12901 }
ed6739ef
ACO		 12902}
12903
99d736a2
ML		 12904/*
12905 * This implements the workaround described in the "notes" section of the mode
12906 * set sequence documentation. When going from no pipes or single pipe to
12907 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12908 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12909 */
12910static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12911{
12912 struct drm_crtc_state *crtc_state;
12913 struct intel_crtc *intel_crtc;
12914 struct drm_crtc *crtc;
12915 struct intel_crtc_state *first_crtc_state = NULL;
12916 struct intel_crtc_state *other_crtc_state = NULL;
12917 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12918 int i;
12919
12920 /* look at all crtc's that are going to be enabled in during modeset */
12921 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12922 intel_crtc = to_intel_crtc(crtc);
12923
12924 if (!crtc_state->active || !needs_modeset(crtc_state))
12925 continue;
12926
12927 if (first_crtc_state) {
12928 other_crtc_state = to_intel_crtc_state(crtc_state);
12929 break;
12930 } else {
12931 first_crtc_state = to_intel_crtc_state(crtc_state);
12932 first_pipe = intel_crtc->pipe;
12933 }
12934 }
12935
12936 /* No workaround needed? */
12937 if (!first_crtc_state)
12938 return 0;
12939
12940 /* w/a possibly needed, check how many crtc's are already enabled. */
12941 for_each_intel_crtc(state->dev, intel_crtc) {
12942 struct intel_crtc_state *pipe_config;
12943
12944 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12945 if (IS_ERR(pipe_config))
12946 return PTR_ERR(pipe_config);
12947
12948 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12949
12950 if (!pipe_config->base.active ||
12951 needs_modeset(&pipe_config->base))
12952 continue;
12953
12954 /* 2 or more enabled crtcs means no need for w/a */
12955 if (enabled_pipe != INVALID_PIPE)
12956 return 0;
12957
12958 enabled_pipe = intel_crtc->pipe;
12959 }
12960
12961 if (enabled_pipe != INVALID_PIPE)
12962 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12963 else if (other_crtc_state)
12964 other_crtc_state->hsw_workaround_pipe = first_pipe;
12965
12966 return 0;
12967}
12968
27c329ed
ML		 12969static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12970{
12971 struct drm_crtc *crtc;
12972 struct drm_crtc_state *crtc_state;
12973 int ret = 0;
12974
12975 /* add all active pipes to the state */
12976 for_each_crtc(state->dev, crtc) {
12977 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12978 if (IS_ERR(crtc_state))
12979 return PTR_ERR(crtc_state);
12980
12981 if (!crtc_state->active || needs_modeset(crtc_state))
12982 continue;
12983
12984 crtc_state->mode_changed = true;
12985
12986 ret = drm_atomic_add_affected_connectors(state, crtc);
12987 if (ret)
12988 break;
12989
12990 ret = drm_atomic_add_affected_planes(state, crtc);
12991 if (ret)
12992 break;
12993 }
12994
12995 return ret;
12996}
12997
c347a676 12998static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12999{
13000 struct drm_device *dev = state->dev;
27c329ed 13001 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13002 int ret;
13003
b359283a
ML		 13004 if (!check_digital_port_conflicts(state)) {
13005 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13006 return -EINVAL;
13007 }
13008
054518dd
ACO		 13009 /*
13010 * See if the config requires any additional preparation, e.g.
13011 * to adjust global state with pipes off. We need to do this
13012 * here so we can get the modeset_pipe updated config for the new
13013 * mode set on this crtc. For other crtcs we need to use the
13014 * adjusted_mode bits in the crtc directly.
13015 */
27c329ed
ML		 13016 if (dev_priv->display.modeset_calc_cdclk) {
13017 unsigned int cdclk;
b432e5cf 13018
27c329ed
ML		 13019 ret = dev_priv->display.modeset_calc_cdclk(state);
13020
13021 cdclk = to_intel_atomic_state(state)->cdclk;
13022 if (!ret && cdclk != dev_priv->cdclk_freq)
13023 ret = intel_modeset_all_pipes(state);
13024
13025 if (ret < 0)
054518dd 13026 return ret;
27c329ed
ML		 13027 } else
13028 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13029
ad421372 13030 intel_modeset_clear_plls(state);
054518dd 13031
99d736a2 13032 if (IS_HASWELL(dev))
ad421372 13033 return haswell_mode_set_planes_workaround(state);
99d736a2 13034
ad421372 13035 return 0;
c347a676
ACO		 13036}
13037
aa363136
MR		 13038/*
13039 * Handle calculation of various watermark data at the end of the atomic check
13040 * phase. The code here should be run after the per-crtc and per-plane 'check'
13041 * handlers to ensure that all derived state has been updated.
13042 */
13043static void calc_watermark_data(struct drm_atomic_state *state)
13044{
13045 struct drm_device *dev = state->dev;
13046 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13047 struct drm_crtc *crtc;
13048 struct drm_crtc_state *cstate;
13049 struct drm_plane *plane;
13050 struct drm_plane_state *pstate;
13051
13052 /*
13053 * Calculate watermark configuration details now that derived
13054 * plane/crtc state is all properly updated.
13055 */
13056 drm_for_each_crtc(crtc, dev) {
13057 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13058 crtc->state;
13059
13060 if (cstate->active)
13061 intel_state->wm_config.num_pipes_active++;
13062 }
13063 drm_for_each_legacy_plane(plane, dev) {
13064 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13065 plane->state;
13066
13067 if (!to_intel_plane_state(pstate)->visible)
13068 continue;
13069
13070 intel_state->wm_config.sprites_enabled = true;
13071 if (pstate->crtc_w != pstate->src_w >> 16 ||
13072 pstate->crtc_h != pstate->src_h >> 16)
13073 intel_state->wm_config.sprites_scaled = true;
13074 }
13075}
13076
74c090b1
ML		 13077/**
13078 * intel_atomic_check - validate state object
13079 * @dev: drm device
13080 * @state: state to validate
13081 */
13082static int intel_atomic_check(struct drm_device *dev,
13083 struct drm_atomic_state *state)
c347a676 13084{
aa363136 13085 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13086 struct drm_crtc *crtc;
13087 struct drm_crtc_state *crtc_state;
13088 int ret, i;
61333b60 13089 bool any_ms = false;
c347a676 13090
74c090b1 13091 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13092 if (ret)
13093 return ret;
13094
c347a676 13095 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13096 struct intel_crtc_state *pipe_config =
13097 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13098
13099 /* Catch I915_MODE_FLAG_INHERITED */
13100 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13101 crtc_state->mode_changed = true;
cfb23ed6 13102
61333b60
ML		 13103 if (!crtc_state->enable) {
13104 if (needs_modeset(crtc_state))
13105 any_ms = true;
c347a676 13106 continue;
61333b60 13107 }
c347a676 13108
26495481 13109 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13110 continue;
13111
26495481
DV		 13112 /* FIXME: For only active_changed we shouldn't need to do any
13113 * state recomputation at all. */
13114
1ed51de9
DV		 13115 ret = drm_atomic_add_affected_connectors(state, crtc);
13116 if (ret)
13117 return ret;
b359283a 13118
cfb23ed6 13119 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13120 if (ret)
13121 return ret;
13122
6764e9f8 13123 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13124 to_intel_crtc_state(crtc->state),
1ed51de9 13125 pipe_config, true)) {
26495481 13126 crtc_state->mode_changed = false;
bfd16b2a 13127 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13128 }
13129
13130 if (needs_modeset(crtc_state)) {
13131 any_ms = true;
cfb23ed6
ML		 13132
13133 ret = drm_atomic_add_affected_planes(state, crtc);
13134 if (ret)
13135 return ret;
13136 }
61333b60 13137
26495481
DV		 13138 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13139 needs_modeset(crtc_state) ?
13140 "[modeset]" : "[fastset]");
c347a676
ACO		 13141 }
13142
61333b60
ML		 13143 if (any_ms) {
13144 ret = intel_modeset_checks(state);
13145
13146 if (ret)
13147 return ret;
27c329ed 13148 } else
aa363136 13149 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
76305b1a 13150
aa363136
MR		 13151 ret = drm_atomic_helper_check_planes(state->dev, state);
13152 if (ret)
13153 return ret;
13154
13155 calc_watermark_data(state);
13156
13157 return 0;
054518dd
ACO		 13158}
13159
5008e874
ML		 13160static int intel_atomic_prepare_commit(struct drm_device *dev,
13161 struct drm_atomic_state *state,
13162 bool async)
13163{
7580d774
ML		 13164 struct drm_i915_private *dev_priv = dev->dev_private;
13165 struct drm_plane_state *plane_state;
5008e874 13166 struct drm_crtc_state *crtc_state;
7580d774 13167 struct drm_plane *plane;
5008e874
ML		 13168 struct drm_crtc *crtc;
13169 int i, ret;
13170
13171 if (async) {
13172 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13173 return -EINVAL;
13174 }
13175
13176 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13177 ret = intel_crtc_wait_for_pending_flips(crtc);
13178 if (ret)
13179 return ret;
7580d774
ML		 13180
13181 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13182 flush_workqueue(dev_priv->wq);
5008e874
ML		 13183 }
13184
f935675f
ML		 13185 ret = mutex_lock_interruptible(&dev->struct_mutex);
13186 if (ret)
13187 return ret;
13188
5008e874 13189 ret = drm_atomic_helper_prepare_planes(dev, state);
7580d774
ML		 13190 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13191 u32 reset_counter;
13192
13193 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13194 mutex_unlock(&dev->struct_mutex);
13195
13196 for_each_plane_in_state(state, plane, plane_state, i) {
13197 struct intel_plane_state *intel_plane_state =
13198 to_intel_plane_state(plane_state);
13199
13200 if (!intel_plane_state->wait_req)
13201 continue;
13202
13203 ret = __i915_wait_request(intel_plane_state->wait_req,
13204 reset_counter, true,
13205 NULL, NULL);
13206
13207 /* Swallow -EIO errors to allow updates during hw lockup. */
13208 if (ret == -EIO)
13209 ret = 0;
13210
13211 if (ret)
13212 break;
13213 }
13214
13215 if (!ret)
13216 return 0;
13217
13218 mutex_lock(&dev->struct_mutex);
13219 drm_atomic_helper_cleanup_planes(dev, state);
13220 }
5008e874 13221
f935675f 13222 mutex_unlock(&dev->struct_mutex);
5008e874
ML		 13223 return ret;
13224}
13225
74c090b1
ML		 13226/**
13227 * intel_atomic_commit - commit validated state object
13228 * @dev: DRM device
13229 * @state: the top-level driver state object
13230 * @async: asynchronous commit
13231 *
13232 * This function commits a top-level state object that has been validated
13233 * with drm_atomic_helper_check().
13234 *
13235 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13236 * we can only handle plane-related operations and do not yet support
13237 * asynchronous commit.
13238 *
13239 * RETURNS
13240 * Zero for success or -errno.
13241 */
13242static int intel_atomic_commit(struct drm_device *dev,
13243 struct drm_atomic_state *state,
13244 bool async)
a6778b3c 13245{
fbee40df 13246 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303 13247 struct drm_crtc_state *crtc_state;
7580d774 13248 struct drm_crtc *crtc;
c0c36b94 13249 int ret = 0;
0a9ab303 13250 int i;
61333b60 13251 bool any_ms = false;
a6778b3c 13252
5008e874 13253 ret = intel_atomic_prepare_commit(dev, state, async);
7580d774
ML		 13254 if (ret) {
13255 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
d4afb8cc 13256 return ret;
7580d774 13257 }
d4afb8cc 13258
1c5e19f8 13259 drm_atomic_helper_swap_state(dev, state);
aa363136 13260 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
1c5e19f8 13261
0a9ab303 13262 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13264
61333b60
ML		 13265 if (!needs_modeset(crtc->state))
13266 continue;
13267
13268 any_ms = true;
a539205a 13269 intel_pre_plane_update(intel_crtc);
460da916 13270
a539205a
ML		 13271 if (crtc_state->active) {
13272 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13273 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13274 intel_crtc->active = false;
13275 intel_disable_shared_dpll(intel_crtc);
a539205a 13276 }
b8cecdf5 13277 }
7758a113 13278
ea9d758d
DV		 13279 /* Only after disabling all output pipelines that will be changed can we
13280 * update the the output configuration. */
4740b0f2 13281 intel_modeset_update_crtc_state(state);
f6e5b160 13282
4740b0f2
ML		 13283 if (any_ms) {
13284 intel_shared_dpll_commit(state);
13285
13286 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13287 modeset_update_crtc_power_domains(state);
4740b0f2 13288 }
47fab737 13289
a6778b3c 13290 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13291 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13293 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13294 bool update_pipe = !modeset &&
13295 to_intel_crtc_state(crtc->state)->update_pipe;
13296 unsigned long put_domains = 0;
f6ac4b2a
ML		 13297
13298 if (modeset && crtc->state->active) {
a539205a
ML		 13299 update_scanline_offset(to_intel_crtc(crtc));
13300 dev_priv->display.crtc_enable(crtc);
13301 }
80715b2f 13302
bfd16b2a
ML		 13303 if (update_pipe) {
13304 put_domains = modeset_get_crtc_power_domains(crtc);
13305
13306 /* make sure intel_modeset_check_state runs */
13307 any_ms = true;
13308 }
13309
f6ac4b2a
ML		 13310 if (!modeset)
13311 intel_pre_plane_update(intel_crtc);
13312
6173ee28
ML		 13313 if (crtc->state->active &&
13314 (crtc->state->planes_changed || update_pipe))
62852622 13315 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13316
13317 if (put_domains)
13318 modeset_put_power_domains(dev_priv, put_domains);
13319
f6ac4b2a 13320 intel_post_plane_update(intel_crtc);
80715b2f 13321 }
a6778b3c 13322
a6778b3c 13323 /* FIXME: add subpixel order */
83a57153 13324
74c090b1 13325 drm_atomic_helper_wait_for_vblanks(dev, state);
f935675f
ML		 13326
13327 mutex_lock(&dev->struct_mutex);
d4afb8cc 13328 drm_atomic_helper_cleanup_planes(dev, state);
f935675f 13329 mutex_unlock(&dev->struct_mutex);
2bfb4627 13330
74c090b1 13331 if (any_ms)
ee165b1a
ML		 13332 intel_modeset_check_state(dev, state);
13333
13334 drm_atomic_state_free(state);
f30da187 13335
74c090b1 13336 return 0;
7f27126e
JB		 13337}
13338
c0c36b94
CW		 13339void intel_crtc_restore_mode(struct drm_crtc *crtc)
13340{
83a57153
ACO		 13341 struct drm_device *dev = crtc->dev;
13342 struct drm_atomic_state *state;
e694eb02 13343 struct drm_crtc_state *crtc_state;
2bfb4627 13344 int ret;
83a57153
ACO		 13345
13346 state = drm_atomic_state_alloc(dev);
13347 if (!state) {
e694eb02 13348 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13349 crtc->base.id);
13350 return;
13351 }
13352
e694eb02 13353 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13354
e694eb02
ML		 13355retry:
13356 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13357 ret = PTR_ERR_OR_ZERO(crtc_state);
13358 if (!ret) {
13359 if (!crtc_state->active)
13360 goto out;
83a57153 13361
e694eb02 13362 crtc_state->mode_changed = true;
74c090b1 13363 ret = drm_atomic_commit(state);
83a57153
ACO		 13364 }
13365
e694eb02
ML		 13366 if (ret == -EDEADLK) {
13367 drm_atomic_state_clear(state);
13368 drm_modeset_backoff(state->acquire_ctx);
13369 goto retry;
4ed9fb37 13370 }
4be07317 13371
2bfb4627 13372 if (ret)
e694eb02 13373out:
2bfb4627 13374 drm_atomic_state_free(state);
c0c36b94
CW		 13375}
13376
25c5b266
DV		 13377#undef for_each_intel_crtc_masked
13378
f6e5b160 13379static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13380 .gamma_set = intel_crtc_gamma_set,
74c090b1 13381 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13382 .destroy = intel_crtc_destroy,
13383 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13384 .atomic_duplicate_state = intel_crtc_duplicate_state,
13385 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13386};
13387
5358901f
DV		 13388static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13389 struct intel_shared_dpll *pll,
13390 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13391{
5358901f 13392 uint32_t val;
ee7b9f93 13393
f458ebbc 13394 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13395 return false;
13396
5358901f 13397 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13398 hw_state->dpll = val;
13399 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13400 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13401
13402 return val & DPLL_VCO_ENABLE;
13403}
13404
15bdd4cf
DV		 13405static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13406 struct intel_shared_dpll *pll)
13407{
3e369b76
ACO		 13408 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13409 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13410}
13411
e7b903d2
DV		 13412static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13413 struct intel_shared_dpll *pll)
13414{
e7b903d2 13415 /* PCH refclock must be enabled first */
89eff4be 13416 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13417
3e369b76 13418 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13419
13420 /* Wait for the clocks to stabilize. */
13421 POSTING_READ(PCH_DPLL(pll->id));
13422 udelay(150);
13423
13424 /* The pixel multiplier can only be updated once the
13425 * DPLL is enabled and the clocks are stable.
13426 *
13427 * So write it again.
13428 */
3e369b76 13429 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13430 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13431 udelay(200);
13432}
13433
13434static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13435 struct intel_shared_dpll *pll)
13436{
13437 struct drm_device *dev = dev_priv->dev;
13438 struct intel_crtc *crtc;
e7b903d2
DV		 13439
13440 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13441 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13442 if (intel_crtc_to_shared_dpll(crtc) == pll)
13443 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13444 }
13445
15bdd4cf
DV		 13446 I915_WRITE(PCH_DPLL(pll->id), 0);
13447 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13448 udelay(200);
13449}
13450
46edb027
DV		 13451static char *ibx_pch_dpll_names[] = {
13452 "PCH DPLL A",
13453 "PCH DPLL B",
13454};
13455
7c74ade1 13456static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13457{
e7b903d2 13458 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13459 int i;
13460
7c74ade1 13461 dev_priv->num_shared_dpll = 2;
ee7b9f93 13462
e72f9fbf 13463 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13464 dev_priv->shared_dplls[i].id = i;
13465 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13466 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13467 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13468 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13469 dev_priv->shared_dplls[i].get_hw_state =
13470 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13471 }
13472}
13473
7c74ade1
DV		 13474static void intel_shared_dpll_init(struct drm_device *dev)
13475{
e7b903d2 13476 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13477
9cd86933
DV		 13478 if (HAS_DDI(dev))
13479 intel_ddi_pll_init(dev);
13480 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13481 ibx_pch_dpll_init(dev);
13482 else
13483 dev_priv->num_shared_dpll = 0;
13484
13485 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13486}
13487
6beb8c23
MR		 13488/**
13489 * intel_prepare_plane_fb - Prepare fb for usage on plane
13490 * @plane: drm plane to prepare for
13491 * @fb: framebuffer to prepare for presentation
13492 *
13493 * Prepares a framebuffer for usage on a display plane. Generally this
13494 * involves pinning the underlying object and updating the frontbuffer tracking
13495 * bits. Some older platforms need special physical address handling for
13496 * cursor planes.
13497 *
f935675f
ML		 13498 * Must be called with struct_mutex held.
13499 *
6beb8c23
MR		 13500 * Returns 0 on success, negative error code on failure.
13501 */
13502int
13503intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13504 const struct drm_plane_state *new_state)
465c120c
MR		 13505{
13506 struct drm_device *dev = plane->dev;
844f9111 13507 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13508 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23 13509 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13510 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
6beb8c23 13511 int ret = 0;
465c120c 13512
1ee49399 13513 if (!obj && !old_obj)
465c120c
MR		 13514 return 0;
13515
5008e874
ML		 13516 if (old_obj) {
13517 struct drm_crtc_state *crtc_state =
13518 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13519
13520 /* Big Hammer, we also need to ensure that any pending
13521 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13522 * current scanout is retired before unpinning the old
13523 * framebuffer. Note that we rely on userspace rendering
13524 * into the buffer attached to the pipe they are waiting
13525 * on. If not, userspace generates a GPU hang with IPEHR
13526 * point to the MI_WAIT_FOR_EVENT.
13527 *
13528 * This should only fail upon a hung GPU, in which case we
13529 * can safely continue.
13530 */
13531 if (needs_modeset(crtc_state))
13532 ret = i915_gem_object_wait_rendering(old_obj, true);
13533
13534 /* Swallow -EIO errors to allow updates during hw lockup. */
13535 if (ret && ret != -EIO)
f935675f 13536 return ret;
5008e874
ML		 13537 }
13538
1ee49399
ML		 13539 if (!obj) {
13540 ret = 0;
13541 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR		 13542 INTEL_INFO(dev)->cursor_needs_physical) {
13543 int align = IS_I830(dev) ? 16 * 1024 : 256;
13544 ret = i915_gem_object_attach_phys(obj, align);
13545 if (ret)
13546 DRM_DEBUG_KMS("failed to attach phys object\n");
13547 } else {
7580d774 13548 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
6beb8c23 13549 }
465c120c 13550
7580d774
ML		 13551 if (ret == 0) {
13552 if (obj) {
13553 struct intel_plane_state *plane_state =
13554 to_intel_plane_state(new_state);
13555
13556 i915_gem_request_assign(&plane_state->wait_req,
13557 obj->last_write_req);
13558 }
13559
a9ff8714 13560 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774 13561 }
fdd508a6 13562
6beb8c23
MR		 13563 return ret;
13564}
13565
38f3ce3a
MR		 13566/**
13567 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13568 * @plane: drm plane to clean up for
13569 * @fb: old framebuffer that was on plane
13570 *
13571 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML		 13572 *
13573 * Must be called with struct_mutex held.
38f3ce3a
MR		 13574 */
13575void
13576intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13577 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13578{
13579 struct drm_device *dev = plane->dev;
1ee49399 13580 struct intel_plane *intel_plane = to_intel_plane(plane);
7580d774 13581 struct intel_plane_state *old_intel_state;
1ee49399
ML		 13582 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13583 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 13584
7580d774
ML		 13585 old_intel_state = to_intel_plane_state(old_state);
13586
1ee49399 13587 if (!obj && !old_obj)
38f3ce3a
MR		 13588 return;
13589
1ee49399
ML		 13590 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13591 !INTEL_INFO(dev)->cursor_needs_physical))
844f9111 13592 intel_unpin_fb_obj(old_state->fb, old_state);
1ee49399
ML		 13593
13594 /* prepare_fb aborted? */
13595 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13596 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13597 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774
ML		 13598
13599 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13600
465c120c
MR		 13601}
13602
6156a456
CK		 13603int
13604skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13605{
13606 int max_scale;
13607 struct drm_device *dev;
13608 struct drm_i915_private *dev_priv;
13609 int crtc_clock, cdclk;
13610
13611 if (!intel_crtc || !crtc_state)
13612 return DRM_PLANE_HELPER_NO_SCALING;
13613
13614 dev = intel_crtc->base.dev;
13615 dev_priv = dev->dev_private;
13616 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13617 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 13618
54bf1ce6 13619 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK		 13620 return DRM_PLANE_HELPER_NO_SCALING;
13621
13622 /*
13623 * skl max scale is lower of:
13624 * close to 3 but not 3, -1 is for that purpose
13625 * or
13626 * cdclk/crtc_clock
13627 */
13628 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13629
13630 return max_scale;
13631}
13632
465c120c 13633static int
3c692a41 13634intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13635 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13636 struct intel_plane_state *state)
13637{
2b875c22
MR		 13638 struct drm_crtc *crtc = state->base.crtc;
13639 struct drm_framebuffer *fb = state->base.fb;
6156a456 13640 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13641 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13642 bool can_position = false;
465c120c 13643
061e4b8d
ML		 13644 /* use scaler when colorkey is not required */
13645 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13646 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13647 min_scale = 1;
13648 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13649 can_position = true;
6156a456 13650 }
d8106366 13651
061e4b8d
ML		 13652 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13653 &state->dst, &state->clip,
da20eabd
ML		 13654 min_scale, max_scale,
13655 can_position, true,
13656 &state->visible);
14af293f
GP		 13657}
13658
13659static void
13660intel_commit_primary_plane(struct drm_plane *plane,
13661 struct intel_plane_state *state)
13662{
2b875c22
MR		 13663 struct drm_crtc *crtc = state->base.crtc;
13664 struct drm_framebuffer *fb = state->base.fb;
13665 struct drm_device *dev = plane->dev;
14af293f 13666 struct drm_i915_private *dev_priv = dev->dev_private;
14af293f 13667
ea2c67bb 13668 crtc = crtc ? crtc : plane->crtc;
ccc759dc 13669
d4b08630
ML		 13670 dev_priv->display.update_primary_plane(crtc, fb,
13671 state->src.x1 >> 16,
13672 state->src.y1 >> 16);
465c120c
MR		 13673}
13674
a8ad0d8e
ML		 13675static void
13676intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13677 struct drm_crtc *crtc)
a8ad0d8e
ML		 13678{
13679 struct drm_device *dev = plane->dev;
13680 struct drm_i915_private *dev_priv = dev->dev_private;
13681
a8ad0d8e
ML		 13682 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13683}
13684
613d2b27
ML		 13685static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13686 struct drm_crtc_state *old_crtc_state)
3c692a41 13687{
32b7eeec 13688 struct drm_device *dev = crtc->dev;
3c692a41 13689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13690 struct intel_crtc_state *old_intel_state =
13691 to_intel_crtc_state(old_crtc_state);
13692 bool modeset = needs_modeset(crtc->state);
3c692a41 13693
f015c551 13694 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13695 intel_update_watermarks(crtc);
3c692a41 13696
c34c9ee4 13697 /* Perform vblank evasion around commit operation */
62852622 13698 intel_pipe_update_start(intel_crtc);
0583236e 13699
bfd16b2a
ML		 13700 if (modeset)
13701 return;
13702
13703 if (to_intel_crtc_state(crtc->state)->update_pipe)
13704 intel_update_pipe_config(intel_crtc, old_intel_state);
13705 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13706 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13707}
13708
613d2b27
ML		 13709static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13710 struct drm_crtc_state *old_crtc_state)
32b7eeec 13711{
32b7eeec 13712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13713
62852622 13714 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13715}
13716
cf4c7c12 13717/**
4a3b8769
MR		 13718 * intel_plane_destroy - destroy a plane
13719 * @plane: plane to destroy
cf4c7c12 13720 *
4a3b8769
MR		 13721 * Common destruction function for all types of planes (primary, cursor,
13722 * sprite).
cf4c7c12 13723 */
4a3b8769 13724void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13725{
13726 struct intel_plane *intel_plane = to_intel_plane(plane);
13727 drm_plane_cleanup(plane);
13728 kfree(intel_plane);
13729}
13730
65a3fea0 13731const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13732 .update_plane = drm_atomic_helper_update_plane,
13733 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13734 .destroy = intel_plane_destroy,
c196e1d6 13735 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13736 .atomic_get_property = intel_plane_atomic_get_property,
13737 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13738 .atomic_duplicate_state = intel_plane_duplicate_state,
13739 .atomic_destroy_state = intel_plane_destroy_state,
13740
465c120c
MR		 13741};
13742
13743static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13744 int pipe)
13745{
13746 struct intel_plane *primary;
8e7d688b 13747 struct intel_plane_state *state;
465c120c 13748 const uint32_t *intel_primary_formats;
45e3743a 13749 unsigned int num_formats;
465c120c
MR		 13750
13751 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13752 if (primary == NULL)
13753 return NULL;
13754
8e7d688b
MR		 13755 state = intel_create_plane_state(&primary->base);
13756 if (!state) {
ea2c67bb
MR		 13757 kfree(primary);
13758 return NULL;
13759 }
8e7d688b 13760 primary->base.state = &state->base;
ea2c67bb 13761
465c120c
MR		 13762 primary->can_scale = false;
13763 primary->max_downscale = 1;
6156a456
CK		 13764 if (INTEL_INFO(dev)->gen >= 9) {
13765 primary->can_scale = true;
af99ceda 13766 state->scaler_id = -1;
6156a456 13767 }
465c120c
MR		 13768 primary->pipe = pipe;
13769 primary->plane = pipe;
a9ff8714 13770 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13771 primary->check_plane = intel_check_primary_plane;
13772 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13773 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13774 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13775 primary->plane = !pipe;
13776
6c0fd451
DL		 13777 if (INTEL_INFO(dev)->gen >= 9) {
13778 intel_primary_formats = skl_primary_formats;
13779 num_formats = ARRAY_SIZE(skl_primary_formats);
13780 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13781 intel_primary_formats = i965_primary_formats;
13782 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13783 } else {
13784 intel_primary_formats = i8xx_primary_formats;
13785 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13786 }
13787
13788 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13789 &intel_plane_funcs,
465c120c
MR		 13790 intel_primary_formats, num_formats,
13791 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13792
3b7a5119
SJ		 13793 if (INTEL_INFO(dev)->gen >= 4)
13794 intel_create_rotation_property(dev, primary);
48404c1e 13795
ea2c67bb
MR		 13796 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13797
465c120c
MR		 13798 return &primary->base;
13799}
13800
3b7a5119
SJ		 13801void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13802{
13803 if (!dev->mode_config.rotation_property) {
13804 unsigned long flags = BIT(DRM_ROTATE_0) |
13805 BIT(DRM_ROTATE_180);
13806
13807 if (INTEL_INFO(dev)->gen >= 9)
13808 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13809
13810 dev->mode_config.rotation_property =
13811 drm_mode_create_rotation_property(dev, flags);
13812 }
13813 if (dev->mode_config.rotation_property)
13814 drm_object_attach_property(&plane->base.base,
13815 dev->mode_config.rotation_property,
13816 plane->base.state->rotation);
13817}
13818
3d7d6510 13819static int
852e787c 13820intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13821 struct intel_crtc_state *crtc_state,
852e787c 13822 struct intel_plane_state *state)
3d7d6510 13823{
061e4b8d 13824 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13825 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13826 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13827 unsigned stride;
13828 int ret;
3d7d6510 13829
061e4b8d
ML		 13830 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13831 &state->dst, &state->clip,
3d7d6510
MR		 13832 DRM_PLANE_HELPER_NO_SCALING,
13833 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13834 true, true, &state->visible);
757f9a3e
GP		 13835 if (ret)
13836 return ret;
13837
757f9a3e
GP		 13838 /* if we want to turn off the cursor ignore width and height */
13839 if (!obj)
da20eabd 13840 return 0;
757f9a3e 13841
757f9a3e 13842 /* Check for which cursor types we support */
061e4b8d 13843 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13844 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13845 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13846 return -EINVAL;
13847 }
13848
ea2c67bb
MR		 13849 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13850 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13851 DRM_DEBUG_KMS("buffer is too small\n");
13852 return -ENOMEM;
13853 }
13854
3a656b54 13855 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13856 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13857 return -EINVAL;
32b7eeec
MR		 13858 }
13859
da20eabd 13860 return 0;
852e787c 13861}
3d7d6510 13862
a8ad0d8e
ML		 13863static void
13864intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13865 struct drm_crtc *crtc)
a8ad0d8e 13866{
a8ad0d8e
ML		 13867 intel_crtc_update_cursor(crtc, false);
13868}
13869
f4a2cf29 13870static void
852e787c
GP		 13871intel_commit_cursor_plane(struct drm_plane *plane,
13872 struct intel_plane_state *state)
13873{
2b875c22 13874 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13875 struct drm_device *dev = plane->dev;
13876 struct intel_crtc *intel_crtc;
2b875c22 13877 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13878 uint32_t addr;
852e787c 13879
ea2c67bb
MR		 13880 crtc = crtc ? crtc : plane->crtc;
13881 intel_crtc = to_intel_crtc(crtc);
13882
a912f12f
GP		 13883 if (intel_crtc->cursor_bo == obj)
13884 goto update;
4ed91096 13885
f4a2cf29 13886 if (!obj)
a912f12f 13887 addr = 0;
f4a2cf29 13888 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13889 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13890 else
a912f12f 13891 addr = obj->phys_handle->busaddr;
852e787c 13892
a912f12f
GP		 13893 intel_crtc->cursor_addr = addr;
13894 intel_crtc->cursor_bo = obj;
852e787c 13895
302d19ac 13896update:
62852622 13897 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13898}
13899
3d7d6510
MR		 13900static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13901 int pipe)
13902{
13903 struct intel_plane *cursor;
8e7d688b 13904 struct intel_plane_state *state;
3d7d6510
MR		 13905
13906 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13907 if (cursor == NULL)
13908 return NULL;
13909
8e7d688b
MR		 13910 state = intel_create_plane_state(&cursor->base);
13911 if (!state) {
ea2c67bb
MR		 13912 kfree(cursor);
13913 return NULL;
13914 }
8e7d688b 13915 cursor->base.state = &state->base;
ea2c67bb 13916
3d7d6510
MR		 13917 cursor->can_scale = false;
13918 cursor->max_downscale = 1;
13919 cursor->pipe = pipe;
13920 cursor->plane = pipe;
a9ff8714 13921 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13922 cursor->check_plane = intel_check_cursor_plane;
13923 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13924 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13925
13926 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13927 &intel_plane_funcs,
3d7d6510
MR		 13928 intel_cursor_formats,
13929 ARRAY_SIZE(intel_cursor_formats),
13930 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13931
13932 if (INTEL_INFO(dev)->gen >= 4) {
13933 if (!dev->mode_config.rotation_property)
13934 dev->mode_config.rotation_property =
13935 drm_mode_create_rotation_property(dev,
13936 BIT(DRM_ROTATE_0) |
13937 BIT(DRM_ROTATE_180));
13938 if (dev->mode_config.rotation_property)
13939 drm_object_attach_property(&cursor->base.base,
13940 dev->mode_config.rotation_property,
8e7d688b 13941 state->base.rotation);
4398ad45
VS		 13942 }
13943
af99ceda
CK		 13944 if (INTEL_INFO(dev)->gen >=9)
13945 state->scaler_id = -1;
13946
ea2c67bb
MR		 13947 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13948
3d7d6510
MR		 13949 return &cursor->base;
13950}
13951
549e2bfb
CK		 13952static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13953 struct intel_crtc_state *crtc_state)
13954{
13955 int i;
13956 struct intel_scaler *intel_scaler;
13957 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13958
13959 for (i = 0; i < intel_crtc->num_scalers; i++) {
13960 intel_scaler = &scaler_state->scalers[i];
13961 intel_scaler->in_use = 0;
549e2bfb
CK		 13962 intel_scaler->mode = PS_SCALER_MODE_DYN;
13963 }
13964
13965 scaler_state->scaler_id = -1;
13966}
13967
b358d0a6 13968static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13969{
fbee40df 13970 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13971 struct intel_crtc *intel_crtc;
f5de6e07 13972 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13973 struct drm_plane *primary = NULL;
13974 struct drm_plane *cursor = NULL;
465c120c 13975 int i, ret;
79e53945 13976
955382f3 13977 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13978 if (intel_crtc == NULL)
13979 return;
13980
f5de6e07
ACO		 13981 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13982 if (!crtc_state)
13983 goto fail;
550acefd
ACO		 13984 intel_crtc->config = crtc_state;
13985 intel_crtc->base.state = &crtc_state->base;
07878248 13986 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13987
549e2bfb
CK		 13988 /* initialize shared scalers */
13989 if (INTEL_INFO(dev)->gen >= 9) {
13990 if (pipe == PIPE_C)
13991 intel_crtc->num_scalers = 1;
13992 else
13993 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13994
13995 skl_init_scalers(dev, intel_crtc, crtc_state);
13996 }
13997
465c120c 13998 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13999 if (!primary)
14000 goto fail;
14001
14002 cursor = intel_cursor_plane_create(dev, pipe);
14003 if (!cursor)
14004 goto fail;
14005
465c120c 14006 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14007 cursor, &intel_crtc_funcs);
14008 if (ret)
14009 goto fail;
79e53945
JB		 14010
14011 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14012 for (i = 0; i < 256; i++) {
14013 intel_crtc->lut_r[i] = i;
14014 intel_crtc->lut_g[i] = i;
14015 intel_crtc->lut_b[i] = i;
14016 }
14017
1f1c2e24
VS		 14018 /*
14019 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14020 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14021 */
80824003
JB		 14022 intel_crtc->pipe = pipe;
14023 intel_crtc->plane = pipe;
3a77c4c4 14024 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14025 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14026 intel_crtc->plane = !pipe;
80824003
JB		 14027 }
14028
4b0e333e
CW		 14029 intel_crtc->cursor_base = ~0;
14030 intel_crtc->cursor_cntl = ~0;
dc41c154 14031 intel_crtc->cursor_size = ~0;
8d7849db 14032
852eb00d
VS		 14033 intel_crtc->wm.cxsr_allowed = true;
14034
22fd0fab
JB		 14035 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14036 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14037 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14038 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14039
79e53945 14040 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14041
14042 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14043 return;
14044
14045fail:
14046 if (primary)
14047 drm_plane_cleanup(primary);
14048 if (cursor)
14049 drm_plane_cleanup(cursor);
f5de6e07 14050 kfree(crtc_state);
3d7d6510 14051 kfree(intel_crtc);
79e53945
JB		 14052}
14053
752aa88a
JB		 14054enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14055{
14056 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14057 struct drm_device *dev = connector->base.dev;
752aa88a 14058
51fd371b 14059 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14060
d3babd3f 14061 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14062 return INVALID_PIPE;
14063
14064 return to_intel_crtc(encoder->crtc)->pipe;
14065}
14066
08d7b3d1 14067int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14068 struct drm_file *file)
08d7b3d1 14069{
08d7b3d1 14070 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14071 struct drm_crtc *drmmode_crtc;
c05422d5 14072 struct intel_crtc *crtc;
08d7b3d1 14073
7707e653 14074 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14075
7707e653 14076 if (!drmmode_crtc) {
08d7b3d1 14077 DRM_ERROR("no such CRTC id\n");
3f2c2057 14078 return -ENOENT;
08d7b3d1
CW		 14079 }
14080
7707e653 14081 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14082 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14083
c05422d5 14084 return 0;
08d7b3d1
CW		 14085}
14086
66a9278e 14087static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14088{
66a9278e
DV		 14089 struct drm_device *dev = encoder->base.dev;
14090 struct intel_encoder *source_encoder;
79e53945 14091 int index_mask = 0;
79e53945
JB		 14092 int entry = 0;
14093
b2784e15 14094 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14095 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14096 index_mask |= (1 << entry);
14097
79e53945
JB		 14098 entry++;
14099 }
4ef69c7a 14100
79e53945
JB		 14101 return index_mask;
14102}
14103
4d302442
CW		 14104static bool has_edp_a(struct drm_device *dev)
14105{
14106 struct drm_i915_private *dev_priv = dev->dev_private;
14107
14108 if (!IS_MOBILE(dev))
14109 return false;
14110
14111 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14112 return false;
14113
e3589908 14114 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14115 return false;
14116
14117 return true;
14118}
14119
84b4e042
JB		 14120static bool intel_crt_present(struct drm_device *dev)
14121{
14122 struct drm_i915_private *dev_priv = dev->dev_private;
14123
884497ed
DL		 14124 if (INTEL_INFO(dev)->gen >= 9)
14125 return false;
14126
cf404ce4 14127 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14128 return false;
14129
14130 if (IS_CHERRYVIEW(dev))
14131 return false;
14132
14133 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14134 return false;
14135
14136 return true;
14137}
14138
79e53945
JB		 14139static void intel_setup_outputs(struct drm_device *dev)
14140{
725e30ad 14141 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14142 struct intel_encoder *encoder;
cb0953d7 14143 bool dpd_is_edp = false;
79e53945 14144
c9093354 14145 intel_lvds_init(dev);
79e53945 14146
84b4e042 14147 if (intel_crt_present(dev))
79935fca 14148 intel_crt_init(dev);
cb0953d7 14149
c776eb2e
VK		 14150 if (IS_BROXTON(dev)) {
14151 /*
14152 * FIXME: Broxton doesn't support port detection via the
14153 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14154 * detect the ports.
14155 */
14156 intel_ddi_init(dev, PORT_A);
14157 intel_ddi_init(dev, PORT_B);
14158 intel_ddi_init(dev, PORT_C);
14159 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14160 int found;
14161
de31facd
JB		 14162 /*
14163 * Haswell uses DDI functions to detect digital outputs.
14164 * On SKL pre-D0 the strap isn't connected, so we assume
14165 * it's there.
14166 */
77179400 14167 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14168 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14169 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED		 14170 intel_ddi_init(dev, PORT_A);
14171
14172 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14173 * register */
14174 found = I915_READ(SFUSE_STRAP);
14175
14176 if (found & SFUSE_STRAP_DDIB_DETECTED)
14177 intel_ddi_init(dev, PORT_B);
14178 if (found & SFUSE_STRAP_DDIC_DETECTED)
14179 intel_ddi_init(dev, PORT_C);
14180 if (found & SFUSE_STRAP_DDID_DETECTED)
14181 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14182 /*
14183 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14184 */
ef11bdb3 14185 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV		 14186 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14187 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14188 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14189 intel_ddi_init(dev, PORT_E);
14190
0e72a5b5 14191 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14192 int found;
5d8a7752 14193 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14194
14195 if (has_edp_a(dev))
14196 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14197
dc0fa718 14198 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14199 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14200 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14201 if (!found)
e2debe91 14202 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14203 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14204 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14205 }
14206
dc0fa718 14207 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14208 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14209
dc0fa718 14210 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14211 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14212
5eb08b69 14213 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14214 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14215
270b3042 14216 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14217 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14218 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14219 /*
14220 * The DP_DETECTED bit is the latched state of the DDC
14221 * SDA pin at boot. However since eDP doesn't require DDC
14222 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14223 * eDP ports may have been muxed to an alternate function.
14224 * Thus we can't rely on the DP_DETECTED bit alone to detect
14225 * eDP ports. Consult the VBT as well as DP_DETECTED to
14226 * detect eDP ports.
14227 */
e66eb81d 14228 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14229 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14230 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14231 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14232 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14233 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14234
e66eb81d 14235 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14236 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14237 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14238 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14239 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14240 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14241
9418c1f1 14242 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14243 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14244 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14245 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14246 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14247 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14248 }
14249
3cfca973 14250 intel_dsi_init(dev);
09da55dc 14251 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14252 bool found = false;
7d57382e 14253
e2debe91 14254 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14255 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14256 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14257 if (!found && IS_G4X(dev)) {
b01f2c3a 14258 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14259 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14260 }
27185ae1 14261
3fec3d2f 14262 if (!found && IS_G4X(dev))
ab9d7c30 14263 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14264 }
13520b05
KH		 14265
14266 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14267
e2debe91 14268 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14269 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14270 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14271 }
27185ae1 14272
e2debe91 14273 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14274
3fec3d2f 14275 if (IS_G4X(dev)) {
b01f2c3a 14276 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14277 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14278 }
3fec3d2f 14279 if (IS_G4X(dev))
ab9d7c30 14280 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14281 }
27185ae1 14282
3fec3d2f 14283 if (IS_G4X(dev) &&
e7281eab 14284 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14285 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14286 } else if (IS_GEN2(dev))
79e53945
JB		 14287 intel_dvo_init(dev);
14288
103a196f 14289 if (SUPPORTS_TV(dev))
79e53945
JB		 14290 intel_tv_init(dev);
14291
0bc12bcb 14292 intel_psr_init(dev);
7c8f8a70 14293
b2784e15 14294 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14295 encoder->base.possible_crtcs = encoder->crtc_mask;
14296 encoder->base.possible_clones =
66a9278e 14297 intel_encoder_clones(encoder);
79e53945 14298 }
47356eb6 14299
dde86e2d 14300 intel_init_pch_refclk(dev);
270b3042
DV		 14301
14302 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14303}
14304
14305static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14306{
60a5ca01 14307 struct drm_device *dev = fb->dev;
79e53945 14308 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14309
ef2d633e 14310 drm_framebuffer_cleanup(fb);
60a5ca01 14311 mutex_lock(&dev->struct_mutex);
ef2d633e 14312 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14313 drm_gem_object_unreference(&intel_fb->obj->base);
14314 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14315 kfree(intel_fb);
14316}
14317
14318static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14319 struct drm_file *file,
79e53945
JB		 14320 unsigned int *handle)
14321{
14322 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14323 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14324
05394f39 14325 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14326}
14327
86c98588
RV		 14328static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14329 struct drm_file *file,
14330 unsigned flags, unsigned color,
14331 struct drm_clip_rect *clips,
14332 unsigned num_clips)
14333{
14334 struct drm_device *dev = fb->dev;
14335 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14336 struct drm_i915_gem_object *obj = intel_fb->obj;
14337
14338 mutex_lock(&dev->struct_mutex);
74b4ea1e 14339 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14340 mutex_unlock(&dev->struct_mutex);
14341
14342 return 0;
14343}
14344
79e53945
JB		 14345static const struct drm_framebuffer_funcs intel_fb_funcs = {
14346 .destroy = intel_user_framebuffer_destroy,
14347 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14348 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14349};
14350
b321803d
DL		 14351static
14352u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14353 uint32_t pixel_format)
14354{
14355 u32 gen = INTEL_INFO(dev)->gen;
14356
14357 if (gen >= 9) {
14358 /* "The stride in bytes must not exceed the of the size of 8K
14359 * pixels and 32K bytes."
14360 */
14361 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14362 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14363 return 32*1024;
14364 } else if (gen >= 4) {
14365 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14366 return 16*1024;
14367 else
14368 return 32*1024;
14369 } else if (gen >= 3) {
14370 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14371 return 8*1024;
14372 else
14373 return 16*1024;
14374 } else {
14375 /* XXX DSPC is limited to 4k tiled */
14376 return 8*1024;
14377 }
14378}
14379
b5ea642a
DV		 14380static int intel_framebuffer_init(struct drm_device *dev,
14381 struct intel_framebuffer *intel_fb,
14382 struct drm_mode_fb_cmd2 *mode_cmd,
14383 struct drm_i915_gem_object *obj)
79e53945 14384{
6761dd31 14385 unsigned int aligned_height;
79e53945 14386 int ret;
b321803d 14387 u32 pitch_limit, stride_alignment;
79e53945 14388
dd4916c5
DV		 14389 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14390
2a80eada
DV		 14391 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14392 /* Enforce that fb modifier and tiling mode match, but only for
14393 * X-tiled. This is needed for FBC. */
14394 if (!!(obj->tiling_mode == I915_TILING_X) !=
14395 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14396 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14397 return -EINVAL;
14398 }
14399 } else {
14400 if (obj->tiling_mode == I915_TILING_X)
14401 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14402 else if (obj->tiling_mode == I915_TILING_Y) {
14403 DRM_DEBUG("No Y tiling for legacy addfb\n");
14404 return -EINVAL;
14405 }
14406 }
14407
9a8f0a12
TU		 14408 /* Passed in modifier sanity checking. */
14409 switch (mode_cmd->modifier[0]) {
14410 case I915_FORMAT_MOD_Y_TILED:
14411 case I915_FORMAT_MOD_Yf_TILED:
14412 if (INTEL_INFO(dev)->gen < 9) {
14413 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14414 mode_cmd->modifier[0]);
14415 return -EINVAL;
14416 }
14417 case DRM_FORMAT_MOD_NONE:
14418 case I915_FORMAT_MOD_X_TILED:
14419 break;
14420 default:
c0f40428
JB		 14421 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14422 mode_cmd->modifier[0]);
57cd6508 14423 return -EINVAL;
c16ed4be 14424 }
57cd6508 14425
b321803d
DL		 14426 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14427 mode_cmd->pixel_format);
14428 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14429 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14430 mode_cmd->pitches[0], stride_alignment);
57cd6508 14431 return -EINVAL;
c16ed4be 14432 }
57cd6508 14433
b321803d
DL		 14434 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14435 mode_cmd->pixel_format);
a35cdaa0 14436 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14437 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14438 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14439 "tiled" : "linear",
a35cdaa0 14440 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14441 return -EINVAL;
c16ed4be 14442 }
5d7bd705 14443
2a80eada 14444 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14445 mode_cmd->pitches[0] != obj->stride) {
14446 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14447 mode_cmd->pitches[0], obj->stride);
5d7bd705 14448 return -EINVAL;
c16ed4be 14449 }
5d7bd705 14450
57779d06 14451 /* Reject formats not supported by any plane early. */
308e5bcb 14452 switch (mode_cmd->pixel_format) {
57779d06 14453 case DRM_FORMAT_C8:
04b3924d
VS		 14454 case DRM_FORMAT_RGB565:
14455 case DRM_FORMAT_XRGB8888:
14456 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14457 break;
14458 case DRM_FORMAT_XRGB1555:
c16ed4be 14459 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14460 DRM_DEBUG("unsupported pixel format: %s\n",
14461 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14462 return -EINVAL;
c16ed4be 14463 }
57779d06 14464 break;
57779d06 14465 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14466 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14467 DRM_DEBUG("unsupported pixel format: %s\n",
14468 drm_get_format_name(mode_cmd->pixel_format));
14469 return -EINVAL;
14470 }
14471 break;
14472 case DRM_FORMAT_XBGR8888:
04b3924d 14473 case DRM_FORMAT_XRGB2101010:
57779d06 14474 case DRM_FORMAT_XBGR2101010:
c16ed4be 14475 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14476 DRM_DEBUG("unsupported pixel format: %s\n",
14477 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14478 return -EINVAL;
c16ed4be 14479 }
b5626747 14480 break;
7531208b
DL		 14481 case DRM_FORMAT_ABGR2101010:
14482 if (!IS_VALLEYVIEW(dev)) {
14483 DRM_DEBUG("unsupported pixel format: %s\n",
14484 drm_get_format_name(mode_cmd->pixel_format));
14485 return -EINVAL;
14486 }
14487 break;
04b3924d
VS		 14488 case DRM_FORMAT_YUYV:
14489 case DRM_FORMAT_UYVY:
14490 case DRM_FORMAT_YVYU:
14491 case DRM_FORMAT_VYUY:
c16ed4be 14492 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14493 DRM_DEBUG("unsupported pixel format: %s\n",
14494 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14495 return -EINVAL;
c16ed4be 14496 }
57cd6508
CW		 14497 break;
14498 default:
4ee62c76
VS		 14499 DRM_DEBUG("unsupported pixel format: %s\n",
14500 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14501 return -EINVAL;
14502 }
14503
90f9a336
VS		 14504 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14505 if (mode_cmd->offsets[0] != 0)
14506 return -EINVAL;
14507
ec2c981e 14508 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14509 mode_cmd->pixel_format,
14510 mode_cmd->modifier[0]);
53155c0a
DV		 14511 /* FIXME drm helper for size checks (especially planar formats)? */
14512 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14513 return -EINVAL;
14514
c7d73f6a
DV		 14515 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14516 intel_fb->obj = obj;
80075d49 14517 intel_fb->obj->framebuffer_references++;
c7d73f6a 14518
79e53945
JB		 14519 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14520 if (ret) {
14521 DRM_ERROR("framebuffer init failed %d\n", ret);
14522 return ret;
14523 }
14524
79e53945
JB		 14525 return 0;
14526}
14527
79e53945
JB		 14528static struct drm_framebuffer *
14529intel_user_framebuffer_create(struct drm_device *dev,
14530 struct drm_file *filp,
308e5bcb 14531 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14532{
05394f39 14533 struct drm_i915_gem_object *obj;
79e53945 14534
308e5bcb
JB		 14535 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14536 mode_cmd->handles[0]));
c8725226 14537 if (&obj->base == NULL)
cce13ff7 14538 return ERR_PTR(-ENOENT);
79e53945 14539
d2dff872 14540 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14541}
14542
0695726e 14543#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14544static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14545{
14546}
14547#endif
14548
79e53945 14549static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14550 .fb_create = intel_user_framebuffer_create,
0632fef6 14551 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14552 .atomic_check = intel_atomic_check,
14553 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14554 .atomic_state_alloc = intel_atomic_state_alloc,
14555 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14556};
14557
e70236a8
JB		 14558/* Set up chip specific display functions */
14559static void intel_init_display(struct drm_device *dev)
14560{
14561 struct drm_i915_private *dev_priv = dev->dev_private;
14562
ee9300bb
DV		 14563 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14564 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14565 else if (IS_CHERRYVIEW(dev))
14566 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14567 else if (IS_VALLEYVIEW(dev))
14568 dev_priv->display.find_dpll = vlv_find_best_dpll;
14569 else if (IS_PINEVIEW(dev))
14570 dev_priv->display.find_dpll = pnv_find_best_dpll;
14571 else
14572 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14573
bc8d7dff
DL		 14574 if (INTEL_INFO(dev)->gen >= 9) {
14575 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14576 dev_priv->display.get_initial_plane_config =
14577 skylake_get_initial_plane_config;
bc8d7dff
DL		 14578 dev_priv->display.crtc_compute_clock =
14579 haswell_crtc_compute_clock;
14580 dev_priv->display.crtc_enable = haswell_crtc_enable;
14581 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14582 dev_priv->display.update_primary_plane =
14583 skylake_update_primary_plane;
14584 } else if (HAS_DDI(dev)) {
0e8ffe1b 14585 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14586 dev_priv->display.get_initial_plane_config =
14587 ironlake_get_initial_plane_config;
797d0259
ACO		 14588 dev_priv->display.crtc_compute_clock =
14589 haswell_crtc_compute_clock;
4f771f10
PZ		 14590 dev_priv->display.crtc_enable = haswell_crtc_enable;
14591 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14592 dev_priv->display.update_primary_plane =
14593 ironlake_update_primary_plane;
09b4ddf9 14594 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14595 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14596 dev_priv->display.get_initial_plane_config =
14597 ironlake_get_initial_plane_config;
3fb37703
ACO		 14598 dev_priv->display.crtc_compute_clock =
14599 ironlake_crtc_compute_clock;
76e5a89c
DV		 14600 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14601 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14602 dev_priv->display.update_primary_plane =
14603 ironlake_update_primary_plane;
89b667f8
JB		 14604 } else if (IS_VALLEYVIEW(dev)) {
14605 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14606 dev_priv->display.get_initial_plane_config =
14607 i9xx_get_initial_plane_config;
d6dfee7a 14608 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14609 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14610 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14611 dev_priv->display.update_primary_plane =
14612 i9xx_update_primary_plane;
f564048e 14613 } else {
0e8ffe1b 14614 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14615 dev_priv->display.get_initial_plane_config =
14616 i9xx_get_initial_plane_config;
d6dfee7a 14617 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14618 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14619 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14620 dev_priv->display.update_primary_plane =
14621 i9xx_update_primary_plane;
f564048e 14622 }
e70236a8 14623
e70236a8 14624 /* Returns the core display clock speed */
ef11bdb3 14625 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1652d19e
VS		 14626 dev_priv->display.get_display_clock_speed =
14627 skylake_get_display_clock_speed;
acd3f3d3
BP		 14628 else if (IS_BROXTON(dev))
14629 dev_priv->display.get_display_clock_speed =
14630 broxton_get_display_clock_speed;
1652d19e
VS		 14631 else if (IS_BROADWELL(dev))
14632 dev_priv->display.get_display_clock_speed =
14633 broadwell_get_display_clock_speed;
14634 else if (IS_HASWELL(dev))
14635 dev_priv->display.get_display_clock_speed =
14636 haswell_get_display_clock_speed;
14637 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14638 dev_priv->display.get_display_clock_speed =
14639 valleyview_get_display_clock_speed;
b37a6434
VS		 14640 else if (IS_GEN5(dev))
14641 dev_priv->display.get_display_clock_speed =
14642 ilk_get_display_clock_speed;
a7c66cd8 14643 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14644 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14645 dev_priv->display.get_display_clock_speed =
14646 i945_get_display_clock_speed;
34edce2f
VS		 14647 else if (IS_GM45(dev))
14648 dev_priv->display.get_display_clock_speed =
14649 gm45_get_display_clock_speed;
14650 else if (IS_CRESTLINE(dev))
14651 dev_priv->display.get_display_clock_speed =
14652 i965gm_get_display_clock_speed;
14653 else if (IS_PINEVIEW(dev))
14654 dev_priv->display.get_display_clock_speed =
14655 pnv_get_display_clock_speed;
14656 else if (IS_G33(dev) || IS_G4X(dev))
14657 dev_priv->display.get_display_clock_speed =
14658 g33_get_display_clock_speed;
e70236a8
JB		 14659 else if (IS_I915G(dev))
14660 dev_priv->display.get_display_clock_speed =
14661 i915_get_display_clock_speed;
257a7ffc 14662 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14663 dev_priv->display.get_display_clock_speed =
14664 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14665 else if (IS_PINEVIEW(dev))
14666 dev_priv->display.get_display_clock_speed =
14667 pnv_get_display_clock_speed;
e70236a8
JB		 14668 else if (IS_I915GM(dev))
14669 dev_priv->display.get_display_clock_speed =
14670 i915gm_get_display_clock_speed;
14671 else if (IS_I865G(dev))
14672 dev_priv->display.get_display_clock_speed =
14673 i865_get_display_clock_speed;
f0f8a9ce 14674 else if (IS_I85X(dev))
e70236a8 14675 dev_priv->display.get_display_clock_speed =
1b1d2716 14676 i85x_get_display_clock_speed;
623e01e5
VS		 14677 else { /* 830 */
14678 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14679 dev_priv->display.get_display_clock_speed =
14680 i830_get_display_clock_speed;
623e01e5 14681 }
e70236a8 14682
7c10a2b5 14683 if (IS_GEN5(dev)) {
3bb11b53 14684 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14685 } else if (IS_GEN6(dev)) {
14686 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14687 } else if (IS_IVYBRIDGE(dev)) {
14688 /* FIXME: detect B0+ stepping and use auto training */
14689 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14690 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14691 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14692 if (IS_BROADWELL(dev)) {
14693 dev_priv->display.modeset_commit_cdclk =
14694 broadwell_modeset_commit_cdclk;
14695 dev_priv->display.modeset_calc_cdclk =
14696 broadwell_modeset_calc_cdclk;
14697 }
30a970c6 14698 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14699 dev_priv->display.modeset_commit_cdclk =
14700 valleyview_modeset_commit_cdclk;
14701 dev_priv->display.modeset_calc_cdclk =
14702 valleyview_modeset_calc_cdclk;
f8437dd1 14703 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14704 dev_priv->display.modeset_commit_cdclk =
14705 broxton_modeset_commit_cdclk;
14706 dev_priv->display.modeset_calc_cdclk =
14707 broxton_modeset_calc_cdclk;
e70236a8 14708 }
8c9f3aaf 14709
8c9f3aaf
JB		 14710 switch (INTEL_INFO(dev)->gen) {
14711 case 2:
14712 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14713 break;
14714
14715 case 3:
14716 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14717 break;
14718
14719 case 4:
14720 case 5:
14721 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14722 break;
14723
14724 case 6:
14725 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14726 break;
7c9017e5 14727 case 7:
4e0bbc31 14728 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14729 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14730 break;
830c81db 14731 case 9:
ba343e02
TU		 14732 /* Drop through - unsupported since execlist only. */
14733 default:
14734 /* Default just returns -ENODEV to indicate unsupported */
14735 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14736 }
7bd688cd 14737
e39b999a 14738 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14739}
14740
b690e96c
JB		 14741/*
14742 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14743 * resume, or other times. This quirk makes sure that's the case for
14744 * affected systems.
14745 */
0206e353 14746static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14747{
14748 struct drm_i915_private *dev_priv = dev->dev_private;
14749
14750 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14751 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14752}
14753
b6b5d049
VS		 14754static void quirk_pipeb_force(struct drm_device *dev)
14755{
14756 struct drm_i915_private *dev_priv = dev->dev_private;
14757
14758 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14759 DRM_INFO("applying pipe b force quirk\n");
14760}
14761
435793df
KP		 14762/*
14763 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14764 */
14765static void quirk_ssc_force_disable(struct drm_device *dev)
14766{
14767 struct drm_i915_private *dev_priv = dev->dev_private;
14768 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14769 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14770}
14771
4dca20ef 14772/*
5a15ab5b
CE		 14773 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14774 * brightness value
4dca20ef
CE		 14775 */
14776static void quirk_invert_brightness(struct drm_device *dev)
14777{
14778 struct drm_i915_private *dev_priv = dev->dev_private;
14779 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14780 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14781}
14782
9c72cc6f
SD		 14783/* Some VBT's incorrectly indicate no backlight is present */
14784static void quirk_backlight_present(struct drm_device *dev)
14785{
14786 struct drm_i915_private *dev_priv = dev->dev_private;
14787 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14788 DRM_INFO("applying backlight present quirk\n");
14789}
14790
b690e96c
JB		 14791struct intel_quirk {
14792 int device;
14793 int subsystem_vendor;
14794 int subsystem_device;
14795 void (*hook)(struct drm_device *dev);
14796};
14797
5f85f176
EE		 14798/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14799struct intel_dmi_quirk {
14800 void (*hook)(struct drm_device *dev);
14801 const struct dmi_system_id (*dmi_id_list)[];
14802};
14803
14804static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14805{
14806 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14807 return 1;
14808}
14809
14810static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14811 {
14812 .dmi_id_list = &(const struct dmi_system_id[]) {
14813 {
14814 .callback = intel_dmi_reverse_brightness,
14815 .ident = "NCR Corporation",
14816 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14817 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14818 },
14819 },
14820 { } /* terminating entry */
14821 },
14822 .hook = quirk_invert_brightness,
14823 },
14824};
14825
c43b5634 14826static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14827 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14828 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14829
b690e96c
JB		 14830 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14831 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14832
5f080c0f
VS		 14833 /* 830 needs to leave pipe A & dpll A up */
14834 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14835
b6b5d049
VS		 14836 /* 830 needs to leave pipe B & dpll B up */
14837 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14838
435793df
KP		 14839 /* Lenovo U160 cannot use SSC on LVDS */
14840 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14841
14842 /* Sony Vaio Y cannot use SSC on LVDS */
14843 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14844
be505f64
AH		 14845 /* Acer Aspire 5734Z must invert backlight brightness */
14846 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14847
14848 /* Acer/eMachines G725 */
14849 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14850
14851 /* Acer/eMachines e725 */
14852 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14853
14854 /* Acer/Packard Bell NCL20 */
14855 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14856
14857 /* Acer Aspire 4736Z */
14858 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14859
14860 /* Acer Aspire 5336 */
14861 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14862
14863 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14864 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14865
dfb3d47b
SD		 14866 /* Acer C720 Chromebook (Core i3 4005U) */
14867 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14868
b2a9601c 14869 /* Apple Macbook 2,1 (Core 2 T7400) */
14870 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14871
d4967d8c
SD		 14872 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14873 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14874
14875 /* HP Chromebook 14 (Celeron 2955U) */
14876 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14877
14878 /* Dell Chromebook 11 */
14879 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14880};
14881
14882static void intel_init_quirks(struct drm_device *dev)
14883{
14884 struct pci_dev *d = dev->pdev;
14885 int i;
14886
14887 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14888 struct intel_quirk *q = &intel_quirks[i];
14889
14890 if (d->device == q->device &&
14891 (d->subsystem_vendor == q->subsystem_vendor ||
14892 q->subsystem_vendor == PCI_ANY_ID) &&
14893 (d->subsystem_device == q->subsystem_device ||
14894 q->subsystem_device == PCI_ANY_ID))
14895 q->hook(dev);
14896 }
5f85f176
EE		 14897 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14898 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14899 intel_dmi_quirks[i].hook(dev);
14900 }
b690e96c
JB		 14901}
14902
9cce37f4
JB		 14903/* Disable the VGA plane that we never use */
14904static void i915_disable_vga(struct drm_device *dev)
14905{
14906 struct drm_i915_private *dev_priv = dev->dev_private;
14907 u8 sr1;
766aa1c4 14908 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14909
2b37c616 14910 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14911 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14912 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14913 sr1 = inb(VGA_SR_DATA);
14914 outb(sr1 | 1<<5, VGA_SR_DATA);
14915 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14916 udelay(300);
14917
01f5a626 14918 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14919 POSTING_READ(vga_reg);
14920}
14921
f817586c
DV		 14922void intel_modeset_init_hw(struct drm_device *dev)
14923{
b6283055 14924 intel_update_cdclk(dev);
a8f78b58 14925 intel_prepare_ddi(dev);
f817586c 14926 intel_init_clock_gating(dev);
8090c6b9 14927 intel_enable_gt_powersave(dev);
f817586c
DV		 14928}
14929
79e53945
JB		 14930void intel_modeset_init(struct drm_device *dev)
14931{
652c393a 14932 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14933 int sprite, ret;
8cc87b75 14934 enum pipe pipe;
46f297fb 14935 struct intel_crtc *crtc;
79e53945
JB		 14936
14937 drm_mode_config_init(dev);
14938
14939 dev->mode_config.min_width = 0;
14940 dev->mode_config.min_height = 0;
14941
019d96cb
DA		 14942 dev->mode_config.preferred_depth = 24;
14943 dev->mode_config.prefer_shadow = 1;
14944
25bab385
TU		 14945 dev->mode_config.allow_fb_modifiers = true;
14946
e6ecefaa 14947 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14948
b690e96c
JB		 14949 intel_init_quirks(dev);
14950
1fa61106
ED		 14951 intel_init_pm(dev);
14952
e3c74757
BW		 14953 if (INTEL_INFO(dev)->num_pipes == 0)
14954 return;
14955
69f92f67
LW		 14956 /*
14957 * There may be no VBT; and if the BIOS enabled SSC we can
14958 * just keep using it to avoid unnecessary flicker. Whereas if the
14959 * BIOS isn't using it, don't assume it will work even if the VBT
14960 * indicates as much.
14961 */
14962 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14963 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14964 DREF_SSC1_ENABLE);
14965
14966 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14967 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14968 bios_lvds_use_ssc ? "en" : "dis",
14969 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14970 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14971 }
14972 }
14973
e70236a8 14974 intel_init_display(dev);
7c10a2b5 14975 intel_init_audio(dev);
e70236a8 14976
a6c45cf0
CW		 14977 if (IS_GEN2(dev)) {
14978 dev->mode_config.max_width = 2048;
14979 dev->mode_config.max_height = 2048;
14980 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14981 dev->mode_config.max_width = 4096;
14982 dev->mode_config.max_height = 4096;
79e53945 14983 } else {
a6c45cf0
CW		 14984 dev->mode_config.max_width = 8192;
14985 dev->mode_config.max_height = 8192;
79e53945 14986 }
068be561 14987
dc41c154
VS		 14988 if (IS_845G(dev) || IS_I865G(dev)) {
14989 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14990 dev->mode_config.cursor_height = 1023;
14991 } else if (IS_GEN2(dev)) {
068be561
DL		 14992 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14993 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14994 } else {
14995 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14996 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14997 }
14998
5d4545ae 14999 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15000
28c97730 15001 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15002 INTEL_INFO(dev)->num_pipes,
15003 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15004
055e393f 15005 for_each_pipe(dev_priv, pipe) {
8cc87b75 15006 intel_crtc_init(dev, pipe);
3bdcfc0c 15007 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15008 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15009 if (ret)
06da8da2 15010 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15011 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15012 }
79e53945
JB		 15013 }
15014
bfa7df01
VS		 15015 intel_update_czclk(dev_priv);
15016 intel_update_cdclk(dev);
15017
e72f9fbf 15018 intel_shared_dpll_init(dev);
ee7b9f93 15019
9cce37f4
JB		 15020 /* Just disable it once at startup */
15021 i915_disable_vga(dev);
79e53945 15022 intel_setup_outputs(dev);
11be49eb
CW		 15023
15024 /* Just in case the BIOS is doing something questionable. */
7733b49b 15025 intel_fbc_disable(dev_priv);
fa9fa083 15026
6e9f798d 15027 drm_modeset_lock_all(dev);
043e9bda 15028 intel_modeset_setup_hw_state(dev);
6e9f798d 15029 drm_modeset_unlock_all(dev);
46f297fb 15030
d3fcc808 15031 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 15032 struct intel_initial_plane_config plane_config = {};
15033
46f297fb
JB		 15034 if (!crtc->active)
15035 continue;
15036
46f297fb 15037 /*
46f297fb
JB		 15038 * Note that reserving the BIOS fb up front prevents us
15039 * from stuffing other stolen allocations like the ring
15040 * on top. This prevents some ugliness at boot time, and
15041 * can even allow for smooth boot transitions if the BIOS
15042 * fb is large enough for the active pipe configuration.
15043 */
eeebeac5
ML		 15044 dev_priv->display.get_initial_plane_config(crtc,
15045 &plane_config);
15046
15047 /*
15048 * If the fb is shared between multiple heads, we'll
15049 * just get the first one.
15050 */
15051 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15052 }
2c7111db
CW		 15053}
15054
7fad798e
DV		 15055static void intel_enable_pipe_a(struct drm_device *dev)
15056{
15057 struct intel_connector *connector;
15058 struct drm_connector *crt = NULL;
15059 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15060 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15061
15062 /* We can't just switch on the pipe A, we need to set things up with a
15063 * proper mode and output configuration. As a gross hack, enable pipe A
15064 * by enabling the load detect pipe once. */
3a3371ff 15065 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15066 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15067 crt = &connector->base;
15068 break;
15069 }
15070 }
15071
15072 if (!crt)
15073 return;
15074
208bf9fd 15075 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15076 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15077}
15078
fa555837
DV		 15079static bool
15080intel_check_plane_mapping(struct intel_crtc *crtc)
15081{
7eb552ae
BW		 15082 struct drm_device *dev = crtc->base.dev;
15083 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15084 u32 val;
fa555837 15085
7eb552ae 15086 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15087 return true;
15088
649636ef 15089 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV		 15090
15091 if ((val & DISPLAY_PLANE_ENABLE) &&
15092 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15093 return false;
15094
15095 return true;
15096}
15097
02e93c35
VS		 15098static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15099{
15100 struct drm_device *dev = crtc->base.dev;
15101 struct intel_encoder *encoder;
15102
15103 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15104 return true;
15105
15106 return false;
15107}
15108
24929352
DV		 15109static void intel_sanitize_crtc(struct intel_crtc *crtc)
15110{
15111 struct drm_device *dev = crtc->base.dev;
15112 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15113 u32 reg;
24929352 15114
24929352 15115 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15116 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15117 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15118
d3eaf884 15119 /* restore vblank interrupts to correct state */
9625604c 15120 drm_crtc_vblank_reset(&crtc->base);
d297e103 15121 if (crtc->active) {
f9cd7b88
VS		 15122 struct intel_plane *plane;
15123
9625604c 15124 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15125
15126 /* Disable everything but the primary plane */
15127 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15128 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15129 continue;
15130
15131 plane->disable_plane(&plane->base, &crtc->base);
15132 }
9625604c 15133 }
d3eaf884 15134
24929352 15135 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15136 * disable the crtc (and hence change the state) if it is wrong. Note
15137 * that gen4+ has a fixed plane -> pipe mapping. */
15138 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15139 bool plane;
15140
24929352
DV		 15141 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15142 crtc->base.base.id);
15143
15144 /* Pipe has the wrong plane attached and the plane is active.
15145 * Temporarily change the plane mapping and disable everything
15146 * ... */
15147 plane = crtc->plane;
b70709a6 15148 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15149 crtc->plane = !plane;
b17d48e2 15150 intel_crtc_disable_noatomic(&crtc->base);
24929352 15151 crtc->plane = plane;
24929352 15152 }
24929352 15153
7fad798e
DV		 15154 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15155 crtc->pipe == PIPE_A && !crtc->active) {
15156 /* BIOS forgot to enable pipe A, this mostly happens after
15157 * resume. Force-enable the pipe to fix this, the update_dpms
15158 * call below we restore the pipe to the right state, but leave
15159 * the required bits on. */
15160 intel_enable_pipe_a(dev);
15161 }
15162
24929352
DV		 15163 /* Adjust the state of the output pipe according to whether we
15164 * have active connectors/encoders. */
02e93c35 15165 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15166 intel_crtc_disable_noatomic(&crtc->base);
24929352 15167
53d9f4e9 15168 if (crtc->active != crtc->base.state->active) {
02e93c35 15169 struct intel_encoder *encoder;
24929352
DV		 15170
15171 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15172 * functions or because of calls to intel_crtc_disable_noatomic,
15173 * or because the pipe is force-enabled due to the
24929352
DV		 15174 * pipe A quirk. */
15175 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15176 crtc->base.base.id,
83d65738 15177 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15178 crtc->active ? "enabled" : "disabled");
15179
4be40c98 15180 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15181 crtc->base.state->active = crtc->active;
24929352
DV		 15182 crtc->base.enabled = crtc->active;
15183
15184 /* Because we only establish the connector -> encoder ->
15185 * crtc links if something is active, this means the
15186 * crtc is now deactivated. Break the links. connector
15187 * -> encoder links are only establish when things are
15188 * actually up, hence no need to break them. */
15189 WARN_ON(crtc->active);
15190
2d406bb0 15191 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15192 encoder->base.crtc = NULL;
24929352 15193 }
c5ab3bc0 15194
a3ed6aad 15195 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15196 /*
15197 * We start out with underrun reporting disabled to avoid races.
15198 * For correct bookkeeping mark this on active crtcs.
15199 *
c5ab3bc0
DV		 15200 * Also on gmch platforms we dont have any hardware bits to
15201 * disable the underrun reporting. Which means we need to start
15202 * out with underrun reporting disabled also on inactive pipes,
15203 * since otherwise we'll complain about the garbage we read when
15204 * e.g. coming up after runtime pm.
15205 *
4cc31489
DV		 15206 * No protection against concurrent access is required - at
15207 * worst a fifo underrun happens which also sets this to false.
15208 */
15209 crtc->cpu_fifo_underrun_disabled = true;
15210 crtc->pch_fifo_underrun_disabled = true;
15211 }
24929352
DV		 15212}
15213
15214static void intel_sanitize_encoder(struct intel_encoder *encoder)
15215{
15216 struct intel_connector *connector;
15217 struct drm_device *dev = encoder->base.dev;
873ffe69 15218 bool active = false;
24929352
DV		 15219
15220 /* We need to check both for a crtc link (meaning that the
15221 * encoder is active and trying to read from a pipe) and the
15222 * pipe itself being active. */
15223 bool has_active_crtc = encoder->base.crtc &&
15224 to_intel_crtc(encoder->base.crtc)->active;
15225
873ffe69
ML		 15226 for_each_intel_connector(dev, connector) {
15227 if (connector->base.encoder != &encoder->base)
15228 continue;
15229
15230 active = true;
15231 break;
15232 }
15233
15234 if (active && !has_active_crtc) {
24929352
DV		 15235 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15236 encoder->base.base.id,
8e329a03 15237 encoder->base.name);
24929352
DV		 15238
15239 /* Connector is active, but has no active pipe. This is
15240 * fallout from our resume register restoring. Disable
15241 * the encoder manually again. */
15242 if (encoder->base.crtc) {
15243 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15244 encoder->base.base.id,
8e329a03 15245 encoder->base.name);
24929352 15246 encoder->disable(encoder);
a62d1497
VS		 15247 if (encoder->post_disable)
15248 encoder->post_disable(encoder);
24929352 15249 }
7f1950fb 15250 encoder->base.crtc = NULL;
24929352
DV		 15251
15252 /* Inconsistent output/port/pipe state happens presumably due to
15253 * a bug in one of the get_hw_state functions. Or someplace else
15254 * in our code, like the register restore mess on resume. Clamp
15255 * things to off as a safer default. */
3a3371ff 15256 for_each_intel_connector(dev, connector) {
24929352
DV		 15257 if (connector->encoder != encoder)
15258 continue;
7f1950fb
EE		 15259 connector->base.dpms = DRM_MODE_DPMS_OFF;
15260 connector->base.encoder = NULL;
24929352
DV		 15261 }
15262 }
15263 /* Enabled encoders without active connectors will be fixed in
15264 * the crtc fixup. */
15265}
15266
04098753 15267void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15268{
15269 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15270 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15271
04098753
ID		 15272 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15273 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15274 i915_disable_vga(dev);
15275 }
15276}
15277
15278void i915_redisable_vga(struct drm_device *dev)
15279{
15280 struct drm_i915_private *dev_priv = dev->dev_private;
15281
8dc8a27c
PZ		 15282 /* This function can be called both from intel_modeset_setup_hw_state or
15283 * at a very early point in our resume sequence, where the power well
15284 * structures are not yet restored. Since this function is at a very
15285 * paranoid "someone might have enabled VGA while we were not looking"
15286 * level, just check if the power well is enabled instead of trying to
15287 * follow the "don't touch the power well if we don't need it" policy
15288 * the rest of the driver uses. */
f458ebbc 15289 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15290 return;
15291
04098753 15292 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15293}
15294
f9cd7b88 15295static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15296{
f9cd7b88 15297 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15298
f9cd7b88 15299 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15300}
15301
f9cd7b88
VS		 15302/* FIXME read out full plane state for all planes */
15303static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15304{
b26d3ea3 15305 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15306 struct intel_plane_state *plane_state =
b26d3ea3 15307 to_intel_plane_state(primary->state);
d032ffa0 15308
19b8d387 15309 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15310 primary_get_hw_state(to_intel_plane(primary));
15311
15312 if (plane_state->visible)
15313 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15314}
15315
30e984df 15316static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15317{
15318 struct drm_i915_private *dev_priv = dev->dev_private;
15319 enum pipe pipe;
24929352
DV		 15320 struct intel_crtc *crtc;
15321 struct intel_encoder *encoder;
15322 struct intel_connector *connector;
5358901f 15323 int i;
24929352 15324
d3fcc808 15325 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15326 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15327 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15328 crtc->config->base.crtc = &crtc->base;
3b117c8f 15329
0e8ffe1b 15330 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15331 crtc->config);
24929352 15332
49d6fa21 15333 crtc->base.state->active = crtc->active;
24929352 15334 crtc->base.enabled = crtc->active;
b70709a6 15335
f9cd7b88 15336 readout_plane_state(crtc);
24929352
DV		 15337
15338 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15339 crtc->base.base.id,
15340 crtc->active ? "enabled" : "disabled");
15341 }
15342
5358901f
DV		 15343 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15344 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15345
3e369b76
ACO		 15346 pll->on = pll->get_hw_state(dev_priv, pll,
15347 &pll->config.hw_state);
5358901f 15348 pll->active = 0;
3e369b76 15349 pll->config.crtc_mask = 0;
d3fcc808 15350 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15351 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15352 pll->active++;
3e369b76 15353 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15354 }
5358901f 15355 }
5358901f 15356
1e6f2ddc 15357 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15358 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15359
3e369b76 15360 if (pll->config.crtc_mask)
bd2bb1b9 15361 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15362 }
15363
b2784e15 15364 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15365 pipe = 0;
15366
15367 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15368 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15369 encoder->base.crtc = &crtc->base;
6e3c9717 15370 encoder->get_config(encoder, crtc->config);
24929352
DV		 15371 } else {
15372 encoder->base.crtc = NULL;
15373 }
15374
6f2bcceb 15375 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15376 encoder->base.base.id,
8e329a03 15377 encoder->base.name,
24929352 15378 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15379 pipe_name(pipe));
24929352
DV		 15380 }
15381
3a3371ff 15382 for_each_intel_connector(dev, connector) {
24929352
DV		 15383 if (connector->get_hw_state(connector)) {
15384 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15385 connector->base.encoder = &connector->encoder->base;
15386 } else {
15387 connector->base.dpms = DRM_MODE_DPMS_OFF;
15388 connector->base.encoder = NULL;
15389 }
15390 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15391 connector->base.base.id,
c23cc417 15392 connector->base.name,
24929352
DV		 15393 connector->base.encoder ? "enabled" : "disabled");
15394 }
7f4c6284
VS		 15395
15396 for_each_intel_crtc(dev, crtc) {
15397 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15398
15399 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15400 if (crtc->base.state->active) {
15401 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15402 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15403 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15404
15405 /*
15406 * The initial mode needs to be set in order to keep
15407 * the atomic core happy. It wants a valid mode if the
15408 * crtc's enabled, so we do the above call.
15409 *
15410 * At this point some state updated by the connectors
15411 * in their ->detect() callback has not run yet, so
15412 * no recalculation can be done yet.
15413 *
15414 * Even if we could do a recalculation and modeset
15415 * right now it would cause a double modeset if
15416 * fbdev or userspace chooses a different initial mode.
15417 *
15418 * If that happens, someone indicated they wanted a
15419 * mode change, which means it's safe to do a full
15420 * recalculation.
15421 */
15422 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15423
15424 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15425 update_scanline_offset(crtc);
7f4c6284
VS		 15426 }
15427 }
30e984df
DV		 15428}
15429
043e9bda
ML		 15430/* Scan out the current hw modeset state,
15431 * and sanitizes it to the current state
15432 */
15433static void
15434intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15435{
15436 struct drm_i915_private *dev_priv = dev->dev_private;
15437 enum pipe pipe;
30e984df
DV		 15438 struct intel_crtc *crtc;
15439 struct intel_encoder *encoder;
35c95375 15440 int i;
30e984df
DV		 15441
15442 intel_modeset_readout_hw_state(dev);
24929352
DV		 15443
15444 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15445 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15446 intel_sanitize_encoder(encoder);
15447 }
15448
055e393f 15449 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15450 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15451 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15452 intel_dump_pipe_config(crtc, crtc->config,
15453 "[setup_hw_state]");
24929352 15454 }
9a935856 15455
d29b2f9d
ACO		 15456 intel_modeset_update_connector_atomic_state(dev);
15457
35c95375
DV		 15458 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15459 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15460
15461 if (!pll->on || pll->active)
15462 continue;
15463
15464 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15465
15466 pll->disable(dev_priv, pll);
15467 pll->on = false;
15468 }
15469
26e1fe4f 15470 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15471 vlv_wm_get_hw_state(dev);
15472 else if (IS_GEN9(dev))
3078999f
PB		 15473 skl_wm_get_hw_state(dev);
15474 else if (HAS_PCH_SPLIT(dev))
243e6a44 15475 ilk_wm_get_hw_state(dev);
292b990e
ML		 15476
15477 for_each_intel_crtc(dev, crtc) {
15478 unsigned long put_domains;
15479
15480 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15481 if (WARN_ON(put_domains))
15482 modeset_put_power_domains(dev_priv, put_domains);
15483 }
15484 intel_display_set_init_power(dev_priv, false);
043e9bda 15485}
7d0bc1ea 15486
043e9bda
ML		 15487void intel_display_resume(struct drm_device *dev)
15488{
15489 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15490 struct intel_connector *conn;
15491 struct intel_plane *plane;
15492 struct drm_crtc *crtc;
15493 int ret;
f30da187 15494
043e9bda
ML		 15495 if (!state)
15496 return;
15497
15498 state->acquire_ctx = dev->mode_config.acquire_ctx;
15499
15500 /* preserve complete old state, including dpll */
15501 intel_atomic_get_shared_dpll_state(state);
15502
15503 for_each_crtc(dev, crtc) {
15504 struct drm_crtc_state *crtc_state =
15505 drm_atomic_get_crtc_state(state, crtc);
15506
15507 ret = PTR_ERR_OR_ZERO(crtc_state);
15508 if (ret)
15509 goto err;
15510
15511 /* force a restore */
15512 crtc_state->mode_changed = true;
45e2b5f6 15513 }
8af6cf88 15514
043e9bda
ML		 15515 for_each_intel_plane(dev, plane) {
15516 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15517 if (ret)
15518 goto err;
15519 }
15520
15521 for_each_intel_connector(dev, conn) {
15522 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15523 if (ret)
15524 goto err;
15525 }
15526
15527 intel_modeset_setup_hw_state(dev);
15528
15529 i915_redisable_vga(dev);
74c090b1 15530 ret = drm_atomic_commit(state);
043e9bda
ML		 15531 if (!ret)
15532 return;
15533
15534err:
15535 DRM_ERROR("Restoring old state failed with %i\n", ret);
15536 drm_atomic_state_free(state);
2c7111db
CW		 15537}
15538
15539void intel_modeset_gem_init(struct drm_device *dev)
15540{
484b41dd 15541 struct drm_crtc *c;
2ff8fde1 15542 struct drm_i915_gem_object *obj;
e0d6149b 15543 int ret;
484b41dd 15544
ae48434c
ID		 15545 mutex_lock(&dev->struct_mutex);
15546 intel_init_gt_powersave(dev);
15547 mutex_unlock(&dev->struct_mutex);
15548
1833b134 15549 intel_modeset_init_hw(dev);
02e792fb
DV		 15550
15551 intel_setup_overlay(dev);
484b41dd
JB		 15552
15553 /*
15554 * Make sure any fbs we allocated at startup are properly
15555 * pinned & fenced. When we do the allocation it's too early
15556 * for this.
15557 */
70e1e0ec 15558 for_each_crtc(dev, c) {
2ff8fde1
MR		 15559 obj = intel_fb_obj(c->primary->fb);
15560 if (obj == NULL)
484b41dd
JB		 15561 continue;
15562
e0d6149b
TU		 15563 mutex_lock(&dev->struct_mutex);
15564 ret = intel_pin_and_fence_fb_obj(c->primary,
15565 c->primary->fb,
7580d774 15566 c->primary->state);
e0d6149b
TU		 15567 mutex_unlock(&dev->struct_mutex);
15568 if (ret) {
484b41dd
JB		 15569 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15570 to_intel_crtc(c)->pipe);
66e514c1
DA		 15571 drm_framebuffer_unreference(c->primary->fb);
15572 c->primary->fb = NULL;
36750f28 15573 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15574 update_state_fb(c->primary);
36750f28 15575 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15576 }
15577 }
0962c3c9
VS		 15578
15579 intel_backlight_register(dev);
79e53945
JB		 15580}
15581
4932e2c3
ID		 15582void intel_connector_unregister(struct intel_connector *intel_connector)
15583{
15584 struct drm_connector *connector = &intel_connector->base;
15585
15586 intel_panel_destroy_backlight(connector);
34ea3d38 15587 drm_connector_unregister(connector);
4932e2c3
ID		 15588}
15589
79e53945
JB		 15590void intel_modeset_cleanup(struct drm_device *dev)
15591{
652c393a 15592 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15593 struct drm_connector *connector;
652c393a 15594
2eb5252e
ID		 15595 intel_disable_gt_powersave(dev);
15596
0962c3c9
VS		 15597 intel_backlight_unregister(dev);
15598
fd0c0642
DV		 15599 /*
15600 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15601 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15602 * experience fancy races otherwise.
15603 */
2aeb7d3a 15604 intel_irq_uninstall(dev_priv);
eb21b92b 15605
fd0c0642
DV		 15606 /*
15607 * Due to the hpd irq storm handling the hotplug work can re-arm the
15608 * poll handlers. Hence disable polling after hpd handling is shut down.
15609 */
f87ea761 15610 drm_kms_helper_poll_fini(dev);
fd0c0642 15611
723bfd70
JB		 15612 intel_unregister_dsm_handler();
15613
7733b49b 15614 intel_fbc_disable(dev_priv);
69341a5e 15615
1630fe75
CW		 15616 /* flush any delayed tasks or pending work */
15617 flush_scheduled_work();
15618
db31af1d
JN		 15619 /* destroy the backlight and sysfs files before encoders/connectors */
15620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15621 struct intel_connector *intel_connector;
15622
15623 intel_connector = to_intel_connector(connector);
15624 intel_connector->unregister(intel_connector);
db31af1d 15625 }
d9255d57 15626
79e53945 15627 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15628
15629 intel_cleanup_overlay(dev);
ae48434c
ID		 15630
15631 mutex_lock(&dev->struct_mutex);
15632 intel_cleanup_gt_powersave(dev);
15633 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15634}
15635
f1c79df3
ZW		 15636/*
15637 * Return which encoder is currently attached for connector.
15638 */
df0e9248 15639struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15640{
df0e9248
CW		 15641 return &intel_attached_encoder(connector)->base;
15642}
f1c79df3 15643
df0e9248
CW		 15644void intel_connector_attach_encoder(struct intel_connector *connector,
15645 struct intel_encoder *encoder)
15646{
15647 connector->encoder = encoder;
15648 drm_mode_connector_attach_encoder(&connector->base,
15649 &encoder->base);
79e53945 15650}
28d52043
DA		 15651
15652/*
15653 * set vga decode state - true == enable VGA decode
15654 */
15655int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15656{
15657 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15658 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15659 u16 gmch_ctrl;
15660
75fa041d
CW		 15661 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15662 DRM_ERROR("failed to read control word\n");
15663 return -EIO;
15664 }
15665
c0cc8a55
CW		 15666 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15667 return 0;
15668
28d52043
DA		 15669 if (state)
15670 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15671 else
15672 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15673
15674 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15675 DRM_ERROR("failed to write control word\n");
15676 return -EIO;
15677 }
15678
28d52043
DA		 15679 return 0;
15680}
c4a1d9e4 15681
c4a1d9e4 15682struct intel_display_error_state {
ff57f1b0
PZ		 15683
15684 u32 power_well_driver;
15685
63b66e5b
CW		 15686 int num_transcoders;
15687
c4a1d9e4
CW		 15688 struct intel_cursor_error_state {
15689 u32 control;
15690 u32 position;
15691 u32 base;
15692 u32 size;
52331309 15693 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15694
15695 struct intel_pipe_error_state {
ddf9c536 15696 bool power_domain_on;
c4a1d9e4 15697 u32 source;
f301b1e1 15698 u32 stat;
52331309 15699 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15700
15701 struct intel_plane_error_state {
15702 u32 control;
15703 u32 stride;
15704 u32 size;
15705 u32 pos;
15706 u32 addr;
15707 u32 surface;
15708 u32 tile_offset;
52331309 15709 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15710
15711 struct intel_transcoder_error_state {
ddf9c536 15712 bool power_domain_on;
63b66e5b
CW		 15713 enum transcoder cpu_transcoder;
15714
15715 u32 conf;
15716
15717 u32 htotal;
15718 u32 hblank;
15719 u32 hsync;
15720 u32 vtotal;
15721 u32 vblank;
15722 u32 vsync;
15723 } transcoder[4];
c4a1d9e4
CW		 15724};
15725
15726struct intel_display_error_state *
15727intel_display_capture_error_state(struct drm_device *dev)
15728{
fbee40df 15729 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15730 struct intel_display_error_state *error;
63b66e5b
CW		 15731 int transcoders[] = {
15732 TRANSCODER_A,
15733 TRANSCODER_B,
15734 TRANSCODER_C,
15735 TRANSCODER_EDP,
15736 };
c4a1d9e4
CW		 15737 int i;
15738
63b66e5b
CW		 15739 if (INTEL_INFO(dev)->num_pipes == 0)
15740 return NULL;
15741
9d1cb914 15742 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15743 if (error == NULL)
15744 return NULL;
15745
190be112 15746 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15747 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15748
055e393f 15749 for_each_pipe(dev_priv, i) {
ddf9c536 15750 error->pipe[i].power_domain_on =
f458ebbc
DV		 15751 __intel_display_power_is_enabled(dev_priv,
15752 POWER_DOMAIN_PIPE(i));
ddf9c536 15753 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15754 continue;
15755
5efb3e28
VS		 15756 error->cursor[i].control = I915_READ(CURCNTR(i));
15757 error->cursor[i].position = I915_READ(CURPOS(i));
15758 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15759
15760 error->plane[i].control = I915_READ(DSPCNTR(i));
15761 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15762 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15763 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15764 error->plane[i].pos = I915_READ(DSPPOS(i));
15765 }
ca291363
PZ		 15766 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15767 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15768 if (INTEL_INFO(dev)->gen >= 4) {
15769 error->plane[i].surface = I915_READ(DSPSURF(i));
15770 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15771 }
15772
c4a1d9e4 15773 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15774
3abfce77 15775 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15776 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15777 }
15778
15779 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15780 if (HAS_DDI(dev_priv->dev))
15781 error->num_transcoders++; /* Account for eDP. */
15782
15783 for (i = 0; i < error->num_transcoders; i++) {
15784 enum transcoder cpu_transcoder = transcoders[i];
15785
ddf9c536 15786 error->transcoder[i].power_domain_on =
f458ebbc 15787 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15788 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15789 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15790 continue;
15791
63b66e5b
CW		 15792 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15793
15794 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15795 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15796 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15797 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15798 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15799 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15800 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15801 }
15802
15803 return error;
15804}
15805
edc3d884
MK		 15806#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15807
c4a1d9e4 15808void
edc3d884 15809intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15810 struct drm_device *dev,
15811 struct intel_display_error_state *error)
15812{
055e393f 15813 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15814 int i;
15815
63b66e5b
CW		 15816 if (!error)
15817 return;
15818
edc3d884 15819 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15820 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15821 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15822 error->power_well_driver);
055e393f 15823 for_each_pipe(dev_priv, i) {
edc3d884 15824 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15825 err_printf(m, " Power: %s\n",
15826 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15827 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15828 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15829
15830 err_printf(m, "Plane [%d]:\n", i);
15831 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15832 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15833 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15834 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15835 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15836 }
4b71a570 15837 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15838 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15839 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15840 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15841 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15842 }
15843
edc3d884
MK		 15844 err_printf(m, "Cursor [%d]:\n", i);
15845 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15846 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15847 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15848 }
63b66e5b
CW		 15849
15850 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15851 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15852 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15853 err_printf(m, " Power: %s\n",
15854 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15855 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15856 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15857 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15858 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15859 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15860 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15861 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15862 }
c4a1d9e4 15863}
e2fcdaa9
VS		 15864
15865void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15866{
15867 struct intel_crtc *crtc;
15868
15869 for_each_intel_crtc(dev, crtc) {
15870 struct intel_unpin_work *work;
e2fcdaa9 15871
5e2d7afc 15872 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15873
15874 work = crtc->unpin_work;
15875
15876 if (work && work->event &&
15877 work->event->base.file_priv == file) {
15878 kfree(work->event);
15879 work->event = NULL;
15880 }
15881
5e2d7afc 15882 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15883 }
15884}
Linux kernel - Deliverables
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