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drm/i915/bdw: don't try to check IPS state on BDW v2
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 92 .dot = { .min = 25000, .max = 350000 },
9c333719 93 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 94 .n = { .min = 2, .max = 16 },
0206e353
AJ		 95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
9c333719 106 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 107 .n = { .min = 2, .max = 16 },
5d536e28
DV		 108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 118 .dot = { .min = 25000, .max = 350000 },
9c333719 119 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 120 .n = { .min = 2, .max = 16 },
0206e353
AJ		 121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
dc730512 312static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 320 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 321 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
b99ab663 324 .p1 = { .min = 2, .max = 3 },
5fdc9c49 325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 326};
327
6b4bf1c4
VS		 328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 332 if (WARN_ON(clock->n == 0 || clock->p == 0))
333 return;
fb03ac01
VS		 334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 336}
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24 412 } else if (IS_VALLEYVIEW(dev)) {
dc730512 413 limit = &intel_limits_vlv;
a6c45cf0
CW		 414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
417 else
418 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 419 } else {
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 421 limit = &intel_limits_i8xx_lvds;
5d536e28 422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 423 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 424 else
425 limit = &intel_limits_i8xx_dac;
79e53945
JB		 426 }
427 return limit;
428}
429
f2b115e6
AJ		 430/* m1 is reserved as 0 in Pineview, n is a ring counter */
431static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 432{
2177832f
SL		 433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 435 if (WARN_ON(clock->n == 0 || clock->p == 0))
436 return;
fb03ac01
VS		 437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 439}
440
7429e9d4
DV		 441static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
442{
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
444}
445
ac58c3f0 446static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 447{
7429e9d4 448 clock->m = i9xx_dpll_compute_m(clock);
79e53945 449 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
451 return;
fb03ac01
VS		 452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
f01b7962
VS		 466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
79e53945 468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 469 INTELPllInvalid("p1 out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 474
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
478
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
484 }
485
79e53945 486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 487 INTELPllInvalid("vco out of range\n");
79e53945
JB		 488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
490 */
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 492 INTELPllInvalid("dot out of range\n");
79e53945
JB		 493
494 return true;
495}
496
d4906093 497static bool
ee9300bb 498i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
79e53945
JB		 501{
502 struct drm_device *dev = crtc->dev;
79e53945 503 intel_clock_t clock;
79e53945
JB		 504 int err = target;
505
a210b028 506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 507 /*
a210b028
DV		 508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
79e53945 511 */
1974cad0 512 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 513 clock.p2 = limit->p2.p2_fast;
514 else
515 clock.p2 = limit->p2.p2_slow;
516 } else {
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
519 else
520 clock.p2 = limit->p2.p2_fast;
521 }
522
0206e353 523 memset(best_clock, 0, sizeof(*best_clock));
79e53945 524
42158660
ZY		 525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
526 clock.m1++) {
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 529 if (clock.m2 >= clock.m1)
42158660
ZY		 530 break;
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 535 int this_err;
536
ac58c3f0
DV		 537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
539 &clock))
540 continue;
541 if (match_clock &&
542 clock.p != match_clock->p)
543 continue;
544
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
547 *best_clock = clock;
548 err = this_err;
549 }
550 }
551 }
552 }
553 }
554
555 return (err != target);
556}
557
558static bool
ee9300bb
DV		 559pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
79e53945
JB		 562{
563 struct drm_device *dev = crtc->dev;
79e53945 564 intel_clock_t clock;
79e53945
JB		 565 int err = target;
566
a210b028 567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 568 /*
a210b028
DV		 569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
79e53945 572 */
1974cad0 573 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 574 clock.p2 = limit->p2.p2_fast;
575 else
576 clock.p2 = limit->p2.p2_slow;
577 } else {
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
580 else
581 clock.p2 = limit->p2.p2_fast;
582 }
583
0206e353 584 memset(best_clock, 0, sizeof(*best_clock));
79e53945 585
42158660
ZY		 586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
587 clock.m1++) {
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 594 int this_err;
595
ac58c3f0 596 pineview_clock(refclk, &clock);
1b894b59
CW		 597 if (!intel_PLL_is_valid(dev, limit,
598 &clock))
79e53945 599 continue;
cec2f356
SP		 600 if (match_clock &&
601 clock.p != match_clock->p)
602 continue;
79e53945
JB		 603
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
606 *best_clock = clock;
607 err = this_err;
608 }
609 }
610 }
611 }
612 }
613
614 return (err != target);
615}
616
d4906093 617static bool
ee9300bb
DV		 618g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
d4906093
ML		 621{
622 struct drm_device *dev = crtc->dev;
d4906093
ML		 623 intel_clock_t clock;
624 int max_n;
625 bool found;
6ba770dc
AJ		 626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 628 found = false;
629
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 631 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 632 clock.p2 = limit->p2.p2_fast;
633 else
634 clock.p2 = limit->p2.p2_slow;
635 } else {
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
638 else
639 clock.p2 = limit->p2.p2_fast;
640 }
641
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
f77f13e2 644 /* based on hardware requirement, prefer smaller n to precision */
d4906093 645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 646 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
653 int this_err;
654
ac58c3f0 655 i9xx_clock(refclk, &clock);
1b894b59
CW		 656 if (!intel_PLL_is_valid(dev, limit,
657 &clock))
d4906093 658 continue;
1b894b59
CW		 659
660 this_err = abs(clock.dot - target);
d4906093
ML		 661 if (this_err < err_most) {
662 *best_clock = clock;
663 err_most = this_err;
664 max_n = clock.n;
665 found = true;
666 }
667 }
668 }
669 }
670 }
2c07245f
ZW		 671 return found;
672}
673
a0c4da24 674static bool
ee9300bb
DV		 675vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
a0c4da24 678{
f01b7962 679 struct drm_device *dev = crtc->dev;
6b4bf1c4 680 intel_clock_t clock;
69e4f900 681 unsigned int bestppm = 1000000;
27e639bf
VS		 682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 684 bool found = false;
a0c4da24 685
6b4bf1c4
VS		 686 target *= 5; /* fast clock */
687
688 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 689
690 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 695 clock.p = clock.p1 * clock.p2;
a0c4da24 696 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 698 unsigned int ppm, diff;
699
6b4bf1c4
VS		 700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
701 refclk * clock.m1);
702
703 vlv_clock(refclk, &clock);
43b0ac53 704
f01b7962
VS		 705 if (!intel_PLL_is_valid(dev, limit,
706 &clock))
43b0ac53
VS		 707 continue;
708
6b4bf1c4
VS		 709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
711
712 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 713 bestppm = 0;
6b4bf1c4 714 *best_clock = clock;
49e497ef 715 found = true;
43b0ac53 716 }
6b4bf1c4 717
c686122c 718 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 719 bestppm = ppm;
6b4bf1c4 720 *best_clock = clock;
49e497ef 721 found = true;
a0c4da24
JB		 722 }
723 }
724 }
725 }
726 }
a0c4da24 727
49e497ef 728 return found;
a0c4da24 729}
a4fc5ed6 730
20ddf665
VS		 731bool intel_crtc_active(struct drm_crtc *crtc)
732{
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
737 *
241bfc38 738 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 739 * as Haswell has gained clock readout/fastboot support.
740 *
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
743 */
744 return intel_crtc->active && crtc->fb &&
241bfc38 745 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 746}
747
a5c961d1
PZ		 748enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
749 enum pipe pipe)
750{
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
753
3b117c8f 754 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 755}
756
57e22f4a 757static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
a928d536
PZ		 758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
57e22f4a 760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
a928d536
PZ		 761
762 frame = I915_READ(frame_reg);
763
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
766}
767
9d0498a2
JB		 768/**
769 * intel_wait_for_vblank - wait for vblank on a given pipe
770 * @dev: drm device
771 * @pipe: pipe to wait for
772 *
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
774 * mode setting code.
775 */
776void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 777{
9d0498a2 778 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 779 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 780
57e22f4a
VS		 781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
a928d536
PZ		 783 return;
784 }
785
300387c0
CW		 786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
788 *
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
795 * vblanks...
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
798 */
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
801
9d0498a2 802 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
805 50))
9d0498a2
JB		 806 DRM_DEBUG_KMS("vblank wait timed out\n");
807}
808
fbf49ea2
VS		 809static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
813 u32 line1, line2;
814 u32 line_mask;
815
816 if (IS_GEN2(dev))
817 line_mask = DSL_LINEMASK_GEN2;
818 else
819 line_mask = DSL_LINEMASK_GEN3;
820
821 line1 = I915_READ(reg) & line_mask;
822 mdelay(5);
823 line2 = I915_READ(reg) & line_mask;
824
825 return line1 == line2;
826}
827
ab7ad7f6
KP		 828/*
829 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 830 * @dev: drm device
831 * @pipe: pipe to wait for
832 *
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
836 *
ab7ad7f6
KP		 837 * On Gen4 and above:
838 * wait for the pipe register state bit to turn off
839 *
840 * Otherwise:
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
58e10eb9 843 *
9d0498a2 844 */
58e10eb9 845void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 846{
847 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
849 pipe);
ab7ad7f6
KP		 850
851 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 852 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 853
854 /* Wait for the Pipe State to go off */
58e10eb9
CW		 855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856 100))
284637d9 857 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 858 } else {
ab7ad7f6 859 /* Wait for the display line to settle */
fbf49ea2 860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
40e9cf64
JB		 1363static void intel_init_dpio(struct drm_device *dev)
1364{
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
8212d563
VS		 1370 /* Enable the CRI clock source so we can get at the display */
1371 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1372 DPLL_INTEGRATED_CRI_CLK_VLV);
1373
e4607fcf 1374 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
5382f5f3
JB		 1375}
1376
1377static void intel_reset_dpio(struct drm_device *dev)
1378{
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380
1381 if (!IS_VALLEYVIEW(dev))
1382 return;
1383
40e9cf64
JB		 1384 /*
1385 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1386 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1387 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1388 * b. The other bits such as sfr settings / modesel may all be set
1389 * to 0.
1390 *
1391 * This should only be done on init and resume from S3 with both
1392 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1393 */
1394 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1395}
1396
426115cf 1397static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1398{
426115cf
DV		 1399 struct drm_device *dev = crtc->base.dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401 int reg = DPLL(crtc->pipe);
1402 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1403
426115cf 1404 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1405
1406 /* No really, not for ILK+ */
1407 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1408
1409 /* PLL is protected by panel, make sure we can write it */
1410 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1411 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1412
426115cf
DV		 1413 I915_WRITE(reg, dpll);
1414 POSTING_READ(reg);
1415 udelay(150);
1416
1417 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1418 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1419
1420 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1422
1423 /* We do this three times for luck */
426115cf 1424 I915_WRITE(reg, dpll);
87442f73
DV		 1425 POSTING_READ(reg);
1426 udelay(150); /* wait for warmup */
426115cf 1427 I915_WRITE(reg, dpll);
87442f73
DV		 1428 POSTING_READ(reg);
1429 udelay(150); /* wait for warmup */
426115cf 1430 I915_WRITE(reg, dpll);
87442f73
DV		 1431 POSTING_READ(reg);
1432 udelay(150); /* wait for warmup */
1433}
1434
66e3d5c0 1435static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1436{
66e3d5c0
DV		 1437 struct drm_device *dev = crtc->base.dev;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 int reg = DPLL(crtc->pipe);
1440 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1441
66e3d5c0 1442 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1443
63d7bbe9 1444 /* No really, not for ILK+ */
87442f73 1445 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1446
1447 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1448 if (IS_MOBILE(dev) && !IS_I830(dev))
1449 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1450
66e3d5c0
DV		 1451 I915_WRITE(reg, dpll);
1452
1453 /* Wait for the clocks to stabilize. */
1454 POSTING_READ(reg);
1455 udelay(150);
1456
1457 if (INTEL_INFO(dev)->gen >= 4) {
1458 I915_WRITE(DPLL_MD(crtc->pipe),
1459 crtc->config.dpll_hw_state.dpll_md);
1460 } else {
1461 /* The pixel multiplier can only be updated once the
1462 * DPLL is enabled and the clocks are stable.
1463 *
1464 * So write it again.
1465 */
1466 I915_WRITE(reg, dpll);
1467 }
63d7bbe9
JB		 1468
1469 /* We do this three times for luck */
66e3d5c0 1470 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
66e3d5c0 1473 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
66e3d5c0 1476 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479}
1480
1481/**
50b44a44 1482 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
50b44a44 1490static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1491{
63d7bbe9
JB		 1492 /* Don't disable pipe A or pipe A PLLs if needed */
1493 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1494 return;
1495
1496 /* Make sure the pipe isn't still relying on us */
1497 assert_pipe_disabled(dev_priv, pipe);
1498
50b44a44
DV		 1499 I915_WRITE(DPLL(pipe), 0);
1500 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1501}
1502
f6071166
JB		 1503static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1504{
1505 u32 val = 0;
1506
1507 /* Make sure the pipe isn't still relying on us */
1508 assert_pipe_disabled(dev_priv, pipe);
1509
1510 /* Leave integrated clock source enabled */
1511 if (pipe == PIPE_B)
1512 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1513 I915_WRITE(DPLL(pipe), val);
1514 POSTING_READ(DPLL(pipe));
1515}
1516
e4607fcf
CML		 1517void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1518 struct intel_digital_port *dport)
89b667f8
JB		 1519{
1520 u32 port_mask;
1521
e4607fcf
CML		 1522 switch (dport->port) {
1523 case PORT_B:
89b667f8 1524 port_mask = DPLL_PORTB_READY_MASK;
e4607fcf
CML		 1525 break;
1526 case PORT_C:
89b667f8 1527 port_mask = DPLL_PORTC_READY_MASK;
e4607fcf
CML		 1528 break;
1529 default:
1530 BUG();
1531 }
89b667f8
JB		 1532
1533 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1534 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
be46ffd4 1535 port_name(dport->port), I915_READ(DPLL(0)));
89b667f8
JB		 1536}
1537
92f2584a 1538/**
e72f9fbf 1539 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1540 * @dev_priv: i915 private structure
1541 * @pipe: pipe PLL to enable
1542 *
1543 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1544 * drives the transcoder clock.
1545 */
e2b78267 1546static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1547{
e2b78267
DV		 1548 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1549 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1550
48da64a8 1551 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1552 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1553 if (WARN_ON(pll == NULL))
48da64a8
CW		 1554 return;
1555
1556 if (WARN_ON(pll->refcount == 0))
1557 return;
ee7b9f93 1558
46edb027
DV		 1559 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1560 pll->name, pll->active, pll->on,
e2b78267 1561 crtc->base.base.id);
92f2584a 1562
cdbd2316
DV		 1563 if (pll->active++) {
1564 WARN_ON(!pll->on);
e9d6944e 1565 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1566 return;
1567 }
f4a091c7 1568 WARN_ON(pll->on);
ee7b9f93 1569
46edb027 1570 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1571 pll->enable(dev_priv, pll);
ee7b9f93 1572 pll->on = true;
92f2584a
JB		 1573}
1574
e2b78267 1575static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1576{
e2b78267
DV		 1577 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1578 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1579
92f2584a
JB		 1580 /* PCH only available on ILK+ */
1581 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1582 if (WARN_ON(pll == NULL))
ee7b9f93 1583 return;
92f2584a 1584
48da64a8
CW		 1585 if (WARN_ON(pll->refcount == 0))
1586 return;
7a419866 1587
46edb027
DV		 1588 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1589 pll->name, pll->active, pll->on,
e2b78267 1590 crtc->base.base.id);
7a419866 1591
48da64a8 1592 if (WARN_ON(pll->active == 0)) {
e9d6944e 1593 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1594 return;
1595 }
1596
e9d6944e 1597 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1598 WARN_ON(!pll->on);
cdbd2316 1599 if (--pll->active)
7a419866 1600 return;
ee7b9f93 1601
46edb027 1602 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1603 pll->disable(dev_priv, pll);
ee7b9f93 1604 pll->on = false;
92f2584a
JB		 1605}
1606
b8a4f404
PZ		 1607static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1608 enum pipe pipe)
040484af 1609{
23670b32 1610 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1611 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1613 uint32_t reg, val, pipeconf_val;
040484af
JB		 1614
1615 /* PCH only available on ILK+ */
1616 BUG_ON(dev_priv->info->gen < 5);
1617
1618 /* Make sure PCH DPLL is enabled */
e72f9fbf 1619 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1620 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1621
1622 /* FDI must be feeding us bits for PCH ports */
1623 assert_fdi_tx_enabled(dev_priv, pipe);
1624 assert_fdi_rx_enabled(dev_priv, pipe);
1625
23670b32
DV		 1626 if (HAS_PCH_CPT(dev)) {
1627 /* Workaround: Set the timing override bit before enabling the
1628 * pch transcoder. */
1629 reg = TRANS_CHICKEN2(pipe);
1630 val = I915_READ(reg);
1631 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1632 I915_WRITE(reg, val);
59c859d6 1633 }
23670b32 1634
ab9412ba 1635 reg = PCH_TRANSCONF(pipe);
040484af 1636 val = I915_READ(reg);
5f7f726d 1637 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1638
1639 if (HAS_PCH_IBX(dev_priv->dev)) {
1640 /*
1641 * make the BPC in transcoder be consistent with
1642 * that in pipeconf reg.
1643 */
dfd07d72
DV		 1644 val &= ~PIPECONF_BPC_MASK;
1645 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1646 }
5f7f726d
PZ		 1647
1648 val &= ~TRANS_INTERLACE_MASK;
1649 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1650 if (HAS_PCH_IBX(dev_priv->dev) &&
1651 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1652 val |= TRANS_LEGACY_INTERLACED_ILK;
1653 else
1654 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1655 else
1656 val |= TRANS_PROGRESSIVE;
1657
040484af
JB		 1658 I915_WRITE(reg, val | TRANS_ENABLE);
1659 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1660 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1661}
1662
8fb033d7 1663static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1664 enum transcoder cpu_transcoder)
040484af 1665{
8fb033d7 1666 u32 val, pipeconf_val;
8fb033d7
PZ		 1667
1668 /* PCH only available on ILK+ */
1669 BUG_ON(dev_priv->info->gen < 5);
1670
8fb033d7 1671 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1672 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1673 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1674
223a6fdf
PZ		 1675 /* Workaround: set timing override bit. */
1676 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1677 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1678 I915_WRITE(_TRANSA_CHICKEN2, val);
1679
25f3ef11 1680 val = TRANS_ENABLE;
937bb610 1681 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1682
9a76b1c6
PZ		 1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1684 PIPECONF_INTERLACED_ILK)
a35f2679 1685 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1686 else
1687 val |= TRANS_PROGRESSIVE;
1688
ab9412ba
DV		 1689 I915_WRITE(LPT_TRANSCONF, val);
1690 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1691 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1692}
1693
b8a4f404
PZ		 1694static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
040484af 1696{
23670b32
DV		 1697 struct drm_device *dev = dev_priv->dev;
1698 uint32_t reg, val;
040484af
JB		 1699
1700 /* FDI relies on the transcoder */
1701 assert_fdi_tx_disabled(dev_priv, pipe);
1702 assert_fdi_rx_disabled(dev_priv, pipe);
1703
291906f1
JB		 1704 /* Ports must be off as well */
1705 assert_pch_ports_disabled(dev_priv, pipe);
1706
ab9412ba 1707 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1708 val = I915_READ(reg);
1709 val &= ~TRANS_ENABLE;
1710 I915_WRITE(reg, val);
1711 /* wait for PCH transcoder off, transcoder state */
1712 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1713 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1714
1715 if (!HAS_PCH_IBX(dev)) {
1716 /* Workaround: Clear the timing override chicken bit again. */
1717 reg = TRANS_CHICKEN2(pipe);
1718 val = I915_READ(reg);
1719 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1720 I915_WRITE(reg, val);
1721 }
040484af
JB		 1722}
1723
ab4d966c 1724static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1725{
8fb033d7
PZ		 1726 u32 val;
1727
ab9412ba 1728 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1729 val &= ~TRANS_ENABLE;
ab9412ba 1730 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1731 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1732 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1733 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1734
1735 /* Workaround: clear timing override bit. */
1736 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1737 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1738 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1739}
1740
b24e7179 1741/**
309cfea8 1742 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1743 * @dev_priv: i915 private structure
1744 * @pipe: pipe to enable
040484af 1745 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1746 *
1747 * Enable @pipe, making sure that various hardware specific requirements
1748 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1749 *
1750 * @pipe should be %PIPE_A or %PIPE_B.
1751 *
1752 * Will wait until the pipe is actually running (i.e. first vblank) before
1753 * returning.
1754 */
040484af 1755static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1756 bool pch_port, bool dsi)
b24e7179 1757{
702e7a56
PZ		 1758 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1759 pipe);
1a240d4d 1760 enum pipe pch_transcoder;
b24e7179
JB		 1761 int reg;
1762 u32 val;
1763
58c6eaa2 1764 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1765 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1766 assert_sprites_disabled(dev_priv, pipe);
1767
681e5811 1768 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1769 pch_transcoder = TRANSCODER_A;
1770 else
1771 pch_transcoder = pipe;
1772
b24e7179
JB		 1773 /*
1774 * A pipe without a PLL won't actually be able to drive bits from
1775 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1776 * need the check.
1777 */
1778 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1779 if (dsi)
1780 assert_dsi_pll_enabled(dev_priv);
1781 else
1782 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1783 else {
1784 if (pch_port) {
1785 /* if driving the PCH, we need FDI enabled */
cc391bbb 1786 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1787 assert_fdi_tx_pll_enabled(dev_priv,
1788 (enum pipe) cpu_transcoder);
040484af
JB		 1789 }
1790 /* FIXME: assert CPU port conditions for SNB+ */
1791 }
b24e7179 1792
702e7a56 1793 reg = PIPECONF(cpu_transcoder);
b24e7179 1794 val = I915_READ(reg);
00d70b15
CW		 1795 if (val & PIPECONF_ENABLE)
1796 return;
1797
1798 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1799 intel_wait_for_vblank(dev_priv->dev, pipe);
1800}
1801
1802/**
309cfea8 1803 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1804 * @dev_priv: i915 private structure
1805 * @pipe: pipe to disable
1806 *
1807 * Disable @pipe, making sure that various hardware specific requirements
1808 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1809 *
1810 * @pipe should be %PIPE_A or %PIPE_B.
1811 *
1812 * Will wait until the pipe has shut down before returning.
1813 */
1814static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1815 enum pipe pipe)
1816{
702e7a56
PZ		 1817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 pipe);
b24e7179
JB		 1819 int reg;
1820 u32 val;
1821
1822 /*
1823 * Make sure planes won't keep trying to pump pixels to us,
1824 * or we might hang the display.
1825 */
1826 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1827 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1828 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1829
1830 /* Don't disable pipe A or pipe A PLLs if needed */
1831 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1832 return;
1833
702e7a56 1834 reg = PIPECONF(cpu_transcoder);
b24e7179 1835 val = I915_READ(reg);
00d70b15
CW		 1836 if ((val & PIPECONF_ENABLE) == 0)
1837 return;
1838
1839 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1840 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1841}
1842
d74362c9
KP		 1843/*
1844 * Plane regs are double buffered, going from enabled->disabled needs a
1845 * trigger in order to latch. The display address reg provides this.
1846 */
1dba99f4
VS		 1847void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane)
d74362c9 1849{
1dba99f4
VS		 1850 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1851
1852 I915_WRITE(reg, I915_READ(reg));
1853 POSTING_READ(reg);
d74362c9
KP		 1854}
1855
b24e7179 1856/**
d1de00ef 1857 * intel_enable_primary_plane - enable the primary plane on a given pipe
b24e7179
JB		 1858 * @dev_priv: i915 private structure
1859 * @plane: plane to enable
1860 * @pipe: pipe being fed
1861 *
1862 * Enable @plane on @pipe, making sure that @pipe is running first.
1863 */
d1de00ef
VS		 1864static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1865 enum plane plane, enum pipe pipe)
b24e7179 1866{
939c2fe8
VS		 1867 struct intel_crtc *intel_crtc =
1868 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1869 int reg;
1870 u32 val;
1871
1872 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1873 assert_pipe_enabled(dev_priv, pipe);
1874
4c445e0e 1875 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
0037f71c 1876
4c445e0e 1877 intel_crtc->primary_enabled = true;
939c2fe8 1878
b24e7179
JB		 1879 reg = DSPCNTR(plane);
1880 val = I915_READ(reg);
00d70b15
CW		 1881 if (val & DISPLAY_PLANE_ENABLE)
1882 return;
1883
1884 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1dba99f4 1885 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1886 intel_wait_for_vblank(dev_priv->dev, pipe);
1887}
1888
b24e7179 1889/**
d1de00ef 1890 * intel_disable_primary_plane - disable the primary plane
b24e7179
JB		 1891 * @dev_priv: i915 private structure
1892 * @plane: plane to disable
1893 * @pipe: pipe consuming the data
1894 *
1895 * Disable @plane; should be an independent operation.
1896 */
d1de00ef
VS		 1897static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
b24e7179 1899{
939c2fe8
VS		 1900 struct intel_crtc *intel_crtc =
1901 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1902 int reg;
1903 u32 val;
1904
4c445e0e 1905 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
0037f71c 1906
4c445e0e 1907 intel_crtc->primary_enabled = false;
939c2fe8 1908
b24e7179
JB		 1909 reg = DSPCNTR(plane);
1910 val = I915_READ(reg);
00d70b15
CW		 1911 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1912 return;
1913
1914 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1dba99f4 1915 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1916 intel_wait_for_vblank(dev_priv->dev, pipe);
1917}
1918
693db184
CW		 1919static bool need_vtd_wa(struct drm_device *dev)
1920{
1921#ifdef CONFIG_INTEL_IOMMU
1922 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1923 return true;
1924#endif
1925 return false;
1926}
1927
127bd2ac 1928int
48b956c5 1929intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1930 struct drm_i915_gem_object *obj,
919926ae 1931 struct intel_ring_buffer *pipelined)
6b95a207 1932{
ce453d81 1933 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1934 u32 alignment;
1935 int ret;
1936
05394f39 1937 switch (obj->tiling_mode) {
6b95a207 1938 case I915_TILING_NONE:
534843da
CW		 1939 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1940 alignment = 128 * 1024;
a6c45cf0 1941 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1942 alignment = 4 * 1024;
1943 else
1944 alignment = 64 * 1024;
6b95a207
KH		 1945 break;
1946 case I915_TILING_X:
1947 /* pin() will align the object as required by fence */
1948 alignment = 0;
1949 break;
1950 case I915_TILING_Y:
80075d49 1951 WARN(1, "Y tiled bo slipped through, driver bug!\n");
6b95a207
KH		 1952 return -EINVAL;
1953 default:
1954 BUG();
1955 }
1956
693db184
CW		 1957 /* Note that the w/a also requires 64 PTE of padding following the
1958 * bo. We currently fill all unused PTE with the shadow page and so
1959 * we should always have valid PTE following the scanout preventing
1960 * the VT-d warning.
1961 */
1962 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1963 alignment = 256 * 1024;
1964
ce453d81 1965 dev_priv->mm.interruptible = false;
2da3b9b9 1966 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1967 if (ret)
ce453d81 1968 goto err_interruptible;
6b95a207
KH		 1969
1970 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971 * fence, whereas 965+ only requires a fence if using
1972 * framebuffer compression. For simplicity, we always install
1973 * a fence as the cost is not that onerous.
1974 */
06d98131 1975 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1976 if (ret)
1977 goto err_unpin;
1690e1eb 1978
9a5a53b3 1979 i915_gem_object_pin_fence(obj);
6b95a207 1980
ce453d81 1981 dev_priv->mm.interruptible = true;
6b95a207 1982 return 0;
48b956c5
CW		 1983
1984err_unpin:
cc98b413 1985 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1986err_interruptible:
1987 dev_priv->mm.interruptible = true;
48b956c5 1988 return ret;
6b95a207
KH		 1989}
1990
1690e1eb
CW		 1991void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1992{
1993 i915_gem_object_unpin_fence(obj);
cc98b413 1994 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1995}
1996
c2c75131
DV		 1997/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1998 * is assumed to be a power-of-two. */
bc752862
CW		 1999unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2000 unsigned int tiling_mode,
2001 unsigned int cpp,
2002 unsigned int pitch)
c2c75131 2003{
bc752862
CW		 2004 if (tiling_mode != I915_TILING_NONE) {
2005 unsigned int tile_rows, tiles;
c2c75131 2006
bc752862
CW		 2007 tile_rows = *y / 8;
2008 *y %= 8;
c2c75131 2009
bc752862
CW		 2010 tiles = *x / (512/cpp);
2011 *x %= 512/cpp;
2012
2013 return tile_rows * pitch * 8 + tiles * 4096;
2014 } else {
2015 unsigned int offset;
2016
2017 offset = *y * pitch + *x * cpp;
2018 *y = 0;
2019 *x = (offset & 4095) / cpp;
2020 return offset & -4096;
2021 }
c2c75131
DV		 2022}
2023
17638cd6
JB		 2024static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2025 int x, int y)
81255565
JB		 2026{
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
05394f39 2031 struct drm_i915_gem_object *obj;
81255565 2032 int plane = intel_crtc->plane;
e506a0c6 2033 unsigned long linear_offset;
81255565 2034 u32 dspcntr;
5eddb70b 2035 u32 reg;
81255565
JB		 2036
2037 switch (plane) {
2038 case 0:
2039 case 1:
2040 break;
2041 default:
84f44ce7 2042 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2043 return -EINVAL;
2044 }
2045
2046 intel_fb = to_intel_framebuffer(fb);
2047 obj = intel_fb->obj;
81255565 2048
5eddb70b
CW		 2049 reg = DSPCNTR(plane);
2050 dspcntr = I915_READ(reg);
81255565
JB		 2051 /* Mask out pixel format bits in case we change it */
2052 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2053 switch (fb->pixel_format) {
2054 case DRM_FORMAT_C8:
81255565
JB		 2055 dspcntr |= DISPPLANE_8BPP;
2056 break;
57779d06
VS		 2057 case DRM_FORMAT_XRGB1555:
2058 case DRM_FORMAT_ARGB1555:
2059 dspcntr |= DISPPLANE_BGRX555;
81255565 2060 break;
57779d06
VS		 2061 case DRM_FORMAT_RGB565:
2062 dspcntr |= DISPPLANE_BGRX565;
2063 break;
2064 case DRM_FORMAT_XRGB8888:
2065 case DRM_FORMAT_ARGB8888:
2066 dspcntr |= DISPPLANE_BGRX888;
2067 break;
2068 case DRM_FORMAT_XBGR8888:
2069 case DRM_FORMAT_ABGR8888:
2070 dspcntr |= DISPPLANE_RGBX888;
2071 break;
2072 case DRM_FORMAT_XRGB2101010:
2073 case DRM_FORMAT_ARGB2101010:
2074 dspcntr |= DISPPLANE_BGRX101010;
2075 break;
2076 case DRM_FORMAT_XBGR2101010:
2077 case DRM_FORMAT_ABGR2101010:
2078 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2079 break;
2080 default:
baba133a 2081 BUG();
81255565 2082 }
57779d06 2083
a6c45cf0 2084 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2085 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2086 dspcntr |= DISPPLANE_TILED;
2087 else
2088 dspcntr &= ~DISPPLANE_TILED;
2089 }
2090
de1aa629
VS		 2091 if (IS_G4X(dev))
2092 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2093
5eddb70b 2094 I915_WRITE(reg, dspcntr);
81255565 2095
e506a0c6 2096 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2097
c2c75131
DV		 2098 if (INTEL_INFO(dev)->gen >= 4) {
2099 intel_crtc->dspaddr_offset =
bc752862
CW		 2100 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2101 fb->bits_per_pixel / 8,
2102 fb->pitches[0]);
c2c75131
DV		 2103 linear_offset -= intel_crtc->dspaddr_offset;
2104 } else {
e506a0c6 2105 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2106 }
e506a0c6 2107
f343c5f6
BW		 2108 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2109 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2110 fb->pitches[0]);
01f2c773 2111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2112 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2113 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2114 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2115 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2116 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2117 } else
f343c5f6 2118 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2119 POSTING_READ(reg);
81255565 2120
17638cd6
JB		 2121 return 0;
2122}
2123
2124static int ironlake_update_plane(struct drm_crtc *crtc,
2125 struct drm_framebuffer *fb, int x, int y)
2126{
2127 struct drm_device *dev = crtc->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130 struct intel_framebuffer *intel_fb;
2131 struct drm_i915_gem_object *obj;
2132 int plane = intel_crtc->plane;
e506a0c6 2133 unsigned long linear_offset;
17638cd6
JB		 2134 u32 dspcntr;
2135 u32 reg;
2136
2137 switch (plane) {
2138 case 0:
2139 case 1:
27f8227b 2140 case 2:
17638cd6
JB		 2141 break;
2142 default:
84f44ce7 2143 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2144 return -EINVAL;
2145 }
2146
2147 intel_fb = to_intel_framebuffer(fb);
2148 obj = intel_fb->obj;
2149
2150 reg = DSPCNTR(plane);
2151 dspcntr = I915_READ(reg);
2152 /* Mask out pixel format bits in case we change it */
2153 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2154 switch (fb->pixel_format) {
2155 case DRM_FORMAT_C8:
17638cd6
JB		 2156 dspcntr |= DISPPLANE_8BPP;
2157 break;
57779d06
VS		 2158 case DRM_FORMAT_RGB565:
2159 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2160 break;
57779d06
VS		 2161 case DRM_FORMAT_XRGB8888:
2162 case DRM_FORMAT_ARGB8888:
2163 dspcntr |= DISPPLANE_BGRX888;
2164 break;
2165 case DRM_FORMAT_XBGR8888:
2166 case DRM_FORMAT_ABGR8888:
2167 dspcntr |= DISPPLANE_RGBX888;
2168 break;
2169 case DRM_FORMAT_XRGB2101010:
2170 case DRM_FORMAT_ARGB2101010:
2171 dspcntr |= DISPPLANE_BGRX101010;
2172 break;
2173 case DRM_FORMAT_XBGR2101010:
2174 case DRM_FORMAT_ABGR2101010:
2175 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2176 break;
2177 default:
baba133a 2178 BUG();
17638cd6
JB		 2179 }
2180
2181 if (obj->tiling_mode != I915_TILING_NONE)
2182 dspcntr |= DISPPLANE_TILED;
2183 else
2184 dspcntr &= ~DISPPLANE_TILED;
2185
b42c6009 2186 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1f5d76db
PZ		 2187 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2188 else
2189 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2190
2191 I915_WRITE(reg, dspcntr);
2192
e506a0c6 2193 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2194 intel_crtc->dspaddr_offset =
bc752862
CW		 2195 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2196 fb->bits_per_pixel / 8,
2197 fb->pitches[0]);
c2c75131 2198 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2199
f343c5f6
BW		 2200 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2201 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2202 fb->pitches[0]);
01f2c773 2203 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2204 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2205 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2206 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2207 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208 } else {
2209 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211 }
17638cd6
JB		 2212 POSTING_READ(reg);
2213
2214 return 0;
2215}
2216
2217/* Assume fb object is pinned & idle & fenced and just update base pointers */
2218static int
2219intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220 int x, int y, enum mode_set_atomic state)
2221{
2222 struct drm_device *dev = crtc->dev;
2223 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2224
6b8e6ed0
CW		 2225 if (dev_priv->display.disable_fbc)
2226 dev_priv->display.disable_fbc(dev);
3dec0095 2227 intel_increase_pllclock(crtc);
81255565 2228
6b8e6ed0 2229 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2230}
2231
96a02917
VS		 2232void intel_display_handle_reset(struct drm_device *dev)
2233{
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct drm_crtc *crtc;
2236
2237 /*
2238 * Flips in the rings have been nuked by the reset,
2239 * so complete all pending flips so that user space
2240 * will get its events and not get stuck.
2241 *
2242 * Also update the base address of all primary
2243 * planes to the the last fb to make sure we're
2244 * showing the correct fb after a reset.
2245 *
2246 * Need to make two loops over the crtcs so that we
2247 * don't try to grab a crtc mutex before the
2248 * pending_flip_queue really got woken up.
2249 */
2250
2251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253 enum plane plane = intel_crtc->plane;
2254
2255 intel_prepare_page_flip(dev, plane);
2256 intel_finish_page_flip_plane(dev, plane);
2257 }
2258
2259 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2261
2262 mutex_lock(&crtc->mutex);
947fdaad
CW		 2263 /*
2264 * FIXME: Once we have proper support for primary planes (and
2265 * disabling them without disabling the entire crtc) allow again
2266 * a NULL crtc->fb.
2267 */
2268 if (intel_crtc->active && crtc->fb)
96a02917
VS		 2269 dev_priv->display.update_plane(crtc, crtc->fb,
2270 crtc->x, crtc->y);
2271 mutex_unlock(&crtc->mutex);
2272 }
2273}
2274
14667a4b
CW		 2275static int
2276intel_finish_fb(struct drm_framebuffer *old_fb)
2277{
2278 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2279 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2280 bool was_interruptible = dev_priv->mm.interruptible;
2281 int ret;
2282
14667a4b
CW		 2283 /* Big Hammer, we also need to ensure that any pending
2284 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2285 * current scanout is retired before unpinning the old
2286 * framebuffer.
2287 *
2288 * This should only fail upon a hung GPU, in which case we
2289 * can safely continue.
2290 */
2291 dev_priv->mm.interruptible = false;
2292 ret = i915_gem_object_finish_gpu(obj);
2293 dev_priv->mm.interruptible = was_interruptible;
2294
2295 return ret;
2296}
2297
198598d0
VS		 2298static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2299{
2300 struct drm_device *dev = crtc->dev;
2301 struct drm_i915_master_private *master_priv;
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303
2304 if (!dev->primary->master)
2305 return;
2306
2307 master_priv = dev->primary->master->driver_priv;
2308 if (!master_priv->sarea_priv)
2309 return;
2310
2311 switch (intel_crtc->pipe) {
2312 case 0:
2313 master_priv->sarea_priv->pipeA_x = x;
2314 master_priv->sarea_priv->pipeA_y = y;
2315 break;
2316 case 1:
2317 master_priv->sarea_priv->pipeB_x = x;
2318 master_priv->sarea_priv->pipeB_y = y;
2319 break;
2320 default:
2321 break;
2322 }
2323}
2324
5c3b82e2 2325static int
3c4fdcfb 2326intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2327 struct drm_framebuffer *fb)
79e53945
JB		 2328{
2329 struct drm_device *dev = crtc->dev;
6b8e6ed0 2330 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2332 struct drm_framebuffer *old_fb;
5c3b82e2 2333 int ret;
79e53945
JB		 2334
2335 /* no fb bound */
94352cf9 2336 if (!fb) {
a5071c2f 2337 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2338 return 0;
2339 }
2340
7eb552ae 2341 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2342 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2343 plane_name(intel_crtc->plane),
2344 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2345 return -EINVAL;
79e53945
JB		 2346 }
2347
5c3b82e2 2348 mutex_lock(&dev->struct_mutex);
265db958 2349 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2350 to_intel_framebuffer(fb)->obj,
919926ae 2351 NULL);
5c3b82e2
CW		 2352 if (ret != 0) {
2353 mutex_unlock(&dev->struct_mutex);
a5071c2f 2354 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2355 return ret;
2356 }
79e53945 2357
bb2043de
DL		 2358 /*
2359 * Update pipe size and adjust fitter if needed: the reason for this is
2360 * that in compute_mode_changes we check the native mode (not the pfit
2361 * mode) to see if we can flip rather than do a full mode set. In the
2362 * fastboot case, we'll flip, but if we don't update the pipesrc and
2363 * pfit state, we'll end up with a big fb scanned out into the wrong
2364 * sized surface.
2365 *
2366 * To fix this properly, we need to hoist the checks up into
2367 * compute_mode_changes (or above), check the actual pfit state and
2368 * whether the platform allows pfit disable with pipe active, and only
2369 * then update the pipesrc and pfit state, even on the flip path.
2370 */
4d6a3e63 2371 if (i915_fastboot) {
d7bf63f2
DL		 2372 const struct drm_display_mode *adjusted_mode =
2373 &intel_crtc->config.adjusted_mode;
2374
4d6a3e63 2375 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2376 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2377 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2378 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2379 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2381 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2382 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2383 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2384 }
0637d60d
JB		 2385 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2386 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
4d6a3e63
JB		 2387 }
2388
94352cf9 2389 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2390 if (ret) {
94352cf9 2391 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2392 mutex_unlock(&dev->struct_mutex);
a5071c2f 2393 DRM_ERROR("failed to update base address\n");
4e6cfefc 2394 return ret;
79e53945 2395 }
3c4fdcfb 2396
94352cf9
DV		 2397 old_fb = crtc->fb;
2398 crtc->fb = fb;
6c4c86f5
DV		 2399 crtc->x = x;
2400 crtc->y = y;
94352cf9 2401
b7f1de28 2402 if (old_fb) {
d7697eea
DV		 2403 if (intel_crtc->active && old_fb != fb)
2404 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2405 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2406 }
652c393a 2407
6b8e6ed0 2408 intel_update_fbc(dev);
4906557e 2409 intel_edp_psr_update(dev);
5c3b82e2 2410 mutex_unlock(&dev->struct_mutex);
79e53945 2411
198598d0 2412 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2413
2414 return 0;
79e53945
JB		 2415}
2416
5e84e1a4
ZW		 2417static void intel_fdi_normal_train(struct drm_crtc *crtc)
2418{
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
2423 u32 reg, temp;
2424
2425 /* enable normal train */
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
61e499bf 2428 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2429 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2430 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2431 } else {
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2434 }
5e84e1a4
ZW		 2435 I915_WRITE(reg, temp);
2436
2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 if (HAS_PCH_CPT(dev)) {
2440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2441 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2442 } else {
2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_NONE;
2445 }
2446 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2447
2448 /* wait one idle pattern time */
2449 POSTING_READ(reg);
2450 udelay(1000);
357555c0
JB		 2451
2452 /* IVB wants error correction enabled */
2453 if (IS_IVYBRIDGE(dev))
2454 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2455 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2456}
2457
1fbc0d78 2458static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
1e833f40 2459{
1fbc0d78
DV		 2460 return crtc->base.enabled && crtc->active &&
2461 crtc->config.has_pch_encoder;
1e833f40
DV		 2462}
2463
01a415fd
DV		 2464static void ivb_modeset_global_resources(struct drm_device *dev)
2465{
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *pipe_B_crtc =
2468 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2469 struct intel_crtc *pipe_C_crtc =
2470 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2471 uint32_t temp;
2472
1e833f40
DV		 2473 /*
2474 * When everything is off disable fdi C so that we could enable fdi B
2475 * with all lanes. Note that we don't care about enabled pipes without
2476 * an enabled pch encoder.
2477 */
2478 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2479 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2480 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2482
2483 temp = I915_READ(SOUTH_CHICKEN1);
2484 temp &= ~FDI_BC_BIFURCATION_SELECT;
2485 DRM_DEBUG_KMS("disabling fdi C rx\n");
2486 I915_WRITE(SOUTH_CHICKEN1, temp);
2487 }
2488}
2489
8db9d77b
ZW		 2490/* The FDI link training functions for ILK/Ibexpeak. */
2491static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2492{
2493 struct drm_device *dev = crtc->dev;
2494 struct drm_i915_private *dev_priv = dev->dev_private;
2495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2496 int pipe = intel_crtc->pipe;
0fc932b8 2497 int plane = intel_crtc->plane;
5eddb70b 2498 u32 reg, temp, tries;
8db9d77b 2499
0fc932b8
JB		 2500 /* FDI needs bits from pipe & plane first */
2501 assert_pipe_enabled(dev_priv, pipe);
2502 assert_plane_enabled(dev_priv, plane);
2503
e1a44743
AJ		 2504 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2505 for train result */
5eddb70b
CW		 2506 reg = FDI_RX_IMR(pipe);
2507 temp = I915_READ(reg);
e1a44743
AJ		 2508 temp &= ~FDI_RX_SYMBOL_LOCK;
2509 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2510 I915_WRITE(reg, temp);
2511 I915_READ(reg);
e1a44743
AJ		 2512 udelay(150);
2513
8db9d77b 2514 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2515 reg = FDI_TX_CTL(pipe);
2516 temp = I915_READ(reg);
627eb5a3
DV		 2517 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2518 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2522
5eddb70b
CW		 2523 reg = FDI_RX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2527 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2528
2529 POSTING_READ(reg);
8db9d77b
ZW		 2530 udelay(150);
2531
5b2adf89 2532 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2533 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2535 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2536
5eddb70b 2537 reg = FDI_RX_IIR(pipe);
e1a44743 2538 for (tries = 0; tries < 5; tries++) {
5eddb70b 2539 temp = I915_READ(reg);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541
2542 if ((temp & FDI_RX_BIT_LOCK)) {
2543 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2544 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2545 break;
2546 }
8db9d77b 2547 }
e1a44743 2548 if (tries == 5)
5eddb70b 2549 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2550
2551 /* Train 2 */
5eddb70b
CW		 2552 reg = FDI_TX_CTL(pipe);
2553 temp = I915_READ(reg);
8db9d77b
ZW		 2554 temp &= ~FDI_LINK_TRAIN_NONE;
2555 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2556 I915_WRITE(reg, temp);
8db9d77b 2557
5eddb70b
CW		 2558 reg = FDI_RX_CTL(pipe);
2559 temp = I915_READ(reg);
8db9d77b
ZW		 2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2562 I915_WRITE(reg, temp);
8db9d77b 2563
5eddb70b
CW		 2564 POSTING_READ(reg);
2565 udelay(150);
8db9d77b 2566
5eddb70b 2567 reg = FDI_RX_IIR(pipe);
e1a44743 2568 for (tries = 0; tries < 5; tries++) {
5eddb70b 2569 temp = I915_READ(reg);
8db9d77b
ZW		 2570 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2571
2572 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2573 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2574 DRM_DEBUG_KMS("FDI train 2 done.\n");
2575 break;
2576 }
8db9d77b 2577 }
e1a44743 2578 if (tries == 5)
5eddb70b 2579 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2580
2581 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2582
8db9d77b
ZW		 2583}
2584
0206e353 2585static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2586 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2587 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2588 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2589 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2590};
2591
2592/* The FDI link training functions for SNB/Cougarpoint. */
2593static void gen6_fdi_link_train(struct drm_crtc *crtc)
2594{
2595 struct drm_device *dev = crtc->dev;
2596 struct drm_i915_private *dev_priv = dev->dev_private;
2597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2598 int pipe = intel_crtc->pipe;
fa37d39e 2599 u32 reg, temp, i, retry;
8db9d77b 2600
e1a44743
AJ		 2601 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2602 for train result */
5eddb70b
CW		 2603 reg = FDI_RX_IMR(pipe);
2604 temp = I915_READ(reg);
e1a44743
AJ		 2605 temp &= ~FDI_RX_SYMBOL_LOCK;
2606 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2607 I915_WRITE(reg, temp);
2608
2609 POSTING_READ(reg);
e1a44743
AJ		 2610 udelay(150);
2611
8db9d77b 2612 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2613 reg = FDI_TX_CTL(pipe);
2614 temp = I915_READ(reg);
627eb5a3
DV		 2615 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2616 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2617 temp &= ~FDI_LINK_TRAIN_NONE;
2618 temp |= FDI_LINK_TRAIN_PATTERN_1;
2619 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2620 /* SNB-B */
2621 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2622 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2623
d74cf324
DV		 2624 I915_WRITE(FDI_RX_MISC(pipe),
2625 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2626
5eddb70b
CW		 2627 reg = FDI_RX_CTL(pipe);
2628 temp = I915_READ(reg);
8db9d77b
ZW		 2629 if (HAS_PCH_CPT(dev)) {
2630 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2632 } else {
2633 temp &= ~FDI_LINK_TRAIN_NONE;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1;
2635 }
5eddb70b
CW		 2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
8db9d77b
ZW		 2639 udelay(150);
2640
0206e353 2641 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
8db9d77b
ZW		 2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
8db9d77b
ZW		 2649 udelay(500);
2650
fa37d39e
SP		 2651 for (retry = 0; retry < 5; retry++) {
2652 reg = FDI_RX_IIR(pipe);
2653 temp = I915_READ(reg);
2654 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655 if (temp & FDI_RX_BIT_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2657 DRM_DEBUG_KMS("FDI train 1 done.\n");
2658 break;
2659 }
2660 udelay(50);
8db9d77b 2661 }
fa37d39e
SP		 2662 if (retry < 5)
2663 break;
8db9d77b
ZW		 2664 }
2665 if (i == 4)
5eddb70b 2666 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2667
2668 /* Train 2 */
5eddb70b
CW		 2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
8db9d77b
ZW		 2671 temp &= ~FDI_LINK_TRAIN_NONE;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2;
2673 if (IS_GEN6(dev)) {
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 /* SNB-B */
2676 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2677 }
5eddb70b 2678 I915_WRITE(reg, temp);
8db9d77b 2679
5eddb70b
CW		 2680 reg = FDI_RX_CTL(pipe);
2681 temp = I915_READ(reg);
8db9d77b
ZW		 2682 if (HAS_PCH_CPT(dev)) {
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685 } else {
2686 temp &= ~FDI_LINK_TRAIN_NONE;
2687 temp |= FDI_LINK_TRAIN_PATTERN_2;
2688 }
5eddb70b
CW		 2689 I915_WRITE(reg, temp);
2690
2691 POSTING_READ(reg);
8db9d77b
ZW		 2692 udelay(150);
2693
0206e353 2694 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2695 reg = FDI_TX_CTL(pipe);
2696 temp = I915_READ(reg);
8db9d77b
ZW		 2697 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2698 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2699 I915_WRITE(reg, temp);
2700
2701 POSTING_READ(reg);
8db9d77b
ZW		 2702 udelay(500);
2703
fa37d39e
SP		 2704 for (retry = 0; retry < 5; retry++) {
2705 reg = FDI_RX_IIR(pipe);
2706 temp = I915_READ(reg);
2707 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708 if (temp & FDI_RX_SYMBOL_LOCK) {
2709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2710 DRM_DEBUG_KMS("FDI train 2 done.\n");
2711 break;
2712 }
2713 udelay(50);
8db9d77b 2714 }
fa37d39e
SP		 2715 if (retry < 5)
2716 break;
8db9d77b
ZW		 2717 }
2718 if (i == 4)
5eddb70b 2719 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2720
2721 DRM_DEBUG_KMS("FDI train done.\n");
2722}
2723
357555c0
JB		 2724/* Manual link training for Ivy Bridge A0 parts */
2725static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2726{
2727 struct drm_device *dev = crtc->dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2730 int pipe = intel_crtc->pipe;
139ccd3f 2731 u32 reg, temp, i, j;
357555c0
JB		 2732
2733 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2734 for train result */
2735 reg = FDI_RX_IMR(pipe);
2736 temp = I915_READ(reg);
2737 temp &= ~FDI_RX_SYMBOL_LOCK;
2738 temp &= ~FDI_RX_BIT_LOCK;
2739 I915_WRITE(reg, temp);
2740
2741 POSTING_READ(reg);
2742 udelay(150);
2743
01a415fd
DV		 2744 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2745 I915_READ(FDI_RX_IIR(pipe)));
2746
139ccd3f
JB		 2747 /* Try each vswing and preemphasis setting twice before moving on */
2748 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2749 /* disable first in case we need to retry */
2750 reg = FDI_TX_CTL(pipe);
2751 temp = I915_READ(reg);
2752 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2753 temp &= ~FDI_TX_ENABLE;
2754 I915_WRITE(reg, temp);
357555c0 2755
139ccd3f
JB		 2756 reg = FDI_RX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 temp &= ~FDI_LINK_TRAIN_AUTO;
2759 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2760 temp &= ~FDI_RX_ENABLE;
2761 I915_WRITE(reg, temp);
357555c0 2762
139ccd3f 2763 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
139ccd3f
JB		 2766 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2767 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2768 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2769 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2770 temp |= snb_b_fdi_train_param[j/2];
2771 temp |= FDI_COMPOSITE_SYNC;
2772 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2773
139ccd3f
JB		 2774 I915_WRITE(FDI_RX_MISC(pipe),
2775 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2776
139ccd3f 2777 reg = FDI_RX_CTL(pipe);
357555c0 2778 temp = I915_READ(reg);
139ccd3f
JB		 2779 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2780 temp |= FDI_COMPOSITE_SYNC;
2781 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2782
139ccd3f
JB		 2783 POSTING_READ(reg);
2784 udelay(1); /* should be 0.5us */
357555c0 2785
139ccd3f
JB		 2786 for (i = 0; i < 4; i++) {
2787 reg = FDI_RX_IIR(pipe);
2788 temp = I915_READ(reg);
2789 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2790
139ccd3f
JB		 2791 if (temp & FDI_RX_BIT_LOCK ||
2792 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2793 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2794 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2795 i);
2796 break;
2797 }
2798 udelay(1); /* should be 0.5us */
2799 }
2800 if (i == 4) {
2801 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2802 continue;
2803 }
357555c0 2804
139ccd3f 2805 /* Train 2 */
357555c0
JB		 2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
139ccd3f
JB		 2808 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2809 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2810 I915_WRITE(reg, temp);
2811
2812 reg = FDI_RX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2815 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2816 I915_WRITE(reg, temp);
2817
2818 POSTING_READ(reg);
139ccd3f 2819 udelay(2); /* should be 1.5us */
357555c0 2820
139ccd3f
JB		 2821 for (i = 0; i < 4; i++) {
2822 reg = FDI_RX_IIR(pipe);
2823 temp = I915_READ(reg);
2824 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2825
139ccd3f
JB		 2826 if (temp & FDI_RX_SYMBOL_LOCK ||
2827 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2828 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2829 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2830 i);
2831 goto train_done;
2832 }
2833 udelay(2); /* should be 1.5us */
357555c0 2834 }
139ccd3f
JB		 2835 if (i == 4)
2836 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2837 }
357555c0 2838
139ccd3f 2839train_done:
357555c0
JB		 2840 DRM_DEBUG_KMS("FDI train done.\n");
2841}
2842
88cefb6c 2843static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2844{
88cefb6c 2845 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2846 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2847 int pipe = intel_crtc->pipe;
5eddb70b 2848 u32 reg, temp;
79e53945 2849
c64e311e 2850
c98e9dcf 2851 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2852 reg = FDI_RX_CTL(pipe);
2853 temp = I915_READ(reg);
627eb5a3
DV		 2854 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2855 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2856 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2857 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2858
2859 POSTING_READ(reg);
c98e9dcf
JB		 2860 udelay(200);
2861
2862 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2863 temp = I915_READ(reg);
2864 I915_WRITE(reg, temp | FDI_PCDCLK);
2865
2866 POSTING_READ(reg);
c98e9dcf
JB		 2867 udelay(200);
2868
20749730
PZ		 2869 /* Enable CPU FDI TX PLL, always on for Ironlake */
2870 reg = FDI_TX_CTL(pipe);
2871 temp = I915_READ(reg);
2872 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2873 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2874
20749730
PZ		 2875 POSTING_READ(reg);
2876 udelay(100);
6be4a607 2877 }
0e23b99d
JB		 2878}
2879
88cefb6c
DV		 2880static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2881{
2882 struct drm_device *dev = intel_crtc->base.dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 int pipe = intel_crtc->pipe;
2885 u32 reg, temp;
2886
2887 /* Switch from PCDclk to Rawclk */
2888 reg = FDI_RX_CTL(pipe);
2889 temp = I915_READ(reg);
2890 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2891
2892 /* Disable CPU FDI TX PLL */
2893 reg = FDI_TX_CTL(pipe);
2894 temp = I915_READ(reg);
2895 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2896
2897 POSTING_READ(reg);
2898 udelay(100);
2899
2900 reg = FDI_RX_CTL(pipe);
2901 temp = I915_READ(reg);
2902 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2903
2904 /* Wait for the clocks to turn off. */
2905 POSTING_READ(reg);
2906 udelay(100);
2907}
2908
0fc932b8
JB		 2909static void ironlake_fdi_disable(struct drm_crtc *crtc)
2910{
2911 struct drm_device *dev = crtc->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2914 int pipe = intel_crtc->pipe;
2915 u32 reg, temp;
2916
2917 /* disable CPU FDI tx and PCH FDI rx */
2918 reg = FDI_TX_CTL(pipe);
2919 temp = I915_READ(reg);
2920 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2921 POSTING_READ(reg);
2922
2923 reg = FDI_RX_CTL(pipe);
2924 temp = I915_READ(reg);
2925 temp &= ~(0x7 << 16);
dfd07d72 2926 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2927 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2928
2929 POSTING_READ(reg);
2930 udelay(100);
2931
2932 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2933 if (HAS_PCH_IBX(dev)) {
2934 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2935 }
0fc932b8
JB		 2936
2937 /* still set train pattern 1 */
2938 reg = FDI_TX_CTL(pipe);
2939 temp = I915_READ(reg);
2940 temp &= ~FDI_LINK_TRAIN_NONE;
2941 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942 I915_WRITE(reg, temp);
2943
2944 reg = FDI_RX_CTL(pipe);
2945 temp = I915_READ(reg);
2946 if (HAS_PCH_CPT(dev)) {
2947 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2948 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2949 } else {
2950 temp &= ~FDI_LINK_TRAIN_NONE;
2951 temp |= FDI_LINK_TRAIN_PATTERN_1;
2952 }
2953 /* BPC in FDI rx is consistent with that in PIPECONF */
2954 temp &= ~(0x07 << 16);
dfd07d72 2955 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2956 I915_WRITE(reg, temp);
2957
2958 POSTING_READ(reg);
2959 udelay(100);
2960}
2961
5bb61643
CW		 2962static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2963{
2964 struct drm_device *dev = crtc->dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2967 unsigned long flags;
2968 bool pending;
2969
10d83730
VS		 2970 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2971 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2972 return false;
2973
2974 spin_lock_irqsave(&dev->event_lock, flags);
2975 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2976 spin_unlock_irqrestore(&dev->event_lock, flags);
2977
2978 return pending;
2979}
2980
e6c3a2a6
CW		 2981static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2982{
0f91128d 2983 struct drm_device *dev = crtc->dev;
5bb61643 2984 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2985
2986 if (crtc->fb == NULL)
2987 return;
2988
2c10d571
DV		 2989 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2990
5bb61643
CW		 2991 wait_event(dev_priv->pending_flip_queue,
2992 !intel_crtc_has_pending_flip(crtc));
2993
0f91128d
CW		 2994 mutex_lock(&dev->struct_mutex);
2995 intel_finish_fb(crtc->fb);
2996 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2997}
2998
e615efe4
ED		 2999/* Program iCLKIP clock to the desired frequency */
3000static void lpt_program_iclkip(struct drm_crtc *crtc)
3001{
3002 struct drm_device *dev = crtc->dev;
3003 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 3004 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 3005 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006 u32 temp;
3007
09153000
DV		 3008 mutex_lock(&dev_priv->dpio_lock);
3009
e615efe4
ED		 3010 /* It is necessary to ungate the pixclk gate prior to programming
3011 * the divisors, and gate it back when it is done.
3012 */
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015 /* Disable SSCCTL */
3016 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3017 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018 SBI_SSCCTL_DISABLE,
3019 SBI_ICLK);
e615efe4
ED		 3020
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3022 if (clock == 20000) {
e615efe4
ED		 3023 auxdiv = 1;
3024 divsel = 0x41;
3025 phaseinc = 0x20;
3026 } else {
3027 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3028 * but the adjusted_mode->crtc_clock in in KHz. To get the
3029 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3030 * convert the virtual clock precision to KHz here for higher
3031 * precision.
3032 */
3033 u32 iclk_virtual_root_freq = 172800 * 1000;
3034 u32 iclk_pi_range = 64;
3035 u32 desired_divisor, msb_divisor_value, pi_value;
3036
12d7ceed 3037 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3038 msb_divisor_value = desired_divisor / iclk_pi_range;
3039 pi_value = desired_divisor % iclk_pi_range;
3040
3041 auxdiv = 0;
3042 divsel = msb_divisor_value - 2;
3043 phaseinc = pi_value;
3044 }
3045
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3053 clock,
e615efe4
ED		 3054 auxdiv,
3055 divsel,
3056 phasedir,
3057 phaseinc);
3058
3059 /* Program SSCDIVINTPHASE6 */
988d6ee8 3060 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3061 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3067 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3068
3069 /* Program SSCAUXDIV */
988d6ee8 3070 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3071 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3073 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3074
3075 /* Enable modulator and associated divider */
988d6ee8 3076 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3077 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3078 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3079
3080 /* Wait for initialization time */
3081 udelay(24);
3082
3083 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3084
3085 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3086}
3087
275f01b2
DV		 3088static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3089 enum pipe pch_transcoder)
3090{
3091 struct drm_device *dev = crtc->base.dev;
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3094
3095 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3096 I915_READ(HTOTAL(cpu_transcoder)));
3097 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3098 I915_READ(HBLANK(cpu_transcoder)));
3099 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3100 I915_READ(HSYNC(cpu_transcoder)));
3101
3102 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3103 I915_READ(VTOTAL(cpu_transcoder)));
3104 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3105 I915_READ(VBLANK(cpu_transcoder)));
3106 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3107 I915_READ(VSYNC(cpu_transcoder)));
3108 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3109 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3110}
3111
1fbc0d78
DV		 3112static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3113{
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 uint32_t temp;
3116
3117 temp = I915_READ(SOUTH_CHICKEN1);
3118 if (temp & FDI_BC_BIFURCATION_SELECT)
3119 return;
3120
3121 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3122 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3123
3124 temp |= FDI_BC_BIFURCATION_SELECT;
3125 DRM_DEBUG_KMS("enabling fdi C rx\n");
3126 I915_WRITE(SOUTH_CHICKEN1, temp);
3127 POSTING_READ(SOUTH_CHICKEN1);
3128}
3129
3130static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3131{
3132 struct drm_device *dev = intel_crtc->base.dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134
3135 switch (intel_crtc->pipe) {
3136 case PIPE_A:
3137 break;
3138 case PIPE_B:
3139 if (intel_crtc->config.fdi_lanes > 2)
3140 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3141 else
3142 cpt_enable_fdi_bc_bifurcation(dev);
3143
3144 break;
3145 case PIPE_C:
3146 cpt_enable_fdi_bc_bifurcation(dev);
3147
3148 break;
3149 default:
3150 BUG();
3151 }
3152}
3153
f67a559d
JB		 3154/*
3155 * Enable PCH resources required for PCH ports:
3156 * - PCH PLLs
3157 * - FDI training & RX/TX
3158 * - update transcoder timings
3159 * - DP transcoding bits
3160 * - transcoder
3161 */
3162static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 int pipe = intel_crtc->pipe;
ee7b9f93 3168 u32 reg, temp;
2c07245f 3169
ab9412ba 3170 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3171
1fbc0d78
DV		 3172 if (IS_IVYBRIDGE(dev))
3173 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3174
cd986abb
DV		 3175 /* Write the TU size bits before fdi link training, so that error
3176 * detection works. */
3177 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3178 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3179
c98e9dcf 3180 /* For PCH output, training FDI link */
674cf967 3181 dev_priv->display.fdi_link_train(crtc);
2c07245f 3182
3ad8a208
DV		 3183 /* We need to program the right clock selection before writing the pixel
3184 * mutliplier into the DPLL. */
303b81e0 3185 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3186 u32 sel;
4b645f14 3187
c98e9dcf 3188 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3189 temp |= TRANS_DPLL_ENABLE(pipe);
3190 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3191 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3192 temp |= sel;
3193 else
3194 temp &= ~sel;
c98e9dcf 3195 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3196 }
5eddb70b 3197
3ad8a208
DV		 3198 /* XXX: pch pll's can be enabled any time before we enable the PCH
3199 * transcoder, and we actually should do this to not upset any PCH
3200 * transcoder that already use the clock when we share it.
3201 *
3202 * Note that enable_shared_dpll tries to do the right thing, but
3203 * get_shared_dpll unconditionally resets the pll - we need that to have
3204 * the right LVDS enable sequence. */
3205 ironlake_enable_shared_dpll(intel_crtc);
3206
d9b6cb56
JB		 3207 /* set transcoder timing, panel must allow it */
3208 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3209 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3210
303b81e0 3211 intel_fdi_normal_train(crtc);
5e84e1a4 3212
c98e9dcf
JB		 3213 /* For PCH DP, enable TRANS_DP_CTL */
3214 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3215 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3216 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3217 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3218 reg = TRANS_DP_CTL(pipe);
3219 temp = I915_READ(reg);
3220 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3221 TRANS_DP_SYNC_MASK |
3222 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3223 temp |= (TRANS_DP_OUTPUT_ENABLE |
3224 TRANS_DP_ENH_FRAMING);
9325c9f0 3225 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3226
3227 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3228 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3229 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3230 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3231
3232 switch (intel_trans_dp_port_sel(crtc)) {
3233 case PCH_DP_B:
5eddb70b 3234 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3235 break;
3236 case PCH_DP_C:
5eddb70b 3237 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3238 break;
3239 case PCH_DP_D:
5eddb70b 3240 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3241 break;
3242 default:
e95d41e1 3243 BUG();
32f9d658 3244 }
2c07245f 3245
5eddb70b 3246 I915_WRITE(reg, temp);
6be4a607 3247 }
b52eb4dc 3248
b8a4f404 3249 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3250}
3251
1507e5bd
PZ		 3252static void lpt_pch_enable(struct drm_crtc *crtc)
3253{
3254 struct drm_device *dev = crtc->dev;
3255 struct drm_i915_private *dev_priv = dev->dev_private;
3256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3257 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3258
ab9412ba 3259 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3260
8c52b5e8 3261 lpt_program_iclkip(crtc);
1507e5bd 3262
0540e488 3263 /* Set transcoder timing. */
275f01b2 3264 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3265
937bb610 3266 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3267}
3268
e2b78267 3269static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3270{
e2b78267 3271 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3272
3273 if (pll == NULL)
3274 return;
3275
3276 if (pll->refcount == 0) {
46edb027 3277 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3278 return;
3279 }
3280
f4a091c7
DV		 3281 if (--pll->refcount == 0) {
3282 WARN_ON(pll->on);
3283 WARN_ON(pll->active);
3284 }
3285
a43f6e0f 3286 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3287}
3288
b89a1d39 3289static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3290{
e2b78267
DV		 3291 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3292 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3293 enum intel_dpll_id i;
ee7b9f93 3294
ee7b9f93 3295 if (pll) {
46edb027
DV		 3296 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3297 crtc->base.base.id, pll->name);
e2b78267 3298 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3299 }
3300
98b6bd99
DV		 3301 if (HAS_PCH_IBX(dev_priv->dev)) {
3302 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3303 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3304 pll = &dev_priv->shared_dplls[i];
98b6bd99 3305
46edb027
DV		 3306 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3307 crtc->base.base.id, pll->name);
98b6bd99
DV		 3308
3309 goto found;
3310 }
3311
e72f9fbf
DV		 3312 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3313 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3314
3315 /* Only want to check enabled timings first */
3316 if (pll->refcount == 0)
3317 continue;
3318
b89a1d39
DV		 3319 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3320 sizeof(pll->hw_state)) == 0) {
46edb027 3321 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3322 crtc->base.base.id,
46edb027 3323 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3324
3325 goto found;
3326 }
3327 }
3328
3329 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3330 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3331 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3332 if (pll->refcount == 0) {
46edb027
DV		 3333 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3334 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3335 goto found;
3336 }
3337 }
3338
3339 return NULL;
3340
3341found:
a43f6e0f 3342 crtc->config.shared_dpll = i;
46edb027
DV		 3343 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3344 pipe_name(crtc->pipe));
ee7b9f93 3345
cdbd2316 3346 if (pll->active == 0) {
66e985c0
DV		 3347 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3348 sizeof(pll->hw_state));
3349
46edb027 3350 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3351 WARN_ON(pll->on);
e9d6944e 3352 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3353
15bdd4cf 3354 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3355 }
3356 pll->refcount++;
e04c7350 3357
ee7b9f93
JB		 3358 return pll;
3359}
3360
a1520318 3361static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3362{
3363 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3364 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3365 u32 temp;
3366
3367 temp = I915_READ(dslreg);
3368 udelay(500);
3369 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3370 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3371 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3372 }
3373}
3374
b074cec8
JB		 3375static void ironlake_pfit_enable(struct intel_crtc *crtc)
3376{
3377 struct drm_device *dev = crtc->base.dev;
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379 int pipe = crtc->pipe;
3380
fd4daa9c 3381 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3382 /* Force use of hard-coded filter coefficients
3383 * as some pre-programmed values are broken,
3384 * e.g. x201.
3385 */
3386 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3387 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3388 PF_PIPE_SEL_IVB(pipe));
3389 else
3390 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3391 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3392 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3393 }
3394}
3395
bb53d4ae
VS		 3396static void intel_enable_planes(struct drm_crtc *crtc)
3397{
3398 struct drm_device *dev = crtc->dev;
3399 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3400 struct intel_plane *intel_plane;
3401
3402 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3403 if (intel_plane->pipe == pipe)
3404 intel_plane_restore(&intel_plane->base);
3405}
3406
3407static void intel_disable_planes(struct drm_crtc *crtc)
3408{
3409 struct drm_device *dev = crtc->dev;
3410 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3411 struct intel_plane *intel_plane;
3412
3413 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3414 if (intel_plane->pipe == pipe)
3415 intel_plane_disable(&intel_plane->base);
3416}
3417
20bc8673 3418void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3419{
3420 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3421
3422 if (!crtc->config.ips_enabled)
3423 return;
3424
3425 /* We can only enable IPS after we enable a plane and wait for a vblank.
3426 * We guarantee that the plane is enabled by calling intel_enable_ips
3427 * only after intel_enable_plane. And intel_enable_plane already waits
3428 * for a vblank, so all we need to do here is to enable the IPS bit. */
3429 assert_plane_enabled(dev_priv, crtc->plane);
2a114cc1
BW		 3430 if (IS_BROADWELL(crtc->base.dev)) {
3431 mutex_lock(&dev_priv->rps.hw_lock);
3432 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3433 mutex_unlock(&dev_priv->rps.hw_lock);
3434 /* Quoting Art Runyan: "its not safe to expect any particular
3435 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 3436 * mailbox." Moreover, the mailbox may return a bogus state,
3437 * so we need to just enable it and continue on.
2a114cc1
BW		 3438 */
3439 } else {
3440 I915_WRITE(IPS_CTL, IPS_ENABLE);
3441 /* The bit only becomes 1 in the next vblank, so this wait here
3442 * is essentially intel_wait_for_vblank. If we don't have this
3443 * and don't wait for vblanks until the end of crtc_enable, then
3444 * the HW state readout code will complain that the expected
3445 * IPS_CTL value is not the one we read. */
3446 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3447 DRM_ERROR("Timed out waiting for IPS enable\n");
3448 }
d77e4531
PZ		 3449}
3450
20bc8673 3451void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3452{
3453 struct drm_device *dev = crtc->base.dev;
3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455
3456 if (!crtc->config.ips_enabled)
3457 return;
3458
3459 assert_plane_enabled(dev_priv, crtc->plane);
2a114cc1
BW		 3460 if (IS_BROADWELL(crtc->base.dev)) {
3461 mutex_lock(&dev_priv->rps.hw_lock);
3462 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3463 mutex_unlock(&dev_priv->rps.hw_lock);
e59150dc 3464 } else {
2a114cc1 3465 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 3466 POSTING_READ(IPS_CTL);
3467 }
d77e4531
PZ		 3468
3469 /* We need to wait for a vblank before we can disable the plane. */
3470 intel_wait_for_vblank(dev, crtc->pipe);
3471}
3472
3473/** Loads the palette/gamma unit for the CRTC with the prepared values */
3474static void intel_crtc_load_lut(struct drm_crtc *crtc)
3475{
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 enum pipe pipe = intel_crtc->pipe;
3480 int palreg = PALETTE(pipe);
3481 int i;
3482 bool reenable_ips = false;
3483
3484 /* The clocks have to be on to load the palette. */
3485 if (!crtc->enabled || !intel_crtc->active)
3486 return;
3487
3488 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3489 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3490 assert_dsi_pll_enabled(dev_priv);
3491 else
3492 assert_pll_enabled(dev_priv, pipe);
3493 }
3494
3495 /* use legacy palette for Ironlake */
3496 if (HAS_PCH_SPLIT(dev))
3497 palreg = LGC_PALETTE(pipe);
3498
3499 /* Workaround : Do not read or write the pipe palette/gamma data while
3500 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3501 */
3502 if (intel_crtc->config.ips_enabled &&
3503 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3504 GAMMA_MODE_MODE_SPLIT)) {
3505 hsw_disable_ips(intel_crtc);
3506 reenable_ips = true;
3507 }
3508
3509 for (i = 0; i < 256; i++) {
3510 I915_WRITE(palreg + 4 * i,
3511 (intel_crtc->lut_r[i] << 16) |
3512 (intel_crtc->lut_g[i] << 8) |
3513 intel_crtc->lut_b[i]);
3514 }
3515
3516 if (reenable_ips)
3517 hsw_enable_ips(intel_crtc);
3518}
3519
f67a559d
JB		 3520static void ironlake_crtc_enable(struct drm_crtc *crtc)
3521{
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3525 struct intel_encoder *encoder;
f67a559d
JB		 3526 int pipe = intel_crtc->pipe;
3527 int plane = intel_crtc->plane;
f67a559d 3528
08a48469
DV		 3529 WARN_ON(!crtc->enabled);
3530
f67a559d
JB		 3531 if (intel_crtc->active)
3532 return;
3533
3534 intel_crtc->active = true;
8664281b
PZ		 3535
3536 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3537 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3538
f6736a1a 3539 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3540 if (encoder->pre_enable)
3541 encoder->pre_enable(encoder);
f67a559d 3542
5bfe2ac0 3543 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3544 /* Note: FDI PLL enabling _must_ be done before we enable the
3545 * cpu pipes, hence this is separate from all the other fdi/pch
3546 * enabling. */
88cefb6c 3547 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3548 } else {
3549 assert_fdi_tx_disabled(dev_priv, pipe);
3550 assert_fdi_rx_disabled(dev_priv, pipe);
3551 }
f67a559d 3552
b074cec8 3553 ironlake_pfit_enable(intel_crtc);
f67a559d 3554
9c54c0dd
JB		 3555 /*
3556 * On ILK+ LUT must be loaded before the pipe is running but with
3557 * clocks enabled
3558 */
3559 intel_crtc_load_lut(crtc);
3560
f37fcc2a 3561 intel_update_watermarks(crtc);
5bfe2ac0 3562 intel_enable_pipe(dev_priv, pipe,
23538ef1 3563 intel_crtc->config.has_pch_encoder, false);
d1de00ef 3564 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3565 intel_enable_planes(crtc);
5c38d48c 3566 intel_crtc_update_cursor(crtc, true);
f67a559d 3567
5bfe2ac0 3568 if (intel_crtc->config.has_pch_encoder)
f67a559d 3569 ironlake_pch_enable(crtc);
c98e9dcf 3570
d1ebd816 3571 mutex_lock(&dev->struct_mutex);
bed4a673 3572 intel_update_fbc(dev);
d1ebd816
BW		 3573 mutex_unlock(&dev->struct_mutex);
3574
fa5c73b1
DV		 3575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 encoder->enable(encoder);
61b77ddd
DV		 3577
3578 if (HAS_PCH_CPT(dev))
a1520318 3579 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3580
3581 /*
3582 * There seems to be a race in PCH platform hw (at least on some
3583 * outputs) where an enabled pipe still completes any pageflip right
3584 * away (as if the pipe is off) instead of waiting for vblank. As soon
3585 * as the first vblank happend, everything works as expected. Hence just
3586 * wait for one vblank before returning to avoid strange things
3587 * happening.
3588 */
3589 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3590}
3591
42db64ef
PZ		 3592/* IPS only exists on ULT machines and is tied to pipe A. */
3593static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3594{
f5adf94e 3595 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3596}
3597
dda9a66a
VS		 3598static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3599{
3600 struct drm_device *dev = crtc->dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603 int pipe = intel_crtc->pipe;
3604 int plane = intel_crtc->plane;
3605
d1de00ef 3606 intel_enable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3607 intel_enable_planes(crtc);
3608 intel_crtc_update_cursor(crtc, true);
3609
3610 hsw_enable_ips(intel_crtc);
3611
3612 mutex_lock(&dev->struct_mutex);
3613 intel_update_fbc(dev);
3614 mutex_unlock(&dev->struct_mutex);
3615}
3616
3617static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3618{
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 int pipe = intel_crtc->pipe;
3623 int plane = intel_crtc->plane;
3624
3625 intel_crtc_wait_for_pending_flips(crtc);
3626 drm_vblank_off(dev, pipe);
3627
3628 /* FBC must be disabled before disabling the plane on HSW. */
3629 if (dev_priv->fbc.plane == plane)
3630 intel_disable_fbc(dev);
3631
3632 hsw_disable_ips(intel_crtc);
3633
3634 intel_crtc_update_cursor(crtc, false);
3635 intel_disable_planes(crtc);
d1de00ef 3636 intel_disable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3637}
3638
e4916946
PZ		 3639/*
3640 * This implements the workaround described in the "notes" section of the mode
3641 * set sequence documentation. When going from no pipes or single pipe to
3642 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3643 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3644 */
3645static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3646{
3647 struct drm_device *dev = crtc->base.dev;
3648 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3649
3650 /* We want to get the other_active_crtc only if there's only 1 other
3651 * active crtc. */
3652 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3653 if (!crtc_it->active || crtc_it == crtc)
3654 continue;
3655
3656 if (other_active_crtc)
3657 return;
3658
3659 other_active_crtc = crtc_it;
3660 }
3661 if (!other_active_crtc)
3662 return;
3663
3664 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3665 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3666}
3667
4f771f10
PZ		 3668static void haswell_crtc_enable(struct drm_crtc *crtc)
3669{
3670 struct drm_device *dev = crtc->dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3673 struct intel_encoder *encoder;
3674 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3675
3676 WARN_ON(!crtc->enabled);
3677
3678 if (intel_crtc->active)
3679 return;
3680
3681 intel_crtc->active = true;
8664281b
PZ		 3682
3683 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3684 if (intel_crtc->config.has_pch_encoder)
3685 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3686
5bfe2ac0 3687 if (intel_crtc->config.has_pch_encoder)
04945641 3688 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3689
3690 for_each_encoder_on_crtc(dev, crtc, encoder)
3691 if (encoder->pre_enable)
3692 encoder->pre_enable(encoder);
3693
1f544388 3694 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3695
b074cec8 3696 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3697
3698 /*
3699 * On ILK+ LUT must be loaded before the pipe is running but with
3700 * clocks enabled
3701 */
3702 intel_crtc_load_lut(crtc);
3703
1f544388 3704 intel_ddi_set_pipe_settings(crtc);
8228c251 3705 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3706
f37fcc2a 3707 intel_update_watermarks(crtc);
5bfe2ac0 3708 intel_enable_pipe(dev_priv, pipe,
23538ef1 3709 intel_crtc->config.has_pch_encoder, false);
42db64ef 3710
5bfe2ac0 3711 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3712 lpt_pch_enable(crtc);
4f771f10 3713
8807e55b 3714 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3715 encoder->enable(encoder);
8807e55b
JN		 3716 intel_opregion_notify_encoder(encoder, true);
3717 }
4f771f10 3718
e4916946
PZ		 3719 /* If we change the relative order between pipe/planes enabling, we need
3720 * to change the workaround. */
3721 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3722 haswell_crtc_enable_planes(crtc);
3723
4f771f10
PZ		 3724 /*
3725 * There seems to be a race in PCH platform hw (at least on some
3726 * outputs) where an enabled pipe still completes any pageflip right
3727 * away (as if the pipe is off) instead of waiting for vblank. As soon
3728 * as the first vblank happend, everything works as expected. Hence just
3729 * wait for one vblank before returning to avoid strange things
3730 * happening.
3731 */
3732 intel_wait_for_vblank(dev, intel_crtc->pipe);
3733}
3734
3f8dce3a
DV		 3735static void ironlake_pfit_disable(struct intel_crtc *crtc)
3736{
3737 struct drm_device *dev = crtc->base.dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 int pipe = crtc->pipe;
3740
3741 /* To avoid upsetting the power well on haswell only disable the pfit if
3742 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3743 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3744 I915_WRITE(PF_CTL(pipe), 0);
3745 I915_WRITE(PF_WIN_POS(pipe), 0);
3746 I915_WRITE(PF_WIN_SZ(pipe), 0);
3747 }
3748}
3749
6be4a607
JB		 3750static void ironlake_crtc_disable(struct drm_crtc *crtc)
3751{
3752 struct drm_device *dev = crtc->dev;
3753 struct drm_i915_private *dev_priv = dev->dev_private;
3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3755 struct intel_encoder *encoder;
6be4a607
JB		 3756 int pipe = intel_crtc->pipe;
3757 int plane = intel_crtc->plane;
5eddb70b 3758 u32 reg, temp;
b52eb4dc 3759
ef9c3aee 3760
f7abfe8b
CW		 3761 if (!intel_crtc->active)
3762 return;
3763
ea9d758d
DV		 3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 encoder->disable(encoder);
3766
e6c3a2a6 3767 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3768 drm_vblank_off(dev, pipe);
913d8d11 3769
5c3fe8b0 3770 if (dev_priv->fbc.plane == plane)
973d04f9 3771 intel_disable_fbc(dev);
2c07245f 3772
0d5b8c61 3773 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3774 intel_disable_planes(crtc);
d1de00ef 3775 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3776
d925c59a
DV		 3777 if (intel_crtc->config.has_pch_encoder)
3778 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3779
b24e7179 3780 intel_disable_pipe(dev_priv, pipe);
32f9d658 3781
3f8dce3a 3782 ironlake_pfit_disable(intel_crtc);
2c07245f 3783
bf49ec8c
DV		 3784 for_each_encoder_on_crtc(dev, crtc, encoder)
3785 if (encoder->post_disable)
3786 encoder->post_disable(encoder);
2c07245f 3787
d925c59a
DV		 3788 if (intel_crtc->config.has_pch_encoder) {
3789 ironlake_fdi_disable(crtc);
913d8d11 3790
d925c59a
DV		 3791 ironlake_disable_pch_transcoder(dev_priv, pipe);
3792 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3793
d925c59a
DV		 3794 if (HAS_PCH_CPT(dev)) {
3795 /* disable TRANS_DP_CTL */
3796 reg = TRANS_DP_CTL(pipe);
3797 temp = I915_READ(reg);
3798 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3799 TRANS_DP_PORT_SEL_MASK);
3800 temp |= TRANS_DP_PORT_SEL_NONE;
3801 I915_WRITE(reg, temp);
3802
3803 /* disable DPLL_SEL */
3804 temp = I915_READ(PCH_DPLL_SEL);
11887397 3805 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3806 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3807 }
e3421a18 3808
d925c59a 3809 /* disable PCH DPLL */
e72f9fbf 3810 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3811
d925c59a
DV		 3812 ironlake_fdi_pll_disable(intel_crtc);
3813 }
6b383a7f 3814
f7abfe8b 3815 intel_crtc->active = false;
46ba614c 3816 intel_update_watermarks(crtc);
d1ebd816
BW		 3817
3818 mutex_lock(&dev->struct_mutex);
6b383a7f 3819 intel_update_fbc(dev);
d1ebd816 3820 mutex_unlock(&dev->struct_mutex);
6be4a607 3821}
1b3c7a47 3822
4f771f10 3823static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3824{
4f771f10
PZ		 3825 struct drm_device *dev = crtc->dev;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3828 struct intel_encoder *encoder;
3829 int pipe = intel_crtc->pipe;
3b117c8f 3830 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3831
4f771f10
PZ		 3832 if (!intel_crtc->active)
3833 return;
3834
dda9a66a
VS		 3835 haswell_crtc_disable_planes(crtc);
3836
8807e55b
JN		 3837 for_each_encoder_on_crtc(dev, crtc, encoder) {
3838 intel_opregion_notify_encoder(encoder, false);
4f771f10 3839 encoder->disable(encoder);
8807e55b 3840 }
4f771f10 3841
8664281b
PZ		 3842 if (intel_crtc->config.has_pch_encoder)
3843 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3844 intel_disable_pipe(dev_priv, pipe);
3845
ad80a810 3846 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3847
3f8dce3a 3848 ironlake_pfit_disable(intel_crtc);
4f771f10 3849
1f544388 3850 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3851
3852 for_each_encoder_on_crtc(dev, crtc, encoder)
3853 if (encoder->post_disable)
3854 encoder->post_disable(encoder);
3855
88adfff1 3856 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3857 lpt_disable_pch_transcoder(dev_priv);
8664281b 3858 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3859 intel_ddi_fdi_disable(crtc);
83616634 3860 }
4f771f10
PZ		 3861
3862 intel_crtc->active = false;
46ba614c 3863 intel_update_watermarks(crtc);
4f771f10
PZ		 3864
3865 mutex_lock(&dev->struct_mutex);
3866 intel_update_fbc(dev);
3867 mutex_unlock(&dev->struct_mutex);
3868}
3869
ee7b9f93
JB		 3870static void ironlake_crtc_off(struct drm_crtc *crtc)
3871{
3872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3873 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3874}
3875
6441ab5f
PZ		 3876static void haswell_crtc_off(struct drm_crtc *crtc)
3877{
3878 intel_ddi_put_crtc_pll(crtc);
3879}
3880
02e792fb
DV		 3881static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3882{
02e792fb 3883 if (!enable && intel_crtc->overlay) {
23f09ce3 3884 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3885 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3886
23f09ce3 3887 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3888 dev_priv->mm.interruptible = false;
3889 (void) intel_overlay_switch_off(intel_crtc->overlay);
3890 dev_priv->mm.interruptible = true;
23f09ce3 3891 mutex_unlock(&dev->struct_mutex);
02e792fb 3892 }
02e792fb 3893
5dcdbcb0
CW		 3894 /* Let userspace switch the overlay on again. In most cases userspace
3895 * has to recompute where to put it anyway.
3896 */
02e792fb
DV		 3897}
3898
61bc95c1
EE		 3899/**
3900 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3901 * cursor plane briefly if not already running after enabling the display
3902 * plane.
3903 * This workaround avoids occasional blank screens when self refresh is
3904 * enabled.
3905 */
3906static void
3907g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3908{
3909 u32 cntl = I915_READ(CURCNTR(pipe));
3910
3911 if ((cntl & CURSOR_MODE) == 0) {
3912 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3913
3914 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3915 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3916 intel_wait_for_vblank(dev_priv->dev, pipe);
3917 I915_WRITE(CURCNTR(pipe), cntl);
3918 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3919 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3920 }
3921}
3922
2dd24552
JB		 3923static void i9xx_pfit_enable(struct intel_crtc *crtc)
3924{
3925 struct drm_device *dev = crtc->base.dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 struct intel_crtc_config *pipe_config = &crtc->config;
3928
328d8e82 3929 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3930 return;
3931
2dd24552 3932 /*
c0b03411
DV		 3933 * The panel fitter should only be adjusted whilst the pipe is disabled,
3934 * according to register description and PRM.
2dd24552 3935 */
c0b03411
DV		 3936 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3937 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3938
b074cec8
JB		 3939 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3940 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3941
3942 /* Border color in case we don't scale up to the full screen. Black by
3943 * default, change to something else for debugging. */
3944 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3945}
3946
586f49dc 3947int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 3948{
586f49dc 3949 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 3950
586f49dc
JB		 3951 /* Obtain SKU information */
3952 mutex_lock(&dev_priv->dpio_lock);
3953 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3954 CCK_FUSE_HPLL_FREQ_MASK;
3955 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 3956
586f49dc 3957 return vco_freq[hpll_freq];
30a970c6
JB		 3958}
3959
3960/* Adjust CDclk dividers to allow high res or save power if possible */
3961static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3962{
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 u32 val, cmd;
3965
3966 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3967 cmd = 2;
3968 else if (cdclk == 266)
3969 cmd = 1;
3970 else
3971 cmd = 0;
3972
3973 mutex_lock(&dev_priv->rps.hw_lock);
3974 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3975 val &= ~DSPFREQGUAR_MASK;
3976 val |= (cmd << DSPFREQGUAR_SHIFT);
3977 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3978 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3979 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3980 50)) {
3981 DRM_ERROR("timed out waiting for CDclk change\n");
3982 }
3983 mutex_unlock(&dev_priv->rps.hw_lock);
3984
3985 if (cdclk == 400) {
3986 u32 divider, vco;
3987
3988 vco = valleyview_get_vco(dev_priv);
3989 divider = ((vco << 1) / cdclk) - 1;
3990
3991 mutex_lock(&dev_priv->dpio_lock);
3992 /* adjust cdclk divider */
3993 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3994 val &= ~0xf;
3995 val |= divider;
3996 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3997 mutex_unlock(&dev_priv->dpio_lock);
3998 }
3999
4000 mutex_lock(&dev_priv->dpio_lock);
4001 /* adjust self-refresh exit latency value */
4002 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4003 val &= ~0x7f;
4004
4005 /*
4006 * For high bandwidth configs, we set a higher latency in the bunit
4007 * so that the core display fetch happens in time to avoid underruns.
4008 */
4009 if (cdclk == 400)
4010 val |= 4500 / 250; /* 4.5 usec */
4011 else
4012 val |= 3000 / 250; /* 3.0 usec */
4013 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4014 mutex_unlock(&dev_priv->dpio_lock);
4015
4016 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4017 intel_i2c_reset(dev);
4018}
4019
4020static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4021{
4022 int cur_cdclk, vco;
4023 int divider;
4024
4025 vco = valleyview_get_vco(dev_priv);
4026
4027 mutex_lock(&dev_priv->dpio_lock);
4028 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4029 mutex_unlock(&dev_priv->dpio_lock);
4030
4031 divider &= 0xf;
4032
4033 cur_cdclk = (vco << 1) / (divider + 1);
4034
4035 return cur_cdclk;
4036}
4037
4038static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4039 int max_pixclk)
4040{
4041 int cur_cdclk;
4042
4043 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4044
4045 /*
4046 * Really only a few cases to deal with, as only 4 CDclks are supported:
4047 * 200MHz
4048 * 267MHz
4049 * 320MHz
4050 * 400MHz
4051 * So we check to see whether we're above 90% of the lower bin and
4052 * adjust if needed.
4053 */
4054 if (max_pixclk > 288000) {
4055 return 400;
4056 } else if (max_pixclk > 240000) {
4057 return 320;
4058 } else
4059 return 266;
4060 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4061}
4062
4063static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4064 unsigned modeset_pipes,
4065 struct intel_crtc_config *pipe_config)
4066{
4067 struct drm_device *dev = dev_priv->dev;
4068 struct intel_crtc *intel_crtc;
4069 int max_pixclk = 0;
4070
4071 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4072 base.head) {
4073 if (modeset_pipes & (1 << intel_crtc->pipe))
4074 max_pixclk = max(max_pixclk,
4075 pipe_config->adjusted_mode.crtc_clock);
4076 else if (intel_crtc->base.enabled)
4077 max_pixclk = max(max_pixclk,
4078 intel_crtc->config.adjusted_mode.crtc_clock);
4079 }
4080
4081 return max_pixclk;
4082}
4083
4084static void valleyview_modeset_global_pipes(struct drm_device *dev,
4085 unsigned *prepare_pipes,
4086 unsigned modeset_pipes,
4087 struct intel_crtc_config *pipe_config)
4088{
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 struct intel_crtc *intel_crtc;
4091 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4092 pipe_config);
4093 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4094
4095 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4096 return;
4097
4098 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4099 base.head)
4100 if (intel_crtc->base.enabled)
4101 *prepare_pipes |= (1 << intel_crtc->pipe);
4102}
4103
4104static void valleyview_modeset_global_resources(struct drm_device *dev)
4105{
4106 struct drm_i915_private *dev_priv = dev->dev_private;
4107 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4108 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4109 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4110
4111 if (req_cdclk != cur_cdclk)
4112 valleyview_set_cdclk(dev, req_cdclk);
4113}
4114
89b667f8
JB		 4115static void valleyview_crtc_enable(struct drm_crtc *crtc)
4116{
4117 struct drm_device *dev = crtc->dev;
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4120 struct intel_encoder *encoder;
4121 int pipe = intel_crtc->pipe;
4122 int plane = intel_crtc->plane;
23538ef1 4123 bool is_dsi;
89b667f8
JB		 4124
4125 WARN_ON(!crtc->enabled);
4126
4127 if (intel_crtc->active)
4128 return;
4129
4130 intel_crtc->active = true;
89b667f8 4131
89b667f8
JB		 4132 for_each_encoder_on_crtc(dev, crtc, encoder)
4133 if (encoder->pre_pll_enable)
4134 encoder->pre_pll_enable(encoder);
4135
23538ef1
JN		 4136 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4137
e9fd1c02
JN		 4138 if (!is_dsi)
4139 vlv_enable_pll(intel_crtc);
89b667f8
JB		 4140
4141 for_each_encoder_on_crtc(dev, crtc, encoder)
4142 if (encoder->pre_enable)
4143 encoder->pre_enable(encoder);
4144
2dd24552
JB		 4145 i9xx_pfit_enable(intel_crtc);
4146
63cbb074
VS		 4147 intel_crtc_load_lut(crtc);
4148
f37fcc2a 4149 intel_update_watermarks(crtc);
23538ef1 4150 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
d1de00ef 4151 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 4152 intel_enable_planes(crtc);
5c38d48c 4153 intel_crtc_update_cursor(crtc, true);
89b667f8 4154
89b667f8 4155 intel_update_fbc(dev);
5004945f
JN		 4156
4157 for_each_encoder_on_crtc(dev, crtc, encoder)
4158 encoder->enable(encoder);
89b667f8
JB		 4159}
4160
0b8765c6 4161static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 4162{
4163 struct drm_device *dev = crtc->dev;
79e53945
JB		 4164 struct drm_i915_private *dev_priv = dev->dev_private;
4165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4166 struct intel_encoder *encoder;
79e53945 4167 int pipe = intel_crtc->pipe;
80824003 4168 int plane = intel_crtc->plane;
79e53945 4169
08a48469
DV		 4170 WARN_ON(!crtc->enabled);
4171
f7abfe8b
CW		 4172 if (intel_crtc->active)
4173 return;
4174
4175 intel_crtc->active = true;
6b383a7f 4176
9d6d9f19
MK		 4177 for_each_encoder_on_crtc(dev, crtc, encoder)
4178 if (encoder->pre_enable)
4179 encoder->pre_enable(encoder);
4180
f6736a1a
DV		 4181 i9xx_enable_pll(intel_crtc);
4182
2dd24552
JB		 4183 i9xx_pfit_enable(intel_crtc);
4184
63cbb074
VS		 4185 intel_crtc_load_lut(crtc);
4186
f37fcc2a 4187 intel_update_watermarks(crtc);
23538ef1 4188 intel_enable_pipe(dev_priv, pipe, false, false);
d1de00ef 4189 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 4190 intel_enable_planes(crtc);
22e407d7 4191 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 4192 if (IS_G4X(dev))
4193 g4x_fixup_plane(dev_priv, pipe);
22e407d7 4194 intel_crtc_update_cursor(crtc, true);
79e53945 4195
0b8765c6
JB		 4196 /* Give the overlay scaler a chance to enable if it's on this pipe */
4197 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 4198
f440eb13 4199 intel_update_fbc(dev);
ef9c3aee 4200
fa5c73b1
DV		 4201 for_each_encoder_on_crtc(dev, crtc, encoder)
4202 encoder->enable(encoder);
0b8765c6 4203}
79e53945 4204
87476d63
DV		 4205static void i9xx_pfit_disable(struct intel_crtc *crtc)
4206{
4207 struct drm_device *dev = crtc->base.dev;
4208 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 4209
328d8e82
DV		 4210 if (!crtc->config.gmch_pfit.control)
4211 return;
87476d63 4212
328d8e82 4213 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 4214
328d8e82
DV		 4215 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4216 I915_READ(PFIT_CONTROL));
4217 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 4218}
4219
0b8765c6
JB		 4220static void i9xx_crtc_disable(struct drm_crtc *crtc)
4221{
4222 struct drm_device *dev = crtc->dev;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4225 struct intel_encoder *encoder;
0b8765c6
JB		 4226 int pipe = intel_crtc->pipe;
4227 int plane = intel_crtc->plane;
ef9c3aee 4228
f7abfe8b
CW		 4229 if (!intel_crtc->active)
4230 return;
4231
ea9d758d
DV		 4232 for_each_encoder_on_crtc(dev, crtc, encoder)
4233 encoder->disable(encoder);
4234
0b8765c6 4235 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 4236 intel_crtc_wait_for_pending_flips(crtc);
4237 drm_vblank_off(dev, pipe);
0b8765c6 4238
5c3fe8b0 4239 if (dev_priv->fbc.plane == plane)
973d04f9 4240 intel_disable_fbc(dev);
79e53945 4241
0d5b8c61
VS		 4242 intel_crtc_dpms_overlay(intel_crtc, false);
4243 intel_crtc_update_cursor(crtc, false);
bb53d4ae 4244 intel_disable_planes(crtc);
d1de00ef 4245 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 4246
b24e7179 4247 intel_disable_pipe(dev_priv, pipe);
24a1f16d 4248
87476d63 4249 i9xx_pfit_disable(intel_crtc);
24a1f16d 4250
89b667f8
JB		 4251 for_each_encoder_on_crtc(dev, crtc, encoder)
4252 if (encoder->post_disable)
4253 encoder->post_disable(encoder);
4254
f6071166
JB		 4255 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4256 vlv_disable_pll(dev_priv, pipe);
4257 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 4258 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 4259
f7abfe8b 4260 intel_crtc->active = false;
46ba614c 4261 intel_update_watermarks(crtc);
f37fcc2a 4262
6b383a7f 4263 intel_update_fbc(dev);
0b8765c6
JB		 4264}
4265
ee7b9f93
JB		 4266static void i9xx_crtc_off(struct drm_crtc *crtc)
4267{
4268}
4269
976f8a20
DV		 4270static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4271 bool enabled)
2c07245f
ZW		 4272{
4273 struct drm_device *dev = crtc->dev;
4274 struct drm_i915_master_private *master_priv;
4275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4276 int pipe = intel_crtc->pipe;
79e53945
JB		 4277
4278 if (!dev->primary->master)
4279 return;
4280
4281 master_priv = dev->primary->master->driver_priv;
4282 if (!master_priv->sarea_priv)
4283 return;
4284
79e53945
JB		 4285 switch (pipe) {
4286 case 0:
4287 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4288 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4289 break;
4290 case 1:
4291 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4292 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4293 break;
4294 default:
9db4a9c7 4295 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4296 break;
4297 }
79e53945
JB		 4298}
4299
976f8a20
DV		 4300/**
4301 * Sets the power management mode of the pipe and plane.
4302 */
4303void intel_crtc_update_dpms(struct drm_crtc *crtc)
4304{
4305 struct drm_device *dev = crtc->dev;
4306 struct drm_i915_private *dev_priv = dev->dev_private;
4307 struct intel_encoder *intel_encoder;
4308 bool enable = false;
4309
4310 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4311 enable |= intel_encoder->connectors_active;
4312
4313 if (enable)
4314 dev_priv->display.crtc_enable(crtc);
4315 else
4316 dev_priv->display.crtc_disable(crtc);
4317
4318 intel_crtc_update_sarea(crtc, enable);
4319}
4320
cdd59983
CW		 4321static void intel_crtc_disable(struct drm_crtc *crtc)
4322{
cdd59983 4323 struct drm_device *dev = crtc->dev;
976f8a20 4324 struct drm_connector *connector;
ee7b9f93 4325 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4327
976f8a20
DV		 4328 /* crtc should still be enabled when we disable it. */
4329 WARN_ON(!crtc->enabled);
4330
4331 dev_priv->display.crtc_disable(crtc);
c77bf565 4332 intel_crtc->eld_vld = false;
976f8a20 4333 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4334 dev_priv->display.off(crtc);
4335
931872fc 4336 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4337 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4338 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4339
4340 if (crtc->fb) {
4341 mutex_lock(&dev->struct_mutex);
1690e1eb 4342 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4343 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4344 crtc->fb = NULL;
4345 }
4346
4347 /* Update computed state. */
4348 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4349 if (!connector->encoder || !connector->encoder->crtc)
4350 continue;
4351
4352 if (connector->encoder->crtc != crtc)
4353 continue;
4354
4355 connector->dpms = DRM_MODE_DPMS_OFF;
4356 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4357 }
4358}
4359
ea5b213a 4360void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4361{
4ef69c7a 4362 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4363
ea5b213a
CW		 4364 drm_encoder_cleanup(encoder);
4365 kfree(intel_encoder);
7e7d76c3
JB		 4366}
4367
9237329d 4368/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4369 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4370 * state of the entire output pipe. */
9237329d 4371static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4372{
5ab432ef
DV		 4373 if (mode == DRM_MODE_DPMS_ON) {
4374 encoder->connectors_active = true;
4375
b2cabb0e 4376 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4377 } else {
4378 encoder->connectors_active = false;
4379
b2cabb0e 4380 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4381 }
79e53945
JB		 4382}
4383
0a91ca29
DV		 4384/* Cross check the actual hw state with our own modeset state tracking (and it's
4385 * internal consistency). */
b980514c 4386static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4387{
0a91ca29
DV		 4388 if (connector->get_hw_state(connector)) {
4389 struct intel_encoder *encoder = connector->encoder;
4390 struct drm_crtc *crtc;
4391 bool encoder_enabled;
4392 enum pipe pipe;
4393
4394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4395 connector->base.base.id,
4396 drm_get_connector_name(&connector->base));
4397
4398 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4399 "wrong connector dpms state\n");
4400 WARN(connector->base.encoder != &encoder->base,
4401 "active connector not linked to encoder\n");
4402 WARN(!encoder->connectors_active,
4403 "encoder->connectors_active not set\n");
4404
4405 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4406 WARN(!encoder_enabled, "encoder not enabled\n");
4407 if (WARN_ON(!encoder->base.crtc))
4408 return;
4409
4410 crtc = encoder->base.crtc;
4411
4412 WARN(!crtc->enabled, "crtc not enabled\n");
4413 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4414 WARN(pipe != to_intel_crtc(crtc)->pipe,
4415 "encoder active on the wrong pipe\n");
4416 }
79e53945
JB		 4417}
4418
5ab432ef
DV		 4419/* Even simpler default implementation, if there's really no special case to
4420 * consider. */
4421void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4422{
5ab432ef
DV		 4423 /* All the simple cases only support two dpms states. */
4424 if (mode != DRM_MODE_DPMS_ON)
4425 mode = DRM_MODE_DPMS_OFF;
d4270e57 4426
5ab432ef
DV		 4427 if (mode == connector->dpms)
4428 return;
4429
4430 connector->dpms = mode;
4431
4432 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 4433 if (connector->encoder)
4434 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 4435
b980514c 4436 intel_modeset_check_state(connector->dev);
79e53945
JB		 4437}
4438
f0947c37
DV		 4439/* Simple connector->get_hw_state implementation for encoders that support only
4440 * one connector and no cloning and hence the encoder state determines the state
4441 * of the connector. */
4442bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4443{
24929352 4444 enum pipe pipe = 0;
f0947c37 4445 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4446
f0947c37 4447 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4448}
4449
1857e1da
DV		 4450static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4451 struct intel_crtc_config *pipe_config)
4452{
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454 struct intel_crtc *pipe_B_crtc =
4455 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4456
4457 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4458 pipe_name(pipe), pipe_config->fdi_lanes);
4459 if (pipe_config->fdi_lanes > 4) {
4460 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4461 pipe_name(pipe), pipe_config->fdi_lanes);
4462 return false;
4463 }
4464
bafb6553 4465 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 4466 if (pipe_config->fdi_lanes > 2) {
4467 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4468 pipe_config->fdi_lanes);
4469 return false;
4470 } else {
4471 return true;
4472 }
4473 }
4474
4475 if (INTEL_INFO(dev)->num_pipes == 2)
4476 return true;
4477
4478 /* Ivybridge 3 pipe is really complicated */
4479 switch (pipe) {
4480 case PIPE_A:
4481 return true;
4482 case PIPE_B:
4483 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4484 pipe_config->fdi_lanes > 2) {
4485 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4486 pipe_name(pipe), pipe_config->fdi_lanes);
4487 return false;
4488 }
4489 return true;
4490 case PIPE_C:
1e833f40 4491 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4492 pipe_B_crtc->config.fdi_lanes <= 2) {
4493 if (pipe_config->fdi_lanes > 2) {
4494 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4495 pipe_name(pipe), pipe_config->fdi_lanes);
4496 return false;
4497 }
4498 } else {
4499 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4500 return false;
4501 }
4502 return true;
4503 default:
4504 BUG();
4505 }
4506}
4507
e29c22c0
DV		 4508#define RETRY 1
4509static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4510 struct intel_crtc_config *pipe_config)
877d48d5 4511{
1857e1da 4512 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4513 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4514 int lane, link_bw, fdi_dotclock;
e29c22c0 4515 bool setup_ok, needs_recompute = false;
877d48d5 4516
e29c22c0 4517retry:
877d48d5
DV		 4518 /* FDI is a binary signal running at ~2.7GHz, encoding
4519 * each output octet as 10 bits. The actual frequency
4520 * is stored as a divider into a 100MHz clock, and the
4521 * mode pixel clock is stored in units of 1KHz.
4522 * Hence the bw of each lane in terms of the mode signal
4523 * is:
4524 */
4525 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4526
241bfc38 4527 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4528
2bd89a07 4529 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4530 pipe_config->pipe_bpp);
4531
4532 pipe_config->fdi_lanes = lane;
4533
2bd89a07 4534 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4535 link_bw, &pipe_config->fdi_m_n);
1857e1da 4536
e29c22c0
DV		 4537 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4538 intel_crtc->pipe, pipe_config);
4539 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4540 pipe_config->pipe_bpp -= 2*3;
4541 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4542 pipe_config->pipe_bpp);
4543 needs_recompute = true;
4544 pipe_config->bw_constrained = true;
4545
4546 goto retry;
4547 }
4548
4549 if (needs_recompute)
4550 return RETRY;
4551
4552 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4553}
4554
42db64ef
PZ		 4555static void hsw_compute_ips_config(struct intel_crtc *crtc,
4556 struct intel_crtc_config *pipe_config)
4557{
3c4ca58c
PZ		 4558 pipe_config->ips_enabled = i915_enable_ips &&
4559 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4560 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4561}
4562
a43f6e0f 4563static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4564 struct intel_crtc_config *pipe_config)
79e53945 4565{
a43f6e0f 4566 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4567 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4568
ad3a4479 4569 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4570 if (INTEL_INFO(dev)->gen < 4) {
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 int clock_limit =
4573 dev_priv->display.get_display_clock_speed(dev);
4574
4575 /*
4576 * Enable pixel doubling when the dot clock
4577 * is > 90% of the (display) core speed.
4578 *
b397c96b
VS		 4579 * GDG double wide on either pipe,
4580 * otherwise pipe A only.
cf532bb2 4581 */
b397c96b 4582 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4583 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4584 clock_limit *= 2;
cf532bb2 4585 pipe_config->double_wide = true;
ad3a4479
VS		 4586 }
4587
241bfc38 4588 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4589 return -EINVAL;
2c07245f 4590 }
89749350 4591
1d1d0e27
VS		 4592 /*
4593 * Pipe horizontal size must be even in:
4594 * - DVO ganged mode
4595 * - LVDS dual channel mode
4596 * - Double wide pipe
4597 */
4598 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4599 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4600 pipe_config->pipe_src_w &= ~1;
4601
8693a824
DL		 4602 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4603 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4604 */
4605 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4606 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4607 return -EINVAL;
44f46b42 4608
bd080ee5 4609 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4610 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4611 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4612 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4613 * for lvds. */
4614 pipe_config->pipe_bpp = 8*3;
4615 }
4616
f5adf94e 4617 if (HAS_IPS(dev))
a43f6e0f
DV		 4618 hsw_compute_ips_config(crtc, pipe_config);
4619
4620 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4621 * clock survives for now. */
4622 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4623 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4624
877d48d5 4625 if (pipe_config->has_pch_encoder)
a43f6e0f 4626 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4627
e29c22c0 4628 return 0;
79e53945
JB		 4629}
4630
25eb05fc
JB		 4631static int valleyview_get_display_clock_speed(struct drm_device *dev)
4632{
4633 return 400000; /* FIXME */
4634}
4635
e70236a8
JB		 4636static int i945_get_display_clock_speed(struct drm_device *dev)
4637{
4638 return 400000;
4639}
79e53945 4640
e70236a8 4641static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4642{
e70236a8
JB		 4643 return 333000;
4644}
79e53945 4645
e70236a8
JB		 4646static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4647{
4648 return 200000;
4649}
79e53945 4650
257a7ffc
DV		 4651static int pnv_get_display_clock_speed(struct drm_device *dev)
4652{
4653 u16 gcfgc = 0;
4654
4655 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4656
4657 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4658 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4659 return 267000;
4660 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4661 return 333000;
4662 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4663 return 444000;
4664 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4665 return 200000;
4666 default:
4667 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4668 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4669 return 133000;
4670 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4671 return 167000;
4672 }
4673}
4674
e70236a8
JB		 4675static int i915gm_get_display_clock_speed(struct drm_device *dev)
4676{
4677 u16 gcfgc = 0;
79e53945 4678
e70236a8
JB		 4679 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4680
4681 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4682 return 133000;
4683 else {
4684 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4685 case GC_DISPLAY_CLOCK_333_MHZ:
4686 return 333000;
4687 default:
4688 case GC_DISPLAY_CLOCK_190_200_MHZ:
4689 return 190000;
79e53945 4690 }
e70236a8
JB		 4691 }
4692}
4693
4694static int i865_get_display_clock_speed(struct drm_device *dev)
4695{
4696 return 266000;
4697}
4698
4699static int i855_get_display_clock_speed(struct drm_device *dev)
4700{
4701 u16 hpllcc = 0;
4702 /* Assume that the hardware is in the high speed state. This
4703 * should be the default.
4704 */
4705 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4706 case GC_CLOCK_133_200:
4707 case GC_CLOCK_100_200:
4708 return 200000;
4709 case GC_CLOCK_166_250:
4710 return 250000;
4711 case GC_CLOCK_100_133:
79e53945 4712 return 133000;
e70236a8 4713 }
79e53945 4714
e70236a8
JB		 4715 /* Shouldn't happen */
4716 return 0;
4717}
79e53945 4718
e70236a8
JB		 4719static int i830_get_display_clock_speed(struct drm_device *dev)
4720{
4721 return 133000;
79e53945
JB		 4722}
4723
2c07245f 4724static void
a65851af 4725intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4726{
a65851af
VS		 4727 while (*num > DATA_LINK_M_N_MASK ||
4728 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4729 *num >>= 1;
4730 *den >>= 1;
4731 }
4732}
4733
a65851af
VS		 4734static void compute_m_n(unsigned int m, unsigned int n,
4735 uint32_t *ret_m, uint32_t *ret_n)
4736{
4737 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4738 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4739 intel_reduce_m_n_ratio(ret_m, ret_n);
4740}
4741
e69d0bc1
DV		 4742void
4743intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4744 int pixel_clock, int link_clock,
4745 struct intel_link_m_n *m_n)
2c07245f 4746{
e69d0bc1 4747 m_n->tu = 64;
a65851af
VS		 4748
4749 compute_m_n(bits_per_pixel * pixel_clock,
4750 link_clock * nlanes * 8,
4751 &m_n->gmch_m, &m_n->gmch_n);
4752
4753 compute_m_n(pixel_clock, link_clock,
4754 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4755}
4756
a7615030
CW		 4757static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4758{
72bbe58c
KP		 4759 if (i915_panel_use_ssc >= 0)
4760 return i915_panel_use_ssc != 0;
41aa3448 4761 return dev_priv->vbt.lvds_use_ssc
435793df 4762 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4763}
4764
c65d77d8
JB		 4765static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4766{
4767 struct drm_device *dev = crtc->dev;
4768 struct drm_i915_private *dev_priv = dev->dev_private;
4769 int refclk;
4770
a0c4da24 4771 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4772 refclk = 100000;
a0c4da24 4773 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4774 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 4775 refclk = dev_priv->vbt.lvds_ssc_freq;
4776 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 4777 } else if (!IS_GEN2(dev)) {
4778 refclk = 96000;
4779 } else {
4780 refclk = 48000;
4781 }
4782
4783 return refclk;
4784}
4785
7429e9d4 4786static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4787{
7df00d7a 4788 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4789}
f47709a9 4790
7429e9d4
DV		 4791static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4792{
4793 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4794}
4795
f47709a9 4796static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4797 intel_clock_t *reduced_clock)
4798{
f47709a9 4799 struct drm_device *dev = crtc->base.dev;
a7516a05 4800 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4801 int pipe = crtc->pipe;
a7516a05
JB		 4802 u32 fp, fp2 = 0;
4803
4804 if (IS_PINEVIEW(dev)) {
7429e9d4 4805 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4806 if (reduced_clock)
7429e9d4 4807 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4808 } else {
7429e9d4 4809 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4810 if (reduced_clock)
7429e9d4 4811 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4812 }
4813
4814 I915_WRITE(FP0(pipe), fp);
8bcc2795 4815 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4816
f47709a9
DV		 4817 crtc->lowfreq_avail = false;
4818 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4819 reduced_clock && i915_powersave) {
4820 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4821 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4822 crtc->lowfreq_avail = true;
a7516a05
JB		 4823 } else {
4824 I915_WRITE(FP1(pipe), fp);
8bcc2795 4825 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4826 }
4827}
4828
5e69f97f
CML		 4829static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4830 pipe)
89b667f8
JB		 4831{
4832 u32 reg_val;
4833
4834 /*
4835 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4836 * and set it to a reasonable value instead.
4837 */
ab3c759a 4838 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 4839 reg_val &= 0xffffff00;
4840 reg_val |= 0x00000030;
ab3c759a 4841 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 4842
ab3c759a 4843 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 4844 reg_val &= 0x8cffffff;
4845 reg_val = 0x8c000000;
ab3c759a 4846 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 4847
ab3c759a 4848 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 4849 reg_val &= 0xffffff00;
ab3c759a 4850 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 4851
ab3c759a 4852 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 4853 reg_val &= 0x00ffffff;
4854 reg_val |= 0xb0000000;
ab3c759a 4855 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 4856}
4857
b551842d
DV		 4858static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4859 struct intel_link_m_n *m_n)
4860{
4861 struct drm_device *dev = crtc->base.dev;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 int pipe = crtc->pipe;
4864
e3b95f1e
DV		 4865 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4866 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4867 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4868 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4869}
4870
4871static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4872 struct intel_link_m_n *m_n)
4873{
4874 struct drm_device *dev = crtc->base.dev;
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 int pipe = crtc->pipe;
4877 enum transcoder transcoder = crtc->config.cpu_transcoder;
4878
4879 if (INTEL_INFO(dev)->gen >= 5) {
4880 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4881 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4882 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4883 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4884 } else {
e3b95f1e
DV		 4885 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4886 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4887 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4888 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4889 }
4890}
4891
03afc4a2
DV		 4892static void intel_dp_set_m_n(struct intel_crtc *crtc)
4893{
4894 if (crtc->config.has_pch_encoder)
4895 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4896 else
4897 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4898}
4899
f47709a9 4900static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4901{
f47709a9 4902 struct drm_device *dev = crtc->base.dev;
a0c4da24 4903 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4904 int pipe = crtc->pipe;
89b667f8 4905 u32 dpll, mdiv;
a0c4da24 4906 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4907 u32 coreclk, reg_val, dpll_md;
a0c4da24 4908
09153000
DV		 4909 mutex_lock(&dev_priv->dpio_lock);
4910
f47709a9
DV		 4911 bestn = crtc->config.dpll.n;
4912 bestm1 = crtc->config.dpll.m1;
4913 bestm2 = crtc->config.dpll.m2;
4914 bestp1 = crtc->config.dpll.p1;
4915 bestp2 = crtc->config.dpll.p2;
a0c4da24 4916
89b667f8
JB		 4917 /* See eDP HDMI DPIO driver vbios notes doc */
4918
4919 /* PLL B needs special handling */
4920 if (pipe)
5e69f97f 4921 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4922
4923 /* Set up Tx target for periodic Rcomp update */
ab3c759a 4924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 4925
4926 /* Disable target IRef on PLL */
ab3c759a 4927 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 4928 reg_val &= 0x00ffffff;
ab3c759a 4929 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 4930
4931 /* Disable fast lock */
ab3c759a 4932 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 4933
4934 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4935 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4936 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4937 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4938 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4939
4940 /*
4941 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4942 * but we don't support that).
4943 * Note: don't use the DAC post divider as it seems unstable.
4944 */
4945 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 4946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 4947
a0c4da24 4948 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 4949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 4950
89b667f8 4951 /* Set HBR and RBR LPF coefficients */
ff9a6750 4952 if (crtc->config.port_clock == 162000 ||
99750bd4 4953 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4954 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ab3c759a 4955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 4956 0x009f0003);
89b667f8 4957 else
ab3c759a 4958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 4959 0x00d0000f);
4960
4961 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4962 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4963 /* Use SSC source */
4964 if (!pipe)
ab3c759a 4965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 4966 0x0df40000);
4967 else
ab3c759a 4968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 4969 0x0df70000);
4970 } else { /* HDMI or VGA */
4971 /* Use bend source */
4972 if (!pipe)
ab3c759a 4973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 4974 0x0df70000);
4975 else
ab3c759a 4976 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 4977 0x0df40000);
4978 }
a0c4da24 4979
ab3c759a 4980 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8
JB		 4981 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4982 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4983 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4984 coreclk |= 0x01000000;
ab3c759a 4985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 4986
ab3c759a 4987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a0c4da24 4988
89b667f8
JB		 4989 /* Enable DPIO clock input */
4990 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4991 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4992 /* We should never disable this, set it here for state tracking */
4993 if (pipe == PIPE_B)
89b667f8 4994 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4995 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4996 crtc->config.dpll_hw_state.dpll = dpll;
4997
ef1b460d
DV		 4998 dpll_md = (crtc->config.pixel_multiplier - 1)
4999 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 5000 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5001
89b667f8
JB		 5002 if (crtc->config.has_dp_encoder)
5003 intel_dp_set_m_n(crtc);
09153000
DV		 5004
5005 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 5006}
5007
f47709a9
DV		 5008static void i9xx_update_pll(struct intel_crtc *crtc,
5009 intel_clock_t *reduced_clock,
eb1cbe48
DV		 5010 int num_connectors)
5011{
f47709a9 5012 struct drm_device *dev = crtc->base.dev;
eb1cbe48 5013 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 5014 u32 dpll;
5015 bool is_sdvo;
f47709a9 5016 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 5017
f47709a9 5018 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 5019
f47709a9
DV		 5020 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5021 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 5022
5023 dpll = DPLL_VGA_MODE_DIS;
5024
f47709a9 5025 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 5026 dpll |= DPLLB_MODE_LVDS;
5027 else
5028 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 5029
ef1b460d 5030 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 5031 dpll |= (crtc->config.pixel_multiplier - 1)
5032 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 5033 }
198a037f
DV		 5034
5035 if (is_sdvo)
4a33e48d 5036 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 5037
f47709a9 5038 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 5039 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 5040
5041 /* compute bitmask from p1 value */
5042 if (IS_PINEVIEW(dev))
5043 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5044 else {
5045 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5046 if (IS_G4X(dev) && reduced_clock)
5047 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5048 }
5049 switch (clock->p2) {
5050 case 5:
5051 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5052 break;
5053 case 7:
5054 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5055 break;
5056 case 10:
5057 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5058 break;
5059 case 14:
5060 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5061 break;
5062 }
5063 if (INTEL_INFO(dev)->gen >= 4)
5064 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5065
09ede541 5066 if (crtc->config.sdvo_tv_clock)
eb1cbe48 5067 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 5068 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 5069 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5070 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5071 else
5072 dpll |= PLL_REF_INPUT_DREFCLK;
5073
5074 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 5075 crtc->config.dpll_hw_state.dpll = dpll;
5076
eb1cbe48 5077 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 5078 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5079 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 5080 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 5081 }
66e3d5c0
DV		 5082
5083 if (crtc->config.has_dp_encoder)
5084 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 5085}
5086
f47709a9 5087static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 5088 intel_clock_t *reduced_clock,
eb1cbe48
DV		 5089 int num_connectors)
5090{
f47709a9 5091 struct drm_device *dev = crtc->base.dev;
eb1cbe48 5092 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 5093 u32 dpll;
f47709a9 5094 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 5095
f47709a9 5096 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 5097
eb1cbe48
DV		 5098 dpll = DPLL_VGA_MODE_DIS;
5099
f47709a9 5100 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 5101 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5102 } else {
5103 if (clock->p1 == 2)
5104 dpll |= PLL_P1_DIVIDE_BY_TWO;
5105 else
5106 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5107 if (clock->p2 == 4)
5108 dpll |= PLL_P2_DIVIDE_BY_4;
5109 }
5110
4a33e48d
DV		 5111 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5112 dpll |= DPLL_DVO_2X_MODE;
5113
f47709a9 5114 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 5115 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5116 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5117 else
5118 dpll |= PLL_REF_INPUT_DREFCLK;
5119
5120 dpll |= DPLL_VCO_ENABLE;
8bcc2795 5121 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 5122}
5123
8a654f3b 5124static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 5125{
5126 struct drm_device *dev = intel_crtc->base.dev;
5127 struct drm_i915_private *dev_priv = dev->dev_private;
5128 enum pipe pipe = intel_crtc->pipe;
3b117c8f 5129 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 5130 struct drm_display_mode *adjusted_mode =
5131 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 5132 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5133
5134 /* We need to be careful not to changed the adjusted mode, for otherwise
5135 * the hw state checker will get angry at the mismatch. */
5136 crtc_vtotal = adjusted_mode->crtc_vtotal;
5137 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 5138
5139 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5140 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 5141 crtc_vtotal -= 1;
5142 crtc_vblank_end -= 1;
b0e77b9c
PZ		 5143 vsyncshift = adjusted_mode->crtc_hsync_start
5144 - adjusted_mode->crtc_htotal / 2;
5145 } else {
5146 vsyncshift = 0;
5147 }
5148
5149 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 5150 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 5151
fe2b8f9d 5152 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 5153 (adjusted_mode->crtc_hdisplay - 1) |
5154 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 5155 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 5156 (adjusted_mode->crtc_hblank_start - 1) |
5157 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 5158 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 5159 (adjusted_mode->crtc_hsync_start - 1) |
5160 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5161
fe2b8f9d 5162 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 5163 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 5164 ((crtc_vtotal - 1) << 16));
fe2b8f9d 5165 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 5166 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 5167 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 5168 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 5169 (adjusted_mode->crtc_vsync_start - 1) |
5170 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5171
b5e508d4
PZ		 5172 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5173 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5174 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5175 * bits. */
5176 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5177 (pipe == PIPE_B || pipe == PIPE_C))
5178 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5179
b0e77b9c
PZ		 5180 /* pipesrc controls the size that is scaled from, which should
5181 * always be the user's requested size.
5182 */
5183 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 5184 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5185 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 5186}
5187
1bd1bd80
DV		 5188static void intel_get_pipe_timings(struct intel_crtc *crtc,
5189 struct intel_crtc_config *pipe_config)
5190{
5191 struct drm_device *dev = crtc->base.dev;
5192 struct drm_i915_private *dev_priv = dev->dev_private;
5193 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5194 uint32_t tmp;
5195
5196 tmp = I915_READ(HTOTAL(cpu_transcoder));
5197 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5198 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5199 tmp = I915_READ(HBLANK(cpu_transcoder));
5200 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5201 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5202 tmp = I915_READ(HSYNC(cpu_transcoder));
5203 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5204 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5205
5206 tmp = I915_READ(VTOTAL(cpu_transcoder));
5207 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5208 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5209 tmp = I915_READ(VBLANK(cpu_transcoder));
5210 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5211 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5212 tmp = I915_READ(VSYNC(cpu_transcoder));
5213 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5214 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5215
5216 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5217 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5218 pipe_config->adjusted_mode.crtc_vtotal += 1;
5219 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5220 }
5221
5222 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 5223 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5224 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5225
5226 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5227 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 5228}
5229
babea61d
JB		 5230static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5231 struct intel_crtc_config *pipe_config)
5232{
5233 struct drm_crtc *crtc = &intel_crtc->base;
5234
5235 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5236 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5237 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5238 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5239
5240 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5241 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5242 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5243 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5244
5245 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5246
241bfc38 5247 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 5248 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5249}
5250
84b046f3
DV		 5251static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5252{
5253 struct drm_device *dev = intel_crtc->base.dev;
5254 struct drm_i915_private *dev_priv = dev->dev_private;
5255 uint32_t pipeconf;
5256
9f11a9e4 5257 pipeconf = 0;
84b046f3 5258
67c72a12
DV		 5259 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5260 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5261 pipeconf |= PIPECONF_ENABLE;
5262
cf532bb2
VS		 5263 if (intel_crtc->config.double_wide)
5264 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 5265
ff9ce46e
DV		 5266 /* only g4x and later have fancy bpc/dither controls */
5267 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 5268 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5269 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5270 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 5271 PIPECONF_DITHER_TYPE_SP;
84b046f3 5272
ff9ce46e
DV		 5273 switch (intel_crtc->config.pipe_bpp) {
5274 case 18:
5275 pipeconf |= PIPECONF_6BPC;
5276 break;
5277 case 24:
5278 pipeconf |= PIPECONF_8BPC;
5279 break;
5280 case 30:
5281 pipeconf |= PIPECONF_10BPC;
5282 break;
5283 default:
5284 /* Case prevented by intel_choose_pipe_bpp_dither. */
5285 BUG();
84b046f3
DV		 5286 }
5287 }
5288
5289 if (HAS_PIPE_CXSR(dev)) {
5290 if (intel_crtc->lowfreq_avail) {
5291 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5292 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5293 } else {
5294 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5295 }
5296 }
5297
84b046f3
DV		 5298 if (!IS_GEN2(dev) &&
5299 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5300 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5301 else
5302 pipeconf |= PIPECONF_PROGRESSIVE;
5303
9f11a9e4
DV		 5304 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5305 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5306
84b046f3
DV		 5307 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5308 POSTING_READ(PIPECONF(intel_crtc->pipe));
5309}
5310
f564048e 5311static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5312 int x, int y,
94352cf9 5313 struct drm_framebuffer *fb)
79e53945
JB		 5314{
5315 struct drm_device *dev = crtc->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318 int pipe = intel_crtc->pipe;
80824003 5319 int plane = intel_crtc->plane;
c751ce4f 5320 int refclk, num_connectors = 0;
652c393a 5321 intel_clock_t clock, reduced_clock;
84b046f3 5322 u32 dspcntr;
a16af721 5323 bool ok, has_reduced_clock = false;
e9fd1c02 5324 bool is_lvds = false, is_dsi = false;
5eddb70b 5325 struct intel_encoder *encoder;
d4906093 5326 const intel_limit_t *limit;
5c3b82e2 5327 int ret;
79e53945 5328
6c2b7c12 5329 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5330 switch (encoder->type) {
79e53945
JB		 5331 case INTEL_OUTPUT_LVDS:
5332 is_lvds = true;
5333 break;
e9fd1c02
JN		 5334 case INTEL_OUTPUT_DSI:
5335 is_dsi = true;
5336 break;
79e53945 5337 }
43565a06 5338
c751ce4f 5339 num_connectors++;
79e53945
JB		 5340 }
5341
f2335330
JN		 5342 if (is_dsi)
5343 goto skip_dpll;
5344
5345 if (!intel_crtc->config.clock_set) {
5346 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5347
e9fd1c02
JN		 5348 /*
5349 * Returns a set of divisors for the desired target clock with
5350 * the given refclk, or FALSE. The returned values represent
5351 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5352 * 2) / p1 / p2.
5353 */
5354 limit = intel_limit(crtc, refclk);
5355 ok = dev_priv->display.find_dpll(limit, crtc,
5356 intel_crtc->config.port_clock,
5357 refclk, NULL, &clock);
f2335330 5358 if (!ok) {
e9fd1c02
JN		 5359 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5360 return -EINVAL;
5361 }
79e53945 5362
f2335330
JN		 5363 if (is_lvds && dev_priv->lvds_downclock_avail) {
5364 /*
5365 * Ensure we match the reduced clock's P to the target
5366 * clock. If the clocks don't match, we can't switch
5367 * the display clock by using the FP0/FP1. In such case
5368 * we will disable the LVDS downclock feature.
5369 */
5370 has_reduced_clock =
5371 dev_priv->display.find_dpll(limit, crtc,
5372 dev_priv->lvds_downclock,
5373 refclk, &clock,
5374 &reduced_clock);
5375 }
5376 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5377 intel_crtc->config.dpll.n = clock.n;
5378 intel_crtc->config.dpll.m1 = clock.m1;
5379 intel_crtc->config.dpll.m2 = clock.m2;
5380 intel_crtc->config.dpll.p1 = clock.p1;
5381 intel_crtc->config.dpll.p2 = clock.p2;
5382 }
7026d4ac 5383
e9fd1c02 5384 if (IS_GEN2(dev)) {
8a654f3b 5385 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5386 has_reduced_clock ? &reduced_clock : NULL,
5387 num_connectors);
e9fd1c02 5388 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5389 vlv_update_pll(intel_crtc);
e9fd1c02 5390 } else {
f47709a9 5391 i9xx_update_pll(intel_crtc,
eb1cbe48 5392 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5393 num_connectors);
e9fd1c02 5394 }
79e53945 5395
f2335330 5396skip_dpll:
79e53945
JB		 5397 /* Set up the display plane register */
5398 dspcntr = DISPPLANE_GAMMA_ENABLE;
5399
da6ecc5d
JB		 5400 if (!IS_VALLEYVIEW(dev)) {
5401 if (pipe == 0)
5402 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5403 else
5404 dspcntr |= DISPPLANE_SEL_PIPE_B;
5405 }
79e53945 5406
8a654f3b 5407 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5408
5409 /* pipesrc and dspsize control the size that is scaled from,
5410 * which should always be the user's requested size.
79e53945 5411 */
929c77fb 5412 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5413 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5414 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5415 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5416
84b046f3
DV		 5417 i9xx_set_pipeconf(intel_crtc);
5418
f564048e
EA		 5419 I915_WRITE(DSPCNTR(plane), dspcntr);
5420 POSTING_READ(DSPCNTR(plane));
5421
94352cf9 5422 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5423
f564048e
EA		 5424 return ret;
5425}
5426
2fa2fe9a
DV		 5427static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5428 struct intel_crtc_config *pipe_config)
5429{
5430 struct drm_device *dev = crtc->base.dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
5432 uint32_t tmp;
5433
5434 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5435 if (!(tmp & PFIT_ENABLE))
5436 return;
2fa2fe9a 5437
06922821 5438 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5439 if (INTEL_INFO(dev)->gen < 4) {
5440 if (crtc->pipe != PIPE_B)
5441 return;
2fa2fe9a
DV		 5442 } else {
5443 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5444 return;
5445 }
5446
06922821 5447 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5448 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5449 if (INTEL_INFO(dev)->gen < 5)
5450 pipe_config->gmch_pfit.lvds_border_bits =
5451 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5452}
5453
acbec814
JB		 5454static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5455 struct intel_crtc_config *pipe_config)
5456{
5457 struct drm_device *dev = crtc->base.dev;
5458 struct drm_i915_private *dev_priv = dev->dev_private;
5459 int pipe = pipe_config->cpu_transcoder;
5460 intel_clock_t clock;
5461 u32 mdiv;
662c6ecb 5462 int refclk = 100000;
acbec814
JB		 5463
5464 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 5465 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 5466 mutex_unlock(&dev_priv->dpio_lock);
5467
5468 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5469 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5470 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5471 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5472 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5473
f646628b 5474 vlv_clock(refclk, &clock);
acbec814 5475
f646628b
VS		 5476 /* clock.dot is the fast clock */
5477 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 5478}
5479
0e8ffe1b
DV		 5480static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5481 struct intel_crtc_config *pipe_config)
5482{
5483 struct drm_device *dev = crtc->base.dev;
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485 uint32_t tmp;
5486
e143a21c 5487 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5488 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5489
0e8ffe1b
DV		 5490 tmp = I915_READ(PIPECONF(crtc->pipe));
5491 if (!(tmp & PIPECONF_ENABLE))
5492 return false;
5493
42571aef
VS		 5494 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5495 switch (tmp & PIPECONF_BPC_MASK) {
5496 case PIPECONF_6BPC:
5497 pipe_config->pipe_bpp = 18;
5498 break;
5499 case PIPECONF_8BPC:
5500 pipe_config->pipe_bpp = 24;
5501 break;
5502 case PIPECONF_10BPC:
5503 pipe_config->pipe_bpp = 30;
5504 break;
5505 default:
5506 break;
5507 }
5508 }
5509
282740f7
VS		 5510 if (INTEL_INFO(dev)->gen < 4)
5511 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5512
1bd1bd80
DV		 5513 intel_get_pipe_timings(crtc, pipe_config);
5514
2fa2fe9a
DV		 5515 i9xx_get_pfit_config(crtc, pipe_config);
5516
6c49f241
DV		 5517 if (INTEL_INFO(dev)->gen >= 4) {
5518 tmp = I915_READ(DPLL_MD(crtc->pipe));
5519 pipe_config->pixel_multiplier =
5520 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5521 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5522 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5523 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5524 tmp = I915_READ(DPLL(crtc->pipe));
5525 pipe_config->pixel_multiplier =
5526 ((tmp & SDVO_MULTIPLIER_MASK)
5527 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5528 } else {
5529 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5530 * port and will be fixed up in the encoder->get_config
5531 * function. */
5532 pipe_config->pixel_multiplier = 1;
5533 }
8bcc2795
DV		 5534 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5535 if (!IS_VALLEYVIEW(dev)) {
5536 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5537 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5538 } else {
5539 /* Mask out read-only status bits. */
5540 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5541 DPLL_PORTC_READY_MASK |
5542 DPLL_PORTB_READY_MASK);
8bcc2795 5543 }
6c49f241 5544
acbec814
JB		 5545 if (IS_VALLEYVIEW(dev))
5546 vlv_crtc_clock_get(crtc, pipe_config);
5547 else
5548 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5549
0e8ffe1b
DV		 5550 return true;
5551}
5552
dde86e2d 5553static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5554{
5555 struct drm_i915_private *dev_priv = dev->dev_private;
5556 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5557 struct intel_encoder *encoder;
74cfd7ac 5558 u32 val, final;
13d83a67 5559 bool has_lvds = false;
199e5d79 5560 bool has_cpu_edp = false;
199e5d79 5561 bool has_panel = false;
99eb6a01
KP		 5562 bool has_ck505 = false;
5563 bool can_ssc = false;
13d83a67
JB		 5564
5565 /* We need to take the global config into account */
199e5d79
KP		 5566 list_for_each_entry(encoder, &mode_config->encoder_list,
5567 base.head) {
5568 switch (encoder->type) {
5569 case INTEL_OUTPUT_LVDS:
5570 has_panel = true;
5571 has_lvds = true;
5572 break;
5573 case INTEL_OUTPUT_EDP:
5574 has_panel = true;
2de6905f 5575 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5576 has_cpu_edp = true;
5577 break;
13d83a67
JB		 5578 }
5579 }
5580
99eb6a01 5581 if (HAS_PCH_IBX(dev)) {
41aa3448 5582 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5583 can_ssc = has_ck505;
5584 } else {
5585 has_ck505 = false;
5586 can_ssc = true;
5587 }
5588
2de6905f
ID		 5589 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5590 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5591
5592 /* Ironlake: try to setup display ref clock before DPLL
5593 * enabling. This is only under driver's control after
5594 * PCH B stepping, previous chipset stepping should be
5595 * ignoring this setting.
5596 */
74cfd7ac
CW		 5597 val = I915_READ(PCH_DREF_CONTROL);
5598
5599 /* As we must carefully and slowly disable/enable each source in turn,
5600 * compute the final state we want first and check if we need to
5601 * make any changes at all.
5602 */
5603 final = val;
5604 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5605 if (has_ck505)
5606 final |= DREF_NONSPREAD_CK505_ENABLE;
5607 else
5608 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5609
5610 final &= ~DREF_SSC_SOURCE_MASK;
5611 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5612 final &= ~DREF_SSC1_ENABLE;
5613
5614 if (has_panel) {
5615 final |= DREF_SSC_SOURCE_ENABLE;
5616
5617 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5618 final |= DREF_SSC1_ENABLE;
5619
5620 if (has_cpu_edp) {
5621 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5622 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5623 else
5624 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5625 } else
5626 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5627 } else {
5628 final |= DREF_SSC_SOURCE_DISABLE;
5629 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5630 }
5631
5632 if (final == val)
5633 return;
5634
13d83a67 5635 /* Always enable nonspread source */
74cfd7ac 5636 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5637
99eb6a01 5638 if (has_ck505)
74cfd7ac 5639 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5640 else
74cfd7ac 5641 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5642
199e5d79 5643 if (has_panel) {
74cfd7ac
CW		 5644 val &= ~DREF_SSC_SOURCE_MASK;
5645 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5646
199e5d79 5647 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5648 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5649 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5650 val |= DREF_SSC1_ENABLE;
e77166b5 5651 } else
74cfd7ac 5652 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5653
5654 /* Get SSC going before enabling the outputs */
74cfd7ac 5655 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5656 POSTING_READ(PCH_DREF_CONTROL);
5657 udelay(200);
5658
74cfd7ac 5659 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5660
5661 /* Enable CPU source on CPU attached eDP */
199e5d79 5662 if (has_cpu_edp) {
99eb6a01 5663 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5664 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5665 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5666 }
13d83a67 5667 else
74cfd7ac 5668 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5669 } else
74cfd7ac 5670 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5671
74cfd7ac 5672 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5673 POSTING_READ(PCH_DREF_CONTROL);
5674 udelay(200);
5675 } else {
5676 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5677
74cfd7ac 5678 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5679
5680 /* Turn off CPU output */
74cfd7ac 5681 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5682
74cfd7ac 5683 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5684 POSTING_READ(PCH_DREF_CONTROL);
5685 udelay(200);
5686
5687 /* Turn off the SSC source */
74cfd7ac
CW		 5688 val &= ~DREF_SSC_SOURCE_MASK;
5689 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5690
5691 /* Turn off SSC1 */
74cfd7ac 5692 val &= ~DREF_SSC1_ENABLE;
199e5d79 5693
74cfd7ac 5694 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5695 POSTING_READ(PCH_DREF_CONTROL);
5696 udelay(200);
5697 }
74cfd7ac
CW		 5698
5699 BUG_ON(val != final);
13d83a67
JB		 5700}
5701
f31f2d55 5702static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5703{
f31f2d55 5704 uint32_t tmp;
dde86e2d 5705
0ff066a9
PZ		 5706 tmp = I915_READ(SOUTH_CHICKEN2);
5707 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5708 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5709
0ff066a9
PZ		 5710 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5711 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5712 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5713
0ff066a9
PZ		 5714 tmp = I915_READ(SOUTH_CHICKEN2);
5715 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5716 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5717
0ff066a9
PZ		 5718 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5719 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5720 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5721}
5722
5723/* WaMPhyProgramming:hsw */
5724static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5725{
5726 uint32_t tmp;
dde86e2d
PZ		 5727
5728 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5729 tmp &= ~(0xFF << 24);
5730 tmp |= (0x12 << 24);
5731 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5732
dde86e2d
PZ		 5733 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5734 tmp |= (1 << 11);
5735 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5736
5737 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5738 tmp |= (1 << 11);
5739 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5740
dde86e2d
PZ		 5741 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5742 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5743 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5744
5745 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5746 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5747 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5748
0ff066a9
PZ		 5749 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5750 tmp &= ~(7 << 13);
5751 tmp |= (5 << 13);
5752 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5753
0ff066a9
PZ		 5754 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5755 tmp &= ~(7 << 13);
5756 tmp |= (5 << 13);
5757 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5758
5759 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5760 tmp &= ~0xFF;
5761 tmp |= 0x1C;
5762 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5763
5764 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5765 tmp &= ~0xFF;
5766 tmp |= 0x1C;
5767 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5768
5769 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5770 tmp &= ~(0xFF << 16);
5771 tmp |= (0x1C << 16);
5772 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5773
5774 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5775 tmp &= ~(0xFF << 16);
5776 tmp |= (0x1C << 16);
5777 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5778
0ff066a9
PZ		 5779 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5780 tmp |= (1 << 27);
5781 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5782
0ff066a9
PZ		 5783 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5784 tmp |= (1 << 27);
5785 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5786
0ff066a9
PZ		 5787 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5788 tmp &= ~(0xF << 28);
5789 tmp |= (4 << 28);
5790 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5791
0ff066a9
PZ		 5792 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5793 tmp &= ~(0xF << 28);
5794 tmp |= (4 << 28);
5795 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5796}
5797
2fa86a1f
PZ		 5798/* Implements 3 different sequences from BSpec chapter "Display iCLK
5799 * Programming" based on the parameters passed:
5800 * - Sequence to enable CLKOUT_DP
5801 * - Sequence to enable CLKOUT_DP without spread
5802 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5803 */
5804static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5805 bool with_fdi)
f31f2d55
PZ		 5806{
5807 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5808 uint32_t reg, tmp;
5809
5810 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5811 with_spread = true;
5812 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5813 with_fdi, "LP PCH doesn't have FDI\n"))
5814 with_fdi = false;
f31f2d55
PZ		 5815
5816 mutex_lock(&dev_priv->dpio_lock);
5817
5818 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5819 tmp &= ~SBI_SSCCTL_DISABLE;
5820 tmp |= SBI_SSCCTL_PATHALT;
5821 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5822
5823 udelay(24);
5824
2fa86a1f
PZ		 5825 if (with_spread) {
5826 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5827 tmp &= ~SBI_SSCCTL_PATHALT;
5828 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5829
2fa86a1f
PZ		 5830 if (with_fdi) {
5831 lpt_reset_fdi_mphy(dev_priv);
5832 lpt_program_fdi_mphy(dev_priv);
5833 }
5834 }
dde86e2d 5835
2fa86a1f
PZ		 5836 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5837 SBI_GEN0 : SBI_DBUFF0;
5838 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5839 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5840 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5841
5842 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5843}
5844
47701c3b
PZ		 5845/* Sequence to disable CLKOUT_DP */
5846static void lpt_disable_clkout_dp(struct drm_device *dev)
5847{
5848 struct drm_i915_private *dev_priv = dev->dev_private;
5849 uint32_t reg, tmp;
5850
5851 mutex_lock(&dev_priv->dpio_lock);
5852
5853 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5854 SBI_GEN0 : SBI_DBUFF0;
5855 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5856 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5857 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5858
5859 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5860 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5861 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5862 tmp |= SBI_SSCCTL_PATHALT;
5863 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5864 udelay(32);
5865 }
5866 tmp |= SBI_SSCCTL_DISABLE;
5867 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5868 }
5869
5870 mutex_unlock(&dev_priv->dpio_lock);
5871}
5872
bf8fa3d3
PZ		 5873static void lpt_init_pch_refclk(struct drm_device *dev)
5874{
5875 struct drm_mode_config *mode_config = &dev->mode_config;
5876 struct intel_encoder *encoder;
5877 bool has_vga = false;
5878
5879 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5880 switch (encoder->type) {
5881 case INTEL_OUTPUT_ANALOG:
5882 has_vga = true;
5883 break;
5884 }
5885 }
5886
47701c3b
PZ		 5887 if (has_vga)
5888 lpt_enable_clkout_dp(dev, true, true);
5889 else
5890 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5891}
5892
dde86e2d
PZ		 5893/*
5894 * Initialize reference clocks when the driver loads
5895 */
5896void intel_init_pch_refclk(struct drm_device *dev)
5897{
5898 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5899 ironlake_init_pch_refclk(dev);
5900 else if (HAS_PCH_LPT(dev))
5901 lpt_init_pch_refclk(dev);
5902}
5903
d9d444cb
JB		 5904static int ironlake_get_refclk(struct drm_crtc *crtc)
5905{
5906 struct drm_device *dev = crtc->dev;
5907 struct drm_i915_private *dev_priv = dev->dev_private;
5908 struct intel_encoder *encoder;
d9d444cb
JB		 5909 int num_connectors = 0;
5910 bool is_lvds = false;
5911
6c2b7c12 5912 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5913 switch (encoder->type) {
5914 case INTEL_OUTPUT_LVDS:
5915 is_lvds = true;
5916 break;
d9d444cb
JB		 5917 }
5918 num_connectors++;
5919 }
5920
5921 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 5922 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 5923 dev_priv->vbt.lvds_ssc_freq);
e91e941b 5924 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 5925 }
5926
5927 return 120000;
5928}
5929
6ff93609 5930static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5931{
c8203565 5932 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5934 int pipe = intel_crtc->pipe;
c8203565
PZ		 5935 uint32_t val;
5936
78114071 5937 val = 0;
c8203565 5938
965e0c48 5939 switch (intel_crtc->config.pipe_bpp) {
c8203565 5940 case 18:
dfd07d72 5941 val |= PIPECONF_6BPC;
c8203565
PZ		 5942 break;
5943 case 24:
dfd07d72 5944 val |= PIPECONF_8BPC;
c8203565
PZ		 5945 break;
5946 case 30:
dfd07d72 5947 val |= PIPECONF_10BPC;
c8203565
PZ		 5948 break;
5949 case 36:
dfd07d72 5950 val |= PIPECONF_12BPC;
c8203565
PZ		 5951 break;
5952 default:
cc769b62
PZ		 5953 /* Case prevented by intel_choose_pipe_bpp_dither. */
5954 BUG();
c8203565
PZ		 5955 }
5956
d8b32247 5957 if (intel_crtc->config.dither)
c8203565
PZ		 5958 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5959
6ff93609 5960 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5961 val |= PIPECONF_INTERLACED_ILK;
5962 else
5963 val |= PIPECONF_PROGRESSIVE;
5964
50f3b016 5965 if (intel_crtc->config.limited_color_range)
3685a8f3 5966 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5967
c8203565
PZ		 5968 I915_WRITE(PIPECONF(pipe), val);
5969 POSTING_READ(PIPECONF(pipe));
5970}
5971
86d3efce
VS		 5972/*
5973 * Set up the pipe CSC unit.
5974 *
5975 * Currently only full range RGB to limited range RGB conversion
5976 * is supported, but eventually this should handle various
5977 * RGB<->YCbCr scenarios as well.
5978 */
50f3b016 5979static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5980{
5981 struct drm_device *dev = crtc->dev;
5982 struct drm_i915_private *dev_priv = dev->dev_private;
5983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5984 int pipe = intel_crtc->pipe;
5985 uint16_t coeff = 0x7800; /* 1.0 */
5986
5987 /*
5988 * TODO: Check what kind of values actually come out of the pipe
5989 * with these coeff/postoff values and adjust to get the best
5990 * accuracy. Perhaps we even need to take the bpc value into
5991 * consideration.
5992 */
5993
50f3b016 5994 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5995 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5996
5997 /*
5998 * GY/GU and RY/RU should be the other way around according
5999 * to BSpec, but reality doesn't agree. Just set them up in
6000 * a way that results in the correct picture.
6001 */
6002 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6003 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6004
6005 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6006 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6007
6008 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6009 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6010
6011 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6012 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6013 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6014
6015 if (INTEL_INFO(dev)->gen > 6) {
6016 uint16_t postoff = 0;
6017
50f3b016 6018 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 6019 postoff = (16 * (1 << 13) / 255) & 0x1fff;
6020
6021 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6022 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6023 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6024
6025 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6026 } else {
6027 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6028
50f3b016 6029 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 6030 mode |= CSC_BLACK_SCREEN_OFFSET;
6031
6032 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6033 }
6034}
6035
6ff93609 6036static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 6037{
756f85cf
PZ		 6038 struct drm_device *dev = crtc->dev;
6039 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 6040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 6041 enum pipe pipe = intel_crtc->pipe;
3b117c8f 6042 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 6043 uint32_t val;
6044
3eff4faa 6045 val = 0;
ee2b0b38 6046
756f85cf 6047 if (IS_HASWELL(dev) && intel_crtc->config.dither)
ee2b0b38
PZ		 6048 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6049
6ff93609 6050 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 6051 val |= PIPECONF_INTERLACED_ILK;
6052 else
6053 val |= PIPECONF_PROGRESSIVE;
6054
702e7a56
PZ		 6055 I915_WRITE(PIPECONF(cpu_transcoder), val);
6056 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 6057
6058 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6059 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf
PZ		 6060
6061 if (IS_BROADWELL(dev)) {
6062 val = 0;
6063
6064 switch (intel_crtc->config.pipe_bpp) {
6065 case 18:
6066 val |= PIPEMISC_DITHER_6_BPC;
6067 break;
6068 case 24:
6069 val |= PIPEMISC_DITHER_8_BPC;
6070 break;
6071 case 30:
6072 val |= PIPEMISC_DITHER_10_BPC;
6073 break;
6074 case 36:
6075 val |= PIPEMISC_DITHER_12_BPC;
6076 break;
6077 default:
6078 /* Case prevented by pipe_config_set_bpp. */
6079 BUG();
6080 }
6081
6082 if (intel_crtc->config.dither)
6083 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6084
6085 I915_WRITE(PIPEMISC(pipe), val);
6086 }
ee2b0b38
PZ		 6087}
6088
6591c6e4 6089static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 6090 intel_clock_t *clock,
6091 bool *has_reduced_clock,
6092 intel_clock_t *reduced_clock)
6093{
6094 struct drm_device *dev = crtc->dev;
6095 struct drm_i915_private *dev_priv = dev->dev_private;
6096 struct intel_encoder *intel_encoder;
6097 int refclk;
d4906093 6098 const intel_limit_t *limit;
a16af721 6099 bool ret, is_lvds = false;
79e53945 6100
6591c6e4
PZ		 6101 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6102 switch (intel_encoder->type) {
79e53945
JB		 6103 case INTEL_OUTPUT_LVDS:
6104 is_lvds = true;
6105 break;
79e53945
JB		 6106 }
6107 }
6108
d9d444cb 6109 refclk = ironlake_get_refclk(crtc);
79e53945 6110
d4906093
ML		 6111 /*
6112 * Returns a set of divisors for the desired target clock with the given
6113 * refclk, or FALSE. The returned values represent the clock equation:
6114 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6115 */
1b894b59 6116 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 6117 ret = dev_priv->display.find_dpll(limit, crtc,
6118 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 6119 refclk, NULL, clock);
6591c6e4
PZ		 6120 if (!ret)
6121 return false;
cda4b7d3 6122
ddc9003c 6123 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 6124 /*
6125 * Ensure we match the reduced clock's P to the target clock.
6126 * If the clocks don't match, we can't switch the display clock
6127 * by using the FP0/FP1. In such case we will disable the LVDS
6128 * downclock feature.
6129 */
ee9300bb
DV		 6130 *has_reduced_clock =
6131 dev_priv->display.find_dpll(limit, crtc,
6132 dev_priv->lvds_downclock,
6133 refclk, clock,
6134 reduced_clock);
652c393a 6135 }
61e9653f 6136
6591c6e4
PZ		 6137 return true;
6138}
6139
d4b1931c
PZ		 6140int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6141{
6142 /*
6143 * Account for spread spectrum to avoid
6144 * oversubscribing the link. Max center spread
6145 * is 2.5%; use 5% for safety's sake.
6146 */
6147 u32 bps = target_clock * bpp * 21 / 20;
6148 return bps / (link_bw * 8) + 1;
6149}
6150
7429e9d4 6151static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 6152{
7429e9d4 6153 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 6154}
6155
de13a2e3 6156static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 6157 u32 *fp,
9a7c7890 6158 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 6159{
de13a2e3 6160 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 6161 struct drm_device *dev = crtc->dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 6163 struct intel_encoder *intel_encoder;
6164 uint32_t dpll;
6cc5f341 6165 int factor, num_connectors = 0;
09ede541 6166 bool is_lvds = false, is_sdvo = false;
79e53945 6167
de13a2e3
PZ		 6168 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6169 switch (intel_encoder->type) {
79e53945
JB		 6170 case INTEL_OUTPUT_LVDS:
6171 is_lvds = true;
6172 break;
6173 case INTEL_OUTPUT_SDVO:
7d57382e 6174 case INTEL_OUTPUT_HDMI:
79e53945 6175 is_sdvo = true;
79e53945 6176 break;
79e53945 6177 }
43565a06 6178
c751ce4f 6179 num_connectors++;
79e53945 6180 }
79e53945 6181
c1858123 6182 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 6183 factor = 21;
6184 if (is_lvds) {
6185 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 6186 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 6187 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 6188 factor = 25;
09ede541 6189 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 6190 factor = 20;
c1858123 6191
7429e9d4 6192 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 6193 *fp |= FP_CB_TUNE;
2c07245f 6194
9a7c7890
DV		 6195 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6196 *fp2 |= FP_CB_TUNE;
6197
5eddb70b 6198 dpll = 0;
2c07245f 6199
a07d6787
EA		 6200 if (is_lvds)
6201 dpll |= DPLLB_MODE_LVDS;
6202 else
6203 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 6204
ef1b460d
DV		 6205 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6206 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 6207
6208 if (is_sdvo)
4a33e48d 6209 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 6210 if (intel_crtc->config.has_dp_encoder)
4a33e48d 6211 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 6212
a07d6787 6213 /* compute bitmask from p1 value */
7429e9d4 6214 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 6215 /* also FPA1 */
7429e9d4 6216 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 6217
7429e9d4 6218 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 6219 case 5:
6220 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6221 break;
6222 case 7:
6223 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6224 break;
6225 case 10:
6226 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6227 break;
6228 case 14:
6229 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6230 break;
79e53945
JB		 6231 }
6232
b4c09f3b 6233 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 6234 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 6235 else
6236 dpll |= PLL_REF_INPUT_DREFCLK;
6237
959e16d6 6238 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 6239}
6240
6241static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 6242 int x, int y,
6243 struct drm_framebuffer *fb)
6244{
6245 struct drm_device *dev = crtc->dev;
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6248 int pipe = intel_crtc->pipe;
6249 int plane = intel_crtc->plane;
6250 int num_connectors = 0;
6251 intel_clock_t clock, reduced_clock;
cbbab5bd 6252 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 6253 bool ok, has_reduced_clock = false;
8b47047b 6254 bool is_lvds = false;
de13a2e3 6255 struct intel_encoder *encoder;
e2b78267 6256 struct intel_shared_dpll *pll;
de13a2e3 6257 int ret;
de13a2e3
PZ		 6258
6259 for_each_encoder_on_crtc(dev, crtc, encoder) {
6260 switch (encoder->type) {
6261 case INTEL_OUTPUT_LVDS:
6262 is_lvds = true;
6263 break;
de13a2e3
PZ		 6264 }
6265
6266 num_connectors++;
a07d6787 6267 }
79e53945 6268
5dc5298b
PZ		 6269 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6270 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6271
ff9a6750 6272 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6273 &has_reduced_clock, &reduced_clock);
ee9300bb 6274 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6275 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6276 return -EINVAL;
79e53945 6277 }
f47709a9
DV		 6278 /* Compat-code for transition, will disappear. */
6279 if (!intel_crtc->config.clock_set) {
6280 intel_crtc->config.dpll.n = clock.n;
6281 intel_crtc->config.dpll.m1 = clock.m1;
6282 intel_crtc->config.dpll.m2 = clock.m2;
6283 intel_crtc->config.dpll.p1 = clock.p1;
6284 intel_crtc->config.dpll.p2 = clock.p2;
6285 }
79e53945 6286
5dc5298b 6287 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6288 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6289 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6290 if (has_reduced_clock)
7429e9d4 6291 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6292
7429e9d4 6293 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6294 &fp, &reduced_clock,
6295 has_reduced_clock ? &fp2 : NULL);
6296
959e16d6 6297 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6298 intel_crtc->config.dpll_hw_state.fp0 = fp;
6299 if (has_reduced_clock)
6300 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6301 else
6302 intel_crtc->config.dpll_hw_state.fp1 = fp;
6303
b89a1d39 6304 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6305 if (pll == NULL) {
84f44ce7
VS		 6306 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6307 pipe_name(pipe));
4b645f14
JB		 6308 return -EINVAL;
6309 }
ee7b9f93 6310 } else
e72f9fbf 6311 intel_put_shared_dpll(intel_crtc);
79e53945 6312
03afc4a2
DV		 6313 if (intel_crtc->config.has_dp_encoder)
6314 intel_dp_set_m_n(intel_crtc);
79e53945 6315
bcd644e0
DV		 6316 if (is_lvds && has_reduced_clock && i915_powersave)
6317 intel_crtc->lowfreq_avail = true;
6318 else
6319 intel_crtc->lowfreq_avail = false;
e2b78267 6320
8a654f3b 6321 intel_set_pipe_timings(intel_crtc);
5eddb70b 6322
ca3a0ff8 6323 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6324 intel_cpu_transcoder_set_m_n(intel_crtc,
6325 &intel_crtc->config.fdi_m_n);
6326 }
2c07245f 6327
6ff93609 6328 ironlake_set_pipeconf(crtc);
79e53945 6329
a1f9e77e
PZ		 6330 /* Set up the display plane register */
6331 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6332 POSTING_READ(DSPCNTR(plane));
79e53945 6333
94352cf9 6334 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6335
1857e1da 6336 return ret;
79e53945
JB		 6337}
6338
eb14cb74
VS		 6339static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6340 struct intel_link_m_n *m_n)
6341{
6342 struct drm_device *dev = crtc->base.dev;
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344 enum pipe pipe = crtc->pipe;
6345
6346 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6347 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6348 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6349 & ~TU_SIZE_MASK;
6350 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6351 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6352 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6353}
6354
6355static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6356 enum transcoder transcoder,
6357 struct intel_link_m_n *m_n)
72419203
DV		 6358{
6359 struct drm_device *dev = crtc->base.dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6361 enum pipe pipe = crtc->pipe;
72419203 6362
eb14cb74
VS		 6363 if (INTEL_INFO(dev)->gen >= 5) {
6364 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6365 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6366 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6367 & ~TU_SIZE_MASK;
6368 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6369 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6370 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6371 } else {
6372 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6373 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6374 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6375 & ~TU_SIZE_MASK;
6376 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6377 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6378 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6379 }
6380}
6381
6382void intel_dp_get_m_n(struct intel_crtc *crtc,
6383 struct intel_crtc_config *pipe_config)
6384{
6385 if (crtc->config.has_pch_encoder)
6386 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6387 else
6388 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6389 &pipe_config->dp_m_n);
6390}
72419203 6391
eb14cb74
VS		 6392static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6393 struct intel_crtc_config *pipe_config)
6394{
6395 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6396 &pipe_config->fdi_m_n);
72419203
DV		 6397}
6398
2fa2fe9a
DV		 6399static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6400 struct intel_crtc_config *pipe_config)
6401{
6402 struct drm_device *dev = crtc->base.dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 uint32_t tmp;
6405
6406 tmp = I915_READ(PF_CTL(crtc->pipe));
6407
6408 if (tmp & PF_ENABLE) {
fd4daa9c 6409 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6410 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6411 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6412
6413 /* We currently do not free assignements of panel fitters on
6414 * ivb/hsw (since we don't use the higher upscaling modes which
6415 * differentiates them) so just WARN about this case for now. */
6416 if (IS_GEN7(dev)) {
6417 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6418 PF_PIPE_SEL_IVB(crtc->pipe));
6419 }
2fa2fe9a 6420 }
79e53945
JB		 6421}
6422
0e8ffe1b
DV		 6423static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6424 struct intel_crtc_config *pipe_config)
6425{
6426 struct drm_device *dev = crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 uint32_t tmp;
6429
e143a21c 6430 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6431 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6432
0e8ffe1b
DV		 6433 tmp = I915_READ(PIPECONF(crtc->pipe));
6434 if (!(tmp & PIPECONF_ENABLE))
6435 return false;
6436
42571aef
VS		 6437 switch (tmp & PIPECONF_BPC_MASK) {
6438 case PIPECONF_6BPC:
6439 pipe_config->pipe_bpp = 18;
6440 break;
6441 case PIPECONF_8BPC:
6442 pipe_config->pipe_bpp = 24;
6443 break;
6444 case PIPECONF_10BPC:
6445 pipe_config->pipe_bpp = 30;
6446 break;
6447 case PIPECONF_12BPC:
6448 pipe_config->pipe_bpp = 36;
6449 break;
6450 default:
6451 break;
6452 }
6453
ab9412ba 6454 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6455 struct intel_shared_dpll *pll;
6456
88adfff1
DV		 6457 pipe_config->has_pch_encoder = true;
6458
627eb5a3
DV		 6459 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6460 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6461 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6462
6463 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6464
c0d43d62 6465 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6466 pipe_config->shared_dpll =
6467 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6468 } else {
6469 tmp = I915_READ(PCH_DPLL_SEL);
6470 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6471 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6472 else
6473 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6474 }
66e985c0
DV		 6475
6476 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6477
6478 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6479 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6480
6481 tmp = pipe_config->dpll_hw_state.dpll;
6482 pipe_config->pixel_multiplier =
6483 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6484 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6485
6486 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6487 } else {
6488 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6489 }
6490
1bd1bd80
DV		 6491 intel_get_pipe_timings(crtc, pipe_config);
6492
2fa2fe9a
DV		 6493 ironlake_get_pfit_config(crtc, pipe_config);
6494
0e8ffe1b
DV		 6495 return true;
6496}
6497
be256dc7
PZ		 6498static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6499{
6500 struct drm_device *dev = dev_priv->dev;
6501 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6502 struct intel_crtc *crtc;
6503 unsigned long irqflags;
bd633a7c 6504 uint32_t val;
be256dc7
PZ		 6505
6506 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
798183c5 6507 WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 6508 pipe_name(crtc->pipe));
6509
6510 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6511 WARN(plls->spll_refcount, "SPLL enabled\n");
6512 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6513 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6514 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6515 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6516 "CPU PWM1 enabled\n");
6517 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6518 "CPU PWM2 enabled\n");
6519 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6520 "PCH PWM1 enabled\n");
6521 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6522 "Utility pin enabled\n");
6523 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6524
6525 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6526 val = I915_READ(DEIMR);
6806e63f 6527 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
be256dc7
PZ		 6528 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6529 val = I915_READ(SDEIMR);
bd633a7c 6530 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6531 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6532 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6533}
6534
6535/*
6536 * This function implements pieces of two sequences from BSpec:
6537 * - Sequence for display software to disable LCPLL
6538 * - Sequence for display software to allow package C8+
6539 * The steps implemented here are just the steps that actually touch the LCPLL
6540 * register. Callers should take care of disabling all the display engine
6541 * functions, doing the mode unset, fixing interrupts, etc.
6542 */
6ff58d53
PZ		 6543static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6544 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6545{
6546 uint32_t val;
6547
6548 assert_can_disable_lcpll(dev_priv);
6549
6550 val = I915_READ(LCPLL_CTL);
6551
6552 if (switch_to_fclk) {
6553 val |= LCPLL_CD_SOURCE_FCLK;
6554 I915_WRITE(LCPLL_CTL, val);
6555
6556 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6557 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6558 DRM_ERROR("Switching to FCLK failed\n");
6559
6560 val = I915_READ(LCPLL_CTL);
6561 }
6562
6563 val |= LCPLL_PLL_DISABLE;
6564 I915_WRITE(LCPLL_CTL, val);
6565 POSTING_READ(LCPLL_CTL);
6566
6567 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6568 DRM_ERROR("LCPLL still locked\n");
6569
6570 val = I915_READ(D_COMP);
6571 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6572 mutex_lock(&dev_priv->rps.hw_lock);
6573 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6574 DRM_ERROR("Failed to disable D_COMP\n");
6575 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6576 POSTING_READ(D_COMP);
6577 ndelay(100);
6578
6579 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6580 DRM_ERROR("D_COMP RCOMP still in progress\n");
6581
6582 if (allow_power_down) {
6583 val = I915_READ(LCPLL_CTL);
6584 val |= LCPLL_POWER_DOWN_ALLOW;
6585 I915_WRITE(LCPLL_CTL, val);
6586 POSTING_READ(LCPLL_CTL);
6587 }
6588}
6589
6590/*
6591 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6592 * source.
6593 */
6ff58d53 6594static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6595{
6596 uint32_t val;
6597
6598 val = I915_READ(LCPLL_CTL);
6599
6600 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6601 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6602 return;
6603
215733fa
PZ		 6604 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6605 * we'll hang the machine! */
c8d9a590 6606 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
215733fa 6607
be256dc7
PZ		 6608 if (val & LCPLL_POWER_DOWN_ALLOW) {
6609 val &= ~LCPLL_POWER_DOWN_ALLOW;
6610 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6611 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6612 }
6613
6614 val = I915_READ(D_COMP);
6615 val |= D_COMP_COMP_FORCE;
6616 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6617 mutex_lock(&dev_priv->rps.hw_lock);
6618 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6619 DRM_ERROR("Failed to enable D_COMP\n");
6620 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6621 POSTING_READ(D_COMP);
be256dc7
PZ		 6622
6623 val = I915_READ(LCPLL_CTL);
6624 val &= ~LCPLL_PLL_DISABLE;
6625 I915_WRITE(LCPLL_CTL, val);
6626
6627 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6628 DRM_ERROR("LCPLL not locked yet\n");
6629
6630 if (val & LCPLL_CD_SOURCE_FCLK) {
6631 val = I915_READ(LCPLL_CTL);
6632 val &= ~LCPLL_CD_SOURCE_FCLK;
6633 I915_WRITE(LCPLL_CTL, val);
6634
6635 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6636 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6637 DRM_ERROR("Switching back to LCPLL failed\n");
6638 }
215733fa 6639
c8d9a590 6640 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 6641}
6642
c67a470b
PZ		 6643void hsw_enable_pc8_work(struct work_struct *__work)
6644{
6645 struct drm_i915_private *dev_priv =
6646 container_of(to_delayed_work(__work), struct drm_i915_private,
6647 pc8.enable_work);
6648 struct drm_device *dev = dev_priv->dev;
6649 uint32_t val;
6650
7125ecb8
PZ		 6651 WARN_ON(!HAS_PC8(dev));
6652
c67a470b
PZ		 6653 if (dev_priv->pc8.enabled)
6654 return;
6655
6656 DRM_DEBUG_KMS("Enabling package C8+\n");
6657
6658 dev_priv->pc8.enabled = true;
6659
6660 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6661 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6662 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6663 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6664 }
6665
6666 lpt_disable_clkout_dp(dev);
6667 hsw_pc8_disable_interrupts(dev);
6668 hsw_disable_lcpll(dev_priv, true, true);
8771a7f8
PZ		 6669
6670 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6671}
6672
6673static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6674{
6675 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6676 WARN(dev_priv->pc8.disable_count < 1,
6677 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6678
6679 dev_priv->pc8.disable_count--;
6680 if (dev_priv->pc8.disable_count != 0)
6681 return;
6682
6683 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6684 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6685}
6686
6687static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6688{
6689 struct drm_device *dev = dev_priv->dev;
6690 uint32_t val;
6691
6692 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6693 WARN(dev_priv->pc8.disable_count < 0,
6694 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6695
6696 dev_priv->pc8.disable_count++;
6697 if (dev_priv->pc8.disable_count != 1)
6698 return;
6699
7125ecb8
PZ		 6700 WARN_ON(!HAS_PC8(dev));
6701
c67a470b
PZ		 6702 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6703 if (!dev_priv->pc8.enabled)
6704 return;
6705
6706 DRM_DEBUG_KMS("Disabling package C8+\n");
6707
8771a7f8
PZ		 6708 intel_runtime_pm_get(dev_priv);
6709
c67a470b
PZ		 6710 hsw_restore_lcpll(dev_priv);
6711 hsw_pc8_restore_interrupts(dev);
6712 lpt_init_pch_refclk(dev);
6713
6714 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6715 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6716 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6717 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6718 }
6719
6720 intel_prepare_ddi(dev);
6721 i915_gem_init_swizzling(dev);
6722 mutex_lock(&dev_priv->rps.hw_lock);
6723 gen6_update_ring_freq(dev);
6724 mutex_unlock(&dev_priv->rps.hw_lock);
6725 dev_priv->pc8.enabled = false;
6726}
6727
6728void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6729{
7c6c2652
CW		 6730 if (!HAS_PC8(dev_priv->dev))
6731 return;
6732
c67a470b
PZ		 6733 mutex_lock(&dev_priv->pc8.lock);
6734 __hsw_enable_package_c8(dev_priv);
6735 mutex_unlock(&dev_priv->pc8.lock);
6736}
6737
6738void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6739{
7c6c2652
CW		 6740 if (!HAS_PC8(dev_priv->dev))
6741 return;
6742
c67a470b
PZ		 6743 mutex_lock(&dev_priv->pc8.lock);
6744 __hsw_disable_package_c8(dev_priv);
6745 mutex_unlock(&dev_priv->pc8.lock);
6746}
6747
6748static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6749{
6750 struct drm_device *dev = dev_priv->dev;
6751 struct intel_crtc *crtc;
6752 uint32_t val;
6753
6754 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6755 if (crtc->base.enabled)
6756 return false;
6757
6758 /* This case is still possible since we have the i915.disable_power_well
6759 * parameter and also the KVMr or something else might be requesting the
6760 * power well. */
6761 val = I915_READ(HSW_PWR_WELL_DRIVER);
6762 if (val != 0) {
6763 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6764 return false;
6765 }
6766
6767 return true;
6768}
6769
6770/* Since we're called from modeset_global_resources there's no way to
6771 * symmetrically increase and decrease the refcount, so we use
6772 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6773 * or not.
6774 */
6775static void hsw_update_package_c8(struct drm_device *dev)
6776{
6777 struct drm_i915_private *dev_priv = dev->dev_private;
6778 bool allow;
6779
7c6c2652
CW		 6780 if (!HAS_PC8(dev_priv->dev))
6781 return;
6782
c67a470b
PZ		 6783 if (!i915_enable_pc8)
6784 return;
6785
6786 mutex_lock(&dev_priv->pc8.lock);
6787
6788 allow = hsw_can_enable_package_c8(dev_priv);
6789
6790 if (allow == dev_priv->pc8.requirements_met)
6791 goto done;
6792
6793 dev_priv->pc8.requirements_met = allow;
6794
6795 if (allow)
6796 __hsw_enable_package_c8(dev_priv);
6797 else
6798 __hsw_disable_package_c8(dev_priv);
6799
6800done:
6801 mutex_unlock(&dev_priv->pc8.lock);
6802}
6803
6804static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6805{
7c6c2652
CW		 6806 if (!HAS_PC8(dev_priv->dev))
6807 return;
6808
3458122e 6809 mutex_lock(&dev_priv->pc8.lock);
c67a470b
PZ		 6810 if (!dev_priv->pc8.gpu_idle) {
6811 dev_priv->pc8.gpu_idle = true;
3458122e 6812 __hsw_enable_package_c8(dev_priv);
c67a470b 6813 }
3458122e 6814 mutex_unlock(&dev_priv->pc8.lock);
c67a470b
PZ		 6815}
6816
6817static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6818{
7c6c2652
CW		 6819 if (!HAS_PC8(dev_priv->dev))
6820 return;
6821
3458122e 6822 mutex_lock(&dev_priv->pc8.lock);
c67a470b
PZ		 6823 if (dev_priv->pc8.gpu_idle) {
6824 dev_priv->pc8.gpu_idle = false;
3458122e 6825 __hsw_disable_package_c8(dev_priv);
c67a470b 6826 }
3458122e 6827 mutex_unlock(&dev_priv->pc8.lock);
be256dc7
PZ		 6828}
6829
6efdf354
ID		 6830#define for_each_power_domain(domain, mask) \
6831 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6832 if ((1 << (domain)) & (mask))
6833
6834static unsigned long get_pipe_power_domains(struct drm_device *dev,
6835 enum pipe pipe, bool pfit_enabled)
6836{
6837 unsigned long mask;
6838 enum transcoder transcoder;
6839
6840 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6841
6842 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6843 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6844 if (pfit_enabled)
6845 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6846
6847 return mask;
6848}
6849
baa70707
ID		 6850void intel_display_set_init_power(struct drm_device *dev, bool enable)
6851{
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853
6854 if (dev_priv->power_domains.init_power_on == enable)
6855 return;
6856
6857 if (enable)
6858 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6859 else
6860 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6861
6862 dev_priv->power_domains.init_power_on = enable;
6863}
6864
4f074129 6865static void modeset_update_power_wells(struct drm_device *dev)
d6dd9eb1 6866{
6efdf354 6867 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
d6dd9eb1 6868 struct intel_crtc *crtc;
d6dd9eb1 6869
6efdf354
ID		 6870 /*
6871 * First get all needed power domains, then put all unneeded, to avoid
6872 * any unnecessary toggling of the power wells.
6873 */
d6dd9eb1 6874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6efdf354
ID		 6875 enum intel_display_power_domain domain;
6876
e7a639c4
DV		 6877 if (!crtc->base.enabled)
6878 continue;
d6dd9eb1 6879
6efdf354
ID		 6880 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6881 crtc->pipe,
6882 crtc->config.pch_pfit.enabled);
6883
6884 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6885 intel_display_power_get(dev, domain);
d6dd9eb1
DV		 6886 }
6887
6efdf354
ID		 6888 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6889 enum intel_display_power_domain domain;
6890
6891 for_each_power_domain(domain, crtc->enabled_power_domains)
6892 intel_display_power_put(dev, domain);
6893
6894 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6895 }
baa70707
ID		 6896
6897 intel_display_set_init_power(dev, false);
4f074129 6898}
c67a470b 6899
4f074129
ID		 6900static void haswell_modeset_global_resources(struct drm_device *dev)
6901{
6902 modeset_update_power_wells(dev);
c67a470b 6903 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6904}
6905
09b4ddf9 6906static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6907 int x, int y,
6908 struct drm_framebuffer *fb)
6909{
6910 struct drm_device *dev = crtc->dev;
6911 struct drm_i915_private *dev_priv = dev->dev_private;
6912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6913 int plane = intel_crtc->plane;
09b4ddf9 6914 int ret;
09b4ddf9 6915
566b734a 6916 if (!intel_ddi_pll_select(intel_crtc))
6441ab5f 6917 return -EINVAL;
566b734a 6918 intel_ddi_pll_enable(intel_crtc);
6441ab5f 6919
03afc4a2
DV		 6920 if (intel_crtc->config.has_dp_encoder)
6921 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6922
6923 intel_crtc->lowfreq_avail = false;
09b4ddf9 6924
8a654f3b 6925 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6926
ca3a0ff8 6927 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6928 intel_cpu_transcoder_set_m_n(intel_crtc,
6929 &intel_crtc->config.fdi_m_n);
6930 }
09b4ddf9 6931
6ff93609 6932 haswell_set_pipeconf(crtc);
09b4ddf9 6933
50f3b016 6934 intel_set_pipe_csc(crtc);
86d3efce 6935
09b4ddf9 6936 /* Set up the display plane register */
86d3efce 6937 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6938 POSTING_READ(DSPCNTR(plane));
6939
6940 ret = intel_pipe_set_base(crtc, x, y, fb);
6941
1f803ee5 6942 return ret;
79e53945
JB		 6943}
6944
0e8ffe1b
DV		 6945static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6946 struct intel_crtc_config *pipe_config)
6947{
6948 struct drm_device *dev = crtc->base.dev;
6949 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6950 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6951 uint32_t tmp;
6952
e143a21c 6953 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6954 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6955
eccb140b
DV		 6956 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6957 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6958 enum pipe trans_edp_pipe;
6959 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6960 default:
6961 WARN(1, "unknown pipe linked to edp transcoder\n");
6962 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6963 case TRANS_DDI_EDP_INPUT_A_ON:
6964 trans_edp_pipe = PIPE_A;
6965 break;
6966 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6967 trans_edp_pipe = PIPE_B;
6968 break;
6969 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6970 trans_edp_pipe = PIPE_C;
6971 break;
6972 }
6973
6974 if (trans_edp_pipe == crtc->pipe)
6975 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6976 }
6977
b97186f0 6978 if (!intel_display_power_enabled(dev,
eccb140b 6979 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6980 return false;
6981
eccb140b 6982 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6983 if (!(tmp & PIPECONF_ENABLE))
6984 return false;
6985
88adfff1 6986 /*
f196e6be 6987 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6988 * DDI E. So just check whether this pipe is wired to DDI E and whether
6989 * the PCH transcoder is on.
6990 */
eccb140b 6991 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6992 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6993 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6994 pipe_config->has_pch_encoder = true;
6995
627eb5a3
DV		 6996 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6997 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6998 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6999
7000 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 7001 }
7002
1bd1bd80
DV		 7003 intel_get_pipe_timings(crtc, pipe_config);
7004
2fa2fe9a
DV		 7005 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7006 if (intel_display_power_enabled(dev, pfit_domain))
7007 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 7008
e59150dc
JB		 7009 if (IS_HASWELL(dev))
7010 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7011 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 7012
6c49f241
DV		 7013 pipe_config->pixel_multiplier = 1;
7014
0e8ffe1b
DV		 7015 return true;
7016}
7017
f564048e 7018static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 7019 int x, int y,
94352cf9 7020 struct drm_framebuffer *fb)
f564048e
EA		 7021{
7022 struct drm_device *dev = crtc->dev;
7023 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 7024 struct intel_encoder *encoder;
0b701d27 7025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 7026 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 7027 int pipe = intel_crtc->pipe;
f564048e
EA		 7028 int ret;
7029
0b701d27 7030 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 7031
b8cecdf5
DV		 7032 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7033
79e53945 7034 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 7035
9256aa19
DV		 7036 if (ret != 0)
7037 return ret;
7038
7039 for_each_encoder_on_crtc(dev, crtc, encoder) {
7040 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7041 encoder->base.base.id,
7042 drm_get_encoder_name(&encoder->base),
7043 mode->base.id, mode->name);
36f2d1f1 7044 encoder->mode_set(encoder);
9256aa19
DV		 7045 }
7046
7047 return 0;
79e53945
JB		 7048}
7049
1a91510d
JN		 7050static struct {
7051 int clock;
7052 u32 config;
7053} hdmi_audio_clock[] = {
7054 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7055 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7056 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7057 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7058 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7059 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7060 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7061 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7062 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7063 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7064};
7065
7066/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7067static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7068{
7069 int i;
7070
7071 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7072 if (mode->clock == hdmi_audio_clock[i].clock)
7073 break;
7074 }
7075
7076 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7077 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7078 i = 1;
7079 }
7080
7081 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7082 hdmi_audio_clock[i].clock,
7083 hdmi_audio_clock[i].config);
7084
7085 return hdmi_audio_clock[i].config;
7086}
7087
3a9627f4
WF		 7088static bool intel_eld_uptodate(struct drm_connector *connector,
7089 int reg_eldv, uint32_t bits_eldv,
7090 int reg_elda, uint32_t bits_elda,
7091 int reg_edid)
7092{
7093 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7094 uint8_t *eld = connector->eld;
7095 uint32_t i;
7096
7097 i = I915_READ(reg_eldv);
7098 i &= bits_eldv;
7099
7100 if (!eld[0])
7101 return !i;
7102
7103 if (!i)
7104 return false;
7105
7106 i = I915_READ(reg_elda);
7107 i &= ~bits_elda;
7108 I915_WRITE(reg_elda, i);
7109
7110 for (i = 0; i < eld[2]; i++)
7111 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7112 return false;
7113
7114 return true;
7115}
7116
e0dac65e 7117static void g4x_write_eld(struct drm_connector *connector,
34427052
JN		 7118 struct drm_crtc *crtc,
7119 struct drm_display_mode *mode)
e0dac65e
WF		 7120{
7121 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7122 uint8_t *eld = connector->eld;
7123 uint32_t eldv;
7124 uint32_t len;
7125 uint32_t i;
7126
7127 i = I915_READ(G4X_AUD_VID_DID);
7128
7129 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7130 eldv = G4X_ELDV_DEVCL_DEVBLC;
7131 else
7132 eldv = G4X_ELDV_DEVCTG;
7133
3a9627f4
WF		 7134 if (intel_eld_uptodate(connector,
7135 G4X_AUD_CNTL_ST, eldv,
7136 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7137 G4X_HDMIW_HDMIEDID))
7138 return;
7139
e0dac65e
WF		 7140 i = I915_READ(G4X_AUD_CNTL_ST);
7141 i &= ~(eldv | G4X_ELD_ADDR);
7142 len = (i >> 9) & 0x1f; /* ELD buffer size */
7143 I915_WRITE(G4X_AUD_CNTL_ST, i);
7144
7145 if (!eld[0])
7146 return;
7147
7148 len = min_t(uint8_t, eld[2], len);
7149 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7150 for (i = 0; i < len; i++)
7151 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7152
7153 i = I915_READ(G4X_AUD_CNTL_ST);
7154 i |= eldv;
7155 I915_WRITE(G4X_AUD_CNTL_ST, i);
7156}
7157
83358c85 7158static void haswell_write_eld(struct drm_connector *connector,
34427052
JN		 7159 struct drm_crtc *crtc,
7160 struct drm_display_mode *mode)
83358c85
WX		 7161{
7162 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7163 uint8_t *eld = connector->eld;
7164 struct drm_device *dev = crtc->dev;
7b9f35a6 7165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 7166 uint32_t eldv;
7167 uint32_t i;
7168 int len;
7169 int pipe = to_intel_crtc(crtc)->pipe;
7170 int tmp;
7171
7172 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7173 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7174 int aud_config = HSW_AUD_CFG(pipe);
7175 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7176
7177
7178 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7179
7180 /* Audio output enable */
7181 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7182 tmp = I915_READ(aud_cntrl_st2);
7183 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7184 I915_WRITE(aud_cntrl_st2, tmp);
7185
7186 /* Wait for 1 vertical blank */
7187 intel_wait_for_vblank(dev, pipe);
7188
7189 /* Set ELD valid state */
7190 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 7191 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 7192 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7193 I915_WRITE(aud_cntrl_st2, tmp);
7194 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 7195 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 7196
7197 /* Enable HDMI mode */
7198 tmp = I915_READ(aud_config);
7e7cb34f 7199 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 7200 /* clear N_programing_enable and N_value_index */
7201 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7202 I915_WRITE(aud_config, tmp);
7203
7204 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7205
7206 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 7207 intel_crtc->eld_vld = true;
83358c85
WX		 7208
7209 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7210 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7211 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7212 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
1a91510d
JN		 7213 } else {
7214 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7215 }
83358c85
WX		 7216
7217 if (intel_eld_uptodate(connector,
7218 aud_cntrl_st2, eldv,
7219 aud_cntl_st, IBX_ELD_ADDRESS,
7220 hdmiw_hdmiedid))
7221 return;
7222
7223 i = I915_READ(aud_cntrl_st2);
7224 i &= ~eldv;
7225 I915_WRITE(aud_cntrl_st2, i);
7226
7227 if (!eld[0])
7228 return;
7229
7230 i = I915_READ(aud_cntl_st);
7231 i &= ~IBX_ELD_ADDRESS;
7232 I915_WRITE(aud_cntl_st, i);
7233 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7234 DRM_DEBUG_DRIVER("port num:%d\n", i);
7235
7236 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7237 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7238 for (i = 0; i < len; i++)
7239 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7240
7241 i = I915_READ(aud_cntrl_st2);
7242 i |= eldv;
7243 I915_WRITE(aud_cntrl_st2, i);
7244
7245}
7246
e0dac65e 7247static void ironlake_write_eld(struct drm_connector *connector,
34427052
JN		 7248 struct drm_crtc *crtc,
7249 struct drm_display_mode *mode)
e0dac65e
WF		 7250{
7251 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7252 uint8_t *eld = connector->eld;
7253 uint32_t eldv;
7254 uint32_t i;
7255 int len;
7256 int hdmiw_hdmiedid;
b6daa025 7257 int aud_config;
e0dac65e
WF		 7258 int aud_cntl_st;
7259 int aud_cntrl_st2;
9b138a83 7260 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 7261
b3f33cbf 7262 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 7263 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7264 aud_config = IBX_AUD_CFG(pipe);
7265 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 7266 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
9ca2fe73
ML		 7267 } else if (IS_VALLEYVIEW(connector->dev)) {
7268 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7269 aud_config = VLV_AUD_CFG(pipe);
7270 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7271 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
e0dac65e 7272 } else {
9b138a83
WX		 7273 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7274 aud_config = CPT_AUD_CFG(pipe);
7275 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 7276 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 7277 }
7278
9b138a83 7279 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e 7280
9ca2fe73
ML		 7281 if (IS_VALLEYVIEW(connector->dev)) {
7282 struct intel_encoder *intel_encoder;
7283 struct intel_digital_port *intel_dig_port;
7284
7285 intel_encoder = intel_attached_encoder(connector);
7286 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7287 i = intel_dig_port->port;
7288 } else {
7289 i = I915_READ(aud_cntl_st);
7290 i = (i >> 29) & DIP_PORT_SEL_MASK;
7291 /* DIP_Port_Select, 0x1 = PortB */
7292 }
7293
e0dac65e
WF		 7294 if (!i) {
7295 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7296 /* operate blindly on all ports */
1202b4c6
WF		 7297 eldv = IBX_ELD_VALIDB;
7298 eldv |= IBX_ELD_VALIDB << 4;
7299 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 7300 } else {
2582a850 7301 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 7302 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 7303 }
7304
3a9627f4
WF		 7305 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7306 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7307 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025 7308 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
1a91510d
JN		 7309 } else {
7310 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7311 }
e0dac65e 7312
3a9627f4
WF		 7313 if (intel_eld_uptodate(connector,
7314 aud_cntrl_st2, eldv,
7315 aud_cntl_st, IBX_ELD_ADDRESS,
7316 hdmiw_hdmiedid))
7317 return;
7318
e0dac65e
WF		 7319 i = I915_READ(aud_cntrl_st2);
7320 i &= ~eldv;
7321 I915_WRITE(aud_cntrl_st2, i);
7322
7323 if (!eld[0])
7324 return;
7325
e0dac65e 7326 i = I915_READ(aud_cntl_st);
1202b4c6 7327 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 7328 I915_WRITE(aud_cntl_st, i);
7329
7330 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7331 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7332 for (i = 0; i < len; i++)
7333 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7334
7335 i = I915_READ(aud_cntrl_st2);
7336 i |= eldv;
7337 I915_WRITE(aud_cntrl_st2, i);
7338}
7339
7340void intel_write_eld(struct drm_encoder *encoder,
7341 struct drm_display_mode *mode)
7342{
7343 struct drm_crtc *crtc = encoder->crtc;
7344 struct drm_connector *connector;
7345 struct drm_device *dev = encoder->dev;
7346 struct drm_i915_private *dev_priv = dev->dev_private;
7347
7348 connector = drm_select_eld(encoder, mode);
7349 if (!connector)
7350 return;
7351
7352 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7353 connector->base.id,
7354 drm_get_connector_name(connector),
7355 connector->encoder->base.id,
7356 drm_get_encoder_name(connector->encoder));
7357
7358 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7359
7360 if (dev_priv->display.write_eld)
34427052 7361 dev_priv->display.write_eld(connector, crtc, mode);
e0dac65e
WF		 7362}
7363
560b85bb
CW		 7364static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7365{
7366 struct drm_device *dev = crtc->dev;
7367 struct drm_i915_private *dev_priv = dev->dev_private;
7368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7369 bool visible = base != 0;
7370 u32 cntl;
7371
7372 if (intel_crtc->cursor_visible == visible)
7373 return;
7374
9db4a9c7 7375 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 7376 if (visible) {
7377 /* On these chipsets we can only modify the base whilst
7378 * the cursor is disabled.
7379 */
9db4a9c7 7380 I915_WRITE(_CURABASE, base);
560b85bb
CW		 7381
7382 cntl &= ~(CURSOR_FORMAT_MASK);
7383 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7384 cntl |= CURSOR_ENABLE |
7385 CURSOR_GAMMA_ENABLE |
7386 CURSOR_FORMAT_ARGB;
7387 } else
7388 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 7389 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 7390
7391 intel_crtc->cursor_visible = visible;
7392}
7393
7394static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7395{
7396 struct drm_device *dev = crtc->dev;
7397 struct drm_i915_private *dev_priv = dev->dev_private;
7398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7399 int pipe = intel_crtc->pipe;
7400 bool visible = base != 0;
7401
7402 if (intel_crtc->cursor_visible != visible) {
548f245b 7403 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7404 if (base) {
7405 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7406 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7407 cntl |= pipe << 28; /* Connect to correct pipe */
7408 } else {
7409 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7410 cntl |= CURSOR_MODE_DISABLE;
7411 }
9db4a9c7 7412 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7413
7414 intel_crtc->cursor_visible = visible;
7415 }
7416 /* and commit changes on next vblank */
b2ea8ef5 7417 POSTING_READ(CURCNTR(pipe));
9db4a9c7 7418 I915_WRITE(CURBASE(pipe), base);
b2ea8ef5 7419 POSTING_READ(CURBASE(pipe));
560b85bb
CW		 7420}
7421
65a21cd6
JB		 7422static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7423{
7424 struct drm_device *dev = crtc->dev;
7425 struct drm_i915_private *dev_priv = dev->dev_private;
7426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7427 int pipe = intel_crtc->pipe;
7428 bool visible = base != 0;
7429
7430 if (intel_crtc->cursor_visible != visible) {
7431 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7432 if (base) {
7433 cntl &= ~CURSOR_MODE;
7434 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7435 } else {
7436 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7437 cntl |= CURSOR_MODE_DISABLE;
7438 }
6bbfa1c5 7439 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
86d3efce 7440 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7441 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7442 }
65a21cd6
JB		 7443 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7444
7445 intel_crtc->cursor_visible = visible;
7446 }
7447 /* and commit changes on next vblank */
b2ea8ef5 7448 POSTING_READ(CURCNTR_IVB(pipe));
65a21cd6 7449 I915_WRITE(CURBASE_IVB(pipe), base);
b2ea8ef5 7450 POSTING_READ(CURBASE_IVB(pipe));
65a21cd6
JB		 7451}
7452
cda4b7d3 7453/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7454static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7455 bool on)
cda4b7d3
CW		 7456{
7457 struct drm_device *dev = crtc->dev;
7458 struct drm_i915_private *dev_priv = dev->dev_private;
7459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7460 int pipe = intel_crtc->pipe;
7461 int x = intel_crtc->cursor_x;
7462 int y = intel_crtc->cursor_y;
d6e4db15 7463 u32 base = 0, pos = 0;
cda4b7d3
CW		 7464 bool visible;
7465
d6e4db15 7466 if (on)
cda4b7d3 7467 base = intel_crtc->cursor_addr;
cda4b7d3 7468
d6e4db15
VS		 7469 if (x >= intel_crtc->config.pipe_src_w)
7470 base = 0;
7471
7472 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7473 base = 0;
7474
7475 if (x < 0) {
efc9064e 7476 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7477 base = 0;
7478
7479 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7480 x = -x;
7481 }
7482 pos |= x << CURSOR_X_SHIFT;
7483
7484 if (y < 0) {
efc9064e 7485 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7486 base = 0;
7487
7488 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7489 y = -y;
7490 }
7491 pos |= y << CURSOR_Y_SHIFT;
7492
7493 visible = base != 0;
560b85bb 7494 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7495 return;
7496
b3dc685e 7497 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
65a21cd6
JB		 7498 I915_WRITE(CURPOS_IVB(pipe), pos);
7499 ivb_update_cursor(crtc, base);
7500 } else {
7501 I915_WRITE(CURPOS(pipe), pos);
7502 if (IS_845G(dev) || IS_I865G(dev))
7503 i845_update_cursor(crtc, base);
7504 else
7505 i9xx_update_cursor(crtc, base);
7506 }
cda4b7d3
CW		 7507}
7508
79e53945 7509static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7510 struct drm_file *file,
79e53945
JB		 7511 uint32_t handle,
7512 uint32_t width, uint32_t height)
7513{
7514 struct drm_device *dev = crtc->dev;
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7517 struct drm_i915_gem_object *obj;
cda4b7d3 7518 uint32_t addr;
3f8bc370 7519 int ret;
79e53945 7520
79e53945
JB		 7521 /* if we want to turn off the cursor ignore width and height */
7522 if (!handle) {
28c97730 7523 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7524 addr = 0;
05394f39 7525 obj = NULL;
5004417d 7526 mutex_lock(&dev->struct_mutex);
3f8bc370 7527 goto finish;
79e53945
JB		 7528 }
7529
7530 /* Currently we only support 64x64 cursors */
7531 if (width != 64 || height != 64) {
7532 DRM_ERROR("we currently only support 64x64 cursors\n");
7533 return -EINVAL;
7534 }
7535
05394f39 7536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7537 if (&obj->base == NULL)
79e53945
JB		 7538 return -ENOENT;
7539
05394f39 7540 if (obj->base.size < width * height * 4) {
79e53945 7541 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7542 ret = -ENOMEM;
7543 goto fail;
79e53945
JB		 7544 }
7545
71acb5eb 7546 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7547 mutex_lock(&dev->struct_mutex);
b295d1b6 7548 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7549 unsigned alignment;
7550
d9e86c0e
CW		 7551 if (obj->tiling_mode) {
7552 DRM_ERROR("cursor cannot be tiled\n");
7553 ret = -EINVAL;
7554 goto fail_locked;
7555 }
7556
693db184
CW		 7557 /* Note that the w/a also requires 2 PTE of padding following
7558 * the bo. We currently fill all unused PTE with the shadow
7559 * page and so we should always have valid PTE following the
7560 * cursor preventing the VT-d warning.
7561 */
7562 alignment = 0;
7563 if (need_vtd_wa(dev))
7564 alignment = 64*1024;
7565
7566 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7567 if (ret) {
7568 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7569 goto fail_locked;
e7b526bb
CW		 7570 }
7571
d9e86c0e
CW		 7572 ret = i915_gem_object_put_fence(obj);
7573 if (ret) {
2da3b9b9 7574 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7575 goto fail_unpin;
7576 }
7577
f343c5f6 7578 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7579 } else {
6eeefaf3 7580 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7581 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7582 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7583 align);
71acb5eb
DA		 7584 if (ret) {
7585 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7586 goto fail_locked;
71acb5eb 7587 }
05394f39 7588 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7589 }
7590
a6c45cf0 7591 if (IS_GEN2(dev))
14b60391
JB		 7592 I915_WRITE(CURSIZE, (height << 12) | width);
7593
3f8bc370 7594 finish:
3f8bc370 7595 if (intel_crtc->cursor_bo) {
b295d1b6 7596 if (dev_priv->info->cursor_needs_physical) {
05394f39 7597 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7598 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7599 } else
cc98b413 7600 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7601 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7602 }
80824003 7603
7f9872e0 7604 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7605
7606 intel_crtc->cursor_addr = addr;
05394f39 7607 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7608 intel_crtc->cursor_width = width;
7609 intel_crtc->cursor_height = height;
7610
f2f5f771
VS		 7611 if (intel_crtc->active)
7612 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7613
79e53945 7614 return 0;
e7b526bb 7615fail_unpin:
cc98b413 7616 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7617fail_locked:
34b8686e 7618 mutex_unlock(&dev->struct_mutex);
bc9025bd 7619fail:
05394f39 7620 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7621 return ret;
79e53945
JB		 7622}
7623
7624static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7625{
79e53945 7626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7627
92e76c8c
VS		 7628 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7629 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
652c393a 7630
f2f5f771
VS		 7631 if (intel_crtc->active)
7632 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7633
7634 return 0;
b8c00ac5
DA		 7635}
7636
79e53945 7637static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7638 u16 *blue, uint32_t start, uint32_t size)
79e53945 7639{
7203425a 7640 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7642
7203425a 7643 for (i = start; i < end; i++) {
79e53945
JB		 7644 intel_crtc->lut_r[i] = red[i] >> 8;
7645 intel_crtc->lut_g[i] = green[i] >> 8;
7646 intel_crtc->lut_b[i] = blue[i] >> 8;
7647 }
7648
7649 intel_crtc_load_lut(crtc);
7650}
7651
79e53945
JB		 7652/* VESA 640x480x72Hz mode to set on the pipe */
7653static struct drm_display_mode load_detect_mode = {
7654 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7655 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7656};
7657
d2dff872
CW		 7658static struct drm_framebuffer *
7659intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7660 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7661 struct drm_i915_gem_object *obj)
7662{
7663 struct intel_framebuffer *intel_fb;
7664 int ret;
7665
7666 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7667 if (!intel_fb) {
7668 drm_gem_object_unreference_unlocked(&obj->base);
7669 return ERR_PTR(-ENOMEM);
7670 }
7671
dd4916c5
DV		 7672 ret = i915_mutex_lock_interruptible(dev);
7673 if (ret)
7674 goto err;
7675
d2dff872 7676 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 7677 mutex_unlock(&dev->struct_mutex);
7678 if (ret)
7679 goto err;
d2dff872
CW		 7680
7681 return &intel_fb->base;
dd4916c5
DV		 7682err:
7683 drm_gem_object_unreference_unlocked(&obj->base);
7684 kfree(intel_fb);
7685
7686 return ERR_PTR(ret);
d2dff872
CW		 7687}
7688
7689static u32
7690intel_framebuffer_pitch_for_width(int width, int bpp)
7691{
7692 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7693 return ALIGN(pitch, 64);
7694}
7695
7696static u32
7697intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7698{
7699 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7700 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7701}
7702
7703static struct drm_framebuffer *
7704intel_framebuffer_create_for_mode(struct drm_device *dev,
7705 struct drm_display_mode *mode,
7706 int depth, int bpp)
7707{
7708 struct drm_i915_gem_object *obj;
0fed39bd 7709 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7710
7711 obj = i915_gem_alloc_object(dev,
7712 intel_framebuffer_size_for_mode(mode, bpp));
7713 if (obj == NULL)
7714 return ERR_PTR(-ENOMEM);
7715
7716 mode_cmd.width = mode->hdisplay;
7717 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7718 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7719 bpp);
5ca0c34a 7720 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7721
7722 return intel_framebuffer_create(dev, &mode_cmd, obj);
7723}
7724
7725static struct drm_framebuffer *
7726mode_fits_in_fbdev(struct drm_device *dev,
7727 struct drm_display_mode *mode)
7728{
4520f53a 7729#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 7730 struct drm_i915_private *dev_priv = dev->dev_private;
7731 struct drm_i915_gem_object *obj;
7732 struct drm_framebuffer *fb;
7733
7734 if (dev_priv->fbdev == NULL)
7735 return NULL;
7736
7737 obj = dev_priv->fbdev->ifb.obj;
7738 if (obj == NULL)
7739 return NULL;
7740
7741 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7742 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7743 fb->bits_per_pixel))
d2dff872
CW		 7744 return NULL;
7745
01f2c773 7746 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7747 return NULL;
7748
7749 return fb;
4520f53a
DV		 7750#else
7751 return NULL;
7752#endif
d2dff872
CW		 7753}
7754
d2434ab7 7755bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7756 struct drm_display_mode *mode,
8261b191 7757 struct intel_load_detect_pipe *old)
79e53945
JB		 7758{
7759 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7760 struct intel_encoder *intel_encoder =
7761 intel_attached_encoder(connector);
79e53945 7762 struct drm_crtc *possible_crtc;
4ef69c7a 7763 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7764 struct drm_crtc *crtc = NULL;
7765 struct drm_device *dev = encoder->dev;
94352cf9 7766 struct drm_framebuffer *fb;
79e53945
JB		 7767 int i = -1;
7768
d2dff872
CW		 7769 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7770 connector->base.id, drm_get_connector_name(connector),
7771 encoder->base.id, drm_get_encoder_name(encoder));
7772
79e53945
JB		 7773 /*
7774 * Algorithm gets a little messy:
7a5e4805 7775 *
79e53945
JB		 7776 * - if the connector already has an assigned crtc, use it (but make
7777 * sure it's on first)
7a5e4805 7778 *
79e53945
JB		 7779 * - try to find the first unused crtc that can drive this connector,
7780 * and use that if we find one
79e53945
JB		 7781 */
7782
7783 /* See if we already have a CRTC for this connector */
7784 if (encoder->crtc) {
7785 crtc = encoder->crtc;
8261b191 7786
7b24056b
DV		 7787 mutex_lock(&crtc->mutex);
7788
24218aac 7789 old->dpms_mode = connector->dpms;
8261b191
CW		 7790 old->load_detect_temp = false;
7791
7792 /* Make sure the crtc and connector are running */
24218aac
DV		 7793 if (connector->dpms != DRM_MODE_DPMS_ON)
7794 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7795
7173188d 7796 return true;
79e53945
JB		 7797 }
7798
7799 /* Find an unused one (if possible) */
7800 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7801 i++;
7802 if (!(encoder->possible_crtcs & (1 << i)))
7803 continue;
7804 if (!possible_crtc->enabled) {
7805 crtc = possible_crtc;
7806 break;
7807 }
79e53945
JB		 7808 }
7809
7810 /*
7811 * If we didn't find an unused CRTC, don't use any.
7812 */
7813 if (!crtc) {
7173188d
CW		 7814 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7815 return false;
79e53945
JB		 7816 }
7817
7b24056b 7818 mutex_lock(&crtc->mutex);
fc303101
DV		 7819 intel_encoder->new_crtc = to_intel_crtc(crtc);
7820 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7821
7822 intel_crtc = to_intel_crtc(crtc);
24218aac 7823 old->dpms_mode = connector->dpms;
8261b191 7824 old->load_detect_temp = true;
d2dff872 7825 old->release_fb = NULL;
79e53945 7826
6492711d
CW		 7827 if (!mode)
7828 mode = &load_detect_mode;
79e53945 7829
d2dff872
CW		 7830 /* We need a framebuffer large enough to accommodate all accesses
7831 * that the plane may generate whilst we perform load detection.
7832 * We can not rely on the fbcon either being present (we get called
7833 * during its initialisation to detect all boot displays, or it may
7834 * not even exist) or that it is large enough to satisfy the
7835 * requested mode.
7836 */
94352cf9
DV		 7837 fb = mode_fits_in_fbdev(dev, mode);
7838 if (fb == NULL) {
d2dff872 7839 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7840 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7841 old->release_fb = fb;
d2dff872
CW		 7842 } else
7843 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7844 if (IS_ERR(fb)) {
d2dff872 7845 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7846 mutex_unlock(&crtc->mutex);
0e8b3d3e 7847 return false;
79e53945 7848 }
79e53945 7849
c0c36b94 7850 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7851 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7852 if (old->release_fb)
7853 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7854 mutex_unlock(&crtc->mutex);
0e8b3d3e 7855 return false;
79e53945 7856 }
7173188d 7857
79e53945 7858 /* let the connector get through one full cycle before testing */
9d0498a2 7859 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7860 return true;
79e53945
JB		 7861}
7862
d2434ab7 7863void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7864 struct intel_load_detect_pipe *old)
79e53945 7865{
d2434ab7
DV		 7866 struct intel_encoder *intel_encoder =
7867 intel_attached_encoder(connector);
4ef69c7a 7868 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7869 struct drm_crtc *crtc = encoder->crtc;
79e53945 7870
d2dff872
CW		 7871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7872 connector->base.id, drm_get_connector_name(connector),
7873 encoder->base.id, drm_get_encoder_name(encoder));
7874
8261b191 7875 if (old->load_detect_temp) {
fc303101
DV		 7876 to_intel_connector(connector)->new_encoder = NULL;
7877 intel_encoder->new_crtc = NULL;
7878 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7879
36206361
DV		 7880 if (old->release_fb) {
7881 drm_framebuffer_unregister_private(old->release_fb);
7882 drm_framebuffer_unreference(old->release_fb);
7883 }
d2dff872 7884
67c96400 7885 mutex_unlock(&crtc->mutex);
0622a53c 7886 return;
79e53945
JB		 7887 }
7888
c751ce4f 7889 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7890 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7891 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7892
7893 mutex_unlock(&crtc->mutex);
79e53945
JB		 7894}
7895
da4a1efa
VS		 7896static int i9xx_pll_refclk(struct drm_device *dev,
7897 const struct intel_crtc_config *pipe_config)
7898{
7899 struct drm_i915_private *dev_priv = dev->dev_private;
7900 u32 dpll = pipe_config->dpll_hw_state.dpll;
7901
7902 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 7903 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 7904 else if (HAS_PCH_SPLIT(dev))
7905 return 120000;
7906 else if (!IS_GEN2(dev))
7907 return 96000;
7908 else
7909 return 48000;
7910}
7911
79e53945 7912/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7913static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7914 struct intel_crtc_config *pipe_config)
79e53945 7915{
f1f644dc 7916 struct drm_device *dev = crtc->base.dev;
79e53945 7917 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7918 int pipe = pipe_config->cpu_transcoder;
293623f7 7919 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7920 u32 fp;
7921 intel_clock_t clock;
da4a1efa 7922 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7923
7924 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7925 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7926 else
293623f7 7927 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7928
7929 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7930 if (IS_PINEVIEW(dev)) {
7931 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7932 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7933 } else {
7934 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7935 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7936 }
7937
a6c45cf0 7938 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7939 if (IS_PINEVIEW(dev))
7940 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7941 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7942 else
7943 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7944 DPLL_FPA01_P1_POST_DIV_SHIFT);
7945
7946 switch (dpll & DPLL_MODE_MASK) {
7947 case DPLLB_MODE_DAC_SERIAL:
7948 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7949 5 : 10;
7950 break;
7951 case DPLLB_MODE_LVDS:
7952 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7953 7 : 14;
7954 break;
7955 default:
28c97730 7956 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7957 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7958 return;
79e53945
JB		 7959 }
7960
ac58c3f0 7961 if (IS_PINEVIEW(dev))
da4a1efa 7962 pineview_clock(refclk, &clock);
ac58c3f0 7963 else
da4a1efa 7964 i9xx_clock(refclk, &clock);
79e53945 7965 } else {
b1c560d1
VS		 7966 u32 lvds = I915_READ(LVDS);
7967 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 7968
7969 if (is_lvds) {
7970 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7971 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 7972
7973 if (lvds & LVDS_CLKB_POWER_UP)
7974 clock.p2 = 7;
7975 else
7976 clock.p2 = 14;
79e53945
JB		 7977 } else {
7978 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7979 clock.p1 = 2;
7980 else {
7981 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7982 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7983 }
7984 if (dpll & PLL_P2_DIVIDE_BY_4)
7985 clock.p2 = 4;
7986 else
7987 clock.p2 = 2;
79e53945 7988 }
da4a1efa
VS		 7989
7990 i9xx_clock(refclk, &clock);
79e53945
JB		 7991 }
7992
18442d08
VS		 7993 /*
7994 * This value includes pixel_multiplier. We will use
241bfc38 7995 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7996 * encoder's get_config() function.
7997 */
7998 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7999}
8000
6878da05
VS		 8001int intel_dotclock_calculate(int link_freq,
8002 const struct intel_link_m_n *m_n)
f1f644dc 8003{
f1f644dc
JB		 8004 /*
8005 * The calculation for the data clock is:
1041a02f 8006 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 8007 * But we want to avoid losing precison if possible, so:
1041a02f 8008 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 8009 *
8010 * and the link clock is simpler:
1041a02f 8011 * link_clock = (m * link_clock) / n
f1f644dc
JB		 8012 */
8013
6878da05
VS		 8014 if (!m_n->link_n)
8015 return 0;
f1f644dc 8016
6878da05
VS		 8017 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8018}
f1f644dc 8019
18442d08
VS		 8020static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8021 struct intel_crtc_config *pipe_config)
6878da05
VS		 8022{
8023 struct drm_device *dev = crtc->base.dev;
79e53945 8024
18442d08
VS		 8025 /* read out port_clock from the DPLL */
8026 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 8027
f1f644dc 8028 /*
18442d08 8029 * This value does not include pixel_multiplier.
241bfc38 8030 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 8031 * agree once we know their relationship in the encoder's
8032 * get_config() function.
79e53945 8033 */
241bfc38 8034 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 8035 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8036 &pipe_config->fdi_m_n);
79e53945
JB		 8037}
8038
8039/** Returns the currently programmed mode of the given pipe. */
8040struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8041 struct drm_crtc *crtc)
8042{
548f245b 8043 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 8044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 8045 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 8046 struct drm_display_mode *mode;
f1f644dc 8047 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 8048 int htot = I915_READ(HTOTAL(cpu_transcoder));
8049 int hsync = I915_READ(HSYNC(cpu_transcoder));
8050 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8051 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 8052 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 8053
8054 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8055 if (!mode)
8056 return NULL;
8057
f1f644dc
JB		 8058 /*
8059 * Construct a pipe_config sufficient for getting the clock info
8060 * back out of crtc_clock_get.
8061 *
8062 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8063 * to use a real value here instead.
8064 */
293623f7 8065 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 8066 pipe_config.pixel_multiplier = 1;
293623f7
VS		 8067 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8068 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8069 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 8070 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8071
773ae034 8072 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 8073 mode->hdisplay = (htot & 0xffff) + 1;
8074 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8075 mode->hsync_start = (hsync & 0xffff) + 1;
8076 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8077 mode->vdisplay = (vtot & 0xffff) + 1;
8078 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8079 mode->vsync_start = (vsync & 0xffff) + 1;
8080 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8081
8082 drm_mode_set_name(mode);
79e53945
JB		 8083
8084 return mode;
8085}
8086
3dec0095 8087static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 8088{
8089 struct drm_device *dev = crtc->dev;
8090 drm_i915_private_t *dev_priv = dev->dev_private;
8091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8092 int pipe = intel_crtc->pipe;
dbdc6479
JB		 8093 int dpll_reg = DPLL(pipe);
8094 int dpll;
652c393a 8095
bad720ff 8096 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 8097 return;
8098
8099 if (!dev_priv->lvds_downclock_avail)
8100 return;
8101
dbdc6479 8102 dpll = I915_READ(dpll_reg);
652c393a 8103 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 8104 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 8105
8ac5a6d5 8106 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 8107
8108 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8109 I915_WRITE(dpll_reg, dpll);
9d0498a2 8110 intel_wait_for_vblank(dev, pipe);
dbdc6479 8111
652c393a
JB		 8112 dpll = I915_READ(dpll_reg);
8113 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 8114 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 8115 }
652c393a
JB		 8116}
8117
8118static void intel_decrease_pllclock(struct drm_crtc *crtc)
8119{
8120 struct drm_device *dev = crtc->dev;
8121 drm_i915_private_t *dev_priv = dev->dev_private;
8122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 8123
bad720ff 8124 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 8125 return;
8126
8127 if (!dev_priv->lvds_downclock_avail)
8128 return;
8129
8130 /*
8131 * Since this is called by a timer, we should never get here in
8132 * the manual case.
8133 */
8134 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 8135 int pipe = intel_crtc->pipe;
8136 int dpll_reg = DPLL(pipe);
8137 int dpll;
f6e5b160 8138
44d98a61 8139 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 8140
8ac5a6d5 8141 assert_panel_unlocked(dev_priv, pipe);
652c393a 8142
dc257cf1 8143 dpll = I915_READ(dpll_reg);
652c393a
JB		 8144 dpll |= DISPLAY_RATE_SELECT_FPA1;
8145 I915_WRITE(dpll_reg, dpll);
9d0498a2 8146 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 8147 dpll = I915_READ(dpll_reg);
8148 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 8149 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 8150 }
8151
8152}
8153
f047e395
CW		 8154void intel_mark_busy(struct drm_device *dev)
8155{
c67a470b
PZ		 8156 struct drm_i915_private *dev_priv = dev->dev_private;
8157
8158 hsw_package_c8_gpu_busy(dev_priv);
8159 i915_update_gfx_val(dev_priv);
f047e395
CW		 8160}
8161
8162void intel_mark_idle(struct drm_device *dev)
652c393a 8163{
c67a470b 8164 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8165 struct drm_crtc *crtc;
652c393a 8166
c67a470b
PZ		 8167 hsw_package_c8_gpu_idle(dev_priv);
8168
652c393a
JB		 8169 if (!i915_powersave)
8170 return;
8171
652c393a 8172 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 8173 if (!crtc->fb)
8174 continue;
8175
725a5b54 8176 intel_decrease_pllclock(crtc);
652c393a 8177 }
b29c19b6
CW		 8178
8179 if (dev_priv->info->gen >= 6)
8180 gen6_rps_idle(dev->dev_private);
652c393a
JB		 8181}
8182
c65355bb
CW		 8183void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8184 struct intel_ring_buffer *ring)
652c393a 8185{
f047e395
CW		 8186 struct drm_device *dev = obj->base.dev;
8187 struct drm_crtc *crtc;
652c393a 8188
f047e395 8189 if (!i915_powersave)
acb87dfb
CW		 8190 return;
8191
652c393a
JB		 8192 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8193 if (!crtc->fb)
8194 continue;
8195
c65355bb
CW		 8196 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8197 continue;
8198
8199 intel_increase_pllclock(crtc);
8200 if (ring && intel_fbc_enabled(dev))
8201 ring->fbc_dirty = true;
652c393a
JB		 8202 }
8203}
8204
79e53945
JB		 8205static void intel_crtc_destroy(struct drm_crtc *crtc)
8206{
8207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 8208 struct drm_device *dev = crtc->dev;
8209 struct intel_unpin_work *work;
8210 unsigned long flags;
8211
8212 spin_lock_irqsave(&dev->event_lock, flags);
8213 work = intel_crtc->unpin_work;
8214 intel_crtc->unpin_work = NULL;
8215 spin_unlock_irqrestore(&dev->event_lock, flags);
8216
8217 if (work) {
8218 cancel_work_sync(&work->work);
8219 kfree(work);
8220 }
79e53945 8221
40ccc72b
MK		 8222 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8223
79e53945 8224 drm_crtc_cleanup(crtc);
67e77c5a 8225
79e53945
JB		 8226 kfree(intel_crtc);
8227}
8228
6b95a207
KH		 8229static void intel_unpin_work_fn(struct work_struct *__work)
8230{
8231 struct intel_unpin_work *work =
8232 container_of(__work, struct intel_unpin_work, work);
b4a98e57 8233 struct drm_device *dev = work->crtc->dev;
6b95a207 8234
b4a98e57 8235 mutex_lock(&dev->struct_mutex);
1690e1eb 8236 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 8237 drm_gem_object_unreference(&work->pending_flip_obj->base);
8238 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 8239
b4a98e57
CW		 8240 intel_update_fbc(dev);
8241 mutex_unlock(&dev->struct_mutex);
8242
8243 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8244 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8245
6b95a207
KH		 8246 kfree(work);
8247}
8248
1afe3e9d 8249static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 8250 struct drm_crtc *crtc)
6b95a207
KH		 8251{
8252 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 8253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8254 struct intel_unpin_work *work;
6b95a207
KH		 8255 unsigned long flags;
8256
8257 /* Ignore early vblank irqs */
8258 if (intel_crtc == NULL)
8259 return;
8260
8261 spin_lock_irqsave(&dev->event_lock, flags);
8262 work = intel_crtc->unpin_work;
e7d841ca
CW		 8263
8264 /* Ensure we don't miss a work->pending update ... */
8265 smp_rmb();
8266
8267 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 8268 spin_unlock_irqrestore(&dev->event_lock, flags);
8269 return;
8270 }
8271
e7d841ca
CW		 8272 /* and that the unpin work is consistent wrt ->pending. */
8273 smp_rmb();
8274
6b95a207 8275 intel_crtc->unpin_work = NULL;
6b95a207 8276
45a066eb
RC		 8277 if (work->event)
8278 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 8279
0af7e4df
MK		 8280 drm_vblank_put(dev, intel_crtc->pipe);
8281
6b95a207
KH		 8282 spin_unlock_irqrestore(&dev->event_lock, flags);
8283
2c10d571 8284 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 8285
8286 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 8287
8288 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 8289}
8290
1afe3e9d
JB		 8291void intel_finish_page_flip(struct drm_device *dev, int pipe)
8292{
8293 drm_i915_private_t *dev_priv = dev->dev_private;
8294 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8295
49b14a5c 8296 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 8297}
8298
8299void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8300{
8301 drm_i915_private_t *dev_priv = dev->dev_private;
8302 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8303
49b14a5c 8304 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 8305}
8306
6b95a207
KH		 8307void intel_prepare_page_flip(struct drm_device *dev, int plane)
8308{
8309 drm_i915_private_t *dev_priv = dev->dev_private;
8310 struct intel_crtc *intel_crtc =
8311 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8312 unsigned long flags;
8313
e7d841ca
CW		 8314 /* NB: An MMIO update of the plane base pointer will also
8315 * generate a page-flip completion irq, i.e. every modeset
8316 * is also accompanied by a spurious intel_prepare_page_flip().
8317 */
6b95a207 8318 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 8319 if (intel_crtc->unpin_work)
8320 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 8321 spin_unlock_irqrestore(&dev->event_lock, flags);
8322}
8323
e7d841ca
CW		 8324inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8325{
8326 /* Ensure that the work item is consistent when activating it ... */
8327 smp_wmb();
8328 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8329 /* and that it is marked active as soon as the irq could fire. */
8330 smp_wmb();
8331}
8332
8c9f3aaf
JB		 8333static int intel_gen2_queue_flip(struct drm_device *dev,
8334 struct drm_crtc *crtc,
8335 struct drm_framebuffer *fb,
ed8d1975
KP		 8336 struct drm_i915_gem_object *obj,
8337 uint32_t flags)
8c9f3aaf
JB		 8338{
8339 struct drm_i915_private *dev_priv = dev->dev_private;
8340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 8341 u32 flip_mask;
6d90c952 8342 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8343 int ret;
8344
6d90c952 8345 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8346 if (ret)
83d4092b 8347 goto err;
8c9f3aaf 8348
6d90c952 8349 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8350 if (ret)
83d4092b 8351 goto err_unpin;
8c9f3aaf
JB		 8352
8353 /* Can't queue multiple flips, so wait for the previous
8354 * one to finish before executing the next.
8355 */
8356 if (intel_crtc->plane)
8357 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8358 else
8359 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8360 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8361 intel_ring_emit(ring, MI_NOOP);
8362 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8363 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8364 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8365 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 8366 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 8367
8368 intel_mark_page_flip_active(intel_crtc);
09246732 8369 __intel_ring_advance(ring);
83d4092b
CW		 8370 return 0;
8371
8372err_unpin:
8373 intel_unpin_fb_obj(obj);
8374err:
8c9f3aaf
JB		 8375 return ret;
8376}
8377
8378static int intel_gen3_queue_flip(struct drm_device *dev,
8379 struct drm_crtc *crtc,
8380 struct drm_framebuffer *fb,
ed8d1975
KP		 8381 struct drm_i915_gem_object *obj,
8382 uint32_t flags)
8c9f3aaf
JB		 8383{
8384 struct drm_i915_private *dev_priv = dev->dev_private;
8385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 8386 u32 flip_mask;
6d90c952 8387 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8388 int ret;
8389
6d90c952 8390 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8391 if (ret)
83d4092b 8392 goto err;
8c9f3aaf 8393
6d90c952 8394 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8395 if (ret)
83d4092b 8396 goto err_unpin;
8c9f3aaf
JB		 8397
8398 if (intel_crtc->plane)
8399 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8400 else
8401 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8402 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8403 intel_ring_emit(ring, MI_NOOP);
8404 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8405 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8406 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8407 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 8408 intel_ring_emit(ring, MI_NOOP);
8409
e7d841ca 8410 intel_mark_page_flip_active(intel_crtc);
09246732 8411 __intel_ring_advance(ring);
83d4092b
CW		 8412 return 0;
8413
8414err_unpin:
8415 intel_unpin_fb_obj(obj);
8416err:
8c9f3aaf
JB		 8417 return ret;
8418}
8419
8420static int intel_gen4_queue_flip(struct drm_device *dev,
8421 struct drm_crtc *crtc,
8422 struct drm_framebuffer *fb,
ed8d1975
KP		 8423 struct drm_i915_gem_object *obj,
8424 uint32_t flags)
8c9f3aaf
JB		 8425{
8426 struct drm_i915_private *dev_priv = dev->dev_private;
8427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8428 uint32_t pf, pipesrc;
6d90c952 8429 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8430 int ret;
8431
6d90c952 8432 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8433 if (ret)
83d4092b 8434 goto err;
8c9f3aaf 8435
6d90c952 8436 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8437 if (ret)
83d4092b 8438 goto err_unpin;
8c9f3aaf
JB		 8439
8440 /* i965+ uses the linear or tiled offsets from the
8441 * Display Registers (which do not change across a page-flip)
8442 * so we need only reprogram the base address.
8443 */
6d90c952
DV		 8444 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8445 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8446 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8447 intel_ring_emit(ring,
f343c5f6 8448 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8449 obj->tiling_mode);
8c9f3aaf
JB		 8450
8451 /* XXX Enabling the panel-fitter across page-flip is so far
8452 * untested on non-native modes, so ignore it for now.
8453 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8454 */
8455 pf = 0;
8456 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8457 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8458
8459 intel_mark_page_flip_active(intel_crtc);
09246732 8460 __intel_ring_advance(ring);
83d4092b
CW		 8461 return 0;
8462
8463err_unpin:
8464 intel_unpin_fb_obj(obj);
8465err:
8c9f3aaf
JB		 8466 return ret;
8467}
8468
8469static int intel_gen6_queue_flip(struct drm_device *dev,
8470 struct drm_crtc *crtc,
8471 struct drm_framebuffer *fb,
ed8d1975
KP		 8472 struct drm_i915_gem_object *obj,
8473 uint32_t flags)
8c9f3aaf
JB		 8474{
8475 struct drm_i915_private *dev_priv = dev->dev_private;
8476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8477 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8478 uint32_t pf, pipesrc;
8479 int ret;
8480
6d90c952 8481 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8482 if (ret)
83d4092b 8483 goto err;
8c9f3aaf 8484
6d90c952 8485 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8486 if (ret)
83d4092b 8487 goto err_unpin;
8c9f3aaf 8488
6d90c952
DV		 8489 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8490 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8491 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8492 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8493
dc257cf1
DV		 8494 /* Contrary to the suggestions in the documentation,
8495 * "Enable Panel Fitter" does not seem to be required when page
8496 * flipping with a non-native mode, and worse causes a normal
8497 * modeset to fail.
8498 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8499 */
8500 pf = 0;
8c9f3aaf 8501 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8502 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8503
8504 intel_mark_page_flip_active(intel_crtc);
09246732 8505 __intel_ring_advance(ring);
83d4092b
CW		 8506 return 0;
8507
8508err_unpin:
8509 intel_unpin_fb_obj(obj);
8510err:
8c9f3aaf
JB		 8511 return ret;
8512}
8513
7c9017e5
JB		 8514static int intel_gen7_queue_flip(struct drm_device *dev,
8515 struct drm_crtc *crtc,
8516 struct drm_framebuffer *fb,
ed8d1975
KP		 8517 struct drm_i915_gem_object *obj,
8518 uint32_t flags)
7c9017e5
JB		 8519{
8520 struct drm_i915_private *dev_priv = dev->dev_private;
8521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8522 struct intel_ring_buffer *ring;
cb05d8de 8523 uint32_t plane_bit = 0;
ffe74d75
CW		 8524 int len, ret;
8525
8526 ring = obj->ring;
1c5fd085 8527 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8528 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8529
8530 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8531 if (ret)
83d4092b 8532 goto err;
7c9017e5 8533
cb05d8de
DV		 8534 switch(intel_crtc->plane) {
8535 case PLANE_A:
8536 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8537 break;
8538 case PLANE_B:
8539 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8540 break;
8541 case PLANE_C:
8542 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8543 break;
8544 default:
8545 WARN_ONCE(1, "unknown plane in flip command\n");
8546 ret = -ENODEV;
ab3951eb 8547 goto err_unpin;
cb05d8de
DV		 8548 }
8549
ffe74d75
CW		 8550 len = 4;
8551 if (ring->id == RCS)
8552 len += 6;
8553
8554 ret = intel_ring_begin(ring, len);
7c9017e5 8555 if (ret)
83d4092b 8556 goto err_unpin;
7c9017e5 8557
ffe74d75
CW		 8558 /* Unmask the flip-done completion message. Note that the bspec says that
8559 * we should do this for both the BCS and RCS, and that we must not unmask
8560 * more than one flip event at any time (or ensure that one flip message
8561 * can be sent by waiting for flip-done prior to queueing new flips).
8562 * Experimentation says that BCS works despite DERRMR masking all
8563 * flip-done completion events and that unmasking all planes at once
8564 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8565 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8566 */
8567 if (ring->id == RCS) {
8568 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8569 intel_ring_emit(ring, DERRMR);
8570 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8571 DERRMR_PIPEB_PRI_FLIP_DONE |
8572 DERRMR_PIPEC_PRI_FLIP_DONE));
8573 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8574 intel_ring_emit(ring, DERRMR);
8575 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8576 }
8577
cb05d8de 8578 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8579 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8580 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8581 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8582
8583 intel_mark_page_flip_active(intel_crtc);
09246732 8584 __intel_ring_advance(ring);
83d4092b
CW		 8585 return 0;
8586
8587err_unpin:
8588 intel_unpin_fb_obj(obj);
8589err:
7c9017e5
JB		 8590 return ret;
8591}
8592
8c9f3aaf
JB		 8593static int intel_default_queue_flip(struct drm_device *dev,
8594 struct drm_crtc *crtc,
8595 struct drm_framebuffer *fb,
ed8d1975
KP		 8596 struct drm_i915_gem_object *obj,
8597 uint32_t flags)
8c9f3aaf
JB		 8598{
8599 return -ENODEV;
8600}
8601
6b95a207
KH		 8602static int intel_crtc_page_flip(struct drm_crtc *crtc,
8603 struct drm_framebuffer *fb,
ed8d1975
KP		 8604 struct drm_pending_vblank_event *event,
8605 uint32_t page_flip_flags)
6b95a207
KH		 8606{
8607 struct drm_device *dev = crtc->dev;
8608 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8609 struct drm_framebuffer *old_fb = crtc->fb;
8610 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8612 struct intel_unpin_work *work;
8c9f3aaf 8613 unsigned long flags;
52e68630 8614 int ret;
6b95a207 8615
e6a595d2
VS		 8616 /* Can't change pixel format via MI display flips. */
8617 if (fb->pixel_format != crtc->fb->pixel_format)
8618 return -EINVAL;
8619
8620 /*
8621 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8622 * Note that pitch changes could also affect these register.
8623 */
8624 if (INTEL_INFO(dev)->gen > 3 &&
8625 (fb->offsets[0] != crtc->fb->offsets[0] ||
8626 fb->pitches[0] != crtc->fb->pitches[0]))
8627 return -EINVAL;
8628
b14c5679 8629 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8630 if (work == NULL)
8631 return -ENOMEM;
8632
6b95a207 8633 work->event = event;
b4a98e57 8634 work->crtc = crtc;
4a35f83b 8635 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8636 INIT_WORK(&work->work, intel_unpin_work_fn);
8637
7317c75e
JB		 8638 ret = drm_vblank_get(dev, intel_crtc->pipe);
8639 if (ret)
8640 goto free_work;
8641
6b95a207
KH		 8642 /* We borrow the event spin lock for protecting unpin_work */
8643 spin_lock_irqsave(&dev->event_lock, flags);
8644 if (intel_crtc->unpin_work) {
8645 spin_unlock_irqrestore(&dev->event_lock, flags);
8646 kfree(work);
7317c75e 8647 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8648
8649 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8650 return -EBUSY;
8651 }
8652 intel_crtc->unpin_work = work;
8653 spin_unlock_irqrestore(&dev->event_lock, flags);
8654
b4a98e57
CW		 8655 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8656 flush_workqueue(dev_priv->wq);
8657
79158103
CW		 8658 ret = i915_mutex_lock_interruptible(dev);
8659 if (ret)
8660 goto cleanup;
6b95a207 8661
75dfca80 8662 /* Reference the objects for the scheduled work. */
05394f39
CW		 8663 drm_gem_object_reference(&work->old_fb_obj->base);
8664 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8665
8666 crtc->fb = fb;
96b099fd 8667
e1f99ce6 8668 work->pending_flip_obj = obj;
e1f99ce6 8669
4e5359cd
SF		 8670 work->enable_stall_check = true;
8671
b4a98e57 8672 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8673 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8674
ed8d1975 8675 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8676 if (ret)
8677 goto cleanup_pending;
6b95a207 8678
7782de3b 8679 intel_disable_fbc(dev);
c65355bb 8680 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8681 mutex_unlock(&dev->struct_mutex);
8682
e5510fac
JB		 8683 trace_i915_flip_request(intel_crtc->plane, obj);
8684
6b95a207 8685 return 0;
96b099fd 8686
8c9f3aaf 8687cleanup_pending:
b4a98e57 8688 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8689 crtc->fb = old_fb;
05394f39
CW		 8690 drm_gem_object_unreference(&work->old_fb_obj->base);
8691 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8692 mutex_unlock(&dev->struct_mutex);
8693
79158103 8694cleanup:
96b099fd
CW		 8695 spin_lock_irqsave(&dev->event_lock, flags);
8696 intel_crtc->unpin_work = NULL;
8697 spin_unlock_irqrestore(&dev->event_lock, flags);
8698
7317c75e
JB		 8699 drm_vblank_put(dev, intel_crtc->pipe);
8700free_work:
96b099fd
CW		 8701 kfree(work);
8702
8703 return ret;
6b95a207
KH		 8704}
8705
f6e5b160 8706static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8707 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8708 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8709};
8710
50f56119
DV		 8711static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8712 struct drm_crtc *crtc)
8713{
8714 struct drm_device *dev;
8715 struct drm_crtc *tmp;
8716 int crtc_mask = 1;
47f1c6c9 8717
50f56119 8718 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8719
50f56119 8720 dev = crtc->dev;
47f1c6c9 8721
50f56119
DV		 8722 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8723 if (tmp == crtc)
8724 break;
8725 crtc_mask <<= 1;
8726 }
47f1c6c9 8727
50f56119
DV		 8728 if (encoder->possible_crtcs & crtc_mask)
8729 return true;
8730 return false;
47f1c6c9 8731}
79e53945 8732
9a935856
DV		 8733/**
8734 * intel_modeset_update_staged_output_state
8735 *
8736 * Updates the staged output configuration state, e.g. after we've read out the
8737 * current hw state.
8738 */
8739static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8740{
9a935856
DV		 8741 struct intel_encoder *encoder;
8742 struct intel_connector *connector;
f6e5b160 8743
9a935856
DV		 8744 list_for_each_entry(connector, &dev->mode_config.connector_list,
8745 base.head) {
8746 connector->new_encoder =
8747 to_intel_encoder(connector->base.encoder);
8748 }
f6e5b160 8749
9a935856
DV		 8750 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8751 base.head) {
8752 encoder->new_crtc =
8753 to_intel_crtc(encoder->base.crtc);
8754 }
f6e5b160
CW		 8755}
8756
9a935856
DV		 8757/**
8758 * intel_modeset_commit_output_state
8759 *
8760 * This function copies the stage display pipe configuration to the real one.
8761 */
8762static void intel_modeset_commit_output_state(struct drm_device *dev)
8763{
8764 struct intel_encoder *encoder;
8765 struct intel_connector *connector;
f6e5b160 8766
9a935856
DV		 8767 list_for_each_entry(connector, &dev->mode_config.connector_list,
8768 base.head) {
8769 connector->base.encoder = &connector->new_encoder->base;
8770 }
f6e5b160 8771
9a935856
DV		 8772 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8773 base.head) {
8774 encoder->base.crtc = &encoder->new_crtc->base;
8775 }
8776}
8777
050f7aeb
DV		 8778static void
8779connected_sink_compute_bpp(struct intel_connector * connector,
8780 struct intel_crtc_config *pipe_config)
8781{
8782 int bpp = pipe_config->pipe_bpp;
8783
8784 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8785 connector->base.base.id,
8786 drm_get_connector_name(&connector->base));
8787
8788 /* Don't use an invalid EDID bpc value */
8789 if (connector->base.display_info.bpc &&
8790 connector->base.display_info.bpc * 3 < bpp) {
8791 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8792 bpp, connector->base.display_info.bpc*3);
8793 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8794 }
8795
8796 /* Clamp bpp to 8 on screens without EDID 1.4 */
8797 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8798 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8799 bpp);
8800 pipe_config->pipe_bpp = 24;
8801 }
8802}
8803
4e53c2e0 8804static int
050f7aeb
DV		 8805compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8806 struct drm_framebuffer *fb,
8807 struct intel_crtc_config *pipe_config)
4e53c2e0 8808{
050f7aeb
DV		 8809 struct drm_device *dev = crtc->base.dev;
8810 struct intel_connector *connector;
4e53c2e0
DV		 8811 int bpp;
8812
d42264b1
DV		 8813 switch (fb->pixel_format) {
8814 case DRM_FORMAT_C8:
4e53c2e0
DV		 8815 bpp = 8*3; /* since we go through a colormap */
8816 break;
d42264b1
DV		 8817 case DRM_FORMAT_XRGB1555:
8818 case DRM_FORMAT_ARGB1555:
8819 /* checked in intel_framebuffer_init already */
8820 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8821 return -EINVAL;
8822 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8823 bpp = 6*3; /* min is 18bpp */
8824 break;
d42264b1
DV		 8825 case DRM_FORMAT_XBGR8888:
8826 case DRM_FORMAT_ABGR8888:
8827 /* checked in intel_framebuffer_init already */
8828 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8829 return -EINVAL;
8830 case DRM_FORMAT_XRGB8888:
8831 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8832 bpp = 8*3;
8833 break;
d42264b1
DV		 8834 case DRM_FORMAT_XRGB2101010:
8835 case DRM_FORMAT_ARGB2101010:
8836 case DRM_FORMAT_XBGR2101010:
8837 case DRM_FORMAT_ABGR2101010:
8838 /* checked in intel_framebuffer_init already */
8839 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8840 return -EINVAL;
4e53c2e0
DV		 8841 bpp = 10*3;
8842 break;
baba133a 8843 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8844 default:
8845 DRM_DEBUG_KMS("unsupported depth\n");
8846 return -EINVAL;
8847 }
8848
4e53c2e0
DV		 8849 pipe_config->pipe_bpp = bpp;
8850
8851 /* Clamp display bpp to EDID value */
8852 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8853 base.head) {
1b829e05
DV		 8854 if (!connector->new_encoder ||
8855 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8856 continue;
8857
050f7aeb 8858 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8859 }
8860
8861 return bpp;
8862}
8863
644db711
DV		 8864static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8865{
8866 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8867 "type: 0x%x flags: 0x%x\n",
1342830c 8868 mode->crtc_clock,
644db711
DV		 8869 mode->crtc_hdisplay, mode->crtc_hsync_start,
8870 mode->crtc_hsync_end, mode->crtc_htotal,
8871 mode->crtc_vdisplay, mode->crtc_vsync_start,
8872 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8873}
8874
c0b03411
DV		 8875static void intel_dump_pipe_config(struct intel_crtc *crtc,
8876 struct intel_crtc_config *pipe_config,
8877 const char *context)
8878{
8879 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8880 context, pipe_name(crtc->pipe));
8881
8882 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8883 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8884 pipe_config->pipe_bpp, pipe_config->dither);
8885 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8886 pipe_config->has_pch_encoder,
8887 pipe_config->fdi_lanes,
8888 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8889 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8890 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8891 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8892 pipe_config->has_dp_encoder,
8893 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8894 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8895 pipe_config->dp_m_n.tu);
c0b03411
DV		 8896 DRM_DEBUG_KMS("requested mode:\n");
8897 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8898 DRM_DEBUG_KMS("adjusted mode:\n");
8899 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8900 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8901 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8902 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8903 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8904 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8905 pipe_config->gmch_pfit.control,
8906 pipe_config->gmch_pfit.pgm_ratios,
8907 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8908 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8909 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8910 pipe_config->pch_pfit.size,
8911 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8912 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8913 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8914}
8915
accfc0c5
DV		 8916static bool check_encoder_cloning(struct drm_crtc *crtc)
8917{
8918 int num_encoders = 0;
8919 bool uncloneable_encoders = false;
8920 struct intel_encoder *encoder;
8921
8922 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8923 base.head) {
8924 if (&encoder->new_crtc->base != crtc)
8925 continue;
8926
8927 num_encoders++;
8928 if (!encoder->cloneable)
8929 uncloneable_encoders = true;
8930 }
8931
8932 return !(num_encoders > 1 && uncloneable_encoders);
8933}
8934
b8cecdf5
DV		 8935static struct intel_crtc_config *
8936intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8937 struct drm_framebuffer *fb,
b8cecdf5 8938 struct drm_display_mode *mode)
ee7b9f93 8939{
7758a113 8940 struct drm_device *dev = crtc->dev;
7758a113 8941 struct intel_encoder *encoder;
b8cecdf5 8942 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8943 int plane_bpp, ret = -EINVAL;
8944 bool retry = true;
ee7b9f93 8945
accfc0c5
DV		 8946 if (!check_encoder_cloning(crtc)) {
8947 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8948 return ERR_PTR(-EINVAL);
8949 }
8950
b8cecdf5
DV		 8951 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8952 if (!pipe_config)
7758a113
DV		 8953 return ERR_PTR(-ENOMEM);
8954
b8cecdf5
DV		 8955 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8956 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8957
e143a21c
DV		 8958 pipe_config->cpu_transcoder =
8959 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8960 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8961
2960bc9c
ID		 8962 /*
8963 * Sanitize sync polarity flags based on requested ones. If neither
8964 * positive or negative polarity is requested, treat this as meaning
8965 * negative polarity.
8966 */
8967 if (!(pipe_config->adjusted_mode.flags &
8968 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8969 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8970
8971 if (!(pipe_config->adjusted_mode.flags &
8972 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8973 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8974
050f7aeb
DV		 8975 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8976 * plane pixel format and any sink constraints into account. Returns the
8977 * source plane bpp so that dithering can be selected on mismatches
8978 * after encoders and crtc also have had their say. */
8979 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8980 fb, pipe_config);
4e53c2e0
DV		 8981 if (plane_bpp < 0)
8982 goto fail;
8983
e41a56be
VS		 8984 /*
8985 * Determine the real pipe dimensions. Note that stereo modes can
8986 * increase the actual pipe size due to the frame doubling and
8987 * insertion of additional space for blanks between the frame. This
8988 * is stored in the crtc timings. We use the requested mode to do this
8989 * computation to clearly distinguish it from the adjusted mode, which
8990 * can be changed by the connectors in the below retry loop.
8991 */
8992 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8993 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8994 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8995
e29c22c0 8996encoder_retry:
ef1b460d 8997 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8998 pipe_config->port_clock = 0;
ef1b460d 8999 pipe_config->pixel_multiplier = 1;
ff9a6750 9000
135c81b8 9001 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 9002 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 9003
7758a113
DV		 9004 /* Pass our mode to the connectors and the CRTC to give them a chance to
9005 * adjust it according to limitations or connector properties, and also
9006 * a chance to reject the mode entirely.
47f1c6c9 9007 */
7758a113
DV		 9008 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9009 base.head) {
47f1c6c9 9010
7758a113
DV		 9011 if (&encoder->new_crtc->base != crtc)
9012 continue;
7ae89233 9013
efea6e8e
DV		 9014 if (!(encoder->compute_config(encoder, pipe_config))) {
9015 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 9016 goto fail;
9017 }
ee7b9f93 9018 }
47f1c6c9 9019
ff9a6750
DV		 9020 /* Set default port clock if not overwritten by the encoder. Needs to be
9021 * done afterwards in case the encoder adjusts the mode. */
9022 if (!pipe_config->port_clock)
241bfc38
DL		 9023 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9024 * pipe_config->pixel_multiplier;
ff9a6750 9025
a43f6e0f 9026 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 9027 if (ret < 0) {
7758a113
DV		 9028 DRM_DEBUG_KMS("CRTC fixup failed\n");
9029 goto fail;
ee7b9f93 9030 }
e29c22c0
DV		 9031
9032 if (ret == RETRY) {
9033 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9034 ret = -EINVAL;
9035 goto fail;
9036 }
9037
9038 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9039 retry = false;
9040 goto encoder_retry;
9041 }
9042
4e53c2e0
DV		 9043 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9044 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9045 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9046
b8cecdf5 9047 return pipe_config;
7758a113 9048fail:
b8cecdf5 9049 kfree(pipe_config);
e29c22c0 9050 return ERR_PTR(ret);
ee7b9f93 9051}
47f1c6c9 9052
e2e1ed41
DV		 9053/* Computes which crtcs are affected and sets the relevant bits in the mask. For
9054 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9055static void
9056intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9057 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 9058{
9059 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 9060 struct drm_device *dev = crtc->dev;
9061 struct intel_encoder *encoder;
9062 struct intel_connector *connector;
9063 struct drm_crtc *tmp_crtc;
79e53945 9064
e2e1ed41 9065 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 9066
e2e1ed41
DV		 9067 /* Check which crtcs have changed outputs connected to them, these need
9068 * to be part of the prepare_pipes mask. We don't (yet) support global
9069 * modeset across multiple crtcs, so modeset_pipes will only have one
9070 * bit set at most. */
9071 list_for_each_entry(connector, &dev->mode_config.connector_list,
9072 base.head) {
9073 if (connector->base.encoder == &connector->new_encoder->base)
9074 continue;
79e53945 9075
e2e1ed41
DV		 9076 if (connector->base.encoder) {
9077 tmp_crtc = connector->base.encoder->crtc;
9078
9079 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9080 }
9081
9082 if (connector->new_encoder)
9083 *prepare_pipes |=
9084 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 9085 }
9086
e2e1ed41
DV		 9087 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9088 base.head) {
9089 if (encoder->base.crtc == &encoder->new_crtc->base)
9090 continue;
9091
9092 if (encoder->base.crtc) {
9093 tmp_crtc = encoder->base.crtc;
9094
9095 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9096 }
9097
9098 if (encoder->new_crtc)
9099 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 9100 }
9101
e2e1ed41
DV		 9102 /* Check for any pipes that will be fully disabled ... */
9103 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9104 base.head) {
9105 bool used = false;
22fd0fab 9106
e2e1ed41
DV		 9107 /* Don't try to disable disabled crtcs. */
9108 if (!intel_crtc->base.enabled)
9109 continue;
7e7d76c3 9110
e2e1ed41
DV		 9111 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9112 base.head) {
9113 if (encoder->new_crtc == intel_crtc)
9114 used = true;
9115 }
9116
9117 if (!used)
9118 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 9119 }
9120
e2e1ed41
DV		 9121
9122 /* set_mode is also used to update properties on life display pipes. */
9123 intel_crtc = to_intel_crtc(crtc);
9124 if (crtc->enabled)
9125 *prepare_pipes |= 1 << intel_crtc->pipe;
9126
b6c5164d
DV		 9127 /*
9128 * For simplicity do a full modeset on any pipe where the output routing
9129 * changed. We could be more clever, but that would require us to be
9130 * more careful with calling the relevant encoder->mode_set functions.
9131 */
e2e1ed41
DV		 9132 if (*prepare_pipes)
9133 *modeset_pipes = *prepare_pipes;
9134
9135 /* ... and mask these out. */
9136 *modeset_pipes &= ~(*disable_pipes);
9137 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 9138
9139 /*
9140 * HACK: We don't (yet) fully support global modesets. intel_set_config
9141 * obies this rule, but the modeset restore mode of
9142 * intel_modeset_setup_hw_state does not.
9143 */
9144 *modeset_pipes &= 1 << intel_crtc->pipe;
9145 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 9146
9147 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9148 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 9149}
79e53945 9150
ea9d758d 9151static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 9152{
ea9d758d 9153 struct drm_encoder *encoder;
f6e5b160 9154 struct drm_device *dev = crtc->dev;
f6e5b160 9155
ea9d758d
DV		 9156 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9157 if (encoder->crtc == crtc)
9158 return true;
9159
9160 return false;
9161}
9162
9163static void
9164intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9165{
9166 struct intel_encoder *intel_encoder;
9167 struct intel_crtc *intel_crtc;
9168 struct drm_connector *connector;
9169
9170 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9171 base.head) {
9172 if (!intel_encoder->base.crtc)
9173 continue;
9174
9175 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9176
9177 if (prepare_pipes & (1 << intel_crtc->pipe))
9178 intel_encoder->connectors_active = false;
9179 }
9180
9181 intel_modeset_commit_output_state(dev);
9182
9183 /* Update computed state. */
9184 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9185 base.head) {
9186 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9187 }
9188
9189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9190 if (!connector->encoder || !connector->encoder->crtc)
9191 continue;
9192
9193 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9194
9195 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 9196 struct drm_property *dpms_property =
9197 dev->mode_config.dpms_property;
9198
ea9d758d 9199 connector->dpms = DRM_MODE_DPMS_ON;
662595df 9200 drm_object_property_set_value(&connector->base,
68d34720
DV		 9201 dpms_property,
9202 DRM_MODE_DPMS_ON);
ea9d758d
DV		 9203
9204 intel_encoder = to_intel_encoder(connector->encoder);
9205 intel_encoder->connectors_active = true;
9206 }
9207 }
9208
9209}
9210
3bd26263 9211static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 9212{
3bd26263 9213 int diff;
f1f644dc
JB		 9214
9215 if (clock1 == clock2)
9216 return true;
9217
9218 if (!clock1 || !clock2)
9219 return false;
9220
9221 diff = abs(clock1 - clock2);
9222
9223 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9224 return true;
9225
9226 return false;
9227}
9228
25c5b266
DV		 9229#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9230 list_for_each_entry((intel_crtc), \
9231 &(dev)->mode_config.crtc_list, \
9232 base.head) \
0973f18f 9233 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 9234
0e8ffe1b 9235static bool
2fa2fe9a
DV		 9236intel_pipe_config_compare(struct drm_device *dev,
9237 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 9238 struct intel_crtc_config *pipe_config)
9239{
66e985c0
DV		 9240#define PIPE_CONF_CHECK_X(name) \
9241 if (current_config->name != pipe_config->name) { \
9242 DRM_ERROR("mismatch in " #name " " \
9243 "(expected 0x%08x, found 0x%08x)\n", \
9244 current_config->name, \
9245 pipe_config->name); \
9246 return false; \
9247 }
9248
08a24034
DV		 9249#define PIPE_CONF_CHECK_I(name) \
9250 if (current_config->name != pipe_config->name) { \
9251 DRM_ERROR("mismatch in " #name " " \
9252 "(expected %i, found %i)\n", \
9253 current_config->name, \
9254 pipe_config->name); \
9255 return false; \
88adfff1
DV		 9256 }
9257
1bd1bd80
DV		 9258#define PIPE_CONF_CHECK_FLAGS(name, mask) \
9259 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 9260 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 9261 "(expected %i, found %i)\n", \
9262 current_config->name & (mask), \
9263 pipe_config->name & (mask)); \
9264 return false; \
9265 }
9266
5e550656
VS		 9267#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9268 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9269 DRM_ERROR("mismatch in " #name " " \
9270 "(expected %i, found %i)\n", \
9271 current_config->name, \
9272 pipe_config->name); \
9273 return false; \
9274 }
9275
bb760063
DV		 9276#define PIPE_CONF_QUIRK(quirk) \
9277 ((current_config->quirks | pipe_config->quirks) & (quirk))
9278
eccb140b
DV		 9279 PIPE_CONF_CHECK_I(cpu_transcoder);
9280
08a24034
DV		 9281 PIPE_CONF_CHECK_I(has_pch_encoder);
9282 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 9283 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9284 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9285 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9286 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9287 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 9288
eb14cb74
VS		 9289 PIPE_CONF_CHECK_I(has_dp_encoder);
9290 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9291 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9292 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9293 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9294 PIPE_CONF_CHECK_I(dp_m_n.tu);
9295
1bd1bd80
DV		 9296 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9297 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9298 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9299 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9300 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9301 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9302
9303 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9304 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9305 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9306 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9307 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9308 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9309
c93f54cf 9310 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 9311
1bd1bd80
DV		 9312 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9313 DRM_MODE_FLAG_INTERLACE);
9314
bb760063
DV		 9315 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9316 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9317 DRM_MODE_FLAG_PHSYNC);
9318 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9319 DRM_MODE_FLAG_NHSYNC);
9320 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9321 DRM_MODE_FLAG_PVSYNC);
9322 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9323 DRM_MODE_FLAG_NVSYNC);
9324 }
045ac3b5 9325
37327abd
VS		 9326 PIPE_CONF_CHECK_I(pipe_src_w);
9327 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 9328
2fa2fe9a
DV		 9329 PIPE_CONF_CHECK_I(gmch_pfit.control);
9330 /* pfit ratios are autocomputed by the hw on gen4+ */
9331 if (INTEL_INFO(dev)->gen < 4)
9332 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9333 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 9334 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9335 if (current_config->pch_pfit.enabled) {
9336 PIPE_CONF_CHECK_I(pch_pfit.pos);
9337 PIPE_CONF_CHECK_I(pch_pfit.size);
9338 }
2fa2fe9a 9339
e59150dc
JB		 9340 /* BDW+ don't expose a synchronous way to read the state */
9341 if (IS_HASWELL(dev))
9342 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 9343
282740f7
VS		 9344 PIPE_CONF_CHECK_I(double_wide);
9345
c0d43d62 9346 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 9347 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 9348 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 9349 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9350 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 9351
42571aef
VS		 9352 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9353 PIPE_CONF_CHECK_I(pipe_bpp);
9354
d71b8d4a 9355 if (!IS_HASWELL(dev)) {
241bfc38 9356 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 9357 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9358 }
5e550656 9359
66e985c0 9360#undef PIPE_CONF_CHECK_X
08a24034 9361#undef PIPE_CONF_CHECK_I
1bd1bd80 9362#undef PIPE_CONF_CHECK_FLAGS
5e550656 9363#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 9364#undef PIPE_CONF_QUIRK
88adfff1 9365
0e8ffe1b
DV		 9366 return true;
9367}
9368
91d1b4bd
DV		 9369static void
9370check_connector_state(struct drm_device *dev)
8af6cf88 9371{
8af6cf88
DV		 9372 struct intel_connector *connector;
9373
9374 list_for_each_entry(connector, &dev->mode_config.connector_list,
9375 base.head) {
9376 /* This also checks the encoder/connector hw state with the
9377 * ->get_hw_state callbacks. */
9378 intel_connector_check_state(connector);
9379
9380 WARN(&connector->new_encoder->base != connector->base.encoder,
9381 "connector's staged encoder doesn't match current encoder\n");
9382 }
91d1b4bd
DV		 9383}
9384
9385static void
9386check_encoder_state(struct drm_device *dev)
9387{
9388 struct intel_encoder *encoder;
9389 struct intel_connector *connector;
8af6cf88
DV		 9390
9391 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9392 base.head) {
9393 bool enabled = false;
9394 bool active = false;
9395 enum pipe pipe, tracked_pipe;
9396
9397 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9398 encoder->base.base.id,
9399 drm_get_encoder_name(&encoder->base));
9400
9401 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9402 "encoder's stage crtc doesn't match current crtc\n");
9403 WARN(encoder->connectors_active && !encoder->base.crtc,
9404 "encoder's active_connectors set, but no crtc\n");
9405
9406 list_for_each_entry(connector, &dev->mode_config.connector_list,
9407 base.head) {
9408 if (connector->base.encoder != &encoder->base)
9409 continue;
9410 enabled = true;
9411 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9412 active = true;
9413 }
9414 WARN(!!encoder->base.crtc != enabled,
9415 "encoder's enabled state mismatch "
9416 "(expected %i, found %i)\n",
9417 !!encoder->base.crtc, enabled);
9418 WARN(active && !encoder->base.crtc,
9419 "active encoder with no crtc\n");
9420
9421 WARN(encoder->connectors_active != active,
9422 "encoder's computed active state doesn't match tracked active state "
9423 "(expected %i, found %i)\n", active, encoder->connectors_active);
9424
9425 active = encoder->get_hw_state(encoder, &pipe);
9426 WARN(active != encoder->connectors_active,
9427 "encoder's hw state doesn't match sw tracking "
9428 "(expected %i, found %i)\n",
9429 encoder->connectors_active, active);
9430
9431 if (!encoder->base.crtc)
9432 continue;
9433
9434 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9435 WARN(active && pipe != tracked_pipe,
9436 "active encoder's pipe doesn't match"
9437 "(expected %i, found %i)\n",
9438 tracked_pipe, pipe);
9439
9440 }
91d1b4bd
DV		 9441}
9442
9443static void
9444check_crtc_state(struct drm_device *dev)
9445{
9446 drm_i915_private_t *dev_priv = dev->dev_private;
9447 struct intel_crtc *crtc;
9448 struct intel_encoder *encoder;
9449 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9450
9451 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9452 base.head) {
9453 bool enabled = false;
9454 bool active = false;
9455
045ac3b5
JB		 9456 memset(&pipe_config, 0, sizeof(pipe_config));
9457
8af6cf88
DV		 9458 DRM_DEBUG_KMS("[CRTC:%d]\n",
9459 crtc->base.base.id);
9460
9461 WARN(crtc->active && !crtc->base.enabled,
9462 "active crtc, but not enabled in sw tracking\n");
9463
9464 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9465 base.head) {
9466 if (encoder->base.crtc != &crtc->base)
9467 continue;
9468 enabled = true;
9469 if (encoder->connectors_active)
9470 active = true;
9471 }
6c49f241 9472
8af6cf88
DV		 9473 WARN(active != crtc->active,
9474 "crtc's computed active state doesn't match tracked active state "
9475 "(expected %i, found %i)\n", active, crtc->active);
9476 WARN(enabled != crtc->base.enabled,
9477 "crtc's computed enabled state doesn't match tracked enabled state "
9478 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9479
0e8ffe1b
DV		 9480 active = dev_priv->display.get_pipe_config(crtc,
9481 &pipe_config);
d62cf62a
DV		 9482
9483 /* hw state is inconsistent with the pipe A quirk */
9484 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9485 active = crtc->active;
9486
6c49f241
DV		 9487 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9488 base.head) {
3eaba51c 9489 enum pipe pipe;
6c49f241
DV		 9490 if (encoder->base.crtc != &crtc->base)
9491 continue;
1d37b689 9492 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9493 encoder->get_config(encoder, &pipe_config);
9494 }
9495
0e8ffe1b
DV		 9496 WARN(crtc->active != active,
9497 "crtc active state doesn't match with hw state "
9498 "(expected %i, found %i)\n", crtc->active, active);
9499
c0b03411
DV		 9500 if (active &&
9501 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9502 WARN(1, "pipe state doesn't match!\n");
9503 intel_dump_pipe_config(crtc, &pipe_config,
9504 "[hw state]");
9505 intel_dump_pipe_config(crtc, &crtc->config,
9506 "[sw state]");
9507 }
8af6cf88
DV		 9508 }
9509}
9510
91d1b4bd
DV		 9511static void
9512check_shared_dpll_state(struct drm_device *dev)
9513{
9514 drm_i915_private_t *dev_priv = dev->dev_private;
9515 struct intel_crtc *crtc;
9516 struct intel_dpll_hw_state dpll_hw_state;
9517 int i;
5358901f
DV		 9518
9519 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9520 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9521 int enabled_crtcs = 0, active_crtcs = 0;
9522 bool active;
9523
9524 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9525
9526 DRM_DEBUG_KMS("%s\n", pll->name);
9527
9528 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9529
9530 WARN(pll->active > pll->refcount,
9531 "more active pll users than references: %i vs %i\n",
9532 pll->active, pll->refcount);
9533 WARN(pll->active && !pll->on,
9534 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9535 WARN(pll->on && !pll->active,
9536 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9537 WARN(pll->on != active,
9538 "pll on state mismatch (expected %i, found %i)\n",
9539 pll->on, active);
9540
9541 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9542 base.head) {
9543 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9544 enabled_crtcs++;
9545 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9546 active_crtcs++;
9547 }
9548 WARN(pll->active != active_crtcs,
9549 "pll active crtcs mismatch (expected %i, found %i)\n",
9550 pll->active, active_crtcs);
9551 WARN(pll->refcount != enabled_crtcs,
9552 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9553 pll->refcount, enabled_crtcs);
66e985c0
DV		 9554
9555 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9556 sizeof(dpll_hw_state)),
9557 "pll hw state mismatch\n");
5358901f 9558 }
8af6cf88
DV		 9559}
9560
91d1b4bd
DV		 9561void
9562intel_modeset_check_state(struct drm_device *dev)
9563{
9564 check_connector_state(dev);
9565 check_encoder_state(dev);
9566 check_crtc_state(dev);
9567 check_shared_dpll_state(dev);
9568}
9569
18442d08
VS		 9570void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9571 int dotclock)
9572{
9573 /*
9574 * FDI already provided one idea for the dotclock.
9575 * Yell if the encoder disagrees.
9576 */
241bfc38 9577 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9578 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9579 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9580}
9581
f30da187
DV		 9582static int __intel_set_mode(struct drm_crtc *crtc,
9583 struct drm_display_mode *mode,
9584 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9585{
9586 struct drm_device *dev = crtc->dev;
dbf2b54e 9587 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9588 struct drm_display_mode *saved_mode, *saved_hwmode;
9589 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9590 struct intel_crtc *intel_crtc;
9591 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9592 int ret = 0;
a6778b3c 9593
a1e22653 9594 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9595 if (!saved_mode)
9596 return -ENOMEM;
3ac18232 9597 saved_hwmode = saved_mode + 1;
a6778b3c 9598
e2e1ed41 9599 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9600 &prepare_pipes, &disable_pipes);
9601
3ac18232
TG		 9602 *saved_hwmode = crtc->hwmode;
9603 *saved_mode = crtc->mode;
a6778b3c 9604
25c5b266
DV		 9605 /* Hack: Because we don't (yet) support global modeset on multiple
9606 * crtcs, we don't keep track of the new mode for more than one crtc.
9607 * Hence simply check whether any bit is set in modeset_pipes in all the
9608 * pieces of code that are not yet converted to deal with mutliple crtcs
9609 * changing their mode at the same time. */
25c5b266 9610 if (modeset_pipes) {
4e53c2e0 9611 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9612 if (IS_ERR(pipe_config)) {
9613 ret = PTR_ERR(pipe_config);
9614 pipe_config = NULL;
9615
3ac18232 9616 goto out;
25c5b266 9617 }
c0b03411
DV		 9618 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9619 "[modeset]");
25c5b266 9620 }
a6778b3c 9621
30a970c6
JB		 9622 /*
9623 * See if the config requires any additional preparation, e.g.
9624 * to adjust global state with pipes off. We need to do this
9625 * here so we can get the modeset_pipe updated config for the new
9626 * mode set on this crtc. For other crtcs we need to use the
9627 * adjusted_mode bits in the crtc directly.
9628 */
c164f833 9629 if (IS_VALLEYVIEW(dev)) {
30a970c6
JB		 9630 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9631 modeset_pipes, pipe_config);
9632
c164f833
VS		 9633 /* may have added more to prepare_pipes than we should */
9634 prepare_pipes &= ~disable_pipes;
9635 }
9636
460da916
DV		 9637 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9638 intel_crtc_disable(&intel_crtc->base);
9639
ea9d758d
DV		 9640 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9641 if (intel_crtc->base.enabled)
9642 dev_priv->display.crtc_disable(&intel_crtc->base);
9643 }
a6778b3c 9644
6c4c86f5
DV		 9645 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9646 * to set it here already despite that we pass it down the callchain.
f6e5b160 9647 */
b8cecdf5 9648 if (modeset_pipes) {
25c5b266 9649 crtc->mode = *mode;
b8cecdf5
DV		 9650 /* mode_set/enable/disable functions rely on a correct pipe
9651 * config. */
9652 to_intel_crtc(crtc)->config = *pipe_config;
9653 }
7758a113 9654
ea9d758d
DV		 9655 /* Only after disabling all output pipelines that will be changed can we
9656 * update the the output configuration. */
9657 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9658
47fab737
DV		 9659 if (dev_priv->display.modeset_global_resources)
9660 dev_priv->display.modeset_global_resources(dev);
9661
a6778b3c
DV		 9662 /* Set up the DPLL and any encoders state that needs to adjust or depend
9663 * on the DPLL.
f6e5b160 9664 */
25c5b266 9665 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9666 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9667 x, y, fb);
9668 if (ret)
9669 goto done;
a6778b3c
DV		 9670 }
9671
9672 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9673 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9674 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9675
25c5b266
DV		 9676 if (modeset_pipes) {
9677 /* Store real post-adjustment hardware mode. */
b8cecdf5 9678 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9679
25c5b266
DV		 9680 /* Calculate and store various constants which
9681 * are later needed by vblank and swap-completion
9682 * timestamping. They are derived from true hwmode.
9683 */
9684 drm_calc_timestamping_constants(crtc);
9685 }
a6778b3c
DV		 9686
9687 /* FIXME: add subpixel order */
9688done:
c0c36b94 9689 if (ret && crtc->enabled) {
3ac18232
TG		 9690 crtc->hwmode = *saved_hwmode;
9691 crtc->mode = *saved_mode;
a6778b3c
DV		 9692 }
9693
3ac18232 9694out:
b8cecdf5 9695 kfree(pipe_config);
3ac18232 9696 kfree(saved_mode);
a6778b3c 9697 return ret;
f6e5b160
CW		 9698}
9699
e7457a9a
DL		 9700static int intel_set_mode(struct drm_crtc *crtc,
9701 struct drm_display_mode *mode,
9702 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9703{
9704 int ret;
9705
9706 ret = __intel_set_mode(crtc, mode, x, y, fb);
9707
9708 if (ret == 0)
9709 intel_modeset_check_state(crtc->dev);
9710
9711 return ret;
9712}
9713
c0c36b94
CW		 9714void intel_crtc_restore_mode(struct drm_crtc *crtc)
9715{
9716 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9717}
9718
25c5b266
DV		 9719#undef for_each_intel_crtc_masked
9720
d9e55608
DV		 9721static void intel_set_config_free(struct intel_set_config *config)
9722{
9723 if (!config)
9724 return;
9725
1aa4b628
DV		 9726 kfree(config->save_connector_encoders);
9727 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9728 kfree(config);
9729}
9730
85f9eb71
DV		 9731static int intel_set_config_save_state(struct drm_device *dev,
9732 struct intel_set_config *config)
9733{
85f9eb71
DV		 9734 struct drm_encoder *encoder;
9735 struct drm_connector *connector;
9736 int count;
9737
1aa4b628
DV		 9738 config->save_encoder_crtcs =
9739 kcalloc(dev->mode_config.num_encoder,
9740 sizeof(struct drm_crtc *), GFP_KERNEL);
9741 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9742 return -ENOMEM;
9743
1aa4b628
DV		 9744 config->save_connector_encoders =
9745 kcalloc(dev->mode_config.num_connector,
9746 sizeof(struct drm_encoder *), GFP_KERNEL);
9747 if (!config->save_connector_encoders)
85f9eb71
DV		 9748 return -ENOMEM;
9749
9750 /* Copy data. Note that driver private data is not affected.
9751 * Should anything bad happen only the expected state is
9752 * restored, not the drivers personal bookkeeping.
9753 */
85f9eb71
DV		 9754 count = 0;
9755 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9756 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9757 }
9758
9759 count = 0;
9760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9761 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9762 }
9763
9764 return 0;
9765}
9766
9767static void intel_set_config_restore_state(struct drm_device *dev,
9768 struct intel_set_config *config)
9769{
9a935856
DV		 9770 struct intel_encoder *encoder;
9771 struct intel_connector *connector;
85f9eb71
DV		 9772 int count;
9773
85f9eb71 9774 count = 0;
9a935856
DV		 9775 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9776 encoder->new_crtc =
9777 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9778 }
9779
9780 count = 0;
9a935856
DV		 9781 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9782 connector->new_encoder =
9783 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9784 }
9785}
9786
e3de42b6 9787static bool
2e57f47d 9788is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9789{
9790 int i;
9791
2e57f47d
CW		 9792 if (set->num_connectors == 0)
9793 return false;
9794
9795 if (WARN_ON(set->connectors == NULL))
9796 return false;
9797
9798 for (i = 0; i < set->num_connectors; i++)
9799 if (set->connectors[i]->encoder &&
9800 set->connectors[i]->encoder->crtc == set->crtc &&
9801 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9802 return true;
9803
9804 return false;
9805}
9806
5e2b584e
DV		 9807static void
9808intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9809 struct intel_set_config *config)
9810{
9811
9812 /* We should be able to check here if the fb has the same properties
9813 * and then just flip_or_move it */
2e57f47d
CW		 9814 if (is_crtc_connector_off(set)) {
9815 config->mode_changed = true;
e3de42b6 9816 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9817 /* If we have no fb then treat it as a full mode set */
9818 if (set->crtc->fb == NULL) {
319d9827
JB		 9819 struct intel_crtc *intel_crtc =
9820 to_intel_crtc(set->crtc);
9821
9822 if (intel_crtc->active && i915_fastboot) {
9823 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9824 config->fb_changed = true;
9825 } else {
9826 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9827 config->mode_changed = true;
9828 }
5e2b584e
DV		 9829 } else if (set->fb == NULL) {
9830 config->mode_changed = true;
72f4901e
DV		 9831 } else if (set->fb->pixel_format !=
9832 set->crtc->fb->pixel_format) {
5e2b584e 9833 config->mode_changed = true;
e3de42b6 9834 } else {
5e2b584e 9835 config->fb_changed = true;
e3de42b6 9836 }
5e2b584e
DV		 9837 }
9838
835c5873 9839 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9840 config->fb_changed = true;
9841
9842 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9843 DRM_DEBUG_KMS("modes are different, full mode set\n");
9844 drm_mode_debug_printmodeline(&set->crtc->mode);
9845 drm_mode_debug_printmodeline(set->mode);
9846 config->mode_changed = true;
9847 }
a1d95703
CW		 9848
9849 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9850 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9851}
9852
2e431051 9853static int
9a935856
DV		 9854intel_modeset_stage_output_state(struct drm_device *dev,
9855 struct drm_mode_set *set,
9856 struct intel_set_config *config)
50f56119 9857{
85f9eb71 9858 struct drm_crtc *new_crtc;
9a935856
DV		 9859 struct intel_connector *connector;
9860 struct intel_encoder *encoder;
f3f08572 9861 int ro;
50f56119 9862
9abdda74 9863 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9864 * of connectors. For paranoia, double-check this. */
9865 WARN_ON(!set->fb && (set->num_connectors != 0));
9866 WARN_ON(set->fb && (set->num_connectors == 0));
9867
9a935856
DV		 9868 list_for_each_entry(connector, &dev->mode_config.connector_list,
9869 base.head) {
9870 /* Otherwise traverse passed in connector list and get encoders
9871 * for them. */
50f56119 9872 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9873 if (set->connectors[ro] == &connector->base) {
9874 connector->new_encoder = connector->encoder;
50f56119
DV		 9875 break;
9876 }
9877 }
9878
9a935856
DV		 9879 /* If we disable the crtc, disable all its connectors. Also, if
9880 * the connector is on the changing crtc but not on the new
9881 * connector list, disable it. */
9882 if ((!set->fb || ro == set->num_connectors) &&
9883 connector->base.encoder &&
9884 connector->base.encoder->crtc == set->crtc) {
9885 connector->new_encoder = NULL;
9886
9887 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9888 connector->base.base.id,
9889 drm_get_connector_name(&connector->base));
9890 }
9891
9892
9893 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9894 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9895 config->mode_changed = true;
50f56119
DV		 9896 }
9897 }
9a935856 9898 /* connector->new_encoder is now updated for all connectors. */
50f56119 9899
9a935856 9900 /* Update crtc of enabled connectors. */
9a935856
DV		 9901 list_for_each_entry(connector, &dev->mode_config.connector_list,
9902 base.head) {
9903 if (!connector->new_encoder)
50f56119
DV		 9904 continue;
9905
9a935856 9906 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9907
9908 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9909 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9910 new_crtc = set->crtc;
9911 }
9912
9913 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9914 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9915 new_crtc)) {
5e2b584e 9916 return -EINVAL;
50f56119 9917 }
9a935856
DV		 9918 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9919
9920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9921 connector->base.base.id,
9922 drm_get_connector_name(&connector->base),
9923 new_crtc->base.id);
9924 }
9925
9926 /* Check for any encoders that needs to be disabled. */
9927 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9928 base.head) {
9929 list_for_each_entry(connector,
9930 &dev->mode_config.connector_list,
9931 base.head) {
9932 if (connector->new_encoder == encoder) {
9933 WARN_ON(!connector->new_encoder->new_crtc);
9934
9935 goto next_encoder;
9936 }
9937 }
9938 encoder->new_crtc = NULL;
9939next_encoder:
9940 /* Only now check for crtc changes so we don't miss encoders
9941 * that will be disabled. */
9942 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9943 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9944 config->mode_changed = true;
50f56119
DV		 9945 }
9946 }
9a935856 9947 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9948
2e431051
DV		 9949 return 0;
9950}
9951
9952static int intel_crtc_set_config(struct drm_mode_set *set)
9953{
9954 struct drm_device *dev;
2e431051
DV		 9955 struct drm_mode_set save_set;
9956 struct intel_set_config *config;
9957 int ret;
2e431051 9958
8d3e375e
DV		 9959 BUG_ON(!set);
9960 BUG_ON(!set->crtc);
9961 BUG_ON(!set->crtc->helper_private);
2e431051 9962
7e53f3a4
DV		 9963 /* Enforce sane interface api - has been abused by the fb helper. */
9964 BUG_ON(!set->mode && set->fb);
9965 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9966
2e431051
DV		 9967 if (set->fb) {
9968 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9969 set->crtc->base.id, set->fb->base.id,
9970 (int)set->num_connectors, set->x, set->y);
9971 } else {
9972 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9973 }
9974
9975 dev = set->crtc->dev;
9976
9977 ret = -ENOMEM;
9978 config = kzalloc(sizeof(*config), GFP_KERNEL);
9979 if (!config)
9980 goto out_config;
9981
9982 ret = intel_set_config_save_state(dev, config);
9983 if (ret)
9984 goto out_config;
9985
9986 save_set.crtc = set->crtc;
9987 save_set.mode = &set->crtc->mode;
9988 save_set.x = set->crtc->x;
9989 save_set.y = set->crtc->y;
9990 save_set.fb = set->crtc->fb;
9991
9992 /* Compute whether we need a full modeset, only an fb base update or no
9993 * change at all. In the future we might also check whether only the
9994 * mode changed, e.g. for LVDS where we only change the panel fitter in
9995 * such cases. */
9996 intel_set_config_compute_mode_changes(set, config);
9997
9a935856 9998 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9999 if (ret)
10000 goto fail;
10001
5e2b584e 10002 if (config->mode_changed) {
c0c36b94
CW		 10003 ret = intel_set_mode(set->crtc, set->mode,
10004 set->x, set->y, set->fb);
5e2b584e 10005 } else if (config->fb_changed) {
4878cae2
VS		 10006 intel_crtc_wait_for_pending_flips(set->crtc);
10007
4f660f49 10008 ret = intel_pipe_set_base(set->crtc,
94352cf9 10009 set->x, set->y, set->fb);
7ca51a3a
JB		 10010 /*
10011 * In the fastboot case this may be our only check of the
10012 * state after boot. It would be better to only do it on
10013 * the first update, but we don't have a nice way of doing that
10014 * (and really, set_config isn't used much for high freq page
10015 * flipping, so increasing its cost here shouldn't be a big
10016 * deal).
10017 */
10018 if (i915_fastboot && ret == 0)
10019 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 10020 }
10021
2d05eae1 10022 if (ret) {
bf67dfeb
DV		 10023 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10024 set->crtc->base.id, ret);
50f56119 10025fail:
2d05eae1 10026 intel_set_config_restore_state(dev, config);
50f56119 10027
2d05eae1
CW		 10028 /* Try to restore the config */
10029 if (config->mode_changed &&
10030 intel_set_mode(save_set.crtc, save_set.mode,
10031 save_set.x, save_set.y, save_set.fb))
10032 DRM_ERROR("failed to restore config after modeset failure\n");
10033 }
50f56119 10034
d9e55608
DV		 10035out_config:
10036 intel_set_config_free(config);
50f56119
DV		 10037 return ret;
10038}
f6e5b160
CW		 10039
10040static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 10041 .cursor_set = intel_crtc_cursor_set,
10042 .cursor_move = intel_crtc_cursor_move,
10043 .gamma_set = intel_crtc_gamma_set,
50f56119 10044 .set_config = intel_crtc_set_config,
f6e5b160
CW		 10045 .destroy = intel_crtc_destroy,
10046 .page_flip = intel_crtc_page_flip,
10047};
10048
79f689aa
PZ		 10049static void intel_cpu_pll_init(struct drm_device *dev)
10050{
affa9354 10051 if (HAS_DDI(dev))
79f689aa
PZ		 10052 intel_ddi_pll_init(dev);
10053}
10054
5358901f
DV		 10055static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10056 struct intel_shared_dpll *pll,
10057 struct intel_dpll_hw_state *hw_state)
ee7b9f93 10058{
5358901f 10059 uint32_t val;
ee7b9f93 10060
5358901f 10061 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 10062 hw_state->dpll = val;
10063 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10064 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 10065
10066 return val & DPLL_VCO_ENABLE;
10067}
10068
15bdd4cf
DV		 10069static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10070 struct intel_shared_dpll *pll)
10071{
10072 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10073 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10074}
10075
e7b903d2
DV		 10076static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10077 struct intel_shared_dpll *pll)
10078{
e7b903d2
DV		 10079 /* PCH refclock must be enabled first */
10080 assert_pch_refclk_enabled(dev_priv);
10081
15bdd4cf
DV		 10082 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10083
10084 /* Wait for the clocks to stabilize. */
10085 POSTING_READ(PCH_DPLL(pll->id));
10086 udelay(150);
10087
10088 /* The pixel multiplier can only be updated once the
10089 * DPLL is enabled and the clocks are stable.
10090 *
10091 * So write it again.
10092 */
10093 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10094 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 10095 udelay(200);
10096}
10097
10098static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10099 struct intel_shared_dpll *pll)
10100{
10101 struct drm_device *dev = dev_priv->dev;
10102 struct intel_crtc *crtc;
e7b903d2
DV		 10103
10104 /* Make sure no transcoder isn't still depending on us. */
10105 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10106 if (intel_crtc_to_shared_dpll(crtc) == pll)
10107 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 10108 }
10109
15bdd4cf
DV		 10110 I915_WRITE(PCH_DPLL(pll->id), 0);
10111 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 10112 udelay(200);
10113}
10114
46edb027
DV		 10115static char *ibx_pch_dpll_names[] = {
10116 "PCH DPLL A",
10117 "PCH DPLL B",
10118};
10119
7c74ade1 10120static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 10121{
e7b903d2 10122 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 10123 int i;
10124
7c74ade1 10125 dev_priv->num_shared_dpll = 2;
ee7b9f93 10126
e72f9fbf 10127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 10128 dev_priv->shared_dplls[i].id = i;
10129 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 10130 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 10131 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10132 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 10133 dev_priv->shared_dplls[i].get_hw_state =
10134 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 10135 }
10136}
10137
7c74ade1
DV		 10138static void intel_shared_dpll_init(struct drm_device *dev)
10139{
e7b903d2 10140 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 10141
10142 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10143 ibx_pch_dpll_init(dev);
10144 else
10145 dev_priv->num_shared_dpll = 0;
10146
10147 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10148 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10149 dev_priv->num_shared_dpll);
10150}
10151
b358d0a6 10152static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 10153{
22fd0fab 10154 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 10155 struct intel_crtc *intel_crtc;
10156 int i;
10157
955382f3 10158 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 10159 if (intel_crtc == NULL)
10160 return;
10161
10162 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10163
10164 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 10165 for (i = 0; i < 256; i++) {
10166 intel_crtc->lut_r[i] = i;
10167 intel_crtc->lut_g[i] = i;
10168 intel_crtc->lut_b[i] = i;
10169 }
10170
1f1c2e24
VS		 10171 /*
10172 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10173 * is hooked to plane B. Hence we want plane A feeding pipe B.
10174 */
80824003
JB		 10175 intel_crtc->pipe = pipe;
10176 intel_crtc->plane = pipe;
1f1c2e24 10177 if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 10178 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 10179 intel_crtc->plane = !pipe;
80824003
JB		 10180 }
10181
22fd0fab
JB		 10182 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10183 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10184 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10185 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10186
79e53945 10187 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 10188}
10189
752aa88a
JB		 10190enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10191{
10192 struct drm_encoder *encoder = connector->base.encoder;
10193
10194 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10195
10196 if (!encoder)
10197 return INVALID_PIPE;
10198
10199 return to_intel_crtc(encoder->crtc)->pipe;
10200}
10201
08d7b3d1 10202int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 10203 struct drm_file *file)
08d7b3d1 10204{
08d7b3d1 10205 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 10206 struct drm_mode_object *drmmode_obj;
10207 struct intel_crtc *crtc;
08d7b3d1 10208
1cff8f6b
DV		 10209 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10210 return -ENODEV;
08d7b3d1 10211
c05422d5
DV		 10212 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10213 DRM_MODE_OBJECT_CRTC);
08d7b3d1 10214
c05422d5 10215 if (!drmmode_obj) {
08d7b3d1 10216 DRM_ERROR("no such CRTC id\n");
3f2c2057 10217 return -ENOENT;
08d7b3d1
CW		 10218 }
10219
c05422d5
DV		 10220 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10221 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 10222
c05422d5 10223 return 0;
08d7b3d1
CW		 10224}
10225
66a9278e 10226static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 10227{
66a9278e
DV		 10228 struct drm_device *dev = encoder->base.dev;
10229 struct intel_encoder *source_encoder;
79e53945 10230 int index_mask = 0;
79e53945
JB		 10231 int entry = 0;
10232
66a9278e
DV		 10233 list_for_each_entry(source_encoder,
10234 &dev->mode_config.encoder_list, base.head) {
10235
10236 if (encoder == source_encoder)
79e53945 10237 index_mask |= (1 << entry);
66a9278e
DV		 10238
10239 /* Intel hw has only one MUX where enocoders could be cloned. */
10240 if (encoder->cloneable && source_encoder->cloneable)
10241 index_mask |= (1 << entry);
10242
79e53945
JB		 10243 entry++;
10244 }
4ef69c7a 10245
79e53945
JB		 10246 return index_mask;
10247}
10248
4d302442
CW		 10249static bool has_edp_a(struct drm_device *dev)
10250{
10251 struct drm_i915_private *dev_priv = dev->dev_private;
10252
10253 if (!IS_MOBILE(dev))
10254 return false;
10255
10256 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10257 return false;
10258
10259 if (IS_GEN5(dev) &&
10260 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10261 return false;
10262
10263 return true;
10264}
10265
79e53945
JB		 10266static void intel_setup_outputs(struct drm_device *dev)
10267{
725e30ad 10268 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 10269 struct intel_encoder *encoder;
cb0953d7 10270 bool dpd_is_edp = false;
79e53945 10271
c9093354 10272 intel_lvds_init(dev);
79e53945 10273
c40c0f5b 10274 if (!IS_ULT(dev))
79935fca 10275 intel_crt_init(dev);
cb0953d7 10276
affa9354 10277 if (HAS_DDI(dev)) {
0e72a5b5
ED		 10278 int found;
10279
10280 /* Haswell uses DDI functions to detect digital outputs */
10281 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10282 /* DDI A only supports eDP */
10283 if (found)
10284 intel_ddi_init(dev, PORT_A);
10285
10286 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10287 * register */
10288 found = I915_READ(SFUSE_STRAP);
10289
10290 if (found & SFUSE_STRAP_DDIB_DETECTED)
10291 intel_ddi_init(dev, PORT_B);
10292 if (found & SFUSE_STRAP_DDIC_DETECTED)
10293 intel_ddi_init(dev, PORT_C);
10294 if (found & SFUSE_STRAP_DDID_DETECTED)
10295 intel_ddi_init(dev, PORT_D);
10296 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 10297 int found;
270b3042
DV		 10298 dpd_is_edp = intel_dpd_is_edp(dev);
10299
10300 if (has_edp_a(dev))
10301 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 10302
dc0fa718 10303 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 10304 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 10305 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 10306 if (!found)
e2debe91 10307 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 10308 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 10309 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 10310 }
10311
dc0fa718 10312 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 10313 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 10314
dc0fa718 10315 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 10316 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 10317
5eb08b69 10318 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 10319 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 10320
270b3042 10321 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 10322 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 10323 } else if (IS_VALLEYVIEW(dev)) {
585a94b8
AB		 10324 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10325 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10326 PORT_B);
10327 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10328 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10329 }
10330
6f6005a5
JB		 10331 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10332 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10333 PORT_C);
10334 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10335 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10336 PORT_C);
10337 }
19c03924 10338
3cfca973 10339 intel_dsi_init(dev);
103a196f 10340 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 10341 bool found = false;
7d57382e 10342
e2debe91 10343 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 10344 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 10345 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 10346 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10347 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 10348 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 10349 }
27185ae1 10350
e7281eab 10351 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 10352 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 10353 }
13520b05
KH		 10354
10355 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 10356
e2debe91 10357 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 10358 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 10359 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 10360 }
27185ae1 10361
e2debe91 10362 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 10363
b01f2c3a
JB		 10364 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10365 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 10366 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 10367 }
e7281eab 10368 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 10369 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 10370 }
27185ae1 10371
b01f2c3a 10372 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 10373 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 10374 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 10375 } else if (IS_GEN2(dev))
79e53945
JB		 10376 intel_dvo_init(dev);
10377
103a196f 10378 if (SUPPORTS_TV(dev))
79e53945
JB		 10379 intel_tv_init(dev);
10380
4ef69c7a
CW		 10381 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10382 encoder->base.possible_crtcs = encoder->crtc_mask;
10383 encoder->base.possible_clones =
66a9278e 10384 intel_encoder_clones(encoder);
79e53945 10385 }
47356eb6 10386
dde86e2d 10387 intel_init_pch_refclk(dev);
270b3042
DV		 10388
10389 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 10390}
10391
ddfe1567
CW		 10392void intel_framebuffer_fini(struct intel_framebuffer *fb)
10393{
10394 drm_framebuffer_cleanup(&fb->base);
80075d49 10395 WARN_ON(!fb->obj->framebuffer_references--);
ddfe1567
CW		 10396 drm_gem_object_unreference_unlocked(&fb->obj->base);
10397}
10398
79e53945
JB		 10399static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10400{
10401 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 10402
ddfe1567 10403 intel_framebuffer_fini(intel_fb);
79e53945
JB		 10404 kfree(intel_fb);
10405}
10406
10407static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 10408 struct drm_file *file,
79e53945
JB		 10409 unsigned int *handle)
10410{
10411 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 10412 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 10413
05394f39 10414 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 10415}
10416
10417static const struct drm_framebuffer_funcs intel_fb_funcs = {
10418 .destroy = intel_user_framebuffer_destroy,
10419 .create_handle = intel_user_framebuffer_create_handle,
10420};
10421
38651674
DA		 10422int intel_framebuffer_init(struct drm_device *dev,
10423 struct intel_framebuffer *intel_fb,
308e5bcb 10424 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 10425 struct drm_i915_gem_object *obj)
79e53945 10426{
53155c0a 10427 int aligned_height, tile_height;
a35cdaa0 10428 int pitch_limit;
79e53945
JB		 10429 int ret;
10430
dd4916c5
DV		 10431 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10432
c16ed4be
CW		 10433 if (obj->tiling_mode == I915_TILING_Y) {
10434 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 10435 return -EINVAL;
c16ed4be 10436 }
57cd6508 10437
c16ed4be
CW		 10438 if (mode_cmd->pitches[0] & 63) {
10439 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10440 mode_cmd->pitches[0]);
57cd6508 10441 return -EINVAL;
c16ed4be 10442 }
57cd6508 10443
a35cdaa0
CW		 10444 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10445 pitch_limit = 32*1024;
10446 } else if (INTEL_INFO(dev)->gen >= 4) {
10447 if (obj->tiling_mode)
10448 pitch_limit = 16*1024;
10449 else
10450 pitch_limit = 32*1024;
10451 } else if (INTEL_INFO(dev)->gen >= 3) {
10452 if (obj->tiling_mode)
10453 pitch_limit = 8*1024;
10454 else
10455 pitch_limit = 16*1024;
10456 } else
10457 /* XXX DSPC is limited to 4k tiled */
10458 pitch_limit = 8*1024;
10459
10460 if (mode_cmd->pitches[0] > pitch_limit) {
10461 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10462 obj->tiling_mode ? "tiled" : "linear",
10463 mode_cmd->pitches[0], pitch_limit);
5d7bd705 10464 return -EINVAL;
c16ed4be 10465 }
5d7bd705
VS		 10466
10467 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10468 mode_cmd->pitches[0] != obj->stride) {
10469 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10470 mode_cmd->pitches[0], obj->stride);
5d7bd705 10471 return -EINVAL;
c16ed4be 10472 }
5d7bd705 10473
57779d06 10474 /* Reject formats not supported by any plane early. */
308e5bcb 10475 switch (mode_cmd->pixel_format) {
57779d06 10476 case DRM_FORMAT_C8:
04b3924d
VS		 10477 case DRM_FORMAT_RGB565:
10478 case DRM_FORMAT_XRGB8888:
10479 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10480 break;
10481 case DRM_FORMAT_XRGB1555:
10482 case DRM_FORMAT_ARGB1555:
c16ed4be 10483 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10484 DRM_DEBUG("unsupported pixel format: %s\n",
10485 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10486 return -EINVAL;
c16ed4be 10487 }
57779d06
VS		 10488 break;
10489 case DRM_FORMAT_XBGR8888:
10490 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10491 case DRM_FORMAT_XRGB2101010:
10492 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10493 case DRM_FORMAT_XBGR2101010:
10494 case DRM_FORMAT_ABGR2101010:
c16ed4be 10495 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10496 DRM_DEBUG("unsupported pixel format: %s\n",
10497 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10498 return -EINVAL;
c16ed4be 10499 }
b5626747 10500 break;
04b3924d
VS		 10501 case DRM_FORMAT_YUYV:
10502 case DRM_FORMAT_UYVY:
10503 case DRM_FORMAT_YVYU:
10504 case DRM_FORMAT_VYUY:
c16ed4be 10505 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10506 DRM_DEBUG("unsupported pixel format: %s\n",
10507 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10508 return -EINVAL;
c16ed4be 10509 }
57cd6508
CW		 10510 break;
10511 default:
4ee62c76
VS		 10512 DRM_DEBUG("unsupported pixel format: %s\n",
10513 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10514 return -EINVAL;
10515 }
10516
90f9a336
VS		 10517 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10518 if (mode_cmd->offsets[0] != 0)
10519 return -EINVAL;
10520
53155c0a
DV		 10521 tile_height = IS_GEN2(dev) ? 16 : 8;
10522 aligned_height = ALIGN(mode_cmd->height,
10523 obj->tiling_mode ? tile_height : 1);
10524 /* FIXME drm helper for size checks (especially planar formats)? */
10525 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10526 return -EINVAL;
10527
c7d73f6a
DV		 10528 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10529 intel_fb->obj = obj;
80075d49 10530 intel_fb->obj->framebuffer_references++;
c7d73f6a 10531
79e53945
JB		 10532 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10533 if (ret) {
10534 DRM_ERROR("framebuffer init failed %d\n", ret);
10535 return ret;
10536 }
10537
79e53945
JB		 10538 return 0;
10539}
10540
79e53945
JB		 10541static struct drm_framebuffer *
10542intel_user_framebuffer_create(struct drm_device *dev,
10543 struct drm_file *filp,
308e5bcb 10544 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10545{
05394f39 10546 struct drm_i915_gem_object *obj;
79e53945 10547
308e5bcb
JB		 10548 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10549 mode_cmd->handles[0]));
c8725226 10550 if (&obj->base == NULL)
cce13ff7 10551 return ERR_PTR(-ENOENT);
79e53945 10552
d2dff872 10553 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10554}
10555
4520f53a 10556#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 10557static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 10558{
10559}
10560#endif
10561
79e53945 10562static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10563 .fb_create = intel_user_framebuffer_create,
0632fef6 10564 .output_poll_changed = intel_fbdev_output_poll_changed,
79e53945
JB		 10565};
10566
e70236a8
JB		 10567/* Set up chip specific display functions */
10568static void intel_init_display(struct drm_device *dev)
10569{
10570 struct drm_i915_private *dev_priv = dev->dev_private;
10571
ee9300bb
DV		 10572 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10573 dev_priv->display.find_dpll = g4x_find_best_dpll;
10574 else if (IS_VALLEYVIEW(dev))
10575 dev_priv->display.find_dpll = vlv_find_best_dpll;
10576 else if (IS_PINEVIEW(dev))
10577 dev_priv->display.find_dpll = pnv_find_best_dpll;
10578 else
10579 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10580
affa9354 10581 if (HAS_DDI(dev)) {
0e8ffe1b 10582 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10583 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10584 dev_priv->display.crtc_enable = haswell_crtc_enable;
10585 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10586 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10587 dev_priv->display.update_plane = ironlake_update_plane;
10588 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10589 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10590 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10591 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10592 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10593 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10594 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10595 } else if (IS_VALLEYVIEW(dev)) {
10596 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10597 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10598 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10599 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10600 dev_priv->display.off = i9xx_crtc_off;
10601 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10602 } else {
0e8ffe1b 10603 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10604 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10605 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10606 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10607 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10608 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10609 }
e70236a8 10610
e70236a8 10611 /* Returns the core display clock speed */
25eb05fc
JB		 10612 if (IS_VALLEYVIEW(dev))
10613 dev_priv->display.get_display_clock_speed =
10614 valleyview_get_display_clock_speed;
10615 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10616 dev_priv->display.get_display_clock_speed =
10617 i945_get_display_clock_speed;
10618 else if (IS_I915G(dev))
10619 dev_priv->display.get_display_clock_speed =
10620 i915_get_display_clock_speed;
257a7ffc 10621 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10622 dev_priv->display.get_display_clock_speed =
10623 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10624 else if (IS_PINEVIEW(dev))
10625 dev_priv->display.get_display_clock_speed =
10626 pnv_get_display_clock_speed;
e70236a8
JB		 10627 else if (IS_I915GM(dev))
10628 dev_priv->display.get_display_clock_speed =
10629 i915gm_get_display_clock_speed;
10630 else if (IS_I865G(dev))
10631 dev_priv->display.get_display_clock_speed =
10632 i865_get_display_clock_speed;
f0f8a9ce 10633 else if (IS_I85X(dev))
e70236a8
JB		 10634 dev_priv->display.get_display_clock_speed =
10635 i855_get_display_clock_speed;
10636 else /* 852, 830 */
10637 dev_priv->display.get_display_clock_speed =
10638 i830_get_display_clock_speed;
10639
7f8a8569 10640 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10641 if (IS_GEN5(dev)) {
674cf967 10642 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10643 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10644 } else if (IS_GEN6(dev)) {
674cf967 10645 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10646 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10647 } else if (IS_IVYBRIDGE(dev)) {
10648 /* FIXME: detect B0+ stepping and use auto training */
10649 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10650 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10651 dev_priv->display.modeset_global_resources =
10652 ivb_modeset_global_resources;
4e0bbc31 10653 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
c82e4d26 10654 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10655 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10656 dev_priv->display.modeset_global_resources =
10657 haswell_modeset_global_resources;
a0e63c22 10658 }
6067aaea 10659 } else if (IS_G4X(dev)) {
e0dac65e 10660 dev_priv->display.write_eld = g4x_write_eld;
30a970c6
JB		 10661 } else if (IS_VALLEYVIEW(dev)) {
10662 dev_priv->display.modeset_global_resources =
10663 valleyview_modeset_global_resources;
9ca2fe73 10664 dev_priv->display.write_eld = ironlake_write_eld;
e70236a8 10665 }
8c9f3aaf
JB		 10666
10667 /* Default just returns -ENODEV to indicate unsupported */
10668 dev_priv->display.queue_flip = intel_default_queue_flip;
10669
10670 switch (INTEL_INFO(dev)->gen) {
10671 case 2:
10672 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10673 break;
10674
10675 case 3:
10676 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10677 break;
10678
10679 case 4:
10680 case 5:
10681 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10682 break;
10683
10684 case 6:
10685 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10686 break;
7c9017e5 10687 case 7:
4e0bbc31 10688 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 10689 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10690 break;
8c9f3aaf 10691 }
7bd688cd
JN		 10692
10693 intel_panel_init_backlight_funcs(dev);
e70236a8
JB		 10694}
10695
b690e96c
JB		 10696/*
10697 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10698 * resume, or other times. This quirk makes sure that's the case for
10699 * affected systems.
10700 */
0206e353 10701static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10702{
10703 struct drm_i915_private *dev_priv = dev->dev_private;
10704
10705 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10706 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10707}
10708
435793df
KP		 10709/*
10710 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10711 */
10712static void quirk_ssc_force_disable(struct drm_device *dev)
10713{
10714 struct drm_i915_private *dev_priv = dev->dev_private;
10715 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10716 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10717}
10718
4dca20ef 10719/*
5a15ab5b
CE		 10720 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10721 * brightness value
4dca20ef
CE		 10722 */
10723static void quirk_invert_brightness(struct drm_device *dev)
10724{
10725 struct drm_i915_private *dev_priv = dev->dev_private;
10726 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10727 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10728}
10729
b690e96c
JB		 10730struct intel_quirk {
10731 int device;
10732 int subsystem_vendor;
10733 int subsystem_device;
10734 void (*hook)(struct drm_device *dev);
10735};
10736
5f85f176
EE		 10737/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10738struct intel_dmi_quirk {
10739 void (*hook)(struct drm_device *dev);
10740 const struct dmi_system_id (*dmi_id_list)[];
10741};
10742
10743static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10744{
10745 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10746 return 1;
10747}
10748
10749static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10750 {
10751 .dmi_id_list = &(const struct dmi_system_id[]) {
10752 {
10753 .callback = intel_dmi_reverse_brightness,
10754 .ident = "NCR Corporation",
10755 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10756 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10757 },
10758 },
10759 { } /* terminating entry */
10760 },
10761 .hook = quirk_invert_brightness,
10762 },
10763};
10764
c43b5634 10765static struct intel_quirk intel_quirks[] = {
b690e96c 10766 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10767 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10768
b690e96c
JB		 10769 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10770 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10771
b690e96c
JB		 10772 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10773 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10774
a4945f95 10775 /* 830 needs to leave pipe A & dpll A up */
dcdaed6e 10776 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10777
10778 /* Lenovo U160 cannot use SSC on LVDS */
10779 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10780
10781 /* Sony Vaio Y cannot use SSC on LVDS */
10782 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10783
ee1452d7
JN		 10784 /*
10785 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10786 * seem to use inverted backlight PWM.
10787 */
10788 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
b690e96c
JB		 10789};
10790
10791static void intel_init_quirks(struct drm_device *dev)
10792{
10793 struct pci_dev *d = dev->pdev;
10794 int i;
10795
10796 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10797 struct intel_quirk *q = &intel_quirks[i];
10798
10799 if (d->device == q->device &&
10800 (d->subsystem_vendor == q->subsystem_vendor ||
10801 q->subsystem_vendor == PCI_ANY_ID) &&
10802 (d->subsystem_device == q->subsystem_device ||
10803 q->subsystem_device == PCI_ANY_ID))
10804 q->hook(dev);
10805 }
5f85f176
EE		 10806 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10807 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10808 intel_dmi_quirks[i].hook(dev);
10809 }
b690e96c
JB		 10810}
10811
9cce37f4
JB		 10812/* Disable the VGA plane that we never use */
10813static void i915_disable_vga(struct drm_device *dev)
10814{
10815 struct drm_i915_private *dev_priv = dev->dev_private;
10816 u8 sr1;
766aa1c4 10817 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10818
10819 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10820 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10821 sr1 = inb(VGA_SR_DATA);
10822 outb(sr1 | 1<<5, VGA_SR_DATA);
10823 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10824 udelay(300);
10825
10826 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10827 POSTING_READ(vga_reg);
10828}
10829
f817586c
DV		 10830void intel_modeset_init_hw(struct drm_device *dev)
10831{
a8f78b58
ED		 10832 intel_prepare_ddi(dev);
10833
f817586c
DV		 10834 intel_init_clock_gating(dev);
10835
5382f5f3 10836 intel_reset_dpio(dev);
40e9cf64 10837
79f5b2c7 10838 mutex_lock(&dev->struct_mutex);
8090c6b9 10839 intel_enable_gt_powersave(dev);
79f5b2c7 10840 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10841}
10842
7d708ee4
ID		 10843void intel_modeset_suspend_hw(struct drm_device *dev)
10844{
10845 intel_suspend_hw(dev);
10846}
10847
79e53945
JB		 10848void intel_modeset_init(struct drm_device *dev)
10849{
652c393a 10850 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10851 int i, j, ret;
79e53945
JB		 10852
10853 drm_mode_config_init(dev);
10854
10855 dev->mode_config.min_width = 0;
10856 dev->mode_config.min_height = 0;
10857
019d96cb
DA		 10858 dev->mode_config.preferred_depth = 24;
10859 dev->mode_config.prefer_shadow = 1;
10860
e6ecefaa 10861 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10862
b690e96c
JB		 10863 intel_init_quirks(dev);
10864
1fa61106
ED		 10865 intel_init_pm(dev);
10866
e3c74757
BW		 10867 if (INTEL_INFO(dev)->num_pipes == 0)
10868 return;
10869
e70236a8
JB		 10870 intel_init_display(dev);
10871
a6c45cf0
CW		 10872 if (IS_GEN2(dev)) {
10873 dev->mode_config.max_width = 2048;
10874 dev->mode_config.max_height = 2048;
10875 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10876 dev->mode_config.max_width = 4096;
10877 dev->mode_config.max_height = 4096;
79e53945 10878 } else {
a6c45cf0
CW		 10879 dev->mode_config.max_width = 8192;
10880 dev->mode_config.max_height = 8192;
79e53945 10881 }
5d4545ae 10882 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10883
28c97730 10884 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10885 INTEL_INFO(dev)->num_pipes,
10886 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10887
08e2a7de 10888 for_each_pipe(i) {
79e53945 10889 intel_crtc_init(dev, i);
7f1f3851
JB		 10890 for (j = 0; j < dev_priv->num_plane; j++) {
10891 ret = intel_plane_init(dev, i, j);
10892 if (ret)
06da8da2
VS		 10893 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10894 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10895 }
79e53945
JB		 10896 }
10897
f42bb70d 10898 intel_init_dpio(dev);
5382f5f3 10899 intel_reset_dpio(dev);
f42bb70d 10900
79f689aa 10901 intel_cpu_pll_init(dev);
e72f9fbf 10902 intel_shared_dpll_init(dev);
ee7b9f93 10903
9cce37f4
JB		 10904 /* Just disable it once at startup */
10905 i915_disable_vga(dev);
79e53945 10906 intel_setup_outputs(dev);
11be49eb
CW		 10907
10908 /* Just in case the BIOS is doing something questionable. */
10909 intel_disable_fbc(dev);
2c7111db
CW		 10910}
10911
24929352
DV		 10912static void
10913intel_connector_break_all_links(struct intel_connector *connector)
10914{
10915 connector->base.dpms = DRM_MODE_DPMS_OFF;
10916 connector->base.encoder = NULL;
10917 connector->encoder->connectors_active = false;
10918 connector->encoder->base.crtc = NULL;
10919}
10920
7fad798e
DV		 10921static void intel_enable_pipe_a(struct drm_device *dev)
10922{
10923 struct intel_connector *connector;
10924 struct drm_connector *crt = NULL;
10925 struct intel_load_detect_pipe load_detect_temp;
10926
10927 /* We can't just switch on the pipe A, we need to set things up with a
10928 * proper mode and output configuration. As a gross hack, enable pipe A
10929 * by enabling the load detect pipe once. */
10930 list_for_each_entry(connector,
10931 &dev->mode_config.connector_list,
10932 base.head) {
10933 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10934 crt = &connector->base;
10935 break;
10936 }
10937 }
10938
10939 if (!crt)
10940 return;
10941
10942 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10943 intel_release_load_detect_pipe(crt, &load_detect_temp);
10944
652c393a 10945
7fad798e
DV		 10946}
10947
fa555837
DV		 10948static bool
10949intel_check_plane_mapping(struct intel_crtc *crtc)
10950{
7eb552ae
BW		 10951 struct drm_device *dev = crtc->base.dev;
10952 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10953 u32 reg, val;
10954
7eb552ae 10955 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10956 return true;
10957
10958 reg = DSPCNTR(!crtc->plane);
10959 val = I915_READ(reg);
10960
10961 if ((val & DISPLAY_PLANE_ENABLE) &&
10962 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10963 return false;
10964
10965 return true;
10966}
10967
24929352
DV		 10968static void intel_sanitize_crtc(struct intel_crtc *crtc)
10969{
10970 struct drm_device *dev = crtc->base.dev;
10971 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10972 u32 reg;
24929352 10973
24929352 10974 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10975 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10976 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10977
10978 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10979 * disable the crtc (and hence change the state) if it is wrong. Note
10980 * that gen4+ has a fixed plane -> pipe mapping. */
10981 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10982 struct intel_connector *connector;
10983 bool plane;
10984
24929352
DV		 10985 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10986 crtc->base.base.id);
10987
10988 /* Pipe has the wrong plane attached and the plane is active.
10989 * Temporarily change the plane mapping and disable everything
10990 * ... */
10991 plane = crtc->plane;
10992 crtc->plane = !plane;
10993 dev_priv->display.crtc_disable(&crtc->base);
10994 crtc->plane = plane;
10995
10996 /* ... and break all links. */
10997 list_for_each_entry(connector, &dev->mode_config.connector_list,
10998 base.head) {
10999 if (connector->encoder->base.crtc != &crtc->base)
11000 continue;
11001
11002 intel_connector_break_all_links(connector);
11003 }
11004
11005 WARN_ON(crtc->active);
11006 crtc->base.enabled = false;
11007 }
24929352 11008
7fad798e
DV		 11009 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11010 crtc->pipe == PIPE_A && !crtc->active) {
11011 /* BIOS forgot to enable pipe A, this mostly happens after
11012 * resume. Force-enable the pipe to fix this, the update_dpms
11013 * call below we restore the pipe to the right state, but leave
11014 * the required bits on. */
11015 intel_enable_pipe_a(dev);
11016 }
11017
24929352
DV		 11018 /* Adjust the state of the output pipe according to whether we
11019 * have active connectors/encoders. */
11020 intel_crtc_update_dpms(&crtc->base);
11021
11022 if (crtc->active != crtc->base.enabled) {
11023 struct intel_encoder *encoder;
11024
11025 /* This can happen either due to bugs in the get_hw_state
11026 * functions or because the pipe is force-enabled due to the
11027 * pipe A quirk. */
11028 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11029 crtc->base.base.id,
11030 crtc->base.enabled ? "enabled" : "disabled",
11031 crtc->active ? "enabled" : "disabled");
11032
11033 crtc->base.enabled = crtc->active;
11034
11035 /* Because we only establish the connector -> encoder ->
11036 * crtc links if something is active, this means the
11037 * crtc is now deactivated. Break the links. connector
11038 * -> encoder links are only establish when things are
11039 * actually up, hence no need to break them. */
11040 WARN_ON(crtc->active);
11041
11042 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11043 WARN_ON(encoder->connectors_active);
11044 encoder->base.crtc = NULL;
11045 }
11046 }
11047}
11048
11049static void intel_sanitize_encoder(struct intel_encoder *encoder)
11050{
11051 struct intel_connector *connector;
11052 struct drm_device *dev = encoder->base.dev;
11053
11054 /* We need to check both for a crtc link (meaning that the
11055 * encoder is active and trying to read from a pipe) and the
11056 * pipe itself being active. */
11057 bool has_active_crtc = encoder->base.crtc &&
11058 to_intel_crtc(encoder->base.crtc)->active;
11059
11060 if (encoder->connectors_active && !has_active_crtc) {
11061 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11062 encoder->base.base.id,
11063 drm_get_encoder_name(&encoder->base));
11064
11065 /* Connector is active, but has no active pipe. This is
11066 * fallout from our resume register restoring. Disable
11067 * the encoder manually again. */
11068 if (encoder->base.crtc) {
11069 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11070 encoder->base.base.id,
11071 drm_get_encoder_name(&encoder->base));
11072 encoder->disable(encoder);
11073 }
11074
11075 /* Inconsistent output/port/pipe state happens presumably due to
11076 * a bug in one of the get_hw_state functions. Or someplace else
11077 * in our code, like the register restore mess on resume. Clamp
11078 * things to off as a safer default. */
11079 list_for_each_entry(connector,
11080 &dev->mode_config.connector_list,
11081 base.head) {
11082 if (connector->encoder != encoder)
11083 continue;
11084
11085 intel_connector_break_all_links(connector);
11086 }
11087 }
11088 /* Enabled encoders without active connectors will be fixed in
11089 * the crtc fixup. */
11090}
11091
44cec740 11092void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 11093{
11094 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 11095 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 11096
8dc8a27c
PZ		 11097 /* This function can be called both from intel_modeset_setup_hw_state or
11098 * at a very early point in our resume sequence, where the power well
11099 * structures are not yet restored. Since this function is at a very
11100 * paranoid "someone might have enabled VGA while we were not looking"
11101 * level, just check if the power well is enabled instead of trying to
11102 * follow the "don't touch the power well if we don't need it" policy
11103 * the rest of the driver uses. */
f9e711e9 11104 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
6aedd1f5 11105 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 11106 return;
11107
e1553faa 11108 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
0fde901f 11109 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 11110 i915_disable_vga(dev);
0fde901f
KM		 11111 }
11112}
11113
30e984df 11114static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 11115{
11116 struct drm_i915_private *dev_priv = dev->dev_private;
11117 enum pipe pipe;
24929352
DV		 11118 struct intel_crtc *crtc;
11119 struct intel_encoder *encoder;
11120 struct intel_connector *connector;
5358901f 11121 int i;
24929352 11122
0e8ffe1b
DV		 11123 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11124 base.head) {
88adfff1 11125 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 11126
0e8ffe1b
DV		 11127 crtc->active = dev_priv->display.get_pipe_config(crtc,
11128 &crtc->config);
24929352
DV		 11129
11130 crtc->base.enabled = crtc->active;
4c445e0e 11131 crtc->primary_enabled = crtc->active;
24929352
DV		 11132
11133 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11134 crtc->base.base.id,
11135 crtc->active ? "enabled" : "disabled");
11136 }
11137
5358901f 11138 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 11139 if (HAS_DDI(dev))
6441ab5f
PZ		 11140 intel_ddi_setup_hw_pll_state(dev);
11141
5358901f
DV		 11142 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11143 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11144
11145 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11146 pll->active = 0;
11147 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11148 base.head) {
11149 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11150 pll->active++;
11151 }
11152 pll->refcount = pll->active;
11153
35c95375
DV		 11154 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11155 pll->name, pll->refcount, pll->on);
5358901f
DV		 11156 }
11157
24929352
DV		 11158 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11159 base.head) {
11160 pipe = 0;
11161
11162 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 11163 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11164 encoder->base.crtc = &crtc->base;
1d37b689 11165 encoder->get_config(encoder, &crtc->config);
24929352
DV		 11166 } else {
11167 encoder->base.crtc = NULL;
11168 }
11169
11170 encoder->connectors_active = false;
6f2bcceb 11171 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352
DV		 11172 encoder->base.base.id,
11173 drm_get_encoder_name(&encoder->base),
11174 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 11175 pipe_name(pipe));
24929352
DV		 11176 }
11177
11178 list_for_each_entry(connector, &dev->mode_config.connector_list,
11179 base.head) {
11180 if (connector->get_hw_state(connector)) {
11181 connector->base.dpms = DRM_MODE_DPMS_ON;
11182 connector->encoder->connectors_active = true;
11183 connector->base.encoder = &connector->encoder->base;
11184 } else {
11185 connector->base.dpms = DRM_MODE_DPMS_OFF;
11186 connector->base.encoder = NULL;
11187 }
11188 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11189 connector->base.base.id,
11190 drm_get_connector_name(&connector->base),
11191 connector->base.encoder ? "enabled" : "disabled");
11192 }
30e984df
DV		 11193}
11194
11195/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11196 * and i915 state tracking structures. */
11197void intel_modeset_setup_hw_state(struct drm_device *dev,
11198 bool force_restore)
11199{
11200 struct drm_i915_private *dev_priv = dev->dev_private;
11201 enum pipe pipe;
30e984df
DV		 11202 struct intel_crtc *crtc;
11203 struct intel_encoder *encoder;
35c95375 11204 int i;
30e984df
DV		 11205
11206 intel_modeset_readout_hw_state(dev);
24929352 11207
babea61d
JB		 11208 /*
11209 * Now that we have the config, copy it to each CRTC struct
11210 * Note that this could go away if we move to using crtc_config
11211 * checking everywhere.
11212 */
11213 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11214 base.head) {
11215 if (crtc->active && i915_fastboot) {
11216 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11217
11218 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11219 crtc->base.base.id);
11220 drm_mode_debug_printmodeline(&crtc->base.mode);
11221 }
11222 }
11223
24929352
DV		 11224 /* HW state is read out, now we need to sanitize this mess. */
11225 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11226 base.head) {
11227 intel_sanitize_encoder(encoder);
11228 }
11229
11230 for_each_pipe(pipe) {
11231 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11232 intel_sanitize_crtc(crtc);
c0b03411 11233 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 11234 }
9a935856 11235
35c95375
DV		 11236 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11237 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11238
11239 if (!pll->on || pll->active)
11240 continue;
11241
11242 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11243
11244 pll->disable(dev_priv, pll);
11245 pll->on = false;
11246 }
11247
96f90c54 11248 if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 11249 ilk_wm_get_hw_state(dev);
11250
45e2b5f6 11251 if (force_restore) {
7d0bc1ea
VS		 11252 i915_redisable_vga(dev);
11253
f30da187
DV		 11254 /*
11255 * We need to use raw interfaces for restoring state to avoid
11256 * checking (bogus) intermediate states.
11257 */
45e2b5f6 11258 for_each_pipe(pipe) {
b5644d05
JB		 11259 struct drm_crtc *crtc =
11260 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 11261
11262 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11263 crtc->fb);
45e2b5f6
DV		 11264 }
11265 } else {
11266 intel_modeset_update_staged_output_state(dev);
11267 }
8af6cf88
DV		 11268
11269 intel_modeset_check_state(dev);
2e938892
DV		 11270
11271 drm_mode_config_reset(dev);
2c7111db
CW		 11272}
11273
11274void intel_modeset_gem_init(struct drm_device *dev)
11275{
1833b134 11276 intel_modeset_init_hw(dev);
02e792fb
DV		 11277
11278 intel_setup_overlay(dev);
24929352 11279
45e2b5f6 11280 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 11281}
11282
11283void intel_modeset_cleanup(struct drm_device *dev)
11284{
652c393a
JB		 11285 struct drm_i915_private *dev_priv = dev->dev_private;
11286 struct drm_crtc *crtc;
d9255d57 11287 struct drm_connector *connector;
652c393a 11288
fd0c0642
DV		 11289 /*
11290 * Interrupts and polling as the first thing to avoid creating havoc.
11291 * Too much stuff here (turning of rps, connectors, ...) would
11292 * experience fancy races otherwise.
11293 */
11294 drm_irq_uninstall(dev);
11295 cancel_work_sync(&dev_priv->hotplug_work);
11296 /*
11297 * Due to the hpd irq storm handling the hotplug work can re-arm the
11298 * poll handlers. Hence disable polling after hpd handling is shut down.
11299 */
f87ea761 11300 drm_kms_helper_poll_fini(dev);
fd0c0642 11301
652c393a
JB		 11302 mutex_lock(&dev->struct_mutex);
11303
723bfd70
JB		 11304 intel_unregister_dsm_handler();
11305
652c393a
JB		 11306 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11307 /* Skip inactive CRTCs */
11308 if (!crtc->fb)
11309 continue;
11310
3dec0095 11311 intel_increase_pllclock(crtc);
652c393a
JB		 11312 }
11313
973d04f9 11314 intel_disable_fbc(dev);
e70236a8 11315
8090c6b9 11316 intel_disable_gt_powersave(dev);
0cdab21f 11317
930ebb46
DV		 11318 ironlake_teardown_rc6(dev);
11319
69341a5e
KH		 11320 mutex_unlock(&dev->struct_mutex);
11321
1630fe75
CW		 11322 /* flush any delayed tasks or pending work */
11323 flush_scheduled_work();
11324
db31af1d
JN		 11325 /* destroy the backlight and sysfs files before encoders/connectors */
11326 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11327 intel_panel_destroy_backlight(connector);
d9255d57 11328 drm_sysfs_connector_remove(connector);
db31af1d 11329 }
d9255d57 11330
79e53945 11331 drm_mode_config_cleanup(dev);
4d7bb011
DV		 11332
11333 intel_cleanup_overlay(dev);
79e53945
JB		 11334}
11335
f1c79df3
ZW		 11336/*
11337 * Return which encoder is currently attached for connector.
11338 */
df0e9248 11339struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 11340{
df0e9248
CW		 11341 return &intel_attached_encoder(connector)->base;
11342}
f1c79df3 11343
df0e9248
CW		 11344void intel_connector_attach_encoder(struct intel_connector *connector,
11345 struct intel_encoder *encoder)
11346{
11347 connector->encoder = encoder;
11348 drm_mode_connector_attach_encoder(&connector->base,
11349 &encoder->base);
79e53945 11350}
28d52043
DA		 11351
11352/*
11353 * set vga decode state - true == enable VGA decode
11354 */
11355int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11356{
11357 struct drm_i915_private *dev_priv = dev->dev_private;
11358 u16 gmch_ctrl;
11359
11360 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11361 if (state)
11362 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11363 else
11364 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11365 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11366 return 0;
11367}
c4a1d9e4 11368
c4a1d9e4 11369struct intel_display_error_state {
ff57f1b0
PZ		 11370
11371 u32 power_well_driver;
11372
63b66e5b
CW		 11373 int num_transcoders;
11374
c4a1d9e4
CW		 11375 struct intel_cursor_error_state {
11376 u32 control;
11377 u32 position;
11378 u32 base;
11379 u32 size;
52331309 11380 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 11381
11382 struct intel_pipe_error_state {
ddf9c536 11383 bool power_domain_on;
c4a1d9e4 11384 u32 source;
52331309 11385 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 11386
11387 struct intel_plane_error_state {
11388 u32 control;
11389 u32 stride;
11390 u32 size;
11391 u32 pos;
11392 u32 addr;
11393 u32 surface;
11394 u32 tile_offset;
52331309 11395 } plane[I915_MAX_PIPES];
63b66e5b
CW		 11396
11397 struct intel_transcoder_error_state {
ddf9c536 11398 bool power_domain_on;
63b66e5b
CW		 11399 enum transcoder cpu_transcoder;
11400
11401 u32 conf;
11402
11403 u32 htotal;
11404 u32 hblank;
11405 u32 hsync;
11406 u32 vtotal;
11407 u32 vblank;
11408 u32 vsync;
11409 } transcoder[4];
c4a1d9e4
CW		 11410};
11411
11412struct intel_display_error_state *
11413intel_display_capture_error_state(struct drm_device *dev)
11414{
0206e353 11415 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 11416 struct intel_display_error_state *error;
63b66e5b
CW		 11417 int transcoders[] = {
11418 TRANSCODER_A,
11419 TRANSCODER_B,
11420 TRANSCODER_C,
11421 TRANSCODER_EDP,
11422 };
c4a1d9e4
CW		 11423 int i;
11424
63b66e5b
CW		 11425 if (INTEL_INFO(dev)->num_pipes == 0)
11426 return NULL;
11427
9d1cb914 11428 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 11429 if (error == NULL)
11430 return NULL;
11431
190be112 11432 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 11433 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11434
52331309 11435 for_each_pipe(i) {
ddf9c536
ID		 11436 error->pipe[i].power_domain_on =
11437 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11438 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 11439 continue;
11440
a18c4c3d
PZ		 11441 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11442 error->cursor[i].control = I915_READ(CURCNTR(i));
11443 error->cursor[i].position = I915_READ(CURPOS(i));
11444 error->cursor[i].base = I915_READ(CURBASE(i));
11445 } else {
11446 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11447 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11448 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11449 }
c4a1d9e4
CW		 11450
11451 error->plane[i].control = I915_READ(DSPCNTR(i));
11452 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11453 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11454 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11455 error->plane[i].pos = I915_READ(DSPPOS(i));
11456 }
ca291363
PZ		 11457 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11458 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11459 if (INTEL_INFO(dev)->gen >= 4) {
11460 error->plane[i].surface = I915_READ(DSPSURF(i));
11461 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11462 }
11463
c4a1d9e4 11464 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11465 }
11466
11467 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11468 if (HAS_DDI(dev_priv->dev))
11469 error->num_transcoders++; /* Account for eDP. */
11470
11471 for (i = 0; i < error->num_transcoders; i++) {
11472 enum transcoder cpu_transcoder = transcoders[i];
11473
ddf9c536 11474 error->transcoder[i].power_domain_on =
38cc1daf
PZ		 11475 intel_display_power_enabled_sw(dev,
11476 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 11477 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 11478 continue;
11479
63b66e5b
CW		 11480 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11481
11482 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11483 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11484 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11485 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11486 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11487 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11488 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11489 }
11490
11491 return error;
11492}
11493
edc3d884
MK		 11494#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11495
c4a1d9e4 11496void
edc3d884 11497intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11498 struct drm_device *dev,
11499 struct intel_display_error_state *error)
11500{
11501 int i;
11502
63b66e5b
CW		 11503 if (!error)
11504 return;
11505
edc3d884 11506 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 11507 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 11508 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11509 error->power_well_driver);
52331309 11510 for_each_pipe(i) {
edc3d884 11511 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 11512 err_printf(m, " Power: %s\n",
11513 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 11514 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11515
11516 err_printf(m, "Plane [%d]:\n", i);
11517 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11518 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11519 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11520 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11521 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11522 }
4b71a570 11523 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11524 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11525 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11526 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11527 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11528 }
11529
edc3d884
MK		 11530 err_printf(m, "Cursor [%d]:\n", i);
11531 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11532 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11533 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11534 }
63b66e5b
CW		 11535
11536 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 11537 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 11538 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 11539 err_printf(m, " Power: %s\n",
11540 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 11541 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11542 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11543 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11544 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11545 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11546 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11547 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11548 }
c4a1d9e4 11549}
Linux kernel - Deliverables
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