drm/i915: add opregion function to notify bios of adapter power state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB
28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH
40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB
48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL
53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB
59} intel_range_t;
60
61typedef struct {
0206e353
AJ
62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB
64} intel_p2_t;
65
d4906093
ML
66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
2377b741
JB
72/* FDI */
73#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
d2acd215
DV
75int
76intel_pch_rawclk(struct drm_device *dev)
77{
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83}
84
021357ac
CW
85static inline u32 /* units of 100MHz */
86intel_fdi_link_freq(struct drm_device *dev)
87{
8b99e68c
CW
88 if (IS_GEN5(dev)) {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 } else
92 return 27;
021357ac
CW
93}
94
5d536e28 95static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ
96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
273e27ca
EA
104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP
106};
107
5d536e28
DV
108static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
119};
120
e4b36699 121static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
273e27ca
EA
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ
135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ
139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
145};
146
147static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP
158};
159
273e27ca 160
e4b36699 161static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA
162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
171 .p2_slow = 10,
172 .p2_fast = 10
044c7c41 173 },
e4b36699
KP
174};
175
176static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA
177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
187};
188
189static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA
190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
044c7c41 200 },
e4b36699
KP
201};
202
203static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA
204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
044c7c41 214 },
e4b36699
KP
215};
216
f2b115e6 217static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ
218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 220 /* Pineview's Ncounter is a ring counter */
0206e353
AJ
221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
273e27ca 223 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ
224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
230};
231
f2b115e6 232static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ
233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP
243};
244
273e27ca
EA
245/* Ironlake / Sandybridge
246 *
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
249 */
b91ad0ec 250static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
261};
262
b91ad0ec 263static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
274};
275
276static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW
287};
288
273e27ca 289/* LVDS 100mhz refclk limits. */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
0206e353 298 .p1 = { .min = 2, .max = 8 },
273e27ca
EA
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
0206e353 311 .p1 = { .min = 2, .max = 6 },
273e27ca
EA
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY
314};
315
a0c4da24
JB
316static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
75e53986 324 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB
325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB
327};
328
329static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB
332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB
340};
341
342static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 345 .n = { .min = 1, .max = 7 },
74a4dd2e 346 .m = { .min = 22, .max = 450 },
a0c4da24
JB
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB
353};
354
1b894b59
CW
355static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 int refclk)
2c07245f 357{
b91ad0ec 358 struct drm_device *dev = crtc->dev;
2c07245f 359 const intel_limit_t *limit;
b91ad0ec
ZW
360
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 362 if (intel_is_dual_link_lvds(dev)) {
1b894b59 363 if (refclk == 100000)
b91ad0ec
ZW
364 limit = &intel_limits_ironlake_dual_lvds_100m;
365 else
366 limit = &intel_limits_ironlake_dual_lvds;
367 } else {
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW
369 limit = &intel_limits_ironlake_single_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_single_lvds;
372 }
c6bb3538 373 } else
b91ad0ec 374 limit = &intel_limits_ironlake_dac;
2c07245f
ZW
375
376 return limit;
377}
378
044c7c41
ML
379static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
380{
381 struct drm_device *dev = crtc->dev;
044c7c41
ML
382 const intel_limit_t *limit;
383
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 385 if (intel_is_dual_link_lvds(dev))
e4b36699 386 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 387 else
e4b36699 388 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML
389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 391 limit = &intel_limits_g4x_hdmi;
044c7c41 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 393 limit = &intel_limits_g4x_sdvo;
044c7c41 394 } else /* The option is for other outputs */
e4b36699 395 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML
396
397 return limit;
398}
399
1b894b59 400static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB
401{
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
404
bad720ff 405 if (HAS_PCH_SPLIT(dev))
1b894b59 406 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 407 else if (IS_G4X(dev)) {
044c7c41 408 limit = intel_g4x_limit(crtc);
f2b115e6 409 } else if (IS_PINEVIEW(dev)) {
2177832f 410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 411 limit = &intel_limits_pineview_lvds;
2177832f 412 else
f2b115e6 413 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB
414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
419 else
420 limit = &intel_limits_vlv_dp;
a6c45cf0
CW
421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
79e53945
JB
426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 428 limit = &intel_limits_i8xx_lvds;
5d536e28 429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 430 limit = &intel_limits_i8xx_dvo;
5d536e28
DV
431 else
432 limit = &intel_limits_i8xx_dac;
79e53945
JB
433 }
434 return limit;
435}
436
f2b115e6
AJ
437/* m1 is reserved as 0 in Pineview, n is a ring counter */
438static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 439{
2177832f
SL
440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444}
445
7429e9d4
DV
446static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447{
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449}
450
ac58c3f0 451static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 452{
7429e9d4 453 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB
454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457}
458
79e53945
JB
459/**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
4ef69c7a 462bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 463{
4ef69c7a 464 struct drm_device *dev = crtc->dev;
4ef69c7a
CW
465 struct intel_encoder *encoder;
466
6c2b7c12
DV
467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
4ef69c7a
CW
469 return true;
470
471 return false;
79e53945
JB
472}
473
7c04d1d9 474#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB
475/**
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
478 */
479
1b894b59
CW
480static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
79e53945 483{
79e53945 484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 485 INTELPllInvalid("p1 out of range\n");
79e53945 486 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 487 INTELPllInvalid("p out of range\n");
79e53945 488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 489 INTELPllInvalid("m2 out of range\n");
79e53945 490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 491 INTELPllInvalid("m1 out of range\n");
f2b115e6 492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 493 INTELPllInvalid("m1 <= m2\n");
79e53945 494 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 495 INTELPllInvalid("m out of range\n");
79e53945 496 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 497 INTELPllInvalid("n out of range\n");
79e53945 498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 499 INTELPllInvalid("vco out of range\n");
79e53945
JB
500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
502 */
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 504 INTELPllInvalid("dot out of range\n");
79e53945
JB
505
506 return true;
507}
508
d4906093 509static bool
ee9300bb 510i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP
511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
79e53945
JB
513{
514 struct drm_device *dev = crtc->dev;
79e53945 515 intel_clock_t clock;
79e53945
JB
516 int err = target;
517
a210b028 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 519 /*
a210b028
DV
520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
79e53945 523 */
1974cad0 524 if (intel_is_dual_link_lvds(dev))
79e53945
JB
525 clock.p2 = limit->p2.p2_fast;
526 else
527 clock.p2 = limit->p2.p2_slow;
528 } else {
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
531 else
532 clock.p2 = limit->p2.p2_fast;
533 }
534
0206e353 535 memset(best_clock, 0, sizeof(*best_clock));
79e53945 536
42158660
ZY
537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
538 clock.m1++) {
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 541 if (clock.m2 >= clock.m1)
42158660
ZY
542 break;
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
547 int this_err;
548
ac58c3f0
DV
549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
551 &clock))
552 continue;
553 if (match_clock &&
554 clock.p != match_clock->p)
555 continue;
556
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
559 *best_clock = clock;
560 err = this_err;
561 }
562 }
563 }
564 }
565 }
566
567 return (err != target);
568}
569
570static bool
ee9300bb
DV
571pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
79e53945
JB
574{
575 struct drm_device *dev = crtc->dev;
79e53945 576 intel_clock_t clock;
79e53945
JB
577 int err = target;
578
a210b028 579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 580 /*
a210b028
DV
581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
79e53945 584 */
1974cad0 585 if (intel_is_dual_link_lvds(dev))
79e53945
JB
586 clock.p2 = limit->p2.p2_fast;
587 else
588 clock.p2 = limit->p2.p2_slow;
589 } else {
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
592 else
593 clock.p2 = limit->p2.p2_fast;
594 }
595
0206e353 596 memset(best_clock, 0, sizeof(*best_clock));
79e53945 597
42158660
ZY
598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
599 clock.m1++) {
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY
602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
606 int this_err;
607
ac58c3f0 608 pineview_clock(refclk, &clock);
1b894b59
CW
609 if (!intel_PLL_is_valid(dev, limit,
610 &clock))
79e53945 611 continue;
cec2f356
SP
612 if (match_clock &&
613 clock.p != match_clock->p)
614 continue;
79e53945
JB
615
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
618 *best_clock = clock;
619 err = this_err;
620 }
621 }
622 }
623 }
624 }
625
626 return (err != target);
627}
628
d4906093 629static bool
ee9300bb
DV
630g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
d4906093
ML
633{
634 struct drm_device *dev = crtc->dev;
d4906093
ML
635 intel_clock_t clock;
636 int max_n;
637 bool found;
6ba770dc
AJ
638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
d4906093
ML
640 found = false;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 643 if (intel_is_dual_link_lvds(dev))
d4906093
ML
644 clock.p2 = limit->p2.p2_fast;
645 else
646 clock.p2 = limit->p2.p2_slow;
647 } else {
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
650 else
651 clock.p2 = limit->p2.p2_fast;
652 }
653
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
f77f13e2 656 /* based on hardware requirement, prefer smaller n to precision */
d4906093 657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 658 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML
659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
665 int this_err;
666
ac58c3f0 667 i9xx_clock(refclk, &clock);
1b894b59
CW
668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
d4906093 670 continue;
1b894b59
CW
671
672 this_err = abs(clock.dot - target);
d4906093
ML
673 if (this_err < err_most) {
674 *best_clock = clock;
675 err_most = this_err;
676 max_n = clock.n;
677 found = true;
678 }
679 }
680 }
681 }
682 }
2c07245f
ZW
683 return found;
684}
685
a0c4da24 686static bool
ee9300bb
DV
687vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
a0c4da24
JB
690{
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
692 u32 m, n, fastclk;
f3f08572 693 u32 updrate, minupdate, p;
a0c4da24
JB
694 unsigned long bestppm, ppm, absppm;
695 int dotclk, flag;
696
af447bd3 697 flag = 0;
a0c4da24
JB
698 dotclk = target * 1000;
699 bestppm = 1000000;
700 ppm = absppm = 0;
701 fastclk = dotclk / (2*100);
702 updrate = 0;
703 minupdate = 19200;
a0c4da24
JB
704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
706
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
712 if (p2 > 10)
713 p2 = p2 - 1;
714 p = p1 * p2;
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
719 m = m1 * m2;
720 vco = updrate * m;
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
725 bestppm = 0;
726 flag = 1;
727 }
728 if (absppm < bestppm - 10) {
729 bestppm = absppm;
730 flag = 1;
731 }
732 if (flag) {
733 bestn = n;
734 bestm1 = m1;
735 bestm2 = m2;
736 bestp1 = p1;
737 bestp2 = p2;
738 flag = 0;
739 }
740 }
741 }
742 }
743 }
744 }
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
750
751 return true;
752}
a4fc5ed6 753
a5c961d1
PZ
754enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756{
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
3b117c8f 760 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ
761}
762
a928d536
PZ
763static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772}
773
9d0498a2
JB
774/**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 783{
9d0498a2 784 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 785 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 786
a928d536
PZ
787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
300387c0
CW
792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
9d0498a2 808 /* Wait for vblank interrupt bit to set */
481b6af3
CW
809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
9d0498a2
JB
812 DRM_DEBUG_KMS("vblank wait timed out\n");
813}
814
ab7ad7f6
KP
815/*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB
817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
ab7ad7f6
KP
824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
58e10eb9 830 *
9d0498a2 831 */
58e10eb9 832void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB
833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ
835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
ab7ad7f6
KP
837
838 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 839 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP
840
841 /* Wait for the Pipe State to go off */
58e10eb9
CW
842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 } else {
837ba00f 846 u32 last_line, line_mask;
58e10eb9 847 int reg = PIPEDSL(pipe);
ab7ad7f6
KP
848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
837ba00f
PZ
850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
ab7ad7f6
KP
855 /* Wait for the display line to settle */
856 do {
837ba00f 857 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 858 mdelay(5);
837ba00f 859 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP
860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 }
79e53945
JB
864}
865
b0ea7d37
DL
866/*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875{
876 u32 bit;
877
c36346e3
DL
878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
b0ea7d37
DL
906 }
907
908 return I915_READ(SDEISR) & bit;
909}
910
b24e7179
JB
911static const char *state_string(bool enabled)
912{
913 return enabled ? "on" : "off";
914}
915
916/* Only for pre-ILK configs */
55607e8a
DV
917void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
b24e7179
JB
919{
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930}
b24e7179 931
23538ef1
JN
932/* XXX: the dsi pll is shared between MIPI DSI ports */
933static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
934{
935 u32 val;
936 bool cur_state;
937
938 mutex_lock(&dev_priv->dpio_lock);
939 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
940 mutex_unlock(&dev_priv->dpio_lock);
941
942 cur_state = val & DSI_PLL_VCO_EN;
943 WARN(cur_state != state,
944 "DSI PLL state assertion failure (expected %s, current %s)\n",
945 state_string(state), state_string(cur_state));
946}
947#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
948#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949
55607e8a 950struct intel_shared_dpll *
e2b78267
DV
951intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
952{
953 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
954
a43f6e0f 955 if (crtc->config.shared_dpll < 0)
e2b78267
DV
956 return NULL;
957
a43f6e0f 958 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV
959}
960
040484af 961/* For ILK+ */
55607e8a
DV
962void assert_shared_dpll(struct drm_i915_private *dev_priv,
963 struct intel_shared_dpll *pll,
964 bool state)
040484af 965{
040484af 966 bool cur_state;
5358901f 967 struct intel_dpll_hw_state hw_state;
040484af 968
9d82aa17
ED
969 if (HAS_PCH_LPT(dev_priv->dev)) {
970 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
971 return;
972 }
973
92b27b08 974 if (WARN (!pll,
46edb027 975 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 976 return;
ee7b9f93 977
5358901f 978 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 979 WARN(cur_state != state,
5358901f
DV
980 "%s assertion failure (expected %s, current %s)\n",
981 pll->name, state_string(state), state_string(cur_state));
040484af 982}
040484af
JB
983
984static void assert_fdi_tx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
ad80a810
PZ
990 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
991 pipe);
040484af 992
affa9354
PZ
993 if (HAS_DDI(dev_priv->dev)) {
994 /* DDI does not have a specific FDI_TX register */
ad80a810 995 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 996 val = I915_READ(reg);
ad80a810 997 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED
998 } else {
999 reg = FDI_TX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_TX_ENABLE);
1002 }
040484af
JB
1003 WARN(cur_state != state,
1004 "FDI TX state assertion failure (expected %s, current %s)\n",
1005 state_string(state), state_string(cur_state));
1006}
1007#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1008#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009
1010static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1011 enum pipe pipe, bool state)
1012{
1013 int reg;
1014 u32 val;
1015 bool cur_state;
1016
d63fa0dc
PZ
1017 reg = FDI_RX_CTL(pipe);
1018 val = I915_READ(reg);
1019 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB
1020 WARN(cur_state != state,
1021 "FDI RX state assertion failure (expected %s, current %s)\n",
1022 state_string(state), state_string(cur_state));
1023}
1024#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1025#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026
1027static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1028 enum pipe pipe)
1029{
1030 int reg;
1031 u32 val;
1032
1033 /* ILK FDI PLL is always enabled */
1034 if (dev_priv->info->gen == 5)
1035 return;
1036
bf507ef7 1037 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1038 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED
1039 return;
1040
040484af
JB
1041 reg = FDI_TX_CTL(pipe);
1042 val = I915_READ(reg);
1043 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1044}
1045
55607e8a
DV
1046void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1047 enum pipe pipe, bool state)
040484af
JB
1048{
1049 int reg;
1050 u32 val;
55607e8a 1051 bool cur_state;
040484af
JB
1052
1053 reg = FDI_RX_CTL(pipe);
1054 val = I915_READ(reg);
55607e8a
DV
1055 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1056 WARN(cur_state != state,
1057 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1058 state_string(state), state_string(cur_state));
040484af
JB
1059}
1060
ea0760cf
JB
1061static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1062 enum pipe pipe)
1063{
1064 int pp_reg, lvds_reg;
1065 u32 val;
1066 enum pipe panel_pipe = PIPE_A;
0de3b485 1067 bool locked = true;
ea0760cf
JB
1068
1069 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1070 pp_reg = PCH_PP_CONTROL;
1071 lvds_reg = PCH_LVDS;
1072 } else {
1073 pp_reg = PP_CONTROL;
1074 lvds_reg = LVDS;
1075 }
1076
1077 val = I915_READ(pp_reg);
1078 if (!(val & PANEL_POWER_ON) ||
1079 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1080 locked = false;
1081
1082 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1083 panel_pipe = PIPE_B;
1084
1085 WARN(panel_pipe == pipe && locked,
1086 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1087 pipe_name(pipe));
ea0760cf
JB
1088}
1089
b840d907
JB
1090void assert_pipe(struct drm_i915_private *dev_priv,
1091 enum pipe pipe, bool state)
b24e7179
JB
1092{
1093 int reg;
1094 u32 val;
63d7bbe9 1095 bool cur_state;
702e7a56
PZ
1096 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1097 pipe);
b24e7179 1098
8e636784
DV
1099 /* if we need the pipe A quirk it must be always on */
1100 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1101 state = true;
1102
b97186f0
PZ
1103 if (!intel_display_power_enabled(dev_priv->dev,
1104 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ
1105 cur_state = false;
1106 } else {
1107 reg = PIPECONF(cpu_transcoder);
1108 val = I915_READ(reg);
1109 cur_state = !!(val & PIPECONF_ENABLE);
1110 }
1111
63d7bbe9
JB
1112 WARN(cur_state != state,
1113 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1114 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB
1115}
1116
931872fc
CW
1117static void assert_plane(struct drm_i915_private *dev_priv,
1118 enum plane plane, bool state)
b24e7179
JB
1119{
1120 int reg;
1121 u32 val;
931872fc 1122 bool cur_state;
b24e7179
JB
1123
1124 reg = DSPCNTR(plane);
1125 val = I915_READ(reg);
931872fc
CW
1126 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1127 WARN(cur_state != state,
1128 "plane %c assertion failure (expected %s, current %s)\n",
1129 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB
1130}
1131
931872fc
CW
1132#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1133#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1134
b24e7179
JB
1135static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
653e1026 1138 struct drm_device *dev = dev_priv->dev;
b24e7179
JB
1139 int reg, i;
1140 u32 val;
1141 int cur_pipe;
1142
653e1026
VS
1143 /* Primary planes are fixed to pipes on gen4+ */
1144 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ
1145 reg = DSPCNTR(pipe);
1146 val = I915_READ(reg);
1147 WARN((val & DISPLAY_PLANE_ENABLE),
1148 "plane %c assertion failure, should be disabled but not\n",
1149 plane_name(pipe));
19ec1358 1150 return;
28c05794 1151 }
19ec1358 1152
b24e7179 1153 /* Need to check both planes against the pipe */
08e2a7de 1154 for_each_pipe(i) {
b24e7179
JB
1155 reg = DSPCNTR(i);
1156 val = I915_READ(reg);
1157 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1158 DISPPLANE_SEL_PIPE_SHIFT;
1159 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB
1160 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1161 plane_name(i), pipe_name(pipe));
b24e7179
JB
1162 }
1163}
1164
19332d7a
JB
1165static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
20674eef 1168 struct drm_device *dev = dev_priv->dev;
19332d7a
JB
1169 int reg, i;
1170 u32 val;
1171
20674eef
VS
1172 if (IS_VALLEYVIEW(dev)) {
1173 for (i = 0; i < dev_priv->num_plane; i++) {
1174 reg = SPCNTR(pipe, i);
1175 val = I915_READ(reg);
1176 WARN((val & SP_ENABLE),
1177 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1178 sprite_name(pipe, i), pipe_name(pipe));
1179 }
1180 } else if (INTEL_INFO(dev)->gen >= 7) {
1181 reg = SPRCTL(pipe);
19332d7a 1182 val = I915_READ(reg);
20674eef 1183 WARN((val & SPRITE_ENABLE),
06da8da2 1184 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS
1185 plane_name(pipe), pipe_name(pipe));
1186 } else if (INTEL_INFO(dev)->gen >= 5) {
1187 reg = DVSCNTR(pipe);
19332d7a 1188 val = I915_READ(reg);
20674eef 1189 WARN((val & DVS_ENABLE),
06da8da2 1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1191 plane_name(pipe), pipe_name(pipe));
19332d7a
JB
1192 }
1193}
1194
92f2584a
JB
1195static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1196{
1197 u32 val;
1198 bool enabled;
1199
9d82aa17
ED
1200 if (HAS_PCH_LPT(dev_priv->dev)) {
1201 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1202 return;
1203 }
1204
92f2584a
JB
1205 val = I915_READ(PCH_DREF_CONTROL);
1206 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1207 DREF_SUPERSPREAD_SOURCE_MASK));
1208 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1209}
1210
ab9412ba
DV
1211static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1212 enum pipe pipe)
92f2584a
JB
1213{
1214 int reg;
1215 u32 val;
1216 bool enabled;
1217
ab9412ba 1218 reg = PCH_TRANSCONF(pipe);
92f2584a
JB
1219 val = I915_READ(reg);
1220 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB
1221 WARN(enabled,
1222 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1223 pipe_name(pipe));
92f2584a
JB
1224}
1225
4e634389
KP
1226static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP
1228{
1229 if ((val & DP_PORT_EN) == 0)
1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1234 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1235 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1236 return false;
1237 } else {
1238 if ((val & DP_PIPE_MASK) != (pipe << 30))
1239 return false;
1240 }
1241 return true;
1242}
1243
1519b995
KP
1244static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, u32 val)
1246{
dc0fa718 1247 if ((val & SDVO_ENABLE) == 0)
1519b995
KP
1248 return false;
1249
1250 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1251 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP
1252 return false;
1253 } else {
dc0fa718 1254 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP
1255 return false;
1256 }
1257 return true;
1258}
1259
1260static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe, u32 val)
1262{
1263 if ((val & LVDS_PORT_EN) == 0)
1264 return false;
1265
1266 if (HAS_PCH_CPT(dev_priv->dev)) {
1267 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1268 return false;
1269 } else {
1270 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1271 return false;
1272 }
1273 return true;
1274}
1275
1276static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, u32 val)
1278{
1279 if ((val & ADPA_DAC_ENABLE) == 0)
1280 return false;
1281 if (HAS_PCH_CPT(dev_priv->dev)) {
1282 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 return false;
1284 } else {
1285 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1286 return false;
1287 }
1288 return true;
1289}
1290
291906f1 1291static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1292 enum pipe pipe, int reg, u32 port_sel)
291906f1 1293{
47a05eca 1294 u32 val = I915_READ(reg);
4e634389 1295 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1296 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 reg, pipe_name(pipe));
de9a35ab 1298
75c5da27
DV
1299 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1300 && (val & DP_PIPEB_SELECT),
de9a35ab 1301 "IBX PCH dp port still using transcoder B\n");
291906f1
JB
1302}
1303
1304static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, int reg)
1306{
47a05eca 1307 u32 val = I915_READ(reg);
b70ad586 1308 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1309 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1310 reg, pipe_name(pipe));
de9a35ab 1311
dc0fa718 1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1313 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1314 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB
1315}
1316
1317static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe)
1319{
1320 int reg;
1321 u32 val;
291906f1 1322
f0575e92
KP
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1324 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB
1326
1327 reg = PCH_ADPA;
1328 val = I915_READ(reg);
b70ad586 1329 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1330 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1331 pipe_name(pipe));
291906f1
JB
1332
1333 reg = PCH_LVDS;
1334 val = I915_READ(reg);
b70ad586 1335 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1336 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1337 pipe_name(pipe));
291906f1 1338
e2debe91
PZ
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1340 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB
1342}
1343
426115cf 1344static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1345{
426115cf
DV
1346 struct drm_device *dev = crtc->base.dev;
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 int reg = DPLL(crtc->pipe);
1349 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1350
426115cf 1351 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV
1352
1353 /* No really, not for ILK+ */
1354 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1355
1356 /* PLL is protected by panel, make sure we can write it */
1357 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1358 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1359
426115cf
DV
1360 I915_WRITE(reg, dpll);
1361 POSTING_READ(reg);
1362 udelay(150);
1363
1364 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1365 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1366
1367 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1368 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV
1369
1370 /* We do this three times for luck */
426115cf 1371 I915_WRITE(reg, dpll);
87442f73
DV
1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
426115cf 1374 I915_WRITE(reg, dpll);
87442f73
DV
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
426115cf 1377 I915_WRITE(reg, dpll);
87442f73
DV
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380}
1381
66e3d5c0 1382static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1383{
66e3d5c0
DV
1384 struct drm_device *dev = crtc->base.dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 int reg = DPLL(crtc->pipe);
1387 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1388
66e3d5c0 1389 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1390
63d7bbe9 1391 /* No really, not for ILK+ */
87442f73 1392 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB
1393
1394 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV
1395 if (IS_MOBILE(dev) && !IS_I830(dev))
1396 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1397
66e3d5c0
DV
1398 I915_WRITE(reg, dpll);
1399
1400 /* Wait for the clocks to stabilize. */
1401 POSTING_READ(reg);
1402 udelay(150);
1403
1404 if (INTEL_INFO(dev)->gen >= 4) {
1405 I915_WRITE(DPLL_MD(crtc->pipe),
1406 crtc->config.dpll_hw_state.dpll_md);
1407 } else {
1408 /* The pixel multiplier can only be updated once the
1409 * DPLL is enabled and the clocks are stable.
1410 *
1411 * So write it again.
1412 */
1413 I915_WRITE(reg, dpll);
1414 }
63d7bbe9
JB
1415
1416 /* We do this three times for luck */
66e3d5c0 1417 I915_WRITE(reg, dpll);
63d7bbe9
JB
1418 POSTING_READ(reg);
1419 udelay(150); /* wait for warmup */
66e3d5c0 1420 I915_WRITE(reg, dpll);
63d7bbe9
JB
1421 POSTING_READ(reg);
1422 udelay(150); /* wait for warmup */
66e3d5c0 1423 I915_WRITE(reg, dpll);
63d7bbe9
JB
1424 POSTING_READ(reg);
1425 udelay(150); /* wait for warmup */
1426}
1427
1428/**
50b44a44 1429 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB
1430 * @dev_priv: i915 private structure
1431 * @pipe: pipe PLL to disable
1432 *
1433 * Disable the PLL for @pipe, making sure the pipe is off first.
1434 *
1435 * Note! This is for pre-ILK only.
1436 */
50b44a44 1437static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1438{
63d7bbe9
JB
1439 /* Don't disable pipe A or pipe A PLLs if needed */
1440 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1441 return;
1442
1443 /* Make sure the pipe isn't still relying on us */
1444 assert_pipe_disabled(dev_priv, pipe);
1445
50b44a44
DV
1446 I915_WRITE(DPLL(pipe), 0);
1447 POSTING_READ(DPLL(pipe));
63d7bbe9
JB
1448}
1449
89b667f8
JB
1450void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1451{
1452 u32 port_mask;
1453
1454 if (!port)
1455 port_mask = DPLL_PORTB_READY_MASK;
1456 else
1457 port_mask = DPLL_PORTC_READY_MASK;
1458
1459 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1460 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1461 'B' + port, I915_READ(DPLL(0)));
1462}
1463
92f2584a 1464/**
e72f9fbf 1465 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB
1466 * @dev_priv: i915 private structure
1467 * @pipe: pipe PLL to enable
1468 *
1469 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1470 * drives the transcoder clock.
1471 */
e2b78267 1472static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1473{
e2b78267
DV
1474 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1475 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1476
48da64a8 1477 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1478 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1479 if (WARN_ON(pll == NULL))
48da64a8
CW
1480 return;
1481
1482 if (WARN_ON(pll->refcount == 0))
1483 return;
ee7b9f93 1484
46edb027
DV
1485 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1486 pll->name, pll->active, pll->on,
e2b78267 1487 crtc->base.base.id);
92f2584a 1488
cdbd2316
DV
1489 if (pll->active++) {
1490 WARN_ON(!pll->on);
e9d6944e 1491 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB
1492 return;
1493 }
f4a091c7 1494 WARN_ON(pll->on);
ee7b9f93 1495
46edb027 1496 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1497 pll->enable(dev_priv, pll);
ee7b9f93 1498 pll->on = true;
92f2584a
JB
1499}
1500
e2b78267 1501static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1502{
e2b78267
DV
1503 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1504 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1505
92f2584a
JB
1506 /* PCH only available on ILK+ */
1507 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1508 if (WARN_ON(pll == NULL))
ee7b9f93 1509 return;
92f2584a 1510
48da64a8
CW
1511 if (WARN_ON(pll->refcount == 0))
1512 return;
7a419866 1513
46edb027
DV
1514 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1515 pll->name, pll->active, pll->on,
e2b78267 1516 crtc->base.base.id);
7a419866 1517
48da64a8 1518 if (WARN_ON(pll->active == 0)) {
e9d6944e 1519 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW
1520 return;
1521 }
1522
e9d6944e 1523 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1524 WARN_ON(!pll->on);
cdbd2316 1525 if (--pll->active)
7a419866 1526 return;
ee7b9f93 1527
46edb027 1528 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1529 pll->disable(dev_priv, pll);
ee7b9f93 1530 pll->on = false;
92f2584a
JB
1531}
1532
b8a4f404
PZ
1533static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1534 enum pipe pipe)
040484af 1535{
23670b32 1536 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1537 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1539 uint32_t reg, val, pipeconf_val;
040484af
JB
1540
1541 /* PCH only available on ILK+ */
1542 BUG_ON(dev_priv->info->gen < 5);
1543
1544 /* Make sure PCH DPLL is enabled */
e72f9fbf 1545 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1546 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB
1547
1548 /* FDI must be feeding us bits for PCH ports */
1549 assert_fdi_tx_enabled(dev_priv, pipe);
1550 assert_fdi_rx_enabled(dev_priv, pipe);
1551
23670b32
DV
1552 if (HAS_PCH_CPT(dev)) {
1553 /* Workaround: Set the timing override bit before enabling the
1554 * pch transcoder. */
1555 reg = TRANS_CHICKEN2(pipe);
1556 val = I915_READ(reg);
1557 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1558 I915_WRITE(reg, val);
59c859d6 1559 }
23670b32 1560
ab9412ba 1561 reg = PCH_TRANSCONF(pipe);
040484af 1562 val = I915_READ(reg);
5f7f726d 1563 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB
1564
1565 if (HAS_PCH_IBX(dev_priv->dev)) {
1566 /*
1567 * make the BPC in transcoder be consistent with
1568 * that in pipeconf reg.
1569 */
dfd07d72
DV
1570 val &= ~PIPECONF_BPC_MASK;
1571 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1572 }
5f7f726d
PZ
1573
1574 val &= ~TRANS_INTERLACE_MASK;
1575 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ
1576 if (HAS_PCH_IBX(dev_priv->dev) &&
1577 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1578 val |= TRANS_LEGACY_INTERLACED_ILK;
1579 else
1580 val |= TRANS_INTERLACED;
5f7f726d
PZ
1581 else
1582 val |= TRANS_PROGRESSIVE;
1583
040484af
JB
1584 I915_WRITE(reg, val | TRANS_ENABLE);
1585 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1586 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB
1587}
1588
8fb033d7 1589static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1590 enum transcoder cpu_transcoder)
040484af 1591{
8fb033d7 1592 u32 val, pipeconf_val;
8fb033d7
PZ
1593
1594 /* PCH only available on ILK+ */
1595 BUG_ON(dev_priv->info->gen < 5);
1596
8fb033d7 1597 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1598 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1599 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1600
223a6fdf
PZ
1601 /* Workaround: set timing override bit. */
1602 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1603 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ
1604 I915_WRITE(_TRANSA_CHICKEN2, val);
1605
25f3ef11 1606 val = TRANS_ENABLE;
937bb610 1607 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1608
9a76b1c6
PZ
1609 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1610 PIPECONF_INTERLACED_ILK)
a35f2679 1611 val |= TRANS_INTERLACED;
8fb033d7
PZ
1612 else
1613 val |= TRANS_PROGRESSIVE;
1614
ab9412ba
DV
1615 I915_WRITE(LPT_TRANSCONF, val);
1616 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1617 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ
1618}
1619
b8a4f404
PZ
1620static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1621 enum pipe pipe)
040484af 1622{
23670b32
DV
1623 struct drm_device *dev = dev_priv->dev;
1624 uint32_t reg, val;
040484af
JB
1625
1626 /* FDI relies on the transcoder */
1627 assert_fdi_tx_disabled(dev_priv, pipe);
1628 assert_fdi_rx_disabled(dev_priv, pipe);
1629
291906f1
JB
1630 /* Ports must be off as well */
1631 assert_pch_ports_disabled(dev_priv, pipe);
1632
ab9412ba 1633 reg = PCH_TRANSCONF(pipe);
040484af
JB
1634 val = I915_READ(reg);
1635 val &= ~TRANS_ENABLE;
1636 I915_WRITE(reg, val);
1637 /* wait for PCH transcoder off, transcoder state */
1638 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1639 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV
1640
1641 if (!HAS_PCH_IBX(dev)) {
1642 /* Workaround: Clear the timing override chicken bit again. */
1643 reg = TRANS_CHICKEN2(pipe);
1644 val = I915_READ(reg);
1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(reg, val);
1647 }
040484af
JB
1648}
1649
ab4d966c 1650static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1651{
8fb033d7
PZ
1652 u32 val;
1653
ab9412ba 1654 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1655 val &= ~TRANS_ENABLE;
ab9412ba 1656 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1657 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1658 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1659 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ
1660
1661 /* Workaround: clear timing override bit. */
1662 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1663 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1664 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB
1665}
1666
b24e7179 1667/**
309cfea8 1668 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB
1669 * @dev_priv: i915 private structure
1670 * @pipe: pipe to enable
040484af 1671 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB
1672 *
1673 * Enable @pipe, making sure that various hardware specific requirements
1674 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1675 *
1676 * @pipe should be %PIPE_A or %PIPE_B.
1677 *
1678 * Will wait until the pipe is actually running (i.e. first vblank) before
1679 * returning.
1680 */
040484af 1681static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1682 bool pch_port, bool dsi)
b24e7179 1683{
702e7a56
PZ
1684 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1685 pipe);
1a240d4d 1686 enum pipe pch_transcoder;
b24e7179
JB
1687 int reg;
1688 u32 val;
1689
58c6eaa2
DV
1690 assert_planes_disabled(dev_priv, pipe);
1691 assert_sprites_disabled(dev_priv, pipe);
1692
681e5811 1693 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ
1694 pch_transcoder = TRANSCODER_A;
1695 else
1696 pch_transcoder = pipe;
1697
b24e7179
JB
1698 /*
1699 * A pipe without a PLL won't actually be able to drive bits from
1700 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1701 * need the check.
1702 */
1703 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN
1704 if (dsi)
1705 assert_dsi_pll_enabled(dev_priv);
1706 else
1707 assert_pll_enabled(dev_priv, pipe);
040484af
JB
1708 else {
1709 if (pch_port) {
1710 /* if driving the PCH, we need FDI enabled */
cc391bbb 1711 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV
1712 assert_fdi_tx_pll_enabled(dev_priv,
1713 (enum pipe) cpu_transcoder);
040484af
JB
1714 }
1715 /* FIXME: assert CPU port conditions for SNB+ */
1716 }
b24e7179 1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW
1720 if (val & PIPECONF_ENABLE)
1721 return;
1722
1723 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB
1724 intel_wait_for_vblank(dev_priv->dev, pipe);
1725}
1726
1727/**
309cfea8 1728 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB
1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe to disable
1731 *
1732 * Disable @pipe, making sure that various hardware specific requirements
1733 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1734 *
1735 * @pipe should be %PIPE_A or %PIPE_B.
1736 *
1737 * Will wait until the pipe has shut down before returning.
1738 */
1739static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1740 enum pipe pipe)
1741{
702e7a56
PZ
1742 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1743 pipe);
b24e7179
JB
1744 int reg;
1745 u32 val;
1746
1747 /*
1748 * Make sure planes won't keep trying to pump pixels to us,
1749 * or we might hang the display.
1750 */
1751 assert_planes_disabled(dev_priv, pipe);
19332d7a 1752 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB
1753
1754 /* Don't disable pipe A or pipe A PLLs if needed */
1755 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1756 return;
1757
702e7a56 1758 reg = PIPECONF(cpu_transcoder);
b24e7179 1759 val = I915_READ(reg);
00d70b15
CW
1760 if ((val & PIPECONF_ENABLE) == 0)
1761 return;
1762
1763 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB
1764 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1765}
1766
d74362c9
KP
1767/*
1768 * Plane regs are double buffered, going from enabled->disabled needs a
1769 * trigger in order to latch. The display address reg provides this.
1770 */
6f1d69b0 1771void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP
1772 enum plane plane)
1773{
14f86147
DL
1774 if (dev_priv->info->gen >= 4)
1775 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1776 else
1777 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP
1778}
1779
b24e7179
JB
1780/**
1781 * intel_enable_plane - enable a display plane on a given pipe
1782 * @dev_priv: i915 private structure
1783 * @plane: plane to enable
1784 * @pipe: pipe being fed
1785 *
1786 * Enable @plane on @pipe, making sure that @pipe is running first.
1787 */
1788static void intel_enable_plane(struct drm_i915_private *dev_priv,
1789 enum plane plane, enum pipe pipe)
1790{
1791 int reg;
1792 u32 val;
1793
1794 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1795 assert_pipe_enabled(dev_priv, pipe);
1796
1797 reg = DSPCNTR(plane);
1798 val = I915_READ(reg);
00d70b15
CW
1799 if (val & DISPLAY_PLANE_ENABLE)
1800 return;
1801
1802 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1803 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB
1804 intel_wait_for_vblank(dev_priv->dev, pipe);
1805}
1806
b24e7179
JB
1807/**
1808 * intel_disable_plane - disable a display plane
1809 * @dev_priv: i915 private structure
1810 * @plane: plane to disable
1811 * @pipe: pipe consuming the data
1812 *
1813 * Disable @plane; should be an independent operation.
1814 */
1815static void intel_disable_plane(struct drm_i915_private *dev_priv,
1816 enum plane plane, enum pipe pipe)
1817{
1818 int reg;
1819 u32 val;
1820
1821 reg = DSPCNTR(plane);
1822 val = I915_READ(reg);
00d70b15
CW
1823 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1824 return;
1825
1826 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB
1827 intel_flush_display_plane(dev_priv, plane);
1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
693db184
CW
1831static bool need_vtd_wa(struct drm_device *dev)
1832{
1833#ifdef CONFIG_INTEL_IOMMU
1834 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1835 return true;
1836#endif
1837 return false;
1838}
1839
127bd2ac 1840int
48b956c5 1841intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1842 struct drm_i915_gem_object *obj,
919926ae 1843 struct intel_ring_buffer *pipelined)
6b95a207 1844{
ce453d81 1845 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH
1846 u32 alignment;
1847 int ret;
1848
05394f39 1849 switch (obj->tiling_mode) {
6b95a207 1850 case I915_TILING_NONE:
534843da
CW
1851 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1852 alignment = 128 * 1024;
a6c45cf0 1853 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW
1854 alignment = 4 * 1024;
1855 else
1856 alignment = 64 * 1024;
6b95a207
KH
1857 break;
1858 case I915_TILING_X:
1859 /* pin() will align the object as required by fence */
1860 alignment = 0;
1861 break;
1862 case I915_TILING_Y:
8bb6e959
DV
1863 /* Despite that we check this in framebuffer_init userspace can
1864 * screw us over and change the tiling after the fact. Only
1865 * pinned buffers can't change their tiling. */
1866 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH
1867 return -EINVAL;
1868 default:
1869 BUG();
1870 }
1871
693db184
CW
1872 /* Note that the w/a also requires 64 PTE of padding following the
1873 * bo. We currently fill all unused PTE with the shadow page and so
1874 * we should always have valid PTE following the scanout preventing
1875 * the VT-d warning.
1876 */
1877 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1878 alignment = 256 * 1024;
1879
ce453d81 1880 dev_priv->mm.interruptible = false;
2da3b9b9 1881 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1882 if (ret)
ce453d81 1883 goto err_interruptible;
6b95a207
KH
1884
1885 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1886 * fence, whereas 965+ only requires a fence if using
1887 * framebuffer compression. For simplicity, we always install
1888 * a fence as the cost is not that onerous.
1889 */
06d98131 1890 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW
1891 if (ret)
1892 goto err_unpin;
1690e1eb 1893
9a5a53b3 1894 i915_gem_object_pin_fence(obj);
6b95a207 1895
ce453d81 1896 dev_priv->mm.interruptible = true;
6b95a207 1897 return 0;
48b956c5
CW
1898
1899err_unpin:
cc98b413 1900 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW
1901err_interruptible:
1902 dev_priv->mm.interruptible = true;
48b956c5 1903 return ret;
6b95a207
KH
1904}
1905
1690e1eb
CW
1906void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1907{
1908 i915_gem_object_unpin_fence(obj);
cc98b413 1909 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW
1910}
1911
c2c75131
DV
1912/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1913 * is assumed to be a power-of-two. */
bc752862
CW
1914unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1915 unsigned int tiling_mode,
1916 unsigned int cpp,
1917 unsigned int pitch)
c2c75131 1918{
bc752862
CW
1919 if (tiling_mode != I915_TILING_NONE) {
1920 unsigned int tile_rows, tiles;
c2c75131 1921
bc752862
CW
1922 tile_rows = *y / 8;
1923 *y %= 8;
c2c75131 1924
bc752862
CW
1925 tiles = *x / (512/cpp);
1926 *x %= 512/cpp;
1927
1928 return tile_rows * pitch * 8 + tiles * 4096;
1929 } else {
1930 unsigned int offset;
1931
1932 offset = *y * pitch + *x * cpp;
1933 *y = 0;
1934 *x = (offset & 4095) / cpp;
1935 return offset & -4096;
1936 }
c2c75131
DV
1937}
1938
17638cd6
JB
1939static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1940 int x, int y)
81255565
JB
1941{
1942 struct drm_device *dev = crtc->dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1945 struct intel_framebuffer *intel_fb;
05394f39 1946 struct drm_i915_gem_object *obj;
81255565 1947 int plane = intel_crtc->plane;
e506a0c6 1948 unsigned long linear_offset;
81255565 1949 u32 dspcntr;
5eddb70b 1950 u32 reg;
81255565
JB
1951
1952 switch (plane) {
1953 case 0:
1954 case 1:
1955 break;
1956 default:
84f44ce7 1957 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB
1958 return -EINVAL;
1959 }
1960
1961 intel_fb = to_intel_framebuffer(fb);
1962 obj = intel_fb->obj;
81255565 1963
5eddb70b
CW
1964 reg = DSPCNTR(plane);
1965 dspcntr = I915_READ(reg);
81255565
JB
1966 /* Mask out pixel format bits in case we change it */
1967 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS
1968 switch (fb->pixel_format) {
1969 case DRM_FORMAT_C8:
81255565
JB
1970 dspcntr |= DISPPLANE_8BPP;
1971 break;
57779d06
VS
1972 case DRM_FORMAT_XRGB1555:
1973 case DRM_FORMAT_ARGB1555:
1974 dspcntr |= DISPPLANE_BGRX555;
81255565 1975 break;
57779d06
VS
1976 case DRM_FORMAT_RGB565:
1977 dspcntr |= DISPPLANE_BGRX565;
1978 break;
1979 case DRM_FORMAT_XRGB8888:
1980 case DRM_FORMAT_ARGB8888:
1981 dspcntr |= DISPPLANE_BGRX888;
1982 break;
1983 case DRM_FORMAT_XBGR8888:
1984 case DRM_FORMAT_ABGR8888:
1985 dspcntr |= DISPPLANE_RGBX888;
1986 break;
1987 case DRM_FORMAT_XRGB2101010:
1988 case DRM_FORMAT_ARGB2101010:
1989 dspcntr |= DISPPLANE_BGRX101010;
1990 break;
1991 case DRM_FORMAT_XBGR2101010:
1992 case DRM_FORMAT_ABGR2101010:
1993 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB
1994 break;
1995 default:
baba133a 1996 BUG();
81255565 1997 }
57779d06 1998
a6c45cf0 1999 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2000 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB
2001 dspcntr |= DISPPLANE_TILED;
2002 else
2003 dspcntr &= ~DISPPLANE_TILED;
2004 }
2005
de1aa629
VS
2006 if (IS_G4X(dev))
2007 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2008
5eddb70b 2009 I915_WRITE(reg, dspcntr);
81255565 2010
e506a0c6 2011 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2012
c2c75131
DV
2013 if (INTEL_INFO(dev)->gen >= 4) {
2014 intel_crtc->dspaddr_offset =
bc752862
CW
2015 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2016 fb->bits_per_pixel / 8,
2017 fb->pitches[0]);
c2c75131
DV
2018 linear_offset -= intel_crtc->dspaddr_offset;
2019 } else {
e506a0c6 2020 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2021 }
e506a0c6 2022
f343c5f6
BW
2023 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2024 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2025 fb->pitches[0]);
01f2c773 2026 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2027 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2028 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2029 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2030 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2031 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2032 } else
f343c5f6 2033 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2034 POSTING_READ(reg);
81255565 2035
17638cd6
JB
2036 return 0;
2037}
2038
2039static int ironlake_update_plane(struct drm_crtc *crtc,
2040 struct drm_framebuffer *fb, int x, int y)
2041{
2042 struct drm_device *dev = crtc->dev;
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2045 struct intel_framebuffer *intel_fb;
2046 struct drm_i915_gem_object *obj;
2047 int plane = intel_crtc->plane;
e506a0c6 2048 unsigned long linear_offset;
17638cd6
JB
2049 u32 dspcntr;
2050 u32 reg;
2051
2052 switch (plane) {
2053 case 0:
2054 case 1:
27f8227b 2055 case 2:
17638cd6
JB
2056 break;
2057 default:
84f44ce7 2058 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB
2059 return -EINVAL;
2060 }
2061
2062 intel_fb = to_intel_framebuffer(fb);
2063 obj = intel_fb->obj;
2064
2065 reg = DSPCNTR(plane);
2066 dspcntr = I915_READ(reg);
2067 /* Mask out pixel format bits in case we change it */
2068 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS
2069 switch (fb->pixel_format) {
2070 case DRM_FORMAT_C8:
17638cd6
JB
2071 dspcntr |= DISPPLANE_8BPP;
2072 break;
57779d06
VS
2073 case DRM_FORMAT_RGB565:
2074 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2075 break;
57779d06
VS
2076 case DRM_FORMAT_XRGB8888:
2077 case DRM_FORMAT_ARGB8888:
2078 dspcntr |= DISPPLANE_BGRX888;
2079 break;
2080 case DRM_FORMAT_XBGR8888:
2081 case DRM_FORMAT_ABGR8888:
2082 dspcntr |= DISPPLANE_RGBX888;
2083 break;
2084 case DRM_FORMAT_XRGB2101010:
2085 case DRM_FORMAT_ARGB2101010:
2086 dspcntr |= DISPPLANE_BGRX101010;
2087 break;
2088 case DRM_FORMAT_XBGR2101010:
2089 case DRM_FORMAT_ABGR2101010:
2090 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB
2091 break;
2092 default:
baba133a 2093 BUG();
17638cd6
JB
2094 }
2095
2096 if (obj->tiling_mode != I915_TILING_NONE)
2097 dspcntr |= DISPPLANE_TILED;
2098 else
2099 dspcntr &= ~DISPPLANE_TILED;
2100
1f5d76db
PZ
2101 if (IS_HASWELL(dev))
2102 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2103 else
2104 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB
2105
2106 I915_WRITE(reg, dspcntr);
2107
e506a0c6 2108 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2109 intel_crtc->dspaddr_offset =
bc752862
CW
2110 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2111 fb->bits_per_pixel / 8,
2112 fb->pitches[0]);
c2c75131 2113 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2114
f343c5f6
BW
2115 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2116 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2117 fb->pitches[0]);
01f2c773 2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2120 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL
2121 if (IS_HASWELL(dev)) {
2122 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2123 } else {
2124 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2125 I915_WRITE(DSPLINOFF(plane), linear_offset);
2126 }
17638cd6
JB
2127 POSTING_READ(reg);
2128
2129 return 0;
2130}
2131
2132/* Assume fb object is pinned & idle & fenced and just update base pointers */
2133static int
2134intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2135 int x, int y, enum mode_set_atomic state)
2136{
2137 struct drm_device *dev = crtc->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2139
6b8e6ed0
CW
2140 if (dev_priv->display.disable_fbc)
2141 dev_priv->display.disable_fbc(dev);
3dec0095 2142 intel_increase_pllclock(crtc);
81255565 2143
6b8e6ed0 2144 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB
2145}
2146
96a02917
VS
2147void intel_display_handle_reset(struct drm_device *dev)
2148{
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 struct drm_crtc *crtc;
2151
2152 /*
2153 * Flips in the rings have been nuked by the reset,
2154 * so complete all pending flips so that user space
2155 * will get its events and not get stuck.
2156 *
2157 * Also update the base address of all primary
2158 * planes to the the last fb to make sure we're
2159 * showing the correct fb after a reset.
2160 *
2161 * Need to make two loops over the crtcs so that we
2162 * don't try to grab a crtc mutex before the
2163 * pending_flip_queue really got woken up.
2164 */
2165
2166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 enum plane plane = intel_crtc->plane;
2169
2170 intel_prepare_page_flip(dev, plane);
2171 intel_finish_page_flip_plane(dev, plane);
2172 }
2173
2174 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176
2177 mutex_lock(&crtc->mutex);
2178 if (intel_crtc->active)
2179 dev_priv->display.update_plane(crtc, crtc->fb,
2180 crtc->x, crtc->y);
2181 mutex_unlock(&crtc->mutex);
2182 }
2183}
2184
14667a4b
CW
2185static int
2186intel_finish_fb(struct drm_framebuffer *old_fb)
2187{
2188 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2189 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2190 bool was_interruptible = dev_priv->mm.interruptible;
2191 int ret;
2192
14667a4b
CW
2193 /* Big Hammer, we also need to ensure that any pending
2194 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2195 * current scanout is retired before unpinning the old
2196 * framebuffer.
2197 *
2198 * This should only fail upon a hung GPU, in which case we
2199 * can safely continue.
2200 */
2201 dev_priv->mm.interruptible = false;
2202 ret = i915_gem_object_finish_gpu(obj);
2203 dev_priv->mm.interruptible = was_interruptible;
2204
2205 return ret;
2206}
2207
198598d0
VS
2208static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2209{
2210 struct drm_device *dev = crtc->dev;
2211 struct drm_i915_master_private *master_priv;
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 if (!dev->primary->master)
2215 return;
2216
2217 master_priv = dev->primary->master->driver_priv;
2218 if (!master_priv->sarea_priv)
2219 return;
2220
2221 switch (intel_crtc->pipe) {
2222 case 0:
2223 master_priv->sarea_priv->pipeA_x = x;
2224 master_priv->sarea_priv->pipeA_y = y;
2225 break;
2226 case 1:
2227 master_priv->sarea_priv->pipeB_x = x;
2228 master_priv->sarea_priv->pipeB_y = y;
2229 break;
2230 default:
2231 break;
2232 }
2233}
2234
5c3b82e2 2235static int
3c4fdcfb 2236intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2237 struct drm_framebuffer *fb)
79e53945
JB
2238{
2239 struct drm_device *dev = crtc->dev;
6b8e6ed0 2240 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2242 struct drm_framebuffer *old_fb;
5c3b82e2 2243 int ret;
79e53945
JB
2244
2245 /* no fb bound */
94352cf9 2246 if (!fb) {
a5071c2f 2247 DRM_ERROR("No FB bound\n");
5c3b82e2
CW
2248 return 0;
2249 }
2250
7eb552ae 2251 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS
2252 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2253 plane_name(intel_crtc->plane),
2254 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2255 return -EINVAL;
79e53945
JB
2256 }
2257
5c3b82e2 2258 mutex_lock(&dev->struct_mutex);
265db958 2259 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2260 to_intel_framebuffer(fb)->obj,
919926ae 2261 NULL);
5c3b82e2
CW
2262 if (ret != 0) {
2263 mutex_unlock(&dev->struct_mutex);
a5071c2f 2264 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW
2265 return ret;
2266 }
79e53945 2267
4d6a3e63
JB
2268 /* Update pipe size and adjust fitter if needed */
2269 if (i915_fastboot) {
2270 I915_WRITE(PIPESRC(intel_crtc->pipe),
2271 ((crtc->mode.hdisplay - 1) << 16) |
2272 (crtc->mode.vdisplay - 1));
2273 if (!intel_crtc->config.pch_pfit.size &&
2274 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2275 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2276 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2277 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2278 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2279 }
2280 }
2281
94352cf9 2282 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2283 if (ret) {
94352cf9 2284 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2285 mutex_unlock(&dev->struct_mutex);
a5071c2f 2286 DRM_ERROR("failed to update base address\n");
4e6cfefc 2287 return ret;
79e53945 2288 }
3c4fdcfb 2289
94352cf9
DV
2290 old_fb = crtc->fb;
2291 crtc->fb = fb;
6c4c86f5
DV
2292 crtc->x = x;
2293 crtc->y = y;
94352cf9 2294
b7f1de28 2295 if (old_fb) {
d7697eea
DV
2296 if (intel_crtc->active && old_fb != fb)
2297 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2298 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2299 }
652c393a 2300
6b8e6ed0 2301 intel_update_fbc(dev);
4906557e 2302 intel_edp_psr_update(dev);
5c3b82e2 2303 mutex_unlock(&dev->struct_mutex);
79e53945 2304
198598d0 2305 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW
2306
2307 return 0;
79e53945
JB
2308}
2309
5e84e1a4
ZW
2310static void intel_fdi_normal_train(struct drm_crtc *crtc)
2311{
2312 struct drm_device *dev = crtc->dev;
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2315 int pipe = intel_crtc->pipe;
2316 u32 reg, temp;
2317
2318 /* enable normal train */
2319 reg = FDI_TX_CTL(pipe);
2320 temp = I915_READ(reg);
61e499bf 2321 if (IS_IVYBRIDGE(dev)) {
357555c0
JB
2322 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2323 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP
2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2327 }
5e84e1a4
ZW
2328 I915_WRITE(reg, temp);
2329
2330 reg = FDI_RX_CTL(pipe);
2331 temp = I915_READ(reg);
2332 if (HAS_PCH_CPT(dev)) {
2333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2334 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2335 } else {
2336 temp &= ~FDI_LINK_TRAIN_NONE;
2337 temp |= FDI_LINK_TRAIN_NONE;
2338 }
2339 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2340
2341 /* wait one idle pattern time */
2342 POSTING_READ(reg);
2343 udelay(1000);
357555c0
JB
2344
2345 /* IVB wants error correction enabled */
2346 if (IS_IVYBRIDGE(dev))
2347 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2348 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW
2349}
2350
1e833f40
DV
2351static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2352{
2353 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2354}
2355
01a415fd
DV
2356static void ivb_modeset_global_resources(struct drm_device *dev)
2357{
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *pipe_B_crtc =
2360 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2361 struct intel_crtc *pipe_C_crtc =
2362 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2363 uint32_t temp;
2364
1e833f40
DV
2365 /*
2366 * When everything is off disable fdi C so that we could enable fdi B
2367 * with all lanes. Note that we don't care about enabled pipes without
2368 * an enabled pch encoder.
2369 */
2370 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2371 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV
2372 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2373 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2374
2375 temp = I915_READ(SOUTH_CHICKEN1);
2376 temp &= ~FDI_BC_BIFURCATION_SELECT;
2377 DRM_DEBUG_KMS("disabling fdi C rx\n");
2378 I915_WRITE(SOUTH_CHICKEN1, temp);
2379 }
2380}
2381
8db9d77b
ZW
2382/* The FDI link training functions for ILK/Ibexpeak. */
2383static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
0fc932b8 2389 int plane = intel_crtc->plane;
5eddb70b 2390 u32 reg, temp, tries;
8db9d77b 2391
0fc932b8
JB
2392 /* FDI needs bits from pipe & plane first */
2393 assert_pipe_enabled(dev_priv, pipe);
2394 assert_plane_enabled(dev_priv, plane);
2395
e1a44743
AJ
2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW
2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ
2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
2402 I915_WRITE(reg, temp);
2403 I915_READ(reg);
e1a44743
AJ
2404 udelay(150);
2405
8db9d77b 2406 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
2407 reg = FDI_TX_CTL(pipe);
2408 temp = I915_READ(reg);
627eb5a3
DV
2409 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2410 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW
2411 temp &= ~FDI_LINK_TRAIN_NONE;
2412 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2413 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2414
5eddb70b
CW
2415 reg = FDI_RX_CTL(pipe);
2416 temp = I915_READ(reg);
8db9d77b
ZW
2417 temp &= ~FDI_LINK_TRAIN_NONE;
2418 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW
2419 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2420
2421 POSTING_READ(reg);
8db9d77b
ZW
2422 udelay(150);
2423
5b2adf89 2424 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV
2425 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2428
5eddb70b 2429 reg = FDI_RX_IIR(pipe);
e1a44743 2430 for (tries = 0; tries < 5; tries++) {
5eddb70b 2431 temp = I915_READ(reg);
8db9d77b
ZW
2432 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434 if ((temp & FDI_RX_BIT_LOCK)) {
2435 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2436 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
2437 break;
2438 }
8db9d77b 2439 }
e1a44743 2440 if (tries == 5)
5eddb70b 2441 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
2442
2443 /* Train 2 */
5eddb70b
CW
2444 reg = FDI_TX_CTL(pipe);
2445 temp = I915_READ(reg);
8db9d77b
ZW
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2448 I915_WRITE(reg, temp);
8db9d77b 2449
5eddb70b
CW
2450 reg = FDI_RX_CTL(pipe);
2451 temp = I915_READ(reg);
8db9d77b
ZW
2452 temp &= ~FDI_LINK_TRAIN_NONE;
2453 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2454 I915_WRITE(reg, temp);
8db9d77b 2455
5eddb70b
CW
2456 POSTING_READ(reg);
2457 udelay(150);
8db9d77b 2458
5eddb70b 2459 reg = FDI_RX_IIR(pipe);
e1a44743 2460 for (tries = 0; tries < 5; tries++) {
5eddb70b 2461 temp = I915_READ(reg);
8db9d77b
ZW
2462 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463
2464 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2465 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
2466 DRM_DEBUG_KMS("FDI train 2 done.\n");
2467 break;
2468 }
8db9d77b 2469 }
e1a44743 2470 if (tries == 5)
5eddb70b 2471 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
2472
2473 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2474
8db9d77b
ZW
2475}
2476
0206e353 2477static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW
2478 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2479 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2480 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2481 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2482};
2483
2484/* The FDI link training functions for SNB/Cougarpoint. */
2485static void gen6_fdi_link_train(struct drm_crtc *crtc)
2486{
2487 struct drm_device *dev = crtc->dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490 int pipe = intel_crtc->pipe;
fa37d39e 2491 u32 reg, temp, i, retry;
8db9d77b 2492
e1a44743
AJ
2493 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2494 for train result */
5eddb70b
CW
2495 reg = FDI_RX_IMR(pipe);
2496 temp = I915_READ(reg);
e1a44743
AJ
2497 temp &= ~FDI_RX_SYMBOL_LOCK;
2498 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
2499 I915_WRITE(reg, temp);
2500
2501 POSTING_READ(reg);
e1a44743
AJ
2502 udelay(150);
2503
8db9d77b 2504 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
627eb5a3
DV
2507 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2508 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW
2509 temp &= ~FDI_LINK_TRAIN_NONE;
2510 temp |= FDI_LINK_TRAIN_PATTERN_1;
2511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512 /* SNB-B */
2513 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2514 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2515
d74cf324
DV
2516 I915_WRITE(FDI_RX_MISC(pipe),
2517 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2518
5eddb70b
CW
2519 reg = FDI_RX_CTL(pipe);
2520 temp = I915_READ(reg);
8db9d77b
ZW
2521 if (HAS_PCH_CPT(dev)) {
2522 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2524 } else {
2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527 }
5eddb70b
CW
2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW
2531 udelay(150);
2532
0206e353 2533 for (i = 0; i < 4; i++) {
5eddb70b
CW
2534 reg = FDI_TX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW
2536 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
2538 I915_WRITE(reg, temp);
2539
2540 POSTING_READ(reg);
8db9d77b
ZW
2541 udelay(500);
2542
fa37d39e
SP
2543 for (retry = 0; retry < 5; retry++) {
2544 reg = FDI_RX_IIR(pipe);
2545 temp = I915_READ(reg);
2546 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547 if (temp & FDI_RX_BIT_LOCK) {
2548 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549 DRM_DEBUG_KMS("FDI train 1 done.\n");
2550 break;
2551 }
2552 udelay(50);
8db9d77b 2553 }
fa37d39e
SP
2554 if (retry < 5)
2555 break;
8db9d77b
ZW
2556 }
2557 if (i == 4)
5eddb70b 2558 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
2559
2560 /* Train 2 */
5eddb70b
CW
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
8db9d77b
ZW
2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
2565 if (IS_GEN6(dev)) {
2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 /* SNB-B */
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569 }
5eddb70b 2570 I915_WRITE(reg, temp);
8db9d77b 2571
5eddb70b
CW
2572 reg = FDI_RX_CTL(pipe);
2573 temp = I915_READ(reg);
8db9d77b
ZW
2574 if (HAS_PCH_CPT(dev)) {
2575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2576 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2577 } else {
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 }
5eddb70b
CW
2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
8db9d77b
ZW
2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
5eddb70b
CW
2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
8db9d77b
ZW
2594 udelay(500);
2595
fa37d39e
SP
2596 for (retry = 0; retry < 5; retry++) {
2597 reg = FDI_RX_IIR(pipe);
2598 temp = I915_READ(reg);
2599 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2600 if (temp & FDI_RX_SYMBOL_LOCK) {
2601 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2602 DRM_DEBUG_KMS("FDI train 2 done.\n");
2603 break;
2604 }
2605 udelay(50);
8db9d77b 2606 }
fa37d39e
SP
2607 if (retry < 5)
2608 break;
8db9d77b
ZW
2609 }
2610 if (i == 4)
5eddb70b 2611 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
2612
2613 DRM_DEBUG_KMS("FDI train done.\n");
2614}
2615
357555c0
JB
2616/* Manual link training for Ivy Bridge A0 parts */
2617static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2618{
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 int pipe = intel_crtc->pipe;
139ccd3f 2623 u32 reg, temp, i, j;
357555c0
JB
2624
2625 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2626 for train result */
2627 reg = FDI_RX_IMR(pipe);
2628 temp = I915_READ(reg);
2629 temp &= ~FDI_RX_SYMBOL_LOCK;
2630 temp &= ~FDI_RX_BIT_LOCK;
2631 I915_WRITE(reg, temp);
2632
2633 POSTING_READ(reg);
2634 udelay(150);
2635
01a415fd
DV
2636 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2637 I915_READ(FDI_RX_IIR(pipe)));
2638
139ccd3f
JB
2639 /* Try each vswing and preemphasis setting twice before moving on */
2640 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2641 /* disable first in case we need to retry */
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2645 temp &= ~FDI_TX_ENABLE;
2646 I915_WRITE(reg, temp);
357555c0 2647
139ccd3f
JB
2648 reg = FDI_RX_CTL(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_LINK_TRAIN_AUTO;
2651 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652 temp &= ~FDI_RX_ENABLE;
2653 I915_WRITE(reg, temp);
357555c0 2654
139ccd3f 2655 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB
2656 reg = FDI_TX_CTL(pipe);
2657 temp = I915_READ(reg);
139ccd3f
JB
2658 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2659 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB
2662 temp |= snb_b_fdi_train_param[j/2];
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2665
139ccd3f
JB
2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2668
139ccd3f 2669 reg = FDI_RX_CTL(pipe);
357555c0 2670 temp = I915_READ(reg);
139ccd3f
JB
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672 temp |= FDI_COMPOSITE_SYNC;
2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2674
139ccd3f
JB
2675 POSTING_READ(reg);
2676 udelay(1); /* should be 0.5us */
357555c0 2677
139ccd3f
JB
2678 for (i = 0; i < 4; i++) {
2679 reg = FDI_RX_IIR(pipe);
2680 temp = I915_READ(reg);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2682
139ccd3f
JB
2683 if (temp & FDI_RX_BIT_LOCK ||
2684 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2685 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2686 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2687 i);
2688 break;
2689 }
2690 udelay(1); /* should be 0.5us */
2691 }
2692 if (i == 4) {
2693 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2694 continue;
2695 }
357555c0 2696
139ccd3f 2697 /* Train 2 */
357555c0
JB
2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
139ccd3f
JB
2700 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2701 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2702 I915_WRITE(reg, temp);
2703
2704 reg = FDI_RX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2707 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB
2708 I915_WRITE(reg, temp);
2709
2710 POSTING_READ(reg);
139ccd3f 2711 udelay(2); /* should be 1.5us */
357555c0 2712
139ccd3f
JB
2713 for (i = 0; i < 4; i++) {
2714 reg = FDI_RX_IIR(pipe);
2715 temp = I915_READ(reg);
2716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2717
139ccd3f
JB
2718 if (temp & FDI_RX_SYMBOL_LOCK ||
2719 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2720 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2721 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2722 i);
2723 goto train_done;
2724 }
2725 udelay(2); /* should be 1.5us */
357555c0 2726 }
139ccd3f
JB
2727 if (i == 4)
2728 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2729 }
357555c0 2730
139ccd3f 2731train_done:
357555c0
JB
2732 DRM_DEBUG_KMS("FDI train done.\n");
2733}
2734
88cefb6c 2735static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2736{
88cefb6c 2737 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2738 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2739 int pipe = intel_crtc->pipe;
5eddb70b 2740 u32 reg, temp;
79e53945 2741
c64e311e 2742
c98e9dcf 2743 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW
2744 reg = FDI_RX_CTL(pipe);
2745 temp = I915_READ(reg);
627eb5a3
DV
2746 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2747 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW
2749 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2750
2751 POSTING_READ(reg);
c98e9dcf
JB
2752 udelay(200);
2753
2754 /* Switch from Rawclk to PCDclk */
5eddb70b
CW
2755 temp = I915_READ(reg);
2756 I915_WRITE(reg, temp | FDI_PCDCLK);
2757
2758 POSTING_READ(reg);
c98e9dcf
JB
2759 udelay(200);
2760
20749730
PZ
2761 /* Enable CPU FDI TX PLL, always on for Ironlake */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2765 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2766
20749730
PZ
2767 POSTING_READ(reg);
2768 udelay(100);
6be4a607 2769 }
0e23b99d
JB
2770}
2771
88cefb6c
DV
2772static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2773{
2774 struct drm_device *dev = intel_crtc->base.dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 int pipe = intel_crtc->pipe;
2777 u32 reg, temp;
2778
2779 /* Switch from PCDclk to Rawclk */
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2783
2784 /* Disable CPU FDI TX PLL */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2788
2789 POSTING_READ(reg);
2790 udelay(100);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2795
2796 /* Wait for the clocks to turn off. */
2797 POSTING_READ(reg);
2798 udelay(100);
2799}
2800
0fc932b8
JB
2801static void ironlake_fdi_disable(struct drm_crtc *crtc)
2802{
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 int pipe = intel_crtc->pipe;
2807 u32 reg, temp;
2808
2809 /* disable CPU FDI tx and PCH FDI rx */
2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2813 POSTING_READ(reg);
2814
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 temp &= ~(0x7 << 16);
dfd07d72 2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
2819 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2820
2821 POSTING_READ(reg);
2822 udelay(100);
2823
2824 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB
2825 if (HAS_PCH_IBX(dev)) {
2826 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2827 }
0fc932b8
JB
2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
dfd07d72 2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
5bb61643
CW
2854static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2855{
2856 struct drm_device *dev = crtc->dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW
2859 unsigned long flags;
2860 bool pending;
2861
10d83730
VS
2862 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2863 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW
2864 return false;
2865
2866 spin_lock_irqsave(&dev->event_lock, flags);
2867 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2868 spin_unlock_irqrestore(&dev->event_lock, flags);
2869
2870 return pending;
2871}
2872
e6c3a2a6
CW
2873static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2874{
0f91128d 2875 struct drm_device *dev = crtc->dev;
5bb61643 2876 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW
2877
2878 if (crtc->fb == NULL)
2879 return;
2880
2c10d571
DV
2881 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2882
5bb61643
CW
2883 wait_event(dev_priv->pending_flip_queue,
2884 !intel_crtc_has_pending_flip(crtc));
2885
0f91128d
CW
2886 mutex_lock(&dev->struct_mutex);
2887 intel_finish_fb(crtc->fb);
2888 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW
2889}
2890
e615efe4
ED
2891/* Program iCLKIP clock to the desired frequency */
2892static void lpt_program_iclkip(struct drm_crtc *crtc)
2893{
2894 struct drm_device *dev = crtc->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2897 u32 temp;
2898
09153000
DV
2899 mutex_lock(&dev_priv->dpio_lock);
2900
e615efe4
ED
2901 /* It is necessary to ungate the pixclk gate prior to programming
2902 * the divisors, and gate it back when it is done.
2903 */
2904 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2905
2906 /* Disable SSCCTL */
2907 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ
2908 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2909 SBI_SSCCTL_DISABLE,
2910 SBI_ICLK);
e615efe4
ED
2911
2912 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2913 if (crtc->mode.clock == 20000) {
2914 auxdiv = 1;
2915 divsel = 0x41;
2916 phaseinc = 0x20;
2917 } else {
2918 /* The iCLK virtual clock root frequency is in MHz,
2919 * but the crtc->mode.clock in in KHz. To get the divisors,
2920 * it is necessary to divide one by another, so we
2921 * convert the virtual clock precision to KHz here for higher
2922 * precision.
2923 */
2924 u32 iclk_virtual_root_freq = 172800 * 1000;
2925 u32 iclk_pi_range = 64;
2926 u32 desired_divisor, msb_divisor_value, pi_value;
2927
2928 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2929 msb_divisor_value = desired_divisor / iclk_pi_range;
2930 pi_value = desired_divisor % iclk_pi_range;
2931
2932 auxdiv = 0;
2933 divsel = msb_divisor_value - 2;
2934 phaseinc = pi_value;
2935 }
2936
2937 /* This should not happen with any sane values */
2938 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2939 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2940 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2941 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2942
2943 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2944 crtc->mode.clock,
2945 auxdiv,
2946 divsel,
2947 phasedir,
2948 phaseinc);
2949
2950 /* Program SSCDIVINTPHASE6 */
988d6ee8 2951 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED
2952 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2953 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2954 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2955 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2956 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2957 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2958 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED
2959
2960 /* Program SSCAUXDIV */
988d6ee8 2961 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED
2962 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2963 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2964 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED
2965
2966 /* Enable modulator and associated divider */
988d6ee8 2967 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2968 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED
2970
2971 /* Wait for initialization time */
2972 udelay(24);
2973
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV
2975
2976 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED
2977}
2978
275f01b2
DV
2979static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2980 enum pipe pch_transcoder)
2981{
2982 struct drm_device *dev = crtc->base.dev;
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2985
2986 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2987 I915_READ(HTOTAL(cpu_transcoder)));
2988 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2989 I915_READ(HBLANK(cpu_transcoder)));
2990 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2991 I915_READ(HSYNC(cpu_transcoder)));
2992
2993 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2994 I915_READ(VTOTAL(cpu_transcoder)));
2995 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2996 I915_READ(VBLANK(cpu_transcoder)));
2997 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2998 I915_READ(VSYNC(cpu_transcoder)));
2999 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3000 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3001}
3002
f67a559d
JB
3003/*
3004 * Enable PCH resources required for PCH ports:
3005 * - PCH PLLs
3006 * - FDI training & RX/TX
3007 * - update transcoder timings
3008 * - DP transcoding bits
3009 * - transcoder
3010 */
3011static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB
3012{
3013 struct drm_device *dev = crtc->dev;
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3016 int pipe = intel_crtc->pipe;
ee7b9f93 3017 u32 reg, temp;
2c07245f 3018
ab9412ba 3019 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3020
cd986abb
DV
3021 /* Write the TU size bits before fdi link training, so that error
3022 * detection works. */
3023 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3024 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3025
c98e9dcf 3026 /* For PCH output, training FDI link */
674cf967 3027 dev_priv->display.fdi_link_train(crtc);
2c07245f 3028
3ad8a208
DV
3029 /* We need to program the right clock selection before writing the pixel
3030 * mutliplier into the DPLL. */
303b81e0 3031 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3032 u32 sel;
4b645f14 3033
c98e9dcf 3034 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV
3035 temp |= TRANS_DPLL_ENABLE(pipe);
3036 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3037 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB
3038 temp |= sel;
3039 else
3040 temp &= ~sel;
c98e9dcf 3041 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3042 }
5eddb70b 3043
3ad8a208
DV
3044 /* XXX: pch pll's can be enabled any time before we enable the PCH
3045 * transcoder, and we actually should do this to not upset any PCH
3046 * transcoder that already use the clock when we share it.
3047 *
3048 * Note that enable_shared_dpll tries to do the right thing, but
3049 * get_shared_dpll unconditionally resets the pll - we need that to have
3050 * the right LVDS enable sequence. */
3051 ironlake_enable_shared_dpll(intel_crtc);
3052
d9b6cb56
JB
3053 /* set transcoder timing, panel must allow it */
3054 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3056
303b81e0 3057 intel_fdi_normal_train(crtc);
5e84e1a4 3058
c98e9dcf
JB
3059 /* For PCH DP, enable TRANS_DP_CTL */
3060 if (HAS_PCH_CPT(dev) &&
417e822d
KP
3061 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3062 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3063 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW
3064 reg = TRANS_DP_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA
3067 TRANS_DP_SYNC_MASK |
3068 TRANS_DP_BPC_MASK);
5eddb70b
CW
3069 temp |= (TRANS_DP_OUTPUT_ENABLE |
3070 TRANS_DP_ENH_FRAMING);
9325c9f0 3071 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB
3072
3073 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3074 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3075 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3076 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB
3077
3078 switch (intel_trans_dp_port_sel(crtc)) {
3079 case PCH_DP_B:
5eddb70b 3080 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB
3081 break;
3082 case PCH_DP_C:
5eddb70b 3083 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB
3084 break;
3085 case PCH_DP_D:
5eddb70b 3086 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB
3087 break;
3088 default:
e95d41e1 3089 BUG();
32f9d658 3090 }
2c07245f 3091
5eddb70b 3092 I915_WRITE(reg, temp);
6be4a607 3093 }
b52eb4dc 3094
b8a4f404 3095 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB
3096}
3097
1507e5bd
PZ
3098static void lpt_pch_enable(struct drm_crtc *crtc)
3099{
3100 struct drm_device *dev = crtc->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3103 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3104
ab9412ba 3105 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3106
8c52b5e8 3107 lpt_program_iclkip(crtc);
1507e5bd 3108
0540e488 3109 /* Set transcoder timing. */
275f01b2 3110 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3111
937bb610 3112 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB
3113}
3114
e2b78267 3115static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3116{
e2b78267 3117 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB
3118
3119 if (pll == NULL)
3120 return;
3121
3122 if (pll->refcount == 0) {
46edb027 3123 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB
3124 return;
3125 }
3126
f4a091c7
DV
3127 if (--pll->refcount == 0) {
3128 WARN_ON(pll->on);
3129 WARN_ON(pll->active);
3130 }
3131
a43f6e0f 3132 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB
3133}
3134
b89a1d39 3135static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3136{
e2b78267
DV
3137 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3138 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3139 enum intel_dpll_id i;
ee7b9f93 3140
ee7b9f93 3141 if (pll) {
46edb027
DV
3142 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3143 crtc->base.base.id, pll->name);
e2b78267 3144 intel_put_shared_dpll(crtc);
ee7b9f93
JB
3145 }
3146
98b6bd99
DV
3147 if (HAS_PCH_IBX(dev_priv->dev)) {
3148 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3149 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3150 pll = &dev_priv->shared_dplls[i];
98b6bd99 3151
46edb027
DV
3152 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3153 crtc->base.base.id, pll->name);
98b6bd99
DV
3154
3155 goto found;
3156 }
3157
e72f9fbf
DV
3158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3159 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB
3160
3161 /* Only want to check enabled timings first */
3162 if (pll->refcount == 0)
3163 continue;
3164
b89a1d39
DV
3165 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3166 sizeof(pll->hw_state)) == 0) {
46edb027 3167 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3168 crtc->base.base.id,
46edb027 3169 pll->name, pll->refcount, pll->active);
ee7b9f93
JB
3170
3171 goto found;
3172 }
3173 }
3174
3175 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV
3176 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3177 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3178 if (pll->refcount == 0) {
46edb027
DV
3179 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3180 crtc->base.base.id, pll->name);
ee7b9f93
JB
3181 goto found;
3182 }
3183 }
3184
3185 return NULL;
3186
3187found:
a43f6e0f 3188 crtc->config.shared_dpll = i;
46edb027
DV
3189 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3190 pipe_name(crtc->pipe));
ee7b9f93 3191
cdbd2316 3192 if (pll->active == 0) {
66e985c0
DV
3193 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3194 sizeof(pll->hw_state));
3195
46edb027 3196 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3197 WARN_ON(pll->on);
e9d6944e 3198 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3199
15bdd4cf 3200 pll->mode_set(dev_priv, pll);
cdbd2316
DV
3201 }
3202 pll->refcount++;
e04c7350 3203
ee7b9f93
JB
3204 return pll;
3205}
3206
a1520318 3207static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB
3208{
3209 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3210 int dslreg = PIPEDSL(pipe);
d4270e57
JB
3211 u32 temp;
3212
3213 temp = I915_READ(dslreg);
3214 udelay(500);
3215 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3216 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3217 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB
3218 }
3219}
3220
b074cec8
JB
3221static void ironlake_pfit_enable(struct intel_crtc *crtc)
3222{
3223 struct drm_device *dev = crtc->base.dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 int pipe = crtc->pipe;
3226
0ef37f3f 3227 if (crtc->config.pch_pfit.size) {
b074cec8
JB
3228 /* Force use of hard-coded filter coefficients
3229 * as some pre-programmed values are broken,
3230 * e.g. x201.
3231 */
3232 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3233 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3234 PF_PIPE_SEL_IVB(pipe));
3235 else
3236 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3237 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3238 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB
3239 }
3240}
3241
bb53d4ae
VS
3242static void intel_enable_planes(struct drm_crtc *crtc)
3243{
3244 struct drm_device *dev = crtc->dev;
3245 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3246 struct intel_plane *intel_plane;
3247
3248 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3249 if (intel_plane->pipe == pipe)
3250 intel_plane_restore(&intel_plane->base);
3251}
3252
3253static void intel_disable_planes(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3257 struct intel_plane *intel_plane;
3258
3259 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3260 if (intel_plane->pipe == pipe)
3261 intel_plane_disable(&intel_plane->base);
3262}
3263
f67a559d
JB
3264static void ironlake_crtc_enable(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3269 struct intel_encoder *encoder;
f67a559d
JB
3270 int pipe = intel_crtc->pipe;
3271 int plane = intel_crtc->plane;
f67a559d 3272
08a48469
DV
3273 WARN_ON(!crtc->enabled);
3274
f67a559d
JB
3275 if (intel_crtc->active)
3276 return;
3277
3278 intel_crtc->active = true;
8664281b
PZ
3279
3280 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3281 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3282
f67a559d
JB
3283 intel_update_watermarks(dev);
3284
f6736a1a 3285 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV
3286 if (encoder->pre_enable)
3287 encoder->pre_enable(encoder);
f67a559d 3288
5bfe2ac0 3289 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV
3290 /* Note: FDI PLL enabling _must_ be done before we enable the
3291 * cpu pipes, hence this is separate from all the other fdi/pch
3292 * enabling. */
88cefb6c 3293 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV
3294 } else {
3295 assert_fdi_tx_disabled(dev_priv, pipe);
3296 assert_fdi_rx_disabled(dev_priv, pipe);
3297 }
f67a559d 3298
b074cec8 3299 ironlake_pfit_enable(intel_crtc);
f67a559d 3300
9c54c0dd
JB
3301 /*
3302 * On ILK+ LUT must be loaded before the pipe is running but with
3303 * clocks enabled
3304 */
3305 intel_crtc_load_lut(crtc);
3306
5bfe2ac0 3307 intel_enable_pipe(dev_priv, pipe,
23538ef1 3308 intel_crtc->config.has_pch_encoder, false);
f67a559d 3309 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3310 intel_enable_planes(crtc);
5c38d48c 3311 intel_crtc_update_cursor(crtc, true);
f67a559d 3312
5bfe2ac0 3313 if (intel_crtc->config.has_pch_encoder)
f67a559d 3314 ironlake_pch_enable(crtc);
c98e9dcf 3315
d1ebd816 3316 mutex_lock(&dev->struct_mutex);
bed4a673 3317 intel_update_fbc(dev);
d1ebd816
BW
3318 mutex_unlock(&dev->struct_mutex);
3319
fa5c73b1
DV
3320 for_each_encoder_on_crtc(dev, crtc, encoder)
3321 encoder->enable(encoder);
61b77ddd
DV
3322
3323 if (HAS_PCH_CPT(dev))
a1520318 3324 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV
3325
3326 /*
3327 * There seems to be a race in PCH platform hw (at least on some
3328 * outputs) where an enabled pipe still completes any pageflip right
3329 * away (as if the pipe is off) instead of waiting for vblank. As soon
3330 * as the first vblank happend, everything works as expected. Hence just
3331 * wait for one vblank before returning to avoid strange things
3332 * happening.
3333 */
3334 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB
3335}
3336
42db64ef
PZ
3337/* IPS only exists on ULT machines and is tied to pipe A. */
3338static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3339{
f5adf94e 3340 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ
3341}
3342
3343static void hsw_enable_ips(struct intel_crtc *crtc)
3344{
3345 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3346
3347 if (!crtc->config.ips_enabled)
3348 return;
3349
3350 /* We can only enable IPS after we enable a plane and wait for a vblank.
3351 * We guarantee that the plane is enabled by calling intel_enable_ips
3352 * only after intel_enable_plane. And intel_enable_plane already waits
3353 * for a vblank, so all we need to do here is to enable the IPS bit. */
3354 assert_plane_enabled(dev_priv, crtc->plane);
3355 I915_WRITE(IPS_CTL, IPS_ENABLE);
3356}
3357
3358static void hsw_disable_ips(struct intel_crtc *crtc)
3359{
3360 struct drm_device *dev = crtc->base.dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362
3363 if (!crtc->config.ips_enabled)
3364 return;
3365
3366 assert_plane_enabled(dev_priv, crtc->plane);
3367 I915_WRITE(IPS_CTL, 0);
3368
3369 /* We need to wait for a vblank before we can disable the plane. */
3370 intel_wait_for_vblank(dev, crtc->pipe);
3371}
3372
4f771f10
PZ
3373static void haswell_crtc_enable(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3378 struct intel_encoder *encoder;
3379 int pipe = intel_crtc->pipe;
3380 int plane = intel_crtc->plane;
4f771f10
PZ
3381
3382 WARN_ON(!crtc->enabled);
3383
3384 if (intel_crtc->active)
3385 return;
3386
3387 intel_crtc->active = true;
8664281b
PZ
3388
3389 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3390 if (intel_crtc->config.has_pch_encoder)
3391 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3392
4f771f10
PZ
3393 intel_update_watermarks(dev);
3394
5bfe2ac0 3395 if (intel_crtc->config.has_pch_encoder)
04945641 3396 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ
3397
3398 for_each_encoder_on_crtc(dev, crtc, encoder)
3399 if (encoder->pre_enable)
3400 encoder->pre_enable(encoder);
3401
1f544388 3402 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3403
b074cec8 3404 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ
3405
3406 /*
3407 * On ILK+ LUT must be loaded before the pipe is running but with
3408 * clocks enabled
3409 */
3410 intel_crtc_load_lut(crtc);
3411
1f544388 3412 intel_ddi_set_pipe_settings(crtc);
8228c251 3413 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3414
5bfe2ac0 3415 intel_enable_pipe(dev_priv, pipe,
23538ef1 3416 intel_crtc->config.has_pch_encoder, false);
4f771f10 3417 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3418 intel_enable_planes(crtc);
5c38d48c 3419 intel_crtc_update_cursor(crtc, true);
4f771f10 3420
42db64ef
PZ
3421 hsw_enable_ips(intel_crtc);
3422
5bfe2ac0 3423 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3424 lpt_pch_enable(crtc);
4f771f10
PZ
3425
3426 mutex_lock(&dev->struct_mutex);
3427 intel_update_fbc(dev);
3428 mutex_unlock(&dev->struct_mutex);
3429
4f771f10
PZ
3430 for_each_encoder_on_crtc(dev, crtc, encoder)
3431 encoder->enable(encoder);
3432
4f771f10
PZ
3433 /*
3434 * There seems to be a race in PCH platform hw (at least on some
3435 * outputs) where an enabled pipe still completes any pageflip right
3436 * away (as if the pipe is off) instead of waiting for vblank. As soon
3437 * as the first vblank happend, everything works as expected. Hence just
3438 * wait for one vblank before returning to avoid strange things
3439 * happening.
3440 */
3441 intel_wait_for_vblank(dev, intel_crtc->pipe);
3442}
3443
3f8dce3a
DV
3444static void ironlake_pfit_disable(struct intel_crtc *crtc)
3445{
3446 struct drm_device *dev = crtc->base.dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448 int pipe = crtc->pipe;
3449
3450 /* To avoid upsetting the power well on haswell only disable the pfit if
3451 * it's in use. The hw state code will make sure we get this right. */
3452 if (crtc->config.pch_pfit.size) {
3453 I915_WRITE(PF_CTL(pipe), 0);
3454 I915_WRITE(PF_WIN_POS(pipe), 0);
3455 I915_WRITE(PF_WIN_SZ(pipe), 0);
3456 }
3457}
3458
6be4a607
JB
3459static void ironlake_crtc_disable(struct drm_crtc *crtc)
3460{
3461 struct drm_device *dev = crtc->dev;
3462 struct drm_i915_private *dev_priv = dev->dev_private;
3463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3464 struct intel_encoder *encoder;
6be4a607
JB
3465 int pipe = intel_crtc->pipe;
3466 int plane = intel_crtc->plane;
5eddb70b 3467 u32 reg, temp;
b52eb4dc 3468
ef9c3aee 3469
f7abfe8b
CW
3470 if (!intel_crtc->active)
3471 return;
3472
ea9d758d
DV
3473 for_each_encoder_on_crtc(dev, crtc, encoder)
3474 encoder->disable(encoder);
3475
e6c3a2a6 3476 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3477 drm_vblank_off(dev, pipe);
913d8d11 3478
5c3fe8b0 3479 if (dev_priv->fbc.plane == plane)
973d04f9 3480 intel_disable_fbc(dev);
2c07245f 3481
0d5b8c61 3482 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3483 intel_disable_planes(crtc);
0d5b8c61
VS
3484 intel_disable_plane(dev_priv, plane, pipe);
3485
d925c59a
DV
3486 if (intel_crtc->config.has_pch_encoder)
3487 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3488
b24e7179 3489 intel_disable_pipe(dev_priv, pipe);
32f9d658 3490
3f8dce3a 3491 ironlake_pfit_disable(intel_crtc);
2c07245f 3492
bf49ec8c
DV
3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 if (encoder->post_disable)
3495 encoder->post_disable(encoder);
2c07245f 3496
d925c59a
DV
3497 if (intel_crtc->config.has_pch_encoder) {
3498 ironlake_fdi_disable(crtc);
913d8d11 3499
d925c59a
DV
3500 ironlake_disable_pch_transcoder(dev_priv, pipe);
3501 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3502
d925c59a
DV
3503 if (HAS_PCH_CPT(dev)) {
3504 /* disable TRANS_DP_CTL */
3505 reg = TRANS_DP_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3508 TRANS_DP_PORT_SEL_MASK);
3509 temp |= TRANS_DP_PORT_SEL_NONE;
3510 I915_WRITE(reg, temp);
3511
3512 /* disable DPLL_SEL */
3513 temp = I915_READ(PCH_DPLL_SEL);
11887397 3514 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3515 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3516 }
e3421a18 3517
d925c59a 3518 /* disable PCH DPLL */
e72f9fbf 3519 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3520
d925c59a
DV
3521 ironlake_fdi_pll_disable(intel_crtc);
3522 }
6b383a7f 3523
f7abfe8b 3524 intel_crtc->active = false;
6b383a7f 3525 intel_update_watermarks(dev);
d1ebd816
BW
3526
3527 mutex_lock(&dev->struct_mutex);
6b383a7f 3528 intel_update_fbc(dev);
d1ebd816 3529 mutex_unlock(&dev->struct_mutex);
6be4a607 3530}
1b3c7a47 3531
4f771f10 3532static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3533{
4f771f10
PZ
3534 struct drm_device *dev = crtc->dev;
3535 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ
3537 struct intel_encoder *encoder;
3538 int pipe = intel_crtc->pipe;
3539 int plane = intel_crtc->plane;
3b117c8f 3540 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3541
4f771f10
PZ
3542 if (!intel_crtc->active)
3543 return;
3544
3545 for_each_encoder_on_crtc(dev, crtc, encoder)
3546 encoder->disable(encoder);
3547
3548 intel_crtc_wait_for_pending_flips(crtc);
3549 drm_vblank_off(dev, pipe);
4f771f10 3550
891348b2 3551 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3552 if (dev_priv->fbc.plane == plane)
4f771f10
PZ
3553 intel_disable_fbc(dev);
3554
42db64ef
PZ
3555 hsw_disable_ips(intel_crtc);
3556
0d5b8c61 3557 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3558 intel_disable_planes(crtc);
891348b2
RV
3559 intel_disable_plane(dev_priv, plane, pipe);
3560
8664281b
PZ
3561 if (intel_crtc->config.has_pch_encoder)
3562 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ
3563 intel_disable_pipe(dev_priv, pipe);
3564
ad80a810 3565 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3566
3f8dce3a 3567 ironlake_pfit_disable(intel_crtc);
4f771f10 3568
1f544388 3569 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ
3570
3571 for_each_encoder_on_crtc(dev, crtc, encoder)
3572 if (encoder->post_disable)
3573 encoder->post_disable(encoder);
3574
88adfff1 3575 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3576 lpt_disable_pch_transcoder(dev_priv);
8664281b 3577 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3578 intel_ddi_fdi_disable(crtc);
83616634 3579 }
4f771f10
PZ
3580
3581 intel_crtc->active = false;
3582 intel_update_watermarks(dev);
3583
3584 mutex_lock(&dev->struct_mutex);
3585 intel_update_fbc(dev);
3586 mutex_unlock(&dev->struct_mutex);
3587}
3588
ee7b9f93
JB
3589static void ironlake_crtc_off(struct drm_crtc *crtc)
3590{
3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3592 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB
3593}
3594
6441ab5f
PZ
3595static void haswell_crtc_off(struct drm_crtc *crtc)
3596{
3597 intel_ddi_put_crtc_pll(crtc);
3598}
3599
02e792fb
DV
3600static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3601{
02e792fb 3602 if (!enable && intel_crtc->overlay) {
23f09ce3 3603 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3604 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3605
23f09ce3 3606 mutex_lock(&dev->struct_mutex);
ce453d81
CW
3607 dev_priv->mm.interruptible = false;
3608 (void) intel_overlay_switch_off(intel_crtc->overlay);
3609 dev_priv->mm.interruptible = true;
23f09ce3 3610 mutex_unlock(&dev->struct_mutex);
02e792fb 3611 }
02e792fb 3612
5dcdbcb0
CW
3613 /* Let userspace switch the overlay on again. In most cases userspace
3614 * has to recompute where to put it anyway.
3615 */
02e792fb
DV
3616}
3617
61bc95c1
EE
3618/**
3619 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3620 * cursor plane briefly if not already running after enabling the display
3621 * plane.
3622 * This workaround avoids occasional blank screens when self refresh is
3623 * enabled.
3624 */
3625static void
3626g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3627{
3628 u32 cntl = I915_READ(CURCNTR(pipe));
3629
3630 if ((cntl & CURSOR_MODE) == 0) {
3631 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3632
3633 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3634 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3635 intel_wait_for_vblank(dev_priv->dev, pipe);
3636 I915_WRITE(CURCNTR(pipe), cntl);
3637 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3638 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3639 }
3640}
3641
2dd24552
JB
3642static void i9xx_pfit_enable(struct intel_crtc *crtc)
3643{
3644 struct drm_device *dev = crtc->base.dev;
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646 struct intel_crtc_config *pipe_config = &crtc->config;
3647
328d8e82 3648 if (!crtc->config.gmch_pfit.control)
2dd24552
JB
3649 return;
3650
2dd24552 3651 /*
c0b03411
DV
3652 * The panel fitter should only be adjusted whilst the pipe is disabled,
3653 * according to register description and PRM.
2dd24552 3654 */
c0b03411
DV
3655 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3656 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3657
b074cec8
JB
3658 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3659 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV
3660
3661 /* Border color in case we don't scale up to the full screen. Black by
3662 * default, change to something else for debugging. */
3663 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB
3664}
3665
89b667f8
JB
3666static void valleyview_crtc_enable(struct drm_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 struct intel_encoder *encoder;
3672 int pipe = intel_crtc->pipe;
3673 int plane = intel_crtc->plane;
23538ef1 3674 bool is_dsi;
89b667f8
JB
3675
3676 WARN_ON(!crtc->enabled);
3677
3678 if (intel_crtc->active)
3679 return;
3680
3681 intel_crtc->active = true;
3682 intel_update_watermarks(dev);
3683
89b667f8
JB
3684 for_each_encoder_on_crtc(dev, crtc, encoder)
3685 if (encoder->pre_pll_enable)
3686 encoder->pre_pll_enable(encoder);
3687
23538ef1
JN
3688 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3689
e9fd1c02
JN
3690 if (!is_dsi)
3691 vlv_enable_pll(intel_crtc);
89b667f8
JB
3692
3693 for_each_encoder_on_crtc(dev, crtc, encoder)
3694 if (encoder->pre_enable)
3695 encoder->pre_enable(encoder);
3696
2dd24552
JB
3697 i9xx_pfit_enable(intel_crtc);
3698
63cbb074
VS
3699 intel_crtc_load_lut(crtc);
3700
23538ef1 3701 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3702 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3703 intel_enable_planes(crtc);
5c38d48c 3704 intel_crtc_update_cursor(crtc, true);
89b667f8 3705
89b667f8 3706 intel_update_fbc(dev);
5004945f
JN
3707
3708 for_each_encoder_on_crtc(dev, crtc, encoder)
3709 encoder->enable(encoder);
89b667f8
JB
3710}
3711
0b8765c6 3712static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB
3713{
3714 struct drm_device *dev = crtc->dev;
79e53945
JB
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3717 struct intel_encoder *encoder;
79e53945 3718 int pipe = intel_crtc->pipe;
80824003 3719 int plane = intel_crtc->plane;
79e53945 3720
08a48469
DV
3721 WARN_ON(!crtc->enabled);
3722
f7abfe8b
CW
3723 if (intel_crtc->active)
3724 return;
3725
3726 intel_crtc->active = true;
6b383a7f
CW
3727 intel_update_watermarks(dev);
3728
9d6d9f19
MK
3729 for_each_encoder_on_crtc(dev, crtc, encoder)
3730 if (encoder->pre_enable)
3731 encoder->pre_enable(encoder);
3732
f6736a1a
DV
3733 i9xx_enable_pll(intel_crtc);
3734
2dd24552
JB
3735 i9xx_pfit_enable(intel_crtc);
3736
63cbb074
VS
3737 intel_crtc_load_lut(crtc);
3738
23538ef1 3739 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3740 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3741 intel_enable_planes(crtc);
22e407d7 3742 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE
3743 if (IS_G4X(dev))
3744 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3745 intel_crtc_update_cursor(crtc, true);
79e53945 3746
0b8765c6
JB
3747 /* Give the overlay scaler a chance to enable if it's on this pipe */
3748 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3749
f440eb13 3750 intel_update_fbc(dev);
ef9c3aee 3751
fa5c73b1
DV
3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 encoder->enable(encoder);
0b8765c6 3754}
79e53945 3755
87476d63
DV
3756static void i9xx_pfit_disable(struct intel_crtc *crtc)
3757{
3758 struct drm_device *dev = crtc->base.dev;
3759 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3760
328d8e82
DV
3761 if (!crtc->config.gmch_pfit.control)
3762 return;
87476d63 3763
328d8e82 3764 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3765
328d8e82
DV
3766 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3767 I915_READ(PFIT_CONTROL));
3768 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV
3769}
3770
0b8765c6
JB
3771static void i9xx_crtc_disable(struct drm_crtc *crtc)
3772{
3773 struct drm_device *dev = crtc->dev;
3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3776 struct intel_encoder *encoder;
0b8765c6
JB
3777 int pipe = intel_crtc->pipe;
3778 int plane = intel_crtc->plane;
ef9c3aee 3779
f7abfe8b
CW
3780 if (!intel_crtc->active)
3781 return;
3782
ea9d758d
DV
3783 for_each_encoder_on_crtc(dev, crtc, encoder)
3784 encoder->disable(encoder);
3785
0b8765c6 3786 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW
3787 intel_crtc_wait_for_pending_flips(crtc);
3788 drm_vblank_off(dev, pipe);
0b8765c6 3789
5c3fe8b0 3790 if (dev_priv->fbc.plane == plane)
973d04f9 3791 intel_disable_fbc(dev);
79e53945 3792
0d5b8c61
VS
3793 intel_crtc_dpms_overlay(intel_crtc, false);
3794 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3795 intel_disable_planes(crtc);
b24e7179 3796 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3797
b24e7179 3798 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3799
87476d63 3800 i9xx_pfit_disable(intel_crtc);
24a1f16d 3801
89b667f8
JB
3802 for_each_encoder_on_crtc(dev, crtc, encoder)
3803 if (encoder->post_disable)
3804 encoder->post_disable(encoder);
3805
e9fd1c02
JN
3806 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3807 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3808
f7abfe8b 3809 intel_crtc->active = false;
6b383a7f
CW
3810 intel_update_fbc(dev);
3811 intel_update_watermarks(dev);
0b8765c6
JB
3812}
3813
ee7b9f93
JB
3814static void i9xx_crtc_off(struct drm_crtc *crtc)
3815{
3816}
3817
976f8a20
DV
3818static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3819 bool enabled)
2c07245f
ZW
3820{
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_master_private *master_priv;
3823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3824 int pipe = intel_crtc->pipe;
79e53945
JB
3825
3826 if (!dev->primary->master)
3827 return;
3828
3829 master_priv = dev->primary->master->driver_priv;
3830 if (!master_priv->sarea_priv)
3831 return;
3832
79e53945
JB
3833 switch (pipe) {
3834 case 0:
3835 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3836 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3837 break;
3838 case 1:
3839 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3840 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3841 break;
3842 default:
9db4a9c7 3843 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB
3844 break;
3845 }
79e53945
JB
3846}
3847
976f8a20
DV
3848/**
3849 * Sets the power management mode of the pipe and plane.
3850 */
3851void intel_crtc_update_dpms(struct drm_crtc *crtc)
3852{
3853 struct drm_device *dev = crtc->dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct intel_encoder *intel_encoder;
3856 bool enable = false;
3857
3858 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3859 enable |= intel_encoder->connectors_active;
3860
3861 if (enable)
3862 dev_priv->display.crtc_enable(crtc);
3863 else
3864 dev_priv->display.crtc_disable(crtc);
3865
3866 intel_crtc_update_sarea(crtc, enable);
3867}
3868
cdd59983
CW
3869static void intel_crtc_disable(struct drm_crtc *crtc)
3870{
cdd59983 3871 struct drm_device *dev = crtc->dev;
976f8a20 3872 struct drm_connector *connector;
ee7b9f93 3873 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3875
976f8a20
DV
3876 /* crtc should still be enabled when we disable it. */
3877 WARN_ON(!crtc->enabled);
3878
3879 dev_priv->display.crtc_disable(crtc);
c77bf565 3880 intel_crtc->eld_vld = false;
976f8a20 3881 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB
3882 dev_priv->display.off(crtc);
3883
931872fc
CW
3884 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3885 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW
3886
3887 if (crtc->fb) {
3888 mutex_lock(&dev->struct_mutex);
1690e1eb 3889 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3890 mutex_unlock(&dev->struct_mutex);
976f8a20
DV
3891 crtc->fb = NULL;
3892 }
3893
3894 /* Update computed state. */
3895 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3896 if (!connector->encoder || !connector->encoder->crtc)
3897 continue;
3898
3899 if (connector->encoder->crtc != crtc)
3900 continue;
3901
3902 connector->dpms = DRM_MODE_DPMS_OFF;
3903 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW
3904 }
3905}
3906
ea5b213a 3907void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3908{
4ef69c7a 3909 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3910
ea5b213a
CW
3911 drm_encoder_cleanup(encoder);
3912 kfree(intel_encoder);
7e7d76c3
JB
3913}
3914
9237329d 3915/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV
3916 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3917 * state of the entire output pipe. */
9237329d 3918static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3919{
5ab432ef
DV
3920 if (mode == DRM_MODE_DPMS_ON) {
3921 encoder->connectors_active = true;
3922
b2cabb0e 3923 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV
3924 } else {
3925 encoder->connectors_active = false;
3926
b2cabb0e 3927 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3928 }
79e53945
JB
3929}
3930
0a91ca29
DV
3931/* Cross check the actual hw state with our own modeset state tracking (and it's
3932 * internal consistency). */
b980514c 3933static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3934{
0a91ca29
DV
3935 if (connector->get_hw_state(connector)) {
3936 struct intel_encoder *encoder = connector->encoder;
3937 struct drm_crtc *crtc;
3938 bool encoder_enabled;
3939 enum pipe pipe;
3940
3941 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3942 connector->base.base.id,
3943 drm_get_connector_name(&connector->base));
3944
3945 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3946 "wrong connector dpms state\n");
3947 WARN(connector->base.encoder != &encoder->base,
3948 "active connector not linked to encoder\n");
3949 WARN(!encoder->connectors_active,
3950 "encoder->connectors_active not set\n");
3951
3952 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3953 WARN(!encoder_enabled, "encoder not enabled\n");
3954 if (WARN_ON(!encoder->base.crtc))
3955 return;
3956
3957 crtc = encoder->base.crtc;
3958
3959 WARN(!crtc->enabled, "crtc not enabled\n");
3960 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3961 WARN(pipe != to_intel_crtc(crtc)->pipe,
3962 "encoder active on the wrong pipe\n");
3963 }
79e53945
JB
3964}
3965
5ab432ef
DV
3966/* Even simpler default implementation, if there's really no special case to
3967 * consider. */
3968void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3969{
5ab432ef 3970 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3971
5ab432ef
DV
3972 /* All the simple cases only support two dpms states. */
3973 if (mode != DRM_MODE_DPMS_ON)
3974 mode = DRM_MODE_DPMS_OFF;
d4270e57 3975
5ab432ef
DV
3976 if (mode == connector->dpms)
3977 return;
3978
3979 connector->dpms = mode;
3980
3981 /* Only need to change hw state when actually enabled */
3982 if (encoder->base.crtc)
3983 intel_encoder_dpms(encoder, mode);
3984 else
8af6cf88 3985 WARN_ON(encoder->connectors_active != false);
0a91ca29 3986
b980514c 3987 intel_modeset_check_state(connector->dev);
79e53945
JB
3988}
3989
f0947c37
DV
3990/* Simple connector->get_hw_state implementation for encoders that support only
3991 * one connector and no cloning and hence the encoder state determines the state
3992 * of the connector. */
3993bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3994{
24929352 3995 enum pipe pipe = 0;
f0947c37 3996 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3997
f0947c37 3998 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW
3999}
4000
1857e1da
DV
4001static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4002 struct intel_crtc_config *pipe_config)
4003{
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005 struct intel_crtc *pipe_B_crtc =
4006 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4007
4008 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4009 pipe_name(pipe), pipe_config->fdi_lanes);
4010 if (pipe_config->fdi_lanes > 4) {
4011 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4012 pipe_name(pipe), pipe_config->fdi_lanes);
4013 return false;
4014 }
4015
4016 if (IS_HASWELL(dev)) {
4017 if (pipe_config->fdi_lanes > 2) {
4018 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4019 pipe_config->fdi_lanes);
4020 return false;
4021 } else {
4022 return true;
4023 }
4024 }
4025
4026 if (INTEL_INFO(dev)->num_pipes == 2)
4027 return true;
4028
4029 /* Ivybridge 3 pipe is really complicated */
4030 switch (pipe) {
4031 case PIPE_A:
4032 return true;
4033 case PIPE_B:
4034 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4035 pipe_config->fdi_lanes > 2) {
4036 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4037 pipe_name(pipe), pipe_config->fdi_lanes);
4038 return false;
4039 }
4040 return true;
4041 case PIPE_C:
1e833f40 4042 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV
4043 pipe_B_crtc->config.fdi_lanes <= 2) {
4044 if (pipe_config->fdi_lanes > 2) {
4045 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4046 pipe_name(pipe), pipe_config->fdi_lanes);
4047 return false;
4048 }
4049 } else {
4050 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4051 return false;
4052 }
4053 return true;
4054 default:
4055 BUG();
4056 }
4057}
4058
e29c22c0
DV
4059#define RETRY 1
4060static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4061 struct intel_crtc_config *pipe_config)
877d48d5 4062{
1857e1da 4063 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4064 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4065 int lane, link_bw, fdi_dotclock;
e29c22c0 4066 bool setup_ok, needs_recompute = false;
877d48d5 4067
e29c22c0 4068retry:
877d48d5
DV
4069 /* FDI is a binary signal running at ~2.7GHz, encoding
4070 * each output octet as 10 bits. The actual frequency
4071 * is stored as a divider into a 100MHz clock, and the
4072 * mode pixel clock is stored in units of 1KHz.
4073 * Hence the bw of each lane in terms of the mode signal
4074 * is:
4075 */
4076 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4077
ff9a6750 4078 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4079 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4080
2bd89a07 4081 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV
4082 pipe_config->pipe_bpp);
4083
4084 pipe_config->fdi_lanes = lane;
4085
2bd89a07 4086 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4087 link_bw, &pipe_config->fdi_m_n);
1857e1da 4088
e29c22c0
DV
4089 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4090 intel_crtc->pipe, pipe_config);
4091 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4092 pipe_config->pipe_bpp -= 2*3;
4093 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4094 pipe_config->pipe_bpp);
4095 needs_recompute = true;
4096 pipe_config->bw_constrained = true;
4097
4098 goto retry;
4099 }
4100
4101 if (needs_recompute)
4102 return RETRY;
4103
4104 return setup_ok ? 0 : -EINVAL;
877d48d5
DV
4105}
4106
42db64ef
PZ
4107static void hsw_compute_ips_config(struct intel_crtc *crtc,
4108 struct intel_crtc_config *pipe_config)
4109{
3c4ca58c
PZ
4110 pipe_config->ips_enabled = i915_enable_ips &&
4111 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4112 pipe_config->pipe_bpp <= 24;
42db64ef
PZ
4113}
4114
a43f6e0f 4115static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4116 struct intel_crtc_config *pipe_config)
79e53945 4117{
a43f6e0f 4118 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4119 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4120
bad720ff 4121 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4122 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV
4123 if (pipe_config->requested_mode.clock * 3
4124 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4125 return -EINVAL;
2c07245f 4126 }
89749350 4127
8693a824
DL
4128 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW
4130 */
4131 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4133 return -EINVAL;
44f46b42 4134
bd080ee5 4135 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4136 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4137 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV
4138 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139 * for lvds. */
4140 pipe_config->pipe_bpp = 8*3;
4141 }
4142
f5adf94e 4143 if (HAS_IPS(dev))
a43f6e0f
DV
4144 hsw_compute_ips_config(crtc, pipe_config);
4145
4146 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4147 * clock survives for now. */
4148 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4149 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4150
877d48d5 4151 if (pipe_config->has_pch_encoder)
a43f6e0f 4152 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4153
e29c22c0 4154 return 0;
79e53945
JB
4155}
4156
25eb05fc
JB
4157static int valleyview_get_display_clock_speed(struct drm_device *dev)
4158{
4159 return 400000; /* FIXME */
4160}
4161
e70236a8
JB
4162static int i945_get_display_clock_speed(struct drm_device *dev)
4163{
4164 return 400000;
4165}
79e53945 4166
e70236a8 4167static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4168{
e70236a8
JB
4169 return 333000;
4170}
79e53945 4171
e70236a8
JB
4172static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4173{
4174 return 200000;
4175}
79e53945 4176
257a7ffc
DV
4177static int pnv_get_display_clock_speed(struct drm_device *dev)
4178{
4179 u16 gcfgc = 0;
4180
4181 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4182
4183 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4184 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4185 return 267000;
4186 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4187 return 333000;
4188 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4189 return 444000;
4190 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4191 return 200000;
4192 default:
4193 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4194 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4195 return 133000;
4196 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4197 return 167000;
4198 }
4199}
4200
e70236a8
JB
4201static int i915gm_get_display_clock_speed(struct drm_device *dev)
4202{
4203 u16 gcfgc = 0;
79e53945 4204
e70236a8
JB
4205 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4206
4207 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4208 return 133000;
4209 else {
4210 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4211 case GC_DISPLAY_CLOCK_333_MHZ:
4212 return 333000;
4213 default:
4214 case GC_DISPLAY_CLOCK_190_200_MHZ:
4215 return 190000;
79e53945 4216 }
e70236a8
JB
4217 }
4218}
4219
4220static int i865_get_display_clock_speed(struct drm_device *dev)
4221{
4222 return 266000;
4223}
4224
4225static int i855_get_display_clock_speed(struct drm_device *dev)
4226{
4227 u16 hpllcc = 0;
4228 /* Assume that the hardware is in the high speed state. This
4229 * should be the default.
4230 */
4231 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4232 case GC_CLOCK_133_200:
4233 case GC_CLOCK_100_200:
4234 return 200000;
4235 case GC_CLOCK_166_250:
4236 return 250000;
4237 case GC_CLOCK_100_133:
79e53945 4238 return 133000;
e70236a8 4239 }
79e53945 4240
e70236a8
JB
4241 /* Shouldn't happen */
4242 return 0;
4243}
79e53945 4244
e70236a8
JB
4245static int i830_get_display_clock_speed(struct drm_device *dev)
4246{
4247 return 133000;
79e53945
JB
4248}
4249
2c07245f 4250static void
a65851af 4251intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4252{
a65851af
VS
4253 while (*num > DATA_LINK_M_N_MASK ||
4254 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW
4255 *num >>= 1;
4256 *den >>= 1;
4257 }
4258}
4259
a65851af
VS
4260static void compute_m_n(unsigned int m, unsigned int n,
4261 uint32_t *ret_m, uint32_t *ret_n)
4262{
4263 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4264 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4265 intel_reduce_m_n_ratio(ret_m, ret_n);
4266}
4267
e69d0bc1
DV
4268void
4269intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4270 int pixel_clock, int link_clock,
4271 struct intel_link_m_n *m_n)
2c07245f 4272{
e69d0bc1 4273 m_n->tu = 64;
a65851af
VS
4274
4275 compute_m_n(bits_per_pixel * pixel_clock,
4276 link_clock * nlanes * 8,
4277 &m_n->gmch_m, &m_n->gmch_n);
4278
4279 compute_m_n(pixel_clock, link_clock,
4280 &m_n->link_m, &m_n->link_n);
2c07245f
ZW
4281}
4282
a7615030
CW
4283static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4284{
72bbe58c
KP
4285 if (i915_panel_use_ssc >= 0)
4286 return i915_panel_use_ssc != 0;
41aa3448 4287 return dev_priv->vbt.lvds_use_ssc
435793df 4288 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW
4289}
4290
a0c4da24
JB
4291static int vlv_get_refclk(struct drm_crtc *crtc)
4292{
4293 struct drm_device *dev = crtc->dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int refclk = 27000; /* for DP & HDMI */
4296
4297 return 100000; /* only one validated so far */
4298
4299 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4300 refclk = 96000;
4301 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4302 if (intel_panel_use_ssc(dev_priv))
4303 refclk = 100000;
4304 else
4305 refclk = 96000;
4306 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4307 refclk = 100000;
4308 }
4309
4310 return refclk;
4311}
4312
c65d77d8
JB
4313static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4314{
4315 struct drm_device *dev = crtc->dev;
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 int refclk;
4318
a0c4da24
JB
4319 if (IS_VALLEYVIEW(dev)) {
4320 refclk = vlv_get_refclk(crtc);
4321 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4322 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4323 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB
4324 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4325 refclk / 1000);
4326 } else if (!IS_GEN2(dev)) {
4327 refclk = 96000;
4328 } else {
4329 refclk = 48000;
4330 }
4331
4332 return refclk;
4333}
4334
7429e9d4 4335static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4336{
7df00d7a 4337 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4338}
f47709a9 4339
7429e9d4
DV
4340static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4341{
4342 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB
4343}
4344
f47709a9 4345static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB
4346 intel_clock_t *reduced_clock)
4347{
f47709a9 4348 struct drm_device *dev = crtc->base.dev;
a7516a05 4349 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4350 int pipe = crtc->pipe;
a7516a05
JB
4351 u32 fp, fp2 = 0;
4352
4353 if (IS_PINEVIEW(dev)) {
7429e9d4 4354 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4355 if (reduced_clock)
7429e9d4 4356 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4357 } else {
7429e9d4 4358 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4359 if (reduced_clock)
7429e9d4 4360 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB
4361 }
4362
4363 I915_WRITE(FP0(pipe), fp);
8bcc2795 4364 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4365
f47709a9
DV
4366 crtc->lowfreq_avail = false;
4367 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB
4368 reduced_clock && i915_powersave) {
4369 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4370 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4371 crtc->lowfreq_avail = true;
a7516a05
JB
4372 } else {
4373 I915_WRITE(FP1(pipe), fp);
8bcc2795 4374 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB
4375 }
4376}
4377
89b667f8
JB
4378static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4379{
4380 u32 reg_val;
4381
4382 /*
4383 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4384 * and set it to a reasonable value instead.
4385 */
ae99258f 4386 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB
4387 reg_val &= 0xffffff00;
4388 reg_val |= 0x00000030;
ae99258f 4389 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4390
ae99258f 4391 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB
4392 reg_val &= 0x8cffffff;
4393 reg_val = 0x8c000000;
ae99258f 4394 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4395
ae99258f 4396 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4397 reg_val &= 0xffffff00;
ae99258f 4398 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4399
ae99258f 4400 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB
4401 reg_val &= 0x00ffffff;
4402 reg_val |= 0xb0000000;
ae99258f 4403 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB
4404}
4405
b551842d
DV
4406static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4407 struct intel_link_m_n *m_n)
4408{
4409 struct drm_device *dev = crtc->base.dev;
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 int pipe = crtc->pipe;
4412
e3b95f1e
DV
4413 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4414 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4415 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4416 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV
4417}
4418
4419static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4420 struct intel_link_m_n *m_n)
4421{
4422 struct drm_device *dev = crtc->base.dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 int pipe = crtc->pipe;
4425 enum transcoder transcoder = crtc->config.cpu_transcoder;
4426
4427 if (INTEL_INFO(dev)->gen >= 5) {
4428 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4429 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4430 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4431 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4432 } else {
e3b95f1e
DV
4433 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4434 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4435 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4436 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV
4437 }
4438}
4439
03afc4a2
DV
4440static void intel_dp_set_m_n(struct intel_crtc *crtc)
4441{
4442 if (crtc->config.has_pch_encoder)
4443 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4444 else
4445 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4446}
4447
f47709a9 4448static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4449{
f47709a9 4450 struct drm_device *dev = crtc->base.dev;
a0c4da24 4451 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4452 int pipe = crtc->pipe;
89b667f8 4453 u32 dpll, mdiv;
a0c4da24 4454 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4455 u32 coreclk, reg_val, dpll_md;
a0c4da24 4456
09153000
DV
4457 mutex_lock(&dev_priv->dpio_lock);
4458
f47709a9
DV
4459 bestn = crtc->config.dpll.n;
4460 bestm1 = crtc->config.dpll.m1;
4461 bestm2 = crtc->config.dpll.m2;
4462 bestp1 = crtc->config.dpll.p1;
4463 bestp2 = crtc->config.dpll.p2;
a0c4da24 4464
89b667f8
JB
4465 /* See eDP HDMI DPIO driver vbios notes doc */
4466
4467 /* PLL B needs special handling */
4468 if (pipe)
4469 vlv_pllb_recal_opamp(dev_priv);
4470
4471 /* Set up Tx target for periodic Rcomp update */
ae99258f 4472 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB
4473
4474 /* Disable target IRef on PLL */
ae99258f 4475 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4476 reg_val &= 0x00ffffff;
ae99258f 4477 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB
4478
4479 /* Disable fast lock */
ae99258f 4480 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB
4481
4482 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB
4483 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4484 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4485 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4486 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB
4487
4488 /*
4489 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4490 * but we don't support that).
4491 * Note: don't use the DAC post divider as it seems unstable.
4492 */
4493 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4494 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4495
a0c4da24 4496 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4497 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4498
89b667f8 4499 /* Set HBR and RBR LPF coefficients */
ff9a6750 4500 if (crtc->config.port_clock == 162000 ||
99750bd4 4501 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4502 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4503 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4504 0x009f0003);
89b667f8 4505 else
4abb2c39 4506 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB
4507 0x00d0000f);
4508
4509 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4510 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4511 /* Use SSC source */
4512 if (!pipe)
ae99258f 4513 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB
4514 0x0df40000);
4515 else
ae99258f 4516 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB
4517 0x0df70000);
4518 } else { /* HDMI or VGA */
4519 /* Use bend source */
4520 if (!pipe)
ae99258f 4521 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB
4522 0x0df70000);
4523 else
ae99258f 4524 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB
4525 0x0df40000);
4526 }
a0c4da24 4527
ae99258f 4528 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB
4529 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4530 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4531 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4532 coreclk |= 0x01000000;
ae99258f 4533 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4534
ae99258f 4535 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4536
89b667f8
JB
4537 /* Enable DPIO clock input */
4538 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4539 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4540 if (pipe)
4541 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB
4542
4543 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV
4544 crtc->config.dpll_hw_state.dpll = dpll;
4545
ef1b460d
DV
4546 dpll_md = (crtc->config.pixel_multiplier - 1)
4547 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV
4548 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4549
89b667f8
JB
4550 if (crtc->config.has_dp_encoder)
4551 intel_dp_set_m_n(crtc);
09153000
DV
4552
4553 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB
4554}
4555
f47709a9
DV
4556static void i9xx_update_pll(struct intel_crtc *crtc,
4557 intel_clock_t *reduced_clock,
eb1cbe48
DV
4558 int num_connectors)
4559{
f47709a9 4560 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4561 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV
4562 u32 dpll;
4563 bool is_sdvo;
f47709a9 4564 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4565
f47709a9 4566 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4567
f47709a9
DV
4568 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4569 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV
4570
4571 dpll = DPLL_VGA_MODE_DIS;
4572
f47709a9 4573 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV
4574 dpll |= DPLLB_MODE_LVDS;
4575 else
4576 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4577
ef1b460d 4578 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV
4579 dpll |= (crtc->config.pixel_multiplier - 1)
4580 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4581 }
198a037f
DV
4582
4583 if (is_sdvo)
4a33e48d 4584 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4585
f47709a9 4586 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4587 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV
4588
4589 /* compute bitmask from p1 value */
4590 if (IS_PINEVIEW(dev))
4591 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4592 else {
4593 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594 if (IS_G4X(dev) && reduced_clock)
4595 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4596 }
4597 switch (clock->p2) {
4598 case 5:
4599 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4600 break;
4601 case 7:
4602 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4603 break;
4604 case 10:
4605 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4606 break;
4607 case 14:
4608 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4609 break;
4610 }
4611 if (INTEL_INFO(dev)->gen >= 4)
4612 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4613
09ede541 4614 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4615 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4616 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV
4617 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4618 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4619 else
4620 dpll |= PLL_REF_INPUT_DREFCLK;
4621
4622 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV
4623 crtc->config.dpll_hw_state.dpll = dpll;
4624
eb1cbe48 4625 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV
4626 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4627 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4628 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4629 }
66e3d5c0
DV
4630
4631 if (crtc->config.has_dp_encoder)
4632 intel_dp_set_m_n(crtc);
eb1cbe48
DV
4633}
4634
f47709a9 4635static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4636 intel_clock_t *reduced_clock,
eb1cbe48
DV
4637 int num_connectors)
4638{
f47709a9 4639 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4640 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4641 u32 dpll;
f47709a9 4642 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4643
f47709a9 4644 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4645
eb1cbe48
DV
4646 dpll = DPLL_VGA_MODE_DIS;
4647
f47709a9 4648 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV
4649 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4650 } else {
4651 if (clock->p1 == 2)
4652 dpll |= PLL_P1_DIVIDE_BY_TWO;
4653 else
4654 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4655 if (clock->p2 == 4)
4656 dpll |= PLL_P2_DIVIDE_BY_4;
4657 }
4658
4a33e48d
DV
4659 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4660 dpll |= DPLL_DVO_2X_MODE;
4661
f47709a9 4662 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV
4663 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4664 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4665 else
4666 dpll |= PLL_REF_INPUT_DREFCLK;
4667
4668 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4669 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV
4670}
4671
8a654f3b 4672static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ
4673{
4674 struct drm_device *dev = intel_crtc->base.dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4677 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV
4678 struct drm_display_mode *adjusted_mode =
4679 &intel_crtc->config.adjusted_mode;
4680 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV
4681 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4682
4683 /* We need to be careful not to changed the adjusted mode, for otherwise
4684 * the hw state checker will get angry at the mismatch. */
4685 crtc_vtotal = adjusted_mode->crtc_vtotal;
4686 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ
4687
4688 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4689 /* the chip adds 2 halflines automatically */
4d8a62ea
DV
4690 crtc_vtotal -= 1;
4691 crtc_vblank_end -= 1;
b0e77b9c
PZ
4692 vsyncshift = adjusted_mode->crtc_hsync_start
4693 - adjusted_mode->crtc_htotal / 2;
4694 } else {
4695 vsyncshift = 0;
4696 }
4697
4698 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4699 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4700
fe2b8f9d 4701 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ
4702 (adjusted_mode->crtc_hdisplay - 1) |
4703 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4704 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ
4705 (adjusted_mode->crtc_hblank_start - 1) |
4706 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4707 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ
4708 (adjusted_mode->crtc_hsync_start - 1) |
4709 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4710
fe2b8f9d 4711 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4712 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4713 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4714 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4715 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4716 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4717 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ
4718 (adjusted_mode->crtc_vsync_start - 1) |
4719 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4720
b5e508d4
PZ
4721 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4722 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4723 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4724 * bits. */
4725 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4726 (pipe == PIPE_B || pipe == PIPE_C))
4727 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4728
b0e77b9c
PZ
4729 /* pipesrc controls the size that is scaled from, which should
4730 * always be the user's requested size.
4731 */
4732 I915_WRITE(PIPESRC(pipe),
4733 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4734}
4735
1bd1bd80
DV
4736static void intel_get_pipe_timings(struct intel_crtc *crtc,
4737 struct intel_crtc_config *pipe_config)
4738{
4739 struct drm_device *dev = crtc->base.dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4742 uint32_t tmp;
4743
4744 tmp = I915_READ(HTOTAL(cpu_transcoder));
4745 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4746 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4747 tmp = I915_READ(HBLANK(cpu_transcoder));
4748 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4749 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4750 tmp = I915_READ(HSYNC(cpu_transcoder));
4751 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4752 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4753
4754 tmp = I915_READ(VTOTAL(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(VBLANK(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4760 tmp = I915_READ(VSYNC(cpu_transcoder));
4761 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4762 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4763
4764 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4765 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4766 pipe_config->adjusted_mode.crtc_vtotal += 1;
4767 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4768 }
4769
4770 tmp = I915_READ(PIPESRC(crtc->pipe));
4771 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4772 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4773}
4774
babea61d
JB
4775static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4776 struct intel_crtc_config *pipe_config)
4777{
4778 struct drm_crtc *crtc = &intel_crtc->base;
4779
4780 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4781 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4782 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4783 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4784
4785 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4786 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4787 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4788 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4789
4790 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4791
4792 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4793 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4794}
4795
84b046f3
DV
4796static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4797{
4798 struct drm_device *dev = intel_crtc->base.dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 uint32_t pipeconf;
4801
9f11a9e4 4802 pipeconf = 0;
84b046f3
DV
4803
4804 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4805 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4806 * core speed.
4807 *
4808 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4809 * pipe == 0 check?
4810 */
4811 if (intel_crtc->config.requested_mode.clock >
4812 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4813 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV
4814 }
4815
ff9ce46e
DV
4816 /* only g4x and later have fancy bpc/dither controls */
4817 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV
4818 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4819 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4820 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4821 PIPECONF_DITHER_TYPE_SP;
84b046f3 4822
ff9ce46e
DV
4823 switch (intel_crtc->config.pipe_bpp) {
4824 case 18:
4825 pipeconf |= PIPECONF_6BPC;
4826 break;
4827 case 24:
4828 pipeconf |= PIPECONF_8BPC;
4829 break;
4830 case 30:
4831 pipeconf |= PIPECONF_10BPC;
4832 break;
4833 default:
4834 /* Case prevented by intel_choose_pipe_bpp_dither. */
4835 BUG();
84b046f3
DV
4836 }
4837 }
4838
4839 if (HAS_PIPE_CXSR(dev)) {
4840 if (intel_crtc->lowfreq_avail) {
4841 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4842 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4843 } else {
4844 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV
4845 }
4846 }
4847
84b046f3
DV
4848 if (!IS_GEN2(dev) &&
4849 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4850 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4851 else
4852 pipeconf |= PIPECONF_PROGRESSIVE;
4853
9f11a9e4
DV
4854 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4855 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4856
84b046f3
DV
4857 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4858 POSTING_READ(PIPECONF(intel_crtc->pipe));
4859}
4860
f564048e 4861static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4862 int x, int y,
94352cf9 4863 struct drm_framebuffer *fb)
79e53945
JB
4864{
4865 struct drm_device *dev = crtc->dev;
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4868 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4869 int pipe = intel_crtc->pipe;
80824003 4870 int plane = intel_crtc->plane;
c751ce4f 4871 int refclk, num_connectors = 0;
652c393a 4872 intel_clock_t clock, reduced_clock;
84b046f3 4873 u32 dspcntr;
a16af721 4874 bool ok, has_reduced_clock = false;
e9fd1c02 4875 bool is_lvds = false, is_dsi = false;
5eddb70b 4876 struct intel_encoder *encoder;
d4906093 4877 const intel_limit_t *limit;
5c3b82e2 4878 int ret;
79e53945 4879
6c2b7c12 4880 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4881 switch (encoder->type) {
79e53945
JB
4882 case INTEL_OUTPUT_LVDS:
4883 is_lvds = true;
4884 break;
e9fd1c02
JN
4885 case INTEL_OUTPUT_DSI:
4886 is_dsi = true;
4887 break;
79e53945 4888 }
43565a06 4889
c751ce4f 4890 num_connectors++;
79e53945
JB
4891 }
4892
c65d77d8 4893 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4894
e9fd1c02
JN
4895 if (!is_dsi) {
4896 /*
4897 * Returns a set of divisors for the desired target clock with
4898 * the given refclk, or FALSE. The returned values represent
4899 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4900 * 2) / p1 / p2.
4901 */
4902 limit = intel_limit(crtc, refclk);
4903 ok = dev_priv->display.find_dpll(limit, crtc,
4904 intel_crtc->config.port_clock,
4905 refclk, NULL, &clock);
4906 if (!ok && !intel_crtc->config.clock_set) {
4907 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4908 return -EINVAL;
4909 }
79e53945
JB
4910 }
4911
cda4b7d3 4912 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4913 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4914
e9fd1c02 4915 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP
4916 /*
4917 * Ensure we match the reduced clock's P to the target clock.
4918 * If the clocks don't match, we can't switch the display clock
4919 * by using the FP0/FP1. In such case we will disable the LVDS
4920 * downclock feature.
4921 */
ee9300bb
DV
4922 has_reduced_clock =
4923 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4924 dev_priv->lvds_downclock,
ee9300bb 4925 refclk, &clock,
5eddb70b 4926 &reduced_clock);
7026d4ac 4927 }
f47709a9
DV
4928 /* Compat-code for transition, will disappear. */
4929 if (!intel_crtc->config.clock_set) {
4930 intel_crtc->config.dpll.n = clock.n;
4931 intel_crtc->config.dpll.m1 = clock.m1;
4932 intel_crtc->config.dpll.m2 = clock.m2;
4933 intel_crtc->config.dpll.p1 = clock.p1;
4934 intel_crtc->config.dpll.p2 = clock.p2;
4935 }
7026d4ac 4936
e9fd1c02 4937 if (IS_GEN2(dev)) {
8a654f3b 4938 i8xx_update_pll(intel_crtc,
2a8f64ca
VP
4939 has_reduced_clock ? &reduced_clock : NULL,
4940 num_connectors);
e9fd1c02
JN
4941 } else if (IS_VALLEYVIEW(dev)) {
4942 if (!is_dsi)
4943 vlv_update_pll(intel_crtc);
4944 } else {
f47709a9 4945 i9xx_update_pll(intel_crtc,
eb1cbe48 4946 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4947 num_connectors);
e9fd1c02 4948 }
79e53945 4949
79e53945
JB
4950 /* Set up the display plane register */
4951 dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
da6ecc5d
JB
4953 if (!IS_VALLEYVIEW(dev)) {
4954 if (pipe == 0)
4955 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4956 else
4957 dspcntr |= DISPPLANE_SEL_PIPE_B;
4958 }
79e53945 4959
8a654f3b 4960 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW
4961
4962 /* pipesrc and dspsize control the size that is scaled from,
4963 * which should always be the user's requested size.
79e53945 4964 */
929c77fb
EA
4965 I915_WRITE(DSPSIZE(plane),
4966 ((mode->vdisplay - 1) << 16) |
4967 (mode->hdisplay - 1));
4968 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4969
84b046f3
DV
4970 i9xx_set_pipeconf(intel_crtc);
4971
f564048e
EA
4972 I915_WRITE(DSPCNTR(plane), dspcntr);
4973 POSTING_READ(DSPCNTR(plane));
4974
94352cf9 4975 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA
4976
4977 intel_update_watermarks(dev);
4978
f564048e
EA
4979 return ret;
4980}
4981
2fa2fe9a
DV
4982static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4983 struct intel_crtc_config *pipe_config)
4984{
4985 struct drm_device *dev = crtc->base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 uint32_t tmp;
4988
4989 tmp = I915_READ(PFIT_CONTROL);
06922821
DV
4990 if (!(tmp & PFIT_ENABLE))
4991 return;
2fa2fe9a 4992
06922821 4993 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV
4994 if (INTEL_INFO(dev)->gen < 4) {
4995 if (crtc->pipe != PIPE_B)
4996 return;
2fa2fe9a
DV
4997 } else {
4998 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4999 return;
5000 }
5001
06922821 5002 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV
5003 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5004 if (INTEL_INFO(dev)->gen < 5)
5005 pipe_config->gmch_pfit.lvds_border_bits =
5006 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5007}
5008
0e8ffe1b
DV
5009static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5010 struct intel_crtc_config *pipe_config)
5011{
5012 struct drm_device *dev = crtc->base.dev;
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 uint32_t tmp;
5015
e143a21c 5016 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5017 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5018
0e8ffe1b
DV
5019 tmp = I915_READ(PIPECONF(crtc->pipe));
5020 if (!(tmp & PIPECONF_ENABLE))
5021 return false;
5022
1bd1bd80
DV
5023 intel_get_pipe_timings(crtc, pipe_config);
5024
2fa2fe9a
DV
5025 i9xx_get_pfit_config(crtc, pipe_config);
5026
6c49f241
DV
5027 if (INTEL_INFO(dev)->gen >= 4) {
5028 tmp = I915_READ(DPLL_MD(crtc->pipe));
5029 pipe_config->pixel_multiplier =
5030 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5031 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5032 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV
5033 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5034 tmp = I915_READ(DPLL(crtc->pipe));
5035 pipe_config->pixel_multiplier =
5036 ((tmp & SDVO_MULTIPLIER_MASK)
5037 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5038 } else {
5039 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5040 * port and will be fixed up in the encoder->get_config
5041 * function. */
5042 pipe_config->pixel_multiplier = 1;
5043 }
8bcc2795
DV
5044 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5045 if (!IS_VALLEYVIEW(dev)) {
5046 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5047 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS
5048 } else {
5049 /* Mask out read-only status bits. */
5050 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5051 DPLL_PORTC_READY_MASK |
5052 DPLL_PORTB_READY_MASK);
8bcc2795 5053 }
6c49f241 5054
0e8ffe1b
DV
5055 return true;
5056}
5057
dde86e2d 5058static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB
5059{
5060 struct drm_i915_private *dev_priv = dev->dev_private;
5061 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5062 struct intel_encoder *encoder;
74cfd7ac 5063 u32 val, final;
13d83a67 5064 bool has_lvds = false;
199e5d79 5065 bool has_cpu_edp = false;
199e5d79 5066 bool has_panel = false;
99eb6a01
KP
5067 bool has_ck505 = false;
5068 bool can_ssc = false;
13d83a67
JB
5069
5070 /* We need to take the global config into account */
199e5d79
KP
5071 list_for_each_entry(encoder, &mode_config->encoder_list,
5072 base.head) {
5073 switch (encoder->type) {
5074 case INTEL_OUTPUT_LVDS:
5075 has_panel = true;
5076 has_lvds = true;
5077 break;
5078 case INTEL_OUTPUT_EDP:
5079 has_panel = true;
2de6905f 5080 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP
5081 has_cpu_edp = true;
5082 break;
13d83a67
JB
5083 }
5084 }
5085
99eb6a01 5086 if (HAS_PCH_IBX(dev)) {
41aa3448 5087 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP
5088 can_ssc = has_ck505;
5089 } else {
5090 has_ck505 = false;
5091 can_ssc = true;
5092 }
5093
2de6905f
ID
5094 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5095 has_panel, has_lvds, has_ck505);
13d83a67
JB
5096
5097 /* Ironlake: try to setup display ref clock before DPLL
5098 * enabling. This is only under driver's control after
5099 * PCH B stepping, previous chipset stepping should be
5100 * ignoring this setting.
5101 */
74cfd7ac
CW
5102 val = I915_READ(PCH_DREF_CONTROL);
5103
5104 /* As we must carefully and slowly disable/enable each source in turn,
5105 * compute the final state we want first and check if we need to
5106 * make any changes at all.
5107 */
5108 final = val;
5109 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5110 if (has_ck505)
5111 final |= DREF_NONSPREAD_CK505_ENABLE;
5112 else
5113 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5114
5115 final &= ~DREF_SSC_SOURCE_MASK;
5116 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5117 final &= ~DREF_SSC1_ENABLE;
5118
5119 if (has_panel) {
5120 final |= DREF_SSC_SOURCE_ENABLE;
5121
5122 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5123 final |= DREF_SSC1_ENABLE;
5124
5125 if (has_cpu_edp) {
5126 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5127 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5128 else
5129 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5130 } else
5131 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5132 } else {
5133 final |= DREF_SSC_SOURCE_DISABLE;
5134 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5135 }
5136
5137 if (final == val)
5138 return;
5139
13d83a67 5140 /* Always enable nonspread source */
74cfd7ac 5141 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5142
99eb6a01 5143 if (has_ck505)
74cfd7ac 5144 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5145 else
74cfd7ac 5146 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5147
199e5d79 5148 if (has_panel) {
74cfd7ac
CW
5149 val &= ~DREF_SSC_SOURCE_MASK;
5150 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5151
199e5d79 5152 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5153 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5154 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5155 val |= DREF_SSC1_ENABLE;
e77166b5 5156 } else
74cfd7ac 5157 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP
5158
5159 /* Get SSC going before enabling the outputs */
74cfd7ac 5160 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
5161 POSTING_READ(PCH_DREF_CONTROL);
5162 udelay(200);
5163
74cfd7ac 5164 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB
5165
5166 /* Enable CPU source on CPU attached eDP */
199e5d79 5167 if (has_cpu_edp) {
99eb6a01 5168 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5169 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5170 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5171 }
13d83a67 5172 else
74cfd7ac 5173 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5174 } else
74cfd7ac 5175 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5176
74cfd7ac 5177 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
5178 POSTING_READ(PCH_DREF_CONTROL);
5179 udelay(200);
5180 } else {
5181 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5182
74cfd7ac 5183 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP
5184
5185 /* Turn off CPU output */
74cfd7ac 5186 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5187
74cfd7ac 5188 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
5189 POSTING_READ(PCH_DREF_CONTROL);
5190 udelay(200);
5191
5192 /* Turn off the SSC source */
74cfd7ac
CW
5193 val &= ~DREF_SSC_SOURCE_MASK;
5194 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP
5195
5196 /* Turn off SSC1 */
74cfd7ac 5197 val &= ~DREF_SSC1_ENABLE;
199e5d79 5198
74cfd7ac 5199 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB
5200 POSTING_READ(PCH_DREF_CONTROL);
5201 udelay(200);
5202 }
74cfd7ac
CW
5203
5204 BUG_ON(val != final);
13d83a67
JB
5205}
5206
f31f2d55 5207static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5208{
f31f2d55 5209 uint32_t tmp;
dde86e2d 5210
0ff066a9
PZ
5211 tmp = I915_READ(SOUTH_CHICKEN2);
5212 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5213 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5214
0ff066a9
PZ
5215 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5216 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5217 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5218
0ff066a9
PZ
5219 tmp = I915_READ(SOUTH_CHICKEN2);
5220 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5221 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5222
0ff066a9
PZ
5223 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5224 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5225 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ
5226}
5227
5228/* WaMPhyProgramming:hsw */
5229static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5230{
5231 uint32_t tmp;
dde86e2d
PZ
5232
5233 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5234 tmp &= ~(0xFF << 24);
5235 tmp |= (0x12 << 24);
5236 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5237
dde86e2d
PZ
5238 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5239 tmp |= (1 << 11);
5240 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5241
5242 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5243 tmp |= (1 << 11);
5244 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5245
dde86e2d
PZ
5246 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5247 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5248 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5249
5250 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5251 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5252 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5253
0ff066a9
PZ
5254 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5255 tmp &= ~(7 << 13);
5256 tmp |= (5 << 13);
5257 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5258
0ff066a9
PZ
5259 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5260 tmp &= ~(7 << 13);
5261 tmp |= (5 << 13);
5262 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ
5263
5264 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5265 tmp &= ~0xFF;
5266 tmp |= 0x1C;
5267 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5270 tmp &= ~0xFF;
5271 tmp |= 0x1C;
5272 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5275 tmp &= ~(0xFF << 16);
5276 tmp |= (0x1C << 16);
5277 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5280 tmp &= ~(0xFF << 16);
5281 tmp |= (0x1C << 16);
5282 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5283
0ff066a9
PZ
5284 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5285 tmp |= (1 << 27);
5286 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5287
0ff066a9
PZ
5288 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5289 tmp |= (1 << 27);
5290 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5291
0ff066a9
PZ
5292 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5293 tmp &= ~(0xF << 28);
5294 tmp |= (4 << 28);
5295 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5296
0ff066a9
PZ
5297 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5298 tmp &= ~(0xF << 28);
5299 tmp |= (4 << 28);
5300 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ
5301}
5302
2fa86a1f
PZ
5303/* Implements 3 different sequences from BSpec chapter "Display iCLK
5304 * Programming" based on the parameters passed:
5305 * - Sequence to enable CLKOUT_DP
5306 * - Sequence to enable CLKOUT_DP without spread
5307 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5308 */
5309static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5310 bool with_fdi)
f31f2d55
PZ
5311{
5312 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ
5313 uint32_t reg, tmp;
5314
5315 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5316 with_spread = true;
5317 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5318 with_fdi, "LP PCH doesn't have FDI\n"))
5319 with_fdi = false;
f31f2d55
PZ
5320
5321 mutex_lock(&dev_priv->dpio_lock);
5322
5323 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5324 tmp &= ~SBI_SSCCTL_DISABLE;
5325 tmp |= SBI_SSCCTL_PATHALT;
5326 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5327
5328 udelay(24);
5329
2fa86a1f
PZ
5330 if (with_spread) {
5331 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5332 tmp &= ~SBI_SSCCTL_PATHALT;
5333 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5334
2fa86a1f
PZ
5335 if (with_fdi) {
5336 lpt_reset_fdi_mphy(dev_priv);
5337 lpt_program_fdi_mphy(dev_priv);
5338 }
5339 }
dde86e2d 5340
2fa86a1f
PZ
5341 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5342 SBI_GEN0 : SBI_DBUFF0;
5343 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5344 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5345 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV
5346
5347 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ
5348}
5349
47701c3b
PZ
5350/* Sequence to disable CLKOUT_DP */
5351static void lpt_disable_clkout_dp(struct drm_device *dev)
5352{
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 uint32_t reg, tmp;
5355
5356 mutex_lock(&dev_priv->dpio_lock);
5357
5358 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5359 SBI_GEN0 : SBI_DBUFF0;
5360 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5361 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5362 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5363
5364 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5365 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5366 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5367 tmp |= SBI_SSCCTL_PATHALT;
5368 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5369 udelay(32);
5370 }
5371 tmp |= SBI_SSCCTL_DISABLE;
5372 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5373 }
5374
5375 mutex_unlock(&dev_priv->dpio_lock);
5376}
5377
bf8fa3d3
PZ
5378static void lpt_init_pch_refclk(struct drm_device *dev)
5379{
5380 struct drm_mode_config *mode_config = &dev->mode_config;
5381 struct intel_encoder *encoder;
5382 bool has_vga = false;
5383
5384 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5385 switch (encoder->type) {
5386 case INTEL_OUTPUT_ANALOG:
5387 has_vga = true;
5388 break;
5389 }
5390 }
5391
47701c3b
PZ
5392 if (has_vga)
5393 lpt_enable_clkout_dp(dev, true, true);
5394 else
5395 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ
5396}
5397
dde86e2d
PZ
5398/*
5399 * Initialize reference clocks when the driver loads
5400 */
5401void intel_init_pch_refclk(struct drm_device *dev)
5402{
5403 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5404 ironlake_init_pch_refclk(dev);
5405 else if (HAS_PCH_LPT(dev))
5406 lpt_init_pch_refclk(dev);
5407}
5408
d9d444cb
JB
5409static int ironlake_get_refclk(struct drm_crtc *crtc)
5410{
5411 struct drm_device *dev = crtc->dev;
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413 struct intel_encoder *encoder;
d9d444cb
JB
5414 int num_connectors = 0;
5415 bool is_lvds = false;
5416
6c2b7c12 5417 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB
5418 switch (encoder->type) {
5419 case INTEL_OUTPUT_LVDS:
5420 is_lvds = true;
5421 break;
d9d444cb
JB
5422 }
5423 num_connectors++;
5424 }
5425
5426 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5427 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV
5428 dev_priv->vbt.lvds_ssc_freq);
5429 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB
5430 }
5431
5432 return 120000;
5433}
5434
6ff93609 5435static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5436{
c8203565 5437 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB
5438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439 int pipe = intel_crtc->pipe;
c8203565
PZ
5440 uint32_t val;
5441
78114071 5442 val = 0;
c8203565 5443
965e0c48 5444 switch (intel_crtc->config.pipe_bpp) {
c8203565 5445 case 18:
dfd07d72 5446 val |= PIPECONF_6BPC;
c8203565
PZ
5447 break;
5448 case 24:
dfd07d72 5449 val |= PIPECONF_8BPC;
c8203565
PZ
5450 break;
5451 case 30:
dfd07d72 5452 val |= PIPECONF_10BPC;
c8203565
PZ
5453 break;
5454 case 36:
dfd07d72 5455 val |= PIPECONF_12BPC;
c8203565
PZ
5456 break;
5457 default:
cc769b62
PZ
5458 /* Case prevented by intel_choose_pipe_bpp_dither. */
5459 BUG();
c8203565
PZ
5460 }
5461
d8b32247 5462 if (intel_crtc->config.dither)
c8203565
PZ
5463 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5464
6ff93609 5465 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ
5466 val |= PIPECONF_INTERLACED_ILK;
5467 else
5468 val |= PIPECONF_PROGRESSIVE;
5469
50f3b016 5470 if (intel_crtc->config.limited_color_range)
3685a8f3 5471 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5472
c8203565
PZ
5473 I915_WRITE(PIPECONF(pipe), val);
5474 POSTING_READ(PIPECONF(pipe));
5475}
5476
86d3efce
VS
5477/*
5478 * Set up the pipe CSC unit.
5479 *
5480 * Currently only full range RGB to limited range RGB conversion
5481 * is supported, but eventually this should handle various
5482 * RGB<->YCbCr scenarios as well.
5483 */
50f3b016 5484static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS
5485{
5486 struct drm_device *dev = crtc->dev;
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489 int pipe = intel_crtc->pipe;
5490 uint16_t coeff = 0x7800; /* 1.0 */
5491
5492 /*
5493 * TODO: Check what kind of values actually come out of the pipe
5494 * with these coeff/postoff values and adjust to get the best
5495 * accuracy. Perhaps we even need to take the bpc value into
5496 * consideration.
5497 */
5498
50f3b016 5499 if (intel_crtc->config.limited_color_range)
86d3efce
VS
5500 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5501
5502 /*
5503 * GY/GU and RY/RU should be the other way around according
5504 * to BSpec, but reality doesn't agree. Just set them up in
5505 * a way that results in the correct picture.
5506 */
5507 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5508 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5509
5510 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5511 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5512
5513 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5514 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5515
5516 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5517 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5518 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5519
5520 if (INTEL_INFO(dev)->gen > 6) {
5521 uint16_t postoff = 0;
5522
50f3b016 5523 if (intel_crtc->config.limited_color_range)
86d3efce
VS
5524 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5525
5526 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5527 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5528 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5529
5530 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5531 } else {
5532 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5533
50f3b016 5534 if (intel_crtc->config.limited_color_range)
86d3efce
VS
5535 mode |= CSC_BLACK_SCREEN_OFFSET;
5536
5537 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5538 }
5539}
5540
6ff93609 5541static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ
5542{
5543 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5545 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ
5546 uint32_t val;
5547
3eff4faa 5548 val = 0;
ee2b0b38 5549
d8b32247 5550 if (intel_crtc->config.dither)
ee2b0b38
PZ
5551 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5552
6ff93609 5553 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ
5554 val |= PIPECONF_INTERLACED_ILK;
5555 else
5556 val |= PIPECONF_PROGRESSIVE;
5557
702e7a56
PZ
5558 I915_WRITE(PIPECONF(cpu_transcoder), val);
5559 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV
5560
5561 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5562 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ
5563}
5564
6591c6e4 5565static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ
5566 intel_clock_t *clock,
5567 bool *has_reduced_clock,
5568 intel_clock_t *reduced_clock)
5569{
5570 struct drm_device *dev = crtc->dev;
5571 struct drm_i915_private *dev_priv = dev->dev_private;
5572 struct intel_encoder *intel_encoder;
5573 int refclk;
d4906093 5574 const intel_limit_t *limit;
a16af721 5575 bool ret, is_lvds = false;
79e53945 5576
6591c6e4
PZ
5577 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5578 switch (intel_encoder->type) {
79e53945
JB
5579 case INTEL_OUTPUT_LVDS:
5580 is_lvds = true;
5581 break;
79e53945
JB
5582 }
5583 }
5584
d9d444cb 5585 refclk = ironlake_get_refclk(crtc);
79e53945 5586
d4906093
ML
5587 /*
5588 * Returns a set of divisors for the desired target clock with the given
5589 * refclk, or FALSE. The returned values represent the clock equation:
5590 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5591 */
1b894b59 5592 limit = intel_limit(crtc, refclk);
ff9a6750
DV
5593 ret = dev_priv->display.find_dpll(limit, crtc,
5594 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5595 refclk, NULL, clock);
6591c6e4
PZ
5596 if (!ret)
5597 return false;
cda4b7d3 5598
ddc9003c 5599 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP
5600 /*
5601 * Ensure we match the reduced clock's P to the target clock.
5602 * If the clocks don't match, we can't switch the display clock
5603 * by using the FP0/FP1. In such case we will disable the LVDS
5604 * downclock feature.
5605 */
ee9300bb
DV
5606 *has_reduced_clock =
5607 dev_priv->display.find_dpll(limit, crtc,
5608 dev_priv->lvds_downclock,
5609 refclk, clock,
5610 reduced_clock);
652c393a 5611 }
61e9653f 5612
6591c6e4
PZ
5613 return true;
5614}
5615
01a415fd
DV
5616static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5617{
5618 struct drm_i915_private *dev_priv = dev->dev_private;
5619 uint32_t temp;
5620
5621 temp = I915_READ(SOUTH_CHICKEN1);
5622 if (temp & FDI_BC_BIFURCATION_SELECT)
5623 return;
5624
5625 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5626 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5627
5628 temp |= FDI_BC_BIFURCATION_SELECT;
5629 DRM_DEBUG_KMS("enabling fdi C rx\n");
5630 I915_WRITE(SOUTH_CHICKEN1, temp);
5631 POSTING_READ(SOUTH_CHICKEN1);
5632}
5633
ebfd86fd 5634static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV
5635{
5636 struct drm_device *dev = intel_crtc->base.dev;
5637 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV
5638
5639 switch (intel_crtc->pipe) {
5640 case PIPE_A:
ebfd86fd 5641 break;
01a415fd 5642 case PIPE_B:
ebfd86fd 5643 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV
5644 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5645 else
5646 cpt_enable_fdi_bc_bifurcation(dev);
5647
ebfd86fd 5648 break;
01a415fd 5649 case PIPE_C:
01a415fd
DV
5650 cpt_enable_fdi_bc_bifurcation(dev);
5651
ebfd86fd 5652 break;
01a415fd
DV
5653 default:
5654 BUG();
5655 }
5656}
5657
d4b1931c
PZ
5658int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5659{
5660 /*
5661 * Account for spread spectrum to avoid
5662 * oversubscribing the link. Max center spread
5663 * is 2.5%; use 5% for safety's sake.
5664 */
5665 u32 bps = target_clock * bpp * 21 / 20;
5666 return bps / (link_bw * 8) + 1;
5667}
5668
7429e9d4 5669static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5670{
7429e9d4 5671 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ
5672}
5673
de13a2e3 5674static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5675 u32 *fp,
9a7c7890 5676 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5677{
de13a2e3 5678 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB
5679 struct drm_device *dev = crtc->dev;
5680 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ
5681 struct intel_encoder *intel_encoder;
5682 uint32_t dpll;
6cc5f341 5683 int factor, num_connectors = 0;
09ede541 5684 bool is_lvds = false, is_sdvo = false;
79e53945 5685
de13a2e3
PZ
5686 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5687 switch (intel_encoder->type) {
79e53945
JB
5688 case INTEL_OUTPUT_LVDS:
5689 is_lvds = true;
5690 break;
5691 case INTEL_OUTPUT_SDVO:
7d57382e 5692 case INTEL_OUTPUT_HDMI:
79e53945 5693 is_sdvo = true;
79e53945 5694 break;
79e53945 5695 }
43565a06 5696
c751ce4f 5697 num_connectors++;
79e53945 5698 }
79e53945 5699
c1858123 5700 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA
5701 factor = 21;
5702 if (is_lvds) {
5703 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5704 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5705 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5706 factor = 25;
09ede541 5707 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5708 factor = 20;
c1858123 5709
7429e9d4 5710 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5711 *fp |= FP_CB_TUNE;
2c07245f 5712
9a7c7890
DV
5713 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5714 *fp2 |= FP_CB_TUNE;
5715
5eddb70b 5716 dpll = 0;
2c07245f 5717
a07d6787
EA
5718 if (is_lvds)
5719 dpll |= DPLLB_MODE_LVDS;
5720 else
5721 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5722
ef1b460d
DV
5723 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5724 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV
5725
5726 if (is_sdvo)
4a33e48d 5727 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5728 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5729 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5730
a07d6787 5731 /* compute bitmask from p1 value */
7429e9d4 5732 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5733 /* also FPA1 */
7429e9d4 5734 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5735
7429e9d4 5736 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA
5737 case 5:
5738 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5739 break;
5740 case 7:
5741 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5742 break;
5743 case 10:
5744 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5745 break;
5746 case 14:
5747 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5748 break;
79e53945
JB
5749 }
5750
b4c09f3b 5751 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5752 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB
5753 else
5754 dpll |= PLL_REF_INPUT_DREFCLK;
5755
959e16d6 5756 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ
5757}
5758
5759static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ
5760 int x, int y,
5761 struct drm_framebuffer *fb)
5762{
5763 struct drm_device *dev = crtc->dev;
5764 struct drm_i915_private *dev_priv = dev->dev_private;
5765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5766 int pipe = intel_crtc->pipe;
5767 int plane = intel_crtc->plane;
5768 int num_connectors = 0;
5769 intel_clock_t clock, reduced_clock;
cbbab5bd 5770 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5771 bool ok, has_reduced_clock = false;
8b47047b 5772 bool is_lvds = false;
de13a2e3 5773 struct intel_encoder *encoder;
e2b78267 5774 struct intel_shared_dpll *pll;
de13a2e3 5775 int ret;
de13a2e3
PZ
5776
5777 for_each_encoder_on_crtc(dev, crtc, encoder) {
5778 switch (encoder->type) {
5779 case INTEL_OUTPUT_LVDS:
5780 is_lvds = true;
5781 break;
de13a2e3
PZ
5782 }
5783
5784 num_connectors++;
a07d6787 5785 }
79e53945 5786
5dc5298b
PZ
5787 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5788 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5789
ff9a6750 5790 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5791 &has_reduced_clock, &reduced_clock);
ee9300bb 5792 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ
5793 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5794 return -EINVAL;
79e53945 5795 }
f47709a9
DV
5796 /* Compat-code for transition, will disappear. */
5797 if (!intel_crtc->config.clock_set) {
5798 intel_crtc->config.dpll.n = clock.n;
5799 intel_crtc->config.dpll.m1 = clock.m1;
5800 intel_crtc->config.dpll.m2 = clock.m2;
5801 intel_crtc->config.dpll.p1 = clock.p1;
5802 intel_crtc->config.dpll.p2 = clock.p2;
5803 }
79e53945 5804
de13a2e3
PZ
5805 /* Ensure that the cursor is valid for the new mode before changing... */
5806 intel_crtc_update_cursor(crtc, true);
5807
5dc5298b 5808 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5809 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5810 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5811 if (has_reduced_clock)
7429e9d4 5812 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5813
7429e9d4 5814 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV
5815 &fp, &reduced_clock,
5816 has_reduced_clock ? &fp2 : NULL);
5817
959e16d6 5818 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV
5819 intel_crtc->config.dpll_hw_state.fp0 = fp;
5820 if (has_reduced_clock)
5821 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5822 else
5823 intel_crtc->config.dpll_hw_state.fp1 = fp;
5824
b89a1d39 5825 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5826 if (pll == NULL) {
84f44ce7
VS
5827 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5828 pipe_name(pipe));
4b645f14
JB
5829 return -EINVAL;
5830 }
ee7b9f93 5831 } else
e72f9fbf 5832 intel_put_shared_dpll(intel_crtc);
79e53945 5833
03afc4a2
DV
5834 if (intel_crtc->config.has_dp_encoder)
5835 intel_dp_set_m_n(intel_crtc);
79e53945 5836
bcd644e0
DV
5837 if (is_lvds && has_reduced_clock && i915_powersave)
5838 intel_crtc->lowfreq_avail = true;
5839 else
5840 intel_crtc->lowfreq_avail = false;
e2b78267
DV
5841
5842 if (intel_crtc->config.has_pch_encoder) {
5843 pll = intel_crtc_to_shared_dpll(intel_crtc);
5844
652c393a
JB
5845 }
5846
8a654f3b 5847 intel_set_pipe_timings(intel_crtc);
5eddb70b 5848
ca3a0ff8 5849 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV
5850 intel_cpu_transcoder_set_m_n(intel_crtc,
5851 &intel_crtc->config.fdi_m_n);
5852 }
2c07245f 5853
ebfd86fd
DV
5854 if (IS_IVYBRIDGE(dev))
5855 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5856
6ff93609 5857 ironlake_set_pipeconf(crtc);
79e53945 5858
a1f9e77e
PZ
5859 /* Set up the display plane register */
5860 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5861 POSTING_READ(DSPCNTR(plane));
79e53945 5862
94352cf9 5863 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL
5864
5865 intel_update_watermarks(dev);
5866
1857e1da 5867 return ret;
79e53945
JB
5868}
5869
72419203
DV
5870static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5871 struct intel_crtc_config *pipe_config)
5872{
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 enum transcoder transcoder = pipe_config->cpu_transcoder;
5876
5877 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5878 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5879 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5880 & ~TU_SIZE_MASK;
5881 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5882 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5883 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5884}
5885
2fa2fe9a
DV
5886static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5887 struct intel_crtc_config *pipe_config)
5888{
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 uint32_t tmp;
5892
5893 tmp = I915_READ(PF_CTL(crtc->pipe));
5894
5895 if (tmp & PF_ENABLE) {
5896 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5897 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV
5898
5899 /* We currently do not free assignements of panel fitters on
5900 * ivb/hsw (since we don't use the higher upscaling modes which
5901 * differentiates them) so just WARN about this case for now. */
5902 if (IS_GEN7(dev)) {
5903 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5904 PF_PIPE_SEL_IVB(crtc->pipe));
5905 }
2fa2fe9a 5906 }
79e53945
JB
5907}
5908
0e8ffe1b
DV
5909static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5910 struct intel_crtc_config *pipe_config)
5911{
5912 struct drm_device *dev = crtc->base.dev;
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5914 uint32_t tmp;
5915
e143a21c 5916 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5917 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5918
0e8ffe1b
DV
5919 tmp = I915_READ(PIPECONF(crtc->pipe));
5920 if (!(tmp & PIPECONF_ENABLE))
5921 return false;
5922
ab9412ba 5923 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV
5924 struct intel_shared_dpll *pll;
5925
88adfff1
DV
5926 pipe_config->has_pch_encoder = true;
5927
627eb5a3
DV
5928 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5929 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5930 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV
5931
5932 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5933
c0d43d62 5934 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV
5935 pipe_config->shared_dpll =
5936 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV
5937 } else {
5938 tmp = I915_READ(PCH_DPLL_SEL);
5939 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5940 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5941 else
5942 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5943 }
66e985c0
DV
5944
5945 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5946
5947 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5948 &pipe_config->dpll_hw_state));
c93f54cf
DV
5949
5950 tmp = pipe_config->dpll_hw_state.dpll;
5951 pipe_config->pixel_multiplier =
5952 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5953 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV
5954 } else {
5955 pipe_config->pixel_multiplier = 1;
627eb5a3
DV
5956 }
5957
1bd1bd80
DV
5958 intel_get_pipe_timings(crtc, pipe_config);
5959
2fa2fe9a
DV
5960 ironlake_get_pfit_config(crtc, pipe_config);
5961
0e8ffe1b
DV
5962 return true;
5963}
5964
be256dc7
PZ
5965static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5966{
5967 struct drm_device *dev = dev_priv->dev;
5968 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5969 struct intel_crtc *crtc;
5970 unsigned long irqflags;
bd633a7c 5971 uint32_t val;
be256dc7
PZ
5972
5973 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5974 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5975 pipe_name(crtc->pipe));
5976
5977 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5978 WARN(plls->spll_refcount, "SPLL enabled\n");
5979 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5980 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5981 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5982 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5983 "CPU PWM1 enabled\n");
5984 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5985 "CPU PWM2 enabled\n");
5986 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5987 "PCH PWM1 enabled\n");
5988 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5989 "Utility pin enabled\n");
5990 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5991
5992 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5993 val = I915_READ(DEIMR);
5994 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5995 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5996 val = I915_READ(SDEIMR);
bd633a7c 5997 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ
5998 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5999 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6000}
6001
6002/*
6003 * This function implements pieces of two sequences from BSpec:
6004 * - Sequence for display software to disable LCPLL
6005 * - Sequence for display software to allow package C8+
6006 * The steps implemented here are just the steps that actually touch the LCPLL
6007 * register. Callers should take care of disabling all the display engine
6008 * functions, doing the mode unset, fixing interrupts, etc.
6009 */
6010void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6011 bool switch_to_fclk, bool allow_power_down)
6012{
6013 uint32_t val;
6014
6015 assert_can_disable_lcpll(dev_priv);
6016
6017 val = I915_READ(LCPLL_CTL);
6018
6019 if (switch_to_fclk) {
6020 val |= LCPLL_CD_SOURCE_FCLK;
6021 I915_WRITE(LCPLL_CTL, val);
6022
6023 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6024 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6025 DRM_ERROR("Switching to FCLK failed\n");
6026
6027 val = I915_READ(LCPLL_CTL);
6028 }
6029
6030 val |= LCPLL_PLL_DISABLE;
6031 I915_WRITE(LCPLL_CTL, val);
6032 POSTING_READ(LCPLL_CTL);
6033
6034 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6035 DRM_ERROR("LCPLL still locked\n");
6036
6037 val = I915_READ(D_COMP);
6038 val |= D_COMP_COMP_DISABLE;
6039 I915_WRITE(D_COMP, val);
6040 POSTING_READ(D_COMP);
6041 ndelay(100);
6042
6043 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6044 DRM_ERROR("D_COMP RCOMP still in progress\n");
6045
6046 if (allow_power_down) {
6047 val = I915_READ(LCPLL_CTL);
6048 val |= LCPLL_POWER_DOWN_ALLOW;
6049 I915_WRITE(LCPLL_CTL, val);
6050 POSTING_READ(LCPLL_CTL);
6051 }
6052}
6053
6054/*
6055 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6056 * source.
6057 */
6058void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6059{
6060 uint32_t val;
6061
6062 val = I915_READ(LCPLL_CTL);
6063
6064 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6065 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6066 return;
6067
215733fa
PZ
6068 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6069 * we'll hang the machine! */
6070 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6071
be256dc7
PZ
6072 if (val & LCPLL_POWER_DOWN_ALLOW) {
6073 val &= ~LCPLL_POWER_DOWN_ALLOW;
6074 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6075 POSTING_READ(LCPLL_CTL);
be256dc7
PZ
6076 }
6077
6078 val = I915_READ(D_COMP);
6079 val |= D_COMP_COMP_FORCE;
6080 val &= ~D_COMP_COMP_DISABLE;
6081 I915_WRITE(D_COMP, val);
35d8f2eb 6082 POSTING_READ(D_COMP);
be256dc7
PZ
6083
6084 val = I915_READ(LCPLL_CTL);
6085 val &= ~LCPLL_PLL_DISABLE;
6086 I915_WRITE(LCPLL_CTL, val);
6087
6088 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6089 DRM_ERROR("LCPLL not locked yet\n");
6090
6091 if (val & LCPLL_CD_SOURCE_FCLK) {
6092 val = I915_READ(LCPLL_CTL);
6093 val &= ~LCPLL_CD_SOURCE_FCLK;
6094 I915_WRITE(LCPLL_CTL, val);
6095
6096 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6097 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6098 DRM_ERROR("Switching back to LCPLL failed\n");
6099 }
215733fa
PZ
6100
6101 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ
6102}
6103
c67a470b
PZ
6104void hsw_enable_pc8_work(struct work_struct *__work)
6105{
6106 struct drm_i915_private *dev_priv =
6107 container_of(to_delayed_work(__work), struct drm_i915_private,
6108 pc8.enable_work);
6109 struct drm_device *dev = dev_priv->dev;
6110 uint32_t val;
6111
6112 if (dev_priv->pc8.enabled)
6113 return;
6114
6115 DRM_DEBUG_KMS("Enabling package C8+\n");
6116
6117 dev_priv->pc8.enabled = true;
6118
6119 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6120 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6121 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6122 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6123 }
6124
6125 lpt_disable_clkout_dp(dev);
6126 hsw_pc8_disable_interrupts(dev);
6127 hsw_disable_lcpll(dev_priv, true, true);
6128}
6129
6130static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6131{
6132 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6133 WARN(dev_priv->pc8.disable_count < 1,
6134 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6135
6136 dev_priv->pc8.disable_count--;
6137 if (dev_priv->pc8.disable_count != 0)
6138 return;
6139
6140 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6141 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ
6142}
6143
6144static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6145{
6146 struct drm_device *dev = dev_priv->dev;
6147 uint32_t val;
6148
6149 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6150 WARN(dev_priv->pc8.disable_count < 0,
6151 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6152
6153 dev_priv->pc8.disable_count++;
6154 if (dev_priv->pc8.disable_count != 1)
6155 return;
6156
6157 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6158 if (!dev_priv->pc8.enabled)
6159 return;
6160
6161 DRM_DEBUG_KMS("Disabling package C8+\n");
6162
6163 hsw_restore_lcpll(dev_priv);
6164 hsw_pc8_restore_interrupts(dev);
6165 lpt_init_pch_refclk(dev);
6166
6167 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6168 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6169 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6170 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6171 }
6172
6173 intel_prepare_ddi(dev);
6174 i915_gem_init_swizzling(dev);
6175 mutex_lock(&dev_priv->rps.hw_lock);
6176 gen6_update_ring_freq(dev);
6177 mutex_unlock(&dev_priv->rps.hw_lock);
6178 dev_priv->pc8.enabled = false;
6179}
6180
6181void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6182{
6183 mutex_lock(&dev_priv->pc8.lock);
6184 __hsw_enable_package_c8(dev_priv);
6185 mutex_unlock(&dev_priv->pc8.lock);
6186}
6187
6188void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6189{
6190 mutex_lock(&dev_priv->pc8.lock);
6191 __hsw_disable_package_c8(dev_priv);
6192 mutex_unlock(&dev_priv->pc8.lock);
6193}
6194
6195static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6196{
6197 struct drm_device *dev = dev_priv->dev;
6198 struct intel_crtc *crtc;
6199 uint32_t val;
6200
6201 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6202 if (crtc->base.enabled)
6203 return false;
6204
6205 /* This case is still possible since we have the i915.disable_power_well
6206 * parameter and also the KVMr or something else might be requesting the
6207 * power well. */
6208 val = I915_READ(HSW_PWR_WELL_DRIVER);
6209 if (val != 0) {
6210 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6211 return false;
6212 }
6213
6214 return true;
6215}
6216
6217/* Since we're called from modeset_global_resources there's no way to
6218 * symmetrically increase and decrease the refcount, so we use
6219 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6220 * or not.
6221 */
6222static void hsw_update_package_c8(struct drm_device *dev)
6223{
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225 bool allow;
6226
6227 if (!i915_enable_pc8)
6228 return;
6229
6230 mutex_lock(&dev_priv->pc8.lock);
6231
6232 allow = hsw_can_enable_package_c8(dev_priv);
6233
6234 if (allow == dev_priv->pc8.requirements_met)
6235 goto done;
6236
6237 dev_priv->pc8.requirements_met = allow;
6238
6239 if (allow)
6240 __hsw_enable_package_c8(dev_priv);
6241 else
6242 __hsw_disable_package_c8(dev_priv);
6243
6244done:
6245 mutex_unlock(&dev_priv->pc8.lock);
6246}
6247
6248static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6249{
6250 if (!dev_priv->pc8.gpu_idle) {
6251 dev_priv->pc8.gpu_idle = true;
6252 hsw_enable_package_c8(dev_priv);
6253 }
6254}
6255
6256static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6257{
6258 if (dev_priv->pc8.gpu_idle) {
6259 dev_priv->pc8.gpu_idle = false;
6260 hsw_disable_package_c8(dev_priv);
6261 }
be256dc7
PZ
6262}
6263
d6dd9eb1
DV
6264static void haswell_modeset_global_resources(struct drm_device *dev)
6265{
d6dd9eb1
DV
6266 bool enable = false;
6267 struct intel_crtc *crtc;
d6dd9eb1
DV
6268
6269 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV
6270 if (!crtc->base.enabled)
6271 continue;
d6dd9eb1 6272
e7a639c4
DV
6273 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6274 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV
6275 enable = true;
6276 }
6277
d6dd9eb1 6278 intel_set_power_well(dev, enable);
c67a470b
PZ
6279
6280 hsw_update_package_c8(dev);
d6dd9eb1
DV
6281}
6282
09b4ddf9 6283static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ
6284 int x, int y,
6285 struct drm_framebuffer *fb)
6286{
6287 struct drm_device *dev = crtc->dev;
6288 struct drm_i915_private *dev_priv = dev->dev_private;
6289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6290 int plane = intel_crtc->plane;
09b4ddf9 6291 int ret;
09b4ddf9 6292
ff9a6750 6293 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ
6294 return -EINVAL;
6295
09b4ddf9
PZ
6296 /* Ensure that the cursor is valid for the new mode before changing... */
6297 intel_crtc_update_cursor(crtc, true);
6298
03afc4a2
DV
6299 if (intel_crtc->config.has_dp_encoder)
6300 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ
6301
6302 intel_crtc->lowfreq_avail = false;
09b4ddf9 6303
8a654f3b 6304 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6305
ca3a0ff8 6306 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV
6307 intel_cpu_transcoder_set_m_n(intel_crtc,
6308 &intel_crtc->config.fdi_m_n);
6309 }
09b4ddf9 6310
6ff93609 6311 haswell_set_pipeconf(crtc);
09b4ddf9 6312
50f3b016 6313 intel_set_pipe_csc(crtc);
86d3efce 6314
09b4ddf9 6315 /* Set up the display plane register */
86d3efce 6316 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ
6317 POSTING_READ(DSPCNTR(plane));
6318
6319 ret = intel_pipe_set_base(crtc, x, y, fb);
6320
6321 intel_update_watermarks(dev);
6322
1f803ee5 6323 return ret;
79e53945
JB
6324}
6325
0e8ffe1b
DV
6326static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6327 struct intel_crtc_config *pipe_config)
6328{
6329 struct drm_device *dev = crtc->base.dev;
6330 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6331 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV
6332 uint32_t tmp;
6333
e143a21c 6334 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV
6335 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6336
eccb140b
DV
6337 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6338 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6339 enum pipe trans_edp_pipe;
6340 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6341 default:
6342 WARN(1, "unknown pipe linked to edp transcoder\n");
6343 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6344 case TRANS_DDI_EDP_INPUT_A_ON:
6345 trans_edp_pipe = PIPE_A;
6346 break;
6347 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6348 trans_edp_pipe = PIPE_B;
6349 break;
6350 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6351 trans_edp_pipe = PIPE_C;
6352 break;
6353 }
6354
6355 if (trans_edp_pipe == crtc->pipe)
6356 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6357 }
6358
b97186f0 6359 if (!intel_display_power_enabled(dev,
eccb140b 6360 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ
6361 return false;
6362
eccb140b 6363 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV
6364 if (!(tmp & PIPECONF_ENABLE))
6365 return false;
6366
88adfff1 6367 /*
f196e6be 6368 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV
6369 * DDI E. So just check whether this pipe is wired to DDI E and whether
6370 * the PCH transcoder is on.
6371 */
eccb140b 6372 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6373 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6374 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV
6375 pipe_config->has_pch_encoder = true;
6376
627eb5a3
DV
6377 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6378 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6379 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV
6380
6381 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV
6382 }
6383
1bd1bd80
DV
6384 intel_get_pipe_timings(crtc, pipe_config);
6385
2fa2fe9a
DV
6386 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6387 if (intel_display_power_enabled(dev, pfit_domain))
6388 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6389
42db64ef
PZ
6390 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6391 (I915_READ(IPS_CTL) & IPS_ENABLE);
6392
6c49f241
DV
6393 pipe_config->pixel_multiplier = 1;
6394
0e8ffe1b
DV
6395 return true;
6396}
6397
f564048e 6398static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6399 int x, int y,
94352cf9 6400 struct drm_framebuffer *fb)
f564048e
EA
6401{
6402 struct drm_device *dev = crtc->dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6404 struct intel_encoder *encoder;
0b701d27 6405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6406 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6407 int pipe = intel_crtc->pipe;
f564048e
EA
6408 int ret;
6409
0b701d27 6410 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6411
b8cecdf5
DV
6412 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6413
79e53945 6414 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6415
9256aa19
DV
6416 if (ret != 0)
6417 return ret;
6418
6419 for_each_encoder_on_crtc(dev, crtc, encoder) {
6420 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6421 encoder->base.base.id,
6422 drm_get_encoder_name(&encoder->base),
6423 mode->base.id, mode->name);
36f2d1f1 6424 encoder->mode_set(encoder);
9256aa19
DV
6425 }
6426
6427 return 0;
79e53945
JB
6428}
6429
3a9627f4
WF
6430static bool intel_eld_uptodate(struct drm_connector *connector,
6431 int reg_eldv, uint32_t bits_eldv,
6432 int reg_elda, uint32_t bits_elda,
6433 int reg_edid)
6434{
6435 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6436 uint8_t *eld = connector->eld;
6437 uint32_t i;
6438
6439 i = I915_READ(reg_eldv);
6440 i &= bits_eldv;
6441
6442 if (!eld[0])
6443 return !i;
6444
6445 if (!i)
6446 return false;
6447
6448 i = I915_READ(reg_elda);
6449 i &= ~bits_elda;
6450 I915_WRITE(reg_elda, i);
6451
6452 for (i = 0; i < eld[2]; i++)
6453 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6454 return false;
6455
6456 return true;
6457}
6458
e0dac65e
WF
6459static void g4x_write_eld(struct drm_connector *connector,
6460 struct drm_crtc *crtc)
6461{
6462 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6463 uint8_t *eld = connector->eld;
6464 uint32_t eldv;
6465 uint32_t len;
6466 uint32_t i;
6467
6468 i = I915_READ(G4X_AUD_VID_DID);
6469
6470 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6471 eldv = G4X_ELDV_DEVCL_DEVBLC;
6472 else
6473 eldv = G4X_ELDV_DEVCTG;
6474
3a9627f4
WF
6475 if (intel_eld_uptodate(connector,
6476 G4X_AUD_CNTL_ST, eldv,
6477 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6478 G4X_HDMIW_HDMIEDID))
6479 return;
6480
e0dac65e
WF
6481 i = I915_READ(G4X_AUD_CNTL_ST);
6482 i &= ~(eldv | G4X_ELD_ADDR);
6483 len = (i >> 9) & 0x1f; /* ELD buffer size */
6484 I915_WRITE(G4X_AUD_CNTL_ST, i);
6485
6486 if (!eld[0])
6487 return;
6488
6489 len = min_t(uint8_t, eld[2], len);
6490 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6491 for (i = 0; i < len; i++)
6492 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6493
6494 i = I915_READ(G4X_AUD_CNTL_ST);
6495 i |= eldv;
6496 I915_WRITE(G4X_AUD_CNTL_ST, i);
6497}
6498
83358c85
WX
6499static void haswell_write_eld(struct drm_connector *connector,
6500 struct drm_crtc *crtc)
6501{
6502 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6503 uint8_t *eld = connector->eld;
6504 struct drm_device *dev = crtc->dev;
7b9f35a6 6505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX
6506 uint32_t eldv;
6507 uint32_t i;
6508 int len;
6509 int pipe = to_intel_crtc(crtc)->pipe;
6510 int tmp;
6511
6512 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6513 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6514 int aud_config = HSW_AUD_CFG(pipe);
6515 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6516
6517
6518 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6519
6520 /* Audio output enable */
6521 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6522 tmp = I915_READ(aud_cntrl_st2);
6523 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6524 I915_WRITE(aud_cntrl_st2, tmp);
6525
6526 /* Wait for 1 vertical blank */
6527 intel_wait_for_vblank(dev, pipe);
6528
6529 /* Set ELD valid state */
6530 tmp = I915_READ(aud_cntrl_st2);
6531 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6532 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6533 I915_WRITE(aud_cntrl_st2, tmp);
6534 tmp = I915_READ(aud_cntrl_st2);
6535 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6536
6537 /* Enable HDMI mode */
6538 tmp = I915_READ(aud_config);
6539 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6540 /* clear N_programing_enable and N_value_index */
6541 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6542 I915_WRITE(aud_config, tmp);
6543
6544 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6545
6546 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6547 intel_crtc->eld_vld = true;
83358c85
WX
6548
6549 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6550 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6551 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6552 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6553 } else
6554 I915_WRITE(aud_config, 0);
6555
6556 if (intel_eld_uptodate(connector,
6557 aud_cntrl_st2, eldv,
6558 aud_cntl_st, IBX_ELD_ADDRESS,
6559 hdmiw_hdmiedid))
6560 return;
6561
6562 i = I915_READ(aud_cntrl_st2);
6563 i &= ~eldv;
6564 I915_WRITE(aud_cntrl_st2, i);
6565
6566 if (!eld[0])
6567 return;
6568
6569 i = I915_READ(aud_cntl_st);
6570 i &= ~IBX_ELD_ADDRESS;
6571 I915_WRITE(aud_cntl_st, i);
6572 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6573 DRM_DEBUG_DRIVER("port num:%d\n", i);
6574
6575 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6576 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6577 for (i = 0; i < len; i++)
6578 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6579
6580 i = I915_READ(aud_cntrl_st2);
6581 i |= eldv;
6582 I915_WRITE(aud_cntrl_st2, i);
6583
6584}
6585
e0dac65e
WF
6586static void ironlake_write_eld(struct drm_connector *connector,
6587 struct drm_crtc *crtc)
6588{
6589 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6590 uint8_t *eld = connector->eld;
6591 uint32_t eldv;
6592 uint32_t i;
6593 int len;
6594 int hdmiw_hdmiedid;
b6daa025 6595 int aud_config;
e0dac65e
WF
6596 int aud_cntl_st;
6597 int aud_cntrl_st2;
9b138a83 6598 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6599
b3f33cbf 6600 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX
6601 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6602 aud_config = IBX_AUD_CFG(pipe);
6603 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6604 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6605 } else {
9b138a83
WX
6606 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6607 aud_config = CPT_AUD_CFG(pipe);
6608 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6609 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF
6610 }
6611
9b138a83 6612 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF
6613
6614 i = I915_READ(aud_cntl_st);
9b138a83 6615 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF
6616 if (!i) {
6617 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6618 /* operate blindly on all ports */
1202b4c6
WF
6619 eldv = IBX_ELD_VALIDB;
6620 eldv |= IBX_ELD_VALIDB << 4;
6621 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6622 } else {
2582a850 6623 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6624 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF
6625 }
6626
3a9627f4
WF
6627 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6628 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6629 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF
6630 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6631 } else
6632 I915_WRITE(aud_config, 0);
e0dac65e 6633
3a9627f4
WF
6634 if (intel_eld_uptodate(connector,
6635 aud_cntrl_st2, eldv,
6636 aud_cntl_st, IBX_ELD_ADDRESS,
6637 hdmiw_hdmiedid))
6638 return;
6639
e0dac65e
WF
6640 i = I915_READ(aud_cntrl_st2);
6641 i &= ~eldv;
6642 I915_WRITE(aud_cntrl_st2, i);
6643
6644 if (!eld[0])
6645 return;
6646
e0dac65e 6647 i = I915_READ(aud_cntl_st);
1202b4c6 6648 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF
6649 I915_WRITE(aud_cntl_st, i);
6650
6651 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6652 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6653 for (i = 0; i < len; i++)
6654 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6655
6656 i = I915_READ(aud_cntrl_st2);
6657 i |= eldv;
6658 I915_WRITE(aud_cntrl_st2, i);
6659}
6660
6661void intel_write_eld(struct drm_encoder *encoder,
6662 struct drm_display_mode *mode)
6663{
6664 struct drm_crtc *crtc = encoder->crtc;
6665 struct drm_connector *connector;
6666 struct drm_device *dev = encoder->dev;
6667 struct drm_i915_private *dev_priv = dev->dev_private;
6668
6669 connector = drm_select_eld(encoder, mode);
6670 if (!connector)
6671 return;
6672
6673 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6674 connector->base.id,
6675 drm_get_connector_name(connector),
6676 connector->encoder->base.id,
6677 drm_get_encoder_name(connector->encoder));
6678
6679 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6680
6681 if (dev_priv->display.write_eld)
6682 dev_priv->display.write_eld(connector, crtc);
6683}
6684
79e53945
JB
6685/** Loads the palette/gamma unit for the CRTC with the prepared values */
6686void intel_crtc_load_lut(struct drm_crtc *crtc)
6687{
6688 struct drm_device *dev = crtc->dev;
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ
6691 enum pipe pipe = intel_crtc->pipe;
6692 int palreg = PALETTE(pipe);
79e53945 6693 int i;
42db64ef 6694 bool reenable_ips = false;
79e53945
JB
6695
6696 /* The clocks have to be on to load the palette. */
aed3f09d 6697 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB
6698 return;
6699
23538ef1
JN
6700 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6702 assert_dsi_pll_enabled(dev_priv);
6703 else
6704 assert_pll_enabled(dev_priv, pipe);
6705 }
14420bd0 6706
f2b115e6 6707 /* use legacy palette for Ironlake */
bad720ff 6708 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ
6709 palreg = LGC_PALETTE(pipe);
6710
6711 /* Workaround : Do not read or write the pipe palette/gamma data while
6712 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6713 */
6714 if (intel_crtc->config.ips_enabled &&
6715 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6716 GAMMA_MODE_MODE_SPLIT)) {
6717 hsw_disable_ips(intel_crtc);
6718 reenable_ips = true;
6719 }
2c07245f 6720
79e53945
JB
6721 for (i = 0; i < 256; i++) {
6722 I915_WRITE(palreg + 4 * i,
6723 (intel_crtc->lut_r[i] << 16) |
6724 (intel_crtc->lut_g[i] << 8) |
6725 intel_crtc->lut_b[i]);
6726 }
42db64ef
PZ
6727
6728 if (reenable_ips)
6729 hsw_enable_ips(intel_crtc);
79e53945
JB
6730}
6731
560b85bb
CW
6732static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6733{
6734 struct drm_device *dev = crtc->dev;
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 bool visible = base != 0;
6738 u32 cntl;
6739
6740 if (intel_crtc->cursor_visible == visible)
6741 return;
6742
9db4a9c7 6743 cntl = I915_READ(_CURACNTR);
560b85bb
CW
6744 if (visible) {
6745 /* On these chipsets we can only modify the base whilst
6746 * the cursor is disabled.
6747 */
9db4a9c7 6748 I915_WRITE(_CURABASE, base);
560b85bb
CW
6749
6750 cntl &= ~(CURSOR_FORMAT_MASK);
6751 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6752 cntl |= CURSOR_ENABLE |
6753 CURSOR_GAMMA_ENABLE |
6754 CURSOR_FORMAT_ARGB;
6755 } else
6756 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6757 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW
6758
6759 intel_crtc->cursor_visible = visible;
6760}
6761
6762static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6763{
6764 struct drm_device *dev = crtc->dev;
6765 struct drm_i915_private *dev_priv = dev->dev_private;
6766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6767 int pipe = intel_crtc->pipe;
6768 bool visible = base != 0;
6769
6770 if (intel_crtc->cursor_visible != visible) {
548f245b 6771 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW
6772 if (base) {
6773 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6774 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6775 cntl |= pipe << 28; /* Connect to correct pipe */
6776 } else {
6777 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6778 cntl |= CURSOR_MODE_DISABLE;
6779 }
9db4a9c7 6780 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW
6781
6782 intel_crtc->cursor_visible = visible;
6783 }
6784 /* and commit changes on next vblank */
9db4a9c7 6785 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW
6786}
6787
65a21cd6
JB
6788static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6789{
6790 struct drm_device *dev = crtc->dev;
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6793 int pipe = intel_crtc->pipe;
6794 bool visible = base != 0;
6795
6796 if (intel_crtc->cursor_visible != visible) {
6797 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6798 if (base) {
6799 cntl &= ~CURSOR_MODE;
6800 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6801 } else {
6802 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6803 cntl |= CURSOR_MODE_DISABLE;
6804 }
1f5d76db 6805 if (IS_HASWELL(dev)) {
86d3efce 6806 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ
6807 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6808 }
65a21cd6
JB
6809 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6810
6811 intel_crtc->cursor_visible = visible;
6812 }
6813 /* and commit changes on next vblank */
6814 I915_WRITE(CURBASE_IVB(pipe), base);
6815}
6816
cda4b7d3 6817/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW
6818static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6819 bool on)
cda4b7d3
CW
6820{
6821 struct drm_device *dev = crtc->dev;
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6824 int pipe = intel_crtc->pipe;
6825 int x = intel_crtc->cursor_x;
6826 int y = intel_crtc->cursor_y;
560b85bb 6827 u32 base, pos;
cda4b7d3
CW
6828 bool visible;
6829
6830 pos = 0;
6831
6b383a7f 6832 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW
6833 base = intel_crtc->cursor_addr;
6834 if (x > (int) crtc->fb->width)
6835 base = 0;
6836
6837 if (y > (int) crtc->fb->height)
6838 base = 0;
6839 } else
6840 base = 0;
6841
6842 if (x < 0) {
6843 if (x + intel_crtc->cursor_width < 0)
6844 base = 0;
6845
6846 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6847 x = -x;
6848 }
6849 pos |= x << CURSOR_X_SHIFT;
6850
6851 if (y < 0) {
6852 if (y + intel_crtc->cursor_height < 0)
6853 base = 0;
6854
6855 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6856 y = -y;
6857 }
6858 pos |= y << CURSOR_Y_SHIFT;
6859
6860 visible = base != 0;
560b85bb 6861 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW
6862 return;
6863
0cd83aa9 6864 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB
6865 I915_WRITE(CURPOS_IVB(pipe), pos);
6866 ivb_update_cursor(crtc, base);
6867 } else {
6868 I915_WRITE(CURPOS(pipe), pos);
6869 if (IS_845G(dev) || IS_I865G(dev))
6870 i845_update_cursor(crtc, base);
6871 else
6872 i9xx_update_cursor(crtc, base);
6873 }
cda4b7d3
CW
6874}
6875
79e53945 6876static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6877 struct drm_file *file,
79e53945
JB
6878 uint32_t handle,
6879 uint32_t width, uint32_t height)
6880{
6881 struct drm_device *dev = crtc->dev;
6882 struct drm_i915_private *dev_priv = dev->dev_private;
6883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6884 struct drm_i915_gem_object *obj;
cda4b7d3 6885 uint32_t addr;
3f8bc370 6886 int ret;
79e53945 6887
79e53945
JB
6888 /* if we want to turn off the cursor ignore width and height */
6889 if (!handle) {
28c97730 6890 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6891 addr = 0;
05394f39 6892 obj = NULL;
5004417d 6893 mutex_lock(&dev->struct_mutex);
3f8bc370 6894 goto finish;
79e53945
JB
6895 }
6896
6897 /* Currently we only support 64x64 cursors */
6898 if (width != 64 || height != 64) {
6899 DRM_ERROR("we currently only support 64x64 cursors\n");
6900 return -EINVAL;
6901 }
6902
05394f39 6903 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6904 if (&obj->base == NULL)
79e53945
JB
6905 return -ENOENT;
6906
05394f39 6907 if (obj->base.size < width * height * 4) {
79e53945 6908 DRM_ERROR("buffer is to small\n");
34b8686e
DA
6909 ret = -ENOMEM;
6910 goto fail;
79e53945
JB
6911 }
6912
71acb5eb 6913 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6914 mutex_lock(&dev->struct_mutex);
b295d1b6 6915 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW
6916 unsigned alignment;
6917
d9e86c0e
CW
6918 if (obj->tiling_mode) {
6919 DRM_ERROR("cursor cannot be tiled\n");
6920 ret = -EINVAL;
6921 goto fail_locked;
6922 }
6923
693db184
CW
6924 /* Note that the w/a also requires 2 PTE of padding following
6925 * the bo. We currently fill all unused PTE with the shadow
6926 * page and so we should always have valid PTE following the
6927 * cursor preventing the VT-d warning.
6928 */
6929 alignment = 0;
6930 if (need_vtd_wa(dev))
6931 alignment = 64*1024;
6932
6933 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW
6934 if (ret) {
6935 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6936 goto fail_locked;
e7b526bb
CW
6937 }
6938
d9e86c0e
CW
6939 ret = i915_gem_object_put_fence(obj);
6940 if (ret) {
2da3b9b9 6941 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW
6942 goto fail_unpin;
6943 }
6944
f343c5f6 6945 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6946 } else {
6eeefaf3 6947 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6948 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW
6949 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6950 align);
71acb5eb
DA
6951 if (ret) {
6952 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6953 goto fail_locked;
71acb5eb 6954 }
05394f39 6955 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH
6956 }
6957
a6c45cf0 6958 if (IS_GEN2(dev))
14b60391
JB
6959 I915_WRITE(CURSIZE, (height << 12) | width);
6960
3f8bc370 6961 finish:
3f8bc370 6962 if (intel_crtc->cursor_bo) {
b295d1b6 6963 if (dev_priv->info->cursor_needs_physical) {
05394f39 6964 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA
6965 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6966 } else
cc98b413 6967 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6968 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6969 }
80824003 6970
7f9872e0 6971 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH
6972
6973 intel_crtc->cursor_addr = addr;
05394f39 6974 intel_crtc->cursor_bo = obj;
cda4b7d3
CW
6975 intel_crtc->cursor_width = width;
6976 intel_crtc->cursor_height = height;
6977
40ccc72b 6978 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6979
79e53945 6980 return 0;
e7b526bb 6981fail_unpin:
cc98b413 6982 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6983fail_locked:
34b8686e 6984 mutex_unlock(&dev->struct_mutex);
bc9025bd 6985fail:
05394f39 6986 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6987 return ret;
79e53945
JB
6988}
6989
6990static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6991{
79e53945 6992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6993
cda4b7d3
CW
6994 intel_crtc->cursor_x = x;
6995 intel_crtc->cursor_y = y;
652c393a 6996
40ccc72b 6997 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB
6998
6999 return 0;
7000}
7001
7002/** Sets the color ramps on behalf of RandR */
7003void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7004 u16 blue, int regno)
7005{
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007
7008 intel_crtc->lut_r[regno] = red >> 8;
7009 intel_crtc->lut_g[regno] = green >> 8;
7010 intel_crtc->lut_b[regno] = blue >> 8;
7011}
7012
b8c00ac5
DA
7013void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7014 u16 *blue, int regno)
7015{
7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017
7018 *red = intel_crtc->lut_r[regno] << 8;
7019 *green = intel_crtc->lut_g[regno] << 8;
7020 *blue = intel_crtc->lut_b[regno] << 8;
7021}
7022
79e53945 7023static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7024 u16 *blue, uint32_t start, uint32_t size)
79e53945 7025{
7203425a 7026 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7028
7203425a 7029 for (i = start; i < end; i++) {
79e53945
JB
7030 intel_crtc->lut_r[i] = red[i] >> 8;
7031 intel_crtc->lut_g[i] = green[i] >> 8;
7032 intel_crtc->lut_b[i] = blue[i] >> 8;
7033 }
7034
7035 intel_crtc_load_lut(crtc);
7036}
7037
79e53945
JB
7038/* VESA 640x480x72Hz mode to set on the pipe */
7039static struct drm_display_mode load_detect_mode = {
7040 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7041 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7042};
7043
d2dff872
CW
7044static struct drm_framebuffer *
7045intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7046 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW
7047 struct drm_i915_gem_object *obj)
7048{
7049 struct intel_framebuffer *intel_fb;
7050 int ret;
7051
7052 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7053 if (!intel_fb) {
7054 drm_gem_object_unreference_unlocked(&obj->base);
7055 return ERR_PTR(-ENOMEM);
7056 }
7057
7058 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7059 if (ret) {
7060 drm_gem_object_unreference_unlocked(&obj->base);
7061 kfree(intel_fb);
7062 return ERR_PTR(ret);
7063 }
7064
7065 return &intel_fb->base;
7066}
7067
7068static u32
7069intel_framebuffer_pitch_for_width(int width, int bpp)
7070{
7071 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7072 return ALIGN(pitch, 64);
7073}
7074
7075static u32
7076intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7077{
7078 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7079 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7080}
7081
7082static struct drm_framebuffer *
7083intel_framebuffer_create_for_mode(struct drm_device *dev,
7084 struct drm_display_mode *mode,
7085 int depth, int bpp)
7086{
7087 struct drm_i915_gem_object *obj;
0fed39bd 7088 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW
7089
7090 obj = i915_gem_alloc_object(dev,
7091 intel_framebuffer_size_for_mode(mode, bpp));
7092 if (obj == NULL)
7093 return ERR_PTR(-ENOMEM);
7094
7095 mode_cmd.width = mode->hdisplay;
7096 mode_cmd.height = mode->vdisplay;
308e5bcb
JB
7097 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7098 bpp);
5ca0c34a 7099 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW
7100
7101 return intel_framebuffer_create(dev, &mode_cmd, obj);
7102}
7103
7104static struct drm_framebuffer *
7105mode_fits_in_fbdev(struct drm_device *dev,
7106 struct drm_display_mode *mode)
7107{
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 struct drm_i915_gem_object *obj;
7110 struct drm_framebuffer *fb;
7111
7112 if (dev_priv->fbdev == NULL)
7113 return NULL;
7114
7115 obj = dev_priv->fbdev->ifb.obj;
7116 if (obj == NULL)
7117 return NULL;
7118
7119 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS
7120 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7121 fb->bits_per_pixel))
d2dff872
CW
7122 return NULL;
7123
01f2c773 7124 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW
7125 return NULL;
7126
7127 return fb;
7128}
7129
d2434ab7 7130bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7131 struct drm_display_mode *mode,
8261b191 7132 struct intel_load_detect_pipe *old)
79e53945
JB
7133{
7134 struct intel_crtc *intel_crtc;
d2434ab7
DV
7135 struct intel_encoder *intel_encoder =
7136 intel_attached_encoder(connector);
79e53945 7137 struct drm_crtc *possible_crtc;
4ef69c7a 7138 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
7139 struct drm_crtc *crtc = NULL;
7140 struct drm_device *dev = encoder->dev;
94352cf9 7141 struct drm_framebuffer *fb;
79e53945
JB
7142 int i = -1;
7143
d2dff872
CW
7144 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7145 connector->base.id, drm_get_connector_name(connector),
7146 encoder->base.id, drm_get_encoder_name(encoder));
7147
79e53945
JB
7148 /*
7149 * Algorithm gets a little messy:
7a5e4805 7150 *
79e53945
JB
7151 * - if the connector already has an assigned crtc, use it (but make
7152 * sure it's on first)
7a5e4805 7153 *
79e53945
JB
7154 * - try to find the first unused crtc that can drive this connector,
7155 * and use that if we find one
79e53945
JB
7156 */
7157
7158 /* See if we already have a CRTC for this connector */
7159 if (encoder->crtc) {
7160 crtc = encoder->crtc;
8261b191 7161
7b24056b
DV
7162 mutex_lock(&crtc->mutex);
7163
24218aac 7164 old->dpms_mode = connector->dpms;
8261b191
CW
7165 old->load_detect_temp = false;
7166
7167 /* Make sure the crtc and connector are running */
24218aac
DV
7168 if (connector->dpms != DRM_MODE_DPMS_ON)
7169 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7170
7173188d 7171 return true;
79e53945
JB
7172 }
7173
7174 /* Find an unused one (if possible) */
7175 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7176 i++;
7177 if (!(encoder->possible_crtcs & (1 << i)))
7178 continue;
7179 if (!possible_crtc->enabled) {
7180 crtc = possible_crtc;
7181 break;
7182 }
79e53945
JB
7183 }
7184
7185 /*
7186 * If we didn't find an unused CRTC, don't use any.
7187 */
7188 if (!crtc) {
7173188d
CW
7189 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7190 return false;
79e53945
JB
7191 }
7192
7b24056b 7193 mutex_lock(&crtc->mutex);
fc303101
DV
7194 intel_encoder->new_crtc = to_intel_crtc(crtc);
7195 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB
7196
7197 intel_crtc = to_intel_crtc(crtc);
24218aac 7198 old->dpms_mode = connector->dpms;
8261b191 7199 old->load_detect_temp = true;
d2dff872 7200 old->release_fb = NULL;
79e53945 7201
6492711d
CW
7202 if (!mode)
7203 mode = &load_detect_mode;
79e53945 7204
d2dff872
CW
7205 /* We need a framebuffer large enough to accommodate all accesses
7206 * that the plane may generate whilst we perform load detection.
7207 * We can not rely on the fbcon either being present (we get called
7208 * during its initialisation to detect all boot displays, or it may
7209 * not even exist) or that it is large enough to satisfy the
7210 * requested mode.
7211 */
94352cf9
DV
7212 fb = mode_fits_in_fbdev(dev, mode);
7213 if (fb == NULL) {
d2dff872 7214 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV
7215 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7216 old->release_fb = fb;
d2dff872
CW
7217 } else
7218 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7219 if (IS_ERR(fb)) {
d2dff872 7220 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7221 mutex_unlock(&crtc->mutex);
0e8b3d3e 7222 return false;
79e53945 7223 }
79e53945 7224
c0c36b94 7225 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7226 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW
7227 if (old->release_fb)
7228 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7229 mutex_unlock(&crtc->mutex);
0e8b3d3e 7230 return false;
79e53945 7231 }
7173188d 7232
79e53945 7233 /* let the connector get through one full cycle before testing */
9d0498a2 7234 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7235 return true;
79e53945
JB
7236}
7237
d2434ab7 7238void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7239 struct intel_load_detect_pipe *old)
79e53945 7240{
d2434ab7
DV
7241 struct intel_encoder *intel_encoder =
7242 intel_attached_encoder(connector);
4ef69c7a 7243 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7244 struct drm_crtc *crtc = encoder->crtc;
79e53945 7245
d2dff872
CW
7246 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7247 connector->base.id, drm_get_connector_name(connector),
7248 encoder->base.id, drm_get_encoder_name(encoder));
7249
8261b191 7250 if (old->load_detect_temp) {
fc303101
DV
7251 to_intel_connector(connector)->new_encoder = NULL;
7252 intel_encoder->new_crtc = NULL;
7253 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7254
36206361
DV
7255 if (old->release_fb) {
7256 drm_framebuffer_unregister_private(old->release_fb);
7257 drm_framebuffer_unreference(old->release_fb);
7258 }
d2dff872 7259
67c96400 7260 mutex_unlock(&crtc->mutex);
0622a53c 7261 return;
79e53945
JB
7262 }
7263
c751ce4f 7264 /* Switch crtc and encoder back off if necessary */
24218aac
DV
7265 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7266 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV
7267
7268 mutex_unlock(&crtc->mutex);
79e53945
JB
7269}
7270
7271/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB
7272static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7273 struct intel_crtc_config *pipe_config)
79e53945 7274{
f1f644dc 7275 struct drm_device *dev = crtc->base.dev;
79e53945 7276 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7277 int pipe = pipe_config->cpu_transcoder;
548f245b 7278 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB
7279 u32 fp;
7280 intel_clock_t clock;
7281
7282 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7283 fp = I915_READ(FP0(pipe));
79e53945 7284 else
39adb7a5 7285 fp = I915_READ(FP1(pipe));
79e53945
JB
7286
7287 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ
7288 if (IS_PINEVIEW(dev)) {
7289 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7290 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL
7291 } else {
7292 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7293 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7294 }
7295
a6c45cf0 7296 if (!IS_GEN2(dev)) {
f2b115e6
AJ
7297 if (IS_PINEVIEW(dev))
7298 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7299 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL
7300 else
7301 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB
7302 DPLL_FPA01_P1_POST_DIV_SHIFT);
7303
7304 switch (dpll & DPLL_MODE_MASK) {
7305 case DPLLB_MODE_DAC_SERIAL:
7306 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7307 5 : 10;
7308 break;
7309 case DPLLB_MODE_LVDS:
7310 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7311 7 : 14;
7312 break;
7313 default:
28c97730 7314 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7315 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB
7316 pipe_config->adjusted_mode.clock = 0;
7317 return;
79e53945
JB
7318 }
7319
ac58c3f0
DV
7320 if (IS_PINEVIEW(dev))
7321 pineview_clock(96000, &clock);
7322 else
7323 i9xx_clock(96000, &clock);
79e53945
JB
7324 } else {
7325 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7326
7327 if (is_lvds) {
7328 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7329 DPLL_FPA01_P1_POST_DIV_SHIFT);
7330 clock.p2 = 14;
7331
7332 if ((dpll & PLL_REF_INPUT_MASK) ==
7333 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7334 /* XXX: might not be 66MHz */
ac58c3f0 7335 i9xx_clock(66000, &clock);
79e53945 7336 } else
ac58c3f0 7337 i9xx_clock(48000, &clock);
79e53945
JB
7338 } else {
7339 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7340 clock.p1 = 2;
7341 else {
7342 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7343 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7344 }
7345 if (dpll & PLL_P2_DIVIDE_BY_4)
7346 clock.p2 = 4;
7347 else
7348 clock.p2 = 2;
7349
ac58c3f0 7350 i9xx_clock(48000, &clock);
79e53945
JB
7351 }
7352 }
7353
a2dc53e7 7354 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB
7355}
7356
7357static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7358 struct intel_crtc_config *pipe_config)
7359{
7360 struct drm_device *dev = crtc->base.dev;
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7363 int link_freq, repeat;
7364 u64 clock;
7365 u32 link_m, link_n;
7366
7367 repeat = pipe_config->pixel_multiplier;
7368
7369 /*
7370 * The calculation for the data clock is:
7371 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7372 * But we want to avoid losing precison if possible, so:
7373 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7374 *
7375 * and the link clock is simpler:
7376 * link_clock = (m * link_clock * repeat) / n
7377 */
7378
7379 /*
7380 * We need to get the FDI or DP link clock here to derive
7381 * the M/N dividers.
7382 *
7383 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7384 * For DP, it's either 1.62GHz or 2.7GHz.
7385 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7386 */
f1f644dc
JB
7387 if (pipe_config->has_pch_encoder)
7388 link_freq = intel_fdi_link_freq(dev) * 10000;
7389 else
7390 link_freq = pipe_config->port_clock;
7391
7392 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7393 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7394
7395 if (!link_m || !link_n)
7396 return;
79e53945 7397
f1f644dc
JB
7398 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7399 do_div(clock, link_n);
7400
7401 pipe_config->adjusted_mode.clock = clock;
79e53945
JB
7402}
7403
7404/** Returns the currently programmed mode of the given pipe. */
7405struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7406 struct drm_crtc *crtc)
7407{
548f245b 7408 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7410 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7411 struct drm_display_mode *mode;
f1f644dc 7412 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ
7413 int htot = I915_READ(HTOTAL(cpu_transcoder));
7414 int hsync = I915_READ(HSYNC(cpu_transcoder));
7415 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7416 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB
7417
7418 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7419 if (!mode)
7420 return NULL;
7421
f1f644dc
JB
7422 /*
7423 * Construct a pipe_config sufficient for getting the clock info
7424 * back out of crtc_clock_get.
7425 *
7426 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7427 * to use a real value here instead.
7428 */
e143a21c 7429 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB
7430 pipe_config.pixel_multiplier = 1;
7431 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7432
7433 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB
7434 mode->hdisplay = (htot & 0xffff) + 1;
7435 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7436 mode->hsync_start = (hsync & 0xffff) + 1;
7437 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7438 mode->vdisplay = (vtot & 0xffff) + 1;
7439 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7440 mode->vsync_start = (vsync & 0xffff) + 1;
7441 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7442
7443 drm_mode_set_name(mode);
79e53945
JB
7444
7445 return mode;
7446}
7447
3dec0095 7448static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB
7449{
7450 struct drm_device *dev = crtc->dev;
7451 drm_i915_private_t *dev_priv = dev->dev_private;
7452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453 int pipe = intel_crtc->pipe;
dbdc6479
JB
7454 int dpll_reg = DPLL(pipe);
7455 int dpll;
652c393a 7456
bad720ff 7457 if (HAS_PCH_SPLIT(dev))
652c393a
JB
7458 return;
7459
7460 if (!dev_priv->lvds_downclock_avail)
7461 return;
7462
dbdc6479 7463 dpll = I915_READ(dpll_reg);
652c393a 7464 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7465 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7466
8ac5a6d5 7467 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB
7468
7469 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7470 I915_WRITE(dpll_reg, dpll);
9d0498a2 7471 intel_wait_for_vblank(dev, pipe);
dbdc6479 7472
652c393a
JB
7473 dpll = I915_READ(dpll_reg);
7474 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7475 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7476 }
652c393a
JB
7477}
7478
7479static void intel_decrease_pllclock(struct drm_crtc *crtc)
7480{
7481 struct drm_device *dev = crtc->dev;
7482 drm_i915_private_t *dev_priv = dev->dev_private;
7483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7484
bad720ff 7485 if (HAS_PCH_SPLIT(dev))
652c393a
JB
7486 return;
7487
7488 if (!dev_priv->lvds_downclock_avail)
7489 return;
7490
7491 /*
7492 * Since this is called by a timer, we should never get here in
7493 * the manual case.
7494 */
7495 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV
7496 int pipe = intel_crtc->pipe;
7497 int dpll_reg = DPLL(pipe);
7498 int dpll;
f6e5b160 7499
44d98a61 7500 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7501
8ac5a6d5 7502 assert_panel_unlocked(dev_priv, pipe);
652c393a 7503
dc257cf1 7504 dpll = I915_READ(dpll_reg);
652c393a
JB
7505 dpll |= DISPLAY_RATE_SELECT_FPA1;
7506 I915_WRITE(dpll_reg, dpll);
9d0498a2 7507 intel_wait_for_vblank(dev, pipe);
652c393a
JB
7508 dpll = I915_READ(dpll_reg);
7509 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7510 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB
7511 }
7512
7513}
7514
f047e395
CW
7515void intel_mark_busy(struct drm_device *dev)
7516{
c67a470b
PZ
7517 struct drm_i915_private *dev_priv = dev->dev_private;
7518
7519 hsw_package_c8_gpu_busy(dev_priv);
7520 i915_update_gfx_val(dev_priv);
f047e395
CW
7521}
7522
7523void intel_mark_idle(struct drm_device *dev)
652c393a 7524{
c67a470b 7525 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7526 struct drm_crtc *crtc;
652c393a 7527
c67a470b
PZ
7528 hsw_package_c8_gpu_idle(dev_priv);
7529
652c393a
JB
7530 if (!i915_powersave)
7531 return;
7532
652c393a 7533 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB
7534 if (!crtc->fb)
7535 continue;
7536
725a5b54 7537 intel_decrease_pllclock(crtc);
652c393a 7538 }
652c393a
JB
7539}
7540
c65355bb
CW
7541void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7542 struct intel_ring_buffer *ring)
652c393a 7543{
f047e395
CW
7544 struct drm_device *dev = obj->base.dev;
7545 struct drm_crtc *crtc;
652c393a 7546
f047e395 7547 if (!i915_powersave)
acb87dfb
CW
7548 return;
7549
652c393a
JB
7550 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7551 if (!crtc->fb)
7552 continue;
7553
c65355bb
CW
7554 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7555 continue;
7556
7557 intel_increase_pllclock(crtc);
7558 if (ring && intel_fbc_enabled(dev))
7559 ring->fbc_dirty = true;
652c393a
JB
7560 }
7561}
7562
79e53945
JB
7563static void intel_crtc_destroy(struct drm_crtc *crtc)
7564{
7565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV
7566 struct drm_device *dev = crtc->dev;
7567 struct intel_unpin_work *work;
7568 unsigned long flags;
7569
7570 spin_lock_irqsave(&dev->event_lock, flags);
7571 work = intel_crtc->unpin_work;
7572 intel_crtc->unpin_work = NULL;
7573 spin_unlock_irqrestore(&dev->event_lock, flags);
7574
7575 if (work) {
7576 cancel_work_sync(&work->work);
7577 kfree(work);
7578 }
79e53945 7579
40ccc72b
MK
7580 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7581
79e53945 7582 drm_crtc_cleanup(crtc);
67e77c5a 7583
79e53945
JB
7584 kfree(intel_crtc);
7585}
7586
6b95a207
KH
7587static void intel_unpin_work_fn(struct work_struct *__work)
7588{
7589 struct intel_unpin_work *work =
7590 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7591 struct drm_device *dev = work->crtc->dev;
6b95a207 7592
b4a98e57 7593 mutex_lock(&dev->struct_mutex);
1690e1eb 7594 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW
7595 drm_gem_object_unreference(&work->pending_flip_obj->base);
7596 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7597
b4a98e57
CW
7598 intel_update_fbc(dev);
7599 mutex_unlock(&dev->struct_mutex);
7600
7601 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7602 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7603
6b95a207
KH
7604 kfree(work);
7605}
7606
1afe3e9d 7607static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7608 struct drm_crtc *crtc)
6b95a207
KH
7609{
7610 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH
7611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7612 struct intel_unpin_work *work;
6b95a207
KH
7613 unsigned long flags;
7614
7615 /* Ignore early vblank irqs */
7616 if (intel_crtc == NULL)
7617 return;
7618
7619 spin_lock_irqsave(&dev->event_lock, flags);
7620 work = intel_crtc->unpin_work;
e7d841ca
CW
7621
7622 /* Ensure we don't miss a work->pending update ... */
7623 smp_rmb();
7624
7625 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH
7626 spin_unlock_irqrestore(&dev->event_lock, flags);
7627 return;
7628 }
7629
e7d841ca
CW
7630 /* and that the unpin work is consistent wrt ->pending. */
7631 smp_rmb();
7632
6b95a207 7633 intel_crtc->unpin_work = NULL;
6b95a207 7634
45a066eb
RC
7635 if (work->event)
7636 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7637
0af7e4df
MK
7638 drm_vblank_put(dev, intel_crtc->pipe);
7639
6b95a207
KH
7640 spin_unlock_irqrestore(&dev->event_lock, flags);
7641
2c10d571 7642 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW
7643
7644 queue_work(dev_priv->wq, &work->work);
e5510fac
JB
7645
7646 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH
7647}
7648
1afe3e9d
JB
7649void intel_finish_page_flip(struct drm_device *dev, int pipe)
7650{
7651 drm_i915_private_t *dev_priv = dev->dev_private;
7652 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7653
49b14a5c 7654 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB
7655}
7656
7657void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7658{
7659 drm_i915_private_t *dev_priv = dev->dev_private;
7660 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7661
49b14a5c 7662 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB
7663}
7664
6b95a207
KH
7665void intel_prepare_page_flip(struct drm_device *dev, int plane)
7666{
7667 drm_i915_private_t *dev_priv = dev->dev_private;
7668 struct intel_crtc *intel_crtc =
7669 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7670 unsigned long flags;
7671
e7d841ca
CW
7672 /* NB: An MMIO update of the plane base pointer will also
7673 * generate a page-flip completion irq, i.e. every modeset
7674 * is also accompanied by a spurious intel_prepare_page_flip().
7675 */
6b95a207 7676 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW
7677 if (intel_crtc->unpin_work)
7678 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH
7679 spin_unlock_irqrestore(&dev->event_lock, flags);
7680}
7681
e7d841ca
CW
7682inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7683{
7684 /* Ensure that the work item is consistent when activating it ... */
7685 smp_wmb();
7686 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7687 /* and that it is marked active as soon as the irq could fire. */
7688 smp_wmb();
7689}
7690
8c9f3aaf
JB
7691static int intel_gen2_queue_flip(struct drm_device *dev,
7692 struct drm_crtc *crtc,
7693 struct drm_framebuffer *fb,
ed8d1975
KP
7694 struct drm_i915_gem_object *obj,
7695 uint32_t flags)
8c9f3aaf
JB
7696{
7697 struct drm_i915_private *dev_priv = dev->dev_private;
7698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7699 u32 flip_mask;
6d90c952 7700 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB
7701 int ret;
7702
6d90c952 7703 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7704 if (ret)
83d4092b 7705 goto err;
8c9f3aaf 7706
6d90c952 7707 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7708 if (ret)
83d4092b 7709 goto err_unpin;
8c9f3aaf
JB
7710
7711 /* Can't queue multiple flips, so wait for the previous
7712 * one to finish before executing the next.
7713 */
7714 if (intel_crtc->plane)
7715 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7716 else
7717 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV
7718 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7719 intel_ring_emit(ring, MI_NOOP);
7720 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7721 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7722 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7723 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7724 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW
7725
7726 intel_mark_page_flip_active(intel_crtc);
6d90c952 7727 intel_ring_advance(ring);
83d4092b
CW
7728 return 0;
7729
7730err_unpin:
7731 intel_unpin_fb_obj(obj);
7732err:
8c9f3aaf
JB
7733 return ret;
7734}
7735
7736static int intel_gen3_queue_flip(struct drm_device *dev,
7737 struct drm_crtc *crtc,
7738 struct drm_framebuffer *fb,
ed8d1975
KP
7739 struct drm_i915_gem_object *obj,
7740 uint32_t flags)
8c9f3aaf
JB
7741{
7742 struct drm_i915_private *dev_priv = dev->dev_private;
7743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7744 u32 flip_mask;
6d90c952 7745 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB
7746 int ret;
7747
6d90c952 7748 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7749 if (ret)
83d4092b 7750 goto err;
8c9f3aaf 7751
6d90c952 7752 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7753 if (ret)
83d4092b 7754 goto err_unpin;
8c9f3aaf
JB
7755
7756 if (intel_crtc->plane)
7757 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7758 else
7759 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV
7760 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7761 intel_ring_emit(ring, MI_NOOP);
7762 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7763 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7764 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7765 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV
7766 intel_ring_emit(ring, MI_NOOP);
7767
e7d841ca 7768 intel_mark_page_flip_active(intel_crtc);
6d90c952 7769 intel_ring_advance(ring);
83d4092b
CW
7770 return 0;
7771
7772err_unpin:
7773 intel_unpin_fb_obj(obj);
7774err:
8c9f3aaf
JB
7775 return ret;
7776}
7777
7778static int intel_gen4_queue_flip(struct drm_device *dev,
7779 struct drm_crtc *crtc,
7780 struct drm_framebuffer *fb,
ed8d1975
KP
7781 struct drm_i915_gem_object *obj,
7782 uint32_t flags)
8c9f3aaf
JB
7783{
7784 struct drm_i915_private *dev_priv = dev->dev_private;
7785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7786 uint32_t pf, pipesrc;
6d90c952 7787 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB
7788 int ret;
7789
6d90c952 7790 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7791 if (ret)
83d4092b 7792 goto err;
8c9f3aaf 7793
6d90c952 7794 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7795 if (ret)
83d4092b 7796 goto err_unpin;
8c9f3aaf
JB
7797
7798 /* i965+ uses the linear or tiled offsets from the
7799 * Display Registers (which do not change across a page-flip)
7800 * so we need only reprogram the base address.
7801 */
6d90c952
DV
7802 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7803 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7804 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7805 intel_ring_emit(ring,
f343c5f6 7806 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7807 obj->tiling_mode);
8c9f3aaf
JB
7808
7809 /* XXX Enabling the panel-fitter across page-flip is so far
7810 * untested on non-native modes, so ignore it for now.
7811 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7812 */
7813 pf = 0;
7814 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7815 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW
7816
7817 intel_mark_page_flip_active(intel_crtc);
6d90c952 7818 intel_ring_advance(ring);
83d4092b
CW
7819 return 0;
7820
7821err_unpin:
7822 intel_unpin_fb_obj(obj);
7823err:
8c9f3aaf
JB
7824 return ret;
7825}
7826
7827static int intel_gen6_queue_flip(struct drm_device *dev,
7828 struct drm_crtc *crtc,
7829 struct drm_framebuffer *fb,
ed8d1975
KP
7830 struct drm_i915_gem_object *obj,
7831 uint32_t flags)
8c9f3aaf
JB
7832{
7833 struct drm_i915_private *dev_priv = dev->dev_private;
7834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7835 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB
7836 uint32_t pf, pipesrc;
7837 int ret;
7838
6d90c952 7839 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7840 if (ret)
83d4092b 7841 goto err;
8c9f3aaf 7842
6d90c952 7843 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7844 if (ret)
83d4092b 7845 goto err_unpin;
8c9f3aaf 7846
6d90c952
DV
7847 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7848 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7849 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7850 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7851
dc257cf1
DV
7852 /* Contrary to the suggestions in the documentation,
7853 * "Enable Panel Fitter" does not seem to be required when page
7854 * flipping with a non-native mode, and worse causes a normal
7855 * modeset to fail.
7856 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7857 */
7858 pf = 0;
8c9f3aaf 7859 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7860 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW
7861
7862 intel_mark_page_flip_active(intel_crtc);
6d90c952 7863 intel_ring_advance(ring);
83d4092b
CW
7864 return 0;
7865
7866err_unpin:
7867 intel_unpin_fb_obj(obj);
7868err:
8c9f3aaf
JB
7869 return ret;
7870}
7871
7c9017e5
JB
7872static int intel_gen7_queue_flip(struct drm_device *dev,
7873 struct drm_crtc *crtc,
7874 struct drm_framebuffer *fb,
ed8d1975
KP
7875 struct drm_i915_gem_object *obj,
7876 uint32_t flags)
7c9017e5
JB
7877{
7878 struct drm_i915_private *dev_priv = dev->dev_private;
7879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7880 struct intel_ring_buffer *ring;
cb05d8de 7881 uint32_t plane_bit = 0;
ffe74d75
CW
7882 int len, ret;
7883
7884 ring = obj->ring;
7885 if (ring == NULL || ring->id != RCS)
7886 ring = &dev_priv->ring[BCS];
7c9017e5
JB
7887
7888 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7889 if (ret)
83d4092b 7890 goto err;
7c9017e5 7891
cb05d8de
DV
7892 switch(intel_crtc->plane) {
7893 case PLANE_A:
7894 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7895 break;
7896 case PLANE_B:
7897 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7898 break;
7899 case PLANE_C:
7900 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7901 break;
7902 default:
7903 WARN_ONCE(1, "unknown plane in flip command\n");
7904 ret = -ENODEV;
ab3951eb 7905 goto err_unpin;
cb05d8de
DV
7906 }
7907
ffe74d75
CW
7908 len = 4;
7909 if (ring->id == RCS)
7910 len += 6;
7911
7912 ret = intel_ring_begin(ring, len);
7c9017e5 7913 if (ret)
83d4092b 7914 goto err_unpin;
7c9017e5 7915
ffe74d75
CW
7916 /* Unmask the flip-done completion message. Note that the bspec says that
7917 * we should do this for both the BCS and RCS, and that we must not unmask
7918 * more than one flip event at any time (or ensure that one flip message
7919 * can be sent by waiting for flip-done prior to queueing new flips).
7920 * Experimentation says that BCS works despite DERRMR masking all
7921 * flip-done completion events and that unmasking all planes at once
7922 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7923 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7924 */
7925 if (ring->id == RCS) {
7926 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7927 intel_ring_emit(ring, DERRMR);
7928 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7929 DERRMR_PIPEB_PRI_FLIP_DONE |
7930 DERRMR_PIPEC_PRI_FLIP_DONE));
7931 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7932 intel_ring_emit(ring, DERRMR);
7933 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7934 }
7935
cb05d8de 7936 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7937 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7938 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7939 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW
7940
7941 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7942 intel_ring_advance(ring);
83d4092b
CW
7943 return 0;
7944
7945err_unpin:
7946 intel_unpin_fb_obj(obj);
7947err:
7c9017e5
JB
7948 return ret;
7949}
7950
8c9f3aaf
JB
7951static int intel_default_queue_flip(struct drm_device *dev,
7952 struct drm_crtc *crtc,
7953 struct drm_framebuffer *fb,
ed8d1975
KP
7954 struct drm_i915_gem_object *obj,
7955 uint32_t flags)
8c9f3aaf
JB
7956{
7957 return -ENODEV;
7958}
7959
6b95a207
KH
7960static int intel_crtc_page_flip(struct drm_crtc *crtc,
7961 struct drm_framebuffer *fb,
ed8d1975
KP
7962 struct drm_pending_vblank_event *event,
7963 uint32_t page_flip_flags)
6b95a207
KH
7964{
7965 struct drm_device *dev = crtc->dev;
7966 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS
7967 struct drm_framebuffer *old_fb = crtc->fb;
7968 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH
7969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7970 struct intel_unpin_work *work;
8c9f3aaf 7971 unsigned long flags;
52e68630 7972 int ret;
6b95a207 7973
e6a595d2
VS
7974 /* Can't change pixel format via MI display flips. */
7975 if (fb->pixel_format != crtc->fb->pixel_format)
7976 return -EINVAL;
7977
7978 /*
7979 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7980 * Note that pitch changes could also affect these register.
7981 */
7982 if (INTEL_INFO(dev)->gen > 3 &&
7983 (fb->offsets[0] != crtc->fb->offsets[0] ||
7984 fb->pitches[0] != crtc->fb->pitches[0]))
7985 return -EINVAL;
7986
6b95a207
KH
7987 work = kzalloc(sizeof *work, GFP_KERNEL);
7988 if (work == NULL)
7989 return -ENOMEM;
7990
6b95a207 7991 work->event = event;
b4a98e57 7992 work->crtc = crtc;
4a35f83b 7993 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH
7994 INIT_WORK(&work->work, intel_unpin_work_fn);
7995
7317c75e
JB
7996 ret = drm_vblank_get(dev, intel_crtc->pipe);
7997 if (ret)
7998 goto free_work;
7999
6b95a207
KH
8000 /* We borrow the event spin lock for protecting unpin_work */
8001 spin_lock_irqsave(&dev->event_lock, flags);
8002 if (intel_crtc->unpin_work) {
8003 spin_unlock_irqrestore(&dev->event_lock, flags);
8004 kfree(work);
7317c75e 8005 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW
8006
8007 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH
8008 return -EBUSY;
8009 }
8010 intel_crtc->unpin_work = work;
8011 spin_unlock_irqrestore(&dev->event_lock, flags);
8012
b4a98e57
CW
8013 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8014 flush_workqueue(dev_priv->wq);
8015
79158103
CW
8016 ret = i915_mutex_lock_interruptible(dev);
8017 if (ret)
8018 goto cleanup;
6b95a207 8019
75dfca80 8020 /* Reference the objects for the scheduled work. */
05394f39
CW
8021 drm_gem_object_reference(&work->old_fb_obj->base);
8022 drm_gem_object_reference(&obj->base);
6b95a207
KH
8023
8024 crtc->fb = fb;
96b099fd 8025
e1f99ce6 8026 work->pending_flip_obj = obj;
e1f99ce6 8027
4e5359cd
SF
8028 work->enable_stall_check = true;
8029
b4a98e57 8030 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8031 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8032
ed8d1975 8033 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB
8034 if (ret)
8035 goto cleanup_pending;
6b95a207 8036
7782de3b 8037 intel_disable_fbc(dev);
c65355bb 8038 intel_mark_fb_busy(obj, NULL);
6b95a207
KH
8039 mutex_unlock(&dev->struct_mutex);
8040
e5510fac
JB
8041 trace_i915_flip_request(intel_crtc->plane, obj);
8042
6b95a207 8043 return 0;
96b099fd 8044
8c9f3aaf 8045cleanup_pending:
b4a98e57 8046 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8047 crtc->fb = old_fb;
05394f39
CW
8048 drm_gem_object_unreference(&work->old_fb_obj->base);
8049 drm_gem_object_unreference(&obj->base);
96b099fd
CW
8050 mutex_unlock(&dev->struct_mutex);
8051
79158103 8052cleanup:
96b099fd
CW
8053 spin_lock_irqsave(&dev->event_lock, flags);
8054 intel_crtc->unpin_work = NULL;
8055 spin_unlock_irqrestore(&dev->event_lock, flags);
8056
7317c75e
JB
8057 drm_vblank_put(dev, intel_crtc->pipe);
8058free_work:
96b099fd
CW
8059 kfree(work);
8060
8061 return ret;
6b95a207
KH
8062}
8063
f6e5b160 8064static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW
8065 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8066 .load_lut = intel_crtc_load_lut,
f6e5b160
CW
8067};
8068
50f56119
DV
8069static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8070 struct drm_crtc *crtc)
8071{
8072 struct drm_device *dev;
8073 struct drm_crtc *tmp;
8074 int crtc_mask = 1;
47f1c6c9 8075
50f56119 8076 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8077
50f56119 8078 dev = crtc->dev;
47f1c6c9 8079
50f56119
DV
8080 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8081 if (tmp == crtc)
8082 break;
8083 crtc_mask <<= 1;
8084 }
47f1c6c9 8085
50f56119
DV
8086 if (encoder->possible_crtcs & crtc_mask)
8087 return true;
8088 return false;
47f1c6c9 8089}
79e53945 8090
9a935856
DV
8091/**
8092 * intel_modeset_update_staged_output_state
8093 *
8094 * Updates the staged output configuration state, e.g. after we've read out the
8095 * current hw state.
8096 */
8097static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8098{
9a935856
DV
8099 struct intel_encoder *encoder;
8100 struct intel_connector *connector;
f6e5b160 8101
9a935856
DV
8102 list_for_each_entry(connector, &dev->mode_config.connector_list,
8103 base.head) {
8104 connector->new_encoder =
8105 to_intel_encoder(connector->base.encoder);
8106 }
f6e5b160 8107
9a935856
DV
8108 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8109 base.head) {
8110 encoder->new_crtc =
8111 to_intel_crtc(encoder->base.crtc);
8112 }
f6e5b160
CW
8113}
8114
9a935856
DV
8115/**
8116 * intel_modeset_commit_output_state
8117 *
8118 * This function copies the stage display pipe configuration to the real one.
8119 */
8120static void intel_modeset_commit_output_state(struct drm_device *dev)
8121{
8122 struct intel_encoder *encoder;
8123 struct intel_connector *connector;
f6e5b160 8124
9a935856
DV
8125 list_for_each_entry(connector, &dev->mode_config.connector_list,
8126 base.head) {
8127 connector->base.encoder = &connector->new_encoder->base;
8128 }
f6e5b160 8129
9a935856
DV
8130 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8131 base.head) {
8132 encoder->base.crtc = &encoder->new_crtc->base;
8133 }
8134}
8135
050f7aeb
DV
8136static void
8137connected_sink_compute_bpp(struct intel_connector * connector,
8138 struct intel_crtc_config *pipe_config)
8139{
8140 int bpp = pipe_config->pipe_bpp;
8141
8142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8143 connector->base.base.id,
8144 drm_get_connector_name(&connector->base));
8145
8146 /* Don't use an invalid EDID bpc value */
8147 if (connector->base.display_info.bpc &&
8148 connector->base.display_info.bpc * 3 < bpp) {
8149 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8150 bpp, connector->base.display_info.bpc*3);
8151 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8152 }
8153
8154 /* Clamp bpp to 8 on screens without EDID 1.4 */
8155 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8156 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8157 bpp);
8158 pipe_config->pipe_bpp = 24;
8159 }
8160}
8161
4e53c2e0 8162static int
050f7aeb
DV
8163compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8164 struct drm_framebuffer *fb,
8165 struct intel_crtc_config *pipe_config)
4e53c2e0 8166{
050f7aeb
DV
8167 struct drm_device *dev = crtc->base.dev;
8168 struct intel_connector *connector;
4e53c2e0
DV
8169 int bpp;
8170
d42264b1
DV
8171 switch (fb->pixel_format) {
8172 case DRM_FORMAT_C8:
4e53c2e0
DV
8173 bpp = 8*3; /* since we go through a colormap */
8174 break;
d42264b1
DV
8175 case DRM_FORMAT_XRGB1555:
8176 case DRM_FORMAT_ARGB1555:
8177 /* checked in intel_framebuffer_init already */
8178 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8179 return -EINVAL;
8180 case DRM_FORMAT_RGB565:
4e53c2e0
DV
8181 bpp = 6*3; /* min is 18bpp */
8182 break;
d42264b1
DV
8183 case DRM_FORMAT_XBGR8888:
8184 case DRM_FORMAT_ABGR8888:
8185 /* checked in intel_framebuffer_init already */
8186 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8187 return -EINVAL;
8188 case DRM_FORMAT_XRGB8888:
8189 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV
8190 bpp = 8*3;
8191 break;
d42264b1
DV
8192 case DRM_FORMAT_XRGB2101010:
8193 case DRM_FORMAT_ARGB2101010:
8194 case DRM_FORMAT_XBGR2101010:
8195 case DRM_FORMAT_ABGR2101010:
8196 /* checked in intel_framebuffer_init already */
8197 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8198 return -EINVAL;
4e53c2e0
DV
8199 bpp = 10*3;
8200 break;
baba133a 8201 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV
8202 default:
8203 DRM_DEBUG_KMS("unsupported depth\n");
8204 return -EINVAL;
8205 }
8206
4e53c2e0
DV
8207 pipe_config->pipe_bpp = bpp;
8208
8209 /* Clamp display bpp to EDID value */
8210 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8211 base.head) {
1b829e05
DV
8212 if (!connector->new_encoder ||
8213 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV
8214 continue;
8215
050f7aeb 8216 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV
8217 }
8218
8219 return bpp;
8220}
8221
c0b03411
DV
8222static void intel_dump_pipe_config(struct intel_crtc *crtc,
8223 struct intel_crtc_config *pipe_config,
8224 const char *context)
8225{
8226 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8227 context, pipe_name(crtc->pipe));
8228
8229 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8230 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8231 pipe_config->pipe_bpp, pipe_config->dither);
8232 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8233 pipe_config->has_pch_encoder,
8234 pipe_config->fdi_lanes,
8235 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8236 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8237 pipe_config->fdi_m_n.tu);
8238 DRM_DEBUG_KMS("requested mode:\n");
8239 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8240 DRM_DEBUG_KMS("adjusted mode:\n");
8241 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8242 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8243 pipe_config->gmch_pfit.control,
8244 pipe_config->gmch_pfit.pgm_ratios,
8245 pipe_config->gmch_pfit.lvds_border_bits);
8246 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8247 pipe_config->pch_pfit.pos,
8248 pipe_config->pch_pfit.size);
42db64ef 8249 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV
8250}
8251
accfc0c5
DV
8252static bool check_encoder_cloning(struct drm_crtc *crtc)
8253{
8254 int num_encoders = 0;
8255 bool uncloneable_encoders = false;
8256 struct intel_encoder *encoder;
8257
8258 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8259 base.head) {
8260 if (&encoder->new_crtc->base != crtc)
8261 continue;
8262
8263 num_encoders++;
8264 if (!encoder->cloneable)
8265 uncloneable_encoders = true;
8266 }
8267
8268 return !(num_encoders > 1 && uncloneable_encoders);
8269}
8270
b8cecdf5
DV
8271static struct intel_crtc_config *
8272intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8273 struct drm_framebuffer *fb,
b8cecdf5 8274 struct drm_display_mode *mode)
ee7b9f93 8275{
7758a113 8276 struct drm_device *dev = crtc->dev;
7758a113 8277 struct intel_encoder *encoder;
b8cecdf5 8278 struct intel_crtc_config *pipe_config;
e29c22c0
DV
8279 int plane_bpp, ret = -EINVAL;
8280 bool retry = true;
ee7b9f93 8281
accfc0c5
DV
8282 if (!check_encoder_cloning(crtc)) {
8283 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8284 return ERR_PTR(-EINVAL);
8285 }
8286
b8cecdf5
DV
8287 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8288 if (!pipe_config)
7758a113
DV
8289 return ERR_PTR(-ENOMEM);
8290
b8cecdf5
DV
8291 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8292 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV
8293 pipe_config->cpu_transcoder =
8294 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8295 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8296
2960bc9c
ID
8297 /*
8298 * Sanitize sync polarity flags based on requested ones. If neither
8299 * positive or negative polarity is requested, treat this as meaning
8300 * negative polarity.
8301 */
8302 if (!(pipe_config->adjusted_mode.flags &
8303 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8304 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8305
8306 if (!(pipe_config->adjusted_mode.flags &
8307 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8308 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8309
050f7aeb
DV
8310 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8311 * plane pixel format and any sink constraints into account. Returns the
8312 * source plane bpp so that dithering can be selected on mismatches
8313 * after encoders and crtc also have had their say. */
8314 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8315 fb, pipe_config);
4e53c2e0
DV
8316 if (plane_bpp < 0)
8317 goto fail;
8318
e29c22c0 8319encoder_retry:
ef1b460d 8320 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8321 pipe_config->port_clock = 0;
ef1b460d 8322 pipe_config->pixel_multiplier = 1;
ff9a6750 8323
135c81b8
DV
8324 /* Fill in default crtc timings, allow encoders to overwrite them. */
8325 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8326
7758a113
DV
8327 /* Pass our mode to the connectors and the CRTC to give them a chance to
8328 * adjust it according to limitations or connector properties, and also
8329 * a chance to reject the mode entirely.
47f1c6c9 8330 */
7758a113
DV
8331 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8332 base.head) {
47f1c6c9 8333
7758a113
DV
8334 if (&encoder->new_crtc->base != crtc)
8335 continue;
7ae89233 8336
efea6e8e
DV
8337 if (!(encoder->compute_config(encoder, pipe_config))) {
8338 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV
8339 goto fail;
8340 }
ee7b9f93 8341 }
47f1c6c9 8342
ff9a6750
DV
8343 /* Set default port clock if not overwritten by the encoder. Needs to be
8344 * done afterwards in case the encoder adjusts the mode. */
8345 if (!pipe_config->port_clock)
8346 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8347
a43f6e0f 8348 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8349 if (ret < 0) {
7758a113
DV
8350 DRM_DEBUG_KMS("CRTC fixup failed\n");
8351 goto fail;
ee7b9f93 8352 }
e29c22c0
DV
8353
8354 if (ret == RETRY) {
8355 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8356 ret = -EINVAL;
8357 goto fail;
8358 }
8359
8360 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8361 retry = false;
8362 goto encoder_retry;
8363 }
8364
4e53c2e0
DV
8365 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8366 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8367 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8368
b8cecdf5 8369 return pipe_config;
7758a113 8370fail:
b8cecdf5 8371 kfree(pipe_config);
e29c22c0 8372 return ERR_PTR(ret);
ee7b9f93 8373}
47f1c6c9 8374
e2e1ed41
DV
8375/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8376 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8377static void
8378intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8379 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB
8380{
8381 struct intel_crtc *intel_crtc;
e2e1ed41
DV
8382 struct drm_device *dev = crtc->dev;
8383 struct intel_encoder *encoder;
8384 struct intel_connector *connector;
8385 struct drm_crtc *tmp_crtc;
79e53945 8386
e2e1ed41 8387 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8388
e2e1ed41
DV
8389 /* Check which crtcs have changed outputs connected to them, these need
8390 * to be part of the prepare_pipes mask. We don't (yet) support global
8391 * modeset across multiple crtcs, so modeset_pipes will only have one
8392 * bit set at most. */
8393 list_for_each_entry(connector, &dev->mode_config.connector_list,
8394 base.head) {
8395 if (connector->base.encoder == &connector->new_encoder->base)
8396 continue;
79e53945 8397
e2e1ed41
DV
8398 if (connector->base.encoder) {
8399 tmp_crtc = connector->base.encoder->crtc;
8400
8401 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8402 }
8403
8404 if (connector->new_encoder)
8405 *prepare_pipes |=
8406 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB
8407 }
8408
e2e1ed41
DV
8409 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8410 base.head) {
8411 if (encoder->base.crtc == &encoder->new_crtc->base)
8412 continue;
8413
8414 if (encoder->base.crtc) {
8415 tmp_crtc = encoder->base.crtc;
8416
8417 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8418 }
8419
8420 if (encoder->new_crtc)
8421 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB
8422 }
8423
e2e1ed41
DV
8424 /* Check for any pipes that will be fully disabled ... */
8425 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8426 base.head) {
8427 bool used = false;
22fd0fab 8428
e2e1ed41
DV
8429 /* Don't try to disable disabled crtcs. */
8430 if (!intel_crtc->base.enabled)
8431 continue;
7e7d76c3 8432
e2e1ed41
DV
8433 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8434 base.head) {
8435 if (encoder->new_crtc == intel_crtc)
8436 used = true;
8437 }
8438
8439 if (!used)
8440 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB
8441 }
8442
e2e1ed41
DV
8443
8444 /* set_mode is also used to update properties on life display pipes. */
8445 intel_crtc = to_intel_crtc(crtc);
8446 if (crtc->enabled)
8447 *prepare_pipes |= 1 << intel_crtc->pipe;
8448
b6c5164d
DV
8449 /*
8450 * For simplicity do a full modeset on any pipe where the output routing
8451 * changed. We could be more clever, but that would require us to be
8452 * more careful with calling the relevant encoder->mode_set functions.
8453 */
e2e1ed41
DV
8454 if (*prepare_pipes)
8455 *modeset_pipes = *prepare_pipes;
8456
8457 /* ... and mask these out. */
8458 *modeset_pipes &= ~(*disable_pipes);
8459 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV
8460
8461 /*
8462 * HACK: We don't (yet) fully support global modesets. intel_set_config
8463 * obies this rule, but the modeset restore mode of
8464 * intel_modeset_setup_hw_state does not.
8465 */
8466 *modeset_pipes &= 1 << intel_crtc->pipe;
8467 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV
8468
8469 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8470 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8471}
79e53945 8472
ea9d758d 8473static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8474{
ea9d758d 8475 struct drm_encoder *encoder;
f6e5b160 8476 struct drm_device *dev = crtc->dev;
f6e5b160 8477
ea9d758d
DV
8478 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8479 if (encoder->crtc == crtc)
8480 return true;
8481
8482 return false;
8483}
8484
8485static void
8486intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8487{
8488 struct intel_encoder *intel_encoder;
8489 struct intel_crtc *intel_crtc;
8490 struct drm_connector *connector;
8491
8492 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8493 base.head) {
8494 if (!intel_encoder->base.crtc)
8495 continue;
8496
8497 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8498
8499 if (prepare_pipes & (1 << intel_crtc->pipe))
8500 intel_encoder->connectors_active = false;
8501 }
8502
8503 intel_modeset_commit_output_state(dev);
8504
8505 /* Update computed state. */
8506 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8507 base.head) {
8508 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8509 }
8510
8511 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8512 if (!connector->encoder || !connector->encoder->crtc)
8513 continue;
8514
8515 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8516
8517 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV
8518 struct drm_property *dpms_property =
8519 dev->mode_config.dpms_property;
8520
ea9d758d 8521 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8522 drm_object_property_set_value(&connector->base,
68d34720
DV
8523 dpms_property,
8524 DRM_MODE_DPMS_ON);
ea9d758d
DV
8525
8526 intel_encoder = to_intel_encoder(connector->encoder);
8527 intel_encoder->connectors_active = true;
8528 }
8529 }
8530
8531}
8532
f1f644dc
JB
8533static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8534 struct intel_crtc_config *new)
8535{
8536 int clock1, clock2, diff;
8537
8538 clock1 = cur->adjusted_mode.clock;
8539 clock2 = new->adjusted_mode.clock;
8540
8541 if (clock1 == clock2)
8542 return true;
8543
8544 if (!clock1 || !clock2)
8545 return false;
8546
8547 diff = abs(clock1 - clock2);
8548
8549 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8550 return true;
8551
8552 return false;
8553}
8554
25c5b266
DV
8555#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8556 list_for_each_entry((intel_crtc), \
8557 &(dev)->mode_config.crtc_list, \
8558 base.head) \
0973f18f 8559 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8560
0e8ffe1b 8561static bool
2fa2fe9a
DV
8562intel_pipe_config_compare(struct drm_device *dev,
8563 struct intel_crtc_config *current_config,
0e8ffe1b
DV
8564 struct intel_crtc_config *pipe_config)
8565{
66e985c0
DV
8566#define PIPE_CONF_CHECK_X(name) \
8567 if (current_config->name != pipe_config->name) { \
8568 DRM_ERROR("mismatch in " #name " " \
8569 "(expected 0x%08x, found 0x%08x)\n", \
8570 current_config->name, \
8571 pipe_config->name); \
8572 return false; \
8573 }
8574
08a24034
DV
8575#define PIPE_CONF_CHECK_I(name) \
8576 if (current_config->name != pipe_config->name) { \
8577 DRM_ERROR("mismatch in " #name " " \
8578 "(expected %i, found %i)\n", \
8579 current_config->name, \
8580 pipe_config->name); \
8581 return false; \
88adfff1
DV
8582 }
8583
1bd1bd80
DV
8584#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8585 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8586 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV
8587 "(expected %i, found %i)\n", \
8588 current_config->name & (mask), \
8589 pipe_config->name & (mask)); \
8590 return false; \
8591 }
8592
bb760063
DV
8593#define PIPE_CONF_QUIRK(quirk) \
8594 ((current_config->quirks | pipe_config->quirks) & (quirk))
8595
eccb140b
DV
8596 PIPE_CONF_CHECK_I(cpu_transcoder);
8597
08a24034
DV
8598 PIPE_CONF_CHECK_I(has_pch_encoder);
8599 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV
8600 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8601 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8602 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8603 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8604 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8605
1bd1bd80
DV
8606 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8607 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8608 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8609 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8610 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8611 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8612
8613 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8614 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8615 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8616 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8617 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8618 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8619
c93f54cf 8620 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8621
1bd1bd80
DV
8622 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8623 DRM_MODE_FLAG_INTERLACE);
8624
bb760063
DV
8625 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8626 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8627 DRM_MODE_FLAG_PHSYNC);
8628 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8629 DRM_MODE_FLAG_NHSYNC);
8630 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8631 DRM_MODE_FLAG_PVSYNC);
8632 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8633 DRM_MODE_FLAG_NVSYNC);
8634 }
045ac3b5 8635
1bd1bd80
DV
8636 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8637 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8638
2fa2fe9a
DV
8639 PIPE_CONF_CHECK_I(gmch_pfit.control);
8640 /* pfit ratios are autocomputed by the hw on gen4+ */
8641 if (INTEL_INFO(dev)->gen < 4)
8642 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8643 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8644 PIPE_CONF_CHECK_I(pch_pfit.pos);
8645 PIPE_CONF_CHECK_I(pch_pfit.size);
8646
42db64ef
PZ
8647 PIPE_CONF_CHECK_I(ips_enabled);
8648
c0d43d62 8649 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8650 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8651 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV
8652 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8653 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8654
66e985c0 8655#undef PIPE_CONF_CHECK_X
08a24034 8656#undef PIPE_CONF_CHECK_I
1bd1bd80 8657#undef PIPE_CONF_CHECK_FLAGS
bb760063 8658#undef PIPE_CONF_QUIRK
88adfff1 8659
f1f644dc
JB
8660 if (!IS_HASWELL(dev)) {
8661 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8662 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB
8663 current_config->adjusted_mode.clock,
8664 pipe_config->adjusted_mode.clock);
8665 return false;
8666 }
8667 }
8668
0e8ffe1b
DV
8669 return true;
8670}
8671
91d1b4bd
DV
8672static void
8673check_connector_state(struct drm_device *dev)
8af6cf88 8674{
8af6cf88
DV
8675 struct intel_connector *connector;
8676
8677 list_for_each_entry(connector, &dev->mode_config.connector_list,
8678 base.head) {
8679 /* This also checks the encoder/connector hw state with the
8680 * ->get_hw_state callbacks. */
8681 intel_connector_check_state(connector);
8682
8683 WARN(&connector->new_encoder->base != connector->base.encoder,
8684 "connector's staged encoder doesn't match current encoder\n");
8685 }
91d1b4bd
DV
8686}
8687
8688static void
8689check_encoder_state(struct drm_device *dev)
8690{
8691 struct intel_encoder *encoder;
8692 struct intel_connector *connector;
8af6cf88
DV
8693
8694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8695 base.head) {
8696 bool enabled = false;
8697 bool active = false;
8698 enum pipe pipe, tracked_pipe;
8699
8700 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8701 encoder->base.base.id,
8702 drm_get_encoder_name(&encoder->base));
8703
8704 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8705 "encoder's stage crtc doesn't match current crtc\n");
8706 WARN(encoder->connectors_active && !encoder->base.crtc,
8707 "encoder's active_connectors set, but no crtc\n");
8708
8709 list_for_each_entry(connector, &dev->mode_config.connector_list,
8710 base.head) {
8711 if (connector->base.encoder != &encoder->base)
8712 continue;
8713 enabled = true;
8714 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8715 active = true;
8716 }
8717 WARN(!!encoder->base.crtc != enabled,
8718 "encoder's enabled state mismatch "
8719 "(expected %i, found %i)\n",
8720 !!encoder->base.crtc, enabled);
8721 WARN(active && !encoder->base.crtc,
8722 "active encoder with no crtc\n");
8723
8724 WARN(encoder->connectors_active != active,
8725 "encoder's computed active state doesn't match tracked active state "
8726 "(expected %i, found %i)\n", active, encoder->connectors_active);
8727
8728 active = encoder->get_hw_state(encoder, &pipe);
8729 WARN(active != encoder->connectors_active,
8730 "encoder's hw state doesn't match sw tracking "
8731 "(expected %i, found %i)\n",
8732 encoder->connectors_active, active);
8733
8734 if (!encoder->base.crtc)
8735 continue;
8736
8737 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8738 WARN(active && pipe != tracked_pipe,
8739 "active encoder's pipe doesn't match"
8740 "(expected %i, found %i)\n",
8741 tracked_pipe, pipe);
8742
8743 }
91d1b4bd
DV
8744}
8745
8746static void
8747check_crtc_state(struct drm_device *dev)
8748{
8749 drm_i915_private_t *dev_priv = dev->dev_private;
8750 struct intel_crtc *crtc;
8751 struct intel_encoder *encoder;
8752 struct intel_crtc_config pipe_config;
8af6cf88
DV
8753
8754 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8755 base.head) {
8756 bool enabled = false;
8757 bool active = false;
8758
045ac3b5
JB
8759 memset(&pipe_config, 0, sizeof(pipe_config));
8760
8af6cf88
DV
8761 DRM_DEBUG_KMS("[CRTC:%d]\n",
8762 crtc->base.base.id);
8763
8764 WARN(crtc->active && !crtc->base.enabled,
8765 "active crtc, but not enabled in sw tracking\n");
8766
8767 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8768 base.head) {
8769 if (encoder->base.crtc != &crtc->base)
8770 continue;
8771 enabled = true;
8772 if (encoder->connectors_active)
8773 active = true;
8774 }
6c49f241 8775
8af6cf88
DV
8776 WARN(active != crtc->active,
8777 "crtc's computed active state doesn't match tracked active state "
8778 "(expected %i, found %i)\n", active, crtc->active);
8779 WARN(enabled != crtc->base.enabled,
8780 "crtc's computed enabled state doesn't match tracked enabled state "
8781 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8782
0e8ffe1b
DV
8783 active = dev_priv->display.get_pipe_config(crtc,
8784 &pipe_config);
d62cf62a
DV
8785
8786 /* hw state is inconsistent with the pipe A quirk */
8787 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8788 active = crtc->active;
8789
6c49f241
DV
8790 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8791 base.head) {
3eaba51c 8792 enum pipe pipe;
6c49f241
DV
8793 if (encoder->base.crtc != &crtc->base)
8794 continue;
3eaba51c
VS
8795 if (encoder->get_config &&
8796 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV
8797 encoder->get_config(encoder, &pipe_config);
8798 }
8799
510d5f2f
JB
8800 if (dev_priv->display.get_clock)
8801 dev_priv->display.get_clock(crtc, &pipe_config);
8802
0e8ffe1b
DV
8803 WARN(crtc->active != active,
8804 "crtc active state doesn't match with hw state "
8805 "(expected %i, found %i)\n", crtc->active, active);
8806
c0b03411
DV
8807 if (active &&
8808 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8809 WARN(1, "pipe state doesn't match!\n");
8810 intel_dump_pipe_config(crtc, &pipe_config,
8811 "[hw state]");
8812 intel_dump_pipe_config(crtc, &crtc->config,
8813 "[sw state]");
8814 }
8af6cf88
DV
8815 }
8816}
8817
91d1b4bd
DV
8818static void
8819check_shared_dpll_state(struct drm_device *dev)
8820{
8821 drm_i915_private_t *dev_priv = dev->dev_private;
8822 struct intel_crtc *crtc;
8823 struct intel_dpll_hw_state dpll_hw_state;
8824 int i;
5358901f
DV
8825
8826 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8827 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8828 int enabled_crtcs = 0, active_crtcs = 0;
8829 bool active;
8830
8831 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8832
8833 DRM_DEBUG_KMS("%s\n", pll->name);
8834
8835 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8836
8837 WARN(pll->active > pll->refcount,
8838 "more active pll users than references: %i vs %i\n",
8839 pll->active, pll->refcount);
8840 WARN(pll->active && !pll->on,
8841 "pll in active use but not on in sw tracking\n");
35c95375
DV
8842 WARN(pll->on && !pll->active,
8843 "pll in on but not on in use in sw tracking\n");
5358901f
DV
8844 WARN(pll->on != active,
8845 "pll on state mismatch (expected %i, found %i)\n",
8846 pll->on, active);
8847
8848 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8849 base.head) {
8850 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8851 enabled_crtcs++;
8852 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8853 active_crtcs++;
8854 }
8855 WARN(pll->active != active_crtcs,
8856 "pll active crtcs mismatch (expected %i, found %i)\n",
8857 pll->active, active_crtcs);
8858 WARN(pll->refcount != enabled_crtcs,
8859 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8860 pll->refcount, enabled_crtcs);
66e985c0
DV
8861
8862 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8863 sizeof(dpll_hw_state)),
8864 "pll hw state mismatch\n");
5358901f 8865 }
8af6cf88
DV
8866}
8867
91d1b4bd
DV
8868void
8869intel_modeset_check_state(struct drm_device *dev)
8870{
8871 check_connector_state(dev);
8872 check_encoder_state(dev);
8873 check_crtc_state(dev);
8874 check_shared_dpll_state(dev);
8875}
8876
f30da187
DV
8877static int __intel_set_mode(struct drm_crtc *crtc,
8878 struct drm_display_mode *mode,
8879 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV
8880{
8881 struct drm_device *dev = crtc->dev;
dbf2b54e 8882 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV
8883 struct drm_display_mode *saved_mode, *saved_hwmode;
8884 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV
8885 struct intel_crtc *intel_crtc;
8886 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8887 int ret = 0;
a6778b3c 8888
3ac18232 8889 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW
8890 if (!saved_mode)
8891 return -ENOMEM;
3ac18232 8892 saved_hwmode = saved_mode + 1;
a6778b3c 8893
e2e1ed41 8894 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV
8895 &prepare_pipes, &disable_pipes);
8896
3ac18232
TG
8897 *saved_hwmode = crtc->hwmode;
8898 *saved_mode = crtc->mode;
a6778b3c 8899
25c5b266
DV
8900 /* Hack: Because we don't (yet) support global modeset on multiple
8901 * crtcs, we don't keep track of the new mode for more than one crtc.
8902 * Hence simply check whether any bit is set in modeset_pipes in all the
8903 * pieces of code that are not yet converted to deal with mutliple crtcs
8904 * changing their mode at the same time. */
25c5b266 8905 if (modeset_pipes) {
4e53c2e0 8906 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV
8907 if (IS_ERR(pipe_config)) {
8908 ret = PTR_ERR(pipe_config);
8909 pipe_config = NULL;
8910
3ac18232 8911 goto out;
25c5b266 8912 }
c0b03411
DV
8913 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8914 "[modeset]");
25c5b266 8915 }
a6778b3c 8916
460da916
DV
8917 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8918 intel_crtc_disable(&intel_crtc->base);
8919
ea9d758d
DV
8920 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8921 if (intel_crtc->base.enabled)
8922 dev_priv->display.crtc_disable(&intel_crtc->base);
8923 }
a6778b3c 8924
6c4c86f5
DV
8925 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8926 * to set it here already despite that we pass it down the callchain.
f6e5b160 8927 */
b8cecdf5 8928 if (modeset_pipes) {
25c5b266 8929 crtc->mode = *mode;
b8cecdf5
DV
8930 /* mode_set/enable/disable functions rely on a correct pipe
8931 * config. */
8932 to_intel_crtc(crtc)->config = *pipe_config;
8933 }
7758a113 8934
ea9d758d
DV
8935 /* Only after disabling all output pipelines that will be changed can we
8936 * update the the output configuration. */
8937 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8938
47fab737
DV
8939 if (dev_priv->display.modeset_global_resources)
8940 dev_priv->display.modeset_global_resources(dev);
8941
a6778b3c
DV
8942 /* Set up the DPLL and any encoders state that needs to adjust or depend
8943 * on the DPLL.
f6e5b160 8944 */
25c5b266 8945 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8946 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW
8947 x, y, fb);
8948 if (ret)
8949 goto done;
a6778b3c
DV
8950 }
8951
8952 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV
8953 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8954 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8955
25c5b266
DV
8956 if (modeset_pipes) {
8957 /* Store real post-adjustment hardware mode. */
b8cecdf5 8958 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8959
25c5b266
DV
8960 /* Calculate and store various constants which
8961 * are later needed by vblank and swap-completion
8962 * timestamping. They are derived from true hwmode.
8963 */
8964 drm_calc_timestamping_constants(crtc);
8965 }
a6778b3c
DV
8966
8967 /* FIXME: add subpixel order */
8968done:
c0c36b94 8969 if (ret && crtc->enabled) {
3ac18232
TG
8970 crtc->hwmode = *saved_hwmode;
8971 crtc->mode = *saved_mode;
a6778b3c
DV
8972 }
8973
3ac18232 8974out:
b8cecdf5 8975 kfree(pipe_config);
3ac18232 8976 kfree(saved_mode);
a6778b3c 8977 return ret;
f6e5b160
CW
8978}
8979
e7457a9a
DL
8980static int intel_set_mode(struct drm_crtc *crtc,
8981 struct drm_display_mode *mode,
8982 int x, int y, struct drm_framebuffer *fb)
f30da187
DV
8983{
8984 int ret;
8985
8986 ret = __intel_set_mode(crtc, mode, x, y, fb);
8987
8988 if (ret == 0)
8989 intel_modeset_check_state(crtc->dev);
8990
8991 return ret;
8992}
8993
c0c36b94
CW
8994void intel_crtc_restore_mode(struct drm_crtc *crtc)
8995{
8996 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8997}
8998
25c5b266
DV
8999#undef for_each_intel_crtc_masked
9000
d9e55608
DV
9001static void intel_set_config_free(struct intel_set_config *config)
9002{
9003 if (!config)
9004 return;
9005
1aa4b628
DV
9006 kfree(config->save_connector_encoders);
9007 kfree(config->save_encoder_crtcs);
d9e55608
DV
9008 kfree(config);
9009}
9010
85f9eb71
DV
9011static int intel_set_config_save_state(struct drm_device *dev,
9012 struct intel_set_config *config)
9013{
85f9eb71
DV
9014 struct drm_encoder *encoder;
9015 struct drm_connector *connector;
9016 int count;
9017
1aa4b628
DV
9018 config->save_encoder_crtcs =
9019 kcalloc(dev->mode_config.num_encoder,
9020 sizeof(struct drm_crtc *), GFP_KERNEL);
9021 if (!config->save_encoder_crtcs)
85f9eb71
DV
9022 return -ENOMEM;
9023
1aa4b628
DV
9024 config->save_connector_encoders =
9025 kcalloc(dev->mode_config.num_connector,
9026 sizeof(struct drm_encoder *), GFP_KERNEL);
9027 if (!config->save_connector_encoders)
85f9eb71
DV
9028 return -ENOMEM;
9029
9030 /* Copy data. Note that driver private data is not affected.
9031 * Should anything bad happen only the expected state is
9032 * restored, not the drivers personal bookkeeping.
9033 */
85f9eb71
DV
9034 count = 0;
9035 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9036 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV
9037 }
9038
9039 count = 0;
9040 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9041 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV
9042 }
9043
9044 return 0;
9045}
9046
9047static void intel_set_config_restore_state(struct drm_device *dev,
9048 struct intel_set_config *config)
9049{
9a935856
DV
9050 struct intel_encoder *encoder;
9051 struct intel_connector *connector;
85f9eb71
DV
9052 int count;
9053
85f9eb71 9054 count = 0;
9a935856
DV
9055 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9056 encoder->new_crtc =
9057 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV
9058 }
9059
9060 count = 0;
9a935856
DV
9061 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9062 connector->new_encoder =
9063 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV
9064 }
9065}
9066
e3de42b6 9067static bool
2e57f47d 9068is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID
9069{
9070 int i;
9071
2e57f47d
CW
9072 if (set->num_connectors == 0)
9073 return false;
9074
9075 if (WARN_ON(set->connectors == NULL))
9076 return false;
9077
9078 for (i = 0; i < set->num_connectors; i++)
9079 if (set->connectors[i]->encoder &&
9080 set->connectors[i]->encoder->crtc == set->crtc &&
9081 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID
9082 return true;
9083
9084 return false;
9085}
9086
5e2b584e
DV
9087static void
9088intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9089 struct intel_set_config *config)
9090{
9091
9092 /* We should be able to check here if the fb has the same properties
9093 * and then just flip_or_move it */
2e57f47d
CW
9094 if (is_crtc_connector_off(set)) {
9095 config->mode_changed = true;
e3de42b6 9096 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV
9097 /* If we have no fb then treat it as a full mode set */
9098 if (set->crtc->fb == NULL) {
319d9827
JB
9099 struct intel_crtc *intel_crtc =
9100 to_intel_crtc(set->crtc);
9101
9102 if (intel_crtc->active && i915_fastboot) {
9103 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9104 config->fb_changed = true;
9105 } else {
9106 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9107 config->mode_changed = true;
9108 }
5e2b584e
DV
9109 } else if (set->fb == NULL) {
9110 config->mode_changed = true;
72f4901e
DV
9111 } else if (set->fb->pixel_format !=
9112 set->crtc->fb->pixel_format) {
5e2b584e 9113 config->mode_changed = true;
e3de42b6 9114 } else {
5e2b584e 9115 config->fb_changed = true;
e3de42b6 9116 }
5e2b584e
DV
9117 }
9118
835c5873 9119 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV
9120 config->fb_changed = true;
9121
9122 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9123 DRM_DEBUG_KMS("modes are different, full mode set\n");
9124 drm_mode_debug_printmodeline(&set->crtc->mode);
9125 drm_mode_debug_printmodeline(set->mode);
9126 config->mode_changed = true;
9127 }
a1d95703
CW
9128
9129 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9130 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV
9131}
9132
2e431051 9133static int
9a935856
DV
9134intel_modeset_stage_output_state(struct drm_device *dev,
9135 struct drm_mode_set *set,
9136 struct intel_set_config *config)
50f56119 9137{
85f9eb71 9138 struct drm_crtc *new_crtc;
9a935856
DV
9139 struct intel_connector *connector;
9140 struct intel_encoder *encoder;
f3f08572 9141 int ro;
50f56119 9142
9abdda74 9143 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV
9144 * of connectors. For paranoia, double-check this. */
9145 WARN_ON(!set->fb && (set->num_connectors != 0));
9146 WARN_ON(set->fb && (set->num_connectors == 0));
9147
9a935856
DV
9148 list_for_each_entry(connector, &dev->mode_config.connector_list,
9149 base.head) {
9150 /* Otherwise traverse passed in connector list and get encoders
9151 * for them. */
50f56119 9152 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV
9153 if (set->connectors[ro] == &connector->base) {
9154 connector->new_encoder = connector->encoder;
50f56119
DV
9155 break;
9156 }
9157 }
9158
9a935856
DV
9159 /* If we disable the crtc, disable all its connectors. Also, if
9160 * the connector is on the changing crtc but not on the new
9161 * connector list, disable it. */
9162 if ((!set->fb || ro == set->num_connectors) &&
9163 connector->base.encoder &&
9164 connector->base.encoder->crtc == set->crtc) {
9165 connector->new_encoder = NULL;
9166
9167 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9168 connector->base.base.id,
9169 drm_get_connector_name(&connector->base));
9170 }
9171
9172
9173 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9174 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9175 config->mode_changed = true;
50f56119
DV
9176 }
9177 }
9a935856 9178 /* connector->new_encoder is now updated for all connectors. */
50f56119 9179
9a935856 9180 /* Update crtc of enabled connectors. */
9a935856
DV
9181 list_for_each_entry(connector, &dev->mode_config.connector_list,
9182 base.head) {
9183 if (!connector->new_encoder)
50f56119
DV
9184 continue;
9185
9a935856 9186 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV
9187
9188 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9189 if (set->connectors[ro] == &connector->base)
50f56119
DV
9190 new_crtc = set->crtc;
9191 }
9192
9193 /* Make sure the new CRTC will work with the encoder */
9a935856
DV
9194 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9195 new_crtc)) {
5e2b584e 9196 return -EINVAL;
50f56119 9197 }
9a935856
DV
9198 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9199
9200 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9201 connector->base.base.id,
9202 drm_get_connector_name(&connector->base),
9203 new_crtc->base.id);
9204 }
9205
9206 /* Check for any encoders that needs to be disabled. */
9207 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9208 base.head) {
9209 list_for_each_entry(connector,
9210 &dev->mode_config.connector_list,
9211 base.head) {
9212 if (connector->new_encoder == encoder) {
9213 WARN_ON(!connector->new_encoder->new_crtc);
9214
9215 goto next_encoder;
9216 }
9217 }
9218 encoder->new_crtc = NULL;
9219next_encoder:
9220 /* Only now check for crtc changes so we don't miss encoders
9221 * that will be disabled. */
9222 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9223 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9224 config->mode_changed = true;
50f56119
DV
9225 }
9226 }
9a935856 9227 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9228
2e431051
DV
9229 return 0;
9230}
9231
9232static int intel_crtc_set_config(struct drm_mode_set *set)
9233{
9234 struct drm_device *dev;
2e431051
DV
9235 struct drm_mode_set save_set;
9236 struct intel_set_config *config;
9237 int ret;
2e431051 9238
8d3e375e
DV
9239 BUG_ON(!set);
9240 BUG_ON(!set->crtc);
9241 BUG_ON(!set->crtc->helper_private);
2e431051 9242
7e53f3a4
DV
9243 /* Enforce sane interface api - has been abused by the fb helper. */
9244 BUG_ON(!set->mode && set->fb);
9245 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9246
2e431051
DV
9247 if (set->fb) {
9248 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9249 set->crtc->base.id, set->fb->base.id,
9250 (int)set->num_connectors, set->x, set->y);
9251 } else {
9252 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV
9253 }
9254
9255 dev = set->crtc->dev;
9256
9257 ret = -ENOMEM;
9258 config = kzalloc(sizeof(*config), GFP_KERNEL);
9259 if (!config)
9260 goto out_config;
9261
9262 ret = intel_set_config_save_state(dev, config);
9263 if (ret)
9264 goto out_config;
9265
9266 save_set.crtc = set->crtc;
9267 save_set.mode = &set->crtc->mode;
9268 save_set.x = set->crtc->x;
9269 save_set.y = set->crtc->y;
9270 save_set.fb = set->crtc->fb;
9271
9272 /* Compute whether we need a full modeset, only an fb base update or no
9273 * change at all. In the future we might also check whether only the
9274 * mode changed, e.g. for LVDS where we only change the panel fitter in
9275 * such cases. */
9276 intel_set_config_compute_mode_changes(set, config);
9277
9a935856 9278 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV
9279 if (ret)
9280 goto fail;
9281
5e2b584e 9282 if (config->mode_changed) {
c0c36b94
CW
9283 ret = intel_set_mode(set->crtc, set->mode,
9284 set->x, set->y, set->fb);
5e2b584e 9285 } else if (config->fb_changed) {
4878cae2
VS
9286 intel_crtc_wait_for_pending_flips(set->crtc);
9287
4f660f49 9288 ret = intel_pipe_set_base(set->crtc,
94352cf9 9289 set->x, set->y, set->fb);
50f56119
DV
9290 }
9291
2d05eae1 9292 if (ret) {
bf67dfeb
DV
9293 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9294 set->crtc->base.id, ret);
50f56119 9295fail:
2d05eae1 9296 intel_set_config_restore_state(dev, config);
50f56119 9297
2d05eae1
CW
9298 /* Try to restore the config */
9299 if (config->mode_changed &&
9300 intel_set_mode(save_set.crtc, save_set.mode,
9301 save_set.x, save_set.y, save_set.fb))
9302 DRM_ERROR("failed to restore config after modeset failure\n");
9303 }
50f56119 9304
d9e55608
DV
9305out_config:
9306 intel_set_config_free(config);
50f56119
DV
9307 return ret;
9308}
f6e5b160
CW
9309
9310static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW
9311 .cursor_set = intel_crtc_cursor_set,
9312 .cursor_move = intel_crtc_cursor_move,
9313 .gamma_set = intel_crtc_gamma_set,
50f56119 9314 .set_config = intel_crtc_set_config,
f6e5b160
CW
9315 .destroy = intel_crtc_destroy,
9316 .page_flip = intel_crtc_page_flip,
9317};
9318
79f689aa
PZ
9319static void intel_cpu_pll_init(struct drm_device *dev)
9320{
affa9354 9321 if (HAS_DDI(dev))
79f689aa
PZ
9322 intel_ddi_pll_init(dev);
9323}
9324
5358901f
DV
9325static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9326 struct intel_shared_dpll *pll,
9327 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9328{
5358901f 9329 uint32_t val;
ee7b9f93 9330
5358901f 9331 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV
9332 hw_state->dpll = val;
9333 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9334 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV
9335
9336 return val & DPLL_VCO_ENABLE;
9337}
9338
15bdd4cf
DV
9339static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9340 struct intel_shared_dpll *pll)
9341{
9342 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9343 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9344}
9345
e7b903d2
DV
9346static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9347 struct intel_shared_dpll *pll)
9348{
e7b903d2
DV
9349 /* PCH refclock must be enabled first */
9350 assert_pch_refclk_enabled(dev_priv);
9351
15bdd4cf
DV
9352 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9353
9354 /* Wait for the clocks to stabilize. */
9355 POSTING_READ(PCH_DPLL(pll->id));
9356 udelay(150);
9357
9358 /* The pixel multiplier can only be updated once the
9359 * DPLL is enabled and the clocks are stable.
9360 *
9361 * So write it again.
9362 */
9363 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9364 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV
9365 udelay(200);
9366}
9367
9368static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9369 struct intel_shared_dpll *pll)
9370{
9371 struct drm_device *dev = dev_priv->dev;
9372 struct intel_crtc *crtc;
e7b903d2
DV
9373
9374 /* Make sure no transcoder isn't still depending on us. */
9375 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9376 if (intel_crtc_to_shared_dpll(crtc) == pll)
9377 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB
9378 }
9379
15bdd4cf
DV
9380 I915_WRITE(PCH_DPLL(pll->id), 0);
9381 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV
9382 udelay(200);
9383}
9384
46edb027
DV
9385static char *ibx_pch_dpll_names[] = {
9386 "PCH DPLL A",
9387 "PCH DPLL B",
9388};
9389
7c74ade1 9390static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9391{
e7b903d2 9392 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB
9393 int i;
9394
7c74ade1 9395 dev_priv->num_shared_dpll = 2;
ee7b9f93 9396
e72f9fbf 9397 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV
9398 dev_priv->shared_dplls[i].id = i;
9399 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9400 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV
9401 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9402 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV
9403 dev_priv->shared_dplls[i].get_hw_state =
9404 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB
9405 }
9406}
9407
7c74ade1
DV
9408static void intel_shared_dpll_init(struct drm_device *dev)
9409{
e7b903d2 9410 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV
9411
9412 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9413 ibx_pch_dpll_init(dev);
9414 else
9415 dev_priv->num_shared_dpll = 0;
9416
9417 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9418 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9419 dev_priv->num_shared_dpll);
9420}
9421
b358d0a6 9422static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9423{
22fd0fab 9424 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB
9425 struct intel_crtc *intel_crtc;
9426 int i;
9427
9428 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9429 if (intel_crtc == NULL)
9430 return;
9431
9432 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9433
9434 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB
9435 for (i = 0; i < 256; i++) {
9436 intel_crtc->lut_r[i] = i;
9437 intel_crtc->lut_g[i] = i;
9438 intel_crtc->lut_b[i] = i;
9439 }
9440
80824003
JB
9441 /* Swap pipes & planes for FBC on pre-965 */
9442 intel_crtc->pipe = pipe;
9443 intel_crtc->plane = pipe;
e2e767ab 9444 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9445 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9446 intel_crtc->plane = !pipe;
80824003
JB
9447 }
9448
22fd0fab
JB
9449 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9450 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9451 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9452 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9453
79e53945 9454 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB
9455}
9456
08d7b3d1 9457int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9458 struct drm_file *file)
08d7b3d1 9459{
08d7b3d1 9460 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV
9461 struct drm_mode_object *drmmode_obj;
9462 struct intel_crtc *crtc;
08d7b3d1 9463
1cff8f6b
DV
9464 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9465 return -ENODEV;
08d7b3d1 9466
c05422d5
DV
9467 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9468 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9469
c05422d5 9470 if (!drmmode_obj) {
08d7b3d1
CW
9471 DRM_ERROR("no such CRTC id\n");
9472 return -EINVAL;
9473 }
9474
c05422d5
DV
9475 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9476 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9477
c05422d5 9478 return 0;
08d7b3d1
CW
9479}
9480
66a9278e 9481static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9482{
66a9278e
DV
9483 struct drm_device *dev = encoder->base.dev;
9484 struct intel_encoder *source_encoder;
79e53945 9485 int index_mask = 0;
79e53945
JB
9486 int entry = 0;
9487
66a9278e
DV
9488 list_for_each_entry(source_encoder,
9489 &dev->mode_config.encoder_list, base.head) {
9490
9491 if (encoder == source_encoder)
79e53945 9492 index_mask |= (1 << entry);
66a9278e
DV
9493
9494 /* Intel hw has only one MUX where enocoders could be cloned. */
9495 if (encoder->cloneable && source_encoder->cloneable)
9496 index_mask |= (1 << entry);
9497
79e53945
JB
9498 entry++;
9499 }
4ef69c7a 9500
79e53945
JB
9501 return index_mask;
9502}
9503
4d302442
CW
9504static bool has_edp_a(struct drm_device *dev)
9505{
9506 struct drm_i915_private *dev_priv = dev->dev_private;
9507
9508 if (!IS_MOBILE(dev))
9509 return false;
9510
9511 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9512 return false;
9513
9514 if (IS_GEN5(dev) &&
9515 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9516 return false;
9517
9518 return true;
9519}
9520
79e53945
JB
9521static void intel_setup_outputs(struct drm_device *dev)
9522{
725e30ad 9523 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9524 struct intel_encoder *encoder;
cb0953d7 9525 bool dpd_is_edp = false;
79e53945 9526
c9093354 9527 intel_lvds_init(dev);
79e53945 9528
c40c0f5b 9529 if (!IS_ULT(dev))
79935fca 9530 intel_crt_init(dev);
cb0953d7 9531
affa9354 9532 if (HAS_DDI(dev)) {
0e72a5b5
ED
9533 int found;
9534
9535 /* Haswell uses DDI functions to detect digital outputs */
9536 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9537 /* DDI A only supports eDP */
9538 if (found)
9539 intel_ddi_init(dev, PORT_A);
9540
9541 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9542 * register */
9543 found = I915_READ(SFUSE_STRAP);
9544
9545 if (found & SFUSE_STRAP_DDIB_DETECTED)
9546 intel_ddi_init(dev, PORT_B);
9547 if (found & SFUSE_STRAP_DDIC_DETECTED)
9548 intel_ddi_init(dev, PORT_C);
9549 if (found & SFUSE_STRAP_DDID_DETECTED)
9550 intel_ddi_init(dev, PORT_D);
9551 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9552 int found;
270b3042
DV
9553 dpd_is_edp = intel_dpd_is_edp(dev);
9554
9555 if (has_edp_a(dev))
9556 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9557
dc0fa718 9558 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9559 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9560 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9561 if (!found)
e2debe91 9562 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9563 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9564 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW
9565 }
9566
dc0fa718 9567 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9568 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9569
dc0fa718 9570 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9571 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9572
5eb08b69 9573 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9574 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9575
270b3042 9576 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9577 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9578 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9579 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB
9580 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9581 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9582 PORT_C);
9583 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9584 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9585 PORT_C);
9586 }
19c03924 9587
dc0fa718 9588 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ
9589 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9590 PORT_B);
67cfc203
VS
9591 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9592 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9593 }
3cfca973
JN
9594
9595 intel_dsi_init(dev);
103a196f 9596 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9597 bool found = false;
7d57382e 9598
e2debe91 9599 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9600 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9601 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB
9602 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9603 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9604 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9605 }
27185ae1 9606
e7281eab 9607 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9608 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9609 }
13520b05
KH
9610
9611 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9612
e2debe91 9613 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9614 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9615 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9616 }
27185ae1 9617
e2debe91 9618 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9619
b01f2c3a
JB
9620 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9621 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9622 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9623 }
e7281eab 9624 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9625 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9626 }
27185ae1 9627
b01f2c3a 9628 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9629 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9630 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9631 } else if (IS_GEN2(dev))
79e53945
JB
9632 intel_dvo_init(dev);
9633
103a196f 9634 if (SUPPORTS_TV(dev))
79e53945
JB
9635 intel_tv_init(dev);
9636
4ef69c7a
CW
9637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9638 encoder->base.possible_crtcs = encoder->crtc_mask;
9639 encoder->base.possible_clones =
66a9278e 9640 intel_encoder_clones(encoder);
79e53945 9641 }
47356eb6 9642
dde86e2d 9643 intel_init_pch_refclk(dev);
270b3042
DV
9644
9645 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB
9646}
9647
ddfe1567
CW
9648void intel_framebuffer_fini(struct intel_framebuffer *fb)
9649{
9650 drm_framebuffer_cleanup(&fb->base);
9651 drm_gem_object_unreference_unlocked(&fb->obj->base);
9652}
9653
79e53945
JB
9654static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9655{
9656 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9657
ddfe1567 9658 intel_framebuffer_fini(intel_fb);
79e53945
JB
9659 kfree(intel_fb);
9660}
9661
9662static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9663 struct drm_file *file,
79e53945
JB
9664 unsigned int *handle)
9665{
9666 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9667 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9668
05394f39 9669 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB
9670}
9671
9672static const struct drm_framebuffer_funcs intel_fb_funcs = {
9673 .destroy = intel_user_framebuffer_destroy,
9674 .create_handle = intel_user_framebuffer_create_handle,
9675};
9676
38651674
DA
9677int intel_framebuffer_init(struct drm_device *dev,
9678 struct intel_framebuffer *intel_fb,
308e5bcb 9679 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9680 struct drm_i915_gem_object *obj)
79e53945 9681{
a35cdaa0 9682 int pitch_limit;
79e53945
JB
9683 int ret;
9684
c16ed4be
CW
9685 if (obj->tiling_mode == I915_TILING_Y) {
9686 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9687 return -EINVAL;
c16ed4be 9688 }
57cd6508 9689
c16ed4be
CW
9690 if (mode_cmd->pitches[0] & 63) {
9691 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9692 mode_cmd->pitches[0]);
57cd6508 9693 return -EINVAL;
c16ed4be 9694 }
57cd6508 9695
a35cdaa0
CW
9696 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9697 pitch_limit = 32*1024;
9698 } else if (INTEL_INFO(dev)->gen >= 4) {
9699 if (obj->tiling_mode)
9700 pitch_limit = 16*1024;
9701 else
9702 pitch_limit = 32*1024;
9703 } else if (INTEL_INFO(dev)->gen >= 3) {
9704 if (obj->tiling_mode)
9705 pitch_limit = 8*1024;
9706 else
9707 pitch_limit = 16*1024;
9708 } else
9709 /* XXX DSPC is limited to 4k tiled */
9710 pitch_limit = 8*1024;
9711
9712 if (mode_cmd->pitches[0] > pitch_limit) {
9713 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9714 obj->tiling_mode ? "tiled" : "linear",
9715 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9716 return -EINVAL;
c16ed4be 9717 }
5d7bd705
VS
9718
9719 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW
9720 mode_cmd->pitches[0] != obj->stride) {
9721 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9722 mode_cmd->pitches[0], obj->stride);
5d7bd705 9723 return -EINVAL;
c16ed4be 9724 }
5d7bd705 9725
57779d06 9726 /* Reject formats not supported by any plane early. */
308e5bcb 9727 switch (mode_cmd->pixel_format) {
57779d06 9728 case DRM_FORMAT_C8:
04b3924d
VS
9729 case DRM_FORMAT_RGB565:
9730 case DRM_FORMAT_XRGB8888:
9731 case DRM_FORMAT_ARGB8888:
57779d06
VS
9732 break;
9733 case DRM_FORMAT_XRGB1555:
9734 case DRM_FORMAT_ARGB1555:
c16ed4be 9735 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS
9736 DRM_DEBUG("unsupported pixel format: %s\n",
9737 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9738 return -EINVAL;
c16ed4be 9739 }
57779d06
VS
9740 break;
9741 case DRM_FORMAT_XBGR8888:
9742 case DRM_FORMAT_ABGR8888:
04b3924d
VS
9743 case DRM_FORMAT_XRGB2101010:
9744 case DRM_FORMAT_ARGB2101010:
57779d06
VS
9745 case DRM_FORMAT_XBGR2101010:
9746 case DRM_FORMAT_ABGR2101010:
c16ed4be 9747 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS
9748 DRM_DEBUG("unsupported pixel format: %s\n",
9749 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9750 return -EINVAL;
c16ed4be 9751 }
b5626747 9752 break;
04b3924d
VS
9753 case DRM_FORMAT_YUYV:
9754 case DRM_FORMAT_UYVY:
9755 case DRM_FORMAT_YVYU:
9756 case DRM_FORMAT_VYUY:
c16ed4be 9757 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS
9758 DRM_DEBUG("unsupported pixel format: %s\n",
9759 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9760 return -EINVAL;
c16ed4be 9761 }
57cd6508
CW
9762 break;
9763 default:
4ee62c76
VS
9764 DRM_DEBUG("unsupported pixel format: %s\n",
9765 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW
9766 return -EINVAL;
9767 }
9768
90f9a336
VS
9769 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9770 if (mode_cmd->offsets[0] != 0)
9771 return -EINVAL;
9772
c7d73f6a
DV
9773 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9774 intel_fb->obj = obj;
9775
79e53945
JB
9776 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9777 if (ret) {
9778 DRM_ERROR("framebuffer init failed %d\n", ret);
9779 return ret;
9780 }
9781
79e53945
JB
9782 return 0;
9783}
9784
79e53945
JB
9785static struct drm_framebuffer *
9786intel_user_framebuffer_create(struct drm_device *dev,
9787 struct drm_file *filp,
308e5bcb 9788 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9789{
05394f39 9790 struct drm_i915_gem_object *obj;
79e53945 9791
308e5bcb
JB
9792 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9793 mode_cmd->handles[0]));
c8725226 9794 if (&obj->base == NULL)
cce13ff7 9795 return ERR_PTR(-ENOENT);
79e53945 9796
d2dff872 9797 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB
9798}
9799
79e53945 9800static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9801 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9802 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB
9803};
9804
e70236a8
JB
9805/* Set up chip specific display functions */
9806static void intel_init_display(struct drm_device *dev)
9807{
9808 struct drm_i915_private *dev_priv = dev->dev_private;
9809
ee9300bb
DV
9810 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9811 dev_priv->display.find_dpll = g4x_find_best_dpll;
9812 else if (IS_VALLEYVIEW(dev))
9813 dev_priv->display.find_dpll = vlv_find_best_dpll;
9814 else if (IS_PINEVIEW(dev))
9815 dev_priv->display.find_dpll = pnv_find_best_dpll;
9816 else
9817 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9818
affa9354 9819 if (HAS_DDI(dev)) {
0e8ffe1b 9820 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9821 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ
9822 dev_priv->display.crtc_enable = haswell_crtc_enable;
9823 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9824 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ
9825 dev_priv->display.update_plane = ironlake_update_plane;
9826 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9827 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9828 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9829 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV
9830 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9831 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9832 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9833 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB
9834 } else if (IS_VALLEYVIEW(dev)) {
9835 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9836 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB
9837 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9838 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9839 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9840 dev_priv->display.off = i9xx_crtc_off;
9841 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9842 } else {
0e8ffe1b 9843 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9844 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9845 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV
9846 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9847 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9848 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9849 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9850 }
e70236a8 9851
e70236a8 9852 /* Returns the core display clock speed */
25eb05fc
JB
9853 if (IS_VALLEYVIEW(dev))
9854 dev_priv->display.get_display_clock_speed =
9855 valleyview_get_display_clock_speed;
9856 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB
9857 dev_priv->display.get_display_clock_speed =
9858 i945_get_display_clock_speed;
9859 else if (IS_I915G(dev))
9860 dev_priv->display.get_display_clock_speed =
9861 i915_get_display_clock_speed;
257a7ffc 9862 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB
9863 dev_priv->display.get_display_clock_speed =
9864 i9xx_misc_get_display_clock_speed;
257a7ffc
DV
9865 else if (IS_PINEVIEW(dev))
9866 dev_priv->display.get_display_clock_speed =
9867 pnv_get_display_clock_speed;
e70236a8
JB
9868 else if (IS_I915GM(dev))
9869 dev_priv->display.get_display_clock_speed =
9870 i915gm_get_display_clock_speed;
9871 else if (IS_I865G(dev))
9872 dev_priv->display.get_display_clock_speed =
9873 i865_get_display_clock_speed;
f0f8a9ce 9874 else if (IS_I85X(dev))
e70236a8
JB
9875 dev_priv->display.get_display_clock_speed =
9876 i855_get_display_clock_speed;
9877 else /* 852, 830 */
9878 dev_priv->display.get_display_clock_speed =
9879 i830_get_display_clock_speed;
9880
7f8a8569 9881 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9882 if (IS_GEN5(dev)) {
674cf967 9883 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9884 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9885 } else if (IS_GEN6(dev)) {
674cf967 9886 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9887 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB
9888 } else if (IS_IVYBRIDGE(dev)) {
9889 /* FIXME: detect B0+ stepping and use auto training */
9890 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9891 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV
9892 dev_priv->display.modeset_global_resources =
9893 ivb_modeset_global_resources;
c82e4d26
ED
9894 } else if (IS_HASWELL(dev)) {
9895 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9896 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV
9897 dev_priv->display.modeset_global_resources =
9898 haswell_modeset_global_resources;
a0e63c22 9899 }
6067aaea 9900 } else if (IS_G4X(dev)) {
e0dac65e 9901 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9902 }
8c9f3aaf
JB
9903
9904 /* Default just returns -ENODEV to indicate unsupported */
9905 dev_priv->display.queue_flip = intel_default_queue_flip;
9906
9907 switch (INTEL_INFO(dev)->gen) {
9908 case 2:
9909 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9910 break;
9911
9912 case 3:
9913 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9914 break;
9915
9916 case 4:
9917 case 5:
9918 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9919 break;
9920
9921 case 6:
9922 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9923 break;
7c9017e5
JB
9924 case 7:
9925 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9926 break;
8c9f3aaf 9927 }
e70236a8
JB
9928}
9929
b690e96c
JB
9930/*
9931 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9932 * resume, or other times. This quirk makes sure that's the case for
9933 * affected systems.
9934 */
0206e353 9935static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB
9936{
9937 struct drm_i915_private *dev_priv = dev->dev_private;
9938
9939 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9940 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB
9941}
9942
435793df
KP
9943/*
9944 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9945 */
9946static void quirk_ssc_force_disable(struct drm_device *dev)
9947{
9948 struct drm_i915_private *dev_priv = dev->dev_private;
9949 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9950 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP
9951}
9952
4dca20ef 9953/*
5a15ab5b
CE
9954 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9955 * brightness value
4dca20ef
CE
9956 */
9957static void quirk_invert_brightness(struct drm_device *dev)
9958{
9959 struct drm_i915_private *dev_priv = dev->dev_private;
9960 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9961 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP
9962}
9963
e85843be
KM
9964/*
9965 * Some machines (Dell XPS13) suffer broken backlight controls if
9966 * BLM_PCH_PWM_ENABLE is set.
9967 */
9968static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9969{
9970 struct drm_i915_private *dev_priv = dev->dev_private;
9971 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9972 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9973}
9974
b690e96c
JB
9975struct intel_quirk {
9976 int device;
9977 int subsystem_vendor;
9978 int subsystem_device;
9979 void (*hook)(struct drm_device *dev);
9980};
9981
5f85f176
EE
9982/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9983struct intel_dmi_quirk {
9984 void (*hook)(struct drm_device *dev);
9985 const struct dmi_system_id (*dmi_id_list)[];
9986};
9987
9988static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9989{
9990 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9991 return 1;
9992}
9993
9994static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9995 {
9996 .dmi_id_list = &(const struct dmi_system_id[]) {
9997 {
9998 .callback = intel_dmi_reverse_brightness,
9999 .ident = "NCR Corporation",
10000 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10001 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10002 },
10003 },
10004 { } /* terminating entry */
10005 },
10006 .hook = quirk_invert_brightness,
10007 },
10008};
10009
c43b5634 10010static struct intel_quirk intel_quirks[] = {
b690e96c 10011 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10012 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10013
b690e96c
JB
10014 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10015 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10016
b690e96c
JB
10017 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10018 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10019
ccd0d36e 10020 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10021 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10022 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP
10023
10024 /* Lenovo U160 cannot use SSC on LVDS */
10025 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS
10026
10027 /* Sony Vaio Y cannot use SSC on LVDS */
10028 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE
10029
10030 /* Acer Aspire 5734Z must invert backlight brightness */
10031 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN
10032
10033 /* Acer/eMachines G725 */
10034 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN
10035
10036 /* Acer/eMachines e725 */
10037 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN
10038
10039 /* Acer/Packard Bell NCL20 */
10040 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV
10041
10042 /* Acer Aspire 4736Z */
10043 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM
10044
10045 /* Dell XPS13 HD Sandy Bridge */
10046 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10047 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10048 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB
10049};
10050
10051static void intel_init_quirks(struct drm_device *dev)
10052{
10053 struct pci_dev *d = dev->pdev;
10054 int i;
10055
10056 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10057 struct intel_quirk *q = &intel_quirks[i];
10058
10059 if (d->device == q->device &&
10060 (d->subsystem_vendor == q->subsystem_vendor ||
10061 q->subsystem_vendor == PCI_ANY_ID) &&
10062 (d->subsystem_device == q->subsystem_device ||
10063 q->subsystem_device == PCI_ANY_ID))
10064 q->hook(dev);
10065 }
5f85f176
EE
10066 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10067 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10068 intel_dmi_quirks[i].hook(dev);
10069 }
b690e96c
JB
10070}
10071
9cce37f4
JB
10072/* Disable the VGA plane that we never use */
10073static void i915_disable_vga(struct drm_device *dev)
10074{
10075 struct drm_i915_private *dev_priv = dev->dev_private;
10076 u8 sr1;
766aa1c4 10077 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB
10078
10079 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10080 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB
10081 sr1 = inb(VGA_SR_DATA);
10082 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW
10083
10084 /* Disable VGA memory on Intel HD */
10085 if (HAS_PCH_SPLIT(dev)) {
10086 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10087 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10088 VGA_RSRC_NORMAL_IO |
10089 VGA_RSRC_NORMAL_MEM);
10090 }
10091
9cce37f4
JB
10092 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10093 udelay(300);
10094
10095 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10096 POSTING_READ(vga_reg);
10097}
10098
81b5c7bc
AW
10099static void i915_enable_vga(struct drm_device *dev)
10100{
10101 /* Enable VGA memory on Intel HD */
10102 if (HAS_PCH_SPLIT(dev)) {
10103 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10104 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10105 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10106 VGA_RSRC_LEGACY_MEM |
10107 VGA_RSRC_NORMAL_IO |
10108 VGA_RSRC_NORMAL_MEM);
10109 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10110 }
10111}
10112
f817586c
DV
10113void intel_modeset_init_hw(struct drm_device *dev)
10114{
fa42e23c 10115 intel_init_power_well(dev);
0232e927 10116
a8f78b58
ED
10117 intel_prepare_ddi(dev);
10118
f817586c
DV
10119 intel_init_clock_gating(dev);
10120
79f5b2c7 10121 mutex_lock(&dev->struct_mutex);
8090c6b9 10122 intel_enable_gt_powersave(dev);
79f5b2c7 10123 mutex_unlock(&dev->struct_mutex);
f817586c
DV
10124}
10125
7d708ee4
ID
10126void intel_modeset_suspend_hw(struct drm_device *dev)
10127{
10128 intel_suspend_hw(dev);
10129}
10130
79e53945
JB
10131void intel_modeset_init(struct drm_device *dev)
10132{
652c393a 10133 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10134 int i, j, ret;
79e53945
JB
10135
10136 drm_mode_config_init(dev);
10137
10138 dev->mode_config.min_width = 0;
10139 dev->mode_config.min_height = 0;
10140
019d96cb
DA
10141 dev->mode_config.preferred_depth = 24;
10142 dev->mode_config.prefer_shadow = 1;
10143
e6ecefaa 10144 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10145
b690e96c
JB
10146 intel_init_quirks(dev);
10147
1fa61106
ED
10148 intel_init_pm(dev);
10149
e3c74757
BW
10150 if (INTEL_INFO(dev)->num_pipes == 0)
10151 return;
10152
e70236a8
JB
10153 intel_init_display(dev);
10154
a6c45cf0
CW
10155 if (IS_GEN2(dev)) {
10156 dev->mode_config.max_width = 2048;
10157 dev->mode_config.max_height = 2048;
10158 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP
10159 dev->mode_config.max_width = 4096;
10160 dev->mode_config.max_height = 4096;
79e53945 10161 } else {
a6c45cf0
CW
10162 dev->mode_config.max_width = 8192;
10163 dev->mode_config.max_height = 8192;
79e53945 10164 }
5d4545ae 10165 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10166
28c97730 10167 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW
10168 INTEL_INFO(dev)->num_pipes,
10169 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10170
08e2a7de 10171 for_each_pipe(i) {
79e53945 10172 intel_crtc_init(dev, i);
7f1f3851
JB
10173 for (j = 0; j < dev_priv->num_plane; j++) {
10174 ret = intel_plane_init(dev, i, j);
10175 if (ret)
06da8da2
VS
10176 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10177 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10178 }
79e53945
JB
10179 }
10180
79f689aa 10181 intel_cpu_pll_init(dev);
e72f9fbf 10182 intel_shared_dpll_init(dev);
ee7b9f93 10183
9cce37f4
JB
10184 /* Just disable it once at startup */
10185 i915_disable_vga(dev);
79e53945 10186 intel_setup_outputs(dev);
11be49eb
CW
10187
10188 /* Just in case the BIOS is doing something questionable. */
10189 intel_disable_fbc(dev);
2c7111db
CW
10190}
10191
24929352
DV
10192static void
10193intel_connector_break_all_links(struct intel_connector *connector)
10194{
10195 connector->base.dpms = DRM_MODE_DPMS_OFF;
10196 connector->base.encoder = NULL;
10197 connector->encoder->connectors_active = false;
10198 connector->encoder->base.crtc = NULL;
10199}
10200
7fad798e
DV
10201static void intel_enable_pipe_a(struct drm_device *dev)
10202{
10203 struct intel_connector *connector;
10204 struct drm_connector *crt = NULL;
10205 struct intel_load_detect_pipe load_detect_temp;
10206
10207 /* We can't just switch on the pipe A, we need to set things up with a
10208 * proper mode and output configuration. As a gross hack, enable pipe A
10209 * by enabling the load detect pipe once. */
10210 list_for_each_entry(connector,
10211 &dev->mode_config.connector_list,
10212 base.head) {
10213 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10214 crt = &connector->base;
10215 break;
10216 }
10217 }
10218
10219 if (!crt)
10220 return;
10221
10222 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10223 intel_release_load_detect_pipe(crt, &load_detect_temp);
10224
652c393a 10225
7fad798e
DV
10226}
10227
fa555837
DV
10228static bool
10229intel_check_plane_mapping(struct intel_crtc *crtc)
10230{
7eb552ae
BW
10231 struct drm_device *dev = crtc->base.dev;
10232 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV
10233 u32 reg, val;
10234
7eb552ae 10235 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV
10236 return true;
10237
10238 reg = DSPCNTR(!crtc->plane);
10239 val = I915_READ(reg);
10240
10241 if ((val & DISPLAY_PLANE_ENABLE) &&
10242 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10243 return false;
10244
10245 return true;
10246}
10247
24929352
DV
10248static void intel_sanitize_crtc(struct intel_crtc *crtc)
10249{
10250 struct drm_device *dev = crtc->base.dev;
10251 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10252 u32 reg;
24929352 10253
24929352 10254 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10255 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV
10256 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10257
10258 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV
10259 * disable the crtc (and hence change the state) if it is wrong. Note
10260 * that gen4+ has a fixed plane -> pipe mapping. */
10261 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV
10262 struct intel_connector *connector;
10263 bool plane;
10264
24929352
DV
10265 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10266 crtc->base.base.id);
10267
10268 /* Pipe has the wrong plane attached and the plane is active.
10269 * Temporarily change the plane mapping and disable everything
10270 * ... */
10271 plane = crtc->plane;
10272 crtc->plane = !plane;
10273 dev_priv->display.crtc_disable(&crtc->base);
10274 crtc->plane = plane;
10275
10276 /* ... and break all links. */
10277 list_for_each_entry(connector, &dev->mode_config.connector_list,
10278 base.head) {
10279 if (connector->encoder->base.crtc != &crtc->base)
10280 continue;
10281
10282 intel_connector_break_all_links(connector);
10283 }
10284
10285 WARN_ON(crtc->active);
10286 crtc->base.enabled = false;
10287 }
24929352 10288
7fad798e
DV
10289 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10290 crtc->pipe == PIPE_A && !crtc->active) {
10291 /* BIOS forgot to enable pipe A, this mostly happens after
10292 * resume. Force-enable the pipe to fix this, the update_dpms
10293 * call below we restore the pipe to the right state, but leave
10294 * the required bits on. */
10295 intel_enable_pipe_a(dev);
10296 }
10297
24929352
DV
10298 /* Adjust the state of the output pipe according to whether we
10299 * have active connectors/encoders. */
10300 intel_crtc_update_dpms(&crtc->base);
10301
10302 if (crtc->active != crtc->base.enabled) {
10303 struct intel_encoder *encoder;
10304
10305 /* This can happen either due to bugs in the get_hw_state
10306 * functions or because the pipe is force-enabled due to the
10307 * pipe A quirk. */
10308 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10309 crtc->base.base.id,
10310 crtc->base.enabled ? "enabled" : "disabled",
10311 crtc->active ? "enabled" : "disabled");
10312
10313 crtc->base.enabled = crtc->active;
10314
10315 /* Because we only establish the connector -> encoder ->
10316 * crtc links if something is active, this means the
10317 * crtc is now deactivated. Break the links. connector
10318 * -> encoder links are only establish when things are
10319 * actually up, hence no need to break them. */
10320 WARN_ON(crtc->active);
10321
10322 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10323 WARN_ON(encoder->connectors_active);
10324 encoder->base.crtc = NULL;
10325 }
10326 }
10327}
10328
10329static void intel_sanitize_encoder(struct intel_encoder *encoder)
10330{
10331 struct intel_connector *connector;
10332 struct drm_device *dev = encoder->base.dev;
10333
10334 /* We need to check both for a crtc link (meaning that the
10335 * encoder is active and trying to read from a pipe) and the
10336 * pipe itself being active. */
10337 bool has_active_crtc = encoder->base.crtc &&
10338 to_intel_crtc(encoder->base.crtc)->active;
10339
10340 if (encoder->connectors_active && !has_active_crtc) {
10341 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10342 encoder->base.base.id,
10343 drm_get_encoder_name(&encoder->base));
10344
10345 /* Connector is active, but has no active pipe. This is
10346 * fallout from our resume register restoring. Disable
10347 * the encoder manually again. */
10348 if (encoder->base.crtc) {
10349 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10350 encoder->base.base.id,
10351 drm_get_encoder_name(&encoder->base));
10352 encoder->disable(encoder);
10353 }
10354
10355 /* Inconsistent output/port/pipe state happens presumably due to
10356 * a bug in one of the get_hw_state functions. Or someplace else
10357 * in our code, like the register restore mess on resume. Clamp
10358 * things to off as a safer default. */
10359 list_for_each_entry(connector,
10360 &dev->mode_config.connector_list,
10361 base.head) {
10362 if (connector->encoder != encoder)
10363 continue;
10364
10365 intel_connector_break_all_links(connector);
10366 }
10367 }
10368 /* Enabled encoders without active connectors will be fixed in
10369 * the crtc fixup. */
10370}
10371
44cec740 10372void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM
10373{
10374 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10375 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10376
8dc8a27c
PZ
10377 /* This function can be called both from intel_modeset_setup_hw_state or
10378 * at a very early point in our resume sequence, where the power well
10379 * structures are not yet restored. Since this function is at a very
10380 * paranoid "someone might have enabled VGA while we were not looking"
10381 * level, just check if the power well is enabled instead of trying to
10382 * follow the "don't touch the power well if we don't need it" policy
10383 * the rest of the driver uses. */
10384 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10385 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ
10386 return;
10387
0fde901f
KM
10388 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10389 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10390 i915_disable_vga(dev);
0fde901f
KM
10391 }
10392}
10393
30e984df 10394static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV
10395{
10396 struct drm_i915_private *dev_priv = dev->dev_private;
10397 enum pipe pipe;
24929352
DV
10398 struct intel_crtc *crtc;
10399 struct intel_encoder *encoder;
10400 struct intel_connector *connector;
5358901f 10401 int i;
24929352 10402
0e8ffe1b
DV
10403 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10404 base.head) {
88adfff1 10405 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10406
0e8ffe1b
DV
10407 crtc->active = dev_priv->display.get_pipe_config(crtc,
10408 &crtc->config);
24929352
DV
10409
10410 crtc->base.enabled = crtc->active;
10411
10412 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10413 crtc->base.base.id,
10414 crtc->active ? "enabled" : "disabled");
10415 }
10416
5358901f 10417 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10418 if (HAS_DDI(dev))
6441ab5f
PZ
10419 intel_ddi_setup_hw_pll_state(dev);
10420
5358901f
DV
10421 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10422 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10423
10424 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10425 pll->active = 0;
10426 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10427 base.head) {
10428 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10429 pll->active++;
10430 }
10431 pll->refcount = pll->active;
10432
35c95375
DV
10433 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10434 pll->name, pll->refcount, pll->on);
5358901f
DV
10435 }
10436
24929352
DV
10437 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10438 base.head) {
10439 pipe = 0;
10440
10441 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB
10442 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10443 encoder->base.crtc = &crtc->base;
510d5f2f 10444 if (encoder->get_config)
045ac3b5 10445 encoder->get_config(encoder, &crtc->config);
24929352
DV
10446 } else {
10447 encoder->base.crtc = NULL;
10448 }
10449
10450 encoder->connectors_active = false;
10451 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10452 encoder->base.base.id,
10453 drm_get_encoder_name(&encoder->base),
10454 encoder->base.crtc ? "enabled" : "disabled",
10455 pipe);
10456 }
10457
510d5f2f
JB
10458 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10459 base.head) {
10460 if (!crtc->active)
10461 continue;
10462 if (dev_priv->display.get_clock)
10463 dev_priv->display.get_clock(crtc,
10464 &crtc->config);
10465 }
10466
24929352
DV
10467 list_for_each_entry(connector, &dev->mode_config.connector_list,
10468 base.head) {
10469 if (connector->get_hw_state(connector)) {
10470 connector->base.dpms = DRM_MODE_DPMS_ON;
10471 connector->encoder->connectors_active = true;
10472 connector->base.encoder = &connector->encoder->base;
10473 } else {
10474 connector->base.dpms = DRM_MODE_DPMS_OFF;
10475 connector->base.encoder = NULL;
10476 }
10477 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10478 connector->base.base.id,
10479 drm_get_connector_name(&connector->base),
10480 connector->base.encoder ? "enabled" : "disabled");
10481 }
30e984df
DV
10482}
10483
10484/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10485 * and i915 state tracking structures. */
10486void intel_modeset_setup_hw_state(struct drm_device *dev,
10487 bool force_restore)
10488{
10489 struct drm_i915_private *dev_priv = dev->dev_private;
10490 enum pipe pipe;
10491 struct drm_plane *plane;
10492 struct intel_crtc *crtc;
10493 struct intel_encoder *encoder;
35c95375 10494 int i;
30e984df
DV
10495
10496 intel_modeset_readout_hw_state(dev);
24929352 10497
babea61d
JB
10498 /*
10499 * Now that we have the config, copy it to each CRTC struct
10500 * Note that this could go away if we move to using crtc_config
10501 * checking everywhere.
10502 */
10503 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10504 base.head) {
10505 if (crtc->active && i915_fastboot) {
10506 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10507
10508 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10509 crtc->base.base.id);
10510 drm_mode_debug_printmodeline(&crtc->base.mode);
10511 }
10512 }
10513
24929352
DV
10514 /* HW state is read out, now we need to sanitize this mess. */
10515 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10516 base.head) {
10517 intel_sanitize_encoder(encoder);
10518 }
10519
10520 for_each_pipe(pipe) {
10521 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10522 intel_sanitize_crtc(crtc);
c0b03411 10523 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10524 }
9a935856 10525
35c95375
DV
10526 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10527 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10528
10529 if (!pll->on || pll->active)
10530 continue;
10531
10532 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10533
10534 pll->disable(dev_priv, pll);
10535 pll->on = false;
10536 }
10537
45e2b5f6 10538 if (force_restore) {
f30da187
DV
10539 /*
10540 * We need to use raw interfaces for restoring state to avoid
10541 * checking (bogus) intermediate states.
10542 */
45e2b5f6 10543 for_each_pipe(pipe) {
b5644d05
JB
10544 struct drm_crtc *crtc =
10545 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV
10546
10547 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10548 crtc->fb);
45e2b5f6 10549 }
b5644d05
JB
10550 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10551 intel_plane_restore(plane);
0fde901f
KM
10552
10553 i915_redisable_vga(dev);
45e2b5f6
DV
10554 } else {
10555 intel_modeset_update_staged_output_state(dev);
10556 }
8af6cf88
DV
10557
10558 intel_modeset_check_state(dev);
2e938892
DV
10559
10560 drm_mode_config_reset(dev);
2c7111db
CW
10561}
10562
10563void intel_modeset_gem_init(struct drm_device *dev)
10564{
1833b134 10565 intel_modeset_init_hw(dev);
02e792fb
DV
10566
10567 intel_setup_overlay(dev);
24929352 10568
45e2b5f6 10569 intel_modeset_setup_hw_state(dev, false);
79e53945
JB
10570}
10571
10572void intel_modeset_cleanup(struct drm_device *dev)
10573{
652c393a
JB
10574 struct drm_i915_private *dev_priv = dev->dev_private;
10575 struct drm_crtc *crtc;
652c393a 10576
fd0c0642
DV
10577 /*
10578 * Interrupts and polling as the first thing to avoid creating havoc.
10579 * Too much stuff here (turning of rps, connectors, ...) would
10580 * experience fancy races otherwise.
10581 */
10582 drm_irq_uninstall(dev);
10583 cancel_work_sync(&dev_priv->hotplug_work);
10584 /*
10585 * Due to the hpd irq storm handling the hotplug work can re-arm the
10586 * poll handlers. Hence disable polling after hpd handling is shut down.
10587 */
f87ea761 10588 drm_kms_helper_poll_fini(dev);
fd0c0642 10589
652c393a
JB
10590 mutex_lock(&dev->struct_mutex);
10591
723bfd70
JB
10592 intel_unregister_dsm_handler();
10593
652c393a
JB
10594 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10595 /* Skip inactive CRTCs */
10596 if (!crtc->fb)
10597 continue;
10598
3dec0095 10599 intel_increase_pllclock(crtc);
652c393a
JB
10600 }
10601
973d04f9 10602 intel_disable_fbc(dev);
e70236a8 10603
81b5c7bc
AW
10604 i915_enable_vga(dev);
10605
8090c6b9 10606 intel_disable_gt_powersave(dev);
0cdab21f 10607
930ebb46
DV
10608 ironlake_teardown_rc6(dev);
10609
69341a5e
KH
10610 mutex_unlock(&dev->struct_mutex);
10611
1630fe75
CW
10612 /* flush any delayed tasks or pending work */
10613 flush_scheduled_work();
10614
dc652f90
JN
10615 /* destroy backlight, if any, before the connectors */
10616 intel_panel_destroy_backlight(dev);
10617
79e53945 10618 drm_mode_config_cleanup(dev);
4d7bb011
DV
10619
10620 intel_cleanup_overlay(dev);
79e53945
JB
10621}
10622
f1c79df3
ZW
10623/*
10624 * Return which encoder is currently attached for connector.
10625 */
df0e9248 10626struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10627{
df0e9248
CW
10628 return &intel_attached_encoder(connector)->base;
10629}
f1c79df3 10630
df0e9248
CW
10631void intel_connector_attach_encoder(struct intel_connector *connector,
10632 struct intel_encoder *encoder)
10633{
10634 connector->encoder = encoder;
10635 drm_mode_connector_attach_encoder(&connector->base,
10636 &encoder->base);
79e53945 10637}
28d52043
DA
10638
10639/*
10640 * set vga decode state - true == enable VGA decode
10641 */
10642int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10643{
10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645 u16 gmch_ctrl;
10646
10647 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10648 if (state)
10649 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10650 else
10651 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10652 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10653 return 0;
10654}
c4a1d9e4 10655
c4a1d9e4 10656struct intel_display_error_state {
ff57f1b0
PZ
10657
10658 u32 power_well_driver;
10659
63b66e5b
CW
10660 int num_transcoders;
10661
c4a1d9e4
CW
10662 struct intel_cursor_error_state {
10663 u32 control;
10664 u32 position;
10665 u32 base;
10666 u32 size;
52331309 10667 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW
10668
10669 struct intel_pipe_error_state {
c4a1d9e4 10670 u32 source;
52331309 10671 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW
10672
10673 struct intel_plane_error_state {
10674 u32 control;
10675 u32 stride;
10676 u32 size;
10677 u32 pos;
10678 u32 addr;
10679 u32 surface;
10680 u32 tile_offset;
52331309 10681 } plane[I915_MAX_PIPES];
63b66e5b
CW
10682
10683 struct intel_transcoder_error_state {
10684 enum transcoder cpu_transcoder;
10685
10686 u32 conf;
10687
10688 u32 htotal;
10689 u32 hblank;
10690 u32 hsync;
10691 u32 vtotal;
10692 u32 vblank;
10693 u32 vsync;
10694 } transcoder[4];
c4a1d9e4
CW
10695};
10696
10697struct intel_display_error_state *
10698intel_display_capture_error_state(struct drm_device *dev)
10699{
0206e353 10700 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10701 struct intel_display_error_state *error;
63b66e5b
CW
10702 int transcoders[] = {
10703 TRANSCODER_A,
10704 TRANSCODER_B,
10705 TRANSCODER_C,
10706 TRANSCODER_EDP,
10707 };
c4a1d9e4
CW
10708 int i;
10709
63b66e5b
CW
10710 if (INTEL_INFO(dev)->num_pipes == 0)
10711 return NULL;
10712
c4a1d9e4
CW
10713 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10714 if (error == NULL)
10715 return NULL;
10716
ff57f1b0
PZ
10717 if (HAS_POWER_WELL(dev))
10718 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10719
52331309 10720 for_each_pipe(i) {
a18c4c3d
PZ
10721 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10722 error->cursor[i].control = I915_READ(CURCNTR(i));
10723 error->cursor[i].position = I915_READ(CURPOS(i));
10724 error->cursor[i].base = I915_READ(CURBASE(i));
10725 } else {
10726 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10727 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10728 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10729 }
c4a1d9e4
CW
10730
10731 error->plane[i].control = I915_READ(DSPCNTR(i));
10732 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10733 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10734 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ
10735 error->plane[i].pos = I915_READ(DSPPOS(i));
10736 }
ca291363
PZ
10737 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10738 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW
10739 if (INTEL_INFO(dev)->gen >= 4) {
10740 error->plane[i].surface = I915_READ(DSPSURF(i));
10741 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10742 }
10743
c4a1d9e4 10744 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW
10745 }
10746
10747 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10748 if (HAS_DDI(dev_priv->dev))
10749 error->num_transcoders++; /* Account for eDP. */
10750
10751 for (i = 0; i < error->num_transcoders; i++) {
10752 enum transcoder cpu_transcoder = transcoders[i];
10753
10754 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10755
10756 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10757 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10758 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10759 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10760 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10761 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10762 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW
10763 }
10764
12d217c7
PZ
10765 /* In the code above we read the registers without checking if the power
10766 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10767 * prevent the next I915_WRITE from detecting it and printing an error
10768 * message. */
907b28c5 10769 intel_uncore_clear_errors(dev);
12d217c7 10770
c4a1d9e4
CW
10771 return error;
10772}
10773
edc3d884
MK
10774#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10775
c4a1d9e4 10776void
edc3d884 10777intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW
10778 struct drm_device *dev,
10779 struct intel_display_error_state *error)
10780{
10781 int i;
10782
63b66e5b
CW
10783 if (!error)
10784 return;
10785
edc3d884 10786 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10787 if (HAS_POWER_WELL(dev))
edc3d884 10788 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10789 error->power_well_driver);
52331309 10790 for_each_pipe(i) {
edc3d884 10791 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10792 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK
10793
10794 err_printf(m, "Plane [%d]:\n", i);
10795 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10796 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10797 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK
10798 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10799 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10800 }
4b71a570 10801 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10802 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10803 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK
10804 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10805 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW
10806 }
10807
edc3d884
MK
10808 err_printf(m, "Cursor [%d]:\n", i);
10809 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10810 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10811 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10812 }
63b66e5b
CW
10813
10814 for (i = 0; i < error->num_transcoders; i++) {
10815 err_printf(m, " CPU transcoder: %c\n",
10816 transcoder_name(error->transcoder[i].cpu_transcoder));
10817 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10818 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10819 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10820 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10821 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10822 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10823 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10824 }
c4a1d9e4 10825}
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