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drm/i915: hw state readout&check support for cpu_transcoder
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
1b894b59
CW		 384static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
2c07245f 386{
b91ad0ec 387 struct drm_device *dev = crtc->dev;
2c07245f 388 const intel_limit_t *limit;
b91ad0ec
ZW		 389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 391 if (intel_is_dual_link_lvds(dev)) {
1b894b59 392 if (refclk == 100000)
b91ad0ec
ZW		 393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
1b894b59 397 if (refclk == 100000)
b91ad0ec
ZW		 398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
c6bb3538 402 } else
b91ad0ec 403 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 404
405 return limit;
406}
407
044c7c41
ML		 408static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409{
410 struct drm_device *dev = crtc->dev;
044c7c41
ML		 411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 414 if (intel_is_dual_link_lvds(dev))
e4b36699 415 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 416 else
e4b36699 417 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 420 limit = &intel_limits_g4x_hdmi;
044c7c41 421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 422 limit = &intel_limits_g4x_sdvo;
044c7c41 423 } else /* The option is for other outputs */
e4b36699 424 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 425
426 return limit;
427}
428
1b894b59 429static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 430{
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
bad720ff 434 if (HAS_PCH_SPLIT(dev))
1b894b59 435 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 436 else if (IS_G4X(dev)) {
044c7c41 437 limit = intel_g4x_limit(crtc);
f2b115e6 438 } else if (IS_PINEVIEW(dev)) {
2177832f 439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 440 limit = &intel_limits_pineview_lvds;
2177832f 441 else
f2b115e6 442 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 443 } else if (IS_VALLEYVIEW(dev)) {
444 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
445 limit = &intel_limits_vlv_dac;
446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
447 limit = &intel_limits_vlv_hdmi;
448 else
449 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 450 } else if (!IS_GEN2(dev)) {
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
452 limit = &intel_limits_i9xx_lvds;
453 else
454 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 455 } else {
456 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 457 limit = &intel_limits_i8xx_lvds;
79e53945 458 else
e4b36699 459 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 460 }
461 return limit;
462}
463
f2b115e6
AJ		 464/* m1 is reserved as 0 in Pineview, n is a ring counter */
465static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 466{
2177832f
SL		 467 clock->m = clock->m2 + 2;
468 clock->p = clock->p1 * clock->p2;
469 clock->vco = refclk * clock->m / clock->n;
470 clock->dot = clock->vco / clock->p;
471}
472
7429e9d4
DV		 473static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
474{
475 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
476}
477
2177832f
SL		 478static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
479{
f2b115e6
AJ		 480 if (IS_PINEVIEW(dev)) {
481 pineview_clock(refclk, clock);
2177832f
SL		 482 return;
483 }
7429e9d4 484 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 485 clock->p = clock->p1 * clock->p2;
486 clock->vco = refclk * clock->m / (clock->n + 2);
487 clock->dot = clock->vco / clock->p;
488}
489
79e53945
JB		 490/**
491 * Returns whether any output on the specified pipe is of the specified type
492 */
4ef69c7a 493bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 494{
4ef69c7a 495 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 496 struct intel_encoder *encoder;
497
6c2b7c12
DV		 498 for_each_encoder_on_crtc(dev, crtc, encoder)
499 if (encoder->type == type)
4ef69c7a
CW		 500 return true;
501
502 return false;
79e53945
JB		 503}
504
7c04d1d9 505#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 506/**
507 * Returns whether the given set of divisors are valid for a given refclk with
508 * the given connectors.
509 */
510
1b894b59
CW		 511static bool intel_PLL_is_valid(struct drm_device *dev,
512 const intel_limit_t *limit,
513 const intel_clock_t *clock)
79e53945 514{
79e53945 515 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 516 INTELPllInvalid("p1 out of range\n");
79e53945 517 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 518 INTELPllInvalid("p out of range\n");
79e53945 519 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 520 INTELPllInvalid("m2 out of range\n");
79e53945 521 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 522 INTELPllInvalid("m1 out of range\n");
f2b115e6 523 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 524 INTELPllInvalid("m1 <= m2\n");
79e53945 525 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 526 INTELPllInvalid("m out of range\n");
79e53945 527 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 528 INTELPllInvalid("n out of range\n");
79e53945 529 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 530 INTELPllInvalid("vco out of range\n");
79e53945
JB		 531 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
532 * connector, etc., rather than just a single range.
533 */
534 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 535 INTELPllInvalid("dot out of range\n");
79e53945
JB		 536
537 return true;
538}
539
d4906093
ML		 540static bool
541intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 542 int target, int refclk, intel_clock_t *match_clock,
543 intel_clock_t *best_clock)
d4906093 544
79e53945
JB		 545{
546 struct drm_device *dev = crtc->dev;
79e53945 547 intel_clock_t clock;
79e53945
JB		 548 int err = target;
549
a210b028 550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 551 /*
a210b028
DV		 552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
79e53945 555 */
1974cad0 556 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
0206e353 567 memset(best_clock, 0, sizeof(*best_clock));
79e53945 568
42158660
ZY		 569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 573 /* m1 is always 0 in Pineview */
574 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 575 break;
576 for (clock.n = limit->n.min;
577 clock.n <= limit->n.max; clock.n++) {
578 for (clock.p1 = limit->p1.min;
579 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 580 int this_err;
581
2177832f 582 intel_clock(dev, refclk, &clock);
1b894b59
CW		 583 if (!intel_PLL_is_valid(dev, limit,
584 &clock))
79e53945 585 continue;
cec2f356
SP		 586 if (match_clock &&
587 clock.p != match_clock->p)
588 continue;
79e53945
JB		 589
590 this_err = abs(clock.dot - target);
591 if (this_err < err) {
592 *best_clock = clock;
593 err = this_err;
594 }
595 }
596 }
597 }
598 }
599
600 return (err != target);
601}
602
d4906093
ML		 603static bool
604intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 605 int target, int refclk, intel_clock_t *match_clock,
606 intel_clock_t *best_clock)
d4906093
ML		 607{
608 struct drm_device *dev = crtc->dev;
d4906093
ML		 609 intel_clock_t clock;
610 int max_n;
611 bool found;
6ba770dc
AJ		 612 /* approximately equals target * 0.00585 */
613 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 614 found = false;
615
616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 617 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629 max_n = limit->n.max;
f77f13e2 630 /* based on hardware requirement, prefer smaller n to precision */
d4906093 631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 632 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 633 for (clock.m1 = limit->m1.max;
634 clock.m1 >= limit->m1.min; clock.m1--) {
635 for (clock.m2 = limit->m2.max;
636 clock.m2 >= limit->m2.min; clock.m2--) {
637 for (clock.p1 = limit->p1.max;
638 clock.p1 >= limit->p1.min; clock.p1--) {
639 int this_err;
640
2177832f 641 intel_clock(dev, refclk, &clock);
1b894b59
CW		 642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
d4906093 644 continue;
1b894b59
CW		 645
646 this_err = abs(clock.dot - target);
d4906093
ML		 647 if (this_err < err_most) {
648 *best_clock = clock;
649 err_most = this_err;
650 max_n = clock.n;
651 found = true;
652 }
653 }
654 }
655 }
656 }
2c07245f
ZW		 657 return found;
658}
659
a0c4da24
JB		 660static bool
661intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
662 int target, int refclk, intel_clock_t *match_clock,
663 intel_clock_t *best_clock)
664{
665 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
666 u32 m, n, fastclk;
667 u32 updrate, minupdate, fracbits, p;
668 unsigned long bestppm, ppm, absppm;
669 int dotclk, flag;
670
af447bd3 671 flag = 0;
a0c4da24
JB		 672 dotclk = target * 1000;
673 bestppm = 1000000;
674 ppm = absppm = 0;
675 fastclk = dotclk / (2*100);
676 updrate = 0;
677 minupdate = 19200;
678 fracbits = 1;
679 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
680 bestm1 = bestm2 = bestp1 = bestp2 = 0;
681
682 /* based on hardware requirement, prefer smaller n to precision */
683 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
684 updrate = refclk / n;
685 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
686 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
687 if (p2 > 10)
688 p2 = p2 - 1;
689 p = p1 * p2;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
692 m2 = (((2*(fastclk * p * n / m1 )) +
693 refclk) / (2*refclk));
694 m = m1 * m2;
695 vco = updrate * m;
696 if (vco >= limit->vco.min && vco < limit->vco.max) {
697 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
698 absppm = (ppm > 0) ? ppm : (-ppm);
699 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
700 bestppm = 0;
701 flag = 1;
702 }
703 if (absppm < bestppm - 10) {
704 bestppm = absppm;
705 flag = 1;
706 }
707 if (flag) {
708 bestn = n;
709 bestm1 = m1;
710 bestm2 = m2;
711 bestp1 = p1;
712 bestp2 = p2;
713 flag = 0;
714 }
715 }
716 }
717 }
718 }
719 }
720 best_clock->n = bestn;
721 best_clock->m1 = bestm1;
722 best_clock->m2 = bestm2;
723 best_clock->p1 = bestp1;
724 best_clock->p2 = bestp2;
725
726 return true;
727}
a4fc5ed6 728
a5c961d1
PZ		 729enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
730 enum pipe pipe)
731{
732 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
3b117c8f 735 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 736}
737
a928d536
PZ		 738static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
739{
740 struct drm_i915_private *dev_priv = dev->dev_private;
741 u32 frame, frame_reg = PIPEFRAME(pipe);
742
743 frame = I915_READ(frame_reg);
744
745 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
746 DRM_DEBUG_KMS("vblank wait timed out\n");
747}
748
9d0498a2
JB		 749/**
750 * intel_wait_for_vblank - wait for vblank on a given pipe
751 * @dev: drm device
752 * @pipe: pipe to wait for
753 *
754 * Wait for vblank to occur on a given pipe. Needed for various bits of
755 * mode setting code.
756 */
757void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 758{
9d0498a2 759 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 760 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 761
a928d536
PZ		 762 if (INTEL_INFO(dev)->gen >= 5) {
763 ironlake_wait_for_vblank(dev, pipe);
764 return;
765 }
766
300387c0
CW		 767 /* Clear existing vblank status. Note this will clear any other
768 * sticky status fields as well.
769 *
770 * This races with i915_driver_irq_handler() with the result
771 * that either function could miss a vblank event. Here it is not
772 * fatal, as we will either wait upon the next vblank interrupt or
773 * timeout. Generally speaking intel_wait_for_vblank() is only
774 * called during modeset at which time the GPU should be idle and
775 * should *not* be performing page flips and thus not waiting on
776 * vblanks...
777 * Currently, the result of us stealing a vblank from the irq
778 * handler is that a single frame will be skipped during swapbuffers.
779 */
780 I915_WRITE(pipestat_reg,
781 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
782
9d0498a2 783 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 784 if (wait_for(I915_READ(pipestat_reg) &
785 PIPE_VBLANK_INTERRUPT_STATUS,
786 50))
9d0498a2
JB		 787 DRM_DEBUG_KMS("vblank wait timed out\n");
788}
789
ab7ad7f6
KP		 790/*
791 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 792 * @dev: drm device
793 * @pipe: pipe to wait for
794 *
795 * After disabling a pipe, we can't wait for vblank in the usual way,
796 * spinning on the vblank interrupt status bit, since we won't actually
797 * see an interrupt when the pipe is disabled.
798 *
ab7ad7f6
KP		 799 * On Gen4 and above:
800 * wait for the pipe register state bit to turn off
801 *
802 * Otherwise:
803 * wait for the display line value to settle (it usually
804 * ends up stopping at the start of the next frame).
58e10eb9 805 *
9d0498a2 806 */
58e10eb9 807void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 808{
809 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 810 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
811 pipe);
ab7ad7f6
KP		 812
813 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 814 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 815
816 /* Wait for the Pipe State to go off */
58e10eb9
CW		 817 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
818 100))
284637d9 819 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 820 } else {
837ba00f 821 u32 last_line, line_mask;
58e10eb9 822 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 823 unsigned long timeout = jiffies + msecs_to_jiffies(100);
824
837ba00f
PZ		 825 if (IS_GEN2(dev))
826 line_mask = DSL_LINEMASK_GEN2;
827 else
828 line_mask = DSL_LINEMASK_GEN3;
829
ab7ad7f6
KP		 830 /* Wait for the display line to settle */
831 do {
837ba00f 832 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 833 mdelay(5);
837ba00f 834 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 835 time_after(timeout, jiffies));
836 if (time_after(jiffies, timeout))
284637d9 837 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 838 }
79e53945
JB		 839}
840
b0ea7d37
DL		 841/*
842 * ibx_digital_port_connected - is the specified port connected?
843 * @dev_priv: i915 private structure
844 * @port: the port to test
845 *
846 * Returns true if @port is connected, false otherwise.
847 */
848bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
849 struct intel_digital_port *port)
850{
851 u32 bit;
852
c36346e3
DL		 853 if (HAS_PCH_IBX(dev_priv->dev)) {
854 switch(port->port) {
855 case PORT_B:
856 bit = SDE_PORTB_HOTPLUG;
857 break;
858 case PORT_C:
859 bit = SDE_PORTC_HOTPLUG;
860 break;
861 case PORT_D:
862 bit = SDE_PORTD_HOTPLUG;
863 break;
864 default:
865 return true;
866 }
867 } else {
868 switch(port->port) {
869 case PORT_B:
870 bit = SDE_PORTB_HOTPLUG_CPT;
871 break;
872 case PORT_C:
873 bit = SDE_PORTC_HOTPLUG_CPT;
874 break;
875 case PORT_D:
876 bit = SDE_PORTD_HOTPLUG_CPT;
877 break;
878 default:
879 return true;
880 }
b0ea7d37
DL		 881 }
882
883 return I915_READ(SDEISR) & bit;
884}
885
b24e7179
JB		 886static const char *state_string(bool enabled)
887{
888 return enabled ? "on" : "off";
889}
890
891/* Only for pre-ILK configs */
892static void assert_pll(struct drm_i915_private *dev_priv,
893 enum pipe pipe, bool state)
894{
895 int reg;
896 u32 val;
897 bool cur_state;
898
899 reg = DPLL(pipe);
900 val = I915_READ(reg);
901 cur_state = !!(val & DPLL_VCO_ENABLE);
902 WARN(cur_state != state,
903 "PLL state assertion failure (expected %s, current %s)\n",
904 state_string(state), state_string(cur_state));
905}
906#define assert_pll_enabled(d, p) assert_pll(d, p, true)
907#define assert_pll_disabled(d, p) assert_pll(d, p, false)
908
040484af
JB		 909/* For ILK+ */
910static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 911 struct intel_pch_pll *pll,
912 struct intel_crtc *crtc,
913 bool state)
040484af 914{
040484af
JB		 915 u32 val;
916 bool cur_state;
917
9d82aa17
ED		 918 if (HAS_PCH_LPT(dev_priv->dev)) {
919 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
920 return;
921 }
922
92b27b08
CW		 923 if (WARN (!pll,
924 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 925 return;
ee7b9f93 926
92b27b08
CW		 927 val = I915_READ(pll->pll_reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
931 pll->pll_reg, state_string(state), state_string(cur_state), val);
932
933 /* Make sure the selected PLL is correctly attached to the transcoder */
934 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 935 u32 pch_dpll;
936
937 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 938 cur_state = pll->pll_reg == _PCH_DPLL_B;
939 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 940 "PLL[%d] not attached to this transcoder %c: %08x\n",
941 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 942 cur_state = !!(val >> (4*crtc->pipe + 3));
943 WARN(cur_state != state,
4bb6f1f3 944 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 945 pll->pll_reg == _PCH_DPLL_B,
946 state_string(state),
4bb6f1f3 947 pipe_name(crtc->pipe),
92b27b08
CW		 948 val);
949 }
d3ccbe86 950 }
040484af 951}
92b27b08
CW		 952#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
953#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 954
955static void assert_fdi_tx(struct drm_i915_private *dev_priv,
956 enum pipe pipe, bool state)
957{
958 int reg;
959 u32 val;
960 bool cur_state;
ad80a810
PZ		 961 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
962 pipe);
040484af 963
affa9354
PZ		 964 if (HAS_DDI(dev_priv->dev)) {
965 /* DDI does not have a specific FDI_TX register */
ad80a810 966 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 967 val = I915_READ(reg);
ad80a810 968 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 969 } else {
970 reg = FDI_TX_CTL(pipe);
971 val = I915_READ(reg);
972 cur_state = !!(val & FDI_TX_ENABLE);
973 }
040484af
JB		 974 WARN(cur_state != state,
975 "FDI TX state assertion failure (expected %s, current %s)\n",
976 state_string(state), state_string(cur_state));
977}
978#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
979#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
980
981static void assert_fdi_rx(struct drm_i915_private *dev_priv,
982 enum pipe pipe, bool state)
983{
984 int reg;
985 u32 val;
986 bool cur_state;
987
d63fa0dc
PZ		 988 reg = FDI_RX_CTL(pipe);
989 val = I915_READ(reg);
990 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 991 WARN(cur_state != state,
992 "FDI RX state assertion failure (expected %s, current %s)\n",
993 state_string(state), state_string(cur_state));
994}
995#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
996#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
997
998static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
999 enum pipe pipe)
1000{
1001 int reg;
1002 u32 val;
1003
1004 /* ILK FDI PLL is always enabled */
1005 if (dev_priv->info->gen == 5)
1006 return;
1007
bf507ef7 1008 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1009 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1010 return;
1011
040484af
JB		 1012 reg = FDI_TX_CTL(pipe);
1013 val = I915_READ(reg);
1014 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1015}
1016
1017static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe)
1019{
1020 int reg;
1021 u32 val;
1022
1023 reg = FDI_RX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1026}
1027
ea0760cf
JB		 1028static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1029 enum pipe pipe)
1030{
1031 int pp_reg, lvds_reg;
1032 u32 val;
1033 enum pipe panel_pipe = PIPE_A;
0de3b485 1034 bool locked = true;
ea0760cf
JB		 1035
1036 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1037 pp_reg = PCH_PP_CONTROL;
1038 lvds_reg = PCH_LVDS;
1039 } else {
1040 pp_reg = PP_CONTROL;
1041 lvds_reg = LVDS;
1042 }
1043
1044 val = I915_READ(pp_reg);
1045 if (!(val & PANEL_POWER_ON) ||
1046 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1047 locked = false;
1048
1049 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1050 panel_pipe = PIPE_B;
1051
1052 WARN(panel_pipe == pipe && locked,
1053 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1054 pipe_name(pipe));
ea0760cf
JB		 1055}
1056
b840d907
JB		 1057void assert_pipe(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, bool state)
b24e7179
JB		 1059{
1060 int reg;
1061 u32 val;
63d7bbe9 1062 bool cur_state;
702e7a56
PZ		 1063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064 pipe);
b24e7179 1065
8e636784
DV		 1066 /* if we need the pipe A quirk it must be always on */
1067 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1068 state = true;
1069
b97186f0
PZ		 1070 if (!intel_display_power_enabled(dev_priv->dev,
1071 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1072 cur_state = false;
1073 } else {
1074 reg = PIPECONF(cpu_transcoder);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & PIPECONF_ENABLE);
1077 }
1078
63d7bbe9
JB		 1079 WARN(cur_state != state,
1080 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1081 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1082}
1083
931872fc
CW		 1084static void assert_plane(struct drm_i915_private *dev_priv,
1085 enum plane plane, bool state)
b24e7179
JB		 1086{
1087 int reg;
1088 u32 val;
931872fc 1089 bool cur_state;
b24e7179
JB		 1090
1091 reg = DSPCNTR(plane);
1092 val = I915_READ(reg);
931872fc
CW		 1093 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1094 WARN(cur_state != state,
1095 "plane %c assertion failure (expected %s, current %s)\n",
1096 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1097}
1098
931872fc
CW		 1099#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1100#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1101
b24e7179
JB		 1102static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104{
1105 int reg, i;
1106 u32 val;
1107 int cur_pipe;
1108
19ec1358 1109 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1110 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1111 reg = DSPCNTR(pipe);
1112 val = I915_READ(reg);
1113 WARN((val & DISPLAY_PLANE_ENABLE),
1114 "plane %c assertion failure, should be disabled but not\n",
1115 plane_name(pipe));
19ec1358 1116 return;
28c05794 1117 }
19ec1358 1118
b24e7179
JB		 1119 /* Need to check both planes against the pipe */
1120 for (i = 0; i < 2; i++) {
1121 reg = DSPCNTR(i);
1122 val = I915_READ(reg);
1123 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1124 DISPPLANE_SEL_PIPE_SHIFT;
1125 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1126 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1127 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1128 }
1129}
1130
19332d7a
JB		 1131static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1132 enum pipe pipe)
1133{
1134 int reg, i;
1135 u32 val;
1136
1137 if (!IS_VALLEYVIEW(dev_priv->dev))
1138 return;
1139
1140 /* Need to check both planes against the pipe */
1141 for (i = 0; i < dev_priv->num_plane; i++) {
1142 reg = SPCNTR(pipe, i);
1143 val = I915_READ(reg);
1144 WARN((val & SP_ENABLE),
06da8da2
VS		 1145 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1147 }
1148}
1149
92f2584a
JB		 1150static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1151{
1152 u32 val;
1153 bool enabled;
1154
9d82aa17
ED		 1155 if (HAS_PCH_LPT(dev_priv->dev)) {
1156 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1157 return;
1158 }
1159
92f2584a
JB		 1160 val = I915_READ(PCH_DREF_CONTROL);
1161 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1162 DREF_SUPERSPREAD_SOURCE_MASK));
1163 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1164}
1165
ab9412ba
DV		 1166static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1167 enum pipe pipe)
92f2584a
JB		 1168{
1169 int reg;
1170 u32 val;
1171 bool enabled;
1172
ab9412ba 1173 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1174 val = I915_READ(reg);
1175 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1176 WARN(enabled,
1177 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1178 pipe_name(pipe));
92f2584a
JB		 1179}
1180
4e634389
KP		 1181static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1183{
1184 if ((val & DP_PORT_EN) == 0)
1185 return false;
1186
1187 if (HAS_PCH_CPT(dev_priv->dev)) {
1188 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1189 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1190 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1191 return false;
1192 } else {
1193 if ((val & DP_PIPE_MASK) != (pipe << 30))
1194 return false;
1195 }
1196 return true;
1197}
1198
1519b995
KP		 1199static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, u32 val)
1201{
dc0fa718 1202 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1203 return false;
1204
1205 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1206 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1207 return false;
1208 } else {
dc0fa718 1209 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1210 return false;
1211 }
1212 return true;
1213}
1214
1215static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, u32 val)
1217{
1218 if ((val & LVDS_PORT_EN) == 0)
1219 return false;
1220
1221 if (HAS_PCH_CPT(dev_priv->dev)) {
1222 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1223 return false;
1224 } else {
1225 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1226 return false;
1227 }
1228 return true;
1229}
1230
1231static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, u32 val)
1233{
1234 if ((val & ADPA_DAC_ENABLE) == 0)
1235 return false;
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1241 return false;
1242 }
1243 return true;
1244}
1245
291906f1 1246static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1247 enum pipe pipe, int reg, u32 port_sel)
291906f1 1248{
47a05eca 1249 u32 val = I915_READ(reg);
4e634389 1250 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1251 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1252 reg, pipe_name(pipe));
de9a35ab 1253
75c5da27
DV		 1254 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1255 && (val & DP_PIPEB_SELECT),
de9a35ab 1256 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1257}
1258
1259static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1260 enum pipe pipe, int reg)
1261{
47a05eca 1262 u32 val = I915_READ(reg);
b70ad586 1263 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1264 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1265 reg, pipe_name(pipe));
de9a35ab 1266
dc0fa718 1267 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1268 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1269 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1270}
1271
1272static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1273 enum pipe pipe)
1274{
1275 int reg;
1276 u32 val;
291906f1 1277
f0575e92
KP		 1278 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1279 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1280 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1281
1282 reg = PCH_ADPA;
1283 val = I915_READ(reg);
b70ad586 1284 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1285 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1286 pipe_name(pipe));
291906f1
JB		 1287
1288 reg = PCH_LVDS;
1289 val = I915_READ(reg);
b70ad586 1290 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1291 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 pipe_name(pipe));
291906f1 1293
e2debe91
PZ		 1294 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1295 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1296 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1297}
1298
63d7bbe9
JB		 1299/**
1300 * intel_enable_pll - enable a PLL
1301 * @dev_priv: i915 private structure
1302 * @pipe: pipe PLL to enable
1303 *
1304 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1305 * make sure the PLL reg is writable first though, since the panel write
1306 * protect mechanism may be enabled.
1307 *
1308 * Note! This is for pre-ILK only.
7434a255
TR		 1309 *
1310 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1311 */
1312static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313{
1314 int reg;
1315 u32 val;
1316
58c6eaa2
DV		 1317 assert_pipe_disabled(dev_priv, pipe);
1318
63d7bbe9 1319 /* No really, not for ILK+ */
a0c4da24 1320 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1321
1322 /* PLL is protected by panel, make sure we can write it */
1323 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1324 assert_panel_unlocked(dev_priv, pipe);
1325
1326 reg = DPLL(pipe);
1327 val = I915_READ(reg);
1328 val |= DPLL_VCO_ENABLE;
1329
1330 /* We do this three times for luck */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340}
1341
1342/**
1343 * intel_disable_pll - disable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to disable
1346 *
1347 * Disable the PLL for @pipe, making sure the pipe is off first.
1348 *
1349 * Note! This is for pre-ILK only.
1350 */
1351static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1352{
1353 int reg;
1354 u32 val;
1355
1356 /* Don't disable pipe A or pipe A PLLs if needed */
1357 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1358 return;
1359
1360 /* Make sure the pipe isn't still relying on us */
1361 assert_pipe_disabled(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val &= ~DPLL_VCO_ENABLE;
1366 I915_WRITE(reg, val);
1367 POSTING_READ(reg);
1368}
1369
89b667f8
JB		 1370void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1371{
1372 u32 port_mask;
1373
1374 if (!port)
1375 port_mask = DPLL_PORTB_READY_MASK;
1376 else
1377 port_mask = DPLL_PORTC_READY_MASK;
1378
1379 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1380 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1381 'B' + port, I915_READ(DPLL(0)));
1382}
1383
92f2584a 1384/**
b6b4e185 1385 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1386 * @dev_priv: i915 private structure
1387 * @pipe: pipe PLL to enable
1388 *
1389 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390 * drives the transcoder clock.
1391 */
b6b4e185 1392static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1393{
ee7b9f93 1394 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1395 struct intel_pch_pll *pll;
92f2584a
JB		 1396 int reg;
1397 u32 val;
1398
48da64a8 1399 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1400 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1401 pll = intel_crtc->pch_pll;
1402 if (pll == NULL)
1403 return;
1404
1405 if (WARN_ON(pll->refcount == 0))
1406 return;
ee7b9f93
JB		 1407
1408 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1409 pll->pll_reg, pll->active, pll->on,
1410 intel_crtc->base.base.id);
92f2584a
JB		 1411
1412 /* PCH refclock must be enabled first */
1413 assert_pch_refclk_enabled(dev_priv);
1414
ee7b9f93 1415 if (pll->active++ && pll->on) {
92b27b08 1416 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1417 return;
1418 }
1419
1420 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1421
1422 reg = pll->pll_reg;
92f2584a
JB		 1423 val = I915_READ(reg);
1424 val |= DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
ee7b9f93
JB		 1428
1429 pll->on = true;
92f2584a
JB		 1430}
1431
ee7b9f93 1432static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1433{
ee7b9f93
JB		 1434 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1435 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1436 int reg;
ee7b9f93 1437 u32 val;
4c609cb8 1438
92f2584a
JB		 1439 /* PCH only available on ILK+ */
1440 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1441 if (pll == NULL)
1442 return;
92f2584a 1443
48da64a8
CW		 1444 if (WARN_ON(pll->refcount == 0))
1445 return;
7a419866 1446
ee7b9f93
JB		 1447 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1448 pll->pll_reg, pll->active, pll->on,
1449 intel_crtc->base.base.id);
7a419866 1450
48da64a8 1451 if (WARN_ON(pll->active == 0)) {
92b27b08 1452 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1453 return;
1454 }
1455
ee7b9f93 1456 if (--pll->active) {
92b27b08 1457 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1458 return;
ee7b9f93
JB		 1459 }
1460
1461 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1462
1463 /* Make sure transcoder isn't still depending on us */
ab9412ba 1464 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1465
ee7b9f93 1466 reg = pll->pll_reg;
92f2584a
JB		 1467 val = I915_READ(reg);
1468 val &= ~DPLL_VCO_ENABLE;
1469 I915_WRITE(reg, val);
1470 POSTING_READ(reg);
1471 udelay(200);
ee7b9f93
JB		 1472
1473 pll->on = false;
92f2584a
JB		 1474}
1475
b8a4f404
PZ		 1476static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1477 enum pipe pipe)
040484af 1478{
23670b32 1479 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1481 uint32_t reg, val, pipeconf_val;
040484af
JB		 1482
1483 /* PCH only available on ILK+ */
1484 BUG_ON(dev_priv->info->gen < 5);
1485
1486 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1487 assert_pch_pll_enabled(dev_priv,
1488 to_intel_crtc(crtc)->pch_pll,
1489 to_intel_crtc(crtc));
040484af
JB		 1490
1491 /* FDI must be feeding us bits for PCH ports */
1492 assert_fdi_tx_enabled(dev_priv, pipe);
1493 assert_fdi_rx_enabled(dev_priv, pipe);
1494
23670b32
DV		 1495 if (HAS_PCH_CPT(dev)) {
1496 /* Workaround: Set the timing override bit before enabling the
1497 * pch transcoder. */
1498 reg = TRANS_CHICKEN2(pipe);
1499 val = I915_READ(reg);
1500 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1501 I915_WRITE(reg, val);
59c859d6 1502 }
23670b32 1503
ab9412ba 1504 reg = PCH_TRANSCONF(pipe);
040484af 1505 val = I915_READ(reg);
5f7f726d 1506 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1507
1508 if (HAS_PCH_IBX(dev_priv->dev)) {
1509 /*
1510 * make the BPC in transcoder be consistent with
1511 * that in pipeconf reg.
1512 */
dfd07d72
DV		 1513 val &= ~PIPECONF_BPC_MASK;
1514 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1515 }
5f7f726d
PZ		 1516
1517 val &= ~TRANS_INTERLACE_MASK;
1518 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1519 if (HAS_PCH_IBX(dev_priv->dev) &&
1520 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1521 val |= TRANS_LEGACY_INTERLACED_ILK;
1522 else
1523 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1524 else
1525 val |= TRANS_PROGRESSIVE;
1526
040484af
JB		 1527 I915_WRITE(reg, val | TRANS_ENABLE);
1528 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1529 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1530}
1531
8fb033d7 1532static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1533 enum transcoder cpu_transcoder)
040484af 1534{
8fb033d7 1535 u32 val, pipeconf_val;
8fb033d7
PZ		 1536
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1539
8fb033d7 1540 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1541 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1542 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1543
223a6fdf
PZ		 1544 /* Workaround: set timing override bit. */
1545 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1546 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1547 I915_WRITE(_TRANSA_CHICKEN2, val);
1548
25f3ef11 1549 val = TRANS_ENABLE;
937bb610 1550 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1551
9a76b1c6
PZ		 1552 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1553 PIPECONF_INTERLACED_ILK)
a35f2679 1554 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1555 else
1556 val |= TRANS_PROGRESSIVE;
1557
ab9412ba
DV		 1558 I915_WRITE(LPT_TRANSCONF, val);
1559 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1560 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1561}
1562
b8a4f404
PZ		 1563static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1564 enum pipe pipe)
040484af 1565{
23670b32
DV		 1566 struct drm_device *dev = dev_priv->dev;
1567 uint32_t reg, val;
040484af
JB		 1568
1569 /* FDI relies on the transcoder */
1570 assert_fdi_tx_disabled(dev_priv, pipe);
1571 assert_fdi_rx_disabled(dev_priv, pipe);
1572
291906f1
JB		 1573 /* Ports must be off as well */
1574 assert_pch_ports_disabled(dev_priv, pipe);
1575
ab9412ba 1576 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1577 val = I915_READ(reg);
1578 val &= ~TRANS_ENABLE;
1579 I915_WRITE(reg, val);
1580 /* wait for PCH transcoder off, transcoder state */
1581 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1582 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1583
1584 if (!HAS_PCH_IBX(dev)) {
1585 /* Workaround: Clear the timing override chicken bit again. */
1586 reg = TRANS_CHICKEN2(pipe);
1587 val = I915_READ(reg);
1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589 I915_WRITE(reg, val);
1590 }
040484af
JB		 1591}
1592
ab4d966c 1593static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1594{
8fb033d7
PZ		 1595 u32 val;
1596
ab9412ba 1597 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1598 val &= ~TRANS_ENABLE;
ab9412ba 1599 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1600 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1601 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1602 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1603
1604 /* Workaround: clear timing override bit. */
1605 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1606 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1607 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1608}
1609
b24e7179 1610/**
309cfea8 1611 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1612 * @dev_priv: i915 private structure
1613 * @pipe: pipe to enable
040484af 1614 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1615 *
1616 * Enable @pipe, making sure that various hardware specific requirements
1617 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1618 *
1619 * @pipe should be %PIPE_A or %PIPE_B.
1620 *
1621 * Will wait until the pipe is actually running (i.e. first vblank) before
1622 * returning.
1623 */
040484af
JB		 1624static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1625 bool pch_port)
b24e7179 1626{
702e7a56
PZ		 1627 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1628 pipe);
1a240d4d 1629 enum pipe pch_transcoder;
b24e7179
JB		 1630 int reg;
1631 u32 val;
1632
58c6eaa2
DV		 1633 assert_planes_disabled(dev_priv, pipe);
1634 assert_sprites_disabled(dev_priv, pipe);
1635
681e5811 1636 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1637 pch_transcoder = TRANSCODER_A;
1638 else
1639 pch_transcoder = pipe;
1640
b24e7179
JB		 1641 /*
1642 * A pipe without a PLL won't actually be able to drive bits from
1643 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1644 * need the check.
1645 */
1646 if (!HAS_PCH_SPLIT(dev_priv->dev))
1647 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1648 else {
1649 if (pch_port) {
1650 /* if driving the PCH, we need FDI enabled */
cc391bbb 1651 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1652 assert_fdi_tx_pll_enabled(dev_priv,
1653 (enum pipe) cpu_transcoder);
040484af
JB		 1654 }
1655 /* FIXME: assert CPU port conditions for SNB+ */
1656 }
b24e7179 1657
702e7a56 1658 reg = PIPECONF(cpu_transcoder);
b24e7179 1659 val = I915_READ(reg);
00d70b15
CW		 1660 if (val & PIPECONF_ENABLE)
1661 return;
1662
1663 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1664 intel_wait_for_vblank(dev_priv->dev, pipe);
1665}
1666
1667/**
309cfea8 1668 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1669 * @dev_priv: i915 private structure
1670 * @pipe: pipe to disable
1671 *
1672 * Disable @pipe, making sure that various hardware specific requirements
1673 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1674 *
1675 * @pipe should be %PIPE_A or %PIPE_B.
1676 *
1677 * Will wait until the pipe has shut down before returning.
1678 */
1679static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1680 enum pipe pipe)
1681{
702e7a56
PZ		 1682 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1683 pipe);
b24e7179
JB		 1684 int reg;
1685 u32 val;
1686
1687 /*
1688 * Make sure planes won't keep trying to pump pixels to us,
1689 * or we might hang the display.
1690 */
1691 assert_planes_disabled(dev_priv, pipe);
19332d7a 1692 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1693
1694 /* Don't disable pipe A or pipe A PLLs if needed */
1695 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1696 return;
1697
702e7a56 1698 reg = PIPECONF(cpu_transcoder);
b24e7179 1699 val = I915_READ(reg);
00d70b15
CW		 1700 if ((val & PIPECONF_ENABLE) == 0)
1701 return;
1702
1703 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1704 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1705}
1706
d74362c9
KP		 1707/*
1708 * Plane regs are double buffered, going from enabled->disabled needs a
1709 * trigger in order to latch. The display address reg provides this.
1710 */
6f1d69b0 1711void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1712 enum plane plane)
1713{
14f86147
DL		 1714 if (dev_priv->info->gen >= 4)
1715 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1716 else
1717 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1718}
1719
b24e7179
JB		 1720/**
1721 * intel_enable_plane - enable a display plane on a given pipe
1722 * @dev_priv: i915 private structure
1723 * @plane: plane to enable
1724 * @pipe: pipe being fed
1725 *
1726 * Enable @plane on @pipe, making sure that @pipe is running first.
1727 */
1728static void intel_enable_plane(struct drm_i915_private *dev_priv,
1729 enum plane plane, enum pipe pipe)
1730{
1731 int reg;
1732 u32 val;
1733
1734 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1735 assert_pipe_enabled(dev_priv, pipe);
1736
1737 reg = DSPCNTR(plane);
1738 val = I915_READ(reg);
00d70b15
CW		 1739 if (val & DISPLAY_PLANE_ENABLE)
1740 return;
1741
1742 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1743 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
b24e7179
JB		 1747/**
1748 * intel_disable_plane - disable a display plane
1749 * @dev_priv: i915 private structure
1750 * @plane: plane to disable
1751 * @pipe: pipe consuming the data
1752 *
1753 * Disable @plane; should be an independent operation.
1754 */
1755static void intel_disable_plane(struct drm_i915_private *dev_priv,
1756 enum plane plane, enum pipe pipe)
1757{
1758 int reg;
1759 u32 val;
1760
1761 reg = DSPCNTR(plane);
1762 val = I915_READ(reg);
00d70b15
CW		 1763 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1764 return;
1765
1766 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1767 intel_flush_display_plane(dev_priv, plane);
1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
693db184
CW		 1771static bool need_vtd_wa(struct drm_device *dev)
1772{
1773#ifdef CONFIG_INTEL_IOMMU
1774 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1775 return true;
1776#endif
1777 return false;
1778}
1779
127bd2ac 1780int
48b956c5 1781intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1782 struct drm_i915_gem_object *obj,
919926ae 1783 struct intel_ring_buffer *pipelined)
6b95a207 1784{
ce453d81 1785 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1786 u32 alignment;
1787 int ret;
1788
05394f39 1789 switch (obj->tiling_mode) {
6b95a207 1790 case I915_TILING_NONE:
534843da
CW		 1791 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1792 alignment = 128 * 1024;
a6c45cf0 1793 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1794 alignment = 4 * 1024;
1795 else
1796 alignment = 64 * 1024;
6b95a207
KH		 1797 break;
1798 case I915_TILING_X:
1799 /* pin() will align the object as required by fence */
1800 alignment = 0;
1801 break;
1802 case I915_TILING_Y:
8bb6e959
DV		 1803 /* Despite that we check this in framebuffer_init userspace can
1804 * screw us over and change the tiling after the fact. Only
1805 * pinned buffers can't change their tiling. */
1806 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1807 return -EINVAL;
1808 default:
1809 BUG();
1810 }
1811
693db184
CW		 1812 /* Note that the w/a also requires 64 PTE of padding following the
1813 * bo. We currently fill all unused PTE with the shadow page and so
1814 * we should always have valid PTE following the scanout preventing
1815 * the VT-d warning.
1816 */
1817 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1818 alignment = 256 * 1024;
1819
ce453d81 1820 dev_priv->mm.interruptible = false;
2da3b9b9 1821 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1822 if (ret)
ce453d81 1823 goto err_interruptible;
6b95a207
KH		 1824
1825 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1826 * fence, whereas 965+ only requires a fence if using
1827 * framebuffer compression. For simplicity, we always install
1828 * a fence as the cost is not that onerous.
1829 */
06d98131 1830 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1831 if (ret)
1832 goto err_unpin;
1690e1eb 1833
9a5a53b3 1834 i915_gem_object_pin_fence(obj);
6b95a207 1835
ce453d81 1836 dev_priv->mm.interruptible = true;
6b95a207 1837 return 0;
48b956c5
CW		 1838
1839err_unpin:
1840 i915_gem_object_unpin(obj);
ce453d81
CW		 1841err_interruptible:
1842 dev_priv->mm.interruptible = true;
48b956c5 1843 return ret;
6b95a207
KH		 1844}
1845
1690e1eb
CW		 1846void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1847{
1848 i915_gem_object_unpin_fence(obj);
1849 i915_gem_object_unpin(obj);
1850}
1851
c2c75131
DV		 1852/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1853 * is assumed to be a power-of-two. */
bc752862
CW		 1854unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1855 unsigned int tiling_mode,
1856 unsigned int cpp,
1857 unsigned int pitch)
c2c75131 1858{
bc752862
CW		 1859 if (tiling_mode != I915_TILING_NONE) {
1860 unsigned int tile_rows, tiles;
c2c75131 1861
bc752862
CW		 1862 tile_rows = *y / 8;
1863 *y %= 8;
c2c75131 1864
bc752862
CW		 1865 tiles = *x / (512/cpp);
1866 *x %= 512/cpp;
1867
1868 return tile_rows * pitch * 8 + tiles * 4096;
1869 } else {
1870 unsigned int offset;
1871
1872 offset = *y * pitch + *x * cpp;
1873 *y = 0;
1874 *x = (offset & 4095) / cpp;
1875 return offset & -4096;
1876 }
c2c75131
DV		 1877}
1878
17638cd6
JB		 1879static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1880 int x, int y)
81255565
JB		 1881{
1882 struct drm_device *dev = crtc->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885 struct intel_framebuffer *intel_fb;
05394f39 1886 struct drm_i915_gem_object *obj;
81255565 1887 int plane = intel_crtc->plane;
e506a0c6 1888 unsigned long linear_offset;
81255565 1889 u32 dspcntr;
5eddb70b 1890 u32 reg;
81255565
JB		 1891
1892 switch (plane) {
1893 case 0:
1894 case 1:
1895 break;
1896 default:
84f44ce7 1897 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1898 return -EINVAL;
1899 }
1900
1901 intel_fb = to_intel_framebuffer(fb);
1902 obj = intel_fb->obj;
81255565 1903
5eddb70b
CW		 1904 reg = DSPCNTR(plane);
1905 dspcntr = I915_READ(reg);
81255565
JB		 1906 /* Mask out pixel format bits in case we change it */
1907 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1908 switch (fb->pixel_format) {
1909 case DRM_FORMAT_C8:
81255565
JB		 1910 dspcntr |= DISPPLANE_8BPP;
1911 break;
57779d06
VS		 1912 case DRM_FORMAT_XRGB1555:
1913 case DRM_FORMAT_ARGB1555:
1914 dspcntr |= DISPPLANE_BGRX555;
81255565 1915 break;
57779d06
VS		 1916 case DRM_FORMAT_RGB565:
1917 dspcntr |= DISPPLANE_BGRX565;
1918 break;
1919 case DRM_FORMAT_XRGB8888:
1920 case DRM_FORMAT_ARGB8888:
1921 dspcntr |= DISPPLANE_BGRX888;
1922 break;
1923 case DRM_FORMAT_XBGR8888:
1924 case DRM_FORMAT_ABGR8888:
1925 dspcntr |= DISPPLANE_RGBX888;
1926 break;
1927 case DRM_FORMAT_XRGB2101010:
1928 case DRM_FORMAT_ARGB2101010:
1929 dspcntr |= DISPPLANE_BGRX101010;
1930 break;
1931 case DRM_FORMAT_XBGR2101010:
1932 case DRM_FORMAT_ABGR2101010:
1933 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1934 break;
1935 default:
baba133a 1936 BUG();
81255565 1937 }
57779d06 1938
a6c45cf0 1939 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1940 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1941 dspcntr |= DISPPLANE_TILED;
1942 else
1943 dspcntr &= ~DISPPLANE_TILED;
1944 }
1945
5eddb70b 1946 I915_WRITE(reg, dspcntr);
81255565 1947
e506a0c6 1948 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1949
c2c75131
DV		 1950 if (INTEL_INFO(dev)->gen >= 4) {
1951 intel_crtc->dspaddr_offset =
bc752862
CW		 1952 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1953 fb->bits_per_pixel / 8,
1954 fb->pitches[0]);
c2c75131
DV		 1955 linear_offset -= intel_crtc->dspaddr_offset;
1956 } else {
e506a0c6 1957 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1958 }
e506a0c6
DV		 1959
1960 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1961 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1962 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1963 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1964 I915_MODIFY_DISPBASE(DSPSURF(plane),
1965 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1966 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1967 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1968 } else
e506a0c6 1969 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1970 POSTING_READ(reg);
81255565 1971
17638cd6
JB		 1972 return 0;
1973}
1974
1975static int ironlake_update_plane(struct drm_crtc *crtc,
1976 struct drm_framebuffer *fb, int x, int y)
1977{
1978 struct drm_device *dev = crtc->dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981 struct intel_framebuffer *intel_fb;
1982 struct drm_i915_gem_object *obj;
1983 int plane = intel_crtc->plane;
e506a0c6 1984 unsigned long linear_offset;
17638cd6
JB		 1985 u32 dspcntr;
1986 u32 reg;
1987
1988 switch (plane) {
1989 case 0:
1990 case 1:
27f8227b 1991 case 2:
17638cd6
JB		 1992 break;
1993 default:
84f44ce7 1994 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1995 return -EINVAL;
1996 }
1997
1998 intel_fb = to_intel_framebuffer(fb);
1999 obj = intel_fb->obj;
2000
2001 reg = DSPCNTR(plane);
2002 dspcntr = I915_READ(reg);
2003 /* Mask out pixel format bits in case we change it */
2004 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2005 switch (fb->pixel_format) {
2006 case DRM_FORMAT_C8:
17638cd6
JB		 2007 dspcntr |= DISPPLANE_8BPP;
2008 break;
57779d06
VS		 2009 case DRM_FORMAT_RGB565:
2010 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2011 break;
57779d06
VS		 2012 case DRM_FORMAT_XRGB8888:
2013 case DRM_FORMAT_ARGB8888:
2014 dspcntr |= DISPPLANE_BGRX888;
2015 break;
2016 case DRM_FORMAT_XBGR8888:
2017 case DRM_FORMAT_ABGR8888:
2018 dspcntr |= DISPPLANE_RGBX888;
2019 break;
2020 case DRM_FORMAT_XRGB2101010:
2021 case DRM_FORMAT_ARGB2101010:
2022 dspcntr |= DISPPLANE_BGRX101010;
2023 break;
2024 case DRM_FORMAT_XBGR2101010:
2025 case DRM_FORMAT_ABGR2101010:
2026 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2027 break;
2028 default:
baba133a 2029 BUG();
17638cd6
JB		 2030 }
2031
2032 if (obj->tiling_mode != I915_TILING_NONE)
2033 dspcntr |= DISPPLANE_TILED;
2034 else
2035 dspcntr &= ~DISPPLANE_TILED;
2036
2037 /* must disable */
2038 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2039
2040 I915_WRITE(reg, dspcntr);
2041
e506a0c6 2042 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2043 intel_crtc->dspaddr_offset =
bc752862
CW		 2044 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2045 fb->bits_per_pixel / 8,
2046 fb->pitches[0]);
c2c75131 2047 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2048
e506a0c6
DV		 2049 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2050 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2051 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2052 I915_MODIFY_DISPBASE(DSPSURF(plane),
2053 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2054 if (IS_HASWELL(dev)) {
2055 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2056 } else {
2057 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2058 I915_WRITE(DSPLINOFF(plane), linear_offset);
2059 }
17638cd6
JB		 2060 POSTING_READ(reg);
2061
2062 return 0;
2063}
2064
2065/* Assume fb object is pinned & idle & fenced and just update base pointers */
2066static int
2067intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2068 int x, int y, enum mode_set_atomic state)
2069{
2070 struct drm_device *dev = crtc->dev;
2071 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2072
6b8e6ed0
CW		 2073 if (dev_priv->display.disable_fbc)
2074 dev_priv->display.disable_fbc(dev);
3dec0095 2075 intel_increase_pllclock(crtc);
81255565 2076
6b8e6ed0 2077 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2078}
2079
96a02917
VS		 2080void intel_display_handle_reset(struct drm_device *dev)
2081{
2082 struct drm_i915_private *dev_priv = dev->dev_private;
2083 struct drm_crtc *crtc;
2084
2085 /*
2086 * Flips in the rings have been nuked by the reset,
2087 * so complete all pending flips so that user space
2088 * will get its events and not get stuck.
2089 *
2090 * Also update the base address of all primary
2091 * planes to the the last fb to make sure we're
2092 * showing the correct fb after a reset.
2093 *
2094 * Need to make two loops over the crtcs so that we
2095 * don't try to grab a crtc mutex before the
2096 * pending_flip_queue really got woken up.
2097 */
2098
2099 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101 enum plane plane = intel_crtc->plane;
2102
2103 intel_prepare_page_flip(dev, plane);
2104 intel_finish_page_flip_plane(dev, plane);
2105 }
2106
2107 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110 mutex_lock(&crtc->mutex);
2111 if (intel_crtc->active)
2112 dev_priv->display.update_plane(crtc, crtc->fb,
2113 crtc->x, crtc->y);
2114 mutex_unlock(&crtc->mutex);
2115 }
2116}
2117
14667a4b
CW		 2118static int
2119intel_finish_fb(struct drm_framebuffer *old_fb)
2120{
2121 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2122 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2123 bool was_interruptible = dev_priv->mm.interruptible;
2124 int ret;
2125
14667a4b
CW		 2126 /* Big Hammer, we also need to ensure that any pending
2127 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2128 * current scanout is retired before unpinning the old
2129 * framebuffer.
2130 *
2131 * This should only fail upon a hung GPU, in which case we
2132 * can safely continue.
2133 */
2134 dev_priv->mm.interruptible = false;
2135 ret = i915_gem_object_finish_gpu(obj);
2136 dev_priv->mm.interruptible = was_interruptible;
2137
2138 return ret;
2139}
2140
198598d0
VS		 2141static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2142{
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_master_private *master_priv;
2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146
2147 if (!dev->primary->master)
2148 return;
2149
2150 master_priv = dev->primary->master->driver_priv;
2151 if (!master_priv->sarea_priv)
2152 return;
2153
2154 switch (intel_crtc->pipe) {
2155 case 0:
2156 master_priv->sarea_priv->pipeA_x = x;
2157 master_priv->sarea_priv->pipeA_y = y;
2158 break;
2159 case 1:
2160 master_priv->sarea_priv->pipeB_x = x;
2161 master_priv->sarea_priv->pipeB_y = y;
2162 break;
2163 default:
2164 break;
2165 }
2166}
2167
5c3b82e2 2168static int
3c4fdcfb 2169intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2170 struct drm_framebuffer *fb)
79e53945
JB		 2171{
2172 struct drm_device *dev = crtc->dev;
6b8e6ed0 2173 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2175 struct drm_framebuffer *old_fb;
5c3b82e2 2176 int ret;
79e53945
JB		 2177
2178 /* no fb bound */
94352cf9 2179 if (!fb) {
a5071c2f 2180 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2181 return 0;
2182 }
2183
7eb552ae 2184 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2185 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2186 plane_name(intel_crtc->plane),
2187 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2188 return -EINVAL;
79e53945
JB		 2189 }
2190
5c3b82e2 2191 mutex_lock(&dev->struct_mutex);
265db958 2192 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2193 to_intel_framebuffer(fb)->obj,
919926ae 2194 NULL);
5c3b82e2
CW		 2195 if (ret != 0) {
2196 mutex_unlock(&dev->struct_mutex);
a5071c2f 2197 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2198 return ret;
2199 }
79e53945 2200
94352cf9 2201 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2202 if (ret) {
94352cf9 2203 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2204 mutex_unlock(&dev->struct_mutex);
a5071c2f 2205 DRM_ERROR("failed to update base address\n");
4e6cfefc 2206 return ret;
79e53945 2207 }
3c4fdcfb 2208
94352cf9
DV		 2209 old_fb = crtc->fb;
2210 crtc->fb = fb;
6c4c86f5
DV		 2211 crtc->x = x;
2212 crtc->y = y;
94352cf9 2213
b7f1de28
CW		 2214 if (old_fb) {
2215 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2216 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2217 }
652c393a 2218
6b8e6ed0 2219 intel_update_fbc(dev);
5c3b82e2 2220 mutex_unlock(&dev->struct_mutex);
79e53945 2221
198598d0 2222 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2223
2224 return 0;
79e53945
JB		 2225}
2226
5e84e1a4
ZW		 2227static void intel_fdi_normal_train(struct drm_crtc *crtc)
2228{
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232 int pipe = intel_crtc->pipe;
2233 u32 reg, temp;
2234
2235 /* enable normal train */
2236 reg = FDI_TX_CTL(pipe);
2237 temp = I915_READ(reg);
61e499bf 2238 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2239 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2240 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2241 } else {
2242 temp &= ~FDI_LINK_TRAIN_NONE;
2243 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2244 }
5e84e1a4
ZW		 2245 I915_WRITE(reg, temp);
2246
2247 reg = FDI_RX_CTL(pipe);
2248 temp = I915_READ(reg);
2249 if (HAS_PCH_CPT(dev)) {
2250 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2251 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2252 } else {
2253 temp &= ~FDI_LINK_TRAIN_NONE;
2254 temp |= FDI_LINK_TRAIN_NONE;
2255 }
2256 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2257
2258 /* wait one idle pattern time */
2259 POSTING_READ(reg);
2260 udelay(1000);
357555c0
JB		 2261
2262 /* IVB wants error correction enabled */
2263 if (IS_IVYBRIDGE(dev))
2264 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2265 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2266}
2267
1e833f40
DV		 2268static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2269{
2270 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2271}
2272
01a415fd
DV		 2273static void ivb_modeset_global_resources(struct drm_device *dev)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 struct intel_crtc *pipe_B_crtc =
2277 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2278 struct intel_crtc *pipe_C_crtc =
2279 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2280 uint32_t temp;
2281
1e833f40
DV		 2282 /*
2283 * When everything is off disable fdi C so that we could enable fdi B
2284 * with all lanes. Note that we don't care about enabled pipes without
2285 * an enabled pch encoder.
2286 */
2287 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2288 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2289 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2290 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2291
2292 temp = I915_READ(SOUTH_CHICKEN1);
2293 temp &= ~FDI_BC_BIFURCATION_SELECT;
2294 DRM_DEBUG_KMS("disabling fdi C rx\n");
2295 I915_WRITE(SOUTH_CHICKEN1, temp);
2296 }
2297}
2298
8db9d77b
ZW		 2299/* The FDI link training functions for ILK/Ibexpeak. */
2300static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2301{
2302 struct drm_device *dev = crtc->dev;
2303 struct drm_i915_private *dev_priv = dev->dev_private;
2304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2305 int pipe = intel_crtc->pipe;
0fc932b8 2306 int plane = intel_crtc->plane;
5eddb70b 2307 u32 reg, temp, tries;
8db9d77b 2308
0fc932b8
JB		 2309 /* FDI needs bits from pipe & plane first */
2310 assert_pipe_enabled(dev_priv, pipe);
2311 assert_plane_enabled(dev_priv, plane);
2312
e1a44743
AJ		 2313 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2314 for train result */
5eddb70b
CW		 2315 reg = FDI_RX_IMR(pipe);
2316 temp = I915_READ(reg);
e1a44743
AJ		 2317 temp &= ~FDI_RX_SYMBOL_LOCK;
2318 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2319 I915_WRITE(reg, temp);
2320 I915_READ(reg);
e1a44743
AJ		 2321 udelay(150);
2322
8db9d77b 2323 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2324 reg = FDI_TX_CTL(pipe);
2325 temp = I915_READ(reg);
627eb5a3
DV		 2326 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2327 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2328 temp &= ~FDI_LINK_TRAIN_NONE;
2329 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2330 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2331
5eddb70b
CW		 2332 reg = FDI_RX_CTL(pipe);
2333 temp = I915_READ(reg);
8db9d77b
ZW		 2334 temp &= ~FDI_LINK_TRAIN_NONE;
2335 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2336 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2337
2338 POSTING_READ(reg);
8db9d77b
ZW		 2339 udelay(150);
2340
5b2adf89 2341 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2342 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2344 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2345
5eddb70b 2346 reg = FDI_RX_IIR(pipe);
e1a44743 2347 for (tries = 0; tries < 5; tries++) {
5eddb70b 2348 temp = I915_READ(reg);
8db9d77b
ZW		 2349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2350
2351 if ((temp & FDI_RX_BIT_LOCK)) {
2352 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2353 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2354 break;
2355 }
8db9d77b 2356 }
e1a44743 2357 if (tries == 5)
5eddb70b 2358 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2359
2360 /* Train 2 */
5eddb70b
CW		 2361 reg = FDI_TX_CTL(pipe);
2362 temp = I915_READ(reg);
8db9d77b
ZW		 2363 temp &= ~FDI_LINK_TRAIN_NONE;
2364 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2365 I915_WRITE(reg, temp);
8db9d77b 2366
5eddb70b
CW		 2367 reg = FDI_RX_CTL(pipe);
2368 temp = I915_READ(reg);
8db9d77b
ZW		 2369 temp &= ~FDI_LINK_TRAIN_NONE;
2370 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2371 I915_WRITE(reg, temp);
8db9d77b 2372
5eddb70b
CW		 2373 POSTING_READ(reg);
2374 udelay(150);
8db9d77b 2375
5eddb70b 2376 reg = FDI_RX_IIR(pipe);
e1a44743 2377 for (tries = 0; tries < 5; tries++) {
5eddb70b 2378 temp = I915_READ(reg);
8db9d77b
ZW		 2379 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2382 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2383 DRM_DEBUG_KMS("FDI train 2 done.\n");
2384 break;
2385 }
8db9d77b 2386 }
e1a44743 2387 if (tries == 5)
5eddb70b 2388 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2389
2390 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2391
8db9d77b
ZW		 2392}
2393
0206e353 2394static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2395 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2396 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2397 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2398 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2399};
2400
2401/* The FDI link training functions for SNB/Cougarpoint. */
2402static void gen6_fdi_link_train(struct drm_crtc *crtc)
2403{
2404 struct drm_device *dev = crtc->dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407 int pipe = intel_crtc->pipe;
fa37d39e 2408 u32 reg, temp, i, retry;
8db9d77b 2409
e1a44743
AJ		 2410 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411 for train result */
5eddb70b
CW		 2412 reg = FDI_RX_IMR(pipe);
2413 temp = I915_READ(reg);
e1a44743
AJ		 2414 temp &= ~FDI_RX_SYMBOL_LOCK;
2415 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2416 I915_WRITE(reg, temp);
2417
2418 POSTING_READ(reg);
e1a44743
AJ		 2419 udelay(150);
2420
8db9d77b 2421 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
627eb5a3
DV		 2424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
2428 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2429 /* SNB-B */
2430 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2431 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2432
d74cf324
DV		 2433 I915_WRITE(FDI_RX_MISC(pipe),
2434 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 if (HAS_PCH_CPT(dev)) {
2439 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_PATTERN_1;
2444 }
5eddb70b
CW		 2445 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447 POSTING_READ(reg);
8db9d77b
ZW		 2448 udelay(150);
2449
0206e353 2450 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2451 reg = FDI_TX_CTL(pipe);
2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2455 I915_WRITE(reg, temp);
2456
2457 POSTING_READ(reg);
8db9d77b
ZW		 2458 udelay(500);
2459
fa37d39e
SP		 2460 for (retry = 0; retry < 5; retry++) {
2461 reg = FDI_RX_IIR(pipe);
2462 temp = I915_READ(reg);
2463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464 if (temp & FDI_RX_BIT_LOCK) {
2465 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2466 DRM_DEBUG_KMS("FDI train 1 done.\n");
2467 break;
2468 }
2469 udelay(50);
8db9d77b 2470 }
fa37d39e
SP		 2471 if (retry < 5)
2472 break;
8db9d77b
ZW		 2473 }
2474 if (i == 4)
5eddb70b 2475 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2476
2477 /* Train 2 */
5eddb70b
CW		 2478 reg = FDI_TX_CTL(pipe);
2479 temp = I915_READ(reg);
8db9d77b
ZW		 2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_2;
2482 if (IS_GEN6(dev)) {
2483 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484 /* SNB-B */
2485 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2486 }
5eddb70b 2487 I915_WRITE(reg, temp);
8db9d77b 2488
5eddb70b
CW		 2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 if (HAS_PCH_CPT(dev)) {
2492 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2493 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2494 } else {
2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_2;
2497 }
5eddb70b
CW		 2498 I915_WRITE(reg, temp);
2499
2500 POSTING_READ(reg);
8db9d77b
ZW		 2501 udelay(150);
2502
0206e353 2503 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2504 reg = FDI_TX_CTL(pipe);
2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2507 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2508 I915_WRITE(reg, temp);
2509
2510 POSTING_READ(reg);
8db9d77b
ZW		 2511 udelay(500);
2512
fa37d39e
SP		 2513 for (retry = 0; retry < 5; retry++) {
2514 reg = FDI_RX_IIR(pipe);
2515 temp = I915_READ(reg);
2516 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517 if (temp & FDI_RX_SYMBOL_LOCK) {
2518 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2519 DRM_DEBUG_KMS("FDI train 2 done.\n");
2520 break;
2521 }
2522 udelay(50);
8db9d77b 2523 }
fa37d39e
SP		 2524 if (retry < 5)
2525 break;
8db9d77b
ZW		 2526 }
2527 if (i == 4)
5eddb70b 2528 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2529
2530 DRM_DEBUG_KMS("FDI train done.\n");
2531}
2532
357555c0
JB		 2533/* Manual link training for Ivy Bridge A0 parts */
2534static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2535{
2536 struct drm_device *dev = crtc->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539 int pipe = intel_crtc->pipe;
2540 u32 reg, temp, i;
2541
2542 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543 for train result */
2544 reg = FDI_RX_IMR(pipe);
2545 temp = I915_READ(reg);
2546 temp &= ~FDI_RX_SYMBOL_LOCK;
2547 temp &= ~FDI_RX_BIT_LOCK;
2548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
2551 udelay(150);
2552
01a415fd
DV		 2553 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2554 I915_READ(FDI_RX_IIR(pipe)));
2555
357555c0
JB		 2556 /* enable CPU FDI TX and PCH FDI RX */
2557 reg = FDI_TX_CTL(pipe);
2558 temp = I915_READ(reg);
627eb5a3
DV		 2559 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2560 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2561 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2562 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2563 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2565 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2566 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2567
d74cf324
DV		 2568 I915_WRITE(FDI_RX_MISC(pipe),
2569 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2570
357555c0
JB		 2571 reg = FDI_RX_CTL(pipe);
2572 temp = I915_READ(reg);
2573 temp &= ~FDI_LINK_TRAIN_AUTO;
2574 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2576 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2577 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2578
2579 POSTING_READ(reg);
2580 udelay(150);
2581
0206e353 2582 for (i = 0; i < 4; i++) {
357555c0
JB		 2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 temp |= snb_b_fdi_train_param[i];
2587 I915_WRITE(reg, temp);
2588
2589 POSTING_READ(reg);
2590 udelay(500);
2591
2592 reg = FDI_RX_IIR(pipe);
2593 temp = I915_READ(reg);
2594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596 if (temp & FDI_RX_BIT_LOCK ||
2597 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2598 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2599 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2600 break;
2601 }
2602 }
2603 if (i == 4)
2604 DRM_ERROR("FDI train 1 fail!\n");
2605
2606 /* Train 2 */
2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2610 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2613 I915_WRITE(reg, temp);
2614
2615 reg = FDI_RX_CTL(pipe);
2616 temp = I915_READ(reg);
2617 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2619 I915_WRITE(reg, temp);
2620
2621 POSTING_READ(reg);
2622 udelay(150);
2623
0206e353 2624 for (i = 0; i < 4; i++) {
357555c0
JB		 2625 reg = FDI_TX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628 temp |= snb_b_fdi_train_param[i];
2629 I915_WRITE(reg, temp);
2630
2631 POSTING_READ(reg);
2632 udelay(500);
2633
2634 reg = FDI_RX_IIR(pipe);
2635 temp = I915_READ(reg);
2636 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2637
2638 if (temp & FDI_RX_SYMBOL_LOCK) {
2639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2640 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2641 break;
2642 }
2643 }
2644 if (i == 4)
2645 DRM_ERROR("FDI train 2 fail!\n");
2646
2647 DRM_DEBUG_KMS("FDI train done.\n");
2648}
2649
88cefb6c 2650static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2651{
88cefb6c 2652 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2653 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2654 int pipe = intel_crtc->pipe;
5eddb70b 2655 u32 reg, temp;
79e53945 2656
c64e311e 2657
c98e9dcf 2658 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2659 reg = FDI_RX_CTL(pipe);
2660 temp = I915_READ(reg);
627eb5a3
DV		 2661 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2662 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2663 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2664 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2665
2666 POSTING_READ(reg);
c98e9dcf
JB		 2667 udelay(200);
2668
2669 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2670 temp = I915_READ(reg);
2671 I915_WRITE(reg, temp | FDI_PCDCLK);
2672
2673 POSTING_READ(reg);
c98e9dcf
JB		 2674 udelay(200);
2675
20749730
PZ		 2676 /* Enable CPU FDI TX PLL, always on for Ironlake */
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2680 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2681
20749730
PZ		 2682 POSTING_READ(reg);
2683 udelay(100);
6be4a607 2684 }
0e23b99d
JB		 2685}
2686
88cefb6c
DV		 2687static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2688{
2689 struct drm_device *dev = intel_crtc->base.dev;
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 int pipe = intel_crtc->pipe;
2692 u32 reg, temp;
2693
2694 /* Switch from PCDclk to Rawclk */
2695 reg = FDI_RX_CTL(pipe);
2696 temp = I915_READ(reg);
2697 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2698
2699 /* Disable CPU FDI TX PLL */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2703
2704 POSTING_READ(reg);
2705 udelay(100);
2706
2707 reg = FDI_RX_CTL(pipe);
2708 temp = I915_READ(reg);
2709 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2710
2711 /* Wait for the clocks to turn off. */
2712 POSTING_READ(reg);
2713 udelay(100);
2714}
2715
0fc932b8
JB		 2716static void ironlake_fdi_disable(struct drm_crtc *crtc)
2717{
2718 struct drm_device *dev = crtc->dev;
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2721 int pipe = intel_crtc->pipe;
2722 u32 reg, temp;
2723
2724 /* disable CPU FDI tx and PCH FDI rx */
2725 reg = FDI_TX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2728 POSTING_READ(reg);
2729
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~(0x7 << 16);
dfd07d72 2733 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2734 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2735
2736 POSTING_READ(reg);
2737 udelay(100);
2738
2739 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2740 if (HAS_PCH_IBX(dev)) {
2741 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2742 }
0fc932b8
JB		 2743
2744 /* still set train pattern 1 */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_LINK_TRAIN_NONE;
2748 temp |= FDI_LINK_TRAIN_PATTERN_1;
2749 I915_WRITE(reg, temp);
2750
2751 reg = FDI_RX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 if (HAS_PCH_CPT(dev)) {
2754 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2755 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2756 } else {
2757 temp &= ~FDI_LINK_TRAIN_NONE;
2758 temp |= FDI_LINK_TRAIN_PATTERN_1;
2759 }
2760 /* BPC in FDI rx is consistent with that in PIPECONF */
2761 temp &= ~(0x07 << 16);
dfd07d72 2762 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2763 I915_WRITE(reg, temp);
2764
2765 POSTING_READ(reg);
2766 udelay(100);
2767}
2768
5bb61643
CW		 2769static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2770{
2771 struct drm_device *dev = crtc->dev;
2772 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2774 unsigned long flags;
2775 bool pending;
2776
10d83730
VS		 2777 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2778 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2779 return false;
2780
2781 spin_lock_irqsave(&dev->event_lock, flags);
2782 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2783 spin_unlock_irqrestore(&dev->event_lock, flags);
2784
2785 return pending;
2786}
2787
e6c3a2a6
CW		 2788static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2789{
0f91128d 2790 struct drm_device *dev = crtc->dev;
5bb61643 2791 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2792
2793 if (crtc->fb == NULL)
2794 return;
2795
2c10d571
DV		 2796 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2797
5bb61643
CW		 2798 wait_event(dev_priv->pending_flip_queue,
2799 !intel_crtc_has_pending_flip(crtc));
2800
0f91128d
CW		 2801 mutex_lock(&dev->struct_mutex);
2802 intel_finish_fb(crtc->fb);
2803 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2804}
2805
e615efe4
ED		 2806/* Program iCLKIP clock to the desired frequency */
2807static void lpt_program_iclkip(struct drm_crtc *crtc)
2808{
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2812 u32 temp;
2813
09153000
DV		 2814 mutex_lock(&dev_priv->dpio_lock);
2815
e615efe4
ED		 2816 /* It is necessary to ungate the pixclk gate prior to programming
2817 * the divisors, and gate it back when it is done.
2818 */
2819 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2820
2821 /* Disable SSCCTL */
2822 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2823 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2824 SBI_SSCCTL_DISABLE,
2825 SBI_ICLK);
e615efe4
ED		 2826
2827 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2828 if (crtc->mode.clock == 20000) {
2829 auxdiv = 1;
2830 divsel = 0x41;
2831 phaseinc = 0x20;
2832 } else {
2833 /* The iCLK virtual clock root frequency is in MHz,
2834 * but the crtc->mode.clock in in KHz. To get the divisors,
2835 * it is necessary to divide one by another, so we
2836 * convert the virtual clock precision to KHz here for higher
2837 * precision.
2838 */
2839 u32 iclk_virtual_root_freq = 172800 * 1000;
2840 u32 iclk_pi_range = 64;
2841 u32 desired_divisor, msb_divisor_value, pi_value;
2842
2843 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2844 msb_divisor_value = desired_divisor / iclk_pi_range;
2845 pi_value = desired_divisor % iclk_pi_range;
2846
2847 auxdiv = 0;
2848 divsel = msb_divisor_value - 2;
2849 phaseinc = pi_value;
2850 }
2851
2852 /* This should not happen with any sane values */
2853 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2854 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2855 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2856 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2857
2858 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2859 crtc->mode.clock,
2860 auxdiv,
2861 divsel,
2862 phasedir,
2863 phaseinc);
2864
2865 /* Program SSCDIVINTPHASE6 */
988d6ee8 2866 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2867 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2868 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2869 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2870 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2871 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2872 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2873 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2874
2875 /* Program SSCAUXDIV */
988d6ee8 2876 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2877 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2878 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2879 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2880
2881 /* Enable modulator and associated divider */
988d6ee8 2882 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2883 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2884 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2885
2886 /* Wait for initialization time */
2887 udelay(24);
2888
2889 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2890
2891 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2892}
2893
275f01b2
DV		 2894static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2895 enum pipe pch_transcoder)
2896{
2897 struct drm_device *dev = crtc->base.dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2900
2901 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2902 I915_READ(HTOTAL(cpu_transcoder)));
2903 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2904 I915_READ(HBLANK(cpu_transcoder)));
2905 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2906 I915_READ(HSYNC(cpu_transcoder)));
2907
2908 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2909 I915_READ(VTOTAL(cpu_transcoder)));
2910 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2911 I915_READ(VBLANK(cpu_transcoder)));
2912 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2913 I915_READ(VSYNC(cpu_transcoder)));
2914 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2915 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2916}
2917
f67a559d
JB		 2918/*
2919 * Enable PCH resources required for PCH ports:
2920 * - PCH PLLs
2921 * - FDI training & RX/TX
2922 * - update transcoder timings
2923 * - DP transcoding bits
2924 * - transcoder
2925 */
2926static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2927{
2928 struct drm_device *dev = crtc->dev;
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931 int pipe = intel_crtc->pipe;
ee7b9f93 2932 u32 reg, temp;
2c07245f 2933
ab9412ba 2934 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2935
cd986abb
DV		 2936 /* Write the TU size bits before fdi link training, so that error
2937 * detection works. */
2938 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2939 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2940
c98e9dcf 2941 /* For PCH output, training FDI link */
674cf967 2942 dev_priv->display.fdi_link_train(crtc);
2c07245f 2943
572deb37
DV		 2944 /* XXX: pch pll's can be enabled any time before we enable the PCH
2945 * transcoder, and we actually should do this to not upset any PCH
2946 * transcoder that already use the clock when we share it.
2947 *
2948 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2949 * unconditionally resets the pll - we need that to have the right LVDS
2950 * enable sequence. */
b6b4e185 2951 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2952
303b81e0 2953 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2954 u32 sel;
4b645f14 2955
c98e9dcf 2956 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2957 switch (pipe) {
2958 default:
2959 case 0:
2960 temp |= TRANSA_DPLL_ENABLE;
2961 sel = TRANSA_DPLLB_SEL;
2962 break;
2963 case 1:
2964 temp |= TRANSB_DPLL_ENABLE;
2965 sel = TRANSB_DPLLB_SEL;
2966 break;
2967 case 2:
2968 temp |= TRANSC_DPLL_ENABLE;
2969 sel = TRANSC_DPLLB_SEL;
2970 break;
d64311ab 2971 }
ee7b9f93
JB		 2972 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2973 temp |= sel;
2974 else
2975 temp &= ~sel;
c98e9dcf 2976 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2977 }
5eddb70b 2978
d9b6cb56
JB		 2979 /* set transcoder timing, panel must allow it */
2980 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2981 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2982
303b81e0 2983 intel_fdi_normal_train(crtc);
5e84e1a4 2984
c98e9dcf
JB		 2985 /* For PCH DP, enable TRANS_DP_CTL */
2986 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2987 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2988 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2989 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2990 reg = TRANS_DP_CTL(pipe);
2991 temp = I915_READ(reg);
2992 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2993 TRANS_DP_SYNC_MASK |
2994 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2995 temp |= (TRANS_DP_OUTPUT_ENABLE |
2996 TRANS_DP_ENH_FRAMING);
9325c9f0 2997 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2998
2999 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3000 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3001 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3002 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3003
3004 switch (intel_trans_dp_port_sel(crtc)) {
3005 case PCH_DP_B:
5eddb70b 3006 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3007 break;
3008 case PCH_DP_C:
5eddb70b 3009 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3010 break;
3011 case PCH_DP_D:
5eddb70b 3012 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3013 break;
3014 default:
e95d41e1 3015 BUG();
32f9d658 3016 }
2c07245f 3017
5eddb70b 3018 I915_WRITE(reg, temp);
6be4a607 3019 }
b52eb4dc 3020
b8a4f404 3021 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3022}
3023
1507e5bd
PZ		 3024static void lpt_pch_enable(struct drm_crtc *crtc)
3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3029 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3030
ab9412ba 3031 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3032
8c52b5e8 3033 lpt_program_iclkip(crtc);
1507e5bd 3034
0540e488 3035 /* Set transcoder timing. */
275f01b2 3036 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3037
937bb610 3038 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3039}
3040
ee7b9f93
JB		 3041static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3042{
3043 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3044
3045 if (pll == NULL)
3046 return;
3047
3048 if (pll->refcount == 0) {
3049 WARN(1, "bad PCH PLL refcount\n");
3050 return;
3051 }
3052
3053 --pll->refcount;
3054 intel_crtc->pch_pll = NULL;
3055}
3056
3057static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3058{
3059 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3060 struct intel_pch_pll *pll;
3061 int i;
3062
3063 pll = intel_crtc->pch_pll;
3064 if (pll) {
3065 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3066 intel_crtc->base.base.id, pll->pll_reg);
3067 goto prepare;
3068 }
3069
98b6bd99
DV		 3070 if (HAS_PCH_IBX(dev_priv->dev)) {
3071 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3072 i = intel_crtc->pipe;
3073 pll = &dev_priv->pch_plls[i];
3074
3075 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3076 intel_crtc->base.base.id, pll->pll_reg);
3077
3078 goto found;
3079 }
3080
ee7b9f93
JB		 3081 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3082 pll = &dev_priv->pch_plls[i];
3083
3084 /* Only want to check enabled timings first */
3085 if (pll->refcount == 0)
3086 continue;
3087
3088 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3089 fp == I915_READ(pll->fp0_reg)) {
3090 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3091 intel_crtc->base.base.id,
3092 pll->pll_reg, pll->refcount, pll->active);
3093
3094 goto found;
3095 }
3096 }
3097
3098 /* Ok no matching timings, maybe there's a free one? */
3099 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3100 pll = &dev_priv->pch_plls[i];
3101 if (pll->refcount == 0) {
3102 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3103 intel_crtc->base.base.id, pll->pll_reg);
3104 goto found;
3105 }
3106 }
3107
3108 return NULL;
3109
3110found:
3111 intel_crtc->pch_pll = pll;
3112 pll->refcount++;
84f44ce7 3113 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3114prepare: /* separate function? */
3115 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3116
e04c7350
CW		 3117 /* Wait for the clocks to stabilize before rewriting the regs */
3118 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3119 POSTING_READ(pll->pll_reg);
3120 udelay(150);
e04c7350
CW		 3121
3122 I915_WRITE(pll->fp0_reg, fp);
3123 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3124 pll->on = false;
3125 return pll;
3126}
3127
a1520318 3128static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3129{
3130 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3131 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3132 u32 temp;
3133
3134 temp = I915_READ(dslreg);
3135 udelay(500);
3136 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3137 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3138 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3139 }
3140}
3141
b074cec8
JB		 3142static void ironlake_pfit_enable(struct intel_crtc *crtc)
3143{
3144 struct drm_device *dev = crtc->base.dev;
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 int pipe = crtc->pipe;
3147
0ef37f3f 3148 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3149 /* Force use of hard-coded filter coefficients
3150 * as some pre-programmed values are broken,
3151 * e.g. x201.
3152 */
3153 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3154 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3155 PF_PIPE_SEL_IVB(pipe));
3156 else
3157 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3158 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3159 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3160 }
3161}
3162
f67a559d
JB		 3163static void ironlake_crtc_enable(struct drm_crtc *crtc)
3164{
3165 struct drm_device *dev = crtc->dev;
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3168 struct intel_encoder *encoder;
f67a559d
JB		 3169 int pipe = intel_crtc->pipe;
3170 int plane = intel_crtc->plane;
3171 u32 temp;
f67a559d 3172
08a48469
DV		 3173 WARN_ON(!crtc->enabled);
3174
f67a559d
JB		 3175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
8664281b
PZ		 3179
3180 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3181 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3182
f67a559d
JB		 3183 intel_update_watermarks(dev);
3184
3185 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3186 temp = I915_READ(PCH_LVDS);
3187 if ((temp & LVDS_PORT_EN) == 0)
3188 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3189 }
3190
f67a559d 3191
5bfe2ac0 3192 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3193 /* Note: FDI PLL enabling _must_ be done before we enable the
3194 * cpu pipes, hence this is separate from all the other fdi/pch
3195 * enabling. */
88cefb6c 3196 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3197 } else {
3198 assert_fdi_tx_disabled(dev_priv, pipe);
3199 assert_fdi_rx_disabled(dev_priv, pipe);
3200 }
f67a559d 3201
bf49ec8c
DV		 3202 for_each_encoder_on_crtc(dev, crtc, encoder)
3203 if (encoder->pre_enable)
3204 encoder->pre_enable(encoder);
f67a559d
JB		 3205
3206 /* Enable panel fitting for LVDS */
b074cec8 3207 ironlake_pfit_enable(intel_crtc);
f67a559d 3208
9c54c0dd
JB		 3209 /*
3210 * On ILK+ LUT must be loaded before the pipe is running but with
3211 * clocks enabled
3212 */
3213 intel_crtc_load_lut(crtc);
3214
5bfe2ac0
DV		 3215 intel_enable_pipe(dev_priv, pipe,
3216 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3217 intel_enable_plane(dev_priv, plane, pipe);
3218
5bfe2ac0 3219 if (intel_crtc->config.has_pch_encoder)
f67a559d 3220 ironlake_pch_enable(crtc);
c98e9dcf 3221
d1ebd816 3222 mutex_lock(&dev->struct_mutex);
bed4a673 3223 intel_update_fbc(dev);
d1ebd816
BW		 3224 mutex_unlock(&dev->struct_mutex);
3225
6b383a7f 3226 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3227
fa5c73b1
DV		 3228 for_each_encoder_on_crtc(dev, crtc, encoder)
3229 encoder->enable(encoder);
61b77ddd
DV		 3230
3231 if (HAS_PCH_CPT(dev))
a1520318 3232 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3233
3234 /*
3235 * There seems to be a race in PCH platform hw (at least on some
3236 * outputs) where an enabled pipe still completes any pageflip right
3237 * away (as if the pipe is off) instead of waiting for vblank. As soon
3238 * as the first vblank happend, everything works as expected. Hence just
3239 * wait for one vblank before returning to avoid strange things
3240 * happening.
3241 */
3242 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3243}
3244
4f771f10
PZ		 3245static void haswell_crtc_enable(struct drm_crtc *crtc)
3246{
3247 struct drm_device *dev = crtc->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250 struct intel_encoder *encoder;
3251 int pipe = intel_crtc->pipe;
3252 int plane = intel_crtc->plane;
4f771f10
PZ		 3253
3254 WARN_ON(!crtc->enabled);
3255
3256 if (intel_crtc->active)
3257 return;
3258
3259 intel_crtc->active = true;
8664281b
PZ		 3260
3261 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3262 if (intel_crtc->config.has_pch_encoder)
3263 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3264
4f771f10
PZ		 3265 intel_update_watermarks(dev);
3266
5bfe2ac0 3267 if (intel_crtc->config.has_pch_encoder)
04945641 3268 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3269
3270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 if (encoder->pre_enable)
3272 encoder->pre_enable(encoder);
3273
1f544388 3274 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3275
1f544388 3276 /* Enable panel fitting for eDP */
b074cec8 3277 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3278
3279 /*
3280 * On ILK+ LUT must be loaded before the pipe is running but with
3281 * clocks enabled
3282 */
3283 intel_crtc_load_lut(crtc);
3284
1f544388 3285 intel_ddi_set_pipe_settings(crtc);
8228c251 3286 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3287
5bfe2ac0
DV		 3288 intel_enable_pipe(dev_priv, pipe,
3289 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3290 intel_enable_plane(dev_priv, plane, pipe);
3291
5bfe2ac0 3292 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3293 lpt_pch_enable(crtc);
4f771f10
PZ		 3294
3295 mutex_lock(&dev->struct_mutex);
3296 intel_update_fbc(dev);
3297 mutex_unlock(&dev->struct_mutex);
3298
3299 intel_crtc_update_cursor(crtc, true);
3300
3301 for_each_encoder_on_crtc(dev, crtc, encoder)
3302 encoder->enable(encoder);
3303
4f771f10
PZ		 3304 /*
3305 * There seems to be a race in PCH platform hw (at least on some
3306 * outputs) where an enabled pipe still completes any pageflip right
3307 * away (as if the pipe is off) instead of waiting for vblank. As soon
3308 * as the first vblank happend, everything works as expected. Hence just
3309 * wait for one vblank before returning to avoid strange things
3310 * happening.
3311 */
3312 intel_wait_for_vblank(dev, intel_crtc->pipe);
3313}
3314
3f8dce3a
DV		 3315static void ironlake_pfit_disable(struct intel_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->base.dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 int pipe = crtc->pipe;
3320
3321 /* To avoid upsetting the power well on haswell only disable the pfit if
3322 * it's in use. The hw state code will make sure we get this right. */
3323 if (crtc->config.pch_pfit.size) {
3324 I915_WRITE(PF_CTL(pipe), 0);
3325 I915_WRITE(PF_WIN_POS(pipe), 0);
3326 I915_WRITE(PF_WIN_SZ(pipe), 0);
3327 }
3328}
3329
6be4a607
JB		 3330static void ironlake_crtc_disable(struct drm_crtc *crtc)
3331{
3332 struct drm_device *dev = crtc->dev;
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3335 struct intel_encoder *encoder;
6be4a607
JB		 3336 int pipe = intel_crtc->pipe;
3337 int plane = intel_crtc->plane;
5eddb70b 3338 u32 reg, temp;
b52eb4dc 3339
ef9c3aee 3340
f7abfe8b
CW		 3341 if (!intel_crtc->active)
3342 return;
3343
ea9d758d
DV		 3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 encoder->disable(encoder);
3346
e6c3a2a6 3347 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3348 drm_vblank_off(dev, pipe);
6b383a7f 3349 intel_crtc_update_cursor(crtc, false);
5eddb70b 3350
b24e7179 3351 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3352
973d04f9
CW		 3353 if (dev_priv->cfb_plane == plane)
3354 intel_disable_fbc(dev);
2c07245f 3355
8664281b 3356 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3357 intel_disable_pipe(dev_priv, pipe);
32f9d658 3358
3f8dce3a 3359 ironlake_pfit_disable(intel_crtc);
2c07245f 3360
bf49ec8c
DV		 3361 for_each_encoder_on_crtc(dev, crtc, encoder)
3362 if (encoder->post_disable)
3363 encoder->post_disable(encoder);
2c07245f 3364
0fc932b8 3365 ironlake_fdi_disable(crtc);
249c0e64 3366
b8a4f404 3367 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3368 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3369
6be4a607
JB		 3370 if (HAS_PCH_CPT(dev)) {
3371 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3372 reg = TRANS_DP_CTL(pipe);
3373 temp = I915_READ(reg);
3374 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3375 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3376 I915_WRITE(reg, temp);
6be4a607
JB		 3377
3378 /* disable DPLL_SEL */
3379 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3380 switch (pipe) {
3381 case 0:
d64311ab 3382 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3383 break;
3384 case 1:
6be4a607 3385 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3386 break;
3387 case 2:
4b645f14 3388 /* C shares PLL A or B */
d64311ab 3389 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3390 break;
3391 default:
3392 BUG(); /* wtf */
3393 }
6be4a607 3394 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3395 }
e3421a18 3396
6be4a607 3397 /* disable PCH DPLL */
ee7b9f93 3398 intel_disable_pch_pll(intel_crtc);
8db9d77b 3399
88cefb6c 3400 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3401
f7abfe8b 3402 intel_crtc->active = false;
6b383a7f 3403 intel_update_watermarks(dev);
d1ebd816
BW		 3404
3405 mutex_lock(&dev->struct_mutex);
6b383a7f 3406 intel_update_fbc(dev);
d1ebd816 3407 mutex_unlock(&dev->struct_mutex);
6be4a607 3408}
1b3c7a47 3409
4f771f10 3410static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3411{
4f771f10
PZ		 3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3415 struct intel_encoder *encoder;
3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
3b117c8f 3418 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3419
4f771f10
PZ		 3420 if (!intel_crtc->active)
3421 return;
3422
3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 encoder->disable(encoder);
3425
3426 intel_crtc_wait_for_pending_flips(crtc);
3427 drm_vblank_off(dev, pipe);
3428 intel_crtc_update_cursor(crtc, false);
3429
891348b2 3430 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3431 if (dev_priv->cfb_plane == plane)
3432 intel_disable_fbc(dev);
3433
891348b2
RV		 3434 intel_disable_plane(dev_priv, plane, pipe);
3435
8664281b
PZ		 3436 if (intel_crtc->config.has_pch_encoder)
3437 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3438 intel_disable_pipe(dev_priv, pipe);
3439
ad80a810 3440 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3441
3f8dce3a 3442 ironlake_pfit_disable(intel_crtc);
4f771f10 3443
1f544388 3444 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3445
3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 if (encoder->post_disable)
3448 encoder->post_disable(encoder);
3449
88adfff1 3450 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3451 lpt_disable_pch_transcoder(dev_priv);
8664281b 3452 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3453 intel_ddi_fdi_disable(crtc);
83616634 3454 }
4f771f10
PZ		 3455
3456 intel_crtc->active = false;
3457 intel_update_watermarks(dev);
3458
3459 mutex_lock(&dev->struct_mutex);
3460 intel_update_fbc(dev);
3461 mutex_unlock(&dev->struct_mutex);
3462}
3463
ee7b9f93
JB		 3464static void ironlake_crtc_off(struct drm_crtc *crtc)
3465{
3466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467 intel_put_pch_pll(intel_crtc);
3468}
3469
6441ab5f
PZ		 3470static void haswell_crtc_off(struct drm_crtc *crtc)
3471{
3472 intel_ddi_put_crtc_pll(crtc);
3473}
3474
02e792fb
DV		 3475static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3476{
02e792fb 3477 if (!enable && intel_crtc->overlay) {
23f09ce3 3478 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3479 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3480
23f09ce3 3481 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3482 dev_priv->mm.interruptible = false;
3483 (void) intel_overlay_switch_off(intel_crtc->overlay);
3484 dev_priv->mm.interruptible = true;
23f09ce3 3485 mutex_unlock(&dev->struct_mutex);
02e792fb 3486 }
02e792fb 3487
5dcdbcb0
CW		 3488 /* Let userspace switch the overlay on again. In most cases userspace
3489 * has to recompute where to put it anyway.
3490 */
02e792fb
DV		 3491}
3492
61bc95c1
EE		 3493/**
3494 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3495 * cursor plane briefly if not already running after enabling the display
3496 * plane.
3497 * This workaround avoids occasional blank screens when self refresh is
3498 * enabled.
3499 */
3500static void
3501g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3502{
3503 u32 cntl = I915_READ(CURCNTR(pipe));
3504
3505 if ((cntl & CURSOR_MODE) == 0) {
3506 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3507
3508 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3509 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3510 intel_wait_for_vblank(dev_priv->dev, pipe);
3511 I915_WRITE(CURCNTR(pipe), cntl);
3512 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3513 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3514 }
3515}
3516
2dd24552
JB		 3517static void i9xx_pfit_enable(struct intel_crtc *crtc)
3518{
3519 struct drm_device *dev = crtc->base.dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521 struct intel_crtc_config *pipe_config = &crtc->config;
3522
328d8e82 3523 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3524 return;
3525
3526 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3527 assert_pipe_disabled(dev_priv, crtc->pipe);
3528
3529 /*
3530 * Enable automatic panel scaling so that non-native modes
3531 * fill the screen. The panel fitter should only be
3532 * adjusted whilst the pipe is disabled, according to
3533 * register description and PRM.
3534 */
3535 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3536 pipe_config->gmch_pfit.control,
3537 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3538
b074cec8
JB		 3539 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3540 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3541
3542 /* Border color in case we don't scale up to the full screen. Black by
3543 * default, change to something else for debugging. */
3544 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3545}
3546
89b667f8
JB		 3547static void valleyview_crtc_enable(struct drm_crtc *crtc)
3548{
3549 struct drm_device *dev = crtc->dev;
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552 struct intel_encoder *encoder;
3553 int pipe = intel_crtc->pipe;
3554 int plane = intel_crtc->plane;
3555
3556 WARN_ON(!crtc->enabled);
3557
3558 if (intel_crtc->active)
3559 return;
3560
3561 intel_crtc->active = true;
3562 intel_update_watermarks(dev);
3563
3564 mutex_lock(&dev_priv->dpio_lock);
3565
3566 for_each_encoder_on_crtc(dev, crtc, encoder)
3567 if (encoder->pre_pll_enable)
3568 encoder->pre_pll_enable(encoder);
3569
3570 intel_enable_pll(dev_priv, pipe);
3571
3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 if (encoder->pre_enable)
3574 encoder->pre_enable(encoder);
3575
3576 /* VLV wants encoder enabling _before_ the pipe is up. */
3577 for_each_encoder_on_crtc(dev, crtc, encoder)
3578 encoder->enable(encoder);
3579
2dd24552
JB		 3580 /* Enable panel fitting for eDP */
3581 i9xx_pfit_enable(intel_crtc);
3582
89b667f8
JB		 3583 intel_enable_pipe(dev_priv, pipe, false);
3584 intel_enable_plane(dev_priv, plane, pipe);
3585
3586 intel_crtc_load_lut(crtc);
3587 intel_update_fbc(dev);
3588
3589 /* Give the overlay scaler a chance to enable if it's on this pipe */
3590 intel_crtc_dpms_overlay(intel_crtc, true);
3591 intel_crtc_update_cursor(crtc, true);
3592
3593 mutex_unlock(&dev_priv->dpio_lock);
3594}
3595
0b8765c6 3596static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3597{
3598 struct drm_device *dev = crtc->dev;
79e53945
JB		 3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3601 struct intel_encoder *encoder;
79e53945 3602 int pipe = intel_crtc->pipe;
80824003 3603 int plane = intel_crtc->plane;
79e53945 3604
08a48469
DV		 3605 WARN_ON(!crtc->enabled);
3606
f7abfe8b
CW		 3607 if (intel_crtc->active)
3608 return;
3609
3610 intel_crtc->active = true;
6b383a7f
CW		 3611 intel_update_watermarks(dev);
3612
63d7bbe9 3613 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3614
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 if (encoder->pre_enable)
3617 encoder->pre_enable(encoder);
3618
2dd24552
JB		 3619 /* Enable panel fitting for LVDS */
3620 i9xx_pfit_enable(intel_crtc);
3621
040484af 3622 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3623 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3624 if (IS_G4X(dev))
3625 g4x_fixup_plane(dev_priv, pipe);
79e53945 3626
0b8765c6 3627 intel_crtc_load_lut(crtc);
bed4a673 3628 intel_update_fbc(dev);
79e53945 3629
0b8765c6
JB		 3630 /* Give the overlay scaler a chance to enable if it's on this pipe */
3631 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3632 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3633
fa5c73b1
DV		 3634 for_each_encoder_on_crtc(dev, crtc, encoder)
3635 encoder->enable(encoder);
0b8765c6 3636}
79e53945 3637
87476d63
DV		 3638static void i9xx_pfit_disable(struct intel_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->base.dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3642
328d8e82
DV		 3643 if (!crtc->config.gmch_pfit.control)
3644 return;
87476d63 3645
328d8e82 3646 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3647
328d8e82
DV		 3648 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3649 I915_READ(PFIT_CONTROL));
3650 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3651}
3652
0b8765c6
JB		 3653static void i9xx_crtc_disable(struct drm_crtc *crtc)
3654{
3655 struct drm_device *dev = crtc->dev;
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3658 struct intel_encoder *encoder;
0b8765c6
JB		 3659 int pipe = intel_crtc->pipe;
3660 int plane = intel_crtc->plane;
ef9c3aee 3661
f7abfe8b
CW		 3662 if (!intel_crtc->active)
3663 return;
3664
ea9d758d
DV		 3665 for_each_encoder_on_crtc(dev, crtc, encoder)
3666 encoder->disable(encoder);
3667
0b8765c6 3668 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3669 intel_crtc_wait_for_pending_flips(crtc);
3670 drm_vblank_off(dev, pipe);
0b8765c6 3671 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3672 intel_crtc_update_cursor(crtc, false);
0b8765c6 3673
973d04f9
CW		 3674 if (dev_priv->cfb_plane == plane)
3675 intel_disable_fbc(dev);
79e53945 3676
b24e7179 3677 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3678 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3679
87476d63 3680 i9xx_pfit_disable(intel_crtc);
24a1f16d 3681
89b667f8
JB		 3682 for_each_encoder_on_crtc(dev, crtc, encoder)
3683 if (encoder->post_disable)
3684 encoder->post_disable(encoder);
3685
63d7bbe9 3686 intel_disable_pll(dev_priv, pipe);
0b8765c6 3687
f7abfe8b 3688 intel_crtc->active = false;
6b383a7f
CW		 3689 intel_update_fbc(dev);
3690 intel_update_watermarks(dev);
0b8765c6
JB		 3691}
3692
ee7b9f93
JB		 3693static void i9xx_crtc_off(struct drm_crtc *crtc)
3694{
3695}
3696
976f8a20
DV		 3697static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3698 bool enabled)
2c07245f
ZW		 3699{
3700 struct drm_device *dev = crtc->dev;
3701 struct drm_i915_master_private *master_priv;
3702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3703 int pipe = intel_crtc->pipe;
79e53945
JB		 3704
3705 if (!dev->primary->master)
3706 return;
3707
3708 master_priv = dev->primary->master->driver_priv;
3709 if (!master_priv->sarea_priv)
3710 return;
3711
79e53945
JB		 3712 switch (pipe) {
3713 case 0:
3714 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3715 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3716 break;
3717 case 1:
3718 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3719 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3720 break;
3721 default:
9db4a9c7 3722 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3723 break;
3724 }
79e53945
JB		 3725}
3726
976f8a20
DV		 3727/**
3728 * Sets the power management mode of the pipe and plane.
3729 */
3730void intel_crtc_update_dpms(struct drm_crtc *crtc)
3731{
3732 struct drm_device *dev = crtc->dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 struct intel_encoder *intel_encoder;
3735 bool enable = false;
3736
3737 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3738 enable |= intel_encoder->connectors_active;
3739
3740 if (enable)
3741 dev_priv->display.crtc_enable(crtc);
3742 else
3743 dev_priv->display.crtc_disable(crtc);
3744
3745 intel_crtc_update_sarea(crtc, enable);
3746}
3747
cdd59983
CW		 3748static void intel_crtc_disable(struct drm_crtc *crtc)
3749{
cdd59983 3750 struct drm_device *dev = crtc->dev;
976f8a20 3751 struct drm_connector *connector;
ee7b9f93 3752 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3754
976f8a20
DV		 3755 /* crtc should still be enabled when we disable it. */
3756 WARN_ON(!crtc->enabled);
3757
3758 dev_priv->display.crtc_disable(crtc);
c77bf565 3759 intel_crtc->eld_vld = false;
976f8a20 3760 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3761 dev_priv->display.off(crtc);
3762
931872fc
CW		 3763 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3764 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3765
3766 if (crtc->fb) {
3767 mutex_lock(&dev->struct_mutex);
1690e1eb 3768 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3769 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3770 crtc->fb = NULL;
3771 }
3772
3773 /* Update computed state. */
3774 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3775 if (!connector->encoder || !connector->encoder->crtc)
3776 continue;
3777
3778 if (connector->encoder->crtc != crtc)
3779 continue;
3780
3781 connector->dpms = DRM_MODE_DPMS_OFF;
3782 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3783 }
3784}
3785
a261b246 3786void intel_modeset_disable(struct drm_device *dev)
79e53945 3787{
a261b246
DV		 3788 struct drm_crtc *crtc;
3789
3790 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3791 if (crtc->enabled)
3792 intel_crtc_disable(crtc);
3793 }
79e53945
JB		 3794}
3795
ea5b213a 3796void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3797{
4ef69c7a 3798 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3799
ea5b213a
CW		 3800 drm_encoder_cleanup(encoder);
3801 kfree(intel_encoder);
7e7d76c3
JB		 3802}
3803
5ab432ef
DV		 3804/* Simple dpms helper for encodres with just one connector, no cloning and only
3805 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3806 * state of the entire output pipe. */
3807void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3808{
5ab432ef
DV		 3809 if (mode == DRM_MODE_DPMS_ON) {
3810 encoder->connectors_active = true;
3811
b2cabb0e 3812 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3813 } else {
3814 encoder->connectors_active = false;
3815
b2cabb0e 3816 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3817 }
79e53945
JB		 3818}
3819
0a91ca29
DV		 3820/* Cross check the actual hw state with our own modeset state tracking (and it's
3821 * internal consistency). */
b980514c 3822static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3823{
0a91ca29
DV		 3824 if (connector->get_hw_state(connector)) {
3825 struct intel_encoder *encoder = connector->encoder;
3826 struct drm_crtc *crtc;
3827 bool encoder_enabled;
3828 enum pipe pipe;
3829
3830 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3831 connector->base.base.id,
3832 drm_get_connector_name(&connector->base));
3833
3834 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3835 "wrong connector dpms state\n");
3836 WARN(connector->base.encoder != &encoder->base,
3837 "active connector not linked to encoder\n");
3838 WARN(!encoder->connectors_active,
3839 "encoder->connectors_active not set\n");
3840
3841 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3842 WARN(!encoder_enabled, "encoder not enabled\n");
3843 if (WARN_ON(!encoder->base.crtc))
3844 return;
3845
3846 crtc = encoder->base.crtc;
3847
3848 WARN(!crtc->enabled, "crtc not enabled\n");
3849 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3850 WARN(pipe != to_intel_crtc(crtc)->pipe,
3851 "encoder active on the wrong pipe\n");
3852 }
79e53945
JB		 3853}
3854
5ab432ef
DV		 3855/* Even simpler default implementation, if there's really no special case to
3856 * consider. */
3857void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3858{
5ab432ef 3859 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3860
5ab432ef
DV		 3861 /* All the simple cases only support two dpms states. */
3862 if (mode != DRM_MODE_DPMS_ON)
3863 mode = DRM_MODE_DPMS_OFF;
d4270e57 3864
5ab432ef
DV		 3865 if (mode == connector->dpms)
3866 return;
3867
3868 connector->dpms = mode;
3869
3870 /* Only need to change hw state when actually enabled */
3871 if (encoder->base.crtc)
3872 intel_encoder_dpms(encoder, mode);
3873 else
8af6cf88 3874 WARN_ON(encoder->connectors_active != false);
0a91ca29 3875
b980514c 3876 intel_modeset_check_state(connector->dev);
79e53945
JB		 3877}
3878
f0947c37
DV		 3879/* Simple connector->get_hw_state implementation for encoders that support only
3880 * one connector and no cloning and hence the encoder state determines the state
3881 * of the connector. */
3882bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3883{
24929352 3884 enum pipe pipe = 0;
f0947c37 3885 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3886
f0947c37 3887 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3888}
3889
1857e1da
DV		 3890static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3891 struct intel_crtc_config *pipe_config)
3892{
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 struct intel_crtc *pipe_B_crtc =
3895 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3896
3897 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3898 pipe_name(pipe), pipe_config->fdi_lanes);
3899 if (pipe_config->fdi_lanes > 4) {
3900 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3901 pipe_name(pipe), pipe_config->fdi_lanes);
3902 return false;
3903 }
3904
3905 if (IS_HASWELL(dev)) {
3906 if (pipe_config->fdi_lanes > 2) {
3907 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3908 pipe_config->fdi_lanes);
3909 return false;
3910 } else {
3911 return true;
3912 }
3913 }
3914
3915 if (INTEL_INFO(dev)->num_pipes == 2)
3916 return true;
3917
3918 /* Ivybridge 3 pipe is really complicated */
3919 switch (pipe) {
3920 case PIPE_A:
3921 return true;
3922 case PIPE_B:
3923 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3924 pipe_config->fdi_lanes > 2) {
3925 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3926 pipe_name(pipe), pipe_config->fdi_lanes);
3927 return false;
3928 }
3929 return true;
3930 case PIPE_C:
1e833f40 3931 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3932 pipe_B_crtc->config.fdi_lanes <= 2) {
3933 if (pipe_config->fdi_lanes > 2) {
3934 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3936 return false;
3937 }
3938 } else {
3939 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3940 return false;
3941 }
3942 return true;
3943 default:
3944 BUG();
3945 }
3946}
3947
e29c22c0
DV		 3948#define RETRY 1
3949static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3950 struct intel_crtc_config *pipe_config)
877d48d5 3951{
1857e1da 3952 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 3953 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3954 int target_clock, lane, link_bw;
e29c22c0 3955 bool setup_ok, needs_recompute = false;
877d48d5 3956
e29c22c0 3957retry:
877d48d5
DV		 3958 /* FDI is a binary signal running at ~2.7GHz, encoding
3959 * each output octet as 10 bits. The actual frequency
3960 * is stored as a divider into a 100MHz clock, and the
3961 * mode pixel clock is stored in units of 1KHz.
3962 * Hence the bw of each lane in terms of the mode signal
3963 * is:
3964 */
3965 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3966
3967 if (pipe_config->pixel_target_clock)
3968 target_clock = pipe_config->pixel_target_clock;
3969 else
3970 target_clock = adjusted_mode->clock;
3971
3972 lane = ironlake_get_lanes_required(target_clock, link_bw,
3973 pipe_config->pipe_bpp);
3974
3975 pipe_config->fdi_lanes = lane;
3976
3977 if (pipe_config->pixel_multiplier > 1)
3978 link_bw *= pipe_config->pixel_multiplier;
3979 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
3980 link_bw, &pipe_config->fdi_m_n);
1857e1da 3981
e29c22c0
DV		 3982 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
3983 intel_crtc->pipe, pipe_config);
3984 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
3985 pipe_config->pipe_bpp -= 2*3;
3986 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
3987 pipe_config->pipe_bpp);
3988 needs_recompute = true;
3989 pipe_config->bw_constrained = true;
3990
3991 goto retry;
3992 }
3993
3994 if (needs_recompute)
3995 return RETRY;
3996
3997 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 3998}
3999
e29c22c0
DV		 4000static int intel_crtc_compute_config(struct drm_crtc *crtc,
4001 struct intel_crtc_config *pipe_config)
79e53945 4002{
2c07245f 4003 struct drm_device *dev = crtc->dev;
b8cecdf5 4004 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4005
bad720ff 4006 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4007 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4008 if (pipe_config->requested_mode.clock * 3
4009 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4010 return -EINVAL;
2c07245f 4011 }
89749350 4012
f9bef081
DV		 4013 /* All interlaced capable intel hw wants timings in frames. Note though
4014 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4015 * timings, so we need to be careful not to clobber these.*/
7ae89233 4016 if (!pipe_config->timings_set)
f9bef081 4017 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4018
8693a824
DL		 4019 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4020 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4021 */
4022 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4023 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4024 return -EINVAL;
44f46b42 4025
bd080ee5 4026 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4027 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4028 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4029 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4030 * for lvds. */
4031 pipe_config->pipe_bpp = 8*3;
4032 }
4033
877d48d5 4034 if (pipe_config->has_pch_encoder)
1857e1da 4035 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4036
e29c22c0 4037 return 0;
79e53945
JB		 4038}
4039
25eb05fc
JB		 4040static int valleyview_get_display_clock_speed(struct drm_device *dev)
4041{
4042 return 400000; /* FIXME */
4043}
4044
e70236a8
JB		 4045static int i945_get_display_clock_speed(struct drm_device *dev)
4046{
4047 return 400000;
4048}
79e53945 4049
e70236a8 4050static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4051{
e70236a8
JB		 4052 return 333000;
4053}
79e53945 4054
e70236a8
JB		 4055static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4056{
4057 return 200000;
4058}
79e53945 4059
e70236a8
JB		 4060static int i915gm_get_display_clock_speed(struct drm_device *dev)
4061{
4062 u16 gcfgc = 0;
79e53945 4063
e70236a8
JB		 4064 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4065
4066 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4067 return 133000;
4068 else {
4069 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4070 case GC_DISPLAY_CLOCK_333_MHZ:
4071 return 333000;
4072 default:
4073 case GC_DISPLAY_CLOCK_190_200_MHZ:
4074 return 190000;
79e53945 4075 }
e70236a8
JB		 4076 }
4077}
4078
4079static int i865_get_display_clock_speed(struct drm_device *dev)
4080{
4081 return 266000;
4082}
4083
4084static int i855_get_display_clock_speed(struct drm_device *dev)
4085{
4086 u16 hpllcc = 0;
4087 /* Assume that the hardware is in the high speed state. This
4088 * should be the default.
4089 */
4090 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4091 case GC_CLOCK_133_200:
4092 case GC_CLOCK_100_200:
4093 return 200000;
4094 case GC_CLOCK_166_250:
4095 return 250000;
4096 case GC_CLOCK_100_133:
79e53945 4097 return 133000;
e70236a8 4098 }
79e53945 4099
e70236a8
JB		 4100 /* Shouldn't happen */
4101 return 0;
4102}
79e53945 4103
e70236a8
JB		 4104static int i830_get_display_clock_speed(struct drm_device *dev)
4105{
4106 return 133000;
79e53945
JB		 4107}
4108
2c07245f 4109static void
a65851af 4110intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4111{
a65851af
VS		 4112 while (*num > DATA_LINK_M_N_MASK ||
4113 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4114 *num >>= 1;
4115 *den >>= 1;
4116 }
4117}
4118
a65851af
VS		 4119static void compute_m_n(unsigned int m, unsigned int n,
4120 uint32_t *ret_m, uint32_t *ret_n)
4121{
4122 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4123 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4124 intel_reduce_m_n_ratio(ret_m, ret_n);
4125}
4126
e69d0bc1
DV		 4127void
4128intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4129 int pixel_clock, int link_clock,
4130 struct intel_link_m_n *m_n)
2c07245f 4131{
e69d0bc1 4132 m_n->tu = 64;
a65851af
VS		 4133
4134 compute_m_n(bits_per_pixel * pixel_clock,
4135 link_clock * nlanes * 8,
4136 &m_n->gmch_m, &m_n->gmch_n);
4137
4138 compute_m_n(pixel_clock, link_clock,
4139 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4140}
4141
a7615030
CW		 4142static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4143{
72bbe58c
KP		 4144 if (i915_panel_use_ssc >= 0)
4145 return i915_panel_use_ssc != 0;
41aa3448 4146 return dev_priv->vbt.lvds_use_ssc
435793df 4147 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4148}
4149
a0c4da24
JB		 4150static int vlv_get_refclk(struct drm_crtc *crtc)
4151{
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 int refclk = 27000; /* for DP & HDMI */
4155
4156 return 100000; /* only one validated so far */
4157
4158 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4159 refclk = 96000;
4160 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4161 if (intel_panel_use_ssc(dev_priv))
4162 refclk = 100000;
4163 else
4164 refclk = 96000;
4165 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4166 refclk = 100000;
4167 }
4168
4169 return refclk;
4170}
4171
c65d77d8
JB		 4172static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4173{
4174 struct drm_device *dev = crtc->dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 int refclk;
4177
a0c4da24
JB		 4178 if (IS_VALLEYVIEW(dev)) {
4179 refclk = vlv_get_refclk(crtc);
4180 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4181 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4182 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4183 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4184 refclk / 1000);
4185 } else if (!IS_GEN2(dev)) {
4186 refclk = 96000;
4187 } else {
4188 refclk = 48000;
4189 }
4190
4191 return refclk;
4192}
4193
7429e9d4
DV		 4194static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4195{
4196 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4197}
4198
4199static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4200{
4201 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4202}
4203
f47709a9 4204static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4205 intel_clock_t *reduced_clock)
4206{
f47709a9 4207 struct drm_device *dev = crtc->base.dev;
a7516a05 4208 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4209 int pipe = crtc->pipe;
a7516a05
JB		 4210 u32 fp, fp2 = 0;
4211
4212 if (IS_PINEVIEW(dev)) {
7429e9d4 4213 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4214 if (reduced_clock)
7429e9d4 4215 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4216 } else {
7429e9d4 4217 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4218 if (reduced_clock)
7429e9d4 4219 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4220 }
4221
4222 I915_WRITE(FP0(pipe), fp);
4223
f47709a9
DV		 4224 crtc->lowfreq_avail = false;
4225 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4226 reduced_clock && i915_powersave) {
4227 I915_WRITE(FP1(pipe), fp2);
f47709a9 4228 crtc->lowfreq_avail = true;
a7516a05
JB		 4229 } else {
4230 I915_WRITE(FP1(pipe), fp);
4231 }
4232}
4233
89b667f8
JB		 4234static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4235{
4236 u32 reg_val;
4237
4238 /*
4239 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4240 * and set it to a reasonable value instead.
4241 */
ae99258f 4242 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4243 reg_val &= 0xffffff00;
4244 reg_val |= 0x00000030;
ae99258f 4245 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4246
ae99258f 4247 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4248 reg_val &= 0x8cffffff;
4249 reg_val = 0x8c000000;
ae99258f 4250 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4251
ae99258f 4252 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4253 reg_val &= 0xffffff00;
ae99258f 4254 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4255
ae99258f 4256 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4257 reg_val &= 0x00ffffff;
4258 reg_val |= 0xb0000000;
ae99258f 4259 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4260}
4261
b551842d
DV		 4262static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4263 struct intel_link_m_n *m_n)
4264{
4265 struct drm_device *dev = crtc->base.dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 int pipe = crtc->pipe;
4268
e3b95f1e
DV		 4269 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4270 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4271 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4272 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4273}
4274
4275static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4276 struct intel_link_m_n *m_n)
4277{
4278 struct drm_device *dev = crtc->base.dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280 int pipe = crtc->pipe;
4281 enum transcoder transcoder = crtc->config.cpu_transcoder;
4282
4283 if (INTEL_INFO(dev)->gen >= 5) {
4284 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4285 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4286 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4287 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4288 } else {
e3b95f1e
DV		 4289 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4290 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4291 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4292 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4293 }
4294}
4295
03afc4a2
DV		 4296static void intel_dp_set_m_n(struct intel_crtc *crtc)
4297{
4298 if (crtc->config.has_pch_encoder)
4299 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4300 else
4301 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4302}
4303
f47709a9 4304static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4305{
f47709a9 4306 struct drm_device *dev = crtc->base.dev;
a0c4da24 4307 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4308 struct drm_display_mode *adjusted_mode =
4309 &crtc->config.adjusted_mode;
4310 struct intel_encoder *encoder;
f47709a9 4311 int pipe = crtc->pipe;
89b667f8 4312 u32 dpll, mdiv;
a0c4da24 4313 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4314 bool is_hdmi;
198a037f 4315 u32 coreclk, reg_val, dpll_md;
a0c4da24 4316
09153000
DV		 4317 mutex_lock(&dev_priv->dpio_lock);
4318
89b667f8 4319 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4320
f47709a9
DV		 4321 bestn = crtc->config.dpll.n;
4322 bestm1 = crtc->config.dpll.m1;
4323 bestm2 = crtc->config.dpll.m2;
4324 bestp1 = crtc->config.dpll.p1;
4325 bestp2 = crtc->config.dpll.p2;
a0c4da24 4326
89b667f8
JB		 4327 /* See eDP HDMI DPIO driver vbios notes doc */
4328
4329 /* PLL B needs special handling */
4330 if (pipe)
4331 vlv_pllb_recal_opamp(dev_priv);
4332
4333 /* Set up Tx target for periodic Rcomp update */
ae99258f 4334 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4335
4336 /* Disable target IRef on PLL */
ae99258f 4337 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4338 reg_val &= 0x00ffffff;
ae99258f 4339 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4340
4341 /* Disable fast lock */
ae99258f 4342 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4343
4344 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4345 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4346 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4347 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4348 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4349
4350 /*
4351 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4352 * but we don't support that).
4353 * Note: don't use the DAC post divider as it seems unstable.
4354 */
4355 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4356 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4357
89b667f8 4358 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4359 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4360
89b667f8
JB		 4361 /* Set HBR and RBR LPF coefficients */
4362 if (adjusted_mode->clock == 162000 ||
4363 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4364 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4365 0x005f0021);
4366 else
ae99258f 4367 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4368 0x00d0000f);
4369
4370 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4371 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4372 /* Use SSC source */
4373 if (!pipe)
ae99258f 4374 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4375 0x0df40000);
4376 else
ae99258f 4377 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4378 0x0df70000);
4379 } else { /* HDMI or VGA */
4380 /* Use bend source */
4381 if (!pipe)
ae99258f 4382 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4383 0x0df70000);
4384 else
ae99258f 4385 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4386 0x0df40000);
4387 }
a0c4da24 4388
ae99258f 4389 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4390 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4391 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4392 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4393 coreclk |= 0x01000000;
ae99258f 4394 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4395
ae99258f 4396 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4397
89b667f8
JB		 4398 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4399 if (encoder->pre_pll_enable)
4400 encoder->pre_pll_enable(encoder);
2a8f64ca 4401
89b667f8
JB		 4402 /* Enable DPIO clock input */
4403 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4404 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4405 if (pipe)
4406 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4407
89b667f8 4408 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4409 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4410 POSTING_READ(DPLL(pipe));
4411 udelay(150);
a0c4da24 4412
89b667f8
JB		 4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4415
198a037f
DV		 4416 dpll_md = 0;
4417 if (crtc->config.pixel_multiplier > 1) {
4418 dpll_md = (crtc->config.pixel_multiplier - 1)
4419 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4420 }
198a037f
DV		 4421 I915_WRITE(DPLL_MD(pipe), dpll_md);
4422 POSTING_READ(DPLL_MD(pipe));
f47709a9 4423
89b667f8
JB		 4424 if (crtc->config.has_dp_encoder)
4425 intel_dp_set_m_n(crtc);
09153000
DV		 4426
4427 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4428}
4429
f47709a9
DV		 4430static void i9xx_update_pll(struct intel_crtc *crtc,
4431 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4432 int num_connectors)
4433{
f47709a9 4434 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4435 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4436 struct intel_encoder *encoder;
f47709a9 4437 int pipe = crtc->pipe;
eb1cbe48
DV		 4438 u32 dpll;
4439 bool is_sdvo;
f47709a9 4440 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4441
f47709a9 4442 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4443
f47709a9
DV		 4444 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4445 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4446
4447 dpll = DPLL_VGA_MODE_DIS;
4448
f47709a9 4449 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4450 dpll |= DPLLB_MODE_LVDS;
4451 else
4452 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4453
198a037f
DV		 4454 if ((crtc->config.pixel_multiplier > 1) &&
4455 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4456 dpll |= (crtc->config.pixel_multiplier - 1)
4457 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4458 }
198a037f
DV		 4459
4460 if (is_sdvo)
4461 dpll |= DPLL_DVO_HIGH_SPEED;
4462
f47709a9 4463 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4464 dpll |= DPLL_DVO_HIGH_SPEED;
4465
4466 /* compute bitmask from p1 value */
4467 if (IS_PINEVIEW(dev))
4468 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4469 else {
4470 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4471 if (IS_G4X(dev) && reduced_clock)
4472 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4473 }
4474 switch (clock->p2) {
4475 case 5:
4476 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4477 break;
4478 case 7:
4479 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4480 break;
4481 case 10:
4482 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4483 break;
4484 case 14:
4485 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4486 break;
4487 }
4488 if (INTEL_INFO(dev)->gen >= 4)
4489 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4490
09ede541 4491 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4492 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4493 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4494 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4495 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4496 else
4497 dpll |= PLL_REF_INPUT_DREFCLK;
4498
4499 dpll |= DPLL_VCO_ENABLE;
4500 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4501 POSTING_READ(DPLL(pipe));
4502 udelay(150);
4503
f47709a9 4504 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4505 if (encoder->pre_pll_enable)
4506 encoder->pre_pll_enable(encoder);
eb1cbe48 4507
f47709a9
DV		 4508 if (crtc->config.has_dp_encoder)
4509 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4510
4511 I915_WRITE(DPLL(pipe), dpll);
4512
4513 /* Wait for the clocks to stabilize. */
4514 POSTING_READ(DPLL(pipe));
4515 udelay(150);
4516
4517 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4518 u32 dpll_md = 0;
4519 if (crtc->config.pixel_multiplier > 1) {
4520 dpll_md = (crtc->config.pixel_multiplier - 1)
4521 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4522 }
198a037f 4523 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4524 } else {
4525 /* The pixel multiplier can only be updated once the
4526 * DPLL is enabled and the clocks are stable.
4527 *
4528 * So write it again.
4529 */
4530 I915_WRITE(DPLL(pipe), dpll);
4531 }
4532}
4533
f47709a9 4534static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4535 struct drm_display_mode *adjusted_mode,
f47709a9 4536 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4537 int num_connectors)
4538{
f47709a9 4539 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4540 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4541 struct intel_encoder *encoder;
f47709a9 4542 int pipe = crtc->pipe;
eb1cbe48 4543 u32 dpll;
f47709a9 4544 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4545
f47709a9 4546 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4547
eb1cbe48
DV		 4548 dpll = DPLL_VGA_MODE_DIS;
4549
f47709a9 4550 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4551 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4552 } else {
4553 if (clock->p1 == 2)
4554 dpll |= PLL_P1_DIVIDE_BY_TWO;
4555 else
4556 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557 if (clock->p2 == 4)
4558 dpll |= PLL_P2_DIVIDE_BY_4;
4559 }
4560
f47709a9 4561 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4562 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4563 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4564 else
4565 dpll |= PLL_REF_INPUT_DREFCLK;
4566
4567 dpll |= DPLL_VCO_ENABLE;
4568 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4569 POSTING_READ(DPLL(pipe));
4570 udelay(150);
4571
f47709a9 4572 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4573 if (encoder->pre_pll_enable)
4574 encoder->pre_pll_enable(encoder);
eb1cbe48 4575
5b5896e4
DV		 4576 I915_WRITE(DPLL(pipe), dpll);
4577
4578 /* Wait for the clocks to stabilize. */
4579 POSTING_READ(DPLL(pipe));
4580 udelay(150);
4581
eb1cbe48
DV		 4582 /* The pixel multiplier can only be updated once the
4583 * DPLL is enabled and the clocks are stable.
4584 *
4585 * So write it again.
4586 */
4587 I915_WRITE(DPLL(pipe), dpll);
4588}
4589
b0e77b9c
PZ		 4590static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4591 struct drm_display_mode *mode,
4592 struct drm_display_mode *adjusted_mode)
4593{
4594 struct drm_device *dev = intel_crtc->base.dev;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4597 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4598 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4599
4600 /* We need to be careful not to changed the adjusted mode, for otherwise
4601 * the hw state checker will get angry at the mismatch. */
4602 crtc_vtotal = adjusted_mode->crtc_vtotal;
4603 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4604
4605 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4606 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4607 crtc_vtotal -= 1;
4608 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4609 vsyncshift = adjusted_mode->crtc_hsync_start
4610 - adjusted_mode->crtc_htotal / 2;
4611 } else {
4612 vsyncshift = 0;
4613 }
4614
4615 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4616 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4617
fe2b8f9d 4618 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4619 (adjusted_mode->crtc_hdisplay - 1) |
4620 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4621 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4622 (adjusted_mode->crtc_hblank_start - 1) |
4623 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4624 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4625 (adjusted_mode->crtc_hsync_start - 1) |
4626 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4627
fe2b8f9d 4628 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4629 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4630 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4631 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4632 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4633 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4634 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4635 (adjusted_mode->crtc_vsync_start - 1) |
4636 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4637
b5e508d4
PZ		 4638 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4639 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4640 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4641 * bits. */
4642 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4643 (pipe == PIPE_B || pipe == PIPE_C))
4644 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4645
b0e77b9c
PZ		 4646 /* pipesrc controls the size that is scaled from, which should
4647 * always be the user's requested size.
4648 */
4649 I915_WRITE(PIPESRC(pipe),
4650 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4651}
4652
1bd1bd80
DV		 4653static void intel_get_pipe_timings(struct intel_crtc *crtc,
4654 struct intel_crtc_config *pipe_config)
4655{
4656 struct drm_device *dev = crtc->base.dev;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4659 uint32_t tmp;
4660
4661 tmp = I915_READ(HTOTAL(cpu_transcoder));
4662 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4663 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4664 tmp = I915_READ(HBLANK(cpu_transcoder));
4665 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4666 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4667 tmp = I915_READ(HSYNC(cpu_transcoder));
4668 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4669 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4670
4671 tmp = I915_READ(VTOTAL(cpu_transcoder));
4672 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4673 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4674 tmp = I915_READ(VBLANK(cpu_transcoder));
4675 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4676 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4677 tmp = I915_READ(VSYNC(cpu_transcoder));
4678 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4679 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4680
4681 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4682 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4683 pipe_config->adjusted_mode.crtc_vtotal += 1;
4684 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4685 }
4686
4687 tmp = I915_READ(PIPESRC(crtc->pipe));
4688 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4689 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4690}
4691
84b046f3
DV		 4692static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4693{
4694 struct drm_device *dev = intel_crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 uint32_t pipeconf;
4697
4698 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4699
4700 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4701 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4702 * core speed.
4703 *
4704 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4705 * pipe == 0 check?
4706 */
4707 if (intel_crtc->config.requested_mode.clock >
4708 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4709 pipeconf |= PIPECONF_DOUBLE_WIDE;
4710 else
4711 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4712 }
4713
ff9ce46e
DV		 4714 /* only g4x and later have fancy bpc/dither controls */
4715 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4716 pipeconf &= ~(PIPECONF_BPC_MASK |
4717 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4718
4719 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4720 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4721 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4722 PIPECONF_DITHER_TYPE_SP;
84b046f3 4723
ff9ce46e
DV		 4724 switch (intel_crtc->config.pipe_bpp) {
4725 case 18:
4726 pipeconf |= PIPECONF_6BPC;
4727 break;
4728 case 24:
4729 pipeconf |= PIPECONF_8BPC;
4730 break;
4731 case 30:
4732 pipeconf |= PIPECONF_10BPC;
4733 break;
4734 default:
4735 /* Case prevented by intel_choose_pipe_bpp_dither. */
4736 BUG();
84b046f3
DV		 4737 }
4738 }
4739
4740 if (HAS_PIPE_CXSR(dev)) {
4741 if (intel_crtc->lowfreq_avail) {
4742 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4743 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4744 } else {
4745 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4746 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4747 }
4748 }
4749
4750 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4751 if (!IS_GEN2(dev) &&
4752 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4753 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4754 else
4755 pipeconf |= PIPECONF_PROGRESSIVE;
4756
9c8e09b7
VS		 4757 if (IS_VALLEYVIEW(dev)) {
4758 if (intel_crtc->config.limited_color_range)
4759 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4760 else
4761 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4762 }
4763
84b046f3
DV		 4764 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4765 POSTING_READ(PIPECONF(intel_crtc->pipe));
4766}
4767
f564048e 4768static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4769 int x, int y,
94352cf9 4770 struct drm_framebuffer *fb)
79e53945
JB		 4771{
4772 struct drm_device *dev = crtc->dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4775 struct drm_display_mode *adjusted_mode =
4776 &intel_crtc->config.adjusted_mode;
4777 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4778 int pipe = intel_crtc->pipe;
80824003 4779 int plane = intel_crtc->plane;
c751ce4f 4780 int refclk, num_connectors = 0;
652c393a 4781 intel_clock_t clock, reduced_clock;
84b046f3 4782 u32 dspcntr;
a16af721
DV		 4783 bool ok, has_reduced_clock = false;
4784 bool is_lvds = false;
5eddb70b 4785 struct intel_encoder *encoder;
d4906093 4786 const intel_limit_t *limit;
5c3b82e2 4787 int ret;
79e53945 4788
6c2b7c12 4789 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4790 switch (encoder->type) {
79e53945
JB		 4791 case INTEL_OUTPUT_LVDS:
4792 is_lvds = true;
4793 break;
79e53945 4794 }
43565a06 4795
c751ce4f 4796 num_connectors++;
79e53945
JB		 4797 }
4798
c65d77d8 4799 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4800
d4906093
ML		 4801 /*
4802 * Returns a set of divisors for the desired target clock with the given
4803 * refclk, or FALSE. The returned values represent the clock equation:
4804 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4805 */
1b894b59 4806 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4807 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4808 &clock);
79e53945
JB		 4809 if (!ok) {
4810 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4811 return -EINVAL;
79e53945
JB		 4812 }
4813
cda4b7d3 4814 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4815 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4816
ddc9003c 4817 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4818 /*
4819 * Ensure we match the reduced clock's P to the target clock.
4820 * If the clocks don't match, we can't switch the display clock
4821 * by using the FP0/FP1. In such case we will disable the LVDS
4822 * downclock feature.
4823 */
ddc9003c 4824 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4825 dev_priv->lvds_downclock,
4826 refclk,
cec2f356 4827 &clock,
5eddb70b 4828 &reduced_clock);
7026d4ac 4829 }
f47709a9
DV		 4830 /* Compat-code for transition, will disappear. */
4831 if (!intel_crtc->config.clock_set) {
4832 intel_crtc->config.dpll.n = clock.n;
4833 intel_crtc->config.dpll.m1 = clock.m1;
4834 intel_crtc->config.dpll.m2 = clock.m2;
4835 intel_crtc->config.dpll.p1 = clock.p1;
4836 intel_crtc->config.dpll.p2 = clock.p2;
4837 }
7026d4ac 4838
eb1cbe48 4839 if (IS_GEN2(dev))
f47709a9 4840 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4841 has_reduced_clock ? &reduced_clock : NULL,
4842 num_connectors);
a0c4da24 4843 else if (IS_VALLEYVIEW(dev))
f47709a9 4844 vlv_update_pll(intel_crtc);
79e53945 4845 else
f47709a9 4846 i9xx_update_pll(intel_crtc,
eb1cbe48 4847 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4848 num_connectors);
79e53945 4849
79e53945
JB		 4850 /* Set up the display plane register */
4851 dspcntr = DISPPLANE_GAMMA_ENABLE;
4852
da6ecc5d
JB		 4853 if (!IS_VALLEYVIEW(dev)) {
4854 if (pipe == 0)
4855 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4856 else
4857 dspcntr |= DISPPLANE_SEL_PIPE_B;
4858 }
79e53945 4859
2582a850 4860 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4861 drm_mode_debug_printmodeline(mode);
4862
b0e77b9c 4863 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4864
4865 /* pipesrc and dspsize control the size that is scaled from,
4866 * which should always be the user's requested size.
79e53945 4867 */
929c77fb
EA		 4868 I915_WRITE(DSPSIZE(plane),
4869 ((mode->vdisplay - 1) << 16) |
4870 (mode->hdisplay - 1));
4871 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4872
84b046f3
DV		 4873 i9xx_set_pipeconf(intel_crtc);
4874
f564048e
EA		 4875 I915_WRITE(DSPCNTR(plane), dspcntr);
4876 POSTING_READ(DSPCNTR(plane));
4877
94352cf9 4878 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4879
4880 intel_update_watermarks(dev);
4881
f564048e
EA		 4882 return ret;
4883}
4884
2fa2fe9a
DV		 4885static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4886 struct intel_crtc_config *pipe_config)
4887{
4888 struct drm_device *dev = crtc->base.dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 uint32_t tmp;
4891
4892 tmp = I915_READ(PFIT_CONTROL);
4893
4894 if (INTEL_INFO(dev)->gen < 4) {
4895 if (crtc->pipe != PIPE_B)
4896 return;
4897
4898 /* gen2/3 store dither state in pfit control, needs to match */
4899 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4900 } else {
4901 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4902 return;
4903 }
4904
4905 if (!(tmp & PFIT_ENABLE))
4906 return;
4907
4908 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4909 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4910 if (INTEL_INFO(dev)->gen < 5)
4911 pipe_config->gmch_pfit.lvds_border_bits =
4912 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4913}
4914
0e8ffe1b
DV		 4915static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4916 struct intel_crtc_config *pipe_config)
4917{
4918 struct drm_device *dev = crtc->base.dev;
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 uint32_t tmp;
4921
eccb140b
DV		 4922 pipe_config->cpu_transcoder = crtc->pipe;
4923
0e8ffe1b
DV		 4924 tmp = I915_READ(PIPECONF(crtc->pipe));
4925 if (!(tmp & PIPECONF_ENABLE))
4926 return false;
4927
1bd1bd80
DV		 4928 intel_get_pipe_timings(crtc, pipe_config);
4929
2fa2fe9a
DV		 4930 i9xx_get_pfit_config(crtc, pipe_config);
4931
0e8ffe1b
DV		 4932 return true;
4933}
4934
dde86e2d 4935static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4936{
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4939 struct intel_encoder *encoder;
74cfd7ac 4940 u32 val, final;
13d83a67 4941 bool has_lvds = false;
199e5d79 4942 bool has_cpu_edp = false;
199e5d79 4943 bool has_panel = false;
99eb6a01
KP		 4944 bool has_ck505 = false;
4945 bool can_ssc = false;
13d83a67
JB		 4946
4947 /* We need to take the global config into account */
199e5d79
KP		 4948 list_for_each_entry(encoder, &mode_config->encoder_list,
4949 base.head) {
4950 switch (encoder->type) {
4951 case INTEL_OUTPUT_LVDS:
4952 has_panel = true;
4953 has_lvds = true;
4954 break;
4955 case INTEL_OUTPUT_EDP:
4956 has_panel = true;
2de6905f 4957 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 4958 has_cpu_edp = true;
4959 break;
13d83a67
JB		 4960 }
4961 }
4962
99eb6a01 4963 if (HAS_PCH_IBX(dev)) {
41aa3448 4964 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 4965 can_ssc = has_ck505;
4966 } else {
4967 has_ck505 = false;
4968 can_ssc = true;
4969 }
4970
2de6905f
ID		 4971 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
4972 has_panel, has_lvds, has_ck505);
13d83a67
JB		 4973
4974 /* Ironlake: try to setup display ref clock before DPLL
4975 * enabling. This is only under driver's control after
4976 * PCH B stepping, previous chipset stepping should be
4977 * ignoring this setting.
4978 */
74cfd7ac
CW		 4979 val = I915_READ(PCH_DREF_CONTROL);
4980
4981 /* As we must carefully and slowly disable/enable each source in turn,
4982 * compute the final state we want first and check if we need to
4983 * make any changes at all.
4984 */
4985 final = val;
4986 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4987 if (has_ck505)
4988 final |= DREF_NONSPREAD_CK505_ENABLE;
4989 else
4990 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4991
4992 final &= ~DREF_SSC_SOURCE_MASK;
4993 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4994 final &= ~DREF_SSC1_ENABLE;
4995
4996 if (has_panel) {
4997 final |= DREF_SSC_SOURCE_ENABLE;
4998
4999 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5000 final |= DREF_SSC1_ENABLE;
5001
5002 if (has_cpu_edp) {
5003 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5004 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5005 else
5006 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5007 } else
5008 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5009 } else {
5010 final |= DREF_SSC_SOURCE_DISABLE;
5011 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5012 }
5013
5014 if (final == val)
5015 return;
5016
13d83a67 5017 /* Always enable nonspread source */
74cfd7ac 5018 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5019
99eb6a01 5020 if (has_ck505)
74cfd7ac 5021 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5022 else
74cfd7ac 5023 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5024
199e5d79 5025 if (has_panel) {
74cfd7ac
CW		 5026 val &= ~DREF_SSC_SOURCE_MASK;
5027 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5028
199e5d79 5029 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5030 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5031 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5032 val |= DREF_SSC1_ENABLE;
e77166b5 5033 } else
74cfd7ac 5034 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5035
5036 /* Get SSC going before enabling the outputs */
74cfd7ac 5037 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5038 POSTING_READ(PCH_DREF_CONTROL);
5039 udelay(200);
5040
74cfd7ac 5041 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5042
5043 /* Enable CPU source on CPU attached eDP */
199e5d79 5044 if (has_cpu_edp) {
99eb6a01 5045 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5046 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5047 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5048 }
13d83a67 5049 else
74cfd7ac 5050 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5051 } else
74cfd7ac 5052 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5053
74cfd7ac 5054 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5055 POSTING_READ(PCH_DREF_CONTROL);
5056 udelay(200);
5057 } else {
5058 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5059
74cfd7ac 5060 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5061
5062 /* Turn off CPU output */
74cfd7ac 5063 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5064
74cfd7ac 5065 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5066 POSTING_READ(PCH_DREF_CONTROL);
5067 udelay(200);
5068
5069 /* Turn off the SSC source */
74cfd7ac
CW		 5070 val &= ~DREF_SSC_SOURCE_MASK;
5071 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5072
5073 /* Turn off SSC1 */
74cfd7ac 5074 val &= ~DREF_SSC1_ENABLE;
199e5d79 5075
74cfd7ac 5076 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5077 POSTING_READ(PCH_DREF_CONTROL);
5078 udelay(200);
5079 }
74cfd7ac
CW		 5080
5081 BUG_ON(val != final);
13d83a67
JB		 5082}
5083
dde86e2d
PZ		 5084/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5085static void lpt_init_pch_refclk(struct drm_device *dev)
5086{
5087 struct drm_i915_private *dev_priv = dev->dev_private;
5088 struct drm_mode_config *mode_config = &dev->mode_config;
5089 struct intel_encoder *encoder;
5090 bool has_vga = false;
5091 bool is_sdv = false;
5092 u32 tmp;
5093
5094 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5095 switch (encoder->type) {
5096 case INTEL_OUTPUT_ANALOG:
5097 has_vga = true;
5098 break;
5099 }
5100 }
5101
5102 if (!has_vga)
5103 return;
5104
c00db246
DV		 5105 mutex_lock(&dev_priv->dpio_lock);
5106
dde86e2d
PZ		 5107 /* XXX: Rip out SDV support once Haswell ships for real. */
5108 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5109 is_sdv = true;
5110
5111 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5112 tmp &= ~SBI_SSCCTL_DISABLE;
5113 tmp |= SBI_SSCCTL_PATHALT;
5114 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5115
5116 udelay(24);
5117
5118 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5119 tmp &= ~SBI_SSCCTL_PATHALT;
5120 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5121
5122 if (!is_sdv) {
5123 tmp = I915_READ(SOUTH_CHICKEN2);
5124 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5125 I915_WRITE(SOUTH_CHICKEN2, tmp);
5126
5127 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5128 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5129 DRM_ERROR("FDI mPHY reset assert timeout\n");
5130
5131 tmp = I915_READ(SOUTH_CHICKEN2);
5132 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5133 I915_WRITE(SOUTH_CHICKEN2, tmp);
5134
5135 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5136 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5137 100))
5138 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5139 }
5140
5141 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5142 tmp &= ~(0xFF << 24);
5143 tmp |= (0x12 << 24);
5144 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5145
dde86e2d
PZ		 5146 if (is_sdv) {
5147 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5148 tmp |= 0x7FFF;
5149 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5150 }
5151
5152 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5153 tmp |= (1 << 11);
5154 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5155
5156 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5157 tmp |= (1 << 11);
5158 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5159
5160 if (is_sdv) {
5161 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5162 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5163 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5164
5165 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5166 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5167 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5168
5169 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5170 tmp |= (0x3F << 8);
5171 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5172
5173 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5174 tmp |= (0x3F << 8);
5175 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5176 }
5177
5178 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5179 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5180 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5181
5182 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5183 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5184 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5185
5186 if (!is_sdv) {
5187 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5188 tmp &= ~(7 << 13);
5189 tmp |= (5 << 13);
5190 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5191
5192 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5193 tmp &= ~(7 << 13);
5194 tmp |= (5 << 13);
5195 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5196 }
5197
5198 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5199 tmp &= ~0xFF;
5200 tmp |= 0x1C;
5201 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5202
5203 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5204 tmp &= ~0xFF;
5205 tmp |= 0x1C;
5206 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5207
5208 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5209 tmp &= ~(0xFF << 16);
5210 tmp |= (0x1C << 16);
5211 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5214 tmp &= ~(0xFF << 16);
5215 tmp |= (0x1C << 16);
5216 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5217
5218 if (!is_sdv) {
5219 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5220 tmp |= (1 << 27);
5221 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5222
5223 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5224 tmp |= (1 << 27);
5225 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5226
5227 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5228 tmp &= ~(0xF << 28);
5229 tmp |= (4 << 28);
5230 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5231
5232 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5233 tmp &= ~(0xF << 28);
5234 tmp |= (4 << 28);
5235 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5236 }
5237
5238 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5239 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5240 tmp |= SBI_DBUFF0_ENABLE;
5241 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5242
5243 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5244}
5245
5246/*
5247 * Initialize reference clocks when the driver loads
5248 */
5249void intel_init_pch_refclk(struct drm_device *dev)
5250{
5251 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5252 ironlake_init_pch_refclk(dev);
5253 else if (HAS_PCH_LPT(dev))
5254 lpt_init_pch_refclk(dev);
5255}
5256
d9d444cb
JB		 5257static int ironlake_get_refclk(struct drm_crtc *crtc)
5258{
5259 struct drm_device *dev = crtc->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_encoder *encoder;
d9d444cb
JB		 5262 int num_connectors = 0;
5263 bool is_lvds = false;
5264
6c2b7c12 5265 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5266 switch (encoder->type) {
5267 case INTEL_OUTPUT_LVDS:
5268 is_lvds = true;
5269 break;
d9d444cb
JB		 5270 }
5271 num_connectors++;
5272 }
5273
5274 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5275 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5276 dev_priv->vbt.lvds_ssc_freq);
5277 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5278 }
5279
5280 return 120000;
5281}
5282
6ff93609 5283static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5284{
c8203565 5285 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5287 int pipe = intel_crtc->pipe;
c8203565
PZ		 5288 uint32_t val;
5289
5290 val = I915_READ(PIPECONF(pipe));
5291
dfd07d72 5292 val &= ~PIPECONF_BPC_MASK;
965e0c48 5293 switch (intel_crtc->config.pipe_bpp) {
c8203565 5294 case 18:
dfd07d72 5295 val |= PIPECONF_6BPC;
c8203565
PZ		 5296 break;
5297 case 24:
dfd07d72 5298 val |= PIPECONF_8BPC;
c8203565
PZ		 5299 break;
5300 case 30:
dfd07d72 5301 val |= PIPECONF_10BPC;
c8203565
PZ		 5302 break;
5303 case 36:
dfd07d72 5304 val |= PIPECONF_12BPC;
c8203565
PZ		 5305 break;
5306 default:
cc769b62
PZ		 5307 /* Case prevented by intel_choose_pipe_bpp_dither. */
5308 BUG();
c8203565
PZ		 5309 }
5310
5311 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5312 if (intel_crtc->config.dither)
c8203565
PZ		 5313 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5314
5315 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5316 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5317 val |= PIPECONF_INTERLACED_ILK;
5318 else
5319 val |= PIPECONF_PROGRESSIVE;
5320
50f3b016 5321 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5322 val |= PIPECONF_COLOR_RANGE_SELECT;
5323 else
5324 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5325
c8203565
PZ		 5326 I915_WRITE(PIPECONF(pipe), val);
5327 POSTING_READ(PIPECONF(pipe));
5328}
5329
86d3efce
VS		 5330/*
5331 * Set up the pipe CSC unit.
5332 *
5333 * Currently only full range RGB to limited range RGB conversion
5334 * is supported, but eventually this should handle various
5335 * RGB<->YCbCr scenarios as well.
5336 */
50f3b016 5337static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5338{
5339 struct drm_device *dev = crtc->dev;
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5342 int pipe = intel_crtc->pipe;
5343 uint16_t coeff = 0x7800; /* 1.0 */
5344
5345 /*
5346 * TODO: Check what kind of values actually come out of the pipe
5347 * with these coeff/postoff values and adjust to get the best
5348 * accuracy. Perhaps we even need to take the bpc value into
5349 * consideration.
5350 */
5351
50f3b016 5352 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5353 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5354
5355 /*
5356 * GY/GU and RY/RU should be the other way around according
5357 * to BSpec, but reality doesn't agree. Just set them up in
5358 * a way that results in the correct picture.
5359 */
5360 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5361 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5362
5363 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5364 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5365
5366 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5367 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5368
5369 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5370 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5371 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5372
5373 if (INTEL_INFO(dev)->gen > 6) {
5374 uint16_t postoff = 0;
5375
50f3b016 5376 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5377 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5378
5379 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5380 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5381 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5382
5383 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5384 } else {
5385 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5386
50f3b016 5387 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5388 mode |= CSC_BLACK_SCREEN_OFFSET;
5389
5390 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5391 }
5392}
5393
6ff93609 5394static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5395{
5396 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5398 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5399 uint32_t val;
5400
702e7a56 5401 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5402
5403 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5404 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5405 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5406
5407 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5408 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5409 val |= PIPECONF_INTERLACED_ILK;
5410 else
5411 val |= PIPECONF_PROGRESSIVE;
5412
702e7a56
PZ		 5413 I915_WRITE(PIPECONF(cpu_transcoder), val);
5414 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5415}
5416
6591c6e4
PZ		 5417static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5418 struct drm_display_mode *adjusted_mode,
5419 intel_clock_t *clock,
5420 bool *has_reduced_clock,
5421 intel_clock_t *reduced_clock)
5422{
5423 struct drm_device *dev = crtc->dev;
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5425 struct intel_encoder *intel_encoder;
5426 int refclk;
d4906093 5427 const intel_limit_t *limit;
a16af721 5428 bool ret, is_lvds = false;
79e53945 5429
6591c6e4
PZ		 5430 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5431 switch (intel_encoder->type) {
79e53945
JB		 5432 case INTEL_OUTPUT_LVDS:
5433 is_lvds = true;
5434 break;
79e53945
JB		 5435 }
5436 }
5437
d9d444cb 5438 refclk = ironlake_get_refclk(crtc);
79e53945 5439
d4906093
ML		 5440 /*
5441 * Returns a set of divisors for the desired target clock with the given
5442 * refclk, or FALSE. The returned values represent the clock equation:
5443 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5444 */
1b894b59 5445 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5446 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5447 clock);
5448 if (!ret)
5449 return false;
cda4b7d3 5450
ddc9003c 5451 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5452 /*
5453 * Ensure we match the reduced clock's P to the target clock.
5454 * If the clocks don't match, we can't switch the display clock
5455 * by using the FP0/FP1. In such case we will disable the LVDS
5456 * downclock feature.
5457 */
6591c6e4
PZ		 5458 *has_reduced_clock = limit->find_pll(limit, crtc,
5459 dev_priv->lvds_downclock,
5460 refclk,
5461 clock,
5462 reduced_clock);
652c393a 5463 }
61e9653f 5464
6591c6e4
PZ		 5465 return true;
5466}
5467
01a415fd
DV		 5468static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t temp;
5472
5473 temp = I915_READ(SOUTH_CHICKEN1);
5474 if (temp & FDI_BC_BIFURCATION_SELECT)
5475 return;
5476
5477 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5479
5480 temp |= FDI_BC_BIFURCATION_SELECT;
5481 DRM_DEBUG_KMS("enabling fdi C rx\n");
5482 I915_WRITE(SOUTH_CHICKEN1, temp);
5483 POSTING_READ(SOUTH_CHICKEN1);
5484}
5485
ebfd86fd
DV		 5486static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5487{
5488 struct drm_device *dev = intel_crtc->base.dev;
5489 struct drm_i915_private *dev_priv = dev->dev_private;
5490
5491 switch (intel_crtc->pipe) {
5492 case PIPE_A:
5493 break;
5494 case PIPE_B:
5495 if (intel_crtc->config.fdi_lanes > 2)
5496 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5497 else
5498 cpt_enable_fdi_bc_bifurcation(dev);
5499
5500 break;
5501 case PIPE_C:
01a415fd
DV		 5502 cpt_enable_fdi_bc_bifurcation(dev);
5503
ebfd86fd 5504 break;
01a415fd
DV		 5505 default:
5506 BUG();
5507 }
5508}
5509
d4b1931c
PZ		 5510int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5511{
5512 /*
5513 * Account for spread spectrum to avoid
5514 * oversubscribing the link. Max center spread
5515 * is 2.5%; use 5% for safety's sake.
5516 */
5517 u32 bps = target_clock * bpp * 21 / 20;
5518 return bps / (link_bw * 8) + 1;
5519}
5520
7429e9d4
DV		 5521static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5522{
5523 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5524}
5525
de13a2e3 5526static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5527 u32 *fp,
9a7c7890 5528 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5529{
de13a2e3 5530 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5531 struct drm_device *dev = crtc->dev;
5532 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5533 struct intel_encoder *intel_encoder;
5534 uint32_t dpll;
6cc5f341 5535 int factor, num_connectors = 0;
09ede541 5536 bool is_lvds = false, is_sdvo = false;
79e53945 5537
de13a2e3
PZ		 5538 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5539 switch (intel_encoder->type) {
79e53945
JB		 5540 case INTEL_OUTPUT_LVDS:
5541 is_lvds = true;
5542 break;
5543 case INTEL_OUTPUT_SDVO:
7d57382e 5544 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5545 is_sdvo = true;
5546 break;
79e53945 5547 }
43565a06 5548
c751ce4f 5549 num_connectors++;
79e53945 5550 }
79e53945 5551
c1858123 5552 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5553 factor = 21;
5554 if (is_lvds) {
5555 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5556 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5557 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5558 factor = 25;
09ede541 5559 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5560 factor = 20;
c1858123 5561
7429e9d4 5562 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5563 *fp |= FP_CB_TUNE;
2c07245f 5564
9a7c7890
DV		 5565 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5566 *fp2 |= FP_CB_TUNE;
5567
5eddb70b 5568 dpll = 0;
2c07245f 5569
a07d6787
EA		 5570 if (is_lvds)
5571 dpll |= DPLLB_MODE_LVDS;
5572 else
5573 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5574
5575 if (intel_crtc->config.pixel_multiplier > 1) {
5576 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5577 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5578 }
198a037f
DV		 5579
5580 if (is_sdvo)
5581 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5582 if (intel_crtc->config.has_dp_encoder)
a07d6787 5583 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5584
a07d6787 5585 /* compute bitmask from p1 value */
7429e9d4 5586 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5587 /* also FPA1 */
7429e9d4 5588 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5589
7429e9d4 5590 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5591 case 5:
5592 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5593 break;
5594 case 7:
5595 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5596 break;
5597 case 10:
5598 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5599 break;
5600 case 14:
5601 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5602 break;
79e53945
JB		 5603 }
5604
b4c09f3b 5605 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5607 else
5608 dpll |= PLL_REF_INPUT_DREFCLK;
5609
de13a2e3
PZ		 5610 return dpll;
5611}
5612
5613static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5614 int x, int y,
5615 struct drm_framebuffer *fb)
5616{
5617 struct drm_device *dev = crtc->dev;
5618 struct drm_i915_private *dev_priv = dev->dev_private;
5619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5620 struct drm_display_mode *adjusted_mode =
5621 &intel_crtc->config.adjusted_mode;
5622 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5623 int pipe = intel_crtc->pipe;
5624 int plane = intel_crtc->plane;
5625 int num_connectors = 0;
5626 intel_clock_t clock, reduced_clock;
cbbab5bd 5627 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5628 bool ok, has_reduced_clock = false;
8b47047b 5629 bool is_lvds = false;
de13a2e3 5630 struct intel_encoder *encoder;
de13a2e3 5631 int ret;
de13a2e3
PZ		 5632
5633 for_each_encoder_on_crtc(dev, crtc, encoder) {
5634 switch (encoder->type) {
5635 case INTEL_OUTPUT_LVDS:
5636 is_lvds = true;
5637 break;
de13a2e3
PZ		 5638 }
5639
5640 num_connectors++;
a07d6787 5641 }
79e53945 5642
5dc5298b
PZ		 5643 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5644 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5645
de13a2e3
PZ		 5646 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5647 &has_reduced_clock, &reduced_clock);
5648 if (!ok) {
5649 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5650 return -EINVAL;
79e53945 5651 }
f47709a9
DV		 5652 /* Compat-code for transition, will disappear. */
5653 if (!intel_crtc->config.clock_set) {
5654 intel_crtc->config.dpll.n = clock.n;
5655 intel_crtc->config.dpll.m1 = clock.m1;
5656 intel_crtc->config.dpll.m2 = clock.m2;
5657 intel_crtc->config.dpll.p1 = clock.p1;
5658 intel_crtc->config.dpll.p2 = clock.p2;
5659 }
79e53945 5660
de13a2e3
PZ		 5661 /* Ensure that the cursor is valid for the new mode before changing... */
5662 intel_crtc_update_cursor(crtc, true);
5663
84f44ce7 5664 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5665 drm_mode_debug_printmodeline(mode);
5666
5dc5298b 5667 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5668 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5669 struct intel_pch_pll *pll;
4b645f14 5670
7429e9d4 5671 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5672 if (has_reduced_clock)
7429e9d4 5673 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5674
7429e9d4 5675 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5676 &fp, &reduced_clock,
5677 has_reduced_clock ? &fp2 : NULL);
5678
ee7b9f93
JB		 5679 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5680 if (pll == NULL) {
84f44ce7
VS		 5681 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5682 pipe_name(pipe));
4b645f14
JB		 5683 return -EINVAL;
5684 }
ee7b9f93
JB		 5685 } else
5686 intel_put_pch_pll(intel_crtc);
79e53945 5687
03afc4a2
DV		 5688 if (intel_crtc->config.has_dp_encoder)
5689 intel_dp_set_m_n(intel_crtc);
79e53945 5690
dafd226c
DV		 5691 for_each_encoder_on_crtc(dev, crtc, encoder)
5692 if (encoder->pre_pll_enable)
5693 encoder->pre_pll_enable(encoder);
79e53945 5694
ee7b9f93
JB		 5695 if (intel_crtc->pch_pll) {
5696 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5697
32f9d658 5698 /* Wait for the clocks to stabilize. */
ee7b9f93 5699 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5700 udelay(150);
5701
8febb297
EA		 5702 /* The pixel multiplier can only be updated once the
5703 * DPLL is enabled and the clocks are stable.
5704 *
5705 * So write it again.
5706 */
ee7b9f93 5707 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5708 }
79e53945 5709
5eddb70b 5710 intel_crtc->lowfreq_avail = false;
ee7b9f93 5711 if (intel_crtc->pch_pll) {
4b645f14 5712 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5713 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5714 intel_crtc->lowfreq_avail = true;
4b645f14 5715 } else {
ee7b9f93 5716 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5717 }
5718 }
5719
b0e77b9c 5720 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5721
ca3a0ff8 5722 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5723 intel_cpu_transcoder_set_m_n(intel_crtc,
5724 &intel_crtc->config.fdi_m_n);
5725 }
2c07245f 5726
ebfd86fd
DV		 5727 if (IS_IVYBRIDGE(dev))
5728 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5729
6ff93609 5730 ironlake_set_pipeconf(crtc);
79e53945 5731
a1f9e77e
PZ		 5732 /* Set up the display plane register */
5733 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5734 POSTING_READ(DSPCNTR(plane));
79e53945 5735
94352cf9 5736 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5737
5738 intel_update_watermarks(dev);
5739
1857e1da 5740 return ret;
79e53945
JB		 5741}
5742
72419203
DV		 5743static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5744 struct intel_crtc_config *pipe_config)
5745{
5746 struct drm_device *dev = crtc->base.dev;
5747 struct drm_i915_private *dev_priv = dev->dev_private;
5748 enum transcoder transcoder = pipe_config->cpu_transcoder;
5749
5750 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5751 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5752 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5753 & ~TU_SIZE_MASK;
5754 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5755 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5756 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5757}
5758
2fa2fe9a
DV		 5759static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5760 struct intel_crtc_config *pipe_config)
5761{
5762 struct drm_device *dev = crtc->base.dev;
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764 uint32_t tmp;
5765
5766 tmp = I915_READ(PF_CTL(crtc->pipe));
5767
5768 if (tmp & PF_ENABLE) {
5769 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5770 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5771 }
5772}
5773
0e8ffe1b
DV		 5774static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5775 struct intel_crtc_config *pipe_config)
5776{
5777 struct drm_device *dev = crtc->base.dev;
5778 struct drm_i915_private *dev_priv = dev->dev_private;
5779 uint32_t tmp;
5780
eccb140b
DV		 5781 pipe_config->cpu_transcoder = crtc->pipe;
5782
0e8ffe1b
DV		 5783 tmp = I915_READ(PIPECONF(crtc->pipe));
5784 if (!(tmp & PIPECONF_ENABLE))
5785 return false;
5786
ab9412ba 5787 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5788 pipe_config->has_pch_encoder = true;
5789
627eb5a3
DV		 5790 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5791 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5792 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5793
5794 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5795 }
5796
1bd1bd80
DV		 5797 intel_get_pipe_timings(crtc, pipe_config);
5798
2fa2fe9a
DV		 5799 ironlake_get_pfit_config(crtc, pipe_config);
5800
0e8ffe1b
DV		 5801 return true;
5802}
5803
d6dd9eb1
DV		 5804static void haswell_modeset_global_resources(struct drm_device *dev)
5805{
d6dd9eb1
DV		 5806 bool enable = false;
5807 struct intel_crtc *crtc;
5808 struct intel_encoder *encoder;
5809
5810 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5811 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5812 enable = true;
5813 /* XXX: Should check for edp transcoder here, but thanks to init
5814 * sequence that's not yet available. Just in case desktop eDP
5815 * on PORT D is possible on haswell, too. */
b074cec8 5816 /* Even the eDP panel fitter is outside the always-on well. */
2b87f3b1 5817 if (crtc->config.pch_pfit.size && crtc->base.enabled)
b074cec8 5818 enable = true;
d6dd9eb1
DV		 5819 }
5820
5821 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5822 base.head) {
5823 if (encoder->type != INTEL_OUTPUT_EDP &&
5824 encoder->connectors_active)
5825 enable = true;
5826 }
5827
d6dd9eb1
DV		 5828 intel_set_power_well(dev, enable);
5829}
5830
09b4ddf9 5831static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5832 int x, int y,
5833 struct drm_framebuffer *fb)
5834{
5835 struct drm_device *dev = crtc->dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5838 struct drm_display_mode *adjusted_mode =
5839 &intel_crtc->config.adjusted_mode;
5840 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5841 int pipe = intel_crtc->pipe;
5842 int plane = intel_crtc->plane;
5843 int num_connectors = 0;
8b47047b 5844 bool is_cpu_edp = false;
09b4ddf9 5845 struct intel_encoder *encoder;
09b4ddf9 5846 int ret;
09b4ddf9
PZ		 5847
5848 for_each_encoder_on_crtc(dev, crtc, encoder) {
5849 switch (encoder->type) {
09b4ddf9 5850 case INTEL_OUTPUT_EDP:
d8e8b582 5851 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5852 is_cpu_edp = true;
5853 break;
5854 }
5855
5856 num_connectors++;
5857 }
5858
5dc5298b
PZ		 5859 /* We are not sure yet this won't happen. */
5860 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5861 INTEL_PCH_TYPE(dev));
5862
5863 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5864 num_connectors, pipe_name(pipe));
5865
3b117c8f 5866 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5867 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5868
5869 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5870
6441ab5f
PZ		 5871 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5872 return -EINVAL;
5873
09b4ddf9
PZ		 5874 /* Ensure that the cursor is valid for the new mode before changing... */
5875 intel_crtc_update_cursor(crtc, true);
5876
84f44ce7 5877 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5878 drm_mode_debug_printmodeline(mode);
5879
03afc4a2
DV		 5880 if (intel_crtc->config.has_dp_encoder)
5881 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5882
5883 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5884
5885 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5886
ca3a0ff8 5887 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5888 intel_cpu_transcoder_set_m_n(intel_crtc,
5889 &intel_crtc->config.fdi_m_n);
5890 }
09b4ddf9 5891
6ff93609 5892 haswell_set_pipeconf(crtc);
09b4ddf9 5893
50f3b016 5894 intel_set_pipe_csc(crtc);
86d3efce 5895
09b4ddf9 5896 /* Set up the display plane register */
86d3efce 5897 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5898 POSTING_READ(DSPCNTR(plane));
5899
5900 ret = intel_pipe_set_base(crtc, x, y, fb);
5901
5902 intel_update_watermarks(dev);
5903
1f803ee5 5904 return ret;
79e53945
JB		 5905}
5906
0e8ffe1b
DV		 5907static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5908 struct intel_crtc_config *pipe_config)
5909{
5910 struct drm_device *dev = crtc->base.dev;
5911 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5912 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5913 uint32_t tmp;
5914
eccb140b
DV		 5915 pipe_config->cpu_transcoder = crtc->pipe;
5916 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5917 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5918 enum pipe trans_edp_pipe;
5919 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5920 default:
5921 WARN(1, "unknown pipe linked to edp transcoder\n");
5922 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5923 case TRANS_DDI_EDP_INPUT_A_ON:
5924 trans_edp_pipe = PIPE_A;
5925 break;
5926 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5927 trans_edp_pipe = PIPE_B;
5928 break;
5929 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5930 trans_edp_pipe = PIPE_C;
5931 break;
5932 }
5933
5934 if (trans_edp_pipe == crtc->pipe)
5935 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5936 }
5937
b97186f0 5938 if (!intel_display_power_enabled(dev,
eccb140b 5939 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5940 return false;
5941
eccb140b 5942 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5943 if (!(tmp & PIPECONF_ENABLE))
5944 return false;
5945
88adfff1 5946 /*
f196e6be 5947 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5948 * DDI E. So just check whether this pipe is wired to DDI E and whether
5949 * the PCH transcoder is on.
5950 */
eccb140b 5951 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5952 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5953 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5954 pipe_config->has_pch_encoder = true;
5955
627eb5a3
DV		 5956 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5957 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5958 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5959
5960 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5961 }
5962
1bd1bd80
DV		 5963 intel_get_pipe_timings(crtc, pipe_config);
5964
2fa2fe9a
DV		 5965 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5966 if (intel_display_power_enabled(dev, pfit_domain))
5967 ironlake_get_pfit_config(crtc, pipe_config);
5968
0e8ffe1b
DV		 5969 return true;
5970}
5971
f564048e 5972static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5973 int x, int y,
94352cf9 5974 struct drm_framebuffer *fb)
f564048e
EA		 5975{
5976 struct drm_device *dev = crtc->dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5978 struct drm_encoder_helper_funcs *encoder_funcs;
5979 struct intel_encoder *encoder;
0b701d27 5980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5981 struct drm_display_mode *adjusted_mode =
5982 &intel_crtc->config.adjusted_mode;
5983 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5984 int pipe = intel_crtc->pipe;
f564048e
EA		 5985 int ret;
5986
0b701d27 5987 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5988
b8cecdf5
DV		 5989 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5990
79e53945 5991 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5992
9256aa19
DV		 5993 if (ret != 0)
5994 return ret;
5995
5996 for_each_encoder_on_crtc(dev, crtc, encoder) {
5997 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5998 encoder->base.base.id,
5999 drm_get_encoder_name(&encoder->base),
6000 mode->base.id, mode->name);
6cc5f341
DV		 6001 if (encoder->mode_set) {
6002 encoder->mode_set(encoder);
6003 } else {
6004 encoder_funcs = encoder->base.helper_private;
6005 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6006 }
9256aa19
DV		 6007 }
6008
6009 return 0;
79e53945
JB		 6010}
6011
3a9627f4
WF		 6012static bool intel_eld_uptodate(struct drm_connector *connector,
6013 int reg_eldv, uint32_t bits_eldv,
6014 int reg_elda, uint32_t bits_elda,
6015 int reg_edid)
6016{
6017 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6018 uint8_t *eld = connector->eld;
6019 uint32_t i;
6020
6021 i = I915_READ(reg_eldv);
6022 i &= bits_eldv;
6023
6024 if (!eld[0])
6025 return !i;
6026
6027 if (!i)
6028 return false;
6029
6030 i = I915_READ(reg_elda);
6031 i &= ~bits_elda;
6032 I915_WRITE(reg_elda, i);
6033
6034 for (i = 0; i < eld[2]; i++)
6035 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6036 return false;
6037
6038 return true;
6039}
6040
e0dac65e
WF		 6041static void g4x_write_eld(struct drm_connector *connector,
6042 struct drm_crtc *crtc)
6043{
6044 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6045 uint8_t *eld = connector->eld;
6046 uint32_t eldv;
6047 uint32_t len;
6048 uint32_t i;
6049
6050 i = I915_READ(G4X_AUD_VID_DID);
6051
6052 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6053 eldv = G4X_ELDV_DEVCL_DEVBLC;
6054 else
6055 eldv = G4X_ELDV_DEVCTG;
6056
3a9627f4
WF		 6057 if (intel_eld_uptodate(connector,
6058 G4X_AUD_CNTL_ST, eldv,
6059 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6060 G4X_HDMIW_HDMIEDID))
6061 return;
6062
e0dac65e
WF		 6063 i = I915_READ(G4X_AUD_CNTL_ST);
6064 i &= ~(eldv | G4X_ELD_ADDR);
6065 len = (i >> 9) & 0x1f; /* ELD buffer size */
6066 I915_WRITE(G4X_AUD_CNTL_ST, i);
6067
6068 if (!eld[0])
6069 return;
6070
6071 len = min_t(uint8_t, eld[2], len);
6072 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6073 for (i = 0; i < len; i++)
6074 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6075
6076 i = I915_READ(G4X_AUD_CNTL_ST);
6077 i |= eldv;
6078 I915_WRITE(G4X_AUD_CNTL_ST, i);
6079}
6080
83358c85
WX		 6081static void haswell_write_eld(struct drm_connector *connector,
6082 struct drm_crtc *crtc)
6083{
6084 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6085 uint8_t *eld = connector->eld;
6086 struct drm_device *dev = crtc->dev;
7b9f35a6 6087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6088 uint32_t eldv;
6089 uint32_t i;
6090 int len;
6091 int pipe = to_intel_crtc(crtc)->pipe;
6092 int tmp;
6093
6094 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6095 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6096 int aud_config = HSW_AUD_CFG(pipe);
6097 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6098
6099
6100 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6101
6102 /* Audio output enable */
6103 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6104 tmp = I915_READ(aud_cntrl_st2);
6105 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6106 I915_WRITE(aud_cntrl_st2, tmp);
6107
6108 /* Wait for 1 vertical blank */
6109 intel_wait_for_vblank(dev, pipe);
6110
6111 /* Set ELD valid state */
6112 tmp = I915_READ(aud_cntrl_st2);
6113 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6114 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6115 I915_WRITE(aud_cntrl_st2, tmp);
6116 tmp = I915_READ(aud_cntrl_st2);
6117 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6118
6119 /* Enable HDMI mode */
6120 tmp = I915_READ(aud_config);
6121 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6122 /* clear N_programing_enable and N_value_index */
6123 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6124 I915_WRITE(aud_config, tmp);
6125
6126 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6127
6128 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6129 intel_crtc->eld_vld = true;
83358c85
WX		 6130
6131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6132 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6133 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6134 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6135 } else
6136 I915_WRITE(aud_config, 0);
6137
6138 if (intel_eld_uptodate(connector,
6139 aud_cntrl_st2, eldv,
6140 aud_cntl_st, IBX_ELD_ADDRESS,
6141 hdmiw_hdmiedid))
6142 return;
6143
6144 i = I915_READ(aud_cntrl_st2);
6145 i &= ~eldv;
6146 I915_WRITE(aud_cntrl_st2, i);
6147
6148 if (!eld[0])
6149 return;
6150
6151 i = I915_READ(aud_cntl_st);
6152 i &= ~IBX_ELD_ADDRESS;
6153 I915_WRITE(aud_cntl_st, i);
6154 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6155 DRM_DEBUG_DRIVER("port num:%d\n", i);
6156
6157 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6158 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6159 for (i = 0; i < len; i++)
6160 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6161
6162 i = I915_READ(aud_cntrl_st2);
6163 i |= eldv;
6164 I915_WRITE(aud_cntrl_st2, i);
6165
6166}
6167
e0dac65e
WF		 6168static void ironlake_write_eld(struct drm_connector *connector,
6169 struct drm_crtc *crtc)
6170{
6171 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6172 uint8_t *eld = connector->eld;
6173 uint32_t eldv;
6174 uint32_t i;
6175 int len;
6176 int hdmiw_hdmiedid;
b6daa025 6177 int aud_config;
e0dac65e
WF		 6178 int aud_cntl_st;
6179 int aud_cntrl_st2;
9b138a83 6180 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6181
b3f33cbf 6182 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6183 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6184 aud_config = IBX_AUD_CFG(pipe);
6185 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6186 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6187 } else {
9b138a83
WX		 6188 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6189 aud_config = CPT_AUD_CFG(pipe);
6190 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6191 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6192 }
6193
9b138a83 6194 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6195
6196 i = I915_READ(aud_cntl_st);
9b138a83 6197 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6198 if (!i) {
6199 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6200 /* operate blindly on all ports */
1202b4c6
WF		 6201 eldv = IBX_ELD_VALIDB;
6202 eldv |= IBX_ELD_VALIDB << 4;
6203 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6204 } else {
2582a850 6205 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6206 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6207 }
6208
3a9627f4
WF		 6209 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6210 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6211 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6212 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6213 } else
6214 I915_WRITE(aud_config, 0);
e0dac65e 6215
3a9627f4
WF		 6216 if (intel_eld_uptodate(connector,
6217 aud_cntrl_st2, eldv,
6218 aud_cntl_st, IBX_ELD_ADDRESS,
6219 hdmiw_hdmiedid))
6220 return;
6221
e0dac65e
WF		 6222 i = I915_READ(aud_cntrl_st2);
6223 i &= ~eldv;
6224 I915_WRITE(aud_cntrl_st2, i);
6225
6226 if (!eld[0])
6227 return;
6228
e0dac65e 6229 i = I915_READ(aud_cntl_st);
1202b4c6 6230 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6231 I915_WRITE(aud_cntl_st, i);
6232
6233 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6234 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6235 for (i = 0; i < len; i++)
6236 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6237
6238 i = I915_READ(aud_cntrl_st2);
6239 i |= eldv;
6240 I915_WRITE(aud_cntrl_st2, i);
6241}
6242
6243void intel_write_eld(struct drm_encoder *encoder,
6244 struct drm_display_mode *mode)
6245{
6246 struct drm_crtc *crtc = encoder->crtc;
6247 struct drm_connector *connector;
6248 struct drm_device *dev = encoder->dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250
6251 connector = drm_select_eld(encoder, mode);
6252 if (!connector)
6253 return;
6254
6255 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6256 connector->base.id,
6257 drm_get_connector_name(connector),
6258 connector->encoder->base.id,
6259 drm_get_encoder_name(connector->encoder));
6260
6261 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6262
6263 if (dev_priv->display.write_eld)
6264 dev_priv->display.write_eld(connector, crtc);
6265}
6266
79e53945
JB		 6267/** Loads the palette/gamma unit for the CRTC with the prepared values */
6268void intel_crtc_load_lut(struct drm_crtc *crtc)
6269{
6270 struct drm_device *dev = crtc->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6273 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6274 int i;
6275
6276 /* The clocks have to be on to load the palette. */
aed3f09d 6277 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6278 return;
6279
f2b115e6 6280 /* use legacy palette for Ironlake */
bad720ff 6281 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6282 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6283
79e53945
JB		 6284 for (i = 0; i < 256; i++) {
6285 I915_WRITE(palreg + 4 * i,
6286 (intel_crtc->lut_r[i] << 16) |
6287 (intel_crtc->lut_g[i] << 8) |
6288 intel_crtc->lut_b[i]);
6289 }
6290}
6291
560b85bb
CW		 6292static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6293{
6294 struct drm_device *dev = crtc->dev;
6295 struct drm_i915_private *dev_priv = dev->dev_private;
6296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6297 bool visible = base != 0;
6298 u32 cntl;
6299
6300 if (intel_crtc->cursor_visible == visible)
6301 return;
6302
9db4a9c7 6303 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6304 if (visible) {
6305 /* On these chipsets we can only modify the base whilst
6306 * the cursor is disabled.
6307 */
9db4a9c7 6308 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6309
6310 cntl &= ~(CURSOR_FORMAT_MASK);
6311 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6312 cntl |= CURSOR_ENABLE |
6313 CURSOR_GAMMA_ENABLE |
6314 CURSOR_FORMAT_ARGB;
6315 } else
6316 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6317 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6318
6319 intel_crtc->cursor_visible = visible;
6320}
6321
6322static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6323{
6324 struct drm_device *dev = crtc->dev;
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6327 int pipe = intel_crtc->pipe;
6328 bool visible = base != 0;
6329
6330 if (intel_crtc->cursor_visible != visible) {
548f245b 6331 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6332 if (base) {
6333 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6334 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6335 cntl |= pipe << 28; /* Connect to correct pipe */
6336 } else {
6337 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6338 cntl |= CURSOR_MODE_DISABLE;
6339 }
9db4a9c7 6340 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6341
6342 intel_crtc->cursor_visible = visible;
6343 }
6344 /* and commit changes on next vblank */
9db4a9c7 6345 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6346}
6347
65a21cd6
JB		 6348static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6349{
6350 struct drm_device *dev = crtc->dev;
6351 struct drm_i915_private *dev_priv = dev->dev_private;
6352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6353 int pipe = intel_crtc->pipe;
6354 bool visible = base != 0;
6355
6356 if (intel_crtc->cursor_visible != visible) {
6357 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6358 if (base) {
6359 cntl &= ~CURSOR_MODE;
6360 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6361 } else {
6362 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6363 cntl |= CURSOR_MODE_DISABLE;
6364 }
86d3efce
VS		 6365 if (IS_HASWELL(dev))
6366 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6367 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6368
6369 intel_crtc->cursor_visible = visible;
6370 }
6371 /* and commit changes on next vblank */
6372 I915_WRITE(CURBASE_IVB(pipe), base);
6373}
6374
cda4b7d3 6375/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6376static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6377 bool on)
cda4b7d3
CW		 6378{
6379 struct drm_device *dev = crtc->dev;
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382 int pipe = intel_crtc->pipe;
6383 int x = intel_crtc->cursor_x;
6384 int y = intel_crtc->cursor_y;
560b85bb 6385 u32 base, pos;
cda4b7d3
CW		 6386 bool visible;
6387
6388 pos = 0;
6389
6b383a7f 6390 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6391 base = intel_crtc->cursor_addr;
6392 if (x > (int) crtc->fb->width)
6393 base = 0;
6394
6395 if (y > (int) crtc->fb->height)
6396 base = 0;
6397 } else
6398 base = 0;
6399
6400 if (x < 0) {
6401 if (x + intel_crtc->cursor_width < 0)
6402 base = 0;
6403
6404 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6405 x = -x;
6406 }
6407 pos |= x << CURSOR_X_SHIFT;
6408
6409 if (y < 0) {
6410 if (y + intel_crtc->cursor_height < 0)
6411 base = 0;
6412
6413 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6414 y = -y;
6415 }
6416 pos |= y << CURSOR_Y_SHIFT;
6417
6418 visible = base != 0;
560b85bb 6419 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6420 return;
6421
0cd83aa9 6422 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6423 I915_WRITE(CURPOS_IVB(pipe), pos);
6424 ivb_update_cursor(crtc, base);
6425 } else {
6426 I915_WRITE(CURPOS(pipe), pos);
6427 if (IS_845G(dev) || IS_I865G(dev))
6428 i845_update_cursor(crtc, base);
6429 else
6430 i9xx_update_cursor(crtc, base);
6431 }
cda4b7d3
CW		 6432}
6433
79e53945 6434static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6435 struct drm_file *file,
79e53945
JB		 6436 uint32_t handle,
6437 uint32_t width, uint32_t height)
6438{
6439 struct drm_device *dev = crtc->dev;
6440 struct drm_i915_private *dev_priv = dev->dev_private;
6441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6442 struct drm_i915_gem_object *obj;
cda4b7d3 6443 uint32_t addr;
3f8bc370 6444 int ret;
79e53945 6445
79e53945
JB		 6446 /* if we want to turn off the cursor ignore width and height */
6447 if (!handle) {
28c97730 6448 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6449 addr = 0;
05394f39 6450 obj = NULL;
5004417d 6451 mutex_lock(&dev->struct_mutex);
3f8bc370 6452 goto finish;
79e53945
JB		 6453 }
6454
6455 /* Currently we only support 64x64 cursors */
6456 if (width != 64 || height != 64) {
6457 DRM_ERROR("we currently only support 64x64 cursors\n");
6458 return -EINVAL;
6459 }
6460
05394f39 6461 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6462 if (&obj->base == NULL)
79e53945
JB		 6463 return -ENOENT;
6464
05394f39 6465 if (obj->base.size < width * height * 4) {
79e53945 6466 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6467 ret = -ENOMEM;
6468 goto fail;
79e53945
JB		 6469 }
6470
71acb5eb 6471 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6472 mutex_lock(&dev->struct_mutex);
b295d1b6 6473 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6474 unsigned alignment;
6475
d9e86c0e
CW		 6476 if (obj->tiling_mode) {
6477 DRM_ERROR("cursor cannot be tiled\n");
6478 ret = -EINVAL;
6479 goto fail_locked;
6480 }
6481
693db184
CW		 6482 /* Note that the w/a also requires 2 PTE of padding following
6483 * the bo. We currently fill all unused PTE with the shadow
6484 * page and so we should always have valid PTE following the
6485 * cursor preventing the VT-d warning.
6486 */
6487 alignment = 0;
6488 if (need_vtd_wa(dev))
6489 alignment = 64*1024;
6490
6491 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6492 if (ret) {
6493 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6494 goto fail_locked;
e7b526bb
CW		 6495 }
6496
d9e86c0e
CW		 6497 ret = i915_gem_object_put_fence(obj);
6498 if (ret) {
2da3b9b9 6499 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6500 goto fail_unpin;
6501 }
6502
05394f39 6503 addr = obj->gtt_offset;
71acb5eb 6504 } else {
6eeefaf3 6505 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6506 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6507 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6508 align);
71acb5eb
DA		 6509 if (ret) {
6510 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6511 goto fail_locked;
71acb5eb 6512 }
05394f39 6513 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6514 }
6515
a6c45cf0 6516 if (IS_GEN2(dev))
14b60391
JB		 6517 I915_WRITE(CURSIZE, (height << 12) | width);
6518
3f8bc370 6519 finish:
3f8bc370 6520 if (intel_crtc->cursor_bo) {
b295d1b6 6521 if (dev_priv->info->cursor_needs_physical) {
05394f39 6522 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6523 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6524 } else
6525 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6526 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6527 }
80824003 6528
7f9872e0 6529 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6530
6531 intel_crtc->cursor_addr = addr;
05394f39 6532 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6533 intel_crtc->cursor_width = width;
6534 intel_crtc->cursor_height = height;
6535
6b383a7f 6536 intel_crtc_update_cursor(crtc, true);
3f8bc370 6537
79e53945 6538 return 0;
e7b526bb 6539fail_unpin:
05394f39 6540 i915_gem_object_unpin(obj);
7f9872e0 6541fail_locked:
34b8686e 6542 mutex_unlock(&dev->struct_mutex);
bc9025bd 6543fail:
05394f39 6544 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6545 return ret;
79e53945
JB		 6546}
6547
6548static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6549{
79e53945 6550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6551
cda4b7d3
CW		 6552 intel_crtc->cursor_x = x;
6553 intel_crtc->cursor_y = y;
652c393a 6554
6b383a7f 6555 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6556
6557 return 0;
6558}
6559
6560/** Sets the color ramps on behalf of RandR */
6561void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6562 u16 blue, int regno)
6563{
6564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6565
6566 intel_crtc->lut_r[regno] = red >> 8;
6567 intel_crtc->lut_g[regno] = green >> 8;
6568 intel_crtc->lut_b[regno] = blue >> 8;
6569}
6570
b8c00ac5
DA		 6571void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6572 u16 *blue, int regno)
6573{
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575
6576 *red = intel_crtc->lut_r[regno] << 8;
6577 *green = intel_crtc->lut_g[regno] << 8;
6578 *blue = intel_crtc->lut_b[regno] << 8;
6579}
6580
79e53945 6581static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6582 u16 *blue, uint32_t start, uint32_t size)
79e53945 6583{
7203425a 6584 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6586
7203425a 6587 for (i = start; i < end; i++) {
79e53945
JB		 6588 intel_crtc->lut_r[i] = red[i] >> 8;
6589 intel_crtc->lut_g[i] = green[i] >> 8;
6590 intel_crtc->lut_b[i] = blue[i] >> 8;
6591 }
6592
6593 intel_crtc_load_lut(crtc);
6594}
6595
79e53945
JB		 6596/* VESA 640x480x72Hz mode to set on the pipe */
6597static struct drm_display_mode load_detect_mode = {
6598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6600};
6601
d2dff872
CW		 6602static struct drm_framebuffer *
6603intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6604 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6605 struct drm_i915_gem_object *obj)
6606{
6607 struct intel_framebuffer *intel_fb;
6608 int ret;
6609
6610 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6611 if (!intel_fb) {
6612 drm_gem_object_unreference_unlocked(&obj->base);
6613 return ERR_PTR(-ENOMEM);
6614 }
6615
6616 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6617 if (ret) {
6618 drm_gem_object_unreference_unlocked(&obj->base);
6619 kfree(intel_fb);
6620 return ERR_PTR(ret);
6621 }
6622
6623 return &intel_fb->base;
6624}
6625
6626static u32
6627intel_framebuffer_pitch_for_width(int width, int bpp)
6628{
6629 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6630 return ALIGN(pitch, 64);
6631}
6632
6633static u32
6634intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6635{
6636 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6637 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6638}
6639
6640static struct drm_framebuffer *
6641intel_framebuffer_create_for_mode(struct drm_device *dev,
6642 struct drm_display_mode *mode,
6643 int depth, int bpp)
6644{
6645 struct drm_i915_gem_object *obj;
0fed39bd 6646 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6647
6648 obj = i915_gem_alloc_object(dev,
6649 intel_framebuffer_size_for_mode(mode, bpp));
6650 if (obj == NULL)
6651 return ERR_PTR(-ENOMEM);
6652
6653 mode_cmd.width = mode->hdisplay;
6654 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6655 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6656 bpp);
5ca0c34a 6657 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6658
6659 return intel_framebuffer_create(dev, &mode_cmd, obj);
6660}
6661
6662static struct drm_framebuffer *
6663mode_fits_in_fbdev(struct drm_device *dev,
6664 struct drm_display_mode *mode)
6665{
6666 struct drm_i915_private *dev_priv = dev->dev_private;
6667 struct drm_i915_gem_object *obj;
6668 struct drm_framebuffer *fb;
6669
6670 if (dev_priv->fbdev == NULL)
6671 return NULL;
6672
6673 obj = dev_priv->fbdev->ifb.obj;
6674 if (obj == NULL)
6675 return NULL;
6676
6677 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6678 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6679 fb->bits_per_pixel))
d2dff872
CW		 6680 return NULL;
6681
01f2c773 6682 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6683 return NULL;
6684
6685 return fb;
6686}
6687
d2434ab7 6688bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6689 struct drm_display_mode *mode,
8261b191 6690 struct intel_load_detect_pipe *old)
79e53945
JB		 6691{
6692 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6693 struct intel_encoder *intel_encoder =
6694 intel_attached_encoder(connector);
79e53945 6695 struct drm_crtc *possible_crtc;
4ef69c7a 6696 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6697 struct drm_crtc *crtc = NULL;
6698 struct drm_device *dev = encoder->dev;
94352cf9 6699 struct drm_framebuffer *fb;
79e53945
JB		 6700 int i = -1;
6701
d2dff872
CW		 6702 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6703 connector->base.id, drm_get_connector_name(connector),
6704 encoder->base.id, drm_get_encoder_name(encoder));
6705
79e53945
JB		 6706 /*
6707 * Algorithm gets a little messy:
7a5e4805 6708 *
79e53945
JB		 6709 * - if the connector already has an assigned crtc, use it (but make
6710 * sure it's on first)
7a5e4805 6711 *
79e53945
JB		 6712 * - try to find the first unused crtc that can drive this connector,
6713 * and use that if we find one
79e53945
JB		 6714 */
6715
6716 /* See if we already have a CRTC for this connector */
6717 if (encoder->crtc) {
6718 crtc = encoder->crtc;
8261b191 6719
7b24056b
DV		 6720 mutex_lock(&crtc->mutex);
6721
24218aac 6722 old->dpms_mode = connector->dpms;
8261b191
CW		 6723 old->load_detect_temp = false;
6724
6725 /* Make sure the crtc and connector are running */
24218aac
DV		 6726 if (connector->dpms != DRM_MODE_DPMS_ON)
6727 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6728
7173188d 6729 return true;
79e53945
JB		 6730 }
6731
6732 /* Find an unused one (if possible) */
6733 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6734 i++;
6735 if (!(encoder->possible_crtcs & (1 << i)))
6736 continue;
6737 if (!possible_crtc->enabled) {
6738 crtc = possible_crtc;
6739 break;
6740 }
79e53945
JB		 6741 }
6742
6743 /*
6744 * If we didn't find an unused CRTC, don't use any.
6745 */
6746 if (!crtc) {
7173188d
CW		 6747 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6748 return false;
79e53945
JB		 6749 }
6750
7b24056b 6751 mutex_lock(&crtc->mutex);
fc303101
DV		 6752 intel_encoder->new_crtc = to_intel_crtc(crtc);
6753 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6754
6755 intel_crtc = to_intel_crtc(crtc);
24218aac 6756 old->dpms_mode = connector->dpms;
8261b191 6757 old->load_detect_temp = true;
d2dff872 6758 old->release_fb = NULL;
79e53945 6759
6492711d
CW		 6760 if (!mode)
6761 mode = &load_detect_mode;
79e53945 6762
d2dff872
CW		 6763 /* We need a framebuffer large enough to accommodate all accesses
6764 * that the plane may generate whilst we perform load detection.
6765 * We can not rely on the fbcon either being present (we get called
6766 * during its initialisation to detect all boot displays, or it may
6767 * not even exist) or that it is large enough to satisfy the
6768 * requested mode.
6769 */
94352cf9
DV		 6770 fb = mode_fits_in_fbdev(dev, mode);
6771 if (fb == NULL) {
d2dff872 6772 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6773 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6774 old->release_fb = fb;
d2dff872
CW		 6775 } else
6776 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6777 if (IS_ERR(fb)) {
d2dff872 6778 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6779 mutex_unlock(&crtc->mutex);
0e8b3d3e 6780 return false;
79e53945 6781 }
79e53945 6782
c0c36b94 6783 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6784 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6785 if (old->release_fb)
6786 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6787 mutex_unlock(&crtc->mutex);
0e8b3d3e 6788 return false;
79e53945 6789 }
7173188d 6790
79e53945 6791 /* let the connector get through one full cycle before testing */
9d0498a2 6792 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6793 return true;
79e53945
JB		 6794}
6795
d2434ab7 6796void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6797 struct intel_load_detect_pipe *old)
79e53945 6798{
d2434ab7
DV		 6799 struct intel_encoder *intel_encoder =
6800 intel_attached_encoder(connector);
4ef69c7a 6801 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6802 struct drm_crtc *crtc = encoder->crtc;
79e53945 6803
d2dff872
CW		 6804 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6805 connector->base.id, drm_get_connector_name(connector),
6806 encoder->base.id, drm_get_encoder_name(encoder));
6807
8261b191 6808 if (old->load_detect_temp) {
fc303101
DV		 6809 to_intel_connector(connector)->new_encoder = NULL;
6810 intel_encoder->new_crtc = NULL;
6811 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6812
36206361
DV		 6813 if (old->release_fb) {
6814 drm_framebuffer_unregister_private(old->release_fb);
6815 drm_framebuffer_unreference(old->release_fb);
6816 }
d2dff872 6817
67c96400 6818 mutex_unlock(&crtc->mutex);
0622a53c 6819 return;
79e53945
JB		 6820 }
6821
c751ce4f 6822 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6823 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6824 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6825
6826 mutex_unlock(&crtc->mutex);
79e53945
JB		 6827}
6828
6829/* Returns the clock of the currently programmed mode of the given pipe. */
6830static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6831{
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6834 int pipe = intel_crtc->pipe;
548f245b 6835 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6836 u32 fp;
6837 intel_clock_t clock;
6838
6839 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6840 fp = I915_READ(FP0(pipe));
79e53945 6841 else
39adb7a5 6842 fp = I915_READ(FP1(pipe));
79e53945
JB		 6843
6844 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6845 if (IS_PINEVIEW(dev)) {
6846 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6847 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6848 } else {
6849 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6850 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6851 }
6852
a6c45cf0 6853 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6854 if (IS_PINEVIEW(dev))
6855 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6856 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6857 else
6858 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6859 DPLL_FPA01_P1_POST_DIV_SHIFT);
6860
6861 switch (dpll & DPLL_MODE_MASK) {
6862 case DPLLB_MODE_DAC_SERIAL:
6863 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6864 5 : 10;
6865 break;
6866 case DPLLB_MODE_LVDS:
6867 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6868 7 : 14;
6869 break;
6870 default:
28c97730 6871 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6872 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6873 return 0;
6874 }
6875
6876 /* XXX: Handle the 100Mhz refclk */
2177832f 6877 intel_clock(dev, 96000, &clock);
79e53945
JB		 6878 } else {
6879 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6880
6881 if (is_lvds) {
6882 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6883 DPLL_FPA01_P1_POST_DIV_SHIFT);
6884 clock.p2 = 14;
6885
6886 if ((dpll & PLL_REF_INPUT_MASK) ==
6887 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6888 /* XXX: might not be 66MHz */
2177832f 6889 intel_clock(dev, 66000, &clock);
79e53945 6890 } else
2177832f 6891 intel_clock(dev, 48000, &clock);
79e53945
JB		 6892 } else {
6893 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6894 clock.p1 = 2;
6895 else {
6896 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6897 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6898 }
6899 if (dpll & PLL_P2_DIVIDE_BY_4)
6900 clock.p2 = 4;
6901 else
6902 clock.p2 = 2;
6903
2177832f 6904 intel_clock(dev, 48000, &clock);
79e53945
JB		 6905 }
6906 }
6907
6908 /* XXX: It would be nice to validate the clocks, but we can't reuse
6909 * i830PllIsValid() because it relies on the xf86_config connector
6910 * configuration being accurate, which it isn't necessarily.
6911 */
6912
6913 return clock.dot;
6914}
6915
6916/** Returns the currently programmed mode of the given pipe. */
6917struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6918 struct drm_crtc *crtc)
6919{
548f245b 6920 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6922 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6923 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6924 int htot = I915_READ(HTOTAL(cpu_transcoder));
6925 int hsync = I915_READ(HSYNC(cpu_transcoder));
6926 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6927 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6928
6929 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6930 if (!mode)
6931 return NULL;
6932
6933 mode->clock = intel_crtc_clock_get(dev, crtc);
6934 mode->hdisplay = (htot & 0xffff) + 1;
6935 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6936 mode->hsync_start = (hsync & 0xffff) + 1;
6937 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6938 mode->vdisplay = (vtot & 0xffff) + 1;
6939 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6940 mode->vsync_start = (vsync & 0xffff) + 1;
6941 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6942
6943 drm_mode_set_name(mode);
79e53945
JB		 6944
6945 return mode;
6946}
6947
3dec0095 6948static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6949{
6950 struct drm_device *dev = crtc->dev;
6951 drm_i915_private_t *dev_priv = dev->dev_private;
6952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6953 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6954 int dpll_reg = DPLL(pipe);
6955 int dpll;
652c393a 6956
bad720ff 6957 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6958 return;
6959
6960 if (!dev_priv->lvds_downclock_avail)
6961 return;
6962
dbdc6479 6963 dpll = I915_READ(dpll_reg);
652c393a 6964 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6965 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6966
8ac5a6d5 6967 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6968
6969 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6970 I915_WRITE(dpll_reg, dpll);
9d0498a2 6971 intel_wait_for_vblank(dev, pipe);
dbdc6479 6972
652c393a
JB		 6973 dpll = I915_READ(dpll_reg);
6974 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6975 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6976 }
652c393a
JB		 6977}
6978
6979static void intel_decrease_pllclock(struct drm_crtc *crtc)
6980{
6981 struct drm_device *dev = crtc->dev;
6982 drm_i915_private_t *dev_priv = dev->dev_private;
6983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6984
bad720ff 6985 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6986 return;
6987
6988 if (!dev_priv->lvds_downclock_avail)
6989 return;
6990
6991 /*
6992 * Since this is called by a timer, we should never get here in
6993 * the manual case.
6994 */
6995 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6996 int pipe = intel_crtc->pipe;
6997 int dpll_reg = DPLL(pipe);
6998 int dpll;
f6e5b160 6999
44d98a61 7000 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7001
8ac5a6d5 7002 assert_panel_unlocked(dev_priv, pipe);
652c393a 7003
dc257cf1 7004 dpll = I915_READ(dpll_reg);
652c393a
JB		 7005 dpll |= DISPLAY_RATE_SELECT_FPA1;
7006 I915_WRITE(dpll_reg, dpll);
9d0498a2 7007 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7008 dpll = I915_READ(dpll_reg);
7009 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7010 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7011 }
7012
7013}
7014
f047e395
CW		 7015void intel_mark_busy(struct drm_device *dev)
7016{
f047e395
CW		 7017 i915_update_gfx_val(dev->dev_private);
7018}
7019
7020void intel_mark_idle(struct drm_device *dev)
652c393a 7021{
652c393a 7022 struct drm_crtc *crtc;
652c393a
JB		 7023
7024 if (!i915_powersave)
7025 return;
7026
652c393a 7027 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7028 if (!crtc->fb)
7029 continue;
7030
725a5b54 7031 intel_decrease_pllclock(crtc);
652c393a 7032 }
652c393a
JB		 7033}
7034
725a5b54 7035void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7036{
f047e395
CW		 7037 struct drm_device *dev = obj->base.dev;
7038 struct drm_crtc *crtc;
652c393a 7039
f047e395 7040 if (!i915_powersave)
acb87dfb
CW		 7041 return;
7042
652c393a
JB		 7043 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7044 if (!crtc->fb)
7045 continue;
7046
f047e395 7047 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7048 intel_increase_pllclock(crtc);
652c393a
JB		 7049 }
7050}
7051
79e53945
JB		 7052static void intel_crtc_destroy(struct drm_crtc *crtc)
7053{
7054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7055 struct drm_device *dev = crtc->dev;
7056 struct intel_unpin_work *work;
7057 unsigned long flags;
7058
7059 spin_lock_irqsave(&dev->event_lock, flags);
7060 work = intel_crtc->unpin_work;
7061 intel_crtc->unpin_work = NULL;
7062 spin_unlock_irqrestore(&dev->event_lock, flags);
7063
7064 if (work) {
7065 cancel_work_sync(&work->work);
7066 kfree(work);
7067 }
79e53945
JB		 7068
7069 drm_crtc_cleanup(crtc);
67e77c5a 7070
79e53945
JB		 7071 kfree(intel_crtc);
7072}
7073
6b95a207
KH		 7074static void intel_unpin_work_fn(struct work_struct *__work)
7075{
7076 struct intel_unpin_work *work =
7077 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7078 struct drm_device *dev = work->crtc->dev;
6b95a207 7079
b4a98e57 7080 mutex_lock(&dev->struct_mutex);
1690e1eb 7081 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7082 drm_gem_object_unreference(&work->pending_flip_obj->base);
7083 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7084
b4a98e57
CW		 7085 intel_update_fbc(dev);
7086 mutex_unlock(&dev->struct_mutex);
7087
7088 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7089 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7090
6b95a207
KH		 7091 kfree(work);
7092}
7093
1afe3e9d 7094static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7095 struct drm_crtc *crtc)
6b95a207
KH		 7096{
7097 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7099 struct intel_unpin_work *work;
6b95a207
KH		 7100 unsigned long flags;
7101
7102 /* Ignore early vblank irqs */
7103 if (intel_crtc == NULL)
7104 return;
7105
7106 spin_lock_irqsave(&dev->event_lock, flags);
7107 work = intel_crtc->unpin_work;
e7d841ca
CW		 7108
7109 /* Ensure we don't miss a work->pending update ... */
7110 smp_rmb();
7111
7112 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7113 spin_unlock_irqrestore(&dev->event_lock, flags);
7114 return;
7115 }
7116
e7d841ca
CW		 7117 /* and that the unpin work is consistent wrt ->pending. */
7118 smp_rmb();
7119
6b95a207 7120 intel_crtc->unpin_work = NULL;
6b95a207 7121
45a066eb
RC		 7122 if (work->event)
7123 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7124
0af7e4df
MK		 7125 drm_vblank_put(dev, intel_crtc->pipe);
7126
6b95a207
KH		 7127 spin_unlock_irqrestore(&dev->event_lock, flags);
7128
2c10d571 7129 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7130
7131 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7132
7133 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7134}
7135
1afe3e9d
JB		 7136void intel_finish_page_flip(struct drm_device *dev, int pipe)
7137{
7138 drm_i915_private_t *dev_priv = dev->dev_private;
7139 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7140
49b14a5c 7141 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7142}
7143
7144void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7145{
7146 drm_i915_private_t *dev_priv = dev->dev_private;
7147 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7148
49b14a5c 7149 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7150}
7151
6b95a207
KH		 7152void intel_prepare_page_flip(struct drm_device *dev, int plane)
7153{
7154 drm_i915_private_t *dev_priv = dev->dev_private;
7155 struct intel_crtc *intel_crtc =
7156 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7157 unsigned long flags;
7158
e7d841ca
CW		 7159 /* NB: An MMIO update of the plane base pointer will also
7160 * generate a page-flip completion irq, i.e. every modeset
7161 * is also accompanied by a spurious intel_prepare_page_flip().
7162 */
6b95a207 7163 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7164 if (intel_crtc->unpin_work)
7165 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7166 spin_unlock_irqrestore(&dev->event_lock, flags);
7167}
7168
e7d841ca
CW		 7169inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7170{
7171 /* Ensure that the work item is consistent when activating it ... */
7172 smp_wmb();
7173 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7174 /* and that it is marked active as soon as the irq could fire. */
7175 smp_wmb();
7176}
7177
8c9f3aaf
JB		 7178static int intel_gen2_queue_flip(struct drm_device *dev,
7179 struct drm_crtc *crtc,
7180 struct drm_framebuffer *fb,
7181 struct drm_i915_gem_object *obj)
7182{
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7185 u32 flip_mask;
6d90c952 7186 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7187 int ret;
7188
6d90c952 7189 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7190 if (ret)
83d4092b 7191 goto err;
8c9f3aaf 7192
6d90c952 7193 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7194 if (ret)
83d4092b 7195 goto err_unpin;
8c9f3aaf
JB		 7196
7197 /* Can't queue multiple flips, so wait for the previous
7198 * one to finish before executing the next.
7199 */
7200 if (intel_crtc->plane)
7201 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7202 else
7203 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7204 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7205 intel_ring_emit(ring, MI_NOOP);
7206 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7207 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7208 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7209 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7210 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7211
7212 intel_mark_page_flip_active(intel_crtc);
6d90c952 7213 intel_ring_advance(ring);
83d4092b
CW		 7214 return 0;
7215
7216err_unpin:
7217 intel_unpin_fb_obj(obj);
7218err:
8c9f3aaf
JB		 7219 return ret;
7220}
7221
7222static int intel_gen3_queue_flip(struct drm_device *dev,
7223 struct drm_crtc *crtc,
7224 struct drm_framebuffer *fb,
7225 struct drm_i915_gem_object *obj)
7226{
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7229 u32 flip_mask;
6d90c952 7230 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7231 int ret;
7232
6d90c952 7233 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7234 if (ret)
83d4092b 7235 goto err;
8c9f3aaf 7236
6d90c952 7237 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7238 if (ret)
83d4092b 7239 goto err_unpin;
8c9f3aaf
JB		 7240
7241 if (intel_crtc->plane)
7242 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7243 else
7244 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7245 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7246 intel_ring_emit(ring, MI_NOOP);
7247 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7248 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7249 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7250 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7251 intel_ring_emit(ring, MI_NOOP);
7252
e7d841ca 7253 intel_mark_page_flip_active(intel_crtc);
6d90c952 7254 intel_ring_advance(ring);
83d4092b
CW		 7255 return 0;
7256
7257err_unpin:
7258 intel_unpin_fb_obj(obj);
7259err:
8c9f3aaf
JB		 7260 return ret;
7261}
7262
7263static int intel_gen4_queue_flip(struct drm_device *dev,
7264 struct drm_crtc *crtc,
7265 struct drm_framebuffer *fb,
7266 struct drm_i915_gem_object *obj)
7267{
7268 struct drm_i915_private *dev_priv = dev->dev_private;
7269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270 uint32_t pf, pipesrc;
6d90c952 7271 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7272 int ret;
7273
6d90c952 7274 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7275 if (ret)
83d4092b 7276 goto err;
8c9f3aaf 7277
6d90c952 7278 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7279 if (ret)
83d4092b 7280 goto err_unpin;
8c9f3aaf
JB		 7281
7282 /* i965+ uses the linear or tiled offsets from the
7283 * Display Registers (which do not change across a page-flip)
7284 * so we need only reprogram the base address.
7285 */
6d90c952
DV		 7286 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7287 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7288 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7289 intel_ring_emit(ring,
7290 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7291 obj->tiling_mode);
8c9f3aaf
JB		 7292
7293 /* XXX Enabling the panel-fitter across page-flip is so far
7294 * untested on non-native modes, so ignore it for now.
7295 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7296 */
7297 pf = 0;
7298 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7299 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7300
7301 intel_mark_page_flip_active(intel_crtc);
6d90c952 7302 intel_ring_advance(ring);
83d4092b
CW		 7303 return 0;
7304
7305err_unpin:
7306 intel_unpin_fb_obj(obj);
7307err:
8c9f3aaf
JB		 7308 return ret;
7309}
7310
7311static int intel_gen6_queue_flip(struct drm_device *dev,
7312 struct drm_crtc *crtc,
7313 struct drm_framebuffer *fb,
7314 struct drm_i915_gem_object *obj)
7315{
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7318 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7319 uint32_t pf, pipesrc;
7320 int ret;
7321
6d90c952 7322 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7323 if (ret)
83d4092b 7324 goto err;
8c9f3aaf 7325
6d90c952 7326 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7327 if (ret)
83d4092b 7328 goto err_unpin;
8c9f3aaf 7329
6d90c952
DV		 7330 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7331 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7332 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7333 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7334
dc257cf1
DV		 7335 /* Contrary to the suggestions in the documentation,
7336 * "Enable Panel Fitter" does not seem to be required when page
7337 * flipping with a non-native mode, and worse causes a normal
7338 * modeset to fail.
7339 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7340 */
7341 pf = 0;
8c9f3aaf 7342 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7343 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7344
7345 intel_mark_page_flip_active(intel_crtc);
6d90c952 7346 intel_ring_advance(ring);
83d4092b
CW		 7347 return 0;
7348
7349err_unpin:
7350 intel_unpin_fb_obj(obj);
7351err:
8c9f3aaf
JB		 7352 return ret;
7353}
7354
7c9017e5
JB		 7355/*
7356 * On gen7 we currently use the blit ring because (in early silicon at least)
7357 * the render ring doesn't give us interrpts for page flip completion, which
7358 * means clients will hang after the first flip is queued. Fortunately the
7359 * blit ring generates interrupts properly, so use it instead.
7360 */
7361static int intel_gen7_queue_flip(struct drm_device *dev,
7362 struct drm_crtc *crtc,
7363 struct drm_framebuffer *fb,
7364 struct drm_i915_gem_object *obj)
7365{
7366 struct drm_i915_private *dev_priv = dev->dev_private;
7367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7368 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7369 uint32_t plane_bit = 0;
7c9017e5
JB		 7370 int ret;
7371
7372 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7373 if (ret)
83d4092b 7374 goto err;
7c9017e5 7375
cb05d8de
DV		 7376 switch(intel_crtc->plane) {
7377 case PLANE_A:
7378 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7379 break;
7380 case PLANE_B:
7381 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7382 break;
7383 case PLANE_C:
7384 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7385 break;
7386 default:
7387 WARN_ONCE(1, "unknown plane in flip command\n");
7388 ret = -ENODEV;
ab3951eb 7389 goto err_unpin;
cb05d8de
DV		 7390 }
7391
7c9017e5
JB		 7392 ret = intel_ring_begin(ring, 4);
7393 if (ret)
83d4092b 7394 goto err_unpin;
7c9017e5 7395
cb05d8de 7396 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7397 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7398 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7399 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7400
7401 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7402 intel_ring_advance(ring);
83d4092b
CW		 7403 return 0;
7404
7405err_unpin:
7406 intel_unpin_fb_obj(obj);
7407err:
7c9017e5
JB		 7408 return ret;
7409}
7410
8c9f3aaf
JB		 7411static int intel_default_queue_flip(struct drm_device *dev,
7412 struct drm_crtc *crtc,
7413 struct drm_framebuffer *fb,
7414 struct drm_i915_gem_object *obj)
7415{
7416 return -ENODEV;
7417}
7418
6b95a207
KH		 7419static int intel_crtc_page_flip(struct drm_crtc *crtc,
7420 struct drm_framebuffer *fb,
7421 struct drm_pending_vblank_event *event)
7422{
7423 struct drm_device *dev = crtc->dev;
7424 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7425 struct drm_framebuffer *old_fb = crtc->fb;
7426 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428 struct intel_unpin_work *work;
8c9f3aaf 7429 unsigned long flags;
52e68630 7430 int ret;
6b95a207 7431
e6a595d2
VS		 7432 /* Can't change pixel format via MI display flips. */
7433 if (fb->pixel_format != crtc->fb->pixel_format)
7434 return -EINVAL;
7435
7436 /*
7437 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7438 * Note that pitch changes could also affect these register.
7439 */
7440 if (INTEL_INFO(dev)->gen > 3 &&
7441 (fb->offsets[0] != crtc->fb->offsets[0] ||
7442 fb->pitches[0] != crtc->fb->pitches[0]))
7443 return -EINVAL;
7444
6b95a207
KH		 7445 work = kzalloc(sizeof *work, GFP_KERNEL);
7446 if (work == NULL)
7447 return -ENOMEM;
7448
6b95a207 7449 work->event = event;
b4a98e57 7450 work->crtc = crtc;
4a35f83b 7451 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7452 INIT_WORK(&work->work, intel_unpin_work_fn);
7453
7317c75e
JB		 7454 ret = drm_vblank_get(dev, intel_crtc->pipe);
7455 if (ret)
7456 goto free_work;
7457
6b95a207
KH		 7458 /* We borrow the event spin lock for protecting unpin_work */
7459 spin_lock_irqsave(&dev->event_lock, flags);
7460 if (intel_crtc->unpin_work) {
7461 spin_unlock_irqrestore(&dev->event_lock, flags);
7462 kfree(work);
7317c75e 7463 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7464
7465 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7466 return -EBUSY;
7467 }
7468 intel_crtc->unpin_work = work;
7469 spin_unlock_irqrestore(&dev->event_lock, flags);
7470
b4a98e57
CW		 7471 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7472 flush_workqueue(dev_priv->wq);
7473
79158103
CW		 7474 ret = i915_mutex_lock_interruptible(dev);
7475 if (ret)
7476 goto cleanup;
6b95a207 7477
75dfca80 7478 /* Reference the objects for the scheduled work. */
05394f39
CW		 7479 drm_gem_object_reference(&work->old_fb_obj->base);
7480 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7481
7482 crtc->fb = fb;
96b099fd 7483
e1f99ce6 7484 work->pending_flip_obj = obj;
e1f99ce6 7485
4e5359cd
SF		 7486 work->enable_stall_check = true;
7487
b4a98e57 7488 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7489 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7490
8c9f3aaf
JB		 7491 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7492 if (ret)
7493 goto cleanup_pending;
6b95a207 7494
7782de3b 7495 intel_disable_fbc(dev);
f047e395 7496 intel_mark_fb_busy(obj);
6b95a207
KH		 7497 mutex_unlock(&dev->struct_mutex);
7498
e5510fac
JB		 7499 trace_i915_flip_request(intel_crtc->plane, obj);
7500
6b95a207 7501 return 0;
96b099fd 7502
8c9f3aaf 7503cleanup_pending:
b4a98e57 7504 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7505 crtc->fb = old_fb;
05394f39
CW		 7506 drm_gem_object_unreference(&work->old_fb_obj->base);
7507 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7508 mutex_unlock(&dev->struct_mutex);
7509
79158103 7510cleanup:
96b099fd
CW		 7511 spin_lock_irqsave(&dev->event_lock, flags);
7512 intel_crtc->unpin_work = NULL;
7513 spin_unlock_irqrestore(&dev->event_lock, flags);
7514
7317c75e
JB		 7515 drm_vblank_put(dev, intel_crtc->pipe);
7516free_work:
96b099fd
CW		 7517 kfree(work);
7518
7519 return ret;
6b95a207
KH		 7520}
7521
f6e5b160 7522static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7523 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7524 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7525};
7526
6ed0f796 7527bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7528{
6ed0f796
DV		 7529 struct intel_encoder *other_encoder;
7530 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7531
6ed0f796
DV		 7532 if (WARN_ON(!crtc))
7533 return false;
7534
7535 list_for_each_entry(other_encoder,
7536 &crtc->dev->mode_config.encoder_list,
7537 base.head) {
7538
7539 if (&other_encoder->new_crtc->base != crtc ||
7540 encoder == other_encoder)
7541 continue;
7542 else
7543 return true;
f47166d2
CW		 7544 }
7545
6ed0f796
DV		 7546 return false;
7547}
47f1c6c9 7548
50f56119
DV		 7549static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7550 struct drm_crtc *crtc)
7551{
7552 struct drm_device *dev;
7553 struct drm_crtc *tmp;
7554 int crtc_mask = 1;
47f1c6c9 7555
50f56119 7556 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7557
50f56119 7558 dev = crtc->dev;
47f1c6c9 7559
50f56119
DV		 7560 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7561 if (tmp == crtc)
7562 break;
7563 crtc_mask <<= 1;
7564 }
47f1c6c9 7565
50f56119
DV		 7566 if (encoder->possible_crtcs & crtc_mask)
7567 return true;
7568 return false;
47f1c6c9 7569}
79e53945 7570
9a935856
DV		 7571/**
7572 * intel_modeset_update_staged_output_state
7573 *
7574 * Updates the staged output configuration state, e.g. after we've read out the
7575 * current hw state.
7576 */
7577static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7578{
9a935856
DV		 7579 struct intel_encoder *encoder;
7580 struct intel_connector *connector;
f6e5b160 7581
9a935856
DV		 7582 list_for_each_entry(connector, &dev->mode_config.connector_list,
7583 base.head) {
7584 connector->new_encoder =
7585 to_intel_encoder(connector->base.encoder);
7586 }
f6e5b160 7587
9a935856
DV		 7588 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7589 base.head) {
7590 encoder->new_crtc =
7591 to_intel_crtc(encoder->base.crtc);
7592 }
f6e5b160
CW		 7593}
7594
9a935856
DV		 7595/**
7596 * intel_modeset_commit_output_state
7597 *
7598 * This function copies the stage display pipe configuration to the real one.
7599 */
7600static void intel_modeset_commit_output_state(struct drm_device *dev)
7601{
7602 struct intel_encoder *encoder;
7603 struct intel_connector *connector;
f6e5b160 7604
9a935856
DV		 7605 list_for_each_entry(connector, &dev->mode_config.connector_list,
7606 base.head) {
7607 connector->base.encoder = &connector->new_encoder->base;
7608 }
f6e5b160 7609
9a935856
DV		 7610 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7611 base.head) {
7612 encoder->base.crtc = &encoder->new_crtc->base;
7613 }
7614}
7615
4e53c2e0
DV		 7616static int
7617pipe_config_set_bpp(struct drm_crtc *crtc,
7618 struct drm_framebuffer *fb,
7619 struct intel_crtc_config *pipe_config)
7620{
7621 struct drm_device *dev = crtc->dev;
7622 struct drm_connector *connector;
7623 int bpp;
7624
d42264b1
DV		 7625 switch (fb->pixel_format) {
7626 case DRM_FORMAT_C8:
4e53c2e0
DV		 7627 bpp = 8*3; /* since we go through a colormap */
7628 break;
d42264b1
DV		 7629 case DRM_FORMAT_XRGB1555:
7630 case DRM_FORMAT_ARGB1555:
7631 /* checked in intel_framebuffer_init already */
7632 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7633 return -EINVAL;
7634 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7635 bpp = 6*3; /* min is 18bpp */
7636 break;
d42264b1
DV		 7637 case DRM_FORMAT_XBGR8888:
7638 case DRM_FORMAT_ABGR8888:
7639 /* checked in intel_framebuffer_init already */
7640 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7641 return -EINVAL;
7642 case DRM_FORMAT_XRGB8888:
7643 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7644 bpp = 8*3;
7645 break;
d42264b1
DV		 7646 case DRM_FORMAT_XRGB2101010:
7647 case DRM_FORMAT_ARGB2101010:
7648 case DRM_FORMAT_XBGR2101010:
7649 case DRM_FORMAT_ABGR2101010:
7650 /* checked in intel_framebuffer_init already */
7651 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7652 return -EINVAL;
4e53c2e0
DV		 7653 bpp = 10*3;
7654 break;
baba133a 7655 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7656 default:
7657 DRM_DEBUG_KMS("unsupported depth\n");
7658 return -EINVAL;
7659 }
7660
4e53c2e0
DV		 7661 pipe_config->pipe_bpp = bpp;
7662
7663 /* Clamp display bpp to EDID value */
7664 list_for_each_entry(connector, &dev->mode_config.connector_list,
7665 head) {
7666 if (connector->encoder && connector->encoder->crtc != crtc)
7667 continue;
7668
7669 /* Don't use an invalid EDID bpc value */
7670 if (connector->display_info.bpc &&
7671 connector->display_info.bpc * 3 < bpp) {
7672 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7673 bpp, connector->display_info.bpc*3);
7674 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7675 }
996a2239
DV		 7676
7677 /* Clamp bpp to 8 on screens without EDID 1.4 */
7678 if (connector->display_info.bpc == 0 && bpp > 24) {
7679 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7680 bpp);
7681 pipe_config->pipe_bpp = 24;
7682 }
4e53c2e0
DV		 7683 }
7684
7685 return bpp;
7686}
7687
b8cecdf5
DV		 7688static struct intel_crtc_config *
7689intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7690 struct drm_framebuffer *fb,
b8cecdf5 7691 struct drm_display_mode *mode)
ee7b9f93 7692{
7758a113 7693 struct drm_device *dev = crtc->dev;
7758a113
DV		 7694 struct drm_encoder_helper_funcs *encoder_funcs;
7695 struct intel_encoder *encoder;
b8cecdf5 7696 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7697 int plane_bpp, ret = -EINVAL;
7698 bool retry = true;
ee7b9f93 7699
b8cecdf5
DV		 7700 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7701 if (!pipe_config)
7758a113
DV		 7702 return ERR_PTR(-ENOMEM);
7703
b8cecdf5
DV		 7704 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7705 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7706 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7707
4e53c2e0
DV		 7708 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7709 if (plane_bpp < 0)
7710 goto fail;
7711
e29c22c0 7712encoder_retry:
7758a113
DV		 7713 /* Pass our mode to the connectors and the CRTC to give them a chance to
7714 * adjust it according to limitations or connector properties, and also
7715 * a chance to reject the mode entirely.
47f1c6c9 7716 */
7758a113
DV		 7717 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7718 base.head) {
47f1c6c9 7719
7758a113
DV		 7720 if (&encoder->new_crtc->base != crtc)
7721 continue;
7ae89233
DV		 7722
7723 if (encoder->compute_config) {
7724 if (!(encoder->compute_config(encoder, pipe_config))) {
7725 DRM_DEBUG_KMS("Encoder config failure\n");
7726 goto fail;
7727 }
7728
7729 continue;
7730 }
7731
7758a113 7732 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7733 if (!(encoder_funcs->mode_fixup(&encoder->base,
7734 &pipe_config->requested_mode,
7735 &pipe_config->adjusted_mode))) {
7758a113
DV		 7736 DRM_DEBUG_KMS("Encoder fixup failed\n");
7737 goto fail;
7738 }
ee7b9f93 7739 }
47f1c6c9 7740
e29c22c0
DV		 7741 ret = intel_crtc_compute_config(crtc, pipe_config);
7742 if (ret < 0) {
7758a113
DV		 7743 DRM_DEBUG_KMS("CRTC fixup failed\n");
7744 goto fail;
ee7b9f93 7745 }
e29c22c0
DV		 7746
7747 if (ret == RETRY) {
7748 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7749 ret = -EINVAL;
7750 goto fail;
7751 }
7752
7753 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7754 retry = false;
7755 goto encoder_retry;
7756 }
7757
7758a113 7758 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7759
4e53c2e0
DV		 7760 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7761 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7762 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7763
b8cecdf5 7764 return pipe_config;
7758a113 7765fail:
b8cecdf5 7766 kfree(pipe_config);
e29c22c0 7767 return ERR_PTR(ret);
ee7b9f93 7768}
47f1c6c9 7769
e2e1ed41
DV		 7770/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7771 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7772static void
7773intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7774 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7775{
7776 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7777 struct drm_device *dev = crtc->dev;
7778 struct intel_encoder *encoder;
7779 struct intel_connector *connector;
7780 struct drm_crtc *tmp_crtc;
79e53945 7781
e2e1ed41 7782 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7783
e2e1ed41
DV		 7784 /* Check which crtcs have changed outputs connected to them, these need
7785 * to be part of the prepare_pipes mask. We don't (yet) support global
7786 * modeset across multiple crtcs, so modeset_pipes will only have one
7787 * bit set at most. */
7788 list_for_each_entry(connector, &dev->mode_config.connector_list,
7789 base.head) {
7790 if (connector->base.encoder == &connector->new_encoder->base)
7791 continue;
79e53945 7792
e2e1ed41
DV		 7793 if (connector->base.encoder) {
7794 tmp_crtc = connector->base.encoder->crtc;
7795
7796 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7797 }
7798
7799 if (connector->new_encoder)
7800 *prepare_pipes |=
7801 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7802 }
7803
e2e1ed41
DV		 7804 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7805 base.head) {
7806 if (encoder->base.crtc == &encoder->new_crtc->base)
7807 continue;
7808
7809 if (encoder->base.crtc) {
7810 tmp_crtc = encoder->base.crtc;
7811
7812 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7813 }
7814
7815 if (encoder->new_crtc)
7816 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7817 }
7818
e2e1ed41
DV		 7819 /* Check for any pipes that will be fully disabled ... */
7820 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7821 base.head) {
7822 bool used = false;
22fd0fab 7823
e2e1ed41
DV		 7824 /* Don't try to disable disabled crtcs. */
7825 if (!intel_crtc->base.enabled)
7826 continue;
7e7d76c3 7827
e2e1ed41
DV		 7828 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7829 base.head) {
7830 if (encoder->new_crtc == intel_crtc)
7831 used = true;
7832 }
7833
7834 if (!used)
7835 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7836 }
7837
e2e1ed41
DV		 7838
7839 /* set_mode is also used to update properties on life display pipes. */
7840 intel_crtc = to_intel_crtc(crtc);
7841 if (crtc->enabled)
7842 *prepare_pipes |= 1 << intel_crtc->pipe;
7843
b6c5164d
DV		 7844 /*
7845 * For simplicity do a full modeset on any pipe where the output routing
7846 * changed. We could be more clever, but that would require us to be
7847 * more careful with calling the relevant encoder->mode_set functions.
7848 */
e2e1ed41
DV		 7849 if (*prepare_pipes)
7850 *modeset_pipes = *prepare_pipes;
7851
7852 /* ... and mask these out. */
7853 *modeset_pipes &= ~(*disable_pipes);
7854 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7855
7856 /*
7857 * HACK: We don't (yet) fully support global modesets. intel_set_config
7858 * obies this rule, but the modeset restore mode of
7859 * intel_modeset_setup_hw_state does not.
7860 */
7861 *modeset_pipes &= 1 << intel_crtc->pipe;
7862 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7863
7864 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7865 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7866}
79e53945 7867
ea9d758d 7868static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7869{
ea9d758d 7870 struct drm_encoder *encoder;
f6e5b160 7871 struct drm_device *dev = crtc->dev;
f6e5b160 7872
ea9d758d
DV		 7873 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7874 if (encoder->crtc == crtc)
7875 return true;
7876
7877 return false;
7878}
7879
7880static void
7881intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7882{
7883 struct intel_encoder *intel_encoder;
7884 struct intel_crtc *intel_crtc;
7885 struct drm_connector *connector;
7886
7887 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7888 base.head) {
7889 if (!intel_encoder->base.crtc)
7890 continue;
7891
7892 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7893
7894 if (prepare_pipes & (1 << intel_crtc->pipe))
7895 intel_encoder->connectors_active = false;
7896 }
7897
7898 intel_modeset_commit_output_state(dev);
7899
7900 /* Update computed state. */
7901 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7902 base.head) {
7903 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7904 }
7905
7906 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7907 if (!connector->encoder || !connector->encoder->crtc)
7908 continue;
7909
7910 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7911
7912 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7913 struct drm_property *dpms_property =
7914 dev->mode_config.dpms_property;
7915
ea9d758d 7916 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7917 drm_object_property_set_value(&connector->base,
68d34720
DV		 7918 dpms_property,
7919 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7920
7921 intel_encoder = to_intel_encoder(connector->encoder);
7922 intel_encoder->connectors_active = true;
7923 }
7924 }
7925
7926}
7927
25c5b266
DV		 7928#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7929 list_for_each_entry((intel_crtc), \
7930 &(dev)->mode_config.crtc_list, \
7931 base.head) \
0973f18f 7932 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 7933
0e8ffe1b 7934static bool
2fa2fe9a
DV		 7935intel_pipe_config_compare(struct drm_device *dev,
7936 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 7937 struct intel_crtc_config *pipe_config)
7938{
08a24034
DV		 7939#define PIPE_CONF_CHECK_I(name) \
7940 if (current_config->name != pipe_config->name) { \
7941 DRM_ERROR("mismatch in " #name " " \
7942 "(expected %i, found %i)\n", \
7943 current_config->name, \
7944 pipe_config->name); \
7945 return false; \
88adfff1
DV		 7946 }
7947
1bd1bd80
DV		 7948#define PIPE_CONF_CHECK_FLAGS(name, mask) \
7949 if ((current_config->name ^ pipe_config->name) & (mask)) { \
7950 DRM_ERROR("mismatch in " #name " " \
7951 "(expected %i, found %i)\n", \
7952 current_config->name & (mask), \
7953 pipe_config->name & (mask)); \
7954 return false; \
7955 }
7956
eccb140b
DV		 7957 PIPE_CONF_CHECK_I(cpu_transcoder);
7958
08a24034
DV		 7959 PIPE_CONF_CHECK_I(has_pch_encoder);
7960 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 7961 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
7962 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
7963 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
7964 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
7965 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 7966
1bd1bd80
DV		 7967 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
7968 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
7969 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
7970 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
7971 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
7972 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
7973
7974 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
7975 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
7976 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
7977 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
7978 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
7979 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
7980
7981 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7982 DRM_MODE_FLAG_INTERLACE);
7983
045ac3b5
JB		 7984 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7985 DRM_MODE_FLAG_PHSYNC);
7986 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7987 DRM_MODE_FLAG_NHSYNC);
7988 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7989 DRM_MODE_FLAG_PVSYNC);
7990 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7991 DRM_MODE_FLAG_NVSYNC);
7992
1bd1bd80
DV		 7993 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
7994 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
7995
2fa2fe9a
DV		 7996 PIPE_CONF_CHECK_I(gmch_pfit.control);
7997 /* pfit ratios are autocomputed by the hw on gen4+ */
7998 if (INTEL_INFO(dev)->gen < 4)
7999 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8000 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8001 PIPE_CONF_CHECK_I(pch_pfit.pos);
8002 PIPE_CONF_CHECK_I(pch_pfit.size);
8003
08a24034 8004#undef PIPE_CONF_CHECK_I
1bd1bd80 8005#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8006
0e8ffe1b
DV		 8007 return true;
8008}
8009
b980514c 8010void
8af6cf88
DV		 8011intel_modeset_check_state(struct drm_device *dev)
8012{
0e8ffe1b 8013 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8014 struct intel_crtc *crtc;
8015 struct intel_encoder *encoder;
8016 struct intel_connector *connector;
0e8ffe1b 8017 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8018
8019 list_for_each_entry(connector, &dev->mode_config.connector_list,
8020 base.head) {
8021 /* This also checks the encoder/connector hw state with the
8022 * ->get_hw_state callbacks. */
8023 intel_connector_check_state(connector);
8024
8025 WARN(&connector->new_encoder->base != connector->base.encoder,
8026 "connector's staged encoder doesn't match current encoder\n");
8027 }
8028
8029 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8030 base.head) {
8031 bool enabled = false;
8032 bool active = false;
8033 enum pipe pipe, tracked_pipe;
8034
8035 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8036 encoder->base.base.id,
8037 drm_get_encoder_name(&encoder->base));
8038
8039 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8040 "encoder's stage crtc doesn't match current crtc\n");
8041 WARN(encoder->connectors_active && !encoder->base.crtc,
8042 "encoder's active_connectors set, but no crtc\n");
8043
8044 list_for_each_entry(connector, &dev->mode_config.connector_list,
8045 base.head) {
8046 if (connector->base.encoder != &encoder->base)
8047 continue;
8048 enabled = true;
8049 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8050 active = true;
8051 }
8052 WARN(!!encoder->base.crtc != enabled,
8053 "encoder's enabled state mismatch "
8054 "(expected %i, found %i)\n",
8055 !!encoder->base.crtc, enabled);
8056 WARN(active && !encoder->base.crtc,
8057 "active encoder with no crtc\n");
8058
8059 WARN(encoder->connectors_active != active,
8060 "encoder's computed active state doesn't match tracked active state "
8061 "(expected %i, found %i)\n", active, encoder->connectors_active);
8062
8063 active = encoder->get_hw_state(encoder, &pipe);
8064 WARN(active != encoder->connectors_active,
8065 "encoder's hw state doesn't match sw tracking "
8066 "(expected %i, found %i)\n",
8067 encoder->connectors_active, active);
8068
8069 if (!encoder->base.crtc)
8070 continue;
8071
8072 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8073 WARN(active && pipe != tracked_pipe,
8074 "active encoder's pipe doesn't match"
8075 "(expected %i, found %i)\n",
8076 tracked_pipe, pipe);
8077
8078 }
8079
8080 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8081 base.head) {
8082 bool enabled = false;
8083 bool active = false;
8084
045ac3b5
JB		 8085 memset(&pipe_config, 0, sizeof(pipe_config));
8086
8af6cf88
DV		 8087 DRM_DEBUG_KMS("[CRTC:%d]\n",
8088 crtc->base.base.id);
8089
8090 WARN(crtc->active && !crtc->base.enabled,
8091 "active crtc, but not enabled in sw tracking\n");
8092
8093 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8094 base.head) {
8095 if (encoder->base.crtc != &crtc->base)
8096 continue;
8097 enabled = true;
8098 if (encoder->connectors_active)
8099 active = true;
045ac3b5
JB		 8100 if (encoder->get_config)
8101 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8102 }
8103 WARN(active != crtc->active,
8104 "crtc's computed active state doesn't match tracked active state "
8105 "(expected %i, found %i)\n", active, crtc->active);
8106 WARN(enabled != crtc->base.enabled,
8107 "crtc's computed enabled state doesn't match tracked enabled state "
8108 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8109
0e8ffe1b
DV		 8110 active = dev_priv->display.get_pipe_config(crtc,
8111 &pipe_config);
8112 WARN(crtc->active != active,
8113 "crtc active state doesn't match with hw state "
8114 "(expected %i, found %i)\n", crtc->active, active);
8115
8116 WARN(active &&
2fa2fe9a 8117 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config),
0e8ffe1b 8118 "pipe state doesn't match!\n");
8af6cf88
DV		 8119 }
8120}
8121
f30da187
DV		 8122static int __intel_set_mode(struct drm_crtc *crtc,
8123 struct drm_display_mode *mode,
8124 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8125{
8126 struct drm_device *dev = crtc->dev;
dbf2b54e 8127 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8128 struct drm_display_mode *saved_mode, *saved_hwmode;
8129 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8130 struct intel_crtc *intel_crtc;
8131 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8132 int ret = 0;
a6778b3c 8133
3ac18232 8134 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8135 if (!saved_mode)
8136 return -ENOMEM;
3ac18232 8137 saved_hwmode = saved_mode + 1;
a6778b3c 8138
e2e1ed41 8139 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8140 &prepare_pipes, &disable_pipes);
8141
3ac18232
TG		 8142 *saved_hwmode = crtc->hwmode;
8143 *saved_mode = crtc->mode;
a6778b3c 8144
25c5b266
DV		 8145 /* Hack: Because we don't (yet) support global modeset on multiple
8146 * crtcs, we don't keep track of the new mode for more than one crtc.
8147 * Hence simply check whether any bit is set in modeset_pipes in all the
8148 * pieces of code that are not yet converted to deal with mutliple crtcs
8149 * changing their mode at the same time. */
25c5b266 8150 if (modeset_pipes) {
4e53c2e0 8151 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8152 if (IS_ERR(pipe_config)) {
8153 ret = PTR_ERR(pipe_config);
8154 pipe_config = NULL;
8155
3ac18232 8156 goto out;
25c5b266 8157 }
25c5b266 8158 }
a6778b3c 8159
460da916
DV		 8160 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8161 intel_crtc_disable(&intel_crtc->base);
8162
ea9d758d
DV		 8163 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8164 if (intel_crtc->base.enabled)
8165 dev_priv->display.crtc_disable(&intel_crtc->base);
8166 }
a6778b3c 8167
6c4c86f5
DV		 8168 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8169 * to set it here already despite that we pass it down the callchain.
f6e5b160 8170 */
b8cecdf5 8171 if (modeset_pipes) {
25c5b266 8172 crtc->mode = *mode;
b8cecdf5
DV		 8173 /* mode_set/enable/disable functions rely on a correct pipe
8174 * config. */
8175 to_intel_crtc(crtc)->config = *pipe_config;
8176 }
7758a113 8177
ea9d758d
DV		 8178 /* Only after disabling all output pipelines that will be changed can we
8179 * update the the output configuration. */
8180 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8181
47fab737
DV		 8182 if (dev_priv->display.modeset_global_resources)
8183 dev_priv->display.modeset_global_resources(dev);
8184
a6778b3c
DV		 8185 /* Set up the DPLL and any encoders state that needs to adjust or depend
8186 * on the DPLL.
f6e5b160 8187 */
25c5b266 8188 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8189 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8190 x, y, fb);
8191 if (ret)
8192 goto done;
a6778b3c
DV		 8193 }
8194
8195 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8196 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8197 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8198
25c5b266
DV		 8199 if (modeset_pipes) {
8200 /* Store real post-adjustment hardware mode. */
b8cecdf5 8201 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8202
25c5b266
DV		 8203 /* Calculate and store various constants which
8204 * are later needed by vblank and swap-completion
8205 * timestamping. They are derived from true hwmode.
8206 */
8207 drm_calc_timestamping_constants(crtc);
8208 }
a6778b3c
DV		 8209
8210 /* FIXME: add subpixel order */
8211done:
c0c36b94 8212 if (ret && crtc->enabled) {
3ac18232
TG		 8213 crtc->hwmode = *saved_hwmode;
8214 crtc->mode = *saved_mode;
a6778b3c
DV		 8215 }
8216
3ac18232 8217out:
b8cecdf5 8218 kfree(pipe_config);
3ac18232 8219 kfree(saved_mode);
a6778b3c 8220 return ret;
f6e5b160
CW		 8221}
8222
f30da187
DV		 8223int intel_set_mode(struct drm_crtc *crtc,
8224 struct drm_display_mode *mode,
8225 int x, int y, struct drm_framebuffer *fb)
8226{
8227 int ret;
8228
8229 ret = __intel_set_mode(crtc, mode, x, y, fb);
8230
8231 if (ret == 0)
8232 intel_modeset_check_state(crtc->dev);
8233
8234 return ret;
8235}
8236
c0c36b94
CW		 8237void intel_crtc_restore_mode(struct drm_crtc *crtc)
8238{
8239 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8240}
8241
25c5b266
DV		 8242#undef for_each_intel_crtc_masked
8243
d9e55608
DV		 8244static void intel_set_config_free(struct intel_set_config *config)
8245{
8246 if (!config)
8247 return;
8248
1aa4b628
DV		 8249 kfree(config->save_connector_encoders);
8250 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8251 kfree(config);
8252}
8253
85f9eb71
DV		 8254static int intel_set_config_save_state(struct drm_device *dev,
8255 struct intel_set_config *config)
8256{
85f9eb71
DV		 8257 struct drm_encoder *encoder;
8258 struct drm_connector *connector;
8259 int count;
8260
1aa4b628
DV		 8261 config->save_encoder_crtcs =
8262 kcalloc(dev->mode_config.num_encoder,
8263 sizeof(struct drm_crtc *), GFP_KERNEL);
8264 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8265 return -ENOMEM;
8266
1aa4b628
DV		 8267 config->save_connector_encoders =
8268 kcalloc(dev->mode_config.num_connector,
8269 sizeof(struct drm_encoder *), GFP_KERNEL);
8270 if (!config->save_connector_encoders)
85f9eb71
DV		 8271 return -ENOMEM;
8272
8273 /* Copy data. Note that driver private data is not affected.
8274 * Should anything bad happen only the expected state is
8275 * restored, not the drivers personal bookkeeping.
8276 */
85f9eb71
DV		 8277 count = 0;
8278 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8279 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8280 }
8281
8282 count = 0;
8283 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8284 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8285 }
8286
8287 return 0;
8288}
8289
8290static void intel_set_config_restore_state(struct drm_device *dev,
8291 struct intel_set_config *config)
8292{
9a935856
DV		 8293 struct intel_encoder *encoder;
8294 struct intel_connector *connector;
85f9eb71
DV		 8295 int count;
8296
85f9eb71 8297 count = 0;
9a935856
DV		 8298 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8299 encoder->new_crtc =
8300 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8301 }
8302
8303 count = 0;
9a935856
DV		 8304 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8305 connector->new_encoder =
8306 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8307 }
8308}
8309
5e2b584e
DV		 8310static void
8311intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8312 struct intel_set_config *config)
8313{
8314
8315 /* We should be able to check here if the fb has the same properties
8316 * and then just flip_or_move it */
8317 if (set->crtc->fb != set->fb) {
8318 /* If we have no fb then treat it as a full mode set */
8319 if (set->crtc->fb == NULL) {
8320 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8321 config->mode_changed = true;
8322 } else if (set->fb == NULL) {
8323 config->mode_changed = true;
72f4901e
DV		 8324 } else if (set->fb->pixel_format !=
8325 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8326 config->mode_changed = true;
8327 } else
8328 config->fb_changed = true;
8329 }
8330
835c5873 8331 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8332 config->fb_changed = true;
8333
8334 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8335 DRM_DEBUG_KMS("modes are different, full mode set\n");
8336 drm_mode_debug_printmodeline(&set->crtc->mode);
8337 drm_mode_debug_printmodeline(set->mode);
8338 config->mode_changed = true;
8339 }
8340}
8341
2e431051 8342static int
9a935856
DV		 8343intel_modeset_stage_output_state(struct drm_device *dev,
8344 struct drm_mode_set *set,
8345 struct intel_set_config *config)
50f56119 8346{
85f9eb71 8347 struct drm_crtc *new_crtc;
9a935856
DV		 8348 struct intel_connector *connector;
8349 struct intel_encoder *encoder;
2e431051 8350 int count, ro;
50f56119 8351
9abdda74 8352 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8353 * of connectors. For paranoia, double-check this. */
8354 WARN_ON(!set->fb && (set->num_connectors != 0));
8355 WARN_ON(set->fb && (set->num_connectors == 0));
8356
50f56119 8357 count = 0;
9a935856
DV		 8358 list_for_each_entry(connector, &dev->mode_config.connector_list,
8359 base.head) {
8360 /* Otherwise traverse passed in connector list and get encoders
8361 * for them. */
50f56119 8362 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8363 if (set->connectors[ro] == &connector->base) {
8364 connector->new_encoder = connector->encoder;
50f56119
DV		 8365 break;
8366 }
8367 }
8368
9a935856
DV		 8369 /* If we disable the crtc, disable all its connectors. Also, if
8370 * the connector is on the changing crtc but not on the new
8371 * connector list, disable it. */
8372 if ((!set->fb || ro == set->num_connectors) &&
8373 connector->base.encoder &&
8374 connector->base.encoder->crtc == set->crtc) {
8375 connector->new_encoder = NULL;
8376
8377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8378 connector->base.base.id,
8379 drm_get_connector_name(&connector->base));
8380 }
8381
8382
8383 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8384 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8385 config->mode_changed = true;
50f56119
DV		 8386 }
8387 }
9a935856 8388 /* connector->new_encoder is now updated for all connectors. */
50f56119 8389
9a935856 8390 /* Update crtc of enabled connectors. */
50f56119 8391 count = 0;
9a935856
DV		 8392 list_for_each_entry(connector, &dev->mode_config.connector_list,
8393 base.head) {
8394 if (!connector->new_encoder)
50f56119
DV		 8395 continue;
8396
9a935856 8397 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8398
8399 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8400 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8401 new_crtc = set->crtc;
8402 }
8403
8404 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8405 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8406 new_crtc)) {
5e2b584e 8407 return -EINVAL;
50f56119 8408 }
9a935856
DV		 8409 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8410
8411 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8412 connector->base.base.id,
8413 drm_get_connector_name(&connector->base),
8414 new_crtc->base.id);
8415 }
8416
8417 /* Check for any encoders that needs to be disabled. */
8418 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8419 base.head) {
8420 list_for_each_entry(connector,
8421 &dev->mode_config.connector_list,
8422 base.head) {
8423 if (connector->new_encoder == encoder) {
8424 WARN_ON(!connector->new_encoder->new_crtc);
8425
8426 goto next_encoder;
8427 }
8428 }
8429 encoder->new_crtc = NULL;
8430next_encoder:
8431 /* Only now check for crtc changes so we don't miss encoders
8432 * that will be disabled. */
8433 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8434 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8435 config->mode_changed = true;
50f56119
DV		 8436 }
8437 }
9a935856 8438 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8439
2e431051
DV		 8440 return 0;
8441}
8442
8443static int intel_crtc_set_config(struct drm_mode_set *set)
8444{
8445 struct drm_device *dev;
2e431051
DV		 8446 struct drm_mode_set save_set;
8447 struct intel_set_config *config;
8448 int ret;
2e431051 8449
8d3e375e
DV		 8450 BUG_ON(!set);
8451 BUG_ON(!set->crtc);
8452 BUG_ON(!set->crtc->helper_private);
2e431051 8453
7e53f3a4
DV		 8454 /* Enforce sane interface api - has been abused by the fb helper. */
8455 BUG_ON(!set->mode && set->fb);
8456 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8457
2e431051
DV		 8458 if (set->fb) {
8459 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8460 set->crtc->base.id, set->fb->base.id,
8461 (int)set->num_connectors, set->x, set->y);
8462 } else {
8463 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8464 }
8465
8466 dev = set->crtc->dev;
8467
8468 ret = -ENOMEM;
8469 config = kzalloc(sizeof(*config), GFP_KERNEL);
8470 if (!config)
8471 goto out_config;
8472
8473 ret = intel_set_config_save_state(dev, config);
8474 if (ret)
8475 goto out_config;
8476
8477 save_set.crtc = set->crtc;
8478 save_set.mode = &set->crtc->mode;
8479 save_set.x = set->crtc->x;
8480 save_set.y = set->crtc->y;
8481 save_set.fb = set->crtc->fb;
8482
8483 /* Compute whether we need a full modeset, only an fb base update or no
8484 * change at all. In the future we might also check whether only the
8485 * mode changed, e.g. for LVDS where we only change the panel fitter in
8486 * such cases. */
8487 intel_set_config_compute_mode_changes(set, config);
8488
9a935856 8489 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8490 if (ret)
8491 goto fail;
8492
5e2b584e 8493 if (config->mode_changed) {
87f1faa6 8494 if (set->mode) {
50f56119
DV		 8495 DRM_DEBUG_KMS("attempting to set mode from"
8496 " userspace\n");
8497 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8498 }
8499
c0c36b94
CW		 8500 ret = intel_set_mode(set->crtc, set->mode,
8501 set->x, set->y, set->fb);
8502 if (ret) {
8503 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8504 set->crtc->base.id, ret);
87f1faa6
DV		 8505 goto fail;
8506 }
5e2b584e 8507 } else if (config->fb_changed) {
4878cae2
VS		 8508 intel_crtc_wait_for_pending_flips(set->crtc);
8509
4f660f49 8510 ret = intel_pipe_set_base(set->crtc,
94352cf9 8511 set->x, set->y, set->fb);
50f56119
DV		 8512 }
8513
d9e55608
DV		 8514 intel_set_config_free(config);
8515
50f56119
DV		 8516 return 0;
8517
8518fail:
85f9eb71 8519 intel_set_config_restore_state(dev, config);
50f56119
DV		 8520
8521 /* Try to restore the config */
5e2b584e 8522 if (config->mode_changed &&
c0c36b94
CW		 8523 intel_set_mode(save_set.crtc, save_set.mode,
8524 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8525 DRM_ERROR("failed to restore config after modeset failure\n");
8526
d9e55608
DV		 8527out_config:
8528 intel_set_config_free(config);
50f56119
DV		 8529 return ret;
8530}
f6e5b160
CW		 8531
8532static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8533 .cursor_set = intel_crtc_cursor_set,
8534 .cursor_move = intel_crtc_cursor_move,
8535 .gamma_set = intel_crtc_gamma_set,
50f56119 8536 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8537 .destroy = intel_crtc_destroy,
8538 .page_flip = intel_crtc_page_flip,
8539};
8540
79f689aa
PZ		 8541static void intel_cpu_pll_init(struct drm_device *dev)
8542{
affa9354 8543 if (HAS_DDI(dev))
79f689aa
PZ		 8544 intel_ddi_pll_init(dev);
8545}
8546
ee7b9f93
JB		 8547static void intel_pch_pll_init(struct drm_device *dev)
8548{
8549 drm_i915_private_t *dev_priv = dev->dev_private;
8550 int i;
8551
8552 if (dev_priv->num_pch_pll == 0) {
8553 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8554 return;
8555 }
8556
8557 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8558 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8559 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8560 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8561 }
8562}
8563
b358d0a6 8564static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8565{
22fd0fab 8566 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8567 struct intel_crtc *intel_crtc;
8568 int i;
8569
8570 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8571 if (intel_crtc == NULL)
8572 return;
8573
8574 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8575
8576 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8577 for (i = 0; i < 256; i++) {
8578 intel_crtc->lut_r[i] = i;
8579 intel_crtc->lut_g[i] = i;
8580 intel_crtc->lut_b[i] = i;
8581 }
8582
80824003
JB		 8583 /* Swap pipes & planes for FBC on pre-965 */
8584 intel_crtc->pipe = pipe;
8585 intel_crtc->plane = pipe;
e2e767ab 8586 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8587 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8588 intel_crtc->plane = !pipe;
80824003
JB		 8589 }
8590
22fd0fab
JB		 8591 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8592 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8593 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8594 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8595
79e53945 8596 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8597}
8598
08d7b3d1 8599int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8600 struct drm_file *file)
08d7b3d1 8601{
08d7b3d1 8602 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8603 struct drm_mode_object *drmmode_obj;
8604 struct intel_crtc *crtc;
08d7b3d1 8605
1cff8f6b
DV		 8606 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8607 return -ENODEV;
08d7b3d1 8608
c05422d5
DV		 8609 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8610 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8611
c05422d5 8612 if (!drmmode_obj) {
08d7b3d1
CW		 8613 DRM_ERROR("no such CRTC id\n");
8614 return -EINVAL;
8615 }
8616
c05422d5
DV		 8617 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8618 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8619
c05422d5 8620 return 0;
08d7b3d1
CW		 8621}
8622
66a9278e 8623static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8624{
66a9278e
DV		 8625 struct drm_device *dev = encoder->base.dev;
8626 struct intel_encoder *source_encoder;
79e53945 8627 int index_mask = 0;
79e53945
JB		 8628 int entry = 0;
8629
66a9278e
DV		 8630 list_for_each_entry(source_encoder,
8631 &dev->mode_config.encoder_list, base.head) {
8632
8633 if (encoder == source_encoder)
79e53945 8634 index_mask |= (1 << entry);
66a9278e
DV		 8635
8636 /* Intel hw has only one MUX where enocoders could be cloned. */
8637 if (encoder->cloneable && source_encoder->cloneable)
8638 index_mask |= (1 << entry);
8639
79e53945
JB		 8640 entry++;
8641 }
4ef69c7a 8642
79e53945
JB		 8643 return index_mask;
8644}
8645
4d302442
CW		 8646static bool has_edp_a(struct drm_device *dev)
8647{
8648 struct drm_i915_private *dev_priv = dev->dev_private;
8649
8650 if (!IS_MOBILE(dev))
8651 return false;
8652
8653 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8654 return false;
8655
8656 if (IS_GEN5(dev) &&
8657 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8658 return false;
8659
8660 return true;
8661}
8662
79e53945
JB		 8663static void intel_setup_outputs(struct drm_device *dev)
8664{
725e30ad 8665 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8666 struct intel_encoder *encoder;
cb0953d7 8667 bool dpd_is_edp = false;
f3cfcba6 8668 bool has_lvds;
79e53945 8669
f3cfcba6 8670 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8671 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8672 /* disable the panel fitter on everything but LVDS */
8673 I915_WRITE(PFIT_CONTROL, 0);
8674 }
79e53945 8675
c40c0f5b 8676 if (!IS_ULT(dev))
79935fca 8677 intel_crt_init(dev);
cb0953d7 8678
affa9354 8679 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8680 int found;
8681
8682 /* Haswell uses DDI functions to detect digital outputs */
8683 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8684 /* DDI A only supports eDP */
8685 if (found)
8686 intel_ddi_init(dev, PORT_A);
8687
8688 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8689 * register */
8690 found = I915_READ(SFUSE_STRAP);
8691
8692 if (found & SFUSE_STRAP_DDIB_DETECTED)
8693 intel_ddi_init(dev, PORT_B);
8694 if (found & SFUSE_STRAP_DDIC_DETECTED)
8695 intel_ddi_init(dev, PORT_C);
8696 if (found & SFUSE_STRAP_DDID_DETECTED)
8697 intel_ddi_init(dev, PORT_D);
8698 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8699 int found;
270b3042
DV		 8700 dpd_is_edp = intel_dpd_is_edp(dev);
8701
8702 if (has_edp_a(dev))
8703 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8704
dc0fa718 8705 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8706 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8707 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8708 if (!found)
e2debe91 8709 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8710 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8711 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8712 }
8713
dc0fa718 8714 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8715 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8716
dc0fa718 8717 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8718 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8719
5eb08b69 8720 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8721 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8722
270b3042 8723 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8724 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8725 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8726 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8727 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8728 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8729
dc0fa718 8730 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8731 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8732 PORT_B);
67cfc203
VS		 8733 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8734 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8735 }
103a196f 8736 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8737 bool found = false;
7d57382e 8738
e2debe91 8739 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8740 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8741 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8742 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8743 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8744 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8745 }
27185ae1 8746
e7281eab 8747 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8748 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8749 }
13520b05
KH		 8750
8751 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8752
e2debe91 8753 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8754 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8755 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8756 }
27185ae1 8757
e2debe91 8758 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8759
b01f2c3a
JB		 8760 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8761 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8762 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8763 }
e7281eab 8764 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8765 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8766 }
27185ae1 8767
b01f2c3a 8768 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8769 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8770 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8771 } else if (IS_GEN2(dev))
79e53945
JB		 8772 intel_dvo_init(dev);
8773
103a196f 8774 if (SUPPORTS_TV(dev))
79e53945
JB		 8775 intel_tv_init(dev);
8776
4ef69c7a
CW		 8777 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8778 encoder->base.possible_crtcs = encoder->crtc_mask;
8779 encoder->base.possible_clones =
66a9278e 8780 intel_encoder_clones(encoder);
79e53945 8781 }
47356eb6 8782
dde86e2d 8783 intel_init_pch_refclk(dev);
270b3042
DV		 8784
8785 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8786}
8787
8788static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8789{
8790 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8791
8792 drm_framebuffer_cleanup(fb);
05394f39 8793 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8794
8795 kfree(intel_fb);
8796}
8797
8798static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8799 struct drm_file *file,
79e53945
JB		 8800 unsigned int *handle)
8801{
8802 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8803 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8804
05394f39 8805 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8806}
8807
8808static const struct drm_framebuffer_funcs intel_fb_funcs = {
8809 .destroy = intel_user_framebuffer_destroy,
8810 .create_handle = intel_user_framebuffer_create_handle,
8811};
8812
38651674
DA		 8813int intel_framebuffer_init(struct drm_device *dev,
8814 struct intel_framebuffer *intel_fb,
308e5bcb 8815 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8816 struct drm_i915_gem_object *obj)
79e53945 8817{
79e53945
JB		 8818 int ret;
8819
c16ed4be
CW		 8820 if (obj->tiling_mode == I915_TILING_Y) {
8821 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8822 return -EINVAL;
c16ed4be 8823 }
57cd6508 8824
c16ed4be
CW		 8825 if (mode_cmd->pitches[0] & 63) {
8826 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8827 mode_cmd->pitches[0]);
57cd6508 8828 return -EINVAL;
c16ed4be 8829 }
57cd6508 8830
5d7bd705 8831 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8832 if (mode_cmd->pitches[0] > 32768) {
8833 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8834 mode_cmd->pitches[0]);
5d7bd705 8835 return -EINVAL;
c16ed4be 8836 }
5d7bd705
VS		 8837
8838 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8839 mode_cmd->pitches[0] != obj->stride) {
8840 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8841 mode_cmd->pitches[0], obj->stride);
5d7bd705 8842 return -EINVAL;
c16ed4be 8843 }
5d7bd705 8844
57779d06 8845 /* Reject formats not supported by any plane early. */
308e5bcb 8846 switch (mode_cmd->pixel_format) {
57779d06 8847 case DRM_FORMAT_C8:
04b3924d
VS		 8848 case DRM_FORMAT_RGB565:
8849 case DRM_FORMAT_XRGB8888:
8850 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8851 break;
8852 case DRM_FORMAT_XRGB1555:
8853 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8854 if (INTEL_INFO(dev)->gen > 3) {
8855 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8856 return -EINVAL;
c16ed4be 8857 }
57779d06
VS		 8858 break;
8859 case DRM_FORMAT_XBGR8888:
8860 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8861 case DRM_FORMAT_XRGB2101010:
8862 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8863 case DRM_FORMAT_XBGR2101010:
8864 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8865 if (INTEL_INFO(dev)->gen < 4) {
8866 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8867 return -EINVAL;
c16ed4be 8868 }
b5626747 8869 break;
04b3924d
VS		 8870 case DRM_FORMAT_YUYV:
8871 case DRM_FORMAT_UYVY:
8872 case DRM_FORMAT_YVYU:
8873 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8874 if (INTEL_INFO(dev)->gen < 5) {
8875 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8876 return -EINVAL;
c16ed4be 8877 }
57cd6508
CW		 8878 break;
8879 default:
c16ed4be 8880 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8881 return -EINVAL;
8882 }
8883
90f9a336
VS		 8884 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8885 if (mode_cmd->offsets[0] != 0)
8886 return -EINVAL;
8887
c7d73f6a
DV		 8888 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8889 intel_fb->obj = obj;
8890
79e53945
JB		 8891 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8892 if (ret) {
8893 DRM_ERROR("framebuffer init failed %d\n", ret);
8894 return ret;
8895 }
8896
79e53945
JB		 8897 return 0;
8898}
8899
79e53945
JB		 8900static struct drm_framebuffer *
8901intel_user_framebuffer_create(struct drm_device *dev,
8902 struct drm_file *filp,
308e5bcb 8903 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8904{
05394f39 8905 struct drm_i915_gem_object *obj;
79e53945 8906
308e5bcb
JB		 8907 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8908 mode_cmd->handles[0]));
c8725226 8909 if (&obj->base == NULL)
cce13ff7 8910 return ERR_PTR(-ENOENT);
79e53945 8911
d2dff872 8912 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8913}
8914
79e53945 8915static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8916 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8917 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8918};
8919
e70236a8
JB		 8920/* Set up chip specific display functions */
8921static void intel_init_display(struct drm_device *dev)
8922{
8923 struct drm_i915_private *dev_priv = dev->dev_private;
8924
affa9354 8925 if (HAS_DDI(dev)) {
0e8ffe1b 8926 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8927 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8928 dev_priv->display.crtc_enable = haswell_crtc_enable;
8929 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8930 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8931 dev_priv->display.update_plane = ironlake_update_plane;
8932 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8933 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8934 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8935 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8936 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8937 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8938 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8939 } else if (IS_VALLEYVIEW(dev)) {
8940 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8941 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8942 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8943 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8944 dev_priv->display.off = i9xx_crtc_off;
8945 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8946 } else {
0e8ffe1b 8947 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8948 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8949 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8950 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8951 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8952 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8953 }
e70236a8 8954
e70236a8 8955 /* Returns the core display clock speed */
25eb05fc
JB		 8956 if (IS_VALLEYVIEW(dev))
8957 dev_priv->display.get_display_clock_speed =
8958 valleyview_get_display_clock_speed;
8959 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8960 dev_priv->display.get_display_clock_speed =
8961 i945_get_display_clock_speed;
8962 else if (IS_I915G(dev))
8963 dev_priv->display.get_display_clock_speed =
8964 i915_get_display_clock_speed;
f2b115e6 8965 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8966 dev_priv->display.get_display_clock_speed =
8967 i9xx_misc_get_display_clock_speed;
8968 else if (IS_I915GM(dev))
8969 dev_priv->display.get_display_clock_speed =
8970 i915gm_get_display_clock_speed;
8971 else if (IS_I865G(dev))
8972 dev_priv->display.get_display_clock_speed =
8973 i865_get_display_clock_speed;
f0f8a9ce 8974 else if (IS_I85X(dev))
e70236a8
JB		 8975 dev_priv->display.get_display_clock_speed =
8976 i855_get_display_clock_speed;
8977 else /* 852, 830 */
8978 dev_priv->display.get_display_clock_speed =
8979 i830_get_display_clock_speed;
8980
7f8a8569 8981 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8982 if (IS_GEN5(dev)) {
674cf967 8983 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8984 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8985 } else if (IS_GEN6(dev)) {
674cf967 8986 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8987 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8988 } else if (IS_IVYBRIDGE(dev)) {
8989 /* FIXME: detect B0+ stepping and use auto training */
8990 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8991 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8992 dev_priv->display.modeset_global_resources =
8993 ivb_modeset_global_resources;
c82e4d26
ED		 8994 } else if (IS_HASWELL(dev)) {
8995 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8996 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8997 dev_priv->display.modeset_global_resources =
8998 haswell_modeset_global_resources;
a0e63c22 8999 }
6067aaea 9000 } else if (IS_G4X(dev)) {
e0dac65e 9001 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9002 }
8c9f3aaf
JB		 9003
9004 /* Default just returns -ENODEV to indicate unsupported */
9005 dev_priv->display.queue_flip = intel_default_queue_flip;
9006
9007 switch (INTEL_INFO(dev)->gen) {
9008 case 2:
9009 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9010 break;
9011
9012 case 3:
9013 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9014 break;
9015
9016 case 4:
9017 case 5:
9018 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9019 break;
9020
9021 case 6:
9022 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9023 break;
7c9017e5
JB		 9024 case 7:
9025 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9026 break;
8c9f3aaf 9027 }
e70236a8
JB		 9028}
9029
b690e96c
JB		 9030/*
9031 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9032 * resume, or other times. This quirk makes sure that's the case for
9033 * affected systems.
9034 */
0206e353 9035static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9036{
9037 struct drm_i915_private *dev_priv = dev->dev_private;
9038
9039 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9040 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9041}
9042
435793df
KP		 9043/*
9044 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9045 */
9046static void quirk_ssc_force_disable(struct drm_device *dev)
9047{
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9050 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9051}
9052
4dca20ef 9053/*
5a15ab5b
CE		 9054 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9055 * brightness value
4dca20ef
CE		 9056 */
9057static void quirk_invert_brightness(struct drm_device *dev)
9058{
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9061 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9062}
9063
b690e96c
JB		 9064struct intel_quirk {
9065 int device;
9066 int subsystem_vendor;
9067 int subsystem_device;
9068 void (*hook)(struct drm_device *dev);
9069};
9070
5f85f176
EE		 9071/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9072struct intel_dmi_quirk {
9073 void (*hook)(struct drm_device *dev);
9074 const struct dmi_system_id (*dmi_id_list)[];
9075};
9076
9077static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9078{
9079 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9080 return 1;
9081}
9082
9083static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9084 {
9085 .dmi_id_list = &(const struct dmi_system_id[]) {
9086 {
9087 .callback = intel_dmi_reverse_brightness,
9088 .ident = "NCR Corporation",
9089 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9090 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9091 },
9092 },
9093 { } /* terminating entry */
9094 },
9095 .hook = quirk_invert_brightness,
9096 },
9097};
9098
c43b5634 9099static struct intel_quirk intel_quirks[] = {
b690e96c 9100 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9101 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9102
b690e96c
JB		 9103 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9104 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9105
b690e96c
JB		 9106 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9107 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9108
ccd0d36e 9109 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9110 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9111 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9112
9113 /* Lenovo U160 cannot use SSC on LVDS */
9114 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9115
9116 /* Sony Vaio Y cannot use SSC on LVDS */
9117 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9118
9119 /* Acer Aspire 5734Z must invert backlight brightness */
9120 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9121
9122 /* Acer/eMachines G725 */
9123 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9124
9125 /* Acer/eMachines e725 */
9126 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9127
9128 /* Acer/Packard Bell NCL20 */
9129 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9130
9131 /* Acer Aspire 4736Z */
9132 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9133};
9134
9135static void intel_init_quirks(struct drm_device *dev)
9136{
9137 struct pci_dev *d = dev->pdev;
9138 int i;
9139
9140 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9141 struct intel_quirk *q = &intel_quirks[i];
9142
9143 if (d->device == q->device &&
9144 (d->subsystem_vendor == q->subsystem_vendor ||
9145 q->subsystem_vendor == PCI_ANY_ID) &&
9146 (d->subsystem_device == q->subsystem_device ||
9147 q->subsystem_device == PCI_ANY_ID))
9148 q->hook(dev);
9149 }
5f85f176
EE		 9150 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9151 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9152 intel_dmi_quirks[i].hook(dev);
9153 }
b690e96c
JB		 9154}
9155
9cce37f4
JB		 9156/* Disable the VGA plane that we never use */
9157static void i915_disable_vga(struct drm_device *dev)
9158{
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 u8 sr1;
766aa1c4 9161 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9162
9163 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9164 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9165 sr1 = inb(VGA_SR_DATA);
9166 outb(sr1 | 1<<5, VGA_SR_DATA);
9167 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9168 udelay(300);
9169
9170 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9171 POSTING_READ(vga_reg);
9172}
9173
f817586c
DV		 9174void intel_modeset_init_hw(struct drm_device *dev)
9175{
fa42e23c 9176 intel_init_power_well(dev);
0232e927 9177
a8f78b58
ED		 9178 intel_prepare_ddi(dev);
9179
f817586c
DV		 9180 intel_init_clock_gating(dev);
9181
79f5b2c7 9182 mutex_lock(&dev->struct_mutex);
8090c6b9 9183 intel_enable_gt_powersave(dev);
79f5b2c7 9184 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9185}
9186
7d708ee4
ID		 9187void intel_modeset_suspend_hw(struct drm_device *dev)
9188{
9189 intel_suspend_hw(dev);
9190}
9191
79e53945
JB		 9192void intel_modeset_init(struct drm_device *dev)
9193{
652c393a 9194 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9195 int i, j, ret;
79e53945
JB		 9196
9197 drm_mode_config_init(dev);
9198
9199 dev->mode_config.min_width = 0;
9200 dev->mode_config.min_height = 0;
9201
019d96cb
DA		 9202 dev->mode_config.preferred_depth = 24;
9203 dev->mode_config.prefer_shadow = 1;
9204
e6ecefaa 9205 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9206
b690e96c
JB		 9207 intel_init_quirks(dev);
9208
1fa61106
ED		 9209 intel_init_pm(dev);
9210
e3c74757
BW		 9211 if (INTEL_INFO(dev)->num_pipes == 0)
9212 return;
9213
e70236a8
JB		 9214 intel_init_display(dev);
9215
a6c45cf0
CW		 9216 if (IS_GEN2(dev)) {
9217 dev->mode_config.max_width = 2048;
9218 dev->mode_config.max_height = 2048;
9219 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9220 dev->mode_config.max_width = 4096;
9221 dev->mode_config.max_height = 4096;
79e53945 9222 } else {
a6c45cf0
CW		 9223 dev->mode_config.max_width = 8192;
9224 dev->mode_config.max_height = 8192;
79e53945 9225 }
5d4545ae 9226 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9227
28c97730 9228 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9229 INTEL_INFO(dev)->num_pipes,
9230 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9231
7eb552ae 9232 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9233 intel_crtc_init(dev, i);
7f1f3851
JB		 9234 for (j = 0; j < dev_priv->num_plane; j++) {
9235 ret = intel_plane_init(dev, i, j);
9236 if (ret)
06da8da2
VS		 9237 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9238 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9239 }
79e53945
JB		 9240 }
9241
79f689aa 9242 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9243 intel_pch_pll_init(dev);
9244
9cce37f4
JB		 9245 /* Just disable it once at startup */
9246 i915_disable_vga(dev);
79e53945 9247 intel_setup_outputs(dev);
11be49eb
CW		 9248
9249 /* Just in case the BIOS is doing something questionable. */
9250 intel_disable_fbc(dev);
2c7111db
CW		 9251}
9252
24929352
DV		 9253static void
9254intel_connector_break_all_links(struct intel_connector *connector)
9255{
9256 connector->base.dpms = DRM_MODE_DPMS_OFF;
9257 connector->base.encoder = NULL;
9258 connector->encoder->connectors_active = false;
9259 connector->encoder->base.crtc = NULL;
9260}
9261
7fad798e
DV		 9262static void intel_enable_pipe_a(struct drm_device *dev)
9263{
9264 struct intel_connector *connector;
9265 struct drm_connector *crt = NULL;
9266 struct intel_load_detect_pipe load_detect_temp;
9267
9268 /* We can't just switch on the pipe A, we need to set things up with a
9269 * proper mode and output configuration. As a gross hack, enable pipe A
9270 * by enabling the load detect pipe once. */
9271 list_for_each_entry(connector,
9272 &dev->mode_config.connector_list,
9273 base.head) {
9274 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9275 crt = &connector->base;
9276 break;
9277 }
9278 }
9279
9280 if (!crt)
9281 return;
9282
9283 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9284 intel_release_load_detect_pipe(crt, &load_detect_temp);
9285
652c393a 9286
7fad798e
DV		 9287}
9288
fa555837
DV		 9289static bool
9290intel_check_plane_mapping(struct intel_crtc *crtc)
9291{
7eb552ae
BW		 9292 struct drm_device *dev = crtc->base.dev;
9293 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9294 u32 reg, val;
9295
7eb552ae 9296 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9297 return true;
9298
9299 reg = DSPCNTR(!crtc->plane);
9300 val = I915_READ(reg);
9301
9302 if ((val & DISPLAY_PLANE_ENABLE) &&
9303 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9304 return false;
9305
9306 return true;
9307}
9308
24929352
DV		 9309static void intel_sanitize_crtc(struct intel_crtc *crtc)
9310{
9311 struct drm_device *dev = crtc->base.dev;
9312 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9313 u32 reg;
24929352 9314
24929352 9315 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9316 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9317 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9318
9319 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9320 * disable the crtc (and hence change the state) if it is wrong. Note
9321 * that gen4+ has a fixed plane -> pipe mapping. */
9322 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9323 struct intel_connector *connector;
9324 bool plane;
9325
24929352
DV		 9326 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9327 crtc->base.base.id);
9328
9329 /* Pipe has the wrong plane attached and the plane is active.
9330 * Temporarily change the plane mapping and disable everything
9331 * ... */
9332 plane = crtc->plane;
9333 crtc->plane = !plane;
9334 dev_priv->display.crtc_disable(&crtc->base);
9335 crtc->plane = plane;
9336
9337 /* ... and break all links. */
9338 list_for_each_entry(connector, &dev->mode_config.connector_list,
9339 base.head) {
9340 if (connector->encoder->base.crtc != &crtc->base)
9341 continue;
9342
9343 intel_connector_break_all_links(connector);
9344 }
9345
9346 WARN_ON(crtc->active);
9347 crtc->base.enabled = false;
9348 }
24929352 9349
7fad798e
DV		 9350 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9351 crtc->pipe == PIPE_A && !crtc->active) {
9352 /* BIOS forgot to enable pipe A, this mostly happens after
9353 * resume. Force-enable the pipe to fix this, the update_dpms
9354 * call below we restore the pipe to the right state, but leave
9355 * the required bits on. */
9356 intel_enable_pipe_a(dev);
9357 }
9358
24929352
DV		 9359 /* Adjust the state of the output pipe according to whether we
9360 * have active connectors/encoders. */
9361 intel_crtc_update_dpms(&crtc->base);
9362
9363 if (crtc->active != crtc->base.enabled) {
9364 struct intel_encoder *encoder;
9365
9366 /* This can happen either due to bugs in the get_hw_state
9367 * functions or because the pipe is force-enabled due to the
9368 * pipe A quirk. */
9369 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9370 crtc->base.base.id,
9371 crtc->base.enabled ? "enabled" : "disabled",
9372 crtc->active ? "enabled" : "disabled");
9373
9374 crtc->base.enabled = crtc->active;
9375
9376 /* Because we only establish the connector -> encoder ->
9377 * crtc links if something is active, this means the
9378 * crtc is now deactivated. Break the links. connector
9379 * -> encoder links are only establish when things are
9380 * actually up, hence no need to break them. */
9381 WARN_ON(crtc->active);
9382
9383 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9384 WARN_ON(encoder->connectors_active);
9385 encoder->base.crtc = NULL;
9386 }
9387 }
9388}
9389
9390static void intel_sanitize_encoder(struct intel_encoder *encoder)
9391{
9392 struct intel_connector *connector;
9393 struct drm_device *dev = encoder->base.dev;
9394
9395 /* We need to check both for a crtc link (meaning that the
9396 * encoder is active and trying to read from a pipe) and the
9397 * pipe itself being active. */
9398 bool has_active_crtc = encoder->base.crtc &&
9399 to_intel_crtc(encoder->base.crtc)->active;
9400
9401 if (encoder->connectors_active && !has_active_crtc) {
9402 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9403 encoder->base.base.id,
9404 drm_get_encoder_name(&encoder->base));
9405
9406 /* Connector is active, but has no active pipe. This is
9407 * fallout from our resume register restoring. Disable
9408 * the encoder manually again. */
9409 if (encoder->base.crtc) {
9410 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9411 encoder->base.base.id,
9412 drm_get_encoder_name(&encoder->base));
9413 encoder->disable(encoder);
9414 }
9415
9416 /* Inconsistent output/port/pipe state happens presumably due to
9417 * a bug in one of the get_hw_state functions. Or someplace else
9418 * in our code, like the register restore mess on resume. Clamp
9419 * things to off as a safer default. */
9420 list_for_each_entry(connector,
9421 &dev->mode_config.connector_list,
9422 base.head) {
9423 if (connector->encoder != encoder)
9424 continue;
9425
9426 intel_connector_break_all_links(connector);
9427 }
9428 }
9429 /* Enabled encoders without active connectors will be fixed in
9430 * the crtc fixup. */
9431}
9432
44cec740 9433void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9434{
9435 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9436 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9437
9438 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9439 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9440 i915_disable_vga(dev);
0fde901f
KM		 9441 }
9442}
9443
24929352
DV		 9444/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9445 * and i915 state tracking structures. */
45e2b5f6
DV		 9446void intel_modeset_setup_hw_state(struct drm_device *dev,
9447 bool force_restore)
24929352
DV		 9448{
9449 struct drm_i915_private *dev_priv = dev->dev_private;
9450 enum pipe pipe;
b5644d05 9451 struct drm_plane *plane;
24929352
DV		 9452 struct intel_crtc *crtc;
9453 struct intel_encoder *encoder;
9454 struct intel_connector *connector;
9455
0e8ffe1b
DV		 9456 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9457 base.head) {
88adfff1 9458 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9459
0e8ffe1b
DV		 9460 crtc->active = dev_priv->display.get_pipe_config(crtc,
9461 &crtc->config);
24929352
DV		 9462
9463 crtc->base.enabled = crtc->active;
9464
9465 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9466 crtc->base.base.id,
9467 crtc->active ? "enabled" : "disabled");
9468 }
9469
affa9354 9470 if (HAS_DDI(dev))
6441ab5f
PZ		 9471 intel_ddi_setup_hw_pll_state(dev);
9472
24929352
DV		 9473 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9474 base.head) {
9475 pipe = 0;
9476
9477 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9478 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9479 encoder->base.crtc = &crtc->base;
9480 if (encoder->get_config)
9481 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9482 } else {
9483 encoder->base.crtc = NULL;
9484 }
9485
9486 encoder->connectors_active = false;
9487 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9488 encoder->base.base.id,
9489 drm_get_encoder_name(&encoder->base),
9490 encoder->base.crtc ? "enabled" : "disabled",
9491 pipe);
9492 }
9493
9494 list_for_each_entry(connector, &dev->mode_config.connector_list,
9495 base.head) {
9496 if (connector->get_hw_state(connector)) {
9497 connector->base.dpms = DRM_MODE_DPMS_ON;
9498 connector->encoder->connectors_active = true;
9499 connector->base.encoder = &connector->encoder->base;
9500 } else {
9501 connector->base.dpms = DRM_MODE_DPMS_OFF;
9502 connector->base.encoder = NULL;
9503 }
9504 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9505 connector->base.base.id,
9506 drm_get_connector_name(&connector->base),
9507 connector->base.encoder ? "enabled" : "disabled");
9508 }
9509
9510 /* HW state is read out, now we need to sanitize this mess. */
9511 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9512 base.head) {
9513 intel_sanitize_encoder(encoder);
9514 }
9515
9516 for_each_pipe(pipe) {
9517 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9518 intel_sanitize_crtc(crtc);
9519 }
9a935856 9520
45e2b5f6 9521 if (force_restore) {
f30da187
DV		 9522 /*
9523 * We need to use raw interfaces for restoring state to avoid
9524 * checking (bogus) intermediate states.
9525 */
45e2b5f6 9526 for_each_pipe(pipe) {
b5644d05
JB		 9527 struct drm_crtc *crtc =
9528 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9529
9530 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9531 crtc->fb);
45e2b5f6 9532 }
b5644d05
JB		 9533 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9534 intel_plane_restore(plane);
0fde901f
KM		 9535
9536 i915_redisable_vga(dev);
45e2b5f6
DV		 9537 } else {
9538 intel_modeset_update_staged_output_state(dev);
9539 }
8af6cf88
DV		 9540
9541 intel_modeset_check_state(dev);
2e938892
DV		 9542
9543 drm_mode_config_reset(dev);
2c7111db
CW		 9544}
9545
9546void intel_modeset_gem_init(struct drm_device *dev)
9547{
1833b134 9548 intel_modeset_init_hw(dev);
02e792fb
DV		 9549
9550 intel_setup_overlay(dev);
24929352 9551
45e2b5f6 9552 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9553}
9554
9555void intel_modeset_cleanup(struct drm_device *dev)
9556{
652c393a
JB		 9557 struct drm_i915_private *dev_priv = dev->dev_private;
9558 struct drm_crtc *crtc;
9559 struct intel_crtc *intel_crtc;
9560
fd0c0642
DV		 9561 /*
9562 * Interrupts and polling as the first thing to avoid creating havoc.
9563 * Too much stuff here (turning of rps, connectors, ...) would
9564 * experience fancy races otherwise.
9565 */
9566 drm_irq_uninstall(dev);
9567 cancel_work_sync(&dev_priv->hotplug_work);
9568 /*
9569 * Due to the hpd irq storm handling the hotplug work can re-arm the
9570 * poll handlers. Hence disable polling after hpd handling is shut down.
9571 */
f87ea761 9572 drm_kms_helper_poll_fini(dev);
fd0c0642 9573
652c393a
JB		 9574 mutex_lock(&dev->struct_mutex);
9575
723bfd70
JB		 9576 intel_unregister_dsm_handler();
9577
652c393a
JB		 9578 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9579 /* Skip inactive CRTCs */
9580 if (!crtc->fb)
9581 continue;
9582
9583 intel_crtc = to_intel_crtc(crtc);
3dec0095 9584 intel_increase_pllclock(crtc);
652c393a
JB		 9585 }
9586
973d04f9 9587 intel_disable_fbc(dev);
e70236a8 9588
8090c6b9 9589 intel_disable_gt_powersave(dev);
0cdab21f 9590
930ebb46
DV		 9591 ironlake_teardown_rc6(dev);
9592
69341a5e
KH		 9593 mutex_unlock(&dev->struct_mutex);
9594
1630fe75
CW		 9595 /* flush any delayed tasks or pending work */
9596 flush_scheduled_work();
9597
dc652f90
JN		 9598 /* destroy backlight, if any, before the connectors */
9599 intel_panel_destroy_backlight(dev);
9600
79e53945 9601 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9602
9603 intel_cleanup_overlay(dev);
79e53945
JB		 9604}
9605
f1c79df3
ZW		 9606/*
9607 * Return which encoder is currently attached for connector.
9608 */
df0e9248 9609struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9610{
df0e9248
CW		 9611 return &intel_attached_encoder(connector)->base;
9612}
f1c79df3 9613
df0e9248
CW		 9614void intel_connector_attach_encoder(struct intel_connector *connector,
9615 struct intel_encoder *encoder)
9616{
9617 connector->encoder = encoder;
9618 drm_mode_connector_attach_encoder(&connector->base,
9619 &encoder->base);
79e53945 9620}
28d52043
DA		 9621
9622/*
9623 * set vga decode state - true == enable VGA decode
9624 */
9625int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9626{
9627 struct drm_i915_private *dev_priv = dev->dev_private;
9628 u16 gmch_ctrl;
9629
9630 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9631 if (state)
9632 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9633 else
9634 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9635 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9636 return 0;
9637}
c4a1d9e4
CW		 9638
9639#ifdef CONFIG_DEBUG_FS
9640#include <linux/seq_file.h>
9641
9642struct intel_display_error_state {
ff57f1b0
PZ		 9643
9644 u32 power_well_driver;
9645
c4a1d9e4
CW		 9646 struct intel_cursor_error_state {
9647 u32 control;
9648 u32 position;
9649 u32 base;
9650 u32 size;
52331309 9651 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9652
9653 struct intel_pipe_error_state {
ff57f1b0 9654 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9655 u32 conf;
9656 u32 source;
9657
9658 u32 htotal;
9659 u32 hblank;
9660 u32 hsync;
9661 u32 vtotal;
9662 u32 vblank;
9663 u32 vsync;
52331309 9664 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9665
9666 struct intel_plane_error_state {
9667 u32 control;
9668 u32 stride;
9669 u32 size;
9670 u32 pos;
9671 u32 addr;
9672 u32 surface;
9673 u32 tile_offset;
52331309 9674 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9675};
9676
9677struct intel_display_error_state *
9678intel_display_capture_error_state(struct drm_device *dev)
9679{
0206e353 9680 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9681 struct intel_display_error_state *error;
702e7a56 9682 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9683 int i;
9684
9685 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9686 if (error == NULL)
9687 return NULL;
9688
ff57f1b0
PZ		 9689 if (HAS_POWER_WELL(dev))
9690 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9691
52331309 9692 for_each_pipe(i) {
702e7a56 9693 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9694 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9695
a18c4c3d
PZ		 9696 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9697 error->cursor[i].control = I915_READ(CURCNTR(i));
9698 error->cursor[i].position = I915_READ(CURPOS(i));
9699 error->cursor[i].base = I915_READ(CURBASE(i));
9700 } else {
9701 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9702 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9703 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9704 }
c4a1d9e4
CW		 9705
9706 error->plane[i].control = I915_READ(DSPCNTR(i));
9707 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9708 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9709 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9710 error->plane[i].pos = I915_READ(DSPPOS(i));
9711 }
ca291363
PZ		 9712 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9713 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9714 if (INTEL_INFO(dev)->gen >= 4) {
9715 error->plane[i].surface = I915_READ(DSPSURF(i));
9716 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9717 }
9718
702e7a56 9719 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9720 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9721 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9722 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9723 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9724 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9725 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9726 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9727 }
9728
12d217c7
PZ		 9729 /* In the code above we read the registers without checking if the power
9730 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9731 * prevent the next I915_WRITE from detecting it and printing an error
9732 * message. */
9733 if (HAS_POWER_WELL(dev))
9734 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9735
c4a1d9e4
CW		 9736 return error;
9737}
9738
edc3d884
MK		 9739#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9740
c4a1d9e4 9741void
edc3d884 9742intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9743 struct drm_device *dev,
9744 struct intel_display_error_state *error)
9745{
9746 int i;
9747
edc3d884 9748 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9749 if (HAS_POWER_WELL(dev))
edc3d884 9750 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9751 error->power_well_driver);
52331309 9752 for_each_pipe(i) {
edc3d884
MK		 9753 err_printf(m, "Pipe [%d]:\n", i);
9754 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9755 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9756 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9757 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9758 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9759 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9760 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9761 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9762 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9763 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9764
9765 err_printf(m, "Plane [%d]:\n", i);
9766 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9767 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9768 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9769 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9770 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9771 }
4b71a570 9772 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9773 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9774 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9775 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9776 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9777 }
9778
edc3d884
MK		 9779 err_printf(m, "Cursor [%d]:\n", i);
9780 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9781 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9782 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9783 }
9784}
9785#endif
Linux kernel - Deliverables
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