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drm/i915: Remove vestigial pitch from post-gen2 FBC control routines
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
291906f1
JB		 983static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
985{
47a05eca
JB		 986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 989 reg, pipe_name(pipe));
291906f1
JB		 990}
991
992static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
994{
47a05eca
JB		 995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 998 reg, pipe_name(pipe));
291906f1
JB		 999}
1000
1001static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
291906f1
JB		 1006
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011 reg = PCH_ADPA;
1012 val = I915_READ(reg);
47a05eca 1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 pipe_name(pipe));
291906f1
JB		 1016
1017 reg = PCH_LVDS;
1018 val = I915_READ(reg);
47a05eca 1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1021 pipe_name(pipe));
291906f1
JB		 1022
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026}
1027
63d7bbe9
JB		 1028/**
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1032 *
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1036 *
1037 * Note! This is for pre-ILK only.
1038 */
1039static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040{
1041 int reg;
1042 u32 val;
1043
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1046
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1054
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1057 POSTING_READ(reg);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1060 POSTING_READ(reg);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1063 POSTING_READ(reg);
1064 udelay(150); /* wait for warmup */
1065}
1066
1067/**
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1071 *
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 *
1074 * Note! This is for pre-ILK only.
1075 */
1076static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077{
1078 int reg;
1079 u32 val;
1080
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083 return;
1084
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1087
1088 reg = DPLL(pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1092 POSTING_READ(reg);
1093}
1094
92f2584a
JB		 1095/**
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1099 *
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1102 */
1103static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1111
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1114
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1119 POSTING_READ(reg);
1120 udelay(200);
1121}
1122
1123static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125{
1126 int reg;
1127 u32 val;
1128
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1131
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1134
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(200);
1141}
1142
040484af
JB		 1143static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
1146 int reg;
1147 u32 val;
1148
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1151
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1154
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
e9bcff5c
JB		 1161
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1163 /*
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1166 */
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169 }
040484af
JB		 1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173}
1174
1175static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int reg;
1179 u32 val;
1180
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1184
291906f1
JB		 1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1187
040484af
JB		 1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1195}
1196
b24e7179 1197/**
309cfea8 1198 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
040484af 1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1202 *
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205 *
1206 * @pipe should be %PIPE_A or %PIPE_B.
1207 *
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1209 * returning.
1210 */
040484af
JB		 1211static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212 bool pch_port)
b24e7179
JB		 1213{
1214 int reg;
1215 u32 val;
1216
1217 /*
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1220 * need the check.
1221 */
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1224 else {
1225 if (pch_port) {
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229 }
1230 /* FIXME: assert CPU port conditions for SNB+ */
1231 }
b24e7179
JB		 1232
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
00d70b15
CW		 1235 if (val & PIPECONF_ENABLE)
1236 return;
1237
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1240}
1241
1242/**
309cfea8 1243 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1246 *
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249 *
1250 * @pipe should be %PIPE_A or %PIPE_B.
1251 *
1252 * Will wait until the pipe has shut down before returning.
1253 */
1254static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
1257 int reg;
1258 u32 val;
1259
1260 /*
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1263 */
1264 assert_planes_disabled(dev_priv, pipe);
1265
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268 return;
1269
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
00d70b15
CW		 1272 if ((val & PIPECONF_ENABLE) == 0)
1273 return;
1274
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277}
1278
1279/**
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1284 *
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1286 */
1287static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
1292
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1295
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
00d70b15
CW		 1298 if (val & DISPLAY_PLANE_ENABLE)
1299 return;
1300
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1303}
1304
1305/*
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1308 */
1309static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310 enum plane plane)
1311{
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1314}
1315
1316/**
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1321 *
1322 * Disable @plane; should be an independent operation.
1323 */
1324static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1326{
1327 int reg;
1328 u32 val;
1329
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
00d70b15
CW		 1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333 return;
1334
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1338}
1339
47a05eca
JB		 1340static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1342{
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1346}
1347
1348static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1350{
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1354}
1355
1356/* Disable any ports connected to this transcoder */
1357static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359{
1360 u32 reg, val;
1361
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369 reg = PCH_ADPA;
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378 POSTING_READ(reg);
1379 udelay(100);
1380 }
1381
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385}
1386
43a9539f
CW		 1387static void i8xx_disable_fbc(struct drm_device *dev)
1388{
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 u32 fbc_ctl;
1391
1392 /* Disable compression */
1393 fbc_ctl = I915_READ(FBC_CONTROL);
1394 if ((fbc_ctl & FBC_CTL_EN) == 0)
1395 return;
1396
1397 fbc_ctl &= ~FBC_CTL_EN;
1398 I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400 /* Wait for compressing bit to clear */
1401 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402 DRM_DEBUG_KMS("FBC idle timed out\n");
1403 return;
1404 }
1405
1406 DRM_DEBUG_KMS("disabled FBC\n");
1407}
1408
80824003
JB		 1409static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1410{
1411 struct drm_device *dev = crtc->dev;
1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_framebuffer *fb = crtc->fb;
1414 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1415 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1417 int plane, i;
1418 u32 fbc_ctl, fbc_ctl2;
1419
bed4a673 1420 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1421 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1422 intel_crtc->plane == dev_priv->cfb_plane &&
1423 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1424 return;
1425
1426 i8xx_disable_fbc(dev);
1427
80824003
JB		 1428 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1429
1430 if (fb->pitch < dev_priv->cfb_pitch)
1431 dev_priv->cfb_pitch = fb->pitch;
1432
1433 /* FBC_CTL wants 64B units */
1434 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1435 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1436 dev_priv->cfb_plane = intel_crtc->plane;
1437 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1438
1439 /* Clear old tags */
1440 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1441 I915_WRITE(FBC_TAG + (i * 4), 0);
1442
1443 /* Set it up... */
1444 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1445 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1446 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1447 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1448 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1449
1450 /* enable it... */
1451 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1452 if (IS_I945GM(dev))
49677901 1453 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1454 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1455 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1456 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1457 fbc_ctl |= dev_priv->cfb_fence;
1458 I915_WRITE(FBC_CONTROL, fbc_ctl);
1459
28c97730 1460 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1461 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1462}
1463
ee5382ae 1464static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1465{
80824003
JB		 1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1469}
1470
74dff282
JB		 1471static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1472{
1473 struct drm_device *dev = crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_framebuffer *fb = crtc->fb;
1476 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1477 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1479 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1480 unsigned long stall_watermark = 200;
1481 u32 dpfc_ctl;
1482
bed4a673
CW		 1483 dpfc_ctl = I915_READ(DPFC_CONTROL);
1484 if (dpfc_ctl & DPFC_CTL_EN) {
f19a079a 1485 if (dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1486 dev_priv->cfb_plane == intel_crtc->plane &&
1487 dev_priv->cfb_y == crtc->y)
1488 return;
1489
1490 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1491 intel_wait_for_vblank(dev, intel_crtc->pipe);
1492 }
1493
05394f39 1494 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1495 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1496 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1497
1498 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1499 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1500 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1501 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1502 } else {
1503 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1504 }
1505
74dff282
JB		 1506 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1507 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1508 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1509 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1510
1511 /* enable it... */
1512 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1513
28c97730 1514 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1515}
1516
43a9539f 1517static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1518{
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 u32 dpfc_ctl;
1521
1522 /* Disable compression */
1523 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1524 if (dpfc_ctl & DPFC_CTL_EN) {
1525 dpfc_ctl &= ~DPFC_CTL_EN;
1526 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1527
bed4a673
CW		 1528 DRM_DEBUG_KMS("disabled FBC\n");
1529 }
74dff282
JB		 1530}
1531
ee5382ae 1532static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1533{
74dff282
JB		 1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535
1536 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1537}
1538
4efe0708
JB		 1539static void sandybridge_blit_fbc_update(struct drm_device *dev)
1540{
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 u32 blt_ecoskpd;
1543
1544 /* Make sure blitter notifies FBC of writes */
fcca7926 1545 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1546 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1547 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1548 GEN6_BLITTER_LOCK_SHIFT;
1549 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1551 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1552 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1553 GEN6_BLITTER_LOCK_SHIFT);
1554 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1555 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1556 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1557}
1558
b52eb4dc
ZY		 1559static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1560{
1561 struct drm_device *dev = crtc->dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 struct drm_framebuffer *fb = crtc->fb;
1564 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1565 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1567 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1568 unsigned long stall_watermark = 200;
1569 u32 dpfc_ctl;
1570
bed4a673
CW		 1571 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1572 if (dpfc_ctl & DPFC_CTL_EN) {
f19a079a 1573 if (dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1574 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1575 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1576 dev_priv->cfb_y == crtc->y)
1577 return;
1578
1579 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1580 intel_wait_for_vblank(dev, intel_crtc->pipe);
1581 }
1582
05394f39 1583 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1584 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1585 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1586 dev_priv->cfb_y = crtc->y;
b52eb4dc 1587
b52eb4dc
ZY		 1588 dpfc_ctl &= DPFC_RESERVED;
1589 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1590 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1591 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593 } else {
1594 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595 }
1596
b52eb4dc
ZY		 1597 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1601 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1602 /* enable it... */
bed4a673 1603 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1604
9c04f015
YL		 1605 if (IS_GEN6(dev)) {
1606 I915_WRITE(SNB_DPFC_CTL_SA,
1607 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1609 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1610 }
1611
b52eb4dc
ZY		 1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613}
1614
43a9539f 1615static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1625
bed4a673
CW		 1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
b52eb4dc
ZY		 1628}
1629
1630static bool ironlake_fbc_enabled(struct drm_device *dev)
1631{
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635}
1636
ee5382ae
AJ		 1637bool intel_fbc_enabled(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641 if (!dev_priv->display.fbc_enabled)
1642 return false;
1643
1644 return dev_priv->display.fbc_enabled(dev);
1645}
1646
43a9539f 1647static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae
AJ		 1648{
1649 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651 if (!dev_priv->display.enable_fbc)
1652 return;
1653
1654 dev_priv->display.enable_fbc(crtc, interval);
1655}
1656
1657void intel_disable_fbc(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 if (!dev_priv->display.disable_fbc)
1662 return;
1663
1664 dev_priv->display.disable_fbc(dev);
1665}
1666
80824003
JB		 1667/**
1668 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1669 * @dev: the drm_device
80824003
JB		 1670 *
1671 * Set up the framebuffer compression hardware at mode set time. We
1672 * enable it if possible:
1673 * - plane A only (on pre-965)
1674 * - no pixel mulitply/line duplication
1675 * - no alpha buffer discard
1676 * - no dual wide
1677 * - framebuffer <= 2048 in width, 1536 in height
1678 *
1679 * We can't assume that any compression will take place (worst case),
1680 * so the compressed buffer has to be the same size as the uncompressed
1681 * one. It also must reside (along with the line length buffer) in
1682 * stolen memory.
1683 *
1684 * We need to enable/disable FBC on a global basis.
1685 */
bed4a673 1686static void intel_update_fbc(struct drm_device *dev)
80824003 1687{
80824003 1688 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1689 struct drm_crtc *crtc = NULL, *tmp_crtc;
1690 struct intel_crtc *intel_crtc;
1691 struct drm_framebuffer *fb;
80824003 1692 struct intel_framebuffer *intel_fb;
05394f39 1693 struct drm_i915_gem_object *obj;
9c928d16
JB		 1694
1695 DRM_DEBUG_KMS("\n");
80824003
JB		 1696
1697 if (!i915_powersave)
1698 return;
1699
ee5382ae 1700 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1701 return;
1702
80824003
JB		 1703 /*
1704 * If FBC is already on, we just have to verify that we can
1705 * keep it that way...
1706 * Need to disable if:
9c928d16 1707 * - more than one pipe is active
80824003
JB		 1708 * - changing FBC params (stride, fence, mode)
1709 * - new fb is too large to fit in compressed buffer
1710 * - going to an unsupported config (interlace, pixel multiply, etc.)
1711 */
9c928d16 1712 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1713 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1714 if (crtc) {
1715 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717 goto out_disable;
1718 }
1719 crtc = tmp_crtc;
1720 }
9c928d16 1721 }
bed4a673
CW		 1722
1723 if (!crtc || crtc->fb == NULL) {
1724 DRM_DEBUG_KMS("no output, disabling\n");
1725 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1726 goto out_disable;
1727 }
bed4a673
CW		 1728
1729 intel_crtc = to_intel_crtc(crtc);
1730 fb = crtc->fb;
1731 intel_fb = to_intel_framebuffer(fb);
05394f39 1732 obj = intel_fb->obj;
bed4a673 1733
c1a9f047
JB		 1734 if (!i915_enable_fbc) {
1735 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1736 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1737 goto out_disable;
1738 }
05394f39 1739 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1740 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1741 "compression\n");
b5e50c3f 1742 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1743 goto out_disable;
1744 }
bed4a673
CW		 1745 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1746 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1747 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1748 "disabling\n");
b5e50c3f 1749 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1750 goto out_disable;
1751 }
bed4a673
CW		 1752 if ((crtc->mode.hdisplay > 2048) ||
1753 (crtc->mode.vdisplay > 1536)) {
28c97730 1754 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1755 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1756 goto out_disable;
1757 }
bed4a673 1758 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1759 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1760 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1761 goto out_disable;
1762 }
05394f39 1763 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1764 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1765 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1766 goto out_disable;
1767 }
1768
c924b934
JW		 1769 /* If the kernel debugger is active, always disable compression */
1770 if (in_dbg_master())
1771 goto out_disable;
1772
bed4a673 1773 intel_enable_fbc(crtc, 500);
80824003
JB		 1774 return;
1775
1776out_disable:
80824003 1777 /* Multiple disables should be harmless */
a939406f
CW		 1778 if (intel_fbc_enabled(dev)) {
1779 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1780 intel_disable_fbc(dev);
a939406f 1781 }
80824003
JB		 1782}
1783
127bd2ac 1784int
48b956c5 1785intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1786 struct drm_i915_gem_object *obj,
919926ae 1787 struct intel_ring_buffer *pipelined)
6b95a207 1788{
ce453d81 1789 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1790 u32 alignment;
1791 int ret;
1792
05394f39 1793 switch (obj->tiling_mode) {
6b95a207 1794 case I915_TILING_NONE:
534843da
CW		 1795 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1796 alignment = 128 * 1024;
a6c45cf0 1797 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1798 alignment = 4 * 1024;
1799 else
1800 alignment = 64 * 1024;
6b95a207
KH		 1801 break;
1802 case I915_TILING_X:
1803 /* pin() will align the object as required by fence */
1804 alignment = 0;
1805 break;
1806 case I915_TILING_Y:
1807 /* FIXME: Is this true? */
1808 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1809 return -EINVAL;
1810 default:
1811 BUG();
1812 }
1813
ce453d81 1814 dev_priv->mm.interruptible = false;
2da3b9b9 1815 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1816 if (ret)
ce453d81 1817 goto err_interruptible;
6b95a207
KH		 1818
1819 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1820 * fence, whereas 965+ only requires a fence if using
1821 * framebuffer compression. For simplicity, we always install
1822 * a fence as the cost is not that onerous.
1823 */
05394f39 1824 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1825 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1826 if (ret)
1827 goto err_unpin;
6b95a207
KH		 1828 }
1829
ce453d81 1830 dev_priv->mm.interruptible = true;
6b95a207 1831 return 0;
48b956c5
CW		 1832
1833err_unpin:
1834 i915_gem_object_unpin(obj);
ce453d81
CW		 1835err_interruptible:
1836 dev_priv->mm.interruptible = true;
48b956c5 1837 return ret;
6b95a207
KH		 1838}
1839
17638cd6
JB		 1840static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1841 int x, int y)
81255565
JB		 1842{
1843 struct drm_device *dev = crtc->dev;
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1846 struct intel_framebuffer *intel_fb;
05394f39 1847 struct drm_i915_gem_object *obj;
81255565
JB		 1848 int plane = intel_crtc->plane;
1849 unsigned long Start, Offset;
81255565 1850 u32 dspcntr;
5eddb70b 1851 u32 reg;
81255565
JB		 1852
1853 switch (plane) {
1854 case 0:
1855 case 1:
1856 break;
1857 default:
1858 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1859 return -EINVAL;
1860 }
1861
1862 intel_fb = to_intel_framebuffer(fb);
1863 obj = intel_fb->obj;
81255565 1864
5eddb70b
CW		 1865 reg = DSPCNTR(plane);
1866 dspcntr = I915_READ(reg);
81255565
JB		 1867 /* Mask out pixel format bits in case we change it */
1868 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1869 switch (fb->bits_per_pixel) {
1870 case 8:
1871 dspcntr |= DISPPLANE_8BPP;
1872 break;
1873 case 16:
1874 if (fb->depth == 15)
1875 dspcntr |= DISPPLANE_15_16BPP;
1876 else
1877 dspcntr |= DISPPLANE_16BPP;
1878 break;
1879 case 24:
1880 case 32:
1881 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1882 break;
1883 default:
17638cd6 1884 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1885 return -EINVAL;
1886 }
a6c45cf0 1887 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1888 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1889 dspcntr |= DISPPLANE_TILED;
1890 else
1891 dspcntr &= ~DISPPLANE_TILED;
1892 }
1893
5eddb70b 1894 I915_WRITE(reg, dspcntr);
81255565 1895
05394f39 1896 Start = obj->gtt_offset;
81255565
JB		 1897 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1898
4e6cfefc
CW		 1899 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1900 Start, Offset, x, y, fb->pitch);
5eddb70b 1901 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1902 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1903 I915_WRITE(DSPSURF(plane), Start);
1904 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1905 I915_WRITE(DSPADDR(plane), Offset);
1906 } else
1907 I915_WRITE(DSPADDR(plane), Start + Offset);
1908 POSTING_READ(reg);
81255565 1909
17638cd6
JB		 1910 return 0;
1911}
1912
1913static int ironlake_update_plane(struct drm_crtc *crtc,
1914 struct drm_framebuffer *fb, int x, int y)
1915{
1916 struct drm_device *dev = crtc->dev;
1917 struct drm_i915_private *dev_priv = dev->dev_private;
1918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1919 struct intel_framebuffer *intel_fb;
1920 struct drm_i915_gem_object *obj;
1921 int plane = intel_crtc->plane;
1922 unsigned long Start, Offset;
1923 u32 dspcntr;
1924 u32 reg;
1925
1926 switch (plane) {
1927 case 0:
1928 case 1:
1929 break;
1930 default:
1931 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1932 return -EINVAL;
1933 }
1934
1935 intel_fb = to_intel_framebuffer(fb);
1936 obj = intel_fb->obj;
1937
1938 reg = DSPCNTR(plane);
1939 dspcntr = I915_READ(reg);
1940 /* Mask out pixel format bits in case we change it */
1941 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1942 switch (fb->bits_per_pixel) {
1943 case 8:
1944 dspcntr |= DISPPLANE_8BPP;
1945 break;
1946 case 16:
1947 if (fb->depth != 16)
1948 return -EINVAL;
1949
1950 dspcntr |= DISPPLANE_16BPP;
1951 break;
1952 case 24:
1953 case 32:
1954 if (fb->depth == 24)
1955 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1956 else if (fb->depth == 30)
1957 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1958 else
1959 return -EINVAL;
1960 break;
1961 default:
1962 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1963 return -EINVAL;
1964 }
1965
1966 if (obj->tiling_mode != I915_TILING_NONE)
1967 dspcntr |= DISPPLANE_TILED;
1968 else
1969 dspcntr &= ~DISPPLANE_TILED;
1970
1971 /* must disable */
1972 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1973
1974 I915_WRITE(reg, dspcntr);
1975
1976 Start = obj->gtt_offset;
1977 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1978
1979 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1980 Start, Offset, x, y, fb->pitch);
1981 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1982 I915_WRITE(DSPSURF(plane), Start);
1983 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1984 I915_WRITE(DSPADDR(plane), Offset);
1985 POSTING_READ(reg);
1986
1987 return 0;
1988}
1989
1990/* Assume fb object is pinned & idle & fenced and just update base pointers */
1991static int
1992intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1993 int x, int y, enum mode_set_atomic state)
1994{
1995 struct drm_device *dev = crtc->dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 int ret;
1998
1999 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2000 if (ret)
2001 return ret;
2002
bed4a673 2003 intel_update_fbc(dev);
3dec0095 2004 intel_increase_pllclock(crtc);
81255565
JB		 2005
2006 return 0;
2007}
2008
5c3b82e2 2009static int
3c4fdcfb
KH		 2010intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2011 struct drm_framebuffer *old_fb)
79e53945
JB		 2012{
2013 struct drm_device *dev = crtc->dev;
79e53945
JB		 2014 struct drm_i915_master_private *master_priv;
2015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2016 int ret;
79e53945
JB		 2017
2018 /* no fb bound */
2019 if (!crtc->fb) {
28c97730 2020 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 2021 return 0;
2022 }
2023
265db958 2024 switch (intel_crtc->plane) {
5c3b82e2
CW		 2025 case 0:
2026 case 1:
2027 break;
2028 default:
5c3b82e2 2029 return -EINVAL;
79e53945
JB		 2030 }
2031
5c3b82e2 2032 mutex_lock(&dev->struct_mutex);
265db958
CW		 2033 ret = intel_pin_and_fence_fb_obj(dev,
2034 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2035 NULL);
5c3b82e2
CW		 2036 if (ret != 0) {
2037 mutex_unlock(&dev->struct_mutex);
2038 return ret;
2039 }
79e53945 2040
265db958 2041 if (old_fb) {
e6c3a2a6 2042 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2043 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2044
e6c3a2a6 2045 wait_event(dev_priv->pending_flip_queue,
01eec727 2046 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2047 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2048
2049 /* Big Hammer, we also need to ensure that any pending
2050 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2051 * current scanout is retired before unpinning the old
2052 * framebuffer.
01eec727
CW		 2053 *
2054 * This should only fail upon a hung GPU, in which case we
2055 * can safely continue.
85345517 2056 */
a8198eea 2057 ret = i915_gem_object_finish_gpu(obj);
01eec727 2058 (void) ret;
265db958
CW		 2059 }
2060
21c74a8e
JW		 2061 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2062 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2063 if (ret) {
265db958 2064 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2065 mutex_unlock(&dev->struct_mutex);
4e6cfefc 2066 return ret;
79e53945 2067 }
3c4fdcfb 2068
b7f1de28
CW		 2069 if (old_fb) {
2070 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2071 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2072 }
652c393a 2073
5c3b82e2 2074 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2075
2076 if (!dev->primary->master)
5c3b82e2 2077 return 0;
79e53945
JB		 2078
2079 master_priv = dev->primary->master->driver_priv;
2080 if (!master_priv->sarea_priv)
5c3b82e2 2081 return 0;
79e53945 2082
265db958 2083 if (intel_crtc->pipe) {
79e53945
JB		 2084 master_priv->sarea_priv->pipeB_x = x;
2085 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2086 } else {
2087 master_priv->sarea_priv->pipeA_x = x;
2088 master_priv->sarea_priv->pipeA_y = y;
79e53945 2089 }
5c3b82e2
CW		 2090
2091 return 0;
79e53945
JB		 2092}
2093
5eddb70b 2094static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2095{
2096 struct drm_device *dev = crtc->dev;
2097 struct drm_i915_private *dev_priv = dev->dev_private;
2098 u32 dpa_ctl;
2099
28c97730 2100 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2101 dpa_ctl = I915_READ(DP_A);
2102 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2103
2104 if (clock < 200000) {
2105 u32 temp;
2106 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2107 /* workaround for 160Mhz:
2108 1) program 0x4600c bits 15:0 = 0x8124
2109 2) program 0x46010 bit 0 = 1
2110 3) program 0x46034 bit 24 = 1
2111 4) program 0x64000 bit 14 = 1
2112 */
2113 temp = I915_READ(0x4600c);
2114 temp &= 0xffff0000;
2115 I915_WRITE(0x4600c, temp | 0x8124);
2116
2117 temp = I915_READ(0x46010);
2118 I915_WRITE(0x46010, temp | 1);
2119
2120 temp = I915_READ(0x46034);
2121 I915_WRITE(0x46034, temp | (1 << 24));
2122 } else {
2123 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2124 }
2125 I915_WRITE(DP_A, dpa_ctl);
2126
5eddb70b 2127 POSTING_READ(DP_A);
32f9d658
ZW		 2128 udelay(500);
2129}
2130
5e84e1a4
ZW		 2131static void intel_fdi_normal_train(struct drm_crtc *crtc)
2132{
2133 struct drm_device *dev = crtc->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136 int pipe = intel_crtc->pipe;
2137 u32 reg, temp;
2138
2139 /* enable normal train */
2140 reg = FDI_TX_CTL(pipe);
2141 temp = I915_READ(reg);
61e499bf 2142 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2143 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2144 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2145 } else {
2146 temp &= ~FDI_LINK_TRAIN_NONE;
2147 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2148 }
5e84e1a4
ZW		 2149 I915_WRITE(reg, temp);
2150
2151 reg = FDI_RX_CTL(pipe);
2152 temp = I915_READ(reg);
2153 if (HAS_PCH_CPT(dev)) {
2154 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2155 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2156 } else {
2157 temp &= ~FDI_LINK_TRAIN_NONE;
2158 temp |= FDI_LINK_TRAIN_NONE;
2159 }
2160 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2161
2162 /* wait one idle pattern time */
2163 POSTING_READ(reg);
2164 udelay(1000);
357555c0
JB		 2165
2166 /* IVB wants error correction enabled */
2167 if (IS_IVYBRIDGE(dev))
2168 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2169 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2170}
2171
8db9d77b
ZW		 2172/* The FDI link training functions for ILK/Ibexpeak. */
2173static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2174{
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178 int pipe = intel_crtc->pipe;
0fc932b8 2179 int plane = intel_crtc->plane;
5eddb70b 2180 u32 reg, temp, tries;
8db9d77b 2181
0fc932b8
JB		 2182 /* FDI needs bits from pipe & plane first */
2183 assert_pipe_enabled(dev_priv, pipe);
2184 assert_plane_enabled(dev_priv, plane);
2185
e1a44743
AJ		 2186 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2187 for train result */
5eddb70b
CW		 2188 reg = FDI_RX_IMR(pipe);
2189 temp = I915_READ(reg);
e1a44743
AJ		 2190 temp &= ~FDI_RX_SYMBOL_LOCK;
2191 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2192 I915_WRITE(reg, temp);
2193 I915_READ(reg);
e1a44743
AJ		 2194 udelay(150);
2195
8db9d77b 2196 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2197 reg = FDI_TX_CTL(pipe);
2198 temp = I915_READ(reg);
77ffb597
AJ		 2199 temp &= ~(7 << 19);
2200 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2201 temp &= ~FDI_LINK_TRAIN_NONE;
2202 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2203 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2204
5eddb70b
CW		 2205 reg = FDI_RX_CTL(pipe);
2206 temp = I915_READ(reg);
8db9d77b
ZW		 2207 temp &= ~FDI_LINK_TRAIN_NONE;
2208 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2209 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2210
2211 POSTING_READ(reg);
8db9d77b
ZW		 2212 udelay(150);
2213
5b2adf89 2214 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2215 if (HAS_PCH_IBX(dev)) {
2216 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2217 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2218 FDI_RX_PHASE_SYNC_POINTER_EN);
2219 }
5b2adf89 2220
5eddb70b 2221 reg = FDI_RX_IIR(pipe);
e1a44743 2222 for (tries = 0; tries < 5; tries++) {
5eddb70b 2223 temp = I915_READ(reg);
8db9d77b
ZW		 2224 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2225
2226 if ((temp & FDI_RX_BIT_LOCK)) {
2227 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2228 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2229 break;
2230 }
8db9d77b 2231 }
e1a44743 2232 if (tries == 5)
5eddb70b 2233 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2234
2235 /* Train 2 */
5eddb70b
CW		 2236 reg = FDI_TX_CTL(pipe);
2237 temp = I915_READ(reg);
8db9d77b
ZW		 2238 temp &= ~FDI_LINK_TRAIN_NONE;
2239 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2240 I915_WRITE(reg, temp);
8db9d77b 2241
5eddb70b
CW		 2242 reg = FDI_RX_CTL(pipe);
2243 temp = I915_READ(reg);
8db9d77b
ZW		 2244 temp &= ~FDI_LINK_TRAIN_NONE;
2245 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2246 I915_WRITE(reg, temp);
8db9d77b 2247
5eddb70b
CW		 2248 POSTING_READ(reg);
2249 udelay(150);
8db9d77b 2250
5eddb70b 2251 reg = FDI_RX_IIR(pipe);
e1a44743 2252 for (tries = 0; tries < 5; tries++) {
5eddb70b 2253 temp = I915_READ(reg);
8db9d77b
ZW		 2254 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2255
2256 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2257 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2258 DRM_DEBUG_KMS("FDI train 2 done.\n");
2259 break;
2260 }
8db9d77b 2261 }
e1a44743 2262 if (tries == 5)
5eddb70b 2263 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2264
2265 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2266
8db9d77b
ZW		 2267}
2268
311bd68e 2269static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2270 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2271 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2272 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2273 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2274};
2275
2276/* The FDI link training functions for SNB/Cougarpoint. */
2277static void gen6_fdi_link_train(struct drm_crtc *crtc)
2278{
2279 struct drm_device *dev = crtc->dev;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2282 int pipe = intel_crtc->pipe;
5eddb70b 2283 u32 reg, temp, i;
8db9d77b 2284
e1a44743
AJ		 2285 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2286 for train result */
5eddb70b
CW		 2287 reg = FDI_RX_IMR(pipe);
2288 temp = I915_READ(reg);
e1a44743
AJ		 2289 temp &= ~FDI_RX_SYMBOL_LOCK;
2290 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2291 I915_WRITE(reg, temp);
2292
2293 POSTING_READ(reg);
e1a44743
AJ		 2294 udelay(150);
2295
8db9d77b 2296 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2297 reg = FDI_TX_CTL(pipe);
2298 temp = I915_READ(reg);
77ffb597
AJ		 2299 temp &= ~(7 << 19);
2300 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2301 temp &= ~FDI_LINK_TRAIN_NONE;
2302 temp |= FDI_LINK_TRAIN_PATTERN_1;
2303 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2304 /* SNB-B */
2305 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2306 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2307
5eddb70b
CW		 2308 reg = FDI_RX_CTL(pipe);
2309 temp = I915_READ(reg);
8db9d77b
ZW		 2310 if (HAS_PCH_CPT(dev)) {
2311 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2312 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2313 } else {
2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
2316 }
5eddb70b
CW		 2317 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2318
2319 POSTING_READ(reg);
8db9d77b
ZW		 2320 udelay(150);
2321
8db9d77b 2322 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2323 reg = FDI_TX_CTL(pipe);
2324 temp = I915_READ(reg);
8db9d77b
ZW		 2325 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2326 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2327 I915_WRITE(reg, temp);
2328
2329 POSTING_READ(reg);
8db9d77b
ZW		 2330 udelay(500);
2331
5eddb70b
CW		 2332 reg = FDI_RX_IIR(pipe);
2333 temp = I915_READ(reg);
8db9d77b
ZW		 2334 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2335
2336 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2337 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
2339 break;
2340 }
2341 }
2342 if (i == 4)
5eddb70b 2343 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2344
2345 /* Train 2 */
5eddb70b
CW		 2346 reg = FDI_TX_CTL(pipe);
2347 temp = I915_READ(reg);
8db9d77b
ZW		 2348 temp &= ~FDI_LINK_TRAIN_NONE;
2349 temp |= FDI_LINK_TRAIN_PATTERN_2;
2350 if (IS_GEN6(dev)) {
2351 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2352 /* SNB-B */
2353 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2354 }
5eddb70b 2355 I915_WRITE(reg, temp);
8db9d77b 2356
5eddb70b
CW		 2357 reg = FDI_RX_CTL(pipe);
2358 temp = I915_READ(reg);
8db9d77b
ZW		 2359 if (HAS_PCH_CPT(dev)) {
2360 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2361 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2362 } else {
2363 temp &= ~FDI_LINK_TRAIN_NONE;
2364 temp |= FDI_LINK_TRAIN_PATTERN_2;
2365 }
5eddb70b
CW		 2366 I915_WRITE(reg, temp);
2367
2368 POSTING_READ(reg);
8db9d77b
ZW		 2369 udelay(150);
2370
2371 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
8db9d77b
ZW		 2374 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2375 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2376 I915_WRITE(reg, temp);
2377
2378 POSTING_READ(reg);
8db9d77b
ZW		 2379 udelay(500);
2380
5eddb70b
CW		 2381 reg = FDI_RX_IIR(pipe);
2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI train 2 done.\n");
2388 break;
2389 }
2390 }
2391 if (i == 4)
5eddb70b 2392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2393
2394 DRM_DEBUG_KMS("FDI train done.\n");
2395}
2396
357555c0
JB		 2397/* Manual link training for Ivy Bridge A0 parts */
2398static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 u32 reg, temp, i;
2405
2406 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2407 for train result */
2408 reg = FDI_RX_IMR(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_RX_SYMBOL_LOCK;
2411 temp &= ~FDI_RX_BIT_LOCK;
2412 I915_WRITE(reg, temp);
2413
2414 POSTING_READ(reg);
2415 udelay(150);
2416
2417 /* enable CPU FDI TX and PCH FDI RX */
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 temp &= ~(7 << 19);
2421 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2422 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2423 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2424 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2427
2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_LINK_TRAIN_AUTO;
2431 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2432 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2433 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2434
2435 POSTING_READ(reg);
2436 udelay(150);
2437
2438 for (i = 0; i < 4; i++ ) {
2439 reg = FDI_TX_CTL(pipe);
2440 temp = I915_READ(reg);
2441 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2442 temp |= snb_b_fdi_train_param[i];
2443 I915_WRITE(reg, temp);
2444
2445 POSTING_READ(reg);
2446 udelay(500);
2447
2448 reg = FDI_RX_IIR(pipe);
2449 temp = I915_READ(reg);
2450 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2451
2452 if (temp & FDI_RX_BIT_LOCK ||
2453 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2454 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2455 DRM_DEBUG_KMS("FDI train 1 done.\n");
2456 break;
2457 }
2458 }
2459 if (i == 4)
2460 DRM_ERROR("FDI train 1 fail!\n");
2461
2462 /* Train 2 */
2463 reg = FDI_TX_CTL(pipe);
2464 temp = I915_READ(reg);
2465 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2467 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2468 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2469 I915_WRITE(reg, temp);
2470
2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
2478 udelay(150);
2479
2480 for (i = 0; i < 4; i++ ) {
2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484 temp |= snb_b_fdi_train_param[i];
2485 I915_WRITE(reg, temp);
2486
2487 POSTING_READ(reg);
2488 udelay(500);
2489
2490 reg = FDI_RX_IIR(pipe);
2491 temp = I915_READ(reg);
2492 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2493
2494 if (temp & FDI_RX_SYMBOL_LOCK) {
2495 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2496 DRM_DEBUG_KMS("FDI train 2 done.\n");
2497 break;
2498 }
2499 }
2500 if (i == 4)
2501 DRM_ERROR("FDI train 2 fail!\n");
2502
2503 DRM_DEBUG_KMS("FDI train done.\n");
2504}
2505
2506static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
5eddb70b 2512 u32 reg, temp;
79e53945 2513
c64e311e 2514 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2515 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2516 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2517
c98e9dcf 2518 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2519 reg = FDI_RX_CTL(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2522 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2523 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2524 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2525
2526 POSTING_READ(reg);
c98e9dcf
JB		 2527 udelay(200);
2528
2529 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2530 temp = I915_READ(reg);
2531 I915_WRITE(reg, temp | FDI_PCDCLK);
2532
2533 POSTING_READ(reg);
c98e9dcf
JB		 2534 udelay(200);
2535
2536 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2537 reg = FDI_TX_CTL(pipe);
2538 temp = I915_READ(reg);
c98e9dcf 2539 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2540 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2541
2542 POSTING_READ(reg);
c98e9dcf 2543 udelay(100);
6be4a607 2544 }
0e23b99d
JB		 2545}
2546
0fc932b8
JB		 2547static void ironlake_fdi_disable(struct drm_crtc *crtc)
2548{
2549 struct drm_device *dev = crtc->dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2552 int pipe = intel_crtc->pipe;
2553 u32 reg, temp;
2554
2555 /* disable CPU FDI tx and PCH FDI rx */
2556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
2558 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2559 POSTING_READ(reg);
2560
2561 reg = FDI_RX_CTL(pipe);
2562 temp = I915_READ(reg);
2563 temp &= ~(0x7 << 16);
2564 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2565 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2566
2567 POSTING_READ(reg);
2568 udelay(100);
2569
2570 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2571 if (HAS_PCH_IBX(dev)) {
2572 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2573 I915_WRITE(FDI_RX_CHICKEN(pipe),
2574 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2575 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2576 }
0fc932b8
JB		 2577
2578 /* still set train pattern 1 */
2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
2581 temp &= ~FDI_LINK_TRAIN_NONE;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583 I915_WRITE(reg, temp);
2584
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590 } else {
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_1;
2593 }
2594 /* BPC in FDI rx is consistent with that in PIPECONF */
2595 temp &= ~(0x07 << 16);
2596 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2597 I915_WRITE(reg, temp);
2598
2599 POSTING_READ(reg);
2600 udelay(100);
2601}
2602
6b383a7f
CW		 2603/*
2604 * When we disable a pipe, we need to clear any pending scanline wait events
2605 * to avoid hanging the ring, which we assume we are waiting on.
2606 */
2607static void intel_clear_scanline_wait(struct drm_device *dev)
2608{
2609 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2610 struct intel_ring_buffer *ring;
6b383a7f
CW		 2611 u32 tmp;
2612
2613 if (IS_GEN2(dev))
2614 /* Can't break the hang on i8xx */
2615 return;
2616
1ec14ad3 2617 ring = LP_RING(dev_priv);
8168bd48
CW		 2618 tmp = I915_READ_CTL(ring);
2619 if (tmp & RING_WAIT)
2620 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2621}
2622
e6c3a2a6
CW		 2623static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2624{
05394f39 2625 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2626 struct drm_i915_private *dev_priv;
2627
2628 if (crtc->fb == NULL)
2629 return;
2630
05394f39 2631 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2632 dev_priv = crtc->dev->dev_private;
2633 wait_event(dev_priv->pending_flip_queue,
05394f39 2634 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2635}
2636
040484af
JB		 2637static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_mode_config *mode_config = &dev->mode_config;
2641 struct intel_encoder *encoder;
2642
2643 /*
2644 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2645 * must be driven by its own crtc; no sharing is possible.
2646 */
2647 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2648 if (encoder->base.crtc != crtc)
2649 continue;
2650
2651 switch (encoder->type) {
2652 case INTEL_OUTPUT_EDP:
2653 if (!intel_encoder_is_pch_edp(&encoder->base))
2654 return false;
2655 continue;
2656 }
2657 }
2658
2659 return true;
2660}
2661
f67a559d
JB		 2662/*
2663 * Enable PCH resources required for PCH ports:
2664 * - PCH PLLs
2665 * - FDI training & RX/TX
2666 * - update transcoder timings
2667 * - DP transcoding bits
2668 * - transcoder
2669 */
2670static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2671{
2672 struct drm_device *dev = crtc->dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2675 int pipe = intel_crtc->pipe;
5eddb70b 2676 u32 reg, temp;
2c07245f 2677
c98e9dcf 2678 /* For PCH output, training FDI link */
674cf967 2679 dev_priv->display.fdi_link_train(crtc);
2c07245f 2680
92f2584a 2681 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2682
c98e9dcf
JB		 2683 if (HAS_PCH_CPT(dev)) {
2684 /* Be sure PCH DPLL SEL is set */
2685 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2686 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2687 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2688 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2689 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2690 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2691 }
5eddb70b 2692
d9b6cb56
JB		 2693 /* set transcoder timing, panel must allow it */
2694 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2695 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2696 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2697 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2698
5eddb70b
CW		 2699 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2700 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2701 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2702
5e84e1a4
ZW		 2703 intel_fdi_normal_train(crtc);
2704
c98e9dcf
JB		 2705 /* For PCH DP, enable TRANS_DP_CTL */
2706 if (HAS_PCH_CPT(dev) &&
2707 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2708 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2709 reg = TRANS_DP_CTL(pipe);
2710 temp = I915_READ(reg);
2711 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2712 TRANS_DP_SYNC_MASK |
2713 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2714 temp |= (TRANS_DP_OUTPUT_ENABLE |
2715 TRANS_DP_ENH_FRAMING);
9325c9f0 2716 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2717
2718 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2719 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2720 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2721 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2722
2723 switch (intel_trans_dp_port_sel(crtc)) {
2724 case PCH_DP_B:
5eddb70b 2725 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2726 break;
2727 case PCH_DP_C:
5eddb70b 2728 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2729 break;
2730 case PCH_DP_D:
5eddb70b 2731 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2732 break;
2733 default:
2734 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2735 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2736 break;
32f9d658 2737 }
2c07245f 2738
5eddb70b 2739 I915_WRITE(reg, temp);
6be4a607 2740 }
b52eb4dc 2741
040484af 2742 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2743}
2744
2745static void ironlake_crtc_enable(struct drm_crtc *crtc)
2746{
2747 struct drm_device *dev = crtc->dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2750 int pipe = intel_crtc->pipe;
2751 int plane = intel_crtc->plane;
2752 u32 temp;
2753 bool is_pch_port;
2754
2755 if (intel_crtc->active)
2756 return;
2757
2758 intel_crtc->active = true;
2759 intel_update_watermarks(dev);
2760
2761 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2762 temp = I915_READ(PCH_LVDS);
2763 if ((temp & LVDS_PORT_EN) == 0)
2764 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2765 }
2766
2767 is_pch_port = intel_crtc_driving_pch(crtc);
2768
2769 if (is_pch_port)
357555c0 2770 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2771 else
2772 ironlake_fdi_disable(crtc);
2773
2774 /* Enable panel fitting for LVDS */
2775 if (dev_priv->pch_pf_size &&
2776 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2777 /* Force use of hard-coded filter coefficients
2778 * as some pre-programmed values are broken,
2779 * e.g. x201.
2780 */
9db4a9c7
JB		 2781 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2782 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2783 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2784 }
2785
2786 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2787 intel_enable_plane(dev_priv, plane, pipe);
2788
2789 if (is_pch_port)
2790 ironlake_pch_enable(crtc);
c98e9dcf 2791
6be4a607 2792 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2793
2794 mutex_lock(&dev->struct_mutex);
bed4a673 2795 intel_update_fbc(dev);
d1ebd816
BW		 2796 mutex_unlock(&dev->struct_mutex);
2797
6b383a7f 2798 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2799}
2800
2801static void ironlake_crtc_disable(struct drm_crtc *crtc)
2802{
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 int pipe = intel_crtc->pipe;
2807 int plane = intel_crtc->plane;
5eddb70b 2808 u32 reg, temp;
b52eb4dc 2809
f7abfe8b
CW		 2810 if (!intel_crtc->active)
2811 return;
2812
e6c3a2a6 2813 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2814 drm_vblank_off(dev, pipe);
6b383a7f 2815 intel_crtc_update_cursor(crtc, false);
5eddb70b 2816
b24e7179 2817 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2818
973d04f9
CW		 2819 if (dev_priv->cfb_plane == plane)
2820 intel_disable_fbc(dev);
2c07245f 2821
b24e7179 2822 intel_disable_pipe(dev_priv, pipe);
32f9d658 2823
6be4a607 2824 /* Disable PF */
9db4a9c7
JB		 2825 I915_WRITE(PF_CTL(pipe), 0);
2826 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2827
0fc932b8 2828 ironlake_fdi_disable(crtc);
2c07245f 2829
47a05eca
JB		 2830 /* This is a horrible layering violation; we should be doing this in
2831 * the connector/encoder ->prepare instead, but we don't always have
2832 * enough information there about the config to know whether it will
2833 * actually be necessary or just cause undesired flicker.
2834 */
2835 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2836
040484af 2837 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2838
6be4a607
JB		 2839 if (HAS_PCH_CPT(dev)) {
2840 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2841 reg = TRANS_DP_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2844 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2845 I915_WRITE(reg, temp);
6be4a607
JB		 2846
2847 /* disable DPLL_SEL */
2848 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2849 switch (pipe) {
2850 case 0:
2851 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2852 break;
2853 case 1:
6be4a607 2854 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2855 break;
2856 case 2:
2857 /* FIXME: manage transcoder PLLs? */
2858 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2859 break;
2860 default:
2861 BUG(); /* wtf */
2862 }
6be4a607 2863 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2864 }
e3421a18 2865
6be4a607 2866 /* disable PCH DPLL */
92f2584a 2867 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2868
6be4a607 2869 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2870 reg = FDI_RX_CTL(pipe);
2871 temp = I915_READ(reg);
2872 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2873
6be4a607 2874 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2875 reg = FDI_TX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2878
2879 POSTING_READ(reg);
6be4a607 2880 udelay(100);
8db9d77b 2881
5eddb70b
CW		 2882 reg = FDI_RX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2885
6be4a607 2886 /* Wait for the clocks to turn off. */
5eddb70b 2887 POSTING_READ(reg);
6be4a607 2888 udelay(100);
6b383a7f 2889
f7abfe8b 2890 intel_crtc->active = false;
6b383a7f 2891 intel_update_watermarks(dev);
d1ebd816
BW		 2892
2893 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2894 intel_update_fbc(dev);
2895 intel_clear_scanline_wait(dev);
d1ebd816 2896 mutex_unlock(&dev->struct_mutex);
6be4a607 2897}
1b3c7a47 2898
6be4a607
JB		 2899static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2900{
2901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2902 int pipe = intel_crtc->pipe;
2903 int plane = intel_crtc->plane;
8db9d77b 2904
6be4a607
JB		 2905 /* XXX: When our outputs are all unaware of DPMS modes other than off
2906 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2907 */
2908 switch (mode) {
2909 case DRM_MODE_DPMS_ON:
2910 case DRM_MODE_DPMS_STANDBY:
2911 case DRM_MODE_DPMS_SUSPEND:
2912 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2913 ironlake_crtc_enable(crtc);
2914 break;
1b3c7a47 2915
6be4a607
JB		 2916 case DRM_MODE_DPMS_OFF:
2917 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2918 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2919 break;
2920 }
2921}
2922
02e792fb
DV		 2923static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2924{
02e792fb 2925 if (!enable && intel_crtc->overlay) {
23f09ce3 2926 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2927 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2928
23f09ce3 2929 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2930 dev_priv->mm.interruptible = false;
2931 (void) intel_overlay_switch_off(intel_crtc->overlay);
2932 dev_priv->mm.interruptible = true;
23f09ce3 2933 mutex_unlock(&dev->struct_mutex);
02e792fb 2934 }
02e792fb 2935
5dcdbcb0
CW		 2936 /* Let userspace switch the overlay on again. In most cases userspace
2937 * has to recompute where to put it anyway.
2938 */
02e792fb
DV		 2939}
2940
0b8765c6 2941static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2942{
2943 struct drm_device *dev = crtc->dev;
79e53945
JB		 2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946 int pipe = intel_crtc->pipe;
80824003 2947 int plane = intel_crtc->plane;
79e53945 2948
f7abfe8b
CW		 2949 if (intel_crtc->active)
2950 return;
2951
2952 intel_crtc->active = true;
6b383a7f
CW		 2953 intel_update_watermarks(dev);
2954
63d7bbe9 2955 intel_enable_pll(dev_priv, pipe);
040484af 2956 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2957 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2958
0b8765c6 2959 intel_crtc_load_lut(crtc);
bed4a673 2960 intel_update_fbc(dev);
79e53945 2961
0b8765c6
JB		 2962 /* Give the overlay scaler a chance to enable if it's on this pipe */
2963 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2964 intel_crtc_update_cursor(crtc, true);
0b8765c6 2965}
79e53945 2966
0b8765c6
JB		 2967static void i9xx_crtc_disable(struct drm_crtc *crtc)
2968{
2969 struct drm_device *dev = crtc->dev;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972 int pipe = intel_crtc->pipe;
2973 int plane = intel_crtc->plane;
b690e96c 2974
f7abfe8b
CW		 2975 if (!intel_crtc->active)
2976 return;
2977
0b8765c6 2978 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2979 intel_crtc_wait_for_pending_flips(crtc);
2980 drm_vblank_off(dev, pipe);
0b8765c6 2981 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2982 intel_crtc_update_cursor(crtc, false);
0b8765c6 2983
973d04f9
CW		 2984 if (dev_priv->cfb_plane == plane)
2985 intel_disable_fbc(dev);
79e53945 2986
b24e7179 2987 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2988 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2989 intel_disable_pll(dev_priv, pipe);
0b8765c6 2990
f7abfe8b 2991 intel_crtc->active = false;
6b383a7f
CW		 2992 intel_update_fbc(dev);
2993 intel_update_watermarks(dev);
2994 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2995}
2996
2997static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2998{
2999 /* XXX: When our outputs are all unaware of DPMS modes other than off
3000 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3001 */
3002 switch (mode) {
3003 case DRM_MODE_DPMS_ON:
3004 case DRM_MODE_DPMS_STANDBY:
3005 case DRM_MODE_DPMS_SUSPEND:
3006 i9xx_crtc_enable(crtc);
3007 break;
3008 case DRM_MODE_DPMS_OFF:
3009 i9xx_crtc_disable(crtc);
79e53945
JB		 3010 break;
3011 }
2c07245f
ZW		 3012}
3013
3014/**
3015 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3016 */
3017static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3018{
3019 struct drm_device *dev = crtc->dev;
e70236a8 3020 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3021 struct drm_i915_master_private *master_priv;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3023 int pipe = intel_crtc->pipe;
3024 bool enabled;
3025
032d2a0d
CW		 3026 if (intel_crtc->dpms_mode == mode)
3027 return;
3028
65655d4a 3029 intel_crtc->dpms_mode = mode;
debcaddc 3030
e70236a8 3031 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3032
3033 if (!dev->primary->master)
3034 return;
3035
3036 master_priv = dev->primary->master->driver_priv;
3037 if (!master_priv->sarea_priv)
3038 return;
3039
3040 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3041
3042 switch (pipe) {
3043 case 0:
3044 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3045 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3046 break;
3047 case 1:
3048 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3049 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3050 break;
3051 default:
9db4a9c7 3052 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3053 break;
3054 }
79e53945
JB		 3055}
3056
cdd59983
CW		 3057static void intel_crtc_disable(struct drm_crtc *crtc)
3058{
3059 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3060 struct drm_device *dev = crtc->dev;
3061
3062 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3063
3064 if (crtc->fb) {
3065 mutex_lock(&dev->struct_mutex);
3066 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3067 mutex_unlock(&dev->struct_mutex);
3068 }
3069}
3070
7e7d76c3
JB		 3071/* Prepare for a mode set.
3072 *
3073 * Note we could be a lot smarter here. We need to figure out which outputs
3074 * will be enabled, which disabled (in short, how the config will changes)
3075 * and perform the minimum necessary steps to accomplish that, e.g. updating
3076 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3077 * panel fitting is in the proper state, etc.
3078 */
3079static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3080{
7e7d76c3 3081 i9xx_crtc_disable(crtc);
79e53945
JB		 3082}
3083
7e7d76c3 3084static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3085{
7e7d76c3 3086 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3087}
3088
3089static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3090{
7e7d76c3 3091 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3092}
3093
3094static void ironlake_crtc_commit(struct drm_crtc *crtc)
3095{
7e7d76c3 3096 ironlake_crtc_enable(crtc);
79e53945
JB		 3097}
3098
3099void intel_encoder_prepare (struct drm_encoder *encoder)
3100{
3101 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3102 /* lvds has its own version of prepare see intel_lvds_prepare */
3103 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3104}
3105
3106void intel_encoder_commit (struct drm_encoder *encoder)
3107{
3108 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3109 /* lvds has its own version of commit see intel_lvds_commit */
3110 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3111}
3112
ea5b213a
CW		 3113void intel_encoder_destroy(struct drm_encoder *encoder)
3114{
4ef69c7a 3115 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3116
ea5b213a
CW		 3117 drm_encoder_cleanup(encoder);
3118 kfree(intel_encoder);
3119}
3120
79e53945
JB		 3121static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3122 struct drm_display_mode *mode,
3123 struct drm_display_mode *adjusted_mode)
3124{
2c07245f 3125 struct drm_device *dev = crtc->dev;
89749350 3126
bad720ff 3127 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3128 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3129 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3130 return false;
2c07245f 3131 }
89749350
CW		 3132
3133 /* XXX some encoders set the crtcinfo, others don't.
3134 * Obviously we need some form of conflict resolution here...
3135 */
3136 if (adjusted_mode->crtc_htotal == 0)
3137 drm_mode_set_crtcinfo(adjusted_mode, 0);
3138
79e53945
JB		 3139 return true;
3140}
3141
e70236a8
JB		 3142static int i945_get_display_clock_speed(struct drm_device *dev)
3143{
3144 return 400000;
3145}
79e53945 3146
e70236a8 3147static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3148{
e70236a8
JB		 3149 return 333000;
3150}
79e53945 3151
e70236a8
JB		 3152static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3153{
3154 return 200000;
3155}
79e53945 3156
e70236a8
JB		 3157static int i915gm_get_display_clock_speed(struct drm_device *dev)
3158{
3159 u16 gcfgc = 0;
79e53945 3160
e70236a8
JB		 3161 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3162
3163 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3164 return 133000;
3165 else {
3166 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3167 case GC_DISPLAY_CLOCK_333_MHZ:
3168 return 333000;
3169 default:
3170 case GC_DISPLAY_CLOCK_190_200_MHZ:
3171 return 190000;
79e53945 3172 }
e70236a8
JB		 3173 }
3174}
3175
3176static int i865_get_display_clock_speed(struct drm_device *dev)
3177{
3178 return 266000;
3179}
3180
3181static int i855_get_display_clock_speed(struct drm_device *dev)
3182{
3183 u16 hpllcc = 0;
3184 /* Assume that the hardware is in the high speed state. This
3185 * should be the default.
3186 */
3187 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3188 case GC_CLOCK_133_200:
3189 case GC_CLOCK_100_200:
3190 return 200000;
3191 case GC_CLOCK_166_250:
3192 return 250000;
3193 case GC_CLOCK_100_133:
79e53945 3194 return 133000;
e70236a8 3195 }
79e53945 3196
e70236a8
JB		 3197 /* Shouldn't happen */
3198 return 0;
3199}
79e53945 3200
e70236a8
JB		 3201static int i830_get_display_clock_speed(struct drm_device *dev)
3202{
3203 return 133000;
79e53945
JB		 3204}
3205
2c07245f
ZW		 3206struct fdi_m_n {
3207 u32 tu;
3208 u32 gmch_m;
3209 u32 gmch_n;
3210 u32 link_m;
3211 u32 link_n;
3212};
3213
3214static void
3215fdi_reduce_ratio(u32 *num, u32 *den)
3216{
3217 while (*num > 0xffffff || *den > 0xffffff) {
3218 *num >>= 1;
3219 *den >>= 1;
3220 }
3221}
3222
2c07245f 3223static void
f2b115e6
AJ		 3224ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3225 int link_clock, struct fdi_m_n *m_n)
2c07245f 3226{
2c07245f
ZW		 3227 m_n->tu = 64; /* default size */
3228
22ed1113
CW		 3229 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3230 m_n->gmch_m = bits_per_pixel * pixel_clock;
3231 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3232 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3233
22ed1113
CW		 3234 m_n->link_m = pixel_clock;
3235 m_n->link_n = link_clock;
2c07245f
ZW		 3236 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3237}
3238
3239
7662c8bd
SL		 3240struct intel_watermark_params {
3241 unsigned long fifo_size;
3242 unsigned long max_wm;
3243 unsigned long default_wm;
3244 unsigned long guard_size;
3245 unsigned long cacheline_size;
3246};
3247
f2b115e6 3248/* Pineview has different values for various configs */
d210246a 3249static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3250 PINEVIEW_DISPLAY_FIFO,
3251 PINEVIEW_MAX_WM,
3252 PINEVIEW_DFT_WM,
3253 PINEVIEW_GUARD_WM,
3254 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3255};
d210246a 3256static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3257 PINEVIEW_DISPLAY_FIFO,
3258 PINEVIEW_MAX_WM,
3259 PINEVIEW_DFT_HPLLOFF_WM,
3260 PINEVIEW_GUARD_WM,
3261 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3262};
d210246a 3263static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3264 PINEVIEW_CURSOR_FIFO,
3265 PINEVIEW_CURSOR_MAX_WM,
3266 PINEVIEW_CURSOR_DFT_WM,
3267 PINEVIEW_CURSOR_GUARD_WM,
3268 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3269};
d210246a 3270static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3271 PINEVIEW_CURSOR_FIFO,
3272 PINEVIEW_CURSOR_MAX_WM,
3273 PINEVIEW_CURSOR_DFT_WM,
3274 PINEVIEW_CURSOR_GUARD_WM,
3275 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3276};
d210246a 3277static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3278 G4X_FIFO_SIZE,
3279 G4X_MAX_WM,
3280 G4X_MAX_WM,
3281 2,
3282 G4X_FIFO_LINE_SIZE,
3283};
d210246a 3284static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3285 I965_CURSOR_FIFO,
3286 I965_CURSOR_MAX_WM,
3287 I965_CURSOR_DFT_WM,
3288 2,
3289 G4X_FIFO_LINE_SIZE,
3290};
d210246a 3291static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3292 I965_CURSOR_FIFO,
3293 I965_CURSOR_MAX_WM,
3294 I965_CURSOR_DFT_WM,
3295 2,
3296 I915_FIFO_LINE_SIZE,
3297};
d210246a 3298static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3299 I945_FIFO_SIZE,
7662c8bd
SL		 3300 I915_MAX_WM,
3301 1,
dff33cfc
JB		 3302 2,
3303 I915_FIFO_LINE_SIZE
7662c8bd 3304};
d210246a 3305static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3306 I915_FIFO_SIZE,
7662c8bd
SL		 3307 I915_MAX_WM,
3308 1,
dff33cfc 3309 2,
7662c8bd
SL		 3310 I915_FIFO_LINE_SIZE
3311};
d210246a 3312static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3313 I855GM_FIFO_SIZE,
3314 I915_MAX_WM,
3315 1,
dff33cfc 3316 2,
7662c8bd
SL		 3317 I830_FIFO_LINE_SIZE
3318};
d210246a 3319static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3320 I830_FIFO_SIZE,
3321 I915_MAX_WM,
3322 1,
dff33cfc 3323 2,
7662c8bd
SL		 3324 I830_FIFO_LINE_SIZE
3325};
3326
d210246a 3327static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3328 ILK_DISPLAY_FIFO,
3329 ILK_DISPLAY_MAXWM,
3330 ILK_DISPLAY_DFTWM,
3331 2,
3332 ILK_FIFO_LINE_SIZE
3333};
d210246a 3334static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3335 ILK_CURSOR_FIFO,
3336 ILK_CURSOR_MAXWM,
3337 ILK_CURSOR_DFTWM,
3338 2,
3339 ILK_FIFO_LINE_SIZE
3340};
d210246a 3341static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3342 ILK_DISPLAY_SR_FIFO,
3343 ILK_DISPLAY_MAX_SRWM,
3344 ILK_DISPLAY_DFT_SRWM,
3345 2,
3346 ILK_FIFO_LINE_SIZE
3347};
d210246a 3348static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3349 ILK_CURSOR_SR_FIFO,
3350 ILK_CURSOR_MAX_SRWM,
3351 ILK_CURSOR_DFT_SRWM,
3352 2,
3353 ILK_FIFO_LINE_SIZE
3354};
3355
d210246a 3356static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3357 SNB_DISPLAY_FIFO,
3358 SNB_DISPLAY_MAXWM,
3359 SNB_DISPLAY_DFTWM,
3360 2,
3361 SNB_FIFO_LINE_SIZE
3362};
d210246a 3363static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3364 SNB_CURSOR_FIFO,
3365 SNB_CURSOR_MAXWM,
3366 SNB_CURSOR_DFTWM,
3367 2,
3368 SNB_FIFO_LINE_SIZE
3369};
d210246a 3370static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3371 SNB_DISPLAY_SR_FIFO,
3372 SNB_DISPLAY_MAX_SRWM,
3373 SNB_DISPLAY_DFT_SRWM,
3374 2,
3375 SNB_FIFO_LINE_SIZE
3376};
d210246a 3377static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3378 SNB_CURSOR_SR_FIFO,
3379 SNB_CURSOR_MAX_SRWM,
3380 SNB_CURSOR_DFT_SRWM,
3381 2,
3382 SNB_FIFO_LINE_SIZE
3383};
3384
3385
dff33cfc
JB		 3386/**
3387 * intel_calculate_wm - calculate watermark level
3388 * @clock_in_khz: pixel clock
3389 * @wm: chip FIFO params
3390 * @pixel_size: display pixel size
3391 * @latency_ns: memory latency for the platform
3392 *
3393 * Calculate the watermark level (the level at which the display plane will
3394 * start fetching from memory again). Each chip has a different display
3395 * FIFO size and allocation, so the caller needs to figure that out and pass
3396 * in the correct intel_watermark_params structure.
3397 *
3398 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3399 * on the pixel size. When it reaches the watermark level, it'll start
3400 * fetching FIFO line sized based chunks from memory until the FIFO fills
3401 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3402 * will occur, and a display engine hang could result.
3403 */
7662c8bd 3404static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3405 const struct intel_watermark_params *wm,
3406 int fifo_size,
7662c8bd
SL		 3407 int pixel_size,
3408 unsigned long latency_ns)
3409{
390c4dd4 3410 long entries_required, wm_size;
dff33cfc 3411
d660467c
JB		 3412 /*
3413 * Note: we need to make sure we don't overflow for various clock &
3414 * latency values.
3415 * clocks go from a few thousand to several hundred thousand.
3416 * latency is usually a few thousand
3417 */
3418 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3419 1000;
8de9b311 3420 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3421
bbb0aef5 3422 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3423
d210246a 3424 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3425
bbb0aef5 3426 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3427
390c4dd4
JB		 3428 /* Don't promote wm_size to unsigned... */
3429 if (wm_size > (long)wm->max_wm)
7662c8bd 3430 wm_size = wm->max_wm;
c3add4b6 3431 if (wm_size <= 0)
7662c8bd
SL		 3432 wm_size = wm->default_wm;
3433 return wm_size;
3434}
3435
3436struct cxsr_latency {
3437 int is_desktop;
95534263 3438 int is_ddr3;
7662c8bd
SL		 3439 unsigned long fsb_freq;
3440 unsigned long mem_freq;
3441 unsigned long display_sr;
3442 unsigned long display_hpll_disable;
3443 unsigned long cursor_sr;
3444 unsigned long cursor_hpll_disable;
3445};
3446
403c89ff 3447static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3448 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3449 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3450 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3451 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3452 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3453
3454 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3455 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3456 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3457 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3458 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3459
3460 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3461 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3462 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3463 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3464 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3465
3466 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3467 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3468 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3469 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3470 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3471
3472 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3473 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3474 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3475 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3476 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3477
3478 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3479 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3480 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3481 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3482 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3483};
3484
403c89ff
CW		 3485static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3486 int is_ddr3,
3487 int fsb,
3488 int mem)
7662c8bd 3489{
403c89ff 3490 const struct cxsr_latency *latency;
7662c8bd 3491 int i;
7662c8bd
SL		 3492
3493 if (fsb == 0 || mem == 0)
3494 return NULL;
3495
3496 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3497 latency = &cxsr_latency_table[i];
3498 if (is_desktop == latency->is_desktop &&
95534263 3499 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3500 fsb == latency->fsb_freq && mem == latency->mem_freq)
3501 return latency;
7662c8bd 3502 }
decbbcda 3503
28c97730 3504 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3505
3506 return NULL;
7662c8bd
SL		 3507}
3508
f2b115e6 3509static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3510{
3511 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3512
3513 /* deactivate cxsr */
3e33d94d 3514 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3515}
3516
bcc24fb4
JB		 3517/*
3518 * Latency for FIFO fetches is dependent on several factors:
3519 * - memory configuration (speed, channels)
3520 * - chipset
3521 * - current MCH state
3522 * It can be fairly high in some situations, so here we assume a fairly
3523 * pessimal value. It's a tradeoff between extra memory fetches (if we
3524 * set this value too high, the FIFO will fetch frequently to stay full)
3525 * and power consumption (set it too low to save power and we might see
3526 * FIFO underruns and display "flicker").
3527 *
3528 * A value of 5us seems to be a good balance; safe for very low end
3529 * platforms but not overly aggressive on lower latency configs.
3530 */
69e302a9 3531static const int latency_ns = 5000;
7662c8bd 3532
e70236a8 3533static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3534{
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 uint32_t dsparb = I915_READ(DSPARB);
3537 int size;
3538
8de9b311
CW		 3539 size = dsparb & 0x7f;
3540 if (plane)
3541 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3542
28c97730 3543 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3544 plane ? "B" : "A", size);
dff33cfc
JB		 3545
3546 return size;
3547}
7662c8bd 3548
e70236a8
JB		 3549static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3550{
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 uint32_t dsparb = I915_READ(DSPARB);
3553 int size;
3554
8de9b311
CW		 3555 size = dsparb & 0x1ff;
3556 if (plane)
3557 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3558 size >>= 1; /* Convert to cachelines */
dff33cfc 3559
28c97730 3560 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3561 plane ? "B" : "A", size);
dff33cfc
JB		 3562
3563 return size;
3564}
7662c8bd 3565
e70236a8
JB		 3566static int i845_get_fifo_size(struct drm_device *dev, int plane)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 uint32_t dsparb = I915_READ(DSPARB);
3570 int size;
3571
3572 size = dsparb & 0x7f;
3573 size >>= 2; /* Convert to cachelines */
3574
28c97730 3575 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3576 plane ? "B" : "A",
3577 size);
e70236a8
JB		 3578
3579 return size;
3580}
3581
3582static int i830_get_fifo_size(struct drm_device *dev, int plane)
3583{
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 uint32_t dsparb = I915_READ(DSPARB);
3586 int size;
3587
3588 size = dsparb & 0x7f;
3589 size >>= 1; /* Convert to cachelines */
3590
28c97730 3591 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3592 plane ? "B" : "A", size);
e70236a8
JB		 3593
3594 return size;
3595}
3596
d210246a
CW		 3597static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3598{
3599 struct drm_crtc *crtc, *enabled = NULL;
3600
3601 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3602 if (crtc->enabled && crtc->fb) {
3603 if (enabled)
3604 return NULL;
3605 enabled = crtc;
3606 }
3607 }
3608
3609 return enabled;
3610}
3611
3612static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3613{
3614 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3615 struct drm_crtc *crtc;
403c89ff 3616 const struct cxsr_latency *latency;
d4294342
ZY		 3617 u32 reg;
3618 unsigned long wm;
d4294342 3619
403c89ff 3620 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3621 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3622 if (!latency) {
3623 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3624 pineview_disable_cxsr(dev);
3625 return;
3626 }
3627
d210246a
CW		 3628 crtc = single_enabled_crtc(dev);
3629 if (crtc) {
3630 int clock = crtc->mode.clock;
3631 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3632
3633 /* Display SR */
d210246a
CW		 3634 wm = intel_calculate_wm(clock, &pineview_display_wm,
3635 pineview_display_wm.fifo_size,
d4294342
ZY		 3636 pixel_size, latency->display_sr);
3637 reg = I915_READ(DSPFW1);
3638 reg &= ~DSPFW_SR_MASK;
3639 reg |= wm << DSPFW_SR_SHIFT;
3640 I915_WRITE(DSPFW1, reg);
3641 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3642
3643 /* cursor SR */
d210246a
CW		 3644 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3645 pineview_display_wm.fifo_size,
d4294342
ZY		 3646 pixel_size, latency->cursor_sr);
3647 reg = I915_READ(DSPFW3);
3648 reg &= ~DSPFW_CURSOR_SR_MASK;
3649 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3650 I915_WRITE(DSPFW3, reg);
3651
3652 /* Display HPLL off SR */
d210246a
CW		 3653 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3654 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3655 pixel_size, latency->display_hpll_disable);
3656 reg = I915_READ(DSPFW3);
3657 reg &= ~DSPFW_HPLL_SR_MASK;
3658 reg |= wm & DSPFW_HPLL_SR_MASK;
3659 I915_WRITE(DSPFW3, reg);
3660
3661 /* cursor HPLL off SR */
d210246a
CW		 3662 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3663 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3664 pixel_size, latency->cursor_hpll_disable);
3665 reg = I915_READ(DSPFW3);
3666 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3667 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3668 I915_WRITE(DSPFW3, reg);
3669 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3670
3671 /* activate cxsr */
3e33d94d
CW		 3672 I915_WRITE(DSPFW3,
3673 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3674 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3675 } else {
3676 pineview_disable_cxsr(dev);
3677 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3678 }
3679}
3680
417ae147
CW		 3681static bool g4x_compute_wm0(struct drm_device *dev,
3682 int plane,
3683 const struct intel_watermark_params *display,
3684 int display_latency_ns,
3685 const struct intel_watermark_params *cursor,
3686 int cursor_latency_ns,
3687 int *plane_wm,
3688 int *cursor_wm)
3689{
3690 struct drm_crtc *crtc;
3691 int htotal, hdisplay, clock, pixel_size;
3692 int line_time_us, line_count;
3693 int entries, tlb_miss;
3694
3695 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3696 if (crtc->fb == NULL || !crtc->enabled) {
3697 *cursor_wm = cursor->guard_size;
3698 *plane_wm = display->guard_size;
417ae147 3699 return false;
5c72d064 3700 }
417ae147
CW		 3701
3702 htotal = crtc->mode.htotal;
3703 hdisplay = crtc->mode.hdisplay;
3704 clock = crtc->mode.clock;
3705 pixel_size = crtc->fb->bits_per_pixel / 8;
3706
3707 /* Use the small buffer method to calculate plane watermark */
3708 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3709 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3710 if (tlb_miss > 0)
3711 entries += tlb_miss;
3712 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3713 *plane_wm = entries + display->guard_size;
3714 if (*plane_wm > (int)display->max_wm)
3715 *plane_wm = display->max_wm;
3716
3717 /* Use the large buffer method to calculate cursor watermark */
3718 line_time_us = ((htotal * 1000) / clock);
3719 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3720 entries = line_count * 64 * pixel_size;
3721 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3722 if (tlb_miss > 0)
3723 entries += tlb_miss;
3724 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3725 *cursor_wm = entries + cursor->guard_size;
3726 if (*cursor_wm > (int)cursor->max_wm)
3727 *cursor_wm = (int)cursor->max_wm;
3728
3729 return true;
3730}
3731
3732/*
3733 * Check the wm result.
3734 *
3735 * If any calculated watermark values is larger than the maximum value that
3736 * can be programmed into the associated watermark register, that watermark
3737 * must be disabled.
3738 */
3739static bool g4x_check_srwm(struct drm_device *dev,
3740 int display_wm, int cursor_wm,
3741 const struct intel_watermark_params *display,
3742 const struct intel_watermark_params *cursor)
652c393a 3743{
417ae147
CW		 3744 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3745 display_wm, cursor_wm);
652c393a 3746
417ae147 3747 if (display_wm > display->max_wm) {
bbb0aef5 3748 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3749 display_wm, display->max_wm);
3750 return false;
3751 }
0e442c60 3752
417ae147 3753 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3754 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3755 cursor_wm, cursor->max_wm);
3756 return false;
3757 }
0e442c60 3758
417ae147
CW		 3759 if (!(display_wm || cursor_wm)) {
3760 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3761 return false;
3762 }
0e442c60 3763
417ae147
CW		 3764 return true;
3765}
0e442c60 3766
417ae147 3767static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3768 int plane,
3769 int latency_ns,
417ae147
CW		 3770 const struct intel_watermark_params *display,
3771 const struct intel_watermark_params *cursor,
3772 int *display_wm, int *cursor_wm)
3773{
d210246a
CW		 3774 struct drm_crtc *crtc;
3775 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3776 unsigned long line_time_us;
3777 int line_count, line_size;
3778 int small, large;
3779 int entries;
0e442c60 3780
417ae147
CW		 3781 if (!latency_ns) {
3782 *display_wm = *cursor_wm = 0;
3783 return false;
3784 }
0e442c60 3785
d210246a
CW		 3786 crtc = intel_get_crtc_for_plane(dev, plane);
3787 hdisplay = crtc->mode.hdisplay;
3788 htotal = crtc->mode.htotal;
3789 clock = crtc->mode.clock;
3790 pixel_size = crtc->fb->bits_per_pixel / 8;
3791
417ae147
CW		 3792 line_time_us = (htotal * 1000) / clock;
3793 line_count = (latency_ns / line_time_us + 1000) / 1000;
3794 line_size = hdisplay * pixel_size;
0e442c60 3795
417ae147
CW		 3796 /* Use the minimum of the small and large buffer method for primary */
3797 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3798 large = line_count * line_size;
0e442c60 3799
417ae147
CW		 3800 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3801 *display_wm = entries + display->guard_size;
4fe5e611 3802
417ae147
CW		 3803 /* calculate the self-refresh watermark for display cursor */
3804 entries = line_count * pixel_size * 64;
3805 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3806 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3807
417ae147
CW		 3808 return g4x_check_srwm(dev,
3809 *display_wm, *cursor_wm,
3810 display, cursor);
3811}
4fe5e611 3812
7ccb4a53 3813#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3814
3815static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3816{
3817 static const int sr_latency_ns = 12000;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3820 int plane_sr, cursor_sr;
3821 unsigned int enabled = 0;
417ae147
CW		 3822
3823 if (g4x_compute_wm0(dev, 0,
3824 &g4x_wm_info, latency_ns,
3825 &g4x_cursor_wm_info, latency_ns,
3826 &planea_wm, &cursora_wm))
d210246a 3827 enabled |= 1;
417ae147
CW		 3828
3829 if (g4x_compute_wm0(dev, 1,
3830 &g4x_wm_info, latency_ns,
3831 &g4x_cursor_wm_info, latency_ns,
3832 &planeb_wm, &cursorb_wm))
d210246a 3833 enabled |= 2;
417ae147
CW		 3834
3835 plane_sr = cursor_sr = 0;
d210246a
CW		 3836 if (single_plane_enabled(enabled) &&
3837 g4x_compute_srwm(dev, ffs(enabled) - 1,
3838 sr_latency_ns,
417ae147
CW		 3839 &g4x_wm_info,
3840 &g4x_cursor_wm_info,
3841 &plane_sr, &cursor_sr))
0e442c60 3842 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3843 else
3844 I915_WRITE(FW_BLC_SELF,
3845 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3846
308977ac
CW		 3847 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3848 planea_wm, cursora_wm,
3849 planeb_wm, cursorb_wm,
3850 plane_sr, cursor_sr);
0e442c60 3851
417ae147
CW		 3852 I915_WRITE(DSPFW1,
3853 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3854 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3855 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3856 planea_wm);
3857 I915_WRITE(DSPFW2,
3858 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3859 (cursora_wm << DSPFW_CURSORA_SHIFT));
3860 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3861 I915_WRITE(DSPFW3,
3862 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3863 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3864}
3865
d210246a 3866static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3867{
3868 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3869 struct drm_crtc *crtc;
3870 int srwm = 1;
4fe5e611 3871 int cursor_sr = 16;
1dc7546d
JB		 3872
3873 /* Calc sr entries for one plane configs */
d210246a
CW		 3874 crtc = single_enabled_crtc(dev);
3875 if (crtc) {
1dc7546d 3876 /* self-refresh has much higher latency */
69e302a9 3877 static const int sr_latency_ns = 12000;
d210246a
CW		 3878 int clock = crtc->mode.clock;
3879 int htotal = crtc->mode.htotal;
3880 int hdisplay = crtc->mode.hdisplay;
3881 int pixel_size = crtc->fb->bits_per_pixel / 8;
3882 unsigned long line_time_us;
3883 int entries;
1dc7546d 3884
d210246a 3885 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3886
3887 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3888 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3889 pixel_size * hdisplay;
3890 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3891 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3892 if (srwm < 0)
3893 srwm = 1;
1b07e04e 3894 srwm &= 0x1ff;
308977ac
CW		 3895 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3896 entries, srwm);
4fe5e611 3897
d210246a 3898 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3899 pixel_size * 64;
d210246a 3900 entries = DIV_ROUND_UP(entries,
8de9b311 3901 i965_cursor_wm_info.cacheline_size);
4fe5e611 3902 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3903 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3904
3905 if (cursor_sr > i965_cursor_wm_info.max_wm)
3906 cursor_sr = i965_cursor_wm_info.max_wm;
3907
3908 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3909 "cursor %d\n", srwm, cursor_sr);
3910
a6c45cf0 3911 if (IS_CRESTLINE(dev))
adcdbc66 3912 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3913 } else {
3914 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3915 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3916 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3917 & ~FW_BLC_SELF_EN);
1dc7546d 3918 }
7662c8bd 3919
1dc7546d
JB		 3920 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3921 srwm);
7662c8bd
SL		 3922
3923 /* 965 has limitations... */
417ae147
CW		 3924 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3925 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3926 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3927 /* update cursor SR watermark */
3928 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3929}
3930
d210246a 3931static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3932{
3933 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3934 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3935 uint32_t fwater_lo;
3936 uint32_t fwater_hi;
d210246a
CW		 3937 int cwm, srwm = 1;
3938 int fifo_size;
dff33cfc 3939 int planea_wm, planeb_wm;
d210246a 3940 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3941
72557b4f 3942 if (IS_I945GM(dev))
d210246a 3943 wm_info = &i945_wm_info;
a6c45cf0 3944 else if (!IS_GEN2(dev))
d210246a 3945 wm_info = &i915_wm_info;
7662c8bd 3946 else
d210246a
CW		 3947 wm_info = &i855_wm_info;
3948
3949 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3950 crtc = intel_get_crtc_for_plane(dev, 0);
3951 if (crtc->enabled && crtc->fb) {
3952 planea_wm = intel_calculate_wm(crtc->mode.clock,
3953 wm_info, fifo_size,
3954 crtc->fb->bits_per_pixel / 8,
3955 latency_ns);
3956 enabled = crtc;
3957 } else
3958 planea_wm = fifo_size - wm_info->guard_size;
3959
3960 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3961 crtc = intel_get_crtc_for_plane(dev, 1);
3962 if (crtc->enabled && crtc->fb) {
3963 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3964 wm_info, fifo_size,
3965 crtc->fb->bits_per_pixel / 8,
3966 latency_ns);
3967 if (enabled == NULL)
3968 enabled = crtc;
3969 else
3970 enabled = NULL;
3971 } else
3972 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3973
28c97730 3974 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3975
3976 /*
3977 * Overlay gets an aggressive default since video jitter is bad.
3978 */
3979 cwm = 2;
3980
18b2190c
AL		 3981 /* Play safe and disable self-refresh before adjusting watermarks. */
3982 if (IS_I945G(dev) || IS_I945GM(dev))
3983 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3984 else if (IS_I915GM(dev))
3985 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3986
dff33cfc 3987 /* Calc sr entries for one plane configs */
d210246a 3988 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3989 /* self-refresh has much higher latency */
69e302a9 3990 static const int sr_latency_ns = 6000;
d210246a
CW		 3991 int clock = enabled->mode.clock;
3992 int htotal = enabled->mode.htotal;
3993 int hdisplay = enabled->mode.hdisplay;
3994 int pixel_size = enabled->fb->bits_per_pixel / 8;
3995 unsigned long line_time_us;
3996 int entries;
dff33cfc 3997
d210246a 3998 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3999
4000 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4001 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4002 pixel_size * hdisplay;
4003 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4004 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4005 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4006 if (srwm < 0)
4007 srwm = 1;
ee980b80
LP		 4008
4009 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4010 I915_WRITE(FW_BLC_SELF,
4011 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4012 else if (IS_I915GM(dev))
ee980b80 4013 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4014 }
4015
28c97730 4016 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4017 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4018
dff33cfc
JB		 4019 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4020 fwater_hi = (cwm & 0x1f);
4021
4022 /* Set request length to 8 cachelines per fetch */
4023 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4024 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4025
4026 I915_WRITE(FW_BLC, fwater_lo);
4027 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4028
d210246a
CW		 4029 if (HAS_FW_BLC(dev)) {
4030 if (enabled) {
4031 if (IS_I945G(dev) || IS_I945GM(dev))
4032 I915_WRITE(FW_BLC_SELF,
4033 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4034 else if (IS_I915GM(dev))
4035 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4036 DRM_DEBUG_KMS("memory self refresh enabled\n");
4037 } else
4038 DRM_DEBUG_KMS("memory self refresh disabled\n");
4039 }
7662c8bd
SL		 4040}
4041
d210246a 4042static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4043{
4044 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4045 struct drm_crtc *crtc;
4046 uint32_t fwater_lo;
dff33cfc 4047 int planea_wm;
7662c8bd 4048
d210246a
CW		 4049 crtc = single_enabled_crtc(dev);
4050 if (crtc == NULL)
4051 return;
7662c8bd 4052
d210246a
CW		 4053 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4054 dev_priv->display.get_fifo_size(dev, 0),
4055 crtc->fb->bits_per_pixel / 8,
4056 latency_ns);
4057 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4058 fwater_lo |= (3<<8) | planea_wm;
4059
28c97730 4060 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4061
4062 I915_WRITE(FW_BLC, fwater_lo);
4063}
4064
7f8a8569 4065#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4066#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4067
1398261a
YL		 4068/*
4069 * Check the wm result.
4070 *
4071 * If any calculated watermark values is larger than the maximum value that
4072 * can be programmed into the associated watermark register, that watermark
4073 * must be disabled.
1398261a 4074 */
b79d4990
JB		 4075static bool ironlake_check_srwm(struct drm_device *dev, int level,
4076 int fbc_wm, int display_wm, int cursor_wm,
4077 const struct intel_watermark_params *display,
4078 const struct intel_watermark_params *cursor)
1398261a
YL		 4079{
4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081
4082 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4083 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4084
4085 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4086 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4087 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4088
4089 /* fbc has it's own way to disable FBC WM */
4090 I915_WRITE(DISP_ARB_CTL,
4091 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4092 return false;
4093 }
4094
b79d4990 4095 if (display_wm > display->max_wm) {
1398261a 4096 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4097 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4098 return false;
4099 }
4100
b79d4990 4101 if (cursor_wm > cursor->max_wm) {
1398261a 4102 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4103 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4104 return false;
4105 }
4106
4107 if (!(fbc_wm || display_wm || cursor_wm)) {
4108 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4109 return false;
4110 }
4111
4112 return true;
4113}
4114
4115/*
4116 * Compute watermark values of WM[1-3],
4117 */
d210246a
CW		 4118static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4119 int latency_ns,
b79d4990
JB		 4120 const struct intel_watermark_params *display,
4121 const struct intel_watermark_params *cursor,
4122 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4123{
d210246a 4124 struct drm_crtc *crtc;
1398261a 4125 unsigned long line_time_us;
d210246a 4126 int hdisplay, htotal, pixel_size, clock;
b79d4990 4127 int line_count, line_size;
1398261a
YL		 4128 int small, large;
4129 int entries;
1398261a
YL		 4130
4131 if (!latency_ns) {
4132 *fbc_wm = *display_wm = *cursor_wm = 0;
4133 return false;
4134 }
4135
d210246a
CW		 4136 crtc = intel_get_crtc_for_plane(dev, plane);
4137 hdisplay = crtc->mode.hdisplay;
4138 htotal = crtc->mode.htotal;
4139 clock = crtc->mode.clock;
4140 pixel_size = crtc->fb->bits_per_pixel / 8;
4141
1398261a
YL		 4142 line_time_us = (htotal * 1000) / clock;
4143 line_count = (latency_ns / line_time_us + 1000) / 1000;
4144 line_size = hdisplay * pixel_size;
4145
4146 /* Use the minimum of the small and large buffer method for primary */
4147 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4148 large = line_count * line_size;
4149
b79d4990
JB		 4150 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4151 *display_wm = entries + display->guard_size;
1398261a
YL		 4152
4153 /*
b79d4990 4154 * Spec says:
1398261a
YL		 4155 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4156 */
4157 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4158
4159 /* calculate the self-refresh watermark for display cursor */
4160 entries = line_count * pixel_size * 64;
b79d4990
JB		 4161 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4162 *cursor_wm = entries + cursor->guard_size;
1398261a 4163
b79d4990
JB		 4164 return ironlake_check_srwm(dev, level,
4165 *fbc_wm, *display_wm, *cursor_wm,
4166 display, cursor);
4167}
4168
d210246a 4169static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4170{
4171 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4172 int fbc_wm, plane_wm, cursor_wm;
4173 unsigned int enabled;
b79d4990
JB		 4174
4175 enabled = 0;
9f405100
CW		 4176 if (g4x_compute_wm0(dev, 0,
4177 &ironlake_display_wm_info,
4178 ILK_LP0_PLANE_LATENCY,
4179 &ironlake_cursor_wm_info,
4180 ILK_LP0_CURSOR_LATENCY,
4181 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4182 I915_WRITE(WM0_PIPEA_ILK,
4183 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4184 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4185 " plane %d, " "cursor: %d\n",
4186 plane_wm, cursor_wm);
d210246a 4187 enabled |= 1;
b79d4990
JB		 4188 }
4189
9f405100
CW		 4190 if (g4x_compute_wm0(dev, 1,
4191 &ironlake_display_wm_info,
4192 ILK_LP0_PLANE_LATENCY,
4193 &ironlake_cursor_wm_info,
4194 ILK_LP0_CURSOR_LATENCY,
4195 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4196 I915_WRITE(WM0_PIPEB_ILK,
4197 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4198 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4199 " plane %d, cursor: %d\n",
4200 plane_wm, cursor_wm);
d210246a 4201 enabled |= 2;
b79d4990
JB		 4202 }
4203
4204 /*
4205 * Calculate and update the self-refresh watermark only when one
4206 * display plane is used.
4207 */
4208 I915_WRITE(WM3_LP_ILK, 0);
4209 I915_WRITE(WM2_LP_ILK, 0);
4210 I915_WRITE(WM1_LP_ILK, 0);
4211
d210246a 4212 if (!single_plane_enabled(enabled))
b79d4990 4213 return;
d210246a 4214 enabled = ffs(enabled) - 1;
b79d4990
JB		 4215
4216 /* WM1 */
d210246a
CW		 4217 if (!ironlake_compute_srwm(dev, 1, enabled,
4218 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4219 &ironlake_display_srwm_info,
4220 &ironlake_cursor_srwm_info,
4221 &fbc_wm, &plane_wm, &cursor_wm))
4222 return;
4223
4224 I915_WRITE(WM1_LP_ILK,
4225 WM1_LP_SR_EN |
4226 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4227 (fbc_wm << WM1_LP_FBC_SHIFT) |
4228 (plane_wm << WM1_LP_SR_SHIFT) |
4229 cursor_wm);
4230
4231 /* WM2 */
d210246a
CW		 4232 if (!ironlake_compute_srwm(dev, 2, enabled,
4233 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4234 &ironlake_display_srwm_info,
4235 &ironlake_cursor_srwm_info,
4236 &fbc_wm, &plane_wm, &cursor_wm))
4237 return;
4238
4239 I915_WRITE(WM2_LP_ILK,
4240 WM2_LP_EN |
4241 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4242 (fbc_wm << WM1_LP_FBC_SHIFT) |
4243 (plane_wm << WM1_LP_SR_SHIFT) |
4244 cursor_wm);
4245
4246 /*
4247 * WM3 is unsupported on ILK, probably because we don't have latency
4248 * data for that power state
4249 */
1398261a
YL		 4250}
4251
d210246a 4252static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4253{
4254 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4255 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4256 int fbc_wm, plane_wm, cursor_wm;
4257 unsigned int enabled;
1398261a
YL		 4258
4259 enabled = 0;
9f405100
CW		 4260 if (g4x_compute_wm0(dev, 0,
4261 &sandybridge_display_wm_info, latency,
4262 &sandybridge_cursor_wm_info, latency,
4263 &plane_wm, &cursor_wm)) {
1398261a
YL		 4264 I915_WRITE(WM0_PIPEA_ILK,
4265 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4266 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4267 " plane %d, " "cursor: %d\n",
4268 plane_wm, cursor_wm);
d210246a 4269 enabled |= 1;
1398261a
YL		 4270 }
4271
9f405100
CW		 4272 if (g4x_compute_wm0(dev, 1,
4273 &sandybridge_display_wm_info, latency,
4274 &sandybridge_cursor_wm_info, latency,
4275 &plane_wm, &cursor_wm)) {
1398261a
YL		 4276 I915_WRITE(WM0_PIPEB_ILK,
4277 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4278 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4279 " plane %d, cursor: %d\n",
4280 plane_wm, cursor_wm);
d210246a 4281 enabled |= 2;
1398261a
YL		 4282 }
4283
4284 /*
4285 * Calculate and update the self-refresh watermark only when one
4286 * display plane is used.
4287 *
4288 * SNB support 3 levels of watermark.
4289 *
4290 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4291 * and disabled in the descending order
4292 *
4293 */
4294 I915_WRITE(WM3_LP_ILK, 0);
4295 I915_WRITE(WM2_LP_ILK, 0);
4296 I915_WRITE(WM1_LP_ILK, 0);
4297
d210246a 4298 if (!single_plane_enabled(enabled))
1398261a 4299 return;
d210246a 4300 enabled = ffs(enabled) - 1;
1398261a
YL		 4301
4302 /* WM1 */
d210246a
CW		 4303 if (!ironlake_compute_srwm(dev, 1, enabled,
4304 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4305 &sandybridge_display_srwm_info,
4306 &sandybridge_cursor_srwm_info,
4307 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4308 return;
4309
4310 I915_WRITE(WM1_LP_ILK,
4311 WM1_LP_SR_EN |
4312 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4313 (fbc_wm << WM1_LP_FBC_SHIFT) |
4314 (plane_wm << WM1_LP_SR_SHIFT) |
4315 cursor_wm);
4316
4317 /* WM2 */
d210246a
CW		 4318 if (!ironlake_compute_srwm(dev, 2, enabled,
4319 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4320 &sandybridge_display_srwm_info,
4321 &sandybridge_cursor_srwm_info,
4322 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4323 return;
4324
4325 I915_WRITE(WM2_LP_ILK,
4326 WM2_LP_EN |
4327 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4328 (fbc_wm << WM1_LP_FBC_SHIFT) |
4329 (plane_wm << WM1_LP_SR_SHIFT) |
4330 cursor_wm);
4331
4332 /* WM3 */
d210246a
CW		 4333 if (!ironlake_compute_srwm(dev, 3, enabled,
4334 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4335 &sandybridge_display_srwm_info,
4336 &sandybridge_cursor_srwm_info,
4337 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4338 return;
4339
4340 I915_WRITE(WM3_LP_ILK,
4341 WM3_LP_EN |
4342 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4343 (fbc_wm << WM1_LP_FBC_SHIFT) |
4344 (plane_wm << WM1_LP_SR_SHIFT) |
4345 cursor_wm);
4346}
4347
7662c8bd
SL		 4348/**
4349 * intel_update_watermarks - update FIFO watermark values based on current modes
4350 *
4351 * Calculate watermark values for the various WM regs based on current mode
4352 * and plane configuration.
4353 *
4354 * There are several cases to deal with here:
4355 * - normal (i.e. non-self-refresh)
4356 * - self-refresh (SR) mode
4357 * - lines are large relative to FIFO size (buffer can hold up to 2)
4358 * - lines are small relative to FIFO size (buffer can hold more than 2
4359 * lines), so need to account for TLB latency
4360 *
4361 * The normal calculation is:
4362 * watermark = dotclock * bytes per pixel * latency
4363 * where latency is platform & configuration dependent (we assume pessimal
4364 * values here).
4365 *
4366 * The SR calculation is:
4367 * watermark = (trunc(latency/line time)+1) * surface width *
4368 * bytes per pixel
4369 * where
4370 * line time = htotal / dotclock
fa143215 4371 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4372 * and latency is assumed to be high, as above.
4373 *
4374 * The final value programmed to the register should always be rounded up,
4375 * and include an extra 2 entries to account for clock crossings.
4376 *
4377 * We don't use the sprite, so we can ignore that. And on Crestline we have
4378 * to set the non-SR watermarks to 8.
5eddb70b 4379 */
7662c8bd
SL		 4380static void intel_update_watermarks(struct drm_device *dev)
4381{
e70236a8 4382 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4383
d210246a
CW		 4384 if (dev_priv->display.update_wm)
4385 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4386}
4387
a7615030
CW		 4388static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4389{
4390 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4391}
4392
5a354204
JB		 4393/**
4394 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4395 * @crtc: CRTC structure
4396 *
4397 * A pipe may be connected to one or more outputs. Based on the depth of the
4398 * attached framebuffer, choose a good color depth to use on the pipe.
4399 *
4400 * If possible, match the pipe depth to the fb depth. In some cases, this
4401 * isn't ideal, because the connected output supports a lesser or restricted
4402 * set of depths. Resolve that here:
4403 * LVDS typically supports only 6bpc, so clamp down in that case
4404 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4405 * Displays may support a restricted set as well, check EDID and clamp as
4406 * appropriate.
4407 *
4408 * RETURNS:
4409 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4410 * true if they don't match).
4411 */
4412static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4413 unsigned int *pipe_bpp)
4414{
4415 struct drm_device *dev = crtc->dev;
4416 struct drm_i915_private *dev_priv = dev->dev_private;
4417 struct drm_encoder *encoder;
4418 struct drm_connector *connector;
4419 unsigned int display_bpc = UINT_MAX, bpc;
4420
4421 /* Walk the encoders & connectors on this crtc, get min bpc */
4422 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4423 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4424
4425 if (encoder->crtc != crtc)
4426 continue;
4427
4428 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4429 unsigned int lvds_bpc;
4430
4431 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4432 LVDS_A3_POWER_UP)
4433 lvds_bpc = 8;
4434 else
4435 lvds_bpc = 6;
4436
4437 if (lvds_bpc < display_bpc) {
4438 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4439 display_bpc = lvds_bpc;
4440 }
4441 continue;
4442 }
4443
4444 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4445 /* Use VBT settings if we have an eDP panel */
4446 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4447
4448 if (edp_bpc < display_bpc) {
4449 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4450 display_bpc = edp_bpc;
4451 }
4452 continue;
4453 }
4454
4455 /* Not one of the known troublemakers, check the EDID */
4456 list_for_each_entry(connector, &dev->mode_config.connector_list,
4457 head) {
4458 if (connector->encoder != encoder)
4459 continue;
4460
4461 if (connector->display_info.bpc < display_bpc) {
4462 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4463 display_bpc = connector->display_info.bpc;
4464 }
4465 }
4466
4467 /*
4468 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4469 * through, clamp it down. (Note: >12bpc will be caught below.)
4470 */
4471 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4472 if (display_bpc > 8 && display_bpc < 12) {
4473 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4474 display_bpc = 12;
4475 } else {
4476 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4477 display_bpc = 8;
4478 }
4479 }
4480 }
4481
4482 /*
4483 * We could just drive the pipe at the highest bpc all the time and
4484 * enable dithering as needed, but that costs bandwidth. So choose
4485 * the minimum value that expresses the full color range of the fb but
4486 * also stays within the max display bpc discovered above.
4487 */
4488
4489 switch (crtc->fb->depth) {
4490 case 8:
4491 bpc = 8; /* since we go through a colormap */
4492 break;
4493 case 15:
4494 case 16:
4495 bpc = 6; /* min is 18bpp */
4496 break;
4497 case 24:
4498 bpc = min((unsigned int)8, display_bpc);
4499 break;
4500 case 30:
4501 bpc = min((unsigned int)10, display_bpc);
4502 break;
4503 case 48:
4504 bpc = min((unsigned int)12, display_bpc);
4505 break;
4506 default:
4507 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4508 bpc = min((unsigned int)8, display_bpc);
4509 break;
4510 }
4511
4512 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4513 bpc, display_bpc);
4514
4515 *pipe_bpp = bpc * 3;
4516
4517 return display_bpc != bpc;
4518}
4519
f564048e
EA		 4520static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4521 struct drm_display_mode *mode,
4522 struct drm_display_mode *adjusted_mode,
4523 int x, int y,
4524 struct drm_framebuffer *old_fb)
79e53945
JB		 4525{
4526 struct drm_device *dev = crtc->dev;
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4529 int pipe = intel_crtc->pipe;
80824003 4530 int plane = intel_crtc->plane;
c751ce4f 4531 int refclk, num_connectors = 0;
652c393a 4532 intel_clock_t clock, reduced_clock;
5eddb70b 4533 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4534 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4535 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4536 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4537 struct intel_encoder *encoder;
d4906093 4538 const intel_limit_t *limit;
5c3b82e2 4539 int ret;
fae14981 4540 u32 temp;
aa9b500d 4541 u32 lvds_sync = 0;
79e53945 4542
5eddb70b
CW		 4543 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4544 if (encoder->base.crtc != crtc)
79e53945
JB		 4545 continue;
4546
5eddb70b 4547 switch (encoder->type) {
79e53945
JB		 4548 case INTEL_OUTPUT_LVDS:
4549 is_lvds = true;
4550 break;
4551 case INTEL_OUTPUT_SDVO:
7d57382e 4552 case INTEL_OUTPUT_HDMI:
79e53945 4553 is_sdvo = true;
5eddb70b 4554 if (encoder->needs_tv_clock)
e2f0ba97 4555 is_tv = true;
79e53945
JB		 4556 break;
4557 case INTEL_OUTPUT_DVO:
4558 is_dvo = true;
4559 break;
4560 case INTEL_OUTPUT_TVOUT:
4561 is_tv = true;
4562 break;
4563 case INTEL_OUTPUT_ANALOG:
4564 is_crt = true;
4565 break;
a4fc5ed6
KP		 4566 case INTEL_OUTPUT_DISPLAYPORT:
4567 is_dp = true;
4568 break;
79e53945 4569 }
43565a06 4570
c751ce4f 4571 num_connectors++;
79e53945
JB		 4572 }
4573
a7615030 4574 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4575 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4576 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4577 refclk / 1000);
a6c45cf0 4578 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4579 refclk = 96000;
4580 } else {
4581 refclk = 48000;
4582 }
4583
d4906093
ML		 4584 /*
4585 * Returns a set of divisors for the desired target clock with the given
4586 * refclk, or FALSE. The returned values represent the clock equation:
4587 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4588 */
1b894b59 4589 limit = intel_limit(crtc, refclk);
d4906093 4590 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4591 if (!ok) {
4592 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4593 return -EINVAL;
79e53945
JB		 4594 }
4595
cda4b7d3 4596 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4597 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4598
ddc9003c
ZY		 4599 if (is_lvds && dev_priv->lvds_downclock_avail) {
4600 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4601 dev_priv->lvds_downclock,
4602 refclk,
4603 &reduced_clock);
18f9ed12
ZY		 4604 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4605 /*
4606 * If the different P is found, it means that we can't
4607 * switch the display clock by using the FP0/FP1.
4608 * In such case we will disable the LVDS downclock
4609 * feature.
4610 */
4611 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4612 "LVDS clock/downclock\n");
18f9ed12
ZY		 4613 has_reduced_clock = 0;
4614 }
652c393a 4615 }
7026d4ac
ZW		 4616 /* SDVO TV has fixed PLL values depend on its clock range,
4617 this mirrors vbios setting. */
4618 if (is_sdvo && is_tv) {
4619 if (adjusted_mode->clock >= 100000
5eddb70b 4620 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4621 clock.p1 = 2;
4622 clock.p2 = 10;
4623 clock.n = 3;
4624 clock.m1 = 16;
4625 clock.m2 = 8;
4626 } else if (adjusted_mode->clock >= 140500
5eddb70b 4627 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4628 clock.p1 = 1;
4629 clock.p2 = 10;
4630 clock.n = 6;
4631 clock.m1 = 12;
4632 clock.m2 = 8;
4633 }
4634 }
4635
f2b115e6 4636 if (IS_PINEVIEW(dev)) {
2177832f 4637 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4638 if (has_reduced_clock)
4639 fp2 = (1 << reduced_clock.n) << 16 |
4640 reduced_clock.m1 << 8 | reduced_clock.m2;
4641 } else {
2177832f 4642 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4643 if (has_reduced_clock)
4644 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4645 reduced_clock.m2;
4646 }
79e53945 4647
929c77fb 4648 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4649
a6c45cf0 4650 if (!IS_GEN2(dev)) {
79e53945
JB		 4651 if (is_lvds)
4652 dpll |= DPLLB_MODE_LVDS;
4653 else
4654 dpll |= DPLLB_MODE_DAC_SERIAL;
4655 if (is_sdvo) {
6c9547ff
CW		 4656 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4657 if (pixel_multiplier > 1) {
4658 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4659 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4660 }
79e53945 4661 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4662 }
929c77fb 4663 if (is_dp)
a4fc5ed6 4664 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4665
4666 /* compute bitmask from p1 value */
f2b115e6
AJ		 4667 if (IS_PINEVIEW(dev))
4668 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4669 else {
2177832f 4670 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4671 if (IS_G4X(dev) && has_reduced_clock)
4672 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4673 }
79e53945
JB		 4674 switch (clock.p2) {
4675 case 5:
4676 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4677 break;
4678 case 7:
4679 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4680 break;
4681 case 10:
4682 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4683 break;
4684 case 14:
4685 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4686 break;
4687 }
929c77fb 4688 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4689 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4690 } else {
4691 if (is_lvds) {
4692 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4693 } else {
4694 if (clock.p1 == 2)
4695 dpll |= PLL_P1_DIVIDE_BY_TWO;
4696 else
4697 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4698 if (clock.p2 == 4)
4699 dpll |= PLL_P2_DIVIDE_BY_4;
4700 }
4701 }
4702
43565a06
KH		 4703 if (is_sdvo && is_tv)
4704 dpll |= PLL_REF_INPUT_TVCLKINBC;
4705 else if (is_tv)
79e53945 4706 /* XXX: just matching BIOS for now */
43565a06 4707 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4708 dpll |= 3;
a7615030 4709 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4710 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4711 else
4712 dpll |= PLL_REF_INPUT_DREFCLK;
4713
4714 /* setup pipeconf */
5eddb70b 4715 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4716
4717 /* Set up the display plane register */
4718 dspcntr = DISPPLANE_GAMMA_ENABLE;
4719
f2b115e6 4720 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4721 enable color space conversion */
929c77fb
EA		 4722 if (pipe == 0)
4723 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4724 else
4725 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4726
a6c45cf0 4727 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4728 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4729 * core speed.
4730 *
4731 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4732 * pipe == 0 check?
4733 */
e70236a8
JB		 4734 if (mode->clock >
4735 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4736 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4737 else
5eddb70b 4738 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4739 }
4740
929c77fb 4741 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4742
28c97730 4743 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4744 drm_mode_debug_printmodeline(mode);
4745
fae14981
EA		 4746 I915_WRITE(FP0(pipe), fp);
4747 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4748
fae14981 4749 POSTING_READ(DPLL(pipe));
c713bb08 4750 udelay(150);
8db9d77b 4751
79e53945
JB		 4752 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4753 * This is an exception to the general rule that mode_set doesn't turn
4754 * things on.
4755 */
4756 if (is_lvds) {
fae14981 4757 temp = I915_READ(LVDS);
5eddb70b 4758 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4759 if (pipe == 1) {
929c77fb 4760 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4761 } else {
929c77fb 4762 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4763 }
a3e17eb8 4764 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4765 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4766 /* Set the B0-B3 data pairs corresponding to whether we're going to
4767 * set the DPLLs for dual-channel mode or not.
4768 */
4769 if (clock.p2 == 7)
5eddb70b 4770 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4771 else
5eddb70b 4772 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4773
4774 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4775 * appropriately here, but we need to look more thoroughly into how
4776 * panels behave in the two modes.
4777 */
929c77fb
EA		 4778 /* set the dithering flag on LVDS as needed */
4779 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4780 if (dev_priv->lvds_dither)
5eddb70b 4781 temp |= LVDS_ENABLE_DITHER;
434ed097 4782 else
5eddb70b 4783 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4784 }
aa9b500d
BF		 4785 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4786 lvds_sync |= LVDS_HSYNC_POLARITY;
4787 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4788 lvds_sync |= LVDS_VSYNC_POLARITY;
4789 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4790 != lvds_sync) {
4791 char flags[2] = "-+";
4792 DRM_INFO("Changing LVDS panel from "
4793 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4794 flags[!(temp & LVDS_HSYNC_POLARITY)],
4795 flags[!(temp & LVDS_VSYNC_POLARITY)],
4796 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4797 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4798 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4799 temp |= lvds_sync;
4800 }
fae14981 4801 I915_WRITE(LVDS, temp);
79e53945 4802 }
434ed097 4803
929c77fb 4804 if (is_dp) {
a4fc5ed6 4805 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4806 }
4807
fae14981 4808 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4809
c713bb08 4810 /* Wait for the clocks to stabilize. */
fae14981 4811 POSTING_READ(DPLL(pipe));
c713bb08 4812 udelay(150);
32f9d658 4813
c713bb08
EA		 4814 if (INTEL_INFO(dev)->gen >= 4) {
4815 temp = 0;
4816 if (is_sdvo) {
4817 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4818 if (temp > 1)
4819 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4820 else
4821 temp = 0;
32f9d658 4822 }
c713bb08
EA		 4823 I915_WRITE(DPLL_MD(pipe), temp);
4824 } else {
4825 /* The pixel multiplier can only be updated once the
4826 * DPLL is enabled and the clocks are stable.
4827 *
4828 * So write it again.
4829 */
fae14981 4830 I915_WRITE(DPLL(pipe), dpll);
79e53945 4831 }
79e53945 4832
5eddb70b 4833 intel_crtc->lowfreq_avail = false;
652c393a 4834 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4835 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4836 intel_crtc->lowfreq_avail = true;
4837 if (HAS_PIPE_CXSR(dev)) {
28c97730 4838 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4839 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4840 }
4841 } else {
fae14981 4842 I915_WRITE(FP1(pipe), fp);
652c393a 4843 if (HAS_PIPE_CXSR(dev)) {
28c97730 4844 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4845 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4846 }
4847 }
4848
734b4157
KH		 4849 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4850 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4851 /* the chip adds 2 halflines automatically */
4852 adjusted_mode->crtc_vdisplay -= 1;
4853 adjusted_mode->crtc_vtotal -= 1;
4854 adjusted_mode->crtc_vblank_start -= 1;
4855 adjusted_mode->crtc_vblank_end -= 1;
4856 adjusted_mode->crtc_vsync_end -= 1;
4857 adjusted_mode->crtc_vsync_start -= 1;
4858 } else
4859 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4860
5eddb70b
CW		 4861 I915_WRITE(HTOTAL(pipe),
4862 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4863 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4864 I915_WRITE(HBLANK(pipe),
4865 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4866 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4867 I915_WRITE(HSYNC(pipe),
4868 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4869 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4870
4871 I915_WRITE(VTOTAL(pipe),
4872 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4873 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4874 I915_WRITE(VBLANK(pipe),
4875 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4876 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4877 I915_WRITE(VSYNC(pipe),
4878 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4879 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4880
4881 /* pipesrc and dspsize control the size that is scaled from,
4882 * which should always be the user's requested size.
79e53945 4883 */
929c77fb
EA		 4884 I915_WRITE(DSPSIZE(plane),
4885 ((mode->vdisplay - 1) << 16) |
4886 (mode->hdisplay - 1));
4887 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4888 I915_WRITE(PIPESRC(pipe),
4889 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4890
f564048e
EA		 4891 I915_WRITE(PIPECONF(pipe), pipeconf);
4892 POSTING_READ(PIPECONF(pipe));
929c77fb 4893 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4894
4895 intel_wait_for_vblank(dev, pipe);
4896
f564048e
EA		 4897 I915_WRITE(DSPCNTR(plane), dspcntr);
4898 POSTING_READ(DSPCNTR(plane));
284d9529 4899 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4900
4901 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4902
4903 intel_update_watermarks(dev);
4904
f564048e
EA		 4905 return ret;
4906}
4907
4908static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4909 struct drm_display_mode *mode,
4910 struct drm_display_mode *adjusted_mode,
4911 int x, int y,
4912 struct drm_framebuffer *old_fb)
79e53945
JB		 4913{
4914 struct drm_device *dev = crtc->dev;
4915 struct drm_i915_private *dev_priv = dev->dev_private;
4916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917 int pipe = intel_crtc->pipe;
80824003 4918 int plane = intel_crtc->plane;
c751ce4f 4919 int refclk, num_connectors = 0;
652c393a 4920 intel_clock_t clock, reduced_clock;
5eddb70b 4921 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4922 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4923 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4924 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4925 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4926 struct intel_encoder *encoder;
d4906093 4927 const intel_limit_t *limit;
5c3b82e2 4928 int ret;
2c07245f 4929 struct fdi_m_n m_n = {0};
fae14981 4930 u32 temp;
aa9b500d 4931 u32 lvds_sync = 0;
5a354204
JB		 4932 int target_clock, pixel_multiplier, lane, link_bw, factor;
4933 unsigned int pipe_bpp;
4934 bool dither;
79e53945 4935
5eddb70b
CW		 4936 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4937 if (encoder->base.crtc != crtc)
79e53945
JB		 4938 continue;
4939
5eddb70b 4940 switch (encoder->type) {
79e53945
JB		 4941 case INTEL_OUTPUT_LVDS:
4942 is_lvds = true;
4943 break;
4944 case INTEL_OUTPUT_SDVO:
7d57382e 4945 case INTEL_OUTPUT_HDMI:
79e53945 4946 is_sdvo = true;
5eddb70b 4947 if (encoder->needs_tv_clock)
e2f0ba97 4948 is_tv = true;
79e53945 4949 break;
79e53945
JB		 4950 case INTEL_OUTPUT_TVOUT:
4951 is_tv = true;
4952 break;
4953 case INTEL_OUTPUT_ANALOG:
4954 is_crt = true;
4955 break;
a4fc5ed6
KP		 4956 case INTEL_OUTPUT_DISPLAYPORT:
4957 is_dp = true;
4958 break;
32f9d658 4959 case INTEL_OUTPUT_EDP:
5eddb70b 4960 has_edp_encoder = encoder;
32f9d658 4961 break;
79e53945 4962 }
43565a06 4963
c751ce4f 4964 num_connectors++;
79e53945
JB		 4965 }
4966
a7615030 4967 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4968 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4969 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4970 refclk / 1000);
a07d6787 4971 } else {
79e53945 4972 refclk = 96000;
8febb297
EA		 4973 if (!has_edp_encoder ||
4974 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4975 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4976 }
4977
d4906093
ML		 4978 /*
4979 * Returns a set of divisors for the desired target clock with the given
4980 * refclk, or FALSE. The returned values represent the clock equation:
4981 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4982 */
1b894b59 4983 limit = intel_limit(crtc, refclk);
d4906093 4984 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4985 if (!ok) {
4986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4987 return -EINVAL;
79e53945
JB		 4988 }
4989
cda4b7d3 4990 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4991 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4992
ddc9003c
ZY		 4993 if (is_lvds && dev_priv->lvds_downclock_avail) {
4994 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4995 dev_priv->lvds_downclock,
4996 refclk,
4997 &reduced_clock);
18f9ed12
ZY		 4998 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4999 /*
5000 * If the different P is found, it means that we can't
5001 * switch the display clock by using the FP0/FP1.
5002 * In such case we will disable the LVDS downclock
5003 * feature.
5004 */
5005 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5006 "LVDS clock/downclock\n");
18f9ed12
ZY		 5007 has_reduced_clock = 0;
5008 }
652c393a 5009 }
7026d4ac
ZW		 5010 /* SDVO TV has fixed PLL values depend on its clock range,
5011 this mirrors vbios setting. */
5012 if (is_sdvo && is_tv) {
5013 if (adjusted_mode->clock >= 100000
5eddb70b 5014 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5015 clock.p1 = 2;
5016 clock.p2 = 10;
5017 clock.n = 3;
5018 clock.m1 = 16;
5019 clock.m2 = 8;
5020 } else if (adjusted_mode->clock >= 140500
5eddb70b 5021 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5022 clock.p1 = 1;
5023 clock.p2 = 10;
5024 clock.n = 6;
5025 clock.m1 = 12;
5026 clock.m2 = 8;
5027 }
5028 }
5029
2c07245f 5030 /* FDI link */
8febb297
EA		 5031 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5032 lane = 0;
5033 /* CPU eDP doesn't require FDI link, so just set DP M/N
5034 according to current link config */
5035 if (has_edp_encoder &&
5036 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5037 target_clock = mode->clock;
5038 intel_edp_link_config(has_edp_encoder,
5039 &lane, &link_bw);
5040 } else {
5041 /* [e]DP over FDI requires target mode clock
5042 instead of link clock */
5043 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5044 target_clock = mode->clock;
8febb297
EA		 5045 else
5046 target_clock = adjusted_mode->clock;
5047
5048 /* FDI is a binary signal running at ~2.7GHz, encoding
5049 * each output octet as 10 bits. The actual frequency
5050 * is stored as a divider into a 100MHz clock, and the
5051 * mode pixel clock is stored in units of 1KHz.
5052 * Hence the bw of each lane in terms of the mode signal
5053 * is:
5054 */
5055 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5056 }
58a27471 5057
8febb297
EA		 5058 /* determine panel color depth */
5059 temp = I915_READ(PIPECONF(pipe));
5060 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5061 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5062 switch (pipe_bpp) {
5063 case 18:
5064 temp |= PIPE_6BPC;
8febb297 5065 break;
5a354204
JB		 5066 case 24:
5067 temp |= PIPE_8BPC;
8febb297 5068 break;
5a354204
JB		 5069 case 30:
5070 temp |= PIPE_10BPC;
8febb297 5071 break;
5a354204
JB		 5072 case 36:
5073 temp |= PIPE_12BPC;
8febb297
EA		 5074 break;
5075 default:
5a354204
JB		 5076 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
5077 temp |= PIPE_8BPC;
5078 pipe_bpp = 24;
5079 break;
8febb297 5080 }
77ffb597 5081
5a354204
JB		 5082 intel_crtc->bpp = pipe_bpp;
5083 I915_WRITE(PIPECONF(pipe), temp);
5084
8febb297
EA		 5085 if (!lane) {
5086 /*
5087 * Account for spread spectrum to avoid
5088 * oversubscribing the link. Max center spread
5089 * is 2.5%; use 5% for safety's sake.
5090 */
5a354204 5091 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5092 lane = bps / (link_bw * 8) + 1;
5eb08b69 5093 }
2c07245f 5094
8febb297
EA		 5095 intel_crtc->fdi_lanes = lane;
5096
5097 if (pixel_multiplier > 1)
5098 link_bw *= pixel_multiplier;
5a354204
JB		 5099 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5100 &m_n);
8febb297 5101
c038e51e
ZW		 5102 /* Ironlake: try to setup display ref clock before DPLL
5103 * enabling. This is only under driver's control after
5104 * PCH B stepping, previous chipset stepping should be
5105 * ignoring this setting.
5106 */
8febb297
EA		 5107 temp = I915_READ(PCH_DREF_CONTROL);
5108 /* Always enable nonspread source */
5109 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5110 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5111 temp &= ~DREF_SSC_SOURCE_MASK;
5112 temp |= DREF_SSC_SOURCE_ENABLE;
5113 I915_WRITE(PCH_DREF_CONTROL, temp);
5114
5115 POSTING_READ(PCH_DREF_CONTROL);
5116 udelay(200);
fc9a2228 5117
8febb297
EA		 5118 if (has_edp_encoder) {
5119 if (intel_panel_use_ssc(dev_priv)) {
5120 temp |= DREF_SSC1_ENABLE;
fc9a2228 5121 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 5122
fc9a2228
CW		 5123 POSTING_READ(PCH_DREF_CONTROL);
5124 udelay(200);
5125 }
8febb297
EA		 5126 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5127
5128 /* Enable CPU source on CPU attached eDP */
5129 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5130 if (intel_panel_use_ssc(dev_priv))
5131 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5132 else
5133 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5134 } else {
5135 /* Enable SSC on PCH eDP if needed */
5136 if (intel_panel_use_ssc(dev_priv)) {
5137 DRM_ERROR("enabling SSC on PCH\n");
5138 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5139 }
5140 }
5141 I915_WRITE(PCH_DREF_CONTROL, temp);
5142 POSTING_READ(PCH_DREF_CONTROL);
5143 udelay(200);
fc9a2228 5144 }
c038e51e 5145
a07d6787
EA		 5146 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5147 if (has_reduced_clock)
5148 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5149 reduced_clock.m2;
79e53945 5150
c1858123 5151 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5152 factor = 21;
5153 if (is_lvds) {
5154 if ((intel_panel_use_ssc(dev_priv) &&
5155 dev_priv->lvds_ssc_freq == 100) ||
5156 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5157 factor = 25;
5158 } else if (is_sdvo && is_tv)
5159 factor = 20;
c1858123 5160
8febb297
EA		 5161 if (clock.m1 < factor * clock.n)
5162 fp |= FP_CB_TUNE;
2c07245f 5163
5eddb70b 5164 dpll = 0;
2c07245f 5165
a07d6787
EA		 5166 if (is_lvds)
5167 dpll |= DPLLB_MODE_LVDS;
5168 else
5169 dpll |= DPLLB_MODE_DAC_SERIAL;
5170 if (is_sdvo) {
5171 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5172 if (pixel_multiplier > 1) {
5173 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5174 }
a07d6787
EA		 5175 dpll |= DPLL_DVO_HIGH_SPEED;
5176 }
5177 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5178 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5179
a07d6787
EA		 5180 /* compute bitmask from p1 value */
5181 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5182 /* also FPA1 */
5183 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5184
5185 switch (clock.p2) {
5186 case 5:
5187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5188 break;
5189 case 7:
5190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5191 break;
5192 case 10:
5193 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5194 break;
5195 case 14:
5196 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5197 break;
79e53945
JB		 5198 }
5199
43565a06
KH		 5200 if (is_sdvo && is_tv)
5201 dpll |= PLL_REF_INPUT_TVCLKINBC;
5202 else if (is_tv)
79e53945 5203 /* XXX: just matching BIOS for now */
43565a06 5204 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5205 dpll |= 3;
a7615030 5206 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5207 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5208 else
5209 dpll |= PLL_REF_INPUT_DREFCLK;
5210
5211 /* setup pipeconf */
5eddb70b 5212 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5213
5214 /* Set up the display plane register */
5215 dspcntr = DISPPLANE_GAMMA_ENABLE;
5216
28c97730 5217 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5218 drm_mode_debug_printmodeline(mode);
5219
5c5313c8
JB		 5220 /* PCH eDP needs FDI, but CPU eDP does not */
5221 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5222 I915_WRITE(PCH_FP0(pipe), fp);
5223 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5224
fae14981 5225 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5226 udelay(150);
5227 }
5228
8db9d77b
ZW		 5229 /* enable transcoder DPLL */
5230 if (HAS_PCH_CPT(dev)) {
5231 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5232 switch (pipe) {
5233 case 0:
5eddb70b 5234 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5235 break;
5236 case 1:
5eddb70b 5237 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5238 break;
5239 case 2:
5240 /* FIXME: manage transcoder PLLs? */
5241 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5242 break;
5243 default:
5244 BUG();
32f9d658 5245 }
8db9d77b 5246 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5247
5248 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5249 udelay(150);
5250 }
5251
79e53945
JB		 5252 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5253 * This is an exception to the general rule that mode_set doesn't turn
5254 * things on.
5255 */
5256 if (is_lvds) {
fae14981 5257 temp = I915_READ(PCH_LVDS);
5eddb70b 5258 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5259 if (pipe == 1) {
5260 if (HAS_PCH_CPT(dev))
5eddb70b 5261 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5262 else
5eddb70b 5263 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5264 } else {
5265 if (HAS_PCH_CPT(dev))
5eddb70b 5266 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5267 else
5eddb70b 5268 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5269 }
a3e17eb8 5270 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5271 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5272 /* Set the B0-B3 data pairs corresponding to whether we're going to
5273 * set the DPLLs for dual-channel mode or not.
5274 */
5275 if (clock.p2 == 7)
5eddb70b 5276 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5277 else
5eddb70b 5278 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5279
5280 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5281 * appropriately here, but we need to look more thoroughly into how
5282 * panels behave in the two modes.
5283 */
aa9b500d
BF		 5284 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5285 lvds_sync |= LVDS_HSYNC_POLARITY;
5286 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5287 lvds_sync |= LVDS_VSYNC_POLARITY;
5288 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5289 != lvds_sync) {
5290 char flags[2] = "-+";
5291 DRM_INFO("Changing LVDS panel from "
5292 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5293 flags[!(temp & LVDS_HSYNC_POLARITY)],
5294 flags[!(temp & LVDS_VSYNC_POLARITY)],
5295 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5296 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5297 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5298 temp |= lvds_sync;
5299 }
fae14981 5300 I915_WRITE(PCH_LVDS, temp);
79e53945 5301 }
434ed097 5302
8febb297
EA		 5303 pipeconf &= ~PIPECONF_DITHER_EN;
5304 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5305 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5306 pipeconf |= PIPECONF_DITHER_EN;
5307 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5308 }
5c5313c8 5309 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5310 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5311 } else {
8db9d77b 5312 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5313 I915_WRITE(TRANSDATA_M1(pipe), 0);
5314 I915_WRITE(TRANSDATA_N1(pipe), 0);
5315 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5316 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5317 }
79e53945 5318
8febb297
EA		 5319 if (!has_edp_encoder ||
5320 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5321 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5322
32f9d658 5323 /* Wait for the clocks to stabilize. */
fae14981 5324 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5325 udelay(150);
5326
8febb297
EA		 5327 /* The pixel multiplier can only be updated once the
5328 * DPLL is enabled and the clocks are stable.
5329 *
5330 * So write it again.
5331 */
fae14981 5332 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5333 }
79e53945 5334
5eddb70b 5335 intel_crtc->lowfreq_avail = false;
652c393a 5336 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5337 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5338 intel_crtc->lowfreq_avail = true;
5339 if (HAS_PIPE_CXSR(dev)) {
28c97730 5340 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5341 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5342 }
5343 } else {
fae14981 5344 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5345 if (HAS_PIPE_CXSR(dev)) {
28c97730 5346 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5347 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5348 }
5349 }
5350
734b4157
KH		 5351 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5352 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5353 /* the chip adds 2 halflines automatically */
5354 adjusted_mode->crtc_vdisplay -= 1;
5355 adjusted_mode->crtc_vtotal -= 1;
5356 adjusted_mode->crtc_vblank_start -= 1;
5357 adjusted_mode->crtc_vblank_end -= 1;
5358 adjusted_mode->crtc_vsync_end -= 1;
5359 adjusted_mode->crtc_vsync_start -= 1;
5360 } else
5361 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5362
5eddb70b
CW		 5363 I915_WRITE(HTOTAL(pipe),
5364 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5365 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5366 I915_WRITE(HBLANK(pipe),
5367 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5368 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5369 I915_WRITE(HSYNC(pipe),
5370 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5371 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5372
5373 I915_WRITE(VTOTAL(pipe),
5374 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5375 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5376 I915_WRITE(VBLANK(pipe),
5377 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5378 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5379 I915_WRITE(VSYNC(pipe),
5380 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5381 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5382
8febb297
EA		 5383 /* pipesrc controls the size that is scaled from, which should
5384 * always be the user's requested size.
79e53945 5385 */
5eddb70b
CW		 5386 I915_WRITE(PIPESRC(pipe),
5387 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5388
8febb297
EA		 5389 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5390 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5391 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5392 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5393
8febb297
EA		 5394 if (has_edp_encoder &&
5395 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5396 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5397 }
5398
5eddb70b
CW		 5399 I915_WRITE(PIPECONF(pipe), pipeconf);
5400 POSTING_READ(PIPECONF(pipe));
79e53945 5401
9d0498a2 5402 intel_wait_for_vblank(dev, pipe);
79e53945 5403
f00a3ddf 5404 if (IS_GEN5(dev)) {
553bd149
ZW		 5405 /* enable address swizzle for tiling buffer */
5406 temp = I915_READ(DISP_ARB_CTL);
5407 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5408 }
5409
5eddb70b 5410 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5411 POSTING_READ(DSPCNTR(plane));
79e53945 5412
5c3b82e2 5413 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5414
5415 intel_update_watermarks(dev);
5416
1f803ee5 5417 return ret;
79e53945
JB		 5418}
5419
f564048e
EA		 5420static int intel_crtc_mode_set(struct drm_crtc *crtc,
5421 struct drm_display_mode *mode,
5422 struct drm_display_mode *adjusted_mode,
5423 int x, int y,
5424 struct drm_framebuffer *old_fb)
5425{
5426 struct drm_device *dev = crtc->dev;
5427 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429 int pipe = intel_crtc->pipe;
f564048e
EA		 5430 int ret;
5431
0b701d27 5432 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5433
f564048e
EA		 5434 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5435 x, y, old_fb);
7662c8bd 5436
79e53945 5437 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5438
1f803ee5 5439 return ret;
79e53945
JB		 5440}
5441
5442/** Loads the palette/gamma unit for the CRTC with the prepared values */
5443void intel_crtc_load_lut(struct drm_crtc *crtc)
5444{
5445 struct drm_device *dev = crtc->dev;
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5448 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5449 int i;
5450
5451 /* The clocks have to be on to load the palette. */
5452 if (!crtc->enabled)
5453 return;
5454
f2b115e6 5455 /* use legacy palette for Ironlake */
bad720ff 5456 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5457 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5458
79e53945
JB		 5459 for (i = 0; i < 256; i++) {
5460 I915_WRITE(palreg + 4 * i,
5461 (intel_crtc->lut_r[i] << 16) |
5462 (intel_crtc->lut_g[i] << 8) |
5463 intel_crtc->lut_b[i]);
5464 }
5465}
5466
560b85bb
CW		 5467static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5468{
5469 struct drm_device *dev = crtc->dev;
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5472 bool visible = base != 0;
5473 u32 cntl;
5474
5475 if (intel_crtc->cursor_visible == visible)
5476 return;
5477
9db4a9c7 5478 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5479 if (visible) {
5480 /* On these chipsets we can only modify the base whilst
5481 * the cursor is disabled.
5482 */
9db4a9c7 5483 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5484
5485 cntl &= ~(CURSOR_FORMAT_MASK);
5486 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5487 cntl |= CURSOR_ENABLE |
5488 CURSOR_GAMMA_ENABLE |
5489 CURSOR_FORMAT_ARGB;
5490 } else
5491 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5492 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5493
5494 intel_crtc->cursor_visible = visible;
5495}
5496
5497static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5498{
5499 struct drm_device *dev = crtc->dev;
5500 struct drm_i915_private *dev_priv = dev->dev_private;
5501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5502 int pipe = intel_crtc->pipe;
5503 bool visible = base != 0;
5504
5505 if (intel_crtc->cursor_visible != visible) {
548f245b 5506 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5507 if (base) {
5508 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5509 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5510 cntl |= pipe << 28; /* Connect to correct pipe */
5511 } else {
5512 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5513 cntl |= CURSOR_MODE_DISABLE;
5514 }
9db4a9c7 5515 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5516
5517 intel_crtc->cursor_visible = visible;
5518 }
5519 /* and commit changes on next vblank */
9db4a9c7 5520 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5521}
5522
cda4b7d3 5523/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5524static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5525 bool on)
cda4b7d3
CW		 5526{
5527 struct drm_device *dev = crtc->dev;
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5530 int pipe = intel_crtc->pipe;
5531 int x = intel_crtc->cursor_x;
5532 int y = intel_crtc->cursor_y;
560b85bb 5533 u32 base, pos;
cda4b7d3
CW		 5534 bool visible;
5535
5536 pos = 0;
5537
6b383a7f 5538 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5539 base = intel_crtc->cursor_addr;
5540 if (x > (int) crtc->fb->width)
5541 base = 0;
5542
5543 if (y > (int) crtc->fb->height)
5544 base = 0;
5545 } else
5546 base = 0;
5547
5548 if (x < 0) {
5549 if (x + intel_crtc->cursor_width < 0)
5550 base = 0;
5551
5552 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5553 x = -x;
5554 }
5555 pos |= x << CURSOR_X_SHIFT;
5556
5557 if (y < 0) {
5558 if (y + intel_crtc->cursor_height < 0)
5559 base = 0;
5560
5561 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5562 y = -y;
5563 }
5564 pos |= y << CURSOR_Y_SHIFT;
5565
5566 visible = base != 0;
560b85bb 5567 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5568 return;
5569
9db4a9c7 5570 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5571 if (IS_845G(dev) || IS_I865G(dev))
5572 i845_update_cursor(crtc, base);
5573 else
5574 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5575
5576 if (visible)
5577 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5578}
5579
79e53945 5580static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5581 struct drm_file *file,
79e53945
JB		 5582 uint32_t handle,
5583 uint32_t width, uint32_t height)
5584{
5585 struct drm_device *dev = crtc->dev;
5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5588 struct drm_i915_gem_object *obj;
cda4b7d3 5589 uint32_t addr;
3f8bc370 5590 int ret;
79e53945 5591
28c97730 5592 DRM_DEBUG_KMS("\n");
79e53945
JB		 5593
5594 /* if we want to turn off the cursor ignore width and height */
5595 if (!handle) {
28c97730 5596 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5597 addr = 0;
05394f39 5598 obj = NULL;
5004417d 5599 mutex_lock(&dev->struct_mutex);
3f8bc370 5600 goto finish;
79e53945
JB		 5601 }
5602
5603 /* Currently we only support 64x64 cursors */
5604 if (width != 64 || height != 64) {
5605 DRM_ERROR("we currently only support 64x64 cursors\n");
5606 return -EINVAL;
5607 }
5608
05394f39 5609 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5610 if (&obj->base == NULL)
79e53945
JB		 5611 return -ENOENT;
5612
05394f39 5613 if (obj->base.size < width * height * 4) {
79e53945 5614 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5615 ret = -ENOMEM;
5616 goto fail;
79e53945
JB		 5617 }
5618
71acb5eb 5619 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5620 mutex_lock(&dev->struct_mutex);
b295d1b6 5621 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5622 if (obj->tiling_mode) {
5623 DRM_ERROR("cursor cannot be tiled\n");
5624 ret = -EINVAL;
5625 goto fail_locked;
5626 }
5627
2da3b9b9 5628 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5629 if (ret) {
5630 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5631 goto fail_locked;
e7b526bb
CW		 5632 }
5633
d9e86c0e
CW		 5634 ret = i915_gem_object_put_fence(obj);
5635 if (ret) {
2da3b9b9 5636 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5637 goto fail_unpin;
5638 }
5639
05394f39 5640 addr = obj->gtt_offset;
71acb5eb 5641 } else {
6eeefaf3 5642 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5643 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5644 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5645 align);
71acb5eb
DA		 5646 if (ret) {
5647 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5648 goto fail_locked;
71acb5eb 5649 }
05394f39 5650 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5651 }
5652
a6c45cf0 5653 if (IS_GEN2(dev))
14b60391
JB		 5654 I915_WRITE(CURSIZE, (height << 12) | width);
5655
3f8bc370 5656 finish:
3f8bc370 5657 if (intel_crtc->cursor_bo) {
b295d1b6 5658 if (dev_priv->info->cursor_needs_physical) {
05394f39 5659 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5660 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5661 } else
5662 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5663 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5664 }
80824003 5665
7f9872e0 5666 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5667
5668 intel_crtc->cursor_addr = addr;
05394f39 5669 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5670 intel_crtc->cursor_width = width;
5671 intel_crtc->cursor_height = height;
5672
6b383a7f 5673 intel_crtc_update_cursor(crtc, true);
3f8bc370 5674
79e53945 5675 return 0;
e7b526bb 5676fail_unpin:
05394f39 5677 i915_gem_object_unpin(obj);
7f9872e0 5678fail_locked:
34b8686e 5679 mutex_unlock(&dev->struct_mutex);
bc9025bd 5680fail:
05394f39 5681 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5682 return ret;
79e53945
JB		 5683}
5684
5685static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5686{
79e53945 5687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5688
cda4b7d3
CW		 5689 intel_crtc->cursor_x = x;
5690 intel_crtc->cursor_y = y;
652c393a 5691
6b383a7f 5692 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5693
5694 return 0;
5695}
5696
5697/** Sets the color ramps on behalf of RandR */
5698void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5699 u16 blue, int regno)
5700{
5701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5702
5703 intel_crtc->lut_r[regno] = red >> 8;
5704 intel_crtc->lut_g[regno] = green >> 8;
5705 intel_crtc->lut_b[regno] = blue >> 8;
5706}
5707
b8c00ac5
DA		 5708void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5709 u16 *blue, int regno)
5710{
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712
5713 *red = intel_crtc->lut_r[regno] << 8;
5714 *green = intel_crtc->lut_g[regno] << 8;
5715 *blue = intel_crtc->lut_b[regno] << 8;
5716}
5717
79e53945 5718static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5719 u16 *blue, uint32_t start, uint32_t size)
79e53945 5720{
7203425a 5721 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5723
7203425a 5724 for (i = start; i < end; i++) {
79e53945
JB		 5725 intel_crtc->lut_r[i] = red[i] >> 8;
5726 intel_crtc->lut_g[i] = green[i] >> 8;
5727 intel_crtc->lut_b[i] = blue[i] >> 8;
5728 }
5729
5730 intel_crtc_load_lut(crtc);
5731}
5732
5733/**
5734 * Get a pipe with a simple mode set on it for doing load-based monitor
5735 * detection.
5736 *
5737 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5738 * its requirements. The pipe will be connected to no other encoders.
79e53945 5739 *
c751ce4f 5740 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5741 * configured for it. In the future, it could choose to temporarily disable
5742 * some outputs to free up a pipe for its use.
5743 *
5744 * \return crtc, or NULL if no pipes are available.
5745 */
5746
5747/* VESA 640x480x72Hz mode to set on the pipe */
5748static struct drm_display_mode load_detect_mode = {
5749 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5750 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5751};
5752
d2dff872
CW		 5753static struct drm_framebuffer *
5754intel_framebuffer_create(struct drm_device *dev,
5755 struct drm_mode_fb_cmd *mode_cmd,
5756 struct drm_i915_gem_object *obj)
5757{
5758 struct intel_framebuffer *intel_fb;
5759 int ret;
5760
5761 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5762 if (!intel_fb) {
5763 drm_gem_object_unreference_unlocked(&obj->base);
5764 return ERR_PTR(-ENOMEM);
5765 }
5766
5767 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5768 if (ret) {
5769 drm_gem_object_unreference_unlocked(&obj->base);
5770 kfree(intel_fb);
5771 return ERR_PTR(ret);
5772 }
5773
5774 return &intel_fb->base;
5775}
5776
5777static u32
5778intel_framebuffer_pitch_for_width(int width, int bpp)
5779{
5780 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5781 return ALIGN(pitch, 64);
5782}
5783
5784static u32
5785intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5786{
5787 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5788 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5789}
5790
5791static struct drm_framebuffer *
5792intel_framebuffer_create_for_mode(struct drm_device *dev,
5793 struct drm_display_mode *mode,
5794 int depth, int bpp)
5795{
5796 struct drm_i915_gem_object *obj;
5797 struct drm_mode_fb_cmd mode_cmd;
5798
5799 obj = i915_gem_alloc_object(dev,
5800 intel_framebuffer_size_for_mode(mode, bpp));
5801 if (obj == NULL)
5802 return ERR_PTR(-ENOMEM);
5803
5804 mode_cmd.width = mode->hdisplay;
5805 mode_cmd.height = mode->vdisplay;
5806 mode_cmd.depth = depth;
5807 mode_cmd.bpp = bpp;
5808 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5809
5810 return intel_framebuffer_create(dev, &mode_cmd, obj);
5811}
5812
5813static struct drm_framebuffer *
5814mode_fits_in_fbdev(struct drm_device *dev,
5815 struct drm_display_mode *mode)
5816{
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5818 struct drm_i915_gem_object *obj;
5819 struct drm_framebuffer *fb;
5820
5821 if (dev_priv->fbdev == NULL)
5822 return NULL;
5823
5824 obj = dev_priv->fbdev->ifb.obj;
5825 if (obj == NULL)
5826 return NULL;
5827
5828 fb = &dev_priv->fbdev->ifb.base;
5829 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5830 fb->bits_per_pixel))
5831 return NULL;
5832
5833 if (obj->base.size < mode->vdisplay * fb->pitch)
5834 return NULL;
5835
5836 return fb;
5837}
5838
7173188d
CW		 5839bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5840 struct drm_connector *connector,
5841 struct drm_display_mode *mode,
8261b191 5842 struct intel_load_detect_pipe *old)
79e53945
JB		 5843{
5844 struct intel_crtc *intel_crtc;
5845 struct drm_crtc *possible_crtc;
4ef69c7a 5846 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5847 struct drm_crtc *crtc = NULL;
5848 struct drm_device *dev = encoder->dev;
d2dff872 5849 struct drm_framebuffer *old_fb;
79e53945
JB		 5850 int i = -1;
5851
d2dff872
CW		 5852 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5853 connector->base.id, drm_get_connector_name(connector),
5854 encoder->base.id, drm_get_encoder_name(encoder));
5855
79e53945
JB		 5856 /*
5857 * Algorithm gets a little messy:
7a5e4805 5858 *
79e53945
JB		 5859 * - if the connector already has an assigned crtc, use it (but make
5860 * sure it's on first)
7a5e4805 5861 *
79e53945
JB		 5862 * - try to find the first unused crtc that can drive this connector,
5863 * and use that if we find one
79e53945
JB		 5864 */
5865
5866 /* See if we already have a CRTC for this connector */
5867 if (encoder->crtc) {
5868 crtc = encoder->crtc;
8261b191 5869
79e53945 5870 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5871 old->dpms_mode = intel_crtc->dpms_mode;
5872 old->load_detect_temp = false;
5873
5874 /* Make sure the crtc and connector are running */
79e53945 5875 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5876 struct drm_encoder_helper_funcs *encoder_funcs;
5877 struct drm_crtc_helper_funcs *crtc_funcs;
5878
79e53945
JB		 5879 crtc_funcs = crtc->helper_private;
5880 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5881
5882 encoder_funcs = encoder->helper_private;
79e53945
JB		 5883 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5884 }
8261b191 5885
7173188d 5886 return true;
79e53945
JB		 5887 }
5888
5889 /* Find an unused one (if possible) */
5890 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5891 i++;
5892 if (!(encoder->possible_crtcs & (1 << i)))
5893 continue;
5894 if (!possible_crtc->enabled) {
5895 crtc = possible_crtc;
5896 break;
5897 }
79e53945
JB		 5898 }
5899
5900 /*
5901 * If we didn't find an unused CRTC, don't use any.
5902 */
5903 if (!crtc) {
7173188d
CW		 5904 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5905 return false;
79e53945
JB		 5906 }
5907
5908 encoder->crtc = crtc;
c1c43977 5909 connector->encoder = encoder;
79e53945
JB		 5910
5911 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5912 old->dpms_mode = intel_crtc->dpms_mode;
5913 old->load_detect_temp = true;
d2dff872 5914 old->release_fb = NULL;
79e53945 5915
6492711d
CW		 5916 if (!mode)
5917 mode = &load_detect_mode;
79e53945 5918
d2dff872
CW		 5919 old_fb = crtc->fb;
5920
5921 /* We need a framebuffer large enough to accommodate all accesses
5922 * that the plane may generate whilst we perform load detection.
5923 * We can not rely on the fbcon either being present (we get called
5924 * during its initialisation to detect all boot displays, or it may
5925 * not even exist) or that it is large enough to satisfy the
5926 * requested mode.
5927 */
5928 crtc->fb = mode_fits_in_fbdev(dev, mode);
5929 if (crtc->fb == NULL) {
5930 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5931 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5932 old->release_fb = crtc->fb;
5933 } else
5934 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5935 if (IS_ERR(crtc->fb)) {
5936 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5937 crtc->fb = old_fb;
5938 return false;
79e53945 5939 }
79e53945 5940
d2dff872 5941 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5942 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5943 if (old->release_fb)
5944 old->release_fb->funcs->destroy(old->release_fb);
5945 crtc->fb = old_fb;
6492711d 5946 return false;
79e53945 5947 }
7173188d 5948
79e53945 5949 /* let the connector get through one full cycle before testing */
9d0498a2 5950 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5951
7173188d 5952 return true;
79e53945
JB		 5953}
5954
c1c43977 5955void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5956 struct drm_connector *connector,
5957 struct intel_load_detect_pipe *old)
79e53945 5958{
4ef69c7a 5959 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5960 struct drm_device *dev = encoder->dev;
5961 struct drm_crtc *crtc = encoder->crtc;
5962 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5963 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5964
d2dff872
CW		 5965 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5966 connector->base.id, drm_get_connector_name(connector),
5967 encoder->base.id, drm_get_encoder_name(encoder));
5968
8261b191 5969 if (old->load_detect_temp) {
c1c43977 5970 connector->encoder = NULL;
79e53945 5971 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5972
5973 if (old->release_fb)
5974 old->release_fb->funcs->destroy(old->release_fb);
5975
0622a53c 5976 return;
79e53945
JB		 5977 }
5978
c751ce4f 5979 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5980 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5981 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5982 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5983 }
5984}
5985
5986/* Returns the clock of the currently programmed mode of the given pipe. */
5987static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5988{
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5991 int pipe = intel_crtc->pipe;
548f245b 5992 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5993 u32 fp;
5994 intel_clock_t clock;
5995
5996 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5997 fp = I915_READ(FP0(pipe));
79e53945 5998 else
39adb7a5 5999 fp = I915_READ(FP1(pipe));
79e53945
JB		 6000
6001 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6002 if (IS_PINEVIEW(dev)) {
6003 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6004 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6005 } else {
6006 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6007 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6008 }
6009
a6c45cf0 6010 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6011 if (IS_PINEVIEW(dev))
6012 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6013 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6014 else
6015 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6016 DPLL_FPA01_P1_POST_DIV_SHIFT);
6017
6018 switch (dpll & DPLL_MODE_MASK) {
6019 case DPLLB_MODE_DAC_SERIAL:
6020 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6021 5 : 10;
6022 break;
6023 case DPLLB_MODE_LVDS:
6024 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6025 7 : 14;
6026 break;
6027 default:
28c97730 6028 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6029 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6030 return 0;
6031 }
6032
6033 /* XXX: Handle the 100Mhz refclk */
2177832f 6034 intel_clock(dev, 96000, &clock);
79e53945
JB		 6035 } else {
6036 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6037
6038 if (is_lvds) {
6039 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6040 DPLL_FPA01_P1_POST_DIV_SHIFT);
6041 clock.p2 = 14;
6042
6043 if ((dpll & PLL_REF_INPUT_MASK) ==
6044 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6045 /* XXX: might not be 66MHz */
2177832f 6046 intel_clock(dev, 66000, &clock);
79e53945 6047 } else
2177832f 6048 intel_clock(dev, 48000, &clock);
79e53945
JB		 6049 } else {
6050 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6051 clock.p1 = 2;
6052 else {
6053 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6054 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6055 }
6056 if (dpll & PLL_P2_DIVIDE_BY_4)
6057 clock.p2 = 4;
6058 else
6059 clock.p2 = 2;
6060
2177832f 6061 intel_clock(dev, 48000, &clock);
79e53945
JB		 6062 }
6063 }
6064
6065 /* XXX: It would be nice to validate the clocks, but we can't reuse
6066 * i830PllIsValid() because it relies on the xf86_config connector
6067 * configuration being accurate, which it isn't necessarily.
6068 */
6069
6070 return clock.dot;
6071}
6072
6073/** Returns the currently programmed mode of the given pipe. */
6074struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6075 struct drm_crtc *crtc)
6076{
548f245b 6077 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6079 int pipe = intel_crtc->pipe;
6080 struct drm_display_mode *mode;
548f245b
JB		 6081 int htot = I915_READ(HTOTAL(pipe));
6082 int hsync = I915_READ(HSYNC(pipe));
6083 int vtot = I915_READ(VTOTAL(pipe));
6084 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6085
6086 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6087 if (!mode)
6088 return NULL;
6089
6090 mode->clock = intel_crtc_clock_get(dev, crtc);
6091 mode->hdisplay = (htot & 0xffff) + 1;
6092 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6093 mode->hsync_start = (hsync & 0xffff) + 1;
6094 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6095 mode->vdisplay = (vtot & 0xffff) + 1;
6096 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6097 mode->vsync_start = (vsync & 0xffff) + 1;
6098 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6099
6100 drm_mode_set_name(mode);
6101 drm_mode_set_crtcinfo(mode, 0);
6102
6103 return mode;
6104}
6105
652c393a
JB		 6106#define GPU_IDLE_TIMEOUT 500 /* ms */
6107
6108/* When this timer fires, we've been idle for awhile */
6109static void intel_gpu_idle_timer(unsigned long arg)
6110{
6111 struct drm_device *dev = (struct drm_device *)arg;
6112 drm_i915_private_t *dev_priv = dev->dev_private;
6113
ff7ea4c0
CW		 6114 if (!list_empty(&dev_priv->mm.active_list)) {
6115 /* Still processing requests, so just re-arm the timer. */
6116 mod_timer(&dev_priv->idle_timer, jiffies +
6117 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6118 return;
6119 }
652c393a 6120
ff7ea4c0 6121 dev_priv->busy = false;
01dfba93 6122 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6123}
6124
652c393a
JB		 6125#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6126
6127static void intel_crtc_idle_timer(unsigned long arg)
6128{
6129 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6130 struct drm_crtc *crtc = &intel_crtc->base;
6131 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6132 struct intel_framebuffer *intel_fb;
652c393a 6133
ff7ea4c0
CW		 6134 intel_fb = to_intel_framebuffer(crtc->fb);
6135 if (intel_fb && intel_fb->obj->active) {
6136 /* The framebuffer is still being accessed by the GPU. */
6137 mod_timer(&intel_crtc->idle_timer, jiffies +
6138 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6139 return;
6140 }
652c393a 6141
ff7ea4c0 6142 intel_crtc->busy = false;
01dfba93 6143 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6144}
6145
3dec0095 6146static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6147{
6148 struct drm_device *dev = crtc->dev;
6149 drm_i915_private_t *dev_priv = dev->dev_private;
6150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6151 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6152 int dpll_reg = DPLL(pipe);
6153 int dpll;
652c393a 6154
bad720ff 6155 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6156 return;
6157
6158 if (!dev_priv->lvds_downclock_avail)
6159 return;
6160
dbdc6479 6161 dpll = I915_READ(dpll_reg);
652c393a 6162 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6163 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6164
6165 /* Unlock panel regs */
dbdc6479
JB		 6166 I915_WRITE(PP_CONTROL,
6167 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6168
6169 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6170 I915_WRITE(dpll_reg, dpll);
9d0498a2 6171 intel_wait_for_vblank(dev, pipe);
dbdc6479 6172
652c393a
JB		 6173 dpll = I915_READ(dpll_reg);
6174 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6175 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6176
6177 /* ...and lock them again */
6178 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6179 }
6180
6181 /* Schedule downclock */
3dec0095
DV		 6182 mod_timer(&intel_crtc->idle_timer, jiffies +
6183 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6184}
6185
6186static void intel_decrease_pllclock(struct drm_crtc *crtc)
6187{
6188 struct drm_device *dev = crtc->dev;
6189 drm_i915_private_t *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6191 int pipe = intel_crtc->pipe;
9db4a9c7 6192 int dpll_reg = DPLL(pipe);
652c393a
JB		 6193 int dpll = I915_READ(dpll_reg);
6194
bad720ff 6195 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6196 return;
6197
6198 if (!dev_priv->lvds_downclock_avail)
6199 return;
6200
6201 /*
6202 * Since this is called by a timer, we should never get here in
6203 * the manual case.
6204 */
6205 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6206 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6207
6208 /* Unlock panel regs */
4a655f04
JB		 6209 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6210 PANEL_UNLOCK_REGS);
652c393a
JB		 6211
6212 dpll |= DISPLAY_RATE_SELECT_FPA1;
6213 I915_WRITE(dpll_reg, dpll);
9d0498a2 6214 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6215 dpll = I915_READ(dpll_reg);
6216 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6217 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6218
6219 /* ...and lock them again */
6220 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6221 }
6222
6223}
6224
6225/**
6226 * intel_idle_update - adjust clocks for idleness
6227 * @work: work struct
6228 *
6229 * Either the GPU or display (or both) went idle. Check the busy status
6230 * here and adjust the CRTC and GPU clocks as necessary.
6231 */
6232static void intel_idle_update(struct work_struct *work)
6233{
6234 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6235 idle_work);
6236 struct drm_device *dev = dev_priv->dev;
6237 struct drm_crtc *crtc;
6238 struct intel_crtc *intel_crtc;
6239
6240 if (!i915_powersave)
6241 return;
6242
6243 mutex_lock(&dev->struct_mutex);
6244
7648fa99
JB		 6245 i915_update_gfx_val(dev_priv);
6246
652c393a
JB		 6247 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6248 /* Skip inactive CRTCs */
6249 if (!crtc->fb)
6250 continue;
6251
6252 intel_crtc = to_intel_crtc(crtc);
6253 if (!intel_crtc->busy)
6254 intel_decrease_pllclock(crtc);
6255 }
6256
45ac22c8 6257
652c393a
JB		 6258 mutex_unlock(&dev->struct_mutex);
6259}
6260
6261/**
6262 * intel_mark_busy - mark the GPU and possibly the display busy
6263 * @dev: drm device
6264 * @obj: object we're operating on
6265 *
6266 * Callers can use this function to indicate that the GPU is busy processing
6267 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6268 * buffer), we'll also mark the display as busy, so we know to increase its
6269 * clock frequency.
6270 */
05394f39 6271void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6272{
6273 drm_i915_private_t *dev_priv = dev->dev_private;
6274 struct drm_crtc *crtc = NULL;
6275 struct intel_framebuffer *intel_fb;
6276 struct intel_crtc *intel_crtc;
6277
5e17ee74
ZW		 6278 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6279 return;
6280
18b2190c 6281 if (!dev_priv->busy)
28cf798f 6282 dev_priv->busy = true;
18b2190c 6283 else
28cf798f
CW		 6284 mod_timer(&dev_priv->idle_timer, jiffies +
6285 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6286
6287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6288 if (!crtc->fb)
6289 continue;
6290
6291 intel_crtc = to_intel_crtc(crtc);
6292 intel_fb = to_intel_framebuffer(crtc->fb);
6293 if (intel_fb->obj == obj) {
6294 if (!intel_crtc->busy) {
6295 /* Non-busy -> busy, upclock */
3dec0095 6296 intel_increase_pllclock(crtc);
652c393a
JB		 6297 intel_crtc->busy = true;
6298 } else {
6299 /* Busy -> busy, put off timer */
6300 mod_timer(&intel_crtc->idle_timer, jiffies +
6301 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6302 }
6303 }
6304 }
6305}
6306
79e53945
JB		 6307static void intel_crtc_destroy(struct drm_crtc *crtc)
6308{
6309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6310 struct drm_device *dev = crtc->dev;
6311 struct intel_unpin_work *work;
6312 unsigned long flags;
6313
6314 spin_lock_irqsave(&dev->event_lock, flags);
6315 work = intel_crtc->unpin_work;
6316 intel_crtc->unpin_work = NULL;
6317 spin_unlock_irqrestore(&dev->event_lock, flags);
6318
6319 if (work) {
6320 cancel_work_sync(&work->work);
6321 kfree(work);
6322 }
79e53945
JB		 6323
6324 drm_crtc_cleanup(crtc);
67e77c5a 6325
79e53945
JB		 6326 kfree(intel_crtc);
6327}
6328
6b95a207
KH		 6329static void intel_unpin_work_fn(struct work_struct *__work)
6330{
6331 struct intel_unpin_work *work =
6332 container_of(__work, struct intel_unpin_work, work);
6333
6334 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6335 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6336 drm_gem_object_unreference(&work->pending_flip_obj->base);
6337 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6338
6b95a207
KH		 6339 mutex_unlock(&work->dev->struct_mutex);
6340 kfree(work);
6341}
6342
1afe3e9d 6343static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6344 struct drm_crtc *crtc)
6b95a207
KH		 6345{
6346 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 struct intel_unpin_work *work;
05394f39 6349 struct drm_i915_gem_object *obj;
6b95a207 6350 struct drm_pending_vblank_event *e;
49b14a5c 6351 struct timeval tnow, tvbl;
6b95a207
KH		 6352 unsigned long flags;
6353
6354 /* Ignore early vblank irqs */
6355 if (intel_crtc == NULL)
6356 return;
6357
49b14a5c
MK		 6358 do_gettimeofday(&tnow);
6359
6b95a207
KH		 6360 spin_lock_irqsave(&dev->event_lock, flags);
6361 work = intel_crtc->unpin_work;
6362 if (work == NULL || !work->pending) {
6363 spin_unlock_irqrestore(&dev->event_lock, flags);
6364 return;
6365 }
6366
6367 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6368
6369 if (work->event) {
6370 e = work->event;
49b14a5c 6371 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6372
6373 /* Called before vblank count and timestamps have
6374 * been updated for the vblank interval of flip
6375 * completion? Need to increment vblank count and
6376 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6377 * to account for this. We assume this happened if we
6378 * get called over 0.9 frame durations after the last
6379 * timestamped vblank.
6380 *
6381 * This calculation can not be used with vrefresh rates
6382 * below 5Hz (10Hz to be on the safe side) without
6383 * promoting to 64 integers.
0af7e4df 6384 */
49b14a5c
MK		 6385 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6386 9 * crtc->framedur_ns) {
0af7e4df 6387 e->event.sequence++;
49b14a5c
MK		 6388 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6389 crtc->framedur_ns);
0af7e4df
MK		 6390 }
6391
49b14a5c
MK		 6392 e->event.tv_sec = tvbl.tv_sec;
6393 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6394
6b95a207
KH		 6395 list_add_tail(&e->base.link,
6396 &e->base.file_priv->event_list);
6397 wake_up_interruptible(&e->base.file_priv->event_wait);
6398 }
6399
0af7e4df
MK		 6400 drm_vblank_put(dev, intel_crtc->pipe);
6401
6b95a207
KH		 6402 spin_unlock_irqrestore(&dev->event_lock, flags);
6403
05394f39 6404 obj = work->old_fb_obj;
d9e86c0e 6405
e59f2bac 6406 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6407 &obj->pending_flip.counter);
6408 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6409 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6410
6b95a207 6411 schedule_work(&work->work);
e5510fac
JB		 6412
6413 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6414}
6415
1afe3e9d
JB		 6416void intel_finish_page_flip(struct drm_device *dev, int pipe)
6417{
6418 drm_i915_private_t *dev_priv = dev->dev_private;
6419 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6420
49b14a5c 6421 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6422}
6423
6424void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6425{
6426 drm_i915_private_t *dev_priv = dev->dev_private;
6427 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6428
49b14a5c 6429 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6430}
6431
6b95a207
KH		 6432void intel_prepare_page_flip(struct drm_device *dev, int plane)
6433{
6434 drm_i915_private_t *dev_priv = dev->dev_private;
6435 struct intel_crtc *intel_crtc =
6436 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6437 unsigned long flags;
6438
6439 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6440 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6441 if ((++intel_crtc->unpin_work->pending) > 1)
6442 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6443 } else {
6444 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6445 }
6b95a207
KH		 6446 spin_unlock_irqrestore(&dev->event_lock, flags);
6447}
6448
8c9f3aaf
JB		 6449static int intel_gen2_queue_flip(struct drm_device *dev,
6450 struct drm_crtc *crtc,
6451 struct drm_framebuffer *fb,
6452 struct drm_i915_gem_object *obj)
6453{
6454 struct drm_i915_private *dev_priv = dev->dev_private;
6455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6456 unsigned long offset;
6457 u32 flip_mask;
6458 int ret;
6459
6460 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6461 if (ret)
6462 goto out;
6463
6464 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6465 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6466
6467 ret = BEGIN_LP_RING(6);
6468 if (ret)
6469 goto out;
6470
6471 /* Can't queue multiple flips, so wait for the previous
6472 * one to finish before executing the next.
6473 */
6474 if (intel_crtc->plane)
6475 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6476 else
6477 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6478 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6479 OUT_RING(MI_NOOP);
6480 OUT_RING(MI_DISPLAY_FLIP |
6481 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6482 OUT_RING(fb->pitch);
6483 OUT_RING(obj->gtt_offset + offset);
6484 OUT_RING(MI_NOOP);
6485 ADVANCE_LP_RING();
6486out:
6487 return ret;
6488}
6489
6490static int intel_gen3_queue_flip(struct drm_device *dev,
6491 struct drm_crtc *crtc,
6492 struct drm_framebuffer *fb,
6493 struct drm_i915_gem_object *obj)
6494{
6495 struct drm_i915_private *dev_priv = dev->dev_private;
6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497 unsigned long offset;
6498 u32 flip_mask;
6499 int ret;
6500
6501 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6502 if (ret)
6503 goto out;
6504
6505 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6506 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6507
6508 ret = BEGIN_LP_RING(6);
6509 if (ret)
6510 goto out;
6511
6512 if (intel_crtc->plane)
6513 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6514 else
6515 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6516 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6517 OUT_RING(MI_NOOP);
6518 OUT_RING(MI_DISPLAY_FLIP_I915 |
6519 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6520 OUT_RING(fb->pitch);
6521 OUT_RING(obj->gtt_offset + offset);
6522 OUT_RING(MI_NOOP);
6523
6524 ADVANCE_LP_RING();
6525out:
6526 return ret;
6527}
6528
6529static int intel_gen4_queue_flip(struct drm_device *dev,
6530 struct drm_crtc *crtc,
6531 struct drm_framebuffer *fb,
6532 struct drm_i915_gem_object *obj)
6533{
6534 struct drm_i915_private *dev_priv = dev->dev_private;
6535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6536 uint32_t pf, pipesrc;
6537 int ret;
6538
6539 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6540 if (ret)
6541 goto out;
6542
6543 ret = BEGIN_LP_RING(4);
6544 if (ret)
6545 goto out;
6546
6547 /* i965+ uses the linear or tiled offsets from the
6548 * Display Registers (which do not change across a page-flip)
6549 * so we need only reprogram the base address.
6550 */
6551 OUT_RING(MI_DISPLAY_FLIP |
6552 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6553 OUT_RING(fb->pitch);
6554 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6555
6556 /* XXX Enabling the panel-fitter across page-flip is so far
6557 * untested on non-native modes, so ignore it for now.
6558 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6559 */
6560 pf = 0;
6561 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6562 OUT_RING(pf | pipesrc);
6563 ADVANCE_LP_RING();
6564out:
6565 return ret;
6566}
6567
6568static int intel_gen6_queue_flip(struct drm_device *dev,
6569 struct drm_crtc *crtc,
6570 struct drm_framebuffer *fb,
6571 struct drm_i915_gem_object *obj)
6572{
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575 uint32_t pf, pipesrc;
6576 int ret;
6577
6578 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6579 if (ret)
6580 goto out;
6581
6582 ret = BEGIN_LP_RING(4);
6583 if (ret)
6584 goto out;
6585
6586 OUT_RING(MI_DISPLAY_FLIP |
6587 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6588 OUT_RING(fb->pitch | obj->tiling_mode);
6589 OUT_RING(obj->gtt_offset);
6590
6591 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6592 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6593 OUT_RING(pf | pipesrc);
6594 ADVANCE_LP_RING();
6595out:
6596 return ret;
6597}
6598
7c9017e5
JB		 6599/*
6600 * On gen7 we currently use the blit ring because (in early silicon at least)
6601 * the render ring doesn't give us interrpts for page flip completion, which
6602 * means clients will hang after the first flip is queued. Fortunately the
6603 * blit ring generates interrupts properly, so use it instead.
6604 */
6605static int intel_gen7_queue_flip(struct drm_device *dev,
6606 struct drm_crtc *crtc,
6607 struct drm_framebuffer *fb,
6608 struct drm_i915_gem_object *obj)
6609{
6610 struct drm_i915_private *dev_priv = dev->dev_private;
6611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6613 int ret;
6614
6615 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6616 if (ret)
6617 goto out;
6618
6619 ret = intel_ring_begin(ring, 4);
6620 if (ret)
6621 goto out;
6622
6623 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6624 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6625 intel_ring_emit(ring, (obj->gtt_offset));
6626 intel_ring_emit(ring, (MI_NOOP));
6627 intel_ring_advance(ring);
6628out:
6629 return ret;
6630}
6631
8c9f3aaf
JB		 6632static int intel_default_queue_flip(struct drm_device *dev,
6633 struct drm_crtc *crtc,
6634 struct drm_framebuffer *fb,
6635 struct drm_i915_gem_object *obj)
6636{
6637 return -ENODEV;
6638}
6639
6b95a207
KH		 6640static int intel_crtc_page_flip(struct drm_crtc *crtc,
6641 struct drm_framebuffer *fb,
6642 struct drm_pending_vblank_event *event)
6643{
6644 struct drm_device *dev = crtc->dev;
6645 struct drm_i915_private *dev_priv = dev->dev_private;
6646 struct intel_framebuffer *intel_fb;
05394f39 6647 struct drm_i915_gem_object *obj;
6b95a207
KH		 6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 struct intel_unpin_work *work;
8c9f3aaf 6650 unsigned long flags;
52e68630 6651 int ret;
6b95a207
KH		 6652
6653 work = kzalloc(sizeof *work, GFP_KERNEL);
6654 if (work == NULL)
6655 return -ENOMEM;
6656
6b95a207
KH		 6657 work->event = event;
6658 work->dev = crtc->dev;
6659 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6660 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6661 INIT_WORK(&work->work, intel_unpin_work_fn);
6662
6663 /* We borrow the event spin lock for protecting unpin_work */
6664 spin_lock_irqsave(&dev->event_lock, flags);
6665 if (intel_crtc->unpin_work) {
6666 spin_unlock_irqrestore(&dev->event_lock, flags);
6667 kfree(work);
468f0b44
CW		 6668
6669 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6670 return -EBUSY;
6671 }
6672 intel_crtc->unpin_work = work;
6673 spin_unlock_irqrestore(&dev->event_lock, flags);
6674
6675 intel_fb = to_intel_framebuffer(fb);
6676 obj = intel_fb->obj;
6677
468f0b44 6678 mutex_lock(&dev->struct_mutex);
6b95a207 6679
75dfca80 6680 /* Reference the objects for the scheduled work. */
05394f39
CW		 6681 drm_gem_object_reference(&work->old_fb_obj->base);
6682 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6683
6684 crtc->fb = fb;
96b099fd
CW		 6685
6686 ret = drm_vblank_get(dev, intel_crtc->pipe);
6687 if (ret)
6688 goto cleanup_objs;
6689
e1f99ce6 6690 work->pending_flip_obj = obj;
e1f99ce6 6691
4e5359cd
SF		 6692 work->enable_stall_check = true;
6693
e1f99ce6
CW		 6694 /* Block clients from rendering to the new back buffer until
6695 * the flip occurs and the object is no longer visible.
6696 */
05394f39 6697 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6698
8c9f3aaf
JB		 6699 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6700 if (ret)
6701 goto cleanup_pending;
6b95a207
KH		 6702
6703 mutex_unlock(&dev->struct_mutex);
6704
e5510fac
JB		 6705 trace_i915_flip_request(intel_crtc->plane, obj);
6706
6b95a207 6707 return 0;
96b099fd 6708
8c9f3aaf
JB		 6709cleanup_pending:
6710 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6711cleanup_objs:
05394f39
CW		 6712 drm_gem_object_unreference(&work->old_fb_obj->base);
6713 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6714 mutex_unlock(&dev->struct_mutex);
6715
6716 spin_lock_irqsave(&dev->event_lock, flags);
6717 intel_crtc->unpin_work = NULL;
6718 spin_unlock_irqrestore(&dev->event_lock, flags);
6719
6720 kfree(work);
6721
6722 return ret;
6b95a207
KH		 6723}
6724
47f1c6c9
CW		 6725static void intel_sanitize_modesetting(struct drm_device *dev,
6726 int pipe, int plane)
6727{
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 u32 reg, val;
6730
6731 if (HAS_PCH_SPLIT(dev))
6732 return;
6733
6734 /* Who knows what state these registers were left in by the BIOS or
6735 * grub?
6736 *
6737 * If we leave the registers in a conflicting state (e.g. with the
6738 * display plane reading from the other pipe than the one we intend
6739 * to use) then when we attempt to teardown the active mode, we will
6740 * not disable the pipes and planes in the correct order -- leaving
6741 * a plane reading from a disabled pipe and possibly leading to
6742 * undefined behaviour.
6743 */
6744
6745 reg = DSPCNTR(plane);
6746 val = I915_READ(reg);
6747
6748 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6749 return;
6750 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6751 return;
6752
6753 /* This display plane is active and attached to the other CPU pipe. */
6754 pipe = !pipe;
6755
6756 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6757 intel_disable_plane(dev_priv, plane, pipe);
6758 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6759}
79e53945 6760
f6e5b160
CW		 6761static void intel_crtc_reset(struct drm_crtc *crtc)
6762{
6763 struct drm_device *dev = crtc->dev;
6764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6765
6766 /* Reset flags back to the 'unknown' status so that they
6767 * will be correctly set on the initial modeset.
6768 */
6769 intel_crtc->dpms_mode = -1;
6770
6771 /* We need to fix up any BIOS configuration that conflicts with
6772 * our expectations.
6773 */
6774 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6775}
6776
6777static struct drm_crtc_helper_funcs intel_helper_funcs = {
6778 .dpms = intel_crtc_dpms,
6779 .mode_fixup = intel_crtc_mode_fixup,
6780 .mode_set = intel_crtc_mode_set,
6781 .mode_set_base = intel_pipe_set_base,
6782 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6783 .load_lut = intel_crtc_load_lut,
6784 .disable = intel_crtc_disable,
6785};
6786
6787static const struct drm_crtc_funcs intel_crtc_funcs = {
6788 .reset = intel_crtc_reset,
6789 .cursor_set = intel_crtc_cursor_set,
6790 .cursor_move = intel_crtc_cursor_move,
6791 .gamma_set = intel_crtc_gamma_set,
6792 .set_config = drm_crtc_helper_set_config,
6793 .destroy = intel_crtc_destroy,
6794 .page_flip = intel_crtc_page_flip,
6795};
6796
b358d0a6 6797static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6798{
22fd0fab 6799 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6800 struct intel_crtc *intel_crtc;
6801 int i;
6802
6803 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6804 if (intel_crtc == NULL)
6805 return;
6806
6807 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6808
6809 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6810 for (i = 0; i < 256; i++) {
6811 intel_crtc->lut_r[i] = i;
6812 intel_crtc->lut_g[i] = i;
6813 intel_crtc->lut_b[i] = i;
6814 }
6815
80824003
JB		 6816 /* Swap pipes & planes for FBC on pre-965 */
6817 intel_crtc->pipe = pipe;
6818 intel_crtc->plane = pipe;
e2e767ab 6819 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6820 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6821 intel_crtc->plane = !pipe;
80824003
JB		 6822 }
6823
22fd0fab
JB		 6824 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6825 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6826 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6827 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6828
5d1d0cc8 6829 intel_crtc_reset(&intel_crtc->base);
04dbff52 6830 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6831 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6832
6833 if (HAS_PCH_SPLIT(dev)) {
6834 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6835 intel_helper_funcs.commit = ironlake_crtc_commit;
6836 } else {
6837 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6838 intel_helper_funcs.commit = i9xx_crtc_commit;
6839 }
6840
79e53945
JB		 6841 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6842
652c393a
JB		 6843 intel_crtc->busy = false;
6844
6845 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6846 (unsigned long)intel_crtc);
79e53945
JB		 6847}
6848
08d7b3d1 6849int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6850 struct drm_file *file)
08d7b3d1
CW		 6851{
6852 drm_i915_private_t *dev_priv = dev->dev_private;
6853 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6854 struct drm_mode_object *drmmode_obj;
6855 struct intel_crtc *crtc;
08d7b3d1
CW		 6856
6857 if (!dev_priv) {
6858 DRM_ERROR("called with no initialization\n");
6859 return -EINVAL;
6860 }
6861
c05422d5
DV		 6862 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6863 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6864
c05422d5 6865 if (!drmmode_obj) {
08d7b3d1
CW		 6866 DRM_ERROR("no such CRTC id\n");
6867 return -EINVAL;
6868 }
6869
c05422d5
DV		 6870 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6871 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6872
c05422d5 6873 return 0;
08d7b3d1
CW		 6874}
6875
c5e4df33 6876static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6877{
4ef69c7a 6878 struct intel_encoder *encoder;
79e53945 6879 int index_mask = 0;
79e53945
JB		 6880 int entry = 0;
6881
4ef69c7a
CW		 6882 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6883 if (type_mask & encoder->clone_mask)
79e53945
JB		 6884 index_mask |= (1 << entry);
6885 entry++;
6886 }
4ef69c7a 6887
79e53945
JB		 6888 return index_mask;
6889}
6890
4d302442
CW		 6891static bool has_edp_a(struct drm_device *dev)
6892{
6893 struct drm_i915_private *dev_priv = dev->dev_private;
6894
6895 if (!IS_MOBILE(dev))
6896 return false;
6897
6898 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6899 return false;
6900
6901 if (IS_GEN5(dev) &&
6902 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6903 return false;
6904
6905 return true;
6906}
6907
79e53945
JB		 6908static void intel_setup_outputs(struct drm_device *dev)
6909{
725e30ad 6910 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6911 struct intel_encoder *encoder;
cb0953d7 6912 bool dpd_is_edp = false;
c5d1b51d 6913 bool has_lvds = false;
79e53945 6914
541998a1 6915 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6916 has_lvds = intel_lvds_init(dev);
6917 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6918 /* disable the panel fitter on everything but LVDS */
6919 I915_WRITE(PFIT_CONTROL, 0);
6920 }
79e53945 6921
bad720ff 6922 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6923 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6924
4d302442 6925 if (has_edp_a(dev))
32f9d658
ZW		 6926 intel_dp_init(dev, DP_A);
6927
cb0953d7
AJ		 6928 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6929 intel_dp_init(dev, PCH_DP_D);
6930 }
6931
6932 intel_crt_init(dev);
6933
6934 if (HAS_PCH_SPLIT(dev)) {
6935 int found;
6936
30ad48b7 6937 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6938 /* PCH SDVOB multiplex with HDMIB */
6939 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6940 if (!found)
6941 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6942 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6943 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6944 }
6945
6946 if (I915_READ(HDMIC) & PORT_DETECTED)
6947 intel_hdmi_init(dev, HDMIC);
6948
6949 if (I915_READ(HDMID) & PORT_DETECTED)
6950 intel_hdmi_init(dev, HDMID);
6951
5eb08b69
ZW		 6952 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6953 intel_dp_init(dev, PCH_DP_C);
6954
cb0953d7 6955 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6956 intel_dp_init(dev, PCH_DP_D);
6957
103a196f 6958 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6959 bool found = false;
7d57382e 6960
725e30ad 6961 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6962 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6963 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6964 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6965 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6966 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6967 }
27185ae1 6968
b01f2c3a
JB		 6969 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6970 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6971 intel_dp_init(dev, DP_B);
b01f2c3a 6972 }
725e30ad 6973 }
13520b05
KH		 6974
6975 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6976
b01f2c3a
JB		 6977 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6978 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6979 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6980 }
27185ae1
ML		 6981
6982 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6983
b01f2c3a
JB		 6984 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6985 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6986 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6987 }
6988 if (SUPPORTS_INTEGRATED_DP(dev)) {
6989 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6990 intel_dp_init(dev, DP_C);
b01f2c3a 6991 }
725e30ad 6992 }
27185ae1 6993
b01f2c3a
JB		 6994 if (SUPPORTS_INTEGRATED_DP(dev) &&
6995 (I915_READ(DP_D) & DP_DETECTED)) {
6996 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6997 intel_dp_init(dev, DP_D);
b01f2c3a 6998 }
bad720ff 6999 } else if (IS_GEN2(dev))
79e53945
JB		 7000 intel_dvo_init(dev);
7001
103a196f 7002 if (SUPPORTS_TV(dev))
79e53945
JB		 7003 intel_tv_init(dev);
7004
4ef69c7a
CW		 7005 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7006 encoder->base.possible_crtcs = encoder->crtc_mask;
7007 encoder->base.possible_clones =
7008 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7009 }
47356eb6
CW		 7010
7011 intel_panel_setup_backlight(dev);
2c7111db
CW		 7012
7013 /* disable all the possible outputs/crtcs before entering KMS mode */
7014 drm_helper_disable_unused_functions(dev);
79e53945
JB		 7015}
7016
7017static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7018{
7019 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7020
7021 drm_framebuffer_cleanup(fb);
05394f39 7022 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7023
7024 kfree(intel_fb);
7025}
7026
7027static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7028 struct drm_file *file,
79e53945
JB		 7029 unsigned int *handle)
7030{
7031 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7032 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7033
05394f39 7034 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7035}
7036
7037static const struct drm_framebuffer_funcs intel_fb_funcs = {
7038 .destroy = intel_user_framebuffer_destroy,
7039 .create_handle = intel_user_framebuffer_create_handle,
7040};
7041
38651674
DA		 7042int intel_framebuffer_init(struct drm_device *dev,
7043 struct intel_framebuffer *intel_fb,
7044 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7045 struct drm_i915_gem_object *obj)
79e53945 7046{
79e53945
JB		 7047 int ret;
7048
05394f39 7049 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7050 return -EINVAL;
7051
7052 if (mode_cmd->pitch & 63)
7053 return -EINVAL;
7054
7055 switch (mode_cmd->bpp) {
7056 case 8:
7057 case 16:
b5626747
JB		 7058 /* Only pre-ILK can handle 5:5:5 */
7059 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7060 return -EINVAL;
7061 break;
7062
57cd6508
CW		 7063 case 24:
7064 case 32:
7065 break;
7066 default:
7067 return -EINVAL;
7068 }
7069
79e53945
JB		 7070 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7071 if (ret) {
7072 DRM_ERROR("framebuffer init failed %d\n", ret);
7073 return ret;
7074 }
7075
7076 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7077 intel_fb->obj = obj;
79e53945
JB		 7078 return 0;
7079}
7080
79e53945
JB		 7081static struct drm_framebuffer *
7082intel_user_framebuffer_create(struct drm_device *dev,
7083 struct drm_file *filp,
7084 struct drm_mode_fb_cmd *mode_cmd)
7085{
05394f39 7086 struct drm_i915_gem_object *obj;
79e53945 7087
05394f39 7088 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7089 if (&obj->base == NULL)
cce13ff7 7090 return ERR_PTR(-ENOENT);
79e53945 7091
d2dff872 7092 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7093}
7094
79e53945 7095static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7096 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7097 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7098};
7099
05394f39 7100static struct drm_i915_gem_object *
aa40d6bb 7101intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7102{
05394f39 7103 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7104 int ret;
7105
2c34b850
BW		 7106 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7107
aa40d6bb
ZN		 7108 ctx = i915_gem_alloc_object(dev, 4096);
7109 if (!ctx) {
9ea8d059
CW		 7110 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7111 return NULL;
7112 }
7113
75e9e915 7114 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7115 if (ret) {
7116 DRM_ERROR("failed to pin power context: %d\n", ret);
7117 goto err_unref;
7118 }
7119
aa40d6bb 7120 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7121 if (ret) {
7122 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7123 goto err_unpin;
7124 }
9ea8d059 7125
aa40d6bb 7126 return ctx;
9ea8d059
CW		 7127
7128err_unpin:
aa40d6bb 7129 i915_gem_object_unpin(ctx);
9ea8d059 7130err_unref:
05394f39 7131 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7132 mutex_unlock(&dev->struct_mutex);
7133 return NULL;
7134}
7135
7648fa99
JB		 7136bool ironlake_set_drps(struct drm_device *dev, u8 val)
7137{
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 u16 rgvswctl;
7140
7141 rgvswctl = I915_READ16(MEMSWCTL);
7142 if (rgvswctl & MEMCTL_CMD_STS) {
7143 DRM_DEBUG("gpu busy, RCS change rejected\n");
7144 return false; /* still busy with another command */
7145 }
7146
7147 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7148 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7149 I915_WRITE16(MEMSWCTL, rgvswctl);
7150 POSTING_READ16(MEMSWCTL);
7151
7152 rgvswctl |= MEMCTL_CMD_STS;
7153 I915_WRITE16(MEMSWCTL, rgvswctl);
7154
7155 return true;
7156}
7157
f97108d1
JB		 7158void ironlake_enable_drps(struct drm_device *dev)
7159{
7160 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7161 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7162 u8 fmax, fmin, fstart, vstart;
f97108d1 7163
ea056c14
JB		 7164 /* Enable temp reporting */
7165 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7166 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7167
f97108d1
JB		 7168 /* 100ms RC evaluation intervals */
7169 I915_WRITE(RCUPEI, 100000);
7170 I915_WRITE(RCDNEI, 100000);
7171
7172 /* Set max/min thresholds to 90ms and 80ms respectively */
7173 I915_WRITE(RCBMAXAVG, 90000);
7174 I915_WRITE(RCBMINAVG, 80000);
7175
7176 I915_WRITE(MEMIHYST, 1);
7177
7178 /* Set up min, max, and cur for interrupt handling */
7179 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7180 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7181 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7182 MEMMODE_FSTART_SHIFT;
7648fa99 7183
f97108d1
JB		 7184 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7185 PXVFREQ_PX_SHIFT;
7186
80dbf4b7 7187 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7188 dev_priv->fstart = fstart;
7189
80dbf4b7 7190 dev_priv->max_delay = fstart;
f97108d1
JB		 7191 dev_priv->min_delay = fmin;
7192 dev_priv->cur_delay = fstart;
7193
80dbf4b7
JB		 7194 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7195 fmax, fmin, fstart);
7648fa99 7196
f97108d1
JB		 7197 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7198
7199 /*
7200 * Interrupts will be enabled in ironlake_irq_postinstall
7201 */
7202
7203 I915_WRITE(VIDSTART, vstart);
7204 POSTING_READ(VIDSTART);
7205
7206 rgvmodectl |= MEMMODE_SWMODE_EN;
7207 I915_WRITE(MEMMODECTL, rgvmodectl);
7208
481b6af3 7209 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7210 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7211 msleep(1);
7212
7648fa99 7213 ironlake_set_drps(dev, fstart);
f97108d1 7214
7648fa99
JB		 7215 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7216 I915_READ(0x112e0);
7217 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7218 dev_priv->last_count2 = I915_READ(0x112f4);
7219 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7220}
7221
7222void ironlake_disable_drps(struct drm_device *dev)
7223{
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7225 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7226
7227 /* Ack interrupts, disable EFC interrupt */
7228 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7229 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7230 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7231 I915_WRITE(DEIIR, DE_PCU_EVENT);
7232 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7233
7234 /* Go back to the starting frequency */
7648fa99 7235 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7236 msleep(1);
7237 rgvswctl |= MEMCTL_CMD_STS;
7238 I915_WRITE(MEMSWCTL, rgvswctl);
7239 msleep(1);
7240
7241}
7242
3b8d8d91
JB		 7243void gen6_set_rps(struct drm_device *dev, u8 val)
7244{
7245 struct drm_i915_private *dev_priv = dev->dev_private;
7246 u32 swreq;
7247
7248 swreq = (val & 0x3ff) << 25;
7249 I915_WRITE(GEN6_RPNSWREQ, swreq);
7250}
7251
7252void gen6_disable_rps(struct drm_device *dev)
7253{
7254 struct drm_i915_private *dev_priv = dev->dev_private;
7255
7256 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7257 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7258 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7259
7260 spin_lock_irq(&dev_priv->rps_lock);
7261 dev_priv->pm_iir = 0;
7262 spin_unlock_irq(&dev_priv->rps_lock);
7263
3b8d8d91
JB		 7264 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7265}
7266
7648fa99
JB		 7267static unsigned long intel_pxfreq(u32 vidfreq)
7268{
7269 unsigned long freq;
7270 int div = (vidfreq & 0x3f0000) >> 16;
7271 int post = (vidfreq & 0x3000) >> 12;
7272 int pre = (vidfreq & 0x7);
7273
7274 if (!pre)
7275 return 0;
7276
7277 freq = ((div * 133333) / ((1<<post) * pre));
7278
7279 return freq;
7280}
7281
7282void intel_init_emon(struct drm_device *dev)
7283{
7284 struct drm_i915_private *dev_priv = dev->dev_private;
7285 u32 lcfuse;
7286 u8 pxw[16];
7287 int i;
7288
7289 /* Disable to program */
7290 I915_WRITE(ECR, 0);
7291 POSTING_READ(ECR);
7292
7293 /* Program energy weights for various events */
7294 I915_WRITE(SDEW, 0x15040d00);
7295 I915_WRITE(CSIEW0, 0x007f0000);
7296 I915_WRITE(CSIEW1, 0x1e220004);
7297 I915_WRITE(CSIEW2, 0x04000004);
7298
7299 for (i = 0; i < 5; i++)
7300 I915_WRITE(PEW + (i * 4), 0);
7301 for (i = 0; i < 3; i++)
7302 I915_WRITE(DEW + (i * 4), 0);
7303
7304 /* Program P-state weights to account for frequency power adjustment */
7305 for (i = 0; i < 16; i++) {
7306 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7307 unsigned long freq = intel_pxfreq(pxvidfreq);
7308 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7309 PXVFREQ_PX_SHIFT;
7310 unsigned long val;
7311
7312 val = vid * vid;
7313 val *= (freq / 1000);
7314 val *= 255;
7315 val /= (127*127*900);
7316 if (val > 0xff)
7317 DRM_ERROR("bad pxval: %ld\n", val);
7318 pxw[i] = val;
7319 }
7320 /* Render standby states get 0 weight */
7321 pxw[14] = 0;
7322 pxw[15] = 0;
7323
7324 for (i = 0; i < 4; i++) {
7325 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7326 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7327 I915_WRITE(PXW + (i * 4), val);
7328 }
7329
7330 /* Adjust magic regs to magic values (more experimental results) */
7331 I915_WRITE(OGW0, 0);
7332 I915_WRITE(OGW1, 0);
7333 I915_WRITE(EG0, 0x00007f00);
7334 I915_WRITE(EG1, 0x0000000e);
7335 I915_WRITE(EG2, 0x000e0000);
7336 I915_WRITE(EG3, 0x68000300);
7337 I915_WRITE(EG4, 0x42000000);
7338 I915_WRITE(EG5, 0x00140031);
7339 I915_WRITE(EG6, 0);
7340 I915_WRITE(EG7, 0);
7341
7342 for (i = 0; i < 8; i++)
7343 I915_WRITE(PXWL + (i * 4), 0);
7344
7345 /* Enable PMON + select events */
7346 I915_WRITE(ECR, 0x80000019);
7347
7348 lcfuse = I915_READ(LCFUSE02);
7349
7350 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7351}
7352
3b8d8d91 7353void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7354{
a6044e23
JB		 7355 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7356 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7357 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7358 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7359 int i;
7360
7361 /* Here begins a magic sequence of register writes to enable
7362 * auto-downclocking.
7363 *
7364 * Perhaps there might be some value in exposing these to
7365 * userspace...
7366 */
7367 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7368 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7369 gen6_gt_force_wake_get(dev_priv);
8fd26859 7370
3b8d8d91 7371 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7372 I915_WRITE(GEN6_RC_CONTROL, 0);
7373
7374 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7375 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7376 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7377 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7378 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7379
7380 for (i = 0; i < I915_NUM_RINGS; i++)
7381 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7382
7383 I915_WRITE(GEN6_RC_SLEEP, 0);
7384 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7385 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7386 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7387 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7388
7df8721b
JB		 7389 if (i915_enable_rc6)
7390 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7391 GEN6_RC_CTL_RC6_ENABLE;
7392
8fd26859 7393 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7394 rc6_mask |
9c3d2f7f 7395 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7396 GEN6_RC_CTL_HW_ENABLE);
7397
3b8d8d91 7398 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7399 GEN6_FREQUENCY(10) |
7400 GEN6_OFFSET(0) |
7401 GEN6_AGGRESSIVE_TURBO);
7402 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7403 GEN6_FREQUENCY(12));
7404
7405 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7406 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7407 18 << 24 |
7408 6 << 16);
ccab5c82
JB		 7409 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7410 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7411 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7412 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7413 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7414 I915_WRITE(GEN6_RP_CONTROL,
7415 GEN6_RP_MEDIA_TURBO |
7416 GEN6_RP_USE_NORMAL_FREQ |
7417 GEN6_RP_MEDIA_IS_GFX |
7418 GEN6_RP_ENABLE |
ccab5c82
JB		 7419 GEN6_RP_UP_BUSY_AVG |
7420 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7421
7422 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7423 500))
7424 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7425
7426 I915_WRITE(GEN6_PCODE_DATA, 0);
7427 I915_WRITE(GEN6_PCODE_MAILBOX,
7428 GEN6_PCODE_READY |
7429 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7430 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7431 500))
7432 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7433
a6044e23
JB		 7434 min_freq = (rp_state_cap & 0xff0000) >> 16;
7435 max_freq = rp_state_cap & 0xff;
7436 cur_freq = (gt_perf_status & 0xff00) >> 8;
7437
7438 /* Check for overclock support */
7439 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7440 500))
7441 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7442 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7443 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7444 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7445 500))
7446 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7447 if (pcu_mbox & (1<<31)) { /* OC supported */
7448 max_freq = pcu_mbox & 0xff;
e281fcaa 7449 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7450 }
7451
7452 /* In units of 100MHz */
7453 dev_priv->max_delay = max_freq;
7454 dev_priv->min_delay = min_freq;
7455 dev_priv->cur_delay = cur_freq;
7456
8fd26859
CW		 7457 /* requires MSI enabled */
7458 I915_WRITE(GEN6_PMIER,
7459 GEN6_PM_MBOX_EVENT |
7460 GEN6_PM_THERMAL_EVENT |
7461 GEN6_PM_RP_DOWN_TIMEOUT |
7462 GEN6_PM_RP_UP_THRESHOLD |
7463 GEN6_PM_RP_DOWN_THRESHOLD |
7464 GEN6_PM_RP_UP_EI_EXPIRED |
7465 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7466 spin_lock_irq(&dev_priv->rps_lock);
7467 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7468 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7469 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7470 /* enable all PM interrupts */
7471 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7472
fcca7926 7473 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7474 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7475}
7476
23b2f8bb
JB		 7477void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7478{
7479 int min_freq = 15;
7480 int gpu_freq, ia_freq, max_ia_freq;
7481 int scaling_factor = 180;
7482
7483 max_ia_freq = cpufreq_quick_get_max(0);
7484 /*
7485 * Default to measured freq if none found, PCU will ensure we don't go
7486 * over
7487 */
7488 if (!max_ia_freq)
7489 max_ia_freq = tsc_khz;
7490
7491 /* Convert from kHz to MHz */
7492 max_ia_freq /= 1000;
7493
7494 mutex_lock(&dev_priv->dev->struct_mutex);
7495
7496 /*
7497 * For each potential GPU frequency, load a ring frequency we'd like
7498 * to use for memory access. We do this by specifying the IA frequency
7499 * the PCU should use as a reference to determine the ring frequency.
7500 */
7501 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7502 gpu_freq--) {
7503 int diff = dev_priv->max_delay - gpu_freq;
7504
7505 /*
7506 * For GPU frequencies less than 750MHz, just use the lowest
7507 * ring freq.
7508 */
7509 if (gpu_freq < min_freq)
7510 ia_freq = 800;
7511 else
7512 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7513 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7514
7515 I915_WRITE(GEN6_PCODE_DATA,
7516 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7517 gpu_freq);
7518 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7519 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7520 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7521 GEN6_PCODE_READY) == 0, 10)) {
7522 DRM_ERROR("pcode write of freq table timed out\n");
7523 continue;
7524 }
7525 }
7526
7527 mutex_unlock(&dev_priv->dev->struct_mutex);
7528}
7529
6067aaea
JB		 7530static void ironlake_init_clock_gating(struct drm_device *dev)
7531{
7532 struct drm_i915_private *dev_priv = dev->dev_private;
7533 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7534
7535 /* Required for FBC */
7536 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7537 DPFCRUNIT_CLOCK_GATE_DISABLE |
7538 DPFDUNIT_CLOCK_GATE_DISABLE;
7539 /* Required for CxSR */
7540 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7541
7542 I915_WRITE(PCH_3DCGDIS0,
7543 MARIUNIT_CLOCK_GATE_DISABLE |
7544 SVSMUNIT_CLOCK_GATE_DISABLE);
7545 I915_WRITE(PCH_3DCGDIS1,
7546 VFMUNIT_CLOCK_GATE_DISABLE);
7547
7548 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7549
6067aaea
JB		 7550 /*
7551 * According to the spec the following bits should be set in
7552 * order to enable memory self-refresh
7553 * The bit 22/21 of 0x42004
7554 * The bit 5 of 0x42020
7555 * The bit 15 of 0x45000
7556 */
7557 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7558 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7559 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7560 I915_WRITE(ILK_DSPCLK_GATE,
7561 (I915_READ(ILK_DSPCLK_GATE) |
7562 ILK_DPARB_CLK_GATE));
7563 I915_WRITE(DISP_ARB_CTL,
7564 (I915_READ(DISP_ARB_CTL) |
7565 DISP_FBC_WM_DIS));
7566 I915_WRITE(WM3_LP_ILK, 0);
7567 I915_WRITE(WM2_LP_ILK, 0);
7568 I915_WRITE(WM1_LP_ILK, 0);
7569
7570 /*
7571 * Based on the document from hardware guys the following bits
7572 * should be set unconditionally in order to enable FBC.
7573 * The bit 22 of 0x42000
7574 * The bit 22 of 0x42004
7575 * The bit 7,8,9 of 0x42020.
7576 */
7577 if (IS_IRONLAKE_M(dev)) {
7578 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7579 I915_READ(ILK_DISPLAY_CHICKEN1) |
7580 ILK_FBCQ_DIS);
7581 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7582 I915_READ(ILK_DISPLAY_CHICKEN2) |
7583 ILK_DPARB_GATE);
7584 I915_WRITE(ILK_DSPCLK_GATE,
7585 I915_READ(ILK_DSPCLK_GATE) |
7586 ILK_DPFC_DIS1 |
7587 ILK_DPFC_DIS2 |
7588 ILK_CLK_FBC);
7589 }
7590
7591 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7592 I915_READ(ILK_DISPLAY_CHICKEN2) |
7593 ILK_ELPIN_409_SELECT);
7594 I915_WRITE(_3D_CHICKEN2,
7595 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7596 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7597}
7598
6067aaea 7599static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7600{
7601 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7602 int pipe;
6067aaea
JB		 7603 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7604
7605 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7606
6067aaea
JB		 7607 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7608 I915_READ(ILK_DISPLAY_CHICKEN2) |
7609 ILK_ELPIN_409_SELECT);
8956c8bb 7610
6067aaea
JB		 7611 I915_WRITE(WM3_LP_ILK, 0);
7612 I915_WRITE(WM2_LP_ILK, 0);
7613 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7614
7615 /*
6067aaea
JB		 7616 * According to the spec the following bits should be
7617 * set in order to enable memory self-refresh and fbc:
7618 * The bit21 and bit22 of 0x42000
7619 * The bit21 and bit22 of 0x42004
7620 * The bit5 and bit7 of 0x42020
7621 * The bit14 of 0x70180
7622 * The bit14 of 0x71180
652c393a 7623 */
6067aaea
JB		 7624 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7625 I915_READ(ILK_DISPLAY_CHICKEN1) |
7626 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7627 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7628 I915_READ(ILK_DISPLAY_CHICKEN2) |
7629 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7630 I915_WRITE(ILK_DSPCLK_GATE,
7631 I915_READ(ILK_DSPCLK_GATE) |
7632 ILK_DPARB_CLK_GATE |
7633 ILK_DPFD_CLK_GATE);
8956c8bb 7634
6067aaea
JB		 7635 for_each_pipe(pipe)
7636 I915_WRITE(DSPCNTR(pipe),
7637 I915_READ(DSPCNTR(pipe)) |
7638 DISPPLANE_TRICKLE_FEED_DISABLE);
7639}
8956c8bb 7640
28963a3e
JB		 7641static void ivybridge_init_clock_gating(struct drm_device *dev)
7642{
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7644 int pipe;
7645 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7646
28963a3e 7647 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7648
28963a3e
JB		 7649 I915_WRITE(WM3_LP_ILK, 0);
7650 I915_WRITE(WM2_LP_ILK, 0);
7651 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7652
28963a3e 7653 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7654
28963a3e
JB		 7655 for_each_pipe(pipe)
7656 I915_WRITE(DSPCNTR(pipe),
7657 I915_READ(DSPCNTR(pipe)) |
7658 DISPPLANE_TRICKLE_FEED_DISABLE);
7659}
7660
6067aaea
JB		 7661static void g4x_init_clock_gating(struct drm_device *dev)
7662{
7663 struct drm_i915_private *dev_priv = dev->dev_private;
7664 uint32_t dspclk_gate;
8fd26859 7665
6067aaea
JB		 7666 I915_WRITE(RENCLK_GATE_D1, 0);
7667 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7668 GS_UNIT_CLOCK_GATE_DISABLE |
7669 CL_UNIT_CLOCK_GATE_DISABLE);
7670 I915_WRITE(RAMCLK_GATE_D, 0);
7671 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7672 OVRUNIT_CLOCK_GATE_DISABLE |
7673 OVCUNIT_CLOCK_GATE_DISABLE;
7674 if (IS_GM45(dev))
7675 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7676 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7677}
1398261a 7678
6067aaea
JB		 7679static void crestline_init_clock_gating(struct drm_device *dev)
7680{
7681 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7682
6067aaea
JB		 7683 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7684 I915_WRITE(RENCLK_GATE_D2, 0);
7685 I915_WRITE(DSPCLK_GATE_D, 0);
7686 I915_WRITE(RAMCLK_GATE_D, 0);
7687 I915_WRITE16(DEUC, 0);
7688}
652c393a 7689
6067aaea
JB		 7690static void broadwater_init_clock_gating(struct drm_device *dev)
7691{
7692 struct drm_i915_private *dev_priv = dev->dev_private;
7693
7694 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7695 I965_RCC_CLOCK_GATE_DISABLE |
7696 I965_RCPB_CLOCK_GATE_DISABLE |
7697 I965_ISC_CLOCK_GATE_DISABLE |
7698 I965_FBC_CLOCK_GATE_DISABLE);
7699 I915_WRITE(RENCLK_GATE_D2, 0);
7700}
7701
7702static void gen3_init_clock_gating(struct drm_device *dev)
7703{
7704 struct drm_i915_private *dev_priv = dev->dev_private;
7705 u32 dstate = I915_READ(D_STATE);
7706
7707 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7708 DSTATE_DOT_CLOCK_GATING;
7709 I915_WRITE(D_STATE, dstate);
7710}
7711
7712static void i85x_init_clock_gating(struct drm_device *dev)
7713{
7714 struct drm_i915_private *dev_priv = dev->dev_private;
7715
7716 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7717}
7718
7719static void i830_init_clock_gating(struct drm_device *dev)
7720{
7721 struct drm_i915_private *dev_priv = dev->dev_private;
7722
7723 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7724}
7725
645c62a5
JB		 7726static void ibx_init_clock_gating(struct drm_device *dev)
7727{
7728 struct drm_i915_private *dev_priv = dev->dev_private;
7729
7730 /*
7731 * On Ibex Peak and Cougar Point, we need to disable clock
7732 * gating for the panel power sequencer or it will fail to
7733 * start up when no ports are active.
7734 */
7735 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7736}
7737
7738static void cpt_init_clock_gating(struct drm_device *dev)
7739{
7740 struct drm_i915_private *dev_priv = dev->dev_private;
7741
7742 /*
7743 * On Ibex Peak and Cougar Point, we need to disable clock
7744 * gating for the panel power sequencer or it will fail to
7745 * start up when no ports are active.
7746 */
7747 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7748 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7749 DPLS_EDP_PPS_FIX_DIS);
652c393a
JB		 7750}
7751
ac668088 7752static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7753{
7754 struct drm_i915_private *dev_priv = dev->dev_private;
7755
7756 if (dev_priv->renderctx) {
ac668088
CW		 7757 i915_gem_object_unpin(dev_priv->renderctx);
7758 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7759 dev_priv->renderctx = NULL;
7760 }
7761
7762 if (dev_priv->pwrctx) {
ac668088
CW		 7763 i915_gem_object_unpin(dev_priv->pwrctx);
7764 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7765 dev_priv->pwrctx = NULL;
7766 }
7767}
7768
7769static void ironlake_disable_rc6(struct drm_device *dev)
7770{
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772
7773 if (I915_READ(PWRCTXA)) {
7774 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7775 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7776 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7777 50);
0cdab21f
CW		 7778
7779 I915_WRITE(PWRCTXA, 0);
7780 POSTING_READ(PWRCTXA);
7781
ac668088
CW		 7782 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7783 POSTING_READ(RSTDBYCTL);
0cdab21f 7784 }
ac668088 7785
99507307 7786 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7787}
7788
ac668088 7789static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7790{
7791 struct drm_i915_private *dev_priv = dev->dev_private;
7792
ac668088
CW		 7793 if (dev_priv->renderctx == NULL)
7794 dev_priv->renderctx = intel_alloc_context_page(dev);
7795 if (!dev_priv->renderctx)
7796 return -ENOMEM;
7797
7798 if (dev_priv->pwrctx == NULL)
7799 dev_priv->pwrctx = intel_alloc_context_page(dev);
7800 if (!dev_priv->pwrctx) {
7801 ironlake_teardown_rc6(dev);
7802 return -ENOMEM;
7803 }
7804
7805 return 0;
d5bb081b
JB		 7806}
7807
7808void ironlake_enable_rc6(struct drm_device *dev)
7809{
7810 struct drm_i915_private *dev_priv = dev->dev_private;
7811 int ret;
7812
ac668088
CW		 7813 /* rc6 disabled by default due to repeated reports of hanging during
7814 * boot and resume.
7815 */
7816 if (!i915_enable_rc6)
7817 return;
7818
2c34b850 7819 mutex_lock(&dev->struct_mutex);
ac668088 7820 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7821 if (ret) {
7822 mutex_unlock(&dev->struct_mutex);
ac668088 7823 return;
2c34b850 7824 }
ac668088 7825
d5bb081b
JB		 7826 /*
7827 * GPU can automatically power down the render unit if given a page
7828 * to save state.
7829 */
7830 ret = BEGIN_LP_RING(6);
7831 if (ret) {
ac668088 7832 ironlake_teardown_rc6(dev);
2c34b850 7833 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7834 return;
7835 }
ac668088 7836
d5bb081b
JB		 7837 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7838 OUT_RING(MI_SET_CONTEXT);
7839 OUT_RING(dev_priv->renderctx->gtt_offset |
7840 MI_MM_SPACE_GTT |
7841 MI_SAVE_EXT_STATE_EN |
7842 MI_RESTORE_EXT_STATE_EN |
7843 MI_RESTORE_INHIBIT);
7844 OUT_RING(MI_SUSPEND_FLUSH);
7845 OUT_RING(MI_NOOP);
7846 OUT_RING(MI_FLUSH);
7847 ADVANCE_LP_RING();
7848
4a246cfc
BW		 7849 /*
7850 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7851 * does an implicit flush, combined with MI_FLUSH above, it should be
7852 * safe to assume that renderctx is valid
7853 */
7854 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7855 if (ret) {
7856 DRM_ERROR("failed to enable ironlake power power savings\n");
7857 ironlake_teardown_rc6(dev);
7858 mutex_unlock(&dev->struct_mutex);
7859 return;
7860 }
7861
d5bb081b
JB		 7862 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7863 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7864 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7865}
7866
645c62a5
JB		 7867void intel_init_clock_gating(struct drm_device *dev)
7868{
7869 struct drm_i915_private *dev_priv = dev->dev_private;
7870
7871 dev_priv->display.init_clock_gating(dev);
7872
7873 if (dev_priv->display.init_pch_clock_gating)
7874 dev_priv->display.init_pch_clock_gating(dev);
7875}
ac668088 7876
e70236a8
JB		 7877/* Set up chip specific display functions */
7878static void intel_init_display(struct drm_device *dev)
7879{
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881
7882 /* We always want a DPMS function */
f564048e 7883 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7884 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 7885 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 7886 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7887 } else {
e70236a8 7888 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 7889 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 7890 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7891 }
e70236a8 7892
ee5382ae 7893 if (I915_HAS_FBC(dev)) {
9c04f015 7894 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7895 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7896 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7897 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7898 } else if (IS_GM45(dev)) {
74dff282
JB		 7899 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7900 dev_priv->display.enable_fbc = g4x_enable_fbc;
7901 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7902 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7903 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7904 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7905 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7906 }
74dff282 7907 /* 855GM needs testing */
e70236a8
JB		 7908 }
7909
7910 /* Returns the core display clock speed */
f2b115e6 7911 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7912 dev_priv->display.get_display_clock_speed =
7913 i945_get_display_clock_speed;
7914 else if (IS_I915G(dev))
7915 dev_priv->display.get_display_clock_speed =
7916 i915_get_display_clock_speed;
f2b115e6 7917 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7918 dev_priv->display.get_display_clock_speed =
7919 i9xx_misc_get_display_clock_speed;
7920 else if (IS_I915GM(dev))
7921 dev_priv->display.get_display_clock_speed =
7922 i915gm_get_display_clock_speed;
7923 else if (IS_I865G(dev))
7924 dev_priv->display.get_display_clock_speed =
7925 i865_get_display_clock_speed;
f0f8a9ce 7926 else if (IS_I85X(dev))
e70236a8
JB		 7927 dev_priv->display.get_display_clock_speed =
7928 i855_get_display_clock_speed;
7929 else /* 852, 830 */
7930 dev_priv->display.get_display_clock_speed =
7931 i830_get_display_clock_speed;
7932
7933 /* For FIFO watermark updates */
7f8a8569 7934 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7935 if (HAS_PCH_IBX(dev))
7936 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7937 else if (HAS_PCH_CPT(dev))
7938 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7939
f00a3ddf 7940 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7941 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7942 dev_priv->display.update_wm = ironlake_update_wm;
7943 else {
7944 DRM_DEBUG_KMS("Failed to get proper latency. "
7945 "Disable CxSR\n");
7946 dev_priv->display.update_wm = NULL;
1398261a 7947 }
674cf967 7948 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7949 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7950 } else if (IS_GEN6(dev)) {
7951 if (SNB_READ_WM0_LATENCY()) {
7952 dev_priv->display.update_wm = sandybridge_update_wm;
7953 } else {
7954 DRM_DEBUG_KMS("Failed to read display plane latency. "
7955 "Disable CxSR\n");
7956 dev_priv->display.update_wm = NULL;
7f8a8569 7957 }
674cf967 7958 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7959 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7960 } else if (IS_IVYBRIDGE(dev)) {
7961 /* FIXME: detect B0+ stepping and use auto training */
7962 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7963 if (SNB_READ_WM0_LATENCY()) {
7964 dev_priv->display.update_wm = sandybridge_update_wm;
7965 } else {
7966 DRM_DEBUG_KMS("Failed to read display plane latency. "
7967 "Disable CxSR\n");
7968 dev_priv->display.update_wm = NULL;
7969 }
28963a3e 7970 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7971
7f8a8569
ZW		 7972 } else
7973 dev_priv->display.update_wm = NULL;
7974 } else if (IS_PINEVIEW(dev)) {
d4294342 7975 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7976 dev_priv->is_ddr3,
d4294342
ZY		 7977 dev_priv->fsb_freq,
7978 dev_priv->mem_freq)) {
7979 DRM_INFO("failed to find known CxSR latency "
95534263 7980 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7981 "disabling CxSR\n",
95534263 7982 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7983 dev_priv->fsb_freq, dev_priv->mem_freq);
7984 /* Disable CxSR and never update its watermark again */
7985 pineview_disable_cxsr(dev);
7986 dev_priv->display.update_wm = NULL;
7987 } else
7988 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7989 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7990 } else if (IS_G4X(dev)) {
e70236a8 7991 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7992 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7993 } else if (IS_GEN4(dev)) {
e70236a8 7994 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7995 if (IS_CRESTLINE(dev))
7996 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7997 else if (IS_BROADWATER(dev))
7998 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7999 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8000 dev_priv->display.update_wm = i9xx_update_wm;
8001 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8002 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8003 } else if (IS_I865G(dev)) {
8004 dev_priv->display.update_wm = i830_update_wm;
8005 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8006 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8007 } else if (IS_I85X(dev)) {
8008 dev_priv->display.update_wm = i9xx_update_wm;
8009 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8010 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8011 } else {
8f4695ed 8012 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8013 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8014 if (IS_845G(dev))
e70236a8
JB		 8015 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8016 else
8017 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8018 }
8c9f3aaf
JB		 8019
8020 /* Default just returns -ENODEV to indicate unsupported */
8021 dev_priv->display.queue_flip = intel_default_queue_flip;
8022
8023 switch (INTEL_INFO(dev)->gen) {
8024 case 2:
8025 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8026 break;
8027
8028 case 3:
8029 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8030 break;
8031
8032 case 4:
8033 case 5:
8034 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8035 break;
8036
8037 case 6:
8038 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8039 break;
7c9017e5
JB		 8040 case 7:
8041 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8042 break;
8c9f3aaf 8043 }
e70236a8
JB		 8044}
8045
b690e96c
JB		 8046/*
8047 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8048 * resume, or other times. This quirk makes sure that's the case for
8049 * affected systems.
8050 */
8051static void quirk_pipea_force (struct drm_device *dev)
8052{
8053 struct drm_i915_private *dev_priv = dev->dev_private;
8054
8055 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8056 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8057}
8058
8059struct intel_quirk {
8060 int device;
8061 int subsystem_vendor;
8062 int subsystem_device;
8063 void (*hook)(struct drm_device *dev);
8064};
8065
8066struct intel_quirk intel_quirks[] = {
8067 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8068 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8069 /* HP Mini needs pipe A force quirk (LP: #322104) */
8070 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8071
8072 /* Thinkpad R31 needs pipe A force quirk */
8073 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8074 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8075 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8076
8077 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8078 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8079 /* ThinkPad X40 needs pipe A force quirk */
8080
8081 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8082 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8083
8084 /* 855 & before need to leave pipe A & dpll A up */
8085 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8086 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8087};
8088
8089static void intel_init_quirks(struct drm_device *dev)
8090{
8091 struct pci_dev *d = dev->pdev;
8092 int i;
8093
8094 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8095 struct intel_quirk *q = &intel_quirks[i];
8096
8097 if (d->device == q->device &&
8098 (d->subsystem_vendor == q->subsystem_vendor ||
8099 q->subsystem_vendor == PCI_ANY_ID) &&
8100 (d->subsystem_device == q->subsystem_device ||
8101 q->subsystem_device == PCI_ANY_ID))
8102 q->hook(dev);
8103 }
8104}
8105
9cce37f4
JB		 8106/* Disable the VGA plane that we never use */
8107static void i915_disable_vga(struct drm_device *dev)
8108{
8109 struct drm_i915_private *dev_priv = dev->dev_private;
8110 u8 sr1;
8111 u32 vga_reg;
8112
8113 if (HAS_PCH_SPLIT(dev))
8114 vga_reg = CPU_VGACNTRL;
8115 else
8116 vga_reg = VGACNTRL;
8117
8118 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8119 outb(1, VGA_SR_INDEX);
8120 sr1 = inb(VGA_SR_DATA);
8121 outb(sr1 | 1<<5, VGA_SR_DATA);
8122 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8123 udelay(300);
8124
8125 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8126 POSTING_READ(vga_reg);
8127}
8128
79e53945
JB		 8129void intel_modeset_init(struct drm_device *dev)
8130{
652c393a 8131 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8132 int i;
8133
8134 drm_mode_config_init(dev);
8135
8136 dev->mode_config.min_width = 0;
8137 dev->mode_config.min_height = 0;
8138
8139 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8140
b690e96c
JB		 8141 intel_init_quirks(dev);
8142
e70236a8
JB		 8143 intel_init_display(dev);
8144
a6c45cf0
CW		 8145 if (IS_GEN2(dev)) {
8146 dev->mode_config.max_width = 2048;
8147 dev->mode_config.max_height = 2048;
8148 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8149 dev->mode_config.max_width = 4096;
8150 dev->mode_config.max_height = 4096;
79e53945 8151 } else {
a6c45cf0
CW		 8152 dev->mode_config.max_width = 8192;
8153 dev->mode_config.max_height = 8192;
79e53945 8154 }
35c3047a 8155 dev->mode_config.fb_base = dev->agp->base;
79e53945 8156
28c97730 8157 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8158 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8159
a3524f1b 8160 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8161 intel_crtc_init(dev, i);
8162 }
8163
9cce37f4
JB		 8164 /* Just disable it once at startup */
8165 i915_disable_vga(dev);
79e53945 8166 intel_setup_outputs(dev);
652c393a 8167
645c62a5 8168 intel_init_clock_gating(dev);
9cce37f4 8169
7648fa99 8170 if (IS_IRONLAKE_M(dev)) {
f97108d1 8171 ironlake_enable_drps(dev);
7648fa99
JB		 8172 intel_init_emon(dev);
8173 }
f97108d1 8174
1c70c0ce 8175 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8176 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8177 gen6_update_ring_freq(dev_priv);
8178 }
3b8d8d91 8179
652c393a
JB		 8180 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8181 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8182 (unsigned long)dev);
2c7111db
CW		 8183}
8184
8185void intel_modeset_gem_init(struct drm_device *dev)
8186{
8187 if (IS_IRONLAKE_M(dev))
8188 ironlake_enable_rc6(dev);
02e792fb
DV		 8189
8190 intel_setup_overlay(dev);
79e53945
JB		 8191}
8192
8193void intel_modeset_cleanup(struct drm_device *dev)
8194{
652c393a
JB		 8195 struct drm_i915_private *dev_priv = dev->dev_private;
8196 struct drm_crtc *crtc;
8197 struct intel_crtc *intel_crtc;
8198
f87ea761 8199 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8200 mutex_lock(&dev->struct_mutex);
8201
723bfd70
JB		 8202 intel_unregister_dsm_handler();
8203
8204
652c393a
JB		 8205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8206 /* Skip inactive CRTCs */
8207 if (!crtc->fb)
8208 continue;
8209
8210 intel_crtc = to_intel_crtc(crtc);
3dec0095 8211 intel_increase_pllclock(crtc);
652c393a
JB		 8212 }
8213
973d04f9 8214 intel_disable_fbc(dev);
e70236a8 8215
f97108d1
JB		 8216 if (IS_IRONLAKE_M(dev))
8217 ironlake_disable_drps(dev);
1c70c0ce 8218 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8219 gen6_disable_rps(dev);
f97108d1 8220
d5bb081b
JB		 8221 if (IS_IRONLAKE_M(dev))
8222 ironlake_disable_rc6(dev);
0cdab21f 8223
69341a5e
KH		 8224 mutex_unlock(&dev->struct_mutex);
8225
6c0d9350
DV		 8226 /* Disable the irq before mode object teardown, for the irq might
8227 * enqueue unpin/hotplug work. */
8228 drm_irq_uninstall(dev);
8229 cancel_work_sync(&dev_priv->hotplug_work);
8230
3dec0095
DV		 8231 /* Shut off idle work before the crtcs get freed. */
8232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8233 intel_crtc = to_intel_crtc(crtc);
8234 del_timer_sync(&intel_crtc->idle_timer);
8235 }
8236 del_timer_sync(&dev_priv->idle_timer);
8237 cancel_work_sync(&dev_priv->idle_work);
8238
79e53945
JB		 8239 drm_mode_config_cleanup(dev);
8240}
8241
f1c79df3
ZW		 8242/*
8243 * Return which encoder is currently attached for connector.
8244 */
df0e9248 8245struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8246{
df0e9248
CW		 8247 return &intel_attached_encoder(connector)->base;
8248}
f1c79df3 8249
df0e9248
CW		 8250void intel_connector_attach_encoder(struct intel_connector *connector,
8251 struct intel_encoder *encoder)
8252{
8253 connector->encoder = encoder;
8254 drm_mode_connector_attach_encoder(&connector->base,
8255 &encoder->base);
79e53945 8256}
28d52043
DA		 8257
8258/*
8259 * set vga decode state - true == enable VGA decode
8260 */
8261int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8262{
8263 struct drm_i915_private *dev_priv = dev->dev_private;
8264 u16 gmch_ctrl;
8265
8266 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8267 if (state)
8268 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8269 else
8270 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8271 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8272 return 0;
8273}
c4a1d9e4
CW		 8274
8275#ifdef CONFIG_DEBUG_FS
8276#include <linux/seq_file.h>
8277
8278struct intel_display_error_state {
8279 struct intel_cursor_error_state {
8280 u32 control;
8281 u32 position;
8282 u32 base;
8283 u32 size;
8284 } cursor[2];
8285
8286 struct intel_pipe_error_state {
8287 u32 conf;
8288 u32 source;
8289
8290 u32 htotal;
8291 u32 hblank;
8292 u32 hsync;
8293 u32 vtotal;
8294 u32 vblank;
8295 u32 vsync;
8296 } pipe[2];
8297
8298 struct intel_plane_error_state {
8299 u32 control;
8300 u32 stride;
8301 u32 size;
8302 u32 pos;
8303 u32 addr;
8304 u32 surface;
8305 u32 tile_offset;
8306 } plane[2];
8307};
8308
8309struct intel_display_error_state *
8310intel_display_capture_error_state(struct drm_device *dev)
8311{
8312 drm_i915_private_t *dev_priv = dev->dev_private;
8313 struct intel_display_error_state *error;
8314 int i;
8315
8316 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8317 if (error == NULL)
8318 return NULL;
8319
8320 for (i = 0; i < 2; i++) {
8321 error->cursor[i].control = I915_READ(CURCNTR(i));
8322 error->cursor[i].position = I915_READ(CURPOS(i));
8323 error->cursor[i].base = I915_READ(CURBASE(i));
8324
8325 error->plane[i].control = I915_READ(DSPCNTR(i));
8326 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8327 error->plane[i].size = I915_READ(DSPSIZE(i));
8328 error->plane[i].pos= I915_READ(DSPPOS(i));
8329 error->plane[i].addr = I915_READ(DSPADDR(i));
8330 if (INTEL_INFO(dev)->gen >= 4) {
8331 error->plane[i].surface = I915_READ(DSPSURF(i));
8332 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8333 }
8334
8335 error->pipe[i].conf = I915_READ(PIPECONF(i));
8336 error->pipe[i].source = I915_READ(PIPESRC(i));
8337 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8338 error->pipe[i].hblank = I915_READ(HBLANK(i));
8339 error->pipe[i].hsync = I915_READ(HSYNC(i));
8340 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8341 error->pipe[i].vblank = I915_READ(VBLANK(i));
8342 error->pipe[i].vsync = I915_READ(VSYNC(i));
8343 }
8344
8345 return error;
8346}
8347
8348void
8349intel_display_print_error_state(struct seq_file *m,
8350 struct drm_device *dev,
8351 struct intel_display_error_state *error)
8352{
8353 int i;
8354
8355 for (i = 0; i < 2; i++) {
8356 seq_printf(m, "Pipe [%d]:\n", i);
8357 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8358 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8359 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8360 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8361 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8362 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8363 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8364 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8365
8366 seq_printf(m, "Plane [%d]:\n", i);
8367 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8368 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8369 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8370 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8371 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8372 if (INTEL_INFO(dev)->gen >= 4) {
8373 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8374 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8375 }
8376
8377 seq_printf(m, "Cursor [%d]:\n", i);
8378 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8379 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8380 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8381 }
8382}
8383#endif
Linux kernel - Deliverables
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