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drm/i915: Always try to inherit the initial fb.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
043e9bda 115static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 116
79e53945 117typedef struct {
0206e353 118 int min, max;
79e53945
JB		 119} intel_range_t;
120
121typedef struct {
0206e353
AJ		 122 int dot_limit;
123 int p2_slow, p2_fast;
79e53945
JB		 124} intel_p2_t;
125
d4906093
ML		 126typedef struct intel_limit intel_limit_t;
127struct intel_limit {
0206e353
AJ		 128 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_p2_t p2;
d4906093 130};
79e53945 131
d2acd215
DV		 132int
133intel_pch_rawclk(struct drm_device *dev)
134{
135 struct drm_i915_private *dev_priv = dev->dev_private;
136
137 WARN_ON(!HAS_PCH_SPLIT(dev));
138
139 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
140}
141
79e50a4f
JN		 142/* hrawclock is 1/4 the FSB frequency */
143int intel_hrawclk(struct drm_device *dev)
144{
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 uint32_t clkcfg;
147
148 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
149 if (IS_VALLEYVIEW(dev))
150 return 200;
151
152 clkcfg = I915_READ(CLKCFG);
153 switch (clkcfg & CLKCFG_FSB_MASK) {
154 case CLKCFG_FSB_400:
155 return 100;
156 case CLKCFG_FSB_533:
157 return 133;
158 case CLKCFG_FSB_667:
159 return 166;
160 case CLKCFG_FSB_800:
161 return 200;
162 case CLKCFG_FSB_1067:
163 return 266;
164 case CLKCFG_FSB_1333:
165 return 333;
166 /* these two are just a guess; one of them might be right */
167 case CLKCFG_FSB_1600:
168 case CLKCFG_FSB_1600_ALT:
169 return 400;
170 default:
171 return 133;
172 }
173}
174
021357ac
CW		 175static inline u32 /* units of 100MHz */
176intel_fdi_link_freq(struct drm_device *dev)
177{
8b99e68c
CW		 178 if (IS_GEN5(dev)) {
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
181 } else
182 return 27;
021357ac
CW		 183}
184
5d536e28 185static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 196};
197
5d536e28
DV		 198static const intel_limit_t intel_limits_i8xx_dvo = {
199 .dot = { .min = 25000, .max = 350000 },
9c333719 200 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 201 .n = { .min = 2, .max = 16 },
5d536e28
DV		 202 .m = { .min = 96, .max = 140 },
203 .m1 = { .min = 18, .max = 26 },
204 .m2 = { .min = 6, .max = 16 },
205 .p = { .min = 4, .max = 128 },
206 .p1 = { .min = 2, .max = 33 },
207 .p2 = { .dot_limit = 165000,
208 .p2_slow = 4, .p2_fast = 4 },
209};
210
e4b36699 211static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 212 .dot = { .min = 25000, .max = 350000 },
9c333719 213 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 214 .n = { .min = 2, .max = 16 },
0206e353
AJ		 215 .m = { .min = 96, .max = 140 },
216 .m1 = { .min = 18, .max = 26 },
217 .m2 = { .min = 6, .max = 16 },
218 .p = { .min = 4, .max = 128 },
219 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 220 .p2 = { .dot_limit = 165000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699 222};
273e27ca 223
e4b36699 224static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 225 .dot = { .min = 20000, .max = 400000 },
226 .vco = { .min = 1400000, .max = 2800000 },
227 .n = { .min = 1, .max = 6 },
228 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 229 .m1 = { .min = 8, .max = 18 },
230 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 231 .p = { .min = 5, .max = 80 },
232 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 233 .p2 = { .dot_limit = 200000,
234 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 238 .dot = { .min = 20000, .max = 400000 },
239 .vco = { .min = 1400000, .max = 2800000 },
240 .n = { .min = 1, .max = 6 },
241 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 242 .m1 = { .min = 8, .max = 18 },
243 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 244 .p = { .min = 7, .max = 98 },
245 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 246 .p2 = { .dot_limit = 112000,
247 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 248};
249
273e27ca 250
e4b36699 251static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 252 .dot = { .min = 25000, .max = 270000 },
253 .vco = { .min = 1750000, .max = 3500000},
254 .n = { .min = 1, .max = 4 },
255 .m = { .min = 104, .max = 138 },
256 .m1 = { .min = 17, .max = 23 },
257 .m2 = { .min = 5, .max = 11 },
258 .p = { .min = 10, .max = 30 },
259 .p1 = { .min = 1, .max = 3},
260 .p2 = { .dot_limit = 270000,
261 .p2_slow = 10,
262 .p2_fast = 10
044c7c41 263 },
e4b36699
KP		 264};
265
266static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 267 .dot = { .min = 22000, .max = 400000 },
268 .vco = { .min = 1750000, .max = 3500000},
269 .n = { .min = 1, .max = 4 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 16, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 5, .max = 80 },
274 .p1 = { .min = 1, .max = 8},
275 .p2 = { .dot_limit = 165000,
276 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 277};
278
279static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 280 .dot = { .min = 20000, .max = 115000 },
281 .vco = { .min = 1750000, .max = 3500000 },
282 .n = { .min = 1, .max = 3 },
283 .m = { .min = 104, .max = 138 },
284 .m1 = { .min = 17, .max = 23 },
285 .m2 = { .min = 5, .max = 11 },
286 .p = { .min = 28, .max = 112 },
287 .p1 = { .min = 2, .max = 8 },
288 .p2 = { .dot_limit = 0,
289 .p2_slow = 14, .p2_fast = 14
044c7c41 290 },
e4b36699
KP		 291};
292
293static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 294 .dot = { .min = 80000, .max = 224000 },
295 .vco = { .min = 1750000, .max = 3500000 },
296 .n = { .min = 1, .max = 3 },
297 .m = { .min = 104, .max = 138 },
298 .m1 = { .min = 17, .max = 23 },
299 .m2 = { .min = 5, .max = 11 },
300 .p = { .min = 14, .max = 42 },
301 .p1 = { .min = 2, .max = 6 },
302 .p2 = { .dot_limit = 0,
303 .p2_slow = 7, .p2_fast = 7
044c7c41 304 },
e4b36699
KP		 305};
306
f2b115e6 307static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 308 .dot = { .min = 20000, .max = 400000},
309 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 310 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 311 .n = { .min = 3, .max = 6 },
312 .m = { .min = 2, .max = 256 },
273e27ca 313 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 314 .m1 = { .min = 0, .max = 0 },
315 .m2 = { .min = 0, .max = 254 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 318 .p2 = { .dot_limit = 200000,
319 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 320};
321
f2b115e6 322static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 323 .dot = { .min = 20000, .max = 400000 },
324 .vco = { .min = 1700000, .max = 3500000 },
325 .n = { .min = 3, .max = 6 },
326 .m = { .min = 2, .max = 256 },
327 .m1 = { .min = 0, .max = 0 },
328 .m2 = { .min = 0, .max = 254 },
329 .p = { .min = 7, .max = 112 },
330 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 331 .p2 = { .dot_limit = 112000,
332 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 333};
334
273e27ca
EA		 335/* Ironlake / Sandybridge
336 *
337 * We calculate clock using (register_value + 2) for N/M1/M2, so here
338 * the range value for them is (actual_value - 2).
339 */
b91ad0ec 340static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 5 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 5, .max = 80 },
348 .p1 = { .min = 1, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 351};
352
b91ad0ec 353static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 118 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 364};
365
366static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 127 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 56 },
374 .p1 = { .min = 2, .max = 8 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 377};
378
273e27ca 379/* LVDS 100mhz refclk limits. */
b91ad0ec 380static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 381 .dot = { .min = 25000, .max = 350000 },
382 .vco = { .min = 1760000, .max = 3510000 },
383 .n = { .min = 1, .max = 2 },
384 .m = { .min = 79, .max = 126 },
385 .m1 = { .min = 12, .max = 22 },
386 .m2 = { .min = 5, .max = 9 },
387 .p = { .min = 28, .max = 112 },
0206e353 388 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 389 .p2 = { .dot_limit = 225000,
390 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 391};
392
393static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 394 .dot = { .min = 25000, .max = 350000 },
395 .vco = { .min = 1760000, .max = 3510000 },
396 .n = { .min = 1, .max = 3 },
397 .m = { .min = 79, .max = 126 },
398 .m1 = { .min = 12, .max = 22 },
399 .m2 = { .min = 5, .max = 9 },
400 .p = { .min = 14, .max = 42 },
0206e353 401 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 402 .p2 = { .dot_limit = 225000,
403 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 404};
405
dc730512 406static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 407 /*
408 * These are the data rate limits (measured in fast clocks)
409 * since those are the strictest limits we have. The fast
410 * clock and actual rate limits are more relaxed, so checking
411 * them would make no difference.
412 */
413 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 414 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 415 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 416 .m1 = { .min = 2, .max = 3 },
417 .m2 = { .min = 11, .max = 156 },
b99ab663 418 .p1 = { .min = 2, .max = 3 },
5fdc9c49 419 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 420};
421
ef9348c8
CML		 422static const intel_limit_t intel_limits_chv = {
423 /*
424 * These are the data rate limits (measured in fast clocks)
425 * since those are the strictest limits we have. The fast
426 * clock and actual rate limits are more relaxed, so checking
427 * them would make no difference.
428 */
429 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 430 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 431 .n = { .min = 1, .max = 1 },
432 .m1 = { .min = 2, .max = 2 },
433 .m2 = { .min = 24 << 22, .max = 175 << 22 },
434 .p1 = { .min = 2, .max = 4 },
435 .p2 = { .p2_slow = 1, .p2_fast = 14 },
436};
437
5ab7b0b7
ID		 438static const intel_limit_t intel_limits_bxt = {
439 /* FIXME: find real dot limits */
440 .dot = { .min = 0, .max = INT_MAX },
e6292556 441 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 442 .n = { .min = 1, .max = 1 },
443 .m1 = { .min = 2, .max = 2 },
444 /* FIXME: find real m2 limits */
445 .m2 = { .min = 2 << 22, .max = 255 << 22 },
446 .p1 = { .min = 2, .max = 4 },
447 .p2 = { .p2_slow = 1, .p2_fast = 20 },
448};
449
cdba954e
ACO		 450static bool
451needs_modeset(struct drm_crtc_state *state)
452{
fc596660 453 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 454}
455
e0638cdf
PZ		 456/**
457 * Returns whether any output on the specified pipe is of the specified type
458 */
4093561b 459bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 460{
409ee761 461 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 462 struct intel_encoder *encoder;
463
409ee761 464 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 465 if (encoder->type == type)
466 return true;
467
468 return false;
469}
470
d0737e1d
ACO		 471/**
472 * Returns whether any output on the specified pipe will have the specified
473 * type after a staged modeset is complete, i.e., the same as
474 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
475 * encoder->crtc.
476 */
a93e255f
ACO		 477static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
478 int type)
d0737e1d 479{
a93e255f 480 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 481 struct drm_connector *connector;
a93e255f 482 struct drm_connector_state *connector_state;
d0737e1d 483 struct intel_encoder *encoder;
a93e255f
ACO		 484 int i, num_connectors = 0;
485
da3ced29 486 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 487 if (connector_state->crtc != crtc_state->base.crtc)
488 continue;
489
490 num_connectors++;
d0737e1d 491
a93e255f
ACO		 492 encoder = to_intel_encoder(connector_state->best_encoder);
493 if (encoder->type == type)
d0737e1d 494 return true;
a93e255f
ACO		 495 }
496
497 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 498
499 return false;
500}
501
a93e255f
ACO		 502static const intel_limit_t *
503intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 504{
a93e255f 505 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 506 const intel_limit_t *limit;
b91ad0ec 507
a93e255f 508 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev)) {
1b894b59 510 if (refclk == 100000)
b91ad0ec
ZW		 511 limit = &intel_limits_ironlake_dual_lvds_100m;
512 else
513 limit = &intel_limits_ironlake_dual_lvds;
514 } else {
1b894b59 515 if (refclk == 100000)
b91ad0ec
ZW		 516 limit = &intel_limits_ironlake_single_lvds_100m;
517 else
518 limit = &intel_limits_ironlake_single_lvds;
519 }
c6bb3538 520 } else
b91ad0ec 521 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 530 const intel_limit_t *limit;
531
a93e255f 532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 533 if (intel_is_dual_link_lvds(dev))
e4b36699 534 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 535 else
e4b36699 536 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 537 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
538 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 539 limit = &intel_limits_g4x_hdmi;
a93e255f 540 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 541 limit = &intel_limits_g4x_sdvo;
044c7c41 542 } else /* The option is for other outputs */
e4b36699 543 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 544
545 return limit;
546}
547
a93e255f
ACO		 548static const intel_limit_t *
549intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 550{
a93e255f 551 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 552 const intel_limit_t *limit;
553
5ab7b0b7
ID		 554 if (IS_BROXTON(dev))
555 limit = &intel_limits_bxt;
556 else if (HAS_PCH_SPLIT(dev))
a93e255f 557 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 558 else if (IS_G4X(dev)) {
a93e255f 559 limit = intel_g4x_limit(crtc_state);
f2b115e6 560 } else if (IS_PINEVIEW(dev)) {
a93e255f 561 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 562 limit = &intel_limits_pineview_lvds;
2177832f 563 else
f2b115e6 564 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 565 } else if (IS_CHERRYVIEW(dev)) {
566 limit = &intel_limits_chv;
a0c4da24 567 } else if (IS_VALLEYVIEW(dev)) {
dc730512 568 limit = &intel_limits_vlv;
a6c45cf0 569 } else if (!IS_GEN2(dev)) {
a93e255f 570 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 571 limit = &intel_limits_i9xx_lvds;
572 else
573 limit = &intel_limits_i9xx_sdvo;
79e53945 574 } else {
a93e255f 575 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 576 limit = &intel_limits_i8xx_lvds;
a93e255f 577 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 578 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 579 else
580 limit = &intel_limits_i8xx_dac;
79e53945
JB		 581 }
582 return limit;
583}
584
dccbea3b
ID		 585/*
586 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
587 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
588 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
589 * The helpers' return value is the rate of the clock that is fed to the
590 * display engine's pipe which can be the above fast dot clock rate or a
591 * divided-down version of it.
592 */
f2b115e6 593/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 594static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 595{
2177832f
SL		 596 clock->m = clock->m2 + 2;
597 clock->p = clock->p1 * clock->p2;
ed5ca77e 598 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 599 return 0;
fb03ac01
VS		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot;
2177832f
SL		 604}
605
7429e9d4
DV		 606static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
607{
608 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
609}
610
dccbea3b 611static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 612{
7429e9d4 613 clock->m = i9xx_dpll_compute_m(clock);
79e53945 614 clock->p = clock->p1 * clock->p2;
ed5ca77e 615 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 616 return 0;
fb03ac01
VS		 617 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
618 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 619
620 return clock->dot;
79e53945
JB		 621}
622
dccbea3b 623static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 624{
625 clock->m = clock->m1 * clock->m2;
626 clock->p = clock->p1 * clock->p2;
627 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 628 return 0;
589eca67
ID		 629 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
630 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 631
632 return clock->dot / 5;
589eca67
ID		 633}
634
dccbea3b 635int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 636{
637 clock->m = clock->m1 * clock->m2;
638 clock->p = clock->p1 * clock->p2;
639 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 640 return 0;
ef9348c8
CML		 641 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
642 clock->n << 22);
643 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 644
645 return clock->dot / 5;
ef9348c8
CML		 646}
647
7c04d1d9 648#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 649/**
650 * Returns whether the given set of divisors are valid for a given refclk with
651 * the given connectors.
652 */
653
1b894b59
CW		 654static bool intel_PLL_is_valid(struct drm_device *dev,
655 const intel_limit_t *limit,
656 const intel_clock_t *clock)
79e53945 657{
f01b7962
VS		 658 if (clock->n < limit->n.min || limit->n.max < clock->n)
659 INTELPllInvalid("n out of range\n");
79e53945 660 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 661 INTELPllInvalid("p1 out of range\n");
79e53945 662 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 663 INTELPllInvalid("m2 out of range\n");
79e53945 664 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 665 INTELPllInvalid("m1 out of range\n");
f01b7962 666
5ab7b0b7 667 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 668 if (clock->m1 <= clock->m2)
669 INTELPllInvalid("m1 <= m2\n");
670
5ab7b0b7 671 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 672 if (clock->p < limit->p.min || limit->p.max < clock->p)
673 INTELPllInvalid("p out of range\n");
674 if (clock->m < limit->m.min || limit->m.max < clock->m)
675 INTELPllInvalid("m out of range\n");
676 }
677
79e53945 678 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 679 INTELPllInvalid("vco out of range\n");
79e53945
JB		 680 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
681 * connector, etc., rather than just a single range.
682 */
683 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 684 INTELPllInvalid("dot out of range\n");
79e53945
JB		 685
686 return true;
687}
688
3b1429d9
VS		 689static int
690i9xx_select_p2_div(const intel_limit_t *limit,
691 const struct intel_crtc_state *crtc_state,
692 int target)
79e53945 693{
3b1429d9 694 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 695
a93e255f 696 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 697 /*
a210b028
DV		 698 * For LVDS just rely on its current settings for dual-channel.
699 * We haven't figured out how to reliably set up different
700 * single/dual channel state, if we even can.
79e53945 701 */
1974cad0 702 if (intel_is_dual_link_lvds(dev))
3b1429d9 703 return limit->p2.p2_fast;
79e53945 704 else
3b1429d9 705 return limit->p2.p2_slow;
79e53945
JB		 706 } else {
707 if (target < limit->p2.dot_limit)
3b1429d9 708 return limit->p2.p2_slow;
79e53945 709 else
3b1429d9 710 return limit->p2.p2_fast;
79e53945 711 }
3b1429d9
VS		 712}
713
714static bool
715i9xx_find_best_dpll(const intel_limit_t *limit,
716 struct intel_crtc_state *crtc_state,
717 int target, int refclk, intel_clock_t *match_clock,
718 intel_clock_t *best_clock)
719{
720 struct drm_device *dev = crtc_state->base.crtc->dev;
721 intel_clock_t clock;
722 int err = target;
79e53945 723
0206e353 724 memset(best_clock, 0, sizeof(*best_clock));
79e53945 725
3b1429d9
VS		 726 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
727
42158660
ZY		 728 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
729 clock.m1++) {
730 for (clock.m2 = limit->m2.min;
731 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 732 if (clock.m2 >= clock.m1)
42158660
ZY		 733 break;
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 738 int this_err;
739
dccbea3b 740 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
761static bool
a93e255f
ACO		 762pnv_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
79e53945 766{
3b1429d9 767 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 768 intel_clock_t clock;
79e53945
JB		 769 int err = target;
770
0206e353 771 memset(best_clock, 0, sizeof(*best_clock));
79e53945 772
3b1429d9
VS		 773 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
774
42158660
ZY		 775 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
776 clock.m1++) {
777 for (clock.m2 = limit->m2.min;
778 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 779 for (clock.n = limit->n.min;
780 clock.n <= limit->n.max; clock.n++) {
781 for (clock.p1 = limit->p1.min;
782 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 783 int this_err;
784
dccbea3b 785 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
79e53945 788 continue;
cec2f356
SP		 789 if (match_clock &&
790 clock.p != match_clock->p)
791 continue;
79e53945
JB		 792
793 this_err = abs(clock.dot - target);
794 if (this_err < err) {
795 *best_clock = clock;
796 err = this_err;
797 }
798 }
799 }
800 }
801 }
802
803 return (err != target);
804}
805
d4906093 806static bool
a93e255f
ACO		 807g4x_find_best_dpll(const intel_limit_t *limit,
808 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
d4906093 811{
3b1429d9 812 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 813 intel_clock_t clock;
814 int max_n;
3b1429d9 815 bool found = false;
6ba770dc
AJ		 816 /* approximately equals target * 0.00585 */
817 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 818
819 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 820
821 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
822
d4906093 823 max_n = limit->n.max;
f77f13e2 824 /* based on hardware requirement, prefer smaller n to precision */
d4906093 825 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 826 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 827 for (clock.m1 = limit->m1.max;
828 clock.m1 >= limit->m1.min; clock.m1--) {
829 for (clock.m2 = limit->m2.max;
830 clock.m2 >= limit->m2.min; clock.m2--) {
831 for (clock.p1 = limit->p1.max;
832 clock.p1 >= limit->p1.min; clock.p1--) {
833 int this_err;
834
dccbea3b 835 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
d4906093 838 continue;
1b894b59
CW		 839
840 this_err = abs(clock.dot - target);
d4906093
ML		 841 if (this_err < err_most) {
842 *best_clock = clock;
843 err_most = this_err;
844 max_n = clock.n;
845 found = true;
846 }
847 }
848 }
849 }
850 }
2c07245f
ZW		 851 return found;
852}
853
d5dd62bd
ID		 854/*
855 * Check if the calculated PLL configuration is more optimal compared to the
856 * best configuration and error found so far. Return the calculated error.
857 */
858static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
859 const intel_clock_t *calculated_clock,
860 const intel_clock_t *best_clock,
861 unsigned int best_error_ppm,
862 unsigned int *error_ppm)
863{
9ca3ba01
ID		 864 /*
865 * For CHV ignore the error and consider only the P value.
866 * Prefer a bigger P value based on HW requirements.
867 */
868 if (IS_CHERRYVIEW(dev)) {
869 *error_ppm = 0;
870
871 return calculated_clock->p > best_clock->p;
872 }
873
24be4e46
ID		 874 if (WARN_ON_ONCE(!target_freq))
875 return false;
876
d5dd62bd
ID		 877 *error_ppm = div_u64(1000000ULL *
878 abs(target_freq - calculated_clock->dot),
879 target_freq);
880 /*
881 * Prefer a better P value over a better (smaller) error if the error
882 * is small. Ensure this preference for future configurations too by
883 * setting the error to 0.
884 */
885 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
886 *error_ppm = 0;
887
888 return true;
889 }
890
891 return *error_ppm + 10 < best_error_ppm;
892}
893
a0c4da24 894static bool
a93e255f
ACO		 895vlv_find_best_dpll(const intel_limit_t *limit,
896 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 897 int target, int refclk, intel_clock_t *match_clock,
898 intel_clock_t *best_clock)
a0c4da24 899{
a93e255f 900 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 901 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 902 intel_clock_t clock;
69e4f900 903 unsigned int bestppm = 1000000;
27e639bf
VS		 904 /* min update 19.2 MHz */
905 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 906 bool found = false;
a0c4da24 907
6b4bf1c4
VS		 908 target *= 5; /* fast clock */
909
910 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 911
912 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 913 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 914 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 915 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 916 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 917 clock.p = clock.p1 * clock.p2;
a0c4da24 918 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 919 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 920 unsigned int ppm;
69e4f900 921
6b4bf1c4
VS		 922 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
923 refclk * clock.m1);
924
dccbea3b 925 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 926
f01b7962
VS		 927 if (!intel_PLL_is_valid(dev, limit,
928 &clock))
43b0ac53
VS		 929 continue;
930
d5dd62bd
ID		 931 if (!vlv_PLL_is_optimal(dev, target,
932 &clock,
933 best_clock,
934 bestppm, &ppm))
935 continue;
6b4bf1c4 936
d5dd62bd
ID		 937 *best_clock = clock;
938 bestppm = ppm;
939 found = true;
a0c4da24
JB		 940 }
941 }
942 }
943 }
a0c4da24 944
49e497ef 945 return found;
a0c4da24 946}
a4fc5ed6 947
ef9348c8 948static bool
a93e255f
ACO		 949chv_find_best_dpll(const intel_limit_t *limit,
950 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 951 int target, int refclk, intel_clock_t *match_clock,
952 intel_clock_t *best_clock)
953{
a93e255f 954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 955 struct drm_device *dev = crtc->base.dev;
9ca3ba01 956 unsigned int best_error_ppm;
ef9348c8
CML		 957 intel_clock_t clock;
958 uint64_t m2;
959 int found = false;
960
961 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 962 best_error_ppm = 1000000;
ef9348c8
CML		 963
964 /*
965 * Based on hardware doc, the n always set to 1, and m1 always
966 * set to 2. If requires to support 200Mhz refclk, we need to
967 * revisit this because n may not 1 anymore.
968 */
969 clock.n = 1, clock.m1 = 2;
970 target *= 5; /* fast clock */
971
972 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
973 for (clock.p2 = limit->p2.p2_fast;
974 clock.p2 >= limit->p2.p2_slow;
975 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 976 unsigned int error_ppm;
ef9348c8
CML		 977
978 clock.p = clock.p1 * clock.p2;
979
980 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
981 clock.n) << 22, refclk * clock.m1);
982
983 if (m2 > INT_MAX/clock.m1)
984 continue;
985
986 clock.m2 = m2;
987
dccbea3b 988 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 989
990 if (!intel_PLL_is_valid(dev, limit, &clock))
991 continue;
992
9ca3ba01
ID		 993 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
994 best_error_ppm, &error_ppm))
995 continue;
996
997 *best_clock = clock;
998 best_error_ppm = error_ppm;
999 found = true;
ef9348c8
CML		 1000 }
1001 }
1002
1003 return found;
1004}
1005
5ab7b0b7
ID		 1006bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1007 intel_clock_t *best_clock)
1008{
1009 int refclk = i9xx_get_refclk(crtc_state, 0);
1010
1011 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1012 target_clock, refclk, NULL, best_clock);
1013}
1014
20ddf665
VS		 1015bool intel_crtc_active(struct drm_crtc *crtc)
1016{
1017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1018
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1021 *
241bfc38 1022 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1023 * as Haswell has gained clock readout/fastboot support.
1024 *
66e514c1 1025 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1026 * properly reconstruct framebuffers.
c3d1f436
MR		 1027 *
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1030 * for atomic.
20ddf665 1031 */
c3d1f436 1032 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1033 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1034}
1035
a5c961d1
PZ		 1036enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1037 enum pipe pipe)
1038{
1039 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1041
6e3c9717 1042 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1043}
1044
fbf49ea2
VS		 1045static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1046{
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 reg = PIPEDSL(pipe);
1049 u32 line1, line2;
1050 u32 line_mask;
1051
1052 if (IS_GEN2(dev))
1053 line_mask = DSL_LINEMASK_GEN2;
1054 else
1055 line_mask = DSL_LINEMASK_GEN3;
1056
1057 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1058 msleep(5);
fbf49ea2
VS		 1059 line2 = I915_READ(reg) & line_mask;
1060
1061 return line1 == line2;
1062}
1063
ab7ad7f6
KP		 1064/*
1065 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1066 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1067 *
1068 * After disabling a pipe, we can't wait for vblank in the usual way,
1069 * spinning on the vblank interrupt status bit, since we won't actually
1070 * see an interrupt when the pipe is disabled.
1071 *
ab7ad7f6
KP		 1072 * On Gen4 and above:
1073 * wait for the pipe register state bit to turn off
1074 *
1075 * Otherwise:
1076 * wait for the display line value to settle (it usually
1077 * ends up stopping at the start of the next frame).
58e10eb9 1078 *
9d0498a2 1079 */
575f7ab7 1080static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1081{
575f7ab7 1082 struct drm_device *dev = crtc->base.dev;
9d0498a2 1083 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1084 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1085 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1086
1087 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1088 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1089
1090 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1091 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1092 100))
284637d9 1093 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1094 } else {
ab7ad7f6 1095 /* Wait for the display line to settle */
fbf49ea2 1096 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1097 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1098 }
79e53945
JB		 1099}
1100
b24e7179
JB		 1101static const char *state_string(bool enabled)
1102{
1103 return enabled ? "on" : "off";
1104}
1105
1106/* Only for pre-ILK configs */
55607e8a
DV		 1107void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
b24e7179
JB		 1109{
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = DPLL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1117 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
b24e7179 1121
23538ef1
JN		 1122/* XXX: the dsi pll is shared between MIPI DSI ports */
1123static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124{
1125 u32 val;
1126 bool cur_state;
1127
a580516d 1128 mutex_lock(&dev_priv->sb_lock);
23538ef1 1129 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1130 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1131
1132 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
1137#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
55607e8a 1140struct intel_shared_dpll *
e2b78267
DV		 1141intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142{
1143 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
6e3c9717 1145 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1146 return NULL;
1147
6e3c9717 1148 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1149}
1150
040484af 1151/* For ILK+ */
55607e8a
DV		 1152void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153 struct intel_shared_dpll *pll,
1154 bool state)
040484af 1155{
040484af 1156 bool cur_state;
5358901f 1157 struct intel_dpll_hw_state hw_state;
040484af 1158
92b27b08 1159 if (WARN (!pll,
46edb027 1160 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1161 return;
ee7b9f93 1162
5358901f 1163 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1164 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll->name, state_string(state), state_string(cur_state));
040484af 1167}
040484af
JB		 1168
1169static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171{
1172 int reg;
1173 u32 val;
1174 bool cur_state;
ad80a810
PZ		 1175 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176 pipe);
040484af 1177
affa9354
PZ		 1178 if (HAS_DDI(dev_priv->dev)) {
1179 /* DDI does not have a specific FDI_TX register */
ad80a810 1180 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1181 val = I915_READ(reg);
ad80a810 1182 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1183 } else {
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_TX_ENABLE);
1187 }
e2c719b7 1188 I915_STATE_WARN(cur_state != state,
040484af
JB		 1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191}
1192#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197{
1198 int reg;
1199 u32 val;
1200 bool cur_state;
1201
d63fa0dc
PZ		 1202 reg = FDI_RX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1205 I915_STATE_WARN(cur_state != state,
040484af
JB		 1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208}
1209#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214{
1215 int reg;
1216 u32 val;
1217
1218 /* ILK FDI PLL is always enabled */
3d13ef2e 1219 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1220 return;
1221
bf507ef7 1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1223 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1224 return;
1225
040484af
JB		 1226 reg = FDI_TX_CTL(pipe);
1227 val = I915_READ(reg);
e2c719b7 1228 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1229}
1230
55607e8a
DV		 1231void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
040484af
JB		 1233{
1234 int reg;
1235 u32 val;
55607e8a 1236 bool cur_state;
040484af
JB		 1237
1238 reg = FDI_RX_CTL(pipe);
1239 val = I915_READ(reg);
55607e8a 1240 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1241 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state), state_string(cur_state));
040484af
JB		 1244}
1245
b680c37a
DV		 1246void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
ea0760cf 1248{
bedd4dba
JN		 1249 struct drm_device *dev = dev_priv->dev;
1250 int pp_reg;
ea0760cf
JB		 1251 u32 val;
1252 enum pipe panel_pipe = PIPE_A;
0de3b485 1253 bool locked = true;
ea0760cf 1254
bedd4dba
JN		 1255 if (WARN_ON(HAS_DDI(dev)))
1256 return;
1257
1258 if (HAS_PCH_SPLIT(dev)) {
1259 u32 port_sel;
1260
ea0760cf 1261 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1262 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266 panel_pipe = PIPE_B;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271 panel_pipe = pipe;
ea0760cf
JB		 1272 } else {
1273 pp_reg = PP_CONTROL;
bedd4dba
JN		 1274 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275 panel_pipe = PIPE_B;
ea0760cf
JB		 1276 }
1277
1278 val = I915_READ(pp_reg);
1279 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1280 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1281 locked = false;
1282
e2c719b7 1283 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1284 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1285 pipe_name(pipe));
ea0760cf
JB		 1286}
1287
93ce0ba6
JN		 1288static void assert_cursor(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290{
1291 struct drm_device *dev = dev_priv->dev;
1292 bool cur_state;
1293
d9d82081 1294 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1295 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1296 else
5efb3e28 1297 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1298
e2c719b7 1299 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe), state_string(state), state_string(cur_state));
1302}
1303#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
b840d907
JB		 1306void assert_pipe(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
b24e7179
JB		 1308{
1309 int reg;
1310 u32 val;
63d7bbe9 1311 bool cur_state;
702e7a56
PZ		 1312 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313 pipe);
b24e7179 1314
b6b5d049
VS		 1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1318 state = true;
1319
f458ebbc 1320 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1322 cur_state = false;
1323 } else {
1324 reg = PIPECONF(cpu_transcoder);
1325 val = I915_READ(reg);
1326 cur_state = !!(val & PIPECONF_ENABLE);
1327 }
1328
e2c719b7 1329 I915_STATE_WARN(cur_state != state,
63d7bbe9 1330 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1331 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1332}
1333
931872fc
CW		 1334static void assert_plane(struct drm_i915_private *dev_priv,
1335 enum plane plane, bool state)
b24e7179
JB		 1336{
1337 int reg;
1338 u32 val;
931872fc 1339 bool cur_state;
b24e7179
JB		 1340
1341 reg = DSPCNTR(plane);
1342 val = I915_READ(reg);
931872fc 1343 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
b24e7179
JB		 1352static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354{
653e1026 1355 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1356 int reg, i;
1357 u32 val;
1358 int cur_pipe;
1359
653e1026
VS		 1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1362 reg = DSPCNTR(pipe);
1363 val = I915_READ(reg);
e2c719b7 1364 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1365 "plane %c assertion failure, should be disabled but not\n",
1366 plane_name(pipe));
19ec1358 1367 return;
28c05794 1368 }
19ec1358 1369
b24e7179 1370 /* Need to check both planes against the pipe */
055e393f 1371 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1372 reg = DSPCNTR(i);
1373 val = I915_READ(reg);
1374 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1376 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1379 }
1380}
1381
19332d7a
JB		 1382static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384{
20674eef 1385 struct drm_device *dev = dev_priv->dev;
1fe47785 1386 int reg, sprite;
19332d7a
JB		 1387 u32 val;
1388
7feb8b88 1389 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1390 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1391 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1392 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite, pipe_name(pipe));
1395 }
1396 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1397 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1398 reg = SPCNTR(pipe, sprite);
20674eef 1399 val = I915_READ(reg);
e2c719b7 1400 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1402 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1403 }
1404 } else if (INTEL_INFO(dev)->gen >= 7) {
1405 reg = SPRCTL(pipe);
19332d7a 1406 val = I915_READ(reg);
e2c719b7 1407 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1409 plane_name(pipe), pipe_name(pipe));
1410 } else if (INTEL_INFO(dev)->gen >= 5) {
1411 reg = DVSCNTR(pipe);
19332d7a 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1415 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1416 }
1417}
1418
08c71e5e
VS		 1419static void assert_vblank_disabled(struct drm_crtc *crtc)
1420{
e2c719b7 1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1422 drm_crtc_vblank_put(crtc);
1423}
1424
89eff4be 1425static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1426{
1427 u32 val;
1428 bool enabled;
1429
e2c719b7 1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1431
92f2584a
JB		 1432 val = I915_READ(PCH_DREF_CONTROL);
1433 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1435 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1436}
1437
ab9412ba
DV		 1438static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
92f2584a
JB		 1440{
1441 int reg;
1442 u32 val;
1443 bool enabled;
1444
ab9412ba 1445 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1446 val = I915_READ(reg);
1447 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1448 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450 pipe_name(pipe));
92f2584a
JB		 1451}
1452
4e634389
KP		 1453static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1455{
1456 if ((val & DP_PORT_EN) == 0)
1457 return false;
1458
1459 if (HAS_PCH_CPT(dev_priv->dev)) {
1460 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463 return false;
44f37d1f
CML		 1464 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466 return false;
f0575e92
KP		 1467 } else {
1468 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469 return false;
1470 }
1471 return true;
1472}
1473
1519b995
KP		 1474static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 val)
1476{
dc0fa718 1477 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1481 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1482 return false;
44f37d1f
CML		 1483 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485 return false;
1519b995 1486 } else {
dc0fa718 1487 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1488 return false;
1489 }
1490 return true;
1491}
1492
1493static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, u32 val)
1495{
1496 if ((val & LVDS_PORT_EN) == 0)
1497 return false;
1498
1499 if (HAS_PCH_CPT(dev_priv->dev)) {
1500 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501 return false;
1502 } else {
1503 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & ADPA_DAC_ENABLE) == 0)
1513 return false;
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
291906f1 1524static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1525 enum pipe pipe, int reg, u32 port_sel)
291906f1 1526{
47a05eca 1527 u32 val = I915_READ(reg);
e2c719b7 1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1530 reg, pipe_name(pipe));
de9a35ab 1531
e2c719b7 1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1533 && (val & DP_PIPEB_SELECT),
de9a35ab 1534 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1535}
1536
1537static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, int reg)
1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1546 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1547 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe)
1552{
1553 int reg;
1554 u32 val;
291906f1 1555
f0575e92
KP		 1556 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1559
1560 reg = PCH_ADPA;
1561 val = I915_READ(reg);
e2c719b7 1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1564 pipe_name(pipe));
291906f1
JB		 1565
1566 reg = PCH_LVDS;
1567 val = I915_READ(reg);
e2c719b7 1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1570 pipe_name(pipe));
291906f1 1571
e2debe91
PZ		 1572 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1575}
1576
d288f65f 1577static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1578 const struct intel_crtc_state *pipe_config)
87442f73 1579{
426115cf
DV		 1580 struct drm_device *dev = crtc->base.dev;
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 int reg = DPLL(crtc->pipe);
d288f65f 1583 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1584
426115cf 1585 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1586
1587 /* No really, not for ILK+ */
1588 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1589
1590 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1591 if (IS_MOBILE(dev_priv->dev))
426115cf 1592 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1593
426115cf
DV		 1594 I915_WRITE(reg, dpll);
1595 POSTING_READ(reg);
1596 udelay(150);
1597
1598 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1599 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1600
d288f65f 1601 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1602 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1603
1604 /* We do this three times for luck */
426115cf 1605 I915_WRITE(reg, dpll);
87442f73
DV		 1606 POSTING_READ(reg);
1607 udelay(150); /* wait for warmup */
426115cf 1608 I915_WRITE(reg, dpll);
87442f73
DV		 1609 POSTING_READ(reg);
1610 udelay(150); /* wait for warmup */
426115cf 1611 I915_WRITE(reg, dpll);
87442f73
DV		 1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
1614}
1615
d288f65f 1616static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1617 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1618{
1619 struct drm_device *dev = crtc->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 int pipe = crtc->pipe;
1622 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1623 u32 tmp;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1628
a580516d 1629 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1630
1631 /* Enable back the 10bit clock to display controller */
1632 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1633 tmp |= DPIO_DCLKP_EN;
1634 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1635
54433e91
VS		 1636 mutex_unlock(&dev_priv->sb_lock);
1637
9d556c99
CML		 1638 /*
1639 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1640 */
1641 udelay(1);
1642
1643 /* Enable PLL */
d288f65f 1644 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1645
1646 /* Check PLL is locked */
a11b0703 1647 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1648 DRM_ERROR("PLL %d failed to lock\n", pipe);
1649
a11b0703 1650 /* not sure when this should be written */
d288f65f 1651 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1652 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1653}
1654
1c4e0274
VS		 1655static int intel_num_dvo_pipes(struct drm_device *dev)
1656{
1657 struct intel_crtc *crtc;
1658 int count = 0;
1659
1660 for_each_intel_crtc(dev, crtc)
3538b9df 1661 count += crtc->base.state->active &&
409ee761 1662 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1663
1664 return count;
1665}
1666
66e3d5c0 1667static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1668{
66e3d5c0
DV		 1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int reg = DPLL(crtc->pipe);
6e3c9717 1672 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1673
66e3d5c0 1674 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1675
63d7bbe9 1676 /* No really, not for ILK+ */
3d13ef2e 1677 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1678
1679 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1680 if (IS_MOBILE(dev) && !IS_I830(dev))
1681 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1682
1c4e0274
VS		 1683 /* Enable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1685 /*
1686 * It appears to be important that we don't enable this
1687 * for the current pipe before otherwise configuring the
1688 * PLL. No idea how this should be handled if multiple
1689 * DVO outputs are enabled simultaneosly.
1690 */
1691 dpll |= DPLL_DVO_2X_MODE;
1692 I915_WRITE(DPLL(!crtc->pipe),
1693 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1694 }
66e3d5c0
DV		 1695
1696 /* Wait for the clocks to stabilize. */
1697 POSTING_READ(reg);
1698 udelay(150);
1699
1700 if (INTEL_INFO(dev)->gen >= 4) {
1701 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1702 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1703 } else {
1704 /* The pixel multiplier can only be updated once the
1705 * DPLL is enabled and the clocks are stable.
1706 *
1707 * So write it again.
1708 */
1709 I915_WRITE(reg, dpll);
1710 }
63d7bbe9
JB		 1711
1712 /* We do this three times for luck */
66e3d5c0 1713 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1714 POSTING_READ(reg);
1715 udelay(150); /* wait for warmup */
66e3d5c0 1716 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1717 POSTING_READ(reg);
1718 udelay(150); /* wait for warmup */
66e3d5c0 1719 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
1722}
1723
1724/**
50b44a44 1725 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1726 * @dev_priv: i915 private structure
1727 * @pipe: pipe PLL to disable
1728 *
1729 * Disable the PLL for @pipe, making sure the pipe is off first.
1730 *
1731 * Note! This is for pre-ILK only.
1732 */
1c4e0274 1733static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1734{
1c4e0274
VS		 1735 struct drm_device *dev = crtc->base.dev;
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 enum pipe pipe = crtc->pipe;
1738
1739 /* Disable DVO 2x clock on both PLLs if necessary */
1740 if (IS_I830(dev) &&
409ee761 1741 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1742 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1743 I915_WRITE(DPLL(PIPE_B),
1744 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1745 I915_WRITE(DPLL(PIPE_A),
1746 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1747 }
1748
b6b5d049
VS		 1749 /* Don't disable pipe or pipe PLLs if needed */
1750 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1751 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1752 return;
1753
1754 /* Make sure the pipe isn't still relying on us */
1755 assert_pipe_disabled(dev_priv, pipe);
1756
b8afb911 1757 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1758 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1759}
1760
f6071166
JB		 1761static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1762{
b8afb911 1763 u32 val;
f6071166
JB		 1764
1765 /* Make sure the pipe isn't still relying on us */
1766 assert_pipe_disabled(dev_priv, pipe);
1767
e5cbfbfb
ID		 1768 /*
1769 * Leave integrated clock source and reference clock enabled for pipe B.
1770 * The latter is needed for VGA hotplug / manual detection.
1771 */
b8afb911 1772 val = DPLL_VGA_MODE_DIS;
f6071166 1773 if (pipe == PIPE_B)
60bfe44f 1774 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1775 I915_WRITE(DPLL(pipe), val);
1776 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1777
1778}
1779
1780static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1781{
d752048d 1782 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1783 u32 val;
1784
a11b0703
VS		 1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1787
a11b0703 1788 /* Set PLL en = 0 */
60bfe44f
VS		 1789 val = DPLL_SSC_REF_CLK_CHV |
1790 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1791 if (pipe != PIPE_A)
1792 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1793 I915_WRITE(DPLL(pipe), val);
1794 POSTING_READ(DPLL(pipe));
d752048d 1795
a580516d 1796 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1797
1798 /* Disable 10bit clock to display controller */
1799 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1800 val &= ~DPIO_DCLKP_EN;
1801 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1802
a580516d 1803 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1804}
1805
e4607fcf 1806void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1807 struct intel_digital_port *dport,
1808 unsigned int expected_mask)
89b667f8
JB		 1809{
1810 u32 port_mask;
00fc31b7 1811 int dpll_reg;
89b667f8 1812
e4607fcf
CML		 1813 switch (dport->port) {
1814 case PORT_B:
89b667f8 1815 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1816 dpll_reg = DPLL(0);
e4607fcf
CML		 1817 break;
1818 case PORT_C:
89b667f8 1819 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1820 dpll_reg = DPLL(0);
9b6de0a1 1821 expected_mask <<= 4;
00fc31b7
CML		 1822 break;
1823 case PORT_D:
1824 port_mask = DPLL_PORTD_READY_MASK;
1825 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1826 break;
1827 default:
1828 BUG();
1829 }
89b667f8 1830
9b6de0a1
VS		 1831 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1832 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1833 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1834}
1835
b14b1055
DV		 1836static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1837{
1838 struct drm_device *dev = crtc->base.dev;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1841
be19f0ff
CW		 1842 if (WARN_ON(pll == NULL))
1843 return;
1844
3e369b76 1845 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1846 if (pll->active == 0) {
1847 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1848 WARN_ON(pll->on);
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850
1851 pll->mode_set(dev_priv, pll);
1852 }
1853}
1854
92f2584a 1855/**
85b3894f 1856 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1857 * @dev_priv: i915 private structure
1858 * @pipe: pipe PLL to enable
1859 *
1860 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1861 * drives the transcoder clock.
1862 */
85b3894f 1863static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1864{
3d13ef2e
DL		 1865 struct drm_device *dev = crtc->base.dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1867 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1868
87a875bb 1869 if (WARN_ON(pll == NULL))
48da64a8
CW		 1870 return;
1871
3e369b76 1872 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1873 return;
ee7b9f93 1874
74dd6928 1875 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1876 pll->name, pll->active, pll->on,
e2b78267 1877 crtc->base.base.id);
92f2584a 1878
cdbd2316
DV		 1879 if (pll->active++) {
1880 WARN_ON(!pll->on);
e9d6944e 1881 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1882 return;
1883 }
f4a091c7 1884 WARN_ON(pll->on);
ee7b9f93 1885
bd2bb1b9
PZ		 1886 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1887
46edb027 1888 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1889 pll->enable(dev_priv, pll);
ee7b9f93 1890 pll->on = true;
92f2584a
JB		 1891}
1892
f6daaec2 1893static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1894{
3d13ef2e
DL		 1895 struct drm_device *dev = crtc->base.dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1897 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1898
92f2584a 1899 /* PCH only available on ILK+ */
80aa9312
JB		 1900 if (INTEL_INFO(dev)->gen < 5)
1901 return;
1902
eddfcbcd
ML		 1903 if (pll == NULL)
1904 return;
92f2584a 1905
eddfcbcd 1906 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1907 return;
7a419866 1908
46edb027
DV		 1909 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1910 pll->name, pll->active, pll->on,
e2b78267 1911 crtc->base.base.id);
7a419866 1912
48da64a8 1913 if (WARN_ON(pll->active == 0)) {
e9d6944e 1914 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1915 return;
1916 }
1917
e9d6944e 1918 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1919 WARN_ON(!pll->on);
cdbd2316 1920 if (--pll->active)
7a419866 1921 return;
ee7b9f93 1922
46edb027 1923 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1924 pll->disable(dev_priv, pll);
ee7b9f93 1925 pll->on = false;
bd2bb1b9
PZ		 1926
1927 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1928}
1929
b8a4f404
PZ		 1930static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1931 enum pipe pipe)
040484af 1932{
23670b32 1933 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1934 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1936 uint32_t reg, val, pipeconf_val;
040484af
JB		 1937
1938 /* PCH only available on ILK+ */
55522f37 1939 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1940
1941 /* Make sure PCH DPLL is enabled */
e72f9fbf 1942 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1943 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1944
1945 /* FDI must be feeding us bits for PCH ports */
1946 assert_fdi_tx_enabled(dev_priv, pipe);
1947 assert_fdi_rx_enabled(dev_priv, pipe);
1948
23670b32
DV		 1949 if (HAS_PCH_CPT(dev)) {
1950 /* Workaround: Set the timing override bit before enabling the
1951 * pch transcoder. */
1952 reg = TRANS_CHICKEN2(pipe);
1953 val = I915_READ(reg);
1954 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1955 I915_WRITE(reg, val);
59c859d6 1956 }
23670b32 1957
ab9412ba 1958 reg = PCH_TRANSCONF(pipe);
040484af 1959 val = I915_READ(reg);
5f7f726d 1960 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1961
1962 if (HAS_PCH_IBX(dev_priv->dev)) {
1963 /*
c5de7c6f
VS		 1964 * Make the BPC in transcoder be consistent with
1965 * that in pipeconf reg. For HDMI we must use 8bpc
1966 * here for both 8bpc and 12bpc.
e9bcff5c 1967 */
dfd07d72 1968 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1969 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1970 val |= PIPECONF_8BPC;
1971 else
1972 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1973 }
5f7f726d
PZ		 1974
1975 val &= ~TRANS_INTERLACE_MASK;
1976 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1977 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1978 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1979 val |= TRANS_LEGACY_INTERLACED_ILK;
1980 else
1981 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1982 else
1983 val |= TRANS_PROGRESSIVE;
1984
040484af
JB		 1985 I915_WRITE(reg, val | TRANS_ENABLE);
1986 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1987 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1988}
1989
8fb033d7 1990static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1991 enum transcoder cpu_transcoder)
040484af 1992{
8fb033d7 1993 u32 val, pipeconf_val;
8fb033d7
PZ		 1994
1995 /* PCH only available on ILK+ */
55522f37 1996 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1997
8fb033d7 1998 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1999 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2000 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2001
223a6fdf
PZ		 2002 /* Workaround: set timing override bit. */
2003 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2004 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2005 I915_WRITE(_TRANSA_CHICKEN2, val);
2006
25f3ef11 2007 val = TRANS_ENABLE;
937bb610 2008 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2009
9a76b1c6
PZ		 2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2011 PIPECONF_INTERLACED_ILK)
a35f2679 2012 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2013 else
2014 val |= TRANS_PROGRESSIVE;
2015
ab9412ba
DV		 2016 I915_WRITE(LPT_TRANSCONF, val);
2017 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2018 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2019}
2020
b8a4f404
PZ		 2021static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2022 enum pipe pipe)
040484af 2023{
23670b32
DV		 2024 struct drm_device *dev = dev_priv->dev;
2025 uint32_t reg, val;
040484af
JB		 2026
2027 /* FDI relies on the transcoder */
2028 assert_fdi_tx_disabled(dev_priv, pipe);
2029 assert_fdi_rx_disabled(dev_priv, pipe);
2030
291906f1
JB		 2031 /* Ports must be off as well */
2032 assert_pch_ports_disabled(dev_priv, pipe);
2033
ab9412ba 2034 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2035 val = I915_READ(reg);
2036 val &= ~TRANS_ENABLE;
2037 I915_WRITE(reg, val);
2038 /* wait for PCH transcoder off, transcoder state */
2039 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2040 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2041
2042 if (!HAS_PCH_IBX(dev)) {
2043 /* Workaround: Clear the timing override chicken bit again. */
2044 reg = TRANS_CHICKEN2(pipe);
2045 val = I915_READ(reg);
2046 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2047 I915_WRITE(reg, val);
2048 }
040484af
JB		 2049}
2050
ab4d966c 2051static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2052{
8fb033d7
PZ		 2053 u32 val;
2054
ab9412ba 2055 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2056 val &= ~TRANS_ENABLE;
ab9412ba 2057 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2058 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2059 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2060 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2061
2062 /* Workaround: clear timing override bit. */
2063 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2064 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2065 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2066}
2067
b24e7179 2068/**
309cfea8 2069 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2070 * @crtc: crtc responsible for the pipe
b24e7179 2071 *
0372264a 2072 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2073 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2074 */
e1fdc473 2075static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2076{
0372264a
PZ		 2077 struct drm_device *dev = crtc->base.dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2080 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2081 pipe);
1a240d4d 2082 enum pipe pch_transcoder;
b24e7179
JB		 2083 int reg;
2084 u32 val;
2085
9e2ee2dd
VS		 2086 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2087
58c6eaa2 2088 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2089 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2090 assert_sprites_disabled(dev_priv, pipe);
2091
681e5811 2092 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2093 pch_transcoder = TRANSCODER_A;
2094 else
2095 pch_transcoder = pipe;
2096
b24e7179
JB		 2097 /*
2098 * A pipe without a PLL won't actually be able to drive bits from
2099 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2100 * need the check.
2101 */
50360403 2102 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2103 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2104 assert_dsi_pll_enabled(dev_priv);
2105 else
2106 assert_pll_enabled(dev_priv, pipe);
040484af 2107 else {
6e3c9717 2108 if (crtc->config->has_pch_encoder) {
040484af 2109 /* if driving the PCH, we need FDI enabled */
cc391bbb 2110 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2111 assert_fdi_tx_pll_enabled(dev_priv,
2112 (enum pipe) cpu_transcoder);
040484af
JB		 2113 }
2114 /* FIXME: assert CPU port conditions for SNB+ */
2115 }
b24e7179 2116
702e7a56 2117 reg = PIPECONF(cpu_transcoder);
b24e7179 2118 val = I915_READ(reg);
7ad25d48 2119 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2120 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2121 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2122 return;
7ad25d48 2123 }
00d70b15
CW		 2124
2125 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2126 POSTING_READ(reg);
b24e7179
JB		 2127}
2128
2129/**
309cfea8 2130 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2131 * @crtc: crtc whose pipes is to be disabled
b24e7179 2132 *
575f7ab7
VS		 2133 * Disable the pipe of @crtc, making sure that various hardware
2134 * specific requirements are met, if applicable, e.g. plane
2135 * disabled, panel fitter off, etc.
b24e7179
JB		 2136 *
2137 * Will wait until the pipe has shut down before returning.
2138 */
575f7ab7 2139static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2140{
575f7ab7 2141 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2142 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2143 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2144 int reg;
2145 u32 val;
2146
9e2ee2dd
VS		 2147 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2148
b24e7179
JB		 2149 /*
2150 * Make sure planes won't keep trying to pump pixels to us,
2151 * or we might hang the display.
2152 */
2153 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2154 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2155 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2156
702e7a56 2157 reg = PIPECONF(cpu_transcoder);
b24e7179 2158 val = I915_READ(reg);
00d70b15
CW		 2159 if ((val & PIPECONF_ENABLE) == 0)
2160 return;
2161
67adc644
VS		 2162 /*
2163 * Double wide has implications for planes
2164 * so best keep it disabled when not needed.
2165 */
6e3c9717 2166 if (crtc->config->double_wide)
67adc644
VS		 2167 val &= ~PIPECONF_DOUBLE_WIDE;
2168
2169 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2170 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2171 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2172 val &= ~PIPECONF_ENABLE;
2173
2174 I915_WRITE(reg, val);
2175 if ((val & PIPECONF_ENABLE) == 0)
2176 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2177}
2178
693db184
CW		 2179static bool need_vtd_wa(struct drm_device *dev)
2180{
2181#ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184#endif
2185 return false;
2186}
2187
50470bb0 2188unsigned int
6761dd31
TU		 2189intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2190 uint64_t fb_format_modifier)
a57ce0b2 2191{
6761dd31
TU		 2192 unsigned int tile_height;
2193 uint32_t pixel_bytes;
a57ce0b2 2194
b5d0e9bf
DL		 2195 switch (fb_format_modifier) {
2196 case DRM_FORMAT_MOD_NONE:
2197 tile_height = 1;
2198 break;
2199 case I915_FORMAT_MOD_X_TILED:
2200 tile_height = IS_GEN2(dev) ? 16 : 8;
2201 break;
2202 case I915_FORMAT_MOD_Y_TILED:
2203 tile_height = 32;
2204 break;
2205 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2206 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2207 switch (pixel_bytes) {
b5d0e9bf 2208 default:
6761dd31 2209 case 1:
b5d0e9bf
DL		 2210 tile_height = 64;
2211 break;
6761dd31
TU		 2212 case 2:
2213 case 4:
b5d0e9bf
DL		 2214 tile_height = 32;
2215 break;
6761dd31 2216 case 8:
b5d0e9bf
DL		 2217 tile_height = 16;
2218 break;
6761dd31 2219 case 16:
b5d0e9bf
DL		 2220 WARN_ONCE(1,
2221 "128-bit pixels are not supported for display!");
2222 tile_height = 16;
2223 break;
2224 }
2225 break;
2226 default:
2227 MISSING_CASE(fb_format_modifier);
2228 tile_height = 1;
2229 break;
2230 }
091df6cb 2231
6761dd31
TU		 2232 return tile_height;
2233}
2234
2235unsigned int
2236intel_fb_align_height(struct drm_device *dev, unsigned int height,
2237 uint32_t pixel_format, uint64_t fb_format_modifier)
2238{
2239 return ALIGN(height, intel_tile_height(dev, pixel_format,
2240 fb_format_modifier));
a57ce0b2
JB		 2241}
2242
f64b98cd
TU		 2243static int
2244intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2245 const struct drm_plane_state *plane_state)
2246{
50470bb0 2247 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2248 unsigned int tile_height, tile_pitch;
50470bb0 2249
f64b98cd
TU		 2250 *view = i915_ggtt_view_normal;
2251
50470bb0
TU		 2252 if (!plane_state)
2253 return 0;
2254
121920fa 2255 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2256 return 0;
2257
9abc4648 2258 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2259
2260 info->height = fb->height;
2261 info->pixel_format = fb->pixel_format;
2262 info->pitch = fb->pitches[0];
2263 info->fb_modifier = fb->modifier[0];
2264
84fe03f7
TU		 2265 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2266 fb->modifier[0]);
2267 tile_pitch = PAGE_SIZE / tile_height;
2268 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2269 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2270 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2271
f64b98cd
TU		 2272 return 0;
2273}
2274
4e9a86b6
VS		 2275static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2276{
2277 if (INTEL_INFO(dev_priv)->gen >= 9)
2278 return 256 * 1024;
985b8bb4
VS		 2279 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2280 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2281 return 128 * 1024;
2282 else if (INTEL_INFO(dev_priv)->gen >= 4)
2283 return 4 * 1024;
2284 else
44c5905e 2285 return 0;
4e9a86b6
VS		 2286}
2287
127bd2ac 2288int
850c4cdc
TU		 2289intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2290 struct drm_framebuffer *fb,
82bc3b2d 2291 const struct drm_plane_state *plane_state,
91af127f
JH		 2292 struct intel_engine_cs *pipelined,
2293 struct drm_i915_gem_request **pipelined_request)
6b95a207 2294{
850c4cdc 2295 struct drm_device *dev = fb->dev;
ce453d81 2296 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2297 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2298 struct i915_ggtt_view view;
6b95a207
KH		 2299 u32 alignment;
2300 int ret;
2301
ebcdd39e
MR		 2302 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2303
7b911adc
TU		 2304 switch (fb->modifier[0]) {
2305 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2306 alignment = intel_linear_alignment(dev_priv);
6b95a207 2307 break;
7b911adc 2308 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2309 if (INTEL_INFO(dev)->gen >= 9)
2310 alignment = 256 * 1024;
2311 else {
2312 /* pin() will align the object as required by fence */
2313 alignment = 0;
2314 }
6b95a207 2315 break;
7b911adc 2316 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2317 case I915_FORMAT_MOD_Yf_TILED:
2318 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2319 "Y tiling bo slipped through, driver bug!\n"))
2320 return -EINVAL;
2321 alignment = 1 * 1024 * 1024;
2322 break;
6b95a207 2323 default:
7b911adc
TU		 2324 MISSING_CASE(fb->modifier[0]);
2325 return -EINVAL;
6b95a207
KH		 2326 }
2327
f64b98cd
TU		 2328 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2329 if (ret)
2330 return ret;
2331
693db184
CW		 2332 /* Note that the w/a also requires 64 PTE of padding following the
2333 * bo. We currently fill all unused PTE with the shadow page and so
2334 * we should always have valid PTE following the scanout preventing
2335 * the VT-d warning.
2336 */
2337 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2338 alignment = 256 * 1024;
2339
d6dd6843
PZ		 2340 /*
2341 * Global gtt pte registers are special registers which actually forward
2342 * writes to a chunk of system memory. Which means that there is no risk
2343 * that the register values disappear as soon as we call
2344 * intel_runtime_pm_put(), so it is correct to wrap only the
2345 * pin/unpin/fence and not more.
2346 */
2347 intel_runtime_pm_get(dev_priv);
2348
ce453d81 2349 dev_priv->mm.interruptible = false;
e6617330 2350 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2351 pipelined_request, &view);
48b956c5 2352 if (ret)
ce453d81 2353 goto err_interruptible;
6b95a207
KH		 2354
2355 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2356 * fence, whereas 965+ only requires a fence if using
2357 * framebuffer compression. For simplicity, we always install
2358 * a fence as the cost is not that onerous.
2359 */
06d98131 2360 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2361 if (ret == -EDEADLK) {
2362 /*
2363 * -EDEADLK means there are no free fences
2364 * no pending flips.
2365 *
2366 * This is propagated to atomic, but it uses
2367 * -EDEADLK to force a locking recovery, so
2368 * change the returned error to -EBUSY.
2369 */
2370 ret = -EBUSY;
2371 goto err_unpin;
2372 } else if (ret)
9a5a53b3 2373 goto err_unpin;
1690e1eb 2374
9a5a53b3 2375 i915_gem_object_pin_fence(obj);
6b95a207 2376
ce453d81 2377 dev_priv->mm.interruptible = true;
d6dd6843 2378 intel_runtime_pm_put(dev_priv);
6b95a207 2379 return 0;
48b956c5
CW		 2380
2381err_unpin:
f64b98cd 2382 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2383err_interruptible:
2384 dev_priv->mm.interruptible = true;
d6dd6843 2385 intel_runtime_pm_put(dev_priv);
48b956c5 2386 return ret;
6b95a207
KH		 2387}
2388
82bc3b2d
TU		 2389static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2390 const struct drm_plane_state *plane_state)
1690e1eb 2391{
82bc3b2d 2392 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2393 struct i915_ggtt_view view;
2394 int ret;
82bc3b2d 2395
ebcdd39e
MR		 2396 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2397
f64b98cd
TU		 2398 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2399 WARN_ONCE(ret, "Couldn't get view from plane state!");
2400
1690e1eb 2401 i915_gem_object_unpin_fence(obj);
f64b98cd 2402 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2403}
2404
c2c75131
DV		 2405/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2406 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2407unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2408 int *x, int *y,
bc752862
CW		 2409 unsigned int tiling_mode,
2410 unsigned int cpp,
2411 unsigned int pitch)
c2c75131 2412{
bc752862
CW		 2413 if (tiling_mode != I915_TILING_NONE) {
2414 unsigned int tile_rows, tiles;
c2c75131 2415
bc752862
CW		 2416 tile_rows = *y / 8;
2417 *y %= 8;
c2c75131 2418
bc752862
CW		 2419 tiles = *x / (512/cpp);
2420 *x %= 512/cpp;
2421
2422 return tile_rows * pitch * 8 + tiles * 4096;
2423 } else {
4e9a86b6 2424 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2425 unsigned int offset;
2426
2427 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2428 *y = (offset & alignment) / pitch;
2429 *x = ((offset & alignment) - *y * pitch) / cpp;
2430 return offset & ~alignment;
bc752862 2431 }
c2c75131
DV		 2432}
2433
b35d63fa 2434static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2435{
2436 switch (format) {
2437 case DISPPLANE_8BPP:
2438 return DRM_FORMAT_C8;
2439 case DISPPLANE_BGRX555:
2440 return DRM_FORMAT_XRGB1555;
2441 case DISPPLANE_BGRX565:
2442 return DRM_FORMAT_RGB565;
2443 default:
2444 case DISPPLANE_BGRX888:
2445 return DRM_FORMAT_XRGB8888;
2446 case DISPPLANE_RGBX888:
2447 return DRM_FORMAT_XBGR8888;
2448 case DISPPLANE_BGRX101010:
2449 return DRM_FORMAT_XRGB2101010;
2450 case DISPPLANE_RGBX101010:
2451 return DRM_FORMAT_XBGR2101010;
2452 }
2453}
2454
bc8d7dff
DL		 2455static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2456{
2457 switch (format) {
2458 case PLANE_CTL_FORMAT_RGB_565:
2459 return DRM_FORMAT_RGB565;
2460 default:
2461 case PLANE_CTL_FORMAT_XRGB_8888:
2462 if (rgb_order) {
2463 if (alpha)
2464 return DRM_FORMAT_ABGR8888;
2465 else
2466 return DRM_FORMAT_XBGR8888;
2467 } else {
2468 if (alpha)
2469 return DRM_FORMAT_ARGB8888;
2470 else
2471 return DRM_FORMAT_XRGB8888;
2472 }
2473 case PLANE_CTL_FORMAT_XRGB_2101010:
2474 if (rgb_order)
2475 return DRM_FORMAT_XBGR2101010;
2476 else
2477 return DRM_FORMAT_XRGB2101010;
2478 }
2479}
2480
5724dbd1 2481static bool
f6936e29
DV		 2482intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2483 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2484{
2485 struct drm_device *dev = crtc->base.dev;
2486 struct drm_i915_gem_object *obj = NULL;
2487 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2488 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2489 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2490 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2491 PAGE_SIZE);
2492
2493 size_aligned -= base_aligned;
46f297fb 2494
ff2652ea
CW		 2495 if (plane_config->size == 0)
2496 return false;
2497
f37b5c2b
DV		 2498 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2499 base_aligned,
2500 base_aligned,
2501 size_aligned);
46f297fb 2502 if (!obj)
484b41dd 2503 return false;
46f297fb 2504
49af449b
DL		 2505 obj->tiling_mode = plane_config->tiling;
2506 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2507 obj->stride = fb->pitches[0];
46f297fb 2508
6bf129df
DL		 2509 mode_cmd.pixel_format = fb->pixel_format;
2510 mode_cmd.width = fb->width;
2511 mode_cmd.height = fb->height;
2512 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2513 mode_cmd.modifier[0] = fb->modifier[0];
2514 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2515
2516 mutex_lock(&dev->struct_mutex);
6bf129df 2517 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2518 &mode_cmd, obj)) {
46f297fb
JB		 2519 DRM_DEBUG_KMS("intel fb init failed\n");
2520 goto out_unref_obj;
2521 }
46f297fb 2522 mutex_unlock(&dev->struct_mutex);
484b41dd 2523
f6936e29 2524 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2525 return true;
46f297fb
JB		 2526
2527out_unref_obj:
2528 drm_gem_object_unreference(&obj->base);
2529 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2530 return false;
2531}
2532
afd65eb4
MR		 2533/* Update plane->state->fb to match plane->fb after driver-internal updates */
2534static void
2535update_state_fb(struct drm_plane *plane)
2536{
2537 if (plane->fb == plane->state->fb)
2538 return;
2539
2540 if (plane->state->fb)
2541 drm_framebuffer_unreference(plane->state->fb);
2542 plane->state->fb = plane->fb;
2543 if (plane->state->fb)
2544 drm_framebuffer_reference(plane->state->fb);
2545}
2546
5724dbd1 2547static void
f6936e29
DV		 2548intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2549 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2550{
2551 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2552 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2553 struct drm_crtc *c;
2554 struct intel_crtc *i;
2ff8fde1 2555 struct drm_i915_gem_object *obj;
88595ac9 2556 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2557 struct drm_plane_state *plane_state = primary->state;
88595ac9 2558 struct drm_framebuffer *fb;
484b41dd 2559
2d14030b 2560 if (!plane_config->fb)
484b41dd
JB		 2561 return;
2562
f6936e29 2563 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2564 fb = &plane_config->fb->base;
2565 goto valid_fb;
f55548b5 2566 }
484b41dd 2567
2d14030b 2568 kfree(plane_config->fb);
484b41dd
JB		 2569
2570 /*
2571 * Failed to alloc the obj, check to see if we should share
2572 * an fb with another CRTC instead
2573 */
70e1e0ec 2574 for_each_crtc(dev, c) {
484b41dd
JB		 2575 i = to_intel_crtc(c);
2576
2577 if (c == &intel_crtc->base)
2578 continue;
2579
2ff8fde1
MR		 2580 if (!i->active)
2581 continue;
2582
88595ac9
DV		 2583 fb = c->primary->fb;
2584 if (!fb)
484b41dd
JB		 2585 continue;
2586
88595ac9 2587 obj = intel_fb_obj(fb);
2ff8fde1 2588 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2589 drm_framebuffer_reference(fb);
2590 goto valid_fb;
484b41dd
JB		 2591 }
2592 }
88595ac9
DV		 2593
2594 return;
2595
2596valid_fb:
be5651f2
ML		 2597 plane_state->src_x = plane_state->src_y = 0;
2598 plane_state->src_w = fb->width << 16;
2599 plane_state->src_h = fb->height << 16;
2600
2601 plane_state->crtc_x = plane_state->src_y = 0;
2602 plane_state->crtc_w = fb->width;
2603 plane_state->crtc_h = fb->height;
2604
88595ac9
DV		 2605 obj = intel_fb_obj(fb);
2606 if (obj->tiling_mode != I915_TILING_NONE)
2607 dev_priv->preserve_bios_swizzle = true;
2608
be5651f2
ML		 2609 drm_framebuffer_reference(fb);
2610 primary->fb = primary->state->fb = fb;
36750f28 2611 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2612 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2613 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2614}
2615
29b9bde6
DV		 2616static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2617 struct drm_framebuffer *fb,
2618 int x, int y)
81255565
JB		 2619{
2620 struct drm_device *dev = crtc->dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
2622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2623 struct drm_plane *primary = crtc->primary;
2624 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2625 struct drm_i915_gem_object *obj;
81255565 2626 int plane = intel_crtc->plane;
e506a0c6 2627 unsigned long linear_offset;
81255565 2628 u32 dspcntr;
f45651ba 2629 u32 reg = DSPCNTR(plane);
48404c1e 2630 int pixel_size;
f45651ba 2631
b70709a6 2632 if (!visible || !fb) {
fdd508a6
VS		 2633 I915_WRITE(reg, 0);
2634 if (INTEL_INFO(dev)->gen >= 4)
2635 I915_WRITE(DSPSURF(plane), 0);
2636 else
2637 I915_WRITE(DSPADDR(plane), 0);
2638 POSTING_READ(reg);
2639 return;
2640 }
2641
c9ba6fad
VS		 2642 obj = intel_fb_obj(fb);
2643 if (WARN_ON(obj == NULL))
2644 return;
2645
2646 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2647
f45651ba
VS		 2648 dspcntr = DISPPLANE_GAMMA_ENABLE;
2649
fdd508a6 2650 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2651
2652 if (INTEL_INFO(dev)->gen < 4) {
2653 if (intel_crtc->pipe == PIPE_B)
2654 dspcntr |= DISPPLANE_SEL_PIPE_B;
2655
2656 /* pipesrc and dspsize control the size that is scaled from,
2657 * which should always be the user's requested size.
2658 */
2659 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2660 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2661 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2662 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2663 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2664 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2665 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2666 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2667 I915_WRITE(PRIMPOS(plane), 0);
2668 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2669 }
81255565 2670
57779d06
VS		 2671 switch (fb->pixel_format) {
2672 case DRM_FORMAT_C8:
81255565
JB		 2673 dspcntr |= DISPPLANE_8BPP;
2674 break;
57779d06 2675 case DRM_FORMAT_XRGB1555:
57779d06 2676 dspcntr |= DISPPLANE_BGRX555;
81255565 2677 break;
57779d06
VS		 2678 case DRM_FORMAT_RGB565:
2679 dspcntr |= DISPPLANE_BGRX565;
2680 break;
2681 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2682 dspcntr |= DISPPLANE_BGRX888;
2683 break;
2684 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2685 dspcntr |= DISPPLANE_RGBX888;
2686 break;
2687 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2688 dspcntr |= DISPPLANE_BGRX101010;
2689 break;
2690 case DRM_FORMAT_XBGR2101010:
57779d06 2691 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2692 break;
2693 default:
baba133a 2694 BUG();
81255565 2695 }
57779d06 2696
f45651ba
VS		 2697 if (INTEL_INFO(dev)->gen >= 4 &&
2698 obj->tiling_mode != I915_TILING_NONE)
2699 dspcntr |= DISPPLANE_TILED;
81255565 2700
de1aa629
VS		 2701 if (IS_G4X(dev))
2702 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2703
b9897127 2704 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2705
c2c75131
DV		 2706 if (INTEL_INFO(dev)->gen >= 4) {
2707 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2708 intel_gen4_compute_page_offset(dev_priv,
2709 &x, &y, obj->tiling_mode,
b9897127 2710 pixel_size,
bc752862 2711 fb->pitches[0]);
c2c75131
DV		 2712 linear_offset -= intel_crtc->dspaddr_offset;
2713 } else {
e506a0c6 2714 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2715 }
e506a0c6 2716
8e7d688b 2717 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2718 dspcntr |= DISPPLANE_ROTATE_180;
2719
6e3c9717
ACO		 2720 x += (intel_crtc->config->pipe_src_w - 1);
2721 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2722
2723 /* Finding the last pixel of the last line of the display
2724 data and adding to linear_offset*/
2725 linear_offset +=
6e3c9717
ACO		 2726 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2727 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2728 }
2729
2730 I915_WRITE(reg, dspcntr);
2731
01f2c773 2732 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2733 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2734 I915_WRITE(DSPSURF(plane),
2735 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2736 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2737 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2738 } else
f343c5f6 2739 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2740 POSTING_READ(reg);
17638cd6
JB		 2741}
2742
29b9bde6
DV		 2743static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2744 struct drm_framebuffer *fb,
2745 int x, int y)
17638cd6
JB		 2746{
2747 struct drm_device *dev = crtc->dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2750 struct drm_plane *primary = crtc->primary;
2751 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2752 struct drm_i915_gem_object *obj;
17638cd6 2753 int plane = intel_crtc->plane;
e506a0c6 2754 unsigned long linear_offset;
17638cd6 2755 u32 dspcntr;
f45651ba 2756 u32 reg = DSPCNTR(plane);
48404c1e 2757 int pixel_size;
f45651ba 2758
b70709a6 2759 if (!visible || !fb) {
fdd508a6
VS		 2760 I915_WRITE(reg, 0);
2761 I915_WRITE(DSPSURF(plane), 0);
2762 POSTING_READ(reg);
2763 return;
2764 }
2765
c9ba6fad
VS		 2766 obj = intel_fb_obj(fb);
2767 if (WARN_ON(obj == NULL))
2768 return;
2769
2770 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2771
f45651ba
VS		 2772 dspcntr = DISPPLANE_GAMMA_ENABLE;
2773
fdd508a6 2774 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2775
2776 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2777 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2778
57779d06
VS		 2779 switch (fb->pixel_format) {
2780 case DRM_FORMAT_C8:
17638cd6
JB		 2781 dspcntr |= DISPPLANE_8BPP;
2782 break;
57779d06
VS		 2783 case DRM_FORMAT_RGB565:
2784 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2785 break;
57779d06 2786 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2787 dspcntr |= DISPPLANE_BGRX888;
2788 break;
2789 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2790 dspcntr |= DISPPLANE_RGBX888;
2791 break;
2792 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2793 dspcntr |= DISPPLANE_BGRX101010;
2794 break;
2795 case DRM_FORMAT_XBGR2101010:
57779d06 2796 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2797 break;
2798 default:
baba133a 2799 BUG();
17638cd6
JB		 2800 }
2801
2802 if (obj->tiling_mode != I915_TILING_NONE)
2803 dspcntr |= DISPPLANE_TILED;
17638cd6 2804
f45651ba 2805 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2806 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2807
b9897127 2808 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2809 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2810 intel_gen4_compute_page_offset(dev_priv,
2811 &x, &y, obj->tiling_mode,
b9897127 2812 pixel_size,
bc752862 2813 fb->pitches[0]);
c2c75131 2814 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2815 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2816 dspcntr |= DISPPLANE_ROTATE_180;
2817
2818 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2819 x += (intel_crtc->config->pipe_src_w - 1);
2820 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2821
2822 /* Finding the last pixel of the last line of the display
2823 data and adding to linear_offset*/
2824 linear_offset +=
6e3c9717
ACO		 2825 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2826 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2827 }
2828 }
2829
2830 I915_WRITE(reg, dspcntr);
17638cd6 2831
01f2c773 2832 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2833 I915_WRITE(DSPSURF(plane),
2834 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2835 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2836 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2837 } else {
2838 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2839 I915_WRITE(DSPLINOFF(plane), linear_offset);
2840 }
17638cd6 2841 POSTING_READ(reg);
17638cd6
JB		 2842}
2843
b321803d
DL		 2844u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2845 uint32_t pixel_format)
2846{
2847 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2848
2849 /*
2850 * The stride is either expressed as a multiple of 64 bytes
2851 * chunks for linear buffers or in number of tiles for tiled
2852 * buffers.
2853 */
2854 switch (fb_modifier) {
2855 case DRM_FORMAT_MOD_NONE:
2856 return 64;
2857 case I915_FORMAT_MOD_X_TILED:
2858 if (INTEL_INFO(dev)->gen == 2)
2859 return 128;
2860 return 512;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 /* No need to check for old gens and Y tiling since this is
2863 * about the display engine and those will be blocked before
2864 * we get here.
2865 */
2866 return 128;
2867 case I915_FORMAT_MOD_Yf_TILED:
2868 if (bits_per_pixel == 8)
2869 return 64;
2870 else
2871 return 128;
2872 default:
2873 MISSING_CASE(fb_modifier);
2874 return 64;
2875 }
2876}
2877
121920fa
TU		 2878unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2879 struct drm_i915_gem_object *obj)
2880{
9abc4648 2881 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2882
2883 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2884 view = &i915_ggtt_view_rotated;
121920fa
TU		 2885
2886 return i915_gem_obj_ggtt_offset_view(obj, view);
2887}
2888
e435d6e5
ML		 2889static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2890{
2891 struct drm_device *dev = intel_crtc->base.dev;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893
2894 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2895 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2896 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2897}
2898
a1b2278e
CK		 2899/*
2900 * This function detaches (aka. unbinds) unused scalers in hardware
2901 */
0583236e 2902static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2903{
a1b2278e
CK		 2904 struct intel_crtc_scaler_state *scaler_state;
2905 int i;
2906
a1b2278e
CK		 2907 scaler_state = &intel_crtc->config->scaler_state;
2908
2909 /* loop through and disable scalers that aren't in use */
2910 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2911 if (!scaler_state->scalers[i].in_use)
2912 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2913 }
2914}
2915
6156a456 2916u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2917{
6156a456 2918 switch (pixel_format) {
d161cf7a 2919 case DRM_FORMAT_C8:
c34ce3d1 2920 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2921 case DRM_FORMAT_RGB565:
c34ce3d1 2922 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2923 case DRM_FORMAT_XBGR8888:
c34ce3d1 2924 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2925 case DRM_FORMAT_XRGB8888:
c34ce3d1 2926 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2927 /*
2928 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2929 * to be already pre-multiplied. We need to add a knob (or a different
2930 * DRM_FORMAT) for user-space to configure that.
2931 */
f75fb42a 2932 case DRM_FORMAT_ABGR8888:
c34ce3d1 2933 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2934 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2935 case DRM_FORMAT_ARGB8888:
c34ce3d1 2936 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2937 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2938 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2939 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2940 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2941 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2942 case DRM_FORMAT_YUYV:
c34ce3d1 2943 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2944 case DRM_FORMAT_YVYU:
c34ce3d1 2945 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2946 case DRM_FORMAT_UYVY:
c34ce3d1 2947 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2948 case DRM_FORMAT_VYUY:
c34ce3d1 2949 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2950 default:
4249eeef 2951 MISSING_CASE(pixel_format);
70d21f0e 2952 }
8cfcba41 2953
c34ce3d1 2954 return 0;
6156a456 2955}
70d21f0e 2956
6156a456
CK		 2957u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2958{
6156a456 2959 switch (fb_modifier) {
30af77c4 2960 case DRM_FORMAT_MOD_NONE:
70d21f0e 2961 break;
30af77c4 2962 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2963 return PLANE_CTL_TILED_X;
b321803d 2964 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2965 return PLANE_CTL_TILED_Y;
b321803d 2966 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2967 return PLANE_CTL_TILED_YF;
70d21f0e 2968 default:
6156a456 2969 MISSING_CASE(fb_modifier);
70d21f0e 2970 }
8cfcba41 2971
c34ce3d1 2972 return 0;
6156a456 2973}
70d21f0e 2974
6156a456
CK		 2975u32 skl_plane_ctl_rotation(unsigned int rotation)
2976{
3b7a5119 2977 switch (rotation) {
6156a456
CK		 2978 case BIT(DRM_ROTATE_0):
2979 break;
1e8df167
SJ		 2980 /*
2981 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2982 * while i915 HW rotation is clockwise, thats why this swapping.
2983 */
3b7a5119 2984 case BIT(DRM_ROTATE_90):
1e8df167 2985 return PLANE_CTL_ROTATE_270;
3b7a5119 2986 case BIT(DRM_ROTATE_180):
c34ce3d1 2987 return PLANE_CTL_ROTATE_180;
3b7a5119 2988 case BIT(DRM_ROTATE_270):
1e8df167 2989 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2990 default:
2991 MISSING_CASE(rotation);
2992 }
2993
c34ce3d1 2994 return 0;
6156a456
CK		 2995}
2996
2997static void skylake_update_primary_plane(struct drm_crtc *crtc,
2998 struct drm_framebuffer *fb,
2999 int x, int y)
3000{
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3004 struct drm_plane *plane = crtc->primary;
3005 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3006 struct drm_i915_gem_object *obj;
3007 int pipe = intel_crtc->pipe;
3008 u32 plane_ctl, stride_div, stride;
3009 u32 tile_height, plane_offset, plane_size;
3010 unsigned int rotation;
3011 int x_offset, y_offset;
3012 unsigned long surf_addr;
6156a456
CK		 3013 struct intel_crtc_state *crtc_state = intel_crtc->config;
3014 struct intel_plane_state *plane_state;
3015 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3016 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3017 int scaler_id = -1;
3018
6156a456
CK		 3019 plane_state = to_intel_plane_state(plane->state);
3020
b70709a6 3021 if (!visible || !fb) {
6156a456
CK		 3022 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3023 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3024 POSTING_READ(PLANE_CTL(pipe, 0));
3025 return;
3b7a5119 3026 }
70d21f0e 3027
6156a456
CK		 3028 plane_ctl = PLANE_CTL_ENABLE |
3029 PLANE_CTL_PIPE_GAMMA_ENABLE |
3030 PLANE_CTL_PIPE_CSC_ENABLE;
3031
3032 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3033 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3034 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3035
3036 rotation = plane->state->rotation;
3037 plane_ctl |= skl_plane_ctl_rotation(rotation);
3038
b321803d
DL		 3039 obj = intel_fb_obj(fb);
3040 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3041 fb->pixel_format);
3b7a5119
SJ		 3042 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3043
6156a456
CK		 3044 /*
3045 * FIXME: intel_plane_state->src, dst aren't set when transitional
3046 * update_plane helpers are called from legacy paths.
3047 * Once full atomic crtc is available, below check can be avoided.
3048 */
3049 if (drm_rect_width(&plane_state->src)) {
3050 scaler_id = plane_state->scaler_id;
3051 src_x = plane_state->src.x1 >> 16;
3052 src_y = plane_state->src.y1 >> 16;
3053 src_w = drm_rect_width(&plane_state->src) >> 16;
3054 src_h = drm_rect_height(&plane_state->src) >> 16;
3055 dst_x = plane_state->dst.x1;
3056 dst_y = plane_state->dst.y1;
3057 dst_w = drm_rect_width(&plane_state->dst);
3058 dst_h = drm_rect_height(&plane_state->dst);
3059
3060 WARN_ON(x != src_x || y != src_y);
3061 } else {
3062 src_w = intel_crtc->config->pipe_src_w;
3063 src_h = intel_crtc->config->pipe_src_h;
3064 }
3065
3b7a5119
SJ		 3066 if (intel_rotation_90_or_270(rotation)) {
3067 /* stride = Surface height in tiles */
2614f17d 3068 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3069 fb->modifier[0]);
3070 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3071 x_offset = stride * tile_height - y - src_h;
3b7a5119 3072 y_offset = x;
6156a456 3073 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3074 } else {
3075 stride = fb->pitches[0] / stride_div;
3076 x_offset = x;
3077 y_offset = y;
6156a456 3078 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3079 }
3080 plane_offset = y_offset << 16 | x_offset;
b321803d 3081
70d21f0e 3082 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3083 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3084 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3085 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3086
3087 if (scaler_id >= 0) {
3088 uint32_t ps_ctrl = 0;
3089
3090 WARN_ON(!dst_w || !dst_h);
3091 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3092 crtc_state->scaler_state.scalers[scaler_id].mode;
3093 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3094 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3095 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3096 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3097 I915_WRITE(PLANE_POS(pipe, 0), 0);
3098 } else {
3099 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3100 }
3101
121920fa 3102 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3103
3104 POSTING_READ(PLANE_SURF(pipe, 0));
3105}
3106
17638cd6
JB		 3107/* Assume fb object is pinned & idle & fenced and just update base pointers */
3108static int
3109intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3110 int x, int y, enum mode_set_atomic state)
3111{
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3114
ff2a3117 3115 if (dev_priv->fbc.disable_fbc)
7733b49b 3116 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3117
29b9bde6
DV		 3118 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3119
3120 return 0;
81255565
JB		 3121}
3122
7514747d 3123static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3124{
96a02917
VS		 3125 struct drm_crtc *crtc;
3126
70e1e0ec 3127 for_each_crtc(dev, crtc) {
96a02917
VS		 3128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3129 enum plane plane = intel_crtc->plane;
3130
3131 intel_prepare_page_flip(dev, plane);
3132 intel_finish_page_flip_plane(dev, plane);
3133 }
7514747d
VS		 3134}
3135
3136static void intel_update_primary_planes(struct drm_device *dev)
3137{
7514747d 3138 struct drm_crtc *crtc;
96a02917 3139
70e1e0ec 3140 for_each_crtc(dev, crtc) {
11c22da6
ML		 3141 struct intel_plane *plane = to_intel_plane(crtc->primary);
3142 struct intel_plane_state *plane_state;
96a02917 3143
11c22da6
ML		 3144 drm_modeset_lock_crtc(crtc, &plane->base);
3145
3146 plane_state = to_intel_plane_state(plane->base.state);
3147
3148 if (plane_state->base.fb)
3149 plane->commit_plane(&plane->base, plane_state);
3150
3151 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3152 }
3153}
3154
7514747d
VS		 3155void intel_prepare_reset(struct drm_device *dev)
3156{
3157 /* no reset support for gen2 */
3158 if (IS_GEN2(dev))
3159 return;
3160
3161 /* reset doesn't touch the display */
3162 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3163 return;
3164
3165 drm_modeset_lock_all(dev);
f98ce92f
VS		 3166 /*
3167 * Disabling the crtcs gracefully seems nicer. Also the
3168 * g33 docs say we should at least disable all the planes.
3169 */
6b72d486 3170 intel_display_suspend(dev);
7514747d
VS		 3171}
3172
3173void intel_finish_reset(struct drm_device *dev)
3174{
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177 /*
3178 * Flips in the rings will be nuked by the reset,
3179 * so complete all pending flips so that user space
3180 * will get its events and not get stuck.
3181 */
3182 intel_complete_page_flips(dev);
3183
3184 /* no reset support for gen2 */
3185 if (IS_GEN2(dev))
3186 return;
3187
3188 /* reset doesn't touch the display */
3189 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3190 /*
3191 * Flips in the rings have been nuked by the reset,
3192 * so update the base address of all primary
3193 * planes to the the last fb to make sure we're
3194 * showing the correct fb after a reset.
11c22da6
ML		 3195 *
3196 * FIXME: Atomic will make this obsolete since we won't schedule
3197 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3198 */
3199 intel_update_primary_planes(dev);
3200 return;
3201 }
3202
3203 /*
3204 * The display has been reset as well,
3205 * so need a full re-initialization.
3206 */
3207 intel_runtime_pm_disable_interrupts(dev_priv);
3208 intel_runtime_pm_enable_interrupts(dev_priv);
3209
3210 intel_modeset_init_hw(dev);
3211
3212 spin_lock_irq(&dev_priv->irq_lock);
3213 if (dev_priv->display.hpd_irq_setup)
3214 dev_priv->display.hpd_irq_setup(dev);
3215 spin_unlock_irq(&dev_priv->irq_lock);
3216
043e9bda 3217 intel_display_resume(dev);
7514747d
VS		 3218
3219 intel_hpd_init(dev_priv);
3220
3221 drm_modeset_unlock_all(dev);
3222}
3223
2e2f351d 3224static void
14667a4b
CW		 3225intel_finish_fb(struct drm_framebuffer *old_fb)
3226{
2ff8fde1 3227 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3228 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3229 bool was_interruptible = dev_priv->mm.interruptible;
3230 int ret;
3231
14667a4b
CW		 3232 /* Big Hammer, we also need to ensure that any pending
3233 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3234 * current scanout is retired before unpinning the old
2e2f351d
CW		 3235 * framebuffer. Note that we rely on userspace rendering
3236 * into the buffer attached to the pipe they are waiting
3237 * on. If not, userspace generates a GPU hang with IPEHR
3238 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3239 *
3240 * This should only fail upon a hung GPU, in which case we
3241 * can safely continue.
3242 */
3243 dev_priv->mm.interruptible = false;
2e2f351d 3244 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3245 dev_priv->mm.interruptible = was_interruptible;
3246
2e2f351d 3247 WARN_ON(ret);
14667a4b
CW		 3248}
3249
7d5e3799
CW		 3250static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3251{
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3255 bool pending;
3256
3257 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3258 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3259 return false;
3260
5e2d7afc 3261 spin_lock_irq(&dev->event_lock);
7d5e3799 3262 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3263 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3264
3265 return pending;
3266}
3267
e30e8f75
GP		 3268static void intel_update_pipe_size(struct intel_crtc *crtc)
3269{
3270 struct drm_device *dev = crtc->base.dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 const struct drm_display_mode *adjusted_mode;
3273
3274 if (!i915.fastboot)
3275 return;
3276
44522d85
ML		 3277 if (HAS_DDI(dev))
3278 intel_set_pipe_csc(&crtc->base);
3279
e30e8f75
GP		 3280 /*
3281 * Update pipe size and adjust fitter if needed: the reason for this is
3282 * that in compute_mode_changes we check the native mode (not the pfit
3283 * mode) to see if we can flip rather than do a full mode set. In the
3284 * fastboot case, we'll flip, but if we don't update the pipesrc and
3285 * pfit state, we'll end up with a big fb scanned out into the wrong
3286 * sized surface.
3287 *
3288 * To fix this properly, we need to hoist the checks up into
3289 * compute_mode_changes (or above), check the actual pfit state and
3290 * whether the platform allows pfit disable with pipe active, and only
3291 * then update the pipesrc and pfit state, even on the flip path.
3292 */
3293
6e3c9717 3294 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3295
3296 I915_WRITE(PIPESRC(crtc->pipe),
3297 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3298 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3299 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3300 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3301 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3302 I915_WRITE(PF_CTL(crtc->pipe), 0);
3303 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3304 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3305 }
6e3c9717
ACO		 3306 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3307 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3308}
3309
5e84e1a4
ZW		 3310static void intel_fdi_normal_train(struct drm_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315 int pipe = intel_crtc->pipe;
3316 u32 reg, temp;
3317
3318 /* enable normal train */
3319 reg = FDI_TX_CTL(pipe);
3320 temp = I915_READ(reg);
61e499bf 3321 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3322 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3323 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3324 } else {
3325 temp &= ~FDI_LINK_TRAIN_NONE;
3326 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3327 }
5e84e1a4
ZW		 3328 I915_WRITE(reg, temp);
3329
3330 reg = FDI_RX_CTL(pipe);
3331 temp = I915_READ(reg);
3332 if (HAS_PCH_CPT(dev)) {
3333 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3334 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3335 } else {
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_NONE;
3338 }
3339 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3340
3341 /* wait one idle pattern time */
3342 POSTING_READ(reg);
3343 udelay(1000);
357555c0
JB		 3344
3345 /* IVB wants error correction enabled */
3346 if (IS_IVYBRIDGE(dev))
3347 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3348 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3349}
3350
8db9d77b
ZW		 3351/* The FDI link training functions for ILK/Ibexpeak. */
3352static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3353{
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
5eddb70b 3358 u32 reg, temp, tries;
8db9d77b 3359
1c8562f6 3360 /* FDI needs bits from pipe first */
0fc932b8 3361 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3362
e1a44743
AJ		 3363 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3364 for train result */
5eddb70b
CW		 3365 reg = FDI_RX_IMR(pipe);
3366 temp = I915_READ(reg);
e1a44743
AJ		 3367 temp &= ~FDI_RX_SYMBOL_LOCK;
3368 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3369 I915_WRITE(reg, temp);
3370 I915_READ(reg);
e1a44743
AJ		 3371 udelay(150);
3372
8db9d77b 3373 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3374 reg = FDI_TX_CTL(pipe);
3375 temp = I915_READ(reg);
627eb5a3 3376 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3377 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3380 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3381
5eddb70b
CW		 3382 reg = FDI_RX_CTL(pipe);
3383 temp = I915_READ(reg);
8db9d77b
ZW		 3384 temp &= ~FDI_LINK_TRAIN_NONE;
3385 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3386 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3387
3388 POSTING_READ(reg);
8db9d77b
ZW		 3389 udelay(150);
3390
5b2adf89 3391 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3392 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3393 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3394 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3395
5eddb70b 3396 reg = FDI_RX_IIR(pipe);
e1a44743 3397 for (tries = 0; tries < 5; tries++) {
5eddb70b 3398 temp = I915_READ(reg);
8db9d77b
ZW		 3399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3400
3401 if ((temp & FDI_RX_BIT_LOCK)) {
3402 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3403 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3404 break;
3405 }
8db9d77b 3406 }
e1a44743 3407 if (tries == 5)
5eddb70b 3408 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3409
3410 /* Train 2 */
5eddb70b
CW		 3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
8db9d77b
ZW		 3413 temp &= ~FDI_LINK_TRAIN_NONE;
3414 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3415 I915_WRITE(reg, temp);
8db9d77b 3416
5eddb70b
CW		 3417 reg = FDI_RX_CTL(pipe);
3418 temp = I915_READ(reg);
8db9d77b
ZW		 3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3421 I915_WRITE(reg, temp);
8db9d77b 3422
5eddb70b
CW		 3423 POSTING_READ(reg);
3424 udelay(150);
8db9d77b 3425
5eddb70b 3426 reg = FDI_RX_IIR(pipe);
e1a44743 3427 for (tries = 0; tries < 5; tries++) {
5eddb70b 3428 temp = I915_READ(reg);
8db9d77b
ZW		 3429 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3430
3431 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3432 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3433 DRM_DEBUG_KMS("FDI train 2 done.\n");
3434 break;
3435 }
8db9d77b 3436 }
e1a44743 3437 if (tries == 5)
5eddb70b 3438 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3439
3440 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3441
8db9d77b
ZW		 3442}
3443
0206e353 3444static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3445 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3446 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3447 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3448 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3449};
3450
3451/* The FDI link training functions for SNB/Cougarpoint. */
3452static void gen6_fdi_link_train(struct drm_crtc *crtc)
3453{
3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457 int pipe = intel_crtc->pipe;
fa37d39e 3458 u32 reg, temp, i, retry;
8db9d77b 3459
e1a44743
AJ		 3460 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3461 for train result */
5eddb70b
CW		 3462 reg = FDI_RX_IMR(pipe);
3463 temp = I915_READ(reg);
e1a44743
AJ		 3464 temp &= ~FDI_RX_SYMBOL_LOCK;
3465 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3466 I915_WRITE(reg, temp);
3467
3468 POSTING_READ(reg);
e1a44743
AJ		 3469 udelay(150);
3470
8db9d77b 3471 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3472 reg = FDI_TX_CTL(pipe);
3473 temp = I915_READ(reg);
627eb5a3 3474 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3475 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3476 temp &= ~FDI_LINK_TRAIN_NONE;
3477 temp |= FDI_LINK_TRAIN_PATTERN_1;
3478 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3479 /* SNB-B */
3480 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3482
d74cf324
DV		 3483 I915_WRITE(FDI_RX_MISC(pipe),
3484 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3485
5eddb70b
CW		 3486 reg = FDI_RX_CTL(pipe);
3487 temp = I915_READ(reg);
8db9d77b
ZW		 3488 if (HAS_PCH_CPT(dev)) {
3489 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3491 } else {
3492 temp &= ~FDI_LINK_TRAIN_NONE;
3493 temp |= FDI_LINK_TRAIN_PATTERN_1;
3494 }
5eddb70b
CW		 3495 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3496
3497 POSTING_READ(reg);
8db9d77b
ZW		 3498 udelay(150);
3499
0206e353 3500 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3501 reg = FDI_TX_CTL(pipe);
3502 temp = I915_READ(reg);
8db9d77b
ZW		 3503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3504 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3505 I915_WRITE(reg, temp);
3506
3507 POSTING_READ(reg);
8db9d77b
ZW		 3508 udelay(500);
3509
fa37d39e
SP		 3510 for (retry = 0; retry < 5; retry++) {
3511 reg = FDI_RX_IIR(pipe);
3512 temp = I915_READ(reg);
3513 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3514 if (temp & FDI_RX_BIT_LOCK) {
3515 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3516 DRM_DEBUG_KMS("FDI train 1 done.\n");
3517 break;
3518 }
3519 udelay(50);
8db9d77b 3520 }
fa37d39e
SP		 3521 if (retry < 5)
3522 break;
8db9d77b
ZW		 3523 }
3524 if (i == 4)
5eddb70b 3525 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3526
3527 /* Train 2 */
5eddb70b
CW		 3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_2;
3532 if (IS_GEN6(dev)) {
3533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3534 /* SNB-B */
3535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3536 }
5eddb70b 3537 I915_WRITE(reg, temp);
8db9d77b 3538
5eddb70b
CW		 3539 reg = FDI_RX_CTL(pipe);
3540 temp = I915_READ(reg);
8db9d77b
ZW		 3541 if (HAS_PCH_CPT(dev)) {
3542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3543 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3544 } else {
3545 temp &= ~FDI_LINK_TRAIN_NONE;
3546 temp |= FDI_LINK_TRAIN_PATTERN_2;
3547 }
5eddb70b
CW		 3548 I915_WRITE(reg, temp);
3549
3550 POSTING_READ(reg);
8db9d77b
ZW		 3551 udelay(150);
3552
0206e353 3553 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
8db9d77b
ZW		 3556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3557 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3558 I915_WRITE(reg, temp);
3559
3560 POSTING_READ(reg);
8db9d77b
ZW		 3561 udelay(500);
3562
fa37d39e
SP		 3563 for (retry = 0; retry < 5; retry++) {
3564 reg = FDI_RX_IIR(pipe);
3565 temp = I915_READ(reg);
3566 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3567 if (temp & FDI_RX_SYMBOL_LOCK) {
3568 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3569 DRM_DEBUG_KMS("FDI train 2 done.\n");
3570 break;
3571 }
3572 udelay(50);
8db9d77b 3573 }
fa37d39e
SP		 3574 if (retry < 5)
3575 break;
8db9d77b
ZW		 3576 }
3577 if (i == 4)
5eddb70b 3578 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3579
3580 DRM_DEBUG_KMS("FDI train done.\n");
3581}
3582
357555c0
JB		 3583/* Manual link training for Ivy Bridge A0 parts */
3584static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3585{
3586 struct drm_device *dev = crtc->dev;
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3589 int pipe = intel_crtc->pipe;
139ccd3f 3590 u32 reg, temp, i, j;
357555c0
JB		 3591
3592 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3593 for train result */
3594 reg = FDI_RX_IMR(pipe);
3595 temp = I915_READ(reg);
3596 temp &= ~FDI_RX_SYMBOL_LOCK;
3597 temp &= ~FDI_RX_BIT_LOCK;
3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
3601 udelay(150);
3602
01a415fd
DV		 3603 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3604 I915_READ(FDI_RX_IIR(pipe)));
3605
139ccd3f
JB		 3606 /* Try each vswing and preemphasis setting twice before moving on */
3607 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3608 /* disable first in case we need to retry */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3612 temp &= ~FDI_TX_ENABLE;
3613 I915_WRITE(reg, temp);
357555c0 3614
139ccd3f
JB		 3615 reg = FDI_RX_CTL(pipe);
3616 temp = I915_READ(reg);
3617 temp &= ~FDI_LINK_TRAIN_AUTO;
3618 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3619 temp &= ~FDI_RX_ENABLE;
3620 I915_WRITE(reg, temp);
357555c0 3621
139ccd3f 3622 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3623 reg = FDI_TX_CTL(pipe);
3624 temp = I915_READ(reg);
139ccd3f 3625 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3626 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3627 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3629 temp |= snb_b_fdi_train_param[j/2];
3630 temp |= FDI_COMPOSITE_SYNC;
3631 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3632
139ccd3f
JB		 3633 I915_WRITE(FDI_RX_MISC(pipe),
3634 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3635
139ccd3f 3636 reg = FDI_RX_CTL(pipe);
357555c0 3637 temp = I915_READ(reg);
139ccd3f
JB		 3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639 temp |= FDI_COMPOSITE_SYNC;
3640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3641
139ccd3f
JB		 3642 POSTING_READ(reg);
3643 udelay(1); /* should be 0.5us */
357555c0 3644
139ccd3f
JB		 3645 for (i = 0; i < 4; i++) {
3646 reg = FDI_RX_IIR(pipe);
3647 temp = I915_READ(reg);
3648 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3649
139ccd3f
JB		 3650 if (temp & FDI_RX_BIT_LOCK ||
3651 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3652 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3653 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3654 i);
3655 break;
3656 }
3657 udelay(1); /* should be 0.5us */
3658 }
3659 if (i == 4) {
3660 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3661 continue;
3662 }
357555c0 3663
139ccd3f 3664 /* Train 2 */
357555c0
JB		 3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
139ccd3f
JB		 3667 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3668 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3669 I915_WRITE(reg, temp);
3670
3671 reg = FDI_RX_CTL(pipe);
3672 temp = I915_READ(reg);
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3675 I915_WRITE(reg, temp);
3676
3677 POSTING_READ(reg);
139ccd3f 3678 udelay(2); /* should be 1.5us */
357555c0 3679
139ccd3f
JB		 3680 for (i = 0; i < 4; i++) {
3681 reg = FDI_RX_IIR(pipe);
3682 temp = I915_READ(reg);
3683 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3684
139ccd3f
JB		 3685 if (temp & FDI_RX_SYMBOL_LOCK ||
3686 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3687 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3688 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3689 i);
3690 goto train_done;
3691 }
3692 udelay(2); /* should be 1.5us */
357555c0 3693 }
139ccd3f
JB		 3694 if (i == 4)
3695 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3696 }
357555c0 3697
139ccd3f 3698train_done:
357555c0
JB		 3699 DRM_DEBUG_KMS("FDI train done.\n");
3700}
3701
88cefb6c 3702static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3703{
88cefb6c 3704 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3705 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3706 int pipe = intel_crtc->pipe;
5eddb70b 3707 u32 reg, temp;
79e53945 3708
c64e311e 3709
c98e9dcf 3710 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
627eb5a3 3713 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3714 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3715 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3716 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3717
3718 POSTING_READ(reg);
c98e9dcf
JB		 3719 udelay(200);
3720
3721 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3722 temp = I915_READ(reg);
3723 I915_WRITE(reg, temp | FDI_PCDCLK);
3724
3725 POSTING_READ(reg);
c98e9dcf
JB		 3726 udelay(200);
3727
20749730
PZ		 3728 /* Enable CPU FDI TX PLL, always on for Ironlake */
3729 reg = FDI_TX_CTL(pipe);
3730 temp = I915_READ(reg);
3731 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3732 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3733
20749730
PZ		 3734 POSTING_READ(reg);
3735 udelay(100);
6be4a607 3736 }
0e23b99d
JB		 3737}
3738
88cefb6c
DV		 3739static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3740{
3741 struct drm_device *dev = intel_crtc->base.dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 /* Switch from PCDclk to Rawclk */
3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3750
3751 /* Disable CPU FDI TX PLL */
3752 reg = FDI_TX_CTL(pipe);
3753 temp = I915_READ(reg);
3754 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3755
3756 POSTING_READ(reg);
3757 udelay(100);
3758
3759 reg = FDI_RX_CTL(pipe);
3760 temp = I915_READ(reg);
3761 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3762
3763 /* Wait for the clocks to turn off. */
3764 POSTING_READ(reg);
3765 udelay(100);
3766}
3767
0fc932b8
JB		 3768static void ironlake_fdi_disable(struct drm_crtc *crtc)
3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773 int pipe = intel_crtc->pipe;
3774 u32 reg, temp;
3775
3776 /* disable CPU FDI tx and PCH FDI rx */
3777 reg = FDI_TX_CTL(pipe);
3778 temp = I915_READ(reg);
3779 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3780 POSTING_READ(reg);
3781
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 temp &= ~(0x7 << 16);
dfd07d72 3785 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3786 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3787
3788 POSTING_READ(reg);
3789 udelay(100);
3790
3791 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3792 if (HAS_PCH_IBX(dev))
6f06ce18 3793 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3794
3795 /* still set train pattern 1 */
3796 reg = FDI_TX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 temp &= ~FDI_LINK_TRAIN_NONE;
3799 temp |= FDI_LINK_TRAIN_PATTERN_1;
3800 I915_WRITE(reg, temp);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 if (HAS_PCH_CPT(dev)) {
3805 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3806 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3807 } else {
3808 temp &= ~FDI_LINK_TRAIN_NONE;
3809 temp |= FDI_LINK_TRAIN_PATTERN_1;
3810 }
3811 /* BPC in FDI rx is consistent with that in PIPECONF */
3812 temp &= ~(0x07 << 16);
dfd07d72 3813 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3814 I915_WRITE(reg, temp);
3815
3816 POSTING_READ(reg);
3817 udelay(100);
3818}
3819
5dce5b93
CW		 3820bool intel_has_pending_fb_unpin(struct drm_device *dev)
3821{
3822 struct intel_crtc *crtc;
3823
3824 /* Note that we don't need to be called with mode_config.lock here
3825 * as our list of CRTC objects is static for the lifetime of the
3826 * device and so cannot disappear as we iterate. Similarly, we can
3827 * happily treat the predicates as racy, atomic checks as userspace
3828 * cannot claim and pin a new fb without at least acquring the
3829 * struct_mutex and so serialising with us.
3830 */
d3fcc808 3831 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3832 if (atomic_read(&crtc->unpin_work_count) == 0)
3833 continue;
3834
3835 if (crtc->unpin_work)
3836 intel_wait_for_vblank(dev, crtc->pipe);
3837
3838 return true;
3839 }
3840
3841 return false;
3842}
3843
d6bbafa1
CW		 3844static void page_flip_completed(struct intel_crtc *intel_crtc)
3845{
3846 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3847 struct intel_unpin_work *work = intel_crtc->unpin_work;
3848
3849 /* ensure that the unpin work is consistent wrt ->pending. */
3850 smp_rmb();
3851 intel_crtc->unpin_work = NULL;
3852
3853 if (work->event)
3854 drm_send_vblank_event(intel_crtc->base.dev,
3855 intel_crtc->pipe,
3856 work->event);
3857
3858 drm_crtc_vblank_put(&intel_crtc->base);
3859
3860 wake_up_all(&dev_priv->pending_flip_queue);
3861 queue_work(dev_priv->wq, &work->work);
3862
3863 trace_i915_flip_complete(intel_crtc->plane,
3864 work->pending_flip_obj);
3865}
3866
46a55d30 3867void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3868{
0f91128d 3869 struct drm_device *dev = crtc->dev;
5bb61643 3870 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3871
2c10d571 3872 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3873 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3874 !intel_crtc_has_pending_flip(crtc),
3875 60*HZ) == 0)) {
3876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3877
5e2d7afc 3878 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3879 if (intel_crtc->unpin_work) {
3880 WARN_ONCE(1, "Removing stuck page flip\n");
3881 page_flip_completed(intel_crtc);
3882 }
5e2d7afc 3883 spin_unlock_irq(&dev->event_lock);
9c787942 3884 }
5bb61643 3885
975d568a
CW		 3886 if (crtc->primary->fb) {
3887 mutex_lock(&dev->struct_mutex);
3888 intel_finish_fb(crtc->primary->fb);
3889 mutex_unlock(&dev->struct_mutex);
3890 }
e6c3a2a6
CW		 3891}
3892
e615efe4
ED		 3893/* Program iCLKIP clock to the desired frequency */
3894static void lpt_program_iclkip(struct drm_crtc *crtc)
3895{
3896 struct drm_device *dev = crtc->dev;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3898 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3899 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3900 u32 temp;
3901
a580516d 3902 mutex_lock(&dev_priv->sb_lock);
09153000 3903
e615efe4
ED		 3904 /* It is necessary to ungate the pixclk gate prior to programming
3905 * the divisors, and gate it back when it is done.
3906 */
3907 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3908
3909 /* Disable SSCCTL */
3910 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3911 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3912 SBI_SSCCTL_DISABLE,
3913 SBI_ICLK);
e615efe4
ED		 3914
3915 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3916 if (clock == 20000) {
e615efe4
ED		 3917 auxdiv = 1;
3918 divsel = 0x41;
3919 phaseinc = 0x20;
3920 } else {
3921 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3922 * but the adjusted_mode->crtc_clock in in KHz. To get the
3923 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3924 * convert the virtual clock precision to KHz here for higher
3925 * precision.
3926 */
3927 u32 iclk_virtual_root_freq = 172800 * 1000;
3928 u32 iclk_pi_range = 64;
3929 u32 desired_divisor, msb_divisor_value, pi_value;
3930
12d7ceed 3931 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3932 msb_divisor_value = desired_divisor / iclk_pi_range;
3933 pi_value = desired_divisor % iclk_pi_range;
3934
3935 auxdiv = 0;
3936 divsel = msb_divisor_value - 2;
3937 phaseinc = pi_value;
3938 }
3939
3940 /* This should not happen with any sane values */
3941 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3942 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3943 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3944 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3945
3946 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3947 clock,
e615efe4
ED		 3948 auxdiv,
3949 divsel,
3950 phasedir,
3951 phaseinc);
3952
3953 /* Program SSCDIVINTPHASE6 */
988d6ee8 3954 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3955 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3956 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3957 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3958 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3959 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3960 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3961 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3962
3963 /* Program SSCAUXDIV */
988d6ee8 3964 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3965 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3966 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3967 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3968
3969 /* Enable modulator and associated divider */
988d6ee8 3970 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3971 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3972 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3973
3974 /* Wait for initialization time */
3975 udelay(24);
3976
3977 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3978
a580516d 3979 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3980}
3981
275f01b2
DV		 3982static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3983 enum pipe pch_transcoder)
3984{
3985 struct drm_device *dev = crtc->base.dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3987 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3988
3989 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3990 I915_READ(HTOTAL(cpu_transcoder)));
3991 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3992 I915_READ(HBLANK(cpu_transcoder)));
3993 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3994 I915_READ(HSYNC(cpu_transcoder)));
3995
3996 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3997 I915_READ(VTOTAL(cpu_transcoder)));
3998 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3999 I915_READ(VBLANK(cpu_transcoder)));
4000 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4001 I915_READ(VSYNC(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4003 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4004}
4005
003632d9 4006static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4007{
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 uint32_t temp;
4010
4011 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4012 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4013 return;
4014
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4016 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4017
003632d9
ACO		 4018 temp &= ~FDI_BC_BIFURCATION_SELECT;
4019 if (enable)
4020 temp |= FDI_BC_BIFURCATION_SELECT;
4021
4022 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4023 I915_WRITE(SOUTH_CHICKEN1, temp);
4024 POSTING_READ(SOUTH_CHICKEN1);
4025}
4026
4027static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4028{
4029 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4030
4031 switch (intel_crtc->pipe) {
4032 case PIPE_A:
4033 break;
4034 case PIPE_B:
6e3c9717 4035 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4036 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4037 else
003632d9 4038 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4039
4040 break;
4041 case PIPE_C:
003632d9 4042 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4043
4044 break;
4045 default:
4046 BUG();
4047 }
4048}
4049
f67a559d
JB		 4050/*
4051 * Enable PCH resources required for PCH ports:
4052 * - PCH PLLs
4053 * - FDI training & RX/TX
4054 * - update transcoder timings
4055 * - DP transcoding bits
4056 * - transcoder
4057 */
4058static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4059{
4060 struct drm_device *dev = crtc->dev;
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063 int pipe = intel_crtc->pipe;
ee7b9f93 4064 u32 reg, temp;
2c07245f 4065
ab9412ba 4066 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4067
1fbc0d78
DV		 4068 if (IS_IVYBRIDGE(dev))
4069 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4070
cd986abb
DV		 4071 /* Write the TU size bits before fdi link training, so that error
4072 * detection works. */
4073 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4074 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4075
c98e9dcf 4076 /* For PCH output, training FDI link */
674cf967 4077 dev_priv->display.fdi_link_train(crtc);
2c07245f 4078
3ad8a208
DV		 4079 /* We need to program the right clock selection before writing the pixel
4080 * mutliplier into the DPLL. */
303b81e0 4081 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4082 u32 sel;
4b645f14 4083
c98e9dcf 4084 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4085 temp |= TRANS_DPLL_ENABLE(pipe);
4086 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4087 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4088 temp |= sel;
4089 else
4090 temp &= ~sel;
c98e9dcf 4091 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4092 }
5eddb70b 4093
3ad8a208
DV		 4094 /* XXX: pch pll's can be enabled any time before we enable the PCH
4095 * transcoder, and we actually should do this to not upset any PCH
4096 * transcoder that already use the clock when we share it.
4097 *
4098 * Note that enable_shared_dpll tries to do the right thing, but
4099 * get_shared_dpll unconditionally resets the pll - we need that to have
4100 * the right LVDS enable sequence. */
85b3894f 4101 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4102
d9b6cb56
JB		 4103 /* set transcoder timing, panel must allow it */
4104 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4105 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4106
303b81e0 4107 intel_fdi_normal_train(crtc);
5e84e1a4 4108
c98e9dcf 4109 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4110 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4111 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4112 reg = TRANS_DP_CTL(pipe);
4113 temp = I915_READ(reg);
4114 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4115 TRANS_DP_SYNC_MASK |
4116 TRANS_DP_BPC_MASK);
e3ef4479 4117 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4118 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4119
4120 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4121 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4122 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4123 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4124
4125 switch (intel_trans_dp_port_sel(crtc)) {
4126 case PCH_DP_B:
5eddb70b 4127 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4128 break;
4129 case PCH_DP_C:
5eddb70b 4130 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4131 break;
4132 case PCH_DP_D:
5eddb70b 4133 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4134 break;
4135 default:
e95d41e1 4136 BUG();
32f9d658 4137 }
2c07245f 4138
5eddb70b 4139 I915_WRITE(reg, temp);
6be4a607 4140 }
b52eb4dc 4141
b8a4f404 4142 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4143}
4144
1507e5bd
PZ		 4145static void lpt_pch_enable(struct drm_crtc *crtc)
4146{
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4150 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4151
ab9412ba 4152 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4153
8c52b5e8 4154 lpt_program_iclkip(crtc);
1507e5bd 4155
0540e488 4156 /* Set transcoder timing. */
275f01b2 4157 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4158
937bb610 4159 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4160}
4161
190f68c5
ACO		 4162struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4163 struct intel_crtc_state *crtc_state)
ee7b9f93 4164{
e2b78267 4165 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4166 struct intel_shared_dpll *pll;
de419ab6 4167 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4168 enum intel_dpll_id i;
ee7b9f93 4169
de419ab6
ML		 4170 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4171
98b6bd99
DV		 4172 if (HAS_PCH_IBX(dev_priv->dev)) {
4173 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4174 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4175 pll = &dev_priv->shared_dplls[i];
98b6bd99 4176
46edb027
DV		 4177 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4178 crtc->base.base.id, pll->name);
98b6bd99 4179
de419ab6 4180 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4181
98b6bd99
DV		 4182 goto found;
4183 }
4184
bcddf610
S		 4185 if (IS_BROXTON(dev_priv->dev)) {
4186 /* PLL is attached to port in bxt */
4187 struct intel_encoder *encoder;
4188 struct intel_digital_port *intel_dig_port;
4189
4190 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4191 if (WARN_ON(!encoder))
4192 return NULL;
4193
4194 intel_dig_port = enc_to_dig_port(&encoder->base);
4195 /* 1:1 mapping between ports and PLLs */
4196 i = (enum intel_dpll_id)intel_dig_port->port;
4197 pll = &dev_priv->shared_dplls[i];
4198 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4199 crtc->base.base.id, pll->name);
de419ab6 4200 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4201
4202 goto found;
4203 }
4204
e72f9fbf
DV		 4205 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4206 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4207
4208 /* Only want to check enabled timings first */
de419ab6 4209 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4210 continue;
4211
190f68c5 4212 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4213 &shared_dpll[i].hw_state,
4214 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4215 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4216 crtc->base.base.id, pll->name,
de419ab6 4217 shared_dpll[i].crtc_mask,
8bd31e67 4218 pll->active);
ee7b9f93
JB		 4219 goto found;
4220 }
4221 }
4222
4223 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4224 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4225 pll = &dev_priv->shared_dplls[i];
de419ab6 4226 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4227 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4228 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4229 goto found;
4230 }
4231 }
4232
4233 return NULL;
4234
4235found:
de419ab6
ML		 4236 if (shared_dpll[i].crtc_mask == 0)
4237 shared_dpll[i].hw_state =
4238 crtc_state->dpll_hw_state;
f2a69f44 4239
190f68c5 4240 crtc_state->shared_dpll = i;
46edb027
DV		 4241 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4242 pipe_name(crtc->pipe));
ee7b9f93 4243
de419ab6 4244 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4245
ee7b9f93
JB		 4246 return pll;
4247}
4248
de419ab6 4249static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4250{
de419ab6
ML		 4251 struct drm_i915_private *dev_priv = to_i915(state->dev);
4252 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4253 struct intel_shared_dpll *pll;
4254 enum intel_dpll_id i;
4255
de419ab6
ML		 4256 if (!to_intel_atomic_state(state)->dpll_set)
4257 return;
8bd31e67 4258
de419ab6 4259 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4260 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261 pll = &dev_priv->shared_dplls[i];
de419ab6 4262 pll->config = shared_dpll[i];
8bd31e67
ACO		 4263 }
4264}
4265
a1520318 4266static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4267{
4268 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4269 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4270 u32 temp;
4271
4272 temp = I915_READ(dslreg);
4273 udelay(500);
4274 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4275 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4276 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4277 }
4278}
4279
86adf9d7
ML		 4280static int
4281skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4282 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4283 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4284{
86adf9d7
ML		 4285 struct intel_crtc_scaler_state *scaler_state =
4286 &crtc_state->scaler_state;
4287 struct intel_crtc *intel_crtc =
4288 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4289 int need_scaling;
6156a456
CK		 4290
4291 need_scaling = intel_rotation_90_or_270(rotation) ?
4292 (src_h != dst_w || src_w != dst_h):
4293 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4294
4295 /*
4296 * if plane is being disabled or scaler is no more required or force detach
4297 * - free scaler binded to this plane/crtc
4298 * - in order to do this, update crtc->scaler_usage
4299 *
4300 * Here scaler state in crtc_state is set free so that
4301 * scaler can be assigned to other user. Actual register
4302 * update to free the scaler is done in plane/panel-fit programming.
4303 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4304 */
86adf9d7 4305 if (force_detach || !need_scaling) {
a1b2278e 4306 if (*scaler_id >= 0) {
86adf9d7 4307 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4308 scaler_state->scalers[*scaler_id].in_use = 0;
4309
86adf9d7
ML		 4310 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4311 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4312 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4313 scaler_state->scaler_users);
4314 *scaler_id = -1;
4315 }
4316 return 0;
4317 }
4318
4319 /* range checks */
4320 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4321 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4322
4323 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4324 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4325 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4326 "size is out of scaler range\n",
86adf9d7 4327 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4328 return -EINVAL;
4329 }
4330
86adf9d7
ML		 4331 /* mark this plane as a scaler user in crtc_state */
4332 scaler_state->scaler_users |= (1 << scaler_user);
4333 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4334 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4335 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4336 scaler_state->scaler_users);
4337
4338 return 0;
4339}
4340
4341/**
4342 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4343 *
4344 * @state: crtc's scaler state
86adf9d7
ML		 4345 *
4346 * Return
4347 * 0 - scaler_usage updated successfully
4348 * error - requested scaling cannot be supported or other error condition
4349 */
e435d6e5 4350int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4351{
4352 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4353 struct drm_display_mode *adjusted_mode =
4354 &state->base.adjusted_mode;
4355
4356 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4357 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4358
e435d6e5 4359 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4360 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4361 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4362 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4363}
4364
4365/**
4366 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4367 *
4368 * @state: crtc's scaler state
86adf9d7
ML		 4369 * @plane_state: atomic plane state to update
4370 *
4371 * Return
4372 * 0 - scaler_usage updated successfully
4373 * error - requested scaling cannot be supported or other error condition
4374 */
da20eabd
ML		 4375static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4376 struct intel_plane_state *plane_state)
86adf9d7
ML		 4377{
4378
4379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4380 struct intel_plane *intel_plane =
4381 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4382 struct drm_framebuffer *fb = plane_state->base.fb;
4383 int ret;
4384
4385 bool force_detach = !fb || !plane_state->visible;
4386
4387 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4388 intel_plane->base.base.id, intel_crtc->pipe,
4389 drm_plane_index(&intel_plane->base));
4390
4391 ret = skl_update_scaler(crtc_state, force_detach,
4392 drm_plane_index(&intel_plane->base),
4393 &plane_state->scaler_id,
4394 plane_state->base.rotation,
4395 drm_rect_width(&plane_state->src) >> 16,
4396 drm_rect_height(&plane_state->src) >> 16,
4397 drm_rect_width(&plane_state->dst),
4398 drm_rect_height(&plane_state->dst));
4399
4400 if (ret || plane_state->scaler_id < 0)
4401 return ret;
4402
a1b2278e 4403 /* check colorkey */
818ed961 4404 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4405 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4406 intel_plane->base.base.id);
a1b2278e
CK		 4407 return -EINVAL;
4408 }
4409
4410 /* Check src format */
86adf9d7
ML		 4411 switch (fb->pixel_format) {
4412 case DRM_FORMAT_RGB565:
4413 case DRM_FORMAT_XBGR8888:
4414 case DRM_FORMAT_XRGB8888:
4415 case DRM_FORMAT_ABGR8888:
4416 case DRM_FORMAT_ARGB8888:
4417 case DRM_FORMAT_XRGB2101010:
4418 case DRM_FORMAT_XBGR2101010:
4419 case DRM_FORMAT_YUYV:
4420 case DRM_FORMAT_YVYU:
4421 case DRM_FORMAT_UYVY:
4422 case DRM_FORMAT_VYUY:
4423 break;
4424 default:
4425 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4426 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4427 return -EINVAL;
a1b2278e
CK		 4428 }
4429
a1b2278e
CK		 4430 return 0;
4431}
4432
e435d6e5
ML		 4433static void skylake_scaler_disable(struct intel_crtc *crtc)
4434{
4435 int i;
4436
4437 for (i = 0; i < crtc->num_scalers; i++)
4438 skl_detach_scaler(crtc, i);
4439}
4440
4441static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4442{
4443 struct drm_device *dev = crtc->base.dev;
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445 int pipe = crtc->pipe;
a1b2278e
CK		 4446 struct intel_crtc_scaler_state *scaler_state =
4447 &crtc->config->scaler_state;
4448
4449 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4450
6e3c9717 4451 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4452 int id;
4453
4454 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4455 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4456 return;
4457 }
4458
4459 id = scaler_state->scaler_id;
4460 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4461 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4462 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4463 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4464
4465 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4466 }
4467}
4468
b074cec8
JB		 4469static void ironlake_pfit_enable(struct intel_crtc *crtc)
4470{
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 int pipe = crtc->pipe;
4474
6e3c9717 4475 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4476 /* Force use of hard-coded filter coefficients
4477 * as some pre-programmed values are broken,
4478 * e.g. x201.
4479 */
4480 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4481 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4482 PF_PIPE_SEL_IVB(pipe));
4483 else
4484 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4485 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4486 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4487 }
4488}
4489
20bc8673 4490void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4491{
cea165c3
VS		 4492 struct drm_device *dev = crtc->base.dev;
4493 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4494
6e3c9717 4495 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4496 return;
4497
cea165c3
VS		 4498 /* We can only enable IPS after we enable a plane and wait for a vblank */
4499 intel_wait_for_vblank(dev, crtc->pipe);
4500
d77e4531 4501 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4502 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4503 mutex_lock(&dev_priv->rps.hw_lock);
4504 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4505 mutex_unlock(&dev_priv->rps.hw_lock);
4506 /* Quoting Art Runyan: "its not safe to expect any particular
4507 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4508 * mailbox." Moreover, the mailbox may return a bogus state,
4509 * so we need to just enable it and continue on.
2a114cc1
BW		 4510 */
4511 } else {
4512 I915_WRITE(IPS_CTL, IPS_ENABLE);
4513 /* The bit only becomes 1 in the next vblank, so this wait here
4514 * is essentially intel_wait_for_vblank. If we don't have this
4515 * and don't wait for vblanks until the end of crtc_enable, then
4516 * the HW state readout code will complain that the expected
4517 * IPS_CTL value is not the one we read. */
4518 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4519 DRM_ERROR("Timed out waiting for IPS enable\n");
4520 }
d77e4531
PZ		 4521}
4522
20bc8673 4523void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4524{
4525 struct drm_device *dev = crtc->base.dev;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527
6e3c9717 4528 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4529 return;
4530
4531 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4532 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4533 mutex_lock(&dev_priv->rps.hw_lock);
4534 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4535 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4536 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4537 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4538 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4539 } else {
2a114cc1 4540 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4541 POSTING_READ(IPS_CTL);
4542 }
d77e4531
PZ		 4543
4544 /* We need to wait for a vblank before we can disable the plane. */
4545 intel_wait_for_vblank(dev, crtc->pipe);
4546}
4547
4548/** Loads the palette/gamma unit for the CRTC with the prepared values */
4549static void intel_crtc_load_lut(struct drm_crtc *crtc)
4550{
4551 struct drm_device *dev = crtc->dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4554 enum pipe pipe = intel_crtc->pipe;
4555 int palreg = PALETTE(pipe);
4556 int i;
4557 bool reenable_ips = false;
4558
4559 /* The clocks have to be on to load the palette. */
53d9f4e9 4560 if (!crtc->state->active)
d77e4531
PZ		 4561 return;
4562
50360403 4563 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4564 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4565 assert_dsi_pll_enabled(dev_priv);
4566 else
4567 assert_pll_enabled(dev_priv, pipe);
4568 }
4569
4570 /* use legacy palette for Ironlake */
7a1db49a 4571 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4572 palreg = LGC_PALETTE(pipe);
4573
4574 /* Workaround : Do not read or write the pipe palette/gamma data while
4575 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4576 */
6e3c9717 4577 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4578 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4579 GAMMA_MODE_MODE_SPLIT)) {
4580 hsw_disable_ips(intel_crtc);
4581 reenable_ips = true;
4582 }
4583
4584 for (i = 0; i < 256; i++) {
4585 I915_WRITE(palreg + 4 * i,
4586 (intel_crtc->lut_r[i] << 16) |
4587 (intel_crtc->lut_g[i] << 8) |
4588 intel_crtc->lut_b[i]);
4589 }
4590
4591 if (reenable_ips)
4592 hsw_enable_ips(intel_crtc);
4593}
4594
7cac945f 4595static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4596{
7cac945f 4597 if (intel_crtc->overlay) {
d3eedb1a
VS		 4598 struct drm_device *dev = intel_crtc->base.dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600
4601 mutex_lock(&dev->struct_mutex);
4602 dev_priv->mm.interruptible = false;
4603 (void) intel_overlay_switch_off(intel_crtc->overlay);
4604 dev_priv->mm.interruptible = true;
4605 mutex_unlock(&dev->struct_mutex);
4606 }
4607
4608 /* Let userspace switch the overlay on again. In most cases userspace
4609 * has to recompute where to put it anyway.
4610 */
4611}
4612
87d4300a
ML		 4613/**
4614 * intel_post_enable_primary - Perform operations after enabling primary plane
4615 * @crtc: the CRTC whose primary plane was just enabled
4616 *
4617 * Performs potentially sleeping operations that must be done after the primary
4618 * plane is enabled, such as updating FBC and IPS. Note that this may be
4619 * called due to an explicit primary plane update, or due to an implicit
4620 * re-enable that is caused when a sprite plane is updated to no longer
4621 * completely hide the primary plane.
4622 */
4623static void
4624intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4625{
4626 struct drm_device *dev = crtc->dev;
87d4300a 4627 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 int pipe = intel_crtc->pipe;
a5c4d7bc 4630
87d4300a
ML		 4631 /*
4632 * BDW signals flip done immediately if the plane
4633 * is disabled, even if the plane enable is already
4634 * armed to occur at the next vblank :(
4635 */
4636 if (IS_BROADWELL(dev))
4637 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4638
87d4300a
ML		 4639 /*
4640 * FIXME IPS should be fine as long as one plane is
4641 * enabled, but in practice it seems to have problems
4642 * when going from primary only to sprite only and vice
4643 * versa.
4644 */
a5c4d7bc
VS		 4645 hsw_enable_ips(intel_crtc);
4646
f99d7069 4647 /*
87d4300a
ML		 4648 * Gen2 reports pipe underruns whenever all planes are disabled.
4649 * So don't enable underrun reporting before at least some planes
4650 * are enabled.
4651 * FIXME: Need to fix the logic to work when we turn off all planes
4652 * but leave the pipe running.
f99d7069 4653 */
87d4300a
ML		 4654 if (IS_GEN2(dev))
4655 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4656
4657 /* Underruns don't raise interrupts, so check manually. */
4658 if (HAS_GMCH_DISPLAY(dev))
4659 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4660}
4661
87d4300a
ML		 4662/**
4663 * intel_pre_disable_primary - Perform operations before disabling primary plane
4664 * @crtc: the CRTC whose primary plane is to be disabled
4665 *
4666 * Performs potentially sleeping operations that must be done before the
4667 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4668 * be called due to an explicit primary plane update, or due to an implicit
4669 * disable that is caused when a sprite plane completely hides the primary
4670 * plane.
4671 */
4672static void
4673intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4674{
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 int pipe = intel_crtc->pipe;
a5c4d7bc 4679
87d4300a
ML		 4680 /*
4681 * Gen2 reports pipe underruns whenever all planes are disabled.
4682 * So diasble underrun reporting before all the planes get disabled.
4683 * FIXME: Need to fix the logic to work when we turn off all planes
4684 * but leave the pipe running.
4685 */
4686 if (IS_GEN2(dev))
4687 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4688
87d4300a
ML		 4689 /*
4690 * Vblank time updates from the shadow to live plane control register
4691 * are blocked if the memory self-refresh mode is active at that
4692 * moment. So to make sure the plane gets truly disabled, disable
4693 * first the self-refresh mode. The self-refresh enable bit in turn
4694 * will be checked/applied by the HW only at the next frame start
4695 * event which is after the vblank start event, so we need to have a
4696 * wait-for-vblank between disabling the plane and the pipe.
4697 */
262cd2e1 4698 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4699 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4700 dev_priv->wm.vlv.cxsr = false;
4701 intel_wait_for_vblank(dev, pipe);
4702 }
87d4300a 4703
87d4300a
ML		 4704 /*
4705 * FIXME IPS should be fine as long as one plane is
4706 * enabled, but in practice it seems to have problems
4707 * when going from primary only to sprite only and vice
4708 * versa.
4709 */
a5c4d7bc 4710 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4711}
4712
ac21b225
ML		 4713static void intel_post_plane_update(struct intel_crtc *crtc)
4714{
4715 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4716 struct drm_device *dev = crtc->base.dev;
7733b49b 4717 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4718 struct drm_plane *plane;
4719
4720 if (atomic->wait_vblank)
4721 intel_wait_for_vblank(dev, crtc->pipe);
4722
4723 intel_frontbuffer_flip(dev, atomic->fb_bits);
4724
852eb00d
VS		 4725 if (atomic->disable_cxsr)
4726 crtc->wm.cxsr_allowed = true;
4727
f015c551
VS		 4728 if (crtc->atomic.update_wm_post)
4729 intel_update_watermarks(&crtc->base);
4730
c80ac854 4731 if (atomic->update_fbc)
7733b49b 4732 intel_fbc_update(dev_priv);
ac21b225
ML		 4733
4734 if (atomic->post_enable_primary)
4735 intel_post_enable_primary(&crtc->base);
4736
4737 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4738 intel_update_sprite_watermarks(plane, &crtc->base,
4739 0, 0, 0, false, false);
4740
4741 memset(atomic, 0, sizeof(*atomic));
4742}
4743
4744static void intel_pre_plane_update(struct intel_crtc *crtc)
4745{
4746 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4747 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4748 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4749 struct drm_plane *p;
4750
4751 /* Track fb's for any planes being disabled */
ac21b225
ML		 4752 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4753 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4754
4755 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4756 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4757 plane->frontbuffer_bit);
ac21b225
ML		 4758 mutex_unlock(&dev->struct_mutex);
4759 }
4760
4761 if (atomic->wait_for_flips)
4762 intel_crtc_wait_for_pending_flips(&crtc->base);
4763
c80ac854 4764 if (atomic->disable_fbc)
25ad93fd 4765 intel_fbc_disable_crtc(crtc);
ac21b225 4766
066cf55b
RV		 4767 if (crtc->atomic.disable_ips)
4768 hsw_disable_ips(crtc);
4769
ac21b225
ML		 4770 if (atomic->pre_disable_primary)
4771 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4772
4773 if (atomic->disable_cxsr) {
4774 crtc->wm.cxsr_allowed = false;
4775 intel_set_memory_cxsr(dev_priv, false);
4776 }
ac21b225
ML		 4777}
4778
d032ffa0 4779static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4780{
4781 struct drm_device *dev = crtc->dev;
4782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4783 struct drm_plane *p;
87d4300a
ML		 4784 int pipe = intel_crtc->pipe;
4785
7cac945f 4786 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4787
d032ffa0
ML		 4788 drm_for_each_plane_mask(p, dev, plane_mask)
4789 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4790
f99d7069
DV		 4791 /*
4792 * FIXME: Once we grow proper nuclear flip support out of this we need
4793 * to compute the mask of flip planes precisely. For the time being
4794 * consider this a flip to a NULL plane.
4795 */
4796 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4797}
4798
f67a559d
JB		 4799static void ironlake_crtc_enable(struct drm_crtc *crtc)
4800{
4801 struct drm_device *dev = crtc->dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4804 struct intel_encoder *encoder;
f67a559d 4805 int pipe = intel_crtc->pipe;
f67a559d 4806
53d9f4e9 4807 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4808 return;
4809
6e3c9717 4810 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4811 intel_prepare_shared_dpll(intel_crtc);
4812
6e3c9717 4813 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4814 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4815
4816 intel_set_pipe_timings(intel_crtc);
4817
6e3c9717 4818 if (intel_crtc->config->has_pch_encoder) {
29407aab 4819 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4820 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4821 }
4822
4823 ironlake_set_pipeconf(crtc);
4824
f67a559d 4825 intel_crtc->active = true;
8664281b 4826
a72e4c9f
DV		 4827 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4828 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4829
f6736a1a 4830 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4831 if (encoder->pre_enable)
4832 encoder->pre_enable(encoder);
f67a559d 4833
6e3c9717 4834 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4835 /* Note: FDI PLL enabling _must_ be done before we enable the
4836 * cpu pipes, hence this is separate from all the other fdi/pch
4837 * enabling. */
88cefb6c 4838 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4839 } else {
4840 assert_fdi_tx_disabled(dev_priv, pipe);
4841 assert_fdi_rx_disabled(dev_priv, pipe);
4842 }
f67a559d 4843
b074cec8 4844 ironlake_pfit_enable(intel_crtc);
f67a559d 4845
9c54c0dd
JB		 4846 /*
4847 * On ILK+ LUT must be loaded before the pipe is running but with
4848 * clocks enabled
4849 */
4850 intel_crtc_load_lut(crtc);
4851
f37fcc2a 4852 intel_update_watermarks(crtc);
e1fdc473 4853 intel_enable_pipe(intel_crtc);
f67a559d 4854
6e3c9717 4855 if (intel_crtc->config->has_pch_encoder)
f67a559d 4856 ironlake_pch_enable(crtc);
c98e9dcf 4857
f9b61ff6
DV		 4858 assert_vblank_disabled(crtc);
4859 drm_crtc_vblank_on(crtc);
4860
fa5c73b1
DV		 4861 for_each_encoder_on_crtc(dev, crtc, encoder)
4862 encoder->enable(encoder);
61b77ddd
DV		 4863
4864 if (HAS_PCH_CPT(dev))
a1520318 4865 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4866}
4867
42db64ef
PZ		 4868/* IPS only exists on ULT machines and is tied to pipe A. */
4869static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4870{
f5adf94e 4871 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4872}
4873
4f771f10
PZ		 4874static void haswell_crtc_enable(struct drm_crtc *crtc)
4875{
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct intel_encoder *encoder;
99d736a2
ML		 4880 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4881 struct intel_crtc_state *pipe_config =
4882 to_intel_crtc_state(crtc->state);
4f771f10 4883
53d9f4e9 4884 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4885 return;
4886
df8ad70c
DV		 4887 if (intel_crtc_to_shared_dpll(intel_crtc))
4888 intel_enable_shared_dpll(intel_crtc);
4889
6e3c9717 4890 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4891 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4892
4893 intel_set_pipe_timings(intel_crtc);
4894
6e3c9717
ACO		 4895 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4896 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4897 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4898 }
4899
6e3c9717 4900 if (intel_crtc->config->has_pch_encoder) {
229fca97 4901 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4902 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4903 }
4904
4905 haswell_set_pipeconf(crtc);
4906
4907 intel_set_pipe_csc(crtc);
4908
4f771f10 4909 intel_crtc->active = true;
8664281b 4910
a72e4c9f 4911 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4912 for_each_encoder_on_crtc(dev, crtc, encoder)
4913 if (encoder->pre_enable)
4914 encoder->pre_enable(encoder);
4915
6e3c9717 4916 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4917 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4918 true);
4fe9467d
ID		 4919 dev_priv->display.fdi_link_train(crtc);
4920 }
4921
1f544388 4922 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4923
1c132b44 4924 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4925 skylake_pfit_enable(intel_crtc);
ff6d9f55 4926 else
1c132b44 4927 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4928
4929 /*
4930 * On ILK+ LUT must be loaded before the pipe is running but with
4931 * clocks enabled
4932 */
4933 intel_crtc_load_lut(crtc);
4934
1f544388 4935 intel_ddi_set_pipe_settings(crtc);
8228c251 4936 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4937
f37fcc2a 4938 intel_update_watermarks(crtc);
e1fdc473 4939 intel_enable_pipe(intel_crtc);
42db64ef 4940
6e3c9717 4941 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4942 lpt_pch_enable(crtc);
4f771f10 4943
6e3c9717 4944 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4945 intel_ddi_set_vc_payload_alloc(crtc, true);
4946
f9b61ff6
DV		 4947 assert_vblank_disabled(crtc);
4948 drm_crtc_vblank_on(crtc);
4949
8807e55b 4950 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4951 encoder->enable(encoder);
8807e55b
JN		 4952 intel_opregion_notify_encoder(encoder, true);
4953 }
4f771f10 4954
e4916946
PZ		 4955 /* If we change the relative order between pipe/planes enabling, we need
4956 * to change the workaround. */
99d736a2
ML		 4957 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4958 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4959 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4960 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4961 }
4f771f10
PZ		 4962}
4963
3f8dce3a
DV		 4964static void ironlake_pfit_disable(struct intel_crtc *crtc)
4965{
4966 struct drm_device *dev = crtc->base.dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 int pipe = crtc->pipe;
4969
4970 /* To avoid upsetting the power well on haswell only disable the pfit if
4971 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4972 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4973 I915_WRITE(PF_CTL(pipe), 0);
4974 I915_WRITE(PF_WIN_POS(pipe), 0);
4975 I915_WRITE(PF_WIN_SZ(pipe), 0);
4976 }
4977}
4978
6be4a607
JB		 4979static void ironlake_crtc_disable(struct drm_crtc *crtc)
4980{
4981 struct drm_device *dev = crtc->dev;
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4984 struct intel_encoder *encoder;
6be4a607 4985 int pipe = intel_crtc->pipe;
5eddb70b 4986 u32 reg, temp;
b52eb4dc 4987
ea9d758d
DV		 4988 for_each_encoder_on_crtc(dev, crtc, encoder)
4989 encoder->disable(encoder);
4990
f9b61ff6
DV		 4991 drm_crtc_vblank_off(crtc);
4992 assert_vblank_disabled(crtc);
4993
6e3c9717 4994 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4995 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4996
575f7ab7 4997 intel_disable_pipe(intel_crtc);
32f9d658 4998
3f8dce3a 4999 ironlake_pfit_disable(intel_crtc);
2c07245f 5000
5a74f70a
VS		 5001 if (intel_crtc->config->has_pch_encoder)
5002 ironlake_fdi_disable(crtc);
5003
bf49ec8c
DV		 5004 for_each_encoder_on_crtc(dev, crtc, encoder)
5005 if (encoder->post_disable)
5006 encoder->post_disable(encoder);
2c07245f 5007
6e3c9717 5008 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5009 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5010
d925c59a
DV		 5011 if (HAS_PCH_CPT(dev)) {
5012 /* disable TRANS_DP_CTL */
5013 reg = TRANS_DP_CTL(pipe);
5014 temp = I915_READ(reg);
5015 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5016 TRANS_DP_PORT_SEL_MASK);
5017 temp |= TRANS_DP_PORT_SEL_NONE;
5018 I915_WRITE(reg, temp);
5019
5020 /* disable DPLL_SEL */
5021 temp = I915_READ(PCH_DPLL_SEL);
11887397 5022 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5023 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5024 }
e3421a18 5025
d925c59a
DV		 5026 ironlake_fdi_pll_disable(intel_crtc);
5027 }
e4ca0612
PJ		 5028
5029 intel_crtc->active = false;
5030 intel_update_watermarks(crtc);
6be4a607 5031}
1b3c7a47 5032
4f771f10 5033static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5034{
4f771f10
PZ		 5035 struct drm_device *dev = crtc->dev;
5036 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5038 struct intel_encoder *encoder;
6e3c9717 5039 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5040
8807e55b
JN		 5041 for_each_encoder_on_crtc(dev, crtc, encoder) {
5042 intel_opregion_notify_encoder(encoder, false);
4f771f10 5043 encoder->disable(encoder);
8807e55b 5044 }
4f771f10 5045
f9b61ff6
DV		 5046 drm_crtc_vblank_off(crtc);
5047 assert_vblank_disabled(crtc);
5048
6e3c9717 5049 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5050 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5051 false);
575f7ab7 5052 intel_disable_pipe(intel_crtc);
4f771f10 5053
6e3c9717 5054 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5055 intel_ddi_set_vc_payload_alloc(crtc, false);
5056
ad80a810 5057 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5058
1c132b44 5059 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5060 skylake_scaler_disable(intel_crtc);
ff6d9f55 5061 else
1c132b44 5062 ironlake_pfit_disable(intel_crtc);
4f771f10 5063
1f544388 5064 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5065
6e3c9717 5066 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5067 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5068 intel_ddi_fdi_disable(crtc);
83616634 5069 }
4f771f10 5070
97b040aa
ID		 5071 for_each_encoder_on_crtc(dev, crtc, encoder)
5072 if (encoder->post_disable)
5073 encoder->post_disable(encoder);
e4ca0612
PJ		 5074
5075 intel_crtc->active = false;
5076 intel_update_watermarks(crtc);
4f771f10
PZ		 5077}
5078
2dd24552
JB		 5079static void i9xx_pfit_enable(struct intel_crtc *crtc)
5080{
5081 struct drm_device *dev = crtc->base.dev;
5082 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5083 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5084
681a8504 5085 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5086 return;
5087
2dd24552 5088 /*
c0b03411
DV		 5089 * The panel fitter should only be adjusted whilst the pipe is disabled,
5090 * according to register description and PRM.
2dd24552 5091 */
c0b03411
DV		 5092 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5093 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5094
b074cec8
JB		 5095 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5096 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5097
5098 /* Border color in case we don't scale up to the full screen. Black by
5099 * default, change to something else for debugging. */
5100 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5101}
5102
d05410f9
DA		 5103static enum intel_display_power_domain port_to_power_domain(enum port port)
5104{
5105 switch (port) {
5106 case PORT_A:
5107 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5108 case PORT_B:
5109 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5110 case PORT_C:
5111 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5112 case PORT_D:
5113 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5114 case PORT_E:
5115 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5116 default:
5117 WARN_ON_ONCE(1);
5118 return POWER_DOMAIN_PORT_OTHER;
5119 }
5120}
5121
77d22dca
ID		 5122#define for_each_power_domain(domain, mask) \
5123 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5124 if ((1 << (domain)) & (mask))
5125
319be8ae
ID		 5126enum intel_display_power_domain
5127intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5128{
5129 struct drm_device *dev = intel_encoder->base.dev;
5130 struct intel_digital_port *intel_dig_port;
5131
5132 switch (intel_encoder->type) {
5133 case INTEL_OUTPUT_UNKNOWN:
5134 /* Only DDI platforms should ever use this output type */
5135 WARN_ON_ONCE(!HAS_DDI(dev));
5136 case INTEL_OUTPUT_DISPLAYPORT:
5137 case INTEL_OUTPUT_HDMI:
5138 case INTEL_OUTPUT_EDP:
5139 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5140 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5141 case INTEL_OUTPUT_DP_MST:
5142 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5143 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5144 case INTEL_OUTPUT_ANALOG:
5145 return POWER_DOMAIN_PORT_CRT;
5146 case INTEL_OUTPUT_DSI:
5147 return POWER_DOMAIN_PORT_DSI;
5148 default:
5149 return POWER_DOMAIN_PORT_OTHER;
5150 }
5151}
5152
5153static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5154{
319be8ae
ID		 5155 struct drm_device *dev = crtc->dev;
5156 struct intel_encoder *intel_encoder;
5157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5158 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5159 unsigned long mask;
5160 enum transcoder transcoder;
5161
292b990e
ML		 5162 if (!crtc->state->active)
5163 return 0;
5164
77d22dca
ID		 5165 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5166
5167 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5168 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5169 if (intel_crtc->config->pch_pfit.enabled ||
5170 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5171 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5172
319be8ae
ID		 5173 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5174 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5175
77d22dca
ID		 5176 return mask;
5177}
5178
292b990e 5179static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5180{
292b990e
ML		 5181 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5183 enum intel_display_power_domain domain;
5184 unsigned long domains, new_domains, old_domains;
77d22dca 5185
292b990e
ML		 5186 old_domains = intel_crtc->enabled_power_domains;
5187 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5188
292b990e
ML		 5189 domains = new_domains & ~old_domains;
5190
5191 for_each_power_domain(domain, domains)
5192 intel_display_power_get(dev_priv, domain);
5193
5194 return old_domains & ~new_domains;
5195}
5196
5197static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5198 unsigned long domains)
5199{
5200 enum intel_display_power_domain domain;
5201
5202 for_each_power_domain(domain, domains)
5203 intel_display_power_put(dev_priv, domain);
5204}
77d22dca 5205
292b990e
ML		 5206static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5207{
5208 struct drm_device *dev = state->dev;
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 unsigned long put_domains[I915_MAX_PIPES] = {};
5211 struct drm_crtc_state *crtc_state;
5212 struct drm_crtc *crtc;
5213 int i;
77d22dca 5214
292b990e
ML		 5215 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5216 if (needs_modeset(crtc->state))
5217 put_domains[to_intel_crtc(crtc)->pipe] =
5218 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5219 }
5220
27c329ed
ML		 5221 if (dev_priv->display.modeset_commit_cdclk) {
5222 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5223
5224 if (cdclk != dev_priv->cdclk_freq &&
5225 !WARN_ON(!state->allow_modeset))
5226 dev_priv->display.modeset_commit_cdclk(state);
5227 }
50f6e502 5228
292b990e
ML		 5229 for (i = 0; i < I915_MAX_PIPES; i++)
5230 if (put_domains[i])
5231 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5232}
5233
adafdc6f
MK		 5234static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5235{
5236 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5237
5238 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5239 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5240 return max_cdclk_freq;
5241 else if (IS_CHERRYVIEW(dev_priv))
5242 return max_cdclk_freq*95/100;
5243 else if (INTEL_INFO(dev_priv)->gen < 4)
5244 return 2*max_cdclk_freq*90/100;
5245 else
5246 return max_cdclk_freq*90/100;
5247}
5248
560a7ae4
DL		 5249static void intel_update_max_cdclk(struct drm_device *dev)
5250{
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252
5253 if (IS_SKYLAKE(dev)) {
5254 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5255
5256 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5257 dev_priv->max_cdclk_freq = 675000;
5258 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5259 dev_priv->max_cdclk_freq = 540000;
5260 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5261 dev_priv->max_cdclk_freq = 450000;
5262 else
5263 dev_priv->max_cdclk_freq = 337500;
5264 } else if (IS_BROADWELL(dev)) {
5265 /*
5266 * FIXME with extra cooling we can allow
5267 * 540 MHz for ULX and 675 Mhz for ULT.
5268 * How can we know if extra cooling is
5269 * available? PCI ID, VTB, something else?
5270 */
5271 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5272 dev_priv->max_cdclk_freq = 450000;
5273 else if (IS_BDW_ULX(dev))
5274 dev_priv->max_cdclk_freq = 450000;
5275 else if (IS_BDW_ULT(dev))
5276 dev_priv->max_cdclk_freq = 540000;
5277 else
5278 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5279 } else if (IS_CHERRYVIEW(dev)) {
5280 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5281 } else if (IS_VALLEYVIEW(dev)) {
5282 dev_priv->max_cdclk_freq = 400000;
5283 } else {
5284 /* otherwise assume cdclk is fixed */
5285 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5286 }
5287
adafdc6f
MK		 5288 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5289
560a7ae4
DL		 5290 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5291 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5292
5293 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5294 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5295}
5296
5297static void intel_update_cdclk(struct drm_device *dev)
5298{
5299 struct drm_i915_private *dev_priv = dev->dev_private;
5300
5301 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5302 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5303 dev_priv->cdclk_freq);
5304
5305 /*
5306 * Program the gmbus_freq based on the cdclk frequency.
5307 * BSpec erroneously claims we should aim for 4MHz, but
5308 * in fact 1MHz is the correct frequency.
5309 */
5310 if (IS_VALLEYVIEW(dev)) {
5311 /*
5312 * Program the gmbus_freq based on the cdclk frequency.
5313 * BSpec erroneously claims we should aim for 4MHz, but
5314 * in fact 1MHz is the correct frequency.
5315 */
5316 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5317 }
5318
5319 if (dev_priv->max_cdclk_freq == 0)
5320 intel_update_max_cdclk(dev);
5321}
5322
70d0c574 5323static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5324{
5325 struct drm_i915_private *dev_priv = dev->dev_private;
5326 uint32_t divider;
5327 uint32_t ratio;
5328 uint32_t current_freq;
5329 int ret;
5330
5331 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5332 switch (frequency) {
5333 case 144000:
5334 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5335 ratio = BXT_DE_PLL_RATIO(60);
5336 break;
5337 case 288000:
5338 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5339 ratio = BXT_DE_PLL_RATIO(60);
5340 break;
5341 case 384000:
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5343 ratio = BXT_DE_PLL_RATIO(60);
5344 break;
5345 case 576000:
5346 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5347 ratio = BXT_DE_PLL_RATIO(60);
5348 break;
5349 case 624000:
5350 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5351 ratio = BXT_DE_PLL_RATIO(65);
5352 break;
5353 case 19200:
5354 /*
5355 * Bypass frequency with DE PLL disabled. Init ratio, divider
5356 * to suppress GCC warning.
5357 */
5358 ratio = 0;
5359 divider = 0;
5360 break;
5361 default:
5362 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5363
5364 return;
5365 }
5366
5367 mutex_lock(&dev_priv->rps.hw_lock);
5368 /* Inform power controller of upcoming frequency change */
5369 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5370 0x80000000);
5371 mutex_unlock(&dev_priv->rps.hw_lock);
5372
5373 if (ret) {
5374 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5375 ret, frequency);
5376 return;
5377 }
5378
5379 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5380 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5381 current_freq = current_freq * 500 + 1000;
5382
5383 /*
5384 * DE PLL has to be disabled when
5385 * - setting to 19.2MHz (bypass, PLL isn't used)
5386 * - before setting to 624MHz (PLL needs toggling)
5387 * - before setting to any frequency from 624MHz (PLL needs toggling)
5388 */
5389 if (frequency == 19200 || frequency == 624000 ||
5390 current_freq == 624000) {
5391 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5392 /* Timeout 200us */
5393 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5394 1))
5395 DRM_ERROR("timout waiting for DE PLL unlock\n");
5396 }
5397
5398 if (frequency != 19200) {
5399 uint32_t val;
5400
5401 val = I915_READ(BXT_DE_PLL_CTL);
5402 val &= ~BXT_DE_PLL_RATIO_MASK;
5403 val |= ratio;
5404 I915_WRITE(BXT_DE_PLL_CTL, val);
5405
5406 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5407 /* Timeout 200us */
5408 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5409 DRM_ERROR("timeout waiting for DE PLL lock\n");
5410
5411 val = I915_READ(CDCLK_CTL);
5412 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5413 val |= divider;
5414 /*
5415 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5416 * enable otherwise.
5417 */
5418 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5419 if (frequency >= 500000)
5420 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5421
5422 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5423 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5424 val |= (frequency - 1000) / 500;
5425 I915_WRITE(CDCLK_CTL, val);
5426 }
5427
5428 mutex_lock(&dev_priv->rps.hw_lock);
5429 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5430 DIV_ROUND_UP(frequency, 25000));
5431 mutex_unlock(&dev_priv->rps.hw_lock);
5432
5433 if (ret) {
5434 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5435 ret, frequency);
5436 return;
5437 }
5438
a47871bd 5439 intel_update_cdclk(dev);
f8437dd1
VK		 5440}
5441
5442void broxton_init_cdclk(struct drm_device *dev)
5443{
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445 uint32_t val;
5446
5447 /*
5448 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5449 * or else the reset will hang because there is no PCH to respond.
5450 * Move the handshake programming to initialization sequence.
5451 * Previously was left up to BIOS.
5452 */
5453 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5454 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5455 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5456
5457 /* Enable PG1 for cdclk */
5458 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5459
5460 /* check if cd clock is enabled */
5461 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5462 DRM_DEBUG_KMS("Display already initialized\n");
5463 return;
5464 }
5465
5466 /*
5467 * FIXME:
5468 * - The initial CDCLK needs to be read from VBT.
5469 * Need to make this change after VBT has changes for BXT.
5470 * - check if setting the max (or any) cdclk freq is really necessary
5471 * here, it belongs to modeset time
5472 */
5473 broxton_set_cdclk(dev, 624000);
5474
5475 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5476 POSTING_READ(DBUF_CTL);
5477
f8437dd1
VK		 5478 udelay(10);
5479
5480 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5481 DRM_ERROR("DBuf power enable timeout!\n");
5482}
5483
5484void broxton_uninit_cdclk(struct drm_device *dev)
5485{
5486 struct drm_i915_private *dev_priv = dev->dev_private;
5487
5488 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5489 POSTING_READ(DBUF_CTL);
5490
f8437dd1
VK		 5491 udelay(10);
5492
5493 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5494 DRM_ERROR("DBuf power disable timeout!\n");
5495
5496 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5497 broxton_set_cdclk(dev, 19200);
5498
5499 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5500}
5501
5d96d8af
DL		 5502static const struct skl_cdclk_entry {
5503 unsigned int freq;
5504 unsigned int vco;
5505} skl_cdclk_frequencies[] = {
5506 { .freq = 308570, .vco = 8640 },
5507 { .freq = 337500, .vco = 8100 },
5508 { .freq = 432000, .vco = 8640 },
5509 { .freq = 450000, .vco = 8100 },
5510 { .freq = 540000, .vco = 8100 },
5511 { .freq = 617140, .vco = 8640 },
5512 { .freq = 675000, .vco = 8100 },
5513};
5514
5515static unsigned int skl_cdclk_decimal(unsigned int freq)
5516{
5517 return (freq - 1000) / 500;
5518}
5519
5520static unsigned int skl_cdclk_get_vco(unsigned int freq)
5521{
5522 unsigned int i;
5523
5524 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5525 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5526
5527 if (e->freq == freq)
5528 return e->vco;
5529 }
5530
5531 return 8100;
5532}
5533
5534static void
5535skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5536{
5537 unsigned int min_freq;
5538 u32 val;
5539
5540 /* select the minimum CDCLK before enabling DPLL 0 */
5541 val = I915_READ(CDCLK_CTL);
5542 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5543 val |= CDCLK_FREQ_337_308;
5544
5545 if (required_vco == 8640)
5546 min_freq = 308570;
5547 else
5548 min_freq = 337500;
5549
5550 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5551
5552 I915_WRITE(CDCLK_CTL, val);
5553 POSTING_READ(CDCLK_CTL);
5554
5555 /*
5556 * We always enable DPLL0 with the lowest link rate possible, but still
5557 * taking into account the VCO required to operate the eDP panel at the
5558 * desired frequency. The usual DP link rates operate with a VCO of
5559 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5560 * The modeset code is responsible for the selection of the exact link
5561 * rate later on, with the constraint of choosing a frequency that
5562 * works with required_vco.
5563 */
5564 val = I915_READ(DPLL_CTRL1);
5565
5566 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5567 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5568 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5569 if (required_vco == 8640)
5570 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5571 SKL_DPLL0);
5572 else
5573 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5574 SKL_DPLL0);
5575
5576 I915_WRITE(DPLL_CTRL1, val);
5577 POSTING_READ(DPLL_CTRL1);
5578
5579 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5580
5581 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5582 DRM_ERROR("DPLL0 not locked\n");
5583}
5584
5585static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5586{
5587 int ret;
5588 u32 val;
5589
5590 /* inform PCU we want to change CDCLK */
5591 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5592 mutex_lock(&dev_priv->rps.hw_lock);
5593 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5594 mutex_unlock(&dev_priv->rps.hw_lock);
5595
5596 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5597}
5598
5599static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5600{
5601 unsigned int i;
5602
5603 for (i = 0; i < 15; i++) {
5604 if (skl_cdclk_pcu_ready(dev_priv))
5605 return true;
5606 udelay(10);
5607 }
5608
5609 return false;
5610}
5611
5612static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5613{
560a7ae4 5614 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5615 u32 freq_select, pcu_ack;
5616
5617 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5618
5619 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5620 DRM_ERROR("failed to inform PCU about cdclk change\n");
5621 return;
5622 }
5623
5624 /* set CDCLK_CTL */
5625 switch(freq) {
5626 case 450000:
5627 case 432000:
5628 freq_select = CDCLK_FREQ_450_432;
5629 pcu_ack = 1;
5630 break;
5631 case 540000:
5632 freq_select = CDCLK_FREQ_540;
5633 pcu_ack = 2;
5634 break;
5635 case 308570:
5636 case 337500:
5637 default:
5638 freq_select = CDCLK_FREQ_337_308;
5639 pcu_ack = 0;
5640 break;
5641 case 617140:
5642 case 675000:
5643 freq_select = CDCLK_FREQ_675_617;
5644 pcu_ack = 3;
5645 break;
5646 }
5647
5648 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5649 POSTING_READ(CDCLK_CTL);
5650
5651 /* inform PCU of the change */
5652 mutex_lock(&dev_priv->rps.hw_lock);
5653 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5654 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5655
5656 intel_update_cdclk(dev);
5d96d8af
DL		 5657}
5658
5659void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5660{
5661 /* disable DBUF power */
5662 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5663 POSTING_READ(DBUF_CTL);
5664
5665 udelay(10);
5666
5667 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5668 DRM_ERROR("DBuf power disable timeout\n");
5669
5670 /* disable DPLL0 */
5671 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5672 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5673 DRM_ERROR("Couldn't disable DPLL0\n");
5674
5675 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5676}
5677
5678void skl_init_cdclk(struct drm_i915_private *dev_priv)
5679{
5680 u32 val;
5681 unsigned int required_vco;
5682
5683 /* enable PCH reset handshake */
5684 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5685 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5686
5687 /* enable PG1 and Misc I/O */
5688 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5689
39d9b85a
GW		 5690 /* DPLL0 not enabled (happens on early BIOS versions) */
5691 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5692 /* enable DPLL0 */
5693 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5694 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5695 }
5696
5d96d8af
DL		 5697 /* set CDCLK to the frequency the BIOS chose */
5698 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5699
5700 /* enable DBUF power */
5701 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5702 POSTING_READ(DBUF_CTL);
5703
5704 udelay(10);
5705
5706 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5707 DRM_ERROR("DBuf power enable timeout\n");
5708}
5709
dfcab17e 5710/* returns HPLL frequency in kHz */
f8bf63fd 5711static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5712{
586f49dc 5713 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5714
586f49dc 5715 /* Obtain SKU information */
a580516d 5716 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5717 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5718 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5719 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5720
dfcab17e 5721 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5722}
5723
5724/* Adjust CDclk dividers to allow high res or save power if possible */
5725static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5726{
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 u32 val, cmd;
5729
164dfd28
VK		 5730 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5731 != dev_priv->cdclk_freq);
d60c4473 5732
dfcab17e 5733 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5734 cmd = 2;
dfcab17e 5735 else if (cdclk == 266667)
30a970c6
JB		 5736 cmd = 1;
5737 else
5738 cmd = 0;
5739
5740 mutex_lock(&dev_priv->rps.hw_lock);
5741 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5742 val &= ~DSPFREQGUAR_MASK;
5743 val |= (cmd << DSPFREQGUAR_SHIFT);
5744 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5745 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5746 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5747 50)) {
5748 DRM_ERROR("timed out waiting for CDclk change\n");
5749 }
5750 mutex_unlock(&dev_priv->rps.hw_lock);
5751
54433e91
VS		 5752 mutex_lock(&dev_priv->sb_lock);
5753
dfcab17e 5754 if (cdclk == 400000) {
6bcda4f0 5755 u32 divider;
30a970c6 5756
6bcda4f0 5757 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5758
30a970c6
JB		 5759 /* adjust cdclk divider */
5760 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5761 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5762 val |= divider;
5763 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5764
5765 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5766 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5767 50))
5768 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5769 }
5770
30a970c6
JB		 5771 /* adjust self-refresh exit latency value */
5772 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5773 val &= ~0x7f;
5774
5775 /*
5776 * For high bandwidth configs, we set a higher latency in the bunit
5777 * so that the core display fetch happens in time to avoid underruns.
5778 */
dfcab17e 5779 if (cdclk == 400000)
30a970c6
JB		 5780 val |= 4500 / 250; /* 4.5 usec */
5781 else
5782 val |= 3000 / 250; /* 3.0 usec */
5783 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5784
a580516d 5785 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5786
b6283055 5787 intel_update_cdclk(dev);
30a970c6
JB		 5788}
5789
383c5a6a
VS		 5790static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5791{
5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793 u32 val, cmd;
5794
164dfd28
VK		 5795 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5796 != dev_priv->cdclk_freq);
383c5a6a
VS		 5797
5798 switch (cdclk) {
383c5a6a
VS		 5799 case 333333:
5800 case 320000:
383c5a6a 5801 case 266667:
383c5a6a 5802 case 200000:
383c5a6a
VS		 5803 break;
5804 default:
5f77eeb0 5805 MISSING_CASE(cdclk);
383c5a6a
VS		 5806 return;
5807 }
5808
9d0d3fda
VS		 5809 /*
5810 * Specs are full of misinformation, but testing on actual
5811 * hardware has shown that we just need to write the desired
5812 * CCK divider into the Punit register.
5813 */
5814 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5815
383c5a6a
VS		 5816 mutex_lock(&dev_priv->rps.hw_lock);
5817 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5818 val &= ~DSPFREQGUAR_MASK_CHV;
5819 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5820 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5821 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5822 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5823 50)) {
5824 DRM_ERROR("timed out waiting for CDclk change\n");
5825 }
5826 mutex_unlock(&dev_priv->rps.hw_lock);
5827
b6283055 5828 intel_update_cdclk(dev);
383c5a6a
VS		 5829}
5830
30a970c6
JB		 5831static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5832 int max_pixclk)
5833{
6bcda4f0 5834 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5835 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5836
30a970c6
JB		 5837 /*
5838 * Really only a few cases to deal with, as only 4 CDclks are supported:
5839 * 200MHz
5840 * 267MHz
29dc7ef3 5841 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5842 * 400MHz (VLV only)
5843 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5844 * of the lower bin and adjust if needed.
e37c67a1
VS		 5845 *
5846 * We seem to get an unstable or solid color picture at 200MHz.
5847 * Not sure what's wrong. For now use 200MHz only when all pipes
5848 * are off.
30a970c6 5849 */
6cca3195
VS		 5850 if (!IS_CHERRYVIEW(dev_priv) &&
5851 max_pixclk > freq_320*limit/100)
dfcab17e 5852 return 400000;
6cca3195 5853 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5854 return freq_320;
e37c67a1 5855 else if (max_pixclk > 0)
dfcab17e 5856 return 266667;
e37c67a1
VS		 5857 else
5858 return 200000;
30a970c6
JB		 5859}
5860
f8437dd1
VK		 5861static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5862 int max_pixclk)
5863{
5864 /*
5865 * FIXME:
5866 * - remove the guardband, it's not needed on BXT
5867 * - set 19.2MHz bypass frequency if there are no active pipes
5868 */
5869 if (max_pixclk > 576000*9/10)
5870 return 624000;
5871 else if (max_pixclk > 384000*9/10)
5872 return 576000;
5873 else if (max_pixclk > 288000*9/10)
5874 return 384000;
5875 else if (max_pixclk > 144000*9/10)
5876 return 288000;
5877 else
5878 return 144000;
5879}
5880
a821fc46
ACO		 5881/* Compute the max pixel clock for new configuration. Uses atomic state if
5882 * that's non-NULL, look at current state otherwise. */
5883static int intel_mode_max_pixclk(struct drm_device *dev,
5884 struct drm_atomic_state *state)
30a970c6 5885{
30a970c6 5886 struct intel_crtc *intel_crtc;
304603f4 5887 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5888 int max_pixclk = 0;
5889
d3fcc808 5890 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5891 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5892 if (IS_ERR(crtc_state))
5893 return PTR_ERR(crtc_state);
5894
5895 if (!crtc_state->base.enable)
5896 continue;
5897
5898 max_pixclk = max(max_pixclk,
5899 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5900 }
5901
5902 return max_pixclk;
5903}
5904
27c329ed 5905static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5906{
27c329ed
ML		 5907 struct drm_device *dev = state->dev;
5908 struct drm_i915_private *dev_priv = dev->dev_private;
5909 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5910
304603f4
ACO		 5911 if (max_pixclk < 0)
5912 return max_pixclk;
30a970c6 5913
27c329ed
ML		 5914 to_intel_atomic_state(state)->cdclk =
5915 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5916
27c329ed
ML		 5917 return 0;
5918}
304603f4 5919
27c329ed
ML		 5920static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5921{
5922 struct drm_device *dev = state->dev;
5923 struct drm_i915_private *dev_priv = dev->dev_private;
5924 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5925
27c329ed
ML		 5926 if (max_pixclk < 0)
5927 return max_pixclk;
85a96e7a 5928
27c329ed
ML		 5929 to_intel_atomic_state(state)->cdclk =
5930 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5931
27c329ed 5932 return 0;
30a970c6
JB		 5933}
5934
1e69cd74
VS		 5935static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5936{
5937 unsigned int credits, default_credits;
5938
5939 if (IS_CHERRYVIEW(dev_priv))
5940 default_credits = PFI_CREDIT(12);
5941 else
5942 default_credits = PFI_CREDIT(8);
5943
164dfd28 5944 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5945 /* CHV suggested value is 31 or 63 */
5946 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5947 credits = PFI_CREDIT_63;
1e69cd74
VS		 5948 else
5949 credits = PFI_CREDIT(15);
5950 } else {
5951 credits = default_credits;
5952 }
5953
5954 /*
5955 * WA - write default credits before re-programming
5956 * FIXME: should we also set the resend bit here?
5957 */
5958 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5959 default_credits);
5960
5961 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5962 credits | PFI_CREDIT_RESEND);
5963
5964 /*
5965 * FIXME is this guaranteed to clear
5966 * immediately or should we poll for it?
5967 */
5968 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5969}
5970
27c329ed 5971static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5972{
a821fc46 5973 struct drm_device *dev = old_state->dev;
27c329ed 5974 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5975 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5976
27c329ed
ML		 5977 /*
5978 * FIXME: We can end up here with all power domains off, yet
5979 * with a CDCLK frequency other than the minimum. To account
5980 * for this take the PIPE-A power domain, which covers the HW
5981 * blocks needed for the following programming. This can be
5982 * removed once it's guaranteed that we get here either with
5983 * the minimum CDCLK set, or the required power domains
5984 * enabled.
5985 */
5986 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5987
27c329ed
ML		 5988 if (IS_CHERRYVIEW(dev))
5989 cherryview_set_cdclk(dev, req_cdclk);
5990 else
5991 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5992
27c329ed 5993 vlv_program_pfi_credits(dev_priv);
1e69cd74 5994
27c329ed 5995 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5996}
5997
89b667f8
JB		 5998static void valleyview_crtc_enable(struct drm_crtc *crtc)
5999{
6000 struct drm_device *dev = crtc->dev;
a72e4c9f 6001 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003 struct intel_encoder *encoder;
6004 int pipe = intel_crtc->pipe;
23538ef1 6005 bool is_dsi;
89b667f8 6006
53d9f4e9 6007 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6008 return;
6009
409ee761 6010 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6011
6e3c9717 6012 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6013 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6014
6015 intel_set_pipe_timings(intel_crtc);
6016
c14b0485
VS		 6017 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6018 struct drm_i915_private *dev_priv = dev->dev_private;
6019
6020 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6021 I915_WRITE(CHV_CANVAS(pipe), 0);
6022 }
6023
5b18e57c
DV		 6024 i9xx_set_pipeconf(intel_crtc);
6025
89b667f8 6026 intel_crtc->active = true;
89b667f8 6027
a72e4c9f 6028 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6029
89b667f8
JB		 6030 for_each_encoder_on_crtc(dev, crtc, encoder)
6031 if (encoder->pre_pll_enable)
6032 encoder->pre_pll_enable(encoder);
6033
9d556c99 6034 if (!is_dsi) {
c0b4c660
VS		 6035 if (IS_CHERRYVIEW(dev)) {
6036 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6037 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6038 } else {
6039 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6040 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6041 }
9d556c99 6042 }
89b667f8
JB		 6043
6044 for_each_encoder_on_crtc(dev, crtc, encoder)
6045 if (encoder->pre_enable)
6046 encoder->pre_enable(encoder);
6047
2dd24552
JB		 6048 i9xx_pfit_enable(intel_crtc);
6049
63cbb074
VS		 6050 intel_crtc_load_lut(crtc);
6051
e1fdc473 6052 intel_enable_pipe(intel_crtc);
be6a6f8e 6053
4b3a9526
VS		 6054 assert_vblank_disabled(crtc);
6055 drm_crtc_vblank_on(crtc);
6056
f9b61ff6
DV		 6057 for_each_encoder_on_crtc(dev, crtc, encoder)
6058 encoder->enable(encoder);
89b667f8
JB		 6059}
6060
f13c2ef3
DV		 6061static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6062{
6063 struct drm_device *dev = crtc->base.dev;
6064 struct drm_i915_private *dev_priv = dev->dev_private;
6065
6e3c9717
ACO		 6066 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6067 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6068}
6069
0b8765c6 6070static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6071{
6072 struct drm_device *dev = crtc->dev;
a72e4c9f 6073 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6075 struct intel_encoder *encoder;
79e53945 6076 int pipe = intel_crtc->pipe;
79e53945 6077
53d9f4e9 6078 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6079 return;
6080
f13c2ef3
DV		 6081 i9xx_set_pll_dividers(intel_crtc);
6082
6e3c9717 6083 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6084 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6085
6086 intel_set_pipe_timings(intel_crtc);
6087
5b18e57c
DV		 6088 i9xx_set_pipeconf(intel_crtc);
6089
f7abfe8b 6090 intel_crtc->active = true;
6b383a7f 6091
4a3436e8 6092 if (!IS_GEN2(dev))
a72e4c9f 6093 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6094
9d6d9f19
MK		 6095 for_each_encoder_on_crtc(dev, crtc, encoder)
6096 if (encoder->pre_enable)
6097 encoder->pre_enable(encoder);
6098
f6736a1a
DV		 6099 i9xx_enable_pll(intel_crtc);
6100
2dd24552
JB		 6101 i9xx_pfit_enable(intel_crtc);
6102
63cbb074
VS		 6103 intel_crtc_load_lut(crtc);
6104
f37fcc2a 6105 intel_update_watermarks(crtc);
e1fdc473 6106 intel_enable_pipe(intel_crtc);
be6a6f8e 6107
4b3a9526
VS		 6108 assert_vblank_disabled(crtc);
6109 drm_crtc_vblank_on(crtc);
6110
f9b61ff6
DV		 6111 for_each_encoder_on_crtc(dev, crtc, encoder)
6112 encoder->enable(encoder);
0b8765c6 6113}
79e53945 6114
87476d63
DV		 6115static void i9xx_pfit_disable(struct intel_crtc *crtc)
6116{
6117 struct drm_device *dev = crtc->base.dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6119
6e3c9717 6120 if (!crtc->config->gmch_pfit.control)
328d8e82 6121 return;
87476d63 6122
328d8e82 6123 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6124
328d8e82
DV		 6125 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6126 I915_READ(PFIT_CONTROL));
6127 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6128}
6129
0b8765c6
JB		 6130static void i9xx_crtc_disable(struct drm_crtc *crtc)
6131{
6132 struct drm_device *dev = crtc->dev;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
6134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6135 struct intel_encoder *encoder;
0b8765c6 6136 int pipe = intel_crtc->pipe;
ef9c3aee 6137
6304cd91
VS		 6138 /*
6139 * On gen2 planes are double buffered but the pipe isn't, so we must
6140 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6141 * We also need to wait on all gmch platforms because of the
6142 * self-refresh mode constraint explained above.
6304cd91 6143 */
564ed191 6144 intel_wait_for_vblank(dev, pipe);
6304cd91 6145
4b3a9526
VS		 6146 for_each_encoder_on_crtc(dev, crtc, encoder)
6147 encoder->disable(encoder);
6148
f9b61ff6
DV		 6149 drm_crtc_vblank_off(crtc);
6150 assert_vblank_disabled(crtc);
6151
575f7ab7 6152 intel_disable_pipe(intel_crtc);
24a1f16d 6153
87476d63 6154 i9xx_pfit_disable(intel_crtc);
24a1f16d 6155
89b667f8
JB		 6156 for_each_encoder_on_crtc(dev, crtc, encoder)
6157 if (encoder->post_disable)
6158 encoder->post_disable(encoder);
6159
409ee761 6160 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6161 if (IS_CHERRYVIEW(dev))
6162 chv_disable_pll(dev_priv, pipe);
6163 else if (IS_VALLEYVIEW(dev))
6164 vlv_disable_pll(dev_priv, pipe);
6165 else
1c4e0274 6166 i9xx_disable_pll(intel_crtc);
076ed3b2 6167 }
0b8765c6 6168
d6db995f
VS		 6169 for_each_encoder_on_crtc(dev, crtc, encoder)
6170 if (encoder->post_pll_disable)
6171 encoder->post_pll_disable(encoder);
6172
4a3436e8 6173 if (!IS_GEN2(dev))
a72e4c9f 6174 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6175
6176 intel_crtc->active = false;
6177 intel_update_watermarks(crtc);
0b8765c6
JB		 6178}
6179
b17d48e2
ML		 6180static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6181{
6182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6183 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6184 enum intel_display_power_domain domain;
6185 unsigned long domains;
6186
6187 if (!intel_crtc->active)
6188 return;
6189
a539205a
ML		 6190 if (to_intel_plane_state(crtc->primary->state)->visible) {
6191 intel_crtc_wait_for_pending_flips(crtc);
6192 intel_pre_disable_primary(crtc);
6193 }
6194
d032ffa0 6195 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6196 dev_priv->display.crtc_disable(crtc);
1f7457b1 6197 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6198
6199 domains = intel_crtc->enabled_power_domains;
6200 for_each_power_domain(domain, domains)
6201 intel_display_power_put(dev_priv, domain);
6202 intel_crtc->enabled_power_domains = 0;
6203}
6204
6b72d486
ML		 6205/*
6206 * turn all crtc's off, but do not adjust state
6207 * This has to be paired with a call to intel_modeset_setup_hw_state.
6208 */
70e0bd74 6209int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6210{
70e0bd74
ML		 6211 struct drm_mode_config *config = &dev->mode_config;
6212 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6213 struct drm_atomic_state *state;
6b72d486 6214 struct drm_crtc *crtc;
70e0bd74
ML		 6215 unsigned crtc_mask = 0;
6216 int ret = 0;
6217
6218 if (WARN_ON(!ctx))
6219 return 0;
6220
6221 lockdep_assert_held(&ctx->ww_ctx);
6222 state = drm_atomic_state_alloc(dev);
6223 if (WARN_ON(!state))
6224 return -ENOMEM;
6225
6226 state->acquire_ctx = ctx;
6227 state->allow_modeset = true;
6228
6229 for_each_crtc(dev, crtc) {
6230 struct drm_crtc_state *crtc_state =
6231 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6232
70e0bd74
ML		 6233 ret = PTR_ERR_OR_ZERO(crtc_state);
6234 if (ret)
6235 goto free;
6236
6237 if (!crtc_state->active)
6238 continue;
6239
6240 crtc_state->active = false;
6241 crtc_mask |= 1 << drm_crtc_index(crtc);
6242 }
6243
6244 if (crtc_mask) {
74c090b1 6245 ret = drm_atomic_commit(state);
70e0bd74
ML		 6246
6247 if (!ret) {
6248 for_each_crtc(dev, crtc)
6249 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6250 crtc->state->active = true;
6251
6252 return ret;
6253 }
6254 }
6255
6256free:
6257 if (ret)
6258 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6259 drm_atomic_state_free(state);
6260 return ret;
ee7b9f93
JB		 6261}
6262
ea5b213a 6263void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6264{
4ef69c7a 6265 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6266
ea5b213a
CW		 6267 drm_encoder_cleanup(encoder);
6268 kfree(intel_encoder);
7e7d76c3
JB		 6269}
6270
0a91ca29
DV		 6271/* Cross check the actual hw state with our own modeset state tracking (and it's
6272 * internal consistency). */
b980514c 6273static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6274{
35dd3c64
ML		 6275 struct drm_crtc *crtc = connector->base.state->crtc;
6276
6277 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6278 connector->base.base.id,
6279 connector->base.name);
6280
0a91ca29 6281 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6282 struct drm_encoder *encoder = &connector->encoder->base;
6283 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6284
35dd3c64
ML		 6285 I915_STATE_WARN(!crtc,
6286 "connector enabled without attached crtc\n");
0a91ca29 6287
35dd3c64
ML		 6288 if (!crtc)
6289 return;
6290
6291 I915_STATE_WARN(!crtc->state->active,
6292 "connector is active, but attached crtc isn't\n");
6293
6294 if (!encoder)
6295 return;
6296
6297 I915_STATE_WARN(conn_state->best_encoder != encoder,
6298 "atomic encoder doesn't match attached encoder\n");
6299
6300 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6301 "attached encoder crtc differs from connector crtc\n");
6302 } else {
4d688a2a
ML		 6303 I915_STATE_WARN(crtc && crtc->state->active,
6304 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6305 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6306 "best encoder set without crtc!\n");
0a91ca29 6307 }
79e53945
JB		 6308}
6309
08d9bc92
ACO		 6310int intel_connector_init(struct intel_connector *connector)
6311{
6312 struct drm_connector_state *connector_state;
6313
6314 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6315 if (!connector_state)
6316 return -ENOMEM;
6317
6318 connector->base.state = connector_state;
6319 return 0;
6320}
6321
6322struct intel_connector *intel_connector_alloc(void)
6323{
6324 struct intel_connector *connector;
6325
6326 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6327 if (!connector)
6328 return NULL;
6329
6330 if (intel_connector_init(connector) < 0) {
6331 kfree(connector);
6332 return NULL;
6333 }
6334
6335 return connector;
6336}
6337
f0947c37
DV		 6338/* Simple connector->get_hw_state implementation for encoders that support only
6339 * one connector and no cloning and hence the encoder state determines the state
6340 * of the connector. */
6341bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6342{
24929352 6343 enum pipe pipe = 0;
f0947c37 6344 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6345
f0947c37 6346 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6347}
6348
6d293983 6349static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6350{
6d293983
ACO		 6351 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6352 return crtc_state->fdi_lanes;
d272ddfa
VS		 6353
6354 return 0;
6355}
6356
6d293983 6357static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6358 struct intel_crtc_state *pipe_config)
1857e1da 6359{
6d293983
ACO		 6360 struct drm_atomic_state *state = pipe_config->base.state;
6361 struct intel_crtc *other_crtc;
6362 struct intel_crtc_state *other_crtc_state;
6363
1857e1da
DV		 6364 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6365 pipe_name(pipe), pipe_config->fdi_lanes);
6366 if (pipe_config->fdi_lanes > 4) {
6367 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6368 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6369 return -EINVAL;
1857e1da
DV		 6370 }
6371
bafb6553 6372 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6373 if (pipe_config->fdi_lanes > 2) {
6374 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6375 pipe_config->fdi_lanes);
6d293983 6376 return -EINVAL;
1857e1da 6377 } else {
6d293983 6378 return 0;
1857e1da
DV		 6379 }
6380 }
6381
6382 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6383 return 0;
1857e1da
DV		 6384
6385 /* Ivybridge 3 pipe is really complicated */
6386 switch (pipe) {
6387 case PIPE_A:
6d293983 6388 return 0;
1857e1da 6389 case PIPE_B:
6d293983
ACO		 6390 if (pipe_config->fdi_lanes <= 2)
6391 return 0;
6392
6393 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6394 other_crtc_state =
6395 intel_atomic_get_crtc_state(state, other_crtc);
6396 if (IS_ERR(other_crtc_state))
6397 return PTR_ERR(other_crtc_state);
6398
6399 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6400 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6401 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6402 return -EINVAL;
1857e1da 6403 }
6d293983 6404 return 0;
1857e1da 6405 case PIPE_C:
251cc67c
VS		 6406 if (pipe_config->fdi_lanes > 2) {
6407 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6408 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6409 return -EINVAL;
251cc67c 6410 }
6d293983
ACO		 6411
6412 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6413 other_crtc_state =
6414 intel_atomic_get_crtc_state(state, other_crtc);
6415 if (IS_ERR(other_crtc_state))
6416 return PTR_ERR(other_crtc_state);
6417
6418 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6419 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6420 return -EINVAL;
1857e1da 6421 }
6d293983 6422 return 0;
1857e1da
DV		 6423 default:
6424 BUG();
6425 }
6426}
6427
e29c22c0
DV		 6428#define RETRY 1
6429static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6430 struct intel_crtc_state *pipe_config)
877d48d5 6431{
1857e1da 6432 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6433 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6434 int lane, link_bw, fdi_dotclock, ret;
6435 bool needs_recompute = false;
877d48d5 6436
e29c22c0 6437retry:
877d48d5
DV		 6438 /* FDI is a binary signal running at ~2.7GHz, encoding
6439 * each output octet as 10 bits. The actual frequency
6440 * is stored as a divider into a 100MHz clock, and the
6441 * mode pixel clock is stored in units of 1KHz.
6442 * Hence the bw of each lane in terms of the mode signal
6443 * is:
6444 */
6445 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6446
241bfc38 6447 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6448
2bd89a07 6449 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6450 pipe_config->pipe_bpp);
6451
6452 pipe_config->fdi_lanes = lane;
6453
2bd89a07 6454 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6455 link_bw, &pipe_config->fdi_m_n);
1857e1da 6456
6d293983
ACO		 6457 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6458 intel_crtc->pipe, pipe_config);
6459 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6460 pipe_config->pipe_bpp -= 2*3;
6461 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6462 pipe_config->pipe_bpp);
6463 needs_recompute = true;
6464 pipe_config->bw_constrained = true;
6465
6466 goto retry;
6467 }
6468
6469 if (needs_recompute)
6470 return RETRY;
6471
6d293983 6472 return ret;
877d48d5
DV		 6473}
6474
8cfb3407
VS		 6475static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6476 struct intel_crtc_state *pipe_config)
6477{
6478 if (pipe_config->pipe_bpp > 24)
6479 return false;
6480
6481 /* HSW can handle pixel rate up to cdclk? */
6482 if (IS_HASWELL(dev_priv->dev))
6483 return true;
6484
6485 /*
b432e5cf
VS		 6486 * We compare against max which means we must take
6487 * the increased cdclk requirement into account when
6488 * calculating the new cdclk.
6489 *
6490 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6491 */
6492 return ilk_pipe_pixel_rate(pipe_config) <=
6493 dev_priv->max_cdclk_freq * 95 / 100;
6494}
6495
42db64ef 6496static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6497 struct intel_crtc_state *pipe_config)
42db64ef 6498{
8cfb3407
VS		 6499 struct drm_device *dev = crtc->base.dev;
6500 struct drm_i915_private *dev_priv = dev->dev_private;
6501
d330a953 6502 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6503 hsw_crtc_supports_ips(crtc) &&
6504 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6505}
6506
a43f6e0f 6507static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6508 struct intel_crtc_state *pipe_config)
79e53945 6509{
a43f6e0f 6510 struct drm_device *dev = crtc->base.dev;
8bd31e67 6511 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6512 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6513
ad3a4479 6514 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6515 if (INTEL_INFO(dev)->gen < 4) {
44913155 6516 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6517
6518 /*
6519 * Enable pixel doubling when the dot clock
6520 * is > 90% of the (display) core speed.
6521 *
b397c96b
VS		 6522 * GDG double wide on either pipe,
6523 * otherwise pipe A only.
cf532bb2 6524 */
b397c96b 6525 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6526 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6527 clock_limit *= 2;
cf532bb2 6528 pipe_config->double_wide = true;
ad3a4479
VS		 6529 }
6530
241bfc38 6531 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6532 return -EINVAL;
2c07245f 6533 }
89749350 6534
1d1d0e27
VS		 6535 /*
6536 * Pipe horizontal size must be even in:
6537 * - DVO ganged mode
6538 * - LVDS dual channel mode
6539 * - Double wide pipe
6540 */
a93e255f 6541 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6542 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6543 pipe_config->pipe_src_w &= ~1;
6544
8693a824
DL		 6545 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6546 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6547 */
6548 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6549 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6550 return -EINVAL;
44f46b42 6551
f5adf94e 6552 if (HAS_IPS(dev))
a43f6e0f
DV		 6553 hsw_compute_ips_config(crtc, pipe_config);
6554
877d48d5 6555 if (pipe_config->has_pch_encoder)
a43f6e0f 6556 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6557
cf5a15be 6558 return 0;
79e53945
JB		 6559}
6560
1652d19e
VS		 6561static int skylake_get_display_clock_speed(struct drm_device *dev)
6562{
6563 struct drm_i915_private *dev_priv = to_i915(dev);
6564 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6565 uint32_t cdctl = I915_READ(CDCLK_CTL);
6566 uint32_t linkrate;
6567
414355a7 6568 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6569 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6570
6571 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6572 return 540000;
6573
6574 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6575 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6576
71cd8423
DL		 6577 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6578 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6579 /* vco 8640 */
6580 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6581 case CDCLK_FREQ_450_432:
6582 return 432000;
6583 case CDCLK_FREQ_337_308:
6584 return 308570;
6585 case CDCLK_FREQ_675_617:
6586 return 617140;
6587 default:
6588 WARN(1, "Unknown cd freq selection\n");
6589 }
6590 } else {
6591 /* vco 8100 */
6592 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6593 case CDCLK_FREQ_450_432:
6594 return 450000;
6595 case CDCLK_FREQ_337_308:
6596 return 337500;
6597 case CDCLK_FREQ_675_617:
6598 return 675000;
6599 default:
6600 WARN(1, "Unknown cd freq selection\n");
6601 }
6602 }
6603
6604 /* error case, do as if DPLL0 isn't enabled */
6605 return 24000;
6606}
6607
acd3f3d3
BP		 6608static int broxton_get_display_clock_speed(struct drm_device *dev)
6609{
6610 struct drm_i915_private *dev_priv = to_i915(dev);
6611 uint32_t cdctl = I915_READ(CDCLK_CTL);
6612 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6613 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6614 int cdclk;
6615
6616 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6617 return 19200;
6618
6619 cdclk = 19200 * pll_ratio / 2;
6620
6621 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6622 case BXT_CDCLK_CD2X_DIV_SEL_1:
6623 return cdclk; /* 576MHz or 624MHz */
6624 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6625 return cdclk * 2 / 3; /* 384MHz */
6626 case BXT_CDCLK_CD2X_DIV_SEL_2:
6627 return cdclk / 2; /* 288MHz */
6628 case BXT_CDCLK_CD2X_DIV_SEL_4:
6629 return cdclk / 4; /* 144MHz */
6630 }
6631
6632 /* error case, do as if DE PLL isn't enabled */
6633 return 19200;
6634}
6635
1652d19e
VS		 6636static int broadwell_get_display_clock_speed(struct drm_device *dev)
6637{
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 uint32_t lcpll = I915_READ(LCPLL_CTL);
6640 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6641
6642 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6643 return 800000;
6644 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6645 return 450000;
6646 else if (freq == LCPLL_CLK_FREQ_450)
6647 return 450000;
6648 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6649 return 540000;
6650 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6651 return 337500;
6652 else
6653 return 675000;
6654}
6655
6656static int haswell_get_display_clock_speed(struct drm_device *dev)
6657{
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659 uint32_t lcpll = I915_READ(LCPLL_CTL);
6660 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6661
6662 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6663 return 800000;
6664 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6665 return 450000;
6666 else if (freq == LCPLL_CLK_FREQ_450)
6667 return 450000;
6668 else if (IS_HSW_ULT(dev))
6669 return 337500;
6670 else
6671 return 540000;
79e53945
JB		 6672}
6673
25eb05fc
JB		 6674static int valleyview_get_display_clock_speed(struct drm_device *dev)
6675{
d197b7d3 6676 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6677 u32 val;
6678 int divider;
6679
6bcda4f0
VS		 6680 if (dev_priv->hpll_freq == 0)
6681 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6682
a580516d 6683 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6684 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6685 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6686
6687 divider = val & DISPLAY_FREQUENCY_VALUES;
6688
7d007f40
VS		 6689 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6690 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6691 "cdclk change in progress\n");
6692
6bcda4f0 6693 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6694}
6695
b37a6434
VS		 6696static int ilk_get_display_clock_speed(struct drm_device *dev)
6697{
6698 return 450000;
6699}
6700
e70236a8
JB		 6701static int i945_get_display_clock_speed(struct drm_device *dev)
6702{
6703 return 400000;
6704}
79e53945 6705
e70236a8 6706static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6707{
e907f170 6708 return 333333;
e70236a8 6709}
79e53945 6710
e70236a8
JB		 6711static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6712{
6713 return 200000;
6714}
79e53945 6715
257a7ffc
DV		 6716static int pnv_get_display_clock_speed(struct drm_device *dev)
6717{
6718 u16 gcfgc = 0;
6719
6720 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6721
6722 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6723 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6724 return 266667;
257a7ffc 6725 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6726 return 333333;
257a7ffc 6727 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6728 return 444444;
257a7ffc
DV		 6729 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6730 return 200000;
6731 default:
6732 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6733 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6734 return 133333;
257a7ffc 6735 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6736 return 166667;
257a7ffc
DV		 6737 }
6738}
6739
e70236a8
JB		 6740static int i915gm_get_display_clock_speed(struct drm_device *dev)
6741{
6742 u16 gcfgc = 0;
79e53945 6743
e70236a8
JB		 6744 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6745
6746 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6747 return 133333;
e70236a8
JB		 6748 else {
6749 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6750 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6751 return 333333;
e70236a8
JB		 6752 default:
6753 case GC_DISPLAY_CLOCK_190_200_MHZ:
6754 return 190000;
79e53945 6755 }
e70236a8
JB		 6756 }
6757}
6758
6759static int i865_get_display_clock_speed(struct drm_device *dev)
6760{
e907f170 6761 return 266667;
e70236a8
JB		 6762}
6763
1b1d2716 6764static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6765{
6766 u16 hpllcc = 0;
1b1d2716 6767
65cd2b3f
VS		 6768 /*
6769 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6770 * encoding is different :(
6771 * FIXME is this the right way to detect 852GM/852GMV?
6772 */
6773 if (dev->pdev->revision == 0x1)
6774 return 133333;
6775
1b1d2716
VS		 6776 pci_bus_read_config_word(dev->pdev->bus,
6777 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6778
e70236a8
JB		 6779 /* Assume that the hardware is in the high speed state. This
6780 * should be the default.
6781 */
6782 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6783 case GC_CLOCK_133_200:
1b1d2716 6784 case GC_CLOCK_133_200_2:
e70236a8
JB		 6785 case GC_CLOCK_100_200:
6786 return 200000;
6787 case GC_CLOCK_166_250:
6788 return 250000;
6789 case GC_CLOCK_100_133:
e907f170 6790 return 133333;
1b1d2716
VS		 6791 case GC_CLOCK_133_266:
6792 case GC_CLOCK_133_266_2:
6793 case GC_CLOCK_166_266:
6794 return 266667;
e70236a8 6795 }
79e53945 6796
e70236a8
JB		 6797 /* Shouldn't happen */
6798 return 0;
6799}
79e53945 6800
e70236a8
JB		 6801static int i830_get_display_clock_speed(struct drm_device *dev)
6802{
e907f170 6803 return 133333;
79e53945
JB		 6804}
6805
34edce2f
VS		 6806static unsigned int intel_hpll_vco(struct drm_device *dev)
6807{
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 static const unsigned int blb_vco[8] = {
6810 [0] = 3200000,
6811 [1] = 4000000,
6812 [2] = 5333333,
6813 [3] = 4800000,
6814 [4] = 6400000,
6815 };
6816 static const unsigned int pnv_vco[8] = {
6817 [0] = 3200000,
6818 [1] = 4000000,
6819 [2] = 5333333,
6820 [3] = 4800000,
6821 [4] = 2666667,
6822 };
6823 static const unsigned int cl_vco[8] = {
6824 [0] = 3200000,
6825 [1] = 4000000,
6826 [2] = 5333333,
6827 [3] = 6400000,
6828 [4] = 3333333,
6829 [5] = 3566667,
6830 [6] = 4266667,
6831 };
6832 static const unsigned int elk_vco[8] = {
6833 [0] = 3200000,
6834 [1] = 4000000,
6835 [2] = 5333333,
6836 [3] = 4800000,
6837 };
6838 static const unsigned int ctg_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 6400000,
6843 [4] = 2666667,
6844 [5] = 4266667,
6845 };
6846 const unsigned int *vco_table;
6847 unsigned int vco;
6848 uint8_t tmp = 0;
6849
6850 /* FIXME other chipsets? */
6851 if (IS_GM45(dev))
6852 vco_table = ctg_vco;
6853 else if (IS_G4X(dev))
6854 vco_table = elk_vco;
6855 else if (IS_CRESTLINE(dev))
6856 vco_table = cl_vco;
6857 else if (IS_PINEVIEW(dev))
6858 vco_table = pnv_vco;
6859 else if (IS_G33(dev))
6860 vco_table = blb_vco;
6861 else
6862 return 0;
6863
6864 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6865
6866 vco = vco_table[tmp & 0x7];
6867 if (vco == 0)
6868 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6869 else
6870 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6871
6872 return vco;
6873}
6874
6875static int gm45_get_display_clock_speed(struct drm_device *dev)
6876{
6877 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6878 uint16_t tmp = 0;
6879
6880 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6881
6882 cdclk_sel = (tmp >> 12) & 0x1;
6883
6884 switch (vco) {
6885 case 2666667:
6886 case 4000000:
6887 case 5333333:
6888 return cdclk_sel ? 333333 : 222222;
6889 case 3200000:
6890 return cdclk_sel ? 320000 : 228571;
6891 default:
6892 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6893 return 222222;
6894 }
6895}
6896
6897static int i965gm_get_display_clock_speed(struct drm_device *dev)
6898{
6899 static const uint8_t div_3200[] = { 16, 10, 8 };
6900 static const uint8_t div_4000[] = { 20, 12, 10 };
6901 static const uint8_t div_5333[] = { 24, 16, 14 };
6902 const uint8_t *div_table;
6903 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6904 uint16_t tmp = 0;
6905
6906 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6907
6908 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6909
6910 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6911 goto fail;
6912
6913 switch (vco) {
6914 case 3200000:
6915 div_table = div_3200;
6916 break;
6917 case 4000000:
6918 div_table = div_4000;
6919 break;
6920 case 5333333:
6921 div_table = div_5333;
6922 break;
6923 default:
6924 goto fail;
6925 }
6926
6927 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6928
caf4e252 6929fail:
34edce2f
VS		 6930 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6931 return 200000;
6932}
6933
6934static int g33_get_display_clock_speed(struct drm_device *dev)
6935{
6936 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6937 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6938 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6939 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6940 const uint8_t *div_table;
6941 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6942 uint16_t tmp = 0;
6943
6944 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6945
6946 cdclk_sel = (tmp >> 4) & 0x7;
6947
6948 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6949 goto fail;
6950
6951 switch (vco) {
6952 case 3200000:
6953 div_table = div_3200;
6954 break;
6955 case 4000000:
6956 div_table = div_4000;
6957 break;
6958 case 4800000:
6959 div_table = div_4800;
6960 break;
6961 case 5333333:
6962 div_table = div_5333;
6963 break;
6964 default:
6965 goto fail;
6966 }
6967
6968 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6969
caf4e252 6970fail:
34edce2f
VS		 6971 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6972 return 190476;
6973}
6974
2c07245f 6975static void
a65851af 6976intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6977{
a65851af
VS		 6978 while (*num > DATA_LINK_M_N_MASK ||
6979 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6980 *num >>= 1;
6981 *den >>= 1;
6982 }
6983}
6984
a65851af
VS		 6985static void compute_m_n(unsigned int m, unsigned int n,
6986 uint32_t *ret_m, uint32_t *ret_n)
6987{
6988 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6989 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6990 intel_reduce_m_n_ratio(ret_m, ret_n);
6991}
6992
e69d0bc1
DV		 6993void
6994intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6995 int pixel_clock, int link_clock,
6996 struct intel_link_m_n *m_n)
2c07245f 6997{
e69d0bc1 6998 m_n->tu = 64;
a65851af
VS		 6999
7000 compute_m_n(bits_per_pixel * pixel_clock,
7001 link_clock * nlanes * 8,
7002 &m_n->gmch_m, &m_n->gmch_n);
7003
7004 compute_m_n(pixel_clock, link_clock,
7005 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7006}
7007
a7615030
CW		 7008static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7009{
d330a953
JN		 7010 if (i915.panel_use_ssc >= 0)
7011 return i915.panel_use_ssc != 0;
41aa3448 7012 return dev_priv->vbt.lvds_use_ssc
435793df 7013 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7014}
7015
a93e255f
ACO		 7016static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7017 int num_connectors)
c65d77d8 7018{
a93e255f 7019 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7020 struct drm_i915_private *dev_priv = dev->dev_private;
7021 int refclk;
7022
a93e255f
ACO		 7023 WARN_ON(!crtc_state->base.state);
7024
5ab7b0b7 7025 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7026 refclk = 100000;
a93e255f 7027 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7028 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7029 refclk = dev_priv->vbt.lvds_ssc_freq;
7030 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7031 } else if (!IS_GEN2(dev)) {
7032 refclk = 96000;
7033 } else {
7034 refclk = 48000;
7035 }
7036
7037 return refclk;
7038}
7039
7429e9d4 7040static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7041{
7df00d7a 7042 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7043}
f47709a9 7044
7429e9d4
DV		 7045static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7046{
7047 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7048}
7049
f47709a9 7050static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7051 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7052 intel_clock_t *reduced_clock)
7053{
f47709a9 7054 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7055 u32 fp, fp2 = 0;
7056
7057 if (IS_PINEVIEW(dev)) {
190f68c5 7058 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7059 if (reduced_clock)
7429e9d4 7060 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7061 } else {
190f68c5 7062 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7063 if (reduced_clock)
7429e9d4 7064 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7065 }
7066
190f68c5 7067 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7068
f47709a9 7069 crtc->lowfreq_avail = false;
a93e255f 7070 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7071 reduced_clock) {
190f68c5 7072 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7073 crtc->lowfreq_avail = true;
a7516a05 7074 } else {
190f68c5 7075 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7076 }
7077}
7078
5e69f97f
CML		 7079static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7080 pipe)
89b667f8
JB		 7081{
7082 u32 reg_val;
7083
7084 /*
7085 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7086 * and set it to a reasonable value instead.
7087 */
ab3c759a 7088 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7089 reg_val &= 0xffffff00;
7090 reg_val |= 0x00000030;
ab3c759a 7091 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7092
ab3c759a 7093 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7094 reg_val &= 0x8cffffff;
7095 reg_val = 0x8c000000;
ab3c759a 7096 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7097
ab3c759a 7098 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7099 reg_val &= 0xffffff00;
ab3c759a 7100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7101
ab3c759a 7102 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7103 reg_val &= 0x00ffffff;
7104 reg_val |= 0xb0000000;
ab3c759a 7105 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7106}
7107
b551842d
DV		 7108static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7109 struct intel_link_m_n *m_n)
7110{
7111 struct drm_device *dev = crtc->base.dev;
7112 struct drm_i915_private *dev_priv = dev->dev_private;
7113 int pipe = crtc->pipe;
7114
e3b95f1e
DV		 7115 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7116 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7117 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7118 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7119}
7120
7121static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7122 struct intel_link_m_n *m_n,
7123 struct intel_link_m_n *m2_n2)
b551842d
DV		 7124{
7125 struct drm_device *dev = crtc->base.dev;
7126 struct drm_i915_private *dev_priv = dev->dev_private;
7127 int pipe = crtc->pipe;
6e3c9717 7128 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7129
7130 if (INTEL_INFO(dev)->gen >= 5) {
7131 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7132 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7133 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7134 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7135 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7136 * for gen < 8) and if DRRS is supported (to make sure the
7137 * registers are not unnecessarily accessed).
7138 */
44395bfe 7139 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7140 crtc->config->has_drrs) {
f769cd24
VK		 7141 I915_WRITE(PIPE_DATA_M2(transcoder),
7142 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7143 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7144 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7145 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7146 }
b551842d 7147 } else {
e3b95f1e
DV		 7148 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7149 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7150 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7151 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7152 }
7153}
7154
fe3cd48d 7155void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7156{
fe3cd48d
R		 7157 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7158
7159 if (m_n == M1_N1) {
7160 dp_m_n = &crtc->config->dp_m_n;
7161 dp_m2_n2 = &crtc->config->dp_m2_n2;
7162 } else if (m_n == M2_N2) {
7163
7164 /*
7165 * M2_N2 registers are not supported. Hence m2_n2 divider value
7166 * needs to be programmed into M1_N1.
7167 */
7168 dp_m_n = &crtc->config->dp_m2_n2;
7169 } else {
7170 DRM_ERROR("Unsupported divider value\n");
7171 return;
7172 }
7173
6e3c9717
ACO		 7174 if (crtc->config->has_pch_encoder)
7175 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7176 else
fe3cd48d 7177 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7178}
7179
251ac862
DV		 7180static void vlv_compute_dpll(struct intel_crtc *crtc,
7181 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7182{
7183 u32 dpll, dpll_md;
7184
7185 /*
7186 * Enable DPIO clock input. We should never disable the reference
7187 * clock for pipe B, since VGA hotplug / manual detection depends
7188 * on it.
7189 */
60bfe44f
VS		 7190 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7191 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7192 /* We should never disable this, set it here for state tracking */
7193 if (crtc->pipe == PIPE_B)
7194 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7195 dpll |= DPLL_VCO_ENABLE;
d288f65f 7196 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7197
d288f65f 7198 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7199 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7200 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7201}
7202
d288f65f 7203static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7204 const struct intel_crtc_state *pipe_config)
a0c4da24 7205{
f47709a9 7206 struct drm_device *dev = crtc->base.dev;
a0c4da24 7207 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7208 int pipe = crtc->pipe;
bdd4b6a6 7209 u32 mdiv;
a0c4da24 7210 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7211 u32 coreclk, reg_val;
a0c4da24 7212
a580516d 7213 mutex_lock(&dev_priv->sb_lock);
09153000 7214
d288f65f
VS		 7215 bestn = pipe_config->dpll.n;
7216 bestm1 = pipe_config->dpll.m1;
7217 bestm2 = pipe_config->dpll.m2;
7218 bestp1 = pipe_config->dpll.p1;
7219 bestp2 = pipe_config->dpll.p2;
a0c4da24 7220
89b667f8
JB		 7221 /* See eDP HDMI DPIO driver vbios notes doc */
7222
7223 /* PLL B needs special handling */
bdd4b6a6 7224 if (pipe == PIPE_B)
5e69f97f 7225 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7226
7227 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7228 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7229
7230 /* Disable target IRef on PLL */
ab3c759a 7231 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7232 reg_val &= 0x00ffffff;
ab3c759a 7233 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7234
7235 /* Disable fast lock */
ab3c759a 7236 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7237
7238 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7239 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7240 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7241 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7242 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7243
7244 /*
7245 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7246 * but we don't support that).
7247 * Note: don't use the DAC post divider as it seems unstable.
7248 */
7249 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7250 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7251
a0c4da24 7252 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7253 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7254
89b667f8 7255 /* Set HBR and RBR LPF coefficients */
d288f65f 7256 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7257 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7258 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7260 0x009f0003);
89b667f8 7261 else
ab3c759a 7262 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7263 0x00d0000f);
7264
681a8504 7265 if (pipe_config->has_dp_encoder) {
89b667f8 7266 /* Use SSC source */
bdd4b6a6 7267 if (pipe == PIPE_A)
ab3c759a 7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7269 0x0df40000);
7270 else
ab3c759a 7271 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7272 0x0df70000);
7273 } else { /* HDMI or VGA */
7274 /* Use bend source */
bdd4b6a6 7275 if (pipe == PIPE_A)
ab3c759a 7276 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7277 0x0df70000);
7278 else
ab3c759a 7279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7280 0x0df40000);
7281 }
a0c4da24 7282
ab3c759a 7283 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7284 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7285 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7286 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7287 coreclk |= 0x01000000;
ab3c759a 7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7289
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7291 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7292}
7293
251ac862
DV		 7294static void chv_compute_dpll(struct intel_crtc *crtc,
7295 struct intel_crtc_state *pipe_config)
1ae0d137 7296{
60bfe44f
VS		 7297 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7298 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7299 DPLL_VCO_ENABLE;
7300 if (crtc->pipe != PIPE_A)
d288f65f 7301 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7302
d288f65f
VS		 7303 pipe_config->dpll_hw_state.dpll_md =
7304 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7305}
7306
d288f65f 7307static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7308 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7309{
7310 struct drm_device *dev = crtc->base.dev;
7311 struct drm_i915_private *dev_priv = dev->dev_private;
7312 int pipe = crtc->pipe;
7313 int dpll_reg = DPLL(crtc->pipe);
7314 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7315 u32 loopfilter, tribuf_calcntr;
9d556c99 7316 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7317 u32 dpio_val;
9cbe40c1 7318 int vco;
9d556c99 7319
d288f65f
VS		 7320 bestn = pipe_config->dpll.n;
7321 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7322 bestm1 = pipe_config->dpll.m1;
7323 bestm2 = pipe_config->dpll.m2 >> 22;
7324 bestp1 = pipe_config->dpll.p1;
7325 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7326 vco = pipe_config->dpll.vco;
a945ce7e 7327 dpio_val = 0;
9cbe40c1 7328 loopfilter = 0;
9d556c99
CML		 7329
7330 /*
7331 * Enable Refclk and SSC
7332 */
a11b0703 7333 I915_WRITE(dpll_reg,
d288f65f 7334 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7335
a580516d 7336 mutex_lock(&dev_priv->sb_lock);
9d556c99 7337
9d556c99
CML		 7338 /* p1 and p2 divider */
7339 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7340 5 << DPIO_CHV_S1_DIV_SHIFT |
7341 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7342 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7343 1 << DPIO_CHV_K_DIV_SHIFT);
7344
7345 /* Feedback post-divider - m2 */
7346 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7347
7348 /* Feedback refclk divider - n and m1 */
7349 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7350 DPIO_CHV_M1_DIV_BY_2 |
7351 1 << DPIO_CHV_N_DIV_SHIFT);
7352
7353 /* M2 fraction division */
25a25dfc 7354 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7355
7356 /* M2 fraction division enable */
a945ce7e
VP		 7357 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7358 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7359 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7360 if (bestm2_frac)
7361 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7362 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7363
de3a0fde
VP		 7364 /* Program digital lock detect threshold */
7365 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7366 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7367 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7368 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7369 if (!bestm2_frac)
7370 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7372
9d556c99 7373 /* Loop filter */
9cbe40c1
VP		 7374 if (vco == 5400000) {
7375 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7376 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7377 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7378 tribuf_calcntr = 0x9;
7379 } else if (vco <= 6200000) {
7380 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7381 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7382 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7383 tribuf_calcntr = 0x9;
7384 } else if (vco <= 6480000) {
7385 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7386 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7387 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7388 tribuf_calcntr = 0x8;
7389 } else {
7390 /* Not supported. Apply the same limits as in the max case */
7391 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7392 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7393 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7394 tribuf_calcntr = 0;
7395 }
9d556c99
CML		 7396 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7397
968040b2 7398 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7399 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7400 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7401 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7402
9d556c99
CML		 7403 /* AFC Recal */
7404 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7405 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7406 DPIO_AFC_RECAL);
7407
a580516d 7408 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7409}
7410
d288f65f
VS		 7411/**
7412 * vlv_force_pll_on - forcibly enable just the PLL
7413 * @dev_priv: i915 private structure
7414 * @pipe: pipe PLL to enable
7415 * @dpll: PLL configuration
7416 *
7417 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7418 * in cases where we need the PLL enabled even when @pipe is not going to
7419 * be enabled.
7420 */
7421void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7422 const struct dpll *dpll)
7423{
7424 struct intel_crtc *crtc =
7425 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7426 struct intel_crtc_state pipe_config = {
a93e255f 7427 .base.crtc = &crtc->base,
d288f65f
VS		 7428 .pixel_multiplier = 1,
7429 .dpll = *dpll,
7430 };
7431
7432 if (IS_CHERRYVIEW(dev)) {
251ac862 7433 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7434 chv_prepare_pll(crtc, &pipe_config);
7435 chv_enable_pll(crtc, &pipe_config);
7436 } else {
251ac862 7437 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7438 vlv_prepare_pll(crtc, &pipe_config);
7439 vlv_enable_pll(crtc, &pipe_config);
7440 }
7441}
7442
7443/**
7444 * vlv_force_pll_off - forcibly disable just the PLL
7445 * @dev_priv: i915 private structure
7446 * @pipe: pipe PLL to disable
7447 *
7448 * Disable the PLL for @pipe. To be used in cases where we need
7449 * the PLL enabled even when @pipe is not going to be enabled.
7450 */
7451void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7452{
7453 if (IS_CHERRYVIEW(dev))
7454 chv_disable_pll(to_i915(dev), pipe);
7455 else
7456 vlv_disable_pll(to_i915(dev), pipe);
7457}
7458
251ac862
DV		 7459static void i9xx_compute_dpll(struct intel_crtc *crtc,
7460 struct intel_crtc_state *crtc_state,
7461 intel_clock_t *reduced_clock,
7462 int num_connectors)
eb1cbe48 7463{
f47709a9 7464 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7465 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7466 u32 dpll;
7467 bool is_sdvo;
190f68c5 7468 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7469
190f68c5 7470 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7471
a93e255f
ACO		 7472 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7473 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7474
7475 dpll = DPLL_VGA_MODE_DIS;
7476
a93e255f 7477 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7478 dpll |= DPLLB_MODE_LVDS;
7479 else
7480 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7481
ef1b460d 7482 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7483 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7484 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7485 }
198a037f
DV		 7486
7487 if (is_sdvo)
4a33e48d 7488 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7489
190f68c5 7490 if (crtc_state->has_dp_encoder)
4a33e48d 7491 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7492
7493 /* compute bitmask from p1 value */
7494 if (IS_PINEVIEW(dev))
7495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7496 else {
7497 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7498 if (IS_G4X(dev) && reduced_clock)
7499 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7500 }
7501 switch (clock->p2) {
7502 case 5:
7503 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7504 break;
7505 case 7:
7506 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7507 break;
7508 case 10:
7509 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7510 break;
7511 case 14:
7512 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7513 break;
7514 }
7515 if (INTEL_INFO(dev)->gen >= 4)
7516 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7517
190f68c5 7518 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7519 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7520 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7521 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7522 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7523 else
7524 dpll |= PLL_REF_INPUT_DREFCLK;
7525
7526 dpll |= DPLL_VCO_ENABLE;
190f68c5 7527 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7528
eb1cbe48 7529 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7530 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7531 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7532 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7533 }
7534}
7535
251ac862
DV		 7536static void i8xx_compute_dpll(struct intel_crtc *crtc,
7537 struct intel_crtc_state *crtc_state,
7538 intel_clock_t *reduced_clock,
7539 int num_connectors)
eb1cbe48 7540{
f47709a9 7541 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7542 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7543 u32 dpll;
190f68c5 7544 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7545
190f68c5 7546 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7547
eb1cbe48
DV		 7548 dpll = DPLL_VGA_MODE_DIS;
7549
a93e255f 7550 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7551 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7552 } else {
7553 if (clock->p1 == 2)
7554 dpll |= PLL_P1_DIVIDE_BY_TWO;
7555 else
7556 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7557 if (clock->p2 == 4)
7558 dpll |= PLL_P2_DIVIDE_BY_4;
7559 }
7560
a93e255f 7561 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7562 dpll |= DPLL_DVO_2X_MODE;
7563
a93e255f 7564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7565 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7566 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7567 else
7568 dpll |= PLL_REF_INPUT_DREFCLK;
7569
7570 dpll |= DPLL_VCO_ENABLE;
190f68c5 7571 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7572}
7573
8a654f3b 7574static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7575{
7576 struct drm_device *dev = intel_crtc->base.dev;
7577 struct drm_i915_private *dev_priv = dev->dev_private;
7578 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7579 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7580 struct drm_display_mode *adjusted_mode =
6e3c9717 7581 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7582 uint32_t crtc_vtotal, crtc_vblank_end;
7583 int vsyncshift = 0;
4d8a62ea
DV		 7584
7585 /* We need to be careful not to changed the adjusted mode, for otherwise
7586 * the hw state checker will get angry at the mismatch. */
7587 crtc_vtotal = adjusted_mode->crtc_vtotal;
7588 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7589
609aeaca 7590 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7591 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7592 crtc_vtotal -= 1;
7593 crtc_vblank_end -= 1;
609aeaca 7594
409ee761 7595 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7596 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7597 else
7598 vsyncshift = adjusted_mode->crtc_hsync_start -
7599 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7600 if (vsyncshift < 0)
7601 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7602 }
7603
7604 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7605 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7606
fe2b8f9d 7607 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7608 (adjusted_mode->crtc_hdisplay - 1) |
7609 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7610 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7611 (adjusted_mode->crtc_hblank_start - 1) |
7612 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7613 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7614 (adjusted_mode->crtc_hsync_start - 1) |
7615 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7616
fe2b8f9d 7617 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7618 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7619 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7620 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7621 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7622 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7623 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7624 (adjusted_mode->crtc_vsync_start - 1) |
7625 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7626
b5e508d4
PZ		 7627 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7628 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7629 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7630 * bits. */
7631 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7632 (pipe == PIPE_B || pipe == PIPE_C))
7633 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7634
b0e77b9c
PZ		 7635 /* pipesrc controls the size that is scaled from, which should
7636 * always be the user's requested size.
7637 */
7638 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7639 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7640 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7641}
7642
1bd1bd80 7643static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7644 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7645{
7646 struct drm_device *dev = crtc->base.dev;
7647 struct drm_i915_private *dev_priv = dev->dev_private;
7648 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7649 uint32_t tmp;
7650
7651 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7652 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7653 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7654 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7655 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7656 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7657 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7658 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7659 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7660
7661 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7662 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7663 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7664 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7665 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7666 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7667 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7668 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7669 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7670
7671 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7672 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7673 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7674 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7675 }
7676
7677 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7678 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7679 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7680
2d112de7
ACO		 7681 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7682 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7683}
7684
f6a83288 7685void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7686 struct intel_crtc_state *pipe_config)
babea61d 7687{
2d112de7
ACO		 7688 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7689 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7690 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7691 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7692
2d112de7
ACO		 7693 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7694 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7695 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7696 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7697
2d112de7 7698 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7699 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7700
2d112de7
ACO		 7701 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7702 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7703
7704 mode->hsync = drm_mode_hsync(mode);
7705 mode->vrefresh = drm_mode_vrefresh(mode);
7706 drm_mode_set_name(mode);
babea61d
JB		 7707}
7708
84b046f3
DV		 7709static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7710{
7711 struct drm_device *dev = intel_crtc->base.dev;
7712 struct drm_i915_private *dev_priv = dev->dev_private;
7713 uint32_t pipeconf;
7714
9f11a9e4 7715 pipeconf = 0;
84b046f3 7716
b6b5d049
VS		 7717 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7718 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7719 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7720
6e3c9717 7721 if (intel_crtc->config->double_wide)
cf532bb2 7722 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7723
ff9ce46e
DV		 7724 /* only g4x and later have fancy bpc/dither controls */
7725 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7726 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7727 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7728 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7729 PIPECONF_DITHER_TYPE_SP;
84b046f3 7730
6e3c9717 7731 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7732 case 18:
7733 pipeconf |= PIPECONF_6BPC;
7734 break;
7735 case 24:
7736 pipeconf |= PIPECONF_8BPC;
7737 break;
7738 case 30:
7739 pipeconf |= PIPECONF_10BPC;
7740 break;
7741 default:
7742 /* Case prevented by intel_choose_pipe_bpp_dither. */
7743 BUG();
84b046f3
DV		 7744 }
7745 }
7746
7747 if (HAS_PIPE_CXSR(dev)) {
7748 if (intel_crtc->lowfreq_avail) {
7749 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7750 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7751 } else {
7752 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7753 }
7754 }
7755
6e3c9717 7756 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7757 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7758 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7759 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7760 else
7761 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7762 } else
84b046f3
DV		 7763 pipeconf |= PIPECONF_PROGRESSIVE;
7764
6e3c9717 7765 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7766 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7767
84b046f3
DV		 7768 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7769 POSTING_READ(PIPECONF(intel_crtc->pipe));
7770}
7771
190f68c5
ACO		 7772static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7773 struct intel_crtc_state *crtc_state)
79e53945 7774{
c7653199 7775 struct drm_device *dev = crtc->base.dev;
79e53945 7776 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7777 int refclk, num_connectors = 0;
c329a4ec
DV		 7778 intel_clock_t clock;
7779 bool ok;
7780 bool is_dsi = false;
5eddb70b 7781 struct intel_encoder *encoder;
d4906093 7782 const intel_limit_t *limit;
55bb9992 7783 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7784 struct drm_connector *connector;
55bb9992
ACO		 7785 struct drm_connector_state *connector_state;
7786 int i;
79e53945 7787
dd3cd74a
ACO		 7788 memset(&crtc_state->dpll_hw_state, 0,
7789 sizeof(crtc_state->dpll_hw_state));
7790
da3ced29 7791 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7792 if (connector_state->crtc != &crtc->base)
7793 continue;
7794
7795 encoder = to_intel_encoder(connector_state->best_encoder);
7796
5eddb70b 7797 switch (encoder->type) {
e9fd1c02
JN		 7798 case INTEL_OUTPUT_DSI:
7799 is_dsi = true;
7800 break;
6847d71b
PZ		 7801 default:
7802 break;
79e53945 7803 }
43565a06 7804
c751ce4f 7805 num_connectors++;
79e53945
JB		 7806 }
7807
f2335330 7808 if (is_dsi)
5b18e57c 7809 return 0;
f2335330 7810
190f68c5 7811 if (!crtc_state->clock_set) {
a93e255f 7812 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7813
e9fd1c02
JN		 7814 /*
7815 * Returns a set of divisors for the desired target clock with
7816 * the given refclk, or FALSE. The returned values represent
7817 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7818 * 2) / p1 / p2.
7819 */
a93e255f
ACO		 7820 limit = intel_limit(crtc_state, refclk);
7821 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7822 crtc_state->port_clock,
e9fd1c02 7823 refclk, NULL, &clock);
f2335330 7824 if (!ok) {
e9fd1c02
JN		 7825 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7826 return -EINVAL;
7827 }
79e53945 7828
f2335330 7829 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7830 crtc_state->dpll.n = clock.n;
7831 crtc_state->dpll.m1 = clock.m1;
7832 crtc_state->dpll.m2 = clock.m2;
7833 crtc_state->dpll.p1 = clock.p1;
7834 crtc_state->dpll.p2 = clock.p2;
f47709a9 7835 }
7026d4ac 7836
e9fd1c02 7837 if (IS_GEN2(dev)) {
c329a4ec 7838 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7839 num_connectors);
9d556c99 7840 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7841 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7842 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7843 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7844 } else {
c329a4ec 7845 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7846 num_connectors);
e9fd1c02 7847 }
79e53945 7848
c8f7a0db 7849 return 0;
f564048e
EA		 7850}
7851
2fa2fe9a 7852static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7853 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7854{
7855 struct drm_device *dev = crtc->base.dev;
7856 struct drm_i915_private *dev_priv = dev->dev_private;
7857 uint32_t tmp;
7858
dc9e7dec
VS		 7859 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7860 return;
7861
2fa2fe9a 7862 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7863 if (!(tmp & PFIT_ENABLE))
7864 return;
2fa2fe9a 7865
06922821 7866 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7867 if (INTEL_INFO(dev)->gen < 4) {
7868 if (crtc->pipe != PIPE_B)
7869 return;
2fa2fe9a
DV		 7870 } else {
7871 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7872 return;
7873 }
7874
06922821 7875 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7876 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7877 if (INTEL_INFO(dev)->gen < 5)
7878 pipe_config->gmch_pfit.lvds_border_bits =
7879 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7880}
7881
acbec814 7882static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7883 struct intel_crtc_state *pipe_config)
acbec814
JB		 7884{
7885 struct drm_device *dev = crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7887 int pipe = pipe_config->cpu_transcoder;
7888 intel_clock_t clock;
7889 u32 mdiv;
662c6ecb 7890 int refclk = 100000;
acbec814 7891
f573de5a
SK		 7892 /* In case of MIPI DPLL will not even be used */
7893 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7894 return;
7895
a580516d 7896 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7897 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7898 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7899
7900 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7901 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7902 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7903 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7904 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7905
dccbea3b 7906 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7907}
7908
5724dbd1
DL		 7909static void
7910i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7911 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7912{
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 u32 val, base, offset;
7916 int pipe = crtc->pipe, plane = crtc->plane;
7917 int fourcc, pixel_format;
6761dd31 7918 unsigned int aligned_height;
b113d5ee 7919 struct drm_framebuffer *fb;
1b842c89 7920 struct intel_framebuffer *intel_fb;
1ad292b5 7921
42a7b088
DL		 7922 val = I915_READ(DSPCNTR(plane));
7923 if (!(val & DISPLAY_PLANE_ENABLE))
7924 return;
7925
d9806c9f 7926 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7927 if (!intel_fb) {
1ad292b5
JB		 7928 DRM_DEBUG_KMS("failed to alloc fb\n");
7929 return;
7930 }
7931
1b842c89
DL		 7932 fb = &intel_fb->base;
7933
18c5247e
DV		 7934 if (INTEL_INFO(dev)->gen >= 4) {
7935 if (val & DISPPLANE_TILED) {
49af449b 7936 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7937 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7938 }
7939 }
1ad292b5
JB		 7940
7941 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7942 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7943 fb->pixel_format = fourcc;
7944 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7945
7946 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7947 if (plane_config->tiling)
1ad292b5
JB		 7948 offset = I915_READ(DSPTILEOFF(plane));
7949 else
7950 offset = I915_READ(DSPLINOFF(plane));
7951 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7952 } else {
7953 base = I915_READ(DSPADDR(plane));
7954 }
7955 plane_config->base = base;
7956
7957 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7958 fb->width = ((val >> 16) & 0xfff) + 1;
7959 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7960
7961 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7962 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7963
b113d5ee 7964 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7965 fb->pixel_format,
7966 fb->modifier[0]);
1ad292b5 7967
f37b5c2b 7968 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7969
2844a921
DL		 7970 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7971 pipe_name(pipe), plane, fb->width, fb->height,
7972 fb->bits_per_pixel, base, fb->pitches[0],
7973 plane_config->size);
1ad292b5 7974
2d14030b 7975 plane_config->fb = intel_fb;
1ad292b5
JB		 7976}
7977
70b23a98 7978static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7979 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7980{
7981 struct drm_device *dev = crtc->base.dev;
7982 struct drm_i915_private *dev_priv = dev->dev_private;
7983 int pipe = pipe_config->cpu_transcoder;
7984 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7985 intel_clock_t clock;
0d7b6b11 7986 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 7987 int refclk = 100000;
7988
a580516d 7989 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 7990 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7991 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7992 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7993 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 7994 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 7995 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 7996
7997 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 7998 clock.m2 = (pll_dw0 & 0xff) << 22;
7999 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8000 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8001 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8002 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8003 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8004
dccbea3b 8005 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8006}
8007
0e8ffe1b 8008static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8009 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8010{
8011 struct drm_device *dev = crtc->base.dev;
8012 struct drm_i915_private *dev_priv = dev->dev_private;
8013 uint32_t tmp;
8014
f458ebbc
DV		 8015 if (!intel_display_power_is_enabled(dev_priv,
8016 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8017 return false;
8018
e143a21c 8019 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8020 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8021
0e8ffe1b
DV		 8022 tmp = I915_READ(PIPECONF(crtc->pipe));
8023 if (!(tmp & PIPECONF_ENABLE))
8024 return false;
8025
42571aef
VS		 8026 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8027 switch (tmp & PIPECONF_BPC_MASK) {
8028 case PIPECONF_6BPC:
8029 pipe_config->pipe_bpp = 18;
8030 break;
8031 case PIPECONF_8BPC:
8032 pipe_config->pipe_bpp = 24;
8033 break;
8034 case PIPECONF_10BPC:
8035 pipe_config->pipe_bpp = 30;
8036 break;
8037 default:
8038 break;
8039 }
8040 }
8041
b5a9fa09
DV		 8042 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8043 pipe_config->limited_color_range = true;
8044
282740f7
VS		 8045 if (INTEL_INFO(dev)->gen < 4)
8046 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8047
1bd1bd80
DV		 8048 intel_get_pipe_timings(crtc, pipe_config);
8049
2fa2fe9a
DV		 8050 i9xx_get_pfit_config(crtc, pipe_config);
8051
6c49f241
DV		 8052 if (INTEL_INFO(dev)->gen >= 4) {
8053 tmp = I915_READ(DPLL_MD(crtc->pipe));
8054 pipe_config->pixel_multiplier =
8055 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8056 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8057 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8058 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8059 tmp = I915_READ(DPLL(crtc->pipe));
8060 pipe_config->pixel_multiplier =
8061 ((tmp & SDVO_MULTIPLIER_MASK)
8062 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8063 } else {
8064 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8065 * port and will be fixed up in the encoder->get_config
8066 * function. */
8067 pipe_config->pixel_multiplier = 1;
8068 }
8bcc2795
DV		 8069 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8070 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8071 /*
8072 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8073 * on 830. Filter it out here so that we don't
8074 * report errors due to that.
8075 */
8076 if (IS_I830(dev))
8077 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8078
8bcc2795
DV		 8079 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8080 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8081 } else {
8082 /* Mask out read-only status bits. */
8083 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8084 DPLL_PORTC_READY_MASK |
8085 DPLL_PORTB_READY_MASK);
8bcc2795 8086 }
6c49f241 8087
70b23a98
VS		 8088 if (IS_CHERRYVIEW(dev))
8089 chv_crtc_clock_get(crtc, pipe_config);
8090 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8091 vlv_crtc_clock_get(crtc, pipe_config);
8092 else
8093 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8094
0f64614d
VS		 8095 /*
8096 * Normally the dotclock is filled in by the encoder .get_config()
8097 * but in case the pipe is enabled w/o any ports we need a sane
8098 * default.
8099 */
8100 pipe_config->base.adjusted_mode.crtc_clock =
8101 pipe_config->port_clock / pipe_config->pixel_multiplier;
8102
0e8ffe1b
DV		 8103 return true;
8104}
8105
dde86e2d 8106static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8107{
8108 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8109 struct intel_encoder *encoder;
74cfd7ac 8110 u32 val, final;
13d83a67 8111 bool has_lvds = false;
199e5d79 8112 bool has_cpu_edp = false;
199e5d79 8113 bool has_panel = false;
99eb6a01
KP		 8114 bool has_ck505 = false;
8115 bool can_ssc = false;
13d83a67
JB		 8116
8117 /* We need to take the global config into account */
b2784e15 8118 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8119 switch (encoder->type) {
8120 case INTEL_OUTPUT_LVDS:
8121 has_panel = true;
8122 has_lvds = true;
8123 break;
8124 case INTEL_OUTPUT_EDP:
8125 has_panel = true;
2de6905f 8126 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8127 has_cpu_edp = true;
8128 break;
6847d71b
PZ		 8129 default:
8130 break;
13d83a67
JB		 8131 }
8132 }
8133
99eb6a01 8134 if (HAS_PCH_IBX(dev)) {
41aa3448 8135 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8136 can_ssc = has_ck505;
8137 } else {
8138 has_ck505 = false;
8139 can_ssc = true;
8140 }
8141
2de6905f
ID		 8142 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8143 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8144
8145 /* Ironlake: try to setup display ref clock before DPLL
8146 * enabling. This is only under driver's control after
8147 * PCH B stepping, previous chipset stepping should be
8148 * ignoring this setting.
8149 */
74cfd7ac
CW		 8150 val = I915_READ(PCH_DREF_CONTROL);
8151
8152 /* As we must carefully and slowly disable/enable each source in turn,
8153 * compute the final state we want first and check if we need to
8154 * make any changes at all.
8155 */
8156 final = val;
8157 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8158 if (has_ck505)
8159 final |= DREF_NONSPREAD_CK505_ENABLE;
8160 else
8161 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8162
8163 final &= ~DREF_SSC_SOURCE_MASK;
8164 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8165 final &= ~DREF_SSC1_ENABLE;
8166
8167 if (has_panel) {
8168 final |= DREF_SSC_SOURCE_ENABLE;
8169
8170 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8171 final |= DREF_SSC1_ENABLE;
8172
8173 if (has_cpu_edp) {
8174 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8175 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8176 else
8177 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8178 } else
8179 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8180 } else {
8181 final |= DREF_SSC_SOURCE_DISABLE;
8182 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8183 }
8184
8185 if (final == val)
8186 return;
8187
13d83a67 8188 /* Always enable nonspread source */
74cfd7ac 8189 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8190
99eb6a01 8191 if (has_ck505)
74cfd7ac 8192 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8193 else
74cfd7ac 8194 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8195
199e5d79 8196 if (has_panel) {
74cfd7ac
CW		 8197 val &= ~DREF_SSC_SOURCE_MASK;
8198 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8199
199e5d79 8200 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8201 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8202 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8203 val |= DREF_SSC1_ENABLE;
e77166b5 8204 } else
74cfd7ac 8205 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8206
8207 /* Get SSC going before enabling the outputs */
74cfd7ac 8208 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8209 POSTING_READ(PCH_DREF_CONTROL);
8210 udelay(200);
8211
74cfd7ac 8212 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8213
8214 /* Enable CPU source on CPU attached eDP */
199e5d79 8215 if (has_cpu_edp) {
99eb6a01 8216 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8217 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8218 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8219 } else
74cfd7ac 8220 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8221 } else
74cfd7ac 8222 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8223
74cfd7ac 8224 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8225 POSTING_READ(PCH_DREF_CONTROL);
8226 udelay(200);
8227 } else {
8228 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8229
74cfd7ac 8230 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8231
8232 /* Turn off CPU output */
74cfd7ac 8233 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8234
74cfd7ac 8235 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8236 POSTING_READ(PCH_DREF_CONTROL);
8237 udelay(200);
8238
8239 /* Turn off the SSC source */
74cfd7ac
CW		 8240 val &= ~DREF_SSC_SOURCE_MASK;
8241 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8242
8243 /* Turn off SSC1 */
74cfd7ac 8244 val &= ~DREF_SSC1_ENABLE;
199e5d79 8245
74cfd7ac 8246 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8247 POSTING_READ(PCH_DREF_CONTROL);
8248 udelay(200);
8249 }
74cfd7ac
CW		 8250
8251 BUG_ON(val != final);
13d83a67
JB		 8252}
8253
f31f2d55 8254static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8255{
f31f2d55 8256 uint32_t tmp;
dde86e2d 8257
0ff066a9
PZ		 8258 tmp = I915_READ(SOUTH_CHICKEN2);
8259 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8260 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8261
0ff066a9
PZ		 8262 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8263 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8264 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8265
0ff066a9
PZ		 8266 tmp = I915_READ(SOUTH_CHICKEN2);
8267 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8268 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8269
0ff066a9
PZ		 8270 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8271 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8272 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8273}
8274
8275/* WaMPhyProgramming:hsw */
8276static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8277{
8278 uint32_t tmp;
dde86e2d
PZ		 8279
8280 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8281 tmp &= ~(0xFF << 24);
8282 tmp |= (0x12 << 24);
8283 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8284
dde86e2d
PZ		 8285 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8286 tmp |= (1 << 11);
8287 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8288
8289 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8290 tmp |= (1 << 11);
8291 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8292
dde86e2d
PZ		 8293 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8294 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8295 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8296
8297 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8298 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8299 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8300
0ff066a9
PZ		 8301 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8302 tmp &= ~(7 << 13);
8303 tmp |= (5 << 13);
8304 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8305
0ff066a9
PZ		 8306 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8307 tmp &= ~(7 << 13);
8308 tmp |= (5 << 13);
8309 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8310
8311 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8312 tmp &= ~0xFF;
8313 tmp |= 0x1C;
8314 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8315
8316 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8317 tmp &= ~0xFF;
8318 tmp |= 0x1C;
8319 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8320
8321 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8322 tmp &= ~(0xFF << 16);
8323 tmp |= (0x1C << 16);
8324 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8325
8326 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8327 tmp &= ~(0xFF << 16);
8328 tmp |= (0x1C << 16);
8329 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8330
0ff066a9
PZ		 8331 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8332 tmp |= (1 << 27);
8333 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8334
0ff066a9
PZ		 8335 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8336 tmp |= (1 << 27);
8337 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8338
0ff066a9
PZ		 8339 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8340 tmp &= ~(0xF << 28);
8341 tmp |= (4 << 28);
8342 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8343
0ff066a9
PZ		 8344 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8345 tmp &= ~(0xF << 28);
8346 tmp |= (4 << 28);
8347 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8348}
8349
2fa86a1f
PZ		 8350/* Implements 3 different sequences from BSpec chapter "Display iCLK
8351 * Programming" based on the parameters passed:
8352 * - Sequence to enable CLKOUT_DP
8353 * - Sequence to enable CLKOUT_DP without spread
8354 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8355 */
8356static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8357 bool with_fdi)
f31f2d55
PZ		 8358{
8359 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8360 uint32_t reg, tmp;
8361
8362 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8363 with_spread = true;
c2699524 8364 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8365 with_fdi = false;
f31f2d55 8366
a580516d 8367 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8368
8369 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8370 tmp &= ~SBI_SSCCTL_DISABLE;
8371 tmp |= SBI_SSCCTL_PATHALT;
8372 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8373
8374 udelay(24);
8375
2fa86a1f
PZ		 8376 if (with_spread) {
8377 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8378 tmp &= ~SBI_SSCCTL_PATHALT;
8379 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8380
2fa86a1f
PZ		 8381 if (with_fdi) {
8382 lpt_reset_fdi_mphy(dev_priv);
8383 lpt_program_fdi_mphy(dev_priv);
8384 }
8385 }
dde86e2d 8386
c2699524 8387 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8388 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8389 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8390 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8391
a580516d 8392 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8393}
8394
47701c3b
PZ		 8395/* Sequence to disable CLKOUT_DP */
8396static void lpt_disable_clkout_dp(struct drm_device *dev)
8397{
8398 struct drm_i915_private *dev_priv = dev->dev_private;
8399 uint32_t reg, tmp;
8400
a580516d 8401 mutex_lock(&dev_priv->sb_lock);
47701c3b 8402
c2699524 8403 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8404 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8405 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8406 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8407
8408 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8409 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8410 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8411 tmp |= SBI_SSCCTL_PATHALT;
8412 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8413 udelay(32);
8414 }
8415 tmp |= SBI_SSCCTL_DISABLE;
8416 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8417 }
8418
a580516d 8419 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8420}
8421
bf8fa3d3
PZ		 8422static void lpt_init_pch_refclk(struct drm_device *dev)
8423{
bf8fa3d3
PZ		 8424 struct intel_encoder *encoder;
8425 bool has_vga = false;
8426
b2784e15 8427 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8428 switch (encoder->type) {
8429 case INTEL_OUTPUT_ANALOG:
8430 has_vga = true;
8431 break;
6847d71b
PZ		 8432 default:
8433 break;
bf8fa3d3
PZ		 8434 }
8435 }
8436
47701c3b
PZ		 8437 if (has_vga)
8438 lpt_enable_clkout_dp(dev, true, true);
8439 else
8440 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8441}
8442
dde86e2d
PZ		 8443/*
8444 * Initialize reference clocks when the driver loads
8445 */
8446void intel_init_pch_refclk(struct drm_device *dev)
8447{
8448 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8449 ironlake_init_pch_refclk(dev);
8450 else if (HAS_PCH_LPT(dev))
8451 lpt_init_pch_refclk(dev);
8452}
8453
55bb9992 8454static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8455{
55bb9992 8456 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8457 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8459 struct drm_connector *connector;
55bb9992 8460 struct drm_connector_state *connector_state;
d9d444cb 8461 struct intel_encoder *encoder;
55bb9992 8462 int num_connectors = 0, i;
d9d444cb
JB		 8463 bool is_lvds = false;
8464
da3ced29 8465 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8466 if (connector_state->crtc != crtc_state->base.crtc)
8467 continue;
8468
8469 encoder = to_intel_encoder(connector_state->best_encoder);
8470
d9d444cb
JB		 8471 switch (encoder->type) {
8472 case INTEL_OUTPUT_LVDS:
8473 is_lvds = true;
8474 break;
6847d71b
PZ		 8475 default:
8476 break;
d9d444cb
JB		 8477 }
8478 num_connectors++;
8479 }
8480
8481 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8482 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8483 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8484 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8485 }
8486
8487 return 120000;
8488}
8489
6ff93609 8490static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8491{
c8203565 8492 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8494 int pipe = intel_crtc->pipe;
c8203565
PZ		 8495 uint32_t val;
8496
78114071 8497 val = 0;
c8203565 8498
6e3c9717 8499 switch (intel_crtc->config->pipe_bpp) {
c8203565 8500 case 18:
dfd07d72 8501 val |= PIPECONF_6BPC;
c8203565
PZ		 8502 break;
8503 case 24:
dfd07d72 8504 val |= PIPECONF_8BPC;
c8203565
PZ		 8505 break;
8506 case 30:
dfd07d72 8507 val |= PIPECONF_10BPC;
c8203565
PZ		 8508 break;
8509 case 36:
dfd07d72 8510 val |= PIPECONF_12BPC;
c8203565
PZ		 8511 break;
8512 default:
cc769b62
PZ		 8513 /* Case prevented by intel_choose_pipe_bpp_dither. */
8514 BUG();
c8203565
PZ		 8515 }
8516
6e3c9717 8517 if (intel_crtc->config->dither)
c8203565
PZ		 8518 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8519
6e3c9717 8520 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8521 val |= PIPECONF_INTERLACED_ILK;
8522 else
8523 val |= PIPECONF_PROGRESSIVE;
8524
6e3c9717 8525 if (intel_crtc->config->limited_color_range)
3685a8f3 8526 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8527
c8203565
PZ		 8528 I915_WRITE(PIPECONF(pipe), val);
8529 POSTING_READ(PIPECONF(pipe));
8530}
8531
86d3efce
VS		 8532/*
8533 * Set up the pipe CSC unit.
8534 *
8535 * Currently only full range RGB to limited range RGB conversion
8536 * is supported, but eventually this should handle various
8537 * RGB<->YCbCr scenarios as well.
8538 */
50f3b016 8539static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8540{
8541 struct drm_device *dev = crtc->dev;
8542 struct drm_i915_private *dev_priv = dev->dev_private;
8543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8544 int pipe = intel_crtc->pipe;
8545 uint16_t coeff = 0x7800; /* 1.0 */
8546
8547 /*
8548 * TODO: Check what kind of values actually come out of the pipe
8549 * with these coeff/postoff values and adjust to get the best
8550 * accuracy. Perhaps we even need to take the bpc value into
8551 * consideration.
8552 */
8553
6e3c9717 8554 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8555 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8556
8557 /*
8558 * GY/GU and RY/RU should be the other way around according
8559 * to BSpec, but reality doesn't agree. Just set them up in
8560 * a way that results in the correct picture.
8561 */
8562 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8563 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8564
8565 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8566 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8567
8568 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8569 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8570
8571 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8572 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8573 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8574
8575 if (INTEL_INFO(dev)->gen > 6) {
8576 uint16_t postoff = 0;
8577
6e3c9717 8578 if (intel_crtc->config->limited_color_range)
32cf0cb0 8579 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8580
8581 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8582 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8583 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8584
8585 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8586 } else {
8587 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8588
6e3c9717 8589 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8590 mode |= CSC_BLACK_SCREEN_OFFSET;
8591
8592 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8593 }
8594}
8595
6ff93609 8596static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8597{
756f85cf
PZ		 8598 struct drm_device *dev = crtc->dev;
8599 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8601 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8602 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8603 uint32_t val;
8604
3eff4faa 8605 val = 0;
ee2b0b38 8606
6e3c9717 8607 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8608 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8609
6e3c9717 8610 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8611 val |= PIPECONF_INTERLACED_ILK;
8612 else
8613 val |= PIPECONF_PROGRESSIVE;
8614
702e7a56
PZ		 8615 I915_WRITE(PIPECONF(cpu_transcoder), val);
8616 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8617
8618 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8619 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8620
3cdf122c 8621 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8622 val = 0;
8623
6e3c9717 8624 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8625 case 18:
8626 val |= PIPEMISC_DITHER_6_BPC;
8627 break;
8628 case 24:
8629 val |= PIPEMISC_DITHER_8_BPC;
8630 break;
8631 case 30:
8632 val |= PIPEMISC_DITHER_10_BPC;
8633 break;
8634 case 36:
8635 val |= PIPEMISC_DITHER_12_BPC;
8636 break;
8637 default:
8638 /* Case prevented by pipe_config_set_bpp. */
8639 BUG();
8640 }
8641
6e3c9717 8642 if (intel_crtc->config->dither)
756f85cf
PZ		 8643 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8644
8645 I915_WRITE(PIPEMISC(pipe), val);
8646 }
ee2b0b38
PZ		 8647}
8648
6591c6e4 8649static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8650 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8651 intel_clock_t *clock,
8652 bool *has_reduced_clock,
8653 intel_clock_t *reduced_clock)
8654{
8655 struct drm_device *dev = crtc->dev;
8656 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8657 int refclk;
d4906093 8658 const intel_limit_t *limit;
c329a4ec 8659 bool ret;
79e53945 8660
55bb9992 8661 refclk = ironlake_get_refclk(crtc_state);
79e53945 8662
d4906093
ML		 8663 /*
8664 * Returns a set of divisors for the desired target clock with the given
8665 * refclk, or FALSE. The returned values represent the clock equation:
8666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8667 */
a93e255f
ACO		 8668 limit = intel_limit(crtc_state, refclk);
8669 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8670 crtc_state->port_clock,
ee9300bb 8671 refclk, NULL, clock);
6591c6e4
PZ		 8672 if (!ret)
8673 return false;
cda4b7d3 8674
6591c6e4
PZ		 8675 return true;
8676}
8677
d4b1931c
PZ		 8678int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8679{
8680 /*
8681 * Account for spread spectrum to avoid
8682 * oversubscribing the link. Max center spread
8683 * is 2.5%; use 5% for safety's sake.
8684 */
8685 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8686 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8687}
8688
7429e9d4 8689static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8690{
7429e9d4 8691 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8692}
8693
de13a2e3 8694static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8695 struct intel_crtc_state *crtc_state,
7429e9d4 8696 u32 *fp,
9a7c7890 8697 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8698{
de13a2e3 8699 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8700 struct drm_device *dev = crtc->dev;
8701 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8702 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8703 struct drm_connector *connector;
55bb9992
ACO		 8704 struct drm_connector_state *connector_state;
8705 struct intel_encoder *encoder;
de13a2e3 8706 uint32_t dpll;
55bb9992 8707 int factor, num_connectors = 0, i;
09ede541 8708 bool is_lvds = false, is_sdvo = false;
79e53945 8709
da3ced29 8710 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8711 if (connector_state->crtc != crtc_state->base.crtc)
8712 continue;
8713
8714 encoder = to_intel_encoder(connector_state->best_encoder);
8715
8716 switch (encoder->type) {
79e53945
JB		 8717 case INTEL_OUTPUT_LVDS:
8718 is_lvds = true;
8719 break;
8720 case INTEL_OUTPUT_SDVO:
7d57382e 8721 case INTEL_OUTPUT_HDMI:
79e53945 8722 is_sdvo = true;
79e53945 8723 break;
6847d71b
PZ		 8724 default:
8725 break;
79e53945 8726 }
43565a06 8727
c751ce4f 8728 num_connectors++;
79e53945 8729 }
79e53945 8730
c1858123 8731 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8732 factor = 21;
8733 if (is_lvds) {
8734 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8735 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8736 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8737 factor = 25;
190f68c5 8738 } else if (crtc_state->sdvo_tv_clock)
8febb297 8739 factor = 20;
c1858123 8740
190f68c5 8741 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8742 *fp |= FP_CB_TUNE;
2c07245f 8743
9a7c7890
DV		 8744 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8745 *fp2 |= FP_CB_TUNE;
8746
5eddb70b 8747 dpll = 0;
2c07245f 8748
a07d6787
EA		 8749 if (is_lvds)
8750 dpll |= DPLLB_MODE_LVDS;
8751 else
8752 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8753
190f68c5 8754 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8755 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8756
8757 if (is_sdvo)
4a33e48d 8758 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8759 if (crtc_state->has_dp_encoder)
4a33e48d 8760 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8761
a07d6787 8762 /* compute bitmask from p1 value */
190f68c5 8763 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8764 /* also FPA1 */
190f68c5 8765 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8766
190f68c5 8767 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8768 case 5:
8769 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8770 break;
8771 case 7:
8772 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8773 break;
8774 case 10:
8775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8776 break;
8777 case 14:
8778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8779 break;
79e53945
JB		 8780 }
8781
b4c09f3b 8782 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8783 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8784 else
8785 dpll |= PLL_REF_INPUT_DREFCLK;
8786
959e16d6 8787 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8788}
8789
190f68c5
ACO		 8790static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8791 struct intel_crtc_state *crtc_state)
de13a2e3 8792{
c7653199 8793 struct drm_device *dev = crtc->base.dev;
de13a2e3 8794 intel_clock_t clock, reduced_clock;
cbbab5bd 8795 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8796 bool ok, has_reduced_clock = false;
8b47047b 8797 bool is_lvds = false;
e2b78267 8798 struct intel_shared_dpll *pll;
de13a2e3 8799
dd3cd74a
ACO		 8800 memset(&crtc_state->dpll_hw_state, 0,
8801 sizeof(crtc_state->dpll_hw_state));
8802
409ee761 8803 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8804
5dc5298b
PZ		 8805 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8806 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8807
190f68c5 8808 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8809 &has_reduced_clock, &reduced_clock);
190f68c5 8810 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8811 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8812 return -EINVAL;
79e53945 8813 }
f47709a9 8814 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8815 if (!crtc_state->clock_set) {
8816 crtc_state->dpll.n = clock.n;
8817 crtc_state->dpll.m1 = clock.m1;
8818 crtc_state->dpll.m2 = clock.m2;
8819 crtc_state->dpll.p1 = clock.p1;
8820 crtc_state->dpll.p2 = clock.p2;
f47709a9 8821 }
79e53945 8822
5dc5298b 8823 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8824 if (crtc_state->has_pch_encoder) {
8825 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8826 if (has_reduced_clock)
7429e9d4 8827 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8828
190f68c5 8829 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8830 &fp, &reduced_clock,
8831 has_reduced_clock ? &fp2 : NULL);
8832
190f68c5
ACO		 8833 crtc_state->dpll_hw_state.dpll = dpll;
8834 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8835 if (has_reduced_clock)
190f68c5 8836 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8837 else
190f68c5 8838 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8839
190f68c5 8840 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8841 if (pll == NULL) {
84f44ce7 8842 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8843 pipe_name(crtc->pipe));
4b645f14
JB		 8844 return -EINVAL;
8845 }
3fb37703 8846 }
79e53945 8847
ab585dea 8848 if (is_lvds && has_reduced_clock)
c7653199 8849 crtc->lowfreq_avail = true;
bcd644e0 8850 else
c7653199 8851 crtc->lowfreq_avail = false;
e2b78267 8852
c8f7a0db 8853 return 0;
79e53945
JB		 8854}
8855
eb14cb74
VS		 8856static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8857 struct intel_link_m_n *m_n)
8858{
8859 struct drm_device *dev = crtc->base.dev;
8860 struct drm_i915_private *dev_priv = dev->dev_private;
8861 enum pipe pipe = crtc->pipe;
8862
8863 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8864 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8865 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8866 & ~TU_SIZE_MASK;
8867 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8868 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8869 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8870}
8871
8872static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8873 enum transcoder transcoder,
b95af8be
VK		 8874 struct intel_link_m_n *m_n,
8875 struct intel_link_m_n *m2_n2)
72419203
DV		 8876{
8877 struct drm_device *dev = crtc->base.dev;
8878 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8879 enum pipe pipe = crtc->pipe;
72419203 8880
eb14cb74
VS		 8881 if (INTEL_INFO(dev)->gen >= 5) {
8882 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8883 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8884 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8885 & ~TU_SIZE_MASK;
8886 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8887 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8888 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8889 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8890 * gen < 8) and if DRRS is supported (to make sure the
8891 * registers are not unnecessarily read).
8892 */
8893 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8894 crtc->config->has_drrs) {
b95af8be
VK		 8895 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8896 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8897 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8898 & ~TU_SIZE_MASK;
8899 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8900 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8901 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8902 }
eb14cb74
VS		 8903 } else {
8904 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8905 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8906 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8907 & ~TU_SIZE_MASK;
8908 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8909 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8910 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8911 }
8912}
8913
8914void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8915 struct intel_crtc_state *pipe_config)
eb14cb74 8916{
681a8504 8917 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8918 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8919 else
8920 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8921 &pipe_config->dp_m_n,
8922 &pipe_config->dp_m2_n2);
eb14cb74 8923}
72419203 8924
eb14cb74 8925static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8926 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8927{
8928 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8929 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8930}
8931
bd2e244f 8932static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8933 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8934{
8935 struct drm_device *dev = crtc->base.dev;
8936 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8937 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8938 uint32_t ps_ctrl = 0;
8939 int id = -1;
8940 int i;
bd2e244f 8941
a1b2278e
CK		 8942 /* find scaler attached to this pipe */
8943 for (i = 0; i < crtc->num_scalers; i++) {
8944 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8945 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8946 id = i;
8947 pipe_config->pch_pfit.enabled = true;
8948 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8949 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8950 break;
8951 }
8952 }
bd2e244f 8953
a1b2278e
CK		 8954 scaler_state->scaler_id = id;
8955 if (id >= 0) {
8956 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8957 } else {
8958 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8959 }
8960}
8961
5724dbd1
DL		 8962static void
8963skylake_get_initial_plane_config(struct intel_crtc *crtc,
8964 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8965{
8966 struct drm_device *dev = crtc->base.dev;
8967 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8968 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8969 int pipe = crtc->pipe;
8970 int fourcc, pixel_format;
6761dd31 8971 unsigned int aligned_height;
bc8d7dff 8972 struct drm_framebuffer *fb;
1b842c89 8973 struct intel_framebuffer *intel_fb;
bc8d7dff 8974
d9806c9f 8975 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8976 if (!intel_fb) {
bc8d7dff
DL		 8977 DRM_DEBUG_KMS("failed to alloc fb\n");
8978 return;
8979 }
8980
1b842c89
DL		 8981 fb = &intel_fb->base;
8982
bc8d7dff 8983 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8984 if (!(val & PLANE_CTL_ENABLE))
8985 goto error;
8986
bc8d7dff
DL		 8987 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8988 fourcc = skl_format_to_fourcc(pixel_format,
8989 val & PLANE_CTL_ORDER_RGBX,
8990 val & PLANE_CTL_ALPHA_MASK);
8991 fb->pixel_format = fourcc;
8992 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8993
40f46283
DL		 8994 tiling = val & PLANE_CTL_TILED_MASK;
8995 switch (tiling) {
8996 case PLANE_CTL_TILED_LINEAR:
8997 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8998 break;
8999 case PLANE_CTL_TILED_X:
9000 plane_config->tiling = I915_TILING_X;
9001 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9002 break;
9003 case PLANE_CTL_TILED_Y:
9004 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9005 break;
9006 case PLANE_CTL_TILED_YF:
9007 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9008 break;
9009 default:
9010 MISSING_CASE(tiling);
9011 goto error;
9012 }
9013
bc8d7dff
DL		 9014 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9015 plane_config->base = base;
9016
9017 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9018
9019 val = I915_READ(PLANE_SIZE(pipe, 0));
9020 fb->height = ((val >> 16) & 0xfff) + 1;
9021 fb->width = ((val >> 0) & 0x1fff) + 1;
9022
9023 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9024 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9025 fb->pixel_format);
bc8d7dff
DL		 9026 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9027
9028 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9029 fb->pixel_format,
9030 fb->modifier[0]);
bc8d7dff 9031
f37b5c2b 9032 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9033
9034 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9035 pipe_name(pipe), fb->width, fb->height,
9036 fb->bits_per_pixel, base, fb->pitches[0],
9037 plane_config->size);
9038
2d14030b 9039 plane_config->fb = intel_fb;
bc8d7dff
DL		 9040 return;
9041
9042error:
9043 kfree(fb);
9044}
9045
2fa2fe9a 9046static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9047 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9048{
9049 struct drm_device *dev = crtc->base.dev;
9050 struct drm_i915_private *dev_priv = dev->dev_private;
9051 uint32_t tmp;
9052
9053 tmp = I915_READ(PF_CTL(crtc->pipe));
9054
9055 if (tmp & PF_ENABLE) {
fd4daa9c 9056 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9057 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9058 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9059
9060 /* We currently do not free assignements of panel fitters on
9061 * ivb/hsw (since we don't use the higher upscaling modes which
9062 * differentiates them) so just WARN about this case for now. */
9063 if (IS_GEN7(dev)) {
9064 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9065 PF_PIPE_SEL_IVB(crtc->pipe));
9066 }
2fa2fe9a 9067 }
79e53945
JB		 9068}
9069
5724dbd1
DL		 9070static void
9071ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9072 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9073{
9074 struct drm_device *dev = crtc->base.dev;
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 u32 val, base, offset;
aeee5a49 9077 int pipe = crtc->pipe;
4c6baa59 9078 int fourcc, pixel_format;
6761dd31 9079 unsigned int aligned_height;
b113d5ee 9080 struct drm_framebuffer *fb;
1b842c89 9081 struct intel_framebuffer *intel_fb;
4c6baa59 9082
42a7b088
DL		 9083 val = I915_READ(DSPCNTR(pipe));
9084 if (!(val & DISPLAY_PLANE_ENABLE))
9085 return;
9086
d9806c9f 9087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9088 if (!intel_fb) {
4c6baa59
JB		 9089 DRM_DEBUG_KMS("failed to alloc fb\n");
9090 return;
9091 }
9092
1b842c89
DL		 9093 fb = &intel_fb->base;
9094
18c5247e
DV		 9095 if (INTEL_INFO(dev)->gen >= 4) {
9096 if (val & DISPPLANE_TILED) {
49af449b 9097 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9098 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9099 }
9100 }
4c6baa59
JB		 9101
9102 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9103 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9104 fb->pixel_format = fourcc;
9105 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9106
aeee5a49 9107 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9108 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9109 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9110 } else {
49af449b 9111 if (plane_config->tiling)
aeee5a49 9112 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9113 else
aeee5a49 9114 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9115 }
9116 plane_config->base = base;
9117
9118 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9119 fb->width = ((val >> 16) & 0xfff) + 1;
9120 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9121
9122 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9123 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9124
b113d5ee 9125 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9126 fb->pixel_format,
9127 fb->modifier[0]);
4c6baa59 9128
f37b5c2b 9129 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9130
2844a921
DL		 9131 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9132 pipe_name(pipe), fb->width, fb->height,
9133 fb->bits_per_pixel, base, fb->pitches[0],
9134 plane_config->size);
b113d5ee 9135
2d14030b 9136 plane_config->fb = intel_fb;
4c6baa59
JB		 9137}
9138
0e8ffe1b 9139static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9140 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9141{
9142 struct drm_device *dev = crtc->base.dev;
9143 struct drm_i915_private *dev_priv = dev->dev_private;
9144 uint32_t tmp;
9145
f458ebbc
DV		 9146 if (!intel_display_power_is_enabled(dev_priv,
9147 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9148 return false;
9149
e143a21c 9150 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9151 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9152
0e8ffe1b
DV		 9153 tmp = I915_READ(PIPECONF(crtc->pipe));
9154 if (!(tmp & PIPECONF_ENABLE))
9155 return false;
9156
42571aef
VS		 9157 switch (tmp & PIPECONF_BPC_MASK) {
9158 case PIPECONF_6BPC:
9159 pipe_config->pipe_bpp = 18;
9160 break;
9161 case PIPECONF_8BPC:
9162 pipe_config->pipe_bpp = 24;
9163 break;
9164 case PIPECONF_10BPC:
9165 pipe_config->pipe_bpp = 30;
9166 break;
9167 case PIPECONF_12BPC:
9168 pipe_config->pipe_bpp = 36;
9169 break;
9170 default:
9171 break;
9172 }
9173
b5a9fa09
DV		 9174 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9175 pipe_config->limited_color_range = true;
9176
ab9412ba 9177 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9178 struct intel_shared_dpll *pll;
9179
88adfff1
DV		 9180 pipe_config->has_pch_encoder = true;
9181
627eb5a3
DV		 9182 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9183 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9184 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9185
9186 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9187
c0d43d62 9188 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9189 pipe_config->shared_dpll =
9190 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9191 } else {
9192 tmp = I915_READ(PCH_DPLL_SEL);
9193 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9194 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9195 else
9196 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9197 }
66e985c0
DV		 9198
9199 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9200
9201 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9202 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9203
9204 tmp = pipe_config->dpll_hw_state.dpll;
9205 pipe_config->pixel_multiplier =
9206 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9207 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9208
9209 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9210 } else {
9211 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9212 }
9213
1bd1bd80
DV		 9214 intel_get_pipe_timings(crtc, pipe_config);
9215
2fa2fe9a
DV		 9216 ironlake_get_pfit_config(crtc, pipe_config);
9217
0e8ffe1b
DV		 9218 return true;
9219}
9220
be256dc7
PZ		 9221static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9222{
9223 struct drm_device *dev = dev_priv->dev;
be256dc7 9224 struct intel_crtc *crtc;
be256dc7 9225
d3fcc808 9226 for_each_intel_crtc(dev, crtc)
e2c719b7 9227 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9228 pipe_name(crtc->pipe));
9229
e2c719b7
RC		 9230 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9231 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9232 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9233 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9234 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9235 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9236 "CPU PWM1 enabled\n");
c5107b87 9237 if (IS_HASWELL(dev))
e2c719b7 9238 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9239 "CPU PWM2 enabled\n");
e2c719b7 9240 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9241 "PCH PWM1 enabled\n");
e2c719b7 9242 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9243 "Utility pin enabled\n");
e2c719b7 9244 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9245
9926ada1
PZ		 9246 /*
9247 * In theory we can still leave IRQs enabled, as long as only the HPD
9248 * interrupts remain enabled. We used to check for that, but since it's
9249 * gen-specific and since we only disable LCPLL after we fully disable
9250 * the interrupts, the check below should be enough.
9251 */
e2c719b7 9252 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9253}
9254
9ccd5aeb
PZ		 9255static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9256{
9257 struct drm_device *dev = dev_priv->dev;
9258
9259 if (IS_HASWELL(dev))
9260 return I915_READ(D_COMP_HSW);
9261 else
9262 return I915_READ(D_COMP_BDW);
9263}
9264
3c4c9b81
PZ		 9265static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9266{
9267 struct drm_device *dev = dev_priv->dev;
9268
9269 if (IS_HASWELL(dev)) {
9270 mutex_lock(&dev_priv->rps.hw_lock);
9271 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9272 val))
f475dadf 9273 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9274 mutex_unlock(&dev_priv->rps.hw_lock);
9275 } else {
9ccd5aeb
PZ		 9276 I915_WRITE(D_COMP_BDW, val);
9277 POSTING_READ(D_COMP_BDW);
3c4c9b81 9278 }
be256dc7
PZ		 9279}
9280
9281/*
9282 * This function implements pieces of two sequences from BSpec:
9283 * - Sequence for display software to disable LCPLL
9284 * - Sequence for display software to allow package C8+
9285 * The steps implemented here are just the steps that actually touch the LCPLL
9286 * register. Callers should take care of disabling all the display engine
9287 * functions, doing the mode unset, fixing interrupts, etc.
9288 */
6ff58d53
PZ		 9289static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9290 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9291{
9292 uint32_t val;
9293
9294 assert_can_disable_lcpll(dev_priv);
9295
9296 val = I915_READ(LCPLL_CTL);
9297
9298 if (switch_to_fclk) {
9299 val |= LCPLL_CD_SOURCE_FCLK;
9300 I915_WRITE(LCPLL_CTL, val);
9301
9302 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9303 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9304 DRM_ERROR("Switching to FCLK failed\n");
9305
9306 val = I915_READ(LCPLL_CTL);
9307 }
9308
9309 val |= LCPLL_PLL_DISABLE;
9310 I915_WRITE(LCPLL_CTL, val);
9311 POSTING_READ(LCPLL_CTL);
9312
9313 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9314 DRM_ERROR("LCPLL still locked\n");
9315
9ccd5aeb 9316 val = hsw_read_dcomp(dev_priv);
be256dc7 9317 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9318 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9319 ndelay(100);
9320
9ccd5aeb
PZ		 9321 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9322 1))
be256dc7
PZ		 9323 DRM_ERROR("D_COMP RCOMP still in progress\n");
9324
9325 if (allow_power_down) {
9326 val = I915_READ(LCPLL_CTL);
9327 val |= LCPLL_POWER_DOWN_ALLOW;
9328 I915_WRITE(LCPLL_CTL, val);
9329 POSTING_READ(LCPLL_CTL);
9330 }
9331}
9332
9333/*
9334 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9335 * source.
9336 */
6ff58d53 9337static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9338{
9339 uint32_t val;
9340
9341 val = I915_READ(LCPLL_CTL);
9342
9343 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9344 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9345 return;
9346
a8a8bd54
PZ		 9347 /*
9348 * Make sure we're not on PC8 state before disabling PC8, otherwise
9349 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9350 */
59bad947 9351 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9352
be256dc7
PZ		 9353 if (val & LCPLL_POWER_DOWN_ALLOW) {
9354 val &= ~LCPLL_POWER_DOWN_ALLOW;
9355 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9356 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9357 }
9358
9ccd5aeb 9359 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9360 val |= D_COMP_COMP_FORCE;
9361 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9362 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9363
9364 val = I915_READ(LCPLL_CTL);
9365 val &= ~LCPLL_PLL_DISABLE;
9366 I915_WRITE(LCPLL_CTL, val);
9367
9368 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9369 DRM_ERROR("LCPLL not locked yet\n");
9370
9371 if (val & LCPLL_CD_SOURCE_FCLK) {
9372 val = I915_READ(LCPLL_CTL);
9373 val &= ~LCPLL_CD_SOURCE_FCLK;
9374 I915_WRITE(LCPLL_CTL, val);
9375
9376 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9377 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9378 DRM_ERROR("Switching back to LCPLL failed\n");
9379 }
215733fa 9380
59bad947 9381 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9382 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9383}
9384
765dab67
PZ		 9385/*
9386 * Package states C8 and deeper are really deep PC states that can only be
9387 * reached when all the devices on the system allow it, so even if the graphics
9388 * device allows PC8+, it doesn't mean the system will actually get to these
9389 * states. Our driver only allows PC8+ when going into runtime PM.
9390 *
9391 * The requirements for PC8+ are that all the outputs are disabled, the power
9392 * well is disabled and most interrupts are disabled, and these are also
9393 * requirements for runtime PM. When these conditions are met, we manually do
9394 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9395 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9396 * hang the machine.
9397 *
9398 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9399 * the state of some registers, so when we come back from PC8+ we need to
9400 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9401 * need to take care of the registers kept by RC6. Notice that this happens even
9402 * if we don't put the device in PCI D3 state (which is what currently happens
9403 * because of the runtime PM support).
9404 *
9405 * For more, read "Display Sequences for Package C8" on the hardware
9406 * documentation.
9407 */
a14cb6fc 9408void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9409{
c67a470b
PZ		 9410 struct drm_device *dev = dev_priv->dev;
9411 uint32_t val;
9412
c67a470b
PZ		 9413 DRM_DEBUG_KMS("Enabling package C8+\n");
9414
c2699524 9415 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9416 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9417 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9418 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9419 }
9420
9421 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9422 hsw_disable_lcpll(dev_priv, true, true);
9423}
9424
a14cb6fc 9425void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9426{
9427 struct drm_device *dev = dev_priv->dev;
9428 uint32_t val;
9429
c67a470b
PZ		 9430 DRM_DEBUG_KMS("Disabling package C8+\n");
9431
9432 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9433 lpt_init_pch_refclk(dev);
9434
c2699524 9435 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9436 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9437 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9438 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9439 }
9440
9441 intel_prepare_ddi(dev);
c67a470b
PZ		 9442}
9443
27c329ed 9444static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9445{
a821fc46 9446 struct drm_device *dev = old_state->dev;
27c329ed 9447 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9448
27c329ed 9449 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9450}
9451
b432e5cf 9452/* compute the max rate for new configuration */
27c329ed 9453static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9454{
b432e5cf 9455 struct intel_crtc *intel_crtc;
27c329ed 9456 struct intel_crtc_state *crtc_state;
b432e5cf 9457 int max_pixel_rate = 0;
b432e5cf 9458
27c329ed
ML		 9459 for_each_intel_crtc(state->dev, intel_crtc) {
9460 int pixel_rate;
9461
9462 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9463 if (IS_ERR(crtc_state))
9464 return PTR_ERR(crtc_state);
9465
9466 if (!crtc_state->base.enable)
b432e5cf
VS		 9467 continue;
9468
27c329ed 9469 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9470
9471 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9472 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9473 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9474
9475 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9476 }
9477
9478 return max_pixel_rate;
9479}
9480
9481static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9482{
9483 struct drm_i915_private *dev_priv = dev->dev_private;
9484 uint32_t val, data;
9485 int ret;
9486
9487 if (WARN((I915_READ(LCPLL_CTL) &
9488 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9489 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9490 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9491 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9492 "trying to change cdclk frequency with cdclk not enabled\n"))
9493 return;
9494
9495 mutex_lock(&dev_priv->rps.hw_lock);
9496 ret = sandybridge_pcode_write(dev_priv,
9497 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9498 mutex_unlock(&dev_priv->rps.hw_lock);
9499 if (ret) {
9500 DRM_ERROR("failed to inform pcode about cdclk change\n");
9501 return;
9502 }
9503
9504 val = I915_READ(LCPLL_CTL);
9505 val |= LCPLL_CD_SOURCE_FCLK;
9506 I915_WRITE(LCPLL_CTL, val);
9507
9508 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9509 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9510 DRM_ERROR("Switching to FCLK failed\n");
9511
9512 val = I915_READ(LCPLL_CTL);
9513 val &= ~LCPLL_CLK_FREQ_MASK;
9514
9515 switch (cdclk) {
9516 case 450000:
9517 val |= LCPLL_CLK_FREQ_450;
9518 data = 0;
9519 break;
9520 case 540000:
9521 val |= LCPLL_CLK_FREQ_54O_BDW;
9522 data = 1;
9523 break;
9524 case 337500:
9525 val |= LCPLL_CLK_FREQ_337_5_BDW;
9526 data = 2;
9527 break;
9528 case 675000:
9529 val |= LCPLL_CLK_FREQ_675_BDW;
9530 data = 3;
9531 break;
9532 default:
9533 WARN(1, "invalid cdclk frequency\n");
9534 return;
9535 }
9536
9537 I915_WRITE(LCPLL_CTL, val);
9538
9539 val = I915_READ(LCPLL_CTL);
9540 val &= ~LCPLL_CD_SOURCE_FCLK;
9541 I915_WRITE(LCPLL_CTL, val);
9542
9543 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9544 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9545 DRM_ERROR("Switching back to LCPLL failed\n");
9546
9547 mutex_lock(&dev_priv->rps.hw_lock);
9548 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9549 mutex_unlock(&dev_priv->rps.hw_lock);
9550
9551 intel_update_cdclk(dev);
9552
9553 WARN(cdclk != dev_priv->cdclk_freq,
9554 "cdclk requested %d kHz but got %d kHz\n",
9555 cdclk, dev_priv->cdclk_freq);
9556}
9557
27c329ed 9558static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9559{
27c329ed
ML		 9560 struct drm_i915_private *dev_priv = to_i915(state->dev);
9561 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9562 int cdclk;
9563
9564 /*
9565 * FIXME should also account for plane ratio
9566 * once 64bpp pixel formats are supported.
9567 */
27c329ed 9568 if (max_pixclk > 540000)
b432e5cf 9569 cdclk = 675000;
27c329ed 9570 else if (max_pixclk > 450000)
b432e5cf 9571 cdclk = 540000;
27c329ed 9572 else if (max_pixclk > 337500)
b432e5cf
VS		 9573 cdclk = 450000;
9574 else
9575 cdclk = 337500;
9576
9577 /*
9578 * FIXME move the cdclk caclulation to
9579 * compute_config() so we can fail gracegully.
9580 */
9581 if (cdclk > dev_priv->max_cdclk_freq) {
9582 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9583 cdclk, dev_priv->max_cdclk_freq);
9584 cdclk = dev_priv->max_cdclk_freq;
9585 }
9586
27c329ed 9587 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9588
9589 return 0;
9590}
9591
27c329ed 9592static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9593{
27c329ed
ML		 9594 struct drm_device *dev = old_state->dev;
9595 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9596
27c329ed 9597 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9598}
9599
190f68c5
ACO		 9600static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9601 struct intel_crtc_state *crtc_state)
09b4ddf9 9602{
190f68c5 9603 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9604 return -EINVAL;
716c2e55 9605
c7653199 9606 crtc->lowfreq_avail = false;
644cef34 9607
c8f7a0db 9608 return 0;
79e53945
JB		 9609}
9610
3760b59c
S		 9611static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9612 enum port port,
9613 struct intel_crtc_state *pipe_config)
9614{
9615 switch (port) {
9616 case PORT_A:
9617 pipe_config->ddi_pll_sel = SKL_DPLL0;
9618 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9619 break;
9620 case PORT_B:
9621 pipe_config->ddi_pll_sel = SKL_DPLL1;
9622 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9623 break;
9624 case PORT_C:
9625 pipe_config->ddi_pll_sel = SKL_DPLL2;
9626 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9627 break;
9628 default:
9629 DRM_ERROR("Incorrect port type\n");
9630 }
9631}
9632
96b7dfb7
S		 9633static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9634 enum port port,
5cec258b 9635 struct intel_crtc_state *pipe_config)
96b7dfb7 9636{
3148ade7 9637 u32 temp, dpll_ctl1;
96b7dfb7
S		 9638
9639 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9640 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9641
9642 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9643 case SKL_DPLL0:
9644 /*
9645 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9646 * of the shared DPLL framework and thus needs to be read out
9647 * separately
9648 */
9649 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9650 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9651 break;
96b7dfb7
S		 9652 case SKL_DPLL1:
9653 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9654 break;
9655 case SKL_DPLL2:
9656 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9657 break;
9658 case SKL_DPLL3:
9659 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9660 break;
96b7dfb7
S		 9661 }
9662}
9663
7d2c8175
DL		 9664static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9665 enum port port,
5cec258b 9666 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9667{
9668 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9669
9670 switch (pipe_config->ddi_pll_sel) {
9671 case PORT_CLK_SEL_WRPLL1:
9672 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9673 break;
9674 case PORT_CLK_SEL_WRPLL2:
9675 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9676 break;
9677 }
9678}
9679
26804afd 9680static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9681 struct intel_crtc_state *pipe_config)
26804afd
DV		 9682{
9683 struct drm_device *dev = crtc->base.dev;
9684 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9685 struct intel_shared_dpll *pll;
26804afd
DV		 9686 enum port port;
9687 uint32_t tmp;
9688
9689 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9690
9691 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9692
96b7dfb7
S		 9693 if (IS_SKYLAKE(dev))
9694 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9695 else if (IS_BROXTON(dev))
9696 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9697 else
9698 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9699
d452c5b6
DV		 9700 if (pipe_config->shared_dpll >= 0) {
9701 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9702
9703 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9704 &pipe_config->dpll_hw_state));
9705 }
9706
26804afd
DV		 9707 /*
9708 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9709 * DDI E. So just check whether this pipe is wired to DDI E and whether
9710 * the PCH transcoder is on.
9711 */
ca370455
DL		 9712 if (INTEL_INFO(dev)->gen < 9 &&
9713 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9714 pipe_config->has_pch_encoder = true;
9715
9716 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9717 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9718 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9719
9720 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9721 }
9722}
9723
0e8ffe1b 9724static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9725 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9726{
9727 struct drm_device *dev = crtc->base.dev;
9728 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9729 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9730 uint32_t tmp;
9731
f458ebbc 9732 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9733 POWER_DOMAIN_PIPE(crtc->pipe)))
9734 return false;
9735
e143a21c 9736 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9737 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9738
eccb140b
DV		 9739 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9740 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9741 enum pipe trans_edp_pipe;
9742 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9743 default:
9744 WARN(1, "unknown pipe linked to edp transcoder\n");
9745 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9746 case TRANS_DDI_EDP_INPUT_A_ON:
9747 trans_edp_pipe = PIPE_A;
9748 break;
9749 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9750 trans_edp_pipe = PIPE_B;
9751 break;
9752 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9753 trans_edp_pipe = PIPE_C;
9754 break;
9755 }
9756
9757 if (trans_edp_pipe == crtc->pipe)
9758 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9759 }
9760
f458ebbc 9761 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9762 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9763 return false;
9764
eccb140b 9765 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9766 if (!(tmp & PIPECONF_ENABLE))
9767 return false;
9768
26804afd 9769 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9770
1bd1bd80
DV		 9771 intel_get_pipe_timings(crtc, pipe_config);
9772
a1b2278e
CK		 9773 if (INTEL_INFO(dev)->gen >= 9) {
9774 skl_init_scalers(dev, crtc, pipe_config);
9775 }
9776
2fa2fe9a 9777 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9778
9779 if (INTEL_INFO(dev)->gen >= 9) {
9780 pipe_config->scaler_state.scaler_id = -1;
9781 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9782 }
9783
bd2e244f 9784 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9785 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9786 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9787 else
1c132b44 9788 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9789 }
88adfff1 9790
e59150dc
JB		 9791 if (IS_HASWELL(dev))
9792 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9793 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9794
ebb69c95
CT		 9795 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9796 pipe_config->pixel_multiplier =
9797 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9798 } else {
9799 pipe_config->pixel_multiplier = 1;
9800 }
6c49f241 9801
0e8ffe1b
DV		 9802 return true;
9803}
9804
560b85bb
CW		 9805static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9806{
9807 struct drm_device *dev = crtc->dev;
9808 struct drm_i915_private *dev_priv = dev->dev_private;
9809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9810 uint32_t cntl = 0, size = 0;
560b85bb 9811
dc41c154 9812 if (base) {
3dd512fb
MR		 9813 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9814 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9815 unsigned int stride = roundup_pow_of_two(width) * 4;
9816
9817 switch (stride) {
9818 default:
9819 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9820 width, stride);
9821 stride = 256;
9822 /* fallthrough */
9823 case 256:
9824 case 512:
9825 case 1024:
9826 case 2048:
9827 break;
4b0e333e
CW		 9828 }
9829
dc41c154
VS		 9830 cntl |= CURSOR_ENABLE |
9831 CURSOR_GAMMA_ENABLE |
9832 CURSOR_FORMAT_ARGB |
9833 CURSOR_STRIDE(stride);
9834
9835 size = (height << 12) | width;
4b0e333e 9836 }
560b85bb 9837
dc41c154
VS		 9838 if (intel_crtc->cursor_cntl != 0 &&
9839 (intel_crtc->cursor_base != base ||
9840 intel_crtc->cursor_size != size ||
9841 intel_crtc->cursor_cntl != cntl)) {
9842 /* On these chipsets we can only modify the base/size/stride
9843 * whilst the cursor is disabled.
9844 */
9845 I915_WRITE(_CURACNTR, 0);
4b0e333e 9846 POSTING_READ(_CURACNTR);
dc41c154 9847 intel_crtc->cursor_cntl = 0;
4b0e333e 9848 }
560b85bb 9849
99d1f387 9850 if (intel_crtc->cursor_base != base) {
9db4a9c7 9851 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9852 intel_crtc->cursor_base = base;
9853 }
4726e0b0 9854
dc41c154
VS		 9855 if (intel_crtc->cursor_size != size) {
9856 I915_WRITE(CURSIZE, size);
9857 intel_crtc->cursor_size = size;
4b0e333e 9858 }
560b85bb 9859
4b0e333e 9860 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9861 I915_WRITE(_CURACNTR, cntl);
9862 POSTING_READ(_CURACNTR);
4b0e333e 9863 intel_crtc->cursor_cntl = cntl;
560b85bb 9864 }
560b85bb
CW		 9865}
9866
560b85bb 9867static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9868{
9869 struct drm_device *dev = crtc->dev;
9870 struct drm_i915_private *dev_priv = dev->dev_private;
9871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9872 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9873 uint32_t cntl;
9874
9875 cntl = 0;
9876 if (base) {
9877 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9878 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9879 case 64:
9880 cntl |= CURSOR_MODE_64_ARGB_AX;
9881 break;
9882 case 128:
9883 cntl |= CURSOR_MODE_128_ARGB_AX;
9884 break;
9885 case 256:
9886 cntl |= CURSOR_MODE_256_ARGB_AX;
9887 break;
9888 default:
3dd512fb 9889 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9890 return;
65a21cd6 9891 }
4b0e333e 9892 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9893
9894 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9895 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9896 }
65a21cd6 9897
8e7d688b 9898 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9899 cntl |= CURSOR_ROTATE_180;
9900
4b0e333e
CW		 9901 if (intel_crtc->cursor_cntl != cntl) {
9902 I915_WRITE(CURCNTR(pipe), cntl);
9903 POSTING_READ(CURCNTR(pipe));
9904 intel_crtc->cursor_cntl = cntl;
65a21cd6 9905 }
4b0e333e 9906
65a21cd6 9907 /* and commit changes on next vblank */
5efb3e28
VS		 9908 I915_WRITE(CURBASE(pipe), base);
9909 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9910
9911 intel_crtc->cursor_base = base;
65a21cd6
JB		 9912}
9913
cda4b7d3 9914/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9915static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9916 bool on)
cda4b7d3
CW		 9917{
9918 struct drm_device *dev = crtc->dev;
9919 struct drm_i915_private *dev_priv = dev->dev_private;
9920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9921 int pipe = intel_crtc->pipe;
9b4101be
ML		 9922 struct drm_plane_state *cursor_state = crtc->cursor->state;
9923 int x = cursor_state->crtc_x;
9924 int y = cursor_state->crtc_y;
d6e4db15 9925 u32 base = 0, pos = 0;
cda4b7d3 9926
d6e4db15 9927 if (on)
cda4b7d3 9928 base = intel_crtc->cursor_addr;
cda4b7d3 9929
6e3c9717 9930 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9931 base = 0;
9932
6e3c9717 9933 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9934 base = 0;
9935
9936 if (x < 0) {
9b4101be 9937 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9938 base = 0;
9939
9940 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9941 x = -x;
9942 }
9943 pos |= x << CURSOR_X_SHIFT;
9944
9945 if (y < 0) {
9b4101be 9946 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9947 base = 0;
9948
9949 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9950 y = -y;
9951 }
9952 pos |= y << CURSOR_Y_SHIFT;
9953
4b0e333e 9954 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9955 return;
9956
5efb3e28
VS		 9957 I915_WRITE(CURPOS(pipe), pos);
9958
4398ad45
VS		 9959 /* ILK+ do this automagically */
9960 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9961 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 9962 base += (cursor_state->crtc_h *
9963 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 9964 }
9965
8ac54669 9966 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9967 i845_update_cursor(crtc, base);
9968 else
9969 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9970}
9971
dc41c154
VS		 9972static bool cursor_size_ok(struct drm_device *dev,
9973 uint32_t width, uint32_t height)
9974{
9975 if (width == 0 || height == 0)
9976 return false;
9977
9978 /*
9979 * 845g/865g are special in that they are only limited by
9980 * the width of their cursors, the height is arbitrary up to
9981 * the precision of the register. Everything else requires
9982 * square cursors, limited to a few power-of-two sizes.
9983 */
9984 if (IS_845G(dev) || IS_I865G(dev)) {
9985 if ((width & 63) != 0)
9986 return false;
9987
9988 if (width > (IS_845G(dev) ? 64 : 512))
9989 return false;
9990
9991 if (height > 1023)
9992 return false;
9993 } else {
9994 switch (width | height) {
9995 case 256:
9996 case 128:
9997 if (IS_GEN2(dev))
9998 return false;
9999 case 64:
10000 break;
10001 default:
10002 return false;
10003 }
10004 }
10005
10006 return true;
10007}
10008
79e53945 10009static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10010 u16 *blue, uint32_t start, uint32_t size)
79e53945 10011{
7203425a 10012 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10014
7203425a 10015 for (i = start; i < end; i++) {
79e53945
JB		 10016 intel_crtc->lut_r[i] = red[i] >> 8;
10017 intel_crtc->lut_g[i] = green[i] >> 8;
10018 intel_crtc->lut_b[i] = blue[i] >> 8;
10019 }
10020
10021 intel_crtc_load_lut(crtc);
10022}
10023
79e53945
JB		 10024/* VESA 640x480x72Hz mode to set on the pipe */
10025static struct drm_display_mode load_detect_mode = {
10026 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10027 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10028};
10029
a8bb6818
DV		 10030struct drm_framebuffer *
10031__intel_framebuffer_create(struct drm_device *dev,
10032 struct drm_mode_fb_cmd2 *mode_cmd,
10033 struct drm_i915_gem_object *obj)
d2dff872
CW		 10034{
10035 struct intel_framebuffer *intel_fb;
10036 int ret;
10037
10038 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10039 if (!intel_fb) {
6ccb81f2 10040 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10041 return ERR_PTR(-ENOMEM);
10042 }
10043
10044 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10045 if (ret)
10046 goto err;
d2dff872
CW		 10047
10048 return &intel_fb->base;
dd4916c5 10049err:
6ccb81f2 10050 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10051 kfree(intel_fb);
10052
10053 return ERR_PTR(ret);
d2dff872
CW		 10054}
10055
b5ea642a 10056static struct drm_framebuffer *
a8bb6818
DV		 10057intel_framebuffer_create(struct drm_device *dev,
10058 struct drm_mode_fb_cmd2 *mode_cmd,
10059 struct drm_i915_gem_object *obj)
10060{
10061 struct drm_framebuffer *fb;
10062 int ret;
10063
10064 ret = i915_mutex_lock_interruptible(dev);
10065 if (ret)
10066 return ERR_PTR(ret);
10067 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10068 mutex_unlock(&dev->struct_mutex);
10069
10070 return fb;
10071}
10072
d2dff872
CW		 10073static u32
10074intel_framebuffer_pitch_for_width(int width, int bpp)
10075{
10076 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10077 return ALIGN(pitch, 64);
10078}
10079
10080static u32
10081intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10082{
10083 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10084 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10085}
10086
10087static struct drm_framebuffer *
10088intel_framebuffer_create_for_mode(struct drm_device *dev,
10089 struct drm_display_mode *mode,
10090 int depth, int bpp)
10091{
10092 struct drm_i915_gem_object *obj;
0fed39bd 10093 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10094
10095 obj = i915_gem_alloc_object(dev,
10096 intel_framebuffer_size_for_mode(mode, bpp));
10097 if (obj == NULL)
10098 return ERR_PTR(-ENOMEM);
10099
10100 mode_cmd.width = mode->hdisplay;
10101 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10102 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10103 bpp);
5ca0c34a 10104 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10105
10106 return intel_framebuffer_create(dev, &mode_cmd, obj);
10107}
10108
10109static struct drm_framebuffer *
10110mode_fits_in_fbdev(struct drm_device *dev,
10111 struct drm_display_mode *mode)
10112{
0695726e 10113#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10114 struct drm_i915_private *dev_priv = dev->dev_private;
10115 struct drm_i915_gem_object *obj;
10116 struct drm_framebuffer *fb;
10117
4c0e5528 10118 if (!dev_priv->fbdev)
d2dff872
CW		 10119 return NULL;
10120
4c0e5528 10121 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10122 return NULL;
10123
4c0e5528
DV		 10124 obj = dev_priv->fbdev->fb->obj;
10125 BUG_ON(!obj);
10126
8bcd4553 10127 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10128 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10129 fb->bits_per_pixel))
d2dff872
CW		 10130 return NULL;
10131
01f2c773 10132 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10133 return NULL;
10134
10135 return fb;
4520f53a
DV		 10136#else
10137 return NULL;
10138#endif
d2dff872
CW		 10139}
10140
d3a40d1b
ACO		 10141static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10142 struct drm_crtc *crtc,
10143 struct drm_display_mode *mode,
10144 struct drm_framebuffer *fb,
10145 int x, int y)
10146{
10147 struct drm_plane_state *plane_state;
10148 int hdisplay, vdisplay;
10149 int ret;
10150
10151 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10152 if (IS_ERR(plane_state))
10153 return PTR_ERR(plane_state);
10154
10155 if (mode)
10156 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10157 else
10158 hdisplay = vdisplay = 0;
10159
10160 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10161 if (ret)
10162 return ret;
10163 drm_atomic_set_fb_for_plane(plane_state, fb);
10164 plane_state->crtc_x = 0;
10165 plane_state->crtc_y = 0;
10166 plane_state->crtc_w = hdisplay;
10167 plane_state->crtc_h = vdisplay;
10168 plane_state->src_x = x << 16;
10169 plane_state->src_y = y << 16;
10170 plane_state->src_w = hdisplay << 16;
10171 plane_state->src_h = vdisplay << 16;
10172
10173 return 0;
10174}
10175
d2434ab7 10176bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10177 struct drm_display_mode *mode,
51fd371b
RC		 10178 struct intel_load_detect_pipe *old,
10179 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10180{
10181 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10182 struct intel_encoder *intel_encoder =
10183 intel_attached_encoder(connector);
79e53945 10184 struct drm_crtc *possible_crtc;
4ef69c7a 10185 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10186 struct drm_crtc *crtc = NULL;
10187 struct drm_device *dev = encoder->dev;
94352cf9 10188 struct drm_framebuffer *fb;
51fd371b 10189 struct drm_mode_config *config = &dev->mode_config;
83a57153 10190 struct drm_atomic_state *state = NULL;
944b0c76 10191 struct drm_connector_state *connector_state;
4be07317 10192 struct intel_crtc_state *crtc_state;
51fd371b 10193 int ret, i = -1;
79e53945 10194
d2dff872 10195 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10196 connector->base.id, connector->name,
8e329a03 10197 encoder->base.id, encoder->name);
d2dff872 10198
51fd371b
RC		 10199retry:
10200 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10201 if (ret)
ad3c558f 10202 goto fail;
6e9f798d 10203
79e53945
JB		 10204 /*
10205 * Algorithm gets a little messy:
7a5e4805 10206 *
79e53945
JB		 10207 * - if the connector already has an assigned crtc, use it (but make
10208 * sure it's on first)
7a5e4805 10209 *
79e53945
JB		 10210 * - try to find the first unused crtc that can drive this connector,
10211 * and use that if we find one
79e53945
JB		 10212 */
10213
10214 /* See if we already have a CRTC for this connector */
10215 if (encoder->crtc) {
10216 crtc = encoder->crtc;
8261b191 10217
51fd371b 10218 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10219 if (ret)
ad3c558f 10220 goto fail;
4d02e2de 10221 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10222 if (ret)
ad3c558f 10223 goto fail;
7b24056b 10224
24218aac 10225 old->dpms_mode = connector->dpms;
8261b191
CW		 10226 old->load_detect_temp = false;
10227
10228 /* Make sure the crtc and connector are running */
24218aac
DV		 10229 if (connector->dpms != DRM_MODE_DPMS_ON)
10230 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10231
7173188d 10232 return true;
79e53945
JB		 10233 }
10234
10235 /* Find an unused one (if possible) */
70e1e0ec 10236 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10237 i++;
10238 if (!(encoder->possible_crtcs & (1 << i)))
10239 continue;
83d65738 10240 if (possible_crtc->state->enable)
a459249c 10241 continue;
a459249c
VS		 10242
10243 crtc = possible_crtc;
10244 break;
79e53945
JB		 10245 }
10246
10247 /*
10248 * If we didn't find an unused CRTC, don't use any.
10249 */
10250 if (!crtc) {
7173188d 10251 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10252 goto fail;
79e53945
JB		 10253 }
10254
51fd371b
RC		 10255 ret = drm_modeset_lock(&crtc->mutex, ctx);
10256 if (ret)
ad3c558f 10257 goto fail;
4d02e2de
DV		 10258 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10259 if (ret)
ad3c558f 10260 goto fail;
79e53945
JB		 10261
10262 intel_crtc = to_intel_crtc(crtc);
24218aac 10263 old->dpms_mode = connector->dpms;
8261b191 10264 old->load_detect_temp = true;
d2dff872 10265 old->release_fb = NULL;
79e53945 10266
83a57153
ACO		 10267 state = drm_atomic_state_alloc(dev);
10268 if (!state)
10269 return false;
10270
10271 state->acquire_ctx = ctx;
10272
944b0c76
ACO		 10273 connector_state = drm_atomic_get_connector_state(state, connector);
10274 if (IS_ERR(connector_state)) {
10275 ret = PTR_ERR(connector_state);
10276 goto fail;
10277 }
10278
10279 connector_state->crtc = crtc;
10280 connector_state->best_encoder = &intel_encoder->base;
10281
4be07317
ACO		 10282 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10283 if (IS_ERR(crtc_state)) {
10284 ret = PTR_ERR(crtc_state);
10285 goto fail;
10286 }
10287
49d6fa21 10288 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10289
6492711d
CW		 10290 if (!mode)
10291 mode = &load_detect_mode;
79e53945 10292
d2dff872
CW		 10293 /* We need a framebuffer large enough to accommodate all accesses
10294 * that the plane may generate whilst we perform load detection.
10295 * We can not rely on the fbcon either being present (we get called
10296 * during its initialisation to detect all boot displays, or it may
10297 * not even exist) or that it is large enough to satisfy the
10298 * requested mode.
10299 */
94352cf9
DV		 10300 fb = mode_fits_in_fbdev(dev, mode);
10301 if (fb == NULL) {
d2dff872 10302 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10303 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10304 old->release_fb = fb;
d2dff872
CW		 10305 } else
10306 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10307 if (IS_ERR(fb)) {
d2dff872 10308 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10309 goto fail;
79e53945 10310 }
79e53945 10311
d3a40d1b
ACO		 10312 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10313 if (ret)
10314 goto fail;
10315
8c7b5ccb
ACO		 10316 drm_mode_copy(&crtc_state->base.mode, mode);
10317
74c090b1 10318 if (drm_atomic_commit(state)) {
6492711d 10319 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10320 if (old->release_fb)
10321 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10322 goto fail;
79e53945 10323 }
9128b040 10324 crtc->primary->crtc = crtc;
7173188d 10325
79e53945 10326 /* let the connector get through one full cycle before testing */
9d0498a2 10327 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10328 return true;
412b61d8 10329
ad3c558f 10330fail:
e5d958ef
ACO		 10331 drm_atomic_state_free(state);
10332 state = NULL;
83a57153 10333
51fd371b
RC		 10334 if (ret == -EDEADLK) {
10335 drm_modeset_backoff(ctx);
10336 goto retry;
10337 }
10338
412b61d8 10339 return false;
79e53945
JB		 10340}
10341
d2434ab7 10342void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10343 struct intel_load_detect_pipe *old,
10344 struct drm_modeset_acquire_ctx *ctx)
79e53945 10345{
83a57153 10346 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10347 struct intel_encoder *intel_encoder =
10348 intel_attached_encoder(connector);
4ef69c7a 10349 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10350 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10352 struct drm_atomic_state *state;
944b0c76 10353 struct drm_connector_state *connector_state;
4be07317 10354 struct intel_crtc_state *crtc_state;
d3a40d1b 10355 int ret;
79e53945 10356
d2dff872 10357 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10358 connector->base.id, connector->name,
8e329a03 10359 encoder->base.id, encoder->name);
d2dff872 10360
8261b191 10361 if (old->load_detect_temp) {
83a57153 10362 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10363 if (!state)
10364 goto fail;
83a57153
ACO		 10365
10366 state->acquire_ctx = ctx;
10367
944b0c76
ACO		 10368 connector_state = drm_atomic_get_connector_state(state, connector);
10369 if (IS_ERR(connector_state))
10370 goto fail;
10371
4be07317
ACO		 10372 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10373 if (IS_ERR(crtc_state))
10374 goto fail;
10375
944b0c76
ACO		 10376 connector_state->best_encoder = NULL;
10377 connector_state->crtc = NULL;
10378
49d6fa21 10379 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10380
d3a40d1b
ACO		 10381 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10382 0, 0);
10383 if (ret)
10384 goto fail;
10385
74c090b1 10386 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10387 if (ret)
10388 goto fail;
d2dff872 10389
36206361
DV		 10390 if (old->release_fb) {
10391 drm_framebuffer_unregister_private(old->release_fb);
10392 drm_framebuffer_unreference(old->release_fb);
10393 }
d2dff872 10394
0622a53c 10395 return;
79e53945
JB		 10396 }
10397
c751ce4f 10398 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10399 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10400 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10401
10402 return;
10403fail:
10404 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10405 drm_atomic_state_free(state);
79e53945
JB		 10406}
10407
da4a1efa 10408static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10409 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10410{
10411 struct drm_i915_private *dev_priv = dev->dev_private;
10412 u32 dpll = pipe_config->dpll_hw_state.dpll;
10413
10414 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10415 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10416 else if (HAS_PCH_SPLIT(dev))
10417 return 120000;
10418 else if (!IS_GEN2(dev))
10419 return 96000;
10420 else
10421 return 48000;
10422}
10423
79e53945 10424/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10425static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10426 struct intel_crtc_state *pipe_config)
79e53945 10427{
f1f644dc 10428 struct drm_device *dev = crtc->base.dev;
79e53945 10429 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10430 int pipe = pipe_config->cpu_transcoder;
293623f7 10431 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10432 u32 fp;
10433 intel_clock_t clock;
dccbea3b 10434 int port_clock;
da4a1efa 10435 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10436
10437 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10438 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10439 else
293623f7 10440 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10441
10442 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10443 if (IS_PINEVIEW(dev)) {
10444 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10445 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10446 } else {
10447 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10448 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10449 }
10450
a6c45cf0 10451 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10452 if (IS_PINEVIEW(dev))
10453 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10454 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10455 else
10456 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10457 DPLL_FPA01_P1_POST_DIV_SHIFT);
10458
10459 switch (dpll & DPLL_MODE_MASK) {
10460 case DPLLB_MODE_DAC_SERIAL:
10461 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10462 5 : 10;
10463 break;
10464 case DPLLB_MODE_LVDS:
10465 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10466 7 : 14;
10467 break;
10468 default:
28c97730 10469 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10470 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10471 return;
79e53945
JB		 10472 }
10473
ac58c3f0 10474 if (IS_PINEVIEW(dev))
dccbea3b 10475 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10476 else
dccbea3b 10477 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10478 } else {
0fb58223 10479 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10480 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10481
10482 if (is_lvds) {
10483 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10484 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10485
10486 if (lvds & LVDS_CLKB_POWER_UP)
10487 clock.p2 = 7;
10488 else
10489 clock.p2 = 14;
79e53945
JB		 10490 } else {
10491 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10492 clock.p1 = 2;
10493 else {
10494 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10495 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10496 }
10497 if (dpll & PLL_P2_DIVIDE_BY_4)
10498 clock.p2 = 4;
10499 else
10500 clock.p2 = 2;
79e53945 10501 }
da4a1efa 10502
dccbea3b 10503 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10504 }
10505
18442d08
VS		 10506 /*
10507 * This value includes pixel_multiplier. We will use
241bfc38 10508 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10509 * encoder's get_config() function.
10510 */
dccbea3b 10511 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10512}
10513
6878da05
VS		 10514int intel_dotclock_calculate(int link_freq,
10515 const struct intel_link_m_n *m_n)
f1f644dc 10516{
f1f644dc
JB		 10517 /*
10518 * The calculation for the data clock is:
1041a02f 10519 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10520 * But we want to avoid losing precison if possible, so:
1041a02f 10521 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10522 *
10523 * and the link clock is simpler:
1041a02f 10524 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10525 */
10526
6878da05
VS		 10527 if (!m_n->link_n)
10528 return 0;
f1f644dc 10529
6878da05
VS		 10530 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10531}
f1f644dc 10532
18442d08 10533static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10534 struct intel_crtc_state *pipe_config)
6878da05
VS		 10535{
10536 struct drm_device *dev = crtc->base.dev;
79e53945 10537
18442d08
VS		 10538 /* read out port_clock from the DPLL */
10539 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10540
f1f644dc 10541 /*
18442d08 10542 * This value does not include pixel_multiplier.
241bfc38 10543 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10544 * agree once we know their relationship in the encoder's
10545 * get_config() function.
79e53945 10546 */
2d112de7 10547 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10548 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10549 &pipe_config->fdi_m_n);
79e53945
JB		 10550}
10551
10552/** Returns the currently programmed mode of the given pipe. */
10553struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10554 struct drm_crtc *crtc)
10555{
548f245b 10556 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10558 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10559 struct drm_display_mode *mode;
5cec258b 10560 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10561 int htot = I915_READ(HTOTAL(cpu_transcoder));
10562 int hsync = I915_READ(HSYNC(cpu_transcoder));
10563 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10564 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10565 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10566
10567 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10568 if (!mode)
10569 return NULL;
10570
f1f644dc
JB		 10571 /*
10572 * Construct a pipe_config sufficient for getting the clock info
10573 * back out of crtc_clock_get.
10574 *
10575 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10576 * to use a real value here instead.
10577 */
293623f7 10578 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10579 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10580 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10581 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10582 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10583 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10584
773ae034 10585 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10586 mode->hdisplay = (htot & 0xffff) + 1;
10587 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10588 mode->hsync_start = (hsync & 0xffff) + 1;
10589 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10590 mode->vdisplay = (vtot & 0xffff) + 1;
10591 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10592 mode->vsync_start = (vsync & 0xffff) + 1;
10593 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10594
10595 drm_mode_set_name(mode);
79e53945
JB		 10596
10597 return mode;
10598}
10599
f047e395
CW		 10600void intel_mark_busy(struct drm_device *dev)
10601{
c67a470b
PZ		 10602 struct drm_i915_private *dev_priv = dev->dev_private;
10603
f62a0076
CW		 10604 if (dev_priv->mm.busy)
10605 return;
10606
43694d69 10607 intel_runtime_pm_get(dev_priv);
c67a470b 10608 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10609 if (INTEL_INFO(dev)->gen >= 6)
10610 gen6_rps_busy(dev_priv);
f62a0076 10611 dev_priv->mm.busy = true;
f047e395
CW		 10612}
10613
10614void intel_mark_idle(struct drm_device *dev)
652c393a 10615{
c67a470b 10616 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10617
f62a0076
CW		 10618 if (!dev_priv->mm.busy)
10619 return;
10620
10621 dev_priv->mm.busy = false;
10622
3d13ef2e 10623 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10624 gen6_rps_idle(dev->dev_private);
bb4cdd53 10625
43694d69 10626 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10627}
10628
79e53945
JB		 10629static void intel_crtc_destroy(struct drm_crtc *crtc)
10630{
10631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10632 struct drm_device *dev = crtc->dev;
10633 struct intel_unpin_work *work;
67e77c5a 10634
5e2d7afc 10635 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10636 work = intel_crtc->unpin_work;
10637 intel_crtc->unpin_work = NULL;
5e2d7afc 10638 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10639
10640 if (work) {
10641 cancel_work_sync(&work->work);
10642 kfree(work);
10643 }
79e53945
JB		 10644
10645 drm_crtc_cleanup(crtc);
67e77c5a 10646
79e53945
JB		 10647 kfree(intel_crtc);
10648}
10649
6b95a207
KH		 10650static void intel_unpin_work_fn(struct work_struct *__work)
10651{
10652 struct intel_unpin_work *work =
10653 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10654 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10655 struct drm_device *dev = crtc->base.dev;
10656 struct drm_plane *primary = crtc->base.primary;
6b95a207 10657
b4a98e57 10658 mutex_lock(&dev->struct_mutex);
a9ff8714 10659 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10660 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10661
f06cc1b9 10662 if (work->flip_queued_req)
146d84f0 10663 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10664 mutex_unlock(&dev->struct_mutex);
10665
a9ff8714 10666 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10667 drm_framebuffer_unreference(work->old_fb);
f99d7069 10668
a9ff8714
VS		 10669 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10670 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10671
6b95a207
KH		 10672 kfree(work);
10673}
10674
1afe3e9d 10675static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10676 struct drm_crtc *crtc)
6b95a207 10677{
6b95a207
KH		 10678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10679 struct intel_unpin_work *work;
6b95a207
KH		 10680 unsigned long flags;
10681
10682 /* Ignore early vblank irqs */
10683 if (intel_crtc == NULL)
10684 return;
10685
f326038a
DV		 10686 /*
10687 * This is called both by irq handlers and the reset code (to complete
10688 * lost pageflips) so needs the full irqsave spinlocks.
10689 */
6b95a207
KH		 10690 spin_lock_irqsave(&dev->event_lock, flags);
10691 work = intel_crtc->unpin_work;
e7d841ca
CW		 10692
10693 /* Ensure we don't miss a work->pending update ... */
10694 smp_rmb();
10695
10696 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10697 spin_unlock_irqrestore(&dev->event_lock, flags);
10698 return;
10699 }
10700
d6bbafa1 10701 page_flip_completed(intel_crtc);
0af7e4df 10702
6b95a207 10703 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10704}
10705
1afe3e9d
JB		 10706void intel_finish_page_flip(struct drm_device *dev, int pipe)
10707{
fbee40df 10708 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10709 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10710
49b14a5c 10711 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10712}
10713
10714void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10715{
fbee40df 10716 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10717 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10718
49b14a5c 10719 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10720}
10721
75f7f3ec
VS		 10722/* Is 'a' after or equal to 'b'? */
10723static bool g4x_flip_count_after_eq(u32 a, u32 b)
10724{
10725 return !((a - b) & 0x80000000);
10726}
10727
10728static bool page_flip_finished(struct intel_crtc *crtc)
10729{
10730 struct drm_device *dev = crtc->base.dev;
10731 struct drm_i915_private *dev_priv = dev->dev_private;
10732
bdfa7542
VS		 10733 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10734 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10735 return true;
10736
75f7f3ec
VS		 10737 /*
10738 * The relevant registers doen't exist on pre-ctg.
10739 * As the flip done interrupt doesn't trigger for mmio
10740 * flips on gmch platforms, a flip count check isn't
10741 * really needed there. But since ctg has the registers,
10742 * include it in the check anyway.
10743 */
10744 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10745 return true;
10746
10747 /*
10748 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10749 * used the same base address. In that case the mmio flip might
10750 * have completed, but the CS hasn't even executed the flip yet.
10751 *
10752 * A flip count check isn't enough as the CS might have updated
10753 * the base address just after start of vblank, but before we
10754 * managed to process the interrupt. This means we'd complete the
10755 * CS flip too soon.
10756 *
10757 * Combining both checks should get us a good enough result. It may
10758 * still happen that the CS flip has been executed, but has not
10759 * yet actually completed. But in case the base address is the same
10760 * anyway, we don't really care.
10761 */
10762 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10763 crtc->unpin_work->gtt_offset &&
10764 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10765 crtc->unpin_work->flip_count);
10766}
10767
6b95a207
KH		 10768void intel_prepare_page_flip(struct drm_device *dev, int plane)
10769{
fbee40df 10770 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10771 struct intel_crtc *intel_crtc =
10772 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10773 unsigned long flags;
10774
f326038a
DV		 10775
10776 /*
10777 * This is called both by irq handlers and the reset code (to complete
10778 * lost pageflips) so needs the full irqsave spinlocks.
10779 *
10780 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10781 * generate a page-flip completion irq, i.e. every modeset
10782 * is also accompanied by a spurious intel_prepare_page_flip().
10783 */
6b95a207 10784 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10785 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10786 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10787 spin_unlock_irqrestore(&dev->event_lock, flags);
10788}
10789
eba905b2 10790static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10791{
10792 /* Ensure that the work item is consistent when activating it ... */
10793 smp_wmb();
10794 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10795 /* and that it is marked active as soon as the irq could fire. */
10796 smp_wmb();
10797}
10798
8c9f3aaf
JB		 10799static int intel_gen2_queue_flip(struct drm_device *dev,
10800 struct drm_crtc *crtc,
10801 struct drm_framebuffer *fb,
ed8d1975 10802 struct drm_i915_gem_object *obj,
6258fbe2 10803 struct drm_i915_gem_request *req,
ed8d1975 10804 uint32_t flags)
8c9f3aaf 10805{
6258fbe2 10806 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10808 u32 flip_mask;
10809 int ret;
10810
5fb9de1a 10811 ret = intel_ring_begin(req, 6);
8c9f3aaf 10812 if (ret)
4fa62c89 10813 return ret;
8c9f3aaf
JB		 10814
10815 /* Can't queue multiple flips, so wait for the previous
10816 * one to finish before executing the next.
10817 */
10818 if (intel_crtc->plane)
10819 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10820 else
10821 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10822 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10823 intel_ring_emit(ring, MI_NOOP);
10824 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10825 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10826 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10827 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10828 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10829
10830 intel_mark_page_flip_active(intel_crtc);
83d4092b 10831 return 0;
8c9f3aaf
JB		 10832}
10833
10834static int intel_gen3_queue_flip(struct drm_device *dev,
10835 struct drm_crtc *crtc,
10836 struct drm_framebuffer *fb,
ed8d1975 10837 struct drm_i915_gem_object *obj,
6258fbe2 10838 struct drm_i915_gem_request *req,
ed8d1975 10839 uint32_t flags)
8c9f3aaf 10840{
6258fbe2 10841 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10843 u32 flip_mask;
10844 int ret;
10845
5fb9de1a 10846 ret = intel_ring_begin(req, 6);
8c9f3aaf 10847 if (ret)
4fa62c89 10848 return ret;
8c9f3aaf
JB		 10849
10850 if (intel_crtc->plane)
10851 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10852 else
10853 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10854 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10855 intel_ring_emit(ring, MI_NOOP);
10856 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10857 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10858 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10859 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10860 intel_ring_emit(ring, MI_NOOP);
10861
e7d841ca 10862 intel_mark_page_flip_active(intel_crtc);
83d4092b 10863 return 0;
8c9f3aaf
JB		 10864}
10865
10866static int intel_gen4_queue_flip(struct drm_device *dev,
10867 struct drm_crtc *crtc,
10868 struct drm_framebuffer *fb,
ed8d1975 10869 struct drm_i915_gem_object *obj,
6258fbe2 10870 struct drm_i915_gem_request *req,
ed8d1975 10871 uint32_t flags)
8c9f3aaf 10872{
6258fbe2 10873 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10874 struct drm_i915_private *dev_priv = dev->dev_private;
10875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10876 uint32_t pf, pipesrc;
10877 int ret;
10878
5fb9de1a 10879 ret = intel_ring_begin(req, 4);
8c9f3aaf 10880 if (ret)
4fa62c89 10881 return ret;
8c9f3aaf
JB		 10882
10883 /* i965+ uses the linear or tiled offsets from the
10884 * Display Registers (which do not change across a page-flip)
10885 * so we need only reprogram the base address.
10886 */
6d90c952
DV		 10887 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10888 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10889 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10890 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10891 obj->tiling_mode);
8c9f3aaf
JB		 10892
10893 /* XXX Enabling the panel-fitter across page-flip is so far
10894 * untested on non-native modes, so ignore it for now.
10895 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10896 */
10897 pf = 0;
10898 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10899 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10900
10901 intel_mark_page_flip_active(intel_crtc);
83d4092b 10902 return 0;
8c9f3aaf
JB		 10903}
10904
10905static int intel_gen6_queue_flip(struct drm_device *dev,
10906 struct drm_crtc *crtc,
10907 struct drm_framebuffer *fb,
ed8d1975 10908 struct drm_i915_gem_object *obj,
6258fbe2 10909 struct drm_i915_gem_request *req,
ed8d1975 10910 uint32_t flags)
8c9f3aaf 10911{
6258fbe2 10912 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10913 struct drm_i915_private *dev_priv = dev->dev_private;
10914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10915 uint32_t pf, pipesrc;
10916 int ret;
10917
5fb9de1a 10918 ret = intel_ring_begin(req, 4);
8c9f3aaf 10919 if (ret)
4fa62c89 10920 return ret;
8c9f3aaf 10921
6d90c952
DV		 10922 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10923 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10924 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10925 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10926
dc257cf1
DV		 10927 /* Contrary to the suggestions in the documentation,
10928 * "Enable Panel Fitter" does not seem to be required when page
10929 * flipping with a non-native mode, and worse causes a normal
10930 * modeset to fail.
10931 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10932 */
10933 pf = 0;
8c9f3aaf 10934 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10935 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10936
10937 intel_mark_page_flip_active(intel_crtc);
83d4092b 10938 return 0;
8c9f3aaf
JB		 10939}
10940
7c9017e5
JB		 10941static int intel_gen7_queue_flip(struct drm_device *dev,
10942 struct drm_crtc *crtc,
10943 struct drm_framebuffer *fb,
ed8d1975 10944 struct drm_i915_gem_object *obj,
6258fbe2 10945 struct drm_i915_gem_request *req,
ed8d1975 10946 uint32_t flags)
7c9017e5 10947{
6258fbe2 10948 struct intel_engine_cs *ring = req->ring;
7c9017e5 10949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10950 uint32_t plane_bit = 0;
ffe74d75
CW		 10951 int len, ret;
10952
eba905b2 10953 switch (intel_crtc->plane) {
cb05d8de
DV		 10954 case PLANE_A:
10955 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10956 break;
10957 case PLANE_B:
10958 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10959 break;
10960 case PLANE_C:
10961 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10962 break;
10963 default:
10964 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10965 return -ENODEV;
cb05d8de
DV		 10966 }
10967
ffe74d75 10968 len = 4;
f476828a 10969 if (ring->id == RCS) {
ffe74d75 10970 len += 6;
f476828a
DL		 10971 /*
10972 * On Gen 8, SRM is now taking an extra dword to accommodate
10973 * 48bits addresses, and we need a NOOP for the batch size to
10974 * stay even.
10975 */
10976 if (IS_GEN8(dev))
10977 len += 2;
10978 }
ffe74d75 10979
f66fab8e
VS		 10980 /*
10981 * BSpec MI_DISPLAY_FLIP for IVB:
10982 * "The full packet must be contained within the same cache line."
10983 *
10984 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10985 * cacheline, if we ever start emitting more commands before
10986 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10987 * then do the cacheline alignment, and finally emit the
10988 * MI_DISPLAY_FLIP.
10989 */
bba09b12 10990 ret = intel_ring_cacheline_align(req);
f66fab8e 10991 if (ret)
4fa62c89 10992 return ret;
f66fab8e 10993
5fb9de1a 10994 ret = intel_ring_begin(req, len);
7c9017e5 10995 if (ret)
4fa62c89 10996 return ret;
7c9017e5 10997
ffe74d75
CW		 10998 /* Unmask the flip-done completion message. Note that the bspec says that
10999 * we should do this for both the BCS and RCS, and that we must not unmask
11000 * more than one flip event at any time (or ensure that one flip message
11001 * can be sent by waiting for flip-done prior to queueing new flips).
11002 * Experimentation says that BCS works despite DERRMR masking all
11003 * flip-done completion events and that unmasking all planes at once
11004 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11005 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11006 */
11007 if (ring->id == RCS) {
11008 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11009 intel_ring_emit(ring, DERRMR);
11010 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11011 DERRMR_PIPEB_PRI_FLIP_DONE |
11012 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11013 if (IS_GEN8(dev))
f1afe24f 11014 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11015 MI_SRM_LRM_GLOBAL_GTT);
11016 else
f1afe24f 11017 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11018 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11019 intel_ring_emit(ring, DERRMR);
11020 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11021 if (IS_GEN8(dev)) {
11022 intel_ring_emit(ring, 0);
11023 intel_ring_emit(ring, MI_NOOP);
11024 }
ffe74d75
CW		 11025 }
11026
cb05d8de 11027 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11028 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11029 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11030 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11031
11032 intel_mark_page_flip_active(intel_crtc);
83d4092b 11033 return 0;
7c9017e5
JB		 11034}
11035
84c33a64
SG		 11036static bool use_mmio_flip(struct intel_engine_cs *ring,
11037 struct drm_i915_gem_object *obj)
11038{
11039 /*
11040 * This is not being used for older platforms, because
11041 * non-availability of flip done interrupt forces us to use
11042 * CS flips. Older platforms derive flip done using some clever
11043 * tricks involving the flip_pending status bits and vblank irqs.
11044 * So using MMIO flips there would disrupt this mechanism.
11045 */
11046
8e09bf83
CW		 11047 if (ring == NULL)
11048 return true;
11049
84c33a64
SG		 11050 if (INTEL_INFO(ring->dev)->gen < 5)
11051 return false;
11052
11053 if (i915.use_mmio_flip < 0)
11054 return false;
11055 else if (i915.use_mmio_flip > 0)
11056 return true;
14bf993e
OM		 11057 else if (i915.enable_execlists)
11058 return true;
84c33a64 11059 else
b4716185 11060 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11061}
11062
ff944564
DL		 11063static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11064{
11065 struct drm_device *dev = intel_crtc->base.dev;
11066 struct drm_i915_private *dev_priv = dev->dev_private;
11067 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11068 const enum pipe pipe = intel_crtc->pipe;
11069 u32 ctl, stride;
11070
11071 ctl = I915_READ(PLANE_CTL(pipe, 0));
11072 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11073 switch (fb->modifier[0]) {
11074 case DRM_FORMAT_MOD_NONE:
11075 break;
11076 case I915_FORMAT_MOD_X_TILED:
ff944564 11077 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11078 break;
11079 case I915_FORMAT_MOD_Y_TILED:
11080 ctl |= PLANE_CTL_TILED_Y;
11081 break;
11082 case I915_FORMAT_MOD_Yf_TILED:
11083 ctl |= PLANE_CTL_TILED_YF;
11084 break;
11085 default:
11086 MISSING_CASE(fb->modifier[0]);
11087 }
ff944564
DL		 11088
11089 /*
11090 * The stride is either expressed as a multiple of 64 bytes chunks for
11091 * linear buffers or in number of tiles for tiled buffers.
11092 */
2ebef630
TU		 11093 stride = fb->pitches[0] /
11094 intel_fb_stride_alignment(dev, fb->modifier[0],
11095 fb->pixel_format);
ff944564
DL		 11096
11097 /*
11098 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11099 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11100 */
11101 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11102 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11103
11104 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11105 POSTING_READ(PLANE_SURF(pipe, 0));
11106}
11107
11108static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11109{
11110 struct drm_device *dev = intel_crtc->base.dev;
11111 struct drm_i915_private *dev_priv = dev->dev_private;
11112 struct intel_framebuffer *intel_fb =
11113 to_intel_framebuffer(intel_crtc->base.primary->fb);
11114 struct drm_i915_gem_object *obj = intel_fb->obj;
11115 u32 dspcntr;
11116 u32 reg;
11117
84c33a64
SG		 11118 reg = DSPCNTR(intel_crtc->plane);
11119 dspcntr = I915_READ(reg);
11120
c5d97472
DL		 11121 if (obj->tiling_mode != I915_TILING_NONE)
11122 dspcntr |= DISPPLANE_TILED;
11123 else
11124 dspcntr &= ~DISPPLANE_TILED;
11125
84c33a64
SG		 11126 I915_WRITE(reg, dspcntr);
11127
11128 I915_WRITE(DSPSURF(intel_crtc->plane),
11129 intel_crtc->unpin_work->gtt_offset);
11130 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11131
ff944564
DL		 11132}
11133
11134/*
11135 * XXX: This is the temporary way to update the plane registers until we get
11136 * around to using the usual plane update functions for MMIO flips
11137 */
11138static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11139{
11140 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11141
11142 intel_mark_page_flip_active(intel_crtc);
11143
34e0adbb 11144 intel_pipe_update_start(intel_crtc);
ff944564
DL		 11145
11146 if (INTEL_INFO(dev)->gen >= 9)
11147 skl_do_mmio_flip(intel_crtc);
11148 else
11149 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11150 ilk_do_mmio_flip(intel_crtc);
11151
34e0adbb 11152 intel_pipe_update_end(intel_crtc);
84c33a64
SG		 11153}
11154
9362c7c5 11155static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11156{
b2cfe0ab
CW		 11157 struct intel_mmio_flip *mmio_flip =
11158 container_of(work, struct intel_mmio_flip, work);
84c33a64 11159
eed29a5b
DV		 11160 if (mmio_flip->req)
11161 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11162 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11163 false, NULL,
11164 &mmio_flip->i915->rps.mmioflips));
84c33a64 11165
b2cfe0ab
CW		 11166 intel_do_mmio_flip(mmio_flip->crtc);
11167
eed29a5b 11168 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11169 kfree(mmio_flip);
84c33a64
SG		 11170}
11171
11172static int intel_queue_mmio_flip(struct drm_device *dev,
11173 struct drm_crtc *crtc,
11174 struct drm_framebuffer *fb,
11175 struct drm_i915_gem_object *obj,
11176 struct intel_engine_cs *ring,
11177 uint32_t flags)
11178{
b2cfe0ab
CW		 11179 struct intel_mmio_flip *mmio_flip;
11180
11181 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11182 if (mmio_flip == NULL)
11183 return -ENOMEM;
84c33a64 11184
bcafc4e3 11185 mmio_flip->i915 = to_i915(dev);
eed29a5b 11186 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11187 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11188
b2cfe0ab
CW		 11189 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11190 schedule_work(&mmio_flip->work);
84c33a64 11191
84c33a64
SG		 11192 return 0;
11193}
11194
8c9f3aaf
JB		 11195static int intel_default_queue_flip(struct drm_device *dev,
11196 struct drm_crtc *crtc,
11197 struct drm_framebuffer *fb,
ed8d1975 11198 struct drm_i915_gem_object *obj,
6258fbe2 11199 struct drm_i915_gem_request *req,
ed8d1975 11200 uint32_t flags)
8c9f3aaf
JB		 11201{
11202 return -ENODEV;
11203}
11204
d6bbafa1
CW		 11205static bool __intel_pageflip_stall_check(struct drm_device *dev,
11206 struct drm_crtc *crtc)
11207{
11208 struct drm_i915_private *dev_priv = dev->dev_private;
11209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11210 struct intel_unpin_work *work = intel_crtc->unpin_work;
11211 u32 addr;
11212
11213 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11214 return true;
11215
908565c2
CW		 11216 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11217 return false;
11218
d6bbafa1
CW		 11219 if (!work->enable_stall_check)
11220 return false;
11221
11222 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11223 if (work->flip_queued_req &&
11224 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11225 return false;
11226
1e3feefd 11227 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11228 }
11229
1e3feefd 11230 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11231 return false;
11232
11233 /* Potential stall - if we see that the flip has happened,
11234 * assume a missed interrupt. */
11235 if (INTEL_INFO(dev)->gen >= 4)
11236 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11237 else
11238 addr = I915_READ(DSPADDR(intel_crtc->plane));
11239
11240 /* There is a potential issue here with a false positive after a flip
11241 * to the same address. We could address this by checking for a
11242 * non-incrementing frame counter.
11243 */
11244 return addr == work->gtt_offset;
11245}
11246
11247void intel_check_page_flip(struct drm_device *dev, int pipe)
11248{
11249 struct drm_i915_private *dev_priv = dev->dev_private;
11250 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11252 struct intel_unpin_work *work;
f326038a 11253
6c51d46f 11254 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11255
11256 if (crtc == NULL)
11257 return;
11258
f326038a 11259 spin_lock(&dev->event_lock);
6ad790c0
CW		 11260 work = intel_crtc->unpin_work;
11261 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11262 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11263 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11264 page_flip_completed(intel_crtc);
6ad790c0 11265 work = NULL;
d6bbafa1 11266 }
6ad790c0
CW		 11267 if (work != NULL &&
11268 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11269 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11270 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11271}
11272
6b95a207
KH		 11273static int intel_crtc_page_flip(struct drm_crtc *crtc,
11274 struct drm_framebuffer *fb,
ed8d1975
KP		 11275 struct drm_pending_vblank_event *event,
11276 uint32_t page_flip_flags)
6b95a207
KH		 11277{
11278 struct drm_device *dev = crtc->dev;
11279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11280 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11281 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11283 struct drm_plane *primary = crtc->primary;
a071fa00 11284 enum pipe pipe = intel_crtc->pipe;
6b95a207 11285 struct intel_unpin_work *work;
a4872ba6 11286 struct intel_engine_cs *ring;
cf5d8a46 11287 bool mmio_flip;
91af127f 11288 struct drm_i915_gem_request *request = NULL;
52e68630 11289 int ret;
6b95a207 11290
2ff8fde1
MR		 11291 /*
11292 * drm_mode_page_flip_ioctl() should already catch this, but double
11293 * check to be safe. In the future we may enable pageflipping from
11294 * a disabled primary plane.
11295 */
11296 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11297 return -EBUSY;
11298
e6a595d2 11299 /* Can't change pixel format via MI display flips. */
f4510a27 11300 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11301 return -EINVAL;
11302
11303 /*
11304 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11305 * Note that pitch changes could also affect these register.
11306 */
11307 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11308 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11309 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11310 return -EINVAL;
11311
f900db47
CW		 11312 if (i915_terminally_wedged(&dev_priv->gpu_error))
11313 goto out_hang;
11314
b14c5679 11315 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11316 if (work == NULL)
11317 return -ENOMEM;
11318
6b95a207 11319 work->event = event;
b4a98e57 11320 work->crtc = crtc;
ab8d6675 11321 work->old_fb = old_fb;
6b95a207
KH		 11322 INIT_WORK(&work->work, intel_unpin_work_fn);
11323
87b6b101 11324 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11325 if (ret)
11326 goto free_work;
11327
6b95a207 11328 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11329 spin_lock_irq(&dev->event_lock);
6b95a207 11330 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11331 /* Before declaring the flip queue wedged, check if
11332 * the hardware completed the operation behind our backs.
11333 */
11334 if (__intel_pageflip_stall_check(dev, crtc)) {
11335 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11336 page_flip_completed(intel_crtc);
11337 } else {
11338 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11339 spin_unlock_irq(&dev->event_lock);
468f0b44 11340
d6bbafa1
CW		 11341 drm_crtc_vblank_put(crtc);
11342 kfree(work);
11343 return -EBUSY;
11344 }
6b95a207
KH		 11345 }
11346 intel_crtc->unpin_work = work;
5e2d7afc 11347 spin_unlock_irq(&dev->event_lock);
6b95a207 11348
b4a98e57
CW		 11349 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11350 flush_workqueue(dev_priv->wq);
11351
75dfca80 11352 /* Reference the objects for the scheduled work. */
ab8d6675 11353 drm_framebuffer_reference(work->old_fb);
05394f39 11354 drm_gem_object_reference(&obj->base);
6b95a207 11355
f4510a27 11356 crtc->primary->fb = fb;
afd65eb4 11357 update_state_fb(crtc->primary);
1ed1f968 11358
e1f99ce6 11359 work->pending_flip_obj = obj;
e1f99ce6 11360
89ed88ba
CW		 11361 ret = i915_mutex_lock_interruptible(dev);
11362 if (ret)
11363 goto cleanup;
11364
b4a98e57 11365 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11366 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11367
75f7f3ec 11368 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11369 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11370
4fa62c89
VS		 11371 if (IS_VALLEYVIEW(dev)) {
11372 ring = &dev_priv->ring[BCS];
ab8d6675 11373 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11374 /* vlv: DISPLAY_FLIP fails to change tiling */
11375 ring = NULL;
48bf5b2d 11376 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11377 ring = &dev_priv->ring[BCS];
4fa62c89 11378 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11379 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11380 if (ring == NULL || ring->id != RCS)
11381 ring = &dev_priv->ring[BCS];
11382 } else {
11383 ring = &dev_priv->ring[RCS];
11384 }
11385
cf5d8a46
CW		 11386 mmio_flip = use_mmio_flip(ring, obj);
11387
11388 /* When using CS flips, we want to emit semaphores between rings.
11389 * However, when using mmio flips we will create a task to do the
11390 * synchronisation, so all we want here is to pin the framebuffer
11391 * into the display plane and skip any waits.
11392 */
82bc3b2d 11393 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11394 crtc->primary->state,
91af127f 11395 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11396 if (ret)
11397 goto cleanup_pending;
6b95a207 11398
121920fa
TU		 11399 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11400 + intel_crtc->dspaddr_offset;
4fa62c89 11401
cf5d8a46 11402 if (mmio_flip) {
84c33a64
SG		 11403 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11404 page_flip_flags);
d6bbafa1
CW		 11405 if (ret)
11406 goto cleanup_unpin;
11407
f06cc1b9
JH		 11408 i915_gem_request_assign(&work->flip_queued_req,
11409 obj->last_write_req);
d6bbafa1 11410 } else {
6258fbe2
JH		 11411 if (!request) {
11412 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11413 if (ret)
11414 goto cleanup_unpin;
11415 }
11416
11417 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11418 page_flip_flags);
11419 if (ret)
11420 goto cleanup_unpin;
11421
6258fbe2 11422 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11423 }
11424
91af127f 11425 if (request)
75289874 11426 i915_add_request_no_flush(request);
91af127f 11427
1e3feefd 11428 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11429 work->enable_stall_check = true;
4fa62c89 11430
ab8d6675 11431 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11432 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11433 mutex_unlock(&dev->struct_mutex);
a071fa00 11434
4e1e26f1 11435 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11436 intel_frontbuffer_flip_prepare(dev,
11437 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11438
e5510fac
JB		 11439 trace_i915_flip_request(intel_crtc->plane, obj);
11440
6b95a207 11441 return 0;
96b099fd 11442
4fa62c89 11443cleanup_unpin:
82bc3b2d 11444 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11445cleanup_pending:
91af127f
JH		 11446 if (request)
11447 i915_gem_request_cancel(request);
b4a98e57 11448 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11449 mutex_unlock(&dev->struct_mutex);
11450cleanup:
f4510a27 11451 crtc->primary->fb = old_fb;
afd65eb4 11452 update_state_fb(crtc->primary);
89ed88ba
CW		 11453
11454 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11455 drm_framebuffer_unreference(work->old_fb);
96b099fd 11456
5e2d7afc 11457 spin_lock_irq(&dev->event_lock);
96b099fd 11458 intel_crtc->unpin_work = NULL;
5e2d7afc 11459 spin_unlock_irq(&dev->event_lock);
96b099fd 11460
87b6b101 11461 drm_crtc_vblank_put(crtc);
7317c75e 11462free_work:
96b099fd
CW		 11463 kfree(work);
11464
f900db47 11465 if (ret == -EIO) {
02e0efb5
ML		 11466 struct drm_atomic_state *state;
11467 struct drm_plane_state *plane_state;
11468
f900db47 11469out_hang:
02e0efb5
ML		 11470 state = drm_atomic_state_alloc(dev);
11471 if (!state)
11472 return -ENOMEM;
11473 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11474
11475retry:
11476 plane_state = drm_atomic_get_plane_state(state, primary);
11477 ret = PTR_ERR_OR_ZERO(plane_state);
11478 if (!ret) {
11479 drm_atomic_set_fb_for_plane(plane_state, fb);
11480
11481 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11482 if (!ret)
11483 ret = drm_atomic_commit(state);
11484 }
11485
11486 if (ret == -EDEADLK) {
11487 drm_modeset_backoff(state->acquire_ctx);
11488 drm_atomic_state_clear(state);
11489 goto retry;
11490 }
11491
11492 if (ret)
11493 drm_atomic_state_free(state);
11494
f0d3dad3 11495 if (ret == 0 && event) {
5e2d7afc 11496 spin_lock_irq(&dev->event_lock);
a071fa00 11497 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11498 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11499 }
f900db47 11500 }
96b099fd 11501 return ret;
6b95a207
KH		 11502}
11503
da20eabd
ML		 11504
11505/**
11506 * intel_wm_need_update - Check whether watermarks need updating
11507 * @plane: drm plane
11508 * @state: new plane state
11509 *
11510 * Check current plane state versus the new one to determine whether
11511 * watermarks need to be recalculated.
11512 *
11513 * Returns true or false.
11514 */
11515static bool intel_wm_need_update(struct drm_plane *plane,
11516 struct drm_plane_state *state)
11517{
11518 /* Update watermarks on tiling changes. */
11519 if (!plane->state->fb || !state->fb ||
11520 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11521 plane->state->rotation != state->rotation)
11522 return true;
11523
11524 if (plane->state->crtc_w != state->crtc_w)
11525 return true;
11526
11527 return false;
11528}
11529
11530int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11531 struct drm_plane_state *plane_state)
11532{
11533 struct drm_crtc *crtc = crtc_state->crtc;
11534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11535 struct drm_plane *plane = plane_state->plane;
11536 struct drm_device *dev = crtc->dev;
11537 struct drm_i915_private *dev_priv = dev->dev_private;
11538 struct intel_plane_state *old_plane_state =
11539 to_intel_plane_state(plane->state);
11540 int idx = intel_crtc->base.base.id, ret;
11541 int i = drm_plane_index(plane);
11542 bool mode_changed = needs_modeset(crtc_state);
11543 bool was_crtc_enabled = crtc->state->active;
11544 bool is_crtc_enabled = crtc_state->active;
11545
11546 bool turn_off, turn_on, visible, was_visible;
11547 struct drm_framebuffer *fb = plane_state->fb;
11548
11549 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11550 plane->type != DRM_PLANE_TYPE_CURSOR) {
11551 ret = skl_update_scaler_plane(
11552 to_intel_crtc_state(crtc_state),
11553 to_intel_plane_state(plane_state));
11554 if (ret)
11555 return ret;
11556 }
11557
11558 /*
11559 * Disabling a plane is always okay; we just need to update
11560 * fb tracking in a special way since cleanup_fb() won't
11561 * get called by the plane helpers.
11562 */
11563 if (old_plane_state->base.fb && !fb)
11564 intel_crtc->atomic.disabled_planes |= 1 << i;
11565
da20eabd
ML		 11566 was_visible = old_plane_state->visible;
11567 visible = to_intel_plane_state(plane_state)->visible;
11568
11569 if (!was_crtc_enabled && WARN_ON(was_visible))
11570 was_visible = false;
11571
11572 if (!is_crtc_enabled && WARN_ON(visible))
11573 visible = false;
11574
11575 if (!was_visible && !visible)
11576 return 0;
11577
11578 turn_off = was_visible && (!visible || mode_changed);
11579 turn_on = visible && (!was_visible || mode_changed);
11580
11581 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11582 plane->base.id, fb ? fb->base.id : -1);
11583
11584 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11585 plane->base.id, was_visible, visible,
11586 turn_off, turn_on, mode_changed);
11587
852eb00d 11588 if (turn_on) {
f015c551 11589 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11590 /* must disable cxsr around plane enable/disable */
11591 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11592 intel_crtc->atomic.disable_cxsr = true;
11593 /* to potentially re-enable cxsr */
11594 intel_crtc->atomic.wait_vblank = true;
11595 intel_crtc->atomic.update_wm_post = true;
11596 }
11597 } else if (turn_off) {
f015c551 11598 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11599 /* must disable cxsr around plane enable/disable */
11600 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11601 if (is_crtc_enabled)
11602 intel_crtc->atomic.wait_vblank = true;
11603 intel_crtc->atomic.disable_cxsr = true;
11604 }
11605 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11606 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11607 }
da20eabd 11608
8be6ca85 11609 if (visible || was_visible)
a9ff8714
VS		 11610 intel_crtc->atomic.fb_bits |=
11611 to_intel_plane(plane)->frontbuffer_bit;
11612
da20eabd
ML		 11613 switch (plane->type) {
11614 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11615 intel_crtc->atomic.wait_for_flips = true;
11616 intel_crtc->atomic.pre_disable_primary = turn_off;
11617 intel_crtc->atomic.post_enable_primary = turn_on;
11618
066cf55b
RV		 11619 if (turn_off) {
11620 /*
11621 * FIXME: Actually if we will still have any other
11622 * plane enabled on the pipe we could let IPS enabled
11623 * still, but for now lets consider that when we make
11624 * primary invisible by setting DSPCNTR to 0 on
11625 * update_primary_plane function IPS needs to be
11626 * disable.
11627 */
11628 intel_crtc->atomic.disable_ips = true;
11629
da20eabd 11630 intel_crtc->atomic.disable_fbc = true;
066cf55b 11631 }
da20eabd
ML		 11632
11633 /*
11634 * FBC does not work on some platforms for rotated
11635 * planes, so disable it when rotation is not 0 and
11636 * update it when rotation is set back to 0.
11637 *
11638 * FIXME: This is redundant with the fbc update done in
11639 * the primary plane enable function except that that
11640 * one is done too late. We eventually need to unify
11641 * this.
11642 */
11643
11644 if (visible &&
11645 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11646 dev_priv->fbc.crtc == intel_crtc &&
11647 plane_state->rotation != BIT(DRM_ROTATE_0))
11648 intel_crtc->atomic.disable_fbc = true;
11649
11650 /*
11651 * BDW signals flip done immediately if the plane
11652 * is disabled, even if the plane enable is already
11653 * armed to occur at the next vblank :(
11654 */
11655 if (turn_on && IS_BROADWELL(dev))
11656 intel_crtc->atomic.wait_vblank = true;
11657
11658 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11659 break;
11660 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11661 break;
11662 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11663 if (turn_off && !mode_changed) {
da20eabd
ML		 11664 intel_crtc->atomic.wait_vblank = true;
11665 intel_crtc->atomic.update_sprite_watermarks |=
11666 1 << i;
11667 }
da20eabd
ML		 11668 }
11669 return 0;
11670}
11671
6d3a1ce7
ML		 11672static bool encoders_cloneable(const struct intel_encoder *a,
11673 const struct intel_encoder *b)
11674{
11675 /* masks could be asymmetric, so check both ways */
11676 return a == b || (a->cloneable & (1 << b->type) &&
11677 b->cloneable & (1 << a->type));
11678}
11679
11680static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11681 struct intel_crtc *crtc,
11682 struct intel_encoder *encoder)
11683{
11684 struct intel_encoder *source_encoder;
11685 struct drm_connector *connector;
11686 struct drm_connector_state *connector_state;
11687 int i;
11688
11689 for_each_connector_in_state(state, connector, connector_state, i) {
11690 if (connector_state->crtc != &crtc->base)
11691 continue;
11692
11693 source_encoder =
11694 to_intel_encoder(connector_state->best_encoder);
11695 if (!encoders_cloneable(encoder, source_encoder))
11696 return false;
11697 }
11698
11699 return true;
11700}
11701
11702static bool check_encoder_cloning(struct drm_atomic_state *state,
11703 struct intel_crtc *crtc)
11704{
11705 struct intel_encoder *encoder;
11706 struct drm_connector *connector;
11707 struct drm_connector_state *connector_state;
11708 int i;
11709
11710 for_each_connector_in_state(state, connector, connector_state, i) {
11711 if (connector_state->crtc != &crtc->base)
11712 continue;
11713
11714 encoder = to_intel_encoder(connector_state->best_encoder);
11715 if (!check_single_encoder_cloning(state, crtc, encoder))
11716 return false;
11717 }
11718
11719 return true;
11720}
11721
11722static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11723 struct drm_crtc_state *crtc_state)
11724{
cf5a15be 11725 struct drm_device *dev = crtc->dev;
ad421372 11726 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11728 struct intel_crtc_state *pipe_config =
11729 to_intel_crtc_state(crtc_state);
6d3a1ce7 11730 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11731 int ret;
6d3a1ce7
ML		 11732 bool mode_changed = needs_modeset(crtc_state);
11733
11734 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11735 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11736 return -EINVAL;
11737 }
11738
852eb00d
VS		 11739 if (mode_changed && !crtc_state->active)
11740 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11741
ad421372
ML		 11742 if (mode_changed && crtc_state->enable &&
11743 dev_priv->display.crtc_compute_clock &&
11744 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11745 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11746 pipe_config);
11747 if (ret)
11748 return ret;
11749 }
11750
e435d6e5
ML		 11751 ret = 0;
11752 if (INTEL_INFO(dev)->gen >= 9) {
11753 if (mode_changed)
11754 ret = skl_update_scaler_crtc(pipe_config);
11755
11756 if (!ret)
11757 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11758 pipe_config);
11759 }
11760
11761 return ret;
6d3a1ce7
ML		 11762}
11763
65b38e0d 11764static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11765 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11766 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11767 .atomic_begin = intel_begin_crtc_commit,
11768 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11769 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11770};
11771
d29b2f9d
ACO		 11772static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11773{
11774 struct intel_connector *connector;
11775
11776 for_each_intel_connector(dev, connector) {
11777 if (connector->base.encoder) {
11778 connector->base.state->best_encoder =
11779 connector->base.encoder;
11780 connector->base.state->crtc =
11781 connector->base.encoder->crtc;
11782 } else {
11783 connector->base.state->best_encoder = NULL;
11784 connector->base.state->crtc = NULL;
11785 }
11786 }
11787}
11788
050f7aeb 11789static void
eba905b2 11790connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11791 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11792{
11793 int bpp = pipe_config->pipe_bpp;
11794
11795 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11796 connector->base.base.id,
c23cc417 11797 connector->base.name);
050f7aeb
DV		 11798
11799 /* Don't use an invalid EDID bpc value */
11800 if (connector->base.display_info.bpc &&
11801 connector->base.display_info.bpc * 3 < bpp) {
11802 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11803 bpp, connector->base.display_info.bpc*3);
11804 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11805 }
11806
11807 /* Clamp bpp to 8 on screens without EDID 1.4 */
11808 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11809 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11810 bpp);
11811 pipe_config->pipe_bpp = 24;
11812 }
11813}
11814
4e53c2e0 11815static int
050f7aeb 11816compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11817 struct intel_crtc_state *pipe_config)
4e53c2e0 11818{
050f7aeb 11819 struct drm_device *dev = crtc->base.dev;
1486017f 11820 struct drm_atomic_state *state;
da3ced29
ACO		 11821 struct drm_connector *connector;
11822 struct drm_connector_state *connector_state;
1486017f 11823 int bpp, i;
4e53c2e0 11824
d328c9d7 11825 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11826 bpp = 10*3;
d328c9d7
DV		 11827 else if (INTEL_INFO(dev)->gen >= 5)
11828 bpp = 12*3;
11829 else
11830 bpp = 8*3;
11831
4e53c2e0 11832
4e53c2e0
DV		 11833 pipe_config->pipe_bpp = bpp;
11834
1486017f
ACO		 11835 state = pipe_config->base.state;
11836
4e53c2e0 11837 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11838 for_each_connector_in_state(state, connector, connector_state, i) {
11839 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11840 continue;
11841
da3ced29
ACO		 11842 connected_sink_compute_bpp(to_intel_connector(connector),
11843 pipe_config);
4e53c2e0
DV		 11844 }
11845
11846 return bpp;
11847}
11848
644db711
DV		 11849static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11850{
11851 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11852 "type: 0x%x flags: 0x%x\n",
1342830c 11853 mode->crtc_clock,
644db711
DV		 11854 mode->crtc_hdisplay, mode->crtc_hsync_start,
11855 mode->crtc_hsync_end, mode->crtc_htotal,
11856 mode->crtc_vdisplay, mode->crtc_vsync_start,
11857 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11858}
11859
c0b03411 11860static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11861 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11862 const char *context)
11863{
6a60cd87
CK		 11864 struct drm_device *dev = crtc->base.dev;
11865 struct drm_plane *plane;
11866 struct intel_plane *intel_plane;
11867 struct intel_plane_state *state;
11868 struct drm_framebuffer *fb;
11869
11870 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11871 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11872
11873 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11874 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11875 pipe_config->pipe_bpp, pipe_config->dither);
11876 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11877 pipe_config->has_pch_encoder,
11878 pipe_config->fdi_lanes,
11879 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11880 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11881 pipe_config->fdi_m_n.tu);
90a6b7b0 11882 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11883 pipe_config->has_dp_encoder,
90a6b7b0 11884 pipe_config->lane_count,
eb14cb74
VS		 11885 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11886 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11887 pipe_config->dp_m_n.tu);
b95af8be 11888
90a6b7b0 11889 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11890 pipe_config->has_dp_encoder,
90a6b7b0 11891 pipe_config->lane_count,
b95af8be
VK		 11892 pipe_config->dp_m2_n2.gmch_m,
11893 pipe_config->dp_m2_n2.gmch_n,
11894 pipe_config->dp_m2_n2.link_m,
11895 pipe_config->dp_m2_n2.link_n,
11896 pipe_config->dp_m2_n2.tu);
11897
55072d19
DV		 11898 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11899 pipe_config->has_audio,
11900 pipe_config->has_infoframe);
11901
c0b03411 11902 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11903 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11904 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11905 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11906 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11907 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11908 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11909 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11910 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11911 crtc->num_scalers,
11912 pipe_config->scaler_state.scaler_users,
11913 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11914 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11915 pipe_config->gmch_pfit.control,
11916 pipe_config->gmch_pfit.pgm_ratios,
11917 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11918 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11919 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11920 pipe_config->pch_pfit.size,
11921 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11922 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11923 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11924
415ff0f6 11925 if (IS_BROXTON(dev)) {
05712c15 11926 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11927 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11928 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11929 pipe_config->ddi_pll_sel,
11930 pipe_config->dpll_hw_state.ebb0,
05712c15 11931 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11932 pipe_config->dpll_hw_state.pll0,
11933 pipe_config->dpll_hw_state.pll1,
11934 pipe_config->dpll_hw_state.pll2,
11935 pipe_config->dpll_hw_state.pll3,
11936 pipe_config->dpll_hw_state.pll6,
11937 pipe_config->dpll_hw_state.pll8,
05712c15 11938 pipe_config->dpll_hw_state.pll9,
c8453338 11939 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11940 pipe_config->dpll_hw_state.pcsdw12);
11941 } else if (IS_SKYLAKE(dev)) {
11942 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11943 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11944 pipe_config->ddi_pll_sel,
11945 pipe_config->dpll_hw_state.ctrl1,
11946 pipe_config->dpll_hw_state.cfgcr1,
11947 pipe_config->dpll_hw_state.cfgcr2);
11948 } else if (HAS_DDI(dev)) {
11949 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.wrpll);
11952 } else {
11953 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11954 "fp0: 0x%x, fp1: 0x%x\n",
11955 pipe_config->dpll_hw_state.dpll,
11956 pipe_config->dpll_hw_state.dpll_md,
11957 pipe_config->dpll_hw_state.fp0,
11958 pipe_config->dpll_hw_state.fp1);
11959 }
11960
6a60cd87
CK		 11961 DRM_DEBUG_KMS("planes on this crtc\n");
11962 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11963 intel_plane = to_intel_plane(plane);
11964 if (intel_plane->pipe != crtc->pipe)
11965 continue;
11966
11967 state = to_intel_plane_state(plane->state);
11968 fb = state->base.fb;
11969 if (!fb) {
11970 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11971 "disabled, scaler_id = %d\n",
11972 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11973 plane->base.id, intel_plane->pipe,
11974 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11975 drm_plane_index(plane), state->scaler_id);
11976 continue;
11977 }
11978
11979 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11980 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11981 plane->base.id, intel_plane->pipe,
11982 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11983 drm_plane_index(plane));
11984 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11985 fb->base.id, fb->width, fb->height, fb->pixel_format);
11986 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11987 state->scaler_id,
11988 state->src.x1 >> 16, state->src.y1 >> 16,
11989 drm_rect_width(&state->src) >> 16,
11990 drm_rect_height(&state->src) >> 16,
11991 state->dst.x1, state->dst.y1,
11992 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11993 }
c0b03411
DV		 11994}
11995
5448a00d 11996static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11997{
5448a00d
ACO		 11998 struct drm_device *dev = state->dev;
11999 struct intel_encoder *encoder;
da3ced29 12000 struct drm_connector *connector;
5448a00d 12001 struct drm_connector_state *connector_state;
00f0b378 12002 unsigned int used_ports = 0;
5448a00d 12003 int i;
00f0b378
VS		 12004
12005 /*
12006 * Walk the connector list instead of the encoder
12007 * list to detect the problem on ddi platforms
12008 * where there's just one encoder per digital port.
12009 */
da3ced29 12010 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12011 if (!connector_state->best_encoder)
00f0b378
VS		 12012 continue;
12013
5448a00d
ACO		 12014 encoder = to_intel_encoder(connector_state->best_encoder);
12015
12016 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12017
12018 switch (encoder->type) {
12019 unsigned int port_mask;
12020 case INTEL_OUTPUT_UNKNOWN:
12021 if (WARN_ON(!HAS_DDI(dev)))
12022 break;
12023 case INTEL_OUTPUT_DISPLAYPORT:
12024 case INTEL_OUTPUT_HDMI:
12025 case INTEL_OUTPUT_EDP:
12026 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12027
12028 /* the same port mustn't appear more than once */
12029 if (used_ports & port_mask)
12030 return false;
12031
12032 used_ports |= port_mask;
12033 default:
12034 break;
12035 }
12036 }
12037
12038 return true;
12039}
12040
83a57153
ACO		 12041static void
12042clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12043{
12044 struct drm_crtc_state tmp_state;
663a3640 12045 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12046 struct intel_dpll_hw_state dpll_hw_state;
12047 enum intel_dpll_id shared_dpll;
8504c74c 12048 uint32_t ddi_pll_sel;
c4e2d043 12049 bool force_thru;
83a57153 12050
7546a384
ACO		 12051 /* FIXME: before the switch to atomic started, a new pipe_config was
12052 * kzalloc'd. Code that depends on any field being zero should be
12053 * fixed, so that the crtc_state can be safely duplicated. For now,
12054 * only fields that are know to not cause problems are preserved. */
12055
83a57153 12056 tmp_state = crtc_state->base;
663a3640 12057 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12058 shared_dpll = crtc_state->shared_dpll;
12059 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12060 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12061 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12062
83a57153 12063 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12064
83a57153 12065 crtc_state->base = tmp_state;
663a3640 12066 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12067 crtc_state->shared_dpll = shared_dpll;
12068 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12069 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12070 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12071}
12072
548ee15b 12073static int
b8cecdf5 12074intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12075 struct intel_crtc_state *pipe_config)
ee7b9f93 12076{
b359283a 12077 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12078 struct intel_encoder *encoder;
da3ced29 12079 struct drm_connector *connector;
0b901879 12080 struct drm_connector_state *connector_state;
d328c9d7 12081 int base_bpp, ret = -EINVAL;
0b901879 12082 int i;
e29c22c0 12083 bool retry = true;
ee7b9f93 12084
83a57153 12085 clear_intel_crtc_state(pipe_config);
7758a113 12086
e143a21c
DV		 12087 pipe_config->cpu_transcoder =
12088 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12089
2960bc9c
ID		 12090 /*
12091 * Sanitize sync polarity flags based on requested ones. If neither
12092 * positive or negative polarity is requested, treat this as meaning
12093 * negative polarity.
12094 */
2d112de7 12095 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12096 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12097 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12098
2d112de7 12099 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12100 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12101 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12102
d328c9d7
DV		 12103 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12104 pipe_config);
12105 if (base_bpp < 0)
4e53c2e0
DV		 12106 goto fail;
12107
e41a56be
VS		 12108 /*
12109 * Determine the real pipe dimensions. Note that stereo modes can
12110 * increase the actual pipe size due to the frame doubling and
12111 * insertion of additional space for blanks between the frame. This
12112 * is stored in the crtc timings. We use the requested mode to do this
12113 * computation to clearly distinguish it from the adjusted mode, which
12114 * can be changed by the connectors in the below retry loop.
12115 */
2d112de7 12116 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12117 &pipe_config->pipe_src_w,
12118 &pipe_config->pipe_src_h);
e41a56be 12119
e29c22c0 12120encoder_retry:
ef1b460d 12121 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12122 pipe_config->port_clock = 0;
ef1b460d 12123 pipe_config->pixel_multiplier = 1;
ff9a6750 12124
135c81b8 12125 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12126 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12127 CRTC_STEREO_DOUBLE);
135c81b8 12128
7758a113
DV		 12129 /* Pass our mode to the connectors and the CRTC to give them a chance to
12130 * adjust it according to limitations or connector properties, and also
12131 * a chance to reject the mode entirely.
47f1c6c9 12132 */
da3ced29 12133 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12134 if (connector_state->crtc != crtc)
7758a113 12135 continue;
7ae89233 12136
0b901879
ACO		 12137 encoder = to_intel_encoder(connector_state->best_encoder);
12138
efea6e8e
DV		 12139 if (!(encoder->compute_config(encoder, pipe_config))) {
12140 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12141 goto fail;
12142 }
ee7b9f93 12143 }
47f1c6c9 12144
ff9a6750
DV		 12145 /* Set default port clock if not overwritten by the encoder. Needs to be
12146 * done afterwards in case the encoder adjusts the mode. */
12147 if (!pipe_config->port_clock)
2d112de7 12148 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12149 * pipe_config->pixel_multiplier;
ff9a6750 12150
a43f6e0f 12151 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12152 if (ret < 0) {
7758a113
DV		 12153 DRM_DEBUG_KMS("CRTC fixup failed\n");
12154 goto fail;
ee7b9f93 12155 }
e29c22c0
DV		 12156
12157 if (ret == RETRY) {
12158 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12159 ret = -EINVAL;
12160 goto fail;
12161 }
12162
12163 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12164 retry = false;
12165 goto encoder_retry;
12166 }
12167
e8fa4270
DV		 12168 /* Dithering seems to not pass-through bits correctly when it should, so
12169 * only enable it on 6bpc panels. */
12170 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12171 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12172 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12173
7758a113 12174fail:
548ee15b 12175 return ret;
ee7b9f93 12176}
47f1c6c9 12177
ea9d758d 12178static void
4740b0f2 12179intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12180{
0a9ab303
ACO		 12181 struct drm_crtc *crtc;
12182 struct drm_crtc_state *crtc_state;
8a75d157 12183 int i;
ea9d758d 12184
7668851f 12185 /* Double check state. */
8a75d157 12186 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12187 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12188
12189 /* Update hwmode for vblank functions */
12190 if (crtc->state->active)
12191 crtc->hwmode = crtc->state->adjusted_mode;
12192 else
12193 crtc->hwmode.crtc_clock = 0;
ea9d758d 12194 }
ea9d758d
DV		 12195}
12196
3bd26263 12197static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12198{
3bd26263 12199 int diff;
f1f644dc
JB		 12200
12201 if (clock1 == clock2)
12202 return true;
12203
12204 if (!clock1 || !clock2)
12205 return false;
12206
12207 diff = abs(clock1 - clock2);
12208
12209 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12210 return true;
12211
12212 return false;
12213}
12214
25c5b266
DV		 12215#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12216 list_for_each_entry((intel_crtc), \
12217 &(dev)->mode_config.crtc_list, \
12218 base.head) \
0973f18f 12219 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12220
cfb23ed6
ML		 12221
12222static bool
12223intel_compare_m_n(unsigned int m, unsigned int n,
12224 unsigned int m2, unsigned int n2,
12225 bool exact)
12226{
12227 if (m == m2 && n == n2)
12228 return true;
12229
12230 if (exact || !m || !n || !m2 || !n2)
12231 return false;
12232
12233 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12234
12235 if (m > m2) {
12236 while (m > m2) {
12237 m2 <<= 1;
12238 n2 <<= 1;
12239 }
12240 } else if (m < m2) {
12241 while (m < m2) {
12242 m <<= 1;
12243 n <<= 1;
12244 }
12245 }
12246
12247 return m == m2 && n == n2;
12248}
12249
12250static bool
12251intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12252 struct intel_link_m_n *m2_n2,
12253 bool adjust)
12254{
12255 if (m_n->tu == m2_n2->tu &&
12256 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12257 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12258 intel_compare_m_n(m_n->link_m, m_n->link_n,
12259 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12260 if (adjust)
12261 *m2_n2 = *m_n;
12262
12263 return true;
12264 }
12265
12266 return false;
12267}
12268
0e8ffe1b 12269static bool
2fa2fe9a 12270intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12271 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12272 struct intel_crtc_state *pipe_config,
12273 bool adjust)
0e8ffe1b 12274{
cfb23ed6
ML		 12275 bool ret = true;
12276
12277#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12278 do { \
12279 if (!adjust) \
12280 DRM_ERROR(fmt, ##__VA_ARGS__); \
12281 else \
12282 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12283 } while (0)
12284
66e985c0
DV		 12285#define PIPE_CONF_CHECK_X(name) \
12286 if (current_config->name != pipe_config->name) { \
cfb23ed6 12287 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12288 "(expected 0x%08x, found 0x%08x)\n", \
12289 current_config->name, \
12290 pipe_config->name); \
cfb23ed6 12291 ret = false; \
66e985c0
DV		 12292 }
12293
08a24034
DV		 12294#define PIPE_CONF_CHECK_I(name) \
12295 if (current_config->name != pipe_config->name) { \
cfb23ed6 12296 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12297 "(expected %i, found %i)\n", \
12298 current_config->name, \
12299 pipe_config->name); \
cfb23ed6
ML		 12300 ret = false; \
12301 }
12302
12303#define PIPE_CONF_CHECK_M_N(name) \
12304 if (!intel_compare_link_m_n(&current_config->name, \
12305 &pipe_config->name,\
12306 adjust)) { \
12307 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12308 "(expected tu %i gmch %i/%i link %i/%i, " \
12309 "found tu %i, gmch %i/%i link %i/%i)\n", \
12310 current_config->name.tu, \
12311 current_config->name.gmch_m, \
12312 current_config->name.gmch_n, \
12313 current_config->name.link_m, \
12314 current_config->name.link_n, \
12315 pipe_config->name.tu, \
12316 pipe_config->name.gmch_m, \
12317 pipe_config->name.gmch_n, \
12318 pipe_config->name.link_m, \
12319 pipe_config->name.link_n); \
12320 ret = false; \
12321 }
12322
12323#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12324 if (!intel_compare_link_m_n(&current_config->name, \
12325 &pipe_config->name, adjust) && \
12326 !intel_compare_link_m_n(&current_config->alt_name, \
12327 &pipe_config->name, adjust)) { \
12328 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12329 "(expected tu %i gmch %i/%i link %i/%i, " \
12330 "or tu %i gmch %i/%i link %i/%i, " \
12331 "found tu %i, gmch %i/%i link %i/%i)\n", \
12332 current_config->name.tu, \
12333 current_config->name.gmch_m, \
12334 current_config->name.gmch_n, \
12335 current_config->name.link_m, \
12336 current_config->name.link_n, \
12337 current_config->alt_name.tu, \
12338 current_config->alt_name.gmch_m, \
12339 current_config->alt_name.gmch_n, \
12340 current_config->alt_name.link_m, \
12341 current_config->alt_name.link_n, \
12342 pipe_config->name.tu, \
12343 pipe_config->name.gmch_m, \
12344 pipe_config->name.gmch_n, \
12345 pipe_config->name.link_m, \
12346 pipe_config->name.link_n); \
12347 ret = false; \
88adfff1
DV		 12348 }
12349
b95af8be
VK		 12350/* This is required for BDW+ where there is only one set of registers for
12351 * switching between high and low RR.
12352 * This macro can be used whenever a comparison has to be made between one
12353 * hw state and multiple sw state variables.
12354 */
12355#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12356 if ((current_config->name != pipe_config->name) && \
12357 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12358 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12359 "(expected %i or %i, found %i)\n", \
12360 current_config->name, \
12361 current_config->alt_name, \
12362 pipe_config->name); \
cfb23ed6 12363 ret = false; \
b95af8be
VK		 12364 }
12365
1bd1bd80
DV		 12366#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12367 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12368 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12369 "(expected %i, found %i)\n", \
12370 current_config->name & (mask), \
12371 pipe_config->name & (mask)); \
cfb23ed6 12372 ret = false; \
1bd1bd80
DV		 12373 }
12374
5e550656
VS		 12375#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12376 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12377 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12378 "(expected %i, found %i)\n", \
12379 current_config->name, \
12380 pipe_config->name); \
cfb23ed6 12381 ret = false; \
5e550656
VS		 12382 }
12383
bb760063
DV		 12384#define PIPE_CONF_QUIRK(quirk) \
12385 ((current_config->quirks | pipe_config->quirks) & (quirk))
12386
eccb140b
DV		 12387 PIPE_CONF_CHECK_I(cpu_transcoder);
12388
08a24034
DV		 12389 PIPE_CONF_CHECK_I(has_pch_encoder);
12390 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12391 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12392
eb14cb74 12393 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12394 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12395
12396 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12397 PIPE_CONF_CHECK_M_N(dp_m_n);
12398
12399 PIPE_CONF_CHECK_I(has_drrs);
12400 if (current_config->has_drrs)
12401 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12402 } else
12403 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12404
2d112de7
ACO		 12405 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12406 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12408 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12409 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12410 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12411
2d112de7
ACO		 12412 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12413 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12414 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12415 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12416 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12417 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12418
c93f54cf 12419 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12420 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12421 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12422 IS_VALLEYVIEW(dev))
12423 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12424 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12425
9ed109a7
DV		 12426 PIPE_CONF_CHECK_I(has_audio);
12427
2d112de7 12428 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12429 DRM_MODE_FLAG_INTERLACE);
12430
bb760063 12431 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12432 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12433 DRM_MODE_FLAG_PHSYNC);
2d112de7 12434 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12435 DRM_MODE_FLAG_NHSYNC);
2d112de7 12436 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12437 DRM_MODE_FLAG_PVSYNC);
2d112de7 12438 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12439 DRM_MODE_FLAG_NVSYNC);
12440 }
045ac3b5 12441
37327abd
VS		 12442 PIPE_CONF_CHECK_I(pipe_src_w);
12443 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12444
333b8ca8 12445 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12446 /* pfit ratios are autocomputed by the hw on gen4+ */
12447 if (INTEL_INFO(dev)->gen < 4)
12448 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12449 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12450
fd4daa9c
CW		 12451 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12452 if (current_config->pch_pfit.enabled) {
333b8ca8
VS		 12453 PIPE_CONF_CHECK_X(pch_pfit.pos);
12454 PIPE_CONF_CHECK_X(pch_pfit.size);
fd4daa9c 12455 }
2fa2fe9a 12456
a1b2278e
CK		 12457 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12458
e59150dc
JB		 12459 /* BDW+ don't expose a synchronous way to read the state */
12460 if (IS_HASWELL(dev))
12461 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12462
282740f7
VS		 12463 PIPE_CONF_CHECK_I(double_wide);
12464
26804afd
DV		 12465 PIPE_CONF_CHECK_X(ddi_pll_sel);
12466
c0d43d62 12467 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12468 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12469 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12470 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12471 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12472 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12473 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12474 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12475 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12476
42571aef
VS		 12477 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12478 PIPE_CONF_CHECK_I(pipe_bpp);
12479
2d112de7 12480 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12481 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12482
66e985c0 12483#undef PIPE_CONF_CHECK_X
08a24034 12484#undef PIPE_CONF_CHECK_I
b95af8be 12485#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12486#undef PIPE_CONF_CHECK_FLAGS
5e550656 12487#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12488#undef PIPE_CONF_QUIRK
cfb23ed6 12489#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12490
cfb23ed6 12491 return ret;
0e8ffe1b
DV		 12492}
12493
08db6652
DL		 12494static void check_wm_state(struct drm_device *dev)
12495{
12496 struct drm_i915_private *dev_priv = dev->dev_private;
12497 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12498 struct intel_crtc *intel_crtc;
12499 int plane;
12500
12501 if (INTEL_INFO(dev)->gen < 9)
12502 return;
12503
12504 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12505 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12506
12507 for_each_intel_crtc(dev, intel_crtc) {
12508 struct skl_ddb_entry *hw_entry, *sw_entry;
12509 const enum pipe pipe = intel_crtc->pipe;
12510
12511 if (!intel_crtc->active)
12512 continue;
12513
12514 /* planes */
dd740780 12515 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12516 hw_entry = &hw_ddb.plane[pipe][plane];
12517 sw_entry = &sw_ddb->plane[pipe][plane];
12518
12519 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12520 continue;
12521
12522 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12523 "(expected (%u,%u), found (%u,%u))\n",
12524 pipe_name(pipe), plane + 1,
12525 sw_entry->start, sw_entry->end,
12526 hw_entry->start, hw_entry->end);
12527 }
12528
12529 /* cursor */
12530 hw_entry = &hw_ddb.cursor[pipe];
12531 sw_entry = &sw_ddb->cursor[pipe];
12532
12533 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12534 continue;
12535
12536 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12537 "(expected (%u,%u), found (%u,%u))\n",
12538 pipe_name(pipe),
12539 sw_entry->start, sw_entry->end,
12540 hw_entry->start, hw_entry->end);
12541 }
12542}
12543
91d1b4bd 12544static void
35dd3c64
ML		 12545check_connector_state(struct drm_device *dev,
12546 struct drm_atomic_state *old_state)
8af6cf88 12547{
35dd3c64
ML		 12548 struct drm_connector_state *old_conn_state;
12549 struct drm_connector *connector;
12550 int i;
8af6cf88 12551
35dd3c64
ML		 12552 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12553 struct drm_encoder *encoder = connector->encoder;
12554 struct drm_connector_state *state = connector->state;
ad3c558f 12555
8af6cf88
DV		 12556 /* This also checks the encoder/connector hw state with the
12557 * ->get_hw_state callbacks. */
35dd3c64 12558 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12559
ad3c558f 12560 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12561 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12562 }
91d1b4bd
DV		 12563}
12564
12565static void
12566check_encoder_state(struct drm_device *dev)
12567{
12568 struct intel_encoder *encoder;
12569 struct intel_connector *connector;
8af6cf88 12570
b2784e15 12571 for_each_intel_encoder(dev, encoder) {
8af6cf88 12572 bool enabled = false;
4d20cd86 12573 enum pipe pipe;
8af6cf88
DV		 12574
12575 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12576 encoder->base.base.id,
8e329a03 12577 encoder->base.name);
8af6cf88 12578
3a3371ff 12579 for_each_intel_connector(dev, connector) {
4d20cd86 12580 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12581 continue;
12582 enabled = true;
ad3c558f
ML		 12583
12584 I915_STATE_WARN(connector->base.state->crtc !=
12585 encoder->base.crtc,
12586 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12587 }
0e32b39c 12588
e2c719b7 12589 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12590 "encoder's enabled state mismatch "
12591 "(expected %i, found %i)\n",
12592 !!encoder->base.crtc, enabled);
7c60d198
ML		 12593
12594 if (!encoder->base.crtc) {
4d20cd86 12595 bool active;
7c60d198 12596
4d20cd86
ML		 12597 active = encoder->get_hw_state(encoder, &pipe);
12598 I915_STATE_WARN(active,
12599 "encoder detached but still enabled on pipe %c.\n",
12600 pipe_name(pipe));
7c60d198 12601 }
8af6cf88 12602 }
91d1b4bd
DV		 12603}
12604
12605static void
4d20cd86 12606check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12607{
fbee40df 12608 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12609 struct intel_encoder *encoder;
4d20cd86
ML		 12610 struct drm_crtc_state *old_crtc_state;
12611 struct drm_crtc *crtc;
12612 int i;
8af6cf88 12613
4d20cd86
ML		 12614 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12616 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12617 bool active;
8af6cf88 12618
4d20cd86
ML		 12619 if (!needs_modeset(crtc->state))
12620 continue;
045ac3b5 12621
4d20cd86
ML		 12622 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12623 pipe_config = to_intel_crtc_state(old_crtc_state);
12624 memset(pipe_config, 0, sizeof(*pipe_config));
12625 pipe_config->base.crtc = crtc;
12626 pipe_config->base.state = old_state;
8af6cf88 12627
4d20cd86
ML		 12628 DRM_DEBUG_KMS("[CRTC:%d]\n",
12629 crtc->base.id);
8af6cf88 12630
4d20cd86
ML		 12631 active = dev_priv->display.get_pipe_config(intel_crtc,
12632 pipe_config);
d62cf62a 12633
b6b5d049 12634 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12635 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12636 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12637 active = crtc->state->active;
6c49f241 12638
4d20cd86 12639 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12640 "crtc active state doesn't match with hw state "
4d20cd86 12641 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12642
4d20cd86 12643 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12644 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12645 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12646
12647 for_each_encoder_on_crtc(dev, crtc, encoder) {
12648 enum pipe pipe;
12649
12650 active = encoder->get_hw_state(encoder, &pipe);
12651 I915_STATE_WARN(active != crtc->state->active,
12652 "[ENCODER:%i] active %i with crtc active %i\n",
12653 encoder->base.base.id, active, crtc->state->active);
12654
12655 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12656 "Encoder connected to wrong pipe %c\n",
12657 pipe_name(pipe));
12658
12659 if (active)
12660 encoder->get_config(encoder, pipe_config);
12661 }
53d9f4e9 12662
4d20cd86 12663 if (!crtc->state->active)
cfb23ed6
ML		 12664 continue;
12665
4d20cd86
ML		 12666 sw_config = to_intel_crtc_state(crtc->state);
12667 if (!intel_pipe_config_compare(dev, sw_config,
12668 pipe_config, false)) {
e2c719b7 12669 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12670 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12671 "[hw state]");
4d20cd86 12672 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12673 "[sw state]");
12674 }
8af6cf88
DV		 12675 }
12676}
12677
91d1b4bd
DV		 12678static void
12679check_shared_dpll_state(struct drm_device *dev)
12680{
fbee40df 12681 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12682 struct intel_crtc *crtc;
12683 struct intel_dpll_hw_state dpll_hw_state;
12684 int i;
5358901f
DV		 12685
12686 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12687 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12688 int enabled_crtcs = 0, active_crtcs = 0;
12689 bool active;
12690
12691 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12692
12693 DRM_DEBUG_KMS("%s\n", pll->name);
12694
12695 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12696
e2c719b7 12697 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12698 "more active pll users than references: %i vs %i\n",
3e369b76 12699 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12700 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12701 "pll in active use but not on in sw tracking\n");
e2c719b7 12702 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12703 "pll in on but not on in use in sw tracking\n");
e2c719b7 12704 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12705 "pll on state mismatch (expected %i, found %i)\n",
12706 pll->on, active);
12707
d3fcc808 12708 for_each_intel_crtc(dev, crtc) {
83d65738 12709 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12710 enabled_crtcs++;
12711 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12712 active_crtcs++;
12713 }
e2c719b7 12714 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12715 "pll active crtcs mismatch (expected %i, found %i)\n",
12716 pll->active, active_crtcs);
e2c719b7 12717 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12718 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12719 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12720
e2c719b7 12721 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12722 sizeof(dpll_hw_state)),
12723 "pll hw state mismatch\n");
5358901f 12724 }
8af6cf88
DV		 12725}
12726
ee165b1a
ML		 12727static void
12728intel_modeset_check_state(struct drm_device *dev,
12729 struct drm_atomic_state *old_state)
91d1b4bd 12730{
08db6652 12731 check_wm_state(dev);
35dd3c64 12732 check_connector_state(dev, old_state);
91d1b4bd 12733 check_encoder_state(dev);
4d20cd86 12734 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12735 check_shared_dpll_state(dev);
12736}
12737
5cec258b 12738void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12739 int dotclock)
12740{
12741 /*
12742 * FDI already provided one idea for the dotclock.
12743 * Yell if the encoder disagrees.
12744 */
2d112de7 12745 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12746 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12747 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12748}
12749
80715b2f
VS		 12750static void update_scanline_offset(struct intel_crtc *crtc)
12751{
12752 struct drm_device *dev = crtc->base.dev;
12753
12754 /*
12755 * The scanline counter increments at the leading edge of hsync.
12756 *
12757 * On most platforms it starts counting from vtotal-1 on the
12758 * first active line. That means the scanline counter value is
12759 * always one less than what we would expect. Ie. just after
12760 * start of vblank, which also occurs at start of hsync (on the
12761 * last active line), the scanline counter will read vblank_start-1.
12762 *
12763 * On gen2 the scanline counter starts counting from 1 instead
12764 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12765 * to keep the value positive), instead of adding one.
12766 *
12767 * On HSW+ the behaviour of the scanline counter depends on the output
12768 * type. For DP ports it behaves like most other platforms, but on HDMI
12769 * there's an extra 1 line difference. So we need to add two instead of
12770 * one to the value.
12771 */
12772 if (IS_GEN2(dev)) {
6e3c9717 12773 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12774 int vtotal;
12775
12776 vtotal = mode->crtc_vtotal;
12777 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12778 vtotal /= 2;
12779
12780 crtc->scanline_offset = vtotal - 1;
12781 } else if (HAS_DDI(dev) &&
409ee761 12782 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12783 crtc->scanline_offset = 2;
12784 } else
12785 crtc->scanline_offset = 1;
12786}
12787
ad421372 12788static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12789{
225da59b 12790 struct drm_device *dev = state->dev;
ed6739ef 12791 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12792 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12793 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12794 struct intel_crtc_state *intel_crtc_state;
12795 struct drm_crtc *crtc;
12796 struct drm_crtc_state *crtc_state;
0a9ab303 12797 int i;
ed6739ef
ACO		 12798
12799 if (!dev_priv->display.crtc_compute_clock)
ad421372 12800 return;
ed6739ef 12801
0a9ab303 12802 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12803 int dpll;
12804
0a9ab303 12805 intel_crtc = to_intel_crtc(crtc);
4978cc93 12806 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12807 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12808
ad421372 12809 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12810 continue;
12811
ad421372 12812 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12813
ad421372
ML		 12814 if (!shared_dpll)
12815 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12816
ad421372
ML		 12817 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12818 }
ed6739ef
ACO		 12819}
12820
99d736a2
ML		 12821/*
12822 * This implements the workaround described in the "notes" section of the mode
12823 * set sequence documentation. When going from no pipes or single pipe to
12824 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12825 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12826 */
12827static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12828{
12829 struct drm_crtc_state *crtc_state;
12830 struct intel_crtc *intel_crtc;
12831 struct drm_crtc *crtc;
12832 struct intel_crtc_state *first_crtc_state = NULL;
12833 struct intel_crtc_state *other_crtc_state = NULL;
12834 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12835 int i;
12836
12837 /* look at all crtc's that are going to be enabled in during modeset */
12838 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12839 intel_crtc = to_intel_crtc(crtc);
12840
12841 if (!crtc_state->active || !needs_modeset(crtc_state))
12842 continue;
12843
12844 if (first_crtc_state) {
12845 other_crtc_state = to_intel_crtc_state(crtc_state);
12846 break;
12847 } else {
12848 first_crtc_state = to_intel_crtc_state(crtc_state);
12849 first_pipe = intel_crtc->pipe;
12850 }
12851 }
12852
12853 /* No workaround needed? */
12854 if (!first_crtc_state)
12855 return 0;
12856
12857 /* w/a possibly needed, check how many crtc's are already enabled. */
12858 for_each_intel_crtc(state->dev, intel_crtc) {
12859 struct intel_crtc_state *pipe_config;
12860
12861 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12862 if (IS_ERR(pipe_config))
12863 return PTR_ERR(pipe_config);
12864
12865 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12866
12867 if (!pipe_config->base.active ||
12868 needs_modeset(&pipe_config->base))
12869 continue;
12870
12871 /* 2 or more enabled crtcs means no need for w/a */
12872 if (enabled_pipe != INVALID_PIPE)
12873 return 0;
12874
12875 enabled_pipe = intel_crtc->pipe;
12876 }
12877
12878 if (enabled_pipe != INVALID_PIPE)
12879 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12880 else if (other_crtc_state)
12881 other_crtc_state->hsw_workaround_pipe = first_pipe;
12882
12883 return 0;
12884}
12885
27c329ed
ML		 12886static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12887{
12888 struct drm_crtc *crtc;
12889 struct drm_crtc_state *crtc_state;
12890 int ret = 0;
12891
12892 /* add all active pipes to the state */
12893 for_each_crtc(state->dev, crtc) {
12894 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12895 if (IS_ERR(crtc_state))
12896 return PTR_ERR(crtc_state);
12897
12898 if (!crtc_state->active || needs_modeset(crtc_state))
12899 continue;
12900
12901 crtc_state->mode_changed = true;
12902
12903 ret = drm_atomic_add_affected_connectors(state, crtc);
12904 if (ret)
12905 break;
12906
12907 ret = drm_atomic_add_affected_planes(state, crtc);
12908 if (ret)
12909 break;
12910 }
12911
12912 return ret;
12913}
12914
12915
c347a676 12916static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12917{
12918 struct drm_device *dev = state->dev;
27c329ed 12919 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12920 int ret;
12921
b359283a
ML		 12922 if (!check_digital_port_conflicts(state)) {
12923 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12924 return -EINVAL;
12925 }
12926
054518dd
ACO		 12927 /*
12928 * See if the config requires any additional preparation, e.g.
12929 * to adjust global state with pipes off. We need to do this
12930 * here so we can get the modeset_pipe updated config for the new
12931 * mode set on this crtc. For other crtcs we need to use the
12932 * adjusted_mode bits in the crtc directly.
12933 */
27c329ed
ML		 12934 if (dev_priv->display.modeset_calc_cdclk) {
12935 unsigned int cdclk;
b432e5cf 12936
27c329ed
ML		 12937 ret = dev_priv->display.modeset_calc_cdclk(state);
12938
12939 cdclk = to_intel_atomic_state(state)->cdclk;
12940 if (!ret && cdclk != dev_priv->cdclk_freq)
12941 ret = intel_modeset_all_pipes(state);
12942
12943 if (ret < 0)
054518dd 12944 return ret;
27c329ed
ML		 12945 } else
12946 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12947
ad421372 12948 intel_modeset_clear_plls(state);
054518dd 12949
99d736a2 12950 if (IS_HASWELL(dev))
ad421372 12951 return haswell_mode_set_planes_workaround(state);
99d736a2 12952
ad421372 12953 return 0;
c347a676
ACO		 12954}
12955
74c090b1
ML		 12956/**
12957 * intel_atomic_check - validate state object
12958 * @dev: drm device
12959 * @state: state to validate
12960 */
12961static int intel_atomic_check(struct drm_device *dev,
12962 struct drm_atomic_state *state)
c347a676
ACO		 12963{
12964 struct drm_crtc *crtc;
12965 struct drm_crtc_state *crtc_state;
12966 int ret, i;
61333b60 12967 bool any_ms = false;
c347a676 12968
74c090b1 12969 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12970 if (ret)
12971 return ret;
12972
c347a676 12973 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12974 struct intel_crtc_state *pipe_config =
12975 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 12976
12977 /* Catch I915_MODE_FLAG_INHERITED */
12978 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12979 crtc_state->mode_changed = true;
cfb23ed6 12980
61333b60
ML		 12981 if (!crtc_state->enable) {
12982 if (needs_modeset(crtc_state))
12983 any_ms = true;
c347a676 12984 continue;
61333b60 12985 }
c347a676 12986
26495481 12987 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 12988 continue;
12989
26495481
DV		 12990 /* FIXME: For only active_changed we shouldn't need to do any
12991 * state recomputation at all. */
12992
1ed51de9
DV		 12993 ret = drm_atomic_add_affected_connectors(state, crtc);
12994 if (ret)
12995 return ret;
b359283a 12996
cfb23ed6 12997 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 12998 if (ret)
12999 return ret;
13000
26495481
DV		 13001 if (i915.fastboot &&
13002 intel_pipe_config_compare(state->dev,
cfb23ed6 13003 to_intel_crtc_state(crtc->state),
1ed51de9 13004 pipe_config, true)) {
26495481
DV		 13005 crtc_state->mode_changed = false;
13006 }
13007
13008 if (needs_modeset(crtc_state)) {
13009 any_ms = true;
cfb23ed6
ML		 13010
13011 ret = drm_atomic_add_affected_planes(state, crtc);
13012 if (ret)
13013 return ret;
13014 }
61333b60 13015
26495481
DV		 13016 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13017 needs_modeset(crtc_state) ?
13018 "[modeset]" : "[fastset]");
c347a676
ACO		 13019 }
13020
61333b60
ML		 13021 if (any_ms) {
13022 ret = intel_modeset_checks(state);
13023
13024 if (ret)
13025 return ret;
27c329ed
ML		 13026 } else
13027 to_intel_atomic_state(state)->cdclk =
13028 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13029
13030 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13031}
13032
74c090b1
ML		 13033/**
13034 * intel_atomic_commit - commit validated state object
13035 * @dev: DRM device
13036 * @state: the top-level driver state object
13037 * @async: asynchronous commit
13038 *
13039 * This function commits a top-level state object that has been validated
13040 * with drm_atomic_helper_check().
13041 *
13042 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13043 * we can only handle plane-related operations and do not yet support
13044 * asynchronous commit.
13045 *
13046 * RETURNS
13047 * Zero for success or -errno.
13048 */
13049static int intel_atomic_commit(struct drm_device *dev,
13050 struct drm_atomic_state *state,
13051 bool async)
a6778b3c 13052{
fbee40df 13053 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13054 struct drm_crtc *crtc;
13055 struct drm_crtc_state *crtc_state;
c0c36b94 13056 int ret = 0;
0a9ab303 13057 int i;
61333b60 13058 bool any_ms = false;
a6778b3c 13059
74c090b1
ML		 13060 if (async) {
13061 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13062 return -EINVAL;
13063 }
13064
d4afb8cc
ACO		 13065 ret = drm_atomic_helper_prepare_planes(dev, state);
13066 if (ret)
13067 return ret;
13068
1c5e19f8
ML		 13069 drm_atomic_helper_swap_state(dev, state);
13070
0a9ab303 13071 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13073
61333b60
ML		 13074 if (!needs_modeset(crtc->state))
13075 continue;
13076
13077 any_ms = true;
a539205a 13078 intel_pre_plane_update(intel_crtc);
460da916 13079
a539205a
ML		 13080 if (crtc_state->active) {
13081 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13082 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13083 intel_crtc->active = false;
13084 intel_disable_shared_dpll(intel_crtc);
a539205a 13085 }
b8cecdf5 13086 }
7758a113 13087
ea9d758d
DV		 13088 /* Only after disabling all output pipelines that will be changed can we
13089 * update the the output configuration. */
4740b0f2 13090 intel_modeset_update_crtc_state(state);
f6e5b160 13091
4740b0f2
ML		 13092 if (any_ms) {
13093 intel_shared_dpll_commit(state);
13094
13095 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13096 modeset_update_crtc_power_domains(state);
4740b0f2 13097 }
47fab737 13098
a6778b3c 13099 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13100 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13102 bool modeset = needs_modeset(crtc->state);
13103
13104 if (modeset && crtc->state->active) {
a539205a
ML		 13105 update_scanline_offset(to_intel_crtc(crtc));
13106 dev_priv->display.crtc_enable(crtc);
13107 }
80715b2f 13108
f6ac4b2a
ML		 13109 if (!modeset)
13110 intel_pre_plane_update(intel_crtc);
13111
a539205a 13112 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13113 intel_post_plane_update(intel_crtc);
80715b2f 13114 }
a6778b3c 13115
a6778b3c 13116 /* FIXME: add subpixel order */
83a57153 13117
74c090b1 13118 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13119 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13120
74c090b1 13121 if (any_ms)
ee165b1a
ML		 13122 intel_modeset_check_state(dev, state);
13123
13124 drm_atomic_state_free(state);
f30da187 13125
74c090b1 13126 return 0;
7f27126e
JB		 13127}
13128
c0c36b94
CW		 13129void intel_crtc_restore_mode(struct drm_crtc *crtc)
13130{
83a57153
ACO		 13131 struct drm_device *dev = crtc->dev;
13132 struct drm_atomic_state *state;
e694eb02 13133 struct drm_crtc_state *crtc_state;
2bfb4627 13134 int ret;
83a57153
ACO		 13135
13136 state = drm_atomic_state_alloc(dev);
13137 if (!state) {
e694eb02 13138 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13139 crtc->base.id);
13140 return;
13141 }
13142
e694eb02 13143 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13144
e694eb02
ML		 13145retry:
13146 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13147 ret = PTR_ERR_OR_ZERO(crtc_state);
13148 if (!ret) {
13149 if (!crtc_state->active)
13150 goto out;
83a57153 13151
e694eb02 13152 crtc_state->mode_changed = true;
74c090b1 13153 ret = drm_atomic_commit(state);
83a57153
ACO		 13154 }
13155
e694eb02
ML		 13156 if (ret == -EDEADLK) {
13157 drm_atomic_state_clear(state);
13158 drm_modeset_backoff(state->acquire_ctx);
13159 goto retry;
4ed9fb37 13160 }
4be07317 13161
2bfb4627 13162 if (ret)
e694eb02 13163out:
2bfb4627 13164 drm_atomic_state_free(state);
c0c36b94
CW		 13165}
13166
25c5b266
DV		 13167#undef for_each_intel_crtc_masked
13168
f6e5b160 13169static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13170 .gamma_set = intel_crtc_gamma_set,
74c090b1 13171 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13172 .destroy = intel_crtc_destroy,
13173 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13174 .atomic_duplicate_state = intel_crtc_duplicate_state,
13175 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13176};
13177
5358901f
DV		 13178static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13179 struct intel_shared_dpll *pll,
13180 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13181{
5358901f 13182 uint32_t val;
ee7b9f93 13183
f458ebbc 13184 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13185 return false;
13186
5358901f 13187 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13188 hw_state->dpll = val;
13189 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13190 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13191
13192 return val & DPLL_VCO_ENABLE;
13193}
13194
15bdd4cf
DV		 13195static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13196 struct intel_shared_dpll *pll)
13197{
3e369b76
ACO		 13198 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13199 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13200}
13201
e7b903d2
DV		 13202static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13203 struct intel_shared_dpll *pll)
13204{
e7b903d2 13205 /* PCH refclock must be enabled first */
89eff4be 13206 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13207
3e369b76 13208 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13209
13210 /* Wait for the clocks to stabilize. */
13211 POSTING_READ(PCH_DPLL(pll->id));
13212 udelay(150);
13213
13214 /* The pixel multiplier can only be updated once the
13215 * DPLL is enabled and the clocks are stable.
13216 *
13217 * So write it again.
13218 */
3e369b76 13219 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13220 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13221 udelay(200);
13222}
13223
13224static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13225 struct intel_shared_dpll *pll)
13226{
13227 struct drm_device *dev = dev_priv->dev;
13228 struct intel_crtc *crtc;
e7b903d2
DV		 13229
13230 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13231 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13232 if (intel_crtc_to_shared_dpll(crtc) == pll)
13233 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13234 }
13235
15bdd4cf
DV		 13236 I915_WRITE(PCH_DPLL(pll->id), 0);
13237 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13238 udelay(200);
13239}
13240
46edb027
DV		 13241static char *ibx_pch_dpll_names[] = {
13242 "PCH DPLL A",
13243 "PCH DPLL B",
13244};
13245
7c74ade1 13246static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13247{
e7b903d2 13248 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13249 int i;
13250
7c74ade1 13251 dev_priv->num_shared_dpll = 2;
ee7b9f93 13252
e72f9fbf 13253 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13254 dev_priv->shared_dplls[i].id = i;
13255 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13256 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13257 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13258 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13259 dev_priv->shared_dplls[i].get_hw_state =
13260 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13261 }
13262}
13263
7c74ade1
DV		 13264static void intel_shared_dpll_init(struct drm_device *dev)
13265{
e7b903d2 13266 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13267
b6283055
VS		 13268 intel_update_cdclk(dev);
13269
9cd86933
DV		 13270 if (HAS_DDI(dev))
13271 intel_ddi_pll_init(dev);
13272 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13273 ibx_pch_dpll_init(dev);
13274 else
13275 dev_priv->num_shared_dpll = 0;
13276
13277 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13278}
13279
6beb8c23
MR		 13280/**
13281 * intel_prepare_plane_fb - Prepare fb for usage on plane
13282 * @plane: drm plane to prepare for
13283 * @fb: framebuffer to prepare for presentation
13284 *
13285 * Prepares a framebuffer for usage on a display plane. Generally this
13286 * involves pinning the underlying object and updating the frontbuffer tracking
13287 * bits. Some older platforms need special physical address handling for
13288 * cursor planes.
13289 *
13290 * Returns 0 on success, negative error code on failure.
13291 */
13292int
13293intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13294 struct drm_framebuffer *fb,
13295 const struct drm_plane_state *new_state)
465c120c
MR		 13296{
13297 struct drm_device *dev = plane->dev;
6beb8c23 13298 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13299 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13300 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13301 int ret = 0;
465c120c 13302
ea2c67bb 13303 if (!obj)
465c120c
MR		 13304 return 0;
13305
6beb8c23 13306 mutex_lock(&dev->struct_mutex);
465c120c 13307
6beb8c23
MR		 13308 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13309 INTEL_INFO(dev)->cursor_needs_physical) {
13310 int align = IS_I830(dev) ? 16 * 1024 : 256;
13311 ret = i915_gem_object_attach_phys(obj, align);
13312 if (ret)
13313 DRM_DEBUG_KMS("failed to attach phys object\n");
13314 } else {
91af127f 13315 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13316 }
465c120c 13317
6beb8c23 13318 if (ret == 0)
a9ff8714 13319 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13320
4c34574f 13321 mutex_unlock(&dev->struct_mutex);
465c120c 13322
6beb8c23
MR		 13323 return ret;
13324}
13325
38f3ce3a
MR		 13326/**
13327 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13328 * @plane: drm plane to clean up for
13329 * @fb: old framebuffer that was on plane
13330 *
13331 * Cleans up a framebuffer that has just been removed from a plane.
13332 */
13333void
13334intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13335 struct drm_framebuffer *fb,
13336 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13337{
13338 struct drm_device *dev = plane->dev;
13339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13340
13341 if (WARN_ON(!obj))
13342 return;
13343
13344 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13345 !INTEL_INFO(dev)->cursor_needs_physical) {
13346 mutex_lock(&dev->struct_mutex);
82bc3b2d 13347 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13348 mutex_unlock(&dev->struct_mutex);
13349 }
465c120c
MR		 13350}
13351
6156a456
CK		 13352int
13353skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13354{
13355 int max_scale;
13356 struct drm_device *dev;
13357 struct drm_i915_private *dev_priv;
13358 int crtc_clock, cdclk;
13359
13360 if (!intel_crtc || !crtc_state)
13361 return DRM_PLANE_HELPER_NO_SCALING;
13362
13363 dev = intel_crtc->base.dev;
13364 dev_priv = dev->dev_private;
13365 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13366 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13367
13368 if (!crtc_clock || !cdclk)
13369 return DRM_PLANE_HELPER_NO_SCALING;
13370
13371 /*
13372 * skl max scale is lower of:
13373 * close to 3 but not 3, -1 is for that purpose
13374 * or
13375 * cdclk/crtc_clock
13376 */
13377 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13378
13379 return max_scale;
13380}
13381
465c120c 13382static int
3c692a41 13383intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13384 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13385 struct intel_plane_state *state)
13386{
2b875c22
MR		 13387 struct drm_crtc *crtc = state->base.crtc;
13388 struct drm_framebuffer *fb = state->base.fb;
6156a456 13389 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13390 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13391 bool can_position = false;
465c120c 13392
061e4b8d
ML		 13393 /* use scaler when colorkey is not required */
13394 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13395 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13396 min_scale = 1;
13397 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13398 can_position = true;
6156a456 13399 }
d8106366 13400
061e4b8d
ML		 13401 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13402 &state->dst, &state->clip,
da20eabd
ML		 13403 min_scale, max_scale,
13404 can_position, true,
13405 &state->visible);
14af293f
GP		 13406}
13407
13408static void
13409intel_commit_primary_plane(struct drm_plane *plane,
13410 struct intel_plane_state *state)
13411{
2b875c22
MR		 13412 struct drm_crtc *crtc = state->base.crtc;
13413 struct drm_framebuffer *fb = state->base.fb;
13414 struct drm_device *dev = plane->dev;
14af293f 13415 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13416 struct intel_crtc *intel_crtc;
14af293f
GP		 13417 struct drm_rect *src = &state->src;
13418
ea2c67bb
MR		 13419 crtc = crtc ? crtc : plane->crtc;
13420 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13421
13422 plane->fb = fb;
9dc806fc
MR		 13423 crtc->x = src->x1 >> 16;
13424 crtc->y = src->y1 >> 16;
ccc759dc 13425
a539205a 13426 if (!crtc->state->active)
302d19ac 13427 return;
465c120c 13428
302d19ac
ML		 13429 if (state->visible)
13430 /* FIXME: kill this fastboot hack */
13431 intel_update_pipe_size(intel_crtc);
13432
d4b08630
ML		 13433 dev_priv->display.update_primary_plane(crtc, fb,
13434 state->src.x1 >> 16,
13435 state->src.y1 >> 16);
465c120c
MR		 13436}
13437
a8ad0d8e
ML		 13438static void
13439intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13440 struct drm_crtc *crtc)
a8ad0d8e
ML		 13441{
13442 struct drm_device *dev = plane->dev;
13443 struct drm_i915_private *dev_priv = dev->dev_private;
13444
a8ad0d8e
ML		 13445 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13446}
13447
613d2b27
ML		 13448static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13449 struct drm_crtc_state *old_crtc_state)
3c692a41 13450{
32b7eeec 13451 struct drm_device *dev = crtc->dev;
3c692a41 13452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13453
f015c551 13454 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13455 intel_update_watermarks(crtc);
3c692a41 13456
c34c9ee4 13457 /* Perform vblank evasion around commit operation */
a539205a 13458 if (crtc->state->active)
34e0adbb 13459 intel_pipe_update_start(intel_crtc);
0583236e
ML		 13460
13461 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13462 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13463}
13464
613d2b27
ML		 13465static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13466 struct drm_crtc_state *old_crtc_state)
32b7eeec 13467{
32b7eeec 13468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13469
8f539a83 13470 if (crtc->state->active)
34e0adbb 13471 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13472}
13473
cf4c7c12 13474/**
4a3b8769
MR		 13475 * intel_plane_destroy - destroy a plane
13476 * @plane: plane to destroy
cf4c7c12 13477 *
4a3b8769
MR		 13478 * Common destruction function for all types of planes (primary, cursor,
13479 * sprite).
cf4c7c12 13480 */
4a3b8769 13481void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13482{
13483 struct intel_plane *intel_plane = to_intel_plane(plane);
13484 drm_plane_cleanup(plane);
13485 kfree(intel_plane);
13486}
13487
65a3fea0 13488const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13489 .update_plane = drm_atomic_helper_update_plane,
13490 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13491 .destroy = intel_plane_destroy,
c196e1d6 13492 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13493 .atomic_get_property = intel_plane_atomic_get_property,
13494 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13495 .atomic_duplicate_state = intel_plane_duplicate_state,
13496 .atomic_destroy_state = intel_plane_destroy_state,
13497
465c120c
MR		 13498};
13499
13500static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13501 int pipe)
13502{
13503 struct intel_plane *primary;
8e7d688b 13504 struct intel_plane_state *state;
465c120c 13505 const uint32_t *intel_primary_formats;
45e3743a 13506 unsigned int num_formats;
465c120c
MR		 13507
13508 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13509 if (primary == NULL)
13510 return NULL;
13511
8e7d688b
MR		 13512 state = intel_create_plane_state(&primary->base);
13513 if (!state) {
ea2c67bb
MR		 13514 kfree(primary);
13515 return NULL;
13516 }
8e7d688b 13517 primary->base.state = &state->base;
ea2c67bb 13518
465c120c
MR		 13519 primary->can_scale = false;
13520 primary->max_downscale = 1;
6156a456
CK		 13521 if (INTEL_INFO(dev)->gen >= 9) {
13522 primary->can_scale = true;
af99ceda 13523 state->scaler_id = -1;
6156a456 13524 }
465c120c
MR		 13525 primary->pipe = pipe;
13526 primary->plane = pipe;
a9ff8714 13527 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13528 primary->check_plane = intel_check_primary_plane;
13529 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13530 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13531 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13532 primary->plane = !pipe;
13533
6c0fd451
DL		 13534 if (INTEL_INFO(dev)->gen >= 9) {
13535 intel_primary_formats = skl_primary_formats;
13536 num_formats = ARRAY_SIZE(skl_primary_formats);
13537 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13538 intel_primary_formats = i965_primary_formats;
13539 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13540 } else {
13541 intel_primary_formats = i8xx_primary_formats;
13542 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13543 }
13544
13545 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13546 &intel_plane_funcs,
465c120c
MR		 13547 intel_primary_formats, num_formats,
13548 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13549
3b7a5119
SJ		 13550 if (INTEL_INFO(dev)->gen >= 4)
13551 intel_create_rotation_property(dev, primary);
48404c1e 13552
ea2c67bb
MR		 13553 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13554
465c120c
MR		 13555 return &primary->base;
13556}
13557
3b7a5119
SJ		 13558void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13559{
13560 if (!dev->mode_config.rotation_property) {
13561 unsigned long flags = BIT(DRM_ROTATE_0) |
13562 BIT(DRM_ROTATE_180);
13563
13564 if (INTEL_INFO(dev)->gen >= 9)
13565 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13566
13567 dev->mode_config.rotation_property =
13568 drm_mode_create_rotation_property(dev, flags);
13569 }
13570 if (dev->mode_config.rotation_property)
13571 drm_object_attach_property(&plane->base.base,
13572 dev->mode_config.rotation_property,
13573 plane->base.state->rotation);
13574}
13575
3d7d6510 13576static int
852e787c 13577intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13578 struct intel_crtc_state *crtc_state,
852e787c 13579 struct intel_plane_state *state)
3d7d6510 13580{
061e4b8d 13581 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13582 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13583 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13584 unsigned stride;
13585 int ret;
3d7d6510 13586
061e4b8d
ML		 13587 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13588 &state->dst, &state->clip,
3d7d6510
MR		 13589 DRM_PLANE_HELPER_NO_SCALING,
13590 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13591 true, true, &state->visible);
757f9a3e
GP		 13592 if (ret)
13593 return ret;
13594
757f9a3e
GP		 13595 /* if we want to turn off the cursor ignore width and height */
13596 if (!obj)
da20eabd 13597 return 0;
757f9a3e 13598
757f9a3e 13599 /* Check for which cursor types we support */
061e4b8d 13600 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13601 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13602 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13603 return -EINVAL;
13604 }
13605
ea2c67bb
MR		 13606 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13607 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13608 DRM_DEBUG_KMS("buffer is too small\n");
13609 return -ENOMEM;
13610 }
13611
3a656b54 13612 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13613 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13614 return -EINVAL;
32b7eeec
MR		 13615 }
13616
da20eabd 13617 return 0;
852e787c 13618}
3d7d6510 13619
a8ad0d8e
ML		 13620static void
13621intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13622 struct drm_crtc *crtc)
a8ad0d8e 13623{
a8ad0d8e
ML		 13624 intel_crtc_update_cursor(crtc, false);
13625}
13626
f4a2cf29 13627static void
852e787c
GP		 13628intel_commit_cursor_plane(struct drm_plane *plane,
13629 struct intel_plane_state *state)
13630{
2b875c22 13631 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13632 struct drm_device *dev = plane->dev;
13633 struct intel_crtc *intel_crtc;
2b875c22 13634 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13635 uint32_t addr;
852e787c 13636
ea2c67bb
MR		 13637 crtc = crtc ? crtc : plane->crtc;
13638 intel_crtc = to_intel_crtc(crtc);
13639
a912f12f
GP		 13640 if (intel_crtc->cursor_bo == obj)
13641 goto update;
4ed91096 13642
f4a2cf29 13643 if (!obj)
a912f12f 13644 addr = 0;
f4a2cf29 13645 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13646 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13647 else
a912f12f 13648 addr = obj->phys_handle->busaddr;
852e787c 13649
a912f12f
GP		 13650 intel_crtc->cursor_addr = addr;
13651 intel_crtc->cursor_bo = obj;
852e787c 13652
302d19ac 13653update:
a539205a 13654 if (crtc->state->active)
a912f12f 13655 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13656}
13657
3d7d6510
MR		 13658static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13659 int pipe)
13660{
13661 struct intel_plane *cursor;
8e7d688b 13662 struct intel_plane_state *state;
3d7d6510
MR		 13663
13664 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13665 if (cursor == NULL)
13666 return NULL;
13667
8e7d688b
MR		 13668 state = intel_create_plane_state(&cursor->base);
13669 if (!state) {
ea2c67bb
MR		 13670 kfree(cursor);
13671 return NULL;
13672 }
8e7d688b 13673 cursor->base.state = &state->base;
ea2c67bb 13674
3d7d6510
MR		 13675 cursor->can_scale = false;
13676 cursor->max_downscale = 1;
13677 cursor->pipe = pipe;
13678 cursor->plane = pipe;
a9ff8714 13679 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13680 cursor->check_plane = intel_check_cursor_plane;
13681 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13682 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13683
13684 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13685 &intel_plane_funcs,
3d7d6510
MR		 13686 intel_cursor_formats,
13687 ARRAY_SIZE(intel_cursor_formats),
13688 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13689
13690 if (INTEL_INFO(dev)->gen >= 4) {
13691 if (!dev->mode_config.rotation_property)
13692 dev->mode_config.rotation_property =
13693 drm_mode_create_rotation_property(dev,
13694 BIT(DRM_ROTATE_0) |
13695 BIT(DRM_ROTATE_180));
13696 if (dev->mode_config.rotation_property)
13697 drm_object_attach_property(&cursor->base.base,
13698 dev->mode_config.rotation_property,
8e7d688b 13699 state->base.rotation);
4398ad45
VS		 13700 }
13701
af99ceda
CK		 13702 if (INTEL_INFO(dev)->gen >=9)
13703 state->scaler_id = -1;
13704
ea2c67bb
MR		 13705 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13706
3d7d6510
MR		 13707 return &cursor->base;
13708}
13709
549e2bfb
CK		 13710static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13711 struct intel_crtc_state *crtc_state)
13712{
13713 int i;
13714 struct intel_scaler *intel_scaler;
13715 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13716
13717 for (i = 0; i < intel_crtc->num_scalers; i++) {
13718 intel_scaler = &scaler_state->scalers[i];
13719 intel_scaler->in_use = 0;
549e2bfb
CK		 13720 intel_scaler->mode = PS_SCALER_MODE_DYN;
13721 }
13722
13723 scaler_state->scaler_id = -1;
13724}
13725
b358d0a6 13726static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13727{
fbee40df 13728 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13729 struct intel_crtc *intel_crtc;
f5de6e07 13730 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13731 struct drm_plane *primary = NULL;
13732 struct drm_plane *cursor = NULL;
465c120c 13733 int i, ret;
79e53945 13734
955382f3 13735 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13736 if (intel_crtc == NULL)
13737 return;
13738
f5de6e07
ACO		 13739 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13740 if (!crtc_state)
13741 goto fail;
550acefd
ACO		 13742 intel_crtc->config = crtc_state;
13743 intel_crtc->base.state = &crtc_state->base;
07878248 13744 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13745
549e2bfb
CK		 13746 /* initialize shared scalers */
13747 if (INTEL_INFO(dev)->gen >= 9) {
13748 if (pipe == PIPE_C)
13749 intel_crtc->num_scalers = 1;
13750 else
13751 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13752
13753 skl_init_scalers(dev, intel_crtc, crtc_state);
13754 }
13755
465c120c 13756 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13757 if (!primary)
13758 goto fail;
13759
13760 cursor = intel_cursor_plane_create(dev, pipe);
13761 if (!cursor)
13762 goto fail;
13763
465c120c 13764 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13765 cursor, &intel_crtc_funcs);
13766 if (ret)
13767 goto fail;
79e53945
JB		 13768
13769 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13770 for (i = 0; i < 256; i++) {
13771 intel_crtc->lut_r[i] = i;
13772 intel_crtc->lut_g[i] = i;
13773 intel_crtc->lut_b[i] = i;
13774 }
13775
1f1c2e24
VS		 13776 /*
13777 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13778 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13779 */
80824003
JB		 13780 intel_crtc->pipe = pipe;
13781 intel_crtc->plane = pipe;
3a77c4c4 13782 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13783 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13784 intel_crtc->plane = !pipe;
80824003
JB		 13785 }
13786
4b0e333e
CW		 13787 intel_crtc->cursor_base = ~0;
13788 intel_crtc->cursor_cntl = ~0;
dc41c154 13789 intel_crtc->cursor_size = ~0;
8d7849db 13790
852eb00d
VS		 13791 intel_crtc->wm.cxsr_allowed = true;
13792
22fd0fab
JB		 13793 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13794 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13795 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13796 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13797
79e53945 13798 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13799
13800 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13801 return;
13802
13803fail:
13804 if (primary)
13805 drm_plane_cleanup(primary);
13806 if (cursor)
13807 drm_plane_cleanup(cursor);
f5de6e07 13808 kfree(crtc_state);
3d7d6510 13809 kfree(intel_crtc);
79e53945
JB		 13810}
13811
752aa88a
JB		 13812enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13813{
13814 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13815 struct drm_device *dev = connector->base.dev;
752aa88a 13816
51fd371b 13817 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13818
d3babd3f 13819 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13820 return INVALID_PIPE;
13821
13822 return to_intel_crtc(encoder->crtc)->pipe;
13823}
13824
08d7b3d1 13825int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13826 struct drm_file *file)
08d7b3d1 13827{
08d7b3d1 13828 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13829 struct drm_crtc *drmmode_crtc;
c05422d5 13830 struct intel_crtc *crtc;
08d7b3d1 13831
7707e653 13832 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13833
7707e653 13834 if (!drmmode_crtc) {
08d7b3d1 13835 DRM_ERROR("no such CRTC id\n");
3f2c2057 13836 return -ENOENT;
08d7b3d1
CW		 13837 }
13838
7707e653 13839 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13840 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13841
c05422d5 13842 return 0;
08d7b3d1
CW		 13843}
13844
66a9278e 13845static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13846{
66a9278e
DV		 13847 struct drm_device *dev = encoder->base.dev;
13848 struct intel_encoder *source_encoder;
79e53945 13849 int index_mask = 0;
79e53945
JB		 13850 int entry = 0;
13851
b2784e15 13852 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13853 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13854 index_mask |= (1 << entry);
13855
79e53945
JB		 13856 entry++;
13857 }
4ef69c7a 13858
79e53945
JB		 13859 return index_mask;
13860}
13861
4d302442
CW		 13862static bool has_edp_a(struct drm_device *dev)
13863{
13864 struct drm_i915_private *dev_priv = dev->dev_private;
13865
13866 if (!IS_MOBILE(dev))
13867 return false;
13868
13869 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13870 return false;
13871
e3589908 13872 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13873 return false;
13874
13875 return true;
13876}
13877
84b4e042
JB		 13878static bool intel_crt_present(struct drm_device *dev)
13879{
13880 struct drm_i915_private *dev_priv = dev->dev_private;
13881
884497ed
DL		 13882 if (INTEL_INFO(dev)->gen >= 9)
13883 return false;
13884
cf404ce4 13885 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13886 return false;
13887
13888 if (IS_CHERRYVIEW(dev))
13889 return false;
13890
13891 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13892 return false;
13893
13894 return true;
13895}
13896
79e53945
JB		 13897static void intel_setup_outputs(struct drm_device *dev)
13898{
725e30ad 13899 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13900 struct intel_encoder *encoder;
cb0953d7 13901 bool dpd_is_edp = false;
79e53945 13902
c9093354 13903 intel_lvds_init(dev);
79e53945 13904
84b4e042 13905 if (intel_crt_present(dev))
79935fca 13906 intel_crt_init(dev);
cb0953d7 13907
c776eb2e
VK		 13908 if (IS_BROXTON(dev)) {
13909 /*
13910 * FIXME: Broxton doesn't support port detection via the
13911 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13912 * detect the ports.
13913 */
13914 intel_ddi_init(dev, PORT_A);
13915 intel_ddi_init(dev, PORT_B);
13916 intel_ddi_init(dev, PORT_C);
13917 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13918 int found;
13919
de31facd
JB		 13920 /*
13921 * Haswell uses DDI functions to detect digital outputs.
13922 * On SKL pre-D0 the strap isn't connected, so we assume
13923 * it's there.
13924 */
0e72a5b5 13925 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13926 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13927 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13928 intel_ddi_init(dev, PORT_A);
13929
13930 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13931 * register */
13932 found = I915_READ(SFUSE_STRAP);
13933
13934 if (found & SFUSE_STRAP_DDIB_DETECTED)
13935 intel_ddi_init(dev, PORT_B);
13936 if (found & SFUSE_STRAP_DDIC_DETECTED)
13937 intel_ddi_init(dev, PORT_C);
13938 if (found & SFUSE_STRAP_DDID_DETECTED)
13939 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 13940 /*
13941 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13942 */
13943 if (IS_SKYLAKE(dev) &&
13944 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13945 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13946 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13947 intel_ddi_init(dev, PORT_E);
13948
0e72a5b5 13949 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13950 int found;
5d8a7752 13951 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13952
13953 if (has_edp_a(dev))
13954 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13955
dc0fa718 13956 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13957 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13958 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13959 if (!found)
e2debe91 13960 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13961 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13962 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13963 }
13964
dc0fa718 13965 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13966 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13967
dc0fa718 13968 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13969 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13970
5eb08b69 13971 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13972 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13973
270b3042 13974 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13975 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13976 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13977 /*
13978 * The DP_DETECTED bit is the latched state of the DDC
13979 * SDA pin at boot. However since eDP doesn't require DDC
13980 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13981 * eDP ports may have been muxed to an alternate function.
13982 * Thus we can't rely on the DP_DETECTED bit alone to detect
13983 * eDP ports. Consult the VBT as well as DP_DETECTED to
13984 * detect eDP ports.
13985 */
d2182a66
VS		 13986 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13987 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13988 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13989 PORT_B);
e17ac6db
VS		 13990 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13991 intel_dp_is_edp(dev, PORT_B))
13992 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13993
d2182a66
VS		 13994 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13995 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13996 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13997 PORT_C);
e17ac6db
VS		 13998 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13999 intel_dp_is_edp(dev, PORT_C))
14000 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14001
9418c1f1 14002 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14003 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14004 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14005 PORT_D);
e17ac6db
VS		 14006 /* eDP not supported on port D, so don't check VBT */
14007 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14008 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14009 }
14010
3cfca973 14011 intel_dsi_init(dev);
09da55dc 14012 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14013 bool found = false;
7d57382e 14014
e2debe91 14015 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14016 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14017 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14018 if (!found && IS_G4X(dev)) {
b01f2c3a 14019 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14020 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14021 }
27185ae1 14022
3fec3d2f 14023 if (!found && IS_G4X(dev))
ab9d7c30 14024 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14025 }
13520b05
KH		 14026
14027 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14028
e2debe91 14029 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14030 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14031 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14032 }
27185ae1 14033
e2debe91 14034 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14035
3fec3d2f 14036 if (IS_G4X(dev)) {
b01f2c3a 14037 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14038 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14039 }
3fec3d2f 14040 if (IS_G4X(dev))
ab9d7c30 14041 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14042 }
27185ae1 14043
3fec3d2f 14044 if (IS_G4X(dev) &&
e7281eab 14045 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14046 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14047 } else if (IS_GEN2(dev))
79e53945
JB		 14048 intel_dvo_init(dev);
14049
103a196f 14050 if (SUPPORTS_TV(dev))
79e53945
JB		 14051 intel_tv_init(dev);
14052
0bc12bcb 14053 intel_psr_init(dev);
7c8f8a70 14054
b2784e15 14055 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14056 encoder->base.possible_crtcs = encoder->crtc_mask;
14057 encoder->base.possible_clones =
66a9278e 14058 intel_encoder_clones(encoder);
79e53945 14059 }
47356eb6 14060
dde86e2d 14061 intel_init_pch_refclk(dev);
270b3042
DV		 14062
14063 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14064}
14065
14066static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14067{
60a5ca01 14068 struct drm_device *dev = fb->dev;
79e53945 14069 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14070
ef2d633e 14071 drm_framebuffer_cleanup(fb);
60a5ca01 14072 mutex_lock(&dev->struct_mutex);
ef2d633e 14073 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14074 drm_gem_object_unreference(&intel_fb->obj->base);
14075 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14076 kfree(intel_fb);
14077}
14078
14079static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14080 struct drm_file *file,
79e53945
JB		 14081 unsigned int *handle)
14082{
14083 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14084 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14085
05394f39 14086 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14087}
14088
86c98588
RV		 14089static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14090 struct drm_file *file,
14091 unsigned flags, unsigned color,
14092 struct drm_clip_rect *clips,
14093 unsigned num_clips)
14094{
14095 struct drm_device *dev = fb->dev;
14096 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14097 struct drm_i915_gem_object *obj = intel_fb->obj;
14098
14099 mutex_lock(&dev->struct_mutex);
74b4ea1e 14100 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14101 mutex_unlock(&dev->struct_mutex);
14102
14103 return 0;
14104}
14105
79e53945
JB		 14106static const struct drm_framebuffer_funcs intel_fb_funcs = {
14107 .destroy = intel_user_framebuffer_destroy,
14108 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14109 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14110};
14111
b321803d
DL		 14112static
14113u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14114 uint32_t pixel_format)
14115{
14116 u32 gen = INTEL_INFO(dev)->gen;
14117
14118 if (gen >= 9) {
14119 /* "The stride in bytes must not exceed the of the size of 8K
14120 * pixels and 32K bytes."
14121 */
14122 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14123 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14124 return 32*1024;
14125 } else if (gen >= 4) {
14126 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14127 return 16*1024;
14128 else
14129 return 32*1024;
14130 } else if (gen >= 3) {
14131 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14132 return 8*1024;
14133 else
14134 return 16*1024;
14135 } else {
14136 /* XXX DSPC is limited to 4k tiled */
14137 return 8*1024;
14138 }
14139}
14140
b5ea642a
DV		 14141static int intel_framebuffer_init(struct drm_device *dev,
14142 struct intel_framebuffer *intel_fb,
14143 struct drm_mode_fb_cmd2 *mode_cmd,
14144 struct drm_i915_gem_object *obj)
79e53945 14145{
6761dd31 14146 unsigned int aligned_height;
79e53945 14147 int ret;
b321803d 14148 u32 pitch_limit, stride_alignment;
79e53945 14149
dd4916c5
DV		 14150 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14151
2a80eada
DV		 14152 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14153 /* Enforce that fb modifier and tiling mode match, but only for
14154 * X-tiled. This is needed for FBC. */
14155 if (!!(obj->tiling_mode == I915_TILING_X) !=
14156 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14157 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14158 return -EINVAL;
14159 }
14160 } else {
14161 if (obj->tiling_mode == I915_TILING_X)
14162 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14163 else if (obj->tiling_mode == I915_TILING_Y) {
14164 DRM_DEBUG("No Y tiling for legacy addfb\n");
14165 return -EINVAL;
14166 }
14167 }
14168
9a8f0a12
TU		 14169 /* Passed in modifier sanity checking. */
14170 switch (mode_cmd->modifier[0]) {
14171 case I915_FORMAT_MOD_Y_TILED:
14172 case I915_FORMAT_MOD_Yf_TILED:
14173 if (INTEL_INFO(dev)->gen < 9) {
14174 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14175 mode_cmd->modifier[0]);
14176 return -EINVAL;
14177 }
14178 case DRM_FORMAT_MOD_NONE:
14179 case I915_FORMAT_MOD_X_TILED:
14180 break;
14181 default:
c0f40428
JB		 14182 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14183 mode_cmd->modifier[0]);
57cd6508 14184 return -EINVAL;
c16ed4be 14185 }
57cd6508 14186
b321803d
DL		 14187 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14188 mode_cmd->pixel_format);
14189 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14190 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14191 mode_cmd->pitches[0], stride_alignment);
57cd6508 14192 return -EINVAL;
c16ed4be 14193 }
57cd6508 14194
b321803d
DL		 14195 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14196 mode_cmd->pixel_format);
a35cdaa0 14197 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14198 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14199 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14200 "tiled" : "linear",
a35cdaa0 14201 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14202 return -EINVAL;
c16ed4be 14203 }
5d7bd705 14204
2a80eada 14205 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14206 mode_cmd->pitches[0] != obj->stride) {
14207 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14208 mode_cmd->pitches[0], obj->stride);
5d7bd705 14209 return -EINVAL;
c16ed4be 14210 }
5d7bd705 14211
57779d06 14212 /* Reject formats not supported by any plane early. */
308e5bcb 14213 switch (mode_cmd->pixel_format) {
57779d06 14214 case DRM_FORMAT_C8:
04b3924d
VS		 14215 case DRM_FORMAT_RGB565:
14216 case DRM_FORMAT_XRGB8888:
14217 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14218 break;
14219 case DRM_FORMAT_XRGB1555:
c16ed4be 14220 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14221 DRM_DEBUG("unsupported pixel format: %s\n",
14222 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14223 return -EINVAL;
c16ed4be 14224 }
57779d06 14225 break;
57779d06 14226 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14227 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14228 DRM_DEBUG("unsupported pixel format: %s\n",
14229 drm_get_format_name(mode_cmd->pixel_format));
14230 return -EINVAL;
14231 }
14232 break;
14233 case DRM_FORMAT_XBGR8888:
04b3924d 14234 case DRM_FORMAT_XRGB2101010:
57779d06 14235 case DRM_FORMAT_XBGR2101010:
c16ed4be 14236 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14237 DRM_DEBUG("unsupported pixel format: %s\n",
14238 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14239 return -EINVAL;
c16ed4be 14240 }
b5626747 14241 break;
7531208b
DL		 14242 case DRM_FORMAT_ABGR2101010:
14243 if (!IS_VALLEYVIEW(dev)) {
14244 DRM_DEBUG("unsupported pixel format: %s\n",
14245 drm_get_format_name(mode_cmd->pixel_format));
14246 return -EINVAL;
14247 }
14248 break;
04b3924d
VS		 14249 case DRM_FORMAT_YUYV:
14250 case DRM_FORMAT_UYVY:
14251 case DRM_FORMAT_YVYU:
14252 case DRM_FORMAT_VYUY:
c16ed4be 14253 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14254 DRM_DEBUG("unsupported pixel format: %s\n",
14255 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14256 return -EINVAL;
c16ed4be 14257 }
57cd6508
CW		 14258 break;
14259 default:
4ee62c76
VS		 14260 DRM_DEBUG("unsupported pixel format: %s\n",
14261 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14262 return -EINVAL;
14263 }
14264
90f9a336
VS		 14265 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14266 if (mode_cmd->offsets[0] != 0)
14267 return -EINVAL;
14268
ec2c981e 14269 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14270 mode_cmd->pixel_format,
14271 mode_cmd->modifier[0]);
53155c0a
DV		 14272 /* FIXME drm helper for size checks (especially planar formats)? */
14273 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14274 return -EINVAL;
14275
c7d73f6a
DV		 14276 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14277 intel_fb->obj = obj;
80075d49 14278 intel_fb->obj->framebuffer_references++;
c7d73f6a 14279
79e53945
JB		 14280 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14281 if (ret) {
14282 DRM_ERROR("framebuffer init failed %d\n", ret);
14283 return ret;
14284 }
14285
79e53945
JB		 14286 return 0;
14287}
14288
79e53945
JB		 14289static struct drm_framebuffer *
14290intel_user_framebuffer_create(struct drm_device *dev,
14291 struct drm_file *filp,
308e5bcb 14292 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14293{
05394f39 14294 struct drm_i915_gem_object *obj;
79e53945 14295
308e5bcb
JB		 14296 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14297 mode_cmd->handles[0]));
c8725226 14298 if (&obj->base == NULL)
cce13ff7 14299 return ERR_PTR(-ENOENT);
79e53945 14300
d2dff872 14301 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14302}
14303
0695726e 14304#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14305static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14306{
14307}
14308#endif
14309
79e53945 14310static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14311 .fb_create = intel_user_framebuffer_create,
0632fef6 14312 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14313 .atomic_check = intel_atomic_check,
14314 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14315 .atomic_state_alloc = intel_atomic_state_alloc,
14316 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14317};
14318
e70236a8
JB		 14319/* Set up chip specific display functions */
14320static void intel_init_display(struct drm_device *dev)
14321{
14322 struct drm_i915_private *dev_priv = dev->dev_private;
14323
ee9300bb
DV		 14324 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14325 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14326 else if (IS_CHERRYVIEW(dev))
14327 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14328 else if (IS_VALLEYVIEW(dev))
14329 dev_priv->display.find_dpll = vlv_find_best_dpll;
14330 else if (IS_PINEVIEW(dev))
14331 dev_priv->display.find_dpll = pnv_find_best_dpll;
14332 else
14333 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14334
bc8d7dff
DL		 14335 if (INTEL_INFO(dev)->gen >= 9) {
14336 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14337 dev_priv->display.get_initial_plane_config =
14338 skylake_get_initial_plane_config;
bc8d7dff
DL		 14339 dev_priv->display.crtc_compute_clock =
14340 haswell_crtc_compute_clock;
14341 dev_priv->display.crtc_enable = haswell_crtc_enable;
14342 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14343 dev_priv->display.update_primary_plane =
14344 skylake_update_primary_plane;
14345 } else if (HAS_DDI(dev)) {
0e8ffe1b 14346 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14347 dev_priv->display.get_initial_plane_config =
14348 ironlake_get_initial_plane_config;
797d0259
ACO		 14349 dev_priv->display.crtc_compute_clock =
14350 haswell_crtc_compute_clock;
4f771f10
PZ		 14351 dev_priv->display.crtc_enable = haswell_crtc_enable;
14352 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14353 dev_priv->display.update_primary_plane =
14354 ironlake_update_primary_plane;
09b4ddf9 14355 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14356 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14357 dev_priv->display.get_initial_plane_config =
14358 ironlake_get_initial_plane_config;
3fb37703
ACO		 14359 dev_priv->display.crtc_compute_clock =
14360 ironlake_crtc_compute_clock;
76e5a89c
DV		 14361 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14362 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14363 dev_priv->display.update_primary_plane =
14364 ironlake_update_primary_plane;
89b667f8
JB		 14365 } else if (IS_VALLEYVIEW(dev)) {
14366 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14367 dev_priv->display.get_initial_plane_config =
14368 i9xx_get_initial_plane_config;
d6dfee7a 14369 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14370 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14371 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14372 dev_priv->display.update_primary_plane =
14373 i9xx_update_primary_plane;
f564048e 14374 } else {
0e8ffe1b 14375 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14376 dev_priv->display.get_initial_plane_config =
14377 i9xx_get_initial_plane_config;
d6dfee7a 14378 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14379 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14380 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14381 dev_priv->display.update_primary_plane =
14382 i9xx_update_primary_plane;
f564048e 14383 }
e70236a8 14384
e70236a8 14385 /* Returns the core display clock speed */
1652d19e
VS		 14386 if (IS_SKYLAKE(dev))
14387 dev_priv->display.get_display_clock_speed =
14388 skylake_get_display_clock_speed;
acd3f3d3
BP		 14389 else if (IS_BROXTON(dev))
14390 dev_priv->display.get_display_clock_speed =
14391 broxton_get_display_clock_speed;
1652d19e
VS		 14392 else if (IS_BROADWELL(dev))
14393 dev_priv->display.get_display_clock_speed =
14394 broadwell_get_display_clock_speed;
14395 else if (IS_HASWELL(dev))
14396 dev_priv->display.get_display_clock_speed =
14397 haswell_get_display_clock_speed;
14398 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14399 dev_priv->display.get_display_clock_speed =
14400 valleyview_get_display_clock_speed;
b37a6434
VS		 14401 else if (IS_GEN5(dev))
14402 dev_priv->display.get_display_clock_speed =
14403 ilk_get_display_clock_speed;
a7c66cd8 14404 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14405 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14406 dev_priv->display.get_display_clock_speed =
14407 i945_get_display_clock_speed;
34edce2f
VS		 14408 else if (IS_GM45(dev))
14409 dev_priv->display.get_display_clock_speed =
14410 gm45_get_display_clock_speed;
14411 else if (IS_CRESTLINE(dev))
14412 dev_priv->display.get_display_clock_speed =
14413 i965gm_get_display_clock_speed;
14414 else if (IS_PINEVIEW(dev))
14415 dev_priv->display.get_display_clock_speed =
14416 pnv_get_display_clock_speed;
14417 else if (IS_G33(dev) || IS_G4X(dev))
14418 dev_priv->display.get_display_clock_speed =
14419 g33_get_display_clock_speed;
e70236a8
JB		 14420 else if (IS_I915G(dev))
14421 dev_priv->display.get_display_clock_speed =
14422 i915_get_display_clock_speed;
257a7ffc 14423 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14424 dev_priv->display.get_display_clock_speed =
14425 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14426 else if (IS_PINEVIEW(dev))
14427 dev_priv->display.get_display_clock_speed =
14428 pnv_get_display_clock_speed;
e70236a8
JB		 14429 else if (IS_I915GM(dev))
14430 dev_priv->display.get_display_clock_speed =
14431 i915gm_get_display_clock_speed;
14432 else if (IS_I865G(dev))
14433 dev_priv->display.get_display_clock_speed =
14434 i865_get_display_clock_speed;
f0f8a9ce 14435 else if (IS_I85X(dev))
e70236a8 14436 dev_priv->display.get_display_clock_speed =
1b1d2716 14437 i85x_get_display_clock_speed;
623e01e5
VS		 14438 else { /* 830 */
14439 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14440 dev_priv->display.get_display_clock_speed =
14441 i830_get_display_clock_speed;
623e01e5 14442 }
e70236a8 14443
7c10a2b5 14444 if (IS_GEN5(dev)) {
3bb11b53 14445 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14446 } else if (IS_GEN6(dev)) {
14447 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14448 } else if (IS_IVYBRIDGE(dev)) {
14449 /* FIXME: detect B0+ stepping and use auto training */
14450 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14451 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14452 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14453 if (IS_BROADWELL(dev)) {
14454 dev_priv->display.modeset_commit_cdclk =
14455 broadwell_modeset_commit_cdclk;
14456 dev_priv->display.modeset_calc_cdclk =
14457 broadwell_modeset_calc_cdclk;
14458 }
30a970c6 14459 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14460 dev_priv->display.modeset_commit_cdclk =
14461 valleyview_modeset_commit_cdclk;
14462 dev_priv->display.modeset_calc_cdclk =
14463 valleyview_modeset_calc_cdclk;
f8437dd1 14464 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14465 dev_priv->display.modeset_commit_cdclk =
14466 broxton_modeset_commit_cdclk;
14467 dev_priv->display.modeset_calc_cdclk =
14468 broxton_modeset_calc_cdclk;
e70236a8 14469 }
8c9f3aaf 14470
8c9f3aaf
JB		 14471 switch (INTEL_INFO(dev)->gen) {
14472 case 2:
14473 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14474 break;
14475
14476 case 3:
14477 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14478 break;
14479
14480 case 4:
14481 case 5:
14482 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14483 break;
14484
14485 case 6:
14486 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14487 break;
7c9017e5 14488 case 7:
4e0bbc31 14489 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14490 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14491 break;
830c81db 14492 case 9:
ba343e02
TU		 14493 /* Drop through - unsupported since execlist only. */
14494 default:
14495 /* Default just returns -ENODEV to indicate unsupported */
14496 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14497 }
7bd688cd
JN		 14498
14499 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14500
14501 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14502}
14503
b690e96c
JB		 14504/*
14505 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14506 * resume, or other times. This quirk makes sure that's the case for
14507 * affected systems.
14508 */
0206e353 14509static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14510{
14511 struct drm_i915_private *dev_priv = dev->dev_private;
14512
14513 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14514 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14515}
14516
b6b5d049
VS		 14517static void quirk_pipeb_force(struct drm_device *dev)
14518{
14519 struct drm_i915_private *dev_priv = dev->dev_private;
14520
14521 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14522 DRM_INFO("applying pipe b force quirk\n");
14523}
14524
435793df
KP		 14525/*
14526 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14527 */
14528static void quirk_ssc_force_disable(struct drm_device *dev)
14529{
14530 struct drm_i915_private *dev_priv = dev->dev_private;
14531 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14532 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14533}
14534
4dca20ef 14535/*
5a15ab5b
CE		 14536 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14537 * brightness value
4dca20ef
CE		 14538 */
14539static void quirk_invert_brightness(struct drm_device *dev)
14540{
14541 struct drm_i915_private *dev_priv = dev->dev_private;
14542 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14543 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14544}
14545
9c72cc6f
SD		 14546/* Some VBT's incorrectly indicate no backlight is present */
14547static void quirk_backlight_present(struct drm_device *dev)
14548{
14549 struct drm_i915_private *dev_priv = dev->dev_private;
14550 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14551 DRM_INFO("applying backlight present quirk\n");
14552}
14553
b690e96c
JB		 14554struct intel_quirk {
14555 int device;
14556 int subsystem_vendor;
14557 int subsystem_device;
14558 void (*hook)(struct drm_device *dev);
14559};
14560
5f85f176
EE		 14561/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14562struct intel_dmi_quirk {
14563 void (*hook)(struct drm_device *dev);
14564 const struct dmi_system_id (*dmi_id_list)[];
14565};
14566
14567static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14568{
14569 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14570 return 1;
14571}
14572
14573static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14574 {
14575 .dmi_id_list = &(const struct dmi_system_id[]) {
14576 {
14577 .callback = intel_dmi_reverse_brightness,
14578 .ident = "NCR Corporation",
14579 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14580 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14581 },
14582 },
14583 { } /* terminating entry */
14584 },
14585 .hook = quirk_invert_brightness,
14586 },
14587};
14588
c43b5634 14589static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14590 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14591 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14592
b690e96c
JB		 14593 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14594 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14595
5f080c0f
VS		 14596 /* 830 needs to leave pipe A & dpll A up */
14597 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14598
b6b5d049
VS		 14599 /* 830 needs to leave pipe B & dpll B up */
14600 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14601
435793df
KP		 14602 /* Lenovo U160 cannot use SSC on LVDS */
14603 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14604
14605 /* Sony Vaio Y cannot use SSC on LVDS */
14606 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14607
be505f64
AH		 14608 /* Acer Aspire 5734Z must invert backlight brightness */
14609 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14610
14611 /* Acer/eMachines G725 */
14612 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14613
14614 /* Acer/eMachines e725 */
14615 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14616
14617 /* Acer/Packard Bell NCL20 */
14618 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14619
14620 /* Acer Aspire 4736Z */
14621 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14622
14623 /* Acer Aspire 5336 */
14624 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14625
14626 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14627 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14628
dfb3d47b
SD		 14629 /* Acer C720 Chromebook (Core i3 4005U) */
14630 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14631
b2a9601c 14632 /* Apple Macbook 2,1 (Core 2 T7400) */
14633 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14634
d4967d8c
SD		 14635 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14636 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14637
14638 /* HP Chromebook 14 (Celeron 2955U) */
14639 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14640
14641 /* Dell Chromebook 11 */
14642 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14643};
14644
14645static void intel_init_quirks(struct drm_device *dev)
14646{
14647 struct pci_dev *d = dev->pdev;
14648 int i;
14649
14650 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14651 struct intel_quirk *q = &intel_quirks[i];
14652
14653 if (d->device == q->device &&
14654 (d->subsystem_vendor == q->subsystem_vendor ||
14655 q->subsystem_vendor == PCI_ANY_ID) &&
14656 (d->subsystem_device == q->subsystem_device ||
14657 q->subsystem_device == PCI_ANY_ID))
14658 q->hook(dev);
14659 }
5f85f176
EE		 14660 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14661 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14662 intel_dmi_quirks[i].hook(dev);
14663 }
b690e96c
JB		 14664}
14665
9cce37f4
JB		 14666/* Disable the VGA plane that we never use */
14667static void i915_disable_vga(struct drm_device *dev)
14668{
14669 struct drm_i915_private *dev_priv = dev->dev_private;
14670 u8 sr1;
766aa1c4 14671 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14672
2b37c616 14673 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14674 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14675 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14676 sr1 = inb(VGA_SR_DATA);
14677 outb(sr1 | 1<<5, VGA_SR_DATA);
14678 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14679 udelay(300);
14680
01f5a626 14681 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14682 POSTING_READ(vga_reg);
14683}
14684
f817586c
DV		 14685void intel_modeset_init_hw(struct drm_device *dev)
14686{
b6283055 14687 intel_update_cdclk(dev);
a8f78b58 14688 intel_prepare_ddi(dev);
f817586c 14689 intel_init_clock_gating(dev);
8090c6b9 14690 intel_enable_gt_powersave(dev);
f817586c
DV		 14691}
14692
79e53945
JB		 14693void intel_modeset_init(struct drm_device *dev)
14694{
652c393a 14695 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14696 int sprite, ret;
8cc87b75 14697 enum pipe pipe;
46f297fb 14698 struct intel_crtc *crtc;
79e53945
JB		 14699
14700 drm_mode_config_init(dev);
14701
14702 dev->mode_config.min_width = 0;
14703 dev->mode_config.min_height = 0;
14704
019d96cb
DA		 14705 dev->mode_config.preferred_depth = 24;
14706 dev->mode_config.prefer_shadow = 1;
14707
25bab385
TU		 14708 dev->mode_config.allow_fb_modifiers = true;
14709
e6ecefaa 14710 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14711
b690e96c
JB		 14712 intel_init_quirks(dev);
14713
1fa61106
ED		 14714 intel_init_pm(dev);
14715
e3c74757
BW		 14716 if (INTEL_INFO(dev)->num_pipes == 0)
14717 return;
14718
69f92f67
LW		 14719 /*
14720 * There may be no VBT; and if the BIOS enabled SSC we can
14721 * just keep using it to avoid unnecessary flicker. Whereas if the
14722 * BIOS isn't using it, don't assume it will work even if the VBT
14723 * indicates as much.
14724 */
14725 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14726 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14727 DREF_SSC1_ENABLE);
14728
14729 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14730 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14731 bios_lvds_use_ssc ? "en" : "dis",
14732 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14733 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14734 }
14735 }
14736
e70236a8 14737 intel_init_display(dev);
7c10a2b5 14738 intel_init_audio(dev);
e70236a8 14739
a6c45cf0
CW		 14740 if (IS_GEN2(dev)) {
14741 dev->mode_config.max_width = 2048;
14742 dev->mode_config.max_height = 2048;
14743 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14744 dev->mode_config.max_width = 4096;
14745 dev->mode_config.max_height = 4096;
79e53945 14746 } else {
a6c45cf0
CW		 14747 dev->mode_config.max_width = 8192;
14748 dev->mode_config.max_height = 8192;
79e53945 14749 }
068be561 14750
dc41c154
VS		 14751 if (IS_845G(dev) || IS_I865G(dev)) {
14752 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14753 dev->mode_config.cursor_height = 1023;
14754 } else if (IS_GEN2(dev)) {
068be561
DL		 14755 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14756 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14757 } else {
14758 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14759 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14760 }
14761
5d4545ae 14762 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14763
28c97730 14764 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14765 INTEL_INFO(dev)->num_pipes,
14766 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14767
055e393f 14768 for_each_pipe(dev_priv, pipe) {
8cc87b75 14769 intel_crtc_init(dev, pipe);
3bdcfc0c 14770 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14771 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14772 if (ret)
06da8da2 14773 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14774 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14775 }
79e53945
JB		 14776 }
14777
e72f9fbf 14778 intel_shared_dpll_init(dev);
ee7b9f93 14779
9cce37f4
JB		 14780 /* Just disable it once at startup */
14781 i915_disable_vga(dev);
79e53945 14782 intel_setup_outputs(dev);
11be49eb
CW		 14783
14784 /* Just in case the BIOS is doing something questionable. */
7733b49b 14785 intel_fbc_disable(dev_priv);
fa9fa083 14786
6e9f798d 14787 drm_modeset_lock_all(dev);
043e9bda 14788 intel_modeset_setup_hw_state(dev);
6e9f798d 14789 drm_modeset_unlock_all(dev);
46f297fb 14790
d3fcc808 14791 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14792 struct intel_initial_plane_config plane_config = {};
14793
46f297fb
JB		 14794 if (!crtc->active)
14795 continue;
14796
46f297fb 14797 /*
46f297fb
JB		 14798 * Note that reserving the BIOS fb up front prevents us
14799 * from stuffing other stolen allocations like the ring
14800 * on top. This prevents some ugliness at boot time, and
14801 * can even allow for smooth boot transitions if the BIOS
14802 * fb is large enough for the active pipe configuration.
14803 */
eeebeac5
ML		 14804 dev_priv->display.get_initial_plane_config(crtc,
14805 &plane_config);
14806
14807 /*
14808 * If the fb is shared between multiple heads, we'll
14809 * just get the first one.
14810 */
14811 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14812 }
2c7111db
CW		 14813}
14814
7fad798e
DV		 14815static void intel_enable_pipe_a(struct drm_device *dev)
14816{
14817 struct intel_connector *connector;
14818 struct drm_connector *crt = NULL;
14819 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14820 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14821
14822 /* We can't just switch on the pipe A, we need to set things up with a
14823 * proper mode and output configuration. As a gross hack, enable pipe A
14824 * by enabling the load detect pipe once. */
3a3371ff 14825 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14826 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14827 crt = &connector->base;
14828 break;
14829 }
14830 }
14831
14832 if (!crt)
14833 return;
14834
208bf9fd 14835 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14836 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14837}
14838
fa555837
DV		 14839static bool
14840intel_check_plane_mapping(struct intel_crtc *crtc)
14841{
7eb552ae
BW		 14842 struct drm_device *dev = crtc->base.dev;
14843 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14844 u32 reg, val;
14845
7eb552ae 14846 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14847 return true;
14848
14849 reg = DSPCNTR(!crtc->plane);
14850 val = I915_READ(reg);
14851
14852 if ((val & DISPLAY_PLANE_ENABLE) &&
14853 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14854 return false;
14855
14856 return true;
14857}
14858
02e93c35
VS		 14859static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14860{
14861 struct drm_device *dev = crtc->base.dev;
14862 struct intel_encoder *encoder;
14863
14864 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14865 return true;
14866
14867 return false;
14868}
14869
24929352
DV		 14870static void intel_sanitize_crtc(struct intel_crtc *crtc)
14871{
14872 struct drm_device *dev = crtc->base.dev;
14873 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14874 u32 reg;
24929352 14875
24929352 14876 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14877 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14878 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14879
d3eaf884 14880 /* restore vblank interrupts to correct state */
9625604c 14881 drm_crtc_vblank_reset(&crtc->base);
d297e103 14882 if (crtc->active) {
3a03dfb0 14883 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14884 update_scanline_offset(crtc);
9625604c
DV		 14885 drm_crtc_vblank_on(&crtc->base);
14886 }
d3eaf884 14887
24929352 14888 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14889 * disable the crtc (and hence change the state) if it is wrong. Note
14890 * that gen4+ has a fixed plane -> pipe mapping. */
14891 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14892 bool plane;
14893
24929352
DV		 14894 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14895 crtc->base.base.id);
14896
14897 /* Pipe has the wrong plane attached and the plane is active.
14898 * Temporarily change the plane mapping and disable everything
14899 * ... */
14900 plane = crtc->plane;
b70709a6 14901 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14902 crtc->plane = !plane;
b17d48e2 14903 intel_crtc_disable_noatomic(&crtc->base);
24929352 14904 crtc->plane = plane;
24929352 14905 }
24929352 14906
7fad798e
DV		 14907 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14908 crtc->pipe == PIPE_A && !crtc->active) {
14909 /* BIOS forgot to enable pipe A, this mostly happens after
14910 * resume. Force-enable the pipe to fix this, the update_dpms
14911 * call below we restore the pipe to the right state, but leave
14912 * the required bits on. */
14913 intel_enable_pipe_a(dev);
14914 }
14915
24929352
DV		 14916 /* Adjust the state of the output pipe according to whether we
14917 * have active connectors/encoders. */
02e93c35 14918 if (!intel_crtc_has_encoders(crtc))
b17d48e2 14919 intel_crtc_disable_noatomic(&crtc->base);
24929352 14920
53d9f4e9 14921 if (crtc->active != crtc->base.state->active) {
02e93c35 14922 struct intel_encoder *encoder;
24929352
DV		 14923
14924 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14925 * functions or because of calls to intel_crtc_disable_noatomic,
14926 * or because the pipe is force-enabled due to the
24929352
DV		 14927 * pipe A quirk. */
14928 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14929 crtc->base.base.id,
83d65738 14930 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14931 crtc->active ? "enabled" : "disabled");
14932
4be40c98 14933 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14934 crtc->base.state->active = crtc->active;
24929352
DV		 14935 crtc->base.enabled = crtc->active;
14936
14937 /* Because we only establish the connector -> encoder ->
14938 * crtc links if something is active, this means the
14939 * crtc is now deactivated. Break the links. connector
14940 * -> encoder links are only establish when things are
14941 * actually up, hence no need to break them. */
14942 WARN_ON(crtc->active);
14943
2d406bb0 14944 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14945 encoder->base.crtc = NULL;
24929352 14946 }
c5ab3bc0 14947
a3ed6aad 14948 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14949 /*
14950 * We start out with underrun reporting disabled to avoid races.
14951 * For correct bookkeeping mark this on active crtcs.
14952 *
c5ab3bc0
DV		 14953 * Also on gmch platforms we dont have any hardware bits to
14954 * disable the underrun reporting. Which means we need to start
14955 * out with underrun reporting disabled also on inactive pipes,
14956 * since otherwise we'll complain about the garbage we read when
14957 * e.g. coming up after runtime pm.
14958 *
4cc31489
DV		 14959 * No protection against concurrent access is required - at
14960 * worst a fifo underrun happens which also sets this to false.
14961 */
14962 crtc->cpu_fifo_underrun_disabled = true;
14963 crtc->pch_fifo_underrun_disabled = true;
14964 }
24929352
DV		 14965}
14966
14967static void intel_sanitize_encoder(struct intel_encoder *encoder)
14968{
14969 struct intel_connector *connector;
14970 struct drm_device *dev = encoder->base.dev;
873ffe69 14971 bool active = false;
24929352
DV		 14972
14973 /* We need to check both for a crtc link (meaning that the
14974 * encoder is active and trying to read from a pipe) and the
14975 * pipe itself being active. */
14976 bool has_active_crtc = encoder->base.crtc &&
14977 to_intel_crtc(encoder->base.crtc)->active;
14978
873ffe69
ML		 14979 for_each_intel_connector(dev, connector) {
14980 if (connector->base.encoder != &encoder->base)
14981 continue;
14982
14983 active = true;
14984 break;
14985 }
14986
14987 if (active && !has_active_crtc) {
24929352
DV		 14988 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14989 encoder->base.base.id,
8e329a03 14990 encoder->base.name);
24929352
DV		 14991
14992 /* Connector is active, but has no active pipe. This is
14993 * fallout from our resume register restoring. Disable
14994 * the encoder manually again. */
14995 if (encoder->base.crtc) {
14996 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14997 encoder->base.base.id,
8e329a03 14998 encoder->base.name);
24929352 14999 encoder->disable(encoder);
a62d1497
VS		 15000 if (encoder->post_disable)
15001 encoder->post_disable(encoder);
24929352 15002 }
7f1950fb 15003 encoder->base.crtc = NULL;
24929352
DV		 15004
15005 /* Inconsistent output/port/pipe state happens presumably due to
15006 * a bug in one of the get_hw_state functions. Or someplace else
15007 * in our code, like the register restore mess on resume. Clamp
15008 * things to off as a safer default. */
3a3371ff 15009 for_each_intel_connector(dev, connector) {
24929352
DV		 15010 if (connector->encoder != encoder)
15011 continue;
7f1950fb
EE		 15012 connector->base.dpms = DRM_MODE_DPMS_OFF;
15013 connector->base.encoder = NULL;
24929352
DV		 15014 }
15015 }
15016 /* Enabled encoders without active connectors will be fixed in
15017 * the crtc fixup. */
15018}
15019
04098753 15020void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15021{
15022 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15023 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15024
04098753
ID		 15025 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15026 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15027 i915_disable_vga(dev);
15028 }
15029}
15030
15031void i915_redisable_vga(struct drm_device *dev)
15032{
15033 struct drm_i915_private *dev_priv = dev->dev_private;
15034
8dc8a27c
PZ		 15035 /* This function can be called both from intel_modeset_setup_hw_state or
15036 * at a very early point in our resume sequence, where the power well
15037 * structures are not yet restored. Since this function is at a very
15038 * paranoid "someone might have enabled VGA while we were not looking"
15039 * level, just check if the power well is enabled instead of trying to
15040 * follow the "don't touch the power well if we don't need it" policy
15041 * the rest of the driver uses. */
f458ebbc 15042 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15043 return;
15044
04098753 15045 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15046}
15047
98ec7739
VS		 15048static bool primary_get_hw_state(struct intel_crtc *crtc)
15049{
15050 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15051
d032ffa0
ML		 15052 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15053}
15054
15055static void readout_plane_state(struct intel_crtc *crtc,
15056 struct intel_crtc_state *crtc_state)
15057{
15058 struct intel_plane *p;
4cf0ebbd 15059 struct intel_plane_state *plane_state;
d032ffa0
ML		 15060 bool active = crtc_state->base.active;
15061
d032ffa0 15062 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15063 if (crtc->pipe != p->pipe)
15064 continue;
15065
4cf0ebbd 15066 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15067
4cf0ebbd
ML		 15068 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15069 plane_state->visible = primary_get_hw_state(crtc);
15070 else {
15071 if (active)
15072 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15073
4cf0ebbd 15074 plane_state->visible = false;
d032ffa0
ML		 15075 }
15076 }
98ec7739
VS		 15077}
15078
30e984df 15079static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15080{
15081 struct drm_i915_private *dev_priv = dev->dev_private;
15082 enum pipe pipe;
24929352
DV		 15083 struct intel_crtc *crtc;
15084 struct intel_encoder *encoder;
15085 struct intel_connector *connector;
5358901f 15086 int i;
24929352 15087
d3fcc808 15088 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15089 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15090 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15091 crtc->config->base.crtc = &crtc->base;
3b117c8f 15092
0e8ffe1b 15093 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15094 crtc->config);
24929352 15095
49d6fa21 15096 crtc->base.state->active = crtc->active;
24929352 15097 crtc->base.enabled = crtc->active;
b70709a6 15098
5c1e3426
ML		 15099 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15100 if (crtc->base.state->active) {
15101 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15102 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15103 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15104
15105 /*
15106 * The initial mode needs to be set in order to keep
15107 * the atomic core happy. It wants a valid mode if the
15108 * crtc's enabled, so we do the above call.
15109 *
15110 * At this point some state updated by the connectors
15111 * in their ->detect() callback has not run yet, so
15112 * no recalculation can be done yet.
15113 *
15114 * Even if we could do a recalculation and modeset
15115 * right now it would cause a double modeset if
15116 * fbdev or userspace chooses a different initial mode.
15117 *
5c1e3426
ML		 15118 * If that happens, someone indicated they wanted a
15119 * mode change, which means it's safe to do a full
15120 * recalculation.
15121 */
1ed51de9 15122 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15123 }
15124
15125 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15126 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15127
15128 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15129 crtc->base.base.id,
15130 crtc->active ? "enabled" : "disabled");
15131 }
15132
5358901f
DV		 15133 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15134 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15135
3e369b76
ACO		 15136 pll->on = pll->get_hw_state(dev_priv, pll,
15137 &pll->config.hw_state);
5358901f 15138 pll->active = 0;
3e369b76 15139 pll->config.crtc_mask = 0;
d3fcc808 15140 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15141 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15142 pll->active++;
3e369b76 15143 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15144 }
5358901f 15145 }
5358901f 15146
1e6f2ddc 15147 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15148 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15149
3e369b76 15150 if (pll->config.crtc_mask)
bd2bb1b9 15151 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15152 }
15153
b2784e15 15154 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15155 pipe = 0;
15156
15157 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15158 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15159 encoder->base.crtc = &crtc->base;
6e3c9717 15160 encoder->get_config(encoder, crtc->config);
24929352
DV		 15161 } else {
15162 encoder->base.crtc = NULL;
15163 }
15164
6f2bcceb 15165 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15166 encoder->base.base.id,
8e329a03 15167 encoder->base.name,
24929352 15168 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15169 pipe_name(pipe));
24929352
DV		 15170 }
15171
3a3371ff 15172 for_each_intel_connector(dev, connector) {
24929352
DV		 15173 if (connector->get_hw_state(connector)) {
15174 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15175 connector->base.encoder = &connector->encoder->base;
15176 } else {
15177 connector->base.dpms = DRM_MODE_DPMS_OFF;
15178 connector->base.encoder = NULL;
15179 }
15180 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15181 connector->base.base.id,
c23cc417 15182 connector->base.name,
24929352
DV		 15183 connector->base.encoder ? "enabled" : "disabled");
15184 }
30e984df
DV		 15185}
15186
043e9bda
ML		 15187/* Scan out the current hw modeset state,
15188 * and sanitizes it to the current state
15189 */
15190static void
15191intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15192{
15193 struct drm_i915_private *dev_priv = dev->dev_private;
15194 enum pipe pipe;
30e984df
DV		 15195 struct intel_crtc *crtc;
15196 struct intel_encoder *encoder;
35c95375 15197 int i;
30e984df
DV		 15198
15199 intel_modeset_readout_hw_state(dev);
24929352
DV		 15200
15201 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15202 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15203 intel_sanitize_encoder(encoder);
15204 }
15205
055e393f 15206 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15207 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15208 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15209 intel_dump_pipe_config(crtc, crtc->config,
15210 "[setup_hw_state]");
24929352 15211 }
9a935856 15212
d29b2f9d
ACO		 15213 intel_modeset_update_connector_atomic_state(dev);
15214
35c95375
DV		 15215 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15216 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15217
15218 if (!pll->on || pll->active)
15219 continue;
15220
15221 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15222
15223 pll->disable(dev_priv, pll);
15224 pll->on = false;
15225 }
15226
26e1fe4f 15227 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15228 vlv_wm_get_hw_state(dev);
15229 else if (IS_GEN9(dev))
3078999f
PB		 15230 skl_wm_get_hw_state(dev);
15231 else if (HAS_PCH_SPLIT(dev))
243e6a44 15232 ilk_wm_get_hw_state(dev);
292b990e
ML		 15233
15234 for_each_intel_crtc(dev, crtc) {
15235 unsigned long put_domains;
15236
15237 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15238 if (WARN_ON(put_domains))
15239 modeset_put_power_domains(dev_priv, put_domains);
15240 }
15241 intel_display_set_init_power(dev_priv, false);
043e9bda 15242}
7d0bc1ea 15243
043e9bda
ML		 15244void intel_display_resume(struct drm_device *dev)
15245{
15246 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15247 struct intel_connector *conn;
15248 struct intel_plane *plane;
15249 struct drm_crtc *crtc;
15250 int ret;
f30da187 15251
043e9bda
ML		 15252 if (!state)
15253 return;
15254
15255 state->acquire_ctx = dev->mode_config.acquire_ctx;
15256
15257 /* preserve complete old state, including dpll */
15258 intel_atomic_get_shared_dpll_state(state);
15259
15260 for_each_crtc(dev, crtc) {
15261 struct drm_crtc_state *crtc_state =
15262 drm_atomic_get_crtc_state(state, crtc);
15263
15264 ret = PTR_ERR_OR_ZERO(crtc_state);
15265 if (ret)
15266 goto err;
15267
15268 /* force a restore */
15269 crtc_state->mode_changed = true;
45e2b5f6 15270 }
8af6cf88 15271
043e9bda
ML		 15272 for_each_intel_plane(dev, plane) {
15273 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15274 if (ret)
15275 goto err;
15276 }
15277
15278 for_each_intel_connector(dev, conn) {
15279 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15280 if (ret)
15281 goto err;
15282 }
15283
15284 intel_modeset_setup_hw_state(dev);
15285
15286 i915_redisable_vga(dev);
74c090b1 15287 ret = drm_atomic_commit(state);
043e9bda
ML		 15288 if (!ret)
15289 return;
15290
15291err:
15292 DRM_ERROR("Restoring old state failed with %i\n", ret);
15293 drm_atomic_state_free(state);
2c7111db
CW		 15294}
15295
15296void intel_modeset_gem_init(struct drm_device *dev)
15297{
484b41dd 15298 struct drm_crtc *c;
2ff8fde1 15299 struct drm_i915_gem_object *obj;
e0d6149b 15300 int ret;
484b41dd 15301
ae48434c
ID		 15302 mutex_lock(&dev->struct_mutex);
15303 intel_init_gt_powersave(dev);
15304 mutex_unlock(&dev->struct_mutex);
15305
1833b134 15306 intel_modeset_init_hw(dev);
02e792fb
DV		 15307
15308 intel_setup_overlay(dev);
484b41dd
JB		 15309
15310 /*
15311 * Make sure any fbs we allocated at startup are properly
15312 * pinned & fenced. When we do the allocation it's too early
15313 * for this.
15314 */
70e1e0ec 15315 for_each_crtc(dev, c) {
2ff8fde1
MR		 15316 obj = intel_fb_obj(c->primary->fb);
15317 if (obj == NULL)
484b41dd
JB		 15318 continue;
15319
e0d6149b
TU		 15320 mutex_lock(&dev->struct_mutex);
15321 ret = intel_pin_and_fence_fb_obj(c->primary,
15322 c->primary->fb,
15323 c->primary->state,
91af127f 15324 NULL, NULL);
e0d6149b
TU		 15325 mutex_unlock(&dev->struct_mutex);
15326 if (ret) {
484b41dd
JB		 15327 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15328 to_intel_crtc(c)->pipe);
66e514c1
DA		 15329 drm_framebuffer_unreference(c->primary->fb);
15330 c->primary->fb = NULL;
36750f28 15331 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15332 update_state_fb(c->primary);
36750f28 15333 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15334 }
15335 }
0962c3c9
VS		 15336
15337 intel_backlight_register(dev);
79e53945
JB		 15338}
15339
4932e2c3
ID		 15340void intel_connector_unregister(struct intel_connector *intel_connector)
15341{
15342 struct drm_connector *connector = &intel_connector->base;
15343
15344 intel_panel_destroy_backlight(connector);
34ea3d38 15345 drm_connector_unregister(connector);
4932e2c3
ID		 15346}
15347
79e53945
JB		 15348void intel_modeset_cleanup(struct drm_device *dev)
15349{
652c393a 15350 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15351 struct drm_connector *connector;
652c393a 15352
2eb5252e
ID		 15353 intel_disable_gt_powersave(dev);
15354
0962c3c9
VS		 15355 intel_backlight_unregister(dev);
15356
fd0c0642
DV		 15357 /*
15358 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15359 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15360 * experience fancy races otherwise.
15361 */
2aeb7d3a 15362 intel_irq_uninstall(dev_priv);
eb21b92b 15363
fd0c0642
DV		 15364 /*
15365 * Due to the hpd irq storm handling the hotplug work can re-arm the
15366 * poll handlers. Hence disable polling after hpd handling is shut down.
15367 */
f87ea761 15368 drm_kms_helper_poll_fini(dev);
fd0c0642 15369
723bfd70
JB		 15370 intel_unregister_dsm_handler();
15371
7733b49b 15372 intel_fbc_disable(dev_priv);
69341a5e 15373
1630fe75
CW		 15374 /* flush any delayed tasks or pending work */
15375 flush_scheduled_work();
15376
db31af1d
JN		 15377 /* destroy the backlight and sysfs files before encoders/connectors */
15378 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15379 struct intel_connector *intel_connector;
15380
15381 intel_connector = to_intel_connector(connector);
15382 intel_connector->unregister(intel_connector);
db31af1d 15383 }
d9255d57 15384
79e53945 15385 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15386
15387 intel_cleanup_overlay(dev);
ae48434c
ID		 15388
15389 mutex_lock(&dev->struct_mutex);
15390 intel_cleanup_gt_powersave(dev);
15391 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15392}
15393
f1c79df3
ZW		 15394/*
15395 * Return which encoder is currently attached for connector.
15396 */
df0e9248 15397struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15398{
df0e9248
CW		 15399 return &intel_attached_encoder(connector)->base;
15400}
f1c79df3 15401
df0e9248
CW		 15402void intel_connector_attach_encoder(struct intel_connector *connector,
15403 struct intel_encoder *encoder)
15404{
15405 connector->encoder = encoder;
15406 drm_mode_connector_attach_encoder(&connector->base,
15407 &encoder->base);
79e53945 15408}
28d52043
DA		 15409
15410/*
15411 * set vga decode state - true == enable VGA decode
15412 */
15413int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15414{
15415 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15416 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15417 u16 gmch_ctrl;
15418
75fa041d
CW		 15419 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15420 DRM_ERROR("failed to read control word\n");
15421 return -EIO;
15422 }
15423
c0cc8a55
CW		 15424 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15425 return 0;
15426
28d52043
DA		 15427 if (state)
15428 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15429 else
15430 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15431
15432 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15433 DRM_ERROR("failed to write control word\n");
15434 return -EIO;
15435 }
15436
28d52043
DA		 15437 return 0;
15438}
c4a1d9e4 15439
c4a1d9e4 15440struct intel_display_error_state {
ff57f1b0
PZ		 15441
15442 u32 power_well_driver;
15443
63b66e5b
CW		 15444 int num_transcoders;
15445
c4a1d9e4
CW		 15446 struct intel_cursor_error_state {
15447 u32 control;
15448 u32 position;
15449 u32 base;
15450 u32 size;
52331309 15451 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15452
15453 struct intel_pipe_error_state {
ddf9c536 15454 bool power_domain_on;
c4a1d9e4 15455 u32 source;
f301b1e1 15456 u32 stat;
52331309 15457 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15458
15459 struct intel_plane_error_state {
15460 u32 control;
15461 u32 stride;
15462 u32 size;
15463 u32 pos;
15464 u32 addr;
15465 u32 surface;
15466 u32 tile_offset;
52331309 15467 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15468
15469 struct intel_transcoder_error_state {
ddf9c536 15470 bool power_domain_on;
63b66e5b
CW		 15471 enum transcoder cpu_transcoder;
15472
15473 u32 conf;
15474
15475 u32 htotal;
15476 u32 hblank;
15477 u32 hsync;
15478 u32 vtotal;
15479 u32 vblank;
15480 u32 vsync;
15481 } transcoder[4];
c4a1d9e4
CW		 15482};
15483
15484struct intel_display_error_state *
15485intel_display_capture_error_state(struct drm_device *dev)
15486{
fbee40df 15487 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15488 struct intel_display_error_state *error;
63b66e5b
CW		 15489 int transcoders[] = {
15490 TRANSCODER_A,
15491 TRANSCODER_B,
15492 TRANSCODER_C,
15493 TRANSCODER_EDP,
15494 };
c4a1d9e4
CW		 15495 int i;
15496
63b66e5b
CW		 15497 if (INTEL_INFO(dev)->num_pipes == 0)
15498 return NULL;
15499
9d1cb914 15500 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15501 if (error == NULL)
15502 return NULL;
15503
190be112 15504 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15505 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15506
055e393f 15507 for_each_pipe(dev_priv, i) {
ddf9c536 15508 error->pipe[i].power_domain_on =
f458ebbc
DV		 15509 __intel_display_power_is_enabled(dev_priv,
15510 POWER_DOMAIN_PIPE(i));
ddf9c536 15511 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15512 continue;
15513
5efb3e28
VS		 15514 error->cursor[i].control = I915_READ(CURCNTR(i));
15515 error->cursor[i].position = I915_READ(CURPOS(i));
15516 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15517
15518 error->plane[i].control = I915_READ(DSPCNTR(i));
15519 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15520 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15521 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15522 error->plane[i].pos = I915_READ(DSPPOS(i));
15523 }
ca291363
PZ		 15524 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15525 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15526 if (INTEL_INFO(dev)->gen >= 4) {
15527 error->plane[i].surface = I915_READ(DSPSURF(i));
15528 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15529 }
15530
c4a1d9e4 15531 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15532
3abfce77 15533 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15534 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15535 }
15536
15537 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15538 if (HAS_DDI(dev_priv->dev))
15539 error->num_transcoders++; /* Account for eDP. */
15540
15541 for (i = 0; i < error->num_transcoders; i++) {
15542 enum transcoder cpu_transcoder = transcoders[i];
15543
ddf9c536 15544 error->transcoder[i].power_domain_on =
f458ebbc 15545 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15546 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15547 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15548 continue;
15549
63b66e5b
CW		 15550 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15551
15552 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15553 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15554 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15555 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15556 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15557 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15558 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15559 }
15560
15561 return error;
15562}
15563
edc3d884
MK		 15564#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15565
c4a1d9e4 15566void
edc3d884 15567intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15568 struct drm_device *dev,
15569 struct intel_display_error_state *error)
15570{
055e393f 15571 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15572 int i;
15573
63b66e5b
CW		 15574 if (!error)
15575 return;
15576
edc3d884 15577 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15578 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15579 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15580 error->power_well_driver);
055e393f 15581 for_each_pipe(dev_priv, i) {
edc3d884 15582 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15583 err_printf(m, " Power: %s\n",
15584 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15585 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15586 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15587
15588 err_printf(m, "Plane [%d]:\n", i);
15589 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15590 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15591 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15592 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15593 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15594 }
4b71a570 15595 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15596 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15597 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15598 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15599 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15600 }
15601
edc3d884
MK		 15602 err_printf(m, "Cursor [%d]:\n", i);
15603 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15604 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15605 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15606 }
63b66e5b
CW		 15607
15608 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15609 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15610 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15611 err_printf(m, " Power: %s\n",
15612 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15613 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15614 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15615 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15616 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15617 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15618 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15619 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15620 }
c4a1d9e4 15621}
e2fcdaa9
VS		 15622
15623void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15624{
15625 struct intel_crtc *crtc;
15626
15627 for_each_intel_crtc(dev, crtc) {
15628 struct intel_unpin_work *work;
e2fcdaa9 15629
5e2d7afc 15630 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15631
15632 work = crtc->unpin_work;
15633
15634 if (work && work->event &&
15635 work->event->base.file_priv == file) {
15636 kfree(work->event);
15637 work->event = NULL;
15638 }
15639
5e2d7afc 15640 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15641 }
15642}
Linux kernel - Deliverables
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